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AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

适用于汽车雷达基带接收器的四通道模拟前端AFE5401-Q1

1 特性

2 应用

1

•

符合汽车应用标准

具有符合 AEC-Q100 的下列结果：

•

汽车雷达

数据采集

SONAR™

–

器件温度 1 级：-40°C 至 125°C 的环境运行温

度范围

3 说明

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

2

AFE5401-Q1 是一款模拟前端 (AFE)，主要面向注重

集成度的应用。此器件包括四个通道，其中每个通道由

一个低噪声放大器 (LNA)，一个可编程均衡器 (EQ)，

一个可编程增益放大器 (PGA)，和一个抗混叠滤波

器，以及后面的高速，12 位模数转换器 (ADC) 组成，

每通道速度 25MSPS。

器件组件充电模式 (CDM) ESD 分类等级 C4B

•

集成模拟前端包括：

–

四路 LNA、均衡器、PGA、抗混叠滤波器和

ADC

30dB PGA 增益时的输入相关噪声：

–

对于 15dB LNA 增益为 2.9nV/√Hz

四个差分输入对中的每一个由 LNA 放大，之后是一个

可调增益范围在 0dB 至 30dB 之间的 PGA。对于每条

通道，在 PGA 和 ADC 之间还集成了一个抗混叠、低

通滤波器 (LPF)。

HIGH_POW_LNA 模式下，对于 18dB LNA 增

益为 2.0nV/√Hz

•

通道上的同时采样

可编程 LNA 增益：

12dB，15dB，16.5dB 和 18dB

每个 LNA，PGA 和抗混叠滤波器输出为差分输出（被

限制在 2V_PP）。抗混叠滤波器驱动片上，12

位，25MSPS ADC。四个 ADC 输出在一条 12 位，并

行，CMOS 输出总线上复用。

•

可编程均衡器模式

内置诊断模式

温度传感器

可编程增益放大器 (PGA)：

此器件采用 9mm x 9mm VQFN-64 封装，并且在

-40°C 至 +105°C 的温度范围内额定运行。要获得更多

信息，请与 AFE5401_info@list.ti.com 联系。

–

0dB 至 30dB（步长 3dB）

可编程、三阶、抗混叠滤波器：

7MHz，8MHz，10.5MHz 和 12MHz

模数转换器 (ADC)：

•

–

器件信息(1)

封装

器件型号

封装尺寸（标称值）

–

四通道，每通道 12 位，25 每秒百万次采样

(MSPS)

AFE5401-Q1

VQFN (64)

9.00mm x 9.00mm

–

无需为基准提供外部去耦合

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

•

并行 CMOS 输出

每通道速率为 25MSPS 时，每通道总内核功率为

64mW

•

电源：1.8V 和 3.3V

封装：9mm x 9mm 超薄四方扁平无引线 (VQFN)-

64

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS619

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

简化电路原理图

AVDD3

DRVDD

AVDD18

DVDD18

Serial Interface

Antialiasing

Filter

Channel

1 of 4

PGA

LNA

EQ

INx

D

[11:0]

ADC

1

INx_AUX

BUF

4:1 MUX

D_GPO [1:0]

1x

ADC_CLK

CMOS, DIFF

Support

4x

DCLK

AFE_CLK

CLKINP

CLKINM

DSYNC1

DSYNC2

Clock

+ Timing Generator

Serialization Factor

TRIG

AVSS

DRVSS

AVSS

DVSS

2

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

8.3 Feature Description................................................. 26

8.4 Device Functional Modes........................................ 33

8.5 Programming........................................................... 42

8.6 Register Maps......................................................... 45

Application and Implementation ........................ 65

9.1 Application Information............................................ 65

9.2 Typical Application .................................................. 65

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 8

6.6 Digital Characteristics ............................................... 9

6.7 Timing Requirements: Output Interface.................. 10

6.8 Timing Requirements: RESET................................ 10

6.9 Timing Requirements: Serial Interface Operation... 11

6.10 Typical Characteristics.......................................... 13

Parameter Measurement Information ................ 22

9

10 Power Supply Recommendations ..................... 69

10.1 Power Supply Sequencing.................................... 69

10.2 Power Supply Decoupling..................................... 69

11 Layout................................................................... 69

11.1 Layout Guidelines ................................................. 69

11.2 Layout Example .................................................... 70

12 器件和文档支持 ..................................................... 72

12.1 文档支持................................................................ 72

12.2 接收文档更新通知 ................................................. 72

12.3 社区资源................................................................ 72

12.4 商标....................................................................... 72

12.5 静电放电警告......................................................... 72

12.6 Glossary................................................................ 72

13 机械、封装和可订购信息....................................... 72

7

8

7.1 Timing Requirements: Across Output Serialization

Modes ...................................................................... 22

Detailed Description ............................................ 24

8.1 Overview ................................................................. 24

8.2 Functional Block Diagram ....................................... 25

4 修订历史记录

Changes from Original (March 2014) to Revision A

Page

•

已添加汽车特性项目 ........................................................................................................................................................... 1

首次公开发布 .......................................................................................................................................................................... 1

已更改将器件信息表更改为最新标准 .................................................................................................................................... 1

Changed order of Pin Functions table to be sorted by pin name instead of pin number....................................................... 5

Changed ESD Rating table title and format, moved Storage temperature parameter to Absolute Maximum Ratings table. 6

已添加 “接收文档更新通知和社区资源”部分.......................................................................................................................... 72

3

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

5 Pin Configuration and Functions

RGC Package

VQFN-64

Top View

1

48

47

46

45

44

43

42

41

40

39

38

D_GPO[1]

D_GPO[0]

D[11]

IN1P_AUX

2

IN1M_AUX

3

IN1P

D[10]

4

5

6

IN1M

D[9]

IN2P_AUX

D[8]

IN2M_AUX

IN2P

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

7

Thermal Pad

IN2M

8

9

IN3P_AUX

10

11

12

13

14

15

16

IN3M_AUX

IN3P

IN3M

37

36

35

34

IN4P_AUX

IN4M_AUX

IN4P

DCLK

33

DRVDD

IN4M

4

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Pin Functions

DESCRIPTION

NAME

NO

D[11:0]

D_GPO[1:0]

AVDD3

AVDD18

AVSS

35-46

CMOS outputs for channels 1 to 4

47, 48

General-purpose CMOS output

3.3-V analog supply voltage

1.8-V analog supply voltage

Analog ground

18

19, 24, 62

20, 23, 61, 63

CLKINM

CLKINP

DCLK

22

Negative differential clock input pin. A single-ended clock is also supported.

Positive differential clock input pin. A single-ended clock is also supported.

CMOS output clock

21

34

DRVDD

DRVSS

DSYNC1

DSYNC2

DVDD18

DVSS

32, 33, 50

CMOS output driver supply

31, 49

CMOS output driver ground

26

Data synchronization clock 1

27

Data synchronization clock 2

28, 30, 51

1.8-V digital supply voltage

29, 52

4

Digital ground

IN1M

Negative differential analog input pin for channel 1

Positive differential analog input pin for channel 1

Negative differential auxiliary analog input pin for channel 1

Positive differential auxiliary analog input pin for channel 1

Negative differential analog input pin for channel 2

Positive differential analog input pin for channel 2

Negative differential auxiliary analog input pin for channel 2

Positive differential auxiliary analog input pin for channel 2

Negative differential analog input pin for channel 3

Positive differential analog input pin for channel 3

Negative differential auxiliary analog input pin for channel 3

Positive differential auxiliary analog input pin for channel 3

Negative differential analog input pin for channel 4

Positive differential analog input pin for channel 4

Positive differential auxiliary analog input pin for channel 4

Negative differential auxiliary analog input pin for channel 4

Do not connect

IN1P

3

IN1M_AUX

IN1P_AUX

IN2M

2

1

8

IN2P

7

IN2M_AUX

IN2P_AUX

IN3M

6

5

12

11

10

9

IN3P

IN3M_AUX

IN3P_AUX

IN4M

16

15

13

14

58, 60

57

56

55

53

54

59

25

17, 64

IN4P

IN4P_AUX

IN4M_AUX

NC

RESET

SCLK

Hardware reset pin (active high). This pin has an internal 150-kΩ pull-down resistor.

Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.

Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.

Serial interface data readout

SDATA

SDOUT

SEN

Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.

Standby control input. This pin has an internal 150-kΩ pull-down resistor.

Trigger for DSYNC1 and DSYNC2. This pin has an internal 150-kΩ pull-down resistor.

Output pins for common-mode bias voltage of the auxiliary input signals

STBY

TRIG

VCM

Located on bottom of package, internally connected to AVSS. Connect to ground plane on the

board.

Thermal pad

Pad

5

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

DRVDD to DRVSS

+3.8

AVDD3 to AVSS

+3.8

Voltage range

V

AVDD18 to AVSS

+2.2

DVDD18 to DVSS

AVSS and DVSS

+2.2

+0.3

Voltage between

AVSS and DRVSS

DVSS and DRVSS

+0.3

V

+0.3

Clock input pins (CLKINP and CLKINM) to AVSS

minimum (2.2, AVDD18 + 0.3)

V

Analog input pins (IN_IP, IN_IM, IN_IP_AUX, and IN_IM_AUX) to AVSS

STBY, RESET, SCLK, SDATA,

SEN, TRIG

Digital control pins to DVSS

–0.3

+3.6

V

Maximum operating junction temperature, T_Jmax

Storage temperature, T_stg

+125

+150

°C

–60

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

TEMPERATURE

T_A

Ambient temperature range

–40

+105

°C

SUPPLIES

DRVDD

Output driver supply

1.7

3

3.6

1.9

V

AVDD3

3-V analog supply voltage

1.8-V analog supply voltage

1.8-V digital supply voltage

3.3

1.8

AVDD18

DVDD18

CLOCK INPUT

1.7

Default mode (DIV_EN disabled)

12.5

25

50

With DIV_EN, DIV_FRC enabled and DIV_REG = 1

With DIV_EN, DIV_FRC enabled and DIV_REG = 2

With DIV_EN, DIV_FRC enabled and DIV_REG = 3

37.5

50

75

CLKIN

Input clock frequency

MHz

100

With decimate-by-2 or decimate-by-4 modes enabled

(DIV_EN disabled)⁽¹⁾

12.5

50

Sine wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

0.2

1.5

1.6

0.7

1.8

Input clock amplitude

differential

V_CLKINP– V_CLKINM

V_PP

V

Single-ended CMOS clock on CLKINP with CLKINM connected to AVSS

Input clock duty cycle

40%

60%

DIGITAL OUTPUT

C_LOAD

Tolerable external load capacitance from each output pin to DRVSS

5

pF

(1) In decimation mode, input clock frequency (CLKIN) can be scaled up to maximum of 200 MHz with the input divider.

6.4 Thermal Information

AFE5401-Q1

THERMAL METRIC⁽¹⁾

RGC (VQFN)

UNIT

64 PINS

24.9

8.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

3.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

3.9

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

6.5 Electrical Characteristics

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +105°C, DRVDD = 3.3 V,

AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK =

25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise

noted. Typical values are at T_NOM= +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

FULL-CHANNEL CHARACTERISTICS

LNA gain = 12 dB

0.5

0.35

LNA gain = 15 dB (default)

LNA gain = 16.5 dB

Maximum differential input signal

amplitude on IN_IP and IN_IM

V_PP

0.3

LNA gain = 18 dB

0.25

Default

1 ± 20%

10 ± 20%

5.5

Input resistance, from each input to

internal dc bias level

kΩ

TERM_INT_20K_LNA / TERM_INT_20K_AUX = 1

Differential input capacitance

Voltage on VCM pins

C_I

Input capacitance

VCM output voltage

VCM output current capability

Gain matching

pF

V

V_VCM

1.45

For 50-mV drop in VCM voltage

Across channels and devices

PGA gain = 30 dB

3

mA

0.15

1

dB

E_G

E_O

Gain error

± 0.6

± 120

2.9

± 1.4

Offset error

PGA gain = 30 dB, 1 sigma value

f_IN= 3 MHz, idle channel, PGA gain = 30 dB (default)

LSB

3.8

Input-referred noise voltage

nV/√Hz

f_IN= 3 MHz, idle channel, PGA gain = 30 dB

(HIGH_POW_LNA mode)

2.5

f_IN= 3 MHz, main channel

65

57

56

67.7

69.2

66

SNR

Signal-to-noise ratio

dBFS

dBc

f_IN= 3 MHz, AUX channel

f_IN= 3 MHz, main channel (default)

f_IN= 3 MHz, main channel (HPL_EN mode)

f_IN= 3 MHz, main channel

SFDR

Spurious-free dynamic range

74

THD

IMD

Total harmonic distortion

Intermodulation distortion

65

dBc

f_IN1= 1.5 MHz, f_IN2= 2 MHz, A_IN1and A_IN2= –7 dBFS

83

dBFS

For a 50-mV_PPsignal on AVDD18 up to 10 MHz, no input

applied to analog inputs

PSRR

Power-supply rejection ratio

> 50

12

dB

Bits

dB

Number of bits in the ADC

Aggressor channel: f_IN= 2 MHz, 1 dB below ADC full-scale.

Victim channel: f_IN= 3 MHz, 1 dB below ADC full-scale.

Crosstalk, main channel to main channel

70

Maximum channel gain

Minimum channel gain

PGA gain resolution

PGA gain range

LNA gain = 18 dB, PGA gain = 30 dB

LNA gain = 12 dB, PGA gain = 0 dB

48

12

3

dB

Maximum PGA gain – minimum PGA gain

30

Differential input voltage range for AUX

channel

2

V_PP

ANTIALIAS FILTER (Third-Order Elliptic)

FILTER_BW = 0 (default)

FILTER_BW = 1

8

7

f_C

3-dB filter corner frequency

MHz

FILTER_BW = 2

10.5

12

FILTER_BW = 3

3-dB filter corner frequency tolerance

Filter attenuation

For all FILTER_BW settings

At 2 × f_C

±5%

30

ATT_2FC

dBc

dB

ATT_STPBND

RP_PSBND

Stop-band attenuation (f_IN> 2.25 × f_C)

40

Ripple in pass band

1.5

8

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Electrical Characteristics (continued)

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +105°C, DRVDD = 3.3 V,

AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK =

25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise

noted. Typical values are at T_NOM= +25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER

Total core power, per channel

AVDD18 current consumption

Idle channel, excluding DRVDD power

Default mode

64

131

153

135

1.5

8

mW

145

I_AVDD18

With HIGH_POW_LNA mode enabled

With HPL_EN mode enabled

mA

I_AVDD3

AVDD3 current consumption

DVDD18 current consumption

3.5

12

mA

I_DVDD18

DRVDD = 3.3 V

DRVDD = 1.8 V

DRVDD = 3.3 V

DRVDD = 1.8 V

14

5-pF load, toggle data test pattern mode

15-pF load, toggle data test pattern mode

8.5

36

I_DRVDD

DRVDD current consumption

mA

20

Power-down

STBY power

5

mW

15

6.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +105°C, DRVDD

= 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted. Typical values are at T_NOM

+25°C.

=

PARAMETER

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (STBY, RESET, SCLK, CLKIN, SDATA, SEN, TRIG)⁽¹⁾

V_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

1.4

V

V_IL

0.4

I_IH

10

4

µA

pF

V

I_IL

C_I

V_{IL_CLKINP}

V_{IH_CLKINP}

DIGITAL OUTPUTS

0.25 × AVDD18

Input clock CMOS single-ended (V_CLKINP), V_CLKINM

connected to AVSS

0.75 × AVDD18

DRVDD – 0.2

V

V_OH

V_OL

High-level output voltage

Low-level output voltage

DRVDD

0

V

0.2

(1) The SEN pin has an internal 150-kΩ pull-up resistor. The STBY, RESET, SCLK, SDATA, and TRIG pins have an internal 150-kΩ pull-

down resistor.

9

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

6.7 Timing Requirements: Output Interface

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +105°C, DRVDD = 3.3 V,

AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with 0.1 µF, AFE_CLK = 25 MHz, LNA

gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted.

Typical values are at T_NOM= +25°C.

MIN

NOM

MAX

UNIT

Aperture delay between the rising edge of the input sampling clock and the

actual time at which the sampling occurs

t_ADLY

3

ns

Time to valid data after coming out of

STANDBY mode

500

2

µs

ms

µs

Time to valid data after coming out of

GLOBAL_PDN mode

Wake-up time

Time to valid data after stopping and

restarting the input clock

500

10.5

t_{AFE_CLK}

cycles

t_LAT

ADC latency (default, after reset)

Data valid⁽¹⁾to 50% of DCLK rising edge,

DRVDD = 3.3 V, load = 5 pF, 4x

serialization, STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 0

Data valid⁽¹⁾to 50% of DCLK rising edge,

DRVDD =1.8 V, load = 5 pF, 4x serialization,

STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 5

4.1

3.7

2.8

2.7

ns

t_SU

Data setup time

50% of DCLK rising edge to data becoming

invalid⁽¹⁾, DRVDD = 3.3 V, load = 5 pF, 4x

serialization, STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 0

t_HO

Data hold time

50% of DCLK rising edge to data becoming

invalid⁽¹⁾, DRVDD = 1.8 V, load = 5 pF, 4x

serialization, STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 5

DRVDD = 3.3 V, load = 5 pF, 10% to 90%,

STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 0

1.2

1.1

ns

CMOS output data and

clock rise and fall time

t_R, t_F

DRVDD = 1.8 V, load = 5 pF, 10% to 90%,

STR_CTRL_CLK and

STR_CTRL_CLK_DATA = 5

Delay from CLKIN rising edge to DCLK rising edge, zero-crossing of input

clock to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x

serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0

t_OUT

6.7

9.5

t_{S_TRIG}

t_{H_TRIG}

TRIG setup time, TRIG pulse duration ≥ t_{AFE_CLK}

TRIG hold time, TRIG pulse duration ≥ t_{AFE_CLK}

4

3

ns

(1) Data valid refers to a logic high of 0.7 × DRVDD and a logic low of 0.3 × DRVDD.

6.8 Timing Requirements: RESET

Typical values are at T_A= +25°C. Minimum and maximum specifications are across the full temperature range of T_MIN

=

–40°C to T_MAX= +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay from power-up of AVDD18 and

DVDD18 to RESET pulse active

t₁

Power-on to reset delay

1

ms

t₂

t₃

Reset pulse duration

Register write delay

Pulse duration of active RESET signal

Delay from RESET disable to SEN active

40

ns

100

10

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

6.9 Timing Requirements: Serial Interface Operation

Minimum specifications are across the full temperature range of T_MIN= –40°C to T_MAX= +105°C, DRVDD = 3.3 V, AVDD3 =

3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, C_LOADon SDOUT = 5 pF, unless otherwise noted.

PARAMETER

MIN

50

20

5

TYP

MAX

UNIT

ns

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

SCLK period

SCLK high time

SCLK low time

Data setup time

Data hold time

ns

5

ns

SEN falling to SCLK rising

8

ns

Time between last SCLK rising edge to SEN rising edge

Delay from SCLK falling edge to SDOUT valid

8

ns

7

11

15

ns

t_LAT

t_ADLY

(1)

t_CLK

IN_IP, IN_IM

N

N+4

N+1

N+3

N+5

N+6

N+7

CLKIN

t_OUT

t_HO

DCLK

t_SU

D[11:0]

CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4

(1) t_CLK= 1 / f_CLKIN

Figure 1. Output Interface Timing Diagram

A high pulse on the RESET pin is required for register initialization through the reset pin. Figure 2 shows the

timing requirement for reset after power-up.

Power Supply

(AVDD18, DVDD18,

AVDD3, DRVDD)

t₁

t₂

RESET

t₃

SEN

Figure 2. Reset Timing

11

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

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SEN

End Sequence

t₆

t₁

t₇

Data latched on rising edge of SCLK

t₂

SCLK

t₃

A[7]

A[6] A[5] A[4]

A[3] A[2] A[1] A[0] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

SDATA

SDOUT

t₄

t₅

Figure 3. Serial Interface Register Write Timing Diagram

SEN

End Sequence

t₆

t₁

t₇

t₂

SCLK

t₃

A[7]

A[6] A[5] A[4] A[3] A[2] A[1] A[0]

X

SDATA

t₄

SDOUT to be latched externally on rising

edge

t₅

t₈

D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

SDOUT

Figure 4. Serial Interface Register Readout Timing Diagram

12

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

6.10 Typical Characteristics

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

0

œ10

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

œ90

œ100

œ110

œ120

œ130

œ140

œ100

œ110

œ120

œ130

œ140

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

C002

SNR = 67.7 dBFS

SFDR = 65.7 dBc

THD = 65.2 dBc

SNR = 53.3 dBFS

SFDR = 63.7 dBc

THD = 63.6 dBc

Figure 5. FFT for 3-MHz, –1-dBFS Input Signal,

0-dB PGA Gain (Sample Rate = 25 MSPS)

Figure 6. FFT for 3-MHz, –1-dBFS Input Signal,

30-dB PGA Gain (Sample Rate = 25 MSPS)

0

œ10

œ20

œ30

œ40

œ50

œ60

œ70

œ80

85

80

75

70

65

60

PGA Gain = 0 dB

PGA Gain = 30 dB

œ90

œ100

œ110

œ120

œ130

œ140

0

2.5

5

7.5

10

12.5

1

2

3

4

5

Frequency (MHz)

Input Signal Frequency (MHz)

C001

C006

f_IN1= 1.5 MHz

f_IN2= 2 MHz

Each Tone at –7-dBFS Amplitude

Two-Tone IMD = –83 dBFS

Figure 7. FFT with Two-Tone Signal

Figure 8. Spurious-Free Dynamic Range vs

Input Signal Frequency

68.3

68.2

68.1

68

53.5

53.3

53.1

52.9

52.7

52.5

67.9

67.8

67.7

67.6

67.5

1

2

3

4

5

1

2

3

4

5

Input Signal Frequency (MHz)

C005

C050

Figure 9. Signal-to-Noise Ratio vs Input Signal Frequency

(PGA Gain = 0 dB)

Figure 10. Signal-To-Noise Ratio vs Input Signal Frequency

(PGA Gain = 30 dB)

13

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Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

68

66

64

62

60

58

56

54

52

80

77

74

71

68

65

62

Default Mode

HPL_EN = 1

0

3

6

9

12

15

18

21

24

27

30

0

3

6

9

12

15

18

21

24

27

30

PGA Gain (dB)

C007

C008

Figure 11. Signal-to-Noise Ratio vs PGA Gain

Figure 12. Spurious-Free Dynamic Range vs PGA Gain

100

90

80

70

60

50

40

69

90

54

80

70

60

50

40

30

20

53.8

53.6

53.4

53.2

53

68.7

68.4

68.1

67.8

67.5

67.2

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

52.8

52.6

-50 -45 -40 -35 -30 -25 -20 -15 -10

Input Signal Amplitude (dBFS)

-5

0

-50 -45 -40 -35 -30 -25 -20 -15 -10

Input Signal Amplitude (dBFS)

-5

0

C001

Figure 13. Signal-to-Noise Ratio,

Spurious-Free Dynamic Range vs

Figure 14. Signal-to-Noise Ratio,

Spurious-Free Dynamic Range vs

Input Signal Amplitude (PGA Gain = 0 dB)

Input Signal Amplitude (PGA Gain = 30 dB)

69

67

68.6

68.2

67.8

67.4

67

66.6

66.2

65.8

65.4

65

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

Input Clock Amplitude, Differential (V_PP

)

Input Clock Amplitude, Differential (V_PP

)

C011

C012

Figure 15. Signal-to-Noise Ratio vs Input Clock Amplitude

(PGA Gain = 0 dB)

Figure 16. Spurious-Free Dynamic Range vs

Input Clock Amplitude (PGA Gain = 0 dB)

14

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

68

67.6

67.2

66.8

66.4

66

67

66.6

66.2

65.8

65.4

65

35

40

45

50

55

60

65

35

40

45

50

55

60

65

Input Clock Duty Cycle (%)

C013

C014

Figure 17. Signal-to-Noise Ratio vs Input Clock Duty Cycle

(PGA Gain = 0 dB)

Figure 18. Spurious-Free Dynamic Range vs

Input Clock Amplitude (PGA Gain = 0 dB)

68.5

68.3

68.1

67.9

67.7

67.5

54

53.5

53

52.5

52

12.5

15

17.5

20

22.5

25

12.5

15

17.5

20

22.5

25

Sampling Frequency (MHz)

C045

C046

Figure 19. Signal-to-Noise Ratio vs Sampling Frequency

(PGA Gain = 0 dB)

Figure 20. Signal-to-Noise Ratio vs Sampling Frequency

(PGA Gain = 30 dB)

78

Default Mode

76

HPL_EN = 1

74

72

70

68

66

64

62

74

72

70

68

66

64

12.5

15

17.5

20

22.5

25

12.5

15

17.5

20

22.5

25

C047

C048

Sampling Frequency (MHz)

Figure 21. Spurious-Free Dynamic Range vs Sampling

Frequency (PGA Gain = 0 dB)

Figure 22. Spurious-Free Dynamic Range vs Sampling

Frequency (PGA Gain = 30 dB)

15

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Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

68.5

68.2

67.9

67.6

67.3

67

53.8

53.5

53.2

52.9

52.6

52.3

52

AVDD18 = 1.7 V

AVDD18 = 1.8 V

AVDD18 = 1.9 V

AVDD18 = 1.7 V

AVDD18 = 1.8 V

AVDD18 = 1.9 V

-40 -25.5 -11

3.5

18 32.5 47 61.5 76 90.5 105

-40.0 -25.5 -11.0 3.5 18.0 32.5 47.0 61.5 76.0 90.5 105.0

Temperature (°C)

C015

C016

Figure 23. Signal-to-Noise Ratio vs AVDD18 and

Temperature (PGA Gain = 0 dB)

Figure 24. Signal-to-Noise Ratio vs AVDD18 and

Temperature (PGA Gain = 30 dB)

72

70

68

66

64

62

70

AVDD18 = 1.7 V

AVDD18 = 1.8 V

AVDD18 = 1.9 V

AVDD18 = 1.7 V

AVDD18 = 1.8 V

AVDD18 = 1.9 V

68

66

64

62

60

-40 -25.5 -11 3.5

18 32.5 47 61.5 76 90.5 105

-40 -25.5 -11

3.5

18 32.5 47 61.5 76 90.5 105

Temperature (°C)

C017

C018

Figure 25. Spurious-Free Dynamic Range vs AVDD18 and

Temperature (PGA Gain = 0 dB, Default Mode)

Figure 26. Spurious-Free Dynamic Range vs AVDD18 and

Temperature (PGA Gain = 30 dB, Default Mode)

78

AVDD18 = 1.7 V

AVDD18 = 1.8 V

76

AVDD18 = 1.9 V

74

72

70

74

72

70

-40 -25.5 -11 3.5

18 32.5 47 61.5 76 90.5 105

-40 -25.5 -11

3.5

18 32.5 47 61.5 76 90.5 105

Temperature (°C)

C051

C052

Figure 27. Spurious-Free Dynamic Range vs AVDD18 and

Temperature (PGA Gain = 0 dB, HPL_EN = 1)

Figure 28. Spurious-Free Dynamic Range vs AVDD18 and

Temperature (PGA Gain = 30 dB, HPL_EN = 1)

16

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

56

55

54

53

52

51

65

64.5

64

Default Mode

HIGH_POW_LNA = 1

63.5

63

12

13

14

15

16

17

18

12

13

14

15

16

17

18

LNA Gain (dB)

C019

C020

Figure 29. Signal-to-Noise Ratio vs LNA Gain

(PGA Gain = 30 dB)

Figure 30. Spurious-Free Dynamic Range vs LNA Gain

(PGA Gain = 30 dB)

4

15

Default Mode

14

13

12

11

10

9

HIGH_POW_LNA = 1

3.5

3

8

7

6

2.5

2

5

4

3

2

12

13

14

15

16

17

18

0

3

6

9

12

15

18

21

24

27

30

LNA Gain (dB)

PGA Gain (dB)

C022

C021

Figure 31. Input-Referred Noise vs LNA Gain

(PGA Gain = 30 dB)

Figure 32. Input-Referred Noise vs PGA Gain

15

500

450

400

350

300

250

200

150

100

50

Default Mode

Temperature = -40°C

Temperature = 25°C

14

13

12

11

10

9

HIGH_POW_LNA = 1

Temperature = 105°C

8

7

6

5

4

3

2

0

3

6

9

12

15

18

21

24

27

30

0

3

6

9

12

15

18

21

24

27

30

PGA Gain (dB)

C024

C023

Figure 33. Input-Referred Noise vs

PGA Gain and Temperature

Figure 34. Output-Referred Noise vs PGA Gain

17

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www.ti.com.cn

Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

3000

2500

2000

1500

1000

500

450

400

350

300

250

200

150

100

50

Temperature = -40°C

Temperature = 25°C

Temperature = 105°C

0

-0.85 -0.75 -0.65 -0.55 -0.45 -0.35 -0.25 -0.15

Gain Error (dB)

0

3

6

9

12

15

18

21

24

27

30

C056

PGA Gain (dB)

C025

Figure 36. Gain Error Histogram for PGA Gain = 30 dB

Figure 35. Output-Referred Noise vs

PGA Gain and Temperature

450

400

350

300

250

200

150

100

50

150

Device = 1

100

Device = 2

50

0

œ50

œ100

œ150

0

3

6

9

12

15

18

21

24

27

30

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Gain Matching ( dB)

PGA Gain (dB)

C027

C057

Figure 38. Channel Offset vs

PGA Gain for Two Typical Devices

Figure 37. Gain Matching Histogram (Maximum Gain

Difference Among the Four Channels within a Device)

3000

20

10

2500

2000

1500

1000

500

0

œ10

œ20

œ30

œ40

œ50

FCF_7 MHz

FCF_8 MHz

FCF_10.5 MHz

FCF_12 MHz

0

-600-500-400-300-200-100

0

100 200 300 400 500 600

0.1

10

Offset Error ( LSB)

C058

f_IN(MHz)

C028

Figure 39. Offset Error Histogram at PGA Gain = 30 dB

Figure 40. Antialias Filter Response vs

FILTER_BW Settings (PGA Gain = 0 dB)

18

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Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

50

20

40

10

30

0

20

œ10

œ20

œ30

œ40

œ50

10

FCF_7 MHz

FCF_8 MHz

FCF_10.5 MHz

FCF_12 MHz

0

AVDD18 = 1.7 V

AVDD18 = 1.8 V

AVDD18 = 1.9 V

œ10

œ20

0.1

1

10

0.1

1

10

f_IN(MHz)

C002

C030

Figure 41. Antialias Filter Response vs

FILTER_BW Settings (PGA Gain = 30 dB)

Figure 42. Antialias Filter Response vs AVDD18

(PGA Gain = 0 dB, FILTER_BW = 8 MHz)

20

10

30

20

10

0

œ10

œ20

œ30

œ40

œ50

œ10

œ20

œ30

œ40

œ50

Temperature = -40°C

Temperature = 25°C

Temperature = 105°C

Default Mode (Eq_Dis)

Eq_EN

Eq_EN_LOW_FC

0.1

1

10

0.1

1

10

f_IN(MHz)

C053

C001

Figure 43. Antialias Filter Response vs Temperature (PGA

Gain = 0 dB, FILTER_BW = 8 MHz)

Figure 44. Antialias Filter Response for Equalizer Modes

(PGA Gain = 0 dB)

60

50

40

30

20

10

30

20

10

0

œ10

Eq_EN, Temperature = -40°C

œ20

œ30

œ40

Default Mode (Eq_Dis)

0

Eq_EN, Temperature = 105°C

Eq_EN

Eq_EN_LOW_FC, Temperature = -40°C

Eq_EN_LOW_FC, Temperature = 105°C

œ10

Eq_EN_LOW_FC

œ20

0.1

1

10

0.1

1

10

f_IN(MHz)

C001

C035

Figure 45. Antialias Filter Response for Equalizer Modes

(PGA Gain = 30 dB)

Figure 46. Antialias Filter Response for

Equalizer Modes across Temperature (PGA Gain = 0 dB)

19

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Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

0

œ10

60

œ20

œ30

œ40

50

40

œ50

œ60

œ70

30

œ80

œ90

20

Eq_EN, Temperature = -40°C

10

œ100

œ110

œ120

œ130

œ140

Eq_EN, Temperature = 105°C

0

Eq_EN_LOW_FC, Temperature = -40°C

Eq_EN_LOW_FC, Temperature = 105°C

œ10

œ20

0

3

5

8

10

13

Frequency (MHz)

C049

0.1

1

10

SNR = 69.2 dBFS

SFDR = 69.8 dBc

THD = 69.7 dBc

f_IN(MHz)

C036

Figure 48. FFT for AUX Channel

(3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)

Figure 47. Antialias Filter Response for

Equalizer Modes across Temperature (PGA Gain = 30 dB)

20

10

0

œ10

œ20

œ30

œ40

œ50

œ10

œ20

œ30

œ40

œ50

œ60

Default Mode

DECIMATE_4_EN = 1, Set 2

œ60

œ70

DECIMATE_2_EN = 1

DECIMATE_4_EN = 1, Set 1

œ80

œ70

0.1

1

10

0.1

1

f_IN(MHz)

C037

C038

Figure 49. Decimate-by-2 Filter Response (Sampling

Frequency = 50 MHz)

Figure 50. Decimate-by-4 Filter Response (Sampling

Frequency = 12.5 MHz)

120

131

Current_AVDD18

105

90

130.5

130

75

129.5

129

60

45

128.5

128

30

15

127.5

127

0

œ15

œ30

œ45

126.5

126

œ45 œ30 œ15

0

15

30

45

60

75

90

105

12.5

15

17.5

20

22.5

25

Set Temperature (°C)

Sampling Frequency (MHz)

C054

C039

Figure 51. Temperature Sensor Response

Figure 52. AVDD18 Supply Current vs Sampling Frequency

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Typical Characteristics (continued)

Typical values are at T_A= +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled

with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner

frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

7

6

5

4

3

2

1.8

1.6

1.4

1.2

1

Current_DVDD18

Current_AVDD3

12.5

15

17.5

20

22.5

25

12.5

15

17.5

20

22.5

25

Sampling Frequency (MHz)

C040

C041

Figure 53. DVDD18 Supply Current vs Sampling Frequency

Figure 54. AVDD3 Supply Current vs Sampling Frequency

40

64

DRVDD = 3.3 V

35

30

25

20

15

10

DRVDD = 1.8 V

63

62

61

60

59

12.5

15

17.5

20

22.5

25

12.5

15

17.5

20

22.5

25

Sampling Frequency (MHz)

C042

C044

Figure 55. DRVDD Supply Current vs Sampling Frequency

(15-pF Load with Toggle Test Mode)

Figure 56. AFE Core Power, Channel Excluding DRVDD

21

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7 Parameter Measurement Information

7.1 Timing Requirements: Across Output Serialization Modes

Table 1 and Table 2 provide details for the 4x serialization timing requirements for DRVDD = 3.3 V and DRVDD

= 1.8 V, respectively. Table 3 and Table 4 provide details for the 3x serialization timing requirements for DRVDD

= 3.3 V and DRVDD = 1.8 V, respectively. Table 5 provides the details for the 2x and 1x serialization timing

requirements for DRVDD = 1.8 V to 3.3 V.

Table 1. Timing Requirements: 4x Serialization (DRVDD = 3.3 V)

OUTPUT

CLOCK (DCLK)

FREQUENCY

(MHz)

SETUP TIME (ns)

t_SU

HOLD TIME (ns)

t_HO

INPUT CLOCK

FREQUENCY

(MHz)

t_OUT(ns)

TYP

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

MIN

MAX

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

12.5

15

50

60

9.1

7.9

6.7

9.5

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

7.1

5.3

4.1

3.5

6.1

4.1

2.8

2.6

6.7

6.4

9.5

9.0

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

20

80

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

25

100

C_LOAD= 15 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 6

25

Table 2. Timing Requirements: 4x Serialization (DRVDD = 1.8 V)

OUTPUT

CLOCK (DCLK)

FREQUENCY

(MHz)

SETUP TIME (ns)

t_SU

HOLD TIME (ns)

t_HO

INPUT CLOCK

FREQUENCY

(MHz)

t_OUT(ns)

TYP

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

MIN

MAX

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

12.5

15

50

60

9.2

7.9

5.6

10.6

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

7.2

5.3

3.7

2.6

6.1

3.9

2.7

5.6

5.3

10.6

10.0

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

20

80

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

25

100

C_LOAD= 15 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 14

25

Table 3. Timing Requirements: 3x Serialization (DRVDD = 3.3 V)

OUTPUT

CLOCK (DCLK)

FREQUENCY

(MHz)

SETUP TIME (ns)

t_SU

HOLD TIME (ns)

t_HO

INPUT CLOCK

FREQUENCY

(MHz)

t_OUT(ns)

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

MIN

TYP MAX

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

12.5

15

37.5

45

12.4

11.8

20.1

17.4

15.1

13.4

12.8

23.2

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

9.9

7.2

5.7

5.1

9.1

6.3

4.1

3.8

20.4

18.0

16.0

15.3

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

20

60

C_LOAD= 5 pF,

STR_CTRL_CLK, STR_CTRL_DATA = 0

25

75

C_LOAD= 15 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 6

25

75

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Table 4. Timing Requirements: 3x Serialization (DRVDD = 1.8 V)

OUTPUT

CLOCK (DCLK)

FREQUENCY

(MHz)

SETUP TIME (ns)

t_SU

HOLD TIME (ns)

t_HO

INPUT CLOCK

FREQUENCY

(MHz)

t_OUT(ns)

TYP MAX

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

MIN

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

12.5

15

37.5

45

12.5

11.9

19.2

23.6

20.1

18.4

16.7

16.4

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

10.0

7.3

9.3

6.4

4.7

4

16.6

14.0

12.4

12.1

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

20

60

C_LOAD= 5 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 5

25

75

5.7

C_LOAD= 15 pF,

STR_CTRL_CLK and STR_CTRL_DATA = 14

25

75

4.7

Table 5. Timing Requirements: 2x and 1x Serialization (DRVDD = 1.8 V to 3.3 V)

OUTPUT

CLOCK (DCLK)

FREQUENCY

(MHz)

SETUP TIME (ns)

t_SU

HOLD TIME (ns)

t_HO

INPUT CLOCK

FREQUENCY

(MHz)

t_OUT(ns)

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

MIN

TYP MAX

2x Serialization mode: C_LOAD= 5 pF.

For DRVDD = 1.8 V, STR_CTRL_CLK and

STR_CTRL_DATA = 5.

For DRVDD = 3.3 V, STR_CTRL_CLK and

STR_CTRL_DATA = 0.

25

50

25

7.3

8.0

5.5

10.5

1x Serialization mode: C_LOAD= 5 pF.

For DRVDD = 1.8 V, STR_CTRL_CLK and

STR_CTRL_DATA = 5.

18.5

17.5

25.2

30.1

For DRVDD = 3.3 V, STR_CTRL_CLK and

STR_CTRL_DATA = 0.

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8 Detailed Description

8.1 Overview

The AFE5401-Q1 is a very low-power, CMOS, monolithic, quad-channel, analog front-end (AFE). The signal path

of each channel consists of a differential low-noise amplifier (LNA) followed by a differential programmable gain

amplifier (PGA) in series with a differential antialias filter. The antialiasing filter output is sampled by a 12-bit,

pipeline, analog-to-digital converter (ADC) based on a switched-capacitor architecture. Each ADC can also be

differentially driven from IN_IP_AUX, IN_IM_AUX through an on-chip buffer (thus bypassing the LNA, PGA, and

antialiasing filter).

Each block in the channel operates with a maximum 2-V_PPoutput swing. Each PGA has a programmable gain

range from 0 dB to 30 dB, with a resolution of 3 dB.

After the input signals are captured by the sampling circuit, the samples are sequentially converted by a series of

low-resolution stages inside the pipeline ADC at the clock rising edge. The outputs of these stages are combined

in a digital logic block to form the final 12-bit word with a latency of 10.5 t_{AFE_CLK}clock cycles. The 12-bit words of

all active channels are multiplexed and output as parallel CMOS levels. In addition to the data streams, a CMOS

clock (DCLK) is also output. This clock must be used by the digital receiver [such as a digital signal processor

(DSP)] to latch the AFE output parallel CMOS data.

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8.2 Functional Block Diagram

VCM

Reference

Serial Interface

PGA

AAF

LNA

EQ

IN1

ADC 1

IN1_AUX

BUF

EQ

IN2

ADC 2

IN2_AUX

BUF

D [11:0]

4:1 MUX

EQ

IN3

D_GPO [1:0]

ADC 3

IN3_AUX

BUF

EQ

IN4

ADC 4

IN4_AUX

BUF

1x

ADC_CLK

4x

DCLK

CMOS, Diff

Support

Input

Clock Divider

CLKINP

CLKINM

f_CLKIN

AFE_CLK

DSYNC1

DSYNC2

Clock + Timing Generator

Serialization Factor

TRIG

DRVSS

AVSS

DVSS

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8.3 Feature Description

8.3.1 Low-Noise Amplifier (LNA)

The analog input signal is buffered and amplified by an on-chip LNA. LNA gain is programmable with the

LNA_GAIN register, as shown in Table 6.

Table 6. LNA_GAIN Register

LNA_GAIN

DESCRIPTION (dB)

LNA_GAIN_Linear

0

1

2

3

15

18

5.5

8

12

4

16.5

6.5

The LNA output is internally limited to 2 V_PP. Thus, the maximum-supported input peak-to-peak swing is set by 2

V / LNA_GAIN_Linear.

Input-referred noise in default mode is 2.9 nV/√Hz at 30-dB PGA gain and 15-dB LNA gain. Input-referred noise

can be further improved to 2.5 nV/√Hz by enabling the HIGH_POW_LNA register bit. However, this noise

reduction results in increased power dissipation.

8.3.2 Programmable Gain Amplifier (PGA)

The PGA amplifies the analog input signal by a programmable gain. Gain can be programmed using the

PGA_GAIN register, common to all channels, in 3-dB steps with a gain range of 30 dB. In default mode, PGA

gain ranges from 0 dB to 30 dB. In equalizer mode, PGA gain ranges from 15 dB to 45 dB. PGA_GAIN register

settings are listed in Table 7. Figure 57 shows the typical SNR values across PGA gain.

Table 7. PGA_GAIN Register Settings

PGA_GAIN Settings

0 (0 dB)

PGA GAIN IN DEFAULT MODE (dB)

PGA GAIN IN EQUALIZER MODE (dB)

0.0

2.9

15.0

17.9

21.0

23.8

26.9

29.8

32.9

35.8

38.9

41.8

44.9

1 (3 dB)

2 (6 dB)

6.0

3 (9 dB)

8.8

4 (12 dB)

5 (15 dB)

6 (18 dB)

7 (21 dB)

8 (24 dB)

9 (27 dB)

10 (30 dB)

11.9

14.8

17.9

20.8

23.9

26.8

29.9

68

66

64

62

60

58

56

54

52

0

3

6

9

12

15

18

21

24

27

30

PGA Gain (dB)

C007

Figure 57. SNR Across PGA Gain

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8.3.3 Antialiasing Filter

The device introduces a third-order, elliptic, active, antialias, low-pass filter (LPF) in the analog signal path. The

filter –3-dB corner frequency can be configured using the FILTER_BW register, as shown in Table 8. The

corresponding frequency response plots are shown in Figure 58 and Figure 59.

Table 8. FILTER_BW Register

FILTER_BW

CORNER FREQUENCY (MHz)

0

1

2

3

8

7

10.5

12

20

10

50

40

30

0

20

œ10

œ20

œ30

œ40

œ50

10

FCF_7 MHz

FCF_8 MHz

FCF_10.5 MHz

FCF_12 MHz

FCF_7 MHz

0

FCF_8 MHz

FCF_10.5 MHz

FCF_12 MHz

œ10

œ20

0.1

1

10

0.1

10

f_IN(MHz)

C002

f_IN(MHz)

C028

Figure 59. Filter Response Across Modes

(PGA Gain = 30 dB)

Figure 58. Filter Response Across Modes

(PGA Gain = 0 dB)

8.3.4 Analog-to-Digital Converter (ADC)

The filtered analog input signal is sampled and converted into a digital equivalent code using a high-speed, low-

power, 12-bit, pipeline ADC. The digital output of the device has a latency of 10.5 t_{AFE_CLK}cycles because of the

pipeline nature of the ADC. The digitized output of the device is in binary twos complement (BTC) format. The

output format can be changed to offset binary format with the OFF_BIN_DATA_FMT register bit.

8.3.5 Digital Gain

The ADC output can be incremented digitally using a digital gain block. Digital gain is common for all channels

and can be configured by enabling MULT_EN and applying the desired DIG_GAIN. Channel gain is given by

Equation 1:

where:

•

(DIG_GAIN + 32) is the mod 128 number.

(1)

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Figure 60 shows the typical digital gain curve for different DIG_GAIN values.

(95, 127/32)

4

(127, 31/32)

1

0

X Axis

96

128

DIG_GAIN

Figure 60. Digital Gain Graph

8.3.6 Input Clock Divider

The device clock input is passed through a clock divider block that can divide the input clock by a factor of 1, 2,

3, or 4. This divided clock (AFE_CLK) is used for simultaneously sampling the four ADC inputs. In default mode,

a division factor of 1 is used where the AFE_CLK frequency is the same as the input clock frequency. The clock

divider block can be enabled using the DIV_EN register bit and, when enabling this bit, the AFE_CLK frequency

is automatically determined by the serialization factor set by the CH_OUT_DIS register bits (Table 12). The

division factor can also be manually specified by enabling the DIV_FRC and DIV_REG register bits. Care must

be taken to ensure that the input clock frequency is within the recommended operating range specified in the

Recommended Operating Conditions.

After device reset, the divider is reset at the first pulse applied on the TRIG pin. This configuration is especially

useful when using multiple devices in the system, where the sampling instants of all ADCs in the system must be

synchronized. Figure 61 illustrates the TRIG timing diagram and the various divided-down AFE_CLK signals.

Figure 62 provides the TRIG input setup and hold time with respect to the device clock input. Bit settings for the

DIV_EN register, DIV_FRD register, and DIV_REG register are provided in Table 9, Table 10, and Table 11,

respectively.

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TRIG

CLKIN

TRIG_INT

AFE_CLK (÷ 2)

AFE_CLK (÷ 3)

AFE_CLK (÷ 4)

Figure 61. Input Clock Divider

CLKIN

TRIG

t_{S_TRIG}

t_{H_TRIG}

Figure 62. TRIG CLKIN Setup and Hold

Table 9. DIV_EN Register

DIV_EN

DESCRIPTION

0

1

Divider disabled and bypassed

Divider enabled

Table 10. DIV_FRC Register

DIV_FRC

DESCRIPTION

0

1

Input divider ratio = serialization factor⁽¹⁾(automatically set)

Input divider ratio = DIV_REG (manually set)

(1) The divider ratio is automatically calculated to the serialization factor value based on the CH_OUT_DIS[1:4] register bits; see Table 12.

Table 11. DIV_REG Register

DIV_REG

DESCRIPTION

Divider disabled and bypassed

0

1

2

3

Divide-by-2

Divide-by-3

Divide-by-4

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8.3.7 Data Output Serialization

The input signals are digitized by the dedicated channel ADCs. Digitized signals are multiplexed and output on

D[11:0] as parallel data.

The output data rate and the DCLK speed are automatically calculated based on the CH_OUT_DIS[1:4] bits. The

number of zeroes in these four bits is equal to the serialization factor for the output data. When the register bit is

set to 1, the output for the respective channel is disabled. The channels are arranged in ascending order, with

the lowest active channel output first and the highest active channel output last. CH_OUT_DIS[1:4] controls only

the output serialization and does not power-down individual channels. Table 12 lists the register values with the

respective serialization factors and output sequence.

Table 12. CH_OUT_DIS Register

SERIALIZATION

CH_OUT_DIS[1] CH_OUT_DIS[2] CH_OUT_DIS[3] CH_OUT_DIS[4]

FACTOR

OUTPUT

CH1 → CH2 → CH3 → CH4

CH2 → CH3 → CH4

CH1 → CH3 → CH4

CH3 → CH4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

3

2

3

2

1

3

2

1

2

1

CH1 → CH2 → CH4

CH2 → CH4

CH1 → CH4

CH4

CH1 → CH2 → CH3

CH2 → CH3

CH1 → CH3

CH3

CH1 → CH2

CH2

CH1

Not supported

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8.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs

8.3.8.1 Main Channels

The device analog input consists of a differential LNA. The common-mode for the LNA inputs is internally set

using two internal, programmable, single-ended resistors, as shown in Figure 63.

IN_IP

RINT_{TERM_LNA}

1 kꢀ

LNA

RINT_{TERM_LNA}

1 kꢀ

IN_IM

Internal Voltage

Reference

CM_LNA Buffer

Device

Figure 63. Common-Mode Biasing of LNA Input Pins

These resistors can be programmed to a higher value using the TERM_INT_20K_LNA register setting as

described in Table 13.

Table 13. Internal Termination Register Setting (LNA)

TERM_INT_20K_LNA

DESCRIPTION

0

1

RINT_{TERM_LNA}= 1 kΩ

RINT_{TERM_LNA}= 10 kΩ

Hence, for proper operation, the input signal must be ac-coupled. Note that external input ac-coupling capacitors

form a high-pass filter (HPF) with RINT_{TERM_LNA}. Therefore, the capacitor values should allow the lowest

frequency of interest to pass with minimum attenuation. For typical frequencies greater than 1 MHz, a value of 50

nF or greater is recommended. The maximum input swing is limited by the LNA gain setting. LNA output swing is

limited to 2 V_PPbefore the output becomes saturated or distorted.

Single ended mode of operation is also possible by connecting non-driven input pin to ground through a

capacitor of 100 nF. However, this will result in reduced linearity.

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8.3.8.2 Auxiliary Channel

The auxiliary analog inputs (IN_IP_AUX, IN_IM _AUX) can be enabled instead of the IN_IP, IN_IM inputs using the

AUX_CH_I_EN bits (Table 14). The auxiliary analog input signal path consists of an input unity-gain buffer

followed by an ADC. The LNA, PGA, equalizer, and antialiasing filter are bypassed and powered down in this

mode. Figure 64 shows the internal block diagram for auxiliary channel mode. When this mode is enabled, the

maximum input swing is limited to 2 V_PPbefore the input becomes saturated or distorted.

Table 14. AUX_CH_I_EN Register

AUX_CH_I_EN

DESCRIPTION

0

1

IN_IP, IN_IM active, analog

IN_IP _AUX, IN_IM_AUX

IN_IP_AUX

RINT_{TERM_AUX}

1 kꢀ

BUF

RINT_{TERM_AUX}

IN_IM_AUX

VCM

Internal Voltage

Reference

CM_AUX Buffer

Device

NOTE: Dashed area denotes one of four channels.

Figure 64. Common-Mode Biasing of Auxiliary Channel Input Pins

The dc common-mode on the IN_IP_AUX, IN_IM _AUX pins are internally biased to the optimum voltage (referred

to as VCM).

The dc common-mode biasing is set with two internal, programmable, single-ended resistors (RINT_{TERM_AUX}).

These resistors can be programmed to a higher value using the TERM_INT_20K_AUX register setting as

described in Table 15.

Table 15. Internal Termination Register Setting (AUX)

TERM_INT_20K_AUX

DESCRIPTION

0

1

RINT_{TERM_AUX}= 1 kΩ

RINT_{TERM_AUX}= 10 kΩ

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The auxiliary inputs can also be ac-coupled as a result of the internal common-mode setting. The external input

ac-coupling capacitors form a high-pass filter with RINT_{TERM_AUX}. Therefore, the capacitor values should allow

the lowest frequency of interest to pass with minimum attenuation.

For typical frequencies greater than 1 MHz, a value of 50 nF or greater is recommended. For instances where

the input signal cannot be ac-coupled because of system requirements, it is recommended to use the VCM

output to set the dc common-mode of the input signal. The driving capability of VCM is limited. A 100-nF

capacitor should be connected on each VCM input to AVSS.

8.4 Device Functional Modes

8.4.1 Equalizer Mode

In some applications, the input signal power linearly decreases with signal frequency. Such types of input

spectrum can be equalized using a first-order signal equalizer. The device can be configured in two different

equalizer modes: EQ_EN and EQ_EN_LOW_FC. Table 16 lists the register settings for these modes.

•

EQ_EN mode: In this mode, a high-pass filter (HPF) is added to the analog signal path between the LNA

output and PGA input.

•

EQ_EN_LOW_FC mode: In this mode, attenuation from the HPF is limited to unity in the pass-band

frequency range.

Table 16. EQ_EN and EQ_EN_LOW_FC Registers

EQ_EN

EQ_EN_LOW_FC

DESCRIPTION

0

1

0

1

0

1

Default mode

Equalizer enabled

Equalizer with low-corner frequency enabled

The HPF and LPF cutoff frequencies (of the antialiasing filter) are the same as per the FILTER_BW setting. In

this mode, overall channel gain increases by an additional fixed gain of 15 dB from the HPF block. Typical

frequency response plots showing different equalizer modes along with the default mode are shown in Figure 65

and Figure 66.

30

20

60

50

10

40

0

30

œ10

œ20

œ30

œ40

œ50

20

10

Default Mode (Eq_Dis)

Eq_EN

Default Mode (Eq_Dis)

Eq_EN

0

œ10

œ20

Eq_EN_LOW_FC

0.1

1

10

0.1

1

10

f_IN(MHz)

C001

Figure 65. Filter Response (PGA Gain = 0 dB)

Figure 66. Filter Response (PGA Gain = 30 dB)

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8.4.2 Data Output Mode

The functionality of DSYNC1, DSYNC2, DCLK, and D[11:0] are controlled by selecting the data output mode.

The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins for 4x serialization modes are shown

in Figure 67 and Figure 68. Any event on the TRIG pin triggers the DSYNC1 and DSYNC2 signals. The DSYNC1

period is determined by the COMP_DSYNC1 register value and the DSYNC2 period is determined by the

SAMPLE_COUNT register value. When OUT_MODE_EN = 0, data output is continuous. When OUT_MODE_EN

= 1, data is active only during the sample phase. Output pins are configured using the registers described in

Table 17 through Table 21.

CLKIN

INPUT

TRIG

CYCLE RESET

TRIG_INT

t_{AFE_CLK}

Pixel = 0 Pixel = 1 Pixel = 2

Pixel = 3

INTERNAL

AFE_CLK

t_OUT

Pixel = 0 Pixel = 1 Pixel = 2

Pixel = 3

CH4

(8)

CH4

(8)

CH3

(5)

CH3 CH4 CH1

CH3

(8)

CH3

(8)

CH1

(9)

CH3

(9)

D[11:0]

CH1

(1)

CH3

(1)

CH1 CH2

(5) (5)

CH4 CH1 CH2

(5) (6) (6)

CH2 CH3 CH4 CH1 CH2

CH1 CH2

(8) (8)

CH2

(9)

CH1 CH2 CH3 CH4

(0) (0) (0) (0)

CH2

(1)

CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4

CH1 CH2 CH3 CH4 CH1

CH1 CH2 CH3 CH4

(6)

(7)

(2)

(3)

(4)

(7)

(8)

(1)

OUT_MODE_EN = 0

D[11:0]

OUT_MODE_EN = 1

CH1 CH2 CH3

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2

CH4

CH1 CH2 CH3 CH4

CH1 CH2

CH1 CH2 CH3

CH1 CH2

CH4

DCLK

COMP_DSYNC1

DSYNC1_HIGH

DSYNC1

OUTPUT

DSYNC2_LOW

BLANKING PHASE

SAMPLE PHASE

DELAY PHASE

T_{TRIG_DSYNC2_LAT}

DELAY PHASE

DSYNC2

SAMPLE COUNT = N

t_DSYNC2= (N+1) * t_{AFE_CLK}

SAMPLE COUNT = N

t_DSYNC2= (N+1) * t_{AFE_CLK}

Figure 67. Data Output Timing Diagram (4x Serialization)

CLKIN

Input

TRIG

TRIG_INT

AFE_CLK

Internal

t_{AFE_CLK}

Pixel = 0

Pixel = 1

Pixel = 2

Pixel = 3

t_OUT

Pixel = 0

Pixel = 1

Pixel = 2

Pixel = 3

D[11:0]

OUT_MODE_EN = 0

CH4

(8)

CH3

(5)

CH3 CH4 CH1

CH3

(8)

CH1

(1)

CH3

(1)

CH1 CH2

(5) (5)

CH4 CH1 CH2

CH2 CH3 CH4 CH1 CH2

(7) (7) (7) (8) (8)

CH1 CH2 CH3 CH4

CH2

(1)

CH4

(1)

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4

(2) (2) (3) (3) (3) (3) (4) (4) (4) (4)

CH1 CH2 CH3 CH4

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2

CH1 CH2

CH1 CH2 CH3 CH4

(6)

(7)

(0)

(2)

(5)

(6)

D[11:0]

OUT_MODE_EN = 1

CH3

(5)

CH1

(1)

CH3

(1)

CH1 CH2

(5) (5)

CH4

(5)

CH1 CH2 CH3 CH4

(0) (0) (0) (0)

CH2

(1)

CH4

(1)

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4

(2) (2) (3) (3) (3) (3) (4) (4) (4) (4)

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2

CH1 CH2 CH3 CH4

CH1 CH2

(2)

DCLK

Output

DSYNC1 COMP_DSYNC1 = 2

DSYNC2

SAMPLE_COUNT = N

t_DSYNC2= (N+1) x t_{AFE_CLK}

Figure 68. Data Output Timing Diagram (4x Serialization, Input Divider Enabled)

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Table 17. Register Functions

REGISTER

FUNCTION

DELAY_COUNT[23:0]

SAMPLE_COUNT[23:0]

COMP_DSYNC1[15:0]

From a TRIG event, the sample phase is delayed for a DELAY_COUNT number of t_{AFE_CLK}cycles

From the end of DELAY_PHASE, the sample phase duration is the SAMPLE_COUNT number of

t_{AFE_CLK}cycles

DSYNC1 period in number of t_{AFE_CLK}cycles

Table 18. DSYNC1_START_LOW Register

DSYNC1_START_LOW

DESCRIPTION

DSYNC1 is high at the sample phase start

0

1

DSYNC1 is low at the sample phase start

Table 19. OUT_MODE_EN Register

OUT_MODE_EN

DESCRIPTION

Data always active

0

1

Data active in sample phase

Table 20. DSYNC_EN Register

DSYNC_EN

DESCRIPTION

Disable DSYNC generation

0

1

Enable DSYNC generation

Table 21. OUT_BLANK_HIZ Register

OUT_BLANK_HIZ

DESCRIPTION

D[11:0] is low during inactive phase

0

1

D[11:0] is high impedance during inactive phase

NOTE

The signal processing blocks in the device are always active and are not controlled by

output mode configuration settings.

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The functionality of the DSYNC1, DSYNC2, DCLK, and D[11:0] output pins with the input divider enabled for 3x

serializations is shown in Figure 69.

CLKIN

INPUT

TRIG

TRIG_INT

Pixel = 0 Pixel = 1Pixel = 2

Pixel = 3

t_{AFE_CLK}

INTERNAL

AFE_CLK

Pixel = 0 Pixel = 1Pixel = 2

Pixel = 3

D[11:0]

OUT_MODE_EN = 0

CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1

CH3 CH1 CH2

(10)

CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1

CH3 CH1 CH2

CH2

(9)

CH1 CH2 CH3

(0) (0) (0)

CH2 CH3 CH1 CH2 CH3

CH1 CH2

(5) (5)

CH1

(1)

CH1 CH2 CH3 CH1 CH2 CH3

CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3

(8)

(9)

(11) (11) (11) (12) (12) (12) (13)

(5)

(6)

(7)

(8)

(9)

(10) (10)

(1)

(2)

(1)

(3)

(4)

D[11:0]

CH3 CH1 CH2 CH3

CH3 CH1 CH2

CH1 CH2 CH3

(0) (0) (0)

CH2 CH3 CH1 CH2 CH3

CH1 CH2

(5) (5)

CH1

(1)

CH1 CH2 CH3 CH1 CH2 CH3

(3) (3) (3) (4) (4) (4)

CH1 CH2 CH3 CH1 CH2 CH3 CH1 CH2 CH3

(5)

(6)

(7)

(1)

(2)

(1)

OUT_MODE_EN = 1

DCLK

DSYNC1

COMP_DSYNC1=2

OUTPUT

DSYNC2

SAMPLE COUNT = N

t_DSYNC2= (N+1)* t_{AFE_CLK}

Figure 69. Data Output Timing (3x Serialization, Input Divider Enabled)

The TRIG to DSYNC2 latency is given by Table 22.

Table 22. TRIG to DSYNC2 Latency across Serialization Modes for AFE_CLK = 25 MHz

(1)

Serialization Modes

T_{TRIG_DSYNC2_LAT}

Units

ns

4x

3x

2x

1x

230

240

250

ns

(1) The TRIG_DSYNC2_LAT delay can vary by ± 8 ns.

8.4.2.1 Header

Each channel has an associated 12-bit header register. These registers can be written by an SPI write. The

content of this register can be read out on the CMOS data output (D[11:0]) by configuring the HEADER_MODE

register, as shown in Table 23.

Table 23. HEADER_MODE Register

HEADER_MODE

DESCRIPTION

0

1

2

3

ADC data at output

Header data at output

[Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data sequence is repeated.

Header data, temperature data, diagnostic data, mean, noise, ADC data

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In HEADER_MODE = 3, the header mode data output is shown in Figure 70.

In this mode, header data is transmitted with a latency with respect to the TRIG input. This latency is given by

Equation 2:

TRIG to Header Latency (T_{TRIG_HEADER_LAT}) = t_{AFE_CLK}+ T_{TRIG_DSYNC2_LAT}

(2)

TRIG

CLKIN

AFE_CLK

TRIG_INT

DCLK

DATA

T_{TRIG_DSYNC2_LAT}

DSYNC2

T_{TRIG_HEADER_LAT}

Figure 70. Header Mode Data Output (HEADER_MODE = 3)

8.4.2.2 Test Pattern Mode

In order to check the interface between the AFE and the receiver system, a test pattern can be directly

programmed on the CMOS output. As shown in Table 24, different test patterns can be selected by setting the

TST_PAT_MODE register.

Table 24. TST_PAT_MODE Register⁽¹⁾

TST_PAT_MODE

DESCRIPTION

0

1

2

3

4

5

6

7

Normal ADC output data

SYNC pattern (D[11:0] = 111111000000)

Deskew pattern (D[11:0] = 010101010101)

Custom pattern as per CUSTOM_PATTERN[11:0] register bits

All 1s

Toggle data (output toggles between all 0s and all 1s)

All 0s

Full-scale ramp data

(1) In decimate-by-2 mode, alternate samples are dropped and thus output data D0 does not toggle for full-scale ramp data and output data

D[11:0] does not toggle for toggle data.

Similarly, in decimate-by-4 mode, three samples are dropped and thus output data D0 and D1 do not toggle for full-scale ramp data and

output data D[11:0] does not toggle for toggle data.

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8.4.3 Parity

Parity for each output sample of an active channel can be read on the D_GPO[1:0] pins by configuring these pins

with the DGPO1_MODE, DGPO0_MODE register, as shown in Table 25. Parity generation can be enabled using

the D_GPO_EN bit, as shown in Table 26. The type of parity generation can be configured to odd or even based

on the PARITY_ODD bit, as shown in Table 27.

Table 25. DGPO0_MODE, DGPO1_MODE Register

DGPO0_MODE, DGPO1_MODE

DESCRIPTION

0

1

2

3

Low

Parity

Overload

D[11]

Table 26. D_GPO_EN Register

D_GPO_EN

DESCRIPTION

0

1

D_GPO[x] pins are disabled

D_GPO[x] pins are enabled

Table 27. PARITY_ODD Register

PARITY_ODD

DESCRIPTION

0

1

Even

Odd

8.4.4 Standby, Power-Down Mode

The device can be put into standby mode with the STDBY register bit. In this mode, all blocks except the ADC

reference blocks are powered down. In GLOBAL_PDN mode, all blocks including the ADC reference blocks are

powered down. However, in both modes, the serial interface is active.

8.4.5 Digital Filtering to Improve Stop-Band Attenuation

The device introduces a standard 11-tap, symmetric finite impulse response (FIR) digital filter for additional stop-

band attenuation in decimate-by-2 and decimate-by-4 modes. In both modes, the FIR digital filter coefficients (C1

to C6) must be configured to obtain the desired filter characteristics. However, set 1 coefficients are loaded by

default at device reset.

In this mode, device power consumption increases and the DSYNC period scales according to the decimation

mode (the DSYNC period increases by 2x in decimate-by-2 mode and 4x in decimate-by-4 mode when

compared to normal mode). Maximum AFE_CLK frequency supported in the decimation modes is 50 MHz.

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8.4.5.1 Decimate-by-2 Mode

In this mode, the DECIMATE_2_EN and FILT_EN register bits must be set, and the filter coefficients should be

configured. Figure 71 shows typical filter response in decimate-by-2 mode for the filter coefficient of set 1

(default). Note that the output data rate is reduced by a factor of 2 as compared to default mode for the given

clock input frequency.

20

10

0

œ10

œ20

œ30

œ40

œ50

œ60

Default Mode

œ70

DECIMATE_2_EN = 1

œ80

0.1

1

10

f_IN(MHz)

C037

Figure 71. Decimate-by-2 Filter Response (f_S= 50 MHz)

8.4.5.2 Decimate-by-4 Mode

In this mode, the DECIMATE_2_EN, DECIMATE_4_EN, and FILT_EN register bits must be set, and the filter

coefficients should be configured. Figure 72 shows a typical filter response in decimate-by-4 mode for the filter

coefficient of set 1 (default) and set 2. Note that the output data rate is reduced by a factor of 4 as compared to

default mode for the given clock input frequency.

10

0

œ10

œ20

œ30

œ40

œ50

DECIMATE_4_EN = 1, Set 2

œ60

DECIMATE_4_EN = 1, Set 1

œ70

0.1

1

f_IN(MHz)

C038

(1) Set 1: C1 = 5, C2 = 2, C3 = –13, C4 = –2, C5 = 38, and C6 = 66. Set 2: C1 = –5, C2 = –2, C3 = 7, C4 = 19, C5 = 30, and C6 = 34.

Figure 72. Decimate-by-4 Filter Response (f_S= 12.5 MHz)

8.4.6 Diagnostic Mode

The device offers various diagnostic modes to check proper device operation at a system level. These modes

can be enabled using the SPI and the outputs of these modes are stored in diagnostic read-only registers.

1. Internal reference status check: In this mode, the on-chip band-gap voltage, ADC reference, and clock

generation are verified for functionality. Reading a 0 on these bits indicates that these blocks are functioning

properly. The DIAG_MODE_EN register bit must be set to 1. The DIG_REG register bits for this mode are:

–

DIG_REG[0] for ADC references,

DIG_REG[1] for band gap, and

DIG_REG[2] for clock generation.

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2. DC input force: In this mode, a dc voltage can be internally forced at the LNA input to test the entire signal

chain. During this test, the device analog inputs should be left floating. This mode can be asserted by setting

the DC_INP_EN bit to 1 and programming the DC_INP_PROG[0:2] bits. In this mode, the equalizer is

disabled internally.

3. Variance (noise) and mean measurement: Variance and mean of the ADC output can be analyzed using the

on-chip STAT module. The STAT_EN, STAT_CALC_CYCLE, and STAT_CH_SEL, STAT_CH_AUTO_SEL

options should be set to compute the variance and mean. These values can be monitored using channel-

specific, read-only registers. Alternatively, these values can also be read using HEADER_MODE. Output

variance and mean calculation is determined by Equation 3.

(3)

STAT_CALC_CYCLE must be set to a large value to obtain better accuracy. Mean provides the average dc

value of the ADC output (mid code). The STAT module integration time is defined by: t_{AFE_CLK}

2^{(STAT_CALC_CYCLE+1)}when the STAT_CH_SEL option is selected. When STAT_CH_AUTO_SEL is enabled,

the STAT module integration time is defined by: 4 × t_{AFE_CLK}× 2^{(STAT_CALC_CYCLE+1)}

×

.

4. Temperature sensor: The device junction temperature measurement can be enabled and monitored using

TEMP_SENS_EN and TEMP_CONV_EN. The temperature output is saved in a diagnostic read-only

register, TEMP_DATA. Alternatively, this data can also be read using HEADER_MODE. The TEMP_DATA

value is a 9-bit, twos complement data in degrees Celsius. The temperature data is internally updated as per

Equation 4:

Temperature Data Update Cycle = 1024 × T_{AFE_CLK}× 16

(4)

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8.4.7 Signal Chain Probe

To enhance system-level debug capabilities, the device offers a mode where the output of each block in the

signal chain can be connected to the ADC input. With this mode, internal signals can be easily monitored to

ensure that each block output is not saturated. Figure 73 shows the device signal chain block diagram. Figure 74

and Figure 75 show typical frequency response plots at the output of each stage.

LNA

AMP 1

AMP 2

AMP 3

MUX

ADC

PGA + Antialiasing Filter

VOUT_ON_ADC[1:0]

Figure 73. Signal Chain Block Diagram

20

15

45

40

35

30

25

20

15

10

5

0

œ5

œ10

œ15

œ20

œ25

AMP1_OUT_ADC

AMP2_OUT_ADC

LNA_OUT_ADC

AMP1_OUT_ADC

AMP2_OUT_ADC

LNA_OUT_ADC

5

0

œ5

0.1

1

10

0.1

1

10

f_IN(MHz)

C001

Figure 74. Frequency Response for

VOUT_ON_ADC Settings (PGA Gain = 0 dB)

Figure 75. Frequency Response for

VOUT_ON_ADC Settings (PGA Gain = 30 dB)

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8.5 Programming

8.5.1 Serial Interface

Different modes can be programmed through the serial interface formed by the SEN (serial interface enable),

SCLK (serial interface clock), SDATA (serial interface data) and RESET pins. SCLK and SDATA have a 150-kΩ

pull-down resistor to ground and SEN has a 150-kΩ pull-up resistor to DVDD18. Serially shifting bits into the

device is enabled when SEN is low. SDATA serial data bits are latched at every SCLK rising edge when SEN is

active (low). Serial data bits are loaded into the register at every 24th SCLK rising edge when SEN is low. If the

word length exceeds a multiple of 24 bits, the excess bits are ignored. Data bits can be loaded in multiples of 24-

bit words within a single active SEN pulse (an internal counter counts groups of 24 clocks after the SEN falling

edge). The interface can function with SCLK frequencies from 20 MHz down to very low speeds and even with a

non-50% duty-cycle SCLK. Data bits are divided into two main portions: a register address (8 bits, A[7:0]) and

data (16 bits, D[15:0]).

8.5.2 Register Initialization

After power up, the internal registers must be initialized to the default value (0). Initialization can be accomplished

in one of two ways:

•

Either through a hardware reset, by applying a positive pulse to the RESET pin, or

Through a software reset with the serial interface, by setting the SW_RST bit high. Setting this bit initializes

the internal registers to the respective default values (all 0s) and then self-resets the SW_RST bit low. In this

case, the RESET pin can stay low (inactive).

NOTE

•

No damage occurs to the part by applying voltage to the RESET pin while device

power is off.

For correct device operation, a positive pulse must be applied to the RESET pin. This

pulse sets the internal control registers to 0. However, no power-supply sequencing is

required.

•

Reset only affects the digital registers and places the device in a default state. Reset

does not function as a power-down and, therefore, all internal blocks are functional.

During a register write through the SPI, the effects on data propagate through the pipe while the internal registers

change values. At the same time, some glitches may be present on the output because of the transition of

register values (for instance, if any output-controlling modes change). The signal on the RESET pin must be low

in order to write to the internal registers because reset is level-sensitive and asynchronous with the input clock.

Although only 40 ns are required after the RESET rising edge to change the registers, the output data may take

up to 20 clock cycles (worst-case) to be considered stable. For more information on RESET, see the Timing

Requirements: RESET.

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Programming (continued)

8.5.2.1 Register Write Mode

In register write mode, the REG_READ_EN bit must be set to 0. In this mode, the SDOUT signal outputs 0.

Figure 76 shows this process.

SEN

End Sequence

t₆

t₁

t₇

Data latched on rising edge of SCLK

t₂

SCLK

t₃

A[7]

A[6] A[5] A[4]

A[3] A[2] A[1] A[0] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

SDATA

t₄

t₅

SDOUT

Figure 76. Serial Interface Register Write

8.5.2.2 Register Read Mode

In register readout mode, the REG_READ_EN bit must be set to 1. Then, a serial interface cycle should be

initiated, specifying the address of the register (A[7:0]) whose content must be read out of the device. The data

bits are don’t care. The device outputs the contents (D[15:0]) of the selected register on the SDOUT pin. The

external controller latches the data on SDOUT at the SCLK rising edge. Figure 77 shows this process.

The timing specifications for the serial interface operation is listed in the Timing Requirements: Serial Interface

Operation.

SEN

End Sequence

t₆

t₁

t₇

t₂

SCLK

t₃

A[7]

A[6] A[5] A[4] A[3] A[2] A[1] A[0]

X

SDATA

t₄

SDOUT to be latched externally on rising

edge

t₅

t₈

D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

SDOUT

Figure 77. Serial Interface Register Readout Enable

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Programming (continued)

8.5.3 CMOS Output Interface

The digital data from the four channels are multiplexed and output over a 12-bit parallel CMOS bus to reduce the

device pin count. In addition to the data, a CMOS clock (DCLK) is also output, which can be used by the digital

receiver to latch the AFE output data. The output data and clock buffers can typically drive a 5-pF load

capacitance in default mode. To drive larger loads (10 pF to 15 pF), the strength of the CMOS output buffers can

be increased using the STR_CTRL_CLK and STR_CTRL_DATA register bits. Note that the setup and hold time

of the output data (with respect to DCLK) degrade with higher load capacitances. See Table 1, which provides

timings for 5-pF and 15-pF load capacitances.

8.5.3.1 Synchronization and Triggering

While the digital data from the four channels is multiplexed on the output bus, some mechanism is required to

identify the data from the individual channels. Other than the output data and DCLK, the device also outputs

DSYNCx signals that can be used for channel identification.

The DSYNCx output signals function with the TRIG input signal. Every time that a trigger pulse is received on the

TRIG pin, the device outputs the DSYNC1 and DSYNC2 signals. The DSYNCx signals can be configured in the

following ways:

•

The delay between the arrival of the TRIG signal and the DSYNCx signal becoming active is programmable in

a number of AFE_CLK cycles (using the DELAY_COUNT register bit).

The period of the DSYNC1 signal is programmable in terms of AFE_CLK clock cycles by using the

COMP_DSYNC1 register bits.

The active time of the DSYNC2 signal is programmable using the SAMPLE_COUNT register bits.

The rising edge of the DSYNC1 signal coincides with the channel 1 data, as shown in Figure 78. This occurrence

can be used by the receiving device to identify individual channels.

The sample phase period corresponds to the period when valid data is available from the device when

OUT_MODE_EN = 1.

CLKIN

INPUT

TRIG

CYCLE RESET

TRIG_INT

t_{AFE_CLK}

Pixel = 0 Pixel = 1 Pixel = 2

Pixel = 3

INTERNAL

AFE_CLK

t_OUT

Pixel = 0 Pixel = 1 Pixel = 2

Pixel = 3

CH4

(8)

CH4

(8)

CH3

(5)

CH3 CH4 CH1

CH3

(8)

CH3

(8)

CH1

(9)

CH3

(9)

D[11:0]

CH1

(1)

CH3

(1)

CH1 CH2

(5) (5)

CH4 CH1 CH2

(5) (6) (6)

CH2 CH3 CH4 CH1 CH2

CH1 CH2

(8) (8)

CH2

(9)

CH1 CH2 CH3 CH4

(0) (0) (0) (0)

CH2

(1)

CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4

CH1 CH2 CH3 CH4 CH1

CH1 CH2 CH3 CH4

(6)

(7)

(2)

(3)

(4)

(7)

(8)

(1)

OUT_MODE_EN = 0

D[11:0]

OUT_MODE_EN = 1

CH1 CH2 CH3

CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2

CH4

CH1 CH2 CH3 CH4

CH1 CH2

CH1 CH2 CH3

CH1 CH2

CH4

DCLK

COMP_DSYNC1

DSYNC1_HIGH

DSYNC1

OUTPUT

DSYNC2_LOW

BLANKING PHASE

SAMPLE PHASE

DELAY PHASE

T_{TRIG_DSYNC2_LAT}

DELAY PHASE

DSYNC2

SAMPLE COUNT = N

t_DSYNC2= (N+1) * t_{AFE_CLK}

SAMPLE COUNT = N

t_DSYNC2= (N+1) * t_{AFE_CLK}

Figure 78. DSYNCx Timing Diagram

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8.6.2 Register Descriptions

Figure 79. Register 0 (00h)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

REG_READ_

EN

SW_RST

Bits 15:2

Bit 1

Must write 0

REG_READ_EN: Register read mode

0 = Write (default)

1 = Enable register read

Bit 0

SW_RST: Software reset

This bit is the software reset for the entire device. This bit is self-clearing.

Figure 80. Register 1 (01h)

15

0

14

0

13

0

12

0

11

0

10

9

0

8

0

STDBY

7

6

5

4

3

2

1

0

DECIMATE_4_

EN

DECIMATE_2_

EN

SE_CLK_

MODE

DIV_REG

DIV_FRC

DIV_EN

GLOBAL_PDN

Bits 15:11

Bit 10

Must write 0

STDBY: Full device standby

0 = Normal (default)

1 = Standby

Bits 9:8

Bit 7

Must write 0

DECIMATE_4_EN

0 = Decimate-by-4 mode not enabled

1 = Decimate-by-4 mode enabled

The DECIMATE_2_EN and FILT_EN bits must be set.

FIR filter coefficients (C1 to C6) must be written for proper operation.

If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must be set.

Bits 6:5

DIV_REG: Input clock divider ratio in DIV_FRC mode

DIV_REG

f_{AFE_CLK}

0

1

2

3

CLKIN ÷ 1

CLKIN ÷ 2

CLKIN ÷ 3

CLKIN ÷ 4

Input divider disabled and bypassed

Bit 4

DIV_FRC: Force input divider ratio

0 = Auto computed based on CH_OUT_DISx (default). For more details, refer to Table 12.

1 = AFE clock frequency is based on DIV_REG settings

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Bit 3

DECIMATE_2_EN

0 = Normal mode

1 = Decimate-by-2 mode enabled

The FILT_EN bit must be set for proper operation.

FIR filter coefficients (C1 to C6) must be written for proper operation.

If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must also be set.

Bit 2

Bit 1

Bit 0

DIV_EN: Enable CLKIN divider

0 = Disabled and bypassed (default)

1 = Enabled

SE_CLK_MODE: Single-ended input clock configuration

0 = Differential (default)

1 = Single-ended

GLOBAL_PDN: Full device power-down

0 = Normal (default)

1 = Global PDN

Figure 81. Register 2 (02h)

15

14

13

5

12

0

11

0

10

0

9

0

8

0

TST_PAT_MODE

7

0

6

4

3

2

0

1

0

DGPO0_MODE

DGPO1_MODE

Bits 15:13

TST_PAT_MODE: Test pattern for CMOS output

0 = Normal (default)

1 = SYNC

2 = Deskew

3 = Custom register 5[15:0]

4 = All 1s

5 = Toggle

6 = All 0s

7 = Ramp

Bits 12:7

Bits 6:5

Must write 0

DGPO0_MODE: DGPO0 mode configuration

0 = Low (default)

1 = Parity

2 = Overload

3 = D[11]

Bits 4:3

Bits 2:0

DGPO1_MODE: DGPO1 mode configuration

0 = Low (default)

1 = Parity

2 = Overload

3 = D[11]

Must write 0

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Figure 82. Register 3 (03h)

15

0

14

0

13

0

12

0

11

0

10

0

9

1

8

0

TEMP_DATA

7

6

5

4

3

2

TEMP_DATA

Bits 15:10

Bits 9:0

Ignore bits

TEMP_DATA: Read-only temperature readout register

Data is 9-bit, twos complement format in degrees Celsius.

Figure 83. Register 4 (04h)

15

14

13

12

11

10

0

9

0

8

0

OUT_BLANK_

HIZ

OUT_MODE_

EN

TEMP_CONV_ TEMP_SENS_

DCLK_INVERT

EN

3

7

0

6

0

5

0

4

0

2

0

1

0

OFF_BIN_

DATA_FMT

Bit 15

OUT_BLANK_HIZ: Output status during blanking phase

0 = D[11:0] and D_GPO[1:0] are low (default) if EN_OUT_MODE = 1

1 = D[11:0] and D_GPO[1:0] are Hi-Z if EN_OUT_MODE = 1

For more details, refer to Figure 67.

Bit 14

Bit 13

Bit 12

Bit 11

OUT_MODE_EN: Enables output mode gating with DSYNC2

0 = CMOS data is always active (default)

1 = Output mode enabled. Data is transmitted only during sample phase.

DCLK_INVERT: Invert DCLK

0 = DCLK rising edge at the center of data (default)

1 = DCLK falling edge at the center of data

TEMP_CONV_EN: Enable Temperature Sensor output to digital conversion

0 = Hold conversion

1 = Convert

TEMP_SENS_EN: Enable temperature sensor block

0 = Disable temperature sensor

1 = Enable temperature sensor

Bits 10:4

Bit 3

Must write 0

OFF_BIN_DATA_FMT: Output data format

0 = Twos complement (default)

1 = Offset binary

Bits 2:0

Must write 0

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Figure 84. Register 5 (05h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CUSTOM_PAT

4

3

CUSTOM_PAT

Bits 15:0

CUSTOM_PAT: Custom pattern data

These bits set the custom data pattern.

Figure 85. Register 6 (06h)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

DIAG_REG[2:0]

Bits 15:3

Bits 2:0

Ignore bits

DIAG_REG: Read only diagnostic readout register

DIAG_REG[0] = 0: ADC references are correct

DIAG_REG[1] = 0: Indicates band gap is correct

DIAG_REG[2] = 0: Indicates clock generation is correct

Figure 86. Register 7 (07h)

15

14

13

12

11

3

10

9

1

8

D_GPO_EN

PARITY_ODD

STAT_EN

DC_INP_EN

DC_INP_PROG

DIAG_MODE_

EN

7

0

6

0

5

0

4

0

2

0

FILTER_BW

HEADER_MODE

Bit 15

Bit 14

Bit 13

Bit 12

D_GPO_EN: Enable D_GPO functionality

0 = D_GPO[x] pins are disabled (default)

1 = D_GPO[x] pins are enabled

PARITY_ODD: Parity type

0 = Even (default)

1 = Odd

STAT_EN: Enable noise and mean calculation of ADC output

0 = Default

1 = Enables noise and mean computation if STAT_CALC_CYCLE is set.

DC_INP_EN: Enable dc analog voltage at LNA input. In this mode, equalizer is

disabled automatically.

0 = Normal

1 = DC input force is controlled by DC_INP_PROG.

Bits 11:9

DC_INP_PROG: DC Input programmability

0 = 0 mV

1 = 0 mV

2 = 50 mV

3 = –50 mV

4 = 100 mV

5 = –100 mV

6 = 100 mV

7 = –100 mV

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AFE5401-Q1

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Bit 8

DIAG_MODE_EN: Enable diagnostic mode

0 = Disable diagnostic circuit

1 = Enable diagnostic circuit

Bits 7:4

Bits 3:2

Must write 0

FILTER_BW: Filter corner frequency

0 = 8 MHz (default)

1 = 7 MHz

2 = 10.5 MHz

3 = 12 MHz

Bits 1:0

HEADER_MODE: Header output mode

0 = ADC data at output (default)

1 = Header data at output

2 = [Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data

sequence is repeated.

3 = Header data, temperature data, diagnostic data, mean, noise, ADC data.

Refer to Figure 70 for more information.

Figure 87. Register 8 (08h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

C2_FIR

4

3

DIG_GAIN_C1_FIR

(1)

Bits 15:8

C2_FIR: Coefficient C2 for FIR digital filter

2 = Default value

Bit 7:0

DIG_GAIN_C1_FIR: Digital Gain common for all channels, coefficient C1 for

decimation filter

where:

•

(DIG_GAIN + 32) is Mod⁽²⁾128.

(5)

Refer to Figure 60 for more information.

Mode

C1 Functionality

With MULT_EN

With DECIMATE_X _EN

5 = Default value

DIG_GAIN

Coefficient C1 for FIR digital filter

(1) C1 to C6 FIR filter coefficients are in twos complement form.

(2) Mod = Remainder of the division.

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Figure 88. Register 9 (09h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

C4_FIR

4

3

C3_FIR

Bits 15:8

C4_FIR: Coefficient C4 for FIR digital filter⁽¹⁾

–2 = Default value

Bit 7:0

C3_FIR: Coefficient C3 for FIR digital filter⁽¹⁾

–13 = Default value

(1) C1 to C6 FIR filter coefficients are in twos complement form.

Figure 89. Register 10 (0Ah)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

C6_FIR

4

3

C5_FIR

Bits 15:8

C6_FIR: Coefficient C6 for FIR digital filter⁽¹⁾

66 = Default value

Bit 7:0

C5_FIR: Coefficient C5 for FIR digital filter⁽¹⁾

38 = Default value

(1) C1 to C6 FIR filter coefficients are in twos complement form.

Figure 90. Register 15 (0Fh)

15

0

14

0

13

0

12

0

11

0

10

9

0

8

0

FAST_DGPO

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bits 15:11,

Must write 0

and Bits 9:0

Bit 10

FAST_DGPO: Fast DGPO output buffer

0 = Default strength (default)

1 = Higher drive strength on D_GPO[x] pins.

Must write 0

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Figure 91. Register 19 (13h)

15

0

14

13

12

11

10

9

8

OB_DISABLE

STR_CTRL_CLK

STR_CTRL_DATA

7

6

5

0

4

0

3

0

2

0

1

0

STR_CTRL_DATA

Bits 15, Bits 5:0 Must write 0

Bit 14

OB_DISABLE: CMOS output buffers D[11:0], DCLK disabled

0 = Active CMOS output buffers

1 = Hi-Z CMOS output Buffers

Bits 13:10

STR_CTRL_CLK: Controls strength of CMOS output DCLK

buffer

STR_CTRL_CLK

Drive Strength

DRVDD (V)

0

6

Default strength (C_LOAD= 5 pF)

Maximum strength (C_LOAD= 15 pF)

Default strength (C_LOAD= 5 pF)

Maximum strength (C_LOAD= 15 pF)

3.3

1.8

5

14

All other options are reserved.

Bit 9:6

STR_CTRL_DATA: Controls strength of CMOS output DATA

buffers

STR_CTRL_DAT

A

Drive Strength

DRVDD (V)

0

6

Default strength (C_LOAD= 5 pF)

Maximum strength (C_LOAD= 15 pF)

Default strength (C_LOAD= 5 pF)

Maximum strength (C_LOAD= 15 pF)

3.3

1.8

5

14

All other options are reserved.

Figure 92. Register 21 (15h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DELAY_COUNT[23:16]

4

3

SAMPLE_COUNT[23:16]

Bits 15:8

DELAY_COUNT[23:16]: Delay counter, upper bits

These bits determine the delay phase in terms of t_{AFE_CLK}

DELAY_PHASE = (DELAY_COUNT + 1) × t_{AFE_CLK}

.

The valid range for DELAY_COUNT is from 0 to (2²⁴– 2).

The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (2²⁴– 2).

Bits 7:0

SAMPLE_COUNT[23:16]: Sample counter, upper bits

These bits determine the sample phase in terms of t_{AFE_CLK}

.

Sample phase = (SAMPLE_COUNT + 1) × t_{AFE_CLK}

.

The valid range for SAMPLE_COUNT is from 0 to (2²⁴– 2).

The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (2²⁴– 2).

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Figure 93. Register 22 (16h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DELAY_COUNT[15:0]

4

3

DELAY_COUNT[15:0]

Bits 15:0

DELAY_COUNT[15:0]: Delay counter, lower bits

These bits determine the delay phase in terms of t_{AFE_CLK}

DELAY_PHASE = (DELAY_COUNT + 1) × t_{AFE_CLK}

.

The valid range for DELAY_COUNT is from 0 to (2²⁴– 2).

The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (2²⁴– 2).

Figure 94. Register 23 (17h)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

SAMPLE_COUNT[15:0]

4

3

SAMPLE_COUNT[15:0]

Bits 15:0

SAMPLE_COUNT[15:0]: Sample counter, lower bits

These bits determine the sample phase in terms of t_{AFE_CLK}

Sample phase = (SAMPLE_COUNT + 1) × t_{AFE_CLK}

.

The valid range for SAMPLE_COUNT is from 0 to (2²⁴– 2).

The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (2²⁴– 2).

Figure 95. Register 24 (18h)

15

14

13

0

12

11

0

10

2

9

8

DSYNC1_

START_LOW

TRIG_FALL

DSYNC_EN

COMP_DSYNC1[15:6]

7

6

5

4

3

1

0

COMP_DSYNC1[15:6]

Bit 15

TRIG_FALL

0 = TRIG event on the TRIG rising edge

1 = TRIG event on the TRIG falling edge

Bit 14

DSYNC1_START_LOW: Selects DSYNC1 start level

0 = DSYNC1 starts with logic high (default)

1 = DSYNC1 starts with logic low

Bit 13

Bit 12

Must write 0

DSYNC_EN: Enable DSYNC1/2 generation

0 = Disable DSYNC1/2 signals (default - logic low)

1 = Enable DSYNC1/2 signals

Bit 11

Must write 0

Bits 10:1

COMP_DSYNC1[15:6]: DSYNC1, upper bits

These bits determine the DSYNC1 period in the number of t_{AFE_CLK}cycles. For

COMP_DSYNC1 = 0 or 1, DSYNC1 is static.

Bit 0

Must write 0

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Figure 96. Register 25 (19h)

15

7

14

6

13

12

11

10

2

9

0

8

0

COMP_DSYNC1[5:0]

5

4

3

1

0

DSYNC2_LOW[23:16]

Bits 15:10

COMP_DSYNC1[5:0]: DSYNC1, lower bits

These bits determine the DSYNC1 period in the number of t_{AFE_CLK}cycles. For

COMP_DSYNC1 = 0 or 1, DSYNC1 is static.

Bits 9:8

Bits 7:0

Must write 0

DSYNC2_LOW[23:16]: DSYNC2, upper bits

Low pulse duration of DSYNC2 in number of t_{AFE_CLK}clocks.

Figure 97. Register 26 (1Ah)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DSYNC2_LOW[15:0]

4

3

DSYNC2_LOW[15:0]

Bits 15:0

DSYNC2_LOW[15:0]: DSYNC2, lower bits

Low pulse duration of DSYNC2 in number of t_{AFE_CLK}clocks.

Figure 98. Register 27 (1Bh)

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DSYNC1_HIGH

4

3

DSYNC1_HIGH

Bits 15:0

DSYNC1_HIGH: DSYNC1

High pulse duration of DSYNC1, in number of t_{AFE_CLK}clocks.

DSYNC1 high = high for [(DSYNC1_HI + COMP_DSYNC1 ÷ 2) Mod ⁽¹⁾COMP_DSYNC1]

(1) Mod = Remainder of the division

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Figure 99. Register 29 (1Dh)

15

14

0

13

12

11

0

10

0

9

8

OFFSET_DIS

STAT_CH_SEL

STAT_CALC_CYCLE

7

6

5

4

0

3

0

2

0

1

0

STAT_CALC_CYCLE

STAT_CH_AUT

O_SEL

Bit 15

OFFSET_DIS: Bypass OFFSET addition at channel output

0 = Default. The OFFSET_CHx register value is added to the channel output.

1 = Disable OFFSET. The OFFSET_CHx register value is not added to the channel output.

Bit 14

Always write 0

Bits 13:12

STAT_CH_SEL: Manual channel selection for computation by STAT module

0 = Channel 1

1 = Channel 2

2 = Channel 3

3 = Channel 4

Bits 11:10

Bits 9:5

Always write 0

STAT_CALC_CYCLE

Number of ADC samples used for STAT computation = 2^{STAT_CALC_CYCLE+1}

STAT_CALC_CYCLE range = 0 to 30

,

and Bits 4:1

Bit 0

Always write 0

STAT_CH_AUTO_SEL: Automatic channel selection for SNR Computation

0 = Static, computation is done based on the STAT_CH_SEL selection

1 = Auto, computation is sequentially done for all four channels

Figure 100. Register 30 (1Eh)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

MULT_EN

7

6

0

5

0

4

0

3

0

2

0

1

0

FILT_EN

Bits 15:9

Bit 8

Must write 0

MULT_EN: Channel multiplier enable

0 = Disable multiplier

1 = Enable multiplier. For digital gain, DIG_GAIN_C1_FIR must be written.

Bit 7

FILT_EN: Digital decimation filter enable

0 = Disable filter

1 = Enable standard 11-tap, symmetric FIR digital filter.

Bits 6:0

Must write 0

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Figure 101. Register 32 (20h)

15

0

14

0

13

0

12

0

11

10

2

9

1

8

0

HEADER_CH1

7

6

5

4

3

HEADER_CH1

Bits 15:12

Bits 11:0

Must write 0

HEADER_CH1: Header information for channel 1

These bits provide the header information for channel 1.

Figure 102. Register 33 (21h)

15

14

13

12

11

0

10

0

9

1

8

0

CH_OUT_DIS1 AUX_CH1_EN

PDN_CH1

INVERT_ CH1

OFFSET_CH1

7

6

5

4

3

2

OFFSET_CH1

Bit 15

CH_OUT_DIS1: Channel 1 disable

Channel 1 is not muxed out.

0 = Channel 1 is output (default)

1 = Channel 1 is not output

Bit 14

Bit 13

Bit 12

AUX_CH1_EN: Enable auxiliary channel for channel 1

0 = Filter (default)

1 = Auxiliary

PDN_CH1: Power-down channel 1

0 = Active (default)

1 = Power-down

INVERT_CH1: Invert channel 1 output

0 = Normal ouput (default)

1 = Inverted output

Bits 11:10

Bits 9:0

Must write 0

OFFSET_CH1: Output offset of channel 1 range

Output offset value = OFFSET_CH1 ÷ 4, output offset value is added to channel output.

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Figure 103. Register 34 (22h)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

MEAN_CH1

7

6

4

3

MEAN_CH1

Bits 15:14

Bits 13:0

Must write 0

MEAN_CH1: Mean for channel 1 (read-only register)

These bits provide the mean information computed by STAT module for channel 1.

Figure 104. Register 35 (23h)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

NOISE_CH1

7

6

4

3

NOISE_CH1

Bits 15:14

Bits 13:0

Must write 0

NOISE_CH1: Noise for channel 1 (read-only register)

These bits provide the noise information computed by STAT module for channel 1.

Figure 105. Register 36 (24h)

15

0

14

0

13

0

12

0

11

10

2

9

1

8

0

HEADER_CH2

7

6

5

4

3

HEADER_CH2

Bits 15:12

Bits 11:0

Must write 0

HEADER_CH2: Header information for channel 2

These bits provide the header information for channel 2.

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Figure 106. Register 37 (25h)

15

14

13

12

11

0

10

0

9

1

8

0

CH_OUT_DIS2 AUX_CH2_EN

PDN_CH2

INVERT_CH2

OFFSET_CH2

7

6

5

4

3

2

OFFSET_CH2

Bit 15

CH_OUT_DIS2: Channel 2 disable

Channel 2 is not muxed out.

0 = Channel 2 is output (default)

1 = Channel 2 is not output

Bit 14

Bit 13

Bit 12

AUX_CH2_EN: Enable auxiliary channel for channel 2

0 = Filter (default)

1 = Auxiliary

PDN_CH2: Power-down channel 2

0 = Active (default)

1 = Power-down

INVERT_CH2: Invert channel 2 output

0 = Normal (default)

1 = Inverted output

Bits 11:10

Bits 9:0

Must write 0

OFFSET_CH2: Output offset of Channel 2

Output offset value = OFFSET_CH2 ÷ 4, output offset value is added to the channel output

Figure 107. Register 38 (26h)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

MEAN_CH2

7

6

4

3

MEAN_CH2

Bits 15:14

Bits 13:0

Must write 0

MEAN_CH2: Mean for channel 2 (read-only register)

These bits provide the mean information computed by the STAT module for channel 2.

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Figure 108. Register 39 (27h)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

NOISE_CH2

7

6

4

3

NOISE_CH2

Bits 15:14

Bits 13:0

Must write 0

NOISE_CH2: Noise for channel 2 (read-only register)

These bits provide the noise information computed by the STAT module for channel 2.

Figure 109. Register 40 (28h)

15

0

14

0

13

0

12

0

11

10

2

9

1

8

0

HEADER_CH3

7

6

5

4

3

HEADER_CH3

Bits 15:12

Bits 11:0

Must write 0

HEADER_CH3: Header information for channel 3

These bits provide the header information for channel 3.

Figure 110. Register 41 (29h)

15

14

13

12

11

0

10

0

9

1

8

0

CH_OUT_DIS3 AUX_CH3_EN

PDN_CH3

INVERT_CH3

OFFSET_CH3

7

6

5

4

3

2

OFFSET_CH3

Bit 15

CH_OUT_DIS3: Channel 3 disable

Channel 3 is not muxed out.

0 = Channel 3 is output (default)

1 = Channel 3 is not output

Bit 14

Bit 13

Bit 12

AUX_CH3_EN: Enable auxiliary channel for channel 3

0 = Filter (default)

1 = Auxiliary

PDN_CH3: Power-down channel 3

0 = Active (default)

1 = Power-down

INVERT_CH3: Invert channel 3 output

0 = Normal (default)

1 = Inverted output

Bits 11:10

Bits 9:0

Must write 0

OFFSET_CH3: Output offset of Channel 3

Output offset value = OFFSET_CH3 ÷ 4, output offset value is added to the channel output

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Figure 111. Register 42 (2Ah)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

MEAN_CH3

7

6

4

3

MEAN_CH3

Bits 15:14

Bits 13:0

Must write 0

MEAN_CH3: Mean for channel 3 (read-only register)

These bits provide the mean information computed by the STAT module for channel 3.

Figure 112. Register 43 (2Bh)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

NOISE_CH3

7

6

4

3

NOISE_CH3

Bits 15:14

Bits 13:0

Must write 0

NOISE_CH3: Noise for channel 3 (read-only register)

These bits provide the noise information computed by the STAT module for channel 3.

Figure 113. Register 44 (2Ch)

15

0

14

0

13

0

12

0

11

10

2

9

1

8

0

HEADER_CH4

7

6

5

4

3

HEADER_CH4

Bits 15:12

Bits 11:0

Must write 0

HEADER_CH4: Header information for channel 4

These bits provide the header information for channel 4.

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Figure 114. Register 45 (2Dh)

15

14

13

12

11

0

10

0

9

1

8

CH_OUT_DIS4 AUX_CH4_EN

PDN_CH4

INVERT_CH4

OFFSET_CH4

7

6

5

4

3

2

0

OFFSET_CH4

Bit 15

CH_OUT_DIS1: Channel 4 disable

Channel 4 is not muxed out.

0 = Channel 4 is output (default)

1 = Channel 4 is not output

Bit 14

Bit 13

Bit 12

AUX_CH4_EN: Enable auxiliary channel for channel 4

0 = Filter (default)

1 = Auxiliary

PDN_CH4: Power-down channel 4

0 = Active (default)

1 = Power-down

INVERT_CH4: Invert channel 4 output

0 = Normal (default)

1 = Inverted output

Bits 11:10

Bits 9:0

Must write 0

OFFSET_CH4: Output offset of channel 4

Output offset value = OFFSET_CH4 ÷ 4, output offset value is added to the channel output

Figure 115. Register 46 (2Eh)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

MEAN_CH4

7

6

4

3

MEAN_CH4

Bits 15:14

Bits 13:0

Must write 0

MEAN_CH4: Mean for channel 4 (read-only register)

These bits provide the mean information computed by the STAT module for channel 4.

Figure 116. Register 47 (2Fh)

15

0

14

0

13

5

12

11

10

2

9

1

8

0

NOISE_CH4

7

6

4

3

NOISE_CH4

Bits 15:14

Bits 13:0

Must write 0

NOISE_CH4: Noise for channel 4 (read-only register)

These bits provide the noise information computed by the STAT module for channel 4.

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Figure 117. Register 65 (41h)

15

0

14

0

13

0

12

0

11

0

10

9

0

8

0

TERM_INT_

20K_AUX

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bits 15:11

Bit 10

Must write 0

TERM_INT_20K_AUX: Auxiliary input termination

This bit is common for all channels. This bit provides an auxiliary input internal differential

termination of 20 kΩ.

0 = 2-kΩ differential resistance (default)

1 = 20-kΩ differential resistance

Bits 9:0

Must write 0

Figure 118. Register 69 (45h)

15

14

13

12

11

10

9

8

TERM_INT_

20K_LNA

LNA_GAIN

PGA_GAIN

7

6

5

0

4

0

3

0

2

0

1

0

PGA_GAIN

EQ_EN

Bit 15

TERM_INT_20K_LNA: LNA input termination

This bit is common for all channels. This bit provides LNA input internal differential

termination of 20 kΩ.

0 = 2-kΩ differential resistance (default)

1 = 20-kΩ differential resistance

Bits 14:13

LNA_GAIN: LNA gain

These bits are common for all channels.

0 = 15 dB (default)

1 = 18 dB

2 = 12 dB

3 = 16.5 dB

Bits 12:7

PGA_GAIN: PGA gain

These bits are common for all channels. PGA gain = 0 dB, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB,

18 dB, 21 dB, 24 dB, 27 dB, and 30 dB.

0 = 0 dB

1 = 3 dB

2 = 6 dB

3 = 9 dB

4 = 12 dB

5 = 15 dB

6 = 18 dB

7 = 21 dB

8 = 24 dB

9 = 27 dB

10 = 30 dB

Bit 6

EQ_EN: Equalizer enable

These bits are common for all channels.

0 = Disabled (default)

1 = Enabled

Bits 5:0

Must write 0

63

AFE5401-Q1

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Figure 119. Register 70 (46h)

15

0

14

13

0

12

0

11

0

10

0

9

0

8

0

HPL_EN

7

0

6

0

5

0

4

0

3

0

2

0

1

0

VOUT_ON_ADC

Bit 15

Must write 0

Bit 14

HPL_EN: High-performance linearity mode

0 = Default

1 = Improves linearity (HD3) with increased power dissipation

Bits 13:2

Bits 1:0

Must write 0

VOUT_ON_ADC: Check analog block output on ADC input

0 = LNA + antialiasing filter + ADC (default)

1 = LNA + ADC

2 = AMP1 + ADC

3 = AMP2 + ADC

Figure 120. Register 71 (47h)

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

2

1

0

HIGH_POW_ EQ_EN_LOW_

LNA FC

Bits 15:4

Bit 3

Must write 0

HIGH_POW_LNA

0 = Default mode

1 = High-power LNA improves channel input-referred noise at high LNA and PGA gains

compared to default mode. This mode increases power dissipation.

Bit 2

EQ_EN_LOW_FC: Enable Equalizer Low Frequency Corner Frequency

0 = Disable

1 = Enable; EQ_EN must also be enabled for this mode

Bits 1:0

Must write 0

Figure 121. Register 100 (64h)

15

0

14

13

12

0

11

0

10

0

9

0

8

0

HF_AFE_CLK_EN

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bits 15

Must write 0

Bits 14:13

HF_AFE_CLK_EN

0 = Default

3 = For f_{AFE_CLK}> 25 MHz ( in decimation modes)

Bits 12:0

Must write 0

64

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The AFE5401-Q1 is a quad-channel, analog front-end (AFE), targeting applications where the level of integration

is critical. Each channel comprises a complete base-band signal chain with:

•

A low-noise amplifier (LNA),

A programmable equalizer (EQ),

A programmable gain amplifier (PGA), and

An antialias filter (AAF)

A high-speed, 12-bit, analog-to-digital converter (ADC) that samples at 25 MSPS per channel.

Having four integrated signal chain channels enables the device to be used in different end-use systems such as:

•

Automotive radar (where a down-converted base-band signal from an RF front-end can be applied to the

inputs of the AFE)

•

Applications where up to 12-MHz voltage signal is available from a transducer

9.2 Typical Application

As Figure 122 illustrates, the device also consists of four auxiliary channels, where the analog signal chain (LNA,

PGA) is bypassed and the analog inputs can be directly digitized. This configuration is very useful in the system

to digitize monitoring signals (such as battery voltages and temperature sensor outputs).

As the Design Requirements section describes, the device can accept a variety of input clock signals (such as

differential sine-wave, LVPECL, or LVDS). The can also functions seamlessly with a single-ended LVCMOS

(1.8 V) clock input.

The device is designed to have a simple CMOS output data interface. Used with the TRIG and DSYNCx signals,

the device can be interfaced to standard video ports of DSPs and other field-programmable gate array (FPGA)

and micro-controller based receivers.

65

AFE5401-Q1

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www.ti.com.cn

Typical Application (continued)

FPGA/DSP

STBY

SCLK

SDATA

SEN

RESET

SDOUT

VCM

AVDD3

AVSS

DRVDD DRVSS

AVDD18 AVSS DVDD18 DVSS

Reference

SERIAL

INTERFACE

PGA

AAF

Channel 1 of 4

LNA

EQ

Baseband signal from

Front-End

INx

D [11:0]

ADC 1

System monitoring

signals (Battery,

Temperature, etc)

BUF

INx_AUX

4:1 MUX

D_GPO [1:0]

1x

ADC_CLK

Input

Clock

CMOS/DIFF

SUPPORT

4x

DCLK

Divider

Clock Input:

CMOS Signal / LVPECL /

LVDS / Sine wave

f_CLKIN

AFE_CLK

CLKINP

CLKINM

DSYNC1

DSYNC2

Clock + Timing

Generator

Serialization Factor

TRIG

Figure 122. Typical Application Diagram

9.2.1 Design Requirements

The device can operate with either single-ended (CMOS) or differential input clocks (such as sine wave,

LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance. In

differential mode, the clock inputs are internally biased to the optimum common-mode voltage (approximately

0.95 V). While driving with an external LVPECL or LVDS driver, TI recommends ac-coupling the clock signals

because the clock pins are internally biased to the common-mode voltage.

9.2.2 Detailed Design Procedure

For the LVDS input clock, R_TERM= 100 Ω is recommended. For the LVPECL clock input, R_TERMmust be

determined based on the LVPECL driver recommendations. To operate using a single-ended clock, connect a

CMOS clock source to CLKINP and tie CLKINM to GND. The device automatically detects the presence of a

single-ended clock without requiring any configuration and disables internal biasing. Typical clock termination

schemes are illustrated in Figure 125, Figure 126, Figure 127, and Figure 128. Typical characteristic plots across

input clock amplitude and duty cycle are shown in Application Curves.

Figure 123 and Figure 124 illustrate the equivalent circuits of the clock input pins for Differential and Single-

Ended input clock respectively.

66

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Typical Application (continued)

Lpkg

20 ꢀ

~ 1 nH

CLKINP

Cbond

~ 1 pF

Resr

Ceq

5 kꢀ

6 pF

~ 100 ꢀ

0.95 V

To Input Divider

Internal

Differential

Clock Buffer

Lpkg

~ 1 nH

20 ꢀ

CLKINM

Ceq

Cbond

~ 1 pF

Resr

~ 100 ꢀ

Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer

Figure 123. Clock Input Equivalent Circuit (Differential Mode)

Lpkg

20 ꢀ

~ 1 nH

CLKINP

Cbond

~ 1 pF

Resr

Ceq

~ 100 ꢀ

To Input Divider

Internal

Single-Ended

Clock Buffer

Lpkg

~ 1 nH

CLKINM

Cbond

~ 1 pF

Resr

~ 100 ꢀ

Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer

Figure 124. Clock Input Equivalent Circuit (Single-Ended Mode)

67

AFE5401-Q1

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www.ti.com.cn

Typical Application (continued)

0.1µF

CLKINP

CLKINM

CLKINP

Differential Sine-wave

clock input

R_TERM

Differential

LVPECL

clock input

CLKINM

0.1µF

R_TERM

Figure 125. Differential Sine-Wave Clock

Driving Circuit

Figure 126. Differential LVPECL Clock

Driving Circuit

0.1µF

CLKINP

CMOS clock input

CLKINP

Differential

LVDS

clock input

R_TERM

CLKINM

0.1µF

Figure 127. Differential LVDS Clock Driving Circuit

9.2.3 Application Curves

Figure 128. Single-Ended Clock Driving Circuit

68

67.6

67.2

66.8

66.4

66

69

68.6

68.2

67.8

67.4

67

35

40

45

50

55

60

65

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

Input Clock Duty Cycle (%)

C013

Input Clock Amplitude, Differential (V_PP

)

C011

Figure 130. Signal-to-Noise Ratio vs Input Clock Duty

Cycle (PGA Gain = 0 dB)

Figure 129. Signal-to-Noise Ratio vs Input Clock Amplitude

(PGA Gain = 0 dB)

68

AFE5401-Q1

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ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

10 Power Supply Recommendations

10.1 Power Supply Sequencing

During power-up, the AVDD18, DVDD18, and DRVDD supplies can appear in any sequence. All supplies are

separated in the device. Externally, they can be driven from separate supplies with suitable filtering. No power

supply sequencing is required.

10.2 Power Supply Decoupling

Minimal external decoupling can be used without loss in performance because the device already includes

internal decoupling. Note that decoupling capacitors can help filter external power-supply noise, so the optimum

number of capacitors depends on the actual application. The decoupling capacitors should be placed as close as

possible to the device supply pins.

11 Layout

11.1 Layout Guidelines

All analog inputs must be differentially and symmetrically routed to the differential input pins of the device for best

performance. CMOS outputs traces should be kept as short as possible to reduce the trace capacitance that

loads the CMOS output buffers. Multiple ground vias can be added around the CMOS output data traces,

especially when the traces are routed on more than one layer. TI recommends matching the lengths of the output

data traces (D[11:0]) to reduce the skew across data bits.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.

This condition is particularly of concern because of the high gain present in the analog input channel. Digital

outputs coupling back to analog inputs can be minimized by proper separation of analog and digital areas in the

board layout. Figure 131 illustrates an example layout where the analog and digital portions are routed

separately. This example also uses splits in the ground plane to minimize digital currents from looping into

analog areas. At the same time, note that the analog and digital grounds are shorted below the device. A single

ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board

are cleanly partitioned.

The device package consists of an exposed pad. In addition to providing a path for heat dissipation, the pad is

also internally connected to the analog ground. Therefore, the exposed pad must be soldered to the ground

plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout

Guidelines and QFN/SON PCB Attachment. Figure 131 and Figure 132 illustrate the layout diagrams taken from

the AFE5401-Q1 EVM User's Guide.

69

AFE5401-Q1

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11.2 Layout Example

Figure 131. Layout Diagram: Signal Routing

70

AFE5401-Q1

www.ti.com.cn

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

Layout Example (continued)

Figure 132. Layout Diagram: Ground Split

71

AFE5401-Q1

ZHCSGC8A –MARCH 2014–REVISED JUNE 2017

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

《QFN 布局指南》

《QFN/SON PCB 连接》

《AFE5401-Q1 EVM 用户指南》

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到任意产品

信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

SONAR is a trademark of Cakewalk, Inc.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，

我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。

72

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AFE5401TRGCRQ1

VQFN

RGC

64

2000

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGC 64

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AFE5401TRGCRQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

RGC0064H

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

9.15

8.85

A

B

PIN 1 INDEX AREA

9.15

8.85

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 7.5

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

17

32

16

33

65

SYMM

2X 7.5

7.4 0.1

60X

0.5

1

48

0.30

0.18

64X

49

64

PIN 1 ID

0.1

C A B

0.5

0.3

64X

0.05

4219011/A 05/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGC0064H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

7.4)

SEE SOLDER MASK

DETAIL

SYMM

64X (0.6)

49

64

64X (0.24)

1

48

60X (0.5)

(3.45) TYP

(R0.05) TYP

(1.16) TYP

65

SYMM

(8.8)

(

0.2) TYP

VIA

33

16

32

17

(1.16) TYP

(3.45) TYP

(8.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219011/A 05/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGC0064H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

64X (0.6)

64

49

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

(1.16) TYP

65

SYMM

(8.8)

(0.58)

36X ( 0.96)

33

16

17

32

(0.58)

(1.16)

TYP

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219011/A 05/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	AFE5401TRGCTQ1
厂家：	TEXAS INSTRUMENTS
描述：	用于汽车雷达的四通道集成模拟前端 \| RGC \| 64 \| -40 to 105 雷达
文件：	总81页 (文件大小：3452K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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