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AFE5805 [TI]

8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND; 8通道模拟前端超声
AFE5805
型号： AFE5805
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND
8通道模拟前端超声
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AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND  
1
FEATURES  
DESCRIPTION  
2
•
8-Channel Complete Analog Front-End:  
LNA, VCA, PGA, LPF, and ADC  
Ultra-Low Noise:  
The AFE5805 is a complete analog front-end device  
specifically designed for ultrasound systems that  
require low power and small size.  
–
•
The AFE5805 consists of eight channels, including a  
–
–
0.85nV/√Hz (TGC)  
1.1nV/√Hz (CW)  
low-noise  
attenuator (VCA), programmable gain amplifier  
(PGA), low-pass filter (LPF), and 12-bit  
amplifier  
(LNA),  
voltage-controlled  
•
•
Low Power:  
a
analog-to-digital converter (ADC) with low voltage  
differential signaling (LVDS) data outputs.  
–
122mW/Channel (40MSPS)  
Low-Noise Pre-Amp (LNA):  
The LNA gain is set for 20dB gain, and has excellent  
noise and signal handling capabilities, including fast  
overload recovery. VCA gain can vary over a 46dB  
range with a 0V to 1.2V control voltage common to all  
channels of the AFE5805.  
–
–
20dB Fixed Gain  
250mVPP Linear Input Range  
•
Variable-Gain Amplifier:  
Gain Control Range: 46dB  
–
•
•
PGA Gain Settings: 20dB, 25dB, 27dB, 30dB  
Low-Pass Filter:  
The PGA can be programmed for gains of 20dB,  
25dB, 27dB, and 30dB. The internal low-pass filter  
can also be programmed to 10MHz or 15MHz.  
–
–
Selectable BW: 10MHz, 15MHz  
2nd-Order  
The LVDS outputs of the ADC reduce the number of  
interface lines to an ASIC or FPGA, thereby enabling  
the high system integration densities desired for  
portable systems. The ADC can either be operated  
with internal or external references. The ADC also  
features a signal-to-noise ratio (SNR) enhancement  
mode that can be useful at high gains.  
•
•
•
•
•
•
Gain Error: ±0.5dB  
Channel Matching: ±0.8dB  
Distortion, HD2: –45dBc at 0.2VPP Input  
Clamping Control  
Fast Overload Recovery  
The AFE5805 is available in a 15mm × 9mm, 135-ball  
BGA package that is Pb-free (RoHS-compliant) and  
green. It is specified for operation from 0°C to +70°C.  
12-Bit Analog-to-Digital Converter:  
–
–
–
10MSPS to 50MSPS  
69.5dB SNR at 10MHz  
6dB Overload Recovery Within One Clock  
Cycle  
SPI  
Logic/Controls  
–
–
–
Serial LVDS Interface  
LVDS  
OUT  
IN1  
Clamp  
and  
Internal and External Reference  
Single-Ended or Differential Clock Input  
.
.
.
.
ADC  
8 Channels  
LNA  
VCA/PGA  
CH1  
.
.
CH8  
LPF  
IN8  
•
•
Integrated CW Switch Matrix  
Reference  
15mm × 9mm, 135-BGA Package:  
–
Pb-Free (RoHS-Compliant) and Green  
CW Switch Matrix  
IOUT (10)  
APPLICATIONS  
•
Medical Imaging, Ultrasound  
–
Portable Systems  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2008, Texas Instruments Incorporated  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
Block Diagram  
AFE5805  
LCLKP  
LCLKN  
6x ADCLK  
12x ADCLK  
1x ADCLK  
Clock  
Buffer  
PLL  
ADCLKP  
ADCLKN  
OUT1P  
OUT1N  
12-Bit  
ADC  
IN1  
LNA  
VCA  
PGA  
LPF  
Digital  
Serializer  
Channels  
2 to 7  
OUT8P  
OUT8N  
12-Bit  
ADC  
IN8  
LNA  
VCA  
PGA  
LPF  
Digital  
Serializer  
20,25,27  
30dB  
10,15MHz  
VCNTL  
Power-  
Down  
CW Switch Matrix  
(8x10)  
ADC  
Control  
Registers  
Reference  
CW[0:9]  
2
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
PACKAGING/ORDERING INFORMATION(1)(2)  
OPERATING  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
PACKAGE-LEAD  
ECO STATUS  
AFE5805ZCF- Tape and Reel, 1000  
R
Pb-Free, Green  
AFE5805  
µFBGA-135  
ZCF  
0°C to +70°C  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content  
can be accessed at www.ti.com/leadfree.  
GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including  
bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion  
dates, go to www.ti.com/leadfree. Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that  
does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering  
processes.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range, unless otherwise noted.  
AFE5805  
–0.3 to +3.9  
–0.3 to +3.9  
–0.3 to +6  
–0.3 to +3.9  
–0.3 to +2.2  
–0.3 to +0.3  
–0.3 to AVDD2 +0.3  
–0.3 to +3  
–0.3 to +2  
TBD  
UNIT  
V
Supply voltage range, AVDD1  
Supply voltage range, AVDD2  
Supply voltage range, AVDD_5V  
Supply voltage range, DVDD  
V
V
V
Supply voltage range, LVDD  
V
Voltage between AVSS1 and LVSS  
Voltage at analog inputs  
V
V
External voltage applied to REFT-pin  
External voltage applied to REFB-pin  
Voltage at digital inputs  
V
V
V
Peak solder temperature  
TBD  
°C  
°C  
°C  
°C  
°C  
V
Maximum junction temperature, TJ any condition(2)  
Maximum junction temperature, TJ continuous operation, long term reliability(3)  
Storage temperature range  
+150  
+125  
–40 to +125  
–40 to +85  
2000  
Operating temperature range  
HBM  
ESD ratings  
CDM  
MM  
500  
V
TBD  
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not supported.  
(2) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.  
(3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this  
temperature may result in reduced reliability and/or lifetime of the device.  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
RECOMMENDED OPERATING CONDITIONS  
AFE5805  
TYP  
PARAMETER  
MIN  
MAX  
UNIT  
SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES  
AVDD1  
Analog supply voltage  
AVDD2, DVDD  
3.0  
3.0  
3.3  
3.6  
3.6  
V
V
AVDD_5V  
4.75  
1.7  
5.25  
1.9  
V
LVDD  
Digital supply voltage  
Differential input voltage range  
Input common-mode voltage  
External reference mode  
External reference mode  
1.8  
V
2
VCM ± 0.05  
2.5  
VPP  
V
REFT  
REFB  
V
0.5  
V
CLOCK INPUTS  
CLKM, CLKP  
10  
40  
50  
MHz  
Input clock amplitude differential (VCLKP – VCLKM),  
peak-to-peak  
Sine wave, ac-coupled  
LVPECL, ac-coupled  
LVDS, ac-coupled  
3.0  
1.6  
0.7  
VPP  
VPP  
VPP  
Input clock CMOS, single-ended (VCLKP  
)
VIL  
0.6  
V
V
VIH  
2.2  
Input clock duty cycle  
50  
%
DIGITAL OUTPUTS  
ADCLKP and ADCLKN outputs (LVDS)  
LCLKP and LCLKN outputs (LVDS)  
10  
60  
1x (sample rate)  
50, 65  
MHz  
MHz  
pF  
6x (sample rate)  
300, 390  
CLOAD  
RLOAD  
TA  
Maximum external capacitance from each pin to LVSS  
Differential load resistance between the LVDS output pairs  
Ambient temperature  
5
100  
Ω
0
+70  
°C  
4
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
ELECTRICAL CHARACTERISTICS  
AVDD_5V = 5.0V, AVDD1 = VDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 1.0µF,  
VCNTL = 1.0V, fIN 5MHz, Clock = 40MSPS, 50% duty cycle, –1dBFS input magnitude, internal reference mode, ISET = 56kΩ,  
LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.  
AFE5805  
PARAMETER  
PREAMPLIFIER (LNA)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Gain  
A
SE-input to differential output  
Linear operation (HD2 ≤ 40dB)  
Limited by internal diodes  
RS = 0Ω, f = 1MHz  
20  
250  
600  
0.75  
3
dB  
mVPP  
mVPP  
nV/√Hz  
pA/√Hz  
V
Input voltage  
VIN  
Maximum input voltage  
Input voltage noise (TGC)  
Input current noise  
Common-mode voltage, input  
Bandwidth  
en (RTI)  
in (RTI)  
VCMI  
Internally generated  
Small-signal, –3dB  
2.4  
70  
BW  
MHz  
kΩ  
Input resistance  
RIN  
8
Input capacitance  
CIN  
Includes internal diodes  
30  
pF  
FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC)  
Input voltage noise (TGC)  
en  
RS = 0Ω, f = 1MHz, PGA = 30dB  
RS = 0Ω, f = 1MHz, PGA = 20dB  
RS = x  
0.85  
0.95  
TBD  
10, 15  
±15  
nV/√Hz  
nV/√Hz  
dB  
Noise figure  
NF  
Low-pass flter bandwidth  
Bandwidth tolerance  
High-pass filter  
LPF  
at –3dB, selectable through SPI  
MHz  
%
HPF  
(First-order, due to internal ac-coupling)  
200  
kHz  
Group delay variation  
Overload recovery  
DC-ACCURACY  
Gain (PGA)  
TBD  
TBD  
ns  
Clock Cycle  
Selectable through SPI  
LNA + PGA gain  
20, 25, 27, 30  
dB  
dB  
dB  
dB  
dB  
dB  
Total gain, max(1)  
50  
Gain range  
Gain error(2)  
VCNTL = 0V to 1.2V  
TBD  
46  
TBD  
±1.0  
0V < VCNTL < 0.1V  
TBD  
±0.5  
TBD  
0.1V < VCNTL < 1.1V (= linear range)  
1.1V < VCNTL < 1.2V  
Gain matching,  
channel-to-channel  
0.1V < VCNTL < 1.1V  
±0.5  
±1.0  
dB  
Gain drift (tempco)  
Offset error  
TBD  
TBD  
TBD  
ppm/°C  
mV (LSB)  
ppm/°C  
VCNTL = TBD, gain = TBD  
Offset drift (tempco)  
GAIN CONTROL (VCA)  
Input voltage range  
Gain slope  
VCNTL  
0 to 1.2  
40  
V
dB/V  
kΩ  
VCNTL = 0.1V to 1.1V  
Input resistance  
25  
Response time  
VCNTL = 0V to 1.2V step; to 90% signal  
TBD  
µs  
DYNAMIC PERFORMANCE  
FIN = 2MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
Signal-to-noise ratio  
SNR  
HD2  
TBD  
dBFS  
FIN = 5MHz; –1dBFS  
FIN = 10MHz; –1dBFS  
TBD  
TBD  
dBFS  
dBFS  
FIN = 2MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
Second-harmonic distortion  
TBD  
TBD  
TBD  
dBc  
dBc  
dBc  
FIN = 5MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
TBD  
TBD  
TBD  
TBD  
FIN = 5MHz; –6dBFS  
(VCNTL = TBD, PGA = TBD)  
(1) Excludes digital gain within ADC.  
(2) Excludes error of internal reference.  
Copyright © 2008, Texas Instruments Incorporated  
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5
Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
ELECTRICAL CHARACTERISTICS (continued)  
AVDD_5V = 5.0V, AVDD1 = VDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 1.0µF,  
VCNTL = 1.0V, fIN 5MHz, Clock = 40MSPS, 50% duty cycle, –1dBFS input magnitude, internal reference mode, ISET = 56kΩ,  
LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.  
AFE5805  
PARAMETER  
Third-harmonic distortion  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
FIN = 2MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
HD3  
THD  
TBD  
dBc  
FIN = 5MHz; –1dBFS  
(VVCNTL = TBD, PGA = TBD)  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
dBc  
dBc  
dBc  
dBc  
FIN = 5MHz; –6dBFS  
(VCNTL = TBD, PGA = TBD)  
FIN = 2MHz; –1dBFS  
(VVCNTL = TBD, PGA = TBD)  
Total harmonic distortion  
FIN = 5MHz; –1dBFS  
(VVCNTL = TBD, PGA = TBD)  
FIN = 10MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
TBD  
TBD  
TBD  
dBc  
dBc  
Overload distortion  
SNR + THD  
up to × dB overload  
FIN = 2.5MHz; –1dBFS  
(VCNTL = TBD, PGA = TBD)  
SINAD  
IMD  
dBFS  
FIN = 5MHz; –1dBFS  
Fin = 10MHz; –1dBFS  
TBD  
TBD  
dBFS  
dBFS  
f1 = 5Mhz at –1dBFS,  
f2 = 5.01MHz at –27dBFS  
Intermodulation distortion  
Crosstalk  
TBD  
dB  
FIN = TBD, VIN = TBD  
(with overload input)  
TBD  
TBD  
dB  
dB  
CW - SIGNAL CHANNELS  
Input voltage noise (CW)  
en  
RS = 0Ω, f = 1MHz  
1.1  
TBD  
nV/√Hz  
%
Output noise correlation factor  
Output transconductance (V/I)  
Dynamic CW output current  
Static CW output current  
Summing of eight channels  
12  
mA/V  
mAPP  
mA  
IOUTAC  
IOUTDC  
2.4 (±1.2)  
0.9  
Output common-mode  
voltage(3)  
VCM  
2.5  
V
Output impedance  
Output capacitance  
50  
kΩ  
<10  
pF  
INTERNAL REFERENCE VOLTAGES (ADC)  
Reference Top  
VREFT  
VREFB  
TBD  
TBD  
TBD  
0.5  
2.5  
2
TBD  
TBD  
TBD  
Reference Bottom  
VREFT – VREFB  
Common-mode voltage  
(internal)  
VCM  
TBD  
1.5  
±2  
TBD  
VCM output current  
mA  
EXTERNAL REFERENCE VOLTAGES (ADC)  
Reference top  
VREFT  
VREFB  
2.4  
0.4  
1.9  
2.6  
0.6  
2.1  
V
V
Reference bottom  
VREFT – VREFB  
Switching current(4)  
POWER SUPPLY  
SUPPLY VOLTAGES  
AVDD1, AVDD2, DVDD  
AVDD_5V  
TBD  
mA  
Specification  
Specification  
3.14  
4.75  
1.7  
3.3  
5
3.47  
5.25  
1.9  
V
V
V
LVDD  
1.8  
(3) CW outputs require an externally applied bias voltage of +2.5V.  
(4) Current drawn by the eight ADC channels from the external reference voltages; sourcing for VREFT, sinking for VREFB.  
6
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
ELECTRICAL CHARACTERISTICS (continued)  
AVDD_5V = 5.0V, AVDD1 = VDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 1.0µF,  
VCNTL = 1.0V, fIN 5MHz, Clock = 40MSPS, 50% duty cycle, –1dBFS input magnitude, internal reference mode, ISET = 56kΩ,  
LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.  
AFE5805  
PARAMETER  
SUPPLY CURRENTS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
IAVDD1 (ADC)  
IAVDD2 (VCA)  
at 40MSPS  
TGC mode  
CW mode  
TGC mode  
CW mode  
TBD  
TBD  
TBD  
TBD  
TBD  
8
TBD  
TBD  
mA  
mA  
mA  
IAVDD_5V (VCA)  
TBD  
TBD  
mA  
TBD  
mA  
IDVDD (VCA)  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
mA  
ILVDD (ADC)  
At 40MSPS  
TBD  
980  
mA  
Power dissipation, total  
All channels, TGC mode , no signal  
All channels, CW mode , no signal  
DC power-supply rejection ratio  
AC power supply rejection ratio  
mW  
mW  
%FSR/V  
dBc  
TBD  
TBD  
TBD  
Power-supply rejection  
POWER-DOWN MODES  
Power-down dissipation, total  
Power-down response time  
Power-up response time  
Power-down dissipation(5)  
Power-down dissipation  
THERMAL CHARACTERISTICS  
Temperature range  
ADC_PD = H  
TBD  
TBD  
10  
TBD  
mW  
µs  
50  
µs  
Standby (fast recovery mode)  
No clock applied  
TBD  
TBD  
mW  
mW  
0
70  
°C  
Thermal resistance, TJA  
TBD  
C/W  
(5) At VCA_PD pin pulled high; see also Power-Down Timing diagram.  
DIGITAL CHARACTERISTICS  
DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level  
'0' or '1'. At CLOAD = 5pF(1), IOUT = 3.5mA(2), RLOAD = 100Ω(2), and no internal termination, unless otherwise noted.  
AFE5805  
PARAMETER  
DIGITAL INPUTS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
High-level input voltage  
Low-level input voltage  
High-level input current  
Low-level input current  
Input capacitance  
1.4  
V
0.3  
V
33  
–33  
3
µA  
µA  
pF  
LVDS OUTPUTS  
High-level output voltage  
Low-level output voltage  
Output differential voltage, |VOD  
VOS output offset voltage(2)  
1375  
1025  
350  
mV  
mV  
mV  
mV  
|
Common-mode voltage of OUTP and OUTN  
1200  
Output capacitance inside the device, from either output  
to ground  
Output capacitance  
2
pF  
(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground.  
(2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.  
Copyright © 2008, Texas Instruments Incorporated  
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Product Folder Link(s): AFE5805  
AFE5805  
www.ti.com  
SBOS421A–MARCH 2008–REVISED MARCH 2008  
PIN CONFIGURATION  
ZCF PACKAGE  
135-BGA  
BOTTOM VIEW  
OUT4M OUT3M OUT2M OUT1M  
LVSS  
LVDD  
LVSS  
OUT5M OUT6M OUT7M OUT8M  
R
OUT4P OUT3P OUT2P OUT1P  
OUT5P  
LVDD  
OUT6P OUT7P OUT8P  
P
N
M
L
LCLKP LCLKM  
LVSS  
LVSS  
LVDD  
AVSS1  
AVSS1  
FCLKM FCLKP  
DNC  
DNC  
AVSS1 AVSS1  
AVSS1 AVSS1  
AVSS1 AVSS1  
DNC  
DNC  
AVSS1  
AVDD1  
CLKP  
CLKM  
AVDD1  
DNC  
AVSS1  
EN_SM  
ISET  
AVDD1  
DNC  
AVSS2  
VCA_CS  
AVSS2  
AVSS2  
AVDD1 AVDD1  
AVSS2 AVSS2  
AVDD1  
AVDD1  
CS  
CM  
K
J
INT/EXT  
AVSS1 AVDD1  
REFT  
SDATA  
AVDD2  
VB6  
REFB  
ADS_  
RESET  
ADS_PD  
CW5  
DNC  
DNC  
VCM  
VB5  
RST  
SCLK  
H
G
F
AVDD2  
AVSS2 AVSS2  
VREFL  
VREFH  
CW4  
CW3  
AVSS2  
CW6  
VB1  
AVSS2  
VB3  
CW7 AVDD_5V  
AVSS2  
AVSS2  
AVSS2 AVSS2  
VB4  
AVSS2  
AVSS2  
VBL7  
IN7  
AVDD_5V CW2  
E
D
C
B
A
AVSS2  
CW8  
CW9  
VBL1  
VCNTL  
DVDD  
DVDD  
DNC  
AVSS2  
AVSS2  
VBL8  
VB2  
AVDD2  
VBL6  
IN6  
CW1  
CW0  
VBL5  
AVDD2 AVSS2 AVSS2  
VBL2  
IN2  
2
VBL3  
IN3  
VBL4  
IN4  
VCA_PD  
IN1  
1
IN8  
6
IN5  
9
3
4
5
7
8
Columns  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
ZCF PACKAGE  
135-BGA  
CONFIGURATION MAP (TOP VIEW)  
R
P
N
M
L
OUT8M  
OUT7M  
OUT7P  
FCLKM  
DNC  
OUT6M  
OUT6P  
LVDD  
OUT5M  
OUT5P  
LVDD  
LVSS  
LVDD  
OUT1M  
OUT1P  
LVSS  
OUT2M  
OUT2P  
LVSS  
OUT3M  
OUT3P  
LCLKM  
DNC  
OUT4M  
OUT4P  
LCLKP  
DNC  
OUT8P  
FCLKP  
DNC  
LVSS  
AVSS1  
AVSS1  
AVDD1  
AVDD1  
CS  
AVSS1  
AVSS1  
AVDD1  
AVSS2  
SCLK  
AVSS1  
AVSS1  
AVDD1  
AVSS2  
RST  
AVSS1  
AVSS1  
DNC  
AVSS1  
AVSS1  
AVDD1  
INT/EXT  
DNC  
EN_SM  
ISET  
AVDD1  
CM  
AVDD1  
DNC  
CLKP  
CLKM  
AVSS1  
ADS_PD  
CW5  
K
J
REFB  
ADS_RESET  
CW4  
REFT  
AVSS2  
VCA_CS  
AVSS2  
AVSS2  
AVSS2  
AVSS2  
AVSS2  
VBL4  
AVDD1  
DNC  
H
G
F
SDATA  
AVDD2  
VB6  
VREFL  
VREFH  
VB4  
AVSS2  
AVSS2  
AVSS2  
AVSS2  
AVSS2  
VBL8  
AVSS2  
AVSS2  
AVSS2  
DVDD  
DVDD  
DNC  
VCM  
AVDD2  
VB1  
CW3  
VB5  
CW6  
E
D
C
B
A
CW2  
AVDD_5V  
VB2  
VB3  
AVDD_5V  
VCNTL  
AVDD2  
VBL2  
CW7  
CW1  
AVSS2  
AVSS2  
VBL7  
AVSS2  
AVSS2  
VBL3  
CW8  
CW0  
AVDD2  
VBL6  
CW9  
VBL5  
VBL1  
IN5  
IN6  
IN7  
IN8  
VCA_PD  
IN4  
IN3  
IN2  
IN1  
9
8
7
6
5
4
3
2
1
Legend: AVDD1  
AVDD2  
+3.3V; Analog  
+3.3V; Analog  
+3.3V; Analog  
+1.8V; Digital  
+5V; Analog  
DVDD  
LVDD  
AVDD_5V  
AVSS1  
AVSS2  
LVSS  
Analog Ground  
Analog Ground  
Digital Ground  
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Table 1. TERMINAL FUNCTIONS  
PIN NO.  
H7  
PIN NAME  
CS  
FUNCTION  
Input  
DESCRIPTION  
Chip select for serial interface; active low  
Power-down pin for ADS; active high  
RESET input for ADS; active low  
H1  
ADS_PD  
ADS_RESET  
SCLK  
Input  
H9  
Input  
H6  
Input  
Serial clock input for serial interface  
Serial data input for serial interface  
H8  
SDATA  
Input  
J2, L2, K7, J7,  
K3, L8, K5, K6  
AVDD1  
AVSS1  
POWER  
GND  
3.3V analog supply for ADS  
Analog ground for ADS  
L3, M3, L4, M4,  
L5, M5, L6, M6,  
L7, M7, J1  
P5, N6, N7  
N3, N4, N5, R5  
C5, D5  
LVDD  
LVSS  
POWER  
GND  
1.8V digital supply for ADS  
Digital ground for ADS  
DVDD  
POWER  
POWER  
POWER  
3.3V digital supply for the VCA; connect to the 3.3V analog supply (AVDD2).  
3.3V analog supply for VCA  
C2, C8, G2, G8  
E2, E8  
AVDD2  
AVDD_5V  
5V supply for VCA  
C3, D3, C4, D4,  
E4, F4, G4, E5,  
F5, G5, C6, D6,  
E6, F6, G6, C7,  
D7, J4, J5,J6  
AVSS2  
GND  
Analog ground for VCA  
K1  
L1  
CLKM  
CLKP  
CM  
Input  
Input  
Negative clock input for ADS (connect to Ground in single-ended clock mode)  
Positive clock input for ADS  
K8  
C9  
D9  
E9  
F9  
G9  
G1  
F1  
E1  
D1  
C1  
L9  
Input/Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
1.5V common-mode I/O for ADS. Becomes input pin in one of the external reference modes.  
CW0  
CW output 0  
CW1  
CW output 1  
CW2  
CW output 2  
CW3  
CW output 3  
CW4  
CW output 4  
CW5  
CW output 5  
CW6  
CW output 6  
CW7  
CW output 7  
CW8  
CW output 8  
CW9  
CW output 9  
EN_SM  
FCLKM  
FCLKP  
IN1  
Enables access to the VCA register. Active high. Connect permanently to 3.3V (AVDD2).  
LVDS frame clock (negative output)  
LVDS frame clock (positive output)  
LNA input Channel 1  
N8  
N9  
A1  
A2  
A3  
A4  
A9  
A8  
A7  
A6  
J3  
Output  
Output  
Input  
IN2  
Input  
LNA input Channel 2  
IN3  
Input  
LNA input Channel 3  
IN4  
Input  
LNA input Channel 4  
IN5  
Input  
LNA input Channel 5  
IN6  
Input  
LNA input Channel 6  
IN7  
Input  
LNA input Channel 7  
IN8  
Input  
LNA input Channel 8  
INT/EXT  
ISET  
Input  
Internal/ external reference mode select for ADS; internal = high  
Current bias pin for ADS. Requires 56kΩ to ground.  
LVDS bit clock (6x); negative output  
LVDS bit clock (6x); positive output  
LVDS data output (negative), Channel 1  
LVDS data output (positive), Channel 1  
LVDS data output (negative), Channel 2  
LVDS data output (positive), Channel 2  
LVDS data output (negative), Channel 3  
K9  
N2  
N1  
R4  
P4  
R3  
P3  
R2  
Input  
LCLKM  
LCLKP  
OUT1M  
OUT1P  
OUT2M  
OUT2P  
OUT3M  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
10  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
Table 1. TERMINAL FUNCTIONS (continued)  
PIN NO.  
P2  
R1  
P1  
R6  
P6  
R7  
P7  
R8  
P8  
R9  
P9  
J9  
PIN NAME  
OUT3P  
OUT4M  
OUT4P  
OUT5M  
OUT5P  
OUT6M  
OUT6P  
OUT7M  
OUT7P  
OUT8M  
OUT8P  
REFB  
REFT  
FUNCTION  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input/Output  
Input/Output  
Input  
DESCRIPTION  
LVDS data output (positive), Channel 3  
LVDS data output (negative), Channel 4  
LVDS data output (positive), Channel 4  
LVDS data output (negative), Channel 5  
LVDS data output (positive), Channel 5  
LVDS data output (negative), Channel 6  
LVDS data output (positive), Channel 6  
LVDS data output (negative), Channel 7  
LVDS data output (positive), Channel 7  
LVDS data output (negative), Channel 8  
LVDS data output (positive), Channel 8  
0.5V Negative reference of ADS. Decoupling to ground. Becomes input in external ref mode.  
2.5V Positive reference of ADS. Decoupling to ground. Becomes input in external ref mode.  
RESET input for VCA. Connect to the VCA_CS pin (H4).  
Connect to RST–pin (H5)  
J8  
H5  
H4  
F2  
RST  
VCA_CS  
VB1  
Output  
Output  
Output  
Output  
Output  
Output  
Output  
Input  
Internal bias voltage. Bypass to ground with 2.2µF.  
D8  
E3  
E7  
F3  
VB2  
Internal bias voltage. Bypass to ground with 0.1µF.  
VB3  
Internal bias voltage. Bypass to ground with 0.1µF.  
VB4  
Internal bias voltage. Bypass to ground with 0.1µF  
VB5  
Internal bias voltage. Bypass to ground with 0.1µF.  
F8  
VB6  
Internal bias voltage. Bypass to ground with 0.1µF.  
B1  
B2  
B3  
B4  
B9  
B8  
B7  
B6  
A5  
G3  
D2  
F7  
VBL1  
Complementary LNA input Channel 1; bypass to ground with 0.1µF.  
Complementary LNA input Channel 2; bypass to ground with 0.1µF.  
Complementary LNA input Channel 3; bypass to ground with 0.1µF.  
Complementary LNA input Channel 4; bypass to ground with 0.1µF.  
Complementary LNA input Channel 5; bypass to ground with 0.1µF.  
Complementary LNA input Channel 6; bypass to ground with 0.1µF.  
Complementary LNA input Channel 7; bypass to ground with 0.1µF.  
Complementary LNA input Channel 8; bypass to ground with 0.1µF.  
Power-down pin for VCA; low = normal mode, high = power-down mode.  
VCA reference voltage. Bypass to ground with 0.1µF.  
VBL2  
Input  
VBL3  
Input  
VBL4  
Input  
VBL5  
Input  
VBL6  
Input  
VBL7  
Input  
VBL8  
Input  
VCA_PD  
VCM  
Input  
Output  
Input  
VCNTL  
VREFH  
VREFL  
VCA control voltage input  
Output  
Output  
Clamp reference voltage (2.0V). Bypass to ground with 0.1µF.  
Clamp reference voltage (2.7V). Bypass to ground with 0.1µF.  
G7  
B5, H2, H3, K2,  
K4, M1, M2,  
M8, M9  
DNC  
Do not connect  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
LVDS TIMING DIAGRAM  
Sample n  
Sample n + 12  
ADC  
Input(1)  
tD(A)  
Sample n + 13  
ADCLK  
tSAMPLE  
12 clocks latency  
LCLKN  
6X ADCLK  
LCLKP  
OUTP  
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11  
SERIAL DATA  
OUTN  
ADCLKN  
1X ADCLK  
ADCLKP  
tPROP  
(1) Referenced to ADC Input (internal mode) for illustration purposes only.  
DEFINITION OF SETUP AND HOLD TIMES  
TIMING CHARACTERISTICS(1)  
AFE5805  
TYP  
PARAMETER  
ADC aperture delay  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
ns  
tD(A)  
1.5  
4.5  
Aperture delay variation Channel-to-channel within the same device (3σ)  
±20  
400  
ps  
tJ  
Aperture jitter  
fS, rms  
Time to valid data after coming out of  
COMPLETE POWER-DOWN mode  
50  
µs  
µs  
µs  
Time to valid data after coming out of PARTIAL  
POWER-DOWN mode (with clock continuing to  
run during power-down)  
tWAKE  
Wake-up time  
2
Time to valid data after stopping and restarting  
the input clock  
40  
12  
Clock  
cycles  
Data latency  
(1) Timing parameters are ensured by design and characterization; not production tested.  
12  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
SERIAL INTERFACE  
The AFE5805 has a set of internal registers that can be accessed through the serial interface formed by pins CS  
(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the  
following actions occur:  
•
•
•
Serial shift of bits into the device is enabled  
SDATA (serial data) is latched at every rising edge of SCLK  
SDATA is loaded into the register at every 24th SCLK rising edge  
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of  
24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16  
bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds  
(a few hertz) and also with a non-50% SCLK duty cycle.  
Register Initialization  
After power-up, the internal registers must be initialized to the respective default values. Initialization can be  
done in one of two ways:  
1. Through a hardware reset, by applying a low-going pulse on the ADS_RESET pin; or  
2. Through a software reset; using the serial interface, set the S_RST bit high. Setting this bit initializes the  
internal registers to the respective default values and then self-resets the bit low. In this case, the  
ADS_RESET pin stays high (inactive).  
Serial Port Interface (SPI) Information  
(connect externally)  
VCA_CS  
[H4]  
RST  
[H5]  
ADS_RESET  
[H9]  
VCA_SCLK  
VCA_SDATA  
SDATA  
CS  
[H8]  
[H76]  
SCLK  
[H6]  
ADS_CS  
ADS_SCLK  
ADS_SDATA  
ADS_RESET  
Tie to:  
+3.3V (AVDD2)  
[L9]  
EN_SM  
AFE5805  
Figure 1. Typical Connection Diagram for the SPI Control Lines  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
SERIAL INTERFACE TIMING  
Start Sequence  
End Sequence  
CS  
t6  
t1  
t2  
t7  
Data latched on rising edge of SCLK  
SCLK  
t3  
D15 D14 D13 D12 D11 D10 D9  
SDATA  
A7 A6 A5 A4 A3 A2 A1 A0  
D8 D7 D6 D5 D4 D3 D2 D1 D0  
t4  
t5  
AFE5805  
PARAMETER  
DESCRIPTION  
SCLK period  
MIN  
TYP  
MAX  
UNIT  
ns  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
50  
20  
20  
5
SCLK high time  
SCLK low time  
Data setup time  
Data hold time  
ns  
ns  
ns  
5
ns  
CS fall to SCLK rise  
Time between last SCLK rising edge to CS rising edge  
8
ns  
8
ns  
Internally-Generated VCA Control Signals  
VCA_SCLK  
VCA_SDATA  
D0  
D39  
VCA_SCLK and VCA_SDATA signals are generated if:  
•
•
Registers with address 16, 17, or 18 (Hex) are written to  
EN_SM is HIGH  
14  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
SERIAL REGISTER MAP  
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1)(2)(3)(4)  
ADDRESS  
IN HEX  
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
NAME  
DESCRIPTION  
DEFAULT  
00  
X
S_RST  
Self-clearing software RESET.  
Inactive  
RE  
S_  
VC  
A
03  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16  
17  
18  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
1
X
X
VCA_DATA<0:15>  
VCA_DATA<16:317  
VCA_DATA<32:39>  
Channel-specific ADC  
power-down mode.  
X
X
X
X
PDN_CH<1:4>  
PDN_CH<1:5>  
PDN_PARTIAL  
PDN_COMPLETE  
PDN_PIN_CFG  
Inactive  
Inactive  
Inactive  
Inactive  
Channel-specific ADC  
power-down mode.  
x
X
X
X
X
Partial power-down mode (fast  
recovery from power-down).  
0F  
X
Register mode for complete  
power-down (slower recovery).  
0
X
0
Configures the PD pin for partial  
power-down mode.  
Complete  
power-down  
X
LVDS current drive  
X
X
X
ILVDS_LCLK<2:0> programmability for LCLKN and  
LCLKP pins.  
3.5mA drive  
LVDS current drive  
ILVDS_FRAME  
11  
X
X
X
programmability for ADCLKN and 3.5mA drive  
ADCLKP pins.  
<2:0>  
LVDS current drive  
X
X
X
ILVDS_DAT<2:0> programmability for OUTN and  
OUTP pins.  
3.5mA drive  
Enables internal termination for  
EN_LVDS_TERM  
Termination  
disabled  
X
1
1
1
LVDS buffers.  
Programmable termination for  
TERM_LCLK<2:0>  
Termination  
disabled  
X
X
X
LCLKN and LCLKP buffers.  
12  
TERM_FRAME  
<2:0>  
Programmable termination for  
ADCLKN and ADCLKP buffers.  
Termination  
disabled  
X
X
X
Programmable termination for  
OUTN and OUTP buffers.  
Termination  
disabled  
X
X
X
TERM_DAT<2:0>  
LFNS_CH<8:1>  
LFNS_CH<8:5>  
Channel-specific, low-frequency  
noise suppression mode enable.  
X
X
X
X
X
X
X
X
Inactive  
Inactive  
14  
24  
Channel-specific, low-frequency  
noise suppression mode enable.  
x
X
X
X
X
X
X
X
X
INP is  
positive  
input  
Swaps the polarity of the analog  
input pins electrically.  
INVERT_CH<1:4>  
INP is  
positive  
input  
Swaps the polarity of the analog  
input pins electrically.  
x
INVERT_CH<8:5>  
EN_RAMP  
Enables a repeating full-scale  
ramp pattern on the outputs.  
X
0
0
0
0
Inactive  
Inactive  
Enables the mode wherein the  
output toggles between two  
defined codes.  
DUALCUSTOM_  
PAT  
X
Enables the mode wherein the  
output is a constant specified  
code.  
SINGLE_CUSTOM  
_PAT  
0
0
X
Inactive  
25  
2MSBs for a single custom  
pattern (and for the first code of  
the dual custom pattern). <11> is  
the MSB.  
BITS_CUSTOM1  
<11:10>  
X
X
Inactive  
Inactive  
Inactive  
BITS_CUSTOM2  
<11:10>  
2MSBs for the second code of  
the dual custom pattern.  
X
X
10 lower bits for the single  
custom pattern (and for the first  
code of the dual custom pattern).  
<0> is the LSB.  
BITS_CUSTOM1  
<9:0>  
26  
X
X
X
X
X
X
X
X
X
X
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.  
(2) X = Register bit referenced by the corresponding name and description (default is 0).  
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.  
(4) Multiple functions in a register should be programmed in a single write operation.  
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Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued)  
ADDRESS  
IN HEX  
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
NAME  
DESCRIPTION  
DEFAULT  
BITS_CUSTOM2  
<9:0>  
10 lower bits for the second  
code of the dual custom pattern.  
27  
X
X
X
X
X
X
X
X
X
X
X
X
Inactive  
X
X
X
X
GAIN_CH1<3:0>  
GAIN_CH2<3:0>  
GAIN_CH3<3:0>  
GAIN_CH4<3:0>  
GAIN_CH5<3:0>  
GAIN_CH6<3:0>  
GAIN_CH7<3:0>  
GAIN_CH8<3:0>  
Programmable gain channel 4.  
Programmable gain channel 3.  
Programmable gain channel 2.  
Programmable gain channel 1.  
Programmable gain channel 5.  
Programmable gain channel 6.  
Programmable gain channel 7.  
Programmable gain channel 8.  
0dB gain  
0dB gain  
0dB gain  
0dB gain  
0dB gain  
0dB gain  
0dB gain  
0dB gain  
X
X
X
X
2A  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2B  
X
X
X
X
X
X
X
X
X
Single-  
ended clock  
1
1
DIFF_CLK  
EN_DCC  
Differential clock mode.  
Enables the duty-cycle correction  
circuit.  
Disabled  
External  
reference  
drives REFT  
and REFB  
42  
45  
Drives the external reference  
mode through the VCM pin.  
1
1
EXT_REF_VCM  
Controls the phase of LCLK  
output relative to data.  
X
X
PHASE_DDR<1:0>  
90 degrees  
0
X
0
PAT_DESKEW  
PAT_SYNC  
Enables deskew pattern mode.  
Enables sync pattern mode.  
Inactive  
Inactive  
X
Binary two's complement format  
for ADC output.  
Straight  
offset binary  
1
1
1
1
X
BTC_MODE  
MSB_FIRST  
Serialized ADC output comes  
out MSB-first.  
LSB-first  
output  
X
Enables SDR output mode  
(LCLK becomes a 12x input  
clock).  
DDR output  
mode  
46  
1
1
1
1
X
1
EN_SDR  
Controls whether the LCLK rising Rising edge  
or falling edge comes in the  
middle of the data window when  
operating in SDR output mode.  
of LCLK in  
middle of  
data window  
1
FALL_SDR  
SUMMARY OF FEATURES  
POWER IMPACT (Relative to Default)  
AT fS = 50MSPS  
FEATURES  
DEFAULT  
SELECTION  
ANALOG FEATURES  
Internal or external reference  
(driven on the REFT and REFB pins)  
N/A  
Pin  
Internal reference mode takes approximately 20mW more power on AVDD  
Exernal reference driven on the VCM pin  
Duty cycle correction circuit  
Off  
Off  
Register 42  
Register 42  
Approximately 8mW less power on AVDD  
Approximately 7mW more power on AVDD  
With zero input to the ADC, low-frequency noise suppression causes digital  
Low-frequency noise suppression  
Off  
Register 14  
Register 42  
switching at fS/2, thereby increasing LVDD power by approximately 5.5mW/channel  
Differential clock mode mode takes approximately 7mW more power on AVDD  
Refer to the Power-Down Modes section in the Electrical Characteristics table  
Single-ended or differential clock  
Power-down mode  
Single-ended  
Off  
Pin and register 0F  
DIGITAL FEATURES  
Programmable digital gain (0dB to 12dB)  
Straight offset or BTC output  
Swap polarity of analog input pins  
LVDS OUTPUT PHYSICAL LAYER  
LVDS internal termination  
0dB  
Straight offset  
Off  
Registers 2A and 2B  
Register 46  
No difference  
No difference  
No difference  
Register 24  
Off  
Register 12  
Register 11  
Approximately 7mW more power on AVDD  
LVDS current programmability  
LVDS OUTPUT TIMING  
3.5mA  
As per LVDS clock and data buffer current setting  
LSB- or MSB-first output  
LSB-first  
DDR  
Register 46  
Register 46  
Register 42  
No difference  
SDR mode takes approximately 2mW more power on LVDD  
(at fS = 30MSPS)  
DDR or SDR output  
LCLK phase relative to data output  
Refer to Figure 2  
No difference  
16  
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DESCRIPTION OF SERIAL REGISTERS  
SOFTWARE RESET  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
00  
X
S_RST  
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears  
to '0'.  
VCA Register Information  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
RES_V  
CA  
03  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VCA  
D15  
VCA  
D14  
VCA  
D13  
VCA  
D12  
VCA  
D11  
VCA  
D10  
VCA  
D9  
VCA  
D8  
VCA  
D7  
VCA  
D6  
VCA  
D5  
VCA  
D4  
VCA  
D3  
VCA  
D2  
1(1)  
D1  
1(1)  
D0  
16  
17  
18  
VCA  
D31  
VCA  
D30  
VCA  
D29  
VCA  
D28  
VCA  
D27  
VCA  
D26  
VCA  
D25  
VCA  
D24  
VCA  
D23  
VCA  
D22  
VCA  
D21  
VCA  
D20  
VCA  
D19  
VCA  
D18  
VCA  
D17  
VCA  
D16  
VCA  
D39  
VCA  
D38  
VCA  
D37  
VCA  
D36  
VCA  
D35  
VCA  
D34  
VCA  
D33  
VCA  
D32  
(1) Bits D0 and D1 of register 16 are forced to '1'.  
space  
•
•
VCA_SCLK and VCA_SDATA become active only when one of the registers 16, 17 or 18 (address in hex) of  
the AFE5805 are written into.  
The contents of all three registers (total 40 bits) are written on VCA_SDATA even if only one of the above  
registers is written into. This condition is only valid if the content of the register has changed because of the  
most recent write. Writing contents that are the same as existing contents does not trigger activity on  
VCA_SDATA.  
•
•
For example, if register 17 is written into after a RESET is applied, then the contents of register 17 as well as  
the default values of the bits in registers 16 and 18 are written into VCA_SDATA.  
If register 16 is then written to, then the new contents of register 16, the previously written contents of register  
17, and the default contents of register 18 are written into VCA_SDATA. Note that regardless of what is  
written into D0 and D1 of register 16, the respective outputs on VCA_SDATA are always ‘1’.  
•
•
Alternatively, all three registers (16, 17 and 18) can also be written within one write cycle of the ADC serial  
interface. In that case, there would be 48 consecutive SCLK edges within the same CS active window.  
VCA_SCLK is generated using an oscillator (running at approximately 6MHz) inside the AFE5805, but the  
oscillator is gated so that it is active only during the write operation of the 40 VCA bits.  
VCA Reset  
•
•
VCA_CS should be permanently connected to the RST-input.  
When VCA_CS goes high (either because of an active low pulse on ADC_RESET for more than 10ns or as a  
result or setting bit RES_VCA), the following functions are performed inside the AFE5805:  
–
–
Bits D0 and D1 of register 16 are forced to ‘1’  
All other bits in registers 16, 17 and 18 are RESET to the respective default values (‘0’ for all bits except  
D5 of register 16 which is set to a default of ‘1’).  
–
No activity on signals VCA_SCLK and VCA_SDATA.  
•
If bit RES_VCA has been set to ‘1’, then the state machine is in the RESET state until RES_VCA is set to ‘0’.  
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VCA Register Map  
BYTE 1  
D0:D7  
BYTE 2  
D12:D15  
BYTE 3  
BYTE 4  
D24:D27 D28:D31  
CH5 CH6  
BYTE 5  
D8:D11  
CH1  
D16:D19  
CH3  
D20:D23  
CH4  
D32:D35  
CH7  
D36:D39  
CH8  
Control  
CH2  
Byte 1—Control Byte Register Map  
BIT NUMBER  
BIT NAME  
1
DESCRIPTION  
D0 (LSB)  
D1  
Start bit; this bit is permanently set high = 1  
Write bit; this bit is permanently set high =1  
1= Power-down mode enabled.  
WR  
D2  
PWR  
BW  
D3  
Low-pass filter bandwidth setting (see Table 1)  
Clamp level setting (see Table 1)  
D4  
CL  
D5  
Mode  
PG0  
PG1  
1 = TGC Mode, 0 = CW Doppler Mode  
LSB of PGA Gain Control (see Table 2)  
MSB of PGA Gain Control  
D6  
D7 (MSB)  
Byte 2—First Data Byte  
BIT NUMBER  
D8 (LSB)  
D9  
BIT NAME  
DB1:1  
DB1:2  
DB1:3  
DB1:4  
DB2:1  
DB2:2  
DB2:3  
DB2:4  
DESCRIPTION  
Channel 1, LSB of Matrix Control  
Channel 1, Matrix Control  
D10  
Channel 1, Matrix Control  
D11  
Channel 1, MSB of Matrix Control  
Channel 2, LSB of Matrix Control  
Channel 2, Matrix Control  
D12  
D13  
D14  
Channel 2, Matrix Control  
D15 (MSB)  
Channel 2, MSB of Matrix Control  
Byte 3—Second Data Byte  
BIT NUMBER  
D16 (LSB)  
D17  
BIT NAME  
DB3:1  
DB3:2  
DB3:3  
DB3:4  
DB4:1  
DB4:2  
DB4:3  
DB4:4  
DESCRIPTION  
Channel 3, LSB of Matrix Control  
Channel 3, Matrix Control  
D18  
Channel 3, Matrix Control  
D19  
Channel 3, MSB of Matrix Control  
Channel 4, LSB of Matrix Control  
Channel 4, Matrix Control  
D20  
D21  
D22  
Channel 4, Matrix Control  
D23 (MSB)  
Channel 4, MSB of Matrix Control  
Byte 4—Third Data Byte  
BIT NUMBER  
D24 (LSB)  
D25  
BIT NAME  
DB5:1  
DB5:2  
DB5:3  
DB5:4  
DB6:1  
DB6:2  
DB6:3  
DB6:4  
DESCRIPTION  
Channel 5, LSB of Matrix Control  
Channel 5, Matrix Control  
D26  
Channel 5, Matrix Control  
D27  
Channel 5, MSB of Matrix Control  
Channel 6, LSB of Matrix Control  
Channel 6, Matrix Control  
D28  
D29  
D30  
Channel 6, Matrix Control  
D31 (MSB)  
Channel 6, MSB of Matrix Control  
18  
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Byte 5—Fourth Data Byte  
BIT NUMBER  
D32 (LSB)  
D33  
BIT NAME  
DB7:1  
DB7:2  
DB7:3  
DB7:4  
DB8:1  
DB8:2  
DB8:3  
DB8:4  
DESCRIPTION  
Channel 7, LSB of Matrix Control  
Channel 7, Matrix Control  
D34  
Channel 7, Matrix Control  
D35  
Channel 7, MSB of Matrix Control  
Channel 8, LSB of Matrix Control  
Channel 8, Matrix Control  
D36  
D37  
D38  
Channel 8, Matrix Control  
D39 (MSB)  
Channel 8, MSB of Matrix Control  
Clamp Level and LPF Bandwidth Setting  
FUNCTION  
Bandwidth set to 15MHz  
BW  
BW  
CL  
D3 = 0  
D3 = 1  
D4 = 0  
D4 = 1  
Bandwidth set to 10MHz  
Clamps the output signal at 2dB below the full-scale of 2VPP (1.6VPP  
Clamp transparent (disabled)  
)
CL  
PGA Gain Setting  
PG1 (D7)  
PG0 (D6)  
FUNCTION  
Sets PGA gain to 20dB  
0
0
1
1
0
1
0
1
Sets PGA gain to 25dB  
Sets PGA gain to 27dB  
Sets PGA gain to 30dB  
CW Switch Matrix Control for Each Channel  
DBn:4 (MSB)  
DBn:3  
DBn:2  
DBn:1 (LSB)  
LNA INPUT CHANNEL n DIRECTED TO  
Output CW0  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output CW1  
Output CW2  
Output CW3  
Output CW4  
Output CW5  
Output CW6  
Output CW7  
Output CW8  
Output CW9  
Connected to AVDD1  
Connected to AVDD1  
Connected to AVDD1  
Connected to AVDD1  
Connected to AVDD1  
Connected to AVDD1  
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POWER-DOWN MODES  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
X
X
X
X
X
X
X
X
PDN_CH<8:1>  
x
0F  
X
PDN_PARTIAL  
PDN_COMPLETE  
PDN_PIN_CFG  
0
X
0
X
Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for  
the ADC channel <N>.  
In addition to channel-specific power-down, the AFE5805 also has two global power-down modes: partial  
power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;  
recovery from this mode is much quicker, provided that the clock has been running for at least 50µs before  
exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and  
involves a much longer recovery time.  
In addition to programming the device for either of these two power-down modes (through either the  
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial  
power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the  
PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin  
is high, the device enters partial power-down mode.  
LVDS DRIVE PROGRAMMABILITY  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
X
X
X
ILVDS_LCLK<2:0>  
ILVDS_FRAME<2:0>  
ILVDS_DAT<2:0>  
11  
X
X
X
X
X
X
The LVDS drive strength of the bit clock (LCLKP or LCLKN) and the frame clock (ADCLKP or ADCLKN) can be  
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTN can also be  
programmed to the same value.  
All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 3  
shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame  
clock and data drive strengths).  
Table 3. Bit Clock Drive Strength(1)  
ILVDS_LCLK<2>  
ILVDS_LCLK<1>  
ILVDS_LCLK<0>  
LVDS DRIVE STRENGTH FOR LCLKP AND LCLKN  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3.5mA (default)  
2.5mA  
1.5mA  
0.5mA  
7.5mA  
6.5mA  
5.5mA  
4.5mA  
(1) Current settings lower than 1.5mA are not recommended.  
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LVDS INTERNAL TERMINATION PROGRAMMING  
ADDRESS  
IN HEX  
D15  
D14  
X
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
EN_LVDS_TERM  
TERM_LCLK<2:0>  
TERM_FRAME<2:0>  
TERM_DAT<2:0>  
1
X
X
X
12  
1
X
X
X
1
X
X
X
The LVDS buffers have high-impedance current sources that drive the outputs. When driving traces with  
characteristic impedances that are not perfectly matched with the termination impedance on the receiver side,  
there may be reflections back to the LVDS output pins of the AFE5805 that cause degraded signal integrity. By  
enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal  
integrity can be significantly improved in such scenarios. To set the internal termination mode, the  
EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock,  
frame clock, and data buffers can be independently programmed using sets of three bits. Table 4 shows an  
example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is  
similar for the frame clock and data drive strengths). These termination values are only typical values and can  
vary by several percentages across temperature and from device to device.  
Table 4. Bit Clock Internal Termination  
INTERNAL TERMINATION BETWEEN  
TERM_LCLK<2>  
TERM_LCLK<1>  
TERM_LCLK<0>  
LCLKP AND LCLKN IN Ω  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None  
260  
150  
94  
125  
80  
66  
55  
LOW-FREQUENCY NOISE SUPPRESSION MODE  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
X
X
X
X
LFNS_CH<1:4>  
LFNS_CH<8:5>  
14  
X
X
X
X
The low-frequency noise suppression mode is especially useful in applications where good noise performance is  
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of  
the AFE5805 to approximately fS/2, thereby moving the noise floor around dc to a much lower value.  
LFNS_CH<8:1> enables this mode individually for each channel.  
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ANALOG INPUT INVERT  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
X
X
X
X
INVERT_CH<1:4>  
INVERT_CH<8:5>  
24  
X
X
X
X
Normally, the INP pin represents the positive analog input pin, and INN represents the complementary negative  
input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be  
swapped. INN now represents the positive input, and INP the negative input.  
LVDS TEST PATTERNS  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
X
D5  
0
D4  
0
D3  
D2  
D1  
D0  
NAME  
EN_RAMP  
0
X
0
DUALCUSTOM_PAT  
SINGLE_CUSTOM_PAT  
BITS_CUSTOM1<11:10>  
BITS_CUSTOM2<11:10>  
BITS_CUSTOM1<9:0>  
BITS_CUSTOM2<9:0>  
PAT_DESKEW  
25  
0
0
X
X
X
X
X
26  
27  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0
45  
X
PAT_SYNC  
The AFE5805 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal  
ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.  
The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the  
full-scale code, it returns back to zero code and ramps again.  
The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and  
programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM<11:0> take the place of  
the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as  
normal ADC data are.  
The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT  
to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>.  
In addition to custom patterns, the device may also be made to output two preset patterns:  
1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the  
010101010101 word.  
2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word.  
Note that only one of the above patterns should be active at any given instant.  
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PROGRAMMABLE GAIN  
ADDRESS  
IN HEX  
D15  
D14  
D13  
D12  
D11  
X
D10  
X
D9  
X
D8  
X
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
NAME  
X
X
X
X
GAIN_CH4<3:0>  
GAIN_CH3<3:0>  
GAIN_CH2<3:0>  
GAIN_CH1<3:0>  
GAIN_CH5<3:0>  
GAIN_CH6<3:0>  
GAIN_CH7<3:0>  
GAIN_CH8<3:0>  
X
X
X
X
2A  
X
X
X
X
X
X
X
X
X
X
X
X
2B  
X
X
X
X
X
X
X
X
The AFE5805, through its registers, allows for a digital gain to be programmed for each channel. This  
programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The  
programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by  
using quantization information from some extra internal bits. The programmable gain for each channel can be  
individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in  
binary from 0dB to 12dB, as shown in Table 5.  
Table 5. Gain Setting for Channel 1  
GAIN_CH1<3>  
GAIN_CH1<2>  
GAIN_CH1<1>  
GAIN_CH1<0>  
CHANNEL 1 GAIN SETTING  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0dB  
1dB  
2dB  
3dB  
4dB  
5dB  
6dB  
7dB  
8dB  
9dB  
10dB  
11dB  
12dB  
Do not use  
Do not use  
Do not use  
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CLOCK, REFERENCE, AND DATA OUTPUT MODES  
ADDRESS  
IN HEX  
D15  
1
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
X
D2  
D1  
D0  
NAME  
X
DIFF_CLK  
EN_DCC  
1
X
42  
1
EXT_REF_VCM  
PHASE_DDR<1:0>  
BTC_MODE  
MSB_FIRST  
EN_SDR  
1
X
X
1
1
1
1
1
X
1
X
46  
1
X
1
1
1
FALL_SDR  
INPUT CLOCK  
The AFE5805 is configured by default to operate with a single-ended input clock; CLKP is driven by a CMOS  
clock and CLKM is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a  
differential input clock on CLKP and CLKM. Operating with a low-jitter differential clock generally provides better  
SNR performance, especially at input frequencies greater than 30MHz.  
In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable  
an internal duty cycle correction circuit. Enable this circuit by setting the EN_DCC bit to '1'.  
EXTERNAL REFERENCE  
The AFE5805 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,  
the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have  
enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The  
advantage of using the external reference mode is that multiple AFE5805 units can be made to operate with the  
same external reference, thereby improving parameters such as gain matching across devices. However, in  
applications that do not have an available high drive, differential external reference, the AFE5805 can still be  
driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the  
INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFT and REFB are  
generated as shown in Equation 1 and Equation 2.  
VCM  
VREFT = 1.5V +  
1.5V  
(1)  
(2)  
VCM  
VREFB = 1.5V -  
1.5V  
24  
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BIT CLOCK PROGRAMMABILITY  
The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge  
transitions in the middle of alternate data windows. Figure 2 shows this default phase.  
ADCLKP  
LCLKP  
OUTP  
Figure 2. LCLK Default Phase  
The phase of LCLK can be programmed relative to the output frame clock and data using bits  
PHASE_DDR<1:0>. Figure 3 shows the LCLK phase modes.  
PHASE_DDR<1:0> = '00'  
PHASE_DDR<1:0> = '10'  
ADCLKP  
ADCLKP  
LCLKP  
OUTP  
LCLKP  
OUTP  
PHASE_DDR<1:0> = '01'  
PHASE_DDR<1:0> = '11'  
ADCLKP  
ADCLKP  
LCLKP  
OUTP  
LCLKP  
OUTP  
Figure 3. LCKL Phase Programmability Modes  
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In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR  
mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12 times the input clock, or  
twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two  
manners shown in Figure 4. As Figure 4 illustrates, only the LCLK rising (or falling) edge is used to capture the  
output data in SDR mode.  
EN_SDR = '1', FALL_SDR = '0'  
ADCLKP  
LCLKP  
OUTP  
EN_SDR = '1', FALL_SDR = '1'  
ADCLKP  
LCLKP  
OUTP  
Figure 4. SDR Interface Modes  
The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.  
DATA OUTPUT FORMAT MODES  
The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the  
MSB, and the output becomes binary two's complement mode.  
Also by default, the first bit of the frame (following the rising edge of ADCLKP) is the LSB of the ADC output.  
Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit  
following the ADCLKP rising edge.  
26  
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TYPICAL CHARACTERISTICS  
AVDD_5V = 5.0V, AVDD1 = VDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 1.0µF,  
VCNTL = 1.0V, fIN 5MHz, Clock = 40MSPS, 50% duty cycle, –1dBFS input magnitude, internal reference mode, ISET = 56kΩ,  
LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.  
GAIN SWEEP  
vs PG SETTING  
10MHz LOW-PASS FILTER RESPONSE  
50  
44  
38  
32  
26  
20  
14  
8
0
-2  
-4  
27dB  
-6  
30dB  
-8  
-10  
-12  
-14  
-16  
-18  
-20  
20dB  
2
25dB  
-4  
-10  
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2  
0
5
10  
15  
20  
25  
30  
35  
VCNTRL (V)  
Frequency (MHz)  
Figure 5.  
Figure 6.  
15MHz LOW-PASS FILTER RESPONSE  
CROSSTALK BETWEEN CH 8 AND CH N AT 2MHz  
0
-2  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
-4  
-6  
-8  
-10  
-12  
-14  
-16  
-18  
-20  
0
5
10  
15  
20  
25  
30  
35  
1
2
3
4
5
6
7
Frequency (MHz)  
Input at Ch N  
Figure 8.  
Figure 7.  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
APPLICATION INFORMATION  
CLOCK INPUT  
The eight channels on the device operate from a  
single ADCLK input. To ensure that the aperture  
delay and jitter are the same for all channels, the  
AFE5805 uses a clock tree network to generate  
individual sampling clocks to each channel. The clock  
paths for all the channels are matched from the  
source point to the sampling circuit. This architecture  
ensures that the performance and timing for all  
channels are identical. The use of the clock tree for  
matching introduces an aperture delay that is defined  
as the delay between the rising edge of ADCLK and  
the actual instant of sampling. The aperture delays  
for all the channels are matched to the best possible  
extent. A mismatch of ±20ps (±3σ) could exist  
between the aperture instants of the eight ADCs  
within the same chip. However, the aperture delays of  
ADCs across two different chips can be several  
hundred picoseconds apart.  
VCM  
VCM  
5kW  
5kW  
CLKP  
CLKM  
Figure 10. Internal Clock Buffer  
0.1mF  
CLKP  
The AFE5805 can operate either in CMOS  
single-ended clock mode (default is DIFF_CLK = 0)  
or differential clock mode (SINE, LVPECL, or LVDS).  
In the single-ended clock mode, CLKM must be forced  
to 0VDC, and the single-ended CMOS applied on the  
CLKP pin. Figure 9 shows this operation.  
Differential Sine-Wave,  
PECL, or LVDS Clock Input  
0.1mF  
CLKM  
Figure 11. Differential Clock Driving Circuit  
(DIFF_CLK = 1)  
CMOS Single-Ended  
CLKP  
Clock  
0.1mF  
0V  
CLKM  
CMOS Clock Input  
CLKP  
CLKM  
0.1mF  
Figure 9. Single-Ended Clock Driving Circuit  
(DIFF_CLK = 0)  
When configured for the differential clock mode  
(register bit DIFF_CLK = 1) the ADS528x clock inputs  
can be driven differentially (SINE, LVPECL, or LVDS)  
with little or no difference in performance between  
Figure 12. Single-Ended Clock Driving Circuit  
When DIFF_CLK = 1  
them, or with  
common-mode voltage of the clock inputs is set to  
VCM using internal 5kΩ resistors, as shown in  
a single-ended (LVCMOS). The  
For best performance, the clock inputs must be  
driven differentially, reducing susceptibility to  
common-mode noise. For high input frequency  
sampling, it is recommended to use a clock source  
with very low jitter. Bandpass filtering of the clock  
source can help reduce the effect of jitter. If the duty  
cycle deviates from 50% by more than 2% or 3%, it is  
recommended to enable the DCC through register bit  
EN_DCC.  
Figure  
10.  
This  
method  
allows  
using  
transformer-coupled drive circuits for a sine wave  
clock or ac-coupling for LVPECL and LVDS clock  
sources, as shown in Figure 11 and Figure 12. When  
operating in the differential clock mode, the  
single-ended CMOS clock can be ac-coupled to the  
CLKP input, with CLKM connected to ground with a  
0.1µF capacitor, as Figure 12 shows.  
28  
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SBOS421A–MARCH 2008–REVISED MARCH 2008  
REFERENCE CIRCUIT  
The device also supports the use of external  
reference voltages. There are two methods to force  
the references externally. The first method involves  
pulling INT/EXT low and forcing externally REFT and  
REFB to 2.5V and 0.5V nominally, respectively. In  
this mode, the internal reference buffer goes to a  
3-state output. The external reference driving circuit  
should be designed to provide the required switching  
current for the eight ADCs inside the chip. It should  
be noted that in this mode, VCM and ISET continue to  
be generated from the internal bandgap voltage, as in  
the internal reference mode. It is therefore important  
to ensure that the common-mode voltage of the  
externally-forced reference voltages matches to  
The digital beam-forming algorithm in an ultrasound  
system relies on gain matching across all receiver  
channels. A typical system would have about 12 octal  
ADCs on the board. In such a case, it is critical to  
ensure that the gain is matched, essentially requiring  
the reference voltages seen by all the ADCs to be the  
same. Matching references within the eight channels  
of a chip is done by using a single internal reference  
voltage buffer. Trimming the reference voltages on  
each chip during production ensures that the  
reference voltages are well-matched across different  
chips.  
within 50mV of VCM  
.
All bias currents required for the internal operation of  
the device are set using an external resistor to  
ground at the ISET pin. Using a 56kΩ resistor on ISET  
generates an internal reference current of 20µA. This  
current is mirrored internally to generate the bias  
current for the internal blocks. Using a larger external  
resistor at ISET reduces the reference bias current and  
thereby scales down the device operating power.  
However, it is recommended that the external resistor  
be within 10% of the specified value of 56kΩ so that  
the internal bias margins for the various blocks are  
proper.  
The second method of forcing the reference voltages  
externally can be accessed by pulling INT/EXT low,  
and programming the serial interface to drive the  
external reference mode through the VCM pin (register  
bit called EXT_REF_VCM). In this mode, VCM  
becomes configured as an input pin that can be  
driven from external circuitry. The internal reference  
buffers driving REFT and REFB are active in this  
mode. Forcing 1.5V on the VCM pin in the mode  
results in REFT and REFB coming to 2.5V and 0.5V,  
respectively. In general, the voltages on REFT and  
REFB in this mode are given by Equation 3 and  
Equation 4:  
Buffering the internal bandgap voltage also generates  
the common-mode voltage VCM, which is set to the  
midlevel of REFT and REFB, and is accessible on a  
pin (pin 65 in TQFP-80 package, pin 53 in QFN-64  
package). It is meant as a reference voltage to derive  
the input common-mode if the input is directly  
coupled. It can also be used to derive the reference  
common-mode voltage in the external reference  
mode. Figure 13 shows the suggested decoupling for  
the reference pins.  
VCM  
VREFT = 1.5V +  
1.5V  
(3)  
VCM  
VREFB = 1.5V -  
1.5V  
(4)  
The state of the reference voltage internal buffers  
during various combinations of the PD, INT/EXT, and  
EXT_REF_VCM register bits is described in Table 6.  
AFE5805  
ISET  
REFT  
REFB  
56.2kW  
+
+
0.1mF  
2.2mF  
2.2mF  
0.1mF  
Figure 13. Suggested Decoupling on the Reference Pins  
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Table 6. State of Reference Voltages for Various Combinations of PD and INT/EXT  
REGISTER BIT  
PD  
INTERNAL BUFFER STATE  
0
0
0
1
0
1
0
0
1
0
1
1
1
INT/EXT  
1
1
0
1
1
EXT_REF_VCM  
REFT buffer  
REFB buffer  
VCM pin  
0
0
0
0
1
1
3-state  
3-state  
1.5V  
2.5V  
0.5V  
1.5V  
3-state  
3-state  
1.5V  
2.5V(1)  
0.5V(1)  
1.5V  
1.5V + VCM/1.5V  
1.5V – VCM/1.5V  
Force  
Do not use  
Do not use  
Do not use  
2.5V(1)  
0.5V(1)  
Force  
Do not use  
Do not use  
Do not use  
(1) Weakly forced with reduced strength.  
Smaller effective inductance of the supply and ground  
pins leads to better noise suppression. For this  
reason, multiple pins are used to drive each supply  
and ground. It is also critical to ensure that the  
impedances of the supply and ground lines on the  
board are kept to the minimum possible values. Use  
of ground planes in the printed circuit board (PCB) as  
well as large decoupling capacitors between the  
supply and ground lines are necessary to obtain the  
best possible SNR performance from the device.  
NOISE COUPLING ISSUES  
High-speed mixed signals are sensitive to various  
types of noise coupling. One primary source of noise  
is the switching noise from the serializer and the  
output buffers. Maximum care is taken to isolate  
these noise sources from the sensitive analog blocks.  
As a starting point, the analog and digital domains of  
the device are clearly demarcated. AVDD and AVSS  
are used to denote the supplies for the analog  
sections, while LVDD and LVSS are used to denote  
the digital supplies. Care is taken to ensure that there  
is minimal interaction between the supply sets within  
the device. The extent of noise coupled and  
transmitted from the digital to the analog sections  
depends on:  
It is recommended that the isolation be maintained  
onboard by using separate supplies to drive AVDD  
and LVDD, as well as separate ground planes for  
AVSS and LVSS. The use of LVDS buffers reduces  
the injected noise considerably, compared to CMOS  
buffers. The current in the LVDS buffer is  
independent of the direction of switching. Also, the  
low output swing as well as the differential nature of  
the LVDS buffer results in low-noise coupling.  
1. The effective inductances of each of the supply  
and ground sets.  
2. The isolation between the digital and analog  
supply and ground sets.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
19-May-2008  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
BGA  
BGA  
BGA  
Drawing  
AFE5805ZCFR  
AFE5805ZCFT  
PAFE5805ZCF  
PREVIEW  
PREVIEW  
PREVIEW  
ZCF  
135  
135  
135  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
ZCF  
ZCF  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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