ALM2402QDRRRQ1 [TI]
具有高电流输出的双路运算放大器 | DRR | 12 | -40 to 125;
| 型号： | ALM2402QDRRRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高电流输出的双路运算放大器 | DRR | 12 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总35页 (文件大小：3043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
ALM2402-Q1 具有高电流输出的双路运算放大器
1 特性
3 说明
1
•
高输出电流驱动能力：400mA 持续电流（每通道）
替换分立式电源升压缓冲器的运算放大器
ALM2402-Q1 是一款具有保护功能的双路高电压、高
电流运算放大器，非常适合用于驱动低阻抗和/或高等
效串联电阻 (ESR) 的容性负载。 ALM2402-Q1 由
5.0V 至 16V 范围内的单电源或分离电源供电运行，可
提供高达 400mA 的直流输出。
–
•
•
•
•
•
两类电源均具有宽电源范围（高达 16V）
过热关断
电流限制
针对低静态电流应用的关断引脚
每个运算放大器均具有过热标志以及过热关断功能。
该器件还为每个输出级提供了独立的电源引脚，允许用
户对输出施加较低电压以限制 Voh，从而限制片上功
耗。
与高容值容性负载（高达 3µF）搭配使用时可保持
稳定
•
•
•
零交叉失真
符合汽车应用要求
ALM2402 提供有 12 引脚无引线 DRR 封装和 14
引脚带引线散热薄型小外形尺寸 (HTSSOP) 封装（预
览）。 这两种封装均包含导热焊盘，有助于散热。 而
且这两种封装的热阻均非常低，能够以最低的芯片温升
实现最佳电流驱动能力， 从而使客户在恶劣的温度条
件下也能够获得较高的驱动电流。 可从下图中确定器
件的最大功耗。
具有符合 AEC-Q100 的下列结果：
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
–
–
器件人体模型 (HBM) 分类等级 H2
器件充电器件模型 (CDM) 分类等级 C5
•
•
•
低偏移电压：1mV（典型值）
内部射频 (RF)/电磁干扰 (EMI) 滤波器
采用带散热焊盘的 3mm x 3mm 12 引脚晶圆级小
外形无引线 (WSON) (DRR) 封装
器件信息(1)
器件型号
封装
封装尺寸
DRR (12)
HTSSOP (14)
3.00mm x 3.00mm
5.00mm x 4.40mm
2 应用
ALM2402-Q1
•
高容值容性负载
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
–
电缆护套
参考缓冲器
功率 FET/IGBT 栅极
超级电容
•
•
跟踪 LDO
感性负载
–
–
–
旋转变压器
双极直流与伺服电机
螺线管与阀门
4 简化电路原理图
VCC_OUT
最大功耗与温度间的关系
VCC
5
4.5
4
VCC
½
VCC_ O1
IN1+
IN1-
+
+
OPAMP
ALM2402
OUT1
3.5
3
OTF1
GND
2.5
2
1.5
1
0.5
-40
-20
0
20
40
60
80
100 120 140
TA(qC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS912
ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
Applications and Implementation ...................... 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 15
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Thermal Information.................................................. 4
7.3 ESD Ratings ............................................................ 4
7.4 Recommended Operating Conditions....................... 4
7.5 Electrical Characteristics........................................... 5
7.6 AC Characteristics .................................................... 5
7.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 商标....................................................................... 22
12.2 静电放电警告......................................................... 22
12.3 术语表 ................................................................... 22
13 机械、封装和可订购信息....................................... 22
8
5 修订历史记录
Changes from Revision A (April 2015) to Revision B
Page
•
已将 HBM 分类中的“等级 2”修正为“等级 H2” ......................................................................................................................... 1
Changes from Original (February 2015) to Revision A
Page
•
最初发布的完整版文档。 ....................................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
ALM2402-Q1
www.ti.com.cn
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
6 Pin Configuration and Functions
HTSSOP
DRR
14
IN1-
IN1+
1
2
3
4
5
6
7
GND
1
2
3
4
5
6
GND
IN1-
IN1+
12
11
10
9
13
12
11
10
9
OUT1
VCC_O1
VCC
OUT1
OTF/SH_DN
IN2+
Exposed
Thermal Pad
Exposed
Thermal Pad
VCC_O1
VCC
OTF/SH_DN
IN2+
IN2-
VCC_O2
OUT2
NC
VCC_O2
OUT2
IN2-
8
GND
GND
7
8
NC
It is recommended to connect the Exposed Pad to ground for best thermal performance. Must not be connected to
any other pin than ground. However, it can be left floating.
HTSSOP is in preview
Pin Functions
PIN
DDR
NO.
2, 4
PWP(1)
NO.
I/O
DESCRIPTION
NAME
IN(X)+
IN(X)-
2, 4
Input
Input
non-inverting opamp input terminal
inverting opamp input terminal
Opamp output
1, 5
1, 5
OUT(X)
11, 7
13, 9
Output
OTF/SH_D
N
3
3
Input/output Over temperature flag and Shutdown (see for truth table)
VCC_O(X)
VCC
8, 10
9
10, 12
11
Input
Input
Input
N/A
Output stage supply pin
Gain stage supply pin
GND
6, 12
N/A
14
Ground pin (Both ground pins must be used and connected together on board)
No Internal Connection (do no connect)
NC
7, 8
(1) Preview.
Copyright © 2015, Texas Instruments Incorporated
3
ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
at 25°C free-air temperature (unless otherwise noted)
MIN
-0.3
-0.3
-0.3
-0.3
MAX
UNIT
V
VCC
Supply Voltage
18
18
18
18
20
7
VCC_(OX) Output supply voltage(2)
V
VOUT(X)
VIN(X)
IOTF
Opamp voltage(2)
V
(2)
Positive and negative input to GND voltage
V
Over Temperature Flag pin maximum Current
Over Temperature Flag pin maximum Voltage
Continuous output short current per opamp
mA
V
VOTF
ISC
0
Internally
Limited
mA
图 6
125
150
150
TA
Operating free-air temperature range
Operating virtual junction temperature(3)
Storage temperature range
–40
-40
°C
°C
°C
TJ
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND/substrate terminal, unless otherwise noted.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
7.2 Thermal Information
ALM2402Q1
THERMAL METRIC(1)
DRR
12 PINS
39.2
UNIT
θJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.5
15.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
15.2
θJCbot
4.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.3 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.4 Recommended Operating Conditions
TA= 25°C
MIN
-40
-40
MAX
150
UNIT
TJ
Junction Temperature
Ambient Temeperature
°C
TA
125
4
Copyright © 2015, Texas Instruments Incorporated
ALM2402-Q1
www.ti.com.cn
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
Recommended Operating Conditions (continued)
TA= 25°C
MIN
MAX
400
UNIT
Continuous output current (sourcing)
(1)
IOUT
mA
Continuous output current (sinking)
400
VIH_OTF
VIL_OTF
VIN(X)
OTF input high voltage (Opamp "On" or full operation state)
OTF input low voltage (Opamp "Off" or shutdown state)
Positive and negative input to GND voltage
Over Temperature Flag pin maximum Voltage
Input Vcc
1.0
0.35
7
0
2
V
VOTF
5
VCC
4.5
3
16
16
VCC_O(X)
Output Vcc
(1) Current Limit must taken into consideration when choosing maximum output current
7.5 Electrical Characteristics
VOTF = 5 V, VCC = VCC_O1 = VCC_O2 = 5 V and 12 V; TA = –40°C to 125°C; Typical Values at TA = 25°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
nA
(1)
(1)
VIO
IIB
Input Offset Voltage
VICM = Vcc/2, RL = 10 kΩ
1
15
(1)
Input Bias Current
Input Offset Current
VICM = Vcc/2
VICM = Vcc/2
VCC = 5.0
1.5
100
30
IIOS
nA
(1)
Input Common Mode Range
0.2
0.2
Vcc-1.2
7
V
VICM
VCC = 12.0 V
IO = 0 A
Total Supply Current (both
amplifiers)(1)
5
0.5(2)
4.87
15
mA
V
ICC
VOTF = 0V
Positive Output Swing
VCC = VCC_O(X) = 5.0
V; VICM = Vcc/2; VID
100 mV
ISINK = 200 mA
ISINK = 100 mA
4.7
=
=
4.85
4.94
Vo
Negative Output Swing
VCC = VCC_O(X) = 5.0
V; VICM = Vcc/2; VID
100 mV
ISOURCE = 200
mA
200
100
165
425
200
mV
ISOURCE = 100
mA
OTF
Over Temp. Fault and Shutdown(3)
Over Temp. Fault low voltage
Short to Supply Limit (low-side limit)(4)
157
175
450
°C
mV
mA
VOL_OTF
Rpullup = 2.5 kΩ, Vpullup = 5.0 V
550
750
ILIMIT
Short to Ground Limit (high-side
limit)(1)(4)
VCC = 5.0 V to 12 V, RL = 10 kΩ, VICM
Vcc/2, VO = Vcc/2
=
65
45
90
90
PSRR
CMRR
AVD
Power Supply Rejection Ratio(1)
Common Mode Rejection Ratio(1)
DC Voltage Gain(1)
dB
dB
dB
VICM = VICM(min) to VICM(max), RL = 10
kΩ, VO = Vcc/2
RL = 10 kΩ, VICM = Vcc/2, VO = 0.3 V to
Vcc-1.5
70
90
(1) Tested and verified in closed loop negative feedback configuration.
(2) Verified by design.
(3) Please see refer to Absolute Maximum Ratings() table for maximum junction temperature recommendations.
(4) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay.
7.6 AC Characteristics
TJ= –40°C to 125°C; Typical Values at TA = TJ = 25°C; VCC = VCC_O1 = VCC_O2 = 5.0 V and 12 V; VICM=VCC/2
PARAMETER
Gain Bandwidth
TEST CONDITIONS
CL=15 pF RL=10 kΩ
MIN
TYP
600
50
MAX
UNIT
KHz
°
GBW
PM
Phase Margin
CL=200 nF RL= 50 Ω
GM
Gain Margin
CL=200 nF RL= 50 Ω
17
dB
SR
Slew Rate
G = +1; CL=50 pF; 3 V step
0.17
-80
V/us
dB
THD + N
Total Harmonic Distortion + Noise
AV = 2 V/V, RL = 100 Ω, Vo = 8 Vpp, Vcc
= 12 V, F = 1 kHz, VICM = Vcc/2
Copyright © 2015, Texas Instruments Incorporated
5
ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
www.ti.com.cn
AC Characteristics (continued)
TJ= –40°C to 125°C; Typical Values at TA = TJ = 25°C; VCC = VCC_O1 = VCC_O2 = 5.0 V and 12 V; VICM=VCC/2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
en
Input Voltage Noise Density
Vcc = 5 V, F = 1kHz, VICM = Vcc/2
110
nV/√HZ
7.7 Typical Characteristics
TA= 25°C and VCC = VCC_O(X)
0.65
0.6
5.01
TA=-40°C
TA=0°C
TA=25°C
TA=85°C
TA=105°C
TA=125°C
TA=-40°C
TA=0°C
TA=25°C
TA=85°C
TA=105°C
TA=125°C
4.98
4.95
4.92
4.89
4.86
4.83
4.8
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
4.77
-350
-300
-250
-200
-150
-100
-50
0
0
50
100
150
200
250
300
350
Iout (mA)
Iout (mA)
图 1. VOH at VCC = 5 V
图 2. VOL at VCC = 5V
0.65
0.6
3.3
3.25
3.2
TA=-40°C
TA=0°C
TA=25°C
TA=85°C
TA=105°C
TA=125°C
TA=-40°C
TA=125°C
TA=0°C
TA=85°C
TA=25°C
0.55
0.5
0.45
0.4
0.35
0.3
3.15
3.1
0.25
0.2
0.15
0.1
3.05
3
0.05
0
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0
50
100
150
200
250
300
350
Iout (mA)
Iout (mA)
图 3. VOH at VCC = 3.3 V
图 4. VOL at VCC = 3.3 V
6
版权 © 2015, Texas Instruments Incorporated
ALM2402-Q1
www.ti.com.cn
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
Typical Characteristics (接下页)
TA= 25°C and VCC = VCC_O(X)
0.75
0.95
0.9
VCC=5V
VCC=12V
VCC=5V
VCC=12V
0.7
0.65
0.6
0.85
0.8
0.55
0.5
0.75
0.7
0.45
0.4
0.65
0.6
0.35
0.55
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TA(qC)
TA(qC)
图 5. Short to Supply Current Limit vs. Temperature
图 6. Short to Groung Current Limit vs. Temperature
400
120
Vcc_o(x) Diode (high side)
GND Diode (low side)
Gain
Phase
350
300
250
200
150
100
50
90
60
30
0
-30
-60
0
200
300
400
500 600 700 800
1000
1
2 3 45 7 10 2030 50 100 200 5001000
Freq (kHz)
10000
Forward Voltage
VCC = 5.0 V
图 7. PMOS (High Side) and NMOS (Low Side) Output Diode
图 8. Gain and Phase (CL = 200 nF and RL = 50 Ω)
Forward Voltage
100
10
1
150
Gain
Phase
Vcc = 5V
Vcc = 12V
120
90
60
30
0
-30
-60
0.1
0.05
1
2 3 45 7 10 2030 50 100 200 5001000
Freq (kHz)
10000
0.01
0.1
1
10
100
1000
10000
Freq (kHz)
VCC = 5.0 V
图 9. Gain and Phase (CL = 50 pF and RL = 10 kΩ)
图 10. Output Impedance vs. Frequency
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ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
www.ti.com.cn
Typical Characteristics (接下页)
TA= 25°C and VCC = VCC_O(X)
140
100
80
60
40
20
0
VCC=5V
VCC=12V
PSRR- Vcc=12V
120
100
80
60
40
20
0
PSRR+ Vcc=12V
PSRR+ Vcc=5V
PSRR- Vcc=5V
0.01
0.1
0.5
2 3 5 10 20
Freq (kHz)
100
1000
10000
0.01
0.1
0.5
2 3 5 10 20
Freq (kHz)
100
1000
10000
图 11. CMRR vs. Frequency
图 12. PSRR vs. Frequency
7.2
5
4.5
4
VCC=5V
VCC=12V
VCC=5V
VCC=12V
6.9
6.6
6.3
6
3.5
3
5.7
5.4
5.1
4.8
4.5
4.2
3.9
2.5
2
1.5
1
0.5
0
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140 160
TA(qC)
TA(qC)
图 13. ICC vs. Temperature
图 14. Input Bias Current vs. Temperature
0.3
0.28
0.26
0.24
0.22
0.2
4.2
VCC=5V Positive Transition
VCC=12V Positive Transition
VCC=5V Negative Transition
VCC=12V Negative Transition
CL=0pF, RL=10k:
3.9
3.6
3.3
3
CL=0pF, RL=50:
CL=200nF, RL=10k:
CL=200nF, RL=50:
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.18
0.16
0.14
0.12
0
10
20
30
40
50
60
70
80
90 100
-60 -40 -20
0
20
40
60
80 100 120 140
t(Ps)
TA(qC)
VCC = 5.0 V
VCC =5.0 V
图 15. Slew Rate
图 16. Slew Rate vs. Temperature
8
版权 © 2015, Texas Instruments Incorporated
ALM2402-Q1
www.ti.com.cn
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
Typical Characteristics (接下页)
TA= 25°C and VCC = VCC_O(X)
-20
-65
-70
-75
-80
-85
-90
RL=100:
RL=10k:
RL=100:
RL=10k:
-40
-60
-80
-100
20 30 50 70100 200
500 1000 2000 5000 1000020000
Frequency (Hz)
20 30 50 70100 200
500 1000 2000 5000 1000020000
Frequency (Hz)
Av = 2V/V
Vo = 8Vpp
Av = 1V/V
Vo = 1Vpp
图 17. THD + Noise (Vcc = 12 V)
图 18. THD + Noise (Vcc = 5 V)
0.4
0.2
0
20%
15%
10%
5%
VCC=5V
VCC=12V
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
0
2
0
2
-60 -40 -20
0
20
40
TA(qC)
60
80 100 120 140
-
0.4 0.8 1.2 1.6
2.4 2.8 3.2 3.6
-3.2 -2.8 -2.4
-1.6 -1.2 -0.8 -0.4
Offset Voltage (mV)
Vcc =12 V and 5 V
Vcm = Vcc/2
Vcm = Vcc/2
图 20. Offset Voltage Production Distribution
图 19. Input Offset vs. Temperature
80
75
70
65
60
55
50
45
40
35
30
25
20
1000
600MHz
1GHz
100MHz
300MHz
33MHz
100
20
10MHz
10
100
1000
10000
100000
-30
-25
-20
-15
-10
-5
0
5
Frequency (Hz)
RF Input Peak Voltage (dBVp)
图 21. . Input Voltage Noise Spectral Density vs. Frequency
图 22. EMIRR vs. Power
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8 Detailed Description
8.1 Overview
ALM2402Q1 is a dual power opamp with features and performance that make it preferable in many applications.
Its high voltage tolerance, low offset and drift make it optimal in sensing applications. While its current limiting
and over temperature detection make it very robust in applications that drive analog signal off of the PCB on to
wires that are susceptible to faults from the outside world.
This device is optimal for applications that require high amounts of power. Its rail to rail output, enabled by the
low Rdson PMOS and NMOS transistors keep the power dissipation low. The small 3mm x 3mm DRR package
with its thermal pad and low θJA also allows users to deliver high currents to loads.
Other key features this device offers is its separate output driver supply (for external high-side current limit
adjustability), wide stability range (with good phase margin up to 1uF) and shutdown capability (for applications
that need low Icc).
8.2 Functional Block Diagram
Vcc
10
PMOS Current
Limiting and
Biasing
+
-
1
2
OTA
EMI
11
Rejection
NMOS Current
Limiting and
Biasing
EN
EN
12
9
3
Internal
Thermal Detection
Circuitry
Vcc
8
PMOS Current
Limiting and
Biasing
+
4
5
OTA
EMI
Rejection
7
-
NMOS Current
Limiting and
Biasing
EN
6
图 23. Functional Block Diagram
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8.3 Feature Description
8.3.1 OTF/SH_DN
The OTF/SH_DN pin is a bidirectional pin that will allow the user to put both opamps in to a low Iq state
(<500µA) when forced low or below VIL_OTF. Due to this pin being bidirectional and it's Enable/Disable
functionality, it must be pulled high or above VIH_OTF through a pullup resistor in order for the opamp to function
properly or within the specs guaranteed in Electrical Characteristics.
When the junction temperature of ALM2402Q1 crosses the limits specified in Electrical Characteristics, the
OTF/SH_DN pin will go low to alert the application that the both output have turned off due to an over
temperature event. Also, the OTF pin will go low if VCC_O1 and VCC_O2 are 0 V.
When OTF/SH_DN is pulled low and the opamps are shutdown, the opamps will be in open-loop even when
there is negative feedback applied. This is due to the loss of open loop gain in the opamps when the biasing is
disabled. Please see Open Loop and Closed Loop for more detail on open and close loop considerations.
8.3.2 Supply Voltage
ALM2402Q1 uses three power rails. VCC powers the opamp signal path (OTA) and protection circuitry and
VCC_O1 and VCC_O2 power the output high side driver.. Each supply can operate at separate voltages levels
(higher or lower). The min and max values listed in Electrical Characteristics table are voltages that will enable
ALM2402Q1 to properly function at or near the specification listed in Electrical Characteristics table. The
specification listed in this table are guaranteed for 5 V and 12 V.
8.3.3 Current Limit and Short Circuit Protection
Each opamp in ALM2402Q1 has seperate internal current limiting for the PMOS (high-side) and NMOS (low-
side) output transistors. If the output is shorted to ground then the PMOS (high-side) current limit is activated and
will limit the current to 750mA nominally (see Electrical Characteristics) or to values shown in 图 6 over
temperature. If the output is shorted to supply then the NMOS (low-side) current limit is activated and will limit the
current to 550mA nominally (see Electrical Characteristics) or to values shown in 图 5 over temperature. The
current limit value decreases with increasing temperature due to the temperature coefficient of a base-emitter
junction voltage. Similarly, the current limit value increases at low temperatures.
A programmable current limit for short to ground scenarios can be achieved by adding resistance between
VCC_O(X) and the supply (or battery).
When current is limited, the safe limits for the die temperature (see Recommended Operating Conditions and
Absolute Maximum Ratings) must be taken in to account. With too much power dissipation, the die temperature
can surpass the thermal shutdown limits and the opamp will shutdown and reactivate once the die has fallen
below thermal limits. However, it is not recommended to continuously operate the device in thermal hysteresis for
long periods of time (see Absolute Maximum Ratings).
8.3.4 Input Common Mode Range and Overvoltage Clamps
ALM2402Q1's input common mode range is between 0.2V and VCC-1.2V (see Electrical Characteristics).
Staying withing this range will allow the opamps to perform and operate within the specification listed in Electrical
Characteristics. Operating beyond these limits can cause distortion and non-linearities.
In order for the inputs to tolerate high voltages in the event of a short to supply, zener diodes have been added
(see 图 24). The current into this zener is limited via internal resistors. When operating near or above the zener
voltage (7 V), the additional voltage gain error caused by the mismatch in internal resistors must be taken in to
account. In unity gain, the opamp will force both gate voltages to be equal to the zener voltage on the positive
input pin and ideally both zeners will sink the same amount of current and force the output voltage to be equal to
Vin. In reality, RN and RP and VZ between both zener diodes do not perfectly match and have some % difference
between their values. This leads to the output being Vo=Vin*(ΔR + ΔVZ) .
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Feature Description (接下页)
½
ALM2402
RN
+
RP
+
VIN
–
图 24. Schematic Including Input Clamps
8.3.5 Thermal Shutdwon
If the die temperature exceeds safe limits, all outputs will be disabled, and the OTF/SH_DN pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume. The OTF/SH_DN pin will
be released after operation has resumed.
When operating the die at a high temperature, the opamp will toggle on and off between the thermal shutdown
hysteresis. In this event the safe limits for the die temperature (see Recommended Operating Conditions and
Thermal Information) must be taken in to account. It is not recommended to continuously operate the device in
thermal hysteresis for long periods of time (see Recommended Operating Conditions).
8.3.6 Output Stage
Designed as a high voltage, high current operational amplifier, the ALM2402Q1 device delivers a robust output
drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output
swing capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails; refer to the graphs in Typical Characteristics section.
Each output transistor has internal reverse diodes between drain and source that will conduct if the output is
forced higher than the supply or lower than ground (reverse current flow). Users may choose to use these as
flyback protection in inductive load driving applications. 图 7 show I-V characteristics of both diodes. It is
recommended to limit the use of these diodes to pulsed operation to minimize junction temperature overheating
due to (VF*IF). Internal current limiting circuitry will not operate when current is flown in the reverse direction and
the reverse diodes are active.
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Feature Description (接下页)
8.3.7 EMI Susceptibility and Input Filtering
Op-amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted
EMI enters the op-amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI
is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While
all op-amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The
ALM2402Q1 device incorporates an internal input low-pass filter that reduces the amplifiers response to EMI.
Both common-mode and differential mode filtering are provided by this filter.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 990 MHz. The EMI rejection ratio (EMIRR)
metric allows op-amps to be directly compared by the EMI immunity. 图 22 shows the results of this testing on
the ALM2402Q1 device. Detailed information can also be found in the application report, EMI Rejection Ratio of
Operational Amplifiers (SBOA128), available for download from www.ti.com
8.4 Device Functional Modes
8.4.1 Open Loop and Closed Loop
Due to its very high open loop DC gain, the ALM2402Q1 will function as a comparator in open loop for most
applications. As noted in Electrical Characteristics table, the majority of electrical characteristics are verified in
negative feedback, closed loop configurations. Certain DC electrical characteristics, like offset, may have a
higher drift across temperature and lifetime when continuously operated in open loop over the lifetime of the
device.
8.4.2 Shutdown
When the OTF/SH_DN pin is left floating or is grounded, the opamp will shutdown to a low Iq state and will not
operate. The opamp outputs will go to a high impedance state. Please see OTF/SH_DN for more detailed
information on OTF/SH_DN pin.
表 1. Shutdown Truth Table
Logic State
Opamp State
Operating
High ( > VIH_OTF see Recommended Operating Conditions)
Low ( < VIL_OTF see Recommended Operating Conditions)
OTF/SH_DN
Shutdown (low Iq state)
9 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ALM2402Q1 is a dual power opamp with performance and protection features that are optimal for many
applications. As it is an opamp, there are many general design consideration that must taken into account. Below
will describe what to consider for most closed loop applications and gives a specific example of ALM2402Q1
being used in a motor drive application.
9.1.1 Capacitive Load and Stability
The ALM2402Q1 device is designed to be used in applications where driving a capacitive load is required. As
with all op-amps, specific instances can occur where the ALM2402Q1 device can become unstable. The
particular op-amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether or not an amplifier is stable in operation. An op-amp in the unity-gain (1 V/V) buffer
configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated
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Application Information (接下页)
at a higher noise gain. The capacitive load, in conjunction with the op-amp output resistance, creates a pole
within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the
capacitive loading increases. When operating in the unity-gain configuration, the ALM2402Q1 device remains
stable with a pure capacitive load up to approximately 3µF. The equivalent series resistance (ESR) of some very
large capacitors (CL greater than 1 μF) is sufficient to alter the phase characteristics in the feedback loop such
that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive
increasingly larger capacitance. This increased capability is evident when observing the overshoot response of
the amplifier at higher voltage gains.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 100mΩ to 10Ω, in series with the output (RS), as shown in
图 25. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads.
V+
RS
VOUT
+
RL
+
CL
VIN
–
图 25. Capacitive Load Drive
Below are application curves displaying the step response of the above configuration with CL = 2.2 µF, RL = 10
MΩ and RL = 100 Ω. Displaying the ALM2402Q1's good stability performance with big capacitive loads.
3.8
3.6
3.4
3.2
3
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2.8
2.6
2.4
2.2
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
t (Ps)
t (s)
图 26. Output Pulse Response (CL = 2.2 µF and RL = 10
MΩ)
图 27. Output Pulse Response (CL = 2.2 µF and RL = 100
Ω)
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9.2 Typical Application
R2
ALM2402Q1
R4
R1
Resolver
+
COSINE
Sensing
Coil
Rotor
Excitation Coil
Vbias
+
CBL
SINE
Sensing
Coil
R3
CBL
V+
V-
excite -
excite +
V+
V-
PGA410x
Resolver to Digital
Converter
图 28. ALM2402Q1 in Resolver Application
High power AC and BLDC motor drive applications need angular and position feedback in order to efficiently and
accurately drive the motor. Position feedback can be achieved by using optical encoders, hall sensors or
resolvers. Resolvers are the go to choice when environmental or longevity requirements are challenging and
extensive.
A resolver acts like a transformer with one primary coil and two secondary coils. The primary coil, or excitation
coil, is located on the rotor of the resolver. As the rotor of the resolver spins, the excitation coil induces a current
into the sine and cosine sensing coils. These coils are oriented 90 degrees from one another and produce a
vector position read by the resolver to digital converter chip.
Resolver excitation coils can have a very low DC resistance (<100 Ω), causing a need of to sink and source up
to 200 mA from the excitation driver. The ALM2402Q1 can source and sink this current while providing current
limiting and thermal shutdown protection. Incorporating these protections in a resolver design can increase the
life of the end product.
The fundamental design steps and ALM2402Q1 benefits shown in this application example can be applied to
other inductive load applications like DC and servo motors. For more information on other applications that
ALM2402Q1 offers a solution to please see (SLVA696), available for download from www.ti.com.
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Typical Application (接下页)
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
Ambient Temperature Range
Available Supply Voltages
EMC Capacitance (CL)
EXAMPLE VALUE
-40°C to 125°C
12 V, 5 V, 3.3 V
100 nF
Excitation Input Voltage Range
Excitation Frequency
2 Vrms - 7 Vrms
10 kHz
9.2.2 Detailed Design Procedure
When using ALM2402Q1 in a resolver application, determine:
•
•
•
•
•
Resolver Excitation Input Impedance or Resistance and Inductance: ZO= 50 + j188; (R = 50 Ω and L = 3 mH)
Resolver Transformation Ration (VEXC/VSINCOS): 0.5 V/V at 10 kHz
Package and θJA : DRR, 39.2°C/W
Opamp Maximum Junction Temperature: 150ºC
Opamp Bandwidth: 600 kHz
9.2.2.1 Resolver Excitation Input (Opamp Output)
Like a transformer, a resolver needs an alternating current input to function properly. The resolver takes this
alternating current from the primary coil (excitation input) and creates a multiple of it on the secondary sides
(SIN, COS ports). When determining how to generate this alternating current it is important to understand an
opamp's ability or limitations. For the excitation input, the resolver input impedance, stability RMS voltage and
desired frequency must be taken in to account:
9.2.2.1.1 Excitation Voltage
For this example, the resolver impedance is specified between 2Vrms and 7Vrms up 20kHz maximum frequency.
Since, the resolver attenuation is ~0.5V/V and most data acquisition microelectronics run off of 5V supply
voltages. An excitation input of 6Vpp (or 2.12Vrms) will be chosen to give the output readout circuitry enough
headroom to measure the secondary side outputs (~3Vpp).
The excitation coil can be driven by a single-ended opamp output with the other side of the coil grounded or
differentially as shown in 图 28. Differential drive offers higher peak to peak voltage (double) on to the excitation
coil, while not using up as much output voltage headroom from the opamp. Leading to lower distortion on the
output signal.
Another consideration for excitation is opamp power dissipation. As described in Power Dissipation and Thermal
Reliability, power dissipation from the opamp can be lowered by driving the output peak voltages close to the
supply and ground voltages. With ALM2402Q1's very low VOH/VOL, this can be easily accomplished. Please see
图 1 for VOH/VOL values with respect to output current and Output Stage for further description of the rail-rail
output stage.
9.2.2.1.2 Excitation Frequency
The excitation frequency is chosen based on the desired secondary side output signal resolution. As shown in
图 34, the excitation signal is similar to a sampling pulse in ADCs, with the real information being in the envelope
created by the rotor. With a GBW of 600kHz, ALM2402Q1 has more than enough open loop gain at 10kHz to
create negligible closed loop gain error.
Along with GBW, ALM2402Q1 has optimal THD and SR performance (see Typical Characteristics) to achieve
6Vpp (or 3Vpp from each opamp). The signal integrity can also be observed in the Typical Characteristics
section.
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9.2.2.1.3 Excitation Impedance
Knowledge of the primary side impedance is very important when chosing an opamp for this application. As
shown below in 图 29, the excitation coil looks like an inductance in series with a resistance. Many time these
values aren't given and must by calculated from the cartesian or polar form, as it is given as a function of
frequency or phase angle. This calculation is a trivial task.
Once the coil resistance is determined, the maximum or peak-peak current needed from ALM2402Q1 can be
determined by below:
VPP
IOUT =
REXC
(1)
In this example the peak-peak output current equates to ~120mA. Each opamp will handle the peak current, with
one sinking max and the other sourcing. Knowledge of the opamp current is very important when determining
ALM2402Q1's power dissipation. Which is discussed in the Power Dissipation and Thermal Reliability section.
R2
CEMC
Excitation Coil
Model
R1
+
LEXC
RCRS
CCRS
ALM2402Q1
Vbias
RL
+
R3
CEMC
R4
图 29. Excitation Coil Implementation
The primary side of a resolver is inductive, but that typically is not all the opamps driving the coils see. As shown
in , many times designers will add a resistor in series with a capacitor to illiminate crossover distortion. Which
happens due to the biasing of BJTs in the discrete implementation. With ALM2402Q1's rail-rail output, this is
rarely needed. This can be seen in the waveforms shown in the section.
It is also common practice to add EMC capacitors to the opamp outputs to help shield other devices on the PCB
from the radiation created by the motor and resolver. When choosing CEMC, it ismportant to take the opamp's
stability in to account. With ALM2402Q1 having bery good phase margin at and above 200nF, no stability issues
will be present for many typical CEMC values.
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9.2.2.2 Resolver Output
As mentioned in the Excitation Frequency section, the excitation signal is similar to a sampling pulse in ADCs,
with the real information being in the envelope created by the rotor. The equations below show the behavior of
the sin and cos outputs. Whereby the excitation signal is attenuated and enveloped by the voltage created from
the electromagnetic response of the rotating rotor. The resolver analog output to digital converter will filter out the
excitation signal and process the sine and cosine angles produced by the rotor. Hince, signal intergity or the sine
and cosine envelope is most important in resolver design and some trade-offs in signal integrity of the excitation
signal can be made for cost or convenience. Many times users can use a square wave or sawtooth signal to
accomplish excitation, as opposed to a sine wave.
VEXC = V ´ sin 2πft
( )
PP
(2)
VSIN = T ´ V ´ sin 2πft ´ sin(θ)
( )
R
PP
(3)
(4)
VCOS = T ´ V ´ sin 2πft ´cos(θ)
( )
R
PP
9.2.2.3 Power Dissipation and Thermal Reliability
Very critical aspects to many industrial and automotive applications are operating temperature and power
dissipation. Resolvers are typically chosen over other position feedback techniques due to their sustainability and
accuracy in harsh conditions and very high temperatures.
Along with the resolver, the electronics used in this system must be able to withstand these conditions.
ALM2402Q1 is Q100 qualified and is able to operate at temperatures up to 125°C. In order to insure that this
device can withstand these temperatures, the internal power dissipation must be determined.
The total power dissipation from ALM2402Q1 in this application is the sum of the power from the input supply
and output supplies.
Input
Supply
Power
Output
Supply
Power
Load
Power
P = P + P - P
L
(
)
D
SS
SSO
(5)
As shown in the equation below. PSS is a function of the internal supply and operating current of both opamps
(ICC). With this opamp being CMOS, the ICC will not increase proportionally to the load like a BJT based design.
It will stay close to the average value listed in Electrical Characteristics.
P = V ´I + V - VOUT (RMS) ´IOUT (RMS)
CCO(X)
(
)
D
CC
CC
For more information on this and calculating and measuring power dissipation with complex loads, please refer
to (SBOA022), available for download from www.ti.com (6)
æ
3 V ö 60 mA
P = 12 V ´ 5 mA + 12 V -
´
= 480 mW
ç
÷
D
2
2
è
ø
(7)
As shown in图 30, the load current will flow out of one opamp, through the load and in to the other. Each opamp
shares the same load at 180° phase difference. The PMOS and NMOS output transistors are resistive when
driven near supply and ground. Operating the output voltage at a high percentage of the supply voltage will
greatly limit the chip power dissipation. The Typical Characteristics section gives more information on the
expected voltage drop, that can be used to determine the limits of VOUT
.
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Vcco1
Vcc
10
IL*sin(ωt+180° )
PMOS Current
Limiting and
Biasing
1
2
+
-
VO1
EMI
Rejection
OTA
11
NMOS Current
Limiting and
Biasing
EN
EN
12
9
3
Internal
Thermal Detection
Circuitry
Vcco2
IL*sin(ωt)
Vcc
8
PMOS Current
Limiting and
Biasing
4
5
+
-
EMI
Rejection
OTA
7
VO2
NMOS Current
Limiting and
Biasing
EN
6
图 30. ALM2402Q1 Current Flow
After the total power dissipation is determined, the junction temperature at the worst expected ampient
temperature case must be determined. This can be determined by 公式 9 below or from 图 31.
T
= PD ´ θ +TA(MAX )
)
JA
J MAX
(
(8)
°C
W
T
= 480 mW ´ 39.2
)
+125°C = 143.8°C
J MAX
(
Where:
TJ(MAX) is the target maximum junction temperature. → 150°C
TA is the operating ambient temperature. → 125°C
θJA is the package junction to ambient thermal resistance. → 39.2°C/W
(9)
For this example, the maximum junction temperature equates to ~144ºC which is in the safe operating region,
below the maximum junction temperature of 150°C. It is required to limit ALM2402Q1's die junction temperature
to less than 150°C. Please see Absolute Maximum Ratings table for further detail.
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
-40
-20
0
20
40
60
80
100 120 140
TA(qC)
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any
allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect
reliability.
图 31. Maximum Power Dissipation vs Temperature (DRR)
9.2.2.3.1 Improving Package Thermal Performance
θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan,
can help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
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9.2.3 Application Curves
Below is test data with ALM2402Q1 exciting TE Connectivity (V23401-D1001-B102) Hollow Shaft Resolver.
表 3. Waveform Legend
Waveform Color
Green
Description
SINE output
Blue
COSINE output
Red
Excitation positive terminal inputs (referenced to ground)
Excitation negative terminal inputs (referenced to ground)
Purple
The peak-peak excitation voltage is the difference between the
green and blue voltages
The peak-peak excitation voltage is the difference between the
green and blue voltages
图 33. Resolver Excitation VEXC≈6Vpp at 10 kHz (ZOOM)
图 32. Resolver Excitation VEXC ≈ 6 Vpp 10 kHz
The peak-peak excitation voltage is the difference between the green and blue voltages
图 34. Resolver Excitation VEXC≈4Vpp at 20 kHz
10 Power Supply Recommendations
The ALM2402Q1 device is recommended for continuous operation from 4.5V to 16V (±2.25V to ±8.0V) for Vcc
and 3.0V to 16V (±1.5V to ±8.0V) for Vcc_o(x); many specifications apply from –40°C to 125°C. The Typical
Characteristics presents parameters that can exhibit significant variance with regard to operating voltage or
temperature.
CAUTION
Supply voltages larger than 18V can permanently damage the device (see Absolute
maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
•
•
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
11.2 Layout Example
This layout does not verify optimum thermal impedance performance. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
图 35. ALM2402Q1 Layout Example
版权 © 2015, Texas Instruments Incorporated
21
ALM2402-Q1
ZHCSDN3B –FEBRUARY 2015–REVISED MAY 2015
www.ti.com.cn
12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ALM2402QDRRRQ1
ALM2402QPWPRQ1
ACTIVE
ACTIVE
WSON
DRR
PWP
12
14
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 125
-40 to 125
ALM24Q
ALM24Q
HTSSOP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ALM2402QDRRRQ1
ALM2402QPWPRQ1
WSON
DRR
12
14
3000
2000
330.0
330.0
12.4
12.4
3.3
6.9
3.3
5.6
1.1
1.6
8.0
8.0
12.0
12.0
Q2
Q1
HTSSOP PWP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ALM2402QDRRRQ1
ALM2402QPWPRQ1
WSON
DRR
PWP
12
14
3000
2000
346.0
350.0
346.0
350.0
33.0
43.0
HTSSOP
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 14
4.4 x 5.0, 0.65 mm pitch
PowerPAD TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224995/A
www.ti.com
PACKAGE OUTLINE
PWP0014H
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
12X 0.65
14
1
2X
5.1
4.9
3.9
NOTE 3
7
8
0.30
14X
0.19
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
4X (0.28)
NOTE 5
4X (0.1)
NOTE 5
8
7
THERMAL
PAD
0.25
GAGE PLANE
2.86
2.02
15
1.2 MAX
0.15
0.05
0 - 8
14
1
0.75
0.50
DETAIL A
(1)
TYPICAL
1.82
0.98
4224353/A 07/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ and may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0014H
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.82)
SYMM
SEE DETAILS
14X (1.5)
1
14
14X (0.45)
(1.1)
TYP
15
SYMM
(2.86)
(5)
NOTE 9
12X (0.65)
8
7
(
0.2) TYP
VIA
(R0.05) TYP
(1.1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-14
/A 07/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0014H
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(1.82)
BASED ON
0.125 THICK
STENCIL
14X (1.5)
(R0.05) TYP
1
14
14X (0.45)
15
(2.86)
SYMM
BASED ON
0.125 THICK
STENCIL
12X (0.65)
8
7
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
SYMM
(5.8)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.03 X 3.20
1.86 X 2.86 (SHOWN)
1.66 X 2.61
0.125
0.15
0.175
1.54 X 2.42
4224353/A 07/2018
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRR0012A
WSON - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
EXPOSED
THERMAL PAD
1.7±0.1
(0.2) TYP
8X 0.5
6
7
2X
2.5±0.1
2.5
1
12
0.3
0.2
12X
PIN 1 ID
(OPTIONAL)
0.4
0.2
12X
0.1
C A
B
0.05
4221617/A 09/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRR0012A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.7)
12X (0.5)
SYMM
1
12
12X (0.25)
SYMM
(2.5)
(1)
10X (0.5)
6
7
(0.6)
(
0.2) VIA
TYP
(2.9)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221617/A 09/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRR0012A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.55)
METAL
TYP
12X (0.5)
1
12
12X (0.25)
(1.11)
SYMM
(0.66)
10X (0.5)
7
6
SYMM
(2.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4221617/A 09/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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