AM1806EZCED4 [TI]
Sitara 处理器：Arm9，LPDDR，DDR2，显示 | ZCE | 361 | -40 to 90;
| 型号： | AM1806EZCED4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sitara 处理器：Arm9，LPDDR，DDR2，显示 | ZCE | 361 | -40 to 90 时钟 双倍数据速率 光电二极管 外围集成电路 |
| 文件： | 总241页 (文件大小：1437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AM1806
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SPRS658B–FEBRUARY 2010–REVISED MAY 2010
AM1806 ARM Microprocessor
Check for Samples: AM1806
1 AM1806 ARM Microprocessor
1.1 Features
12
– With Modem Control Signals
• Highlights
– 16-byte FIFO
– 16x or 13x Oversampling Option
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– One Multichannel Audio Serial Port
– Two Independent Programmable Realtime
Unit (PRU) Cores
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
– TwoEnhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• 375/456-MHz ARM926EJ-S™ RISC MPU
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
•
Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– 2 Channel Controllers
– 3 Transfer Controllers
– Standard power management mechanism
– 64 Independent DMA Channels
– 16 Quick DMA Channels
– Programmable Transfer Burst Size
•
•
Clock gating
Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
• Two External Memory Interfaces:
– EMIFA
•
•
•
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
16-Bit SDRAM With 128 MB Address
Space
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
– DDR2/Mobile DDR Memory Controller
• One Multichannel Audio Serial Port:
– Transmit/Receive Clocks
•
16-Bit DDR2 SDRAM With 512 MB
Address Space or
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
•
16-Bit mDDR SDRAM With 256 MB
Address Space
• Three Configurable 16550 type UART Modules:
– FIFO buffers for Transmit and Receive
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
ARM926EJ-S is a trademark of ARM Limited.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2010, Texas Instruments Incorporated
AM1806
SPRS658B–FEBRUARY 2010–REVISED MAY 2010
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• Two Multichannel Buffered Serial Ports:
– Transmit/Receive Clocks
• One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
• Two Enhanced Pulse Width Modulators
(eHRPWM):
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-channel TDM
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
– FIFO buffers for Transmit and Receive
• Video Port Interface (VPIF):
– Two 8-bit SD (BT.656), Single 16-bit or Single
Raw (8-/10-/12-bit) Video Capture Channels
– Two 8-bit SD (BT.656), Single 16-bit Video
Display Channels
• Three 32-Bit Enhanced Capture Modules
(eCAP):
• Universal Parallel Port (uPP):
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
– High-Speed Parallel Interface to FPGAs and
Data Converters
– Data Width on Each of Two Channels is 8- to
16-bit Inclusive
– Single Data Rate or Dual Data Rate Transfers
– Supports Multiple Interfaces with START,
ENABLE and WAIT Controls
• 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZCE Suffix], 0.65-mm Ball Pitch
• Commercial or Extended Temperature
• Community Resources
• Real-Time Clock With 32 KHz Oscillator and
Separate Power Rail
• Three One 64-Bit General-Purpose Timers
(Configurable as Two 32-Bit Timers)
– TI E2E Community
– TI Embedded Processors Wiki
2
AM1806 ARM Microprocessor
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1.2 Trademarks
All trademarks are the property of their respective owners.
Copyright © 2010, Texas Instruments Incorporated
AM1806 ARM Microprocessor
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1.3 Description
The device is a Low-power applications processor based on ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C) Bus interfaces;
one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel
buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit
general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port
interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with
RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit
enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary
pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM
external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile
DDR controller.
The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters,
FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on
each of two channels. Single-date rate and double-data rate transfers are supported as well as START,
ENABLE and WAIT signals to provide control for a variety of data converters.
A Video Port Interface (VPIF) is included providing a flexible video input/output port.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM . These include C compilers, and
scheduling, and a Windows™ debugger interface for visibility into source code execution.
4
AM1806 ARM Microprocessor
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1.4 Functional Block Diagram
ARM Subsystem
JTAG Interface
System Control
ARM926EJ-S CPU
With MMU
PLL/Clock
Generator
w/OSC
Input
Clock(s)
4KB ETB
General-
Purpose
Timer (x3)
16KB
I-Cache
16KB
D-Cache
Power/Sleep
Controller
8KB RAM
(Vector Table)
RTC/
32-kHz
OSC
Pin
Multiplexing
64KB ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interfaces
Display
Video
Parallel Port Internal Memory Customizable Interface
2
SPI
I C
UART
(x3)
EDMA3
(x2)
128KB
RAM
PRU Subsystem
McASP
w/FIFO
LCD
Ctlr
McBSP
(x2)
uPP
VPIF
(x2)
(x2)
Control Timers
Connectivity
HPI
External Memory Interfaces
MMC/SD
(8b)
(x2)
USB2.0
OTG Ctlr
PHY
EMIFA(8b/16B)
DDR2/MDDR
NAND/Flash
Controller
ePWM eCAP
(x2)
(x3)
16b SDRAM
(1) Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
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AM1806 ARM Microprocessor
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1
AM1806 ARM Microprocessor ........................ 1
1.1 Features .............................................. 1
1.2 Trademarks .......................................... 3
1.3 Description ........................................... 4
1.4 Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Overview ........................................ 8
3.1 Device Characteristics ............................... 8
3.2 Device Compatibility ................................. 9
3.3 ARM Subsystem ..................................... 9
3.4 Memory Map Summary ............................. 12
3.5 Pin Assignments .................................... 15
3.6 Pin Multiplexing Control ............................ 18
3.7 Terminal Functions ................................. 19
Device Configuration ................................. 56
4.1 Boot Modes ......................................... 56
4.2 SYSCFG Module ................................... 56
6.7 Interrupts ............................................ 75
6.8 Power and Sleep Controller (PSC) ................. 81
6.9 EDMA ............................................... 86
6.10 External Memory Interface A (EMIFA) ............. 92
6.11 DDR2/mDDR Controller ........................... 102
6.12 Memory Protection Units .......................... 115
6.13 MMC / SD / SDIO (MMCSD0, MMCSD1) ......... 118
6.14 Multichannel Audio Serial Port (McASP) .......... 121
6.15 Multichannel Buffered Serial Port (McBSP) ....... 130
6.16 Serial Peripheral Interface Ports (SPI0, SPI1) .... 140
6.17 Inter-Integrated Circuit Serial Ports (I2C) ......... 163
6.18 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 167
6.19 Universal Serial Bus OTG Controller (USB0)
[USB2.0 OTG] ..................................... 169
6.20 LCD Controller (LCDC) ............................ 176
6.21 Host-Port Interface (UHPI) ........................ 191
6.22 Universal Parallel Port (uPP) ...................... 199
6.23 Video Port Interface (VPIF) ....................... 204
6.24 Enhanced Capture (eCAP) Peripheral ............ 210
6.25 Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM) ........................................ 213
6.26 Timers ............................................. 218
6.27 Real Time Clock (RTC) ........................... 220
6.28 General-Purpose Input/Output (GPIO) ............ 223
6.29 Programmable Real-Time Unit Subsystem (PRUSS)
..................................................... 227
2
3
4
5
4.3 Pullup/Pulldown Resistors .......................... 59
Device Operating Conditions ....................... 60
5.1
Absolute Maximum Ratings Over Operating
Junction Temperature Range
(Unless Otherwise Noted) ................................. 60
5.2 Recommended Operating Conditions .............. 61
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Junction
6.30 Emulation Logic ................................... 230
Device and Documentation Support ............. 236
Temperature (Unless Otherwise Noted) ............ 63
Peripheral Information and Electrical
7
8
6
Specifications .......................................... 64
7.1 Device Support .................................... 236
7.2 Documentation Support ........................... 236
6.1 Parameter Information .............................. 64
6.2
Recommended Clock and Control Signal Transition
Mechanical Packaging and Orderable
Behavior ............................................ 65
6.3 Power Supplies ..................................... 65
6.4 Reset ............................................... 66
Information ............................................ 237
8.1
Device and Development-Support Tool
Nomenclature ..................................... 237
8.2 Thermal Data for ZCE Package ................... 238
8.3 Thermal Data for ZWT Package .................. 239
6.5
Crystal Oscillator or External Clock Input .......... 69
6.6 Clock PLLs ......................................... 70
6
Contents
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2 Revision History
This data manual revision history highlights the changes made to the SPRS658A device-specific data
manual to make it an SPRS658B revision.
Table 2-1. Revision History
ADDITIONS/MODIFICATIONS/DELETIONS
Deleted "10/100 Mb/s Ethernet MAC (EMAC)" from "Highlights" in Section 1.1
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3 Device Overview
3.1 Device Characteristics
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provides an overview of the device. The table shows significant features of the device, including the
capacity of on-chip RAM, peripherals, and the package type with pin count.
Table 3-1. Characteristics of the device
HARDWARE FEATURES
DDR2/mDDR Controller
AM1806
DDR2, 16-bit bus width, up to 150 MHz
Mobile DDR, 16-bit bus width, up to 133 MHz
Asynchronous (8/16-bit bus width) RAM, Flash,
16-bit SDRAM, NOR, NAND
EMIFA
Flash Card Interface
EDMA3
MMC and SD cards supported.
64 independent channels, 16 QDMA channels,
2 channel controllers, 3 transfer controllers
4 64-Bit General Purpose (configurable as 2 separate 32-bit
timers, 1 configurable as Watch Dog)
Timers
UART
3 (each with RTS and CTS flow control)
2 (Each with one hardware chip select)
2 (both Master/Slave)
SPI
I2C
Multichannel Audio Serial Port [McASP]
Multichannel Buffered Serial Port [McBSP]
1 (each with transmit/receive, FIFO buffer, 16 serializers)
2 (each with transmit/receive, FIFO buffer, 16)
Peripherals
4 Single Edge, 4 Dual Edge Symmetric, or
2 Dual Edge Asymmetric Outputs
eHRPWM
Not all peripherals pins
are available at the
USB 2.0 (USB0)
High-Speed OTG Controller with on-chip OTG PHY
same time (for more
detail, see the Device
Configurations section).
General-Purpose Input/Output Port
LCD Controller
9 banks of 16-bit
1
Universal Parallel Port (uPP)
Video Port Interface (VPIF)
PRU Subsystem (PRUSS)
Size (Bytes)
1
1 (video in and video out)
2 Programmable PRU Cores
168KB RAM, 1088KB Boot ROM
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
On-Chip Memory
Organization
ADDITIONAL MEMORY
128KB RAM
C674x CPU ID + CPU
Rev ID
Control Status Register (CSR.[31:16])
Revision ID Register (MM_REVID[15:0])
0x1400
0x0000
C674x Megamodule
Revision
JTAG BSDL_ID
CPU Frequency
DEVIDR0 Register
MHz
0x0B7D_102F
ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
1.2 V nominal for 375 MHz verion
1.3 V nominal for 456 MHz verion
Core (V)
I/O (V)
Voltage
1.8V or 3.3 V
13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE)
16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)
Packages
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(1)
AI
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
8
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3.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
3.3 ARM Subsystem
The ARM Subsystem includes the following features:
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian
System Control Co-Processor 15 (CP15)
MMU
16KB Instruction cache
16KB Data cache
Write Buffer
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt controller
3.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data caches
Write buffer
Separate instruction and data (internal RAM) interfaces
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
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3.3.3 MMU
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
3.3.4 Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.3.5 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the AM1808 also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
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•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The AM1808 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
3.3.7 ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, including EMIFA, DDR2, and the
additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the
ARM by default.
See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.
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3.4 Memory Map Summary
Table 3-2. AM1808 Top Level Memory Map
Start Address
0x0000 0000
0x0000 1000
End Address
0x0000 0FFF
0x01BB FFFF
Size
4K
ARM Mem Map
EDMA Mem Map PRUSS Mem
Map
Master
Peripheral Mem
Mem Map Map
LCDC
PRUSS Local
Address
Space
0x01BC 0000 0x01BC 0FFF
4K
ARM ETB
memory
0x01BC 1000
0x01BC 1800
0x01BC 17FF
0x01BC 18FF
2K
ARM ETB reg
256
ARM Ice
Crusher
0x01BC 1900
0x01C0 0000
0x01C0 8000
0x01C0 8400
0x01C0 8800
0x01C1 0000
0x01C1 1000
0x01C1 2000
0x01C1 4000
0x01C1 5000
0x01C2 0000
0x01C2 1000
0x01C2 2000
0x01C2 3000
0x01C2 4000
0x01C4 0000
0x01C4 1000
0x01C4 2000
0x01C4 3000
0x01D0 0000
0x01D0 1000
0x01D0 2000
0x01D0 3000
0x01BF FFFF
0x01C0 7FFF
0x01C0 83FF
0x01C0 87FF
0x01C0 FFFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 3FFF
0x01C1 4FFF
0x01C1 FFFF
0x01C2 0FFF
0x01C2 1FFF
0x01C2 2FFF
0x01C2 3FFF
0x01C3 FFFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 2FFF
0x01CF FFFF
0x01D0 0FFF
0x01D0 1FFF
0x01D0 2FFF
0x01D0 BFFF
32K
1K
EDMA3 CC
EDMA3 TC0
EDMA3 TC1
1K
4K
4K
PSC 0
PLL Controller 0
4K
SYSCFG0
4K
4K
4K
4K
Timer0
Timer1
I2C 0
RTC
4K
4K
4K
MMC/SD 0
SPI 0
UART 0
4K
4K
4K
McASP 0 Control
McASP 0 AFIFO Ctrl
McASP 0 Data
0x01D0 C000 0x01D0 CFFF
0x01D0 D000 0x01D0 DFFF
4K
4K
UART 1
UART 2
0x01D0 E000
0x01D1 0000
0x01D1 0800
0x01D1 1000
0x01D1 1800
0x01D1 2000
0x01E0 0000
0x01E1 0000
0x01E1 1000
0x01E1 3000
0x01E1 4000
0x01D0 FFFF
0x01D1 07FF
0x01D1 0FFF
0x01D1 17FF
0x01D1 1FFF
0x01DF FFFF
0x01E0 FFFF
0x01E1 0FFF
0x01E1 2FFF
0x01E1 3FFF
0x01E1 4FFF
2K
2K
2K
2K
McBSP0
McBSP0 FIFO Ctrl
McBSP1
McBSP1 FIFO Ctrl
64K
4K
USB0
UHPI
4K
4K
LCD Controller
Memory Protection Unit 1 (MPU 1)
12
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Table 3-2. AM1808 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem Map
EDMA Mem Map PRUSS Mem
Map
Master
Peripheral Mem
LCDC
Mem Map
Map
0x01E1 5000
0x01E1 6000
0x01E1 7000
0x01E1 8000
0x01E1 A000
0x01E1 B000
0x01E1 C000
0x01E2 0000
0x01E2 2000
0x01E2 3000
0x01E2 4000
0x01E2 5000
0x01E2 6000
0x01E2 7000
0x01E2 8000
0x01E2 9000
0x01E1 5FFF
0x01E1 6FFF
0x01E1 7FFF
0x01E1 9FFF
0x01E1 AFFF
0x01E1 BFFF
0x01E1 FFFF
0x01E2 1FFF
0x01E2 2FFF
0x01E2 3FFF
0x01E2 4FFF
0x01E2 5FFF
0x01E2 6FFF
0x01E2 7FFF
0x01E2 8FFF
0x01E2 BFFF
4K
4K
4K
Memory Protection Unit 2 (MPU 2)
UPP
VPIF
4K
4K
PLL Controller 1
MMCSD1
4K
4K
4K
GPIO
PSC 1
I2C 1
0x01E2 C000 0x01E2 CFFF
4K
SYSCFG1
0x01E2 D000
0x01E3 0000
0x01E3 8000
0x01E3 8400
0x01F0 0000
0x01F0 1000
0x01F0 2000
0x01F0 3000
0x01F0 4000
0x01F0 6000
0x01F0 7000
0x01F0 8000
0x01F0 9000
0x01F0 C000
0x01F0 D000
0x01F0 E000
0x01F0 F000
0x01F1 0000
0x01F1 1000
0x01F1 2000
0x4000 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x6800 8000
0x8000 0000
0x8002 0000
0x01E2 FFFF
0x01E3 7FFF
0x01E3 83FF
0x01EF FFFF
0x01F0 0FFF
0x01F0 1FFF
0x01F0 2FFF
0x01F0 3FFF
0x01F0 5FFF
0x01F0 6FFF
0x01F0 7FFF
0x01F0 8FFF
0x01F0 BFFF
0x01F0 CFFF
0x01F0 DFFF
0x01F0 EFFF
0x01F0 FFFF
0x01F1 0FFF
0x01F1 1FFF
0x3FFF FFFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6800 7FFF
0x7FFF FFFF
0x8001 FFFF
0xAFFF FFFF
32K
1K
EDMA3 CC1
EDMA3 TC2
4K
4K
4K
4K
eHRPWM 0
HRPWM 0
eHRPWM 1
HRPWM 1
4K
4K
4K
ECAP 0
ECAP 1
ECAP 2
4K
4K
4K
Timer2
Timer3
SPI1
4K
4K
McBSP0 FIFO Data
McBSP1 FIFO Data
512M
32M
32M
32M
32M
32K
EMIFA SDRAM data (CS0)
EMIFA async data (CS2)
EMIFA async data (CS3)
EMIFA async data (CS4)
EMIFA async data (CS5)
EMIFA Control Regs
128K
On-chip RAM
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Table 3-2. AM1808 Top Level Memory Map (continued)
Start Address
End Address
Size
ARM Mem Map
EDMA Mem Map PRUSS Mem
Map
Master
Peripheral Mem
Mem Map Map
LCDC
0xB000 0000
0xB000 8000
0xB000 7FFF
0xBFFF FFFF
32K
512M
64K
DDR2 Control Regs
DDR2 Data
0xC000 0000 0xDFFF FFFF
0xE000 0000 0xFFFC FFFF
0xFFFD 0000 0xFFFD FFFF
ARM local
ROM
0xFFFE 0000 0xFFFE DFFF
0xFFFE E000 0xFFFE FFFF
8K
8K
ARM Interrupt
Controller
0xFFFF 0000
0xFFFF 2000
0xFFFF 1FFF
0xFFFF FFFF
ARM local
RAM
ARM Local
RAM (PRU0
only)
14
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3.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1 Pin Map (Bottom View)
The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four
quadrants (A, B, C, and D). The pin assignments for both packages are identical.
1
2
3
4
5
6
7
8
9
10
VP_DOUT[0]/
LCD_D[0]/
UPP_XD[8]/
GP7[8]/
PRU1_R31[8]
VP_DOUT[2]/
LCD_D[2]/
UPP_XD[10]/
GP7[10]/
PRU1_R31[10]
VP_DOUT[1]/
LCD_D[1]/
UPP_XD[9]/
GP7[9]/
PRU1_R31[9]
DDR_A[10]
DDR_A[6]
DDR_A[2]
DDR_CLKN
DDR_CLKP
DDR_D[15]
DDR_RAS
W
V
U
T
W
V
U
T
VP_DOUT[3]/
LCD_D[3]/
UPP_XD[11]/
GP7[11]/
PRU1_R31[11]
VP_DOUT[4]/
LCD_D[4]/
UPP_XD[12]/
GP7[12]/
PRU1_R31[12]
VP_DOUT[5]/
LCD_D[5]/
UPP_XD[13]/
GP7[13]/
PRU1_R31[13]
DDR_A[3]
DDR_CKE
DDR_BA[0]
DDR_D[13]
DDR_A[12]
DDR_A[5]
DDR_CS
VP_DOUT[8]/
LCD_D[8]/
UPP_XD[0]/
GP7[0]/
VP_DOUT[6]/
LCD_D[6]/
UPP_XD[14]/
GP7[14]/
PRU1_R31[14]
VP_DOUT[7]/
LCD_D[7]/
UPP_XD[15]/
GP7[15]/
PRU1_R31[15]
DDR_A[8]
DDR_A[4]
DDR_A[7]
DDR_A[0]
DDR_BA[2]
DDR_CAS
DDR_D[12]
BOOT[0]
VP_DOUT[9]/
LCD_D[9]/
UPP_XD[1]/
GP7[1]/
VP_DOUT[10]/
LCD_D[10]/
UPP_XD[2]/
GP7[2]/
VP_DOUT[11]/
LCD_D[11]/
UPP_XD[3]/
GP7[3]/
DDR_A[11]
DDR_A[13]
DDR_A[9]
DDR_A[1]
DDR_BA[1]
DDR_D[10]
DDR_WE
BOOT[1]
BOOT[2]
BOOT[3]
VP_DOUT[12]/
LCD_D[12]/
UPP_XD[4]/
GP7[4]/
VP_DOUT[13]/
LCD_D[13]/
UPP_XD[5]/
GP7[5]/
VP_DOUT[14]/
LCD_D[14]/
UPP_XD[6]/
GP7[6]/
LCD_AC_ENB_CS/
GP6[0]/
PRU1_R31[28]
DVDD3318_C
DDR_VREF
DVDD3318_C
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DVDD18
DDR_DQM[1]
DDR_DVDD18
DDR_DVDD18
R
P
N
M
L
R
P
N
M
L
BOOT[4]
BOOT[5]
BOOT[6]
VP_DOUT[15]/
LCD_D[15]/
UPP_XD[7]/
GP7[7]/
NC
NC
NC
NC
NC
NC
DVDD3318_C
DDR_DVDD18
DDR_DVDD18
BOOT[7]
NC
NC
V
RV
DD
CV
DD
NC
SS
NC
V
V
V
V
V
V
CV
CV
DD
SS
SS
SS
SS
DD
SS
SS
DV
NC
V
V
DV
V
V
V
V
DD3318_C
SS
DD18
SS
SS
SS
SS
SS
VP_CLKOUT2/
MMCSD1_DAT[2]/
PRU1_R30[2]/
GP6[3]/
VP_CLKOUT3/
PRU1_R30[0]/
GP6[1]/
V
V
DV
V
V
V
V
SS
K
DD18
SS
SS
SS
K
SS
SS
CV
DD
PRU1_R31[1]
PRU1_R31[3]
1
2
3
4
5
6
7
8
9
10
Figure 3-1. Pin Map (Quad A)
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11
12
13
14
15
16
17
18
19
VP_CLKIN0/
UHPI_HCS/
PRU1_R30[10]/
GP6[7]/
VP_DIN[4]/
UHPI_HD[12]/
UPP_D[12]/
VP_DIN[2]/
UHPI_HD[10]/
UPP_D[10]/
VP_DIN[1]/
UHPI_HD[9]/
UPP_D[9]/
VP_DIN[0]/
PRU0_R30[28]/
UHPI_HCNTL1/
UPP_CHA_START/
GP6[10]
UHPI_HD[8]/
UPP_D[8]/
PRU1_R31[29]
DDR_DQM[0]
W
V
U
T
W
V
U
T
DDR_D[7]
DDR_D[6]
PRU0_R31[26]
PRU0_R31[24]
PRU0_R31[23]
UPP_2xTXCLK
VP_DIN[6]/
UHPI_HD[14]/
UPP_D[14]/
VP_DIN[3]/
UHPI_HD[11]/
UPP_D[11]/
VP_DIN[15]_
VSYNC/
UHPI_HD[7]/
UPP_D[7]/
PRU0_R30[15]/
PRU0_R31[15]
VP_DIN[14]_
HSYNC/
UHPI_HD[6]/
UPP_D[6]/
PRU0_R30[14]/
PRU0_R31[14]
VP_CLKIN1/
UHPI_HDS1/
PRU1_R30[9]/
GP6[6]/
DDR_DQS[1]
DDR_D[5]
DDR_D[2]
DDR_D[4]
PRU0_R31[28]
PRU0_R31[25]
PRU1_R31[16]
VP_DIN[7]/
UHPI_HD[15]/
UPP_D[15]/
VP_DIN[13]_
FIELD/
UHPI_HD[5]/
UPP_D[5]/
PRU0_R30[13]/
PRU0_R31[13]
PRU0_R30[27]/ PRU0_R30[29]/
UHPI_HHWIL/ UHPI_HCNTL0/
UPP_CHA_ENABLE/ UPP_CHA_CLOCK/
DDR_D[14]
DDR_ZP
DDR_D[3]
DDR_D[1]
DDR_D[0]
PRU0_R31[29]
GP6[9]
GP6[11]
VP_DIN[12]/
UHPI_HD[4]/
UPP_D[4]/
PRU0_R30[12]/
PRU0_R31[12]
CLKOUT/
UHPI_HDS2/
PRU1_R30[13]/
GP6[14]
PRU0_R30[26]/
UHPI_HRW/
UPP_CHA_WAIT/
GP6[8]/
PRU1_R31[17]
RESETOUT/
UHPI_HAS/
PRU1_R30[14]/
GP6[15]
DDR_D[9]
DDR_D[11]
DDR_D[8]
DDR_DQS[0]
RSV2
VP_DIN[5]/
UHPI_HD[13]/
UPP_D[13]/
VP_DIN[9]/
UHPI_HD[1]/
UPP_D[1]/
PRU0_R30[9]/
PRU0_R31[9]
VP_DIN[11]/
UHPI_HD[3]/
UPP_D[3]/
PRU0_R30[11]/
PRU0_R31[11]
VP_DIN[10]/
UHPI_HD[2]/
UPP_D[2]/
PRU0_R30[10]/
PRU0_R31[10]
PRU0_R30[30] /
UHPI_HINT/
PRU1_R30[11]/
GP6[12]
PRU0_R30[31]/
UHPI_HRDY/
PRU1_R30[12]
GP6[13]
DDR_DQGATE0
DDR_DQGATE1
DVDD18
R
P
N
M
L
R
P
N
M
L
PRU0_R31[27]
VP_DIN[8]/
UHPI_HD[0]/
UPP_D[0]/
GP6[5]/
V
DVDD3318_C
NC
NC
USB0_ID
NC
NC
DVDD18
SS
PRU1_R31[0]
PLL1_VDDA
PLL1_VSSA
PLL0_VDDA
NC
USB0_VDDA12
USB0_VDDA33
USB0_DM
OSCVSS
USB0_VBUS
USB0_DP
OSCIN
V
SS
V
SS
V
SS
V
SS
V
SS
DVDD3318_C
DVDD3318_C
DVDD3318_C
USB0_VDDA18
NC
NC
PLL0_VSSA
TDI
RTC_CVDD
CV
TMS
DD
TRST
RTCK/
GP8[0]
DVDD3318_C
DVDD3318_B
USB0_DRVVBUS
CV
EMU1
OSCOUT
K
DD
RESET
K
11
12
13
14
15
16
17
18
19
Figure 3-2. Pin Map (Quad B)
16
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11
12
13
14
15
16
17
18
19
DV
V
CV
DV
DD3318_B
RTC_XI
TCK
RSVDN
J
H
G
F
SS
DD
DD18
J
EMU0
TDO
SPI1_SOMI/
GP2[11]
SPI1_ENA/
GP2[12]
CV
CV
CV
RV
DD
V
SS
RTC_VSS
RTC_XO
DD
DD
DD
H
SPI1_SCS[7]/
I2C0_SCL/
TM64P2_OUT12/
GP1[15]
SPI1_SCS[6]/
I2C0_SDA/
TM64P3_OUT12/
GP1[4]
SPI1_SIMO/
GP2[10]
SPI1_CLK/
GP2[13]
DV
DV
DD3318_A
DV
DV
CV
DD3318_A
DD18
DD18
DD
G
SPI1_SCS[1]/
EPWM1A/
PRU0_R30[7]/
GP2[15]/
TM64P2_IN12
SPI1_SCS[4]/
UART2_TXD/
I2C1_SDA/
GP1[2]
SPI1_SCS[5]/
UART2_RXD/
I2C1_SCL/
GP1[3]
SPI1_SCS[2]/
UART1_TXD/
GP1[0]
DV
DV
DV
DV
DD3318_A
DD3318_B
DD3318_B
DD3318_B
DV
DD18
F
SPI0_SCS[1]/
TM64P0_OUT12/
GP1[7]/
SPI0_SCS[3]/
UART0_CTS/
GP8[2]
SPI1_SCS[0]/
EPWM1B/
PRU0_R30[8]/
GP2[14]/
TM64P3_IN12
SPI1_SCS[3]/
UART1_RXD/
GP1[1]
EMA_A[18]/
MMCSD0_DAT[3]/
PRU1_R30[26]/
GP4[2]/
EMA_A[16]/
MMCSD0_DAT[5]/
PRU1_R30[24]/
GP4[0]
EMA_A[6]/
GP5[6]
DV
DD3318_B
CV
DD
E
D
C
B
A
E
TM64P0_IN12
PRU1_R31[18]
SPI0_SCS[2]/
UART0_RTS/
GP8[1]
SPI0_SCS[0]/
TM64P1_OUT12/
GP1[6]/
SPI0_CLK/
EPWM0A/
GP1[8]
SPI0_SCS[4]/
UART0_TXD/
GP8[3]
EMA_A[13]/
PRU0_R30[21]/
PRU1_R30[21]
GP5[13]
EMA_A[9]/
PRU1_R30[17]/
GP5[9]
EMA_A[12]/
PRU1_R30[20]/
GP5[12]
EMA_A[3]/
GP5[3]
EMA_A[1]/
GP5[1]
D
TM64P1_IN12
SPI0_SOMI/
EPWMSYNCI/
GP8[6]
SPI0_SIMO/
EPWMSYNCO/
GP8[5]
SPI0_SCS[5]/
UART0_RXD/
GP8[4]
EMA_A[15]/
MMCSD0_DAT[6]/
PRU1_R30[23]/
GP5[15]
SPI0_ENA/
EPWM0B/
PRU0_R30[6]
EMA_A[0]/
GP5[0]
EMA_BA[0]/
GP2[8]
EMA_A[5]/
GP5[5]
C
EMA_A[10]/
PRU1_R30[18]/
GP5[10]
EMA_A[17]/
MMCSD0_DAT[4]/
PRU1_R30[25]
GP4[1]
EMA_A[11]/
PRU1_R30[19]/
GP5[11]
EMA_A7/
PRU1_R30[15]/
GP5[7]
EMA_A[2]/
GP5[2]
EMA_CS[2]/
GP3[15]
EMA_WAIT[0]/
PRU0_R30[0]/
GP3[8]/
EMA_WAIT[1]/
PRU0_R30[1]/
GP2[1]/
EMA_OE/
GP3[10]
EMA_CS[5]/
GP3[12]
B
PRU0_R31[0]
PRU0_R31[1]
EMA_A[20]/
MMCSD0_DAT[1]/
PRU1_R30[28]/
GP4[4]/
EMA_A[14]/
MMCSD0_DAT[7]/
PRU1_R30[22]/
GP5[14]
EMA_A[8]/
PRU1_R30[16]/
GP5[8]
EMA_CS[3]/
GP3[14]
EMA_A[4]/
GP5[4]
EMA_BA[1]/
GP2[9]
EMA_RAS/
PRU0_R30[3]/
GP2[5]/
EMA_CS[0]/
GP2[0]
A
V
SS
PRU0_R31[3]
PRU1_R31[20]
11
12
13
14
15
16
17
18
19
Figure 3-3. Pin Map (Quad C)
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1
2
3
4
5
6
7
8
9
10
VP_CLKIN3/
MMCSD1_DAT[1]/
PRU1_R30[1]/
GP6[2]/
PRU0_R30[23]/
MMCSD1_CMD/
UPP_CHB_ENABLE/
GP8[13]/
NC
DV
DV
DV
DV
DD3318_C
CV
V
V
V
SS
NC
J
H
G
F
DD
SS
V
SS
J
SS
PRU1_R31[2]
PRU1_R31[25]
VP_CLKIN2/
MMCSD1_DAT[3]/
PRU1_R30[3]/
GP6[4]/
MMCSD1_DAT[5]/
LCD_HSYNC/
PRU1_R30[5]/
GP8[9]/
V
V
V
V
SS
DD3318_A
DD3318_A
DD3318_A
CV
CV
CV
DD
DD
DD
SS
H
G
F
SS
SS
PRU1_R31[4]
PRU1_R31[6]
PRU0_R30[25]/
MMCSD1_DAT[0]/
PRU0_R30[24]/
MMCSD1_CLK/
UPP_CHB_CLOCK/ UPP_CHB_START/
MMCSD1_DAT[4]/
LCD_VSYNC/
PRU1_R30[4]/
GP8[8]/
PRU0_R30[22]/
PRU1_R30[8]/
UPP_CHB_WAIT/
GP8[12]/
DV
DV
DD3318_B
DD18
CV
DV
DD18
CV
DD
DD
GP8[15]/
PRU1_R31[27]
GP8[14]/
PRU1_R31[26]
PRU1_R31[5]
PRU1_R31[24]
AXR0/
ECAP0_APWM0/
GP8[7]/
RTC_ALARM/
UART2_CTS/
GP0[8]/
MMCSD1_DAT[7]/
LCD_PCLK/
PRU1_R30[7]/
GP8[11]
MMCSD1_DAT[6]/
LCD_MCLK/
PRU1_R30[6]/
GP8[10]/
EMA_CS[4]/
GP3[13]
DV
DV
DV
DV
DD3318_B
DD3318_B
DD3318_B
DD3318_B
CLKS0
DEEPSLEEP
PRU1_R31[7]
AXR1/
DX0/
GP1[9]
AXR2/
DR0/
GP1[10]
AXR3/
FSX0/
GP1[11]
AXR8/
CLKS1/
ECAP1_APWM1/
GP0[0]/
PRU0_R31[8]
EMA_A[23]/
MMCSD0_CLK/
PRU1_R30[31]/
GP4[7]/
EMA_D[15]/
GP3[7]
EMA_D[5]/
GP4[13]
EMA_D[3]/
GP4[11]
EMA_D[8]/
GP3[0]
RV
DD
E
D
C
B
A
E
D
C
B
A
PRU1_R31[23]
AXR4/
FSR0/
GP1[12]
AXR5/
CLKX0/
GP1[13]
AXR7/
AXR10/
DR1/
GP0[2]
AMUTE/
PRU0_R30[16]/
UART2_RTS/
GP0[9]/
EMA_D[11]/
GP3[3]
EMA_D[7]/
GP4[15]
EMA_SDCKE/
PRU0_R30[4]/
GP2[6]/
EMA_D[9]/
GP3[1]
EPWM1TZ[0]/
PRU0_R30[17]
GP1[15]/
EMA_A_RW/
GP3[9]
PRU0_R31[4]
PRU0_R31[7]
PRU0_R31[16]
AXR6/
CLKR0/
GP1[14]/
AXR9/
DX1/
GP0[1]
AXR12/
FSR1/
GP0[4]
AXR11/
FSX1/
GP0[3]
EMA_A[19]/
MMCSD0_DAT[2]/
PRU1_R30[27]/
GP4[3]/
AFSR/
GP0[13]/
PRU0_R31[20]
EMA_D[6]/
GP4[14]
EMA_D[14]/
GP3[6]
EMA_WEN_DQM[0]/
GP2[3]
EMA_D[0]/
GP4[8]
PRU0_R31[6]
PRU1_R31[19]
AXR13/
CLKX1/
GP0[5]
AXR14/
CLKR1/
GP0[6]
EMA_A[21]/
MMCSD0_DAT[0]/
PRU1_R30[29]/
GP4[5]/
ACLKX/
PRU0_R30[19]/
GP0[14]/
AFSX/
GP0[12]/
PRU0_R31[19]
EMA_D[4]/
GP4[12]
EMA_D[13]/
GP3[5]
EMA_CLK/
PRU0_R30[5]/
GP2[7]/
EMA_D[2]/
GP4[10]
EMA_WE/
GP3[11]
PRU0_R31[21]
PRU0_R31[5]
PRU1_R31[21]
AHCLKX/
USB_REFCLKIN/
UART1_CTS/
GP0[10]/
AXR15/
EPWM0TZ[0]/
ECAP2_APWM2/
GP0[7]
AHCLKR/
PRU0_R30[18]/
UART1_RTS/
GP0[11]/
EMA_A[22]/
MMCSD0_CMD/
PRU1_R30[30]/
GP4[6]/
ACLKR/
PRU0_R30[20]/
GP0[15]/
EMA_D[12]/
GP3[4]
EMA_D[10]/
GP3[2]
EMA_D[1]/
GP4[9]
EMA_WEN_DQM[1]/
GP2[2]
EMA_CAS/
PRU0_R30[2]/
GP2[4]/
PRU0_R31[17]
PRU0_R31[22]
PRU0_R31[2]
PRU0_R31[18]
PRU1_R31[22]
1
2
3
4
5
6
7
8
9
10
Figure 3-4. Pin Map (Quad D)
3.6 Pin Multiplexing Control
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin.
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3.7 Terminal Functions
Table 3-3 to Table 3-27 identify the external signal names, the associated pin/ball numbers along with the
mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal
pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin
description.
3.7.1 Device Reset and JTAG
Table 3-3. Reset and JTAG Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
RESET
RESET
K14
T17
I
IPU
B
C
Device reset input
RESETOUT / UHPI_HAS / PRU1_R30[14] /
GP6[15]
O(4)
CP[21]
Reset output
JTAG
TMS
TDI
L16
M16
J18
J15
L17
J16
K16
K17
I
I
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPD
B
B
B
B
B
B
B
B
JTAG test mode select
JTAG test data input
JTAG test data output
JTAG test clock
TDO
TCK
O
I
TRST
EMU0
EMU1
I
JTAG test reset
I/O
I/O
I/O
Emulation pin
Emulation pin
(5)
RTCK/ GP8[0]
JTAG Test Clock Return Clock Output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor. CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
(4) Open drain mode for RESETOUT function.
(5) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
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3.7.2 High-Frequency Oscillator and PLL
Table 3-4. High-Frequency Oscillator and PLL Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
O
PULL(2)
CP[22]
DESCRIPTION
PLL Observation Clock
GROUP(3)
NO.
T18
CLKOUT / UHPI_HDS2 /
PRU1_R30[13] / GP6[14]
C
1.2-V OSCILLATOR
OSCIN
L19
K19
L18
I
—
—
—
—
Oscillator input
OSCOUT
OSCVSS
O
—
Oscillator output
GND
—
Oscillator ground (for filter only)
1.2-V PLL0
PLL0_VDDA
PLL0_VSSA
L15
PWR
GND
—
—
—
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
M17
—
1.2-V PLL1
PLL1_VDDA
PLL1_VSSA
N15
M15
PWR
GND
—
—
—
—
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.3 Real-Time Clock and 32-kHz Oscillator
Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
J19
H19
F4
RTC_XI
I
—
—
—
—
A
RTC 32-kHz oscillator input
RTC 32-kHz oscillator output
RTC Alarm
RTC_XO
O
O
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP
CP[0]
RTC module core power
(isolated from chip CVDD
RTC_CVDD
RTC_Vss
L14
H18
PWR
GND
—
—
—
—
)
Oscillator ground (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
3.7.4 DEEPSLEEP Power Control
Table 3-6. DEEPSLEEP Power Control Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
I
PULL(2)
CP[0]
DESCRIPTION
GROUP(3)
NO.
F4
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP
A
DEEPSLEEP power control output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.5 External Memory Interface A (EMIFA)
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
E6
C7
B6
A6
D6
A7
D9
E10
D7
C6
E7
B5
E8
B8
A8
C9
EMA_D[15] / GP3[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
EMA_D[14] / GP3[6]
EMA_D[13] / GP3[5]
EMA_D[12] / GP3[4]
EMA_D[11] / GP3[3]
EMA_D[10] / GP3[2]
EMA_D[9] / GP3[1]
EMA_D[8] / GP3[0]
EMA_D[7] / GP4[15]
EMA_D[6] / GP4[14]
EMA_D[5] / GP4[13]
EMA_D[4] / GP4[12]
EMA_D[3] / GP4[11]
EMA_D[2] / GP4[10]
EMA_D[1] / GP4[9]
EMA_D[0] / GP4[8]
EMIFA data bus
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
A10
EMA_A[22] / MMCSD0_CMD /
PRU1_R30[30] / GP4[6] / PRU1_R31[22]
O
O
O
O
O
O
O
O
O
O
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[19]
CP[19]
CP[19]
B
B
B
B
B
B
B
B
B
B
EMA_A[21] / MMCSD0_DAT[0] /
PRU1_R30[29] / GP4[5] / PRU1_R31[21]
B10
A11
C10
E11
B11
E12
C11
A12
D11
EMA_A[20] / MMCSD0_DAT[1] /
PRU1_R30[28] / GP4[4] / PRU1_R31[20]
EMA_A[19] / MMCSD0_DAT[2] /
PRU1_R30[27] / GP4[3] / PRU1_R31[19]
EMA_A[18] / MMCSD0_DAT[3] /
PRU1_R30[26] / GP4[2] / PRU1_R31[18]
EMA_A[17] / MMCSD0_DAT[4] /
PRU1_R30[25] / GP4[1]
EMA_A[16] / MMCSD0_DAT[5] /
PRU1_R30[24] / GP4[0]
EMA_A[15] / MMCSD0_DAT[6] /
PRU1_R30[23] / GP5[15]
EMA_A[14] / MMCSD0_DAT[7] /
PRU1_R30[22] / GP5[14]
EMIFA address bus
EMA_A[13] /PRU0_R30[21] / PRU1_R30[21]
/ GP5[13]
EMA_A[12] / PRU1_R30[20] / GP5[12]
EMA_A[11] / PRU1_R30[19] / GP5[11]
EMA_A[10] / PRU1_R30[18] / GP5[10]
EMA_A[9] / PRU1_R30[17] / GP5[9]
EMA_A[8] / PRU1_R30[16] / GP5[8]
EMA_A[7] / PRU1_R30[15] / GP5[7]
EMA_A[6] / GP5[6]
D13
B12
C12
D12
A13
B13
E13
C13
A14
D14
B14
D15
C14
C15
A15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[16]
CP[16]
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
EMA_A[5] / GP5[5]
EMA_A[4] / GP5[4]
EMA_A[3] / GP5[3]
EMA_A[2] / GP5[2]
EMA_A[1] / GP5[1]
EMA_A[0] / GP5[0]
EMA_BA[0] / GP2[8]
EMIFA bank address
EMA_BA[1] / GP2[9]
EMA_CLK / PRU0_R30[5] / GP2[7] /
PRU0_R31[5]
B7
D8
O
O
O
O
CP[16]
CP[16]
CP[16]
CP[16]
B
B
B
B
EMIFA clock
EMA_SDCKE / PRU0_R30[4] / GP2[6] /
PRU0_R31[4]
EMIFA SDRAM clock enable
EMIFA SDRAM row address strobe
EMA_RAS / PRU0_R30[3] / GP2[5] /
PRU0_R31[3]
A16
A9
EMA_CAS / PRU0_R30[2] / GP2[4] /
PRU0_R31[2]
EMIFA SDRAM column address strobe
EMIFA SDRAM Chip Select
EMA_CS[0] / GP2[0]
EMA_CS[2] / GP3[15]
EMA_CS[3] / GP3[14]
EMA_CS[4] / GP3[13]
EMA_CS[5] / GP3[12]
EMA_A_RW / GP3[9]
EMA_WE / GP3[11]
A18
B17
A17
F9
O
O
O
O
O
O
O
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
B
B
B
B
B
B
B
EMIFA Async Chip Select
B16
D10
B9
EMIFA Async Read/Write control
EMIFA SDRAM write enable
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Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
A5
EMIFA write enable/data mask for
EMA_D[15:8]
EMA_WEN_DQM[1] / GP2[2]
O
CP[16]
B
EMA_WEN_DQM[0] / GP2[3]
EMA_OE / GP3[10]
C8
O
O
CP[16]
CP[16]
B
B
EMIFA write enable/data mask for EMA_D[7:0]
EMIFA output enable
B15
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] /
PRU0_R31[0]
B18
B19
I
I
CP[16]
CP[16]
B
B
EMIFA wait input/interrupt
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] /
PRU0_R31[1]
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3.7.6 DDR2 Controller (DDR2)
Table 3-8. DDR2 Controller (DDR2) Terminal Functions
SIGNAL
NAME
TYPE(1)
PULL(2)
DESCRIPTION
NO.
W10
U11
V10
U10
T12
T10
T11
T13
W11
W12
V12
V13
U13
V14
U14
U15
T5
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
DDR_D[8]
DDR_D[7]
DDR_D[6]
DDR_D[5]
DDR_D[4]
DDR_D[3]
DDR_D[2]
DDR_D[1]
DDR_D[0]
DDR_A[13]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
DDR_CLKP
DDR_CLKN
DDR_CKE
DDR_WE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
DDR2 SDRAM data bus
V4
O
T4
O
W4
T6
O
O
U4
O
U6
O
DDR2 row/column address
W5
V5
O
O
U5
O
V6
O
W6
T7
O
O
U7
O
W8
W7
V7
O
DDR2 clock (positive)
DDR2 clock (negative)
DDR2 clock enable
O
O
T8
O
DDR2 write enable
DDR_RAS
DDR_CAS
DDR_CS
W9
U9
O
DDR2 row address strobe
DDR2 column address strobe
DDR2 chip select
O
V9
O
DDR_DQM[0]
DDR_DQM[1]
W13
R10
O
DDR2 data mask outputs
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module.
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Table 3-8. DDR2 Controller (DDR2) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
PULL(2)
DESCRIPTION
NO.
T14
V11
U8
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
I/O
I/O
O
IPD
IPD
IPD
IPD
IPD
DDR2 data strobe inputs/outputs
T9
O
DDR2 SDRAM bank address
V8
O
DDR2 loopback signal for external DQS gating.
Route to DDR and back to DDR_DQGATE1 with
same constraints as used for DDR clock and data.
DDR_DQGATE0
DDR_DQGATE1
DDR_ZP
R11
R12
U12
R6
O
I
IPD
IPD
—
DDR2 loopback signal for external DQS gating.
Route to DDR and back to DDR_DQGATE0 with
same constraints as used for DDR clock and data.
DDR2 reference output for drive strength calibration
of N and P channel outputs. Tie to ground via 50
ohm resistor @ 0.5% tolerance.
O
I
DDR voltage input for the DDR2/mDDR I/O buffers.
Note even in the case of mDDR an external resistor
divider connected to this pin is necessary.
DDR_VREF
—
N10, P10, N9,
P9, R9, P8,
R8, P7, R7,
N6
DDR_DVDD18
PWR
—
DDR PHY 1.8V power supply pins
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3.7.7 Serial Peripheral Interface Modules (SPI)
Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
SPI0
SPI0_CLK / EPWM0A / GP1[8]
D19
C17
D17
E16
D16
E17
D18
C19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[7]
CP[7]
CP[10]
CP[10]
CP[9]
CP[9]
CP[8]
CP[8]
A
A
A
A
A
A
A
A
SPI0 clock
SPI0_ENA / EPWM0B / PRU0_R30[6]
SPI0 enable
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / TM64P1_IN12
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / TM64P0_IN12
SPI0_SCS[2] / UART0_RTS / GP8[1]
SPI0 chip selects
SPI0_SCS[3] / UART0_CTS / GP8[2]
SPI0_SCS[4] / UART0_TXD / GP8[3]
SPI0_SCS[5] / UART0_RXD / GP8[4]
SPI0 data
slave-in-master-out
SPI0_SIMO / EPWMSYNCO / GP8[5]
SPI0_SOMI / EPWMSYNCI / GP8[6]
C18
C16
I/O/Z
I/O/Z
CP[7]
CP[7]
A
A
SPI0 data
slave-out-master-in
SPI1
SPI1_CLK / GP2[13]
SPI1_ENA / GP2[12]
G19
H16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[15]
CP[15]
CP[14]
CP[14]
CP[13]
CP[13]
CP[12]
CP[12]
CP[11]
CP[11]
A
A
A
A
A
A
A
A
A
A
SPI1 clock
SPI1 enable
SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] / TM64P3_IN12 E19
SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12 F18
SPI1_SCS[2] / UART1_TXD / GP1[0]
F19
E18
F16
F17
G18
G16
SPI1_SCS[3] / UART1_RXD / GP1[1]
SPI1 chip selects
SPI1_SCS[4] / UART2_TXD / I2C1_SDA /GP1[2]
SPI1_SCS[5] / UART2_RXD / I2C1_SCL /GP1[3]
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
SPI1 data
slave-in-master-out
SPI1_SIMO / GP2[10]
SPI1_SOMI / GP2[11]
G17
H17
I/O/Z
I/O/Z
CP[15]
CP[15]
A
A
SPI1 data
slave-out-master-in
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.8 Programmable Real-Time Unit (PRU)
Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
PRU0 Output Signals
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
R17
R16
U17
W15
U16
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]
O
O
O
O
O
CP[23]
CP[23]
CP[24]
CP[24]
CP[24]
C
C
C
C
C
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] /
PRU1_R31[17]
T15
G1
G2
J4
O
O
O
O
O
CP[24]
CP30]
CP[30]
CP[30]
CP[30]
C
C
C
C
C
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15] /
PRU1_R31[27]
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
PRU1_R31[25]
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13]
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]
D11
A1
O
O
O
O
O
O
CP[19]
CP[0]
CP[0]
CP[0]
CP[4]
CP[0]
B
A
A
A
A
A
B1
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18] A2
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]
D2
D5
PRU0 Output Signals
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
PRU0_R31[15]
V18
V19
U19
T16
R18
R19
O
O
O
O
O
O
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
C
C
C
C
C
C
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /
PRU0_R31[14]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9] R15
SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] / TM64P3_IN12 E19
SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12 F18
O
O
O
O
O
O
O
O
O
O
CP[27]
CP[14]
CP[14]
CP[7]
C
A
A
A
B
B
B
B
B
B
SPI0_ENA / EPWM0B / PRU0_R30[6]
C17
B7
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
D8
A16
A9
B19
B18
PRU0 Input Signals
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Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued)
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
U18
V16
R14
W16
V17
W17
W18
A1
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / PRU0_R31[23]
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]
AFSR / GP0[13] / PRU0_R31[20]
I
I
I
I
I
I
I
I
I
I
I
I
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[0]
C
C
C
C
C
C
C
A
A
A
A
A
B1
CP[0]
C2
CP[0]
AFSX / GP0[12] / PRU0_R31[19]
B2
CP[0]
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18] A2
CP[0]
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
PRU0_R31[17]
A3
I
I
I
CP[0]
CP[0]
A
A
C
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]
D5
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
PRU0_R31[15]
V18
CP[27]
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /
PRU0_R31[14]
V19
U19
T16
R18
R19
I
I
I
I
I
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
C
C
C
C
C
PRU0 Input Signals
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9] R15
I
I
I
I
I
I
I
I
I
I
CP[27]
CP[3]
C
A
A
A
B
B
B
B
B
B
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]
E4
D2
CP[4]
C1
CP[5]
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]
B7
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
D8
A16
A9
B19
B18
PRU1 Output Signals
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Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
E9
MMCSD0_CLK / PRU1_R30[31] /GP4[7] / PRU1_R31[23]
O
O
CP[18]
CP[18]
B
B
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] /
A10
B10
A11
C10
E11
PRU1_R31[22]
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] /
O
O
O
O
CP[18]
CP[18]
CP[18]
CP[18]
B
B
B
B
PRU1_R31[21]
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] /
PRU1_R31[20]
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] /
PRU1_R31[19]
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] /
PRU1_R31[18]
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15]
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14]
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13]
EMA_A[12] / PRU1_R30[20] / GP5[12]
B11
E12
C11
A12
D11
D13
B12
C12
D12
A13
B13
T17
T18
R17
R16
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[18]
CP[18]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[20]
CP[21]
CP[22]
CP[23]
CP[23]
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
EMA_A[11] / PRU1_R30[19] / GP5[11]
EMA_A[10] / PRU1_R30[18] / GP5[10]
EMA_A[9] / PRU1_R30[17] / GP5[9]
EMA_A[8] / PRU1_R30[16] / GP5[8]
EMA_A[7] / PRU1_R30[15] / GP5[7]
PRU1 Output Signals
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /
UPP_2xTXCLK
W14
O
O
O
O
O
CP[25]
CP[25]
CP[30]
CP[31]
CP[31]
C
C
C
C
C
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
F1
F2
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
G4
H3
K3
O
O
O
O
CP[31]
CP[31]
CP[30]
CP[30]
C
C
C
C
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
J3
O
O
CP[30]
CP[30]
C
C
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
K4
PRU1 Input Signals
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Table 3-10. Programmable Real-Time Unit (PRU) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
W19
R5
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / PRU1_R31[29]
LCD_AC_ENB_CS / GP6[0] / PRU1_R31[28]
I
I
CP[26]
CP[31]
C
C
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15] /
PRU1_R31[27]
G1
G2
J4
I
I
I
CP[30]
CP[30]
CP[30]
C
C
C
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
PRU1_R31[25]
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3
E9
I
I
I
CP[30]
CP[18]
CP[18]
C
B
B
MMCSD0_CLK / PRU1_R30[31] /GP4[7] / PRU1_R31[23]
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] /
PRU1_R31[22]
A10
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] /
PRU1_R31[21]
B10
A11
C10
E11
T15
I
I
I
I
I
CP[18]
CP[18]
CP[18]
CP[18]
CP[24]
B
B
B
B
C
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] /
PRU1_R31[20]
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] /
PRU1_R31[19]
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] /
PRU1_R31[18]
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] /
PRU1_R31[17]
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15
I
I
I
I
I
I
I
I
I
CP[25]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
C
C
C
C
C
C
C
C
C
PRU1 Input Signals
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15]
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14]
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13]
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10]
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]
U2
U1
V3
V2
V1
W3
W2
W1
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
F2
H4
G4
H3
K3
J3
I
I
I
I
I
I
CP[31]
CP[31]
CP[31]
CP[30]
CP[30]
CP[30]
C
C
C
C
C
C
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
K4
I
I
CP[30]
CP[27]
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
P17
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3.7.9 Enhanced Capture/Auxiliary PWM Modules (eCAP0)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-11. Enhanced Capture Module (eCAP) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
eCAP0
PULL(2)
DESCRIPTION
GROUP(3)
NO.
F3
enhanced capture 0 input or
auxiliary PWM 0 output
AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0
I/O
eCAP1
I/O
CP[6]
CP[3]
CP[1]
A
A
A
enhanced capture 1 input or
auxiliary PWM 1 output
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8] E4
eCAP2
A4 I/O
enhanced capture 2 input or
auxiliary PWM 2 output
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
Table 3-12. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
CP[7]
DESCRIPTION
GROUP(3)
NO.
eHRPWM0
eHRPWM0 A output
(with high-resolution)
SPI0_CLK / EPWM0A / GP1[8]
D19
I/O
A
SPI0_ENA / EPWM0B / PRU0_R30[6]
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
SPI0_SOMI / EPWMSYNCI / GP8[6]
C17
A4
I/O
CP[7]
CP[1]
CP[7]
CP[7]
A
A
A
A
eHRPWM0 B output
I/O
eHRPWM0 trip zone input
eHRPWM0 sync input
eHRPWM0 sync output
C16
C18
I/O
SPI0_SIMO / EPWMSYNCO / GP8[5]
I/O
eHRPWM1
SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] /
TM64P2_IN12
eHRPWM1 A output
(with high-resolution)
F18
E19
D2
I/O
I/O
I/O
CP[14]
CP[14]
CP[4]
A
A
A
SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] /
TM64P3_IN12
eHRPWM1 B output
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /
PRU0_R31[7]
eHRPWM1 trip zone input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.11 Boot
Table 3-13. Boot Mode Selection Terminal Functions(1)
SIGNAL
NAME
POWER
TYPE(2)
PULL(3)
DESCRIPTION
GROUP(4)
NO.
P4
R3
R2
R1
T3
VP_DOUT[15/]/ LCD_D[15]/ UPP_XD[7] /GP7[7] / BOOT[7]
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] /GP7[6] / BOOT[6]
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] /GP7[5] / BOOT[5]
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] /GP7[3] / BOOT[3]
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] /GP7[2] / BOOT[2]
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] /GP7[1] / BOOT[1]
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] /GP7[0] / BOOT[0]
I
I
I
I
I
I
I
I
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
C
C
C
C
C
C
C
C
Boot Mode Selection Pins
T2
T1
U3
(1) Boot decoding is defined in the bootloader application report.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(3) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(4) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
UART0
SPI0_SCS[5] / UART0_RXD / GP8[4]
SPI0_SCS[4] / UART0_TXD / GP8[3]
SPI0_SCS[2] / UART0_RTS / GP8[1]
SPI0_SCS[3] / UART0_CTS / GP8[2]
C19
D18
D16
E17
I
CP[8]
CP[8]
CP[9]
CP[9]
A
A
A
A
UART0 receive data
O
O
I
UART0 transmit data
UART0 ready-to-send output
UART0 clear-to-send input
UART1
SPI1_SCS[3] / UART1_RXD / GP1[1]
SPI1_SCS[2] / UART1_TXD / GP1[0]
E18
F19
I
CP[13]
CP[13]
A
A
UART1 receive data
UART1 transmit data
O
AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /
PRU0_R31[18]
A2
A3
O
I
CP[0]
CP[0]
A
A
UART1 ready-to-send output
UART1 clear-to-send input
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
PRU0_R31[17]
UART2
SPI1_SCS[5] / UART2_RXD / I2C1_SCL /GP1[3]
SPI1_SCS[4] / UART2_TXD / I2C1_SDA /GP1[2]
F17
F16
I
CP[12]
CP[12]
A
A
UART2 receive data
UART2 transmit data
O
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /
PRU0_R31[16]
D5
F4
O
I
CP[0]
CP[0]
A
A
UART2 ready-to-send output
UART2 clear-to-send input
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
I2C0
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
G18
G16
I/O
I/O
CP[11]
CP[11]
A
A
I2C0 serial data
I2C0 serial clock
I2C1
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]
F16
F17
I/O
I/O
CP[12]
CP[12]
A
A
I2C1 serial data
I2C1 serial clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.14 Timers
Table 3-16. Timers Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
TIMER0
SPI0_SCS[1] /TM64P0_OUT12 / GP1[7] / TM64P0_IN12
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / TM64P0_IN12
E16
E16
I
CP[10]
CP[10]
A
A
Timer0 lower input.
Timer0 lower
output
O
TIMER1 (Watchdog)
SPI0_SCS[0] /TM64P1_OUT12 / GP1[6] / TM64P1_IN12
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / TM64P1_IN12
D17
I
CP[10]
CP[10]
A
A
Timer1 lower input.
Timer1 lower
output
D17
O
TIMER2
SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12
F18
G16
I
CP[14]
CP[11]
A
A
Timer2 lower input.
Timer2 lower
output
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
O
TIMER3
SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] / TM64P3_IN12
E19
G18
I
CP[14]
CP[11]
A
A
Timer3 lower input.
Timer3 lower
output
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.15 Multichannel Audio Serial Ports (McASP)
Table 3-17. Multichannel Audio Serial Ports Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
McASP0
I/O
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
AXR14 / CLKR1 / GP0[6]
AXR13 / CLKX1 / GP0[5]
AXR12 / FSR1 / GP0[4]
A4
B4
B3
C4
C5
D4
C3
CP[1]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[3]
A
A
A
A
A
A
A
A
I/O
I/O
I/O
AXR11 / FSX1 / GP0[3]
I/O
AXR10 / DR1 / GP0[2]
I/O
AXR9 / DX1 / GP0[1]
I/O
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8] E4
I/O
McASP0 serial data
A
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /
PRU0_R31[7]
D2
I/O
CP[4]
AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]
AXR5 / CLKX0 / GP1[13]
C1
D3
D1
E3
E2
E1
F3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[5]
CP[5]
CP[5]
CP[5]
CP[5]
CP[5]
CP[6]
A
A
A
A
A
A
A
AXR4 / FSR0 / GP1[12]
AXR3 / FSX0 / GP1[11]
AXR2 / DR0 / GP1[10]
AXR1 / DX0 / GP1[9]
AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
PRU0_R31[17]
A3
I/O
CP[0]
A
McASP0 transmit master clock
ACLKX / PRU0_R30[19]/ GP0[14]/ PRU0_R31[21]
AFSX / GP0[12] / PRU0_R31[19]
B1
B2
I/O
I/O
CP[0]
CP[0]
A
A
McASP0 transmit bit clock
McASP0 transmit frame sync
AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /
PRU0_R31[18]
A2
I/O
CP[0]
A
McASP0 receive master clock
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
AFSR / GP0[13] / PRU0_R31[20]
A1
C2
I/O
I/O
CP[0]
CP[0]
A
A
McASP0 receive bit clock
McASP0 receive frame sync
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /
PRU0_R31[16]
D5
I/O
CP[0]
A
McASP0 mute output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.16 Multichannel Buffered Serial Ports (McBSP)
Table 3-18. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
McBSP0
AXR0 / ECAP0_APWM0 / GP8[7] /CLKS0
AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]
AXR4 / FSR0 / GP1[12] /
F3
C1
D1
E2
D3
E3
E1
I
CP[6]
CP[5]
A
A
A
A
A
A
A
McBSP0 sample rate generator clock input
McBSP0 receive clock
I/O
I/O
I
CP[5]
McBSP0 receive frame sync
McBSP0 receive data
AXR2 / DR0 / GP1[10] /
CP[5]
AXR5 / CLKX0 / GP1[13] /
AXR3 / FSX0 / GP1[11]
I/O
I/O
O
CP[5]
McBSP0 transmit clock
CP[5]
McBSP0 transmit frame sync
McBSP0 transmit data
AXR1 / DX0 / GP1[9]
CP[5]
McBSP1
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] /
PRU0_R31[8]
E4
I
CP[3]
A
McBSP1 sample rate generator clock input
AXR14 / CLKR1 / GP0[6]
AXR12 / FSR1 / GP0[4]
AXR10 / DR1 / GP0[2]
AXR13 / CLKX1 / GP0[5]
AXR11 / FSX1 / GP0[3]
AXR9 / DX1 / GP0[1]
B4
C4
D4
B3
C5
C3
I/O
I/O
I
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
A
A
A
A
A
A
McBSP1 receive clock
McBSP1 receive frame sync
McBSP1 receive data
I/O
I/O
O
McBSP1 transmit clock
McBSP1 transmit frame sync
McBSP1 transmit data
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.17 Universal Serial Bus Modules (USB0)
Table 3-19. Universal Serial Bus (USB) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
USB0 2.0 OTG (USB0)
USB0_DM
M18
M19
N18
A
A
IPD
IPD
—
—
—
—
USB0 PHY data minus
USB0 PHY data plus
USB0 PHY 3.3-V supply
USB0_DP
USB0_VDDA33
PWR
USB0 PHY identification
(mini-A or mini-B plug)
USB0_ID
P16
A
—
—
USB0_VBUS
N19
K18
A
0
—
—
B
USB0 bus voltage
USB0_DRVVBUS
IPD
USB0 controller VBUS control output.
AHCLKX / USB_REFCLKIN / UART1_CTS /
GP0[10] / PRU0_R31[17]
A3
I
CP[0]
A
USB_REFCLKIN. Optional clock input
USB0_VDDA18
USB0_VDDA12
USB_CVDD
N14
N17
M12
PWR
A
—
—
—
—
—
—
USB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
USB0 core logic 1.2-V supply input
PWR
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.18 Multimedia Card/Secure Digital (MMC/SD)
Table 3-20. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
MMCSD0
MMCSD0_CLK / PRU1_R30[31] /GP4[7] / PRU1_R31[23]
E9
O
CP[18]
CP[18]
B
B
MMCSD0 Clock
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] /
PRU1_R31[22]
A10
I/O
MMCSD0 Command
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14]
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15]
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]
A12
C11
E12
B11
I/O
I/O
I/O
I/O
CP[19]
CP[19]
CP[18]
CP[18]
B
B
B
B
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] /
PRU1_R31[18]
E11
C10
A11
B10
I/O
I/O
I/O
I/O
CP[18]
CP[18]
CP[18]
CP[18]
B
B
B
B
MMC/SD0 data
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] /
PRU1_R31[19]
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] /
PRU1_R31[20]
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] /
PRU1_R31[21]
MMCSD1
PRU0_R30[24] /MMCSD1_CLK / UPP_CHB_START /
GP8[14]/PRU1_R31[26]/
G2
O
CP[30]
C
MMCSD1 Clock
PRU0_R30[23] /MMCSD1_CMD / UPP_CHB_ENABLE /
GP8[13]/PRU1_R31[25]
J4
F1
F2
I/O
I/O
I/O
CP[30]
CP[31]
CP[31]
C
C
C
MMCSD1 Command
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
MMCSD1_DAT[6] / LCD_MCLK /PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
MMCSD1_DAT[5] / LCD_HSYNC /PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
G4
H3
K3
J3
I/O
I/O
I/O
I/O
I/O
I/O
CP[31]
CP[31]
CP[30]
CP[30]
CP[30]
CP[30]
C
C
C
C
C
C
MMCSD1_DAT[4] / LCD_VSYNC /PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
MMC/SD1 data
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
VP_CLKIN3 / MMCSD1_DAT[1]/ PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]/
PRU1_R31[27]
G1
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.19 Liquid Crystal Display Controller(LCD)
Table 3-21. Liquid Crystal Display Controller (LCD) Terminal Functions
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
P4
R3
R2
R1
T3
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
C
C
C
C
C
C
C
C
T2
T1
U3
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] /
PRU1_R31[15]
U2
U1
V3
V2
V1
W3
I/O
I/O
I/O
I/O
I/O
I/O
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
C
C
C
C
C
C
LCD data bus
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] /
PRU1_R31[14]
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] /
PRU1_R31[13]
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] /
PRU1_R31[12]
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] /
PRU1_R31[11]
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] /
PRU1_R31[10]
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
W2
W1
F1
I/O
I/O
O
CP[28]
CP[28]
CP[31]
C
C
C
LCD pixel clock
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
G4
R5
F2
O
O
O
O
CP[31]
CP[31]
CP[31]
CP[31]
C
C
C
C
LCD horizontal sync
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
LCD vertical sync
LCD AC bias enable chip
select
LCD_AC_ENB_CS / GP6[0]/ / PRU1_R31[28]
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
LCD memory clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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3.7.20 Universal Host-Port Interface (UHPI)
Table 3-22. Universal Host-Port Interface (UHPI) Terminal Functions
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
U18
V16
R14
W16
V17
W17
W18
W19
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / PRU0_R31[23]
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / PRU1_R31[29]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
C
C
C
C
C
C
C
C
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7]/PRU0_R30[15] /
PRU0_R31[15]
V18
V19
U19
T16
R18
R19
I/O
I/O
I/O
I/O
I/O
I/O
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
C
C
C
C
C
C
UHPI data bus
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
PRU0_R31[14]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9] R15
I/O
CP[27]
CP[27]
CP[24]
CP[24]
C
C
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
P17
U17
W15
I/O
I
I
UHPI access control
UHPI half-word
identification control
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]
U16
T15
I
I
CP[24]
CP[24]
C
C
PRU0_R30[26] /UHPI_HRW / UPP_CHA_WAIT /
GP6[8]/PRU1_R31[17]
UHPI read/write
UHPI chip select
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] / UPP_2xTXCLK W14
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15
I
I
CP[25]
CP[25]
CP[22]
CP[23]
CP[23]
CP[21]
C
C
C
C
C
C
UHPI data strobe
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]
PRU0_R30[31] /UHPI_HRDY / PRU1_R30[12] /GP6[13]
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]
T18
R16
R17
T17
I
I
UHPI host interrupt
UHPI ready
O
I
UHPI address strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
44
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3.7.21 Universal Parallel Port (uPP)
Table 3-23. Universal Parallel Port (uPP) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
VP_CLKIN0 / UHPI_HCS1 /PRU1_R30[10] / GP6[7] /
UPP_2xTXCLK
uPP 2x transmit clock
input
W14
I
CP[25]
CP[30]
CP[30]
CP[30]
CP[30]
C
PRU0_R30[25] /MMCSD1_DAT[0] / UPP_CHB_CLOCK /
GP8[15]/PRU1_R31[27]
G1
G2
J4
I/O
I/O
I/O
I/O
C
C
C
C
uPP channel B clock
uPP channel B start
uPP channel B enable
uPP channel B wait
PRU0_R30[24]/ MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE /
GP8[13]/PRU1_R31[25]
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12]/
PRU1_R31[24]
G3
PRU0_R30[29] /UHPI_CNTL0 / UPP_CHA_CLOCK / GP6[11]
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]
U17
W15
U16
I/O
I/O
I/O
CP[24]
CP[24]
CP[24]
C
C
C
uPP channel A clock
uPP channel A start
uPP channel A enable
PRU0_R30[26] /UHPI_HRW / UPP_CHA_WAIT / GP6[8] /
PRU1_R31[17]
T15
I/O
CP[24]
C
uPP channel A wait
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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Table 3-23. Universal Parallel Port (uPP) Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
U2
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] /
I/O
I/O
I/O
I/O
I/O
I/O
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
C
C
C
C
C
C
PRU1_R31[15]
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] /
U1
V3
V2
V1
W3
PRU1_R31[14]
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] /
PRU1_R31[13]
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] /
PRU1_R31[12]
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] /
PRU1_R31[11]
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] /
PRU1_R31[10]
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / PRU0_R31[23]
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / PRU1_R31[29]
W2
W1
P4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[28]
CP[28]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
R3
R2
R1
T3
T2
T1
U3
uPP data bus
U18
V16
R14
W16
V17
W17
W18
W19
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7]/PRU0_R30[15] /
PRU0_R31[15]
V18
V19
U19
T16
R18
R19
I/O
I/O
I/O
I/O
I/O
I/O
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
C
C
C
C
C
C
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
PRU0_R31[14]
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] /PRU0_R30[13] /
PRU0_R31[13]
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /
PRU0_R31[12]
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /
PRU0_R31[11]
VP_DIN[10] / UHPI_HD[2] / UPP_D[2]/ PRU0_R30[10] /
PRU0_R31[10]
VP_DIN[9] / UHPI_HD[1] / UPP_D[1]/ PRU0_R30[9] /
PRU0_R31[9]
R15
P17
I/O
I/O
CP[27]
CP[27]
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
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3.7.22 Video Port Interface (VPIF)
Table 3-24. Video Port Interface (VPIF) Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
VIDEO INPUT
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /
UPP_2xTXCLK
VPIF capture channel 0
input clock
W14
I
I
I
I
I
I
I
I
I
CP[25]
CP[25]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
CP[27]
C
C
C
C
C
C
C
C
C
VPIF capture channel 1
input clock
VP_CLKIN1 / UHPI_HDS1/PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /
PRU0_R31[15]
V18
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
PRU0_R31[14]
V19
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /
PRU0_R31[13]
U19
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /
PRU0_R31[12]
T16
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /
PRU0_R31[11]
R18
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /
PRU0_R31[10]
R19
VPIF capture data bus
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] /
PRU0_R31[9]
R15
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / PRU0_R31[29]
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / PRU0_R31[28]
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / PRU0_R31[27]
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / PRU0_R31[26]
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / PRU0_R31[25]
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / PRU0_R31[24]
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / PRU0_R31[23]
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / PRU1_R31[29]
P17
U18
V16
R14
W16
V17
W17
W18
W19
I
I
I
I
I
I
I
I
I
CP[27]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
CP[26]
C
C
C
C
C
C
C
C
C
VIDEO OUTPUT
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
VPIF display channel 2
input clock
H3
I
CP[30]
CP[30]
CP[30]
CP[30]
C
C
C
C
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
VPIF display channel 2
output clock
K3
J3
O
I
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
VPIF display channel 3
input clock
VPIF display channel 3
output clock
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
K4
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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Table 3-24. Video Port Interface (VPIF) Terminal Functions (continued)
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
P4
R3
R2
R1
T3
VP_DOUT[15] / LCD_D[15] /UPP_XD[7] / GP7[7] / BOOT[7]
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
VP_DOUT[13] / LCD_D[13] /UPP_XD[5] / GP7[5] / BOOT[5]
VP_DOUT[12] / LCD_D[12] /UPP_XD[4] / GP7[4] / BOOT[4]
VP_DOUT[11] / LCD_D[11] /UPP_XD[3] / GP7[3] / BOOT[3]
VP_DOUT[10] / LCD_D[10] /UPP_XD[2] / GP7[2] / BOOT[2]
VP_DOUT[9] / LCD_D[9] /UPP_XD[1] / GP7[1] / BOOT[1]
VP_DOUT[8] / LCD_D[8] /UPP_XD[0] / GP7[0] / BOOT[0]
VP_DOUT[7] / LCD_D[7] /UPP_XD[15] / GP7[15] / PRU1_R31[15]
VP_DOUT[6] / LCD_D[6] /UPP_XD[14] / GP7[14] / PRU1_R31[14]
VP_DOUT[5] / LCD_D[5] /UPP_XD[13] / GP7[13] / PRU1_R31[13]
VP_DOUT[4] / LCD_D[4] /UPP_XD[12] / GP7[12] / PRU1_R31[12]
VP_DOUT[3] / LCD_D[3] /UPP_XD[11] / GP7[11] / PRU1_R31[11]
VP_DOUT[2] / LCD_D[2] /UPP_XD[10] / GP7[10] / PRU1_R31[10]
VP_DOUT[1] / LCD_D[1] /UPP_XD[9] / GP7[9] / PRU1_R31[9]
VP_DOUT[0] /LCD_D[0] /UPP_XD[8] / GP7[8] / PRU1_R31[8]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T2
T1
U3
U2
U1
V3
V2
V1
W3
W2
W1
VPIF display data bus
48
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3.7.23 General Purpose Input Output
Table 3-25. General Purpose Input Output Terminal Functions
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
GP0
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]
AFSR / GP0[13] / PRU0_R31[20]
A1
B1
C2
B2
I/O
I/O
I/O
I/O
CP[0]
CP[0]
CP[0]
CP[0]
A
A
A
A
AFSX / GP0[12] /PRU0_R31[19]
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] /
PRU0_R31[18]
A2
A3
I/O
I/O
CP[0]
CP[0]
A
A
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /
PRU0_R31[17]
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
AXR14 / CLKR1 / GP0[6]
D5
F4
A4
B4
B3
C4
C5
D4
C3
E4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[0]
CP[0]
CP[1]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[2]
CP[3]
A
A
A
A
A
A
A
A
A
A
GPIO Bank 0
AXR13 / CLKX1 / GP0[5]
AXR12 / FSR1 / GP0[4]
AXR11 / FSX1 / GP0[3]
AXR10 / DR1 / GP0[2]
AXR9 / DX1 / GP0[1]
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]
GP1
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]
AXR5 / CLKX0 / GP1[13]
D2
C1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[4]
CP[5]
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D3
CP[5]
AXR4 / FSR0 / GP1[12]
D1
CP[5]
AXR3 / FSX0 / GP1[11]
E3
CP[5]
AXR2 / DR0 / GP1[10]
E2
CP[5]
AXR1 / DX0 / GP1[9]
E1
CP[5]
SPI0_CLK / EPWM0A / GP1[8]
D19
E16
D17
G16
G18
F17
F16
E18
F19
CP[7]
GPIO Bank 1
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / TM64P0_IN12
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / TM64P1_IN12
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]
SPI1_SCS[3] / UART1_RXD / GP1[1]
SPI1_SCS[2] / UART1_TXD / GP1[0]
CP[10]
CP[10]
CP[11]
CP[11]
CP[12]
CP[12]
CP[13]
CP[13]
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a
pull-up, an external pull-up can be used.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
GP2
SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12 F18
SPI1_SCS[0] / EPWM1B / PRU0_R30[8] / GP2[14] / TM64P3_IN12 E19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[14]
CP[14]
CP[15]
CP[15]
CP[15]
CP[15]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
SPI1_CLK / GP2[13]
G19
H16
H17
G17
A15
C15
B7
SPI1_ENA / GP2[12]
SPI1_SOMI / GP2[11]
SPI1_SIMO / GP2[10]
EMA_BA[1] / GP2[9]
EMA_BA[0] / GP2[8]
GPIO Bank 2
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]
EMA_WEN_DQM[0] / GP2[3]
D8
A16
A9
C8
EMA_WEN_DQM[1] / GP2[2]
A5
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]
EMA_CS[0] / GP2[0]
B19
A18
GP3
EMA_CS[2] / GP3[15]
EMA_CS[3] / GP3[14]
EMA_CS[4] / GP3[13]
EMA_CS[5] / GP3[12]
EMA_WE / GP3[11]
B17
A17
F9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B16
B9
EMA_OE / GP3[10]
B15
D10
B18
E6
EMA_A_RW / GP3[9]
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]
EMA_D[15] / GP3[7]
GPIO Bank 3
EMA_D[14] / GP3[6]
C7
EMA_D[13] / GP3[5]
B6
EMA_D[12] / GP3[4]
A6
EMA_D[11] / GP3[3]
D6
EMA_D[10] / GP3[2]
A7
EMA_D[9] / GP3[1]
D9
EMA_D[8] / GP3[0]
E10
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
GP4
EMA_D[7] / GP4[15]
EMA_D[6] / GP4[14]
EMA_D[5] / GP4[13]
EMA_D[4] / GP4[12]
EMA_D[3] / GP4[11]
EMA_D[2] / GP4[10]
EMA_D[1] / GP4[9]
EMA_D[0] / GP4[8]
D7
C6
E7
B5
E8
B8
A8
C9
E9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[17]
CP[18]
B
B
B
B
B
B
B
B
B
MMCSD0_CLK / PRU1_R30[31] / GP4[7] / PRU1_R31[23]
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] /
PRU1_R31[22]
GPIO Bank 4
A10
B10
A11
C10
E11
I/O
I/O
I/O
I/O
I/O
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
B
B
B
B
B
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] /
PRU1_R31[21]
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] /
PRU1_R31[20]
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] /
PRU1_R31[19]
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] /
PRU1_R31[18]
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]
B11
E12
I/O
I/O
CP[18]
CP[18]
B
B
GP5
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15]
EMA_A[14] / MMCSD0_DAT[7] /PRU1_R30[22] / GP5[14]
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13]
EMA_A[12] / PRU1_R30[20] / GP5[12]
EMA_A[11] / PRU1_R30[19] / GP5[11]
EMA_A[10] / PRU1_R30[18] / GP5[10]
EMA_A[9] / PRU1_R30[17] / GP5[9]
EMA_A[8] / PRU1_R30[16] / GP5[8]
EMA_A[7] / PRU1_R30[15] / GP5[7]
EMA_A[6] / GP5[6]
C11
A12
D11
D13
B12
C12
D12
A13
B13
E13
C13
A14
D14
B14
D15
C14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
GPIO Bank 5
EMA_A[5] / GP5[5]
EMA_A[4] / GP5[4]
EMA_A[3] / GP5[3]
EMA_A[2] / GP5[2]
EMA_A[1] / GP5[1]
EMA_A[0] / GP5[0]
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
GP6
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]
T17
T18
R17
R16
U17
W15
U16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[21]
CP[22]
CP[23]
CP[23]
CP[24]
CP[24]
CP[24]
C
C
C
C
C
C
C
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] /
PRU1_R31[17]
T15
I/O
I/O
CP[24]
CP[25]
C
C
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /
UPP_2xTXCLK
W14
GPIO Bank 6
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] /
PRU1_R31[16]
V15
P17
H3
I/O
I/O
I/O
CP[25]
CP[27]
CP[30]
C
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /
PRU1_R31[4]
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /
PRU1_R31[3]
K3
J3
I/O
I/O
CP[30]
CP[30]
C
C
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /
PRU1_R31[2]
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
LCD_AC_ENB_CS / GP6[0] / PRU1_R31[28]
K4
R5
I/O
I/O
CP[30]
CP[31]
C
C
GP7
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15] U2
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14] U1
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13] V3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[28]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
CP[29]
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]
V2
V1
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] W3
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] /PRU1_R31[8]
VP_DOUT[15/]/ LCD_D[15]/ UPP_XD[7] / GP7[7] / BOOT[7]
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]
W2
W1
P4
R3
R2
R1
T3
T2
T1
U3
GPIO Bank 7
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
SIGNAL
NAME
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NO.
GP8
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]
/ PRU1_R31[27]
G1
G2
J4
I/O
I/O
I/O
CP30]
CP[30]
CP[30]
C
C
C
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
PRU1_R31[25]
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3
F1
F2
I/O
I/O
I/O
CP[30]
CP[31]
CP[31]
C
C
C
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4
G4
I/O
I/O
CP[31]
CP[31]
C
C
GPIO Bank 8
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0
SPI0_SOMI /EPWMSYNCI / GP8[6]
SPI0_SIMO / EPWMSYNCO / GP8[5]
SPI0_SCS[5] / UART0_RXD / GP8[4]
SPI0_SCS[4] / UART0_TXD / GP8[3]
SPI0_SCS[3] / UART0_CTS / GP8[2]
SPI0_SCS[2] / UART0_RTS / GP8[1]
F3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CP[6]
CP[7]
CP[7]
CP[8]
CP[8]
CP[9]
CP[9]
IPD
A
A
A
A
A
A
A
B
C16
C18
C19
D18
E17
D16
K17
(1)
GP8[0]
(1) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
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3.7.24 Reserved and No Connect
Table 3-26. Reserved and No Connect Terminal Functions
SIGNAL
NAME
TYPE(1)
DESCRIPTION
NO.
T19
Reserved. For proper device operation, this pin must be tied either directly to
CVDD or left unconnected (do not connect to ground).
RSV2
NC
PWR
M3, M14, N16
J17
—
I
No connect (Leave unconnected, do not connect to power or ground.)
Reserved. For proper device operation, the pin must be pulled up to supply
DVDD3318_B.
RSVDN
(1) PWR = Supply voltage.
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3.7.25 Supply and Ground
Table 3-27. Supply and Ground Terminal Functions
SIGNAL
NAME
TYPE(1)
DESCRIPTION
NO.
E15, G7, G8,
G13, H6, H7,
H10, H11,
CVDD (Core supply)
H12, H13, J6,
J12, K6, K12,
L12, M8, M9,
N8
PWR
Variable (1.2V - 1.0V) core supply voltage pins
RVDD (Internal RAM supply)
DVDD18 (I/O supply)
E5, H14, N7
PWR
PWR
1.2V internal ram supply voltage pins
1.8V I/O supply voltage pins
F14, G6, G10,
G11, G12,
J13, K5, L6,
P13, R13
F5, F15, G5,
G14, G15, H5
DVDD3318_A (I/O supply)
DVDD3318_B (I/O supply)
PWR
PWR
1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group A
1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group B
E14, F6, F7,
F8, F10, F11,
F12, F13, G9,
J14, K15
J5, K13, L4,
L13, M13,
N13, P5, P6,
P12, R4
DVDD3318_C (I/O supply)
PWR
GND
1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group C
A19, H8, H9,
H15, J7, J8,
J9, J10, J11,
K7, K8, K9,
K10, K11, L5,
L7, L8, L9,
VSS (Ground)
Ground pins.
L10, L11, M4,
M5, M6, M7,
M10, M11, N5,
N11, N12, P11
(1) PWR = Supply voltage, GND - Ground.
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4 Device Configuration
4.1 Boot Modes
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This device supports a variety of boot modes through an internal ARM ROM bootloader. This device does
not support dedicated hardware boot modes. The input states of the BOOT pins are sampled and latched
into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device
reset is deasserted. Boot mode selection is determined by the values of the BOOT pins.
See Using the OMAP-L1x8 Bootloader Application Report (SPRAB41) for more details on the ROM Boot
Loader.
The following boot modes are supported:
•
NAND Flash boot
8-bit NAND
NOR Flash boot
–
•
–
–
–
NOR Direct boot (8-bit or 16-bit)
NOR Legacy boot (8-bit or 16-bit)
NOR AIS boot (8-bit or 16-bit)
•
•
HPI Boot
I2C0/I2C1 Boot
–
–
EEPROM (Master Mode)
External Host (Slave Mode)
•
•
SPI0/ SPI1 Boot
–
–
–
Serial Flash (Master Mode)
SERIAL EEPROM (Master Mode)
External Host (Slave Mode)
UART0/UART1/UART2 Boot
External Host
–
4.2 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
•
•
•
•
•
•
Readable Device, Die, and Chip Revision ID
Control of Pin Multiplexing
Priority of bus accesses different bus masters in the system
Capture at power on reset the chip BOOT pin values and make them available to software
Control of the DeepSleep power management function
Enable and selection of the programmable pin pullups and pulldowns
Special case settings for peripherals:
–
–
–
–
–
Locking of PLL controller settings
Default burst sizes for EDMA3 transfer controllers
Selection of the source for the eCAP module input capture (including on chip sources)
McASP AMUTEIN selection and clearing of AMUTE status for the McASP
Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
–
–
Clock source selection for EMIFA
DDR2 Controller PHY settings
•
Selects the source of emulation suspend signal (from ARM) of peripherals supporting this function.
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Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
•
A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
•
Additionally, many registers are accessible only by a host (ARM) when it is operating in its privileged
mode. (ex. from the kernel, but not from user space code).
Table 4-1. System Configuration (SYSCFG) Module Register Access
Register Address
0x01C1 4000
0x01C14008
0x01C1400C
0x01C14010
0x01C14014
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
0x01C1 4158
0x01C1 415C
0x01C1 4160
0x01C1 4164
0x01C1 4168
0x01C1 416C
Register Name
REVID
Register Description
Revision Identification Register
Register Access
—
DIEIDR0
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
Boot Configuration Register
—
DIEIDR1
—
DIEIDR2
—
DIEIDR3
—
BOOTCFG
KICK0R
Privileged mode
Privileged mode
Privileged mode
—
Kick 0 Register
KICK1R
Kick 1 Register
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
IENCLR
Interrupt Enable Clear Register
End of Interrupt Register
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
PINMUX4
PINMUX5
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
PINMUX13
PINMUX14
PINMUX15
PINMUX16
PINMUX17
PINMUX18
PINMUX19
Fault Address Register
Fault Status Register
Master Priority 0 Registers
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Master Priority 1 Registers
Master Priority 2 Registers
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
Pin Multiplexing Control 4 Register
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Pin Multiplexing Control 13 Register
Pin Multiplexing Control 14 Register
Pin Multiplexing Control 15 Register
Pin Multiplexing Control 16 Register
Pin Multiplexing Control 17 Register
Pin Multiplexing Control 18 Register
Pin Multiplexing Control 19 Register
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Table 4-1. System Configuration (SYSCFG) Module Register Access (continued)
Register Address
0x01C1 4170
0x01C1 4174
0x01C1 4178
0x01C1 417C
0x01C1 4180
0x01C1 4184
0x01C1 4188
0x01C1 418C
0x01E2 C000
0x01E2 C004
0x01E2 C008
0x01E2 C00C
0x01E2 C010
0x01E2 C014
0x01E2 C018
Register Name
SUSPSRC
Register Description
Suspend Source Register
Register Access
Privileged mode
—
Reserved
Reserved
—
CFGCHIP0
CFGCHIP1
CFGCHIP2
CFGCHIP3
CFGCHIP4
VTPIO_CTL
DDR_SLEW
DeepSleep
PUPD_ENA
PUPD_SEL
RXACTIVE
PWRDN
Chip Configuration 0 Register
Chip Configuration 1 Register
Chip Configuration 2 Register
Chip Configuration 3 Register
Chip Configuration 4 Register
VTPIO COntrol Register
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
DDR Slew Register
DeepSleep Register
Pullup / Pulldown Enable Register
Pullup / Pulldown Selection Register
RXACTIVE Control Register
PWRDN Control Register
58
Device Configuration
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4.3 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the IO supply rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
•
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
•
•
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see , Recommended Operating Conditions.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range
(1)
(Unless Otherwise Noted)
Core Logic, Variable and Fixed
-0.5 V to 1.4 V
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA , PLL1_VDDA ,
(2)
USB_CVDD )
Supply voltage ranges
I/O, 1.8V
(USB0_VDDA18, DDR_DVDD18)
-0.5 V to 2 V
-0.5 V to 3.8V
(2)
I/O, 3.3V
(2)
(DVDD3318_A, DVDD3318_B, DVDD3318_C, USB0_VDDA33)
Oscillator inputs (OSCIN, RTC_XI), 1.2V
-0.3 V to CVDD + 0.3V
-0.3V to DVDD + 0.3V
Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Steady State)
Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Transient)
DVDD + 20%
up to 20% of Signal
Period
Input voltage (VI) ranges
USB 5V Tolerant IOs:
5.25V(3)
(USB0_DM, USB0_DP, USB0_ID)
USB0 VBUS Pin
5.50V(3)
Dual-voltage LVCMOS outputs, 3.3V or 1.8V
(Steady State)
-0.5 V to DVDD + 0.3V
Output voltage (VO) ranges
Clamp Current
Dual-voltage LVCMOS outputs, 3.3V or 1.8V
(Transient)
DVDD + 20%
up to 20% of Signal
Period
Input or Output Voltages 0.3V above or below their respective power
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
±20mA
Commercial (default)
Extended (A version)
(default)
0°C to 90°C
-40°C to 105°C
-55°C to 150°C
Operating Junction Temperature ranges,
TJ
Storage temperature range, Tstg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a maximum of 24 hours.
60
Device Operating Conditions
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5.2 Recommended Operating Conditions
NAME
DESCRIPTION
CONDITION
MIN
1.25
1.14
1.05
0.95
1.14
0.9
NOM
1.3
MAX
1.35
1.32
1.16
1.05
1.32
1.32
1.32
1.32
1.32
1.89
3.45
1.89
UNIT
V
CVDD
Core Logic Supply Voltage (variable) 1.3V operating point
1.2V operating point
1.2 or 1.26
1.1
V
1.1V operating point
V
1.0V operating point
1.0
V
RVDD
Internal RAM Supply Voltage
RTC Core Logic Supply Voltage
PLL0 Supply Voltage
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.2 or 1.26
1.8
V
(1)
RTC_CVDD
PLL0_VDDA
PLL1_VDDA
USB_CVDD
V
1.14
1.14
1.14
1.71
3.15
1.71
V
PLL1 Supply Voltage
V
USB0 Core Logic Supply Voltage
USB0 PHY Supply Voltage
USB0 PHY Supply Voltage
DDR2 PHY Supply Voltage
V
USB0_VDDA18
USB0_VDDA33
DDR_DVDD18
V
3.3
V
Supply
Voltage
1.8
V
0.5*
DDR_DVDD1
8
0.49*
DDR_DVDD18
0.51*
DDR_DVDD18
DDR_VREF
DDR2/mDDR reference voltage
V
V
DDR2/mDDR impedance control,
connected via 50Ω resistor to Vss
DDR_ZP
Vss
1.8V operating point
1.71
3.15
1.71
3.15
1.71
3.15
1.8
3.3
1.8
3.3
1.8
3.3
1.89
3.45
1.89
3.45
1.89
3.45
V
V
V
V
V
V
Power Group A Dual-voltage IO
Supply Voltage
DVDD3318_A
3.3V operating point
1.8V operating point
Power Group B Dual-voltage IO
Supply Voltage
DVDD3318_B
3.3V operating point
1.8V operating point
Power Group C Dual-voltage IO
Supply Voltage
DVDD3318_C
VSS
3.3V operating point
Supply
Ground
Core Logic Digital Ground
V
PLL0_VSSA
PLL1_VSSA
OSCVSS(2)
RTC_VSS(2)
USB0_VSSA
USB0_VSSA33
PLL0 Ground
V
V
V
V
V
V
PLL1 Ground
Oscillator Ground
RTC Oscillator Ground
USB0 PHY Ground
USB0 PHY Ground
0
2
0
0
Voltage
Input High
VIH
High-level input voltage, Dual-voltage I/O, 3.3V(3)
V
(3)
High-level input voltage, Dual-voltage I/O, 1.8V
0.65*DVDD
0.8*RTC_CVDD
0.8*CVDD
V
V
V
V
V
V
V
V
High-level input voltage, RTC_XI
High-level input voltage, OSCIN
VIL
Low-level input voltage, Dual-voltage I/O, 3.3V(3)
0.8
0.35*DVDD
0.2*RTC_CVDD
0.2*CVDD
5.25
Voltage
(3)
Input Low
Low-level input voltage, Dual-voltage I/O, 1.8V
Low-level input voltage, RTC_XI
Low-level input voltage, OSCIN
USB external charge pump input
USB
USB0_VBUS
tt
0
Transition
Time
Transition time, 10%-90%, All Inputs (unless otherwise
specified in the electrical data sections)
(4)
0.25P
ns
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(3) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and
adhere to the JESD79-2A standard.
(4) Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity
on input signals.
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Recommended Operating Conditions (continued)
NAME
DESCRIPTION
CONDITION
MIN
0
NOM
MAX
456
UNIT
CVDD = 1.3V
operating point
CVDD = 1.2V
operating point
0
0
0
0
0
0
0
375
200
100
456
375
200
100
Commercial temperature grade
(default)
MHz
CVDD = 1.1V
operating point
CVDD = 1.0V
operating point
Operating
Frequency
FPLL0_SYSCLK6
CVDD = 1.3V
operating point
CVDD = 1.2V
operating point
Extended temperature grade (A
suffix)
MHz
CVDD = 1.1V
operating point
CVDD = 1.0V
operating point
62
Device Operating Conditions
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Low/full speed:
USB0_DM and USB0_DP
2.8
USB0_VDDA33
High speed:
USB_DM and USB_DP
360
440
mV
DVDD= 3.15V, IOH = -4 mA
2.4
V
V
High-level output voltage
VOH
(dual-voltage LVCMOS IOs at 3.3V)(1)
DVDD= 3.15V, IOH = -100 mA
2.95
High-level output voltage
DVDD= 1.65V, IOH = -2 mA
DVDD-0.45
V
V
(dual-voltage LVCMOS IOs at 1.8V)(1)
Low/full speed:
USB_DM and USB_DP
0.0
-10
0.3
10
High speed:
USB_DM and USB_DP
mV
VOL
DVDD= 3.15V, IOL = 4mA
0.4
0.2
V
V
Low-level output voltage
(dual-voltage LVCMOS I/Os at 3.3V)
DVDD= 3.15V, IOL = 100 mA
Low-level output voltage
(dual-voltage LVCMOS I/Os at 1.8V)
DVDD= 1.65V, IOL = 2mA
0.45
±9
V
VI = VSS to DVDD without opposing
internal resistor
mA
mA
mA
mA
mA
Input current(1)
(dual-voltage LVCMOS I/Os)
VI = VSS to DVDD with opposing
70
-75
-77
310
-270
-286
-6
(3)
internal pullup resistor
(2)
II
VI = VSS to DVDD with opposing
internal pulldown resistor
(3)
VI = VSS to DVDD with opposing
internal pulldown resistor
Input current (DDR2/mDDR I/Os)
(3)
High-level output current(1)
(dual-voltage LVCMOS I/Os)
Low-level output current(1)
(dual-voltage LVCMOS I/Os)
IOH
IOL
All peripherals
All peripherals
6
mA
pF
pF
Input capacitance (dual-voltage LVCMOS)
3
3
Capacit
ance
Output capacitance (dual-voltage
LVCMOS)
(1) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and
adhere to the JESD79-2A standard.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
V
ref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
64
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
6.3 Power Supplies
6.3.1 Power-on Sequence
The device should be powered-on in the following order:
•
1) RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
•
•
2a) All variable 1.2V - 1.0V core logic supplies (CVDD)
2b) All static 1.2V logic supplies (RVDD, VDDA_12_PLL0, VDDA_12_PLL1, USB_CVDD ). If voltage
scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply
and powered up together.
•
•
3) All static 1.8V IO supplies (DVDD18, DDR_DVDD18, USB0_VDDA18 ) and any of the LVCMOS IO
supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).
4) All analog 3.3V PHY supplies (USB0_VDDA33; this is not required if USB0 is not used) and any of
the LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or
DVDD3318_C).
There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies
operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V
supplies by more than 2 volts.
RESET must be maintained active until all power supplies have reached their nominal values.
6.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V
(DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts.
There is no specific required voltage ramp down rate for any of the supplies (except as required to meet
the above mentioned voltage condition).
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6.4 Reset
6.4.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active
through the reset sequence. RESETOUT is an output for use by other controllers in the system that
indicates the device is currently in reset.
RTCK is maintained active through a POR.
A summary of the effects of Power-On Reset is given below:
•
•
•
•
•
All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC
A watchdog reset triggers a POR.
6.4.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which
remains active through the reset sequence. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
RTCK is maintained active through a POR.
A summary of the effects of Warm Reset is given below:
•
•
•
•
•
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
Internal memory is maintained through a warm reset
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the
RTC
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6.4.3 Reset Electrical Data Timings
Table 6-1 assumes testing over the recommended operating conditions.
(2)
Table 6-1. Reset Timing Requirements ((1)
,
)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
100
20
MAX MIN
MAX MIN
MAX
1
2
3
tw(RSTL)
Pulse width, RESET/TRST low
100
100
20
ns
ns
tsu(BPV-RSTH)
th(RSTH-BPV)
Setup time, boot pins valid before RESET/TRST high
Hold time, boot pins valid after RESET/TRST high
20
20
20
20
ns
td(RSTH-RESETOUTH) RESET high to RESETOUT high; Warm reset
RESET high to RESETOUT high; Power-on Reset
14
14
14
16
16
16
20
20
20
cycles(3)
4
5
td(RSTL-RESETOUTL) Delay time, RESET/TRST low to RESETOUT low
ns
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-3 for details.
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
RESET
1
TRST
4
RESETOUT
3
2
Boot Pins
Config
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
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Power Supplies Stable
OSCIN
TRST
1
RESET
5
4
RESETOUT
3
2
Config
Boot Pins
Driven or Hi-Z
Figure 6-5. Warm Reset (RESET active, TRST high) Timing
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6.5 Crystal Oscillator or External Clock Input
The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to
generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For
input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For
input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.
Typical C1, C2 values are 10-20 pF.
Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 6-7
illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
C1
OSCVSS
Figure 6-6. On-Chip Oscillator
Table 6-2. Oscillator Timing Requirements
PARAMETER
MIN
12
MAX
30
UNIT
MHz
fosc
Oscillator frequency range (OSCIN/OSCOUT)
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Clock
Input
to PLL
OSCIN
OSCOUT
NC
OSCVSS
Figure 6-7. External 1.2V Clock Source
Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock
PARAMETER
MIN
12
MAX
50
UNIT
MHz
ns
fOSCIN
OSCIN frequency range
Cycle time, external clock driven on OSCIN
tc(OSCIN)
20
tw(OSCINH) Pulse width high, external clock on OSCIN
tw(OSCINL) Pulse width low, external clock on OSCIN
0.4 tc(OSCIN)
0.4 tc(OSCIN)
ns
ns
(1)
tt(OSCIN)
tj(OSCIN)
Transition time, OSCIN
Period jitter, OSCIN
0.25P
ns
0.02P(1)
ns
(1) Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity
on input signals.
6.6 Clock PLLs
The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the
mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows
the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.
The PLL controller provides the following:
•
•
•
•
Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down
The various clock outputs given by the controller are as follows:
•
•
Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
•
Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
•
PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN
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6.6.1 PLL Device-Specific Information
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-8.
1.14V - 1.32V
50R
50R
PLLn_VDDA
0.1
µF
0.01
µF
VSS
PLLn_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0
outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have
programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology.
The PLLs are disabled by default after a device reset. They must be configured by software according to
the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by
setting PLLEN = 1.
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PLL Controller 0
PLLCTL[EXTCLKSRC]
PLL1_SYSCLK3
1
0
PLLCTL[PLLEN]
0
PLLCTL[CLKMODE]
PLLDIV1 (/1)
SYSCLK1
SYSCLK2
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
SYSCLK3
Square
1
Wave
PLLDIV2 (/2)
PLLDIV4 (/4)
PLLDIV5 (/3)
PLLDIV6 (/1)
PLLDIV7 (/6)
PLLDIV3 (/3)
OSCIN
PREDIV
PLL
POSTDIV
1
Crystal
0
PLLM
EMIFA
Internal
Clock
0
1
DIV4.5
Source
CFGCHIP3[EMA_CLKSRC]
AUXCLK
OSCDIV
PLLC0 OBSCLK
(CLKOUT Pin)
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
PLLC1 OBSCLK
OCSEL[OCSRC]
PLLCTL[PLLEN]
PLL Controller 1
PLLDIV2 (/2)
0
1
SYSCLK2
SYSCLK3
SYSCLK1
PLLDIV3 (/3)
PLLDIV1 (/1)
PLL
POSTDIV
PLLM
DDR2/mDDR
Internal
Clock
Source
14h
17h
18h
19h
SYSCLK1
SYSCLK2
SYSCLK3
OSCDIV
PLLC1 OBSCLK
OCSEL[OCSRC]
Figure 6-9. PLL Topology
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Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)
Default
Value
NO.
PARAMETER
MIN
MAX
N/A
UNIT
ns
1
PLLRST: Assertion time during initialization
N/A
N/A
/1
1000
2000 N
m
Max PLL Lock Time =
Lock time: The time that the application has to
wait for the PLL to acquire lock before setting
PLLEN, after changing PREDIV, PLLM, or
OSCIN
OSCIN
cycles
2
N/A
where N = Pre-Divider Ratio
M = PLL Multiplier
(1)
3
4
5
6
7
PREDIV: Pre-divider value
PLLREF: PLL input frequency
PLLM: PLL multiplier values
PLLOUT: PLL output frequency
POSTDIV: Post-divider value
/1
12
/32
50
ns
MHz
x20
N/A
/1
x4
x32
600(1)
/32
400
/2(1)
MHz
ns
(1) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
6.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1
manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are
responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock
inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks
from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test
points.
PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2
Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or
peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency
scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on
the application requirements. In addition, some peripherals have specific clock options independent of the
ASYNC clock domain.
6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
The processor supports multiple operating points by scaling voltage and frequency to minimize power
consumption for a given level of processor performance.
Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers
(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values
does not require relocking the PLL and provides lower latency to switch between operating points, but at
the expense of the frequencies being limited by the integer divide values (only the divide values are
altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by
changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must
relock, incurring additional latency to change between operating points. Detailed information on modifying
the PLL Controller settings can be found in SPRUGU4 - AM1806 ARM Microprocessor System Reference
Guide .
Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The
processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching
between voltage-frequency operating points, the voltage must always support the desired frequency.
When moving from a high-performance operating point to a lower performance operating point, the
frequency should be lowered first followed by the voltage. When moving from a low-performance operating
point to a higher performance operating point, the voltage should be raised first followed by the frequency.
Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained
at their nominal voltages at all operating points.
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The maximum voltage slew rate for CVdd supply changes is 1 mV/us.
For additional information on power management solutions from TI for this processor, follow the Power
Management link in the Product Folder on www.ti.com for this processor.
The processor supports multiple clock domains some of which have clock ratio requirements to each
other. PLL0_SYSCLK2:PLL0_SYSCLK4:PLL0_SYSCLK6 are synchronous to each other and the
SYSCLKn dividers must always be configured such that the ratio between these domains is 2:4:1. The
ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific
ratio requirement.
The table below summarizes the maximum internal clock frequencies at each of the voltage operating
points.
Table 6-5. Maximum Internal Clock Frequencies at Each Voltage Operating Point
CLOCK SOURCE
PLL0_SYSCLK1
CLOCK DOMAIN
Not used on this processor
1.3V NOM
-
1.2V NOM
-
1.1V NOM
-
1.0V NOM
-
SYSCLK2 clock domain peripherals and optional
clock source for ASYNC3 clock domain peripherals
PLL0_SYSCLK2
228 MHz
187.5 MHz
100 MHz
50 MHz
PLL0_SYSCLK3
PLL0_SYSCLK4
PLL0_SYSCLK5
PLL0_SYSCLK6
PLL0_SYSCLK7
Optional clock for ASYNC1 clock domain
SYSCLK4 domain peripherals
Not used on this processor
ARM subsystem
133 MHz
133 MHz
100 MHz
75 MHz
114 MHz
93.75 MHz
50 MHz
25 MHz
-
-
-
-
456 MHz
-
375 MHz
-
200 MHz
-
100 MHz
-
Not used on this processor
DDR2/mDDR Interface clock source (memory
interface clock is one-half of the value shown)
PLL1_SYSCLK1
PLL1_SYSCLK2
300 MHz
152 MHz
300 MHz
150 MHz
300 MHz
100 MHz
266 MHz
75 MHz
Optional clock source for ASYNC3 clock domain
peripherals
PLL1_SYSCLK3
McASP AUXCLK
PLL0_AUXCLK
ASYNC
Alternate clock source input to PLL Controller 0
Bypass clock source for the McASP
50 MHz
50 MHz
48 MHz
100 MHz
50 MHz
152 MHz
50 MHz
50 MHz
48 MHz
100 MHz
50 MHz
150 MHz
50 MHz
50 MHz
48 MHz
66.6 MHz
50 MHz
100 MHz
50 MHz
50 MHz
48 MHz
33.3 MHz
50 MHz
75 MHz
Bypass clock source for the USB0
ASYNC Clock Domain (EMIFA)
ASYNC2
ASYNC2 Clock Domain (multiple peripherals)
ASYNC3 Clock Domain (multiple peripherals)
ASYNC3
Some interfaces have specific limitations on supported modes/speeds at each operating point. See the
corresponding peripheral sections of this document for more information.
TI provides software components (called the Power Manager) to perform DVFS and abstract the task from
the user. The Power Manager controls changing operating points (both frequency and voltage) and
handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions
between operating points.
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6.7 Interrupts
6.7.1 ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC)
extends the number of interrupts to 100, and provides features like programmable masking, priority,
hardware nesting support, and interrupt vector generation.
6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
The ARM Interrupt controller organizes interrupts into the following hierarchy:
•
Peripheral Interrupt Requests
Individual Interrupt Sources from Peripherals
101 System Interrupts
–
•
–
One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
–
After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
•
32 Interrupt Channels
–
–
Each System Interrupt is mapped to one of the 32 Interrupt Channels
Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
–
If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
•
•
Host Interrupts (FIQ and IRQ)
–
–
Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
Debug Interrupts
–
–
Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
Sources can be selected from any of the System Interrupts or Host Interrupts
6.7.1.2 AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
6.7.1.3 AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
6.7.1.4 AINTC System Interrupt Assignments
System Interrupt assignments are listed in Table 6-6
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Table 6-6. AINTC System Interrupt Assignments
System Interrupt
Interrupt Name
COMMTX
Source
0
1
ARM
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRU_EVTOUT1
PRU_EVTOUT2
PRU_EVTOUT3
PRU_EVTOUT4
PRU_EVTOUT5
PRU_EVTOUT6
PRU_EVTOUT7
EDMA3_0_CC0_INT0
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
PRUSS Interrupt
4
5
6
7
8
9
10
11
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
43
44
45
46
EDMA3_0_CC0_ERRINT
EDMA3_0 Channel Controller 0 Error Interrupt
EDMA3_0_TC0_ERRINT
EDMA3_0 Transfer Controller 0 Error Interrupt
EMIFA_INT
EMIFA
IIC0_INT
I2C0
MMCSD0_INT0
MMCSD0 MMC/SD Interrupt
MMCSD0 SDIO Interrupt
PSC0
MMCSD0_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
RTC
SPI0_INT
SPI0
T64P0_TINT12
Timer64P0 Interrupt 12
Timer64P0 Interrupt 34
Timer64P1 Interrupt 12
Timer64P1 Interrupt 34
UART0
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
-
Reserved
PROTERR
SYSCFG Protection Shared Interrupt
Reserved
-
-
Reserved
-
Reserved
-
Reserved
EDMA3_0_TC1_ERRINT
EDMA3_0 Transfer Controller 1 Error Interrupt
Reserved
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
DDR2_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
DDR2 Controller
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
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Table 6-6. AINTC System Interrupt Assignments (continued)
System Interrupt
Interrupt Name
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
GPIO_B8INT
IIC1_INT
Source
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
GPIO Bank 8 Interrupt
I2C1
LCDC_INT
LCD Controller
UART_INT1
MCASP_INT
PSC1_ALLINT
SPI1_INT
UART1
McASP0 Combined RX / TX Interrupts
PSC1
SPI1
UHPI_ARMINT
USB0_INT
UHPI ARM Interrupt
USB0 Interrupt
-
Reserved
-
Reserved
UART2_INT
-
UART2
Reserved
EHRPWM0
HiResTimer / PWM0 Interrupt
HiResTimer / PWM0 Trip Zone Interrupt
HiResTimer / PWM1 Interrupt
HiResTimer / PWM1 Trip Zone Interrupt
Reserved
EHRPWM0TZ
EHRPWM1
EHRPWM1TZ
-
T64P2_ALL
Timer64P2 - Combined TINT12 and TINT34
ECAP0
ECAP0
ECAP1
ECAP1
ECAP2
ECAP2
MMCSD1_INT0
MMCSD1_INT1
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
T64P1_CMPINT6
T64P1_CMPINT7
ARMCLKSTOPREQ
MMCSD1 MMC/SD Interrupt
MMCSD1 SDIO Interrupt
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
Timer64P1 - Compare 6
Timer64P1 - Compare 7
PSC0
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Table 6-6. AINTC System Interrupt Assignments (continued)
System Interrupt
91
Interrupt Name
uPP_ALLINT
Source
uPP Combined Interrupt
•
•
•
•
•
•
•
•
•
•
Channel I End-of-Line Interrupt
Channel I End-of-Window Interrupt
Channel I DMA Access Interrupt
Channel I Overflow-Underrun Interrupt
Channel I DMA Programming Error Interrupt
Channel Q End-of-Line Interrupt
Channel Q End-of-Window Interrupt
Channel Q DMA Access Interrupt
Channel Q Overflow-Underrun Interrupt
Channel Q DMA Programming Error Interrupt
92
93
VPIF_ALLINT
VPIF Combined Interrupt
•
•
•
•
•
Channel 0 Frame Interrupt
Channel 1 Frame Interrupt
Channel 2 Frame Interrupt
Channel 3 Frame Interrupt
Error Interrupt
EDMA3_1_CC0_INT0
EDMA3_1 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
94
95
EDMA3_1_CC0_ERRINT
EDMA3_1_TC0_ERRINT
T64P3_ALL
EDMA3_1Channel Controller 0 Error Interrupt
EDMA3_1 Transfer Controller 0 Error Interrupt
Timer64P 3 - Combined TINT12 and TINT34
McBSP0 Receive Interrupt
96
97
MCBSP0_RINT
98
MCBSP0_XINT
McBSP0 Transmit Interrupt
99
MCBSP1_RINT
McBSP1 Receive Interrupt
100
MCBSP1_XINT
McBSP1 Transmit Interrupt
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6.7.1.5 AINTC Memory Map
Table 6-7. AINTC Memory Map
BYTE ADDRESS
0xFFFE E000
ACRONYM
DESCRIPTION
REV
Revision Register
Control Register
Reserved
0xFFFE E004
CR
0xFFFE E008 - 0xFFFE E00F
0xFFFE E010
-
GER
-
Global Enable Register
Reserved
0xFFFE E014 - 0xFFFE E01B
0xFFFE E01C
GNLR
SISR
SICR
EISR
EICR
-
Global Nesting Level Register
0xFFFE E020
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E024
0xFFFE E028
0xFFFE E02C
0xFFFE E030
0xFFFE E034
HIEISR
HIDISR
-
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Reserved
0xFFFE E038
0xFFFE E03C - 0xFFFE E04F
0xFFFE E050
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
0xFFFE E05C - 0xFFFE E07F
0xFFFE E080
-
Reserved
GPIR
GPVR
-
Global Prioritized Index Register
Global Prioritized Vector Register
Reserved
0xFFFE E084
0xFFFE E088 - 0xFFFE E1FF
0xFFFE E200
SRSR[0]
SRSR[1]
SRSR[2]
SRSR[3]
-
System Interrupt Status Raw / Set Registers
0xFFFE E204
0xFFFE E208
0xFFFE E20C
0xFFFE E210- 0xFFFE E27F
0xFFFE E280
Reserved
SECR[0]
SECR[1]
SECR[2]
SECR[3]
-
System Interrupt Status Enabled / Clear Registers
0xFFFE E284
0xFFFE E288
0xFFFE E28C
0xFFFE E290 - 0xFFFE E2FF
0xFFFE E300
Reserved
ESR[0]
ESR[1]
ESR[2]
ESR[3]
-
System Interrupt Enable Set Registers
0xFFFE E304
0xFFFE E308
0xFFFE E30C
0xFFFE E310 - 0xFFFE E37F
0xFFFE E380
Reserved
ECR[0]
ECR[1]
ECR[2]
ECR[3]
-
System Interrupt Enable Clear Registers
0xFFFE E384
0xFFFE E388
0xFFFE E38C
0xFFFE E390 - 0xFFFE E3FF
Reserved
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Table 6-7. AINTC Memory Map (continued)
BYTE ADDRESS
0xFFFE E400 - 0xFFFE E45B
0xFFFE E404
ACRONYM
CMR[0]
DESCRIPTION
Channel Map Registers
CMR[1]
CMR[2]
CMR[3]
CMR[4]
CMR[5]
CMR[6]
CMR[7]
CMR[8]
CMR[9]
CMR[10]
CMR[11]
CMR[12]
CMR[13]
CMR[14]
CMR[15]
CMR[16]
CMR[17]
CMR[18]
CMR[19]
CMR[20]
CMR[21]
CMR[22]
CMR[23]
CMR[24]
CMR[25]
-
0xFFFE E408
0xFFFE E40C
0xFFFE E410
0xFFFE E414
0xFFFE E418
0xFFFE E41C
0xFFFE E420
0xFFFE E424
0xFFFE E428
0xFFFE E42C
0xFFFE E430
0xFFFE E434
0xFFFE E438
0xFFFE E43C
0xFFFE E440
0xFFFE E444
0xFFFE E448
0xFFFE E44C
0xFFFE E450
0xFFFE E454
0xFFFE E458
0xFFFE E45C
0xFFFE E460
0xFFFE E464
0xFFFE E468 - 0xFFFE E8FF
0xFFFE E900
Reserved
HIPIR[0]
HIPIR[1]
-
Host Interrupt Prioritized Index Registers
0xFFFE E904
0xFFFE E908 - 0xFFFE EEFF
0xFFFE EF00
Reserved
DSR[0]
DSR[1]
-
Debug Select Registers
0xFFFE EF04
0xFFFE EF08 - 0xFFFE F0FF
0xFFFE F100
Reserved
HINLR[0]
HINLR[1]
-
Host Interrupt Nesting Level Registers
0xFFFE F104
0xFFFE F108 - 0xFFFE F4FF
0xFFFE F500
Reserved
HIER[0]
-
Host Interrupt Enable Register
Reserved
0xFFFE F504 - 0xFFFE F5FF
0xFFFE F600
HIPVR[0] -
HIPVR[1]
-
Host Interrupt Prioritized Vector Registers
0xFFFE F604
0xFFFE F608 - 0xFFFE FFFF
Reserved
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6.8 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
•
Provides a software interface to:
–
–
–
Control module clock enable/disable
Control module reset
Control CPU local reset
•
Supports IcePick emulation features: power, clock and reset
PSC0 controls 16 local PSCs.
PSC1 controls 32 local PSCs.
Table 6-8. Power and Sleep Controller (PSC) Registers
PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS
ACRONYM
REVID
REGISTER DESCRIPTION
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
0x01C1 0000
0x01C1 0018
0x01C1 0040
0x01E2 7000
0x01E2 7018
0x01E2 7040
INTEVAL
MERRPR0
Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
Power Error Pending Register
0x01C1 0050
0x01E2 7050
MERRCR0
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01C1 0800
0x01C1 0804
0x01C1 0808
0x01C1 080C
0x01C1 0810
0x01C1 0814
0x01C1 0818
0x01C1 081C
0x01C1 0820
0x01C1 0824
0x01C1 0828
0x01C1 082C
0x01C1 0830
0x01C1 0834
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
0x01E2 7800
0x01E2 7804
0x01E2 7808
0x01E2 780C
0x01E2 7810
0x01E2 7814
0x01E2 7818
0x01E2 781C
0x01E2 7820
0x01E2 7824
0x01E2 7828
0x01E2 782C
0x01E2 7830
0x01E2 7834
PERRPR
PERRCR
PTCMD
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
Module 0 Status Register
PTSTAT
PDSTAT0
PDSTAT1
PDCTL0
PDCTL1
PDCFG0
PDCFG1
MDSTAT0
MDSTAT1
MDSTAT2
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
Module 1 Status Register
Module 2 Status Register
Module 3 Status Register
Module 4 Status Register
Module 5 Status Register
Module 6 Status Register
Module 7 Status Register
Module 8 Status Register
Module 9 Status Register
Module 10 Status Register
Module 11 Status Register
Module 12 Status Register
Module 13 Status Register
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Table 6-8. Power and Sleep Controller (PSC) Registers (continued)
PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS
ACRONYM
MDSTAT14
REGISTER DESCRIPTION
Module 14 Status Register
0x01C1 0838
0x01E2 7838
0x01E2 783C
0x01E2 7840
0x01E2 7844
0x01E2 7848
0x01E2 784C
0x01E2 7850
0x01E2 7854
0x01E2 7858
0x01E2 785C
0x01E2 7860
0x01E2 7864
0x01E2 7868
0x01E2 786C
0x01E2 7870
0x01E2 7874
0x01E2 7878
0x01E2 787C
0x01E2 7A00
0x01E2 7A04
0x01E2 7A08
0x01E2 7A0C
0x01E2 7A10
0x01E2 7A14
0x01E2 7A18
0x01E2 7A1C
0x01E2 7A20
0x01E2 7A24
0x01E2 7A28
0x01E2 7A2C
0x01E2 7A30
0x01E2 7A34
0x01E2 7A38
0x01E2 7A3C
0x01E2 7A40
0x01E2 7A44
0x01E2 7A48
0x01E2 7A4C
0x01E2 7A50
0x01E2 7A54
0x01E2 7A58
0x01E2 7A5C
0x01E2 7A60
0x01E2 7A64
0x01E2 7A68
0x01E2 7A6C
0x01E2 7A70
0x01C1 083C
MDSTAT15
MDSTAT16
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
MDSTAT28
MDSTAT29
MDSTAT30
MDSTAT31
MDCTL0
Module 15 Status Register
Module 16 Status Register
Module 17 Status Register
Module 18 Status Register
Module 19 Status Register
Module 20 Status Register
Module 21 Status Register
Module 22 Status Register
Module 23 Status Register
Module 24 Status Register
Module 25 Status Register
Module 26 Status Register
Module 27 Status Register
Module 28 Status Register
Module 29 Status Register
Module 30 Status Register
Module 31 Status Register
Module 0 Control Register
Module 1 Control Register
Module 2 Control Register
Module 3 Control Register
Module 4 Control Register
Module 5 Control Register
Module 6 Control Register
Module 7 Control Register
Module 8 Control Register
Module 9 Control Register
Module 10 Control Register
Module 11 Control Register
Module 12 Control Register
Module 13 Control Register
Module 14 Control Register
Module 15 Control Register
Module 16 Control Register
Module 17 Control Register
Module 18 Control Register
Module 19 Control Register
Module 20 Control Register
Module 21 Control Register
Module 22 Control Register
Module 23 Control Register
Module 24 Control Register
Module 25 Control Register
Module 26 Control Register
Module 27 Control Register
Module 28 Control Register
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x01C1 0A00
0x01C1 0A04
MDCTL1
0x01C1 0A08
MDCTL2
0x01C1 0A0C
MDCTL3
0x01C1 0A10
MDCTL4
0x01C1 0A14
MDCTL5
0x01C1 0A18
MDCTL6
0x01C1 0A1C
MDCTL7
0x01C1 0A20
MDCTL8
0x01C1 0A24
MDCTL9
0x01C1 0A28
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
MDCTL16
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
0x01C1 0A2C
0x01C1 0A30
0x01C1 0A34
0x01C1 0A38
0x01C1 0A3C
-
-
-
-
-
-
-
-
-
-
-
-
-
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Table 6-8. Power and Sleep Controller (PSC) Registers (continued)
PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS
ACRONYM
MDCTL29
REGISTER DESCRIPTION
Module 29 Control Register
-
-
-
0x01E2 7A74
0x01E2 7A78
0x01E2 7A7C
MDCTL30
MDCTL31
Module 30 Control Register
Module 31 Control Register
6.8.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-9 and Table 6-10 lists the set of peripherals/modules that are controlled by the PSC,
the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.8.1.1.
Table 6-9. PSC0 Default Module Configuration
LPSC
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
Number
0
1
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
EMIFA (Br7)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Enable
—
—
2
—
3
—
4
SPI 0
—
5
MMC/SD 0
—
6
ARM Interrupt Controller
ARM RAM/ROM
—
—
7
Yes
—
8
—
9
UART 0
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
Enable
—
10
11
12
13
14
15
SCR0 (Br 0, Br 1, Br 2, Br 8)
SCR1 (Br 4)
Yes
Yes
Yes
—
Enable
SCR2 (Br 3, Br 5, Br 6)
PRUSS
Enable
SwRstDisable
SwRstDisable
—
ARM
—
—
—
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Table 6-10. PSC1 Default Module Configuration
LPSC
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
Number
0
EDMA3 Channel Controller 1
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
1
USB0 (USB2.0)
—
2
—
—
3
GPIO
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
—
4
UHPI
—
5
—
—
6
DDR2 (and SCR_F3)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
—
—
7
McASP0 ( + McASP0 FIFO)
—
8
SATA
—
8
—
—
9
VPIF
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SPI 1
—
I2C 1
—
UART 1
—
UART 2
—
McBSP0 ( + McBSP0 FIFO)
McBSP1 ( + McBSP1 FIFO)
LCDC
—
—
—
eHRPWM0/1
—
MMCSD1
—
uPP
—
ECAP0/1/2
—
EDMA3 Transfer Controller 2
—
—
—
—
—
—
—
SCR_F0 (and bridge F0)
SCR_F1 (and bridge F1)
SCR_F2 (and bridge F2)
SCR_F6 (and bridge F3)
SCR_F7 (and bridge F4)
SCR_F8 (and bridge F5)
Bridge F7 (DDR Controller path)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
PD_SHRAM
Enable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Enable
Enable
Enable
Enable
Enable
Enable
On-chip RAM (including SCR_F4
and bridge F6)
Enable
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6.8.1.1 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-11.
Table 6-11. Module States
Module State
Enable
Module Reset
De-asserted
Module Clock Module State Definition
On
A module in the enable state has its module reset de-asserted and it has its clock on.
This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its module
clock off. This state is typically used for disabling a module clock to save power. The
device is designed in full static CMOS, so when you stop a module clock, it retains the
module’s state. When the clock is restarted, the module resumes operating from the
stopping point.
SyncReset
Asserted
Asserted
On
Off
A module state in the SyncReset state has its module reset asserted and it has its
clock on. Generally, software is not expected to initiate this state
SwRstDisable
A module in the SwResetDisable state has its module reset asserted and it has its
clock disabled. After initial power-on, several modules come up in the SwRstDisable
state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its module
clock disabled, similar to the Disable state. However this is a special state, once a
module is configured in this state by software, it can “automatically” transition to
“Enable” state whenever there is an internal read/write request made to it, and after
servicing the request it will “automatically” transition into the sleep state (with module
reset re de-asserted and module clock disabled), without any software intervention.
The transition from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are fully
operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its module
clock disabled, similar to the Disable state. However this is a special state, once a
module is configured in this state by software, it will “automatically” transition to
“Enable” state whenever there is an internal read/write request made to it, and will
remain in the “Enabled” state from then on (with module reset re de-asserted and
module clock on), without any software intervention. The transition from sleep to
enabled state has some cycle latency associated with it. It is not envisioned to use this
mode when peripherals are fully operational and moving data.
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6.9 EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses.
6.9.1 EDMA3 Channel Synchronization Events
Each EDMA channel controller supports up to 32 channels which service peripherals and memory.
Table 6-12lists the source of the EDMA synchronization events associated with each of the programmable
EDMA channels.
Table 6-12. EDMA Synchronization Events
EDMA0 Channel Controller 0
Event
0
Event Name / Source
McASP0 Receive
McASP0 Transmit
McBSP0 Receive
McBSP0 Transmit
McBSP1 Receive
McBSP1 Transmit
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event Name / Source
MMCSD0 Receive
MMCSD0 Transmit
SPI1 Receive
1
2
3
SPI1 Transmit
4
PRU_EVTOUT6
PRU_EVTOUT7
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
5
6
7
8
9
UART0 Transmit
I2C0 Transmit
10
11
12
13
14
15
Timer64P0 Event Out 12
Timer64P0 Event Out 34
UART1 Receive
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART2 Transmit
UART1 Transmit
SPI0 Receive
SPI0 Transmit
EDMA1 Channel Controller 1
Event Name / Source
Event
0
Event
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Event Name / Source
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
GPIO Bank 8 Interrupt
Reserved
Timer64P2 Compare Event 0
Timer64P2 Compare Event 1
Timer64P2 Compare Event 2
Timer64P2 Compare Event 3
Timer64P2 Compare Event 4
Timer64P2 Compare Event 5
Timer64P2 Compare Event 6
Timer64P2 Compare Event 7
Timer64P3 Compare Event 0
Timer64P3 Compare Event 1
Timer64P3 Compare Event 2
Timer64P3 Compare Event 3
Timer64P3 Compare Event 4
Timer64P3 Compare Event 5
Timer64P3 Compare Event 6
Timer64P3 Compare Event 7
1
2
3
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
Timer64P2 Event Out 12
Timer64P2 Event Out 34
Timer64P3 Event Out 12
Timer64P3 Event Out 34
MMCSD0 Receive
MMCSD0 Transmit
Reserved
9
10
11
12
13
14
15
Reserved
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6.9.2 EDMA Peripheral Register Descriptions
Table 6-13 is the list of EDMA3 Channel Controller Registers and Table 6-14 is the list of EDMA3 Transfer
Controller registers.
Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers
EDMA0 Channel Controller 0 EDMA1 Channel Controller 0
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 0000
0x01C0 0004
BYTE ADDRESS
0x01E3 0000
PID
CCCFG
Peripheral Identification Register
EDMA3CC Configuration Register
0x01E3 0004
Global Registers
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01E3 0200
0x01E3 0204
0x01E3 0208
0x01E3 020C
0x01E3 0210
0x01E3 0214
0x01E3 0218
0x01E3 021C
0x01E3 0240
0x01E3 0244
0x01E3 0248
0x01E3 024C
0x01E3 0260
0x01E3 0284
0x01E3 0300
0x01E3 0308
0x01E3 0310
0x01E3 0314
0x01E3 0318
0x01E3 031C
0x01E3 0320
0x01E3 0340
0x01E3 0348
0x01E3 0350
0x01E3 0358
0x01E3 0380
0x01E3 0384
0x01E3 0388
0x01E3 038C
QCHMAP0 QDMA Channel 0 Mapping Register
QCHMAP1 QDMA Channel 1 Mapping Register
QCHMAP2 QDMA Channel 2 Mapping Register
QCHMAP3 QDMA Channel 3 Mapping Register
QCHMAP4 QDMA Channel 4 Mapping Register
QCHMAP5 QDMA Channel 5 Mapping Register
QCHMAP6 QDMA Channel 6 Mapping Register
QCHMAP7 QDMA Channel 7 Mapping Register
DMAQNUM0 DMA Channel Queue Number Register 0
DMAQNUM1 DMA Channel Queue Number Register 1
DMAQNUM2 DMA Channel Queue Number Register 2
DMAQNUM3 DMA Channel Queue Number Register 3
QDMAQNUM QDMA Channel Queue Number Register
QUEPRI
EMR
Queue Priority Register(1)
Event Missed Register
EMCR
QEMR
QEMCR
CCERR
Event Missed Clear Register
QDMA Event Missed Register
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERRCLR EDMA3CC Error Clear Register
EEVAL
DRAE0
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Error Evaluate Register
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C 0x01E3 0400 - 0x01E3 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C 0x01E3 0440 - 0x01E3 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
0x01E3 0600
0x01E3 0604
0x01E3 0620
0x01E3 0640
QSTAT0
QSTAT1
Queue 0 Status Register
Queue 1 Status Register
QWMTHRA Queue Watermark Threshold A Register
CCSTAT EDMA3CC Status Register
Global Channel Registers
ER Event Register
0x01C0 1000
0x01E3 1000
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
EDMA0 Channel Controller 0 EDMA1 Channel Controller 0
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 1008
0x01C0 1010
0x01C0 1018
0x01C0 1020
0x01C0 1028
0x01C0 1030
0x01C0 1038
0x01C0 1040
0x01C0 1050
0x01C0 1058
0x01C0 1060
0x01C0 1068
0x01C0 1070
0x01C0 1078
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
0x01C0 1090
0x01C0 1094
BYTE ADDRESS
0x01E3 1008
0x01E3 1010
0x01E3 1018
0x01E3 1020
0x01E3 1028
0x01E3 1030
0x01E3 1038
0x01E3 1040
0x01E3 1050
0x01E3 1058
0x01E3 1060
0x01E3 1068
0x01E3 1070
0x01E3 1078
0x01E3 1080
0x01E3 1084
0x01E3 1088
0x01E3 108C
0x01E3 1090
0x01E3 1094
ECR
ESR
Event Clear Register
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
SECR
IER
IECR
IESR
IPR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000
0x01C0 2008
0x01C0 2010
0x01C0 2018
0x01C0 2020
0x01C0 2028
0x01C0 2030
0x01C0 2038
0x01C0 2040
0x01C0 2050
0x01C0 2058
0x01C0 2060
0x01C0 2068
0x01C0 2070
0x01C0 2078
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
0x01E3 2000
ER
ECR
Event Register
0x01E3 2008
0x01E3 2010
0x01E3 2018
0x01E3 2020
0x01E3 2028
0x01E3 2030
0x01E3 2038
0x01E3 2040
0x01E3 2050
0x01E3 2058
0x01E3 2060
0x01E3 2068
0x01E3 2070
0x01E3 2078
0x01E3 2080
0x01E3 2084
0x01E3 2088
0x01E3 208C
0x01E3 2090
0x01E3 2094
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
SECR
IER
IECR
IESR
IPR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
0x01C0 2200
0x01C0 2208
0x01C0 2210
0x01E3 2200
ER
Event Register
0x01E3 2208
0x01E3 2210
ECR
ESR
Event Clear Register
Event Set Register
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
EDMA0 Channel Controller 0 EDMA1 Channel Controller 0
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01C0 2218
0x01C0 2220
0x01C0 2228
0x01C0 2230
0x01C0 2238
0x01C0 2240
0x01C0 2250
0x01C0 2258
0x01C0 2260
0x01C0 2268
0x01C0 2270
0x01C0 2278
0x01C0 2280
0x01C0 2284
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
BYTE ADDRESS
0x01E3 2218
0x01E3 2220
0x01E3 2228
0x01E3 2230
0x01E3 2238
0x01E3 2240
0x01E3 2250
0x01E3 2258
0x01E3 2260
0x01E3 2268
0x01E3 2270
0x01E3 2278
0x01E3 2280
0x01E3 2284
0x01E3 2288
0x01E3 228C
0x01E3 2290
0x01E3 2294
CER
EER
Chained Event Register
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
IECR
IESR
IPR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
—
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
0x01C0 4000 - 0x01C0 4FFF 0x01E3 4000 - 0x01E3 4FFF
Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers
EDMA0
EDMA0
EDMA1
ACRONYM
REGISTER DESCRIPTION
Transfer Controller Transfer Controller Transfer Controller
0
1
0
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
0x01E3 8000
0x01E3 8004
0x01E3 8100
0x01E3 8120
0x01E3 8124
0x01E3 8128
0x01E3 812C
0x01E3 8130
0x01E3 8140
0x01E3 8240
0x01E3 8244
0x01E3 8248
0x01E3 824C
0x01E3 8250
0x01E3 8254
0x01E3 8258
0x01E3 825C
0x01E3 8260
0x01E3 8280
0x01E3 8284
PID
Peripheral Identification Register
EDMA3TC Configuration Register
EDMA3TC Channel Status Register
Error Status Register
TCCFG
TCSTAT
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
Source Active B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF Source Active Source Address B-Reference Register
SADSTBREF Source Active Destination Address B-Reference Register
DFCNTRLD
Destination FIFO Set Count Reload Register
DFSRCBREF Destination FIFO Set Source Address B-Reference
Register
0x01C0 8288
0x01C0 8688
0x01E3 8288
DFDSTBREF Destination FIFO Set Destination Address B-Reference
Register
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Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
EDMA0
EDMA0
EDMA1
ACRONYM
REGISTER DESCRIPTION
Transfer Controller Transfer Controller Transfer Controller
0
1
0
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
0x01C0 8310
0x01C0 8314
0x01C0 8340
0x01C0 8344
0x01C0 8348
0x01C0 834C
0x01C0 8350
0x01C0 8354
0x01C0 8380
0x01C0 8384
0x01C0 8388
0x01C0 838C
0x01C0 8390
0x01C0 8394
0x01C0 83C0
0x01C0 83C4
0x01C0 83C8
0x01C0 83CC
0x01C0 83D0
0x01C0 83D4
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
0x01C0 8710
0x01C0 8714
0x01C0 8740
0x01C0 8744
0x01C0 8748
0x01C0 874C
0x01C0 8750
0x01C0 8754
0x01C0 8780
0x01C0 8784
0x01C0 8788
0x01C0 878C
0x01C0 8790
0x01C0 8794
0x01C0 87C0
0x01C0 87C4
0x01C0 87C8
0x01C0 87CC
0x01C0 87D0
0x01C0 87D4
0x01E3 8300
0x01E3 8304
0x01E3 8308
0x01E3 830C
0x01E3 8310
0x01E3 8314
0x01E3 8340
0x01E3 8344
0x01E3 8348
0x01E3 834C
0x01E3 8350
0x01E3 8354
0x01E3 8380
0x01E3 8384
0x01E3 8388
0x01E3 838C
0x01E3 8390
0x01E3 8394
0x01E3 83C0
0x01E3 83C4
0x01E3 83C8
0x01E3 83CC
0x01E3 83D0
0x01E3 83D4
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO B-Index Register 0
DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO B-Index Register 1
DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO B-Index Register 2
DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO B-Index Register 3
DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3
Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-16 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-15. EDMA Parameter Set RAM
EDMA0
EDMA1
Channel Controller 0
BYTE ADDRESS RANGE
Channel Controller 0
BYTE ADDRESS RANGE
DESCRIPTION
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01CC0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
0x01E3 4000 - 0x01E3 401F
0x01E3 4020 - 0x01E3 403F
0x01E3 4040 - 0x01CE3 405F
0x01E3 4060 - 0x01E3 407F
0x01E3 4080 - 0x01E3 409F
0x01E3 40A0 - 0x01E3 40BF
...
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 4FC0 - 0x01C0 4FDF
0x01C0 4FE0 - 0x01C0 4FFF
0x01E3 4FC0 - 0x01E3 4FDF
0x01E3 4FE0 - 0x01E3 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
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Table 6-16. Parameter Set Entries
OFFSET BYTE ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
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6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on this device, EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIFA data bus width is up to 16-bits.The device supports up to 24 address lines and two external
wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]).
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Synchronous DRAM Memory Support
The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It
has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:
•
•
•
•
One, Two, and Four Bank SDRAM devices
Devices with Eight, Nine, Ten, and Eleven Column Address
CAS Latency of two or three clock cycles
Sixteen Bit Data Bus Width
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown
mode achieves even lower power, except the device must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices.
Table 6-17 shows the supported SDRAM configurations for EMIFA.
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Table 6-17. EMIFA Supported SDRAM Configurations(1)
SDRAM
Memory Data
Bus Width
(bits)
EMIFA Data
Bus Size
(bits)
Memory
Density
(Mbits)
Number of
Memories
Total Memory Total Memory
Rows
Columns
Banks
(Mbits)
(Mbytes)
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15
16
16
16
16
16
16
16
16
16
16
16
15
8
8
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
256
512
32
256
512
64
8
1024
512
128
64
1024
512
9
9
1024
2048
1024
2048
4096
2048
4096
4096
256
128
256
128
256
512
256
512
512
32
1024
2048
1024
2048
4096
2048
4096
4096
128
16
9
10
10
10
11
11
11
8
8
512
64
256
8
1024
512
128
64
512
9
256
9
1024
2048
1024
2048
4096
2048
4096
4096
128
256
128
256
512
256
512
512
512
8
9
1024
512
10
10
10
11
11
11
1024
2048
1024
2048
2048
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
6.10.3 EMIFA SDRAM Loading Limitations
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
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6.10.4 External Memory Interface Register Descriptions
Table 6-18 is a list of the EMIF registers.
Table 6-18. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
0x6800 00C8
0x6800 00CC
0x6800 00D0
0x6800 00D4
0x6800 00D8
0x6800 00DC
ACRONYM
MIDR
REGISTER DESCRIPTION
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register
SDCR
SDRCR
SDRAM Refresh Control Register
CE2CFG
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
SDRAM Timing Register
CE3CFG
CE4CFG
CE5CFG
SDTIMR
SDSRETR
SDRAM Self Refresh Exit Timing Register
EMIFA Interrupt Raw Register
INTRAW
INTMSK
EMIFA Interrupt Mask Register
INTMSKSET
INTMSKCLR
NANDFCR
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NANDFSR
NAND Flash Status Register
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NANDERRADD1
NANDERRADD2
NANDERRVAL1
NANDERRVAL2
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
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6.10.5 EMIFA Electrical Data/Timing
Table 6-19 through Table 6-22 assume testing over recommended operating conditions.
Table 6-19. Timing Requirements for EMIFA SDRAM Interface
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX
Input setup time, read data valid on EMA_D[15:0] before
EMA_CLK rising
19 tsu(EMA_DV-EM_CLKH)
20 th(CLKH-DIV)
2
3
3
ns
ns
Input hold time, read data valid on EMA_D[15:0] after
EMA_CLK rising
1.6
1.6
1.6
Table 6-20. Switching Characteristics for EMIFA SDRAM Interface
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX
1
2
3
4
5
tc(CLK)
Cycle time, EMIF clock EMA_CLK
10
3
15
5
20
8
ns
ns
ns
ns
ns
tw(CLK)
Pulse width, EMIF clock EMA_CLK high or low
Delay time, EMA_CLK rising to EMA_CS[0] valid
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
7
7
9.5
9.5
13
13
1
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0]
invalid
6
7
toh(CLKH-DQMIV)
td(CLKH-AV)
toh(CLKH-AIV)
td(CLKH-DV)
ns
ns
ns
Delay time, EMA_CLK rising to EMA_A[12:0] and
EMA_BA[1:0] valid
7
9.5
13
Output hold time, EMA_CLK rising to EMA_A[12:0] and
EMA_BA[1:0] invalid
8
9
1
1
1
Delay time, EMA_CLK rising to EMA_D[15:0] valid
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
Delay time, EMA_CLK rising to EMA_RAS valid
7
7
7
7
7
9.5
9.5
9.5
9.5
9.5
13
13
13
13
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 toh(CLKH-DIV)
11 td(CLKH-RASV)
12 toh(CLKH-RASIV)
13 td(CLKH-CASV)
14 toh(CLKH-CASIV)
15 td(CLKH-WEV)
16 toh(CLKH-WEIV)
17 tdis(CLKH-DHZ)
18 tena(CLKH-DLZ)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_RAS invalid
Delay time, EMA_CLK rising to EMA_CAS valid
Output hold time, EMA_CLK rising to EMA_CAS invalid
Delay time, EMA_CLK rising to EMA_WE valid
Output hold time, EMA_CLK rising to EMA_WE invalid
Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMA_CLK
EMA_CS[0]
3
5
7
7
9
4
6
EMA_WE_DQM[1:0]
EMA_BA[1:0]
8
8
EMA_A[12:0]
10
EMA_D[15:0]
EMA_RAS
EMA_CAS
EMA_WE
11
12
13
15
16
Figure 6-10. EMIFA Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMA_CLK
EMA_CS[0]
3
5
7
7
4
6
EMA_WE_DQM[1:0]
EMA_BA[1:0]
8
8
EMA_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMA_D[15:0]
EMA_RAS
11
12
13
14
EMA_CAS
EMA_WE
Figure 6-11. EMIFA Basic SDRAM Read Operation
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(1)
Table 6-21. Timing Requirements for EMIFA Asynchronous Memory Interface
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
MAX MIN MAX MIN
READS and WRITES
E
2
tc(CLK)
Cycle time, EMIFA module clock
10
2E
15
2E
20
2E
ns
ns
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and deassertion
READS
12
13
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
3
0
5
0
7
0
ns
ns
Setup Time, EM_WAIT asserted before end of Strobe
Phase(2)
14
tsu (EMOEL-EMWAIT)
4E+3
4E+3
4E+3
ns
WRITES
Setup Time, EM_WAIT asserted before end of Strobe
Phase(2)
28
tsu (EMWEL-EMWAIT)
4E+3
4E+3
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
(1) (2) (3)
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface
1.3V, 1.2V, 1.1V, 1.0V
Nom
NO
.
PARAMETER
UNIT
ns
MIN
MAX
READS and WRITES
1
3
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
READS
(RS+RST+RH)*E
- 3
(RS+RST+RH)*E
+ 3
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(EMRCYCLE)
(RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(E
WC*16))*E - 3
C*16))*E
WC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
4
5
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
(RH)*E - 3
-3
0
(RH)*E
0
+3
(RH)*E + 3
+3
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RH)*E-3
(RS)*E
(RH)*E
(RS)*E
(RH)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
(RH)*E+3
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
EMA_OE low
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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(1) (2) (3)
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface
(continued)
1.3V, 1.2V, 1.1V, 1.0V
Nom
NO
.
PARAMETER
UNIT
MIN
MAX
(RST)*E+3
EMA_OE active low width (EW = 0)
EMA_OE active low width (EW = 1)
(RST)*E-3
(RST)*E
ns
ns
10 tw(EMOEL)
(RST+(EWC*16))
*E-3
(RST+(EWC*16))
*E+3
(RST+(EWC*16))*E
4E
td(EMWAITH-
EMOEH)
Delay time from EMA_WAIT deasserted to
EMA_OE high
11
3E-3
4E+3
ns
WRITES
(WS+WST+WH)*
E-3
(WS+WST+WH)*
E+3
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15 tc(EMWCYCLE)
(WS+WST+WH+( (WS+WST+WH+(E (WS+WST+WH+(
EWC*16))*E - 3
WC*16))*E
EWC*16))*E + 3
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
16 tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
-3
(WH)*E-3
-3
0
(WH)*E
0
+3
(WH)*E+3
+3
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
17 th(EMWEH-EMCEH)
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
tsu(EMDQMV-
EMWEL)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
18
19
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
th(EMWEH-
EMDQMIV)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
20 tsu(EMBAV-EMWEL)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WST)*E
(WH)*E+3
ns
ns
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E+3
24 tw(EMWEL)
(WST+(EWC*16))
*E-3
(WST+(EWC*16))
*E+3
EMA_WE active low width (EW = 1)
(WST+(EWC*16))*E
td(EMWAITH-
EMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
25
3E-3
(WS)*E-3
(WH)*E-3
4E
(WS)*E
(WH)*E
4E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
Output setup time, EMA_D[15:0] valid to
EMA_WE low
26 tsu(EMDV-EMWEL)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
27 th(EMWEH-EMDIV)
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3
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
EMA_A_RW
1
4
8
5
9
6
7
29
30
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 6-12. Asynchronous Memory Read Timing for EMIFA
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15
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
EMA_A_RW
16
17
19
21
23
32
1
18
20
22
24
31
EMA_WE
26
27
EMA_D[15:0]
EMA_OE
Figure 6-13. Asynchronous Memory Write Timing for EMIFA
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
EMA_A_RW
14
11
EMA_OE
2
2
EMA_WAIT
Asserted
Deasserted
Figure 6-14. EMA_WAIT Read Timing Requirements
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Figure 6-15. EMA_WAIT Write Timing Requirements
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6.11 DDR2/mDDR Controller
The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports
JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
The DDR2/mDDR Memory Controller support the following features:
•
•
•
•
•
JESD79-2A standard compliant DDR2 SDRAM
Mobile DDR SDRAM
512 MByte memory space for DDR2
256 MByte memory space for mDDR
CAS latencies:
–
–
DDR2: 2, 3, 4 and 5
mDDR: 2 and 3
•
Internal banks:
–
–
DDR2: 1, 2, 4 and 8
mDDR:1, 2 and 4
•
•
•
•
•
•
•
•
•
•
•
•
Burst length: 8
Burst type: sequential
1 chip select (CS) signal
Page sizes: 256, 512, 1024 and 2048
SDRAM autoinitialization
Self-refresh mode
Partial array self-refresh (for mDDR)
Power down mode
Prioritized refresh
Programmable refresh rate and backlog counter
Programmable timing parameters
Little endian
6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
Table 6-23. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR
Memory Controller
No.
PARAMETER
1.3V
1.2V
1.1V
1.0V
UNIT
MIN MAX MIN
MAX MIN
MAX MIN
MAX
72 degree DLL
configuration
(1)
(1)
(1)
125
125
90
150
150
150
133
125
150
150
133
133
125
125
75
150
150
133
133
—
—
—
DDR2
90 degree DLL
configuration
(1)
Cycle time,
125
90
—
DDR_CLKP
/
1
tc(DDR_CLK)
MHz
72 degree DLL
configuration
65
95
133
133
DDR_CLKN
mDDR
90 degree DLL
configuration
105
105
100
(1) DDR2 is not supported at this voltage operating point.
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6.11.2 DDR2/mDDR Controller Register Description(s)
Table 6-24. DDR2/mDDR Controller Registers
BYTE ADDRESS
0xB000 0000
0xB000 0004
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
0xB000 00E4
0x01E2 C000
ACRONYM
REVID
REGISTER DESCRIPTION
Revision ID Register
SDRSTAT
SDCR
SDRAM Status Register
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRCR
SDTIMR1
SDTIMR2
SDCR2
PBBPR
PC1
SDRAM Timing Register 2
SDRAM Configuration Register 2
Peripheral Bus Burst Priority Register
Performance Counter 1 Registers
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PC2
PCC
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
Interrupt Mask Set Register
IMCR
Interrupt Mask Clear Register
DDR PHY Control Register 1
DRPYC1R
VTPIO_CTL
VTP IO Control Register
6.11.3 DDR2/mDDR Interface
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2
Timing Specification (SPRAAV0).
6.11.3.1 DDR2/mDDR Interface Schematic
Figure 6-16 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The
dual-memory system shown in Figure 6-17. Pin numbers for the device can be obtained from the pin
description section.
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DDR2/mDDR Memory Controller
DDR2/mDDR
ODT
DQ0
DDR_D[0]
DDR_D[7]
T
T
DQ7
DDR_DQM[0]
DDR_DQS[0]
T
T
LDM
LDQS
NC
LDQS
DQ8
DDR_D[8]
T
DDR_D[15]
T
DQ15
DDR_DQM[1]
DDR_DQS[1]
T
T
UDM
UDQS
UDQS
BA0
NC
DDR_BA[0]
T
DDR_BA[2]
DDR_A[0]
T
T
BA2
A0
DDR_A[13]
DDR_CS
T
T
T
T
T
T
T
T
A13
CS
DDR_CAS
DDR_RAS
DDR_WE
CAS
RAS
WE
CKE
CK
DDR_CKE
DDR_CLKP
DDR_CLKN
CK
DDR_ZP
(1)
DDR_DVDD18
DDR_DQGATE0
DDR_DQGATE1
T
T
VREF(3)
0.1 μF
0.1 μF
1 K Ω 1%
DDR_VREF
VREF
0.1 μF(2)
0.1 μF(2)
0.1 μF(2)
1 K Ω 1%
T
Terminator, if desired. See terminator comments.
(1) See Figure 6-23 for DQGATE routing specifications.
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,
these capacitors can be eliminated completely.
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-16. DDR2/mDDR Single-Memory High Level Schematic
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ODT
DDR_D[0:7]
T
DQ0 - DQ7
BA0-BA2
A0-A13
DDR_DQM[0]
DDR_DQS[0]
T
T
DM
DQS
DQS
NC
CK
CK
CS
CAS
RAS
WE
CKE
VREF
DDR_BA[0:2]
DDR_A[0:13]
T
T
BA0-BA2
A0-A13
DDR_CLKP
DDR_CLKN
DDR_CS
T
T
T
T
T
T
T
CK
CK
CS
DDR_CAS
DDR_RAS
DDR_WE
CAS
RAS
WE
CKE
DDR_CKE
DDR_DQM1
DDR_DQS1
T
T
DM
DQS
DQS
NC
DDR_D[8:15]
T
DQ0 - DQ7
DDR_DVDD18
DDR_ZP
ODT
(1)
DDR_DQGATE0
T
T
VREF(3)
0.1 μF
DDR_DQGATE1
1 K Ω 1%
VREF
DDR_VREF
0.1 μF(2)
0.1 μF(2)
0.1 μF(2)
1 K Ω 1%
0.1 μF
T
Terminator, if desired. See terminator comments.
(1) See Figure 6-23 for DQGATE routing specifications.
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,
these capacitors can be eliminated completely.
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-17. DDR2/mDDR Dual-Memory High Level Schematic
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6.11.3.2 Compatible JEDEC DDR2/mDDR Devices
Table 6-25 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this
interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade
DDR2/mDDR devices.
The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control
signals are shared just like regular dual chip memory configurations.
Table 6-25. Compatible JEDEC DDR2/mDDR Devices
No. Parameter
Min
Max
Unit
Notes
(1)
1
2
3
JEDEC DDR2/mDDR Device Speed Grade
DDR2/mDDR-400
See Note
JEDEC DDR2/mDDR Device Bit Width
JEDEC DDR2/mDDR Device Count
x8
1
x16
2
Bits
(2)
Devices See Note
(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories
6.11.3.3 PCB Stackup
The minimum stackup required for routing the device is a six layer stack as shown in Table 6-26.
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size
of the PCB footprint.Complete stack up specifications are provided in Table 6-27.
Table 6-26. Device Minimum PCB Stack Up
Layer
Type
Signal
Plane
Plane
Signal
Plane
Signal
Description
Top Routing Mostly Horizontal
Ground
1
2
3
4
5
6
Power
Internal Routing
Ground
Bottom Routing Mostly Vertical
Table 6-27. PCB Stack Up Specifications
No. Parameter
Min
6
Typ
Max Unit
Notes
1
2
3
4
5
6
7
8
8
9
PCB Routing/Plane Layers
Signal Routing Layers
3
Full ground layers under DDR2/mDDR routing region
Number of ground plane cuts allowed within DDR routing region
Number of ground reference planes required for each DDR2/mDDR routing layer
Number of layers between DDR2/mDDR routing layer and reference ground plane
PCB Routing Feature Size
2
0
1
0
4
4
Mils
Mils
Mils
Mils
PCB Trace Width w
PCB BGA escape via pad size
18
8
PCB BGA escape via hole size
(1)
(2)
10 Device BGA pad size
See Note
See Note
11 DDR2/mDDR Device BGA pad size
12 Single Ended Impedance, Zo
13 Impedance Control
50
75
Ω
Ω
(3)
Z-5
Z
Z+5
See Note
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.
(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
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6.11.3.4 Placement
Figure 6-17 shows the required placement for the device as well as the DDR2/mDDR devices. The
dimensions for Figure 6-18 are defined in Table 6-28. The placement does not restrict the side of the PCB
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second
DDR2/mDDR device is omitted from the placement.
X
A1
Y
OFFSET
DDR2/mDDR
Y
Device
Y
OFFSET
A1
Recommended DDR2/mDDR
Device Orientation
Figure 6-18. Device and DDR2/mDDR Device Placement
Table 6-28. Placement Specifications
No. Parameter
Min
Max
1750
1280
650
Unit
Notes
(1) (2)
1
2
3
4
X
Mils See Notes
Mils See Notes
Mils See Notes
,
(1) (2)
Y
,
(1) (2) (3)
Y Offset
.
,
(4)
(5)
Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region
4
w
See Note
(1) See Figure 6-18 for dimension definitions.
(2) Measurements from center of device to center of DDR2/mDDR device.
(3) For single memory systems it is recommended that Y Offset be as small as possible.
(4) w = PCB trace width as defined in Table 6-27 .
(5) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by
a ground plane.
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6.11.3.5 DDR2/mDDR Keep Out Region
The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-19. The size of this
region varies with the placement and DDR routing. Additional clearances required for the keep out region
are shown in Table 6-28.
A1
DDR2/mDDR
Device
A1
Region should encompass all DDR2/mDDR circuitry and varies
depending on placement. Non-DDR2/mDDR signals should not be
routed on the DDR signal layers within the DDR2/mDDR keep out
region. Non-DDR2/mDDR signals may be routed in the region
provided they are routed on layers separated from DDR2/mDDR
signal layers by a ground layer. No breaks should be allowed in the
reference ground layers in this region. In addition, the 1.8 V power
plane should cover the entire keep out region.
Figure 6-19. DDR2/mDDR Keepout Region
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6.11.3.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other
circuitry. Table 6-29 contains the minimum numbers and capacitance required for the bulk bypass
capacitors. Note that this table only covers the bypass needs of the device and DDR2/mDDR interfaces.
Additional bulk bypass capacitance may be needed for other circuitry.
Table 6-29. Bulk Bypass Capacitors
No. Parameter
Min
3
Max
Unit
Notes
(1)
1
2
3
4
5
6
DDR_DVDD18 Supply Bulk Bypass Capacitor Count
Devices See Note
DDR_DVDD18 Supply Bulk Bypass Total Capacitance
DDR#1 Bulk Bypass Capacitor Count
30
1
mF
(1)
Devices See Note
DDR#1 Bulk Bypass Total Capacitance
DDR#2 Bulk Bypass Capacitor Count
22
1
mF
(1) (2)
Devices See Notes
,
(2)
DDR#2 Bulk Bypass Total Capacitance
22
mF
See Note
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2) Only used on dual-memory systems
6.11.3.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is
particularly important to minimize the parasitic series inductance of the HS bypass cap,
device/DDR2/mDDR power, and device/DDR2/mDDR ground connections. Table 6-30 contains the
specification for the HS bypass capacitors as well as for the power connections on the PCB.
Table 6-30. High-Speed Bypass Capacitors
No. Parameter
Min
Max
0402
250
Unit
Notes
(1)
1
2
3
4
5
HS Bypass Capacitor Package Size
10 Mils See Note
Mils
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor
Trace length from bypass capacitor contact to connection via
(2)
2
1
Vias
Mils
Vias
See Note
30
35
Number of connection vias for each DDR2/mDDR device power or
ground balls
1
6
7
8
9
Trace length from DDR2/mDDR device power ball to connection via
DDR_DVDD18 Supply HS Bypass Capacitor Count
DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance
DDR#1 HS Bypass Capacitor Count
Mils
(3)
(3)
10
0.6
8
Devices See Note
mF
Devices See Note
10 DDR#1 HS Bypass Capacitor Total Capacitance
11 DDR#2 HS Bypass Capacitor Count
0.4
8
mF
(3) (4)
Devices See Notes
,
(4)
12 DDR#2 HS Bypass Capacitor Total Capacitance
0.4
mF
See Note
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Only used on dual-memory systems
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6.11.3.8 Net Classes
Table 6-31 lists the clock net classes for the DDR2/mDDR interface. Table 6-32 lists the signal net
classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes
are used for the termination and routing rules that follow.
Table 6-31. Clock Net Class Definitions
Clock Net Class
CK
Pin Names
DDR_CLKP / DDR_CLKN
DDR_DQS[0]
DQS0
DQS1
DDR_DQS[1]
Table 6-32. Signal Net Class Definitions
Clock Net Class
Associated Clock Net Class Pin Names
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
D0
D1
DQS0
DDR_D[7:0], DDR_DQM0
DQS1
DDR_D[15:8], DDR_DQM1
DDR_DQGATE0, DDR_DQGATE1
DQGATE
CK, DQS0, DQS1
6.11.3.9 DDR2/mDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-33 shows the specifications for the series terminators.
Table 6-33. DDR2/mDDR Signal Terminations
No. Parameter
Min
0
Typ
Max Unit
Notes
(1)
1
2
3
4
CK Net Class
10
Zo
Zo
Zo
Ω
Ω
Ω
Ω
See Note
See Notes
See Notes
See Notes
(1) (2) (3)
ADDR_CTRL Net Class
0
22
22
10
,
,
(1) (2) (3) (4)
Data Byte Net Classes (DQS[0], DQS[1], D0, D1)
DQGATE Net Class (DQGATE)
0
,
,
,
(1) (2) (3)
0
,
,
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
(4) When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.
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6.11.3.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the device.
VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a
resistive divider as shown in Figure 6-16. Other methods of creating VREF are not recommended.
Figure 6-20 shows the layout guidelines for VREF.
VREF Bypass Capacitor
DDR2/mDDR Device
A1
VREF Nominal Minimum
DDR2/mDDR
Trace Width is 20 Mils
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 6-20. VREF Routing and Topology
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6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
T
A
A1
Figure 6-21. CK and ADDR_CTRL Routing and Topology
Table 6-34. CK and ADDR_CTRL Routing Specification
No. Parameter
Min
Typ
Max
Unit
Notes
(1)
(2)
1
2
Center to Center CK-CKN Spacing
2w
25
See Note
See Note
(3)
CK A to B/A to C Skew Length Mismatch
Mils
Mils
3
CK B to C Skew Length Mismatch
25
(1)
(2)
(4)
4
Center to center CK to other DDR2/mDDR trace spacing
CK/ADDR_CTRL nominal trace length
4w
See Note
See Note
5
CACLM-50
CACLM
CACLM+50
100
Mils
Mils
Mils
6
ADDR_CTRL to CK Skew Length Mismatch
7
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
Center to center ADDR_CTRL to other DDR2/mDDR trace spacing
Center to center ADDR_CTRL to other ADDR_CTRL trace spacing
ADDR_CTRL A to B/A to C Skew Length Mismatch
ADDR_CTRL B to C Skew Length Mismatch
100
(1)
(2)
(2)
(3)
8
4w
See Note
See Note
See Note
(1)
9
3w
10
11
100
100
Mils
Mils
(1) w = PCB trace width as defined in Table 6-27 .
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Series terminator, if used, should be located closest to device.
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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Figure 6-22 shows the topology and routing for the DQS and DQ net class; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
A1
Figure 6-22. DQS and DQ Routing and Topology
Table 6-35. DQS and DQ Routing Specification
No. Parameter
Min
Typ
Max
25
Unit
Mils
Notes
1
2
DQS E Skew Length Mismatch
(1)
(2)
Center to center DQS to other DDR2/mDDR trace
spacing
4w
See Note
(3) (4)
3
4
5
6
DQS/D nominal trace length
D to DQS Skew Length Mismatch
D to D Skew Length Mismatch
DQLM-50
DQLM
DQLM+50
100
Mils See Notes
,
(4)
Mils See Note
Mils See Note
See Notes
(4)
100
(1)
(2) (5)
Center to center D to other DDR2/mDDR trace
spacing
4w
,
(1)
(6) (2)
7
8
Center to Center D to other D trace spacing
DQ/DQS E Skew Length Mismatch
3w
See Notes
,
(4)
100
Mils See Note
(1) w = PCB trace width as defined in Table 6-27 .
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Series terminator, if used, should be located closest to DDR.
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) D's from other DQS domains are considered other DDR2/mDDR trace.
(6) DQLM is the longest Manhattan distance of each of the DQS and D net class.
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Figure 6-23 shows the routing for the DQGATE net class. Table 6-36 contains the routing specification.
A1
T
F
T
A1
Figure 6-23. DQGATE Routing
Table 6-36. DQGATE Routing Specification
No. Parameter
Min
Typ
Max
Unit
Notes
(1)
(3)
1
2
3
4
DQGATE Length F
CKB0B1
See Note
(2)
Center to center DQGATE to any other trace spacing
DQS/D nominal trace length
4w
DQLM-50
DQLM
DQLM+50
100
Mils
Mils
DQGATE Skew
See Note
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2) w = PCB trace width as defined in Table 6-27 .
(3) Skew from CKB0B1
6.11.3.12 MDDR/DDR2 Boundary Scan Limitations
Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells
between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are
tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects
between functional and boundary scan paths.
The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output
enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD
capability is still available.
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6.12 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
•
•
•
•
•
•
•
Provides memory protection for fixed and programmable address ranges.
Supports multiple programmable address region.
Supports secure and debug access privileges.
Supports read, write, and execute access privileges.
Supports privid(8) associations with ranges.
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
MMR access is also protected.
Table 6-37. MPU1 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 4000
REVID
CONFIG
Revision ID
0x01E1 4004
Configuration
0x01E1 4010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 4014
Interrupt enable status/clear
0x01E1 4018
IENSET
Interrupt enable
0x01E1 401C
IENCLR
Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF
0x01E1 4200
-
Reserved
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 4204
0x01E1 4208
0x01E1 420C - 0x01E1 420F
0x01E1 4210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 4214
0x01E1 4218
0x01E1 421C - 0x01E1 421F
0x01E1 4220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 4224
0x01E1 4228
0x01E1 422C - 0x01E1 422F
0x01E1 4230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 4234
0x01E1 4238
0x01E1 423C - 0x01E1 423F
0x01E1 4240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 4244
0x01E1 4248
0x01E1 424C - 0x01E1 424F
0x01E1 4250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 4254
0x01E1 4258
0x01E1 425C - 0x01E1 42FF
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Table 6-37. MPU1 Configuration Registers (continued)
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 4300
0x01E1 4304
FLTADDRR
FLTSTAT
FLTCLR
-
Fault address
Fault status
Fault clear
Reserved
0x01E1 4308
0x01E1 430C - 0x01E1 4FFF
Table 6-38. MPU2 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 5000
0x01E1 5004
REVID
CONFIG
Revision ID
Configuration
0x01E1 5010
IRAWSTAT
IENSTAT
Interrupt raw status/set
0x01E1 5014
Interrupt enable status/clear
0x01E1 5018
IENSET
Interrupt enable
0x01E1 501C
IENCLR
Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF
0x01E1 5100
-
Reserved
FXD_MPSAR
FXD_MPEAR
FXD_MPPA
-
Fixed range start address
0x01E1 5104
Fixed range end start address
Fixed range memory page protection attributes
Reserved
0x01E1 5108
0x01E1 510C - 0x01E1 51FF
0x01E1 5200
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 5204
0x01E1 5208
0x01E1 520C - 0x01E1 520F
0x01E1 5210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 5214
0x01E1 5218
0x01E1 521C - 0x01E1 521F
0x01E1 5220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 5224
0x01E1 5228
0x01E1 522C - 0x01E1 522F
0x01E1 5230
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 5234
0x01E1 5238
0x01E1 523C - 0x01E1 523F
0x01E1 5240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 5244
0x01E1 5248
0x01E1 524C - 0x01E1 524F
0x01E1 5250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 5254
0x01E1 5258
0x01E1 525C - 0x01E1 525F
0x01E1 5260
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
0x01E1 5264
0x01E1 5268
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Table 6-38. MPU2 Configuration Registers (continued)
MPU1
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 526C - 0x01E1 526F
0x01E1 5270
-
Reserved
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPA
-
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Reserved
0x01E1 5274
0x01E1 5278
0x01E1 527C - 0x01E1 527F
0x01E1 5280
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPA
-
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Reserved
0x01E1 5284
0x01E1 5288
0x01E1 528C - 0x01E1 528F
0x01E1 5290
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
-
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Reserved
0x01E1 5294
0x01E1 5298
0x01E1 529C - 0x01E1 529F
0x01E1 52A0
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
-
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Reserved
0x01E1 52A4
0x01E1 52A8
0x01E1 52AC - 0x01E1 52AF
0x01E1 52B0
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
-
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Reserved
0x01E1 52B4
0x01E1 52B8
0x01E1 52BC - 0x01E1 52FF
0x01E1 5300
FLTADDRR
FLTSTAT
Fault address
0x01E1 5304
Fault status
0x01E1 5308
FLTCLR
Fault clear
0x01E1 530C - 0x01E1 5FFF
-
Reserved
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6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
6.13.1 MMCSD Peripheral Description
The device includes an two MMCSD controllers which are compliant with MMC V3.31, Secure Digital Part
1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller have following features:
•
•
•
•
•
•
•
MultiMediaCard (MMC).
Secure Digital (SD) Memory Card.
MMC/SD protocol support.
SDIO protocol support.
Programmable clock frequency.
512 bit Read/Write FIFO to lower system overhead.
Slave EDMA transfer capability.
The device MMC/SD Controller does not support SPI mode.
6.13.2 MMCSD Peripheral Register Description(s)
Table 6-39. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
MMCSD0
BYTE ADDRESS
MMCSD1
BYTE ADDRESS
ACRONYM
REGISTER DESCSRIPTION
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
0x01E1 B000
0x01E1 B004
0x01E1 B008
0x01E1 B00C
0x01E1 B010
0x01E1 B014
0x01E1 B018
0x01E1 B01C
0x01E1 B020
0x01E1 B024
0x01E1 B028
0x01E1 B02C
0x01E1 B030
0x01E1 B034
0x01E1 B038
0x01E1 B03C
0x01E1 B040
0x01E1 B044
0x01E1 B048
0x01E1 B050
0x01E1 B064
0x01E1 B068
0x01E1 B06C
0x01E1 B070
0x01E1 B074
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
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6.13.3 MMC/SD Electrical Data/Timing
Table 6-40 through Table 6-41 assume testing over recommended operating conditions.
Table 6-40. Timing Requirements for MMC/SD
(see Figure 6-25 and Figure 6-27)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
4
MAX MIN MAX MIN
1
2
3
4
tsu(CMDV-CLKH) Setup time, MMCSD_CMD valid before MMCSD_CLK high
th(CLKH-CMDV) Hold time, MMCSD_CMD valid after MMCSD_CLK high
tsu(DATV-CLKH) Setup time, MMCSD_DATx valid before MMCSD_CLK high
4
6
ns
ns
ns
ns
2.5
4.5
2.5
2.5
5
2.5
6
th(CLKH-DATV)
Hold time, MMCSD_DATx valid after MMCSD_CLK high
2.5
2.5
Table 6-41. Switching Characteristics for MMC/SD (see Figure 6-24 through Figure 6-27)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
0
MAX MIN MAX MIN
7
f(CLK)
Operating frequency, MMCSD_CLK
Identification mode frequency, MMCSD_CLK
Pulse width, MMCSD_CLK low
52
0
50
0
0
25
MHz
KHz
ns
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
0
400
0
400
400
9
6.5
6.5
6.5
6.5
10
10
10
11
12
13
14
Pulse width, MMCSD_CLK high
ns
Rise time, MMCSD_CLK
3
3
3
10
10
4
ns
tf(CLK)
Fall time, MMCSD_CLK
3
ns
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4
-4
2.5
3.3
-4
-4
3
-4
-4
ns
3.5
4
ns
10
9
7
MMCSD_CLK
MMCSD_CMD
13
13
13
Valid
13
START
XMIT
Valid
Valid
END
Figure 6-24. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 6-25. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 6-26. MMC/SD Host Write Timing
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9
10
7
MMCSD_CLK
4
4
3
Start
3
MMCSD_DATx
D0
D1
Dx
End
Figure 6-27. MMC/SD Host Read and Card CRC Status Timing
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6.14 Multichannel Audio Serial Port (McASP)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
Time slots of 8,12,16, 20, 24, 28, and 32 bits
First bit delay 0, 1, or 2 clocks
MSB or LSB first bit order
Left- or right-aligned data words within time slots
•
•
•
DIT Mode with 384-bit Channel Status and 384-bit User Data registers
Extensive error checking and mute generation logic
All unused pins GPIO-capable
•
Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it
more tolerant to DMA latency.
•
Dynamic Adjustment of Clock Dividers
–
Clock Divider Value may be changed without resetting the McASP
Pins
Function
AHCLKRx
ACLKRx
AFSRx
Receive Master Clock
Receive Logic
Clock/Fram e Generator
State Machine
Peripheral
Configuration
Bus
GIO
Receive Bit Clock
Control
Receive Left/Right Clock or Fram e Sync
The McASP DOES NOT have a
dedicated AMUTEIN pin.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
DIT RAM
384 C
384 U
AFSXx
Transm it Left/Right Clock or Fram e Sync
Transm it Bit Clock
Transm it Logic
Clock/Fram e Generator
State Machine
Optional
ACLKXx
AHCLKXx
Transm it M aster Clock
Transm it
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transm it/Receive Serial Data Pin
Transm it/Receive Serial Data Pin
Form atter
McASP
DMA Bus
(Dedicated)
Receive
Serializer y
McASP
AXRx[y]
Transm it/Receive Serial Data Pin
Form atter
Figure 6-28. McASP Block Diagram
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6.14.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-42. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-43
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-44. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port
BYTE ADDRESS
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
ACRONYM
REV
REGISTER DESCRIPTION
Revision identification register
PFUNC
PDIR
Pin function register
Pin direction register
PDOUT
PDIN
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write address: PDOUT)
Pin data clear register (alternate write address: PDOUT)
Global control register
PDSET
PDCLR
GBLCTL
AMUTE
DLBCTL
DITCTL
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only receive bits are
affected - allows receiver to be reset independently from transmitter
RGBLCTL
0x01D0 0064
0x01D0 0068
0x01D0 006C
0x01D0 0070
0x01D0 0074
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
RMASK
RFMT
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
RINTCTL
RSTAT
RSLOT
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
RCLKCHK
REVTCTL
Transmitter global control register. Alias of GBLCTL, only transmit bits are
affected - allows transmitter to be reset independently from receiver
XGBLCTL
0x01D0 00A4
0x01D0 00A8
0x01D0 00AC
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 00BC
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8
0x01D0 00CC
0x01D0 0100
0x01D0 0104
XMASK
XFMT
Transmit format unit bit mask register
Transmit bit stream format register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
Transmit frame sync control register
Transmit clock control register
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
XINTCTL
XSTAT
Transmitter status register
XSLOT
Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
Left (even TDM time slot) channel status register (DIT mode) 0
Left (even TDM time slot) channel status register (DIT mode) 1
XCLKCHK
XEVTCTL
DITCSRA0
DITCSRA1
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Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port (continued)
BYTE ADDRESS
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 013C
0x01D0 0140
0x01D0 0144
0x01D0 0148
0x01D0 014C
0x01D0 0150
0x01D0 0154
0x01D0 0158
0x01D0 015C
0x01D0 0180
0x01D0 0184
0x01D0 0188
0x01D0 018C
0x01D0 0190
0x01D0 0194
0x01D0 0198
0x01D0 019C
0x01D0 01A0
0x01D0 01A4
0x01D0 01A8
0x01D0 01AC
0x01D0 01B0
0x01D0 01B4
0x01D0 01B8
0x01D0 01BC
0x01D0 0200
0x01D0 0204
0x01D0 0208
0x01D0 020C
0x01D0 0210
0x01D0 0214
0x01D0 0218
0x01D0 021C
ACRONYM
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
SRCTL0
REGISTER DESCRIPTION
Left (even TDM time slot) channel status register (DIT mode) 2
Left (even TDM time slot) channel status register (DIT mode) 3
Left (even TDM time slot) channel status register (DIT mode) 4
Left (even TDM time slot) channel status register (DIT mode) 5
Right (odd TDM time slot) channel status register (DIT mode) 0
Right (odd TDM time slot) channel status register (DIT mode) 1
Right (odd TDM time slot) channel status register (DIT mode) 2
Right (odd TDM time slot) channel status register (DIT mode) 3
Right (odd TDM time slot) channel status register (DIT mode) 4
Right (odd TDM time slot) channel status register (DIT mode) 5
Left (even TDM time slot) channel user data register (DIT mode) 0
Left (even TDM time slot) channel user data register (DIT mode) 1
Left (even TDM time slot) channel user data register (DIT mode) 2
Left (even TDM time slot) channel user data register (DIT mode) 3
Left (even TDM time slot) channel user data register (DIT mode) 4
Left (even TDM time slot) channel user data register (DIT mode) 5
Right (odd TDM time slot) channel user data register (DIT mode) 0
Right (odd TDM time slot) channel user data register (DIT mode) 1
Right (odd TDM time slot) channel user data register (DIT mode) 2
Right (odd TDM time slot) channel user data register (DIT mode) 3
Right (odd TDM time slot) channel user data register (DIT mode) 4
Right (odd TDM time slot) channel user data register (DIT mode) 5
Serializer control register 0
SRCTL1
Serializer control register 1
SRCTL2
Serializer control register 2
SRCTL3
Serializer control register 3
SRCTL4
Serializer control register 4
SRCTL5
Serializer control register 5
SRCTL6
Serializer control register 6
SRCTL7
Serializer control register 7
SRCTL8
Serializer control register 8
SRCTL9
Serializer control register 9
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
XBUF0(1)
XBUF1(1)
XBUF2(1)
XBUF3(1)
XBUF4(1)
XBUF5(1)
XBUF6(1)
XBUF7(1)
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port (continued)
BYTE ADDRESS
0x01D0 0220
0x01D0 0224
0x01D0 0228
0x01D0 022C
0x01D0 0230
0x01D0 0234
0x01D0 0238
0x01D0 023C
0x01D0 0280
0x01D0 0284
0x01D0 0288
0x01D0 028C
0x01D0 0290
0x01D0 0294
0x01D0 0298
0x01D0 029C
0x01D0 02A0
0x01D0 02A4
0x01D0 02A8
0x01D0 02AC
0x01D0 02B0
0x01D0 02B4
0x01D0 02B8
0x01D0 02BC
ACRONYM
XBUF8(1)
XBUF9(1)
XBUF10(1)
XBUF11(1)
XBUF12(1)
XBUF13(1)
XBUF14(1)
XBUF15(1)
RBUF0(2)
RBUF1(2)
RBUF2(2)
RBUF3(2)
RBUF4(2)
RBUF5(3)
RBUF6(3)
RBUF7(3)
RBUF8(3)
RBUF9(3)
RBUF10(3)
RBUF11(3)
RBUF12(3)
RBUF13(3)
RBUF14(3)
RBUF15(3)
REGISTER DESCRIPTION
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
(3) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 6-43. McASP Registers Accessed Through DMA Port
ACCESS TYPE
Read Accesses
BYTE ADDRESS
0x01D0 2000
ACRONYM
RBUF
REGISTER DESCRIPTION
Receive buffer DMA port address. Cycles through receive
serializers, skipping over transmit serializers and inactive
serializers. Starts at the lowest serializer at the beginning of each
time slot. Reads from DMA port only if XBUSEL = 0 in XFMT.
Write Accesses
0x01D0 2000
XBUF
Transmit buffer DMA port address. Cycles through transmit
serializers, skipping over receive and inactive serializers. Starts at
the lowest serializer at the beginning of each time slot. Writes to
DMA port only if RBUSEL = 0 in RFMT.
Table 6-44. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
0x01D0 1018
0x01D0 101C
ACRONYM
AFIFOREV
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
REGISTER DESCRIPTION
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
Read FIFO control register
Read FIFO status register
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6.14.2 McASP Electrical Data/Timing
6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-45 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-29 and
Figure 6-30).
Table 6-45. Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)(1) (2)
1.3V, 1.2V
1.1V
MIN MAX
NO.
PARAMETER
UNIT
MIN
25
12.5
25(3)
12.5
11.5
4
MAX
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
Cycle time, AHCLKR/X
28
14
28(3)
14
12
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
AHCLKR/X ext
AHCLKR/X ext
Pulse duration, ACLKR/W high or low
AHCLKR/X int
Setup time,
5
tsu(AFSRX-ACLKRX)
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
(4)
AFSR/X input to ACLKR/X
4
5
-1
-2
1
Hold time,
6
7
8
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
1
AFSR/X input after ACLKR/X(4)
1
1
11.5
4
12
5
Setup time,
AXR0[n] input to ACLKR/X(4) (5)
AHCLKR/X ext
AHCLKR/X int
-1
-2
4
Hold time,
AHCLKR/X ext input
AHCLKR/X ext output
3
AXR0[n] input after ACLKR/X(4) (5)
3
4
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) This timing is limited by the timing shown or 2P, whichever is greater.
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-46. Timing Requirements for McASP0 (1.0V)(1) (2)
1.0V
MIN
NO.
PARAMETER
UNIT
MAX
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
Cycle time, AHCLKR/X
35
17.5
35(3)
17.5
16
5.5
5.5
-2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
AHCLKR/X ext
AHCLKR/X ext
Pulse duration, ACLKR/W high or low
AHCLKR/X int
Setup time,
AFSR/X input to ACLKR/X
5
tsu(AFSRX-ACLKRX)
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
(4)
Hold time,
6
7
8
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
AHCLKR/X ext input
AHCLKR/X ext output
AHCLKR/X int
1
AFSR/X input after ACLKR/X(4)
1
16
5.5
-2
Setup time,
AXR0[n] input to ACLKR/X(4) (5)
AHCLKR/X ext
AHCLKR/X int
Hold time,
AHCLKR/X ext input
AHCLKR/X ext output
5
AXR0[n] input after ACLKR/X(4) (5)
5
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) This timing is limited by the timing shown or 2P, whichever is greater.
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-47. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)(1)
1.3V, 1.2V
1.1V
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
25
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
AH – 2.5(2)
25(3) (4)
A – 2.5(5)
AH – 2.5(2)
28(3) (4)
A – 2.5(5)
ACLKR/X int
Pulse duration, ACLKR/X high or low
ACLKR/X int
ACLKR/X int
-1
2
6
-1
2
8
14.5
14.5
8
Delay time, ACLKR/X transmit edge to
AFSX/R output valid(6)
13 td(ACLKRX-AFSRX)
ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
13.5
13.5
6
2
2
-1
2
-1
2
Delay time, ACLKX transmit edge to
AXR output valid
14 td(ACLKX-AXRV)
ACLKR/X ext input
ACLKR/X ext output
13.5
13.5
6
15
15
8
2
2
Disable time, ACLKR/X transmit edge to ACLKR/X int
0
0
15 tdis(ACLKX-AXRHZ) AXR high impedance following last data
bit
ACLKR/X ext
2
13.5
2
15
ns
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Table 6-48. Switching Characteristics for McASP0 (1.0V)(1)
1.0V
NO.
9
PARAMETER
UNIT
MIN
MAX
tc(AHCLKRX)
Cycle time, AHCLKR/X
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
AH – 2.5(2)
35(3) (4)
A – 2.5(5)
ACLKR/X int
ACLKR/X int
ACLKR/X int
Pulse duration, ACLKR/X high or low
-0.5
2
10
19
19
10
19
19
10
19
13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid(6) ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
2
-0.5
2
14 td(ACLKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X ext input
ACLKR/X ext output
ACLKR/X int
2
0
Disable time, ACLKR/X transmit edge to AXR high
impedance following last data bit
15 tdis(ACLKX-AXRHZ)
ACLKR/X ext
2
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) P = SYSCLK2 period
(4) This timing is limited by the timing shown or 2P, whichever is greater.
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-29. McASP Input Timings
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 6-30. McASP Output Timings
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6.15 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
•
External shift clock or an internal, programmable frequency shift clock for data transfer
Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it
more tolerant to DMA latency
If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 1 or greater.
6.15.1 McBSP Peripheral Register Description(s)
Table 6-49. McBSP/FIFO Registers
McBSP0
BYTE
McBSP1
BYTE
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
McBSP Registers
0x01D1 0000 0x01D1 1000
0x01D1 0004 0x01D1 1004
0x01D1 0008 0x01D1 1008
0x01D1 000C 0x01D1 100C
0x01D1 0010 0x01D1 1010
0x01D1 0014 0x01D1 1014
0x01D1 0018 0x01D1 1018
0x01D1 001C 0x01D1 101C
0x01D1 0020 0x01D1 1020
0x01D1 0024 0x01D1 1024
0x01D1 0028 0x01D1 1028
0x01D1 002C 0x01D1 102C
0x01D1 0030 0x01D1 1030
0x01D1 0034 0x01D1 1034
0x01D1 0038 0x01D1 1038
0x01D1 003C 0x01D1 103C
DRR
DXR
McBSP Data Receive Register (read-only)
McBSP Data Transmit Register
SPCR
McBSP Serial Port Control Register
RCR
McBSP Receive Control Register
XCR
McBSP Transmit Control Register
SRGR
McBSP Sample Rate Generator register
MCR
McBSP Multichannel Control Register
RCERE0
XCERE0
PCR
McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
McBSP Pin Control Register
RCERE1
XCERE1
RCERE2
XCERE2
RCERE3
XCERE3
McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
McBSP FIFO Control and Status Registers
0x01D1 0800 0x01D1 1800
0x01D1 0810 0x01D1 1810
0x01D1 0814 0x01D1 1814
0x01D1 0818 0x01D1 1818
0x01D1 081C 0x01D1 181C
BFIFOREV
BFIFO Revision Identification Register
Write FIFO Control Register
Write FIFO Status Register
Read FIFO Control Register
Read FIFO Status Register
McBSP FIFO Data Registers
McBSP FIFO Receive Buffer
McBSP FIFO Transmit Buffer
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
0x01F1 0000 0x01F1 1000
0x01F1 0000 0x01F1 1000
RBUF
XBUF
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6.15.2 McBSP Electrical Data/Timing
The following assume testing over recommended operating conditions.
6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 6-50. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V](1) (see Figure 6-31)
1.3V, 1.2V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P or 20(2) (3)
2P or 25(2) (3)
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
P - 1(4)
P - 1(4)
14
4
15.5
Setup time, external FSR high before CLKR
low
5
6
7
8
tsu(FRH-CKRL)
ns
ns
ns
ns
ns
ns
5
6
6
th(CKRL-FRH) Hold time, external FSR high after CLKR low
tsu(DRV-CKRL) Setup time, DR valid before CLKR low
th(CKRL-DRV) Hold time, DR valid after CLKR low
3
3
14
4
15.5
5
3
3
3
3
14
4
15.5
5
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
6
6
3
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 6-51. Timing Requirements for McBSP0 [1.0V](1) (see Figure 6-31)
1.0V
MIN
NO.
PARAMETER
UNIT
MAX
2P or
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
ns
ns
26.6(2) (3)
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
P - 1(4)
20
5
5
6
7
8
tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
th(CKRL-FRH) Hold time, external FSR high after CLKR low
tsu(DRV-CKRL) Setup time, DR valid before CLKR low
th(CKRL-DRV) Hold time, DR valid after CLKR low
ns
ns
ns
ns
ns
ns
6
3
20
5
3
3
20
5
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
6
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 6-52. Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V](1) (2)
(see Figure 6-31)
1.3V, 1.2V
MIN
1.1V
NO.
PARAMETER
UNIT
MAX
14.5
MIN
2
MAX
16
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
2
3
td(CKSH-CKRXH)
tc(CKRX)
tw(CKRX)
td(CKRH-FRV)
2
ns
ns
2P or 20(3)
2P or 25(3)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
(4) (5)
(4) (5)
Pulse duration, CLKR/X high or
CLKR/X low
C - 2(6)
C + 2(6)
C - 2(6)
C + 2(6)
ns
ns
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
-4
5.5
14.5
-4
5.5
16
Delay time, CLKR high to internal FSR
valid
4
9
2
2
-4
-4
5.5
5.5
Delay time, CLKX high to internal FSX
valid
td(CKXH-FXV)
ns
ns
ns
2
-4
14.5
2
16
7.5
-5.5
7.5
Disable time, DX high impedance
following last data bit from CLKX high
12 tdis(CKXH-DXHZ)
-2
16
-22
16
-4 + D1(7)
2 + D1(7)
-4(8)
5.5 + D2(7)
14.5 + D2(7)
5(8)
-4 + D1(7)
2 + D1(7)
-4(8)
5.5 + D2(7)
16 + D2(7)
5(8)
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
14 td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-2(8)
14.5(8)
-2(8)
16(8)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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Table 6-53. Switching Characteristics for McBSP0 [1.0V](1) (2)
(see Figure 6-31)
1.0V
NO.
1
PARAMETER
UNIT
ns
MIN
3
MAX
21.5
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input
td(CKSH-CKRXH)
2P or
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
26.6(3) (4)
ns
(5)
3
4
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
C - 2(6)
C + 2(6)
10
ns
ns
-4
td(CKRH-FRV)
2.5
21.5
10
-4
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
2.5
-4
21.5
10
Disable time, DX high impedance following last data bit from CLKX
high
12 tdis(CKXH-DXHZ)
-2
21.5
10 + D2(7)
-4 + D1(7)
2.5 + D1(7) 21.5 + D2(7)
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
-4(8)
5(8)
14 td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-2(8)
21.5(8)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Table 6-54. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V](1) (see Figure 6-31)
1.3V, 1.2V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
CLKR/X ext
2P or 20(2) (3)
P - 1(5)
2P or 25(2) (4)
P - 1(6)
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(5) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
(6) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 6-54. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (1) (see Figure 6-31 ) (continued)
1.3V, 1.2V
1.1V
MIN
NO.
5
PARAMETER
UNIT
ns
MIN
15
5
MAX
MAX
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
18
5
Setup time, external FSR high before CLKR
low
tsu(FRH-CKRL)
6
6
6
th(CKRL-FRH) Hold time, external FSR high after CLKR low
tsu(DRV-CKRL) Setup time, DR valid before CLKR low
th(CKRL-DRV) Hold time, DR valid after CLKR low
ns
3
3
15
5
18
5
7
ns
3
3
8
ns
3
3
15
5
18
5
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
ns
6
6
ns
3
3
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Table 6-55. Timing Requirements for McBSP1 [1.0V](1) (see Figure 6-31)
1.0V
MIN
NO.
PARAMETER
UNIT
MAX
2P or
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
ns
ns
26.6(2) (3)
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
P - 1(4)
21
10
6
5
6
7
8
tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
th(CKRL-FRH) Hold time, external FSR high after CLKR low
tsu(DRV-CKRL) Setup time, DR valid before CLKR low
th(CKRL-DRV) Hold time, DR valid after CLKR low
ns
ns
ns
ns
ns
ns
3
21
10
3
3
21
10
6
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 6-56. Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V](1) (2)
(see Figure 6-31)
1.3V, 1.2V
MIN
1.1V
NO.
PARAMETER
UNIT
MAX
16.5
MIN
1.5
MAX
18
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
2
3
td(CKSH-CKRXH)
tc(CKRX)
tw(CKRX)
td(CKRH-FRV)
0.5
ns
ns
2P or 20(3)
2P or 25(3)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
(4) (5)
(4) (5)
Pulse duration, CLKR/X high or
CLKR/X low
C - 2(6)
C + 2(6)
C - 2(6)
C + 2(6)
ns
ns
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
-4
6.5
16.5
-4
13
18
Delay time, CLKR high to internal FSR
valid
4
9
1
1
-4
6.5
-4
13
Delay time, CLKX high to internal FSX
valid
td(CKXH-FXV)
ns
ns
ns
1
-4
16.5
1
-4
18
6.5
13
Disable time, DX high impedance
following last data bit from CLKX high
12 tdis(CKXH-DXHZ)
-2
16.5
-2
18
-4 + D1(7)
1 + D1(7)
-4(8)
6.5 + D2(7)
16.5 + D2(7)
6.5(8)
-4 + D1(7)
1 + D1(7)
-4(8)
13 + D2(7)
18 + D2(7)
13(8)
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
14 td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-2(8)
16.5(8)
-2(8)
18(9)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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Table 6-57. Switching Characteristics for McBSP1 [1.0V](1) (2)
(see Figure 6-31)
1.0V
NO.
1
PARAMETER
UNIT
ns
MIN
1.5
MAX
23
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input
td(CKSH-CKRXH)
2P or
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
26.6(3) (4)
ns
(5)
3
4
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
C - 2(6)
C + 2(6)
13
ns
ns
-4
td(CKRH-FRV)
2.5
23
-4
13
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
1
-4
23
13
Disable time, DX high impedance following last data bit from CLKX
high
12 tdis(CKXH-DXHZ)
-2
23
-4 + D1(7)
1 + D1(8)
-4(9)
13 + D2(8)
23 + D2(8)
13(9)
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
14 td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-2(9)
23(9)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
3
8
Bit(n1)
(n2)
(n3)
2
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13 (A)
14
12
13 (A)
DX
Bit 0
Bit(n1)
(n2)
(n3)
Figure 6-31. McBSP Timing(B)
Table 6-58. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-32)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
4
MAX MIN MAX MIN
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4.5
4
5
4
ns
ns
4
Table 6-59. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-32)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
5
MAX MIN MAX MIN
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
5
4
10
4
ns
ns
4
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 6-32. FSR Timing When GSYNC = 1
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6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-33 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
Configuration Bus
16-Bit Shift Register
16-Bit Buffer
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
DMA Requests
Clock
Control
Figure 6-33. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin
when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
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Optional − Slave Chip Select
Optional Enable (Ready)
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
MASTER SPI
SLAVE SPI
Figure 6-34. Illustration of SPI Master-to-SPI Slave Connection
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6.16.1 SPI Peripheral Registers Description(s)
Table 6-60 is a list of the SPI registers.
Table 6-60. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
ACRONYM
DESCRIPTION
Global Control Register 0
BYTE ADDRESS
0x01F0 E000
0x01F0 E004
0x01F0 E008
0x01F0 E00C
0x01F0 E010
0x01F0 E014
0x01F0 E018
0x01F0 E01C
0x01F0 E020
0x01F0 E024
0x01F0 E028
0x01F0 E02C
0x01F0 E030
0x01F0 E034
0x01F0 E038
0x01F0 E03C
0x01F0 E040
0x01F0 E044
0x01F0 E048
0x01F0 E04C
0x01F0 E050
0x01F0 E054
0x01F0 E058
0x01F0 E05C
0x01F0 E060
0x01F0 E064
0x01C4 1000
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010
0x01C4 1014
0x01C4 1018
0x01C4 101C
0x01C4 1020
0x01C4 1024
0x01C4 1028
0x01C4 102C
0x01C4 1030
0x01C4 1034
0x01C4 1038
0x01C4 103C
0x01C4 1040
0x01C4 1044
0x01C4 1048
0x01C4 104C
0x01C4 1050
0x01C4 1054
0x01C4 1058
0x01C4 105C
0x01C4 1060
0x01C4 1064
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
Flag Register
SPIPC0
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
Emulation Register
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
INTVEC0
INTVEC1
Format Register 1
Format Register 2
Format Register 3
Interrupt Vector for SPI INT0
Interrupt Vector for SPI INT1
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6.16.2 SPI Electrical Data/Timing
6.16.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-35
through Figure 6-38).
Table 6-61. General Timing Requirements for SPI0 Master Modes(1)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
256P
MIN
MAX
256P
Cycle Time, SPI0_CLK, All Master
Modes
1
2
3
tc(SPC)M
20(2)
256P
30(2)
40(2)
ns
ns
ns
Pulse Width High, SPI0_CLK, All
Master Modes
tw(SPCH)M
tw(SPCL)M
0.5M-1
0.5M-1
0.5M-1
0.5M-1
0.5M-1
0.5M-1
Pulse Width Low, SPI0_CLK, All
Master Modes
Delay,
initial
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
-0.5M+5
5
5
6
data bit
valid on
SPI0_SI
MO after
initial
Polarity = 0, Phase = 1,
to SPI0_CLK rising
-0.5M+5
5
-0.5M+6
6
4
5
6
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
edge on
SPI0_CL
K(3)
Polarity = 1, Phase = 1,
to SPI0_CLK falling
-0.5M+5
-0.5M+5
-0.5M+6
Delay,
Polarity = 0, Phase = 0,
5
5
5
5
5
5
6
6
6
subsequ from SPI0_CLK rising
ent bits
Polarity = 0, Phase = 1,
valid on
from SPI0_CLK falling
SPI0_SI
Polarity = 1, Phase = 0,
from SPI0_CLK falling
MO after
transmit
edge of
SPI0_CL
K
Polarity = 1, Phase = 1,
from SPI0_CLK rising
5
5
6
Output
hold
time,
SPI0_SI
MO valid
after
receive
edge of
SPI0_CL
K
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5M-3
0.5M-3
0.5M-3
Input
Polarity = 0, Phase = 0,
to SPI0_CLK falling
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Setup
Time,
SPI0_S
OMI
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
7
tsu(SOMI_SPC)M valid
before
ns
receive
edge of
SPI0_CL
K
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.5
1.5
1.5
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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(1)
Table 6-61. General Timing Requirements for SPI0 Master Modes
(continued)
1.3V, 1.2V
MIN MAX
1.1V
1.0V
MIN MAX
NO.
PARAMETER
UNIT
MIN
4
MAX
Input
Hold
Polarity = 0, Phase = 0,
from SPI0_CLK falling
4
4
4
5
5
5
Time,
SPI0_S
OMI
Polarity = 0, Phase = 1,
from SPI0_CLK rising
4
4
Polarity = 1, Phase = 0,
from SPI0_CLK rising
8
tih(SPC_SOMI)M valid
ns
after
receive
edge of
SPI0_CL
K
Polarity = 1, Phase = 1,
from SPI0_CLK falling
4
4
5
Table 6-62. General Timing Requirements for SPI0 Slave Modes(1)
1.3V, 1.2V
1.1V
1.0V
MIN
60(2)
NO.
9
PARAMETER
UNIT
MIN
40(2)
18
MAX
MIN
MAX
256P
MAX
256P
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
256P
50(2)
22
ns
ns
ns
10 tw(SPCH)S
11 tw(SPCL)S
27
18
22
27
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
Setup time, transmit
Polarity = 0, Phase = 1,
data written to SPI
to SPI0_CLK rising
12 tsu(SOMI_SPC)S before initial clock
edge from
ns
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
master.(3) (4)
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
17
17
17
17
20
20
20
20
27
27
27
27
Delay, subsequent
bits valid on
SPI0_SOMI after
transmit edge of
SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
13 td(SPC_SOMI)S
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5S-6
0.5S-6
0.5S-6
0.5S-6
1.5
0.5S-16
0.5S-16
0.5S-16
0.5S-16
1.5
0.5S-20
0.5S-20
0.5S-20
0.5S-20
1.5
Output hold time,
SPI0_SOMI valid
14 toh(SPC_SOMI)S after
receive edge of
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
SPI0_CLK
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
Input Setup Time,
SPI0_SIMO valid
15 tsu(SIMO_SPC)S before
Polarity = 0, Phase = 1,
to SPI0_CLK rising
1.5
1.5
1.5
Polarity = 1, Phase = 0,
to SPI0_CLK rising
receive edge of
SPI0_CLK
1.5
1.5
1.5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
1.5
1.5
1.5
(1) P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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(1)
Table 6-62. General Timing Requirements for SPI0 Slave Modes
(continued)
1.3V, 1.2V
1.1V
MIN
1.0V
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
4
4
4
4
4
5
5
5
5
Input Hold Time,
SPI0_SIMO valid
16 tih(SPC_SIMO)S after
receive edge of
Polarity = 0, Phase = 1,
from SPI0_CLK rising
4
4
4
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
SPI0_CLK
Polarity = 1, Phase = 1,
from SPI0_CLK falling
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(1) (2) (3)
Table 6-63. Additional SPI0 Master Timings, 4-Pin Enable Option
1.3V, 1.2V
1.1V
MAX
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MIN
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5
3P+5
0.5M+3P+5
3P+5
3P+6
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+3P+5
3P+5
0.5M+3P+6
3P+6
Delay from slave assertion of SPI0_ENA active to first
17 td(ENA_SPC)M
ns
SPI0_CLK from master.(4)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5
0.5M+P+5
P+5
0.5M+3P+5
0.5M+P+5
P+5
0.5M+3P+6
0.5M+P+6
P+6
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert SPI0_ENA after final SPI0_CLK
edge to ensure master does not begin the next transfer.(5)
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-61 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
(1) (2) (3)
Table 6-64. Additional SPI0 Master Timings, 4-Pin Chip Select Option
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P-1
2P-2
2P-3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+2P-1
2P-1
0.5M+2P-2
2P-2
0.5M+2P-3
2P-3
19 td(SCS_SPC)M
Delay from SPI0_SCS active to first SPI0_CLK(4) (5)
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+2P-1
0.5M+2P-2
0.5M+2P-3
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-61 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
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(1) (2) (3)
Table 6-64. Additional SPI0 Master Timings, 4-Pin Chip Select Option
(continued)
1.3V, 1.2V
1.1V
1.0V
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MAX
Polarity = 0, Phase = 0,
0.5M+P-1
0.5M+P-2
0.5M+P-3
P-3
from SPI0_CLK falling
Polarity = 0, Phase = 1,
P-1
P-2
0.5M+P-2
P-2
from SPI0_CLK falling
Delay from final SPI0_CLK edge to master deasserting
SPI0_SCS
20 td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P-1
P-1
0.5M+P-3
P-3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(1) (2) (3)
Table 6-65. Additional SPI0 Master Timings, 5-Pin Option
1.3V, 1.2V
MAX
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.(4)
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P-2
P-2
0.5M+P-2
P-2
0.5M+P-3
P-3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS
20 td(SPC_SCS)M
ns
ns
(5) (6)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P-2
P-2
0.5M+P-2
P-2
0.5M+P-3
P-3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after master
21 td(SCSL_ENAL)M asserts SPI0_SCS to delay the master from beginning the next
transfer,
C2TDELAY+P
C2TDELAY+P
C2TDELAY+P
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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(1) (2) (3)
Table 6-65. Additional SPI0 Master Timings, 5-Pin Option
(continued)
1.3V, 1.2V
1.1V
MAX
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P-2
2P-2
2P-3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+2P-2
2P-2
0.5M+2P-2
2P-2
0.5M+2P-3
2P-3
Delay from SPI0_SCS active to first
SPI0_CLK(7) (8) (9)
22 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+2P-2
0.5M+2P-2
0.5M+2P-3
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P+5
0.5M+3P+5
3P+5
3P+5
0.5M+3P+5
3P+5
3P+6
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5M+3P+6
3P+6
Delay from assertion of SPI0_ENA
low to first SPI0_CLK edge.(10)
23 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5M+3P+5
0.5M+3P+5
0.5M+3P+6
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
(1) (2) (3)
Table 6-66. Additional SPI0 Slave Timings, 4-Pin Enable Option
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5P-3
2.5P+17.5
–
1.5P-3
2.5P+20
1.5P-3
2.5P+27
Polarity = 0, Phase = 1,
from SPI0_CLK falling
–
–
Delay from final
– 0.5M+1.5P-3 0.5M+2.5P+17. – 0.5M+1.5P-3
5
– 0.5M+1.5P-3
0.5M+2.5P+20
0.5M+2.5P+27
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
24 td(SPC_ENAH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
1.5P-3
2.5P+17.5
1.5P-3
2.5P+20
1.5P-3
2.5P+27
Polarity = 1, Phase = 1,
from SPI0_CLK rising
–
– 0.5M+1.5P-3
– 0.5M+1.5P-3
– 0.5+2.5P+20
– 0.5M+1.5P-3
– 0.5+2.5P+27
0.5+2.5P+17.5
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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(1) (2) (3)
Table 6-67. Additional SPI0 Slave Timings, 4-Pin Chip Select Option
1.3V, 1.2V
1.1V
MIN
P + 1.5
1.0V
MIN
NO.
PARAMETER
UNIT
ns
MIN
MAX
MAX
MAX
25 td(SCSL_SPC)S
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.
P + 1.5
P + 1.5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4
P+4
0.5M+P+4
P+4
0.5M+P+5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5
0.5M+P+5
P+5
Required delay from final SPI0_CLK edge before SPI0_SCS is
deasserted.
26 td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5M+P+4
P+4
0.5M+P+4
P+4
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+17.
5
27 tena(SCSL_SOMI)S
28 tdis(SCSH_SOMI)S
Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI
P+20
P+20
P+27
P+27
ns
ns
P+17.
5
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(1) (2) (3)
Table 6-68. Additional SPI0 Slave Timings, 5-Pin Option
1.3V, 1.2V
1.1V
MIN
1.0V
MIN
NO.
PARAMETER
UNIT
ns
MIN
P + 1.5
MAX
MAX
MAX
25 td(SCSL_SPC)S
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.
P + 1.5
P + 1.5
Polarity = 0, Phase = 0, 0.5M+P
0.5M+P
+4
0.5M+P
+5
from SPI0_CLK falling
+4
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+4
P+4
P+5
Required delay from final SPI0_CLK edge before SPI0_SCS is
deasserted.
26 td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0, 0.5M+P
from SPI0_CLK rising
0.5M+P
+4
0.5M+P
+5
+4
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4
P+4
P+5
27 tena(SCSL_SOMI)S
28 tdis(SCSH_SOMI)S
29 tena(SCSL_ENA)S
Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid
P+17.5
P+17.5
17.5
P+20
P+20
20
P+27
P+27
27
ns
ns
ns
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-62 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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(1) (2) (3)
Table 6-68. Additional SPI0 Slave Timings, 5-Pin Option
(continued)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5P+17
.5
2.5P+20
2.5P+20
2.5P+20
2.5P+20
2.5P+27
2.5P+27
2.5P+27
2.5P+27
Polarity = 0, Phase = 1,
from SPI0_CLK rising
2.5P+17
.5
Delay from final clock receive edge on SPI0_CLK to slave 3-stating
or driving high SPI0_ENA.(4)
30 tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
2.5P+17
.5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
2.5P+17
.5
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
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Table 6-69. General Timing Requirements for SPI1 Master Modes(1)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
20(2)
MAX
256P
MIN
30(2)
MAX
256P
MIN
40(2)
MAX
256P
1
2
tc(SPC)M
tw(SPCH)M
tw(SPCL)M
Cycle Time, SPI1_CLK, All Master Modes
ns
ns
Pulse Width High, SPI1_CLK, All Master
Modes
0.5M-1
0.5M-1
0.5M-1
0.5M-1
0.5M-1
Pulse Width Low, SPI1_CLK, All Master
Modes
3
0.5M-1
ns
Polarity = 0, Phase =
0,
5
5
6
to SPI1_CLK rising
Polarity = 0, Phase =
Delay, initial data
1,
-0.5M+5
5
-0.5M+5
5
-0.5M+6
6
bit valid on
to SPI1_CLK rising
4,5 td(SIMO_SPC)M SPI1_SIMO to
initial edge on
ns
Polarity = 1, Phase =
0,
SPI1_CLK(3)
to SPI1_CLK falling
Polarity = 1, Phase =
1,
-0.5M+5
-0.5M+5
-0.5M+6
to SPI1_CLK falling
Polarity = 0, Phase =
0,
5
5
5
5
5
5
5
5
6
6
6
6
from SPI1_CLK
rising
Polarity = 0, Phase =
1,
from SPI1_CLK
falling
Delay, subsequent
bits valid on
5
td(SPC_SIMO)M SPI1_SIMO after
transmit edge of
ns
Polarity = 1, Phase =
0,
from SPI1_CLK
falling
SPI1_CLK
Polarity = 1, Phase =
1,
from SPI1_CLK
rising
Polarity = 0, Phase =
0,
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
0.5M-3
from SPI1_CLK
falling
Polarity = 0, Phase =
1,
from SPI1_CLK
rising
Output hold time,
SPI1_SIMO valid
6
toh(SPC_SIMO)M after
receive edge of
ns
Polarity = 1, Phase =
0,
from SPI1_CLK
rising
SPI1_CLK
Polarity = 1, Phase =
1,
from SPI1_CLK
falling
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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(1)
Table 6-69. General Timing Requirements for SPI1 Master Modes
(continued)
1.3V, 1.2V
MIN MAX
1.1V
1.0V
MIN MAX
NO.
PARAMETER
UNIT
MIN
1.5
MAX
Polarity = 0, Phase =
0,
to SPI1_CLK falling
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SOMI valid
tsu(SOMI_SPC)M before
1.5
1.5
1.5
7
ns
Polarity = 1, Phase =
0,
to SPI1_CLK rising
receive edge of
SPI1_CLK
Polarity = 1, Phase =
1,
to SPI1_CLK falling
Polarity = 0, Phase =
0,
4
4
4
4
5
5
5
5
6
6
6
6
from SPI1_CLK
falling
Polarity = 0, Phase =
1,
from SPI1_CLK
rising
Input Hold Time,
SPI1_SOMI valid
8
tih(SPC_SOMI)M after
ns
Polarity = 1, Phase =
0,
from SPI1_CLK
rising
receive edge of
SPI1_CLK
Polarity = 1, Phase =
1,
from SPI1_CLK
falling
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Table 6-70. General Timing Requirements for SPI1 Slave Modes(1)
1.3V, 1.2V
1.1V
1.0V
MIN
60(2)
NO.
PARAMETER
UNIT
MIN
40(2)
18
MAX
MIN
MAX
256P
MAX
256P
9
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
Pulse Width High, SPI1_CLK, All Slave Modes
Pulse Width Low, SPI1_CLK, All Slave Modes
256P
50(2)
22
ns
ns
ns
10 tw(SPCH)S
11 tw(SPCL)S
27
18
22
27
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Setup time, transmit data
written to SPI before initial
clock edge from
12 tsu(SOMI_SPC)S
ns
ns
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
master.(3) (4)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK rising
15
15
15
15
17
17
17
17
19
19
19
19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay, subsequent bits valid
on SPI1_SOMI after
transmit edge of SPI1_CLK
13 td(SPC_SOMI)S
Polarity = 1, Phase = 0,
from SPI1_CLK falling
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5S-4
0.5S-4
0.5S-4
0.5S-4
1.5
0.5S-10
0.5S-12
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5S-10
0.5S-12
Output hold time,
14 toh(SPC_SOMI)S SPI1_SOMI valid after
receive edge of SPI1_CLK
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5S-10
0.5S-12
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5S-10
0.5S-12
Polarity = 0, Phase = 0,
to SPI1_CLK falling
1.5
1.5
1.5
1.5
5
1.5
1.5
1.5
1.5
6
Polarity = 0, Phase = 1,
to SPI1_CLK rising
1.5
Input Setup Time,
15 tsu(SIMO_SPC)S SPI1_SIMO valid before
receive edge of SPI1_CLK
Polarity = 1, Phase = 0,
to SPI1_CLK rising
1.5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
1.5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
4
Polarity = 0, Phase = 1,
from SPI1_CLK rising
4
5
6
Input Hold Time,
16 tih(SPC_SIMO)S SPI1_SIMO valid after
receive edge of SPI1_CLK
Polarity = 1, Phase = 0,
from SPI1_CLK rising
4
5
6
Polarity = 1, Phase = 1,
from SPI1_CLK falling
4
5
6
(1) P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)
(2) This timing is limited by the timing shown or 3P, whichever is greater.
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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Table 6-71. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)
1.3V, 1.2V
1.1V
MAX
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MIN
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5
3P+5
0.5M+3P+5
3P+5
3P+6
Delay from slave
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5
3P+5
0.5M+3P+6
3P+6
assertion of SPI1_ENA
active to first
17 td(EN A_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
SPI1_CLK from
master.(4)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5
0.5M+P+5
P+5
0.5M+3P+5
0.5M+P+5
P+5
0.5M+3P+6
0.5M+P+6
P+6
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Max delay for slave to
deassert SPI1_ENA
after final SPI1_CLK
edge to ensure master
does not begin the
next transfer.(5)
Polarity = 0, Phase = 1,
from SPI1_CLK falling
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5
P+5
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-69 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 6-72. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)
1.3V, 1.2V
1.1V
MIN
1.0V
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
MAX
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P-1
2P-5
0.5M+2P-5
2P-5
2P-6
0.5M+2P-6
2P-6
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Delay from
0.5M+2P-1
2P-1
SPI1_SCS active
to first
19 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
SPI1_CLK(4) (5)
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+2P-1
0.5M+P-1
P-1
0.5M+2P-5
0.5M+P-5
P-5
0.5M+2P-6
0.5M+P-6
P-6
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final
SPI1_CLK edge to
master
Polarity = 0, Phase = 1,
from SPI1_CLK falling
20 td(SPC_SCS)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
deasserting
0.5M+P-1
P-1
0.5M+P-5
P-5
0.5M+P-6
P-6
(6) (7)
SPI1_SCS
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-69 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-73. Additional(1) SPI1 Master Timings, 5-Pin Option(2) (3)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+5
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5
0.5M+P+5
P+5
Max delay for slave to deassert SPI1_ENA after final
SPI1_CLK edge to ensure master does not begin the next
transfer.(4)
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P-1
P-1
0.5M+P-5
P-5
0.5M+P-6
P-6
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final SPI1_CLK edge to
master deasserting SPI1_SCS
20 td(SPC_SCS)M
ns
ns
ns
(5) (6)
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P-1
P-1
0.5M+P-5
P-5
0.5M+P-6
P-6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to
21 td(SCSL_ENAL)M delay the
master from beginning the next transfer,
C2TDELAY+P
C2TDELAY+P
C2TDELAY+P
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P-1
2P-5
2P-6
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+2P-1
2P-1
0.5M+2P-5
2P-5
0.5M+2P-6
2P-6
22 td(SCS_SPC)M
Delay from SPI1_SCS active to first SPI1_CLK(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+2P-1
0.5M+2P-5
0.5M+2P-6
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-70 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
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(2) (3)
Table 6-73. Additional (1) SPI1 Master Timings, 5-Pin Option
(continued)
1.3V, 1.2V
MIN MAX
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
3P+5
MIN
MAX
3P+6
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P+5
0.5M+3P+5
3P+5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5M+3P+5
3P+5
0.5M+3P+6
3P+6
Delay from assertion of SPI1_ENA low to first SPI1_CLK
edge.(10)
23 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5M+3P+5
0.5M+3P+5
0.5M+3P+6
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-74. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5P-3
2.5P+15
1.5P-10
2.5P+17
1.5P-12
2.5P+19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19
–0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19
Delay from final
24 td(SPC_ENAH)S SPI1_CLK edge to slave
deasserting SPI1_ENA.
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-70 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-75. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)
1.3V, 1.2V
MIN MAX
P+1.5
1.1V
1.0V
NO.
PARAMETER
UNIT
ns
MIN
MAX
MIN
MAX
25 td(SCSL_SPC)S
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.
P+1.5
P+1.5
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-70 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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(2) (3)
Table 6-75. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option
(continued)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+4
0.5M+P+4
P+4
Required delay from final SPI1_CLK edge before
SPI1_SCS is deasserted.
26 td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
P+15
P+15
P+17
P+17
P+19
P+19
ns
ns
Table 6-76. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
ns
MIN
MAX
MIN
MAX
MIN
MAX
25 td(SCSL_SPC)S
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.
P+1.5
P+1.5
P+1.5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4
P+4
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Required delay from final SPI1_CLK edge before
SPI1_SCS is deasserted.
26 td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5M+P+4
P+4
0.5M+P+5
P+5
0.5M+P+6
P+6
Polarity = 1, Phase = 1,
from SPI1_CLK rising
27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
29 tena(SCSL_ENA)S Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid
P+15
P+15
15
P+17
P+17
17
P+19
P+19
19
ns
ns
ns
(1) These parameters are in addition to the general timings for SPI slave modes ( Table 6-70 ).
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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(2) (3)
Table 6-76. Additional (1) SPI1 Slave Timings, 5-Pin Option
(continued)
1.3V, 1.2V
MIN MAX
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5P+15
2.5P+15
2.5P+15
2.5P+15
2.5P+17
2.5P+19
2.5P+19
2.5P+19
2.5P+19
Polarity = 0, Phase = 1,
from SPI1_CLK rising
2.5P+17
2.5P+17
2.5P+17
Delay from final clock receive edge on SPI1_CLK to slave
3-stating or driving high SPI1_ENA.(4)
30 tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 6-35. SPI Timings—Master Mode
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9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(n−1)
SO(0)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
Figure 6-36. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-37. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPIx_SOMI
SPIx_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
(A)
(A)
DESEL
DESEL
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-38. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.17 Inter-Integrated Circuit Serial Ports (I2C)
6.17.1 I2C Device-Specific Information
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
Figure 6-39 is block diagram of the device I2C Module.
Clock Prescaler
Control
I2CCOARx
Prescaler
Register
Own Address
Register
I2CPSCx
Slave Address
Register
I2CSARx
Bit Clock Generator
Noise
I2Cx_SCL
Clock Divide
High Register
I2CCLKHx
Filter
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
Peripheral ID
Register 1
Transmit Shift
Register
I2CXSRx
I2CDXRx
Peripheral ID
Register 2
I2CPID2
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
I2CRSRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
I2CPDIR
I2CPDIN
Pin Direction
Register
Pin Data In
Register
Pin Data Set
Register
Pin Data Clear
Register
I2CPDSET
I2CPDCLR
Figure 6-39. I2C Module Block Diagram
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6.17.2 I2C Peripheral Registers Description(s)
Table 6-77 is the list of the I2C registers.
Table 6-77. Inter-Integrated Circuit (I2C) Registers
I2C0
BYTE ADDRESS
I2C1
ACRONYM
REGISTER DESCRIPTION
I2C Own Address Register
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
ICOAR
ICIMR
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
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6.17.3 I2C Electrical Data/Timing
6.17.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-78 and Table 6-79 assume testing over recommended operating conditions (see Figure 6-40 and
Figure 6-41).
Table 6-78. Timing Requirements for I2C Input
1.3V, 1.2V, 1.1V, 1.0V
NO.
PARAMETER
Standard Mode
Fast Mode
MIN MAX
UNIT
MIN
10
4.7
4
MAX
1
2
tc(SCL)
Cycle time, I2Cx_SCL
2.5
ms
ms
ms
ms
ms
ns
ms
ms
ns
ns
ns
ns
ms
ns
pF
tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low
0.6
3
th(SCLL-SDAL)
tw(SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
Pulse duration, I2Cx_SCL high
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Rise time, I2Cx_SDA
0.6
4
4.7
4
1.3
5
tw(SCLH)
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
tr(SDA)
0.6
100
6
250
0
7
0
0.9
8
4.7
1.3
9
1000
1000
300
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0.6
300
300
300
300
10
11
12
13
14
15
tr(SCL)
Rise time, I2Cx_SCL
tf(SDA)
Fall time, I2Cx_SDA
tf(SCL)
Fall time, I2Cx_SCL
300
tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high
4
tw(SP)
Cb
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
N/A
0
50
400
400
(1)
Table 6-79. Switching Characteristics for I2C
1.3V, 1.2V, 1.1V, 1.0V
NO.
PARAMETER
Standard Mode
Fast Mode
MAX
UNIT
MIN
10
4.7
4
MAX
MIN
2.5
0.6
0.6
1.3
0.6
100
0
16
17
18
19
20
21
22
23
28
tc(SCL)
Cycle time, I2Cx_SCL
ms
ms
ms
ms
ms
ns
ms
ms
ms
tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low
th(SDAL-SCLL)
tw(SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
4.7
4
tw(SCLH)
Pulse duration, I2Cx_SCL high
tsu(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high
250
0
th(SCLL-SDAV)
tw(SDAH)
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
0.9
4.7
4
1.3
0.6
tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high
(1) I2C must be configured correctly to meet the timings in Table 6-79 .
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11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-40. I2C Receive Timings
26
24
I2Cx_SDA
I2Cx_SCL
21
23
19
28
20
25
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-41. I2C Transmit Timings
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6.18 Universal Asynchronous Receiver/Transmitter (UART)
Each UART has the following features:
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 3MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS)
The UART registers are listed in Section 6.18.1
6.18.1 UART Peripheral Registers Description(s)
Table 6-80 is the list of UART registers.
Table 6-80. UART Registers
UART0
BYTE ADDRESS
UART1
BYTE ADDRESS
UART2
ACRONYM
REGISTER DESCRIPTION
BYTE ADDRESS
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D018
0x01D0 D01C
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2018
0x01C4 201C
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
0x01D0 C000
0x01D0 C000
0x01D0 C004
0x01D0 C008
0x01D0 C008
0x01D0 C00C
0x01D0 C010
0x01D0 C014
0x01D0 C018
0x01D0 C01C
0x01D0 C020
0x01D0 C024
0x01D0 C028
0x01D0 C030
0x01D0 C034
RBR
THR
IER
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
IIR
FCR
LCR
MCR
LSR
Modem Control Register
Line Status Register
MSR
SCR
DLL
Modem Status Register
Scratchpad Register
Divisor LSB Latch
DLH
REVID1
Divisor MSB Latch
Revision Identification Register 1
PWREMU_MGMT Power and Emulation Management Register
MDR
Mode Definition Register
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6.18.2 UART Electrical Data/Timing
Table 6-81. Timing Requirements for UART Receive(1) (see Figure 6-42)
1.3V, 1.2V, 1.1V, 1.0V
NO.
PARAMETER
UNIT
MIN
MAX
1.05U
1.05U
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
0.96U
0.96U
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-82. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-42)
1.3V, 1.2V, 1.1V, 1.0V
NO.
PARAMETER
UNIT
MIN
MAX
(2) (3)
(4)
1
2
3
f(baud)
Maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
D/E
MBaud
ns
tw(UTXDB)
tw(UTXSB)
U - 2
U - 2
U + 2
U + 2
ns
(1) U = UART baud time = 1/programmed baud rate.
(2) D = UART input clock in MHz.
For UART0, the UART input clock is SYSCLK2.
For UART1 or UART2, the UART input clock is ASYNC3 (either PLL0_SYCLK2 or PLL1_SYSCLK2).
(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF/DDR loading,
system frequency, etc.
3
2
Start
UART_TXDn
Bit
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 6-42. UART Transmit/Receive Timing
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6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
The USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
•
Integrated USB 2.0 High Speed PHY
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Table 6-83 is the list of USB OTG registers.
Table 6-83. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
0x01E0 0000
0x01E0 0004
0x01E0 0008
0x01E0 000C
0x01E0 0010
0x01E0 0014
0x01E0 0018
0x01E0 001C
0x01E0 0020
0x01E0 0024
0x01E0 0028
0x01E0 002C
0x01E0 0030
0x01E0 0034
0x01E0 0038
0x01E0 003C
0x01E0 0040
0x01E0 0050
0x01E0 0054
0x01E0 0058
0x01E0 005C
0x01E0 0400
0x01E0 0401
0x01E0 0402
0x01E0 0404
0x01E0 0406
0x01E0 0408
0x01E0 040A
0x01E0 040B
0x01E0 040C
0x01E0 040E
0x01E0 040F
ACRONYM
REVID
REGISTER DESCRIPTION
Revision Register
CTRLR
Control Register
STATR
Status Register
EMUR
Emulation Register
MODE
Mode Register
AUTOREQ
SRPFIXTIME
TEARDOWN
INTSRCR
INTSETR
Autorequest Register
SRP Fix Time Register
Teardown Register
USB Interrupt Source Register
USB Interrupt Source Set Register
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
USB Interrupt Source Clear Register
USB Interrupt Mask Register
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
INTVECTR
GENRNDISSZ1
GENRNDISSZ2
GENRNDISSZ3
GENRNDISSZ4
FADDR
USB Interrupt Vector Register
Generic RNDIS Size EP1
Generic RNDIS Size EP2
Generic RNDIS Size EP3
Generic RNDIS Size EP4
Function Address Register
POWER
Power Management Register
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
Register to Enable the USB 2.0 Test Modes
TESTMODE
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Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Indexed Registers
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410
0x01E0 0412
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index register set to select
Endpoints 1-4 only)
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint
0)
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints
1-4)
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
0x01E0 0416
Maximum Packet Size for Peripheral/Host Receive Endpoint (Index register set to select
Endpoints 1-4 only)
PERI_RXCSR
HOST_RXCSR
COUNT0
Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints
1-4)
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
0x01E0 041A
0x01E0 041B
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint. (Index register set to select Endpoints 1-4 only)
HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041C
0x01E0 041D
0x01E0 041F
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint. (Index register set to select Endpoints 1-4 only)
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only)
CONFIGDATA
Returns details of core configuration. (Index register set to select Endpoint 0)
FIFO
0x01E0 0420
0x01E0 0424
0x01E0 0428
0x01E0 042C
0x01E0 0430
FIFO0
FIFO1
FIFO2
FIFO3
FIFO4
Transmit and Receive FIFO Register for Endpoint 0
Transmit and Receive FIFO Register for Endpoint 1
Transmit and Receive FIFO Register for Endpoint 2
Transmit and Receive FIFO Register for Endpoint 3
Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
0x01E0 0460
DEVCTL
Device Control Register
Dynamic FIFO Control
0x01E0 0462
0x01E0 0463
0x01E0 0464
TXFIFOSZ
RXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
TXFIFOADDR
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 0464
0x01E0 0466
HWVERS
Hardware Version Register
RXFIFOADDR
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
Target Endpoint 0 Control Registers, Valid Only in Host Mode
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Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 0480
ACRONYM
REGISTER DESCRIPTION
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
0x01E0 0482
0x01E0 0483
0x01E0 0484
0x01E0 0486
0x01E0 0487
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
0x01E0 0488
0x01E0 048A
0x01E0 048B
0x01E0 048C
0x01E0 048E
0x01E0 048F
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
0x01E0 0490
0x01E0 0492
0x01E0 0493
0x01E0 0494
0x01E0 0496
0x01E0 0497
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
0x01E0 0498
0x01E0 049A
0x01E0 049B
0x01E0 049C
0x01E0 049E
0x01E0 049F
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
TXHUBADDR
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
0x01E0 04A0
TXFUNCADDR
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
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Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 04A2
ACRONYM
REGISTER DESCRIPTION
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A3
0x01E0 04A4
0x01E0 04A6
0x01E0 04A7
TXHUBPORT
RXFUNCADDR
RXHUBADDR
RXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
Control Status Register for Endpoint 0 in Peripheral Mode
Control Status Register for Endpoint 0 in Host Mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
0x01E0 0502
PERI_CSR0
HOST_CSR0
COUNT0
0x01E0 0508
0x01E0 050A
0x01E0 050B
0x01E0 050F
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK Response Timeout on Endpoint 0
Returns details of core configuration.
Control and Status Register for Endpoint 1
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
0x01E0 0510
0x01E0 0512
TXMAXP
PERI_TXCSR
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0514
0x01E0 0516
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
HOST_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0518
0x01E0 051A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 051B
0x01E0 051C
0x01E0 051D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
0x01E0 0520
0x01E0 0522
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
HOST_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0524
0x01E0 0526
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
HOST_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0528
0x01E0 052A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 052B
0x01E0 052C
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
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Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 052D
ACRONYM
REGISTER DESCRIPTION
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
0x01E0 0530
0x01E0 0532
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
HOST_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0534
0x01E0 0536
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
HOST_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538
0x01E0 053A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 053B
0x01E0 053C
0x01E0 053D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540
0x01E0 0542
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
HOST_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544
0x01E0 0546
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
HOST_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0548
0x01E0 054A
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
0x01E0 054B
0x01E0 054C
0x01E0 054D
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
DMA Registers
0x01E0 1000
0x01E0 1004
0x01E0 1008
0x01E0 1800
0x01E0 1808
0x01E0 180C
0x01E0 1810
0x01E0 1820
0x01E0 1828
0x01E0 182C
0x01E0 1830
0x01E0 1840
DMAREVID
TDFDQ
DMA Revision Register
DMA Teardown Free Descriptor Queue Control Register
DMA Emulation Control Register
DMAEMU
TXGCR[0]
RXGCR[0]
RXHPCRA[0]
RXHPCRB[0]
TXGCR[1]
RXGCR[1]
RXHPCRA[1]
RXHPCRB[1]
TXGCR[2]
Transmit Channel 0 Global Configuration Register
Receive Channel 0 Global Configuration Register
Receive Channel 0 Host Packet Configuration Register A
Receive Channel 0 Host Packet Configuration Register B
Transmit Channel 1 Global Configuration Register
Receive Channel 1 Global Configuration Register
Receive Channel 1 Host Packet Configuration Register A
Receive Channel 1 Host Packet Configuration Register B
Transmit Channel 2 Global Configuration Register
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Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2C00
0x01E0 2D00
0x01E0 2D04
. . .
ACRONYM
RXGCR[2]
REGISTER DESCRIPTION
Receive Channel 2 Global Configuration Register
RXHPCRA[2]
RXHPCRB[2]
TXGCR[3]
Receive Channel 2 Host Packet Configuration Register A
Receive Channel 2 Host Packet Configuration Register B
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
RXGCR[3]
RXHPCRA[3]
RXHPCRB[3]
Receive Channel 3 Host Packet Configuration Register A
Receive Channel 3 Host Packet Configuration Register B
DMA_SCHED_CTRL DMA Scheduler Control Register
ENTRY[0]
ENTRY[1]
. . .
DMA Scheduler Table Word 0
DMA Scheduler Table Word 1
. . .
0x01E0 2DFC
ENTRY[63]
DMA Scheduler Table Word 63
Queue Manager Registers
0x01E0 4000
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
. . .
QMGRREVID
DIVERSION
FDBSC0
Queue Manager Revision Register
Queue Diversion Register
Free Descriptor/Buffer Starvation Count Register 0
Free Descriptor/Buffer Starvation Count Register 1
Free Descriptor/Buffer Starvation Count Register 2
Free Descriptor/Buffer Starvation Count Register 3
Linking RAM Region 0 Base Address Register
Linking RAM Region 0 Size Register
Linking RAM Region 1 Base Address Register
Queue Pending Register 0
FDBSC1
FDBSC2
FDBSC3
LRAM0BASE
LRAM0SIZE
LRAM1BASE
PEND0
PEND1
Queue Pending Register 1
QMEMRBASE[0]
QMEMRCTRL[0]
QMEMRBASE[1]
QMEMRCTRL[1]
. . .
Memory Region 0 Base Address Register
Memory Region 0 Control Register
Memory Region 1 Base Address Register
Memory Region 1 Control Register
. . .
0x01E0 5070
0x01E0 5074
0x01E0 600C
0x01E0 601C
. . .
QMEMRBASE[7]
QMEMRCTRL[7]
CTRLD[0]
Memory Region 7 Base Address Register
Memory Region 7 Control Register
Queue Manager Queue 0 Control Register D
Queue Manager Queue 1 Control Register D
. . .
CTRLD[1]
. . .
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
. . .
CTRLD[63]
QSTATA[0]
QSTATB[0]
QSTATC[0]
QSTATA[1]
QSTATB[1]
QSTATC[1]
. . .
Queue Manager Queue 63 Status Register D
Queue Manager Queue 0 Status Register A
Queue Manager Queue 0 Status Register B
Queue Manager Queue 0 Status Register C
Queue Manager Queue 1 Status Register A
Queue Manager Queue 1 Status Register B
Queue Manager Queue 1 Status Register C
. . .
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
QSTATA[63]
QSTATB[63]
QSTATC[63]
Queue Manager Queue 63 Status Register A
Queue Manager Queue 63 Status Register B
Queue Manager Queue 63 Status Register C
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6.19.1 USB0 [USB2.0] Electrical Data/Timing
Table 6-84. Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see
Figure 6-43)
1.3V, 1.2V, 1.1V, 1.0V
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
NO.
PARAMETER
UNIT
MIN
75
MAX
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB_DP and USB_DM signals(1)
Fall time, USB_DP and USB_DM signals(1)
Rise/Fall time, matching(2)
Output signal cross-over voltage(1)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter
Pulse duration, EOP receiver
300
300
120
2
20
20
111
2
ns
ns
%
tf(D)
75
4
trfM
80
90
1.3
–
–
VCRS
1.3
–
V
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
2
2
(3)ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
25
2
6
1
1
10
1
7
8
9
1250
670
1500
160
82
175
–
–
–
Data Rate
1.5
–
12
480 Mb/s
10 ZDRV
11 ZINP
Driver Output Resistance
–
40.5
49.5
40.5
-
49.5
-
Ω
Ω
Receiver Input Impedance
100k
100k
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
t
t
per − jr
USB_DM
90% V
OH
V
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 6-43. USB2.0 Integrated Transceiver Interface Timing
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6.20 LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
•
The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
•
The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability
of control signals (CS, WE, OE, ALE) and output data.
Table 6-85 lists the LCD Controller registers.
Table 6-85. LCD Controller Registers
BYTE ADDRESS
0x01E1 3000
0x01E1 3004
0x01E1 3008
0x01E1 300C
0x01E1 3010
0x01E1 3014
0x01E1 3018
0x01E1 301C
0x01E1 3020
0x01E1 3024
0x01E1 3028
0x01E1 302C
0x01E1 3030
0x01E1 3034
0x01E1 3038
0x01E1 3040
0x01E1 3044
0x01E1 3048
0x01E1 304C
0x01E1 3050
ACRONYM
REVID
REGISTER DESCRIPTION
LCD Revision Identification Register
LCD_CTRL
LCD Control Register
LCD_STAT
LCD Status Register
LIDD_CTRL
LCD LIDD Control Register
LIDD_CS0_CONF
LIDD_CS0_ADDR
LIDD_CS0_DATA
LIDD_CS1_CONF
LIDD_CS1_ADDR
LIDD_CS1_DATA
RASTER_CTRL
LCD LIDD CS0 Configuration Register
LCD LIDD CS0 Address Read/Write Register
LCD LIDD CS0 Data Read/Write Register
LCD LIDD CS1 Configuration Register
LCD LIDD CS1 Address Read/Write Register
LCD LIDD CS1 Data Read/Write Register
LCD Raster Control Register
RASTER_TIMING_0
RASTER_TIMING_1
RASTER_TIMING_2
RASTER_SUBPANEL
LCDDMA_CTRL
LCDDMA_FB0_BASE
LCDDMA_FB0_CEILING
LCDDMA_FB1_BASE
LCDDMA_FB1_CEILING
LCD Raster Timing 0 Register
LCD Raster Timing 1 Register
LCD Raster Timing 2 Register
LCD Raster Subpanel Display Register
LCD DMA Control Register
LCD DMA Frame Buffer 0 Base Address Register
LCD DMA Frame Buffer 0 Ceiling Address Register
LCD DMA Frame Buffer 1 Base Address Register
LCD DMA Frame Buffer 1 Ceiling Address Register
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6.20.1 LCD Interface Display Driver (LIDD Mode)
Table 6-86. Timing Requirements for LCD LIDD Mode
1.3V, 1.2V,
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
7
MAX MIN MAX
16 tsu(LCD_D)
17 th(LCD_D)
Setup time, LCD_D[15:0] valid before LCD_CLK (SYSCLK2) high
Hold time, LCD_D[15:0] valid after LCD_CLK (SYSCLK2) high
8
0
ns
ns
0
Table 6-87. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
1.3V, 1.2V,
1.0V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX MIN
MAX
9
4
5
6
7
8
9
td(LCD_D_V)
td(LCD_D_I)
td(LCD_E_A
td(LCD_E_I)
td(LCD_A_A)
td(LCD_A_I)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] valid (write)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] invalid (write)
Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS low
Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS high
Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC low
Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC high
Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC low
Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC high
0
0
0
0
0
0
0
0
0
0
0
0
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
)
9
9
9
9
10 td(LCD_W_A)
11 td(LCD_W_I)
9
9
12 td(LCD_STRB_A) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK high
13 td(LCD_STRB_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK low
9
9
14 td(LCD_D_Z)
15 td(Z_LCD_D)
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] in 3-state
9
Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] (valid from 3-state)
9
CS_DELAY
R_SU
1
R_HOLD
(1 to 15)
(0 to 3)
W_SU
(0 to 31)
(0 to 31)
2
W_STROBE
(1 to 63)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
W_HOLD
(1 to 15)
3
LCD_CLK
(SYSCLK2)
4
5
14
17
16
15
LCD_D[15:0]
LCD_PCLK
Write Data
Data[7:0]
Read Status
Not Used
RS
8
9
LCD_VSYNC
LCD_HSYNC
10
11
R/W
12
12
13
13
E0
E1
LCD_AC_ENB_CS
Figure 6-44. Character Display HD44780 Write
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W_HOLD
(1–15)
R_SU
(0–31)
R_STROBE R_HOLD CS_DELAY
(1–63) (1–5) (0−3)
W_SU
(0–31)
W_STROBE
(1–63)
CS_DELAY
(0 − 3)
1
2
Not
Used
3
LCD_CLK
(SYSCLK2)
4
17
15
5
14
16
LCD_D[7:0]
LCD_PCLK
Data[7:0]
Write Instruction
Read
Data
Not
Used
8
9
RS
LCD_VSYNC
LCD_HSYNC
10
11
R/W
12
13
13
12
E0
E1
LCD_AC_ENB_CS
Figure 6-45. Character Display HD44780 Read
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0−3)
1
2
3
Clock
LCD_CLK
(SYSCLK2)
4
6
5
7
5
4
LCD_D[15:0]
Write Address
Write Data
Data[15:0]
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
A0
R/W
E
LCD_VSYNC
10
11
10
11
LCD_HSYNC
LCD_PCLK
12
13
12
13
Figure 6-46. Micro-Interface Graphic Display 6800 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
CS_DELAY
(0−3)
R_STROBE R_HOLD CS_DELAY
(1−63 (0−3)
1
(1−63)
(1−15)
3
2
Clock
LCD_CLK
(SYSCLK2)
4
6
14
5
7
16
15
Data[15:0]
17
LCD_D[15:0]
Write Address
Read
Data
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
R/W
E
11
10
13
12
13
12
Figure 6-47. Micro-Interface Graphic Display 6800 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_HOLD CS_DELAY
R_STROBE
(1−63)
1
(1−63)
(1−15)
(0−3)
(1−15)
(0−3)
2
3
Clock
LCD_CLK
(SYSCLK2)
17
17
14 16
14
15
7
16
15
LCD_D[15:0]
Data[15:0]
Read
Status
Read
Data
6
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
8
9
LCD_VSYNC
LCD_HSYNC
A0
R/W
E
13
12
12
13
LCD_PCLK
Figure 6-48. Micro-Interface Graphic Display 6800 Status
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
W_STROBE
(1−63)
CS_DELAY
(0−3)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
(0 − 3)
1
2
(0−31)
3
Clock
LCD_CLK
(SYSCLK2)
4
5
4
5
LCD_D[15:0]
Write Address
Write Data
7
6
6
8
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
WR
RD
11
10
10
11
Figure 6-49. Micro-Interface Graphic Display 8080 Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
W_STROBE
(1−63)
CS_DELAY
R_STROBE
(1−63)
R_HOLD CS_DELAY
(1−15) (0−3)
1
(0−3)
Clock
2
3
LCD_CLK
(SYSCLK2)
4
6
5
16
17
15
Data[15:0]
14
LCD_D[15:0]
Write Address
Read
Data
7
7
6
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
LCD_VSYNC
LCD_HSYNC
LCD_PCLK
A0
11
10
WR
12
13
RD
Figure 6-50. Micro-Interface Graphic Display 8080 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_STROBE R_HOLD
CS_DELAY
(0−3)
1
2
(1−15)
(1−63)
(1−63)
(1−15)
(0−3)
3
Clock
LCD_CLK
(SYSCLK2)
17
16
17
15
14
6
16
15
7
14
6
Data[15:0]
LCD_D[15:0]
Read Data
Read Status
7
9
LCD_AC_ENB_CS
CS0
CS1
8
A0
WR
RD
LCD_VSYNC
LCD_HSYNC
12
13
13
12
LCD_PCLK
Figure 6-51. Micro-Interface Graphic Display 8080 Status
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6.20.2 LCD Raster Mode
Table 6-88. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
See Figure 6-52 through Figure 6-56
1.3V, 1.2V,
1.0V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX MIN
MAX
fclock(PIXEL_CLK)
tc(PIXEL_CLK)
Clock frequency, pixel clock
F/2(1)
F/2(1) MHz
1
2
3
4
5
6
7
8
9
Cycle time, pixel clock
26.66
33.33
ns
ns
ns
tw(PIXEL_CLK_H)
tw(PIXEL_CLK_L)
td(LCD_D_V)
Pulse duration, pixel clock high
10
10
0
10
10
0
Pulse duration, pixel clock low
Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)
Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write)
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high
Delay time, LCD_PCLK low to LCD_VSYNC high
Delay time, LCD_PCLK low to LCD_VSYNC low
Delay time, LCD_PCLK high to LCD_HSYNC high
Delay time, LCD_PCLK high to LCD_HSYNC low
7
7
7
7
7
7
7
7
9
9
9
9
9
9
9
9
ns
ns
ns
ns
ns
ns
ns
ns
td(LCD_D_IV)
0
0
td(LCD_AC_ENB_CS_A)
td(LCD_AC_ENB_CS_I)
td(LCD_VSYNC_A)
td(LCD_VSYNC_I)
0
0
0
0
0
0
0
0
10 td(LCD_HSYNC_A)
11 td(LCD_HSYNC_I)
(1) F = frequency of LCD_PCLK in ns
0
0
0
0
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-52. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
P−2,
1
P−1,
1
1, 1
1, 2
1, 3
2, 1
2, 2
3, 1
P, 1
P, 2
P, 3
P−1,
2
LCD
P,
1,
L−2
L−2
1,
L−1
2,
L−1
P,
L−1
P−1,
L−1
P−2,
L
P−1,
L
1, L
2, L
3, L
P, L
Figure 6-52. LCD Raster-Mode Display Format
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Frame Time ~ 70Hz
Active TFT
VSW
(1 to 64)
VBP
(0 to 255)
LPP
(1 to 1024)
VFP
VSW
(1 to 64)
(0 to 255)
Line
Time
Hsync
LCD_HSYNC
LCD_VSYNC
Vsync
Data
LCD_D[15:0]
1, L−1
P, L−1
1, L
P, L
1, 2
P, 2
1, 1
P, 1
Enable
LCD_AC_ENB_CS
ACB
(0 to 255)
ACB
(0 to 255)
10
11
Hsync
LCD_HSYNC
CLK
LCD_PCLK
Data
LCD_D[15:0]
2, 1
1, 2
P, 2
P, 1
1, 1
2, 2
PLL
HFP
HSW
HBP
(1 to 256)
PLL
16 y (1 to 1024)
16 y (1 to 1024)
(1 to 256)
(1 to 64)
Line 1
Line 2
Figure 6-53. LCD Raster-Mode Active
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Frame Time ~ 70Hz
VBP = 0
VFP = 0
VBP = 0
VFP = 0
VSW = 1
(1 to 64)
LPP
VSW = 1
Passive STN
LCD_HSYNC
(1 to 64)
(1 to 1024)
Line
Time
LP
FP
LCD_VSYNC
1, L
Data
1, 2
P, 2
1, 1:
P, 1
1, 5:
P, 5
1, L
P, L
1, 1
P, 1
1, L:
P, L
1, 3: 1, 4:
P, 3 P, 4
1, 6:
P, 6
1, 2:
P, 2
LCD_D[7:0]
1, L−1
P, L−1
1, L−4 1, L−3
P, L−4 P, L−3
1, L−2
P, L−2
1, L−1
P, L−1
M
LCD_AC_ENB_CS
ACB
ACB
(0 to 255)
(0 to 255)
11
10
LP
LCD_HSYNC
LCD_PCLK
LCD_D[7:0]
CP
Data
1, 5
P, 6
1, 6
2, 6
2, 5
P, 5
PPL
HFP
HSW
(1 to 64)
HBP
PPL
16 y (1 to 1024)
(1 to 256)
(1 to 256)
16 y (1 to 2024)
Line 6
Line 5
Figure 6-54. LCD Raster-Mode Passive
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6
LCD_AC_ENB_CS
8
LCD_VSYNC
LCD_HSYNC
11
10
1
2
3
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
2, L
2, 1
1, L
P, L
1, 1
P, 1
(passive mode)
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, L
P, L
2, L
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
(1 to 1024)
×
HFP
(1 to 256
(1 to 1024)
(1 to 64)
(1 to 256)
×
16
16
Line L
Line 1 (Passive Only)
Figure 6-55. LCD Raster-Mode Control Signal Activation
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7
LCD_AC_ENB_CS
9
LCD_VSYNC
11
10
LCD_HSYNC
1
3
4
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
2, 1
2, 2
1, 1
P, 1
1, 2
P, 2
(passive mode)
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_D[15:0]
(active mode)
1, 1
P, 1
2, 1
VBP = 0
VFP = 0
VSW = 1
PPL
HSW
HBP
PPL
(1 to 1024)
×
HFP
(1 to 1024)
(1 to 256
(1 to 64)
(1 to 256)
×
16
16
Line 1 for passive
Line 1 for active
Line 2 for passive
Figure 6-56. LCD Raster-Mode Control Signal Deactivation
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SPRS658B–FEBRUARY 2010–REVISED MAY 2010
6.21 Host-Port Interface (UHPI)
6.21.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16).
The host port interface (UHPI) provides a parallel port interface through which an external host processor
can directly access the processor's resources (configuration and program/data memories). The external
host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The UHPI
enables a host device and the processor to exchange information via internal or external memory.
Dedicated address (HPIA) and data (HPID) registers within the UHPI provide the data path between the
external host interface and the processor resources. A UHPI control register (HPIC) is available to the
host and the CPU for various configuration and interrupt functions.
6.21.2 HPI Peripheral Register Description(s)
Table 6-89. HPI Control Registers
BYTE ADDRESS
0x01E1 0000
ACRONYM
PID
REGISTER DESCRIPTION
COMMENTS
Peripheral Identification Register
The CPU has read/write access
to the PWREMU_MGMT register.
0x01E1 0004
PWREMU_MGMT
HPI power and emulation management register
0x01E1 0008
0x01E1 000C
0x01E1 0010
0x01E1 0014
0x01E1 0018
0x01E1 001C
0x01E1 0020
0x01E1 0024
01E1 0028
-
Reserved
GPIO_EN
GPIO_DIR1
GPIO_DAT1
GPIO_DIR2
GPIO_DAT2
GPIO_DIR3
GPIO_DAT3
-
General Purpose IO Enable Register
General Purpose IO Direction Register 1
General Purpose IO Data Register 1
General Purpose IO Direction Register 2
General Purpose IO Data Register 2
General Purpose IO Direction Register 3
General Purpose IO Data Register 3
Reserved
01E1 002C
-
Reserved
The Host and the CPU both have
read/write access to the HPIC
register.
01E1 0030
01E1 0034
HPIC
HPI control register
HPIA
HPI address register
(Write)
The Host has read/write access
to the HPIA registers. The CPU
has only read access to the HPIA
registers.
(HPIAW)(1)
HPIA
HPI address register
(Read)
01E1 0038
(HPIAR)(1)
01E1 000C - 01E1 07FF
-
Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
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6.21.3 HPI Electrical Data/Timing
Table 6-90. Timing Requirements for Host-Port Interface [1.3V, 1.2V, 1.1V](1) (2)
1.3V, 1.2V, 1.1V, 1.0V
NO.
UNIT
MIN
5
MAX
1
2
3
4
9
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tw(HSTBL)
Setup time, select signals(3) valid before UHPI_HSTROBE low
Hold time, select signals(3) valid after UHPI_HSTROBE low
Pulse duration, UHPI_HSTROBE active low
ns
ns
ns
ns
2
15
2M
5
tw(HSTBH)
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses
Setup time, selects signals valid before UHPI_HAS low
Hold time, select signals valid after UHPI_HAS low
tsu(SELV-HASL)
10 th(HASL-SELV)
11 tsu(HDV-HSTBH)
12 th(HSTBH-HDV)
2
Setup time, host data valid before UHPI_HSTROBE high
Hold time, host data valid after UHPI_HSTROBE high
5
ns
ns
2
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE
should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes
will not complete properly.
13 th(HRDYL-HSTBH)
2
ns
16 tsu(HASL-HSTBL)
17 th(HSTBL-HASH)
Setup time, UHPI_HAS low before UHPI_HSTROBE low
Hold time, UHPI_HAS low after UHPI_HSTROBE low
5
2
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period in ns.
(3) Select signals include: HCNTL[1:0], HR/W and HHWIL.
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Table 6-91. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface
[1.3V, 1.2V, 1.1V](1) (2) (3)
1.3V, 1.2V
1.1V
NO.
PARAMETER
UNIT
MIN
MAX MIN MAX
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with
auto-increment) and data not in Read
FIFO (can only happen to first half-word
of HPID access)
Delay time, HSTROBE low to
HRDY valid
5
td(HSTBL-HRDYV)
15
17
ns
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
5a
6
td(HASL-HRDYV)
ten(HSTBL-HDLZ)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDHZ)
Delay time, HAS low to HRDY valid
15
0
17
0
Enable time, HD driven from HSTROBE low
Delay time, HRDY low to HD valid
1.5
1.5
1.5
1.5
ns
ns
ns
ns
7
8
Output hold time, HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
14
15
17
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is already
in Read FIFO
Delay time, HSTROBE low to
HD valid
15
td(HSTBL-HDV)
15
17
ns
Case 3: Second half-word of HPID read
with or without auto-increment
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is
Delay time, HSTROBE high to full (can happen to either half-word)
18
td(HSTBH-HRDYV)
15
17
ns
HRDY valid
Case 2: HPIA write (can happen to
either half-word)
Case 3: HPID write without
auto-increment (only happens to
second half-word)
(1) M=SYSCLK2 period in ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
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Table 6-92. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface
[1.0V](1) (2) (3)
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
For HPI Write, HRDY can go high (not ready) for
these HPI Write conditions; otherwise, HRDY
stays low (ready):
Case 1: Back-to-back HPIA writes (can be either
first or second half-word)
Case 2: HPIA write following a PREFETCH
command (can be either first or second
half-word)
Case 3: HPID write when FIFO is full or flushing
(can be either first or second half-word)
Case 4: HPIA write and Write FIFO not empty
For HPI Read, HRDY can go high (not ready) for
these HPI Read conditions:
Case 1: HPID read (with auto-increment) and
data not in Read FIFO (can only happen to first
half-word of HPID access)
Delay time, HSTROBE low to HRDY
valid
5
td(HSTBL-HRDYV)
22
ns
Case 2: First half-word access of HPID Read
without auto-increment
For HPI Read, HRDY stays low (ready) for these
HPI Read conditions:
Case 1: HPID read with auto-increment and data
is already in Read FIFO (applies to either
half-word of HPID access)
Case 2: HPID read without auto-increment and
data is already in Read FIFO (always applies to
second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either
half-word access)
5a
6
td(HASL-HRDYV)
ten(HSTBL-HDLZ)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDHZ)
Delay time, HAS low to HRDY valid
22
0
Enable time, HD driven from HSTROBE low
Delay time, HRDY low to HD valid
1.5
1.5
ns
ns
ns
ns
7
8
Output hold time, HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
14
22
For HPI Read. Applies to conditions where data
is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Delay time, HSTROBE low to HD
valid
Case 2: First half-word of HPID read with
auto-increment and data is already in Read
FIFO
15
td(HSTBL-HDV)
22
ns
Case 3: Second half-word of HPID read with or
without auto-increment
For HPI Write, HRDY can go high (not ready) for
these HPI Write conditions; otherwise, HRDY
stays low (ready):
Case 1: HPID write when Write FIFO is full (can
happen to either half-word)
Case 2: HPIA write (can happen to either
half-word)
Delay time, HSTROBE high to HRDY
valid
18
td(HSTBH-HRDYV)
22
ns
Case 3: HPID write without auto-increment (only
happens to second half-word)
(1) M=SYSCLK2 period in ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
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UHPI_HCS
(D)
UHPI_HAS
2
2
1
1
1
1
1
1
UHPI_HCNTL[1:0]
UHPI_HR/W
2
2
2
2
UHPI_HHWIL
4
3
3
(A)(C)
UHPI_HSTROBE
15
15
14
14
8
6
8
6
UHPI_HD[15:0]
(output)
13
7
1st Half-Word
2nd Half-Word
5
(B)
UHPI_HRDY
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1
XOR HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D
The diagram above assumes UHPI_HAS has been pulled high.
Figure 6-57. UHPI Read Timing (HAS Not Used, Tied High)
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(A)
UHPI_HAS
17
10
17
10
9
9
9
9
UHPI_HCNTL[1:0]
10
10
10
10
9
UHPI_HR/W
9
UHPI_HHWIL
4
3
(B)
UHPI_HSTROBE
16
16
UHPI_HCS
14
14
6
8
15
8
UHPI_HD[15:0]
(output)
5a
1st half-word
2nd half-word
7
UHPI_HRDY
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-58. UHPI Read Timing (HAS Used)
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UHPI_HCS
(D)
UHPI_HAS
1
1
1
1
1
1
2
2
2
2
2
UHPI_HCNTL[1:0]
UHPI_HR/W
2
3
UHPI_HHWIL
3
4
(A)(C)
UHPI_HSTROBE
11
11
12
12
UHPI_HD[15:0]
(input)
1st Half-Word
18
2nd Half-Word
18
5
13
13
5
(B)
UHPI_HRDY
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR
UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS
timing requirements are reflected by parameters for UHPI_HSTROBE.
D
The diagram above assumes UHPI_HAS has been pulled high.
Figure 6-59. UHPI Write Timing (HAS Not Used, Tied High)
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17
10
17
†
UHPI_HAS
10
10
10
9
9
9
9
UHPI_HCNTL[1:0]
10
10
9
UHPI_HR/W
9
UHPI_HHWIL
3
4
‡
UHPI_HSTROBE
16
11
16
UHPI_HCS
11
12
12
UHPI_HD[15:0]
(input)
1st half-word
2nd half-word
5a
13
UHPI_HRDY
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-60. UHPI Write Timing (HAS Used)
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6.22 Universal Parallel Port (uPP)
The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated
data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital
converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may
also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve
high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which
its individual channels operate in opposite directions.
The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU
overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data
to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically
service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA
resources service a single I/O channel. In this mode, only one I/O channel may be used.
The features of the uPP include:
•
•
Programmable data width per channel (from 8 to 16 bits inclusive)
Programmable data justification
–
–
–
Right-justify with zero extend
Right-justify with sign extend
Left-justify with zero fill
•
•
•
•
•
Supports multiplexing of interleaved data during SDR transmit
Optional frame START signal with programmable polarity
Optional data ENABLE signal with programmable polarity
Optional synchronization WAIT signal with programmable polarity
Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface
–
–
Supports multiplexing of interleaved data during SDR transmit
Supports demultiplexing and multiplexing of interleaved data during DDR transfers
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6.22.1 uPP Register Descriptions
Table 6-93 shows the uPP registers.
Table 6-93. Universal Parallel Port (uPP) Registers
BYTE ADDRESS
0x01E1 6000
0x01E1 6004
0x01E1 6008
0x01E1 6010
0x01E1 6014
0x01E1 6018
0x01E1 601C
0x01E1 6020
0x01E1 6024
0x01E1 6028
0x01E1 602C
0x01E1 6030
0x01E1 6040
0x01E1 6044
0x01E1 6048
0x01E1 6050
0x01E1 6054
0x01E1 6058
0x01E1 6060
0x01E1 6064
0x01E1 6068
0x01E1 6070
0x01E1 6074
0x01E1 6078
ACRONYM
UPPID
REGISTER DESCRIPTION
uPP Peripheral Identification Register
UPPCR
UPDLB
UPCTL
UPICR
UPIVR
UPTCR
UPISR
UPIER
UPIES
UPIEC
UPEOI
UPID0
UPID1
UPID2
UPIS0
UPIS1
UPIS2
UPQD0
UPQD1
UPQD2
UPQS0
UPQS1
UPQS2
uPP Peripheral Control Register
uPP Digital Loopback Register
uPP Channel Control Register
uPP Interface Configuration Register
uPP Interface Idle Value Register
uPP Threshold Configuration Register
uPP Interrupt Raw Status Register
uPP Interrupt Enabled Status Register
uPP Interrupt Enable Set Register
uPP Interrupt Enable Clear Register
uPP End-of-Interrupt Register
uPP DMA Channel I Descriptor 0 Register
uPP DMA Channel I Descriptor 1 Register
uPP DMA Channel I Descriptor 2 Register
uPP DMA Channel I Status 0 Register
uPP DMA Channel I Status 1 Register
uPP DMA Channel I Status 2 Register
uPP DMA Channel Q Descriptor 0 Register
uPP DMA Channel Q Descriptor 1 Register
uPP DMA Channel Q Descriptor 2 Register
uPP DMA Channel Q Status 0 Register
uPP DMA Channel Q Status 1 Register
uPP DMA Channel Q Status 2 Register
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6.22.2 uPP Electrical Data/Timing
Table 6-94. Timing Requirements for uPP (see Figure 6-61, Figure 6-62, Figure 6-63, Figure 6-64)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
1
PARAMETER
UNIT
ns
MIN
13.33
26.66
5
MAX MIN MAX MIN
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
20
40
8
26.66
53.33
10
tc(INCLK)
Cycle time, CHn_CLK
ns
ns
2
tw(INCLKH)
Pulse width, CHn_CLK high
Pulse width, CHn_CLK low
10
16
8
20
5
10
3
tw(INCLKL)
10
16
5.5
0.8
5.5
0.8
20
4
5
6
7
tsu(STV-INCLKH)
th(INCLKH-STV)
tsu(ENV-INCLKH)
th(INCLKH-ENV)
Setup time, CHn_START valid before CHn_CLK high
Hold time, CHn_START valid after CHn_CLK high
Setup time, CHn_ENABLE valid before CHn_CLK high
Hold time, CHn_ENABLE valid after CHn_CLK high
4
6.5
0.8
6.5
0.8
ns
ns
ns
ns
0.8
4
0.8
Setup time, CHn_DATA/XDATA valid before CHn_CLK
high
8
tsu(DV-INCLKH)
4
5.5
6.5
ns
9
th(INCLKH-DV)
tsu(DV-INCLKL)
th(INCLKL-DV)
tsu(WTV-INCLKL)
th(INCLKL-WTV)
tc(2xTXCLK)
Hold time, CHn_DATA/XDATA valid after CHn_CLK high
Setup time, CHn_DATA/XDATA valid before CHn_CLK low
Hold time, CHn_DATA/XDATA valid after CHn_CLK low
Setup time, CHn_WAIT valid before CHn_CLK high
Hold time, CHn_WAIT valid after CHn_CLK high
Cycle time, 2xTXCLK input clock(1)
0.8
4
0.8
5.5
0.8
12
0.8
6.5
ns
ns
ns
ns
ns
ns
10
11
19
20
21
0.8
10
0.8
14
0.8
6.66
0.8
10
0.8
13.33
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.
Table 6-95. Switching Characteristics Over Recommended Operating Conditions for uPP
1.3V, 1.2V
1.1V
1.0V
NO.
12
PARAMETER
UNIT
ns
MIN
MAX MIN MAX MIN
MAX
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
13.33
20
40
8
26.66
53.33
10
20
10
20
2
tc(OUTCLK)
Cycle time, CHn_CLK
26.66
5
10
5
ns
ns
13
tw(OUTCLKH)
Pulse width, CHn_CLK high
Pulse width, CHn_CLK low
16
8
14
tw(OUTCLKL)
10
2
16
2
15
16
17
18
td(OUTCLKH-STV) Delay time, CHn_START valid after CHn_CLK high
td(OUTCLKH-ENV) Delay time, CHn_ENABLE valid after CHn_CLK high
11
11
11
11
15
15
15
15
21
21
21
21
ns
ns
ns
ns
2
2
2
td(OUTCLKH-DV)
td(OUTCLKL-DV)
Delay time, CHn_DATA/XDATA valid after CHn_CLK high
Delay time, CHn_DATA/XDATA valid after CHn_CLK low
2
2
2
2
2
2
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1
2
3
CHx_CLK
4
5
CHx_START
6
7
CHx_ENABLE
CHx_WAIT
8
9
CHx_DATA[n:0]
CHx_XDATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 6-61. uPP Single Data Rate (SDR) Receive Timing
1
2
3
CHx_CLK
4
5
CHx_START
6
7
CHx_ENABLE
CHx_WAIT
10
8
11
9
CHx_DATA[n:0]
CHx_XDATA[n:0]
I1 Q1 I2 Q2 I3 Q3
I4 Q4
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
Figure 6-62. uPP Double Data Rate (DDR) Receive Timing
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12
13
14
CHx_CLK
15
16
CHx_START
CHx_ENABLE
CHx_WAIT
19
20
17
CHx_DATA[n:0]
CHx_XDATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 6-63. uPP Single Data Rate (SDR) Transmit Timing
12
13
14
CHx_CLK
CHx_START
CHx_ENABLE
CHx_WAIT
15
16
19
20
17
18
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
CHx_DATA[n:0]
CHx_XDATA[n:0]
I1 Q1 I2 Q2 I3 Q3
I4 Q4
Figure 6-64. uPP Double Data Rate (DDR) Transmit Timing
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6.23 Video Port Interface (VPIF)
The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:
•
Up to 2 Video Capture Channels (Channel 0 and Channel 1)
–
–
–
Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
Single Raw Video (8-/10-/12-bit)
•
Up to 2 Video Display Channels (Channel 2 and Channel 3)
–
–
Two 8-bit SD Video Display with embedded timing codes (BT.656)
Single 16-bit HD Video Display with embedded timing codes (BT.1120)
The VPIF capture channel input data format is selectable based on the settings of the specific Channel
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register.
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6.23.1 VPIF Register Descriptions
Table 6-96 shows the VPIF registers.
Table 6-96. Video Port Interface (VPIF) Registers
BYTE ADDRESS
0x01E1 7000
ACRONYM
PID
REGISTER DESCRIPTION
Peripheral identification register
0x01E1 7004
CH0_CTRL
CH1_CTRL
CH2_CTRL
CH3_CTRL
-
Channel 0 control register
Channel 1 control register
Channel 2 control register
Channel 3 control register
Reserved
0x01E1 7008
0x01E1 700C
0x01E1 7010
0x01E1 7014 - 0x01E1 701F
0x01E1 7020
INTEN
Interrupt enable
0x01E1 7024
INTENSET
INTENCLR
INTSTAT
INTSTATCLR
EMU_CTRL
DMA_SIZE
-
Interrupt enable set
Interrupt enable clear
Interrupt status
0x01E1 7028
0x01E1 702C
0x01E1 7030
Interrupt status clear
Emulation control
0x01E1 7034
0x01E1 7038
DMA size control
0x01E1 703C - 0x01E1 703F
Reserved
CAPTURE CHANNEL 0 REGISTERS
CH0_TY_STRTADR
0x01E1 7040
0x01E1 7044
0x01E1 7048
0x01E1 704C
0x01E1 7050
0x01E1 7054
0x01E1 7058
0x01E1 705C
0x01E1 7060
0x01E1 7064
0x01E1 7068
0x01E1 706C
0x01E1 7070
0x01E1 7074
0x01E1 7078
0x01E1 707C
Channel 0 Top Field luma buffer start address
Channel 0 Bottom Field luma buffer start address
Channel 0 Top Field chroma buffer start address
Channel 0 Bottom Field chroma buffer start address
Channel 0 Top Field horizontal ancillary data buffer start address
Channel 0 Bottom Field horizontal ancillary data buffer start address
Channel 0 Top Field vertical ancillary data buffer start address
Channel 0 Bottom Field vertical ancillary data buffer start address
Channel 0 sub-picture configuration
CH0_BY_STRTADR
CH0_TC_STRTADR
CH0_BC_STRTADR
CH0_THA_STRTADR
CH0_BHA_STRTADR
CH0_TVA_STRTADR
CH0_BVA_STRTADR
CH0_SUBPIC_CFG
CH0_IMG_ADD_OFST
CH0_HA_ADD_OFST
CH0_HSIZE_CFG
Channel 0 image data address offset
Channel 0 horizontal ancillary data address offset
Channel 0 horizontal data size configuration
CH0_VSIZE_CFG0
CH0_VSIZE_CFG1
CH0_VSIZE_CFG2
CH0_VSIZE
Channel 0 vertical data size configuration (0)
Channel 0 vertical data size configuration (1)
Channel 0 vertical data size configuration (2)
Channel 0 vertical image size
CAPTURE CHANNEL 1 REGISTERS
0x01E1 7080
0x01E1 7084
0x01E1 7088
0x01E1 708C
0x01E1 7090
0x01E1 7094
0x01E1 7098
0x01E1 709C
0x01E1 70A0
0x01E1 70A4
0x01E1 70A8
0x01E1 70AC
CH1_TY_STRTADR
CH1_BY_STRTADR
CH1_TC_STRTADR
CH1_BC_STRTADR
CH1_THA_STRTADR
CH1_BHA_STRTADR
CH1_TVA_STRTADR
CH1_BVA_STRTADR
CH1_SUBPIC_CFG
CH1_IMG_ADD_OFST
CH1_HA_ADD_OFST
CH1_HSIZE_CFG
Channel 1 Top Field luma buffer start address
Channel 1 Bottom Field luma buffer start address
Channel 1 Top Field chroma buffer start address
Channel 1 Bottom Field chroma buffer start address
Channel 1 Top Field horizontal ancillary data buffer start address
Channel 1 Bottom Field horizontal ancillary data buffer start address
Channel 1 Top Field vertical ancillary data buffer start address
Channel 1 Bottom Field vertical ancillary data buffer start address
Channel 1 sub-picture configuration
Channel 1 image data address offset
Channel 1 horizontal ancillary data address offset
Channel 1 horizontal data size configuration
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Table 6-96. Video Port Interface (VPIF) Registers (continued)
BYTE ADDRESS
0x01E1 70B0
0x01E1 70B4
0x01E1 70B8
0x01E1 70BC
ACRONYM
REGISTER DESCRIPTION
Channel 1 vertical data size configuration (0)
CH1_VSIZE_CFG0
CH1_VSIZE_CFG1
CH1_VSIZE_CFG2
CH1_VSIZE
Channel 1 vertical data size configuration (1)
Channel 1 vertical data size configuration (2)
Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
0x01E1 70C0
0x01E1 70C4
0x01E1 70C8
0x01E1 70CC
0x01E1 70D0
0x01E1 70D4
0x01E1 70D8
0x01E1 70DC
0x01E1 70E0
0x01E1 70E4
0x01E1 70E8
0x01E1 70EC
0x01E1 70F0
0x01E1 70F4
0x01E1 70F8
0x01E1 70FC
0x01E1 7100
0x01E1 7104
0x01E1 7108
0x01E1 710C
0x01E1 7110
0x01E1 7114
0x01E1 7118
0x01E1 711C
0x01E1 7120 - 0x01E1 713F
CH2_TY_STRTADR
CH2_BY_STRTADR
CH2_TC_STRTADR
CH2_BC_STRTADR
CH2_THA_STRTADR
CH2_BHA_STRTADR
CH2_TVA_STRTADR
CH2_BVA_STRTADR
CH2_SUBPIC_CFG
CH2_IMG_ADD_OFST
CH2_HA_ADD_OFST
CH2_HSIZE_CFG
CH2_VSIZE_CFG0
CH2_VSIZE_CFG1
CH2_VSIZE_CFG2
CH2_VSIZE
Channel 2 Top Field luma buffer start address
Channel 2 Bottom Field luma buffer start address
Channel 2 Top Field chroma buffer start address
Channel 2 Bottom Field chroma buffer start address
Channel 2 Top Field horizontal ancillary data buffer start address
Channel 2 Bottom Field horizontal ancillary data buffer start address
Channel 2 Top Field vertical ancillary data buffer start address
Channel 2 Bottom Field vertical ancillary data buffer start address
Channel 2 sub-picture configuration
Channel 2 image data address offset
Channel 2 horizontal ancillary data address offset
Channel 2 horizontal data size configuration
Channel 2 vertical data size configuration (0)
Channel 2 vertical data size configuration (1)
Channel 2 vertical data size configuration (2)
Channel 2 vertical image size
CH2_THA_STRTPOS
CH2_THA_SIZE
Channel 2 Top Field horizontal ancillary data insertion start position
Channel 2 Top Field horizontal ancillary data size
Channel 2 Bottom Field horizontal ancillary data insertion start position
Channel 2 Bottom Field horizontal ancillary data size
Channel 2 Top Field vertical ancillary data insertion start position
Channel 2 Top Field vertical ancillary data size
Channel 2 Bottom Field vertical ancillary data insertion start position
Channel 2 Bottom Field vertical ancillary data size
Reserved
CH2_BHA_STRTPOS
CH2_BHA_SIZE
CH2_TVA_STRTPOS
CH2_TVA_SIZE
CH2_BVA_STRTPOS
CH2_BVA_SIZE
-
DISPLAY CHANNEL 3 REGISTERS
0x01E1 7140
0x01E1 7144
0x01E1 7148
0x01E1 714C
0x01E1 7150
0x01E1 7154
0x01E1 7158
0x01E1 715C
0x01E1 7160
0x01E1 7164
0x01E1 7168
0x01E1 716C
0x01E1 7170
0x01E1 7174
0x01E1 7178
0x01E1 717C
CH3_TY_STRTADR
CH3_BY_STRTADR
CH3_TC_STRTADR
CH3_BC_STRTADR
CH3_THA_STRTADR
CH3_BHA_STRTADR
CH3_TVA_STRTADR
CH3_BVA_STRTADR
CH3_SUBPIC_CFG
CH3_IMG_ADD_OFST
CH3_HA_ADD_OFST
CH3_HSIZE_CFG
Channel 3 Field 0 luma buffer start address
Channel 3 Field 1 luma buffer start address
Channel 3 Field 0 chroma buffer start address
Channel 3 Field 1 chroma buffer start address
Channel 3 Field 0 horizontal ancillary data buffer start address
Channel 3 Field 1 horizontal ancillary data buffer start address
Channel 3 Field 0 vertical ancillary data buffer start address
Channel 3 Field 1 vertical ancillary data buffer start address
Channel 3 sub-picture configuration
Channel 3 image data address offset
Channel 3 horizontal ancillary data address offset
Channel 3 horizontal data size configuration
Channel 3 vertical data size configuration (0)
Channel 3 vertical data size configuration (1)
Channel 3 vertical data size configuration (2)
Channel 3 vertical image size
CH3_VSIZE_CFG0
CH3_VSIZE_CFG1
CH3_VSIZE_CFG2
CH3_VSIZE
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Table 6-96. Video Port Interface (VPIF) Registers (continued)
BYTE ADDRESS
ACRONYM
CH3_THA_STRTPOS
CH3_THA_SIZE
CH3_BHA_STRTPOS
CH3_BHA_SIZE
CH3_TVA_STRTPOS
CH3_TVA_SIZE
CH3_BVA_STRTPOS
CH3_BVA_SIZE
-
REGISTER DESCRIPTION
Channel 3 Top Field horizontal ancillary data insertion start position
Channel 3 Top Field horizontal ancillary data size
Channel 3 Bottom Field horizontal ancillary data insertion start position
Channel 3 Bottom Field horizontal ancillary data size
Channel 3 Top Field vertical ancillary data insertion start position
Channel 3 Top Field vertical ancillary data size
0x01E1 7180
0x01E1 7184
0x01E1 7188
0x01E1 718C
0x01E1 7190
0x01E1 7194
0x01E1 7198
Channel 3 Bottom Field vertical ancillary data insertion start position
Channel 3 Bottom Field vertical ancillary data size
Reserved
0x01E1 719C
0x01E1 71A0 - 0x01E1 71FF
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6.23.2 VPIF Electrical Data/Timing
Table 6-97. Timing Requirements for VPIF VP_CLKINx Inputs(1) (see Figure 6-65)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
1
PARAMETER
UNIT
MIN
13.3
13.3
0.4C
0.4C
MAX MIN MAX MIN
Cycle time, VP_CLKIN0
20
20
37
37
ns
ns
ns
ns
ns
tc(VKI)
Cycle time, VP_CLKIN1/2/3
Pulse duration, VP_CLKINx high
Pulse duration, VP_CLKINx low
Transition time, VP_CLKINx
2
3
4
tw(VKIH)
tw(VKIL)
tt(VKI)
0.4C
0.4C
0.4C
0.4C
5
5
5
(1) C = VP_CLKINx period in ns.
1
4
2
3
VP_CLKINx
4
Figure 6-65. Video Port Capture VP_CLKINx Timing
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Table 6-98. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see Figure 6-66)
1.3V, 1.2V
1.1V
1.0V
MAX
NO.
PARAMETER
UNIT
MIN
4
MAX MIN MAX MIN
1
2
tsu(VDINV-VKIH)
th(VKIH-VDINV)
Setup time, VP_DINx valid before VP_CLKIN0/1 high
Hold time, VP_DINx valid after VP_CLKIN0/1 high
6
0
7
0
ns
ns
0
VP_CLKIN0/1
1
2
VP_DINx/FIELD/
HSYNC/VSYNC
Figure 6-66. VPIF Channels 0/1 Video Capture Data and Control Input Timing
Table 6-99. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown
With Respect to VP_CLKOUT2/3(1)
(see Figure 6-67)
1.3V, 1.2V
1.1V
1.0V
NO.
PARAMETER
UNIT
MIN
13.3
0.4C
0.4C
MAX MIN MAX MIN
MAX
1
2
3
4
tc(VKO)
Cycle time, VP_CLKOUT2/3
20
37
ns
ns
ns
ns
tw(VKOH)
tw(VKOL)
tt(VKO)
Pulse duration, VP_CLKOUT2/3 high
Pulse duration, VP_CLKOUT2/3 low
Transition time, VP_CLKOUT2/3
0.4C
0.4C
0.4C
0.4C
5
5
5
Delay time,
VP_CLKOUT2/3 high to VP_DOUTx valid
11
12
td(VKOH-VPDOUTV)
8.5
12
17
ns
ns
Delay time,
VP_CLKOUT2/3 high to VP_DOUTx invalid
td(VCLKOH-VPDOUTIV)
1.5
1.5
1.5
(1) C = VP_CLKO2/3 period in ns.
2
1
VP_CLKOUTx
(Positive Edge
Clocking)
3
4
4
VP_CLKOUTx
(Negative Edge
Clocking)
11
12
VP_DOUTx
Figure 6-67. VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3
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6.24 Enhanced Capture (eCAP) Peripheral
The device contains up to three enhanced capture (eCAP) modules. Figure 6-68 shows a functional block
diagram of a module.
Uses for ECAP include:
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
•
•
•
•
•
•
•
•
•
32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the ASYNC3 clock domain rate.
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CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to Interrupt
Controller
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 6-68. eCAP Functional Block Diagram
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Table 6-100 is the list of the ECAP registers.
Table 6-100. ECAPx Configuration Registers
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
ACRONYM
DESCRIPTION
Time-Stamp Counter
BYTE ADDRESS
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 800C
0x01F0 8010
0x01F0 8014
0x01F0 8028
0x01F0 802A
0x01F0 802C
0x01F0 802E
0x01F0 8030
0x01F0 8032
0x01F0 805C
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 600C
0x01F0 6010
0x01F0 6014
0x01F0 6028
0x01F0 602A
0x01F0 602C
0x01F0 602E
0x01F0 6030
0x01F0 6032
0x01F0 605C
0x01F0 7000
0x01F0 7004
0x01F0 7008
0x01F0 700C
0x01F0 7010
0x01F0 7014
0x01F0 7028
0x01F0 702A
0x01F0 702C
0x01F0 702E
0x01F0 7030
0x01F0 7032
0x01F0 705C
TSCTR
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
REVID
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Revision ID
Table 6-101 shows the eCAP timing requirement and Table 6-102 shows the eCAP switching
characteristics.
Table 6-101. Timing Requirements for Enhanced Capture (eCAP)
PARAMETER
TEST CONDITIONS
1.3V, 1.2V, 1.1V, 1.0V
MIN
MAX
UNIT
cycles
cycles
tw(CAP)
Capture input pulse width
Asynchronous
Synchronous
2tc(SCO)
2tc(SCO)
Table 6-102. Switching Characteristics Over Recommended Operating Conditions for eCAP
PARAMETER
1.3V, 1.2V
MIN MAX
20
1.1V
1.0V
UNIT
ns
MIN
20
MAX
MIN
20
MAX
tw(APWM)
Pulse duration, APWMx output high/low
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6.25 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The device contains two enhanced PWM Modules (eHRPWM). Figure 6-69 shows a block diagram of
multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM.
EPWMSYNCI
EPWM0SYNCI
EPWM0INT
EPWM0A
EPWM0B
ePWM0 module
TZ
Interrupt
EPWM0SYNCO
Controllers
GPIO
MUX
EPWM1SYNCI
EPWM1INT
EPWM1A
EPWM1B
ePWM1 module
EPWM1SYNCO
TZ
To eCAP0
module
EPWMSYNCO
(sync in)
Peripheral Bus
Figure 6-69. Multiple PWM Modules in a C6748 System
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMSYNCO
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMSYNCI
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
Event
trigger
and
interrupt
(ET)
TBPHS active (24)
control
EPWMxINT
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxB
EPWMxTZINT
TZ
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 6-70. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
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Table 6-103. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0
eHRPWM1
BYTE ADDRESS
BYTE ADDRESS
ACRONYM
SHADOW
REGISTER DESCRIPTION
Time-Base Submodule Registers
0x01F0 0000
0x01F0 0002
0x01F0 0004
0x01F0 0006
0x01F0 0008
0x01F0 000A
0x01F0 2000
0x01F0 2002
0x01F0 2004
0x01F0 2006
0x01F0 2008
0x01F0 200A
TBCTL
TBSTS
TBPHSHR
No
No
No
No
No
Yes
Time-Base Control Register
Time-Base Status Register
Extension for HRPWM Phase Register
Time-Base Phase Register
Time-Base Counter Register
Time-Base Period Register
(1)
TBPHS
TBCNT
TBPRD
Counter-Compare Submodule Registers
0x01F0 000E
0x01F0 0010
0x01F0 0012
0x01F0 0014
0x01F0 200E
0x01F0 2010
0x01F0 2012
0x01F0 2014
CMPCTL
CMPAHR
CMPA
No
No
Counter-Compare Control Register
(1)
Extension for HRPWM Counter-Compare A Register
Counter-Compare A Register
Yes
Yes
CMPB
Counter-Compare B Register
Action-Qualifier Submodule Registers
0x01F0 0016
0x01F0 0018
0x01F0 001A
0x01F0 001C
0x01F0 2016
0x01F0 2018
0x01F0 201A
0x01F0 201C
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
No
No
Action-Qualifier Control Register for Output A (eHRPWMxA)
Action-Qualifier Control Register for Output B (eHRPWMxB)
Action-Qualifier Software Force Register
No
Yes
Action-Qualifier Continuous S/W Force Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E
0x01F0 0020
0x01F0 0022
0x01F0 201E
0x01F0 2020
0x01F0 2022
DBCTL
DBRED
DBFED
No
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
PWM-Chopper Submodule Registers
PCCTL No PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 003C
0x01F0 203C
0x01F0 0024
0x01F0 0028
0x01F0 002A
0x01F0 002C
0x01F0 002E
0x01F0 0030
0x01F0 2024
0x01F0 2028
0x01F0 202A
0x01F0 202C
0x01F0 202E
0x01F0 2030
TZSEL
No
No
No
No
No
No
Trip-Zone Select Register
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032
0x01F0 0034
0x01F0 0036
0x01F0 0038
0x01F0 003A
0x01F0 2032
0x01F0 2034
0x01F0 2036
0x01F0 2038
0x01F0 203A
ETSEL
No
No
No
No
No
Event-Trigger Selection Register
ETPS
ETFLG
ETCLR
ETFRC
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG No HRPWM Configuration Register
(1)
0x01F0 1020
0x01F0 3020
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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6.25.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-104 shows the PWM timing requirements and
Table 6-105, switching characteristics.
Table 6-104. Timing Requirements for eHRPWM
PARAMETER
TEST CONDITIONS
1.3V, 1.2V, 1.1V, 1.0V
UNIT
MIN
MAX
tw(SYNCIN)
Sync input pulse width
Asynchronous
Synchronous
2tc(SCO)
2tc(SCO)
cycles
cycles
Table 6-105. Switching Characteristics Over Recommended Operating Conditions for eHRPWM
PARAMETER
TEST
CONDITIONS
1.3V, 1.2V
1.1V
MIN
1.0V
MIN
UNIT
MIN
MAX
MAX
MAX
tw(PWM)
Pulse duration, PWMx output
high/low
ns
20
20
26.6
tw(SYNCOUT)
td(PWM)TZA
Sync output pulse width
8tc(SCO)
8tc(SCO)
8tc(SCO)
cycles
ns
Delay time, trip input active to
PWM forced high
Delay time, trip input active to
PWM forced low
no pin load; no
additional
programmable
delay
25
20
25
20
25
20
td(TZ-PWM)HZ
Delay time, trip input active to
PWM Hi-Z
no additional
programmable
delay
ns
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6.25.2 Trip-Zone Input Timing
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(A)
PWM
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-71. PWM Hi-Z Characteristics
Table 6-106. Trip-Zone input Timing Requirements
PARAMETER
TEST CONDITIONS
1.3V, 1.2V, 1.1V, 1.0V
MIN
MAX
UNIT
cycles
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
1tc(SCO)
2tc(SCO)
Table 6-107 shows the high-resolution PWM switching characteristics.
Table 6-107. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
1.3V, 1.2V
TYP
1.1V
TYP
200
1.0V
TYP MAX UNIT
200 ps
MIN
MAX
MIN
MAX
MIN
Micro Edge Positioning (MEP) step size(1)
200
(1) MEP step size will increase with low voltage and high temperature and decrease with high voltage and cold temperature. Applications
that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries
for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period
dynamically while the HRPWM is in operation.
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6.26 Timers
The timers support the following features:
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)
Table 6-108 lists the timer registers.
Table 6-108. Timer Registers
TIMER64P 0
BYTE
TIMER64P 1
BYTE
TIMER64P 2 BYTE
ADDRESS
TIMER64P 3
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
0x01F0 C000
0x01F0 C004
0x01F0 C008
0x01F0 C00C
0x01F0 C010
0x01F0 C014
0x01F0 C018
0x01F0 C01C
0x01F0 C020
0x01F0 C024
0x01F0 C028
0x01F0 C034
0x01F0 C038
0x01F0 C03C
0x01F0 C040
0x01F0 C044
0x01F0 C060
0x01F0 C064
0x01F0 C068
0x01F0 C06C
0x01F0 C070
0x01F0 C074
0x01F0 C078
0x01F0 C07C
0x01F0 D000
0x01F0 D004
0x01F0 D008
0x01F0 D00C
0x01F0 D010
0x01F0 D014
0x01F0 D018
0x01F0 D01C
0x01F0 D020
0x01F0 D024
0x01F0 D028
0x01F0 D034
0x01F0 D038
0x01F0 D03C
0x01F0 D040
0x01F0 D044
0x01F0 D060
0x01F0 D064
0x01F0 D068
0x01F0 D06C
0x01F0 D070
0x01F0 D074
0x01F0 D078
0x01F0 D07C
REV
Revision Register
Emulation Management Register
EMUMGT
GPINTGPEN GPIO Interrupt and GPIO Enable Register
GPDATGPDIR GPIO Data and GPIO Direction Register
TIM12
TIM34
PRD12
PRD34
TCR
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
TGCR
WDTCR
REL12
REL34
CAP12
CAP34
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
INTCTLSTAT Timer Interrupt Control and Status Register
CMP0
CMP1
CMP2
CMP3
CMP4
CMP5
CMP6
CMP7
Compare Register 0
Compare Register 1
Compare Register 2
Compare Register 3
Compare Register 4
Compare Register 5
Compare Register 6
Compare Register 7
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6.26.1 Timer Electrical Data/Timing
Table 6-109. Timing Requirements for Timer Input(1) (2) (see Figure 6-72)
1.3V, 1.2V, 1.1V,
1.0V
NO.
PARAMETER
UNIT
MIN
4P
MAX
1
2
3
4
tc(TM64Px_IN12) Cycle time, TM64Px_IN12
tw(TINPH) Pulse duration, TM64Px_IN12 high
tw(TINPL) Pulse duration, TM64Px_IN12 low
tt(TM64Px_IN12) Transition time, TM64Px_IN12
ns
ns
ns
ns
0.45C
0.45C
0.55C
0.55C
0.05C
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
(2) C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
1
2
3
4
4
TM64P0_IN12
Figure 6-72. Timer Timing
(1)
Table 6-110. Switching Characteristics Over Recommended Operating Conditions for Timer Output
1.3V, 1.2V, 1.1V,
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
5
6
tw(TOUTH)
tw(TOUTL)
Pulse duration, TM64P0_OUT12 high
Pulse duration, TM64P0_OUT12 low
4P
4P
ns
ns
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 6-73. Timer Timing
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6.27 Real Time Clock (RTC)
The RTC provides a time reference to an application running on the device. The current date and time is
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do
not interfere with the accuracy of the time and date.
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time
registers are updated, or at programmable periodic intervals.
The real-time clock (RTC) provides the following features:
•
•
•
•
•
•
•
•
•
100-year calendar (xx00 to xx99)
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
12-hour clock mode (with AM and PM) or 24-hour clock mode
Alarm interrupt
Periodic interrupt
Single interrupt to the CPU
Supports external 32.768-kHz crystal or external clock source of the same frequency
Separate isolated power supply
Figure 6-74 shows a block diagram of the RTC.
Oscillator
Compensation
Week
Days
Counter
32 kHz
RTC_XI
XTAL
Hours
Days
Years
Seconds
Minutes
Months
RTC_XO
Oscillator
Alarm
Interrupts
Alarm
Periodic
Interrupts
Timer
Figure 6-74. Real-Time Clock Block Diagram
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6.27.1 Clock Source
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current
time and calendar information. Even if the RTC is not used, it must remain powered when the rest of the
device is powered.
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the
output from the oscillator back to the crystal.
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is
connected to RTC_XI, and RTC_XO is left unconnected.
If the RTC is not used, the RTC_XI pin should be held either low or high, RTC_XO should be left
unconnected, RTC_CVDD should be connected to the device CVDD and RTC_VSS should remain
grounded.
Switch for Device
Core Power
+1.2V
CVDD
Real Time Clock
C2
RTC_CVDD
RTC_XI
XTAL
32.768
kHz
Real
Time
Clock
(RTC)
Module
RTC_XO
32K
OSC
C1
RTC_VSS
Isolated RTC
Power Domain
Figure 6-75. Clock Source
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6.27.2 Registers
Table 6-111 lists the memory-mapped registers for the RTC. See the device-specific data manual for the
memory address of these registers.
Table 6-111. Real-Time Clock (RTC) Registers
BYTE ADDRESS
0x01C2 3000
0x01C2 3004
0x01C2 3008
0x01C2 300C
0x01C2 3010
0x01C2 3014
0x01C2 3018
0x01C2 3020
0x01C2 3024
0x01C2 3028
0x01C2 302C
0x01C2 3030
0x01C2 3034
0x01C2 3040
0x01C2 3044
0x01C2 3048
0x01C2 304C
0x01C2 3050
0x01C2 3054
0x01C2 3060
0x01C2 3064
0x01C2 3068
0x01C2 306C
0x01C2 3070
ACRONYM
SECOND
MINUTE
REGISTER DESCRIPTION
Seconds Register
Minutes Register
HOUR
Hours Register
DAY
Day of the Month Register
Month Register
MONTH
YEAR
Year Register
DOTW
Day of the Week Register
Alarm Seconds Register
Alarm Minutes Register
Alarm Hours Register
Alarm Days Register
Alarm Months Register
Alarm Years Register
Control Register
ALARMSECOND
ALARMMINUTE
ALARMHOUR
ALARMDAY
ALARMMONTH
ALARMYEAR
CTRL
STATUS
Status Register
INTERRUPT
COMPLSB
COMPMSB
OSC
Interrupt Enable Register
Compensation (LSB) Register
Compensation (MSB) Register
Oscillator Register
SCRATCH0
SCRATCH1
SCRATCH2
KICK0
Scratch 0 (General-Purpose) Register
Scratch 1 (General-Purpose) Register
Scratch 2 (General-Purpose) Register
Kick 0 (Write Protect) Register
KICK1
Kick 1 (Write Protect) Register
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6.28 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The device GPIO peripheral supports the following:
•
•
Up to 144 Pins configurable as GPIO
External Interrupt and DMA request Capability
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
GPIO Banks 0, 1, 2, 3, 4, 5, 6, 7 and 8 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,
44, 45, 46, 47, 48, 49 and 50 respectively
GPIO Banks 0, 1, 2, 3, 4, and 5 are assigned to EDMA events 6, 7, 22, 23, 28, 29, and 29
respectively on Channel Controller 0 and GPIO Banks 6, 7, and 8 are assigned to EDMA events
16, 17, and 18 respectively on Channel Controller 1.
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-112.
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6.28.1 GPIO Register Description(s)
Table 6-112. GPIO Registers
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
ACRONYM
REGISTER DESCRIPTION
REV
Peripheral Revision Register
RESERVED
BINTEN
Reserved
GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
0x01E2 6028
0x01E2 602C
0x01E2 6030
0x01E2 6034
DIR01
GPIO Banks 0 and 1 Direction Register
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
GPIO Banks 0 and 1 Output Data Register
GPIO Banks 0 and 1 Set Data Register
GPIO Banks 0 and 1 Clear Data Register
GPIO Banks 0 and 1 Input Data Register
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
SET_RIS_TRIG01
CLR_RIS_TRIG01
SET_FAL_TRIG01
CLR_FAL_TRIG01
INTSTAT01
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
DIR23
GPIO Banks 2 and 3 Direction Register
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
GPIO Banks 2 and 3 Output Data Register
GPIO Banks 2 and 3 Set Data Register
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
SET_RIS_TRIG23
CLR_RIS_TRIG23
SET_FAL_TRIG23
CLR_FAL_TRIG23
INTSTAT23
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
DIR45
GPIO Banks 4 and 5 Direction Register
OUT_DATA45
SET_DATA45
CLR_DATA45
IN_DATA45
GPIO Banks 4 and 5 Output Data Register
GPIO Banks 4 and 5 Set Data Register
GPIO Banks 4 and 5 Clear Data Register
GPIO Banks 4 and 5 Input Data Register
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
SET_RIS_TRIG45
CLR_RIS_TRIG45
SET_FAL_TRIG45
CLR_FAL_TRIG45
INTSTAT45
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Table 6-112. GPIO Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
GPIO Banks 6 and 7
0x01E2 6088
0x01E2 608C
0x01E2 6090
0x01E2 6094
0x01E2 6098
0x01E2 609C
0x01E2 60A0
0x01E2 60A4
0x01E2 60A8
0x01E2 60AC
DIR67
GPIO Banks 6 and 7 Direction Register
GPIO Banks 6 and 7 Output Data Register
GPIO Banks 6 and 7 Set Data Register
GPIO Banks 6 and 7 Clear Data Register
GPIO Banks 6 and 7 Input Data Register
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
GPIO Bank 8
OUT_DATA67
SET_DATA67
CLR_DATA67
IN_DATA67
SET_RIS_TRIG67
CLR_RIS_TRIG67
SET_FAL_TRIG67
CLR_FAL_TRIG67
INTSTAT67
0x01E2 60B0
0x01E2 60B4
0x01E2 60B8
0x01E2 60BC
0x01E2 60C0
0x01E2 60C4
0x01E2 60C8
0x01E2 60CC
0x01E2 60D0
0x01E2 60D4
DIR8
GPIO Bank 8 Direction Register
OUT_DATA8
SET_DATA8
GPIO Bank 8 Output Data Register
GPIO Bank 8 Set Data Register
CLR_DATA8
IN_DATA8
GPIO Bank 8 Clear Data Register
GPIO Bank 8 Input Data Register
SET_RIS_TRIG8
CLR_RIS_TRIG8
SET_FAL_TRIG8
CLR_FAL_TRIG8
INTSTAT8
GPIO Bank 8 Set Rising Edge Interrupt Register
GPIO Bank 8 Clear Rising Edge Interrupt Register
GPIO Bank 8 Set Falling Edge Interrupt Register
GPIO Bank 8 Clear Falling Edge Interrupt Register
GPIO Bank 8 Interrupt Status Register
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6.28.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-113. Timing Requirements for GPIO Inputs(1) (see Figure 6-76)
1.3V, 1.2V, 1.1V,
1.0V
NO.
UNIT
MIN
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPn[m] as input high
Pulse duration, GPn[m] as input low
2C(1) (2)
2C(1) (2)
ns
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 6-114. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-76)
1.3V, 1.2V, 1.1V,
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GPn[m] as output high
Pulse duration, GPn[m] as output low
2C(1) (2)
2C(1) (2)
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m]
as input
4
3
GPn[m]
as output
Figure 6-76. GPIO Port Timing
6.28.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-115. Timing Requirements for External Interrupts(1) (see Figure 6-77)
1.3V, 1.2V, 1.1V,
1.0V
NO.
PARAMETER
UNIT
MIN
MAX
1
2
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
2C(1) (2)
2C(1) (2)
ns
ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to
access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m]
as input
Figure 6-77. GPIO External Interrupt Timing
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6.29 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
•
•
Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
•
A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 6-116 and in Table 6-117. Note that these two memory maps are implemented
inside the PRUSS and are local to the components of the PRUSS.
Table 6-116. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
PRU0
PRU1
0x0000 0000 - 0x0000 0FFF
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 6-117. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
PRU0
Data RAM 0
Reserved
PRU1
Data RAM 1
Reserved
(1)
(1)
(1)
(1)
0x0000 0000 - 0x0000 01FF
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
0x0000 2200 - 0x0000 3FFF
0x0000 4000 - 0x0000 6FFF
0x0000 7000 - 0x0000 73FF
0x0000 7400 - 0x0000 77FF
0x0000 7800 - 0x0000 7BFF
0x0000 7C00 - 0xFFFF FFFF
Data RAM 1
Reserved
Data RAM 0
Reserved
INTC Registers
PRU0 Control Registers
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
Reserved
PRU1 Control Registers
Reserved
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 6-118. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
Table 6-118. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
BYTE ADDRESS
REGION
0x01C3 0000 - 0x01C3 01FF
Data RAM 0
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Table 6-118. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map (continued)
BYTE ADDRESS
REGION
Reserved
0x01C3 0200 - 0x01C3 1FFF
0x01C3 2000 - 0x01C3 21FF
0x01C3 2200 - 0x01C3 3FFF
0x01C3 4000 - 0x01C3 6FFF
0x01C3 7000 - 0x01C3 73FF
0x01C3 7400 - 0x01C3 77FF
0x01C3 7800 - 0x01C3 7BFF
0x01C3 7C00 - 0x01C3 7FFF
0x01C3 8000 - 0x01C3 8FFF
0x01C3 9000 - 0x01C3 BFFF
0x01C3 C000 - 0x01C3 CFFF
0x01C3 D000 - 0x01C3 FFFF
Data RAM 1
Reserved
INTC Registers
PRU0 Control Registers
PRU0 Debug Registers
PRU1 Control Registers
PRU1 Debug Registers
PRU0 Instruction RAM
Reserved
PRU1 Instruction RAM
Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses
6.29.1 PRUSS Register Descriptions
Table 6-119. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS
0x01C3 7000
PRU1 BYTE ADDRESS
0x01C3 7800
ACRONYM
CONTROL
STATUS
REGISTER DESCRIPTION
PRU Control Register
PRU Status Register
0x01C3 7004
0x01C3 7804
0x01C3 7008
0x01C3 7808
WAKEUP
CYCLCNT
STALLCNT
PRU Wakeup Enable Register
PRU Cycle Count
0x01C3 700C
0x01C3 780C
0x01C3 7010
0x01C3 7810
PRU Stall Count
PRU Constant Table Block Index
Register 0
0x01C3 7020
0x01C3 7028
0x01C3 7820
0x01C3 7828
CONTABBLKIDX0
CONTABPROPTR0
PRU Constant Table Programmable
Pointer Register 0
PRU Constant Table Programmable
Pointer Register 1
0x01C3 702C
0x01C3 782C
CONTABPROPTR1
PRU Internal General Purpose
Register 0 (for Debug)
0x01C37400 - 0x01C3747C
0x01C37480 - 0x01C374FC
0x01C3 7C00 - 0x01C3 7C7C
0x01C3 7C80 - 0x01C3 7CFC
INTGPR0 – INTGPR31
INTCTER0 – INTCTER31
PRU Internal General Purpose
Register 0 (for Debug)
Table 6-120. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS
0x01C3 4000
0x01C3 4004
0x01C3 4010
0x01C3 401C
0x01C3 4020
0x01C3 4024
0x01C3 4028
0x01C3 402C
0x01C3 4034
0x01C3 4038
0x01C3 4080
ACRONYM
REVID
REGISTER DESCRIPTION
Revision ID Register
CONTROL
Control Register
GLBLEN
Global Enable Register
GLBLNSTLVL
STATIDXSET
STATIDXCLR
ENIDXSET
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
Global Prioritized Index Register
ENIDXCLR
HSTINTENIDXSET
HSTINTENIDXCLR
GLBLPRIIDX
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Table 6-120. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
BYTE ADDRESS
0x01C3 4200
ACRONYM
STATSETINT0
REGISTER DESCRIPTION
System Interrupt Status Raw/Set Register 0
System Interrupt Status Raw/Set Register 1
System Interrupt Status Enabled/Clear Register 0
System Interrupt Status Enabled/Clear Register 1
System Interrupt Enable Set Register 0
System Interrupt Enable Set Register 1
System Interrupt Enable Clear Register 0
System Interrupt Enable Clear Register 1
Channel Map Registers 0-15
0x01C3 4204
STATSETINT1
0x01C3 4280
STATCLRINT0
0x01C3 4284
STATCLRINT1
0x01C3 4300
ENABLESET0
0x01C3 4304
ENABLESET1
0x01C3 4380
ENABLECLR0
0x01C3 4384
ENABLECLR1
0x01C3 4400 - 0x01C3 4440
0x01C3 4800 - 0x01C3 4808
CHANMAP0 - CHANMAP15
HOSTMAP0 - HOSTMAP2
Host Map Register 0-2
HOSTINTPRIIDX0 -
HOSTINTPRIIDX9
0x01C3 4900 - 0x01C3 4928
Host Interrupt Prioritized Index Registers 0-9
0x01C3 4D00
0x01C3 4D04
0x01C3 4D80
0x01C3 4D84
POLARITY0
POLARITY1
TYPE0
System Interrupt Polarity Register 0
System Interrupt Polarity Register 1
System Interrupt Type Register 0
System Interrupt Type Register 1
TYPE1
HOSTINTNSTLVL0-
HOSTINTNSTLVL9
0x01C3 5100 - 0x01C3 5128
0x01C3 5500
Host Interrupt Nesting Level Registers 0-9
Host Interrupt Enable Register
HOSTINTEN
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6.30 Emulation Logic
This section describes the steps to use a third party debugger on the ARM926EJ-S within the device. The
debug capabilities and features for ARM are as shown below.
ARM:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Advanced Debug
–
–
Global Start
Global Stop
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
•
Program Trace
–
–
–
–
Program flow corruption
Code coverage
Path coverage
Thread/interrupt synchronization problems
•
•
•
Data Trace
–
Memory corruption
Timing Trace
–
Profiling
Analysis Actions
–
–
–
–
–
–
–
Stop program execution
Control trace streams
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
•
•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
–
–
Application access
Debugger access
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Table 6-121. ARM Debug Features
Category
Hardware Feature
Availability
Unlimited
Software breakpoint
Up to 14 HWBPs, including:
2 precise(1) HWBP inside ARM core which are shared with watch points.
8 imprecise(1) HWBPs from ETM’s address comparators, which are shared with trace
function, and can be used as watch points.
Basic Debug
Hardware breakpoint
4 imprecise(1) HWBPs from ICECrusher.
Up to 6 watch points, including:
2 from ARM core which is shared with HWBPs and can be associated with a data.
Watch point
8 from ETM’s address comparators, which are shared with trace function, and
HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
Watch point with Data
8 watch points from ETM can be associated with a data comparator, and ETM has
total 4 data comparators.
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
External Event Trigger Out
Address range for trace
1
1
4
Data qualification for trace
System events for trace control
Counters/Timers for trace control
State Machines/Sequencers
Context/Thread ID Comparator
Independent trigger control units
Capture depth PC
2
20
Trace Control
2x16-bit
1x3-State State Machine
1
12
4k bytes ETB
4k bytes ETB
Y
On-chip Trace
Capture
Capture depth PC + Timing
Application accessible
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
6.30.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and
emulation signals EMU0 and EMU1. TRST holds the debug and boundary scan logic in reset when pulled
low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the
device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST
should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be
performed while the TRST pin is pulled low.
Table 6-122. JTAG Port Description
PIN
TYPE
I
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to be reset
along with the IEEE 1149.1 interface
TRST
Test Logic Reset
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Depending on the emulator attached to , this is a free running clock or a gated clock
depending on RTCK monitoring.
TCK
I
Test Clock
Synchronized TCK. Depending on the emulator attached to, the JTAG signals are
clocked from RTCK or RTCK is monitored by the emulator to gate TCK.
RTCK
O
Returned Test Clock
TMS
TDI
I
I
Test Mode Select
Test Data Input
Test Data Output
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
TDO
O
Scan data output of the device
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Table 6-122. JTAG Port Description (continued)
PIN
TYPE
I/O
NAME
DESCRIPTION
EMU0
EMU1
Emulation 0
Emulation 1
Channel 0 trigger + HSRTDX
Channel 1 trigger + HSRTDX
I/O
6.30.2 Scan Chain Configuration Parameters
Table 6-123 shows the TAP configuration details required to configure the router/emulator for this device.
Table 6-123. JTAG Port Description
Router Port ID
Default TAP
TAP Name
C674x
Tap IR Length
17
18
19
No
No
No
38
4
ARM926
ETB
4
The router is revision C and has a 6-bit IR length.
6.30.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
6.30.3.1 Adding TAPS to the Scan Chain
The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans
must be completed to add the ARM926EJ-S to the scan chain.
A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only
the router’s TAP.
TDO
TDI
Router
CLK
TMS
Steps
Router
ARM926EJ-S/ETM
Figure 6-78. Adding ARM926EJ-S to the scan chain
Pre-amble: The device whose data reaches the emulator first is listed first in the board configuration file.
This device is a pre-amble for all the other devices. This device has the lowest device ID.
Post-amble: The device whose data reaches the emulator last is listed last in the board configuration file.
This device is a post-amble for all the other devices. This device has the highest device ID.
•
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '0'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '0'.
Parameter : The IR main count is '6'.
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–
Parameter : The DR main count is '1'.
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa2002108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
–
–
–
–
–
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
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The initial scan chain contains only the TAP router module. The following steps must be completed in
order to add ETB TAP to the scan chain.
ARM926EJ-S/ETM
TDI
Router
TDO
CLK
TMS
Steps
ETB
ARM926EJ-S/ETM
Router
Figure 6-79. Adding ETB to the scan chain
Function : Do a send-only JTAG IR/DR scan.
•
•
•
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000007'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '8'.
Parameter : The send data value is '0x00000089'.
Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-ir'.
Parameter : The JTAG destination state is 'pause-ir'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is '0x00000002'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Embed the port address in next command.
–
–
Parameter : The port address field is '0x0f000000'.
Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
–
–
–
–
–
–
Parameter : The route to JTAG shift state is 'shortest transition'.
Parameter : The JTAG shift state is 'shift-dr'.
Parameter : The JTAG destination state is 'pause-dr'.
Parameter : The bit length of the command is '32'.
Parameter : The send data value is '0xa3302108'.
Parameter : The actual receive data is 'discarded'.
•
Function : Do a send-only all-ones JTAG IR/DR scan.
Parameter : The JTAG shift state is 'shift-ir'.
–
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–
–
–
–
Parameter : The JTAG destination state is 'run-test/idle'.
Parameter : The bit length of the command is '6'.
Parameter : The send data value is 'all-ones'.
Parameter : The actual receive data is 'discarded'.
•
•
Function : Wait for a minimum number of TCLK pulses.
Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
–
–
–
–
–
–
–
Parameter : The IR pre-amble count is '0'.
Parameter : The IR post-amble count is '6 + 4'.
Parameter : The DR pre-amble count is '0'.
Parameter : The DR post-amble count is '1 + 1'.
Parameter : The IR main count is '4'.
Parameter : The DR main count is '1'.
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7 Device and Documentation Support
7.1 Device Support
www.ti.com
TI offers an extensive line of development tools for the device platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tool's support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the device applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the device, visit the Texas Instruments web site
on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing
and availability, contact the nearest TI field sales office or authorized distributor.
7.2 Documentation Support
The following documents describe the device. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
Reference Guides
SPRUGU4 AM1806 ARM Microprocessor System Reference Guide
SPRUFU0
AM17x/AM18x ARM Microprocessor Peripherals Overview Reference Guide
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8 Mechanical Packaging and Orderable Information
This section describes the device orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
8.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
AM1xxx processors and support tools. Each commercial AM1xxx platform member has one of three
prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators
for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
NULL devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
Figure 8-1 provides a legend for reading the complete device.
( )
( )
AM1806
X
ZWT
3
DEVICE SPEED RANGE
PREFIX
3 = 375 MHz
4 = 456 MHz
X = Experimental Device
P = Prototype Device
Blank = Production Device
TEMPERATURE RANGE (JUNCTION)
Blank
D
A
=
=
=
0°C to 90°C (Commercial Grade)
-40°C to 90°C (Industrial Grade)
-40°C to 105°C (Extended Grade)
DEVICE
PACKAGE TYPE
SILICON REVISION
ZCE = 361 Pin Plastic BGA, with Pb-free
Soldered Balls [Green], 0.65-mm Ball Pitch
B
= Silicon Revision 2.0
ZWT = 361 Pin Plastic BGA, with Pb-free
Soldered Balls [Green]; 0.80-mm Ball Pitch
A. BGA = Ball Grid Array
Figure 8-1. Device Nomenclature
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8.2 Thermal Data for ZCE Package
The following table(s) show the thermal resistance characteristics for the PBGA–ZCE mechanical
package.
Table 8-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]
NO.
1
°C/W(1)
7.6
AIR FLOW (m/s)(2)
RΘJC
RΘJB
RΘJA
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N /A
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
2
11.3
23.9
21.2
20.3
19.5
18.6
0.2
3
4
5
RΘJMA
Junction-to-moving air
6
7
8
9
0.3
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.3
0.4
0.5
11.2
11.1
11.1
11.0
10.9
PsiJB
Junction-to-board
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness
and 1.5oz (50um) inner copper thickness
(2) m/s = meters per second
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8.3 Thermal Data for ZWT Package
The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical
package.
Table 8-2. Thermal Resistance Characteristics (PBGA Package) [ZWT]
NO.
1
°C/W(1)
7.3
AIR FLOW (m/s)(2)
RΘJC
RΘJB
RΘJA
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N /A
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
2
12.4
23.7
21.0
20.1
19.3
18.4
0.2
3
4
5
RΘJMA
Junction-to-moving air
6
7
8
9
0.3
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.3
0.4
0.5
12.3
12.2
12.1
12.0
11.9
PsiJB
Junction-to-board
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
(2) m/s = meters per second
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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SI9137LG
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SI9122E
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