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AM2431BSDGHIALXR [TI]

具有工业通信和信息安全功能且频率高达 800MHz 的 Arm® Cortex®-R5F MCU | ALX | 293 | -40 to 125;
AM2431BSDGHIALXR
型号： AM2431BSDGHIALXR
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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具有工业通信和信息安全功能且频率高达 800MHz 的 Arm® Cortex®-R5F MCU | ALX | 293 | -40 to 125

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AM2434, AM2432, AM2431  
SPRSP65B – APRIL 2021 – REVISED JULY 2021  
AM243x Sitara™ Microcontrollers  
– Multiplier with optional accumulator  
(MAC)  
1 Features  
Processor cores:  
– CRC16/32 hardware accelerator  
– Byte swap for Big/Little Endian  
conversion  
– SUM32 hardware accelerator for UDP  
checksum  
– Task Manager for preemption support  
Up to 2× 10/100/1000 Ethernet ports  
Three Data RAMs with ECC  
8 banks of 30 × 32-bit register scratchpad  
memory  
Interrupt controller and task manager  
2× 64-bit Industrial Ethernet Peripherals  
(IEPs) for time stamping and other time  
synchronization functions  
•
Up to 2× Dual-core Arm® Cortex®-R5F MCU  
subsystems operating at up to 800 MHz, highly-  
integrated for real-time processing  
– Dual-core Arm® Cortex®-R5F clusters support  
dual-core and single-core operation  
– 32KB ICache and 32KB DCache per R5F core  
with SECDED ECC on all memories  
– Single-core: 128KB TCM per cluster (128KB  
TCM per R5F core)  
•
•
•
•
•
– Dual-core: 128KB TCM per cluster (64KB TCM  
per R5F core)  
•
1× Single-core Arm® Cortex®-M4F MCU  
subsystem at up to 400 MHz  
•
18× Sigma-Delta filters  
– Short circuit logic  
– 256KB SRAM with SECDED ECC  
– Over-current logic  
Memory subsystem:  
•
•
•
6× Multi-protocol position encoder interfaces  
One Enhanced Capture Module (ECAP)  
16550-compatible UART with a  
– Dedicated 192-MHz clock to support 12-  
Mbps PROFIBUS  
•
Up to 2MB of On-chip RAM (OCSRAM) with  
SECDED ECC:  
– Can be divided into smaller banks in  
increments of 256KB for as many as 8 separate  
memory banks  
– Each memory bank can be allocated to a single  
core to facilitate software task partitioning  
DDR Subsystem (DDRSS)  
– Supports LPDDR4, DDR4 memory types  
– 16-Bit data bus with inline ECC  
– Supports speeds up to 1600 MT/s  
System on Chip (SoC) Services:  
•
Device Management Security Controller (DMSC-L)  
•
– Centralized SoC system controller  
– Manages system services including initial boot,  
security, and clock/reset/power management  
– Communication with various processing units  
over message manager  
Industrial subsystem:  
– Simplified interface for optimizing unused  
peripherals  
– On-Chip Debug functionality through JTAG and  
Trace interfaces)  
•
2× Gigabit Industrial Communication Subsystems  
(PRU_ICSSG)  
– Optional support for Profinet IRT, Profinet  
RT, EtherNet/IP, EtherCAT, Time-Sensitive  
Networking (TSN), and other Networking  
Protocols  
– Backwards compatibility with 10/100Mb  
PRU_ICSS  
– Each PRU_ICSSG contains:  
•
•
Data Movement Subsystem (DMSS)  
– Block Copy DMA (BCDMA)  
– Packet DMA (PKTDMA)  
– Secure Proxy (SEC_PROXY)  
– Ring Accelerator (RINGACC)  
Time Sync Subsystem  
– Central Platform Time Sync (CPTS) module  
– Timer Manager (TIMERMANAGER) with 1024  
timers  
•
3× PRU RISC Cores per Slice (2× Slice per  
PRU_ICSSG)  
– PRU General Use core (PRU)  
– PRU Real-Time Unit core (PRU-RTU)  
– PRU Transmit core (PRU-TX)  
Each PRU core supports the following  
features:  
– Time Sync and Compare event interrupt routers  
•
Security:  
•
Secure Boot supported  
– Hardware-enforced Root-of-Trust (RoT)  
– Support to switch RoT via backup key  
– Instruction RAM with ECC  
– Broadside RAM  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
AM2434, AM2432, AM2431  
SPRSP65B – APRIL 2021 – REVISED JULY 2021  
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– Support for takeover protection, IP protection,  
and anti-roll back protection  
Support for cryptographic acceleration  
– Session-aware cryptographic engine with ability  
to auto-switch key-material based on incoming  
data stream  
General connectivity peripherals:  
•
•
6× Inter-Integrated Circuit (I2C) ports  
9× configurable Universal Asynchronous Receive/  
Transmit (UART) modules  
•
•
1× 12-bit Analog-to-Digital Converters (ADC)  
– Up to 4 MSPS  
– Supports cryptographic cores  
– 8× multiplexed analog inputs  
7× Multichannel Serial Peripheral Interfaces  
(MCSPI) controllers  
•
•
•
•
•
•
AES – 128/192/256 Bits key sizes  
3DES – 56/112/168 Bits key sizes  
MD5, SHA1  
•
•
3× General-Purpose I/O (GPIO) modules  
SHA2 – 224/256/384/512  
Industrial and control interfaces:  
DRBG with true random number generator  
PKA (Public Key Accelerator) to Assist in  
RSA/ECC processing  
•
9× Enhanced Pulse-Width Modulator (EPWM)  
modules  
– DMA support  
Debugging security  
– Secure software controlled debug access  
– Security aware debugging  
Trusted Execution Environment (TEE) supported  
– Arm TrustZone® based TEE  
– Extensive firewall support for isolation  
– Secure DMA Path and Interconnect  
– Secure watchdog/timer/IPC  
•
•
3× Enhanced Capture (ECAP) modules  
3× Enhanced Quadrature Encoder Pulse (EQEP)  
modules  
•
•
•
2× Modular Controller Area Network (MCAN)  
modules with full CAN-FD support  
•
•
2× Fast Serial Interface Transmitter (FSI_TX)  
cores  
6× Fast Serial Interface Receiver (FSI_RX) cores  
•
•
Secure storage support  
On-the-Fly encryption (OTFE) support for OSPI  
interface in XIP mode  
Networking security support for data (Payload)  
encryption/authentication via packet based  
hardware cryptographic engine  
Security co-processor (DMSC-L) for key and  
security management, with dedicated device level  
interconnect for security  
Memory controllers:  
•
2× MultiMedia Card/Secure Digital (MMC/SD)  
interfaces  
•
•
– One 4-bit for SD/SDIO  
– One 8-bit for eMMC  
– Integrated analog switch for voltage switching  
between 3.3V to 1.8V for high-speed cards  
1× General-Purpose Memory Controller (GPMC)  
– 16-bit parallel bus with 133 MHz clock or  
– 32-bit parallel bus with 100 MHz clock  
– Error Location Module (ELM) support  
•
•
High-speed serial interfaces:  
•
1× Integrated Ethernet switch supporting up to 2  
external ports (CPSW3G)  
– Up to 2 RGMII (10/100/1000)  
– IEEE 1588 (2008 Annex D, Annex E, Annex F)  
with 802.1AS PTP  
– Clause 45 MDIO PHY management  
– Energy efficient Ethernet (802.3az)  
1× PCI-Express® Gen2 controller (PCIE)  
– Supports Gen2 operation  
– Supports Single Lane operation  
1× USB 3.1-Gen1 Dual-role Device (DRD)  
Subsystem (USBSS)  
– One shared USBSS port for enhanced  
SuperSpeed Gen1 or USB 2.0  
1× Flash Subsystem (FSS) that can be configured  
as Octal SPI (OSPI) flash interfaces or one Quad  
SPI (QSPI)  
Power Management:  
•
•
•
Simplified power sequence  
Dual-voltage I/O Support  
•
•
Integrated SDIO LDO for handling automatic  
voltage transition for SD interface  
Integrated voltage supervisor for safety monitoring  
of over-under voltage conditions  
Integrated power supply glitch detector for  
detecting fast supply transients  
•
•
– Port configurable as USB host, USB peripheral,  
or USB Dual-role Device  
– Integrated USB VBUS detection  
1× Serializer/Deserializer (SERDES)  
– One SERDES lane to support PCI-Express®  
Gen2 and USB SuperSpeed Gen1  
•
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Functional Safety:  
SoC Architecture:  
•
Functional Safety-Compliant Targeted  
– Developed for functional safety applications  
– Documentation will be available to aid IEC  
61508 functional safety system design  
– Systematic capability up to SIL 3  
– Hardware integrity up to SIL 2 targeted for MCU  
domain  
•
Supports primary boot from UART, I2C, OSPI/  
QSPI Flash, SPI Flash, parallel NOR Flash,  
parallel NAND Flash, SD, eMMC, USB 2.0, PCIe,  
and Ethernet interfaces  
•
16-nm FinFET technology  
Package options:  
•
•
ALV FCBGA (441-pin) (Lidded) Flip-Chip Ball Grid  
Array package, 17.2 mm × 17.2 mm, 0.8-mm pitch  
ALX FC/CSP (293-pin) (SiP) Flip-Chip Chip Scale  
Package package, 11 mm × 11 mm, 0.5-mm pitch  
– Quality-managed MAIN Domain  
– Safety-related certification  
•
IEC 61508 certification planned  
– ECC or parity on calculation-critical memories  
– ECC and parity on select internal bus  
interconnects  
– Built-In Self-Test (BIST) for CPU and on-chip  
RAM  
– Error Signaling Module (ESM) with external  
error pin  
– Run-time safety diagnostics, including:  
•
•
•
Voltage, Temperature, and Clock Monitoring  
Windowed Watchdog Timers  
CRC Engine for memory integrity checks  
– MCU Domain with dedicated memory,  
interfaces, and M4FSS capable of being  
isolated from the larger SoC with Freedom  
From Interference (FFI) features  
•
•
•
•
•
Separate interconnect  
Firewalls and timeout gaskets  
Dedicated PLL  
Dedicated I/O supply  
Separate reset  
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2 Applications  
•
•
•
•
Programmable Logic Controller (PLC)  
Motor Drives  
Remote I/O  
Industrial Robots  
3 Description  
AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The  
AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require  
a combination of real-time communications and processing. The AM243x family provides scalable performance  
with up to four Cortex-R5F MCUs and one Cortex-M4F.  
The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high-  
performance Arm Cortex-R5F cores, Tightly-Coupled Memory banks, configurable SRAM partitioning, and  
dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This  
deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the  
peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable  
a number of different architectures found in these systems.  
The PRU-ICSSG in AM243x provides the flexible industrial communications capability necessary to run gigabit  
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU-ICSSG also enables  
additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.  
Functional safety features can be enabled through the integrated Cortex-M4F along with its dedicated  
peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.  
Device Information  
PART NUMBER  
XAM2434...ALV(2)  
PACKAGE(1)  
FCBGA (441) [Lidded]  
FC/CSP (293) [SiP]  
FCBGA (441) [Lidded]  
FC/CSP (293) [SiP]  
FCBGA (441) [Lidded]  
FC/CSP (293) [SiP]  
BODY SIZE  
17.2 mm × 17.2 mm  
11 mm × 11 mm  
XAM2434...ALX(2)  
XAM2432...ALV(2)  
XAM2432...ALX(2)  
XAM2431..ALV(2)  
XAM2431..ALX(2)  
17.2 mm × 17.2 mm  
11 mm × 11 mm  
17.2 mm × 17.2 mm  
11 mm × 11 mm  
(1) For more information, see Section 11, Mechanical, Packaging, and Orderable Information.  
(2) All XAM243x part numbers correspond to the fully featured XAM2434ASFGGAALX or  
XAM2434ASFGGAALV.  
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3.1 Functional Block Diagram  
Figure 3-1 is the functional block diagram for the device.  
AM243x  
Real-time cores  
Isolated core(A)  
Arm®  
Arm®  
Arm®  
Arm®  
Arm®  
Cortex®-R5F Cortex®-R5F Cortex®-R5F Cortex®-R5F  
Cortex®-M4F  
128KB TCM  
128KB TCM  
256KB SRAM  
System Memory  
DDR4/LPDDR4 with inline ECC  
2 MB SRAM with ECC  
2x MMCSD  
Security  
System Services  
SHA  
PKA  
DRBG  
12x GP Timers  
AES  
Sync  
4x WWDT  
Manager  
Secure  
Boot  
MD5  
3DES  
Isolated Connectivity(A)  
(for use with Cortex-M4F)  
Industrial Connectivity  
GPMC / ELM  
General Connectivity  
GPIO  
5x MCSPI  
4x I2C  
PRU-ICSS(Gb)  
PCIe  
1x Single lane  
Gen 2  
Encoder  
with 9x ∑∆  
GPIO  
2x MCSPI  
2x I2C  
8x FSI  
9x EPWM  
3x ECAP  
3x EQEP  
2x CAN-FD  
2x GMAC  
2-port Gb  
Ethernet  
7x UART  
PRU-ICSS(Gb)  
2x UART  
OSPI or QSPI  
1x ADC  
1x USB 3.1 DRD  
Encoder  
2x GMAC  
with 9x ∑∆  
intro_001  
A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across SoC when in non-isolated  
configuration.  
B. USB3.1 and PCIe share a common SerDes lane.  
Figure 3-1. Functional Block Diagram  
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Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................4  
3 Description.......................................................................4  
3.1 Functional Block Diagram...........................................5  
4 Revision History.............................................................. 6  
5 Device Comparison.........................................................7  
5.1 Related Products........................................................ 9  
6 Terminal Configuration and Functions........................10  
6.1 Pin Diagram.............................................................. 10  
6.2 Pin Attributes (ALV Package)....................................12  
6.3 Pin Attributes (ALX Package)................................... 75  
6.4 Signal Descriptions................................................. 122  
6.5 Pin Multiplexing.......................................................167  
6.6 Connections for Unused Pins................................. 177  
7 Specifications.............................................................. 181  
7.1 Absolute Maximum Ratings.................................... 181  
7.2 ESD Ratings........................................................... 182  
7.3 Power-On Hours (POH)..........................................182  
7.4 Recommended Operating Conditions.....................183  
7.5 Operating Performance Points................................185  
7.6 Power Consumption Summary............................... 185  
7.7 Electrical Characteristics.........................................186  
7.8 VPP Specifications for One-Time Programmable  
7.9 Thermal Resistance Characteristics....................... 193  
7.10 Timing and Switching Characteristics................... 194  
8 Detailed Description....................................................285  
8.1 Overview.................................................................285  
8.2 Processor Subsystems........................................... 286  
8.3 Accelerators and Coprocessors..............................287  
8.4 Other Subsystems.................................................. 287  
9 Applications, Implementation, and Layout............... 295  
9.1 Power Supply Mapping...........................................295  
9.2 Device Connection and Layout Fundamentals....... 296  
9.3 Peripheral- and Interface-Specific Design  
Information................................................................ 297  
10 Device and Documentation Support........................303  
10.1 Device Nomenclature............................................303  
10.2 Tools and Software............................................... 305  
10.3 Documentation Support........................................ 306  
10.4 Support Resources............................................... 306  
10.5 Trademarks...........................................................306  
10.6 Electrostatic Discharge Caution............................306  
10.7 Glossary................................................................306  
11 Mechanical, Packaging, and Orderable  
Information.................................................................. 307  
11.1 Packaging Information.......................................... 307  
(OTP) eFuses............................................................192  
4 Revision History  
Changes from July 1, 2021 to July 16, 2021 (from Revision A (July 2021) to Revision B (July  
2021))  
Page  
•
Added footnote for AM2432_ALV/ALX and AM2431_ALV/ALX device options regarding pre-production part  
numbers..............................................................................................................................................................4  
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5 Device Comparison  
Table 5-1 shows a comparison between devices, highlighting the differences.  
Table 5-1. Device Comparison  
REFERENCE  
NAME  
AM2434  
(ALV)  
AM2432  
(ALV)  
AM2431  
(ALV)  
AM2434  
(ALX)  
AM2432  
(ALX)  
AM2431  
(ALX)  
FEATURES(1)  
JTAG DEVICE ID Comparison (Features)  
C: ----------- C: 0x19023 C: 0x19003 C: ----------- C: 0x19023 C: 0x19003  
CTRLMMR_JTAG_DEVICE_ID[31:13] DEVICE_ID register D: 0x19064 D: 0x19024 D: 0x19004 D: 0x19064 D: 0x19024 D: 0x19004  
bit-field value(2)  
E: 0x19065 E: 0x19025 E: ----------- E: 0x19065 E: 0x19025 E: -----------  
F: 0x19066 F: 0x19026 F: ----------- F: 0x19066 F: 0x19026 F: -----------  
PROCESSORS AND ACCELERATORS  
Speed Grades  
See Table 7-2  
2 × Dual  
Core  
2 × Single 1 × Single 2 × Dual  
2× Single  
Core  
1 × Single  
Core  
Arm Cortex-R5F Processor  
R5FSS  
Core  
Core  
Core  
Cluster  
Cluster  
Cluster  
Cluster  
Cluster  
Cluster  
Arm Cortex-M4F Processor  
M4FSS  
DMSC-L  
Security  
Safety  
1 × Single Core  
1 × Single Core  
Device Management Security  
Controller  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
Crypto Accelerators  
Functional Safety-capable MCU  
Domain with M4FSS  
PROGRAM AND DATA STORAGE  
Shared On-Chip Memory (OCSRAM)  
in MAIN Domain  
OCSRAM  
2MB  
2MB  
R5F Tightly Coupled Memory (TCM)(3)  
TCM  
256KB  
256KB  
256KB  
128KB  
256KB  
256KB  
256KB  
128KB  
Shared On-Chip Memory (OCSRAM)  
in MCU Domain  
MCU_MSRAM  
Up to 2GB (16-bit data) with inline  
ECC  
DDR4/LPDDR4 DDR Subsystem  
DDRSS  
-
-
General-Purpose Memory Controller  
w/Error Location Module (ELM)  
GPMC w/ELM  
Up to 1GB with ECC  
PERIPHERALS  
Modular Controller Area Network  
Interface  
MCAN  
2
2
Full CAN-FD Support  
MCAN  
GPIO  
I2C  
Optional  
Up to 198  
Optional  
General-Purpose I/O  
Up to 148  
Inter-Integrated Circuit Interface  
Analog-to-Digital Converter  
6 (2 in MCU Domain)  
1
3 (MAIN Domain Only)  
1
ADC  
Multichannel Serial Peripheral  
Interface  
MCSPI  
7 (2 in MCU Domain)  
4 (MAIN Domain Only)  
MMC0  
MMC1  
eMMC (8-bits)  
-
MultiMedia Card/ Secure Digital  
Interface  
SD/SDIO (4-bits)  
SD/SDIO (4-bits)  
FSI_TX  
FSI_RX  
OSPI/QSPI  
PCIE  
2
6
1
Fast Serial Interface  
4
Flash Subsystem (FSS)  
Yes(4)  
QSPI-Mode Only  
-
PCI Express Port with Integrated PHY  
Single Lane  
Programmable Real-Time Unit  
Subsystem  
(PRU Cores, eGPIO, UART, ECAP.  
EPWM)  
PRU_ICSSG  
2
2
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Table 5-1. Device Comparison (continued)  
REFERENCE  
NAME  
AM2434  
(ALV)  
AM2432  
(ALV)  
AM2431  
(ALV)  
AM2434  
(ALX)  
AM2432  
(ALX)  
AM2431  
(ALX)  
FEATURES(1)  
Industrial Communication Subsystem  
Support  
(RGMII/MII and additional Networking  
Interfaces)  
PRU_ICSSG  
Optional  
Optional  
Gigabit Ethernet Interface  
General-Purpose Timers  
CPSW3G  
TIMER  
Yes (2 External Ports)  
16 (4 in MCU Domain)  
Yes (2 External Ports)  
16 (4 in MCU Domain)  
Enhanced Pulse-Width Modulation  
Module  
EPWM  
ECAP  
EQEP  
9
3
3
7(5)  
3
Enhanced Capture Module  
Enhanced Quadrature Encoder Pulse  
Module  
3
Universal Asynchronous Receiver/  
Transmitter  
UART  
USB  
9 (2 in MCU Domain)  
Yes  
8 (1 in MCU Domain)  
Universal Serial Bus (USB3.1 Gen1)  
SuperSpeed Dual-Role-Device (DRD)  
Port with SS PHY  
No USB SuperSpeed Support  
(USB2 Only)  
(1) Features noted as “not supported” or "-", must not be used. Their functionality is not supported by TI for this family of devices. These  
features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been  
retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.  
(2) For more details about the CTRLMMR_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device's associated Technical  
Reference Manual.  
(3) The R5F cores share Tightly Coupled Memory within a cluster and can be allocated per system requirements.  
(4) One simultaneous flash interface configured as OSPI0 or QSPI0.  
(5) Only the A output signal is available for the EHRPWM5 instance of the ALX package type.  
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5.1 Related Products  
Sitara™ processors Broad family of scalable processors based on Arm® Cortex® cores with flexible  
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara  
processors have the reliability needed for use in industrial applications.  
AM243x Sitara™ microcontrollers AM243x microcontrollers enable gigabit industrial Ethernet networks, robust  
operation with extensive ECC on memories, and enhanced security features.  
Sitara™ processors - Applications Sitara™ processors provide scalable solutions for a wide range of  
applications from HMIs and gateways to more complex equipment such as drives and substation automation  
equipment. Sitara processors also offer multi-protocol support for industrial communication protocols such as  
EtherCAT®, Ethernet/IP, and Profinet.  
Sitara™ processors - Reference designs TI provides many reference designs containing ‘building block’  
solutions to enable customers to rapidly develop their own unique products and solutions.  
Companion Products for AM243x Review products that are frequently purchased or used in conjunction with  
this product to complete your design.  
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6 Terminal Configuration and Functions  
6.1 Pin Diagram  
Note  
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt  
is made to use "ball" only when referring to the physical package.  
The diagrams in this section are used in conjunction with the other Terminal Configuration and Functions tables  
to locate signal names and ball grid numbers.  
6.1.1 AM243x ALV Pin Diagram  
ALV FCBGA-N441 Pin Diagram shows the ball locations for the lidded 441-ball flip chip ball grid array (FCBGA)  
package.  
Figure 6-1. ALV FCBGA-N441 Pin Diagram (Bottom View)  
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6.1.2 AM243x ALX Pin Diagram  
ALX FCBGA-N293 Pin Diagram shows the ball locations for the non-lidded 293-ball flip chip ball grid array  
(FCBGA) package.  
Figure 6-2. ALX FCBGA-N293 Pin Diagram (Bottom View)  
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6.2 Pin Attributes (ALV Package)  
The following list describes the contents of each column in the Pin Attributes table:  
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.  
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically taken from the primary MUXMODE 0 signal  
function).  
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.  
Note  
The Pin Attributes table, defines the pin multiplexed signal functions implemented at the pin and does not define secondary multiplexing  
of signal functions implemented in device subsystems. Secondary multiplexing of signal functions are not described in this table. For more  
information on seconadry multiplexed signal functions, see the respective peripheral chapter of the device TRM.  
4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:  
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal function is not necessarily the default pin  
multiplexed signal function.  
Note  
The value found in the MUX MODE AFTER RESET column defines the default pin multiplexed signal function selected when  
MCU_PORz is deasserted.  
b. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all MUXMODE values have been implemented.  
The only valid MUXMODE values are those defined as pin multiplexed signal functions within the Pin Attributes table. Only valid values of  
MUXMODE should be used.  
c. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the rising edge of PORz_OUT. These input  
signal functions are fixed to their respective pins and are not programmable via MUXMODE.  
d. An empty box or "-" means Not Applicable.  
5. TYPE: Signal type and direction:  
•
•
•
•
•
•
•
•
•
•
I = Input  
O = Output  
IO = Input, Output, or simultaneously Input and Output  
IOD = Input, Output, or simultaneously Input and Output, with open-drain output function  
IOZ = Input, Output, or simultaneously Input and Output, with three-state output function  
OZ = Output with three-state output function  
A = Analog  
PWR = Power  
GND = Ground  
CAP = LDO Capacitor.  
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6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic "1", or "pad" level) when the pin multiplexed  
signal function is not selected by MUXMODE.  
•
•
•
•
0: Logic 0 driven to the subsystem input.  
1: Logic 1 driven to the subsystem input.  
pad: Logic state of the pad is driven to the subsystem input.  
An empty box or "-" means Not Applicable.  
7. BALL STATE DURING RESET (RX/TX/PULL): State of the terminal while MCU_PORz is asserted, where RX defines the state of the input buffer, TX  
defines the state of the output buffer, and PULL defines the state of internal pull resistors:  
•
•
•
RX (Input buffer)  
– Off: The input buffer is disabled.  
– On: The input buffer is enabled.  
TX (Output buffer)  
– Off: The output buffer is disabled.  
– Low: The output buffer is enabled and drives VOL  
PULL (Internal pull resistors)  
.
– Off: Internal pull resistors are turned off.  
– Up: Internal pull-up resistor is turned on.  
– Down: Internal pull-down resistor is turned on.  
An empty box or "-" means Not Applicable.  
•
8. BALL STATE AFTER RESET (RX/TX/PULL): State of the terminal after MCU_PORz is deasserted, where RX defines the state of the input buffer,  
TX defines the state of the output buffer, and PULL defines the state of internal pull resistors:  
•
•
•
RX (Input buffer)  
– Off: The input buffer is disabled.  
– On: The input buffer is enabled.  
TX (Output buffer)  
– Off: The output buffer is disabled.  
– SS: The subsystem selected with MUXMODE determines the output buffer state.  
PULL (Internal pull resistors)  
– Off: Internal pull resistors are turned off.  
– Up: Internal pull-up resistor is turned on.  
– Down: Internal pull-down resistor is turned on.  
An empty box or "-" means Not Applicable.  
•
9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal function after MCU_PORz is deasserted.  
An empty box means Not Applicable.  
10. I/O VOLTAGE VALUE: This column describes I/O operating voltage options of the respective power supply, when applicable.  
An empty box or "-" means Not Applicable.  
For more information, see valid operating voltage range(s) defined for each power supply in Recommended Operating Conditions.  
11. POWER: The power supply of the associated I/O, when applicable.  
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An empty box or "-" means Not Applicable.  
12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:  
•
•
•
Yes: With hysteresis  
No: Without hysteresis  
An empty box or "-" means Not Applicable.  
For more information, see the hysteresis values in Electrical Characteristics.  
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be used to determine which Electrical  
Characteristics table is applicable.  
An empty box or "-" means Not Applicable.  
For electrical characteristics, refer to the appropriate buffer type table in Electrical Characteristics.  
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled  
via software.  
•
•
•
•
PU: Internal pull-up  
PD: Internal pull-down  
PU/PD: Internal pull-up and pull-down  
An empty box or "-" means No internal pull.  
Note  
Configuring two pins to the same pin multiplexed signal function is not supported as it can yield unexpected results. This can be easily  
prevented with the proper software configuration.  
Note  
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be  
avoided.  
Table 6-1. Pin Attributes (ALV Package)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
NUMBER  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
G20  
F20  
E21  
D20  
ADC0_AIN0  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
0
0
0
0
A
1.8 V  
VDDA_ADC0  
Yes  
Yes  
Yes  
Yes  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
A
A
A
1.8 V  
1.8 V  
1.8 V  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
G21  
F21  
F19  
E20  
H12  
T7  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
CAP_VDDS0  
CAP_VDDS1  
CAP_VDDS2  
CAP_VDDS3  
CAP_VDDS4  
CAP_VDDS5  
0
0
0
0
A
1.8 V  
VDDA_ADC0  
Yes  
Yes  
Yes  
Yes  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
A
1.8 V  
1.8 V  
1.8 V  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
ADC0_AIN6  
ADC0_AIN7  
CAP_VDDS0  
CAP_VDDS1  
CAP_VDDS2  
CAP_VDDS3  
CAP_VDDS4  
CAP_VDDS5  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
A
A
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
O
R11  
N14  
M16  
L13  
K15  
H10  
H2  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
H1  
IO  
J5  
O
K5  
O
F6  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
O
H4  
O
D2  
O
C5  
DDR0_A1  
DDR0_A1  
O
E2  
DDR0_A2  
DDR0_A2  
O
D4  
DDR0_A3  
DDR0_A3  
O
D3  
DDR0_A4  
DDR0_A4  
O
F2  
DDR0_A5  
DDR0_A5  
O
J2  
DDR0_A6  
DDR0_A6  
O
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
L5  
J3  
DDR0_A7  
DDR0_A7  
O
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
DDR  
DDR0_A8  
DDR0_A8  
O
O
O
O
O
O
O
O
O
O
A
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
J4  
DDR0_A9  
DDR0_A9  
K3  
J1  
DDR0_A10  
DDR0_A11  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_A10  
DDR0_A11  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
M5  
K4  
G4  
G5  
G2  
H3  
H5  
F1  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
A2  
B5  
A4  
B3  
O
O
O
O
O
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
C4  
C2  
B4  
N5  
L4  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
IO  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.8 V/3.3 V  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDS_DDR, VDDS_DDR_C  
VDDSHV0  
DDR  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
LVCMOS  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
L2  
DDR0_DQ10  
DDR0_DQ11  
M3  
N4  
N3  
M4  
N2  
C1  
B1  
N1  
M1  
E5  
F5  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
DDR0_RESET0_n  
ECAP0_IN_APWM_OUT  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
O
D5  
D18  
DDR0_RESET0_n  
ECAP0_IN_APWM_OUT  
SYNC0_OUT  
O
0
1
2
5
6
7
0
IO  
O
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
0
Yes  
PU/PD  
CPTS0_RFT_CLK  
CP_GEMAC_CPTS0_RFT_CLK  
SPI4_CS3  
I
0
I
0
IO  
IO  
IO  
1
GPIO1_68  
pad  
D10  
EMU0  
EMU0  
On / Off / Up  
On / Off / Up  
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
E10  
C19  
A19  
EMU1  
EMU1  
0
IO  
On / Off / Up  
Off / Off / Off  
Off / Off / Off  
On / Off / Up  
Off / Off / Off  
Off / Off / Off  
0
0
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
Yes  
Yes  
LVCMOS  
I2C OD FS  
LVCMOS  
PU/PD  
MCU_OBSCLK0  
EXTINTn  
15  
0
7
0
1
2
5
7
0
1
2
3
6
7
9
0
1
2
3
4
6
7
9
O
I
EXTINTn  
1
VDDSHV0  
VDDSHV0  
GPIO1_70  
IO  
I
pad  
0
EXT_REFCLK1  
EXT_REFCLK1  
SYNC1_OUT  
PU/PD  
O
IO  
O
IO  
O
I
SPI2_CS3  
1
CLKOUT0  
GPIO1_69  
pad  
P16  
GPMC0_ADVn_ALE  
GPMC0_ADVn_ALE  
FSI_RX5_CLK  
UART5_RXD  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
1
0
I
EHRPWM_TZn_IN3  
TRC_DATA15  
GPIO0_32  
I
O
IO  
I
pad  
0
PRG0_PWM3_TZ_IN  
GPMC0_CLK  
R17  
GPMC0_CLK  
O
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_RX4_CLK  
UART4_RTSn  
EHRPWM3_SYNCO  
GPMC0_FCLK_MUX  
TRC_DATA14  
GPIO0_31  
0
O
O
O
O
IO  
O
pad  
PRG0_PWM3_TZ_OUT  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
N17  
GPMC0_DIR  
GPMC0_DIR  
EQEP0_B  
0
3
7
8
9
0
1
2
3
6
7
9
0
1
2
3
6
7
9
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
0
GPIO0_40  
IO  
IO  
IO  
O
I
pad  
0
EHRPWM6_B  
PRG1_PWM2_B0  
GPMC0_OEn_REn  
FSI_RX5_D0  
1
R18  
GPMC0_OEn_REn  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0
UART5_TXD  
O
IO  
O
IO  
IO  
O
I
EHRPWM4_A  
TRC_DATA16  
GPIO0_33  
pad  
0
PRG0_PWM3_A1  
GPMC0_WEn  
FSI_RX5_D1  
T21  
GPMC0_WEn  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0
UART5_RTSn  
EHRPWM4_B  
TRC_DATA17  
GPIO0_34  
O
IO  
O
IO  
IO  
pad  
1
PRG0_PWM3_B1  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
N16  
GPMC0_WPn  
GPMC0_WPn  
0
1
3
4
6
7
8
9
0
1
2
3
6
7
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_TX1_CLK  
EQEP0_A  
O
I
0
GPMC0_A22  
TRC_DATA22  
GPIO0_39  
OZ  
O
IO  
IO  
IO  
IO  
I
pad  
0
EHRPWM6_A  
PRG1_PWM2_A0  
GPMC0_AD0  
FSI_RX2_CLK  
UART2_RXD  
EHRPWM0_SYNCI  
TRC_CLK  
0
T20  
GPMC0_AD0  
0
On / Off / Off  
On / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
I
1
I
0
O
IO  
I
GPIO0_15  
pad  
BOOTMODE00  
Bootstra  
p
U21  
GPMC0_AD1  
GPMC0_AD1  
0
1
2
3
6
7
9
IO  
I
0
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_RX2_D0  
UART2_TXD  
O
O
O
IO  
O
I
EHRPWM0_SYNCO  
TRC_CTL  
GPIO0_16  
pad  
PRG0_PWM2_TZ_OUT  
BOOTMODE01  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
T18  
GPMC0_AD2  
GPMC0_AD2  
FSI_RX2_D1  
UART2_RTSn  
0
1
2
3
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
0
O
I
EHRPWM_TZn_IN0  
TRC_DATA0  
0
O
IO  
I
GPIO0_17  
pad  
0
PRG0_PWM2_TZ_IN  
BOOTMODE02  
Bootstra  
p
I
U20  
GPMC0_AD3  
GPMC0_AD3  
FSI_RX3_CLK  
UART3_RXD  
EHRPWM0_A  
TRC_DATA1  
0
1
2
3
6
7
9
IO  
I
0
0
1
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
IO  
O
IO  
IO  
I
GPIO0_18  
pad  
0
PRG0_PWM2_A0  
BOOTMODE03  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U18  
GPMC0_AD4  
GPMC0_AD4  
FSI_RX3_D0  
UART3_TXD  
EHRPWM0_B  
TRC_DATA2  
GPIO0_82  
0
1
2
3
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
0
O
IO  
O
IO  
IO  
I
0
pad  
1
PRG0_PWM2_B0  
BOOTMODE04  
Bootstra  
p
U19  
GPMC0_AD5  
GPMC0_AD5  
FSI_RX3_D1  
UART3_RTSn  
EHRPWM1_A  
TRC_DATA3  
0
1
2
3
6
7
9
IO  
I
0
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
IO  
IO  
I
0
GPIO0_83  
pad  
0
PRG0_PWM2_A1  
BOOTMODE05  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V20  
GPMC0_AD6  
GPMC0_AD6  
FSI_RX4_D0  
UART4_RXD  
EHRPWM1_B  
TRC_DATA4  
GPIO0_21  
0
1
2
3
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
0
1
0
I
IO  
O
IO  
IO  
I
pad  
1
PRG0_PWM2_B1  
BOOTMODE06  
Bootstra  
p
V21  
GPMC0_AD7  
GPMC0_AD7  
FSI_RX4_D1  
0
1
2
3
4
6
7
9
IO  
I
0
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
UART4_TXD  
O
I
EHRPWM_TZn_IN1  
EHRPWM8_A  
TRC_DATA5  
0
0
IO  
O
IO  
IO  
I
GPIO0_22  
pad  
0
PRG1_PWM2_A2  
BOOTMODE07  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V19  
GPMC0_AD8  
GPMC0_AD8  
0
1
2
3
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_RX0_CLK  
UART2_CTSn  
EHRPWM2_A  
TRC_DATA6  
I
0
1
0
I
IO  
O
IO  
IO  
I
GPIO0_23  
pad  
0
PRG0_PWM2_A2  
BOOTMODE08  
Bootstra  
p
T17  
GPMC0_AD9  
GPMC0_AD9  
FSI_RX0_D0  
UART3_CTSn  
EHRPWM2_B  
TRC_DATA7  
0
1
2
3
6
7
9
IO  
I
0
0
1
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
IO  
O
IO  
IO  
I
GPIO0_24  
pad  
1
PRG0_PWM2_B2  
BOOTMODE09  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
R16  
GPMC0_AD10  
GPMC0_AD10  
0
1
2
3
4
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_RX0_D1  
I
0
1
0
0
UART4_CTSn  
EHRPWM_TZn_IN2  
EHRPWM8_B  
TRC_DATA8  
I
I
IO  
O
IO  
IO  
I
GPIO0_25  
pad  
1
PRG1_PWM2_B2  
BOOTMODE10  
Bootstra  
p
W20  
GPMC0_AD11  
GPMC0_AD11  
FSI_RX1_CLK  
UART5_CTSn  
EQEP1_A  
0
1
2
3
6
7
8
IO  
I
0
0
1
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I
I
TRC_DATA9  
GPIO0_26  
O
IO  
IO  
I
pad  
0
EHRPWM7_A  
BOOTMODE11  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
W21  
GPMC0_AD12  
GPMC0_AD12  
0
1
2
3
6
7
8
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_RX1_D0  
UART6_CTSn  
EQEP1_B  
I
0
1
0
I
I
TRC_DATA10  
GPIO0_27  
O
IO  
IO  
I
pad  
0
EHRPWM7_B  
BOOTMODE12  
Bootstra  
p
V18  
GPMC0_AD13  
GPMC0_AD13  
FSI_RX1_D1  
EHRPWM3_A  
TRC_DATA11  
GPIO0_28  
0
1
3
6
7
9
IO  
I
0
0
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
IO  
O
IO  
IO  
I
pad  
0
PRG0_PWM3_A0  
BOOTMODE13  
Bootstra  
p
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y21  
GPMC0_AD14  
GPMC0_AD14  
0
1
2
3
6
7
9
IO  
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_TX0_D0  
UART6_RXD  
EHRPWM3_B  
TRC_DATA12  
GPIO0_29  
O
I
1
0
IO  
O
IO  
IO  
I
pad  
1
PRG0_PWM3_B0  
BOOTMODE14  
Bootstra  
p
Y20  
GPMC0_AD15  
GPMC0_AD15  
FSI_TX0_D1  
0
1
2
3
6
7
IO  
O
O
I
0
On / Off / Off  
On / Off / Off  
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
UART6_TXD  
EHRPWM3_SYNCI  
TRC_DATA13  
GPIO0_30  
0
O
IO  
I
pad  
BOOTMODE15  
Bootstra  
p
P17  
GPMC0_BE0n_CLE  
GPMC0_BE0n_CLE  
FSI_TX1_D0  
0
1
2
3
5
6
7
9
O
O
O
I
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
UART6_RTSn  
EHRPWM_TZn_IN4  
EHRPWM7_A  
TRC_DATA18  
0
0
IO  
O
IO  
IO  
GPIO0_35  
pad  
0
PRG1_PWM2_A1  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
T19  
GPMC0_BE1n  
GPMC0_BE1n  
0
1
3
6
7
9
0
3
6
7
8
0
3
5
7
8
9
0
1
2
3
5
7
9
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
FSI_TX0_CLK  
EHRPWM5_A  
TRC_DATA19  
GPIO0_36  
O
IO  
O
IO  
IO  
O
IO  
O
IO  
I
0
pad  
0
PRG0_PWM3_A2  
GPMC0_CSn0  
EQEP0_S  
R19  
GPMC0_CSn0  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
TRC_DATA23  
GPIO0_41  
pad  
0
EHRPWM6_SYNCI  
GPMC0_CSn1  
EQEP0_I  
R20  
GPMC0_CSn1  
O
IO  
I
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
EHRPWM_TZn_IN2  
GPIO0_42  
0
IO  
O
O
O
IOD  
IO  
IO  
I
pad  
EHRPWM6_SYNCO  
PRG1_PWM2_TZ_OUT  
GPMC0_CSn2  
I2C2_SCL  
P19  
GPMC0_CSn2  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
1
TIMER_IO8  
0
EQEP1_S  
0
EHRPWM_TZn_IN4  
GPIO0_43  
0
IO  
I
pad  
0
PRG1_PWM2_TZ_IN  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
R21  
GPMC0_CSn3  
GPMC0_CSn3  
0
1
2
3
4
5
7
0
3
6
7
9
0
1
3
4
5
6
7
9
0
4
7
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
I2C2_SDA  
IOD  
IO  
IO  
OZ  
I
1
TIMER_IO9  
0
0
EQEP1_I  
GPMC0_A20  
EHRPWM_TZn_IN5  
GPIO0_44  
0
IO  
I
pad  
1
W19  
GPMC0_WAIT0  
GPMC0_WAIT0  
EHRPWM5_B  
TRC_DATA20  
GPIO0_37  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
IO  
O
0
IO  
IO  
I
pad  
1
PRG0_PWM3_B2  
GPMC0_WAIT1  
FSI_TX1_D1  
EHRPWM_TZn_IN5  
GPMC0_A21  
EHRPWM7_B  
TRC_DATA21  
GPIO0_38  
Y18  
GPMC0_WAIT1  
1
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
O
I
0
0
OZ  
IO  
O
IO  
IO  
IOD  
I
pad  
1
PRG1_PWM2_B1  
I2C0_SCL  
A18  
I2C0_SCL  
1
Off / Off / Off  
On / SS / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
I2C OD FS  
UART6_CTSn  
GPIO1_64  
1
IO  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
B18  
C18  
I2C0_SDA  
I2C1_SCL  
I2C0_SDA  
UART6_RTSn  
GPIO1_65  
I2C1_SCL  
0
4
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
6
7
8
9
IOD  
O
1
Off / Off / Off  
On / SS / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
I2C OD FS  
LVCMOS  
IO  
IOD  
I
pad  
1
Off / Off / Off  
Off / Off / Off  
Yes  
Yes  
Yes  
PU/PD  
PU/PD  
PU/PD  
CPTS0_HW1TSPUSH  
TIMER_IO0  
SPI2_CS1  
0
IO  
IO  
IO  
IOD  
I
0
1
GPIO1_66  
pad  
1
B19  
I2C1_SDA  
I2C1_SDA  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
LVCMOS  
CPTS0_HW2TSPUSH  
TIMER_IO1  
SPI2_CS2  
0
IO  
IO  
IO  
I
0
1
GPIO1_67  
pad  
1
B17  
MCAN0_RX  
MCAN0_RX  
UART4_TXD  
TIMER_IO3  
SYNC3_OUT  
SPI4_CS2  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
LVCMOS  
O
IO  
O
0
IO  
IO  
IO  
I
1
GPIO1_61  
pad  
0
EQEP2_S  
UART0_RIn  
1
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
A17  
MCAN0_TX  
MCAN0_TX  
UART4_RXD  
TIMER_IO2  
SYNC2_OUT  
SPI4_CS1  
0
1
2
3
6
7
8
9
0
1
2
3
4
5
6
7
8
9
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
I
1
IO  
O
IO  
IO  
IO  
O
I
0
1
GPIO1_60  
EQEP2_I  
pad  
0
UART0_DTRn  
MCAN1_RX  
I2C3_SDA  
D17  
MCAN1_RX  
1
1
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IOD  
IO  
O
IO  
O
O
IO  
I
ECAP2_IN_APWM_OUT  
OBSCLK0  
TIMER_IO5  
0
UART5_TXD  
EHRPWM_SOCB  
GPIO1_63  
pad  
0
EQEP2_B  
UART0_DSRn  
OBSCLK0  
I
1
15  
O
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
C17  
MCAN1_TX  
MCAN1_TX  
I2C3_SCL  
0
1
2
3
4
5
6
7
8
9
0
7
0
7
0
7
0
7
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IOD  
IO  
O
1
ECAP1_IN_APWM_OUT  
SYSCLKOUT0  
0
TIMER_IO4  
IO  
I
0
1
UART5_RXD  
EHRPWM_SOCA  
GPIO1_62  
O
IO  
I
pad  
0
EQEP2_A  
UART0_DCDn  
I
1
E9  
MCU_I2C0_SCL  
MCU_I2C0_SDA  
MCU_I2C1_SCL  
MCU_I2C1_SDA  
MCU_I2C0_SCL  
MCU_GPIO0_18  
MCU_I2C0_SDA  
MCU_GPIO0_19  
MCU_I2C1_SCL  
MCU_GPIO0_20  
MCU_I2C1_SDA  
MCU_GPIO0_21  
MCU_OSC0_XI  
MCU_OSC0_XO  
MCU_PORz  
IOD  
IO  
IOD  
IO  
IOD  
IO  
IOD  
IO  
I
1
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / SS / Off  
On / SS / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
I2C OD FS  
I2C OD FS  
LVCMOS  
LVCMOS  
pad  
1
A10  
A11  
B10  
pad  
1
PU/PD  
PU/PD  
pad  
1
pad  
C21  
B20  
B21  
B13  
MCU_OSC0_XI  
MCU_OSC0_XO  
MCU_PORz  
1.8 V  
VDDS_OSC  
VDDS_OSC  
VDDS_OSC  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
HFOSC  
O
1.8 V  
HFOSC  
0
0
7
0
0
I
0
0
0
0
0
1.8 V  
FS RESET  
LVCMOS  
MCU_RESETSTATz  
MCU_RESETSTATz  
MCU_GPIO0_22  
MCU_RESETz  
MCU_SAFETY_ERRORn  
O
Off / Low / Off  
On / Off / Up  
Off / SS / Off  
On / Off / Up  
1.8 V/3.3 V  
PU/PD  
IO  
I
pad  
B12  
A20  
MCU_RESETz  
1.8 V/3.3 V  
1.8 V  
VDDSHV_MCU  
VDDS_OSC  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
MCU_SAFETY_ERRORn  
IO  
Off / Off / Down On / SS / Down  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
E6  
D7  
D6  
C6  
MCU_SPI0_CLK  
MCU_SPI0_CLK  
0
7
0
7
0
7
0
1
2
7
0
7
0
7
0
7
0
1
7
0
7
0
7
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
MCU_GPIO0_11  
MCU_SPI1_CLK  
MCU_GPIO0_7  
MCU_SPI0_CS0  
MCU_GPIO0_13  
MCU_SPI0_CS1  
MCU_OBSCLK0  
MCU_SYSCLKOUT0  
MCU_GPIO0_12  
MCU_SPI0_D0  
MCU_GPIO0_10  
MCU_SPI0_D1  
MCU_GPIO0_4  
MCU_SPI1_CS0  
MCU_GPIO0_5  
MCU_SPI1_CS1  
MCU_EXT_REFCLK0  
MCU_GPIO0_6  
MCU_SPI1_D0  
MCU_GPIO0_8  
MCU_SPI1_D1  
MCU_GPIO0_9  
IO  
IO  
IO  
IO  
IO  
IO  
O
pad  
0
MCU_SPI1_CLK  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
pad  
1
MCU_SPI0_CS0  
MCU_SPI0_CS1  
pad  
1
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
pad  
0
E7  
B6  
A7  
B7  
MCU_SPI0_D0  
MCU_SPI0_D1  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
pad  
0
pad  
1
pad  
1
0
IO  
IO  
IO  
IO  
IO  
pad  
0
C7  
C8  
MCU_SPI1_D0  
MCU_SPI1_D1  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
pad  
0
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
D8  
MCU_UART0_CTSn  
MCU_UART0_CTSn  
0
1
2
7
0
1
2
7
0
7
0
7
0
1
2
7
0
1
2
7
0
7
0
7
I
1
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
MCU_TIMER_IO0  
MCU_SPI0_CS2  
MCU_GPIO0_1  
IO  
IO  
IO  
O
0
1
pad  
E8  
MCU_UART0_RTSn  
MCU_UART0_RTSn  
MCU_TIMER_IO1  
MCU_SPI1_CS2  
MCU_GPIO0_0  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
I
0
1
pad  
1
A9  
A8  
B8  
MCU_UART0_RXD  
MCU_UART0_TXD  
MCU_UART1_CTSn  
MCU_UART0_RXD  
MCU_GPIO0_3  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
IO  
O
pad  
MCU_UART0_TXD  
MCU_GPIO0_2  
IO  
I
pad  
1
MCU_UART1_CTSn  
MCU_TIMER_IO2  
MCU_SPI0_CS3  
MCU_GPIO0_16  
MCU_UART1_RTSn  
MCU_TIMER_IO3  
MCU_SPI1_CS3  
MCU_GPIO0_17  
MCU_UART1_RXD  
MCU_GPIO0_14  
MCU_UART1_TXD  
MCU_GPIO0_15  
IO  
IO  
IO  
O
0
1
pad  
B9  
MCU_UART1_RTSn  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
I
0
1
pad  
1
C9  
D9  
MCU_UART1_RXD  
MCU_UART1_TXD  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
IO  
O
pad  
IO  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
F18  
G18  
J21  
G19  
L20  
MMC0_CALPAD  
MMC0_CALPAD  
A
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
SDIO  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
MMC0_CLK  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
IO  
IO  
IO  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
MMC0_CMD  
MMC0_DS  
MMC1_CLK  
1
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
MMC1_CLK  
UART2_CTSn  
TIMER_IO4  
UART4_RXD  
GPIO1_75  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
IO  
I
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV5  
VDDSHV5  
VDDSHV0  
Yes  
Yes  
Yes  
1
IO  
I
0
1
IO  
IO  
O
IO  
O
IO  
I
pad  
1
J19  
MMC1_CMD  
MMC1_CMD  
UART2_RTSn  
TIMER_IO5  
UART4_TXD  
GPIO1_76  
1.8 V/3.3 V  
SDIO  
PU/PD  
0
pad  
1
D19  
MMC1_SDCD  
MMC1_SDCD  
UART3_CTSn  
TIMER_IO6  
UART5_RXD  
GPIO1_77  
1.8 V/3.3 V  
LVCMOS  
PU/PD  
I
1
IO  
I
0
1
IO  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
C20  
MMC1_SDWP  
MMC1_SDWP  
0
1
2
3
7
I
1
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
UART3_RTSn  
TIMER_IO7  
UART5_TXD  
GPIO1_78  
O
IO  
O
0
IO  
IO  
pad  
1
K20  
J20  
J18  
J17  
H17  
H19  
H18  
G17  
K21  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
MMC1_DAT0  
MMC0_DAT0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
SDIO  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1
1
1
1
1
1
1
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
1.8 V  
VDDS_MMC0, VDD_MMC0,  
VDD_DLL_MMC0  
MMC1_DAT0  
0
1
2
3
7
IO  
I
1
0
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV5  
Yes  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO3  
IO  
O
IO  
UART3_TXD  
GPIO1_74  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
L21  
K19  
K18  
MMC1_DAT1  
MMC1_DAT1  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
7
0
7
0
7
0
7
0
7
IO  
1
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV5  
VDDSHV5  
VDDSHV5  
Yes  
SDIO  
PU/PD  
PU/PD  
PU/PD  
CP_GEMAC_CPTS0_HW1TSPUSH  
TIMER_IO2  
I
0
IO  
I
0
UART3_RXD  
1
GPIO1_73  
IO  
IO  
O
pad  
1
MMC1_DAT2  
MMC1_DAT2  
CP_GEMAC_CPTS0_TS_SYNC  
TIMER_IO1  
Yes  
SDIO  
IO  
O
0
UART2_TXD  
GPIO1_72  
IO  
IO  
O
pad  
1
MMC1_DAT3  
MMC1_DAT3  
CP_GEMAC_CPTS0_TS_COMP  
TIMER_IO0  
Yes  
SDIO  
IO  
I
0
UART2_RXD  
1
GPIO1_71  
IO  
O
pad  
N20  
N19  
N21  
L19  
L18  
OSPI0_CLK  
OSPI0_CLK  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
GPIO0_0  
IO  
I
pad  
0
OSPI0_DQS  
OSPI0_LBCLKO  
OSPI0_CSn0  
OSPI0_CSn1  
OSPI0_DQS  
GPIO0_2  
IO  
IO  
IO  
O
pad  
0
OSPI0_LBCLKO  
GPIO0_1  
pad  
OSPI0_CSn0  
GPIO0_11  
IO  
O
pad  
pad  
OSPI0_CSn1  
GPIO0_12  
IO  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
K17  
L17  
OSPI0_CSn2  
OSPI0_CSn3  
OSPI0_CSn2  
0
2
7
0
1
2
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
OSPI0_RESET_OUT1  
GPIO0_13  
O
IO  
O
pad  
OSPI0_CSn3  
OSPI0_RESET_OUT0  
OSPI0_ECC_FAIL  
GPIO0_14  
Off / Off / Off  
Off / Off / Off  
Yes  
O
I
1
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
pad  
0
M19  
M18  
M20  
M21  
P21  
P20  
N18  
M17  
E17  
OSPI0_D0  
OSPI0_D1  
OSPI0_D2  
OSPI0_D3  
OSPI0_D4  
OSPI0_D5  
OSPI0_D6  
OSPI0_D7  
PORz_OUT  
OSPI0_D0  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Low / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / SS / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV0  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
GPIO0_3  
pad  
0
OSPI0_D1  
GPIO0_4  
pad  
0
OSPI0_D2  
GPIO0_5  
pad  
0
OSPI0_D3  
GPIO0_6  
pad  
0
OSPI0_D4  
GPIO0_7  
pad  
0
OSPI0_D5  
GPIO0_8  
pad  
0
OSPI0_D6  
GPIO0_9  
pad  
0
OSPI0_D7  
GPIO0_10  
pad  
PORz_OUT  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
P3  
P2  
Y1  
PRG0_MDIO0_MDC  
PRG0_MDIO0_MDIO  
PRG0_PRU0_GPO0  
PRG0_MDIO0_MDC  
0
7
9
0
7
9
0
1
2
3
7
O
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
GPIO1_41  
IO  
OZ  
IO  
IO  
OZ  
IO  
I
pad  
GPMC0_A13  
PRG0_MDIO0_MDIO  
GPIO1_40  
0
Yes  
Yes  
LVCMOS  
LVCMOS  
pad  
GPMC0_A12  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPI0  
PRG0_RGMII1_RD0  
PRG0_PWM3_A0  
GPIO1_0  
0
0
I
0
IO  
IO  
I
0
pad  
1
UART2_CTSn  
10  
0
R4  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPI1  
PRG0_RGMII1_RD1  
PRG0_PWM3_B0  
GPIO1_1  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
0
3
IO  
IO  
O
IO  
I
1
7
pad  
UART2_TXD  
10  
0
U2  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPI2  
PRG0_RGMII1_RD2  
PRG0_PWM2_A0  
GPIO1_2  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
0
3
IO  
IO  
OZ  
O
0
7
pad  
GPMC0_A0  
9
UART2_RTSn  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V2  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO3  
0
1
2
3
7
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU0_GPI3  
PRG0_RGMII1_RD3  
PRG0_PWM3_A2  
GPIO1_3  
I
0
I
0
IO  
IO  
I
0
pad  
1
UART3_CTSn  
10  
0
AA2  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPI4  
PRG0_RGMII1_RX_CTL  
PRG0_PWM2_B0  
GPIO1_4  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
0
3
IO  
IO  
OZ  
O
IO  
I
1
7
pad  
GPMC0_A1  
9
UART3_TXD  
10  
0
R3  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPI5  
PRG0_PWM3_B2  
GPIO1_5  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
3
IO  
IO  
O
IO  
I
1
7
pad  
UART3_RTSn  
10  
0
T3  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPI6  
PRG0_RGMII1_RXC  
PRG0_PWM3_A1  
GPIO1_6  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
0
3
IO  
IO  
I
0
7
pad  
1
UART4_CTSn  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
T1  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO7  
0
1
2
3
4
5
6
7
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU0_GPI7  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_PWM3_B1  
CPTS0_HW2TSPUSH  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO6  
I
0
I
0
IO  
I
1
0
I
0
IO  
IO  
O
IO  
I
0
GPIO1_7  
pad  
UART4_TXD  
10  
0
T2  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPI8  
PRG0_PWM2_A1  
GPIO1_8  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
3
IO  
IO  
OZ  
O
IO  
I
0
7
pad  
GPMC0_A2  
9
UART4_RTSn  
10  
0
W6  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPI9  
PRG0_UART0_CTSn  
PRG0_PWM3_TZ_IN  
RGMII1_RX_CTL  
RMII1_RX_ER  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
1
3
I
0
4
I
0
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT28  
GPIO1_9  
6
IO  
IO  
I
0
7
pad  
1
UART2_RXD  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
AA5  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO10  
0
1
2
3
4
5
6
7
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU0_GPI10  
PRG0_UART0_RTSn  
PRG0_PWM2_B1  
RGMII1_RXC  
I
0
O
IO  
I
1
0
RMII_REF_CLK  
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT29  
GPIO1_10  
IO  
IO  
I
0
pad  
1
UART3_RXD  
10  
0
Y3  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPI11  
PRG0_RGMII1_TD0  
PRG0_PWM3_TZ_OUT  
GPIO1_11  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
O
O
IO  
I
3
7
pad  
1
UART4_RXD  
10  
0
AA3  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPI12  
PRG0_RGMII1_TD1  
PRG0_PWM0_A0  
GPIO1_12  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
O
IO  
IO  
OZ  
3
0
7
pad  
GPMC0_A14  
9
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
R6  
V4  
T5  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO13  
0
1
2
3
6
7
9
0
1
2
3
6
7
9
0
1
2
3
6
7
9
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG0_PRU0_GPI13  
PRG0_RGMII1_TD2  
PRG0_PWM0_B0  
SPI3_D0  
I
0
O
IO  
IO  
IO  
OZ  
IO  
I
1
0
GPIO1_13  
pad  
GPMC0_A15  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPI14  
PRG0_RGMII1_TD3  
PRG0_PWM0_A1  
SPI3_D1  
0
0
Yes  
LVCMOS  
O
IO  
IO  
IO  
OZ  
IO  
I
0
0
GPIO1_14  
pad  
GPMC0_A3  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPI15  
PRG0_RGMII1_TX_CTL  
PRG0_PWM0_B1  
SPI3_CS1  
0
0
Yes  
LVCMOS  
O
IO  
IO  
IO  
OZ  
1
1
GPIO1_15  
pad  
GPMC0_A16  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U4  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO16  
0
1
2
3
6
7
9
0
1
2
3
4
5
6
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU0_GPI16  
PRG0_RGMII1_TXC  
PRG0_PWM0_A2  
SPI3_CLK  
I
0
IO  
IO  
IO  
IO  
OZ  
IO  
I
0
0
0
GPIO1_16  
pad  
GPMC0_A4  
U1  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPI17  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_PWM0_B2  
CPTS0_TS_SYNC  
CP_GEMAC_CPTS0_TS_SYNC  
SPI3_CS0  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
1
O
IO  
IO  
IO  
OZ  
1
GPIO1_17  
pad  
0
TIMER_IO11  
GPMC0_A17  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V1  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO18  
0
1
2
3
4
5
6
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU0_GPI18  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
CP_GEMAC_CPTS0_HW1TSPUSH  
EHRPWM8_A  
I
0
I
0
I
0
I
0
I
0
IO  
IO  
I
0
GPIO1_18  
pad  
1
UART4_CTSn  
GPMC0_A5  
OZ  
I
UART2_RXD  
10  
0
1
0
0
W1  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPI19  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_PWM0_TZ_OUT  
CPTS0_TS_COMP  
CP_GEMAC_CPTS0_TS_COMP  
EHRPWM8_B  
IO  
I
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
2
O
O
O
O
IO  
IO  
O
OZ  
I
3
4
5
6
0
GPIO1_19  
7
pad  
UART4_RTSn  
8
GPMC0_A6  
9
UART3_RXD  
10  
1
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y2  
W2  
V3  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO0  
0
1
2
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG0_PRU1_GPI0  
PRG0_RGMII2_RD0  
GPIO1_20  
I
0
I
0
IO  
I
pad  
0
EQEP0_A  
UART5_CTSn  
10  
0
I
1
PRG0_PRU1_GPO1  
PRG0_PRU1_GPI1  
PRG0_RGMII2_RD1  
GPIO1_21  
IO  
I
0
Yes  
1
0
2
I
0
7
IO  
I
pad  
0
EQEP0_B  
8
UART5_TXD  
10  
0
O
IO  
I
PRG0_PRU1_GPO2  
PRG0_PRU1_GPI2  
PRG0_RGMII2_RD2  
PRG0_PWM2_A2  
GPIO1_22  
0
Yes  
1
0
2
I
0
3
IO  
IO  
IO  
O
0
7
pad  
0
EQEP0_S  
8
UART5_RTSn  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
T4  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO3  
0
1
2
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG0_PRU1_GPI3  
PRG0_RGMII2_RD3  
GPIO1_23  
I
0
I
0
IO  
I
pad  
0
EQEP1_A  
GPMC0_A18  
OZ  
I
UART6_CTSn  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPI4  
PRG0_RGMII2_RX_CTL  
PRG0_PWM2_B2  
GPIO1_24  
10  
0
1
W3  
IO  
I
0
Yes  
LVCMOS  
1
0
2
I
0
3
IO  
IO  
I
1
7
pad  
0
EQEP1_B  
8
UART6_TXD  
10  
0
O
IO  
I
P4  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPI5  
GPIO1_25  
0
Yes  
LVCMOS  
1
0
7
IO  
IO  
O
pad  
0
EQEP1_S  
8
UART6_RTSn  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
R5  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO6  
0
1
2
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU1_GPI6  
PRG0_RGMII2_RXC  
GPIO1_26  
I
0
I
0
IO  
I
pad  
0
EQEP2_A  
GPMC0_A19  
OZ  
I
UART4_CTSn  
10  
0
1
W5  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPI7  
PRG0_IEP1_EDC_LATCH_IN1  
RGMII1_RD0  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
I
0
4
I
0
RMII1_RXD0  
5
I
0
GPIO1_27  
7
IO  
I
pad  
0
EQEP2_B  
8
UART4_TXD  
10  
0
O
IO  
I
R1  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPI8  
PRG0_PWM2_TZ_OUT  
GPIO1_28  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
3
O
IO  
IO  
O
7
pad  
0
EQEP2_S  
8
UART4_RTSn  
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y5  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO9  
0
1
2
4
5
6
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU1_GPI9  
PRG0_UART0_RXD  
RGMII1_RD1  
I
0
I
1
I
0
RMII1_RXD1  
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT30  
GPIO1_29  
IO  
IO  
IO  
I
0
pad  
0
EQEP0_I  
UART5_RXD  
10  
0
1
V6  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPI10  
PRG0_UART0_TXD  
PRG0_PWM2_TZ_IN  
RGMII1_RD2  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
O
I
3
0
0
4
I
RMII1_TXD0  
5
O
IO  
IO  
IO  
I
PRG0_IEP0_EDIO_DATA_IN_OUT31  
GPIO1_30  
6
0
7
pad  
0
EQEP1_I  
8
UART6_RXD  
10  
0
1
W4  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPI11  
PRG0_RGMII2_TD0  
GPIO1_31  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
2
O
IO  
IO  
I
7
pad  
0
EQEP2_I  
8
UART4_RXD  
10  
1
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y4  
T6  
U6  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO12  
0
1
2
3
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG0_PRU1_GPI12  
PRG0_RGMII2_TD1  
PRG0_PWM1_A0  
GPIO1_32  
I
0
O
IO  
IO  
I
0
pad  
0
EQEP2_B  
GPMC0_A7  
OZ  
O
IO  
I
UART4_TXD  
10  
0
PRG0_PRU1_GPO13  
PRG0_PRU1_GPI13  
PRG0_RGMII2_TD2  
PRG0_PWM1_B0  
GPIO1_33  
0
0
Yes  
1
2
O
IO  
IO  
IO  
OZ  
I
3
1
7
pad  
0
EQEP0_I  
8
GPMC0_A8  
9
UART5_RXD  
10  
0
1
0
0
PRG0_PRU1_GPO14  
PRG0_PRU1_GPI14  
PRG0_RGMII2_TD3  
PRG0_PWM1_A1  
GPIO1_34  
IO  
I
Yes  
1
2
O
IO  
IO  
IO  
OZ  
I
3
0
7
pad  
0
EQEP1_I  
8
GPMC0_A9  
9
UART6_RXD  
10  
1
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U5  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO15  
0
1
2
3
7
9
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG0_PRU1_GPI15  
PRG0_RGMII2_TX_CTL  
PRG0_PWM1_B1  
I
0
O
IO  
IO  
OZ  
IO  
IO  
I
1
GPIO1_35  
pad  
GPMC0_A10  
PRG0_ECAP0_IN_APWM_OUT  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPI16  
PRG0_RGMII2_TXC  
PRG0_PWM1_A2  
10  
0
0
AA4  
0
Yes  
LVCMOS  
1
0
2
IO  
IO  
IO  
OZ  
O
IO  
I
0
3
0
GPIO1_36  
7
pad  
GPMC0_A11  
9
PRG0_ECAP0_SYNC_OUT  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPI17  
PRG0_IEP1_EDC_SYNC_OUT1  
PRG0_PWM1_B2  
10  
0
V5  
0
0
Yes  
LVCMOS  
1
2
O
IO  
I
3
1
0
RGMII1_RD3  
4
RMII1_TXD1  
5
O
IO  
O
I
GPIO1_37  
7
pad  
0
PRG0_ECAP0_SYNC_OUT  
PRG0_ECAP0_SYNC_IN  
8
10  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
P5  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO18  
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
4
7
0
4
7
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_PRU1_GPI18  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_PWM1_TZ_IN  
MDIO0_MDIO  
I
0
0
0
0
I
I
IO  
O
IO  
IO  
I
RMII1_TX_EN  
EHRPWM7_A  
0
GPIO1_38  
pad  
0
PRG0_ECAP0_SYNC_IN  
PRG0_PRU1_GPO19  
PRG0_PRU1_GPI19  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_PWM1_TZ_OUT  
MDIO0_MDC  
R2  
PRG0_PRU1_GPO19  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0
O
O
O
I
RMII1_CRS_DV  
0
EHRPWM7_B  
IO  
IO  
IO  
O
O
IO  
IO  
IO  
IO  
0
GPIO1_39  
pad  
0
PRG0_ECAP0_IN_APWM_OUT  
PRG1_MDIO0_MDC  
MDIO0_MDC  
Y6  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO0_86  
pad  
0
AA6  
PRG1_MDIO0_MDIO  
MDIO0_MDIO  
Off / Off / Off  
Off / Off / Off  
0
GPIO0_85  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y7  
U8  
W8  
V8  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO0  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PRG1_PRU0_GPI0  
PRG1_RGMII1_RD0  
PRG1_PWM3_A0  
GPIO0_45  
I
0
I
0
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD16  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPI1  
PRG1_RGMII1_RD1  
PRG1_PWM3_B0  
GPIO0_46  
0
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
0
I
0
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD17  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPI2  
PRG1_RGMII1_RD2  
PRG1_PWM2_A0  
GPIO0_47  
0
0
I
0
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD18  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPI3  
PRG1_RGMII1_RD3  
PRG1_PWM3_A2  
GPIO0_48  
0
0
I
0
IO  
IO  
IO  
0
pad  
0
GPMC0_AD19  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y8  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO4  
0
1
2
3
7
8
0
1
3
4
7
8
0
1
2
3
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG1_PRU0_GPI4  
PRG1_RGMII1_RX_CTL  
PRG1_PWM2_B0  
GPIO0_49  
I
0
I
0
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD20  
V13  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPI5  
PRG1_PWM3_B2  
RGMII1_RX_CTL  
GPIO0_50  
0
Yes  
0
IO  
I
1
0
IO  
IO  
IO  
I
pad  
0
GPMC0_AD21  
AA7  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPI6  
PRG1_RGMII1_RXC  
PRG1_PWM3_A1  
GPIO0_51  
0
Yes  
0
I
0
IO  
IO  
IO  
0
pad  
0
GPMC0_AD22  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U13  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO7  
0
1
2
3
4
5
6
7
8
0
1
3
4
7
8
0
1
2
3
4
5
6
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU0_GPI7  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_PWM3_B1  
CPTS0_HW2TSPUSH  
CLKOUT0  
I
0
0
1
0
I
IO  
I
O
IO  
IO  
IO  
IO  
I
TIMER_IO10  
0
GPIO0_52  
pad  
0
GPMC0_AD23  
W13  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPI8  
PRG1_PWM2_A1  
RGMII1_RXC  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
IO  
I
0
0
GPIO0_53  
IO  
IO  
IO  
I
pad  
0
GPMC0_AD24  
U15  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPI9  
PRG1_UART0_CTSn  
PRG1_PWM3_TZ_IN  
RGMII1_TX_CTL  
RMII1_RX_ER  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
I
1
I
0
O
I
0
PRG1_IEP0_EDIO_DATA_IN_OUT28  
GPIO0_54  
IO  
IO  
IO  
0
pad  
0
GPMC0_AD25  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U14  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU0_GPI10  
PRG1_UART0_RTSn  
PRG1_PWM2_B1  
RGMII1_TXC  
I
0
O
IO  
IO  
I
1
0
RMII_REF_CLK  
0
PRG1_IEP0_EDIO_DATA_IN_OUT29  
GPIO0_55  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD26  
AA8  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPI11  
PRG1_RGMII1_TD0  
PRG1_PWM3_TZ_OUT  
GPIO0_56  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
O
O
IO  
IO  
IO  
I
pad  
0
GPMC0_AD27  
U9  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPI12  
PRG1_RGMII1_TD1  
PRG1_PWM0_A0  
GPIO0_57  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
O
IO  
IO  
IO  
0
pad  
0
GPMC0_AD28  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
W9  
AA9  
Y9  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO13  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PRG1_PRU0_GPI13  
PRG1_RGMII1_TD2  
PRG1_PWM0_B0  
GPIO0_58  
I
0
O
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD29  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPI14  
PRG1_RGMII1_TD3  
PRG1_PWM0_A1  
GPIO0_59  
0
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
0
O
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD30  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPI15  
PRG1_RGMII1_TX_CTL  
PRG1_PWM0_B1  
GPIO0_60  
0
0
O
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD31  
V9  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPI16  
PRG1_RGMII1_TXC  
PRG1_PWM0_A2  
GPIO0_61  
0
0
IO  
IO  
IO  
O
0
0
pad  
GPMC0_BE2n  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U7  
V7  
W7  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU0_GPO17  
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG1_PRU0_GPI17  
PRG1_IEP0_EDC_SYNC_OUT1  
PRG1_PWM0_B2  
CPTS0_TS_SYNC  
TIMER_IO7  
I
0
O
IO  
O
IO  
IO  
OZ  
IO  
I
1
0
GPIO0_62  
pad  
GPMC0_A0  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPI18  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
TIMER_IO8  
0
Yes  
0
I
0
I
0
I
0
IO  
IO  
OZ  
IO  
I
0
GPIO0_63  
pad  
GPMC0_A1  
PRG1_PRU0_GPO19  
PRG1_PRU0_GPI19  
PRG1_IEP0_EDC_SYNC_OUT0  
PRG1_PWM0_TZ_OUT  
CPTS0_TS_COMP  
TIMER_IO9  
0
0
Yes  
O
O
O
IO  
IO  
OZ  
0
GPIO0_64  
pad  
GPMC0_A2  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
W11  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO0  
0
1
2
4
5
7
8
0
1
2
4
5
7
8
0
1
2
3
4
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PRG1_PRU1_GPI0  
PRG1_RGMII2_RD0  
RGMII2_RD0  
I
0
I
0
I
0
RMII2_RXD0  
I
0
GPIO0_65  
IO  
OZ  
IO  
I
pad  
GPMC0_A3  
V11  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPI1  
PRG1_RGMII2_RD1  
RGMII2_RD1  
0
Yes  
LVCMOS  
0
I
0
I
0
RMII2_RXD1  
I
0
GPIO0_66  
IO  
OZ  
IO  
I
pad  
GPMC0_A4  
AA12  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPI2  
PRG1_RGMII2_RD2  
PRG1_PWM2_A2  
RGMII2_RD2  
0
Yes  
LVCMOS  
0
I
0
IO  
I
0
0
GPIO0_67  
IO  
OZ  
pad  
GPMC0_A5  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y12  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO3  
0
1
2
4
7
8
0
1
2
3
4
5
7
8
0
1
4
7
8
0
1
2
4
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI3  
PRG1_RGMII2_RD3  
RGMII2_RD3  
I
0
I
0
I
0
GPIO0_68  
IO  
OZ  
IO  
I
pad  
GPMC0_A6  
W12  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPI4  
PRG1_RGMII2_RX_CTL  
PRG1_PWM2_B2  
RGMII2_RX_CTL  
RMII2_RX_ER  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
I
0
IO  
I
1
0
I
0
GPIO0_69  
IO  
OZ  
IO  
I
pad  
GPMC0_A7  
AA13  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPI5  
RGMII1_RD0  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
I
0
GPIO0_70  
IO  
OZ  
IO  
I
pad  
GPMC0_A8  
U11  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPI6  
PRG1_RGMII2_RXC  
RGMII2_RXC  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
I
0
I
0
GPIO0_71  
IO  
OZ  
pad  
GPMC0_A9  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V15  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO7  
0
1
2
4
5
6
7
8
0
1
3
4
7
8
0
1
2
4
5
6
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI7  
PRG1_IEP1_EDC_LATCH_IN1  
RGMII1_TD0  
I
0
0
I
O
I
RMII1_RXD0  
0
SPI3_CS3  
IO  
IO  
OZ  
IO  
I
1
GPIO0_72  
pad  
GPMC0_A10  
U12  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPI8  
PRG1_PWM2_TZ_OUT  
RGMII1_RD1  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
I
0
GPIO0_73  
IO  
OZ  
IO  
I
pad  
GPMC0_A11  
V14  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPI9  
PRG1_UART0_RXD  
RGMII1_TD1  
0
0
1
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
I
O
I
RMII1_RXD1  
0
PRG1_IEP0_EDIO_DATA_IN_OUT30  
GPIO0_74  
IO  
IO  
OZ  
0
pad  
GPMC0_A12  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
W14  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
4
5
7
8
0
1
2
3
4
5
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI10  
PRG1_UART0_TXD  
PRG1_PWM2_TZ_IN  
RGMII1_TD2  
I
0
O
I
0
O
O
IO  
IO  
OZ  
IO  
I
RMII1_TXD0  
PRG1_IEP0_EDIO_DATA_IN_OUT31  
GPIO0_75  
0
pad  
GPMC0_A13  
AA10  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPI11  
PRG1_RGMII2_TD0  
RGMII2_TD0  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
O
O
IO  
OZ  
IO  
I
RMII2_TXD0  
GPIO0_76  
pad  
GPMC0_A14  
V10  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPI12  
PRG1_RGMII2_TD1  
PRG1_PWM1_A0  
RGMII2_TD1  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
O
IO  
OZ  
0
RMII2_TXD1  
GPIO0_77  
pad  
GPMC0_A15  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
U10  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO13  
0
1
2
3
4
5
7
8
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI13  
PRG1_RGMII2_TD2  
PRG1_PWM1_B0  
RGMII2_TD2  
I
0
O
IO  
O
1
RMII2_CRS_DV  
GPIO0_78  
I
0
IO  
OZ  
IO  
I
pad  
GPMC0_A16  
AA11  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPI14  
PRG1_RGMII2_TD3  
PRG1_PWM1_A1  
RGMII2_TD3  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
0
GPIO0_79  
IO  
OZ  
IO  
I
pad  
GPMC0_A17  
Y11  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPI15  
PRG1_RGMII2_TX_CTL  
PRG1_PWM1_B1  
RGMII2_TX_CTL  
RMII2_TX_EN  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
1
O
GPIO0_80  
IO  
OZ  
pad  
GPMC0_A18  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y10  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO16  
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
7
8
9
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI16  
PRG1_RGMII2_TXC  
PRG1_PWM1_A2  
RGMII2_TXC  
I
0
IO  
IO  
IO  
IO  
OZ  
IO  
I
0
0
0
GPIO0_81  
pad  
GPMC0_A19  
AA14  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPI17  
PRG1_IEP1_EDC_SYNC_OUT1  
PRG1_PWM1_B2  
RGMII1_TD3  
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
O
IO  
O
O
IO  
O
O
IO  
I
1
RMII1_TXD1  
GPIO0_19  
pad  
GPMC0_BE3n  
PRG1_ECAP0_SYNC_OUT  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPI18  
PRG1_IEP1_EDC_LATCH_IN0  
PRG1_PWM1_TZ_IN  
RGMII1_RD2  
Y13  
PRG1_PRU1_GPO18  
0
0
0
0
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
I
I
I
RMII1_TX_EN  
O
IO  
I
GPIO0_20  
pad  
1
UART5_CTSn  
PRG1_ECAP0_SYNC_IN  
I
0
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
V12  
PRG1_PRU1_GPO19  
PRG1_PRU1_GPO19  
0
1
2
3
4
5
6
7
8
9
0
0
IO  
0
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
0
0
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
PRG1_PRU1_GPI19  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_PWM1_TZ_OUT  
RGMII1_RD3  
I
0
O
O
I
0
RMII1_CRS_DV  
I
0
SPI3_CS2  
IO  
IO  
O
IO  
O
I
1
GPIO0_84  
pad  
UART5_RTSn  
PRG1_ECAP0_IN_APWM_OUT  
RESETSTATz  
0
F16  
E18  
T13  
RESETSTATz  
Off / Low / Off  
On / Off / Up  
Off / SS / Off  
On / Off / Up  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
SERDES  
PU/PD  
PU/PD  
RESET_REQz  
SERDES0_REXT  
RESET_REQz  
SERDES0_REXT  
A
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
W16  
W17  
Y15  
Y16  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
IO  
IO  
I
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
SERDES  
SERDES  
SERDES  
SERDES  
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
SERDES0_RX0_P  
SERDES0_RX0_P  
I
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
AA16  
AA17  
SERDES0_TX0_N  
SERDES0_TX0_P  
SERDES0_TX0_N  
O
1.8 V  
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
SERDES  
SERDES  
SERDES0_TX0_P  
O
1.8 V  
VDDA_1P8_SERDES0,  
VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C  
D13  
C14  
SPI0_CLK  
SPI1_CLK  
SPI0_CLK  
0
7
0
3
7
0
7
0
1
2
3
4
5
6
7
0
7
0
7
IO  
IO  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO1_44  
pad  
0
SPI1_CLK  
VDDSHV0  
EHRPWM6_SYNCI  
GPIO1_49  
0
IO  
IO  
IO  
IO  
O
pad  
1
D12  
C13  
SPI0_CS0  
SPI0_CS1  
SPI0_CS0  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO1_42  
pad  
1
SPI0_CS1  
CPTS0_TS_COMP  
I2C2_SCL  
IOD  
IO  
O
1
0
TIMER_IO10  
PRG0_IEP0_EDIO_OUTVALID  
UART6_RXD  
ADC_EXT_TRIGGER0  
GPIO1_43  
I
1
I
0
IO  
IO  
IO  
IO  
IO  
pad  
0
A13  
A14  
SPI0_D0  
SPI0_D1  
SPI0_D0  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO1_45  
pad  
0
SPI0_D1  
GPIO1_46  
pad  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
B14  
D14  
SPI1_CS0  
SPI1_CS0  
EHRPWM6_A  
GPIO1_47  
SPI1_CS1  
0
3
7
0
1
2
4
5
6
7
8
0
3
7
0
3
7
0
0
0
0
0
IO  
1
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
PU/PD  
IO  
IO  
IO  
O
0
pad  
1
SPI1_CS1  
Off / Off / Off  
Off / Off / Off  
Yes  
LVCMOS  
CPTS0_TS_SYNC  
I2C2_SDA  
IOD  
O
1
PRG1_IEP0_EDIO_OUTVALID  
UART6_TXD  
ADC_EXT_TRIGGER1  
GPIO1_48  
O
I
0
IO  
IO  
IO  
O
pad  
0
TIMER_IO11  
SPI1_D0  
B15  
A15  
SPI1_D0  
SPI1_D1  
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
EHRPWM6_SYNCO  
GPIO1_50  
IO  
IO  
IO  
IO  
I
pad  
0
SPI1_D1  
Off / Off / Off  
Off / Off / Off  
EHRPWM6_B  
GPIO1_51  
0
pad  
B11  
C11  
A12  
C12  
D11  
TCK  
TDI  
TCK  
On / Off / Up  
On / Off / Up  
Off / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
Off / SS / Up  
On / Off / Up  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
TDI  
I
TDO  
TMS  
TRSTn  
TDO  
OZ  
I
TMS  
TRSTn  
I
On / Off / Down On / Off / Down  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
B16  
UART0_CTSn  
UART0_CTSn  
SPI0_CS2  
0
1
2
3
4
6
7
8
9
0
1
3
4
6
7
8
0
2
7
8
0
2
7
8
I
1
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
I
1
ADC_EXT_TRIGGER0  
UART2_RXD  
TIMER_IO6  
SPI4_CLK  
0
I
1
IO  
IO  
IO  
IO  
O
O
IO  
O
IO  
IO  
IO  
IO  
I
0
0
GPIO1_54  
pad  
0
EQEP0_S  
CP_GEMAC_CPTS0_TS_SYNC  
UART0_RTSn  
SPI0_CS3  
A16  
UART0_RTSn  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
1
UART2_TXD  
TIMER_IO7  
SPI4_D0  
0
0
GPIO1_55  
pad  
0
EQEP0_I  
D15  
UART0_RXD  
UART0_RXD  
SPI2_D0  
1
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
I
0
GPIO1_52  
pad  
0
EQEP0_A  
C16  
UART0_TXD  
UART0_TXD  
SPI2_D1  
O
IO  
IO  
I
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
0
GPIO1_53  
pad  
0
EQEP0_B  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
D16  
UART1_CTSn  
UART1_CTSn  
SPI1_CS2  
0
1
2
3
4
5
6
7
8
0
1
4
5
6
7
8
0
2
5
7
8
I
1
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
I
1
0
0
1
ADC_EXT_TRIGGER1  
PCIE0_CLKREQn  
UART3_RXD  
IO  
I
CP_GEMAC_CPTS0_TS_SYNC  
SPI4_D1  
O
IO  
IO  
IO  
O
IO  
O
I
0
GPIO1_58  
pad  
0
EQEP1_S  
E16  
UART1_RTSn  
UART1_RTSn  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
SPI1_CS3  
1
UART3_TXD  
CP_GEMAC_CPTS0_HW2TSPUSH  
SPI4_CS0  
0
IO  
IO  
IO  
I
1
GPIO1_59  
pad  
0
EQEP1_I  
E15  
UART1_RXD  
UART1_RXD  
1
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
SPI2_CS0  
IO  
O
IO  
I
1
CP_GEMAC_CPTS0_TS_COMP  
GPIO1_56  
pad  
0
EQEP1_A  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
E14  
UART1_TXD  
UART1_TXD  
SPI2_CLK  
0
2
5
7
8
O
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
I
0
CP_GEMAC_CPTS0_HW1TSPUSH  
0
GPIO1_57  
EQEP1_B  
USB0_DM  
IO  
I
pad  
0
AA20  
AA19  
USB0_DM  
USB0_DP  
IO  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
USB2PHY  
USB2PHY  
USB0_DP  
IO  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
E19  
U16  
USB0_DRVVBUS  
USB0_ID  
USB0_DRVVBUS  
GPIO1_79  
0
7
O
IO  
A
Off / Off / Down Off / Off / Down  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
pad  
USB0_ID  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
USB2PHY  
U17  
T14  
USB0_RCALIB  
USB0_VBUS  
USB0_RCALIB  
USB0_VBUS  
IO  
A
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
USB2PHY  
USB2PHY  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
P12, P13  
P11  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
PWR  
PWR  
PWR  
PWR  
PWR  
T12  
R14  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
R15  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
H15  
R13  
J13  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_3P3_SDIO  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDA_3P3_USB0  
VDDA_ADC  
VDDA_ADC  
VDDA_MCU  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
VDDA_TEMP0  
VDDA_TEMP1  
VDDR_CORE  
VDDSHV0  
K12  
N12  
H9  
VDDA_MCU  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
VDDA_TEMP0  
VDDA_TEMP1  
VDDR_CORE  
VDDSHV0  
J11  
G11  
L11  
L10, M13  
F11, G12,  
G14  
M7, N6, P7 VDDSHV1  
VDDSHV1  
VDDSHV2  
PWR  
PWR  
R10, R8,  
T9  
VDDSHV2  
P14, P15  
M14, M15  
L14, L15  
VDDSHV3  
VDDSHV3  
PWR  
PWR  
PWR  
PWR  
VDDSHV4  
VDDSHV4  
VDDSHV5  
VDDSHV5  
F9, G10,  
G8  
VDDSHV_MCU  
VDDSHV_MCU  
F7, G6, H7, VDDS_DDR  
J6, K7, L6  
VDDS_DDR  
PWR  
J8  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
PWR  
PWR  
PWR  
J15, K14  
H13  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
J10, J12,  
K11, K9,  
L12, L8,  
M11, M9,  
N10, N8,  
P9  
VDD_CORE  
VDD_CORE  
PWR  
H14  
K13  
K16  
E12  
F13  
F14  
K10  
G15  
VDD_DLL_MMC0  
VDD_MMC0  
VDD_DLL_MMC0  
VDD_MMC0  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
VPP  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
VPP  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
BALL NAME  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
UP/DOWN  
TYPE  
NUMBER  
MODE  
TYPE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
A1, A21,  
A5, A6,  
VSS  
VSS  
PWR  
AA1, AA15,  
AA18,  
AA21, C10,  
C15, C3,  
D1, E11,  
E13, F10,  
F15, F8,  
G1, G16,  
G3, G7,  
G9, H11,  
H20, H21,  
H6, H8,  
J14, J16,  
J7, J9, K6,  
K8, L1,  
L16, L3,  
L7, L9,  
M10, M12,  
M6, M8,  
N11, N13,  
N15, N7,  
N9, P1,  
P10, P18,  
P6, P8,  
R12, R7,  
R9, T10,  
T11, T15,  
T16, T8,  
U3, V17,  
W10, W18,  
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Table 6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
STATE  
STATE  
I/O  
PULL  
UP/DOWN  
TYPE  
BALL  
MUX  
MODE  
AFTER  
RESET  
BUFFER  
TYPE  
BALL NAME  
NUMBER  
SIGNAL NAME  
TYPE  
DSIS  
DURING  
RESET  
AFTER  
VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
RESET  
RX/TX/PULL  
RX/TX/PULL  
Y14, Y17,  
Y19  
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6.3 Pin Attributes (ALX Package)  
Table 6-2. Pin Attributes (ALX Package)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
TYPE VOLTAGE  
VALUE  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
H21  
ADC0_AIN0  
ADC0_AIN0  
GPIO1_80  
ADC0_AIN1  
GPIO1_81  
ADC0_AIN2  
GPIO1_82  
ADC0_AIN3  
GPIO1_83  
ADC0_AIN4  
GPIO1_84  
ADC0_AIN5  
GPIO1_85  
ADC0_AIN6  
GPIO1_86  
ADC0_AIN7  
GPIO1_87  
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
-
A
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
-
-
-
-
-
-
-
-
PADCONFIG_172  
PADCONFIG_173  
PADCONFIG_174  
PADCONFIG_175  
PADCONFIG_176  
PADCONFIG_177  
PADCONFIG_178  
PADCONFIG_179  
0x000F42B0  
0x000F42B4  
0x000F42B8  
0x000F42BC  
0x000F42C0  
0x000F42C4  
0x000F42C8  
0x000F42CC  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
I
F19  
F21  
F20  
H20  
E21  
G20  
E20  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
A
I
A
I
A
I
A
I
A
I
A
I
A
I
D12  
N5  
CAP_VDDS0  
CAP_VDDS0  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAP_VDDS1  
CAP_VDDS1  
-
-
U9  
CAP_VDDS2  
CAP_VDDS2  
-
-
R16  
N18  
M18  
J17  
D9  
CAP_VDDS3  
CAP_VDDS3  
-
-
CAP_VDDS4  
CAP_VDDS4  
-
-
CAP_VDDS5  
CAP_VDDS5  
-
-
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
-
-
-
POR_POK  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
MCU_PADCONFIG_3  
1
C5  
B3  
EMU0  
EMU1  
EMU0  
0
IO  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
PU/PD  
0x0408407C  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
0
0
EMU1  
0
IO  
O
I
PU/PD MCU_PADCONFIG_3 0x04084080  
2
MCU_OBSCLK0  
EXT_REFCLK1  
SYNC1_OUT  
SPI2_CS3  
15  
A18  
EXT_REFCLK1  
0
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_157  
0x000F4274  
Off / Off / Off  
Off / Off / Off  
7
1
O
IO  
O
IO  
IO  
I
2
CLKOUT0  
5
GPIO1_69  
7
R21  
GPMC0_AD0  
GPMC0_AD0  
FSI_RX2_CLK  
UART2_RXD  
EHRPWM0_SYNCI  
TRC_CLK  
0
1.8 V/3.3 V  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_15  
0x000F403C  
On / Off / Off  
On / Off / Off  
7
1
2
I
3
I
6
O
IO  
I
GPIO0_15  
7
BOOTMODE00  
GPMC0_AD1  
FSI_RX2_D0  
UART2_TXD  
EHRPWM0_SYNCO  
TRC_CTL  
Bootstrap  
R20  
GPMC0_AD1  
0
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_16  
0x000F4040  
On / Off / Off  
On / Off / Off  
7
1
2
O
O
O
IO  
O
I
3
6
GPIO0_16  
7
9
PRG0_PWM2_TZ_OUT  
BOOTMODE01  
Bootstrap  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
T19  
V21  
U21  
GPMC0_AD2  
GPMC0_AD2  
0
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_17  
PU/PD PADCONFIG_18  
PU/PD PADCONFIG_19  
0x000F4044  
0x000F4048  
0x000F404C  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
FSI_RX2_D1  
UART2_RTSn  
EHRPWM_TZn_IN0  
TRC_DATA0  
1
2
O
I
3
6
O
IO  
I
GPIO0_17  
7
PRG0_PWM2_TZ_IN  
BOOTMODE02  
GPMC0_AD3  
FSI_RX3_CLK  
UART3_RXD  
EHRPWM0_A  
TRC_DATA1  
9
Bootstrap  
I
GPMC0_AD3  
0
IO  
I
VDDSHV3  
Yes  
1
2
I
3
IO  
O
IO  
IO  
I
6
GPIO0_18  
7
PRG0_PWM2_A0  
BOOTMODE03  
GPMC0_AD4  
FSI_RX3_D0  
UART3_TXD  
9
Bootstrap  
GPMC0_AD4  
0
IO  
I
VDDSHV3  
Yes  
1
2
O
IO  
O
IO  
IO  
I
EHRPWM0_B  
TRC_DATA2  
3
6
GPIO0_82  
7
9
PRG0_PWM2_B0  
BOOTMODE04  
Bootstrap  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
T20  
GPMC0_AD5  
GPMC0_AD5  
FSI_RX3_D1  
UART3_RTSn  
EHRPWM1_A  
TRC_DATA3  
0
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_20  
PU/PD PADCONFIG_21  
PU/PD PADCONFIG_22  
0x000F4050  
0x000F4054  
0x000F4058  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
1
2
O
IO  
O
IO  
IO  
I
3
6
GPIO0_83  
7
PRG0_PWM2_A1  
BOOTMODE05  
GPMC0_AD6  
FSI_RX4_D0  
UART4_RXD  
EHRPWM1_B  
TRC_DATA4  
9
Bootstrap  
T18  
GPMC0_AD6  
0
IO  
I
VDDSHV3  
Yes  
1
2
I
3
IO  
O
IO  
IO  
I
6
GPIO0_21  
7
PRG0_PWM2_B1  
BOOTMODE06  
GPMC0_AD7  
FSI_RX4_D1  
UART4_TXD  
EHRPWM_TZn_IN1  
EHRPWM8_A  
TRC_DATA5  
9
Bootstrap  
U19  
GPMC0_AD7  
0
IO  
I
VDDSHV3  
Yes  
1
2
O
I
3
4
IO  
O
IO  
IO  
I
6
GPIO0_22  
7
9
PRG1_PWM2_A2  
BOOTMODE07  
Bootstrap  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
U18  
U20  
V20  
GPMC0_AD8  
GPMC0_AD8  
0
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_23  
PU/PD PADCONFIG_24  
PU/PD PADCONFIG_25  
0x000F405C  
0x000F4060  
0x000F4064  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
FSI_RX0_CLK  
UART2_CTSn  
EHRPWM2_A  
TRC_DATA6  
1
2
I
3
IO  
O
IO  
IO  
I
6
GPIO0_23  
7
PRG0_PWM2_A2  
BOOTMODE08  
GPMC0_AD9  
FSI_RX0_D0  
UART3_CTSn  
EHRPWM2_B  
TRC_DATA7  
9
Bootstrap  
GPMC0_AD9  
0
IO  
I
VDDSHV3  
Yes  
1
2
I
3
IO  
O
IO  
IO  
I
6
GPIO0_24  
7
PRG0_PWM2_B2  
BOOTMODE09  
GPMC0_AD10  
FSI_RX0_D1  
UART4_CTSn  
EHRPWM_TZn_IN2  
EHRPWM8_B  
TRC_DATA8  
9
Bootstrap  
GPMC0_AD10  
0
IO  
I
VDDSHV3  
Yes  
1
2
I
3
I
4
IO  
O
IO  
IO  
I
6
GPIO0_25  
7
9
PRG1_PWM2_B2  
BOOTMODE10  
Bootstrap  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
W20  
GPMC0_AD11  
GPMC0_AD11  
FSI_RX1_CLK  
UART5_CTSn  
EQEP1_A  
0
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_26  
PU/PD PADCONFIG_27  
PU/PD PADCONFIG_28  
0x000F4068  
0x000F406C  
0x000F4070  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
1
2
I
3
I
TRC_DATA9  
GPIO0_26  
6
O
IO  
IO  
I
7
EHRPWM7_A  
BOOTMODE11  
GPMC0_AD12  
FSI_RX1_D0  
UART6_CTSn  
EQEP1_B  
8
Bootstrap  
Y20  
GPMC0_AD12  
0
IO  
I
VDDSHV3  
Yes  
1
2
I
3
I
TRC_DATA10  
GPIO0_27  
6
O
IO  
IO  
I
7
EHRPWM7_B  
BOOTMODE12  
GPMC0_AD13  
FSI_RX1_D1  
EHRPWM3_A  
TRC_DATA11  
GPIO0_28  
8
Bootstrap  
Y19  
GPMC0_AD13  
0
IO  
I
VDDSHV3  
Yes  
1
3
IO  
O
IO  
IO  
I
6
7
9
PRG0_PWM3_A0  
BOOTMODE13  
Bootstrap  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
On / Off / Off On / Off / Off 7  
Y18  
GPMC0_AD14  
GPMC0_AD14  
0
IO  
O
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_29  
0x000F4074  
FSI_TX0_D0  
UART6_RXD  
EHRPWM3_B  
TRC_DATA12  
GPIO0_29  
1
2
3
IO  
O
IO  
IO  
I
6
7
PRG0_PWM3_B0  
BOOTMODE14  
GPMC0_AD15  
FSI_TX0_D1  
UART6_TXD  
EHRPWM3_SYNCI  
TRC_DATA13  
GPIO0_30  
9
Bootstrap  
AA19 GPMC0_AD15  
0
IO  
O
O
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_30  
0x000F4078  
On / Off / Off  
On / Off / Off  
7
1
2
3
6
O
IO  
I
7
BOOTMODE15  
GPMC0_BE1n  
FSI_TX0_CLK  
EHRPWM5_A  
TRC_DATA19  
GPIO0_36  
Bootstrap  
P21  
GPMC0_BE1n  
0
1
3
6
7
9
0
4
7
O
O
IO  
O
IO  
IO  
IOD  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV3  
Yes  
PU/PD PADCONFIG_37  
0x000F4094  
Off / Off / Off  
Off / Off / Off  
7
PRG0_PWM3_A2  
I2C0_SCL  
B16  
I2C0_SCL  
1.8 V/3.3 V  
I2C OD FS  
VDDSHV0  
Yes  
-
PADCONFIG_152  
0x000F4260  
Off / Off / Off  
On / SS / Off  
0
UART6_CTSn  
GPIO1_64  
IO  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
B15  
I2C0_SDA  
I2C0_SDA  
0
4
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
6
7
8
9
IOD  
O
1.8 V/3.3 V  
1.8 V/3.3 V  
I2C OD FS  
LVCMOS  
VDDSHV0  
Yes  
-
PADCONFIG_153  
0x000F4264  
0x000F4268  
Off / Off / Off  
On / SS / Off  
0
UART6_RTSn  
GPIO1_65  
IO  
IOD  
I
A17  
B18  
A14  
I2C1_SCL  
I2C1_SDA  
MCAN0_RX  
I2C1_SCL  
VDDSHV0  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
Yes  
PU/PD PADCONFIG_154  
PU/PD PADCONFIG_155  
PU/PD PADCONFIG_149  
Off / Off / Off  
Off / Off / Off  
7
CPTS0_HW1TSPUSH  
TIMER_IO0  
SPI2_CS1  
IO  
IO  
IO  
IOD  
I
GPIO1_66  
I2C1_SDA  
1.8 V/3.3 V  
LVCMOS  
0x000F426C  
Off / Off / Off  
Off / Off / Off  
7
CPTS0_HW2TSPUSH  
TIMER_IO1  
SPI2_CS2  
IO  
IO  
IO  
I
GPIO1_67  
MCAN0_RX  
UART4_TXD  
TIMER_IO3  
SYNC3_OUT  
SPI4_CS2  
1.8 V/3.3 V  
LVCMOS  
0x000F4254  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
IO  
IO  
IO  
I
GPIO1_61  
EQEP2_S  
UART0_RIn  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
B13  
MCAN0_TX  
MCAN0_TX  
0
1
2
3
6
7
8
9
0
1
2
3
4
5
6
7
8
9
15  
O
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_148  
0x000F4250  
UART4_RXD  
TIMER_IO2  
SYNC2_OUT  
SPI4_CS1  
IO  
O
IO  
IO  
IO  
O
I
GPIO1_60  
EQEP2_I  
UART0_DTRn  
MCAN1_RX  
I2C3_SDA  
A15  
MCAN1_RX  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_151  
0x000F425C  
Off / Off / Off  
Off / Off / Off  
7
IOD  
IO  
O
IO  
O
O
IO  
I
ECAP2_IN_APWM_OUT  
OBSCLK0  
TIMER_IO5  
UART5_TXD  
EHRPWM_SOCB  
GPIO1_63  
EQEP2_B  
UART0_DSRn  
OBSCLK0  
I
O
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
B14  
MCAN1_TX  
MCAN1_TX  
0
1
2
3
4
5
6
7
8
9
-
O
IOD  
IO  
O
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_150  
0x000F4258  
Off / Off / Off  
Off / Off / Off  
7
I2C3_SCL  
ECAP1_IN_APWM_OUT  
SYSCLKOUT0  
TIMER_IO4  
UART5_RXD  
EHRPWM_SOCA  
GPIO1_62  
O
IO  
I
EQEP2_A  
UART0_DCDn  
MCU_OSC0_XI  
MCU_OSC0_XO  
I
D20  
C21  
MCU_OSC0_XI  
MCU_OSC0_XO  
I
1.8 V  
1.8 V  
HFOSC  
HFOSC  
VDDS_OSC  
VDDS_OSC  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
MCU_PADCONFIG_2  
3
C20  
A6  
MCU_PORz  
MCU_PORz  
0
I
1.8 V  
FS RESET  
LVCMOS  
VDDS_OSC  
Yes  
Yes  
-
0x0408405C  
-
-
-
MCU_RESETSTATz  
MCU_RESETSTATz  
MCU_GPIO0_22  
0
7
O
1.8 V/3.3 V  
VDDSHV_MCU  
PU/PD MCU_PADCONFIG_2 0x04084060  
4
Off / Low / Off  
Off / SS / Off  
0
IO  
MCU_PADCONFIG_2  
A5  
MCU_RESETz  
MCU_RESETz  
0
0
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV_MCU  
Yes  
PU/PD  
PU/PD  
0x04084058  
0x04084064  
On / Off / Up  
On / Off / Up  
0
2
MCU_PADCONFIG_2  
5
Off / Off /  
Down  
On / SS /  
Down  
B20  
D4  
MCU_SAFETY_ERRORn MCU_SAFETY_ERRORn  
IO  
1.8 V  
LVCMOS  
LVCMOS  
VDDS_OSC  
Yes  
Yes  
0
7
MCU_UART0_CTSn  
MCU_UART0_CTSn  
MCU_TIMER_IO0  
MCU_SPI0_CS2  
MCU_GPIO0_1  
0
1
2
7
I
1.8 V/3.3 V  
VDDSHV_MCU  
PU/PD MCU_PADCONFIG_1 0x04084030  
2
Off / Off / Off  
Off / Off / Off  
IO  
IO  
IO  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
C2  
MCU_UART0_RTSn  
MCU_UART0_RTSn  
0
1
2
7
0
7
0
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
O
IO  
IO  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV_MCU  
Yes  
PU/PD MCU_PADCONFIG_1 0x04084034  
3
Off / Off / Off  
Off / Off / Off  
7
MCU_TIMER_IO1  
MCU_SPI1_CS2  
MCU_GPIO0_0  
MCU_UART0_RXD  
MCU_GPIO0_3  
MCU_UART0_TXD  
MCU_GPIO0_2  
MMC1_CLK  
D6  
B2  
MCU_UART0_RXD  
MCU_UART0_TXD  
MMC1_CLK  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
SDIO  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV5  
Yes  
Yes  
Yes  
PU/PD MCU_PADCONFIG_1 0x04084028  
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
IO  
O
IO  
IO  
I
PU/PD MCU_PADCONFIG_1 0x0408402C  
1
J20  
PU/PD PADCONFIG_163  
PU/PD PADCONFIG_165  
PU/PD PADCONFIG_166  
0x000F428C  
0x000F4294  
0x000F4298  
UART2_CTSn  
TIMER_IO4  
IO  
I
UART4_RXD  
GPIO1_75  
IO  
IO  
O
IO  
O
IO  
I
J21  
MMC1_CMD  
MMC1_CMD  
UART2_RTSn  
TIMER_IO5  
1.8 V/3.3 V  
SDIO  
VDDSHV5  
Yes  
Off / Off / Off  
Off / Off / Off  
7
UART4_TXD  
GPIO1_76  
B17  
MMC1_SDCD  
MMC1_SDCD  
UART3_CTSn  
TIMER_IO6  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
Off / Off / Off  
Off / Off / Off  
7
I
IO  
I
UART5_RXD  
GPIO1_77  
IO  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
C16  
MMC1_SDWP  
MMC1_SDWP  
UART3_RTSn  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_167  
PU/PD PADCONFIG_162  
PU/PD PADCONFIG_161  
PU/PD PADCONFIG_160  
PU/PD PADCONFIG_159  
0x000F429C  
0x000F4288  
0x000F4284  
0x000F4280  
0x000F427C  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
O
IO  
O
IO  
IO  
I
TIMER_IO7  
UART5_TXD  
GPIO1_78  
J18  
J19  
K20  
K18  
MMC1_DAT0  
MMC1_DAT1  
MMC1_DAT2  
MMC1_DAT3  
MMC1_DAT0  
SDIO  
VDDSHV5  
VDDSHV5  
VDDSHV5  
VDDSHV5  
Yes  
Yes  
Yes  
Yes  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO3  
IO  
O
IO  
IO  
I
UART3_TXD  
GPIO1_74  
MMC1_DAT1  
SDIO  
CP_GEMAC_CPTS0_HW1TSPUSH  
TIMER_IO2  
IO  
I
UART3_RXD  
GPIO1_73  
IO  
IO  
O
IO  
O
IO  
IO  
O
IO  
I
MMC1_DAT2  
SDIO  
CP_GEMAC_CPTS0_TS_SYNC  
TIMER_IO1  
UART2_TXD  
GPIO1_72  
MMC1_DAT3  
SDIO  
CP_GEMAC_CPTS0_TS_COMP  
TIMER_IO0  
UART2_RXD  
GPIO1_71  
IO  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
P20  
P17  
M21  
L20  
M20  
L19  
N20  
L21  
N19  
OSPI0_CLK  
OSPI0_CLK  
GPIO0_0  
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
0
7
9
0
7
9
O
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
PU/PD PADCONFIG_0  
PU/PD PADCONFIG_2  
PU/PD PADCONFIG_1  
PU/PD PADCONFIG_11  
PU/PD PADCONFIG_12  
PU/PD PADCONFIG_3  
PU/PD PADCONFIG_4  
PU/PD PADCONFIG_5  
PU/PD PADCONFIG_6  
0x000F4000  
0x000F4008  
0x000F4004  
0x000F402C  
0x000F4030  
0x000F400C  
0x000F4010  
0x000F4014  
0x000F4018  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
7
7
OSPI0_DQS  
OSPI0_DQS  
GPIO0_2  
IO  
IO  
IO  
O
OSPI0_LBCLKO  
OSPI0_CSn0  
OSPI0_CSn1  
OSPI0_D0  
OSPI0_LBCLKO  
GPIO0_1  
OSPI0_CSn0  
GPIO0_11  
IO  
O
OSPI0_CSn1  
GPIO0_12  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
OSPI0_D0  
GPIO0_3  
OSPI0_D1  
OSPI0_D1  
GPIO0_4  
OSPI0_D2  
OSPI0_D2  
GPIO0_5  
OSPI0_D3  
OSPI0_D3  
GPIO0_6  
D18  
D2  
PORz_OUT  
PORz_OUT  
PRG0_MDIO0_MDC  
GPIO1_41  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
VDDSHV0  
VDDSHV1  
Yes  
Yes  
PU/PD PADCONFIG_171  
PU/PD PADCONFIG_129  
0x000F42AC  
0x000F4204  
Off / Low / Off  
Off / Off / Off  
Off / SS / Off  
Off / Off / Off  
0
7
PRG0_MDIO0_MDC  
O
IO  
OZ  
IO  
IO  
OZ  
GPMC0_A13  
PRG0_MDIO0_MDIO  
GPIO1_40  
E4  
PRG0_MDIO0_MDIO  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_128  
0x000F4200  
Off / Off / Off  
Off / Off / Off  
7
GPMC0_A12  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
J3  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPI0  
PRG0_RGMII1_RD0  
PRG0_PWM3_A0  
GPIO1_0  
0
1
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_88  
PU/PD PADCONFIG_89  
PU/PD PADCONFIG_90  
0x000F4160  
0x000F4164  
0x000F4168  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
2
I
3
IO  
IO  
I
7
UART2_CTSn  
10  
0
J4  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPI1  
PRG0_RGMII1_RD1  
PRG0_PWM3_B0  
GPIO1_1  
IO  
I
VDDSHV1  
Yes  
1
2
I
3
IO  
IO  
O
IO  
I
7
UART2_TXD  
10  
0
G1  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPI2  
PRG0_RGMII1_RD2  
PRG0_PWM2_A0  
GPIO1_2  
VDDSHV1  
Yes  
1
2
I
3
IO  
IO  
OZ  
O
IO  
I
7
GPMC0_A0  
9
UART2_RTSn  
10  
0
H1  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPI3  
PRG0_RGMII1_RD3  
PRG0_PWM3_A2  
GPIO1_3  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_91  
0x000F416C  
Off / Off / Off  
Off / Off / Off  
7
1
2
I
3
IO  
IO  
I
7
UART3_CTSn  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
K2  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO4  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_92  
0x000F4170  
Off / Off / Off  
Off / Off / Off  
7
PRG0_PRU0_GPI4  
PRG0_RGMII1_RX_CTL  
PRG0_PWM2_B0  
GPIO1_4  
2
I
3
IO  
IO  
OZ  
O
IO  
I
7
GPMC0_A1  
9
UART3_TXD  
10  
0
F2  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPI5  
PRG0_PWM3_B2  
GPIO1_5  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_93  
0x000F4174  
Off / Off / Off  
Off / Off / Off  
7
1
3
IO  
IO  
O
IO  
I
7
UART3_RTSn  
10  
0
H2  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPI6  
PRG0_RGMII1_RXC  
PRG0_PWM3_A1  
GPIO1_6  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_94  
0x000F4178  
Off / Off / Off  
Off / Off / Off  
7
1
2
I
3
IO  
IO  
I
7
UART4_CTSn  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
E2  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPI7  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_PWM3_B1  
CPTS0_HW2TSPUSH  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO6  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_95  
0x000F417C  
Off / Off / Off  
Off / Off / Off  
7
2
I
3
IO  
I
4
5
I
6
IO  
IO  
O
IO  
I
GPIO1_7  
7
UART4_TXD  
10  
0
H5  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPI8  
PRG0_PWM2_A1  
GPIO1_8  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_96  
0x000F4180  
Off / Off / Off  
Off / Off / Off  
7
1
3
IO  
IO  
OZ  
O
IO  
I
7
GPMC0_A2  
9
UART4_RTSn  
10  
0
Y3  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPI9  
PRG0_UART0_CTSn  
PRG0_PWM3_TZ_IN  
RGMII1_RX_CTL  
RMII1_RX_ER  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_97  
0x000F4184  
Off / Off / Off  
Off / Off / Off  
7
1
2
I
3
I
4
I
5
I
PRG0_IEP0_EDIO_DATA_IN_OUT28  
GPIO1_9  
6
IO  
IO  
I
7
UART2_RXD  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
U1  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO10  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_98  
0x000F4188  
Off / Off / Off  
Off / Off / Off  
7
PRG0_PRU0_GPI10  
PRG0_UART0_RTSn  
PRG0_PWM2_B1  
RGMII1_RXC  
2
O
IO  
I
3
4
RMII_REF_CLK  
5
I
PRG0_IEP0_EDIO_DATA_IN_OUT29  
GPIO1_10  
6
IO  
IO  
I
7
UART3_RXD  
10  
0
L1  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPI11  
PRG0_RGMII1_TD0  
PRG0_PWM3_TZ_OUT  
GPIO1_11  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_99  
0x000F418C  
Off / Off / Off  
Off / Off / Off  
7
1
2
O
O
IO  
I
3
7
UART4_RXD  
10  
0
K1  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPI12  
PRG0_RGMII1_TD1  
PRG0_PWM0_A0  
GPIO1_12  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_100  
0x000F4190  
Off / Off / Off  
Off / Off / Off  
7
1
2
O
IO  
IO  
OZ  
3
7
GPMC0_A14  
9
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
N1  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPI13  
PRG0_RGMII1_TD2  
PRG0_PWM0_B0  
SPI3_D0  
0
1
2
3
6
7
9
0
1
2
3
6
7
9
0
1
2
3
6
7
9
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_101  
PU/PD PADCONFIG_102  
PU/PD PADCONFIG_103  
0x000F4194  
0x000F4198  
0x000F419C  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
O
IO  
IO  
IO  
OZ  
IO  
I
GPIO1_13  
GPMC0_A15  
N2  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPI14  
PRG0_RGMII1_TD3  
PRG0_PWM0_A1  
SPI3_D1  
VDDSHV1  
Yes  
O
IO  
IO  
IO  
OZ  
IO  
I
GPIO1_14  
GPMC0_A3  
N4  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPI15  
PRG0_RGMII1_TX_CTL  
PRG0_PWM0_B1  
SPI3_CS1  
VDDSHV1  
Yes  
O
IO  
IO  
IO  
OZ  
GPIO1_15  
GPMC0_A16  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
N3  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO16  
0
1
2
3
6
7
9
0
1
2
3
4
5
6
7
8
9
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_104  
0x000F41A0  
PRG0_PRU0_GPI16  
PRG0_RGMII1_TXC  
PRG0_PWM0_A2  
SPI3_CLK  
IO  
IO  
IO  
IO  
OZ  
IO  
I
GPIO1_16  
GPMC0_A4  
E1  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPI17  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_PWM0_B2  
CPTS0_TS_SYNC  
CP_GEMAC_CPTS0_TS_SYNC  
SPI3_CS0  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_105  
0x000F41A4  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
O
IO  
IO  
IO  
OZ  
GPIO1_17  
TIMER_IO11  
GPMC0_A17  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
K4  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPI18  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
CP_GEMAC_CPTS0_HW1TSPUSH  
EHRPWM8_A  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_106  
0x000F41A8  
2
I
3
I
4
I
5
I
6
IO  
IO  
I
GPIO1_18  
7
UART4_CTSn  
8
GPMC0_A5  
9
OZ  
I
UART2_RXD  
10  
0
G2  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPI19  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_PWM0_TZ_OUT  
CPTS0_TS_COMP  
CP_GEMAC_CPTS0_TS_COMP  
EHRPWM8_B  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_107  
0x000F41AC  
Off / Off / Off  
Off / Off / Off  
7
1
2
O
O
O
O
IO  
IO  
O
OZ  
I
3
4
5
6
GPIO1_19  
7
UART4_RTSn  
8
GPMC0_A6  
9
UART3_RXD  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
L5  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO0  
0
1
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_108  
PU/PD PADCONFIG_109  
PU/PD PADCONFIG_110  
0x000F41B0  
0x000F41B4  
0x000F41B8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
PRG0_PRU1_GPI0  
PRG0_RGMII2_RD0  
GPIO1_20  
2
I
7
IO  
I
EQEP0_A  
8
UART5_CTSn  
10  
0
I
J2  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPI1  
PRG0_RGMII2_RD1  
GPIO1_21  
IO  
I
VDDSHV1  
Yes  
1
2
I
7
IO  
I
EQEP0_B  
8
UART5_TXD  
10  
0
O
IO  
I
M2  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPI2  
PRG0_RGMII2_RD2  
PRG0_PWM2_A2  
GPIO1_22  
VDDSHV1  
Yes  
1
2
I
3
IO  
IO  
IO  
O
7
EQEP0_S  
8
UART5_RTSn  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
L2  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPI3  
PRG0_RGMII2_RD3  
GPIO1_23  
0
1
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_111  
PU/PD PADCONFIG_112  
PU/PD PADCONFIG_113  
0x000F41BC  
0x000F41C0  
0x000F41C4  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
2
I
7
IO  
I
EQEP1_A  
8
GPMC0_A18  
9
OZ  
I
UART6_CTSn  
10  
0
L3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPI4  
PRG0_RGMII2_RX_CTL  
PRG0_PWM2_B2  
GPIO1_24  
IO  
I
VDDSHV1  
Yes  
1
2
I
3
IO  
IO  
I
7
EQEP1_B  
8
UART6_TXD  
10  
0
O
IO  
I
E3  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPI5  
GPIO1_25  
VDDSHV1  
Yes  
1
7
IO  
IO  
O
EQEP1_S  
8
UART6_RTSn  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
F5  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO6  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_114  
0x000F41C8  
PRG0_PRU1_GPI6  
PRG0_RGMII2_RXC  
GPIO1_26  
2
I
7
IO  
I
EQEP2_A  
8
GPMC0_A19  
9
OZ  
I
UART4_CTSn  
10  
0
T5  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPI7  
PRG0_IEP1_EDC_LATCH_IN1  
RGMII1_RD0  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_115  
0x000F41CC  
Off / Off / Off  
Off / Off / Off  
7
1
2
I
4
I
RMII1_RXD0  
5
I
GPIO1_27  
7
IO  
I
EQEP2_B  
8
UART4_TXD  
10  
0
O
IO  
I
F4  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPI8  
PRG0_PWM2_TZ_OUT  
GPIO1_28  
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_116  
0x000F41D0  
Off / Off / Off  
Off / Off / Off  
7
1
3
O
IO  
IO  
O
7
EQEP2_S  
8
UART4_RTSn  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
R2  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPI9  
PRG0_UART0_RXD  
RGMII1_RD1  
0
1
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_117  
0x000F41D4  
2
I
4
I
RMII1_RXD1  
5
I
PRG0_IEP0_EDIO_DATA_IN_OUT30  
GPIO1_29  
6
IO  
IO  
IO  
I
7
EQEP0_I  
8
UART5_RXD  
10  
0
U2  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPI10  
PRG0_UART0_TXD  
PRG0_PWM2_TZ_IN  
RGMII1_RD2  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_118  
0x000F41D8  
Off / Off / Off  
Off / Off / Off  
7
1
2
O
I
3
4
I
RMII1_TXD0  
5
O
IO  
IO  
IO  
I
PRG0_IEP0_EDIO_DATA_IN_OUT31  
GPIO1_30  
6
7
EQEP1_I  
8
UART6_RXD  
10  
0
P1  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPI11  
PRG0_RGMII2_TD0  
GPIO1_31  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_119  
0x000F41DC  
Off / Off / Off  
Off / Off / Off  
7
1
2
O
IO  
IO  
I
7
EQEP2_I  
8
UART4_RXD  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
P2  
T4  
R5  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO12  
0
1
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_120  
PU/PD PADCONFIG_121  
PU/PD PADCONFIG_122  
0x000F41E0  
0x000F41E4  
0x000F41E8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
PRG0_PRU1_GPI12  
PRG0_RGMII2_TD1  
PRG0_PWM1_A0  
GPIO1_32  
2
O
3
IO  
IO  
I
7
EQEP2_B  
8
GPMC0_A7  
9
OZ  
O
UART4_TXD  
10  
0
PRG0_PRU1_GPO13  
PRG0_PRU1_GPI13  
PRG0_RGMII2_TD2  
PRG0_PWM1_B0  
GPIO1_33  
IO  
I
VDDSHV1  
Yes  
1
2
O
3
IO  
IO  
IO  
OZ  
I
7
EQEP0_I  
8
GPMC0_A8  
9
UART5_RXD  
10  
0
PRG0_PRU1_GPO14  
PRG0_PRU1_GPI14  
PRG0_RGMII2_TD3  
PRG0_PWM1_A1  
GPIO1_34  
IO  
I
VDDSHV1  
Yes  
1
2
O
3
IO  
IO  
IO  
OZ  
I
7
EQEP1_I  
8
GPMC0_A9  
9
UART6_RXD  
10  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
M4  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPI15  
PRG0_RGMII2_TX_CTL  
PRG0_PWM1_B1  
0
1
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_123  
PU/PD PADCONFIG_124  
PU/PD PADCONFIG_125  
0x000F41EC  
0x000F41F0  
0x000F41F4  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
2
O
3
IO  
IO  
OZ  
IO  
IO  
I
GPIO1_35  
7
GPMC0_A10  
9
PRG0_ECAP0_IN_APWM_OUT  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPI16  
PRG0_RGMII2_TXC  
PRG0_PWM1_A2  
10  
0
T3  
PRG0_PRU1_GPO16  
VDDSHV1  
Yes  
1
2
IO  
IO  
IO  
OZ  
O
3
GPIO1_36  
7
GPMC0_A11  
9
PRG0_ECAP0_SYNC_OUT  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPI17  
PRG0_IEP1_EDC_SYNC_OUT1  
PRG0_PWM1_B2  
10  
0
T1  
PRG0_PRU1_GPO17  
IO  
I
VDDSHV1  
Yes  
1
2
O
3
IO  
I
RGMII1_RD3  
4
RMII1_TXD1  
5
O
GPIO1_37  
7
IO  
O
PRG0_ECAP0_SYNC_OUT  
PRG0_ECAP0_SYNC_IN  
8
10  
I
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
D1  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO18  
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
4
7
0
4
7
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_126  
0x000F41F8  
PRG0_PRU1_GPI18  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_PWM1_TZ_IN  
MDIO0_MDIO  
I
I
IO  
O
IO  
IO  
I
RMII1_TX_EN  
EHRPWM7_A  
GPIO1_38  
PRG0_ECAP0_SYNC_IN  
PRG0_PRU1_GPO19  
PRG0_PRU1_GPI19  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_PWM1_TZ_OUT  
MDIO0_MDC  
F3  
PRG0_PRU1_GPO19  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV1  
Yes  
PU/PD PADCONFIG_127  
0x000F41FC  
Off / Off / Off  
Off / Off / Off  
7
O
O
O
I
RMII1_CRS_DV  
EHRPWM7_B  
IO  
IO  
IO  
O
O
IO  
IO  
IO  
IO  
GPIO1_39  
PRG0_ECAP0_IN_APWM_OUT  
PRG1_MDIO0_MDC  
MDIO0_MDC  
W1  
V2  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
PU/PD PADCONFIG_87  
PU/PD PADCONFIG_86  
0x000F415C  
0x000F4158  
Off / Off / Off  
Off / Off / Off  
7
7
GPIO0_86  
PRG1_MDIO0_MDIO  
MDIO0_MDIO  
Off / Off / Off  
Off / Off / Off  
GPIO0_85  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
V4  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPI0  
PRG1_RGMII1_RD0  
PRG1_PWM3_A0  
GPIO0_45  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_46  
PU/PD PADCONFIG_47  
PU/PD PADCONFIG_48  
PU/PD PADCONFIG_49  
0x000F40B8  
0x000F40BC  
0x000F40C0  
0x000F40C4  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
I
IO  
IO  
IO  
IO  
I
GPMC0_AD16  
W5  
AA4  
Y5  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPI1  
PRG1_RGMII1_RD1  
PRG1_PWM3_B0  
GPIO0_46  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
Yes  
I
IO  
IO  
IO  
IO  
I
GPMC0_AD17  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPI2  
PRG1_RGMII1_RD2  
PRG1_PWM2_A0  
GPIO0_47  
I
IO  
IO  
IO  
IO  
I
GPMC0_AD18  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPI3  
PRG1_RGMII1_RD3  
PRG1_PWM3_A2  
GPIO0_48  
I
IO  
IO  
IO  
GPMC0_AD19  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
AA5  
U14  
Y2  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO4  
0
1
2
3
7
8
0
1
3
4
7
8
0
1
2
3
7
8
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_50  
PU/PD PADCONFIG_51  
PU/PD PADCONFIG_52  
0x000F40C8  
0x000F40CC  
0x000F40D0  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
PRG1_PRU0_GPI4  
PRG1_RGMII1_RX_CTL  
PRG1_PWM2_B0  
GPIO0_49  
I
IO  
IO  
IO  
IO  
I
GPMC0_AD20  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPI5  
PRG1_PWM3_B2  
RGMII1_RX_CTL  
GPIO0_50  
VDDSHV2  
Yes  
IO  
I
IO  
IO  
IO  
I
GPMC0_AD21  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPI6  
PRG1_RGMII1_RXC  
PRG1_PWM3_A1  
GPIO0_51  
VDDSHV2  
Yes  
I
IO  
IO  
IO  
GPMC0_AD22  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
V13  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPI7  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_PWM3_B1  
CPTS0_HW2TSPUSH  
CLKOUT0  
0
1
2
3
4
5
6
7
8
0
1
3
4
7
8
0
1
2
3
4
5
6
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_53  
0x000F40D4  
Off / Off / Off  
Off / Off / Off  
7
I
IO  
I
O
IO  
IO  
IO  
IO  
I
TIMER_IO10  
GPIO0_52  
GPMC0_AD23  
Y13  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPI8  
PRG1_PWM2_A1  
RGMII1_RXC  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_54  
0x000F40D8  
Off / Off / Off  
Off / Off / Off  
7
IO  
I
GPIO0_53  
IO  
IO  
IO  
I
GPMC0_AD24  
W16  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPI9  
PRG1_UART0_CTSn  
PRG1_PWM3_TZ_IN  
RGMII1_TX_CTL  
RMII1_RX_ER  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_55  
0x000F40DC  
Off / Off / Off  
Off / Off / Off  
7
I
I
O
I
PRG1_IEP0_EDIO_DATA_IN_OUT28  
GPIO0_54  
IO  
IO  
IO  
GPMC0_AD25  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
W13  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_56  
0x000F40E0  
Off / Off / Off  
Off / Off / Off  
7
PRG1_PRU0_GPI10  
PRG1_UART0_RTSn  
PRG1_PWM2_B1  
RGMII1_TXC  
O
IO  
IO  
I
RMII_REF_CLK  
PRG1_IEP0_EDIO_DATA_IN_OUT29  
GPIO0_55  
IO  
IO  
IO  
IO  
I
GPMC0_AD26  
V5  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPI11  
PRG1_RGMII1_TD0  
PRG1_PWM3_TZ_OUT  
GPIO0_56  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_57  
0x000F40E4  
Off / Off / Off  
Off / Off / Off  
7
O
O
IO  
IO  
IO  
I
GPMC0_AD27  
W2  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPI12  
PRG1_RGMII1_TD1  
PRG1_PWM0_A0  
GPIO0_57  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_58  
0x000F40E8  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
IO  
IO  
GPMC0_AD28  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
V6  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPI13  
PRG1_RGMII1_TD2  
PRG1_PWM0_B0  
GPIO0_58  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_59  
PU/PD PADCONFIG_60  
PU/PD PADCONFIG_61  
PU/PD PADCONFIG_62  
0x000F40EC  
0x000F40F0  
0x000F40F4  
0x000F40F8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
O
IO  
IO  
IO  
IO  
I
GPMC0_AD29  
AA7  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPI14  
PRG1_RGMII1_TD3  
PRG1_PWM0_A1  
GPIO0_59  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
Yes  
O
IO  
IO  
IO  
IO  
I
GPMC0_AD30  
Y7  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPI15  
PRG1_RGMII1_TX_CTL  
PRG1_PWM0_B1  
GPIO0_60  
O
IO  
IO  
IO  
IO  
I
GPMC0_AD31  
W6  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPI16  
PRG1_RGMII1_TXC  
PRG1_PWM0_A2  
GPIO0_61  
IO  
IO  
IO  
O
GPMC0_BE2n  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
T2  
Y4  
U3  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU0_GPO17  
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
IO  
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_63  
PU/PD PADCONFIG_64  
PU/PD PADCONFIG_65  
0x000F40FC  
0x000F4100  
0x000F4104  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
PRG1_PRU0_GPI17  
PRG1_IEP0_EDC_SYNC_OUT1  
PRG1_PWM0_B2  
CPTS0_TS_SYNC  
TIMER_IO7  
O
IO  
O
IO  
IO  
OZ  
IO  
I
GPIO0_62  
GPMC0_A0  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPI18  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
TIMER_IO8  
VDDSHV2  
Yes  
I
I
I
IO  
IO  
OZ  
IO  
I
GPIO0_63  
GPMC0_A1  
PRG1_PRU0_GPO19  
PRG1_PRU0_GPI19  
PRG1_IEP0_EDC_SYNC_OUT0  
PRG1_PWM0_TZ_OUT  
CPTS0_TS_COMP  
TIMER_IO9  
VDDSHV2  
Yes  
O
O
O
IO  
IO  
OZ  
GPIO0_64  
GPMC0_A2  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
AA10 PRG1_PRU1_GPO0  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPI0  
PRG1_RGMII2_RD0  
RGMII2_RD0  
0
1
2
4
5
7
8
0
1
2
4
5
7
8
0
1
2
3
4
7
8
IO  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_66  
PU/PD PADCONFIG_67  
PU/PD PADCONFIG_68  
0x000F4108  
0x000F410C  
0x000F4110  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
I
I
I
RMII2_RXD0  
I
GPIO0_65  
IO  
OZ  
IO  
I
GPMC0_A3  
Y10  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPI1  
PRG1_RGMII2_RD1  
RGMII2_RD1  
VDDSHV2  
Yes  
I
I
RMII2_RXD1  
I
GPIO0_66  
IO  
OZ  
IO  
I
GPMC0_A4  
Y11  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPI2  
PRG1_RGMII2_RD2  
PRG1_PWM2_A2  
RGMII2_RD2  
VDDSHV2  
Yes  
I
IO  
I
GPIO0_67  
IO  
OZ  
GPMC0_A5  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
V12  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO3  
0
1
2
4
7
8
0
1
2
3
4
5
7
8
0
1
4
7
8
0
1
2
4
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_69  
0x000F4114  
PRG1_PRU1_GPI3  
PRG1_RGMII2_RD3  
RGMII2_RD3  
I
I
GPIO0_68  
IO  
OZ  
IO  
I
GPMC0_A6  
Y12  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPI4  
PRG1_RGMII2_RX_CTL  
PRG1_PWM2_B2  
RGMII2_RX_CTL  
RMII2_RX_ER  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_70  
0x000F4118  
Off / Off / Off  
Off / Off / Off  
7
I
IO  
I
I
GPIO0_69  
IO  
OZ  
IO  
I
GPMC0_A7  
AA11  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPI5  
RGMII1_RD0  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_71  
0x000F411C  
Off / Off / Off  
Off / Off / Off  
7
I
GPIO0_70  
IO  
OZ  
IO  
I
GPMC0_A8  
V10  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPI6  
PRG1_RGMII2_RXC  
RGMII2_RXC  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_72  
0x000F4120  
Off / Off / Off  
Off / Off / Off  
7
I
I
GPIO0_71  
IO  
OZ  
GPMC0_A9  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Y14  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPI7  
PRG1_IEP1_EDC_LATCH_IN1  
RGMII1_TD0  
0
1
2
4
5
6
7
8
0
1
3
4
7
8
0
1
2
4
5
6
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_73  
0x000F4124  
Off / Off / Off  
Off / Off / Off  
7
I
O
I
RMII1_RXD0  
SPI3_CS3  
IO  
IO  
OZ  
IO  
I
GPIO0_72  
GPMC0_A10  
W11  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPI8  
PRG1_PWM2_TZ_OUT  
RGMII1_RD1  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_74  
0x000F4128  
Off / Off / Off  
Off / Off / Off  
7
O
I
GPIO0_73  
IO  
OZ  
IO  
I
GPMC0_A11  
Y16  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPI9  
PRG1_UART0_RXD  
RGMII1_TD1  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_75  
0x000F412C  
Off / Off / Off  
Off / Off / Off  
7
I
O
I
RMII1_RXD1  
PRG1_IEP0_EDIO_DATA_IN_OUT30  
GPIO0_74  
IO  
IO  
OZ  
GPMC0_A12  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
U13  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
4
5
7
8
0
1
2
3
4
5
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_76  
0x000F4130  
Off / Off / Off  
Off / Off / Off  
7
PRG1_PRU1_GPI10  
PRG1_UART0_TXD  
PRG1_PWM2_TZ_IN  
RGMII1_TD2  
O
I
O
RMII1_TXD0  
O
PRG1_IEP0_EDIO_DATA_IN_OUT31  
GPIO0_75  
IO  
IO  
OZ  
IO  
I
GPMC0_A13  
Y6  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPI11  
PRG1_RGMII2_TD0  
RGMII2_TD0  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_77  
0x000F4134  
Off / Off / Off  
Off / Off / Off  
7
O
O
RMII2_TXD0  
O
GPIO0_76  
IO  
OZ  
IO  
I
GPMC0_A14  
AA8  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPI12  
PRG1_RGMII2_TD1  
PRG1_PWM1_A0  
RGMII2_TD1  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_78  
0x000F4138  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
RMII2_TXD1  
O
GPIO0_77  
IO  
OZ  
GPMC0_A15  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Y9  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPI13  
PRG1_RGMII2_TD2  
PRG1_PWM1_B0  
RGMII2_TD2  
0
1
2
3
4
5
7
8
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_79  
0x000F413C  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
RMII2_CRS_DV  
GPIO0_78  
I
IO  
OZ  
IO  
I
GPMC0_A16  
W9  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPI14  
PRG1_RGMII2_TD3  
PRG1_PWM1_A1  
RGMII2_TD3  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_80  
0x000F4140  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
GPIO0_79  
IO  
OZ  
IO  
I
GPMC0_A17  
V9  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPI15  
PRG1_RGMII2_TX_CTL  
PRG1_PWM1_B1  
RGMII2_TX_CTL  
RMII2_TX_EN  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_81  
0x000F4144  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
O
GPIO0_80  
IO  
OZ  
GPMC0_A18  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
Off / Off / Off Off / Off / Off 7  
Y8  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO16  
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
7
8
9
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_82  
0x000F4148  
PRG1_PRU1_GPI16  
PRG1_RGMII2_TXC  
PRG1_PWM1_A2  
RGMII2_TXC  
IO  
IO  
IO  
IO  
OZ  
IO  
I
GPIO0_81  
GPMC0_A19  
AA14 PRG1_PRU1_GPO17  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPI17  
PRG1_IEP1_EDC_SYNC_OUT1  
PRG1_PWM1_B2  
RGMII1_TD3  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_83  
0x000F414C  
Off / Off / Off  
Off / Off / Off  
7
O
IO  
O
O
IO  
O
O
IO  
I
RMII1_TXD1  
GPIO0_19  
GPMC0_BE3n  
PRG1_ECAP0_SYNC_OUT  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPI18  
PRG1_IEP1_EDC_LATCH_IN0  
PRG1_PWM1_TZ_IN  
RGMII1_RD2  
Y15  
PRG1_PRU1_GPO18  
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_84  
0x000F4150  
Off / Off / Off  
Off / Off / Off  
7
I
I
I
RMII1_TX_EN  
O
IO  
I
GPIO0_20  
UART5_CTSn  
PRG1_ECAP0_SYNC_IN  
I
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
AA13 PRG1_PRU1_GPO19  
PRG1_PRU1_GPO19  
PRG1_PRU1_GPI19  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_PWM1_TZ_OUT  
RGMII1_RD3  
0
1
2
3
4
5
6
7
8
9
0
0
-
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV2  
Yes  
PU/PD PADCONFIG_85  
0x000F4154  
Off / Off / Off  
Off / Off / Off  
7
O
O
I
RMII1_CRS_DV  
SPI3_CS2  
I
IO  
IO  
O
IO  
O
I
GPIO0_84  
UART5_RTSn  
PRG1_ECAP0_IN_APWM_OUT  
RESETSTATz  
E19  
C17  
RESETSTATz  
RESET_REQz  
1.8 V/3.3 V  
1.8 V/3.3 V  
RSVD  
LVCMOS  
LVCMOS  
RSVD  
VDDSHV0  
VDDSHV0  
RSVD  
Yes  
Yes  
-
PU/PD PADCONFIG_169  
PU/PD PADCONFIG_168  
0x000F42A4  
0x000F42A0  
-
Off / Low / Off  
On / Off / Up  
-
Off / SS / Off  
On / Off / Up  
-
0
0
-
RESET_REQz  
H11, J13 RSVD  
RSVD  
A
-
-
B8  
SPI0_CLK  
SPI0_CLK  
0
7
0
1
2
3
4
5
6
7
0
7
IO  
IO  
IO  
O
IOD  
IO  
O
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_132  
0x000F4210  
Off / Off / Off  
Off / Off / Off  
7
GPIO1_44  
B7  
SPI0_CS1  
SPI0_CS1  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_131  
0x000F420C  
Off / Off / Off  
Off / Off / Off  
7
CPTS0_TS_COMP  
I2C2_SCL  
TIMER_IO10  
PRG0_IEP0_EDIO_OUTVALID  
UART6_RXD  
ADC_EXT_TRIGGER0  
GPIO1_43  
I
IO  
IO  
IO  
A8  
SPI0_D0  
SPI0_D0  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_133  
0x000F4214  
Off / Off / Off  
Off / Off / Off  
7
GPIO1_45  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
C9  
SPI0_D1  
SPI0_D1  
0
7
IO  
IO  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_134  
0x000F4218  
Off / Off / Off  
Off / Off / Off  
7
GPIO1_46  
MCU_PADCONFIG_2  
C6  
A3  
B5  
B4  
TCK  
TDI  
TCK  
TDI  
0
0
0
0
0
I
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
PU/PD  
6
0x04084068  
0x04084070  
0x04084074  
0x04084078  
On / Off / Up  
On / Off / Up  
Off / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
Off / SS / Up  
On / Off / Up  
0
0
0
0
MCU_PADCONFIG_2  
PU/PD  
8
I
MCU_PADCONFIG_2  
PU/PD  
9
TDO  
TMS  
TDO  
TMS  
TRSTn  
OZ  
MCU_PADCONFIG_3  
PU/PD  
0
I
I
MCU_PADCONFIG_2  
PU/PD  
7
On / Off /  
Down  
On / Off /  
Down  
B6  
B9  
TRSTn  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
VDDSHV_MCU  
VDDSHV0  
Yes  
Yes  
0x0408406C  
0x000F4238  
0
7
UART0_CTSn  
UART0_CTSn  
SPI0_CS2  
0
1
2
3
4
6
7
8
9
I
PU/PD PADCONFIG_142  
Off / Off / Off  
Off / Off / Off  
IO  
I
ADC_EXT_TRIGGER0  
UART2_RXD  
I
TIMER_IO6  
IO  
IO  
IO  
IO  
O
SPI4_CLK  
GPIO1_54  
EQEP0_S  
CP_GEMAC_CPTS0_TS_SYNC  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
A9  
UART0_RTSn  
UART0_RTSn  
SPI0_CS3  
0
1
3
4
6
7
8
0
2
7
8
0
2
7
8
0
1
2
3
4
5
6
7
8
O
IO  
O
IO  
IO  
IO  
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_143  
0x000F423C  
Off / Off / Off  
Off / Off / Off  
7
UART2_TXD  
TIMER_IO7  
SPI4_D0  
GPIO1_55  
EQEP0_I  
B10  
B11  
C11  
UART0_RXD  
UART0_TXD  
UART1_CTSn  
UART0_RXD  
SPI2_D0  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
LVCMOS  
LVCMOS  
LVCMOS  
VDDSHV0  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
Yes  
PU/PD PADCONFIG_140  
PU/PD PADCONFIG_141  
PU/PD PADCONFIG_146  
0x000F4230  
0x000F4234  
0x000F4248  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
IO  
IO  
I
GPIO1_52  
EQEP0_A  
UART0_TXD  
SPI2_D1  
O
IO  
IO  
I
GPIO1_53  
EQEP0_B  
UART1_CTSn  
SPI1_CS2  
I
IO  
I
ADC_EXT_TRIGGER1  
PCIE0_CLKREQn  
UART3_RXD  
CP_GEMAC_CPTS0_TS_SYNC  
SPI4_D1  
IO  
I
O
IO  
IO  
IO  
GPIO1_58  
EQEP1_S  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
A11  
UART1_RTSn  
UART1_RTSn  
0
1
4
5
6
7
8
0
2
5
7
8
0
2
5
7
8
O
IO  
O
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_147  
0x000F424C  
Off / Off / Off  
Off / Off / Off  
7
SPI1_CS3  
UART3_TXD  
CP_GEMAC_CPTS0_HW2TSPUSH  
SPI4_CS0  
IO  
IO  
IO  
I
GPIO1_59  
EQEP1_I  
B12  
UART1_RXD  
UART1_RXD  
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_144  
0x000F4240  
Off / Off / Off  
Off / Off / Off  
7
SPI2_CS0  
IO  
O
IO  
I
CP_GEMAC_CPTS0_TS_COMP  
GPIO1_56  
EQEP1_A  
A12  
UART1_TXD  
UART1_TXD  
O
IO  
I
1.8 V/3.3 V  
LVCMOS  
VDDSHV0  
Yes  
PU/PD PADCONFIG_145  
0x000F4244  
Off / Off / Off  
Off / Off / Off  
7
SPI2_CLK  
CP_GEMAC_CPTS0_HW1TSPUSH  
GPIO1_57  
IO  
I
EQEP1_B  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
AA17 USB0_DM  
AA16 USB0_DP  
USB0_DM  
USB0_DP  
-
-
IO  
IO  
1.8 V/3.3 V  
USB2PHY  
-
-
-
-
-
-
-
-
-
-
-
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
1.8 V/3.3 V  
1.8 V/3.3 V  
USB2PHY  
LVCMOS  
-
-
-
B19  
USB0_DRVVBUS  
USB0_DRVVBUS  
GPIO1_79  
0
7
O
VDDSHV0  
Yes  
PU/PD PADCONFIG_170  
0x000F42A8  
Off / Off /  
Down  
Off / Off /  
Down  
7
IO  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
Y17  
W17  
V18  
USB0_ID  
USB0_ID  
-
-
-
A
A
A
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
USB2PHY  
USB2PHY  
USB2PHY  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
USB0_RCALIB  
USB0_VBUS  
USB0_RCALIB  
USB0_VBUS  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
V16  
U15  
K15  
U16  
VDDA_0P85_USB0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_0P85_USB0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
-
-
-
-
PWR  
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G17,  
H17  
VDDA_ADC  
VDDA_ADC  
-
PWR  
-
-
-
-
-
-
-
-
-
-
H14  
N12  
G9  
VDDA_MCU  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
VDDA_TEMP0  
VDDA_TEMP1  
VDDA_MCU  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
VDDA_TEMP0  
VDDA_TEMP1  
-
-
-
-
-
-
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G12  
G11  
M11  
G5, G6,  
J10,  
J12,  
VDDR_CORE  
VDDR_CORE  
-
-
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P14, P8,  
R10  
C13,  
D13,  
E14  
VDDSHV0  
VDDSHV0  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
L6, M6,  
VDDSHV1  
VDDSHV1  
VDDSHV2  
VDDSHV3  
-
-
-
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P5, P6  
T11, T8,  
U11, U7, VDDSHV2  
U8  
R17,  
VDDSHV3  
T17  
N16,  
VDDSHV4  
N17  
VDDSHV4  
VDDSHV5  
-
-
-
-
PWR  
PWR  
PWR  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L16, L17 VDDSHV5  
E7, E8,  
VDDSHV_MCU  
VDDSHV_MCU  
VDDS_OSC  
E9  
F18  
VDDS_OSC  
F11,  
G10,  
H15,  
H8, J9,  
K11,  
K14,  
L13, L9, VDD_CORE  
VDD_CORE  
-
PWR  
-
-
-
-
-
-
-
-
-
-
M14,  
M8,  
N10,  
N9,  
R12,  
R13, R9  
F14  
E15  
G13  
E16  
VMON_1P8_SOC  
VMON_1P8_SOC  
VMON_3P3_SOC  
VMON_VSYS  
VPP  
-
-
-
-
A
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VMON_3P3_SOC  
VMON_VSYS  
VPP  
A
PWR  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
#
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
A1, A2,  
A20,  
A21,  
AA1,  
AA2,  
AA20,  
AA21,  
B1, B21,  
D10,  
D16,  
D17,  
E11,  
E13, E6,  
F17, F8,  
G16,  
H16,  
H6, H7, VSS  
J11,  
VSS  
-
GND  
-
-
-
-
-
-
-
-
-
-
J16, J5,  
J6, K16,  
K6, K7,  
K8, L10,  
L11,  
L12,  
M15,  
M16,  
M7,  
N11,  
N13,  
N6, P11,  
P15,  
P16, P7,  
R11, R6,  
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Table 6-2. Pin Attributes (ALX Package) (continued)  
PULL  
BALL STATE BALL STATE  
MUX  
MODE  
AFTER  
IO  
BALL  
#
MUX  
BUFFER  
TYPE  
UP/  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
DURING  
RESET  
AFTER  
RESET  
BALL NAME  
SIGNAL NAME  
TYPE VOLTAGE  
VALUE  
POWER  
HYS  
MODE  
DOWN  
TYPE  
(RX/TX/PULL) (RX/TX/PULL) RESET  
T14, U6,  
Y1, Y21  
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6.4 Signal Descriptions  
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing  
options.  
The following list describes the column headers:  
1. SIGNAL NAME: The name of the signal passing through the pin.  
Note  
Signal names and descriptions provided in each Signal Descriptions table, represent the pin  
multiplexed signal function which is implemented at the pin and selected via PADCONFIG  
registers. Device subsystems may provide secondary multiplexing of signal functions, which are  
not described in these tables. For more information on secondary multiplexed signal functions,  
see the respective peripheral chapter of the device TRM.  
2. PIN TYPE: Signal direction and type:  
•
•
•
•
•
•
•
•
•
•
I = Input  
O = Output  
IO = Input, Output, or simultaneously Input and Output  
IOD = Input, Output, or simultaneously Input and Output with open-drain output function  
IOZ = Input, Output, or simultaneously Input and Output with three-state output function  
OZ = Output with three-state output function  
A = Analog  
PWR = Power  
GND = Ground  
CAP = LDO Capacitor  
3. DESCRIPTION: Description of the signal  
4. BALL: Associated ball number  
For more information on the I/O cell configurations, see the Pad Configuration Registers section in Device  
Configuration chapter of the device TRM.  
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Note  
The following peripheral instances and signals are not supported by the AM243x_ALX device  
package. In some cases, the entire peripheral can not be used due to critical interface signal  
availability.  
MAIN Domain  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDRSS0*  
GPIO0_[7:10]  
GPIO0_[13:14]  
GPIO0_[31:35]  
GPIO0_[37:44]  
GPIO1_[42]  
GPIO1_[47:51]  
GPIO1_[68,70]  
I2C2*  
SPI1*  
SYNC0  
CP_GEMAC_CPTS0_RFT_CLK  
ECAP0_IN_APWM_OUT  
EHRPWM5_B  
EHRPWM4*  
EHRPWM6*  
SERDES0*  
OSPI0_D[4:7]  
OSPI0_RESET_OUT[0:1]  
OSPI0_CSn[2:3]  
OSPI0_ECC_FAIL  
GPMC0*  
GPMC0_FCLK_MUX  
MMC0*  
FSI_TX1*  
FSI_RX[4:5]*  
PRG1_IEP0_EDIO_OUTVALID  
CPTS0_RFT_CLK  
TRACE[14:23]  
EXTINTn  
MCU Domain  
•
•
•
•
•
•
•
MCU_I2C[0:1]*  
MCU_SPI[0:1]*  
MCU_UART1*  
MCU_GPIO[4:21]  
MCU_TIMER_IO[2:3]  
MCU_EXT_REFCLK0  
MCU_SYSCLKOUT0  
*Entire peripheral instance is unsupported.  
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6.4.1 ADC  
MAIN Domain Instances  
6.4.1.1 ADC0 Signal Descriptions  
Table 6-3. ADC0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
ADC0_AIN0  
A
A
A
A
A
A
A
A
I
ADC Analog Input 0 / GPIO1_80 (Input Only)  
ADC Analog Input 1 / GPIO1_81 (Input Only)  
ADC Analog Input 2 / GPIO1_82 (Input Only)  
ADC Analog Input 3 / GPIO1_83 (Input Only)  
ADC Analog Input 4 / GPIO1_84 (Input Only)  
ADC Analog Input 5 / GPIO1_85 (Input Only)  
ADC Analog Input 6 / GPIO1_86 (Input Only)  
ADC Analog Input 7 / GPIO1_87 (Input Only)  
ADC Trigger Input  
G20  
F20  
H21  
F19  
ADC0_AIN1  
ADC0_AIN2  
E21  
F21  
ADC0_AIN3  
D20  
F20  
ADC0_AIN4  
G21  
H20  
E21  
ADC0_AIN5  
F21  
ADC0_AIN6  
F19  
G20  
E20  
ADC0_AIN7  
E20  
ADC_EXT_TRIGGER0  
ADC_EXT_TRIGGER1  
B16, C13  
D14, D16  
B7, B9  
C11  
I
ADC Trigger Input  
6.4.2 DDRSS  
MAIN Domain Instances  
6.4.2.1 DDRSS0 Signal Descriptions  
Table 6-4. DDRSS0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
DDR0_ACT_n  
O
IO  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DDRSS Activation Command  
DDRSS Alert  
H2  
H1  
J5  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
DDRSS Column Address Strobe  
DDRSS Command and Address Parity  
DDRSS Row Address Strobe  
DDRSS Write Enable  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
K5  
F6  
H4  
D2  
C5  
E2  
D4  
D3  
F2  
J2  
DDR0_A1  
DDR0_A2  
DDR0_A3  
DDR0_A4  
DDR0_A5  
DDR0_A6  
DDR0_A7  
L5  
J3  
DDR0_A8  
DDR0_A9  
J4  
DDR0_A10  
DDR0_A11  
K3  
J1  
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Table 6-4. DDRSS0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
DDRSS Address Bus  
ALV  
ALX  
TYPE  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
O
M5  
K4  
G4  
G5  
G2  
H3  
F1  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
A2  
B5  
A4  
B3  
C4  
C2  
B4  
N5  
L4  
O
DDRSS Address Bus  
DDRSS Bank Address  
DDRSS Bank Address  
DDRSS Bank Group  
DDRSS Bank Group  
DDRSS Clock  
O
O
DDR0_BG0  
DDR0_BG1  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
O
O
O
O
DDRSS Negative Clock  
DDRSS Clock Enable  
DDRSS Clock Enable  
DDRSS Chip Select 0  
DDRSS Chip Select 1  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data  
O
O
O
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
L2  
DDRSS Data  
M3  
N4  
N3  
M4  
N2  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
Data strobe 0 input/output for byte 0 of the 16-  
bit data bus. This signal is output to the DDRSS  
memory when writing and input when reading.  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
IO  
IO  
IO  
C1  
B1  
N1  
Data strobe 0 invert  
Data strobe 1 input/output for byte 2 of the 16-  
bit data bus. This signal is output to the DDRSS  
memory when writing and input when reading.  
DDR0_DQS1_n  
DDR0_ODT0  
IO  
O
Data strobe 1 invert  
M1  
E5  
DDRSS On-Die Termination for Chip Select 0  
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Table 6-4. DDRSS0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
DDR0_ODT1  
O
DDRSS On-Die Termination for Chip Select 1  
DDRSS Reset  
F5  
D5  
DDR0_RESET0_n  
O
6.4.3 GPIO  
MAIN Domain Instances  
6.4.3.1 GPIO0 Signal Descriptions  
Table 6-5. GPIO0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
GPIO0_0  
GPIO0_1  
GPIO0_2  
GPIO0_3  
GPIO0_4  
GPIO0_5  
GPIO0_6  
GPIO0_7  
GPIO0_8  
GPIO0_9  
GPIO0_10  
GPIO0_11  
GPIO0_12  
GPIO0_13  
GPIO0_14  
GPIO0_15  
GPIO0_16  
GPIO0_17  
GPIO0_18  
GPIO0_19  
GPIO0_20  
GPIO0_21  
GPIO0_22  
GPIO0_23  
GPIO0_24  
GPIO0_25  
GPIO0_26  
GPIO0_27  
GPIO0_28  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
N20  
N21  
N19  
M19  
M18  
M20  
M21  
P21  
P20  
N18  
M17  
L19  
P20  
M21  
P17  
L19  
N20  
L21  
N19  
L20  
L18  
M20  
K17  
L17  
T20  
U21  
T18  
U20  
AA14  
Y13  
V20  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
R21  
R20  
T19  
V21  
AA14  
Y15  
T18  
U19  
U18  
U20  
V20  
W20  
Y20  
Y19  
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Table 6-5. GPIO0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
General Purpose Input/Output  
ALV  
ALX  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
GPIO0_29  
GPIO0_30  
GPIO0_31  
GPIO0_32  
GPIO0_33  
GPIO0_34  
GPIO0_35  
GPIO0_36  
GPIO0_37  
GPIO0_38  
GPIO0_39  
GPIO0_40  
GPIO0_41  
GPIO0_42  
GPIO0_43  
GPIO0_44  
GPIO0_45  
GPIO0_46  
GPIO0_47  
GPIO0_48  
GPIO0_49  
GPIO0_50  
GPIO0_51  
GPIO0_52  
GPIO0_53  
GPIO0_54  
GPIO0_55  
GPIO0_56  
GPIO0_57  
GPIO0_58  
GPIO0_59  
GPIO0_60  
GPIO0_61  
GPIO0_62  
GPIO0_63  
GPIO0_64  
GPIO0_65  
GPIO0_66  
Y21  
Y20  
R17  
P16  
R18  
T21  
P17  
T19  
W19  
Y18  
N16  
N17  
R19  
R20  
P19  
R21  
Y7  
Y18  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
AA19  
P21  
V4  
W5  
AA4  
Y5  
U8  
W8  
V8  
Y8  
AA5  
U14  
Y2  
V13  
AA7  
U13  
W13  
U15  
U14  
AA8  
U9  
V13  
Y13  
W16  
W13  
V5  
W2  
V6  
W9  
AA9  
Y9  
AA7  
Y7  
V9  
W6  
T2  
U7  
V7  
Y4  
W7  
U3  
W11  
V11  
AA10  
Y10  
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Table 6-5. GPIO0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
General Purpose Input/Output  
ALV  
ALX  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
GPIO0_67  
GPIO0_68  
GPIO0_69  
GPIO0_70  
GPIO0_71  
GPIO0_72  
GPIO0_73  
GPIO0_74  
GPIO0_75  
GPIO0_76  
GPIO0_77  
GPIO0_78  
GPIO0_79  
GPIO0_80  
GPIO0_81  
GPIO0_82  
GPIO0_83  
GPIO0_84  
GPIO0_85  
GPIO0_86  
AA12  
Y12  
W12  
AA13  
U11  
V15  
U12  
V14  
W14  
AA10  
V10  
U10  
AA11  
Y11  
Y11  
V12  
Y12  
AA11  
V10  
Y14  
W11  
Y16  
U13  
Y6  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
AA8  
Y9  
W9  
V9  
Y10  
U18  
U19  
V12  
AA6  
Y6  
Y8  
U21  
T20  
AA13  
V2  
W1  
6.4.3.2 GPIO1 Signal Descriptions  
Table 6-6. GPIO1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
GPIO1_0  
GPIO1_1  
GPIO1_2  
GPIO1_3  
GPIO1_4  
GPIO1_5  
GPIO1_6  
GPIO1_7  
GPIO1_8  
GPIO1_9  
GPIO1_10  
GPIO1_11  
GPIO1_12  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
Y1  
R4  
J3  
J4  
U2  
G1  
H1  
K2  
F2  
H2  
E2  
H5  
Y3  
U1  
L1  
K1  
V2  
AA2  
R3  
T3  
T1  
T2  
W6  
AA5  
Y3  
AA3  
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Table 6-6. GPIO1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
General Purpose Input/Output  
ALV  
ALX  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
GPIO1_13  
GPIO1_14  
GPIO1_15  
GPIO1_16  
GPIO1_17  
GPIO1_18  
GPIO1_19  
GPIO1_20  
GPIO1_21  
GPIO1_22  
GPIO1_23  
GPIO1_24  
GPIO1_25  
GPIO1_26  
GPIO1_27  
GPIO1_28  
GPIO1_29  
GPIO1_30  
GPIO1_31  
GPIO1_32  
GPIO1_33  
GPIO1_34  
GPIO1_35  
GPIO1_36  
GPIO1_37  
GPIO1_38  
GPIO1_39  
GPIO1_40  
GPIO1_41  
GPIO1_42  
GPIO1_43  
GPIO1_44  
GPIO1_45  
GPIO1_46  
GPIO1_47  
GPIO1_48  
GPIO1_49  
GPIO1_50  
R6  
V4  
N1  
N2  
N4  
N3  
E1  
K4  
G2  
L5  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
T5  
U4  
U1  
V1  
W1  
Y2  
W2  
V3  
J2  
M2  
L2  
T4  
W3  
P4  
L3  
E3  
F5  
T5  
F4  
R2  
U2  
P1  
P2  
T4  
R5  
M4  
T3  
T1  
D1  
F3  
E4  
D2  
R5  
W5  
R1  
Y5  
V6  
W4  
Y4  
T6  
U6  
U5  
AA4  
V5  
P5  
R2  
P2  
P3  
D12  
C13  
D13  
A13  
A14  
B14  
D14  
C14  
B15  
B7  
B8  
A8  
C9  
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Table 6-6. GPIO1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
General Purpose Input/Output  
ALV  
ALX  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
GPIO1_51  
GPIO1_52  
GPIO1_53  
GPIO1_54  
GPIO1_55  
GPIO1_56  
GPIO1_57  
GPIO1_58  
GPIO1_59  
GPIO1_60  
GPIO1_61  
GPIO1_62  
GPIO1_63  
GPIO1_64  
GPIO1_65  
GPIO1_66  
GPIO1_67  
GPIO1_68  
GPIO1_69  
GPIO1_70  
GPIO1_71  
GPIO1_72  
GPIO1_73  
GPIO1_74  
GPIO1_75  
GPIO1_76  
GPIO1_77  
GPIO1_78  
GPIO1_79  
GPIO1_80  
GPIO1_81  
GPIO1_82  
GPIO1_83  
GPIO1_84  
GPIO1_85  
GPIO1_86  
GPIO1_87  
A15  
D15  
C16  
B16  
A16  
E15  
E14  
D16  
E16  
A17  
B17  
C17  
D17  
A18  
B18  
C18  
B19  
D18  
A19  
C19  
K18  
K19  
L21  
K21  
L20  
J19  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
B10  
B11  
B9  
A9  
B12  
A12  
C11  
A11  
B13  
A14  
B14  
A15  
B16  
B15  
A17  
B18  
A18  
K18  
K20  
J19  
J18  
J20  
J21  
B17  
C16  
B19  
H21  
F19  
F21  
F20  
H20  
E21  
G20  
E20  
D19  
C20  
E19  
G20  
F20  
E21  
D20  
G21  
F21  
F19  
E20  
I
I
I
I
I
I
I
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MCU Domain Instances  
6.4.3.3 MCU_GPIO0 Signal Descriptions  
Table 6-7. MCU_GPIO0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
General Purpose Input/Output  
ALV  
ALX  
TYPE  
MCU_GPIO0_0  
IO  
E8  
D8  
A8  
C2  
D4  
B2  
D6  
MCU_GPIO0_1  
MCU_GPIO0_2  
MCU_GPIO0_3  
MCU_GPIO0_4  
MCU_GPIO0_5  
MCU_GPIO0_6  
MCU_GPIO0_7  
MCU_GPIO0_8  
MCU_GPIO0_9  
MCU_GPIO0_10  
MCU_GPIO0_11  
MCU_GPIO0_12  
MCU_GPIO0_13  
MCU_GPIO0_14  
MCU_GPIO0_15  
MCU_GPIO0_16  
MCU_GPIO0_17  
MCU_GPIO0_18  
MCU_GPIO0_19  
MCU_GPIO0_20  
MCU_GPIO0_21  
MCU_GPIO0_22  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
IO  
IO  
A9  
IO  
B6  
IO  
A7  
IO  
B7  
IO  
D7  
C7  
C8  
E7  
IO  
IO  
IO  
IO  
E6  
IO  
C6  
D6  
C9  
D9  
B8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
B9  
E9  
A10  
A11  
B10  
B13  
A6  
6.4.4 I2C  
MAIN Domain Instances  
6.4.4.1 I2C0 Signal Descriptions  
Table 6-8. I2C0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
I2C0_SCL  
I2C0_SDA  
IOD  
IOD  
I2C Clock  
I2C Data  
A18  
B18  
B16  
B15  
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6.4.4.2 I2C1 Signal Descriptions  
Table 6-9. I2C1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
I2C1_SCL  
I2C1_SDA  
IOD  
IOD  
I2C Clock  
I2C Data  
C18  
B19  
A17  
B18  
6.4.4.3 I2C2 Signal Descriptions  
Table 6-10. I2C2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
I2C2_SCL  
I2C2_SDA  
IOD  
IOD  
I2C Clock  
I2C Data  
C13, P19  
D14, R21  
B7  
6.4.4.4 I2C3 Signal Descriptions  
Table 6-11. I2C3 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
I2C3_SCL  
I2C3_SDA  
IOD  
IOD  
I2C Clock  
I2C Data  
C17  
D17  
B14  
A15  
MCU Domain Instances  
6.4.4.5 MCU_I2C0 Signal Descriptions  
Table 6-12. MCU_I2C0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCU_I2C0_SCL  
MCU_I2C0_SDA  
IOD  
IOD  
I2C Clock  
I2C Data  
E9  
A10  
6.4.4.6 MCU_I2C1 Signal Descriptions  
Table 6-13. MCU_I2C1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCU_I2C1_SCL  
IOD  
IOD  
I2C Clock  
I2C Data  
A11  
B10  
MCU_I2C1_SDA  
6.4.5 MCAN  
MAIN Domain Instances  
6.4.5.1 MCAN0 Signal Descriptions  
Table 6-14. MCAN0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCAN0_RX  
I
MCAN Receive Data  
B17  
A14  
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Table 6-14. MCAN0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
MCAN Transmit Data  
ALV  
ALX  
TYPE  
MCAN0_TX  
O
A17  
B13  
6.4.5.2 MCAN1 Signal Descriptions  
Table 6-15. MCAN1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCAN1_RX  
I
MCAN Receive Data  
MCAN Transmit Data  
D17  
C17  
A15  
B14  
MCAN1_TX  
O
6.4.6 SPI (MCSPI)  
MAIN Domain Instances  
6.4.6.1 MCSPI0 Signal Descriptions  
Table 6-16. MCSPI0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
SPI0_CLK  
SPI0_CS0  
SPI0_CS1  
SPI0_CS2  
SPI0_CS3  
SPI0_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
D13  
D12  
C13  
B16  
A16  
A13  
A14  
B8  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
B7  
B9  
A9  
A8  
C9  
SPI0_D1  
SPI Data 1  
6.4.6.2 MCSPI1 Signal Descriptions  
Table 6-17. MCSPI1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
SPI1_CLK  
SPI1_CS0  
SPI1_CS1  
SPI1_CS2  
SPI1_CS3  
SPI1_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
C14  
B14  
D14  
D16  
E16  
B15  
A15  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
C11  
A11  
SPI1_D1  
SPI Data 1  
6.4.6.3 MCSPI2 Signal Descriptions  
Table 6-18. MCSPI2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
SPI2_CLK  
IO  
SPI Clock  
E14  
A12  
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Table 6-18. MCSPI2 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
SPI2_CS0  
SPI2_CS1  
SPI2_CS2  
SPI2_CS3  
SPI2_D0  
IO  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
E15  
C18  
B19  
A19  
D15  
C16  
B12  
A17  
B18  
A18  
B10  
B11  
IO  
IO  
IO  
IO  
SPI2_D1  
IO  
SPI Data 1  
6.4.6.4 MCSPI3 Signal Descriptions  
Table 6-19. MCSPI3 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
SPI3_CLK  
SPI3_CS0  
SPI3_CS1  
SPI3_CS2  
SPI3_CS3  
SPI3_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
U4  
U1  
N3  
E1  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
T5  
N4  
V12  
V15  
R6  
AA13  
Y14  
N1  
SPI3_D1  
SPI Data 1  
V4  
N2  
6.4.6.5 MCSPI4 Signal Descriptions  
Table 6-20. MCSPI4 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
SPI4_CLK  
SPI4_CS0  
SPI4_CS1  
SPI4_CS2  
SPI4_CS3  
SPI4_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
B16  
E16  
A17  
B17  
D18  
A16  
D16  
B9  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 0  
SPI Chip Select 2  
SPI Data 0  
A11  
B13  
A14  
A9  
SPI4_D1  
SPI Data 1  
C11  
MCU Domain Instances  
6.4.6.6 MCU_MCSPI0 Signal Descriptions  
Table 6-21. MCU_MCSPI0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
MCU_SPI0_CLK  
IO  
SPI Clock  
E6  
D6  
C6  
MCU_SPI0_CS0  
MCU_SPI0_CS1  
IO  
SPI Chip Select 0  
SPI Chip Select 1  
IO  
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Table 6-21. MCU_MCSPI0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCU_SPI0_CS2  
MCU_SPI0_CS3  
MCU_SPI0_D0  
MCU_SPI0_D1  
IO  
IO  
IO  
IO  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
D8  
B8  
E7  
B6  
D4  
SPI Data 1  
6.4.6.7 MCU_MCSPI1 Signal Descriptions  
Table 6-22. MCU_MCSPI1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
MCU_SPI1_CLK  
IO  
SPI Clock  
D7  
A7  
B7  
E8  
B9  
C7  
C8  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
MCU_SPI1_CS2  
MCU_SPI1_CS3  
MCU_SPI1_D0  
MCU_SPI1_D1  
IO  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
IO  
IO  
C2  
IO  
IO  
IO  
SPI Data 1  
6.4.7 UART  
MAIN Domain Instances  
6.4.7.1 UART0 Signal Descriptions  
Table 6-23. UART0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART0_CTSn  
I
I
UART Clear to Send (active low)  
UART Data Carrier Detect (active low)  
UART Data Set Ready (active low)  
UART Data Terminal Ready (active low)  
UART Ring Indicator  
B16  
C17  
D17  
A17  
B17  
A16  
D15  
C16  
B9  
UART0_DCDn  
UART0_DSRn  
UART0_DTRn  
UART0_RIn  
B14  
A15  
B13  
A14  
A9  
I
O
I
UART0_RTSn  
UART0_RXD  
UART0_TXD  
O
I
UART Request to Send (active low)  
UART Receive Data  
B10  
B11  
O
UART Transmit Data  
6.4.7.2 UART1 Signal Descriptions  
Table 6-24. UART1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART1_CTSn  
I
O
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
D16  
E16  
E15  
C11  
A11  
B12  
UART1_RTSn  
UART1_RXD  
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Table 6-24. UART1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
UART1_TXD  
O
UART Transmit Data  
E14  
A12  
6.4.7.3 UART2 Signal Descriptions  
Table 6-25. UART2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART2_CTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
L20, V19, Y1  
J19, T18, U2  
J20, J3, U18  
G1, J21, T19  
UART2_RTSn  
UART2_RXD  
UART2_TXD  
O
B16, K18, T20, V1, B9, K18, K4, R21,  
I
UART Receive Data  
UART Transmit Data  
W6  
Y3  
O
A16, K19, R4, U21  
A9, J4, K20, R20  
6.4.7.4 UART3 Signal Descriptions  
Table 6-26. UART3 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART3_CTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
D19, T17, V2  
C20, R3, U19  
B17, H1, U20  
C16, F2, T20  
UART3_RTSn  
UART3_RXD  
UART3_TXD  
O
AA5, D16, L21,  
U20, W1  
C11, G2, J19, U1,  
V21  
I
UART Receive Data  
UART Transmit Data  
O
AA2, E16, K21, U18 A11, J18, K2, U21  
6.4.7.5 UART4 Signal Descriptions  
Table 6-27. UART4 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART4_CTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
R16, R5, T3, V1  
R1, R17, T2, W1  
F5, H2, K4, V20  
F4, G2, H5  
UART4_RTSn  
UART4_RXD  
O
A17, L20, V20, W4, B13, J20, L1, P1,  
I
UART Receive Data  
UART Transmit Data  
Y3  
T18  
B17, J19, T1, V21,  
W5, Y4  
A14, E2, J21, P2,  
T5, U19  
UART4_TXD  
O
6.4.7.6 UART5 Signal Descriptions  
Table 6-28. UART5 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART5_CTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
W20, Y13, Y2  
T21, V12, V3  
L5, W20, Y15  
AA13, M2  
UART5_RTSn  
UART5_RXD  
O
C17, D19, P16, T6,  
Y5  
I
UART Receive Data  
B14, B17, R2, T4  
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Table 6-28. UART5 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
UART5_TXD  
O
UART Transmit Data  
C20, D17, R18, W2  
A15, C16, J2  
6.4.7.7 UART6 Signal Descriptions  
Table 6-29. UART6 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
UART6_CTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
A18, T4, W21  
B18, P17, P4  
B16, L2, Y20  
B15, E3  
UART6_RTSn  
UART6_RXD  
UART6_TXD  
O
I
C13, U6, V6, Y21  
D14, W3, Y20  
B7, R5, U2, Y18  
AA19, L3  
O
UART Transmit Data  
MCU Domain Instances  
6.4.7.8 MCU_UART0 Signal Descriptions  
Table 6-30. MCU_UART0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCU_UART0_CTSn  
MCU_UART0_RTSn  
MCU_UART0_RXD  
MCU_UART0_TXD  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
D8  
E8  
A9  
A8  
D4  
C2  
D6  
B2  
O
I
O
UART Transmit Data  
6.4.7.9 MCU_UART1 Signal Descriptions  
Table 6-31. MCU_UART1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
MCU_UART1_CTSn  
MCU_UART1_RTSn  
MCU_UART1_RXD  
MCU_UART1_TXD  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
B8  
B9  
C9  
D9  
O
I
O
UART Transmit Data  
6.4.8 MDIO  
MAIN Domain Instances  
6.4.8.1 MDIO0 Signal Descriptions  
Table 6-32. MDIO0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MDIO0_MDC  
MDIO0_MDIO  
O
MDIO Clock  
MDIO Data  
R2, Y6  
F3, W1  
D1, V2  
IO  
AA6, P5  
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6.4.9 CPSW  
MAIN Domain Instances  
6.4.9.1 CPSW3G0 Signal Descriptions  
Table 6-33. CPSW3G0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
RGMII1_RXC  
I
I
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
RMII Carrier Sense / Data Valid  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Carrier Sense / Data Valid  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Receive Data 0  
AA5, W13  
V13, W6  
U14  
U1, Y13  
U14, Y3  
W13  
RGMII1_RX_CTL  
RGMII1_TXC  
RGMII1_TX_CTL  
RGMII2_RXC  
RGMII2_RX_CTL  
RGMII2_TXC  
RGMII2_TX_CTL  
RGMII1_RD0  
RGMII1_RD1  
RGMII1_RD2  
RGMII1_RD3  
RGMII1_TD0  
RGMII1_TD1  
RGMII1_TD2  
RGMII1_TD3  
RGMII2_RD0  
RGMII2_RD1  
RGMII2_RD2  
RGMII2_RD3  
RGMII2_TD0  
RGMII2_TD1  
RGMII2_TD2  
RGMII2_TD3  
RMII1_CRS_DV  
RMII1_RX_ER  
RMII1_TX_EN  
RMII2_CRS_DV  
RMII2_RX_ER  
RMII2_TX_EN  
RMII1_RXD0  
RMII1_RXD1  
RMII1_TXD0  
RMII1_TXD1  
RMII2_RXD0  
IO  
O
I
U15  
W16  
U11  
V10  
I
W12  
Y12  
IO  
O
I
Y10  
Y8  
Y11  
V9  
AA13, W5  
U12, Y5  
V6, Y13  
V12, V5  
V15  
AA11, T5  
R2, W11  
U2, Y15  
AA13, T1  
Y14  
I
I
I
O
O
O
O
I
V14  
Y16  
W14  
U13  
AA14  
W11  
AA14  
AA10  
Y10  
I
V11  
I
AA12  
Y12  
Y11  
I
V12  
O
O
O
O
I
AA10  
V10  
Y6  
AA8  
U10  
Y9  
AA11  
W9  
R2, V12  
U15, W6  
P5, Y13  
U10  
AA13, F3  
W16, Y3  
D1, Y15  
Y9  
I
O
I
I
W12  
Y12  
O
I
Y11  
V9  
V15, W5  
V14, Y5  
V6, W14  
AA14, V5  
W11  
T5, Y14  
R2, Y16  
U13, U2  
AA14, T1  
AA10  
I
RMII Receive Data 1  
O
O
I
RMII Transmit Data 0  
RMII Transmit Data 1  
RMII Receive Data 0  
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Table 6-33. CPSW3G0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
RMII Receive Data 1  
ALV  
ALX  
RMII2_RXD1  
RMII2_TXD0  
RMII2_TXD1  
RMII_REF_CLK  
I
V11  
AA10  
Y10  
Y6  
O
O
I
RMII Transmit Data 0  
RMII Transmit Data 1  
RMII Reference Clock  
V10  
AA8  
AA5, U14  
U1, W13  
6.4.10 ECAP  
MAIN Domain Instances  
6.4.10.1 ECAP0 Signal Descriptions  
Table 6-34. ECAP0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP0_IN_APWM_OUT  
IO  
D18  
6.4.10.2 ECAP1 Signal Descriptions  
Table 6-35. ECAP1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP1_IN_APWM_OUT  
IO  
C17  
B14  
6.4.10.3 ECAP2 Signal Descriptions  
Table 6-36. ECAP2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
ECAP2_IN_APWM_OUT  
IO  
D17  
A15  
EQEP  
MAIN Domain Instances  
6.4.11.1 EQEP0 Signal Descriptions  
Table 6-37. EQEP0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EQEP0_A  
EQEP0_B  
EQEP0_I  
EQEP0_S  
I
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
D15, N16, Y2  
C16, N17, W2  
A16, R20, T6, Y5  
B16, R19, V3  
B10, L5  
B11, J2  
I
IO  
IO  
A9, R2, T4  
B9, M2  
EQEP Strobe  
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6.4.11.2 EQEP1 Signal Descriptions  
Table 6-38. EQEP1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EQEP1_A  
EQEP1_B  
EQEP1_I  
EQEP1_S  
I
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
E15, T4, W20  
E14, W21, W3  
E16, R21, U6, V6  
D16, P19, P4  
B12, L2, W20  
A12, L3, Y20  
A11, R5, U2  
C11, E3  
I
IO  
IO  
EQEP Strobe  
6.4.11.3 EQEP2 Signal Descriptions  
Table 6-39. EQEP2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EQEP2_A  
EQEP2_B  
EQEP2_I  
EQEP2_S  
I
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
C17, R5  
D17, W5, Y4  
A17, W4  
B14, F5  
A15, P2, T5  
B13, P1  
I
IO  
IO  
EQEP Strobe  
B17, R1  
A14, F4  
6.4.11 EPWM  
MAIN Domain Instances  
6.4.11.1 EPWM Signal Descriptions  
Table 6-40. EPWM Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM_SOCA  
EHRPWM_SOCB  
EHRPWM_TZn_IN0  
EHRPWM_TZn_IN1  
EHRPWM_TZn_IN2  
EHRPWM_TZn_IN3  
EHRPWM_TZn_IN4  
EHRPWM_TZn_IN5  
O
O
I
EHRPWM Start of Conversion A  
C17  
D17  
B14  
A15  
T19  
U19  
V20  
EHRPWM Start of Conversion B  
EHRPWM Trip Zone Input 0 (active low)  
EHRPWM Trip Zone Input 1 (active low)  
EHRPWM Trip Zone Input 2 (active low)  
EHRPWM Trip Zone Input 3 (active low)  
EHRPWM Trip Zone Input 4 (active low)  
EHRPWM Trip Zone Input 5 (active low)  
T18  
I
V21  
I
R16, R20  
P16  
I
I
P17, P19  
R21, Y18  
I
6.4.11.2 EPWM0 Signal Descriptions  
Table 6-41. EPWM0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM0_A  
IO  
IO  
I
EHRPWM Output A  
U20  
U18  
T20  
U21  
T18  
V21  
U21  
R21  
R20  
T19  
EHRPWM0_B  
EHRPWM Output B  
EHRPWM0_SYNCI  
EHRPWM0_SYNCO  
EHRPWM_TZn_IN0  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
EHRPWM Trip Zone Input 0 (active low)  
O
I
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6.4.11.3 EPWM1 Signal Descriptions  
Table 6-42. EPWM1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM1_A  
IO  
IO  
I
EHRPWM Output A  
U19  
V20  
V21  
T20  
T18  
U19  
EHRPWM1_B  
EHRPWM Output B  
EHRPWM_TZn_IN1  
EHRPWM Trip Zone Input 1 (active low)  
6.4.11.4 EPWM2 Signal Descriptions  
Table 6-43. EPWM2 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM2_A  
IO  
IO  
I
EHRPWM Output A  
V19  
T17  
U18  
U20  
V20  
EHRPWM2_B  
EHRPWM Output B  
EHRPWM_TZn_IN2  
EHRPWM Trip Zone Input 2 (active low)  
R16, R20  
6.4.11.5 EPWM3 Signal Descriptions  
Table 6-44. EPWM3 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM3_A  
IO  
IO  
I
EHRPWM Output A  
V18  
Y21  
Y20  
R17  
P16  
Y19  
Y18  
EHRPWM3_B  
EHRPWM Output B  
EHRPWM3_SYNCI  
EHRPWM3_SYNCO  
EHRPWM_TZn_IN3  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
EHRPWM Trip Zone Input 3 (active low)  
AA19  
O
I
6.4.11.6 EPWM4 Signal Descriptions  
Table 6-45. EPWM4 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM4_A  
IO  
IO  
I
EHRPWM Output A  
R18  
T21  
EHRPWM4_B  
EHRPWM Output B  
EHRPWM_TZn_IN4  
EHRPWM Trip Zone Input 4 (active low)  
P17, P19  
6.4.11.7 EPWM5 Signal Descriptions  
Table 6-46. EPWM5 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM5_A  
IO  
IO  
I
EHRPWM Output A  
T19  
W19  
P21  
EHRPWM5_B  
EHRPWM Output B  
EHRPWM_TZn_IN5  
EHRPWM Trip Zone Input 5 (active low)  
R21, Y18  
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6.4.11.8 EPWM6 Signal Descriptions  
Table 6-47. EPWM6 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM6_A  
IO  
IO  
I
EHRPWM Output A  
B14, N16  
A15, N17  
C14, R19  
B15, R20  
EHRPWM6_B  
EHRPWM Output B  
EHRPWM6_SYNCI  
EHRPWM6_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
O
6.4.11.9 EPWM7 Signal Descriptions  
Table 6-48. EPWM7 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM7_A  
EHRPWM7_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
P17, P5, W20  
R2, W21, Y18  
D1, W20  
F3, Y20  
6.4.11.10 EPWM8 Signal Descriptions  
Table 6-49. EPWM8 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EHRPWM8_A  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
V1, V21  
R16, W1  
K4, U19  
G2, V20  
EHRPWM8_B  
6.4.12 SERDES  
MAIN Domain Instances  
6.4.12.1 SERDES0 Signal Descriptions  
Table 6-50. SERDES0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
PCIE0_CLKREQn  
SERDES0_REXT  
IO  
A
PCIE Clock Request Signal  
D16  
T13  
C11  
External Calibration Resistor  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_TX0_N  
SERDES0_TX0_P  
IO  
IO  
I
Serdes Reference Clock Input/Output (negative)  
Serdes Reference Clock Input/Output (positive)  
SERDES Differential Receive Data (negative)  
SERDES Differential Receive Data (positive)  
SERDES Differential Transmit Data (negative)  
SERDES Differential Transmit Data (positive)  
W16  
W17  
Y15  
I
Y16  
O
O
AA16  
AA17  
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6.4.13 USB  
MAIN Domain Instances  
6.4.13.1 USB0 Signal Descriptions  
Table 6-51. USB0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
USB0_DM  
USB0_DP  
IO  
IO  
O
A
USB 2.0 Differential Data (negative)  
USB 2.0 Differential Data (positive)  
USB VBUS control output (active high)  
USB 2.0 Dual-Role Device Role Select  
Pin to connect to calibration resistor  
USB Level-shifted VBUS Input  
AA20  
AA19  
E19  
AA17  
AA16  
B19  
USB0_DRVVBUS  
USB0_ID  
U16  
U17  
T14  
Y17  
USB0_RCALIB  
USB0_VBUS  
A
W17  
V18  
A
6.4.14 OSPI  
MAIN Domain Instances  
6.4.14.1 OSPI0 Signal Descriptions  
Table 6-52. OSPI0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
OSPI0_CLK  
O
I
OSPI Clock  
N20  
N19  
L17  
N21  
L19  
L18  
K17  
L17  
M19  
M18  
M20  
M21  
P21  
P20  
N18  
M17  
L17  
K17  
P20  
P17  
OSPI0_DQS  
OSPI0_ECC_FAIL  
OSPI0_LBCLKO  
OSPI0_CSn0  
OSPI0_CSn1  
OSPI0_CSn2  
OSPI0_CSn3  
OSPI0_D0  
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI ECC Status  
I
IO  
O
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Chip Select 2 (active low)  
OSPI Chip Select 3 (active low)  
OSPI Data 0  
M21  
L20  
O
M20  
O
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
L19  
N20  
L21  
N19  
OSPI0_D1  
OSPI Data 1  
OSPI0_D2  
OSPI Data 2  
OSPI0_D3  
OSPI Data 3  
OSPI0_D4  
OSPI Data 2  
OSPI0_D5  
OSPI Data 2  
OSPI0_D6  
OSPI Data 2  
OSPI0_D7  
OSPI Data 2  
OSPI0_RESET_OUT0  
OSPI0_RESET_OUT1  
OSPI Reset  
O
OSPI Reset  
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6.4.15 GPMC  
MAIN Domain Instances  
6.4.15.1 GPMC0 Signal Descriptions  
Table 6-53. GPMC0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
GPMC Address Valid (active low) or Address Latch  
Enable  
GPMC0_ADVn_ALE  
O
P16  
GPMC0_CLK  
GPMC0_DIR  
O
O
GPMC clock  
R17  
N17  
GPMC Data Bus Signal Direction Control  
GPMC Output Enable (active low) or Read Enable  
(active low)  
GPMC0_OEn_REn  
O
R18  
GPMC0_WEn  
GPMC0_WPn  
O
O
GPMC Write Enable (active low)  
T21  
N16  
GPMC Flash Write Protect (active low)  
GPMC Address 0 Output. Only used to effectively  
address 8-bit data non-multiplexed memories  
GPMC0_A0  
GPMC0_A1  
GPMC0_A2  
GPMC0_A3  
GPMC0_A4  
GPMC0_A5  
GPMC0_A6  
GPMC0_A7  
GPMC0_A8  
GPMC0_A9  
GPMC0_A10  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
U2, U7  
AA2, V7  
T2, W7  
G1, T2  
K2, Y4  
GPMC address 1 Output in A/D non-multiplexed  
mode and Address 17 in A/D multiplexed mode  
GPMC address 2 Output in A/D non-multiplexed  
mode and Address 18 in A/D multiplexed mode  
H5, U3  
GPMC address 3 Output in A/D non-multiplexed  
mode and Address 19 in A/D multiplexed mode  
V4, W11  
U4, V11  
AA12, V1  
W1, Y12  
W12, Y4  
AA13, T6  
U11, U6  
U5, V15  
AA4, U12  
P2, V14  
P3, W14  
AA10, AA3  
AA10, N2  
N3, Y10  
K4, Y11  
G2, V12  
P2, Y12  
AA11, T4  
R5, V10  
M4, Y14  
T3, W11  
E4, Y16  
D2, U13  
K1, Y6  
GPMC address 4 Output in A/D non-multiplexed  
mode and Address 20 in A/D multiplexed mode  
GPMC address 5 Output in A/D non-multiplexed  
mode and Address 21 in A/D multiplexed mode  
GPMC address 6 Output in A/D non-multiplexed  
mode and Address 22 in A/D multiplexed mode  
GPMC address 7 Output in A/D non-multiplexed  
mode and Address 23 in A/D multiplexed mode  
GPMC address 8 Output in A/D non-multiplexed  
mode and Address 24 in A/D multiplexed mode  
GPMC address 9 Output in A/D non-multiplexed  
mode and Address 25 in A/D multiplexed mode  
GPMC address 10 Output in A/D non-multiplexed  
mode and Address 26 in A/D multiplexed mode  
GPMC address 11 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 12 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 13 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 14 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
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Table 6-53. GPMC0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
R6, V10  
T5, U10  
AA11, U1  
T4, Y11  
R5, Y10  
R21  
ALX  
AA8, N1  
N4, Y9  
E1, W9  
L2, V9  
F5, Y8  
TYPE  
GPMC address 15 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
GPMC0_A20  
GPMC0_A21  
GPMC0_A22  
OZ  
GPMC address 16 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
GPMC address 17 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 18 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 19 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 20 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 21 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
Y18  
GPMC address 22 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
N16  
GPMC Data 0 Input/Output in A/D non-multiplexed  
mode and additionally Address 1 Output in A/D  
multiplexed mode  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
R21  
R20  
T19  
V21  
U21  
T20  
T18  
U19  
U18  
GPMC Data 1 Input/Output in A/D non-multiplexed  
mode and additionally Address 2 Output in A/D  
multiplexed mode  
GPMC Data 2 Input/Output in A/D non-multiplexed  
mode and additionally Address 3 Output in A/D  
multiplexed mode  
GPMC Data 3 Input/Output in A/D non-multiplexed  
mode and additionally Address 4 Output in A/D  
multiplexed mode  
GPMC Data 4 Input/Output in A/D non-multiplexed  
mode and additionally Address 5 Output in A/D  
multiplexed mode  
GPMC Data 5 Input/Output in A/D non-multiplexed  
mode and additionally Address 6 Output in A/D  
multiplexed mode  
GPMC Data 6 Input/Output in A/D non-multiplexed  
mode and additionally Address 7 Output in A/D  
multiplexed mode  
GPMC Data 7 Input/Output in A/D non-multiplexed  
mode and additionally Address 8 Output in A/D  
multiplexed mode  
GPMC Data 8 Input/Output in A/D non-multiplexed  
mode and additionally Address 9 Output in A/D  
multiplexed mode  
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Table 6-53. GPMC0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
GPMC Data 9 Input/Output in A/D non-multiplexed  
mode and additionally Address 10 Output in A/D  
multiplexed mode  
GPMC0_AD9  
IO  
T17  
U20  
V20  
W20  
Y20  
Y19  
Y18  
AA19  
V4  
GPMC Data 10 Input/Output in A/D non-multiplexed  
mode and additionally Address 11 Output in A/D  
multiplexed mode  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_AD16  
GPMC0_AD17  
GPMC0_AD18  
GPMC0_AD19  
GPMC0_AD20  
GPMC0_AD21  
GPMC0_AD22  
GPMC0_AD23  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
R16  
W20  
W21  
V18  
Y21  
Y20  
Y7  
GPMC Data 11 Input/Output in A/D non-multiplexed  
mode and additionally Address 12 Output in A/D  
multiplexed mode  
GPMC Data 12 Input/Output in A/D non-multiplexed  
mode and additionally Address 13 Output in A/D  
multiplexed mode  
GPMC Data 13 Input/Output in A/D non-multiplexed  
mode and additionally Address 14 Output in A/D  
multiplexed mode  
GPMC Data 14 Input/Output in A/D non-multiplexed  
mode and additionally Address 15 Output in A/D  
multiplexed mode  
GPMC Data 15 Input/Output in A/D non-multiplexed  
mode and additionally Address 16 Output in A/D  
multiplexed mode  
GPMC Data 16 Input/Output in A/D non-multiplexed  
mode and additionally Address 17 Output in A/D  
multiplexed mode  
GPMC Data 17 Input/Output in A/D non-multiplexed  
mode and additionally Address 18 Output in A/D  
multiplexed mode  
U8  
W5  
GPMC Data 18 Input/Output in A/D non-multiplexed  
mode and additionally Address 19 Output in A/D  
multiplexed mode  
W8  
AA4  
Y5  
GPMC Data 19 Input/Output in A/D non-multiplexed  
mode and additionally Address 20 Output in A/D  
multiplexed mode  
V8  
GPMC Data 20 Input/Output in A/D non-multiplexed  
mode and additionally Address 21 Output in A/D  
multiplexed mode  
Y8  
AA5  
U14  
Y2  
GPMC Data 21 Input/Output in A/D non-multiplexed  
mode and additionally Address 22 Output in A/D  
multiplexed mode  
V13  
AA7  
U13  
GPMC Data 22 Input/Output in A/D non-multiplexed  
mode and additionally Address 23 Output in A/D  
multiplexed mode  
GPMC Data 23 Input/Output in A/D non-multiplexed  
mode and additionally Address 24 Output in A/D  
multiplexed mode  
V13  
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Table 6-53. GPMC0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
GPMC Data 24 Input/Output in A/D non-multiplexed  
mode and additionally Address 25 Output in A/D  
multiplexed mode  
GPMC0_AD24  
GPMC0_AD25  
GPMC0_AD26  
GPMC0_AD27  
GPMC0_AD28  
GPMC0_AD29  
GPMC0_AD30  
IO  
W13  
Y13  
GPMC Data 25 Input/Output in A/D non-multiplexed  
mode and additionally Address 26 Output in A/D  
multiplexed mode  
IO  
IO  
IO  
IO  
IO  
IO  
U15  
U14  
AA8  
U9  
W16  
W13  
V5  
GPMC Data 26 Input/Output in A/D non-multiplexed  
mode and additionally Address 27 Output in A/D  
multiplexed mode  
GPMC Data 27 Input/Output in A/D non-multiplexed  
mode and additionally Address 28 Output in A/D  
multiplexed mode  
GPMC Data 28 Input/Output in A/D non-multiplexed  
mode and additionally Address 29 Output in A/D  
multiplexed mode  
W2  
V6  
GPMC Data 29 Input/Output in A/D non-multiplexed  
mode and additionally Address 30 Output in A/D  
multiplexed mode  
W9  
GPMC Data 30 Input/Output in A/D non-multiplexed  
mode and additionally Address 31 Output in A/D  
multiplexed mode  
AA9  
AA7  
Y7  
GPMC Data 31 Input/Output in A/D non-multiplexed  
mode and additionally Address 0 Output in A/D  
multiplexed mode  
GPMC0_AD31  
IO  
O
Y9  
GPMC Lower-Byte Enable (active low) or Command  
Latch Enable  
GPMC0_BE0n_CLE  
P17  
GPMC0_BE1n  
GPMC0_BE2n  
GPMC0_BE3n  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_WAIT0  
GPMC0_WAIT1  
O
O
O
O
O
O
O
I
GPMC Upper-Byte Enable (active low)  
GPMC Upper-Byte Enable (active low)  
GPMC Upper-Byte Enable (active low)  
GPMC Chip Select 0 (active low)  
GPMC Chip Select 1 (active low)  
GPMC Chip Select 2 (active low)  
GPMC Chip Select 3 (active low)  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
T19  
V9  
P21  
W6  
AA14  
R19  
R20  
P19  
R21  
W19  
Y18  
AA14  
I
6.4.16 MMC  
MAIN Domain Instances  
6.4.16.1 MMC0 Signal Descriptions  
Table 6-54. MMC0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MMC0_CALPAD  
A
MMC/SD/SDIO Calibration Resistor  
F18  
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Table 6-54. MMC0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
MMC/SD/SDIO Clock  
ALV  
ALX  
TYPE  
MMC0_CLK  
IO  
G18  
J21  
G19  
K20  
J20  
J18  
J17  
H17  
H19  
H18  
G17  
MMC0_CMD  
MMC0_DS  
IO  
MMC/SD/SDIO Command  
MMC Data Strobe  
IO  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
IO  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
6.4.16.2 MMC1 Signal Descriptions  
Table 6-55. MMC1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MMC1_CLK  
IO  
IO  
I
MMC/SD/SDIO Clock  
MMC/SD/SDIO Command  
SD Card Detect  
L20  
J19  
D19  
C20  
K21  
L21  
K19  
K18  
J20  
J21  
B17  
C16  
J18  
J19  
K20  
K18  
MMC1_CMD  
MMC1_SDCD  
MMC1_SDWP  
MMC1_DAT0  
MMC1_DAT1  
MMC1_DAT2  
MMC1_DAT3  
I
SD Write Protect  
IO  
IO  
IO  
IO  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
6.4.17 FSITX  
MAIN Domain Instances  
6.4.17.1 FSI0 TX Signal Descriptions  
Table 6-56. FSI0 TX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_TX0_CLK  
O
O
O
FSI Clock  
FSI Data  
FSI Data  
T19  
Y21  
Y20  
P21  
Y18  
FSI_TX0_D0  
FSI_TX0_D1  
AA19  
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6.4.17.2 FSI1 TX Signal Descriptions  
Table 6-57. FSI1 TX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_TX1_CLK  
O
O
O
FSI Clock  
FSI Data  
FSI Data  
N16  
P17  
Y18  
FSI_TX1_D0  
FSI_TX1_D1  
6.4.18 FSIRX  
MAIN Domain Instances  
6.4.18.1 FSI0 RX Signal Descriptions  
Table 6-58. FSI0 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX0_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
V19  
T17  
R16  
U18  
U20  
V20  
FSI_RX0_D0  
FSI_RX0_D1  
6.4.18.2 FSI1 RX Signal Descriptions  
Table 6-59. FSI1 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX1_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
W20  
W21  
V18  
W20  
Y20  
Y19  
FSI_RX1_D0  
FSI_RX1_D1  
6.4.18.3 FSI2 RX Signal Descriptions  
Table 6-60. FSI2 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX2_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
T20  
U21  
T18  
R21  
R20  
T19  
FSI_RX2_D0  
FSI_RX2_D1  
6.4.18.4 FSI3 RX Signal Descriptions  
Table 6-61. FSI3 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX3_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
U20  
U18  
U19  
V21  
U21  
T20  
FSI_RX3_D0  
FSI_RX3_D1  
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6.4.18.5 FSI4 RX Signal Descriptions  
Table 6-62. FSI4 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX4_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
R17  
V20  
V21  
FSI_RX4_D0  
FSI_RX4_D1  
T18  
U19  
6.4.18.6 FSI5 RX Signal Descriptions  
Table 6-63. FSI5 RX Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
FSI_RX5_CLK  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
P16  
R18  
T21  
FSI_RX5_D0  
FSI_RX5_D1  
6.4.19 CPTS  
MAIN Domain Instances  
6.4.19.1 CPTS0 Signal Descriptions  
Table 6-64. CPTS0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
CPTS0_RFT_CLK  
I
O
O
I
CPTS Reference Clock  
D18  
CPTS0_TS_COMP  
CPTS0_TS_SYNC  
CPTS0_HW1TSPUSH  
CPTS0_HW2TSPUSH  
CPTS Time Stamp Counter Compare  
CPTS Time Stamp Counter Bit  
CPTS Hardware Time Stamp Push 1  
CPTS Hardware Time Stamp Push 2  
C13, W1, W7  
D14, U1, U7  
C18, V1, V7  
B19, T1, U13  
B7, G2, U3  
E1, T2  
A17, K4, Y4  
B18, E2, V13  
I
6.4.19.2 CP GEMAC CPTS0 Signal Descriptions  
Table 6-65. CP GEMAC CPTS0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
D18  
ALX  
CP_GEMAC_CPTS0_RFT_CL  
K
I
O
O
I
CPTS Reference Clock  
CP_GEMAC_CPTS0_TS_CO  
MP  
CPTS Time Stamp Counter Compare  
CPTS Time Stamp Counter Bit  
E15, K18, W1  
B16, D16, K19, U1  
E14, L21, V1  
E16, K21, T1  
B12, G2, K18  
B9, C11, E1, K20  
A12, J19, K4  
CP_GEMAC_CPTS0_TS_SYN  
C
CP_GEMAC_CPTS0_HW1TS  
PUSH  
CPTS Hardware Time Stamp Push 1  
CPTS Hardware Time Stamp Push 2  
CP_GEMAC_CPTS0_HW2TS  
PUSH  
I
A11, E2, J18  
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6.4.20 ICSSG  
MAIN Domain Instances  
6.4.20.1 PRU_ICSSG0 Signal Descriptions  
Table 6-66. PRU_ICSSG0 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
PRG0_ECAP0_IN_APWM_OU  
T
PRU-ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Ouput  
IO  
R2, U5  
F3, M4  
PRG0_ECAP0_SYNC_IN  
PRG0_ECAP0_SYNC_OUT  
I
PRU-ICSSG ECAP Sync Input  
PRU-ICSSG ECAP Sync Output  
P5, V5  
D1, T1  
T1, T3  
O
AA4, V5  
PRG0_IEP0_EDIO_OUTVALI  
D
O
I
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
C13  
V1  
B7  
K4  
E2  
G2  
E1  
Y3  
U1  
R2  
U2  
D1  
T5  
F3  
T1  
PRG0_IEP0_EDC_LATCH_IN  
0
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRG0_IEP0_EDC_LATCH_IN  
1
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
I
T1  
PRG0_IEP0_EDC_SYNC_OU  
T0  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
IO  
IO  
IO  
IO  
I
W1  
U1  
W6  
AA5  
Y5  
PRG0_IEP0_EDC_SYNC_OU  
T1  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRG0_IEP0_EDIO_DATA_IN_  
OUT28  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
PRG0_IEP0_EDIO_DATA_IN_  
OUT29  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
PRG0_IEP0_EDIO_DATA_IN_  
OUT30  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
PRG0_IEP0_EDIO_DATA_IN_  
OUT31  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
V6  
PRG0_IEP1_EDC_LATCH_IN  
0
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
P5  
PRG0_IEP1_EDC_LATCH_IN  
1
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
I
W5  
R2  
V5  
PRG0_IEP1_EDC_SYNC_OU  
T0  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
PRG0_IEP1_EDC_SYNC_OU  
T1  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRG0_MDIO0_MDC  
PRG0_MDIO0_MDIO  
PRG0_PRU0_GPI0  
PRG0_PRU0_GPI1  
PRG0_PRU0_GPI2  
PRG0_PRU0_GPI3  
PRG0_PRU0_GPI4  
PRG0_PRU0_GPI5  
O
PRU-ICSSG MDIO Clock  
P3  
P2  
D2  
E4  
J3  
IO  
PRU-ICSSG MDIO Data  
I
I
I
I
I
I
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
Y1  
R4  
U2  
V2  
J4  
G1  
H1  
K2  
F2  
AA2  
R3  
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Table 6-66. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
PRU-ICSSG PRU Data Input  
ALV  
ALX  
TYPE  
PRG0_PRU0_GPI6  
PRG0_PRU0_GPI7  
PRG0_PRU0_GPI8  
PRG0_PRU0_GPI9  
PRG0_PRU0_GPI10  
PRG0_PRU0_GPI11  
PRG0_PRU0_GPI12  
PRG0_PRU0_GPI13  
PRG0_PRU0_GPI14  
PRG0_PRU0_GPI15  
PRG0_PRU0_GPI16  
PRG0_PRU0_GPI17  
PRG0_PRU0_GPI18  
PRG0_PRU0_GPI19  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPI0  
PRG0_PRU1_GPI1  
PRG0_PRU1_GPI2  
PRG0_PRU1_GPI3  
I
I
T3  
T1  
H2  
E2  
H5  
Y3  
U1  
L1  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
I
T2  
I
W6  
AA5  
Y3  
I
I
I
AA3  
R6  
V4  
K1  
N1  
N2  
N4  
N3  
E1  
K4  
G2  
J3  
I
I
I
T5  
I
U4  
U1  
V1  
I
I
I
W1  
Y1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
R4  
U2  
V2  
J4  
G1  
H1  
K2  
F2  
H2  
E2  
H5  
Y3  
U1  
L1  
AA2  
R3  
T3  
T1  
T2  
W6  
AA5  
Y3  
AA3  
R6  
V4  
K1  
N1  
N2  
N4  
N3  
E1  
K4  
G2  
L5  
T5  
U4  
U1  
V1  
W1  
Y2  
I
W2  
V3  
J2  
I
M2  
L2  
I
T4  
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Table 6-66. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
PRU-ICSSG PRU Data Input  
ALV  
ALX  
PRG0_PRU1_GPI4  
PRG0_PRU1_GPI5  
PRG0_PRU1_GPI6  
PRG0_PRU1_GPI7  
PRG0_PRU1_GPI8  
PRG0_PRU1_GPI9  
PRG0_PRU1_GPI10  
PRG0_PRU1_GPI11  
PRG0_PRU1_GPI12  
PRG0_PRU1_GPI13  
PRG0_PRU1_GPI14  
PRG0_PRU1_GPI15  
PRG0_PRU1_GPI16  
PRG0_PRU1_GPI17  
PRG0_PRU1_GPI18  
PRG0_PRU1_GPI19  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
PRG0_PWM0_TZ_IN  
PRG0_PWM0_TZ_OUT  
I
I
W3  
P4  
R5  
W5  
R1  
Y5  
V6  
W4  
Y4  
T6  
L3  
E3  
F5  
T5  
F4  
R2  
U2  
P1  
P2  
T4  
R5  
M4  
T3  
T1  
D1  
F3  
L5  
J2  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
I
I
I
I
I
I
I
I
I
U6  
U5  
AA4  
V5  
P5  
R2  
Y2  
W2  
V3  
T4  
I
I
I
I
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
M2  
L2  
L3  
E3  
F5  
T5  
F4  
R2  
U2  
P1  
P2  
T4  
R5  
M4  
T3  
T1  
D1  
F3  
K4  
G2  
W3  
P4  
R5  
W5  
R1  
Y5  
V6  
W4  
Y4  
T6  
U6  
U5  
AA4  
V5  
P5  
R2  
V1  
W1  
O
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Table 6-66. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
PRG0_PWM1_TZ_IN  
PRG0_PWM1_TZ_OUT  
PRG0_PWM2_TZ_IN  
PRG0_PWM2_TZ_OUT  
PRG0_PWM3_TZ_IN  
PRG0_PWM3_TZ_OUT  
PRG0_PWM0_A0  
PRG0_PWM0_A1  
PRG0_PWM0_A2  
PRG0_PWM0_B0  
PRG0_PWM0_B1  
PRG0_PWM0_B2  
PRG0_PWM1_A0  
PRG0_PWM1_A1  
PRG0_PWM1_A2  
PRG0_PWM1_B0  
PRG0_PWM1_B1  
PRG0_PWM1_B2  
PRG0_PWM2_A0  
PRG0_PWM2_A1  
PRG0_PWM2_A2  
PRG0_PWM2_B0  
PRG0_PWM2_B1  
PRG0_PWM2_B2  
PRG0_PWM3_A0  
PRG0_PWM3_A1  
PRG0_PWM3_A2  
PRG0_PWM3_B0  
PRG0_PWM3_B1  
PRG0_PWM3_B2  
PRG0_RGMII1_RXC  
PRG0_RGMII1_RX_CTL  
PRG0_RGMII1_TXC  
PRG0_RGMII1_TX_CTL  
PRG0_RGMII2_RXC  
PRG0_RGMII2_RX_CTL  
PRG0_RGMII2_TXC  
PRG0_RGMII2_TX_CTL  
I
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
P5  
R2  
D1  
F3  
O
I
T18, V6  
R1, U21  
P16, W6  
R17, Y3  
AA3  
T19, U2  
F4, R20  
Y3  
O
I
O
L1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
K1  
V4  
N2  
U4  
N3  
R6  
N1  
T5  
N4  
U1  
E1  
Y4  
P2  
U6  
R5  
AA4  
T3  
T6  
T4  
U5  
M4  
V5  
T1  
U2, U20  
T2, U19  
V19, V3  
AA2, U18  
AA5, V20  
T17, W3  
V18, Y1  
R18, T3  
T19, V2  
R4, Y21  
T1, T21  
R3, W19  
T3  
G1, V21  
H5, T20  
M2, U18  
K2, U21  
T18, U1  
L3, U20  
J3, Y19  
H2  
H1, P21  
J4, Y18  
E2  
F2  
H2  
I
AA2  
K2  
IO  
O
U4  
N3  
T5  
N4  
I
R5  
F5  
I
W3  
L3  
IO  
O
AA4  
T3  
U5  
M4  
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Table 6-66. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
PRG0_RGMII1_RD0  
PRG0_RGMII1_RD1  
PRG0_RGMII1_RD2  
PRG0_RGMII1_RD3  
PRG0_RGMII1_TD0  
PRG0_RGMII1_TD1  
PRG0_RGMII1_TD2  
PRG0_RGMII1_TD3  
PRG0_RGMII2_RD0  
PRG0_RGMII2_RD1  
PRG0_RGMII2_RD2  
PRG0_RGMII2_RD3  
PRG0_RGMII2_TD0  
PRG0_RGMII2_TD1  
PRG0_RGMII2_TD2  
PRG0_RGMII2_TD3  
PRG0_UART0_CTSn  
PRG0_UART0_RTSn  
PRG0_UART0_RXD  
PRG0_UART0_TXD  
I
I
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU-ICSSG UART Clear to Send (active low)  
PRU-ICSSG UART Request to Send (active low)  
PRU-ICSSG UART Receive Data  
PRU-ICSSG UART Transmit Data  
Y1  
R4  
U2  
V2  
J3  
J4  
I
G1  
H1  
L1  
K1  
N1  
N2  
L5  
J2  
I
O
O
O
O
I
Y3  
AA3  
R6  
V4  
Y2  
I
W2  
V3  
I
M2  
L2  
P1  
P2  
T4  
R5  
Y3  
U1  
R2  
U2  
I
T4  
O
O
O
O
I
W4  
Y4  
T6  
U6  
W6  
AA5  
Y5  
O
I
O
V6  
6.4.20.2 PRU_ICSSG1 Signal Descriptions  
Table 6-67. PRU_ICSSG1 Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
PRG1_ECAP0_IN_APWM_OU  
T
PRU-ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Ouput  
IO  
V12  
AA13  
PRG1_ECAP0_SYNC_IN  
PRG1_ECAP0_SYNC_OUT  
I
PRU-ICSSG ECAP Sync Input  
PRU-ICSSG ECAP Sync Output  
Y13  
Y15  
O
AA14  
AA14  
PRG1_IEP0_EDIO_OUTVALI  
D
O
I
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
D14  
V7  
PRG1_IEP0_EDC_LATCH_IN  
0
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
Y4  
V13  
U3  
PRG1_IEP0_EDC_LATCH_IN  
1
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
I
U13  
W7  
U7  
PRG1_IEP0_EDC_SYNC_OU  
T0  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
PRG1_IEP0_EDC_SYNC_OU  
T1  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
T2  
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Table 6-67. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
U15  
U14  
V14  
W14  
Y13  
V15  
V12  
AA14  
ALX  
TYPE  
PRG1_IEP0_EDIO_DATA_IN_  
OUT28  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
IO  
W16  
W13  
Y16  
PRG1_IEP0_EDIO_DATA_IN_  
OUT29  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
IO  
IO  
IO  
I
PRG1_IEP0_EDIO_DATA_IN_  
OUT30  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
PRG1_IEP0_EDIO_DATA_IN_  
OUT31  
PRU_ICSSG Industrial Ethernet Digital I/O Data  
Input/Output  
U13  
PRG1_IEP1_EDC_LATCH_IN  
0
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
Y15  
PRG1_IEP1_EDC_LATCH_IN  
1
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
I
Y14  
PRG1_IEP1_EDC_SYNC_OU  
T0  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
AA13  
AA14  
PRG1_IEP1_EDC_SYNC_OU  
T1  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
PRG1_PRU0_GPI0  
PRG1_PRU0_GPI1  
PRG1_PRU0_GPI2  
PRG1_PRU0_GPI3  
PRG1_PRU0_GPI4  
PRG1_PRU0_GPI5  
PRG1_PRU0_GPI6  
PRG1_PRU0_GPI7  
PRG1_PRU0_GPI8  
PRG1_PRU0_GPI9  
PRG1_PRU0_GPI10  
PRG1_PRU0_GPI11  
PRG1_PRU0_GPI12  
PRG1_PRU0_GPI13  
PRG1_PRU0_GPI14  
PRG1_PRU0_GPI15  
PRG1_PRU0_GPI16  
PRG1_PRU0_GPI17  
PRG1_PRU0_GPI18  
PRG1_PRU0_GPI19  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
O
PRU-ICSSG MDIO Clock  
Y6  
AA6  
Y7  
W1  
V2  
IO  
PRU-ICSSG MDIO Data  
I
I
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
V4  
U8  
W5  
AA4  
Y5  
I
W8  
V8  
I
I
Y8  
AA5  
U14  
Y2  
I
V13  
AA7  
U13  
W13  
U15  
U14  
AA8  
U9  
I
I
V13  
Y13  
W16  
W13  
V5  
I
I
I
I
I
W2  
V6  
I
W9  
AA9  
Y9  
I
AA7  
Y7  
I
I
V9  
W6  
T2  
I
U7  
I
V7  
Y4  
I
W7  
Y7  
U3  
IO  
IO  
V4  
U8  
W5  
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Table 6-67. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU1_GPI0  
PRG1_PRU1_GPI1  
PRG1_PRU1_GPI2  
PRG1_PRU1_GPI3  
PRG1_PRU1_GPI4  
PRG1_PRU1_GPI5  
PRG1_PRU1_GPI6  
PRG1_PRU1_GPI7  
PRG1_PRU1_GPI8  
PRG1_PRU1_GPI9  
PRG1_PRU1_GPI10  
PRG1_PRU1_GPI11  
PRG1_PRU1_GPI12  
PRG1_PRU1_GPI13  
PRG1_PRU1_GPI14  
PRG1_PRU1_GPI15  
PRG1_PRU1_GPI16  
PRG1_PRU1_GPI17  
PRG1_PRU1_GPI18  
PRG1_PRU1_GPI19  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
W8  
V8  
AA4  
Y5  
Y8  
AA5  
U14  
Y2  
V13  
AA7  
U13  
W13  
U15  
U14  
AA8  
U9  
V13  
Y13  
W16  
W13  
V5  
W2  
W9  
V6  
AA9  
Y9  
AA7  
Y7  
V9  
W6  
U7  
T2  
V7  
Y4  
W7  
U3  
W11  
V11  
AA12  
Y12  
W12  
AA13  
U11  
V15  
U12  
V14  
W14  
AA10  
V10  
U10  
AA11  
Y11  
Y10  
AA14  
Y13  
V12  
AA10  
Y10  
Y11  
V12  
Y12  
AA11  
V10  
Y14  
W11  
Y16  
U13  
Y6  
I
I
I
I
I
I
I
I
I
I
I
I
AA8  
Y9  
I
I
W9  
I
V9  
I
Y8  
I
AA14  
Y15  
AA13  
I
I
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Table 6-67. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO19  
PRG1_PWM0_TZ_IN  
PRG1_PWM0_TZ_OUT  
PRG1_PWM1_TZ_IN  
PRG1_PWM1_TZ_OUT  
PRG1_PWM2_TZ_IN  
PRG1_PWM2_TZ_OUT  
PRG1_PWM3_TZ_IN  
PRG1_PWM3_TZ_OUT  
PRG1_PWM0_A0  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
W11  
V11  
AA10  
Y10  
Y11  
V12  
Y12  
AA11  
V10  
Y14  
W11  
Y16  
U13  
Y6  
AA12  
Y12  
W12  
AA13  
U11  
V15  
U12  
V14  
W14  
AA10  
V10  
AA8  
Y9  
U10  
AA11  
Y11  
W9  
V9  
Y10  
Y8  
AA14  
Y13  
AA14  
Y15  
AA13  
Y4  
V12  
V7  
O
W7  
U3  
I
Y13  
Y15  
AA13  
U13  
W11  
W16  
V5  
O
V12  
I
P19, W14  
R20, U12  
U15  
AA8  
U9  
O
I
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
W2  
PRG1_PWM0_A1  
AA9  
V9  
AA7  
W6  
PRG1_PWM0_A2  
PRG1_PWM0_B0  
W9  
V6  
PRG1_PWM0_B1  
Y9  
Y7  
PRG1_PWM0_B2  
U7  
T2  
PRG1_PWM1_A0  
V10  
AA8  
W9  
PRG1_PWM1_A1  
AA11  
Y10  
PRG1_PWM1_A2  
Y8  
PRG1_PWM1_B0  
U10  
Y9  
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Table 6-67. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
PRU_ICSSG PWM Output B  
ALV  
ALX  
PRG1_PWM1_B1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
Y11  
AA14  
N16, W8  
P17, W13  
AA12, V21  
N17, Y8  
U14, Y18  
R16, W12  
Y7  
V9  
AA14  
AA4  
Y13  
U19, Y11  
AA5  
W13  
V20, Y12  
V4  
PRG1_PWM1_B2  
PRU_ICSSG PWM Output B  
PRG1_PWM2_A0  
PRU_ICSSG PWM Output A  
PRG1_PWM2_A1  
PRU_ICSSG PWM Output A  
PRG1_PWM2_A2  
PRU_ICSSG PWM Output A  
PRG1_PWM2_B0  
PRU_ICSSG PWM Output B  
PRG1_PWM2_B1  
PRU_ICSSG PWM Output B  
PRG1_PWM2_B2  
PRU_ICSSG PWM Output B  
PRG1_PWM3_A0  
PRU_ICSSG PWM Output A  
PRG1_PWM3_A1  
PRU_ICSSG PWM Output A  
AA7  
Y2  
PRG1_PWM3_A2  
PRU_ICSSG PWM Output A  
V8  
Y5  
PRG1_PWM3_B0  
PRU_ICSSG PWM Output B  
U8  
W5  
PRG1_PWM3_B1  
PRU_ICSSG PWM Output B  
U13  
V13  
U14  
Y2  
PRG1_PWM3_B2  
PRU_ICSSG PWM Output B  
V13  
PRG1_RGMII1_RXC  
PRG1_RGMII1_RX_CTL  
PRG1_RGMII1_TXC  
PRG1_RGMII1_TX_CTL  
PRG1_RGMII2_RXC  
PRG1_RGMII2_RX_CTL  
PRG1_RGMII2_TXC  
PRG1_RGMII2_TX_CTL  
PRG1_RGMII1_RD0  
PRG1_RGMII1_RD1  
PRG1_RGMII1_RD2  
PRG1_RGMII1_RD3  
PRG1_RGMII1_TD0  
PRG1_RGMII1_TD1  
PRG1_RGMII1_TD2  
PRG1_RGMII1_TD3  
PRG1_RGMII2_RD0  
PRG1_RGMII2_RD1  
PRG1_RGMII2_RD2  
PRG1_RGMII2_RD3  
PRG1_RGMII2_TD0  
PRG1_RGMII2_TD1  
PRG1_RGMII2_TD2  
PRG1_RGMII2_TD3  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
AA7  
I
Y8  
AA5  
W6  
IO  
O
I
V9  
Y9  
Y7  
U11  
V10  
Y12  
Y8  
I
W12  
Y10  
IO  
O
I
Y11  
V9  
Y7  
V4  
I
U8  
W5  
I
W8  
AA4  
Y5  
I
V8  
O
O
O
O
I
AA8  
V5  
U9  
W2  
W9  
V6  
AA9  
AA7  
AA10  
Y10  
Y11  
V12  
Y6  
W11  
V11  
I
I
AA12  
Y12  
I
O
O
O
O
AA10  
V10  
AA8  
Y9  
U10  
AA11  
W9  
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Table 6-67. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
PRG1_UART0_CTSn  
PRG1_UART0_RTSn  
PRG1_UART0_RXD  
PRG1_UART0_TXD  
I
PRU-ICSSG UART Clear to Send (active low)  
PRU-ICSSG UART Request to Send (active low)  
PRU-ICSSG UART Receive Data  
U15  
U14  
V14  
W14  
W16  
W13  
Y16  
U13  
O
I
O
PRU-ICSSG UART Transmit Data  
6.4.21 DMTIMER  
MAIN Domain Instances  
6.4.21.1 DMTIMER Signal Descriptions  
Table 6-68. DMTIMER Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
C18, K18  
B19, K19  
A17, L21  
B17, K21  
C17, L20  
D17, J19  
B16, D19, T1  
A16, C20, U7  
P19, V7  
ALX  
A17, K18  
B18, K20  
B13, J19  
A14, J18  
B14, J20  
A15, J21  
B17, B9, E2  
A9, C16, T2  
Y4  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO1  
TIMER_IO2  
TIMER_IO3  
TIMER_IO4  
TIMER_IO5  
TIMER_IO6  
TIMER_IO7  
TIMER_IO8  
TIMER_IO9  
TIMER_IO10  
TIMER_IO11  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
R21, W7  
U3  
Timer Inputs and Outputs (not tied to single timer  
instance)  
C13, U13  
D14, U1  
B7, V13  
E1  
Timer Inputs and Outputs (not tied to single timer  
instance)  
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MCU Domain Instances  
6.4.21.2 MCU_DMTIMER Signal Descriptions  
Table 6-69. MCU_DMTIMER Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
D8  
E8  
ALX  
D4  
TYPE  
Timer Inputs and Outputs (not tied to single timer  
instance)  
MCU_TIMER_IO0  
MCU_TIMER_IO1  
MCU_TIMER_IO2  
MCU_TIMER_IO3  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
IO  
IO  
IO  
C2  
Timer Inputs and Outputs (not tied to single timer  
instance)  
B8  
Timer Inputs and Outputs (not tied to single timer  
instance)  
B9  
6.4.22 TRACE  
MAIN Domain Instances  
6.4.22.1 Trace Signal Descriptions  
Table 6-70. Trace Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
TRC_CLK  
TRC_CTL  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Clock  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
Y21  
Y20  
R17  
P16  
R18  
T21  
P17  
T19  
R21  
R20  
T19  
V21  
U21  
T20  
T18  
U19  
U18  
U20  
V20  
W20  
Y20  
Y19  
Y18  
AA19  
Trace Control  
Trace Data 0  
Trace Data 1  
Trace Data 2  
Trace Data 3  
Trace Data 4  
Trace Data 5  
Trace Data 6  
Trace Data 7  
Trace Data 8  
Trace Data 9  
Trace Data 10  
Trace Data 11  
Trace Data 12  
Trace Data 13  
Trace Data 14  
Trace Data 15  
Trace Data 16  
Trace Data 17  
Trace Data 18  
Trace Data 19  
TRC_DATA0  
TRC_DATA1  
TRC_DATA2  
TRC_DATA3  
TRC_DATA4  
TRC_DATA5  
TRC_DATA6  
TRC_DATA7  
TRC_DATA8  
TRC_DATA9  
TRC_DATA10  
TRC_DATA11  
TRC_DATA12  
TRC_DATA13  
TRC_DATA14  
TRC_DATA15  
TRC_DATA16  
TRC_DATA17  
TRC_DATA18  
TRC_DATA19  
P21  
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Table 6-70. Trace Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
TRC_DATA20  
O
Trace Data 20  
Trace Data 21  
Trace Data 22  
Trace Data 23  
W19  
Y18  
N16  
R19  
TRC_DATA21  
TRC_DATA22  
TRC_DATA23  
O
O
O
6.4.23 JTAG  
MAIN Domain Instances  
6.4.23.1 JTAG Signal Descriptions  
Table 6-71. JTAG Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
EMU0  
EMU1  
TCK  
IO  
Emulation Control 0  
Emulation Control 1  
JTAG Test Clock Input  
JTAG Test Data Input  
JTAG Test Data Output  
JTAG Test Mode Select Input  
JTAG Reset  
D10  
E10  
B11  
C11  
A12  
C12  
D11  
C5  
B3  
C6  
A3  
B5  
B4  
B6  
IO  
I
TDI  
I
TDO  
OZ  
TMS  
I
I
TRSTn  
6.4.24 SYSBOOT  
MAIN Domain Instances  
6.4.24.1 Sysboot Signal Descriptions  
Table 6-72. Sysboot Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
BOOTMODE00  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode pin 0  
Bootmode pin 1  
Bootmode pin 2  
Bootmode pin 3  
Bootmode pin 4  
Bootmode pin 5  
Bootmode pin 6  
Bootmode pin 7  
Bootmode pin 8  
Bootmode pin 9  
Bootmode pin 10  
Bootmode pin 11  
Bootmode pin 12  
Bootmode pin 13  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
R21  
R20  
T19  
V21  
U21  
T20  
T18  
U19  
U18  
U20  
V20  
W20  
Y20  
Y19  
BOOTMODE01  
BOOTMODE02  
BOOTMODE03  
BOOTMODE04  
BOOTMODE05  
BOOTMODE06  
BOOTMODE07  
BOOTMODE08  
BOOTMODE09  
BOOTMODE10  
BOOTMODE11  
BOOTMODE12  
BOOTMODE13  
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Table 6-72. Sysboot Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
BOOTMODE14  
BOOTMODE15  
I
I
Bootmode pin 14  
Bootmode pin 15  
Y21  
Y20  
Y18  
AA19  
6.4.25 SYSTEM  
MAIN Domain Instances  
6.4.25.1 System Signal Descriptions  
Table 6-73. System Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
RMII Clock Output (50 MHz). This pin is used for  
clock source to the external PHY and must be routed  
back to the RMII_REF_CLK pin for proper device  
operation.  
CLKOUT0  
EXTINTn  
O
I
A19, U13  
C19  
A18, V13  
External Interrupt  
External clock input to Main Domain, routed to Timer  
clock muxes as one of the selectable input clock  
sources for Timer/WDT modules, or as reference  
clock to MAIN_PLL2 (PER1 PLL)  
EXT_REFCLK1  
I
A19  
A18  
A15  
GPMC functional clock output selected through a  
mux logic  
GPMC0_FCLK_MUX  
OBSCLK0  
O
O
R17  
D17  
Observation clock output for test and debug  
purposes only  
PORz_OUT  
O
O
I
Main Domain POR status output  
E17  
F16  
E18  
D18  
A19  
A17  
B17  
D18  
E19  
C17  
RESETSTATz  
RESET_REQz  
SYNC0_OUT  
SYNC1_OUT  
SYNC2_OUT  
SYNC3_OUT  
Main Domain warm reset status output  
Main Domain external warm reset request input  
CPTS Time Stamp Generator Bit 0  
CPTS Time Stamp Generator Bit 1  
CPTS Time Stamp Generator Bit 2  
CPTS Time Stamp Generator Bit 3  
O
O
O
O
A18  
B13  
A14  
SYSCLK0 output from Main PLL controller (divided  
by 6) for test and debug purposes only  
SYSCLKOUT0  
O
C17  
B14  
MCU Domain Instances  
6.4.25.2 MCU System Signal Descriptions  
Table 6-74. MCU System Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
External system clock input  
ALV  
B7  
ALX  
TYPE  
MCU_EXT_REFCLK0  
MCU_OBSCLK0  
I
Observation clock output for test and debug  
purposes only  
O
C6, E10  
B3  
MCU_PORz  
I
MCU Domain cold reset  
B21  
B13  
C20  
A6  
MCU_RESETSTATz  
O
MCU Domain warm reset status output  
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Table 6-74. MCU System Signal Descriptions (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
MCU Domain warm reset  
ALV  
ALX  
TYPE  
MCU_RESETz  
I
B12  
A20  
A5  
MCU_SAFETY_ERRORn  
MCU_SYSCLKOUT0  
IO  
Error signal output from MCU Domain ESM  
B20  
MCU Domain system clock output for test and debug  
purposes only  
O
C6  
6.4.26 CLOCK  
MCU Domain Instances  
6.4.26.1 MCU Clock Signal Descriptions  
Table 6-75. MCU Clock Signal Descriptions  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
MCU_OSC0_XI  
I
High frequency oscillator input  
High frequency oscillator output  
C21  
B20  
D20  
C21  
MCU_OSC0_XO  
O
6.4.27 VMON  
6.4.27.1 VMON Signal Description  
Table 6-76. VMON Signal Description  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
A
A
A
A
Voltage monitor input for 1.8 V MCU power supply  
Voltage monitor input for 1.8 V SoC power supply  
Voltage monitor input for 3.3 V MCU power supply  
Voltage monitor input for 3.3 V SoC power supply  
K16  
E12  
F13  
F14  
F14  
E15  
Voltage monitor input, fixed 0.45 V (+/-3%)  
threshold. Use with external precision voltage divider  
to monitor a higher voltage rail such as the PMIC  
input supply.  
VMON_VSYS  
A
K10  
G13  
6.4.28 Power Supply  
6.4.28.1 Power Supply Signal Description  
Table 6-77. Power Supply Signal Description  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP_VDDS0  
External capacitor connection for IO group 0  
External capacitor connection for IO group 1  
External capacitor connection for IO group 2  
External capacitor connection for IO group 3  
External capacitor connection for IO group 4  
External capacitor connection for IO group 5  
External capacitor connection for MMC1  
External capacitor connection for IO MCU  
H12  
T7  
D12  
N5  
CAP_VDDS1  
CAP_VDDS2  
R11  
N14  
M16  
L13  
K15  
H10  
U9  
CAP_VDDS3  
R16  
N18  
M18  
J17  
D9  
CAP_VDDS4  
CAP_VDDS5  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
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Table 6-77. Power Supply Signal Description (continued)  
SIGNAL  
NAME  
SIGNAL  
TYPE  
DESCRIPTION  
ALV  
ALX  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_ADC  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
SERDES0 0.85 V analog supply  
SERDES0 clock 0.85 V analog supply  
USB0 0.85 V analog supply  
SERDES0 1.8 V analog supply  
USB0 1.8 V analog supply  
P12, P13  
P11  
T12  
R14  
R15  
H15  
R13  
J13  
V16  
U15  
K15  
SDIO 3.3 V analog supply  
USB0 3.3 V analog supply  
U16  
ADC0 analog supply  
G17, H17  
H14  
VDDA_MCU  
POR and MCU PLL analog supply  
Main, PER1, and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
K12  
N12  
H9  
VDDA_PLL0  
N12  
VDDA_PLL1  
G9  
VDDA_PLL2  
J11  
G12  
VDDA_TEMP0  
TEMP0 analog supply  
G11  
L11  
G11  
VDDA_TEMP1  
TEMP1 analog supply  
M11  
G5, G6, J10, J12,  
P14, P8, R10  
VDDR_CORE  
PWR  
RAM supply  
L10, M13  
VDDSHV0  
VDDSHV1  
PWR  
PWR  
IO supply for IO group 0  
IO supply for IO group 1  
F11, G12, G14  
M7, N6, P7  
C13, D13, E14  
L6, M6, P5, P6  
T11, T8, U11, U7,  
U8  
VDDSHV2  
PWR  
IO supply for IO group 2  
R10, R8, T9  
VDDSHV3  
PWR  
PWR  
PWR  
PWR  
IO supply for IO group 3  
IO supply for IO group 4  
IO supply for IO group 5  
IO supply for IO MCU  
P14, P15  
M14, M15  
L14, L15  
R17, T17  
N16, N17  
L16, L17  
VDDSHV4  
VDDSHV5  
VDDSHV_MCU  
F9, G10, G8  
E7, E8, E9  
F7, G6, H7, J6, K7,  
L6  
VDDS_DDR  
PWR  
DDR PHY IO supply  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
PWR  
PWR  
PWR  
DDR clock IO supply  
MMC0 PHY IO supply  
MCU_OSC0 supply  
J8  
J15, K14  
H13  
F18  
F11, G10, H15, H8,  
J9, K11, K14, L13,  
L9, M14, M8, N10,  
N9, R12, R13, R9  
J10, J12, K11, K9,  
L12, L8, M11, M9,  
N10, N8, P9  
VDD_CORE  
PWR  
Core supply  
VDD_DLL_MMC0  
VDD_MMC0  
VPP  
PWR  
PWR  
PWR  
MMC0 PLL analog supply  
MMC0 PHY core supply  
H14  
K13  
G15  
eFuse ROM programming supply  
E16  
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Table 6-77. Power Supply Signal Description (continued)  
SIGNAL  
NAME  
SIGNAL  
DESCRIPTION  
ALV  
ALX  
TYPE  
A1, A21, A5, A6,  
AA1, AA15, AA18,  
AA21, C10, C15,  
C3, D1, E11, E13,  
F10, F15, F8, G1,  
G16, G3, G7, G9,  
H11, H20, H21, H6,  
H8, J14, J16, J7,  
J9, K6, K8, L1, L16,  
L3, L7, L9, M10,  
M12, M6, M8, N11,  
N13, N15, N7, N9,  
P1, P10, P18, P6,  
P8, R12, R7, R9,  
T10, T11, T15, T16,  
T8, U3, V17, W10,  
W18, Y14, Y17,  
Y19  
A1, A2, A20, A21,  
AA1, AA2, AA20,  
AA21, B1, B21,  
D10, D16, D17,  
E11, E13, E6, F17,  
F8, G16, H16, H6,  
H7, J11, J16, J5,  
J6, K16, K6, K7, K8,  
L10, L11, L12, M15,  
M16, M7, N11, N13,  
N6, P11, P15, P16,  
P7, R11, R6, T14,  
U6, Y1, Y21  
VSS  
GND  
Ground  
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6.5 Pin Multiplexing  
Table 6-78. Pin Multiplexing  
MUX MODE SETTINGS  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
[Bootstrap:0]  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
P20  
M21  
N20  
N21  
PADCONFIG_0  
PADCONFIG_1  
0x000F4000  
OSPI0_CLK  
GPIO0_0  
GPIO0_1  
0x000F4004 OSPI0_LBCLK  
O
P17  
L19  
N20  
L21  
N19  
N19  
M19  
M18  
M20  
M21  
P21  
P20  
N18  
M17  
L19  
PADCONFIG_2  
PADCONFIG_3  
PADCONFIG_4  
PADCONFIG_5  
PADCONFIG_6  
PADCONFIG_7  
PADCONFIG_8  
PADCONFIG_9  
PADCONFIG_10  
PADCONFIG_11  
PADCONFIG_12  
PADCONFIG_13  
0x000F4008  
0x000F400C  
0x000F4010  
0x000F4014  
0x000F4018  
0x000F401C  
0x000F4020  
0x000F4024  
0x000F4028  
0x000F402C  
0x000F4030  
0x000F4034  
OSPI0_DQS  
OSPI0_D0  
OSPI0_D1  
OSPI0_D2  
OSPI0_D3  
OSPI0_D4  
OSPI0_D5  
OSPI0_D6  
OSPI0_D7  
OSPI0_CSn0  
OSPI0_CSn1  
OSPI0_CSn2  
GPIO0_2  
GPIO0_3  
GPIO0_4  
GPIO0_5  
GPIO0_6  
GPIO0_7  
GPIO0_8  
GPIO1*  
GPIO0_10  
GPIO0_11  
GPIO0_12  
GPIO0_13  
L20  
M20  
L18  
K17  
OSPI0_RES  
ET_OUT1  
L17  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
T17  
R16  
W20  
PADCONFIG_14  
PADCONFIG_15  
PADCONFIG_16  
PADCONFIG_17  
PADCONFIG_18  
PADCONFIG_19  
PADCONFIG_20  
PADCONFIG_21  
PADCONFIG_22  
PADCONFIG_23  
PADCONFIG_24  
PADCONFIG_25  
PADCONFIG_26  
0x000F4038  
0x000F403C  
0x000F4040  
0x000F4044  
0x000F4048  
0x000F404C  
0x000F4050  
0x000F4054  
0x000F4058  
0x000F405C  
0x000F4060  
OSPI0_CSn3 OSPI0_RES OSPI0_ECC_  
ET_OUT0 FAIL  
GPIO0_14  
GPIO0_15  
GPIO0_16  
R21  
R20  
T19  
V21  
U21  
T20  
T18  
U19  
U18  
U20  
V20  
W20  
GPMC0_AD0 FSI_RX2_CL UART2_RXD EHRPWM0_  
SYNCI  
TRC_CLK  
TRC_CTL  
BOOTMODE  
00  
K
GPMC0_AD1 FSI_RX2_D0 UART2_TXD EHRPWM0_  
SYNCO  
PRG0_PWM  
2_TZ_OUT  
BOOTMODE  
01  
GPMC0_AD2 FSI_RX2_D1 UART2_RTS EHRPWM_T  
TRC_DATA0 GPIO0_17  
TRC_DATA1 GPIO0_18  
TRC_DATA2 GPIO0_82  
TRC_DATA3 GPIO0_83  
TRC_DATA4 GPIO0_21  
TRC_DATA5 GPIO0_22  
TRC_DATA6 GPIO0_23  
TRC_DATA7 GPIO0_24  
TRC_DATA8 GPIO0_25  
PRG0_PWM  
2_TZ_IN  
BOOTMODE  
02  
n
Zn_IN0  
GPMC0_AD3 FSI_RX3_CL UART3_RXD EHRPWM0_  
PRG0_PWM  
2_A0  
BOOTMODE  
03  
K
A
GPMC0_AD4 FSI_RX3_D0 UART3_TXD EHRPWM0_  
B
PRG0_PWM  
2_B0  
BOOTMODE  
04  
GPMC0_AD5 FSI_RX3_D1 UART3_RTS EHRPWM1_  
PRG0_PWM  
2_A1  
BOOTMODE  
05  
n
A
GPMC0_AD6 FSI_RX4_D0 UART4_RXD EHRPWM1_  
B
PRG0_PWM  
2_B1  
BOOTMODE  
06  
GPMC0_AD7 FSI_RX4_D1 UART4_TXD EHRPWM_T EHRPWM8_  
PRG1_PWM  
2_A2  
BOOTMODE  
07  
Zn_IN1  
A
GPMC0_AD8 FSI_RX0_CL UART2_CTS EHRPWM2_  
PRG0_PWM  
2_A2  
BOOTMODE  
08  
K
n
A
GPMC0_AD9 FSI_RX0_D0 UART3_CTS EHRPWM2_  
PRG0_PWM  
2_B2  
BOOTMODE  
09  
n
B
0x000F4064 GPMC0_AD10 FSI_RX0_D1 UART4_CTS EHRPWM_T EHRPWM8_  
PRG1_PWM  
2_B2  
BOOTMODE  
10  
n
Zn_IN2  
B
0x000F4068 GPMC0_AD11 FSI_RX1_CL UART5_CTS  
EQEP1_A  
TRC_DATA9 GPIO0_26 EHRPWM7_  
A
BOOTMODE  
11  
K
n
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
Y20  
W21  
PADCONFIG_27  
PADCONFIG_28  
PADCONFIG_29  
PADCONFIG_30  
PADCONFIG_31  
PADCONFIG_33  
PADCONFIG_34  
PADCONFIG_35  
PADCONFIG_36  
PADCONFIG_37  
PADCONFIG_38  
PADCONFIG_39  
PADCONFIG_40  
PADCONFIG_41  
PADCONFIG_42  
PADCONFIG_43  
PADCONFIG_44  
PADCONFIG_45  
PADCONFIG_46  
PADCONFIG_47  
PADCONFIG_48  
PADCONFIG_49  
PADCONFIG_50  
0x000F406C GPMC0_AD12 FSI_RX1_D0 UART6_CTS  
n
EQEP1_B  
TRC_DATA1 GPIO0_27 EHRPWM7_  
BOOTMODE  
12  
0
B
Y19  
Y18  
V18  
Y21  
Y20  
R17  
P16  
R18  
T21  
P17  
T19  
W19  
Y18  
N16  
N17  
R19  
R20  
P19  
R21  
Y7  
0x000F4070 GPMC0_AD13 FSI_RX1_D1  
EHRPWM3_  
A
TRC_DATA11 GPIO0_28  
PRG0_PWM  
3_A0  
BOOTMODE  
13  
0x000F4074 GPMC0_AD14 FSI_TX0_D0 UART6_RXD EHRPWM3_  
B
TRC_DATA1 GPIO0_29  
2
PRG0_PWM  
3_B0  
BOOTMODE  
14  
AA19  
0x000F4078 GPMC0_AD15 FSI_TX0_D1 UART6_TXD EHRPWM3_  
SYNCI  
TRC_DATA1 GPIO0_30  
3
BOOTMODE  
15  
0x000F407C  
GPMC0_CLK FSI_RX4_CL UART4_RTS EHRPWM3_ GPMC0_FCL  
SYNCO K_MUX  
TRC_DATA1 GPIO0_31  
4
PRG0_PWM  
3_TZ_OUT  
K
n
0x000F4084  
GPMC0_ADV FSI_RX5_CL UART5_RXD EHRPWM_T  
n_ALE Zn_IN3  
TRC_DATA1 GPIO0_32  
5
PRG0_PWM  
3_TZ_IN  
K
0x000F4088 GPMC0_OEn_ FSI_RX5_D0 UART5_TXD EHRPWM4_  
REn  
TRC_DATA1 GPIO0_33  
6
PRG0_PWM  
3_A1  
A
0x000F408C GPMC0_WEn FSI_RX5_D1 UART5_RTS EHRPWM4_  
TRC_DATA1 GPIO0_34  
7
PRG0_PWM  
3_B1  
n
B
0x000F4090 GPMC0_BE0n FSI_TX1_D0 UART6_RTS EHRPWM_T  
EHRPWM7_ TRC_DATA1 GPIO0_35  
PRG1_PWM  
2_A1  
_CLE  
n
Zn_IN4  
A
8
P21  
0x000F4094 GPMC0_BE1n FSI_TX0_CL  
K
EHRPWM5_  
A
TRC_DATA1 GPIO0_36  
9
PRG0_PWM  
3_A2  
0x000F4098 GPMC0_WAIT  
0
EHRPWM5_  
B
TRC_DATA2 GPIO0_37  
0
PRG0_PWM  
3_B2  
0x000F409C GPMC0_WAIT FSI_TX1_D1  
1
EHRPWM_T GPMC0_A21 EHRPWM7_ TRC_DATA2 GPIO0_38  
Zn_IN5  
PRG1_PWM  
2_B1  
B
1
0x000F40A0 GPMC0_WPn FSI_TX1_CL  
K
EQEP0_A  
GPMC0_A22  
TRC_DATA2 GPIO0_39 EHRPWM6_ PRG1_PWM  
2_A0  
2
A
0x000F40A4  
GPMC0_DIR  
EQEP0_B  
EQEP0_S  
EQEP0_I  
EQEP1_S  
EQEP1_I  
GPIO0_40 EHRPWM6_ PRG1_PWM  
2_B0  
B
0x000F40A8 GPMC0_CSn0  
0x000F40AC GPMC0_CSn1  
0x000F40B0 GPMC0_CSn2  
0x000F40B4 GPMC0_CSn3  
TRC_DATA2 GPIO0_41 EHRPWM6_  
SYNCI  
3
EHRPWM_T  
Zn_IN2  
GPIO0_42 EHRPWM6_ PRG1_PWM  
SYNCO  
2_TZ_OUT  
I2C2_SCL  
I2C2_SDA  
TIMER_IO8  
TIMER_IO9  
EHRPWM_T  
Zn_IN4  
GPIO0_43  
GPIO0_44  
PRG1_PWM  
2_TZ_IN  
GPMC0_A20 EHRPWM_T  
Zn_IN5  
V4  
W5  
AA4  
Y5  
0x000F40B8 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO0 _GPI0 1_RD0 3_A0  
GPIO0_45 GPMC0_AD1  
6
U8  
0x000F40BC PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO1 _GPI1 1_RD1 3_B0  
GPIO0_46 GPMC0_AD1  
7
W8  
0x000F40C0 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO2 _GPI2 1_RD2 2_A0  
GPIO0_47 GPMC0_AD1  
8
V8  
0x000F40C4 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO3 _GPI3 1_RD3 3_A2  
GPIO0_48 GPMC0_AD1  
9
AA5  
Y8  
0x000F40C8 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO4 _GPI4 1_RX_CTL 2_B0  
GPIO0_49 GPMC0_AD2  
0
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
U14  
V13  
PADCONFIG_51  
PADCONFIG_52  
PADCONFIG_53  
0x000F40CC PRG1_PRU0_ PRG1_PRU0  
GPO5 _GPI5  
PRG1_PWM RGMII1_RX_  
3_B2 CTL  
GPIO0_50 GPMC0_AD2  
1
Y2  
AA7  
U13  
0x000F40D0 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO6 _GPI6 1_RXC 3_A1  
GPIO0_51 GPMC0_AD2  
2
V13  
0x000F40D4 PRG1_PRU0_ PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_HW2  
CLKOUT0  
TIMER_IO10 GPIO0_52 GPMC0_AD2  
3
GPO7  
_GPI7  
EDC_LATCH  
_IN1  
3_B1  
TSPUSH  
Y13  
W13  
U15  
PADCONFIG_54  
PADCONFIG_55  
0x000F40D8 PRG1_PRU0_ PRG1_PRU0  
GPO8 _GPI8  
PRG1_PWM RGMII1_RXC  
2_A1  
GPIO0_53 GPMC0_AD2  
4
W16  
0x000F40DC PRG1_PRU0_ PRG1_PRU0 PRG1_UART PRG1_PWM RGMII1_TX_ RMII1_RX_E PRG1_IEP0_ GPIO0_54 GPMC0_AD2  
GPO9  
_GPI9  
0_CTSn  
3_TZ_IN  
CTL  
R
EDIO_DATA_  
IN_OUT28  
5
W13  
U14  
PADCONFIG_56  
0x000F40E0 PRG1_PRU0_ PRG1_PRU0 PRG1_UART PRG1_PWM RGMII1_TXC RMII_REF_C PRG1_IEP0_ GPIO0_55 GPMC0_AD2  
GPO10  
_GPI10  
0_RTSn  
2_B1  
LK  
EDIO_DATA_  
IN_OUT29  
6
V5  
W2  
V6  
AA8  
U9  
PADCONFIG_57  
PADCONFIG_58  
PADCONFIG_59  
PADCONFIG_60  
PADCONFIG_61  
PADCONFIG_62  
PADCONFIG_63  
0x000F40E4 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO11 _GPI11 1_TD0 3_TZ_OUT  
GPIO0_56 GPMC0_AD2  
7
0x000F40E8 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO12 _GPI12 1_TD1 0_A0  
GPIO0_57 GPMC0_AD2  
8
W9  
AA9  
Y9  
0x000F40EC PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO13 _GPI13 1_TD2 0_B0  
GPIO0_58 GPMC0_AD2  
9
AA7  
Y7  
0x000F40F0 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO14 _GPI14 1_TD3 0_A1  
GPIO0_59 GPMC0_AD3  
0
0x000F40F4 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO15 _GPI15 1_TX_CTL 0_B1  
GPIO0_60 GPMC0_AD3  
1
W6  
T2  
V9  
0x000F40F8 PRG1_PRU0_ PRG1_PRU0 PRG1_RGMII PRG1_PWM  
GPO16 _GPI16 1_TXC 0_A2  
GPIO0_61 GPMC0_BE2  
n
U7  
0x000F40FC PRG1_PRU0_ PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_TS_  
TIMER_IO7 GPIO0_62 GPMC0_A0  
TIMER_IO8 GPIO0_63 GPMC0_A1  
TIMER_IO9 GPIO0_64 GPMC0_A2  
GPO17  
_GPI17  
EDC_SYNC_  
OUT1  
0_B2  
SYNC  
Y4  
U3  
V7  
PADCONFIG_64  
PADCONFIG_65  
0x000F4100 PRG1_PRU0_ PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_HW1  
GPO18  
_GPI18  
EDC_LATCH  
_IN0  
0_TZ_IN  
TSPUSH  
W7  
0x000F4104 PRG1_PRU0_ PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_TS_  
GPO19  
_GPI19  
EDC_SYNC_ 0_TZ_OUT  
OUT0  
COMP  
AA10  
Y10  
W11  
V11  
PADCONFIG_66  
PADCONFIG_67  
PADCONFIG_68  
PADCONFIG_69  
PADCONFIG_70  
PADCONFIG_71  
0x000F4108 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII  
GPO0 _GPI0 2_RD0  
RGMII2_RD0 RMII2_RXD0  
RGMII2_RD1 RMII2_RXD1  
GPIO0_65 GPMC0_A3  
GPIO0_66 GPMC0_A4  
GPIO0_67 GPMC0_A5  
GPIO0_68 GPMC0_A6  
GPIO0_69 GPMC0_A7  
GPIO0_70 GPMC0_A8  
0x000F410C PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII  
GPO1 _GPI1 2_RD1  
Y11  
AA12  
Y12  
0x000F4110 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_RD2  
GPO2 _GPI2 2_RD2 2_A2  
V12  
0x000F4114 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII  
GPO3 _GPI3 2_RD3  
RGMII2_RD3  
Y12  
W12  
AA13  
0x000F4118 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_RX_ RMII2_RX_E  
GPO4  
_GPI4  
2_RX_CTL  
2_B2  
CTL  
R
AA11  
0x000F411C PRG1_PRU1_ PRG1_PRU1  
RGMII1_RD0  
GPO5 _GPI5  
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
V10  
U11  
PADCONFIG_72  
PADCONFIG_73  
0x000F4120 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII  
GPO6 _GPI6 2_RXC  
RGMII2_RXC  
GPIO0_71 GPMC0_A9  
Y14  
V15  
0x000F4124 PRG1_PRU1_ PRG1_PRU1 PRG1_IEP1_  
RGMII1_TD0 RMII1_RXD0  
SPI3_CS3  
GPIO0_72 GPMC0_A10  
GPO7  
_GPI7  
EDC_LATCH  
_IN1  
W11  
Y16  
U12  
V14  
PADCONFIG_74  
PADCONFIG_75  
0x000F4128 PRG1_PRU1_ PRG1_PRU1  
GPO8 _GPI8  
PRG1_PWM RGMII1_RD1  
2_TZ_OUT  
GPIO0_73 GPMC0_A11  
0x000F412C PRG1_PRU1_ PRG1_PRU1 PRG1_UART  
GPO9 _GPI9 0_RXD  
RGMII1_TD1 RMII1_RXD1 PRG1_IEP0_ GPIO0_74 GPMC0_A12  
EDIO_DATA_  
IN_OUT30  
U13  
W14  
PADCONFIG_76  
0x000F4130 PRG1_PRU1_ PRG1_PRU1 PRG1_UART PRG1_PWM RGMII1_TD2 RMII1_TXD0 PRG1_IEP0_ GPIO0_75 GPMC0_A13  
GPO10  
_GPI10  
0_TXD  
2_TZ_IN  
EDIO_DATA_  
IN_OUT31  
Y6  
AA8  
Y9  
AA10  
V10  
PADCONFIG_77  
PADCONFIG_78  
PADCONFIG_79  
PADCONFIG_80  
PADCONFIG_81  
PADCONFIG_82  
PADCONFIG_83  
0x000F4134 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII  
GPO11 _GPI11 2_TD0  
RGMII2_TD0 RMII2_TXD0  
GPIO0_76 GPMC0_A14  
GPIO0_77 GPMC0_A15  
GPIO0_78 GPMC0_A16  
GPIO0_79 GPMC0_A17  
GPIO0_80 GPMC0_A18  
GPIO0_81 GPMC0_A19  
0x000F4138 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_TD1 RMII2_TXD1  
GPO12 _GPI12 2_TD1 1_A0  
U10  
0x000F413C PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_TD2 RMII2_CRS_  
GPO13 _GPI13 2_TD2 1_B0 DV  
W9  
V9  
AA11  
Y11  
0x000F4140 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_TD3  
GPO14 _GPI14 2_TD3 1_A1  
0x000F4144 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_TX_ RMII2_TX_E  
GPO15 _GPI15 2_TX_CTL 1_B1 CTL  
N
Y8  
Y10  
0x000F4148 PRG1_PRU1_ PRG1_PRU1 PRG1_RGMII PRG1_PWM RGMII2_TXC  
GPO16 _GPI16 2_TXC 1_A2  
AA14  
AA14  
0x000F414C PRG1_PRU1_ PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_TD3 RMII1_TXD1  
GPIO0_19 GPMC0_BE3 PRG1_ECAP  
GPO17  
_GPI17  
EDC_SYNC_  
OUT1  
1_B2  
n
0_SYNC_OU  
T
Y15  
Y13  
V12  
PADCONFIG_84  
PADCONFIG_85  
0x000F4150 PRG1_PRU1_ PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_RD2 RMII1_TX_E  
GPIO0_20 UART5_CTS PRG1_ECAP  
0_SYNC_IN  
GPO18  
_GPI18  
EDC_LATCH  
_IN0  
1_TZ_IN  
N
n
AA13  
0x000F4154 PRG1_PRU1_ PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_RD3 RMII1_CRS_  
SPI3_CS2  
GPIO0_84 UART5_RTS PRG1_ECAP  
GPO19  
_GPI19  
EDC_SYNC_ 1_TZ_OUT  
OUT0  
DV  
n
0_IN_APWM  
_OUT  
V2  
W1  
J3  
AA6  
Y6  
PADCONFIG_86  
PADCONFIG_87  
PADCONFIG_88  
PADCONFIG_89  
PADCONFIG_90  
PADCONFIG_91  
PADCONFIG_92  
0x000F4158 PRG1_MDIO0  
_MDIO  
MDIO0_MDI  
O
GPIO0_85  
GPIO0_86  
GPIO1_0  
GPIO1_1  
GPIO1_2  
GPIO1_3  
GPIO1_4  
0x000F415C PRG1_MDIO0  
_MDC  
MDIO0_MDC  
Y1  
0x000F4160 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO0 _GPI0 1_RD0 3_A0  
UART2_CTS  
n
J4  
R4  
0x000F4164 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO1 _GPI1 1_RD1 3_B0  
UART2_TXD  
G1  
H1  
K2  
U2  
0x000F4168 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO2 _GPI2 1_RD2 2_A0  
GPMC0_A0 UART2_RTS  
n
V2  
0x000F416C PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO3 _GPI3 1_RD3 3_A2  
UART3_CTS  
n
AA2  
0x000F4170 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO4 _GPI4 1_RX_CTL 2_B0  
GPMC0_A1 UART3_TXD  
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www.ti.com  
Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
F2  
R3  
PADCONFIG_93  
PADCONFIG_94  
PADCONFIG_95  
0x000F4174 PRG0_PRU0_ PRG0_PRU0  
GPO5 _GPI5  
PRG0_PWM  
3_B2  
GPIO1_5  
UART3_RTS  
n
H2  
E2  
T3  
T1  
0x000F4178 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO6 _GPI6 1_RXC 3_A1  
GPIO1_6  
UART4_CTS  
n
0x000F417C PRG0_PRU0_ PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_HW2 CP_GEMAC_ TIMER_IO6 GPIO1_7  
UART4_TXD  
GPO7  
_GPI7  
EDC_LATCH  
_IN1  
3_B1  
TSPUSH  
CPTS0_HW2  
TSPUSH  
H5  
Y3  
T2  
PADCONFIG_96  
PADCONFIG_97  
0x000F4180 PRG0_PRU0_ PRG0_PRU0  
GPO8 _GPI8  
PRG0_PWM  
2_A1  
GPIO1_8  
GPMC0_A2 UART4_RTS  
n
W6  
0x000F4184 PRG0_PRU0_ PRG0_PRU0 PRG0_UART PRG0_PWM RGMII1_RX_ RMII1_RX_E PRG0_IEP0_ GPIO1_9  
UART2_RXD  
GPO9  
_GPI9  
0_CTSn  
3_TZ_IN  
CTL  
R
EDIO_DATA_  
IN_OUT28  
U1  
AA5  
PADCONFIG_98  
0x000F4188 PRG0_PRU0_ PRG0_PRU0 PRG0_UART PRG0_PWM RGMII1_RXC RMII_REF_C PRG0_IEP0_ GPIO1_10  
UART3_RXD  
GPO10  
_GPI10  
0_RTSn  
2_B1  
LK  
EDIO_DATA_  
IN_OUT29  
L1  
K1  
N1  
N2  
N4  
N3  
E1  
Y3  
AA3  
R6  
V4  
PADCONFIG_99  
PADCONFIG_100  
PADCONFIG_101  
PADCONFIG_102  
PADCONFIG_103  
PADCONFIG_104  
PADCONFIG_105  
0x000F418C PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO11 _GPI11 1_TD0 3_TZ_OUT  
GPIO1_11  
GPIO1_12  
GPIO1_13  
GPIO1_14  
GPIO1_15  
GPIO1_16  
UART4_RXD  
GPMC0_A14  
0x000F4190 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO12 _GPI12 1_TD1 0_A0  
0x000F4194 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO13 _GPI13 1_TD2 0_B0  
SPI3_D0  
SPI3_D1  
GPMC0_A15  
0x000F4198 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO14 _GPI14 1_TD3 0_A1  
GPMC0_A3  
T5  
0x000F419C PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO15 _GPI15 1_TX_CTL 0_B1  
SPI3_CS1  
SPI3_CLK  
GPMC0_A16  
U4  
U1  
0x000F41A0 PRG0_PRU0_ PRG0_PRU0 PRG0_RGMII PRG0_PWM  
GPO16 _GPI16 1_TXC 0_A2  
GPMC0_A4  
0x000F41A4 PRG0_PRU0_ PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_TS_ CP_GEMAC_ SPI3_CS0  
GPIO1_17 TIMER_IO11 GPMC0_A17  
GPO17  
_GPI17  
EDC_SYNC_  
OUT1  
0_B2  
SYNC  
CPTS0_TS_  
SYNC  
K4  
G2  
V1  
PADCONFIG_106  
PADCONFIG_107  
0x000F41A8 PRG0_PRU0_ PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_HW1 CP_GEMAC_ EHRPWM8_ GPIO1_18 UART4_CTS GPMC0_A5 UART2_RXD  
GPO18  
_GPI18  
EDC_LATCH  
_IN0  
0_TZ_IN  
TSPUSH  
CPTS0_HW1  
TSPUSH  
A
n
W1  
0x000F41AC PRG0_PRU0_ PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_TS_ CP_GEMAC_ EHRPWM8_ GPIO1_19 UART4_RTS GPMC0_A6 UART3_RXD  
GPO19  
_GPI19  
EDC_SYNC_ 0_TZ_OUT  
OUT0  
COMP  
CPTS0_TS_  
COMP  
B
n
L5  
J2  
Y2  
W2  
V3  
T4  
PADCONFIG_108  
PADCONFIG_109  
PADCONFIG_110  
PADCONFIG_111  
PADCONFIG_112  
PADCONFIG_113  
0x000F41B0 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII  
GPO0 _GPI0 2_RD0  
GPIO1_20  
GPIO1_21  
GPIO1_22  
GPIO1_23  
GPIO1_24  
GPIO1_25  
EQEP0_A  
EQEP0_B  
EQEP0_S  
EQEP1_A  
EQEP1_B  
EQEP1_S  
UART5_CTS  
n
0x000F41B4 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII  
GPO1 _GPI1 2_RD1  
UART5_TXD  
M2  
L2  
L3  
E3  
0x000F41B8 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO2 _GPI2 2_RD2 2_A2  
UART5_RTS  
n
0x000F41BC PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII  
GPO3 _GPI3 2_RD3  
GPMC0_A18 UART6_CTS  
n
W3  
P4  
0x000F41C0 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO4 _GPI4 2_RX_CTL 2_B2  
UART6_TXD  
0x000F41C4 PRG0_PRU1_ PRG0_PRU1  
GPO5 _GPI5  
UART6_RTS  
n
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
F5  
R5  
PADCONFIG_114  
PADCONFIG_115  
0x000F41C8 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII  
GPO6 _GPI6 2_RXC  
GPIO1_26  
EQEP2_A  
GPMC0_A19 UART4_CTS  
n
T5  
W5  
0x000F41CC PRG0_PRU1_ PRG0_PRU1 PRG0_IEP1_  
RGMII1_RD0 RMII1_RXD0  
GPIO1_27  
GPIO1_28  
EQEP2_B  
UART4_TXD  
GPO7  
_GPI7  
EDC_LATCH  
_IN1  
F4  
R2  
R1  
Y5  
PADCONFIG_116  
PADCONFIG_117  
0x000F41D0 PRG0_PRU1_ PRG0_PRU1  
GPO8 _GPI8  
PRG0_PWM  
2_TZ_OUT  
EQEP2_S  
EQEP0_I  
UART4_RTS  
n
0x000F41D4 PRG0_PRU1_ PRG0_PRU1 PRG0_UART  
GPO9 _GPI9 0_RXD  
RGMII1_RD1 RMII1_RXD1 PRG0_IEP0_ GPIO1_29  
UART5_RXD  
EDIO_DATA_  
IN_OUT30  
U2  
V6  
PADCONFIG_118  
0x000F41D8 PRG0_PRU1_ PRG0_PRU1 PRG0_UART PRG0_PWM RGMII1_RD2 RMII1_TXD0 PRG0_IEP0_ GPIO1_30  
EQEP1_I  
UART6_RXD  
GPO10  
_GPI10  
0_TXD  
2_TZ_IN  
EDIO_DATA_  
IN_OUT31  
P1  
P2  
T4  
R5  
M4  
W4  
Y4  
T6  
PADCONFIG_119  
PADCONFIG_120  
PADCONFIG_121  
PADCONFIG_122  
PADCONFIG_123  
0x000F41DC PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII  
GPO11 _GPI11 2_TD0  
GPIO1_31  
GPIO1_32  
GPIO1_33  
GPIO1_34  
GPIO1_35  
EQEP2_I  
EQEP2_B  
EQEP0_I  
EQEP1_I  
UART4_RXD  
GPMC0_A7 UART4_TXD  
GPMC0_A8 UART5_RXD  
GPMC0_A9 UART6_RXD  
0x000F41E0 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO12 _GPI12 2_TD1 1_A0  
0x000F41E4 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO13 _GPI13 2_TD2 1_B0  
U6  
U5  
0x000F41E8 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO14 _GPI14 2_TD3 1_A1  
0x000F41EC PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO15 _GPI15 2_TX_CTL 1_B1  
GPMC0_A10 PRG0_ECAP  
0_IN_APWM  
_OUT  
T3  
T1  
D1  
F3  
AA4  
V5  
PADCONFIG_124  
PADCONFIG_125  
PADCONFIG_126  
PADCONFIG_127  
0x000F41F0 PRG0_PRU1_ PRG0_PRU1 PRG0_RGMII PRG0_PWM  
GPO16 _GPI16 2_TXC 1_A2  
GPIO1_36  
GPMC0_A11 PRG0_ECAP  
0_SYNC_OU  
T
0x000F41F4 PRG0_PRU1_ PRG0_PRU1 PRG0_IEP1_ PRG0_PWM RGMII1_RD3 RMII1_TXD1  
GPIO1_37 PRG0_ECAP  
PRG0_ECAP  
0_SYNC_IN  
GPO17  
_GPI17  
EDC_SYNC_  
OUT1  
1_B2  
0_SYNC_OU  
T
P5  
0x000F41F8 PRG0_PRU1_ PRG0_PRU1 PRG0_IEP1_ PRG0_PWM MDIO0_MDI RMII1_TX_E EHRPWM7_ GPIO1_38 PRG0_ECAP  
GPO18  
_GPI18  
EDC_LATCH  
_IN0  
1_TZ_IN  
O
N
A
0_SYNC_IN  
R2  
0x000F41FC PRG0_PRU1_ PRG0_PRU1 PRG0_IEP1_ PRG0_PWM MDIO0_MDC RMII1_CRS_ EHRPWM7_ GPIO1_39 PRG0_ECAP  
GPO19  
_GPI19  
EDC_SYNC_ 1_TZ_OUT  
OUT0  
DV  
B
0_IN_APWM  
_OUT  
E4  
D2  
P2  
P3  
PADCONFIG_128  
PADCONFIG_129  
0x000F4200 PRG0_MDIO0  
_MDIO  
GPIO1_40  
GPIO1_41  
GPIO1_42  
GPMC0_A12  
GPMC0_A13  
0x000F4204 PRG0_MDIO0  
_MDC  
D12  
C13  
PADCONFIG_130  
PADCONFIG_131  
0x000F4208  
0x000F420C  
SPI0_CS0  
SPI0_CS1  
B7  
CPTS0_TS_  
COMP  
I2C2_SCL  
TIMER_IO10 PRG0_IEP0_ UART6_RXD ADC_EXT_T GPIO1_43  
EDIO_OUTV  
ALID  
RIGGER0  
B8  
A8  
C9  
D13  
A13  
A14  
PADCONFIG_132  
PADCONFIG_133  
PADCONFIG_134  
0x000F4210  
0x000F4214  
0x000F4218  
SPI0_CLK  
SPI0_D0  
SPI0_D1  
GPIO1_44  
GPIO1_45  
GPIO1_46  
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
B14  
PADCONFIG_135  
PADCONFIG_136  
0x000F421C  
0x000F4220  
SPI1_CS0  
EHRPWM6_  
A
GPIO1_47  
D14  
SPI1_CS1  
CPTS0_TS_  
SYNC  
I2C2_SDA  
PRG1_IEP0_ UART6_TXD ADC_EXT_T GPIO1_48 TIMER_IO11  
EDIO_OUTV  
ALID  
RIGGER1  
C14  
B15  
A15  
PADCONFIG_137  
PADCONFIG_138  
PADCONFIG_139  
0x000F4224  
0x000F4228  
0x000F422C  
SPI1_CLK  
SPI1_D0  
SPI1_D1  
EHRPWM6_  
SYNCI  
GPIO1_49  
GPIO1_50  
GPIO1_51  
EHRPWM6_  
SYNCO  
EHRPWM6_  
B
B10  
B11  
B9  
D15  
C16  
B16  
PADCONFIG_140  
PADCONFIG_141  
PADCONFIG_142  
0x000F4230  
0x000F4234  
UART0_RXD  
UART0_TXD  
SPI2_D0  
SPI2_D1  
GPIO1_52  
GPIO1_53  
GPIO1_54  
EQEP0_A  
EQEP0_B  
EQEP0_S  
0x000F4238 UART0_CTSn  
SPI0_CS2  
SPI0_CS3  
ADC_EXT_T UART2_RXD TIMER_IO6  
RIGGER0  
SPI4_CLK  
SPI4_D0  
CP_GEMAC_  
CPTS0_TS_  
SYNC  
A9  
A16  
E15  
PADCONFIG_143  
PADCONFIG_144  
0x000F423C UART0_RTSn  
UART2_TXD TIMER_IO7  
SPI2_CS0  
GPIO1_55  
GPIO1_56  
EQEP0_I  
EQEP1_A  
B12  
0x000F4240  
0x000F4244  
UART1_RXD  
UART1_TXD  
CP_GEMAC_  
CPTS0_TS_  
COMP  
A12  
C11  
A11  
B13  
E14  
D16  
E16  
A17  
PADCONFIG_145  
PADCONFIG_146  
PADCONFIG_147  
PADCONFIG_148  
SPI2_CLK  
CP_GEMAC_  
CPTS0_HW1  
TSPUSH  
GPIO1_57  
GPIO1_58  
GPIO1_59  
EQEP1_B  
EQEP1_S  
EQEP1_I  
EQEP2_I  
0x000F4248 UART1_CTSn  
0x000F424C UART1_RTSn  
SPI1_CS2  
SPI1_CS3  
ADC_EXT_T PCIE0_CLKR UART3_RXD CP_GEMAC_  
RIGGER1  
SPI4_D1  
EQn  
CPTS0_TS_  
SYNC  
UART3_TXD CP_GEMAC_ SPI4_CS0  
CPTS0_HW2  
TSPUSH  
0x000F4250  
MCAN0_TX  
UART4_RXD TIMER_IO2 SYNC2_OUT  
UART4_TXD TIMER_IO3 SYNC3_OUT  
SPI4_CS1  
SPI4_CS2  
GPIO1_60  
GPIO1_61  
UART0_DTR  
n
A14  
B14  
B17  
C17  
PADCONFIG_149  
PADCONFIG_150  
0x000F4254  
0x000F4258  
MCAN0_RX  
MCAN1_TX  
EQEP2_S  
EQEP2_A  
UART0_RIn  
I2C3_SCL  
ECAP1_IN_A SYSCLKOUT TIMER_IO4 UART5_RXD EHRPWM_S GPIO1_62  
PWM_OUT  
UART0_DCD  
n
0
OCA  
A15  
B16  
B15  
A17  
B18  
D17  
A18  
B18  
C18  
B19  
D18  
PADCONFIG_151  
PADCONFIG_152  
PADCONFIG_153  
PADCONFIG_154  
PADCONFIG_155  
PADCONFIG_156  
0x000F425C  
0x000F4260  
0x000F4264  
0x000F4268  
0x000F426C  
0x000F4270  
MCAN1_RX  
I2C0_SCL  
I2C0_SDA  
I2C1_SCL  
I2C1_SDA  
I2C3_SDA  
ECAP2_IN_A  
PWM_OUT  
OBSCLK0  
TIMER_IO5 UART5_TXD EHRPWM_S GPIO1_63  
OCB  
EQEP2_B  
UART0_DSR  
n
OBSCLK0  
UART6_CTS  
n
GPIO1_64  
GPIO1_65  
GPIO1_66  
GPIO1_67  
GPIO1_68  
UART6_RTS  
n
CPTS0_HW1 TIMER_IO0  
TSPUSH  
SPI2_CS1  
SPI2_CS2  
CPTS0_HW2 TIMER_IO1  
TSPUSH  
ECAP0_IN_A SYNC0_OUT CPTS0_RFT  
PWM_OUT _CLK  
CP_GEMAC_ SPI4_CS3  
CPTS0_RFT  
_CLK  
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
A18  
A19  
PADCONFIG_157  
0x000F4274 EXT_REFCLK SYNC1_OUT  
1
SPI2_CS3  
CLKOUT0  
GPIO1_69  
C19  
K18  
PADCONFIG_158  
PADCONFIG_159  
0x000F4278  
0x000F427C  
EXTINTn  
GPIO1_70  
GPIO1_71  
K18  
K20  
J19  
J18  
MMC1_DAT3 CP_GEMAC_ TIMER_IO0 UART2_RXD  
CPTS0_TS_  
COMP  
K19  
L21  
K21  
PADCONFIG_160  
PADCONFIG_161  
PADCONFIG_162  
0x000F4280  
0x000F4284  
0x000F4288  
MMC1_DAT2 CP_GEMAC_ TIMER_IO1 UART2_TXD  
GPIO1_72  
GPIO1_73  
GPIO1_74  
CPTS0_TS_  
SYNC  
MMC1_DAT1 CP_GEMAC_ TIMER_IO2 UART3_RXD  
CPTS0_HW1  
TSPUSH  
MMC1_DAT0 CP_GEMAC_ TIMER_IO3 UART3_TXD  
CPTS0_HW2  
TSPUSH  
J20  
J21  
B17  
C16  
L20  
J19  
D19  
C20  
PADCONFIG_163  
PADCONFIG_165  
PADCONFIG_166  
PADCONFIG_167  
0x000F428C  
0x000F4294  
0x000F4298  
MMC1_CLK  
UART2_CTS TIMER_IO4 UART4_RXD  
n
GPIO1_75  
GPIO1_76  
GPIO1_77  
GPIO1_78  
MMC1_CMD UART2_RTS TIMER_IO5 UART4_TXD  
n
MMC1_SDCD UART3_CTS TIMER_IO6 UART5_RXD  
n
0x000F429C MMC1_SDWP UART3_RTS TIMER_IO7 UART5_TXD  
n
C17  
E19  
B19  
E18  
F16  
E19  
PADCONFIG_168  
PADCONFIG_169  
PADCONFIG_170  
0x000F42A0 RESET_REQz  
0x000F42A4 RESETSTATz  
0x000F42A8 USB0_DRVVB  
US  
GPIO1_79  
D18  
H21  
F19  
F21  
F20  
H20  
E21  
G20  
E20  
E17  
G20  
F20  
E21  
D20  
G21  
F21  
F19  
E20  
D6  
PADCONFIG_171  
PADCONFIG_172  
PADCONFIG_173  
PADCONFIG_174  
PADCONFIG_175  
PADCONFIG_176  
PADCONFIG_177  
PADCONFIG_178  
PADCONFIG_179  
0x000F42AC  
0x000F42B0  
0x000F42B4  
0x000F42B8  
0x000F42BC  
0x000F42C0  
0x000F42C4  
0x000F42C8  
0x000F42CC  
0x04084000  
PORz_OUT  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
GPIO1_80  
GPIO1_81  
GPIO1_82  
GPIO1_83  
GPIO1_84  
GPIO1_85  
GPIO1_86  
GPIO1_87  
MCU_PADCONFIG  
_0  
MCU_SPI0_C  
S0  
MCU_GPI  
O0_13  
C6  
E6  
E7  
MCU_PADCONFIG  
_1  
0x04084004  
0x04084008  
MCU_SPI0_C MCU_OBSC MCU_SYSCL  
MCU_GPI  
O0_12  
S1  
LK0  
KOUT0  
MCU_PADCONFIG  
_2  
MCU_SPI0_C  
LK  
MCU_GPI  
O0_11  
MCU_PADCONFIG  
_3  
0x0408400C MCU_SPI0_D  
0
MCU_GPI  
O0_10  
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
B6  
MCU_PADCONFIG  
_4  
0x04084010  
0x04084014  
0x04084018  
MCU_SPI0_D  
1
MCU_GPI  
O0_4  
A7  
B7  
MCU_PADCONFIG  
_5  
MCU_SPI1_C  
S0  
MCU_GPI  
O0_5  
MCU_PADCONFIG  
_6  
MCU_SPI1_C MCU_EXT_R  
S1 EFCLK0  
MCU_GPI  
O0_6  
D7  
MCU_PADCONFIG  
_7  
0x0408401C MCU_SPI1_C  
LK  
MCU_GPI  
O0_7  
C7  
MCU_PADCONFIG  
_8  
0x04084020  
MCU_SPI1_D  
0
MCU_GPI  
O0_8  
C8  
MCU_PADCONFIG  
_9  
0x04084024  
MCU_SPI1_D  
1
MCU_GPI  
O1*  
D6  
B2  
D4  
C2  
A9  
MCU_PADCONFIG  
_10  
0x04084028 MCU_UART0_  
RXD  
MCU_GPI  
O0_3  
A8  
MCU_PADCONFIG  
_11  
0x0408402C MCU_UART0_  
TXD  
MCU_GPI  
O0_2  
D8  
MCU_PADCONFIG  
_12  
0x04084030 MCU_UART0_ MCU_TIMER MCU_SPI0_  
CTSn _IO0 CS2  
MCU_GPI  
O0_1  
E8  
MCU_PADCONFIG  
_13  
0x04084034 MCU_UART0_ MCU_TIMER MCU_SPI1_  
MCU_GPI  
O0_0  
RTSn  
_IO1  
CS2  
C9  
MCU_PADCONFIG  
_14  
0x04084038 MCU_UART1_  
RXD  
MCU_GPI  
O0_14  
D9  
MCU_PADCONFIG  
_15  
0x0408403C MCU_UART1_  
TXD  
MCU_GPI  
O0_15  
B8  
MCU_PADCONFIG  
_16  
0x04084040 MCU_UART1_ MCU_TIMER MCU_SPI0_  
CTSn _IO2 CS3  
MCU_GPI  
O0_16  
B9  
MCU_PADCONFIG  
_17  
0x04084044 MCU_UART1_ MCU_TIMER MCU_SPI1_  
MCU_GPI  
O0_17  
RTSn  
_IO3  
CS3  
E9  
MCU_PADCONFIG  
_18  
0x04084048  
0x0408404C  
0x04084050  
0x04084054  
MCU_I2C0_S  
CL  
MCU_GPI  
O0_18  
A10  
A11  
B10  
B12  
B21  
B13  
A20  
B11  
MCU_PADCONFIG  
_19  
MCU_I2C0_S  
DA  
MCU_GPI  
O0_19  
MCU_PADCONFIG  
_20  
MCU_I2C1_S  
CL  
MCU_GPI  
O0_20  
MCU_PADCONFIG  
_21  
MCU_I2C1_S  
DA  
MCU_GPI  
O0_21  
A5  
C20  
A6  
MCU_PADCONFIG  
_22  
0x04084058 MCU_RESETz  
MCU_PADCONFIG  
_23  
0x0408405C  
0x04084060  
MCU_PORz  
MCU_PADCONFIG  
_24  
MCU_RESET  
STATz  
MCU_GPI  
O0_22  
B20  
C6  
MCU_PADCONFIG  
_25  
0x04084064 MCU_SAFETY  
_ERRORn  
MCU_PADCONFIG  
_26  
0x04084068  
TCK  
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Table 6-78. Pin Multiplexing (continued)  
MUX MODE SETTINGS  
[Bootstrap:0]  
(ALX)  
BALL BALL  
#
(ALV)  
PADCONFIG  
REGISTER  
PADCONFIG  
ADDRESS  
#
0
1
2
3
4
5
6
7
8
9
10  
15  
Bootstrap  
B6  
D11  
MCU_PADCONFIG  
_27  
0x0408406C  
0x04084070  
0x04084074  
0x04084078  
0x0408407C  
0x04084080  
TRSTn  
A3  
B5  
B4  
C5  
B3  
C11  
A12  
C12  
D10  
E10  
MCU_PADCONFIG  
_28  
TDI  
TDO  
MCU_PADCONFIG  
_29  
MCU_PADCONFIG  
_30  
TMS  
MCU_PADCONFIG  
_31  
EMU0  
EMU1  
MCU_PADCONFIG  
_32  
MCU_OB  
SCLK0  
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6.6 Connections for Unused Pins  
This section describes the Unused/Reserved balls connection requirements for the mechanical packages  
supported.  
Table 6-79. Reserved Balls Specific Connection Requirements (ALV)  
PKG  
BALL NUMBER  
CONNECTION REQUIREMENTS  
ALV  
D21, F12, F17, G13, H16, K1, K2, V16, W15  
These balls must be left unconnected.  
Table 6-80. Unused Balls Specific Connection Requirements (ALV)  
BALL  
NUMBER  
(ALV)  
BALL NAME  
CONNECTION REQUIREMENTS  
Each of these balls must be connected to VSS through a separate  
external pull resistor to ensure these balls are held to a valid logic  
low level if unused.  
TBD  
TBD  
TBD  
Each of these balls must be connected to the corresponding power  
supply through a separate external pull resistor to ensure these balls  
are held to a valid logic high level, if unused.(1)  
TBD  
J13  
VDDA_ADC  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
If the entire ADC is not used, each of these balls must be connected  
directly to VSS.  
G20  
F20  
E21,  
D20  
G21  
F21  
F19  
E20  
G20  
F20  
E21,  
D20  
G21  
F21  
F19  
E20  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
Any unused AIN ball must be pulled to VSS through a resistor  
or connected directly to VSS when VDDA_ADC is connected to a  
power source.  
F7  
G6  
H7  
J6,  
K7  
L6  
J8  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR_C  
If DDRSS is not used, each of these balls must be connected directly  
to VSS.  
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Table 6-80. Unused Balls Specific Connection Requirements (ALV) (continued)  
BALL  
NUMBER  
(ALV)  
BALL NAME  
CONNECTION REQUIREMENTS  
H2  
H1  
J5  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
DDR0_A1  
DDR0_A2  
DDR0_A3  
DDR0_A4  
K5  
F6  
H4  
D2  
C5  
E2  
D4  
D3  
F2  
J2  
DDR0_A5  
DDR0_A6  
L5  
DDR0_A7  
J3  
DDR0_A8  
J4  
DDR0_A9  
K3  
J1  
DDR0_A10  
DDR0_A11  
M5  
K4  
G4  
G5  
G2  
H3  
H5  
F1  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
A2  
B5  
A4  
B3  
C4  
C2  
B4  
N5  
L4  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
DDR0_RESET0_n  
Leave unconnected.  
Note: The DDR0 pins in this list can only be left unconnected  
when VDDS_DDR and VDDS_DDR_C are connected to VSS. The  
DDR0 pins must be connected as defined in the AM64x/AM243x  
DDR Board Design and Layout Guidelines, when VDDS_DDR and  
VDDS_DDR_C are connected to a power source.  
L2  
M3  
N4  
N3  
M4  
N2  
C1  
B1  
N1  
M1  
E5  
F5  
D5  
K13  
H14  
VDD_MMC0  
VDD_DLL_MMC0  
If MMC0 is not used, each of these balls must be connected to the  
same power source as VDD_CORE.  
J15  
K14  
VDDS_MMC0  
VDDS_MMC0  
If MMC0 is not used, each of these balls must be connected to  
any 1.8V power source that does not violate device power supply  
sequencing requirements.  
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Table 6-80. Unused Balls Specific Connection Requirements (ALV) (continued)  
BALL  
NUMBER  
(ALV)  
BALL NAME  
CONNECTION REQUIREMENTS  
F18  
G18  
J21  
G19  
K20  
J20  
J18  
J17  
H17  
H19  
H18  
G17  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
If MMC0 is not used, each of these balls must be left unconnected.  
P12  
P13  
P11  
R14  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_1P8_SERDES0  
If SERDES0 is not used, each of these balls must be connected  
directly to VSS.  
T13  
SERDES0_REXT  
Leave unconnected.  
W16  
W17  
Y15  
Y16  
AA16  
AA17  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_TX0_N  
SERDES0_TX0_P  
Note: The SERDES0_REXT pin can only be left unconnected  
when VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and  
VDDA_1P8_SERDES0 are connected to VSS. The  
SERDES0_REXT pin must be connected to VSS through  
the appropriate external resistor when VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are  
connected to a power source.  
T12  
R15  
R13  
VDDA_0P85_USB0  
VDDA_1P8_USB0  
VDDA_3P3_USB0  
If USB0 is not used, each of these balls must be connected directly  
to VSS.  
AA20  
AA19  
U16  
U17  
T14  
USB0_DM  
USB0_DP  
USB0_ID  
USB0_RCALIB  
USB0_VBUS  
Leave unconnected.  
Note: The USB0_RCALIB pin can only be left unconnected when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0  
are connected to VSS. The USB0_RCALIB pin must be  
connected to VSS through the appropriate external resistor when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are  
connected to a power source.  
Table 6-81. Reserved Balls Specific Connection Requirements (ALX)  
PKG  
BALL NUMBER  
CONNECTION REQUIREMENTS  
ALX  
H11, J13  
These balls must be left unconnected.  
Table 6-82. Unused Balls Specific Connection Requirements (ALX)  
BALL NUMBER (ALX)  
BALL NAME  
CONNECTION REQUIREMENTS  
Each of these balls must be connected to VSS through a separate  
external pull resistor to ensure these balls are held to a valid logic  
low level if unused.  
TBD  
TBD  
TBD  
TBD  
Each of these balls must be connected to the corresponding power  
supply through a separate external pull resistor to ensure these balls  
are held to a valid logic high level, if unused.(1)  
J13  
VDDA_ADC  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
If the entire ADC is not used, each of these balls must be connected  
directly to VSS.  
H21  
F19  
F21,  
F20  
H20  
E21  
G20  
E20  
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Table 6-82. Unused Balls Specific Connection Requirements (ALX) (continued)  
BALL NUMBER (ALX)  
BALL NAME  
CONNECTION REQUIREMENTS  
H21  
F19  
F21,  
F20  
H20  
E21  
G20  
E20  
ADC0_AIN0  
Any unused AIN ball must be pulled to VSS through a resistor  
or connected directly to VSS when VDDA_ADC is connected to a  
power source.  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
V16  
U15  
U16  
VDDA_0P85_USB0  
VDDA_1P8_USB0  
VDDA_3P3_USB0  
If USB0 is not used, each of these balls must be connected directly  
to VSS.  
AA17  
AA16  
Y17  
W17  
V18  
USB0_DM  
USB0_DP  
USB0_ID  
USB0_RCALIB  
USB0_VBUS  
Leave unconnected.  
Note: The USB0_RCALIB pin can only be left unconnected when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0  
are connected to VSS. The USB0_RCALIB pin must be  
connected to VSS through the appropriate external resistor when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are  
connected to a power source.  
(1) To determine which power supply is associated with any IO refer to the Pin Attributes tables.  
Note  
All power balls must be supplied with the voltages specified in Section 7.4, Recommended Operating  
Conditions, unless otherwise specified in Section 6.4, Signal Descriptions.  
Note  
All other unused signal balls with a Pad Configuration register can be left unconnected with their  
multiplexing mode set to GPIO input and internal pulldown resistor enabled.  
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case  
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.  
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on  
the internal pull resistor to hold a valid logic level.  
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for  
some operating conditions. This may be the case when connected to components with leakage to the  
opposite logic level, or when external noise sources couple to signal traces attached to balls which  
are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be  
required to hold a valid logic level on balls with external connections.  
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state  
which could damage the IO cell.  
Note  
All other unused signal balls without a Pad Configuration register should be left unconnected.  
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7 Specifications  
7.1 Absolute Maximum Ratings  
Table 7-1. Absolute Maximum Ratings  
PARAMETER  
MIN  
MAX  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
TBD  
TBD  
2.2  
Unit  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE  
VDDR_CORE  
VDD_MMC0  
Core supply  
RAM supply  
-0.3  
-0.3  
MMC0 PHY core supply  
MMC0 PLL analog supply  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
VDD_DLL_MMC0  
VDDA_0P85_SERDES0 SERDES0 0.85 V analog supply  
VDDA_0P85_SERDES0_C SERDES0 clock 0.85 V analog supply  
VDDA_0P85_USB0  
VDDS_DDR  
USB0 0.85 V analog supply  
DDR PHY IO supply  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
DDR clock IO supply  
MMC0 PHY IO supply  
MCU_OSC0 supply  
2.2  
VDDA_MCU  
VDDA_ADC0  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
POR and MCU PLL analog supply  
ADC0 analog supply  
2.2  
2.2  
Main, PER1, and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
2.2  
2.2  
2.2  
VDDA_1P8_SERDES0 SERDES0 1.8 V analog supply  
2.2  
VDDA_1P8_USB0  
VDDA_TEMP0  
VDDA_TEMP1  
VPP  
USB0 1.8 V analog supply  
TEMP0 analog supply  
2.2  
2.2  
TEMP1 analog supply  
2.2  
eFuse ROM programming supply  
IO supply for IO MCU  
TBD  
3.8  
VDDSHV_MCU  
VDDSHV0  
IO supply for IO group 0  
IO supply for IO group 1  
IO supply for IO group 2  
IO supply for IO group 3  
IO supply for IO group 4  
IO supply for IO group 5  
USB0 3.3 V analog supply  
SDIO 3.3 V analog supply  
3.8  
VDDSHV1  
3.8  
VDDSHV2  
3.8  
VDDSHV3  
3.8  
VDDSHV4  
3.8  
VDDSHV5  
3.8  
VDDA_3P3_USB0  
VDDA_3P3_SDIO  
3.8  
TBD  
MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL,  
I2C0_SDA, EXTINTn, MCU_PORz  
-0.3  
TBD  
V
Steady-state max voltage  
at all fail-safe IO pins  
VMON_1P8_MCU, VMON_1P8_SOC  
VMON_3P3_MCU, VMON_3P3_SOC  
VMON_VSYS(2)  
-0.3  
-0.3  
-0.3  
-0.3  
2.2  
3.8  
2.2  
3.6  
V
V
V
V
USB0_VBUS(4)  
Steady-state max voltage  
at all other IO pins(1)  
IO  
Supply  
All other IO pins  
-0.3  
V
Voltage + 0.3  
20% of IO supply voltage for up to 20% of the  
signal period (see Figure 7-1, IO Transient Voltage  
Ranges)  
Transient overshoot and  
undershoot at IO pin  
0.2 × VDD(3)  
TBD  
V
Latch-up performance  
TBD  
mA  
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Table 7-1. Absolute Maximum Ratings (continued)  
PARAMETER  
MIN  
MAX  
Unit  
TSTG  
Storage temperature  
-55  
+150  
°C  
(1) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For  
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be  
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used  
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,  
including power supply ramp-up and ramp-down sequences.  
(2) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.5, System Power  
Supply Monitor Design Guidelines.  
(3) VDD is the voltage on the corresponding power-supply pin(s) for the IO.  
(4) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.4, USB  
Design Guidelines.  
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power  
supply voltage. This allows external voltage sources to be connected to these IO terminals when the  
respective IO power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL, I2C0_SDA,  
EXTINTn, VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, VMON_3P3_SOC, and MCU_PORz are  
the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be  
limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 7.1.  
Overshoot = 20% of nominal  
IO supply voltage  
Tovershoot  
Tperiod  
Tundershoot  
Undershoot = 20% of nominal  
IO supply voltage  
A. Tovershoot + Tundershoot < 20% of Tperiod  
Figure 7-1. IO Transient Voltage Ranges  
7.2 ESD Ratings  
VALUE  
TBD  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)  
Electrostatic discharge  
(ESD)  
V(ESD)  
V
TBD  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Power-On Hours (POH)  
Temperature Range  
JUNCTION TEMP (Tj)  
0°C to 90°C  
LIFETIME (POH)(1) (2) (3)  
Commercial Junction Temperature Range  
Extended Junction Temperature Range  
TBD  
TBD  
-40°C to 105°C  
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard  
terms and conditions for TI semiconductor products.  
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted  
temperatures.  
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.  
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7.4 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
SUPPLY NAME  
DESCRIPTION  
MIN(3)  
0.81  
0.81  
0.81  
0.81  
0.81  
NOM  
0.85  
0.85  
0.85  
0.85  
0.85  
MAX(3)  
0.895  
0.895  
0.895  
0.895  
0.895  
UNIT  
VDD_CORE  
Core supply  
0.85 V Operation  
V
V
V
V
V
VDDR_CORE  
VDD_MMC0  
RAM supply  
MMC0 PHY core supply  
VDD_DLL_MMC0  
MMC0 PLL analog supply  
VDDA_0P85_SERDES0 SERDES0 0.85 V analog supply  
VDDA_0P85_SERDES0_  
SERDES0 clock 0.85 V analog supply  
C
0.81  
0.85  
0.895  
V
VDDA_0P85_USB0  
USB0 0.85 V analog supply  
0.81  
1.06  
1.14  
1.06  
1.14  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
3.135  
3.135  
3.135  
3.135  
0
0.85  
1.1  
1.2  
1.1  
1.2  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
3.3  
3.3  
3.3  
3.3  
see(1)  
see(2)  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
0.895  
1.17  
1.26  
1.17  
1.26  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
3.465  
3.465  
3.465  
3.465  
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1.1 V Operation  
1.2 V Operation  
1.1 V Operation  
1.2 V Operation  
VDDS_DDR  
DDR PHY IO supply  
VDDS_DDR_C  
DDR clock IO supply  
VDDS_MMC0  
VDDS_OSC  
VDDA_MCU  
VDDA_ADC0  
VDDA_PLL0  
VDDA_PLL1  
VDDA_PLL2  
MMC0 PHY IO supply  
MCU_OSC0 supply  
POR and MCU PLL analog supply  
ADC0 analog supply  
Main, PER and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
VDDA_1P8_SERDES0 SERDES0 1.8 V analog supply  
VDDA_1P8_USB0  
VDDA_TEMP0  
VDDA_TEMP1  
VPP  
USB0 1.8 V analog supply  
TEMP0 analog supply  
TEMP1 analog supply  
eFuse ROM programming supply  
Voltage monitor for 1.8 V MCU power supply  
Voltage monitor for 1.8 V SoC power supply  
USB0 3.3 V analog supply  
VMON_1P8_MCU  
VMON_1P8_SOC  
VDDA_3P3_USB0  
VDDA_3P3_SDIO  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
SDIO 3.3 V analog supply  
Voltage monitor for 3.3 V MCU power supply  
Voltage monitor for 3.3 V SoC power supply  
Voltage monitor pin  
USB0_VBUS  
USB Level-shifted VBUS Input  
0
3.465  
1.89  
3.465  
1.89  
3.465  
1.89  
3.465  
1.89  
3.465  
1.89  
3.465  
1.89  
3.465  
1.8 V Operation  
3.3 V Operation  
1.8 V Operation  
3.3 V Operation  
1.8 V Operation  
3.3 V Operation  
1.8 V Operation  
3.3 V Operation  
1.8 V Operation  
3.3 V Operation  
1.8 V Operation  
3.3 V Operation  
1.71  
3.135  
1.71  
3.135  
1.71  
3.135  
1.71  
3.135  
1.71  
3.135  
1.71  
3.135  
VDDSHV_MCU  
VDDSHV0  
VDDSHV1  
VDDSHV2  
VDDSHV3  
VDDSHV4  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
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over operating free-air temperature range (unless otherwise noted)  
SUPPLY NAME  
DESCRIPTION  
MIN(3)  
1.71  
3.135  
-40  
NOM  
1.8  
MAX(3)  
1.89  
3.465  
105  
UNIT  
V
1.8 V Operation  
3.3 V Operation  
Extended  
VDDSHV5  
Dual-voltage IO supply  
3.3  
V
TJ  
Operating junction temperature range  
°C  
Commercial  
0
90  
(1) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.5, System Power  
Supply Monitor Design Guidelines.  
(2) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.4, USB  
Design Guidelines.  
(3) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This  
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.  
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7.5 Operating Performance Points  
This section describes the operating conditions of the device. This section also contains the description of each  
Operating Performance Point (OPP) for processor clocks and device core clocks.  
Note  
The OPP voltage and frequency values may change following the silicon characterization result.  
Table 7-2 describes the maximum supported frequency per speed grade for the device.  
Table 7-2. Speed Grade Maximum Frequency  
MAXIMUM FREQUENCY (MHz)  
DEVICE(1)  
SPEED  
GRADE  
INFRA  
(CBASS)  
R5FSS  
800  
M4FSS  
400  
ICSSG  
333  
DMSC-L  
250  
DDR4  
LPDDR4  
800  
800  
AM243x...ALV  
AM243x...ALV  
S
K
250  
250  
(DDR-1600)(2)  
(LPDDR-1600)(2)  
800  
800  
400  
400  
TBD  
250  
(DDR-1600)(2)  
(LPDDR-1600)(2)  
AM243x...ALX  
AM243x...ALX  
S
K
800  
400  
400  
400  
250  
250  
333  
250  
250  
N/A  
N/A  
N/A  
N/A  
TBD  
(1) N/A in this table stands for Not Applicable.  
(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.  
7.6 Power Consumption Summary  
For information on the device power consumption contact your TI Representative.  
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7.7 Electrical Characteristics  
Note  
The interfaces or signals described in the following Electrical Characteristics tables correspond to the  
interfaces or signals available when the associated PADCONFIG register is configured for multiplexing  
mode 0 (Primary Function).  
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical  
characteristics, unless multiplexing involves a combined PHY and GPIO topology. In this case,  
different DC electrical characteristics are specified for the different multiplexing modes (Functions).  
7.7.1 Fail-Safe Reset (FS RESET) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
0.3 ×  
UNIT  
VIL  
Input Low Voltage  
V
V
V
VDDS_OSC  
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
TBD  
0.7 ×  
VDDS_OSC  
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
TBD  
V
200  
mV  
VI = 1.8 V  
or  
VI = 0 V  
IIN  
Input Leakage Current.  
Input Slew Rate  
±10  
µA  
SRI  
TBD  
TBD  
TBD  
V/s  
7.7.2 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.8 V MODE  
VIL  
Input Low Voltage  
0.3 × VDD(1)  
0.3 × VDD(1)  
V
V
VILSS  
Input Low Voltage Steady State  
Input High Voltage  
VIH  
0.7 × VDD(1)  
0.7 × VDD(1)  
0.1 × VDD(1)  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
TBD  
±10  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
VOL  
IOL  
Output Low Voltage  
Low Level Output Current  
Input Slew Rate  
0.2 × VDD(1)  
V
VOL(MAX)  
20  
mA  
V/s  
SRI  
TBD  
TBD  
TBD  
3.3 V MODE (2)  
VIL  
Input Low Voltage  
0.3 × VDD(1)  
0.25 × VDD(1)  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.7 × VDD(1)  
0.7 × VDD(1)  
0.05 × VDD(1)  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
TBD  
±10  
0.4  
mV  
VI = 3.3 V  
or  
VI = 0 V  
IIN  
Input Leakage Current.  
Output Low Voltage  
±10  
µA  
V
VOL  
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over recommended operating conditions (unless otherwise noted)  
PARAMETER  
Low Level Output Current  
Input Slew Rate  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
mA  
IOL  
VOL(MAX)  
20  
SRI  
TBD  
TBD  
8E + 7  
V/s  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see POWER  
column of the Pin Attributes table.  
(2) I2C HS-mode is not supported when operating the IO in 3.3 V mode.  
7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
0.35 ×  
VDDS_OSC  
UNIT  
VIL  
Input Low Voltage  
V
0.65 ×  
VDDS_OSC  
VIH  
Input High Voltage  
V
VHYS  
Input Hysteresis Voltage  
49  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±TBD  
µA  
VI = 0.0 V  
7.7.4 eMMCPHY Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
0.35 ×  
VDDS_MMC0  
VIL  
Input Low Voltage  
V
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.20  
0.65 ×  
VDDS_MMC0  
VIHSS  
IIN  
Input High Voltage Steady State  
Input Leakage Current.  
Pull-up Resistor  
1.4  
V
VI = 1.8 V or 0 V  
±10  
25  
uA  
kΩ  
kΩ  
V
RPU  
RPD  
VOL  
15  
15  
20  
20  
Pull-down Resistor  
25  
Output Low Voltage  
IOL = 2 mA  
IOH = -2 mA  
0.30  
VDDS_MMC0  
- 0.30  
VOH  
SRI  
Output High Voltage  
Input Slew Rate  
V
5E + 8  
V/s  
7.7.5 SDIO Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.8 V MODE  
VIL  
Input Low Voltage  
0.58  
0.58  
V
V
VILSS  
Input Low Voltage Steady State  
Input High Voltage  
VIH  
1.27  
1.7  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
RPU  
RPD  
Pull-up Resistor  
40  
40  
50  
50  
60  
60  
kΩ  
kΩ  
Pull-down Resistor  
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UNIT  
SPRSP65B – APRIL 2021 – REVISED JULY 2021  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
VOL  
VOH  
Output Low Voltage  
0.45  
V
V
VDDSHV5 -  
0.45  
Output High Voltage  
IOL  
Low Level Output Current  
High Level Output Current  
Input Slew Rate  
VOL(MAX)  
VOH(MIN)  
4
4
mA  
mA  
V/s  
IOH  
SRI  
TBD  
3.3 V MODE  
0.25 ×  
VDDSHV5  
VIL  
Input Low Voltage  
V
V
V
0.15 ×  
VDDSHV5  
VILSS  
VIH  
VIHSS  
VHYS  
Input Low Voltage Steady State  
Input High Voltage  
0.625 ×  
VDDSHV5  
0.625 ×  
VDDSHV5  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
VI = 3.3 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
RPU  
RPD  
Pull-up Resistor  
40  
40  
50  
50  
60  
60  
kΩ  
kΩ  
Pull-down Resistor  
0.125 ×  
VDDSHV5  
VOL  
VOH  
Output Low Voltage  
Output High Voltage  
V
V
0.75 ×  
VDDSHV5  
IOL  
Low Level Output Current  
High Level Output Current  
Input Slew Rate  
VOL(MAX)  
VOH(MIN)  
6
10  
mA  
mA  
V/s  
IOH  
SRI  
TBD  
TBD  
TBD  
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7.7.6 ADC12B Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
VSS  
-1  
TYP  
MAX UNIT  
VADC_AIN[7:0] Full-scale Input Range  
VDDA_ADC0  
V
DNL  
INL  
Differential Non-Linearity  
Integral Non-Linearity  
0.5  
±1  
2
LSB  
±3 LSB  
LSB  
LSBGAIN-  
Gain Error  
±2  
ERROR  
LSBOFFSET-  
Offset Error  
±2  
LSB  
pF  
ERROR  
CIN  
Input Sampling Capacitance  
5.5  
Input Signal: 200 kHz  
sine wave at -0.5 dB  
Full Scale  
SNR  
Signal-to-Noise Ratio  
70  
75  
80  
69  
dB  
dB  
dB  
Input Signal: 200 kHz  
sine wave at -0.5 dB  
Full Scale  
THD  
Total Harmonic Distortion  
Spurious Free Dynamic Range  
Input Signal: 200 kHz  
sine wave at -0.5 dB  
Full Scale  
SFDR  
Input Signal: 200 kHz  
sine wave at -0.5 dB  
Full Scale  
SNR(PLUS) Signal-to-Noise Plus Distortion  
dB  
Ω
RADC_AIN[0:7] Input Impedance of ADC0_AIN[7:0]  
f = input frequency  
[1/((65.97  
× 10–-12) ×  
f)]  
IIN  
Input Leakage  
ADC0_AIN[7:0] = VSS  
4
μA  
μA  
ADC0_AIN[7:0] =  
VDDA_ADC0  
10  
Sampling Dynamics  
FSMPL_CLK SMPL_CLK Frequency  
60  
13  
MHz  
ADC0  
SMPL_  
CLK  
tC  
Conversion Time  
Acquisition time  
Cycles  
ADC0  
SMPL_  
CLK  
tACQ  
2
257  
4
Cycles  
TR  
Sampling Rate  
ADC0 SMPL_CLK =  
60 MHz  
MSPS  
dB  
CCISO  
Channel to Channel Isolation  
100  
General Purpose Input Mode (1)  
VIL  
VILSS  
VIH  
Input Low Voltage  
0.35 ×  
VDDA_ADC0  
V
V
V
Input Low Voltage Steady State  
Input High Voltage  
0.35 ×  
VDDA_ADC0  
0.65 ×  
VDDA_ADC0  
0.65 ×  
VDDA_ADC0  
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
200  
mV  
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MAX UNIT  
SPRSP65B – APRIL 2021 – REVISED JULY 2021  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
ADC0_AIN[7:0] =  
VDDA_ADC0  
or  
II  
Input Leakage Current  
2
μA  
ADC0_AIN[7:0] = VSS  
(1) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate  
as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1).  
7.7.7 LVCMOS Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.8-V MODE  
VIL  
Input Low Voltage  
0.35 × VDD(1)  
0.3 × VDD(1)  
V
V
V
VILSS Input Low Voltage Steady State  
VIH Input High Voltage  
0.65 × VDD(1)  
0.85 × VDD(1)  
150  
VIHS  
Input High Voltage Steady State  
V
S
VHYS Input Hysteresis Voltage  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0.0 V  
RPU Pull-up Resistor  
15  
15  
22  
22  
30  
30  
kΩ  
kΩ  
V
RPD Pull-down Resistor  
VOL Output Low Voltage  
VOH Output High Voltage  
0.45  
0.45 × VDD(1)  
V
IOL  
Low Level Output Current  
VOL(MAX)  
VOH(MIN)  
3
3
mA  
mA  
V/s  
IOH High Level Output Current  
SRI Input Slew Rate  
TBD  
TBD  
TBD  
3.3-V MODE  
VIL  
Input Low Voltage  
0.8  
0.6  
V
V
V
VILSS Input Low Voltage Steady State  
VIH Input High Voltage  
2.0  
2.0  
VIHS  
Input High Voltage Steady State  
V
S
VHYS Input Hysteresis Voltage  
150  
mV  
VI = 3.3 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0.0 V  
RPD Pull-down Resistor  
RPD Pull-down Resistor  
VOL Output Low Voltage  
VOH Output High Voltage  
15  
15  
22  
22  
30  
30  
kΩ  
kΩ  
V
0.4  
2.4  
5
V
IOL  
Low Level Output Current  
VOL(MAX)  
VOH(MIN)  
mA  
mA  
V/s  
IOH High Level Output Current  
SRI Input Slew Rate  
9
TBD  
TBD  
TBD  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the  
POWER column of the Pin Attributes table.  
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7.7.8 USB2PHY Electrical Characteristics  
Note  
USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000  
including ECNs and Errata as applicable.  
7.7.9 DDR Electrical Characteristics  
Note  
The DDR interface is compatible with DDR4 and LPDDR4 devices  
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7.8 VPP Specifications for One-Time Programmable (OTP) eFuses  
This section specifies the operating conditions required for programming the OTP eFuses..  
7.8.1 Recommended Operating Conditions for OTP eFuse Programming  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
VDD_CORE  
Supply voltage range for the core domain during OTP  
operation; OPP NOM (BOOT)  
See Recommended Operating  
V
Conditions  
VPP  
Supply voltage range for the eFuse ROM domain during  
normal operation without hardware support to program eFuse  
ROM  
NC(2)  
V
V
V
Supply voltage range for the eFuse ROM domain during  
normal operation with hardware support to program eFuse  
ROM  
0
Supply voltage range for the eFuse ROM domain during OTP  
programming(1)  
1.71  
1.8  
1.89  
I(VPP)  
SR(VPP)  
Tj  
VPP current  
TBD  
6E + 4  
85  
mA  
V/s  
°C  
VPP Slew Rate  
Temperature (ambient)  
0
25  
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family  
is a example device that meets the supply voltage range needed for VPP.  
(2) NC stands for No Connect.  
7.8.2 Hardware Requirements  
The following hardware requirements must be met when programming keys in the OTP eFuses:  
•
•
The VPP power supply must be disabled when not programming OTP registers.  
The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see  
Section 7.10.2, Power Supply Sequencing).  
7.8.3 Programming Sequence  
Programming sequence for OTP eFuses:  
•
Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during  
power up and normal operation.  
•
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP  
software package).  
•
•
•
Apply the voltage on the VPP terminal according to the specification in Section 7.8.1.  
Run the software that programs the OTP registers.  
After validating the content of the OTP registers, remove the voltage from the VPP terminal.  
7.8.4 Impact to Your Hardware Warranty  
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that  
the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence  
step. Further the TI Device may fail to secure boot if the error code correction check fails for the Production  
Keys or if the image is not signed and optionally encrypted with the current active Production Keys. These  
types of situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices  
conformed to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY  
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.  
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7.9 Thermal Resistance Characteristics  
This section provides the thermal resistance characteristics used on this device.  
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below  
the TJ value identified in Recommended Operating Conditions.  
7.9.1 Thermal Resistance Characteristics  
Table 7-3. ALV Package Thermal Resistance Characteristics  
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.  
AIR FLOW  
(m/s)(2)  
AIR FLOW  
(m/s)(2)  
°C/W(1) (3)  
°C/W(1) (3)  
NO.  
PARAMETER  
DESCRIPTION  
ALV Package  
ALX Package  
T1  
T2  
RΘJC  
RΘJB  
RΘJA  
Junction-to-case  
0.98  
3.87  
12.8  
TBD  
TBD  
TBD  
0.53  
TBD  
TBD  
TBD  
3.74  
TBD  
TBD  
TBD  
N/A  
N/A  
0
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
N/A  
N/A  
0
Junction-to-board  
Junction-to-free air  
T3  
T4  
1
1
T5  
RΘJA  
Junction-to-moving air  
2
2
T6  
3
3
T7  
0
0
T8  
1
1
ΨJT  
Junction-to-package top  
T9  
2
2
T10  
T11  
T12  
T13  
T14  
3
3
0
0
1
1
ΨJB  
Junction-to-board  
2
2
3
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on  
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these  
EIA/JEDEC standards:  
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Packages  
(2) m/s = meters per second.  
(3) °C/W = degrees Celsius per watt.  
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7.10 Timing and Switching Characteristics  
Note  
The Timing Requirements and Switching Characteristics values may change following the silicon  
characterization result.  
Note  
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,  
unless specific instructions are given otherwise.  
7.10.1 Timing Parameters and Information  
The timing parameter symbols used in Timing and Switching Characteristics sections are created in accordance  
with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been  
abbreviated in Table 7-4:  
Table 7-4. Timing Parameters Subscripts  
SYMBOL  
PARAMETER  
Cycle time (period)  
Delay time  
c
d
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
Unknown, changing, or don't care level  
Fall time  
X
F
H
High  
L
Low  
R
Rise time  
V
Valid  
IV  
AE  
FE  
LE  
Z
Invalid  
Active Edge  
First Edge  
Last Edge  
High impedance  
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7.10.2 Power Supply Sequencing  
This section describes power supply sequencing required to ensure proper device operation. The power supply  
names described in this section comprise a superset of a family of compatible devices. Some members of this  
family will not include a subset of these power supplies and their associated device modules.  
Note  
All power sequence timing shown is preliminary and under evaluation. Updates will be provided as  
details become known during validation testing.  
7.10.2.1 Power Supply Slew Rate Requirement  
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the  
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in Figure 7-2, TI recommends  
having the supply ramp slew for a 1.8-V supply of more than 100 µs.  
Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.  
Supply value  
t
slew rate < 18 mV/μs  
slew > (supply value) / (18 mV/μs)  
or  
supply value × 55.6 μs/V  
SPRT740_ELCH_06  
Figure 7-2. Power Supply Slew and Slew Rate  
7.10.2.2 Power-Up Sequencing  
The Figure 7-3 diagram describes the device power-up sequencing.  
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Figure 7-3. Power-Up Sequencing  
1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to  
be a pre-regulated supply that sources power management devices which source all other supplies.  
2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information,  
see Section 9.3.5, System Power Supply Monitor Design Guidelines.  
3. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or  
3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO  
supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period  
defined by this waveform.  
4. The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be  
connected to the respective 3.3V supply source.  
5. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or  
3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO  
supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period  
defined by this waveform.  
6. The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be  
connected to the respective 1.8V supply source.  
7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp  
together.  
8. VDD_CORE and VDDR_CORE are expected to be powered by the same source such that they ramp  
together.  
9. VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/  
down sequences and during normal device operation. This supply shall only be sourced while programming  
eFuse.  
7.10.2.3 Power-Down Sequencing  
Figure 7-4 describes the device power-down sequencing.  
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Figure 7-4. Power-Down Sequencing  
1. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.  
2. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.  
7.10.3 System Timing  
For more details about features and additional description information on the subsystem multiplexing signals,  
see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-5. System Timing Conditions  
PARAMETER  
MIN  
0.5  
3
MAX  
2
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
CL  
Input slew rate  
OUTPUT CONDITIONS  
Output load capacitance  
30  
7.10.3.1 Reset Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for reset  
related signals.  
Table 7-6. MCU_PORz Timing Requirements  
see Figure 7-5  
NO.  
MIN  
MAX UNIT  
Hold time, MCU_PORz active (low) at Power-up  
after supplies valid (using external crystal)  
RST1  
9500000  
ns  
th(SUPPLIES_VALID - MCU_PORz)  
Hold time, MCU_PORz active (low) at Power-up  
after supplies valid and external clock stable (using  
external LVCMOS oscillator)  
RST2  
1200  
ns  
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Table 7-6. MCU_PORz Timing Requirements (continued)  
see Figure 7-5  
NO.  
MIN  
MAX UNIT  
Pulse Width minimum, MCU_PORz low after  
Power-up (without removal of Power or system  
reference clock MCU_OSC0_XI/XO)  
RST3 tw(MCU_PORzL)  
1200  
ns  
Figure 7-5. MCU_PORz Timing Requirements  
Table 7-7. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
see Figure 7-6  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_PORz active (low) to  
MCU_RESETSTATz active (low)  
RST4 td(MCU_PORzL-MCU_RESETSTATzL)  
RST5 td(MCU_PORzH-MCU_RESETSTATzH)  
RST6 td(MCU_PORzL-RESETSTATzL)  
RST7 td(MCU_PORzH-RESETSTATzH)  
RST8 tw(MCU_RESETSTATzL)  
0
ns  
Delay time, MCU_PORz inactive (high) to  
MCU_RESETSTATz inactive (high)  
6120*S(1)  
0
ns  
ns  
ns  
ns  
Delay time, MCU_PORz active (low) to  
RESETSTATz active (low)  
Delay time, MCU_PORz inactive (high) to  
RESETSTATz inactive (high)  
9195*S(1)  
4040*S(1)  
Pulse Width Minimum MCU_RESETSTATz low  
(SW_MCU_WARMRST)  
Pulse Width Minimum RESETSTATz low  
(SW_MCU_WARMRST, SW_MAIN_PORz, or  
SW_MAIN_WARMRST)  
RST9 tw(RESETSTATzL)  
301200  
ns  
(1) S = MCU_OSC0_XI/XO clock period  
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Figure 7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
Table 7-8. MCU_RESETz Timing Requirements  
see Figure 7-7  
NO.  
MIN  
MAX UNIT  
(1)  
RST10 tw(MCU_RESETzL)  
Pulse Width minimum, MCU_RESETz active (low)  
1200  
ns  
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
Table 7-9. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
see Figure 7-7  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_RESETz active (low) to  
MCU_RESETSTATz active (low)  
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)  
0
ns  
Delay time, MCU_RESETz inactive (high) to  
MCU_RESETSTATz inactive (high)  
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)  
RST13 td(MCU_RESETzL-RESETSTATzL)  
966*S(1)  
0
ns  
ns  
ns  
Delay time, MCU_RESETz active (low) to  
RESETSTATz active (low)  
RST14 td(MCU_RESETzH-RESETSTATzH)  
Delay time, MCU_RESETz inactive (high) to  
RESETSTATz inactive (high)  
4040*S(1)  
(1) S = MCU_OSC0_XI/XO clock period  
Figure 7-7. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching  
Characteristics  
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Table 7-10. RESET_REQz Timing Requirements  
see Figure 7-8  
NO.  
MIN  
MAX UNIT  
(1)  
RST15 tw(RESET_REQzL)  
Pulse Width minimum, RESET_REQz active (low)  
1200  
ns  
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
Table 7-11. RESETSTATz Switching Characteristics  
see Figure 7-8  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, RESET_REQz active (low) to  
RESETSTATz active (low)  
RST16 td(RESET_REQzL-RESETSTATzL)  
T(1)  
ns  
Delay time, RESET_REQz inactive (high) to  
RESETSTATz inactive (high)  
RST17 td(RESET_REQzH-RESETSTATzH)  
W(2)  
ns  
(1) T = Reset Isolation Time (Software Dependent)  
(2) W = Max [300 μs (Typical) from RESETz_REQz inactive (high), Reset Isolation Time + 300 μs (TYP) from RESET_REQz active (low)]  
Figure 7-8. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics  
Table 7-12. EMUx Timing Requirements  
see Figure 7-9  
NO.  
MIN  
MAX UNIT  
Setup time, EMU[1:0] before MCU_PORz inactive  
(high)  
RST18 tsu(EMUx-MCU_PORz)  
3*S(1)  
ns  
Hold time, EMU[1:0] after MCU_PORz inactive  
(high)  
RST19 th(MCU_PORz - EMUx)  
10  
ns  
(1) S = MCU_OSC0_XI/XO clock period  
Figure 7-9. EMUx Timing Requirements  
Table 7-13. BOOTMODE Timing Requirements  
see Figure 7-10  
NO.  
MIN  
MAX UNIT  
Setup time, BOOTMODE[15:00] before  
PORz_OUT high (External MCU PORz event or  
Software SW_MAIN_PORz)  
RST23 tsu(BOOTMODE-PORz_OUT)  
3*S(1)  
ns  
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Table 7-13. BOOTMODE Timing Requirements (continued)  
see Figure 7-10  
NO.  
MIN  
MAX UNIT  
Hold time, BOOTMODE[15:00] after PORz_OUT  
high (External MCU PORz event, Software  
SW_MAIN_PORz)  
RST24 th(PORz_OUT - BOOTMODE)  
0
ns  
(1) S = MCU_OSC0_XI/XO clock period  
Table 7-14. PORz_OUT Switching Characteristics  
see Figure 7-10  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_PORz active (low) to  
PORz_OUT active (low)  
RST25 td(MCU_PORzL-PORz_OUT)  
0
ns  
Delay time, MCU_PORz inactive (high) to  
PORz_OUT inactive (high)  
RST26 td(MCU_PORzH-PORz_OUT)  
RST27 tw(PORz_OUTL)  
0
ns  
ns  
Pulse Width Minimum PORz_OUT low  
(MCU_PORz, SW_MAIN_PORz)  
1200  
Figure 7-10. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics  
7.10.3.2 Safety Signal Timing  
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn.  
Table 7-15. MCU_SAFETY_ERRORn Switching Characteristics  
see Figure 7-11  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Cycle time minimum, MCU_SAFETY_ERRORn  
(PWM mode enabled)  
SFTY1 tc(MCU_SAFETY_ERRORn)  
(P*H)+(P*L)(1) (3) (4)  
ns  
Pulse width minimum, MCU_SAFETY_ERRORn  
active (PWM mode disabled)(5)  
SFTY2 tw(MCU_SAFETY_ERRORn)  
P*R(1) (2)  
50*P(1)  
ns  
ns  
td (ERROR_CONDITION-  
Delay time, ERROR CONDITION to  
MCU_SAFETY_ERRORn active(5)  
SFTY3  
MCU_SAFETY_ERRORnL)  
(1) P = ESM functional clock  
(2) R = Error Pin Counter Pre-Load Register count value  
(3) H = Error Pin PWM High Pre-Load Register count value  
(4) L = Error Pin PWM Low Pre-Load Register count value  
(5) When PWM mode is enabled, MCU_SAFETY_ERRORn stops toggling after RST22 and will maintain its value (either high or low) until  
the error is cleared. When PWM mode is disabled, MCU_SAFETY_ERRORn is active low.  
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Figure 7-11. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics  
7.10.3.3 Clock Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for clock  
signals.  
Table 7-16. Clock Timng Requiements  
see Figure 7-12  
NO.  
MIN  
10  
MAX UNIT  
CLK1 tc(EXT_REFCLK1)  
CLK2 tw(EXT_REFCLK1H)  
CLK3 tw(EXT_REFCLK1L)  
Cycle time minimum, EXT_REFCLK1  
ns  
Pulse Duration minimum, EXT_REFCLK1 high  
Pulse Duration minimum, EXT_REFCLK1 low  
E*0.45(1)  
E*0.45(1)  
E*0.55(1)  
E*0.55(1)  
ns  
ns  
(1) E = EXT_REFCLK1 cycle time  
Figure 7-12. Clock Timing Requirements  
Table 7-17. Clock Switching Characteristics  
see Figure 7-13  
NO.  
PARAMETER  
MIN  
8
MAX UNIT  
CLK4 tc(SYSCLKOUT0)  
CLK5 tw(SYSCLKOUT0H)  
CLK6 tw(SYSCLKOUT0L)  
CLK7 tc(OBSCLK0)  
Cycle time minimum,SYSCLKOUT0  
Pulse Duration minimum, SYSCLKOUT0 high  
Pulse Duration minimum, SYSCLKOUT0 low  
Cycle time minimum, OBSCLK0  
ns  
A*0.4(1)  
A*0.4(1)  
5
A*0.6(1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A*0.6(1)  
CLK8 tw(OBSCLK0H)  
CLK9 tw(OBSCLK0L)  
CLK10 tc(CLKOUT0)  
Pulse Duration minimum, OBSCLK0 high  
Pulse Duration minimum,OBSCLK0 low  
Cycle time minimum, CLKOUT0  
B*0.45(2)  
B*0.45(2)  
20  
B*0.55(2)  
B*0.55(2)  
CLK11 tw(CLKOUT0H)  
CLK12 tw(CLKOUT0L)  
Pulse Duration minimum, CLKOUT0 high  
Pulse Duration minimum,CLKOUT0 low  
C*0.4(3)  
C*0.4(3)  
C*0.6(3)  
C*0.6(3)  
(1) A = SYSCLKOUT0 cycle time  
(2) B = OBSCLK0 cycle time  
(3) C = CLKOUT0 cycle time  
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Figure 7-13. Clock Switching Characteristics  
7.10.4 Clock Specifications  
7.10.4.1 Input Clocks / Oscillators  
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as  
follows:  
•
MCU_OSC0_XI/MCU_OSC0_XO — Еxternal main crystal interface pins connected to the internal high-  
frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock  
MCU_HFOSC0_CLKOUT.  
•
General purpose clock inputs  
– MCU_EXT_REFCLK0 — Optional external system clock input for MCU domain.  
– EXT_REFCLK1 — Optional external system clock input for MAIN domain.  
– SERDES0_REFCLK0P/N — Optional SERDES0 reference clock input for PCIe.  
External CPTS reference clock inputs  
•
– CP_GEMAC_CPTS0_RFT_CLK — CPTS reference clock input.  
– CPTS_RFT_CLK — CPTS reference clock input.  
Figure 7-14 shows the external input clock sources and the output clocks to peripherals.  
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DEVICE  
Reference Clock Output  
CLKOUT  
Main Domain System Clock (MAIN_SYSCLK0) divided-by-4  
MCU Domain System Clock (MCU_SYSCLK0) divided-by-4  
SYSCLKOUT0  
MCU_SYSCLKOUT0  
MCU_OSC0_XI  
MCU_OSC0_XO  
External main crystal interface pins connected to internal oscillator  
which provides reference clock to PLLs within MCU domain  
and MAIN domain.  
JTAG Clock Input  
TCK  
MCU Warm Reset Input / Device Warm Reset Input  
MCU_RESETz  
MCU_PORz  
MCU Power ON Reset / Device Power ON Reset  
Boot Mode Configuration / Devices Select  
DDR Differential Clock Outputs  
BOOTMODE[15:00]  
DDR0_CK0/DDR0_CK0_n  
SERDES0_REFCLK0P/N  
Optional SERDES0 Reference Clock Input for PCIe  
Observation Clock Outputs for MCU Domain Clock / MAIN Domain Clocks  
Optional External System Clock Inputs - (MCU Domain) / (MAIN Domain)  
MCU_OBSCLK0 / OBSCLK0  
MCU_EXT_REFCLK0 / EXT_REFCLK1  
CPTS Reference Clock Inputs  
CP_GEMAC_CPTS0_RFT_CLK / CPTS0_RFT_CLK  
CP_GEMAC_CPTS0_RFT_CLK /  
CPTS0_RFT_CLK  
J7ES_CLOCK_01  
Figure 7-14. Input Clocks Interface  
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the  
device TRM.  
7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source  
Figure 7-15 shows the recommended crystal circuit. All discrete components used to implement the oscillator  
circuit should be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.  
Device  
MCU_OSC0_XO  
MCU_OSC0_XI  
Crystal  
CL2  
CL1  
PCB Ground  
AM65x_MCU_OSC_INT_01  
Figure 7-15. MCU_OSC0 Crystal Implementation  
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The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-18 summarizes the  
required electrical constraints.  
Table 7-18. MCU_OSC0 Crystal Circuit Requirements  
PARAMETER  
Fxtal  
MIN  
TYP  
25  
MAX UNIT  
MHz  
Crystal Parallel Resonance Frequency  
Crystal Frequency Stability and Tolerance  
Fxtal  
Ethernet RGMII and RMII  
not used  
±100  
ppm  
Ethernet RGMII and RMII  
using derived clock  
±50  
CL1+PCBXI  
CL2+PCBXO  
CL  
Capacitance of CL1 + CPCBXI  
Capacitance of CL2 + CPCBXO  
Crystal Load Capacitance  
12  
12  
6
24  
24  
12  
7
pF  
pF  
pF  
pF  
pF  
pF  
Ω
Cshunt  
Crystal Circuit Shunt Capacitance  
ESRxtal = 30 Ω  
25 MHz  
25 MHz  
25 MHz  
ESRxtal = 40 Ω  
ESRxtal = 50 Ω  
5
5
ESRxtal  
Crystal Effective Series Resistance  
100  
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal  
based on worst case environment and expected life expectancy of the system.  
Table 7-19 details the switching characteristics of the oscillator.  
Table 7-19. MCU_OSC0 Switching Characteristics - Crystal Mode  
PARAMETER  
MIN  
TYP  
MAX UNIT  
1.44  
CXI  
XI Capacitance  
pF  
pF  
pF  
ms  
CXO  
CXIXO  
ts  
XO Capacitance  
1.52  
XI to XO Mutual Capacitance  
Start-up Time  
0.01  
4
VDD_MCU (min.)  
VDD_MCU  
VSS  
VDDS_OSC0 (min.)  
VDDS_OSC0  
MCU_OSC0_XO  
tsX  
VSS  
Time  
AM65x_MCU_OSC_STARTUP_02  
Figure 7-16. MCU_OSC0 Start-up Time  
7.10.4.1.1.1 Load Capacitance  
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined  
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors  
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to  
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the  
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PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits  
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic  
capacitance values are defined in Table 7-19.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
MCU_OSC0_XI  
CL1  
CPCBXI  
CXI  
CL2  
CPCBXO  
CXO  
MCU_OSC0_XO  
AM65x_MCU_OSC_CC_05  
Figure 7-17. Load Capacitance  
Load capacitors, CL1 and CL2 in Figure 7-15, should be chosen such that the below equation is satisfied. CL in  
the equation is the load specified by the crystal manufacturer.  
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]  
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the  
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to  
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO  
=
0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -  
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF  
7.10.4.1.1.2 Shunt Capacitance  
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for  
MCU_OSC0 operating conditions defined in Table 7-18. Shunt capacitance, Cshunt, of the crystal circuit is a  
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal  
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB  
designer should be able to extract mutual parasitic capacitance between these signal traces. The device  
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined  
in Table 7-19.  
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is  
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can  
also be minimized by placing a ground trace between these signals when the layout requires them to be routed  
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as  
possible when selecting a crystal.  
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Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
MCU_OSC0_XI  
CPCBXIXO  
CXIXO  
CO  
MCU_OSC0_XO  
AM65x_MCU_OSC_SC_06  
Figure 7-18. Shunt Capacitance  
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt  
capacitance specified by the crystal manufacturer.  
Cshunt ≥ CO + CPCBXIXO + CXIXO  
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,  
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.  
7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source  
Figure 7-19 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V  
LVCMOS square-wave digital clock source.  
Note  
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This  
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that may enter a  
unknown state when DC is applied to the input. Therefore, application software should power down  
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.  
Device  
MCU_OSC0_XO  
MCU_OSC0_XI  
PCB Ground  
AM65x_MCU_OSC_EXT_CLK_03  
Figure 7-19. 1.8-V LVCMOS-Compatible Clock Input  
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7.10.4.2 Output Clocks  
The device provides several system clock outputs. Summary of these output clocks are as follows:  
•
MCU_SYSCLKOUT0  
– MCU_SYSCLKOUT0 is the MCU Domain system clock (MCU_SYSCK0) divided-by-4. This clock output is  
provided for test and debug purposes only.  
•
•
MCU_OBSCLK0  
– Observation clock output for test and debug purposes only.  
SYSCLKOUT0  
– SYSCLKOUT0 is the Main domain system clock (MAIN_SYSCLK0) divided-by-4. This clock output is  
provided for test and debug purposes only.  
•
CLKOUT0  
– CLKOUT0 is the Ethernet Subsytem clock (MAIN_PLL0_HSDIV4_CLKOUT) divided-by-5 or divided-  
by-10. This clock output was provided to source to the external PHY. When configured to operate as  
the RMII Clock source (50 MHz), it must also routed back to the RMII_REF_CLK pin for proper device  
operation.  
•
•
OBSCLK0  
– Observation clock output for test and debug purposes only.  
GPMC_FCLK_MUX  
– GPMC_FCLK_MUX is the GPMC0 functional clock (GPMC_FCLK). This clock is provided as an  
alternative GPMC interface clock when attached devices require a continuous running clock.  
For more information, see Clock Outputs section in Clocking chapter and GPMC Clock Configuration section in  
Peripherals chapter in the device TRM.  
7.10.4.3 PLLs  
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from  
off-chip power-sources.  
There is one PLL in the MCU domain:  
•
MCU0_PLL  
There are six PLLs in the MAIN domain:  
•
•
•
•
•
•
ARM0_PLL  
MAIN_PLL  
PER0_PLL  
PER1_PLL  
DDR PLL  
R5F PLL  
Note  
For more information, see:  
•
•
Device Configuration / Clocking / PLLs section in the device TRM.  
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit  
(PRU_ICSSG) section in the device TRM.  
Note  
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is  
ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.  
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7.10.5 Peripherals  
7.10.5.1 CPSW3G  
For more details about features and additional description information on the device Gigabit Ethernet MAC, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
7.10.5.1.1 CPSW3G MDIO Timing  
Table 7-20, Table 7-21, Table 7-22, and Figure 7-20 present timing conditions, requirements, and switching  
characteristics for CPSW3G MDIO.  
Table 7-20. CPSW3G MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
Table 7-21. CPSW3G MDIO Timing Requirements  
see Figure 7-20  
NO.  
PARAMETER  
MIN  
90  
0
MAX  
UNIT  
ns  
MDIO1 tsu(MDIO_MDC)  
MDIO2 th(MDC_MDIO)  
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high  
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high  
ns  
Table 7-22. CPWS3G MDIO Switching Characteristics  
see Figure 7-20  
NO.  
PARAMETER  
MIN  
400  
160  
160  
-150  
MAX  
UNIT  
ns  
MDIO3 tc(MDC)  
Cycle time, MDIO[x]_MDC  
MDIO4 tw(MDCH)  
MDIO5 tw(MDCL)  
MDIO7 td(MDC_MDIO)  
Pulse Duration, MDIO[x]_MDC high  
Pulse Duration, MDIO[x]_MDC low  
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid  
ns  
ns  
150  
ns  
MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
Figure 7-20. CPSW3G MDIO Timing Requirements and Switching Characteristics  
7.10.5.1.2 CPSW3G RMII Timing  
Table 7-23, Table 7-24, Figure 7-21, Table 7-25, Figure 7-22 Table 7-26, and Figure 7-23 present timing  
conditions, requirements, and switching characteristics for CPSW3G RMII.  
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Table 7-23. CPSW3G RMII Timing Conditions  
PARAMETER  
MIN  
INPUT CONDITIONS  
VDDSHVx(1) = 1.8V  
VDDSHVx(1) = 3.3V  
0.18  
0.4  
0.54 V/ns  
1.2 V/ns  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
3
25  
pF  
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to the Pin Attributes section, for more information on IO power rail  
assignments.  
Table 7-24. RMII[x]_REF_CLK Timing Requirements – RMII Mode  
see Figure 7-21  
NO.  
PARAMETER  
tc(REF_CLK)  
tw(REF_CLKH)  
tw(REF_CLKL)  
DESCRIPTION  
Cycle time, RMII[x]_REF_CLK  
MIN  
MAX  
20.001  
13  
UNIT  
ns  
RMII1  
RMII2  
RMII3  
19.999  
Pulse Duration, RMII[x]_REF_CLK High  
Pulse Duration, RMII[x]_REF_CLK Low  
7
7
ns  
13  
ns  
RMII1  
RMII2  
RMII[x]_REF_CLK  
RMII3  
Figure 7-21. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode  
Table 7-25. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode  
see Figure 7-22  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
4
MAX  
UNIT  
ns  
RMII4  
tsu(RXD-REF_CLK)  
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK  
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK  
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK  
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK  
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK  
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK  
tsu(CRS_DV-REF_CLK)  
tsu(RX_ER-REF_CLK)  
th(REF_CLK-RXD)  
4
ns  
4
ns  
RMII5  
2
ns  
th(REF_CLK-CRS_DV)  
th(REF_CLK-RX_ER)  
2
ns  
2
ns  
RMII4  
RMII5  
RMII[x]_REF_CLK  
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,  
RMII[x]_RX_ER  
Figure 7-22. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII  
Mode  
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Table 7-26. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode  
see Figure 7-23  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
RMII6 td(REF_CLK-TXD)  
Delay time, RMII[x]_REF_CLK High to RMII[x]_  
TXD[1:0] valid  
2
10  
ns  
td(REF_CLK-TX_EN)  
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN  
valid  
2
10  
ns  
RMII6  
RMII[x]_REF_CLK  
RMII[x]_TXD[1:0], RMII[x]_TX_EN  
Figure 7-23. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode  
7.10.5.1.3 CPSW3G RGMII Timing  
Table 7-27, Table 7-28, Table 7-29, Figure 7-24, Table 7-30, Table 7-31, and Figure 7-25 present timing  
conditions, requirements, and switching characteristics for CPSW3G RGMII.  
Table 7-27. CPSW3G RGMII Timing Conditions  
PARAMETER  
MIN  
2.64  
2
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
5
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
PCB CONNECTIVITY REQUIREMENTS  
RGMII[x]_RXC,  
RGMII[x]_RD[3:0],  
RGMII[x]_RX_CTL  
50  
50  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
Delay)  
RGMII[x]_TXC,  
RGMII[x]_TD[3:0],  
RGMII[x]_TX_CTL  
Table 7-28. RGMII[x]_RXC Timing Requirements – RGMII Mode  
see Figure 7-24  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_RXC  
MODE  
10Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII1 tc(RXC)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
RGMII2 tw(RXCH)  
Pulse duration, RGMII[x]_RXC high  
Pulse duration, RGMII[x]_RXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
RGMII3 tw(RXCL)  
100Mbps  
1000Mbps  
3.6  
4.4  
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Table 7-29. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode  
see Figure 7-24  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
1
MAX UNIT  
RGMII4 tsu(RD-RXC)  
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
1
1
tsu(RX_CTL-RXC)  
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
10Mbps  
1
1
RGMII5 th(RXC-RD)  
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
10Mbps  
1
1
th(RXC-RX_CTL)  
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
1
1
RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
RGMII[x]_RX_CTL(B)  
1st Half-byte  
RXDV  
2nd Half-byte  
RXERR  
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of  
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.  
Figure 7-24. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII  
Mode  
Table 7-30. RGMII[x]_TXC Switching Characteristics – RGMII Mode  
see Figure 7-25  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_TXC  
MODE  
10Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII6 tc(TXC)  
RGMII7 tw(TXCH)  
RGMII8 tw(TXCL)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_TXC high  
Pulse duration, RGMII[x]_TXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
100Mbps  
1000Mbps  
3.6  
4.4  
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Table 7-31. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode  
see Figure 7-25  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
MAX UNIT  
RGMII9 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC  
high/low  
100Mbps  
1000Mbps  
10Mbps  
RGMII10 toh(TXC-TD)  
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC  
high/low  
100Mbps  
1000Mbps  
10Mbps  
toh(TXC-TX_CTL)  
Output hold time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
100Mbps  
1000Mbps  
RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of  
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.  
Figure 7-25. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics  
- RGMII Mode  
7.10.5.2 DDRSS  
For more details about features and additional description information on the device (LP)DDR4 Memory  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-32 and Figure 7-26 present switching characteristics for DDRSS.  
Table 7-32. DDRSS Switching Characteristics  
see Figure 7-26  
NO.  
PARAMETER  
DDR TYPE  
LPDDR4  
DDR4  
MIN  
1.25  
1.25  
MAX UNIT  
20  
ns  
ns  
tc(DDR_CKP/  
1
Cycle time, DDR_CKP and DDR_CKN  
DDR_CKN)  
1.6  
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DDR0_CKP  
DDR0_CKN  
Figure 7-26. DDRSS Switching Characteristics  
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.  
7.10.5.3 ECAP  
Table 7-33, Table 7-34, Figure 7-27, Table 7-35, and Figure 7-28 present timing conditions, requirements, and  
switching characteristics for ECAP.  
Table 7-33. ECAP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
Table 7-34. ECAP Timing Requirements  
see Figure 7-27  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CAP (asynchronous)  
MIN  
2 + 2P(1)  
MAX  
UNIT  
CAP1 tw(CAP)  
ns  
(1) P = sysclk period in ns.  
CAP1  
CAP  
EPERIPHERALS_TIMNG_01  
Figure 7-27. ECAP Timings Requirements  
Table 7-35. ECAP Switching Characteristics  
see Figure 7-28  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
CAP2 tw(APWM)  
Pulse duration, APWMx high/low  
-2 + 2P(1)  
ns  
(1) P = sysclk period in ns.  
CAP2  
APWM  
EPERIPHERALS_TIMNG_02  
Figure 7-28. ECAP Switching Characteristics  
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.  
7.10.5.4 EPWM  
Table 7-36, Table 7-37, Figure 7-29, Table 7-38, Figure 7-30, Figure 7-31, and Figure 7-32 present timing  
conditions, requirements, and switching characteristics for EPWM.  
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Table 7-36. EPWM Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
Table 7-37. EPWM Timing Requirements  
see Figure 7-29  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_SYNCI  
MIN  
2 + 2P(1)  
2 + 3P(1)  
MAX  
UNIT  
ns  
PWM6 tw(SYNCIN)  
PWM7 tw(TZ)  
Pulse duration, EHRPWM_TZn_IN low  
ns  
(1) P = sysclk period in ns.  
PWM6  
EHRPWM_SYNCI  
PWM7  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMNG_07  
Figure 7-29. EPWM Timing Requirements  
Table 7-38. EPWM Switching Characteristics  
see Figure 7-30, Figure 7-31, and Figure 7-32  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_A/B high/low  
Pulse duration, EHRPWM_SYNCO  
MIN  
P - 3(1)  
P - 3(1)  
MAX  
UNIT  
PWM1 tw(PWM)  
ns  
ns  
ns  
PWM2 tw(SYNCOUT)  
PWM3 td(TZ-PWM)  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced  
high/low  
11  
11  
PWM4 td(TZ-PWMZ)  
PWM5 tw(SOC)  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z  
Pulse duration, EHRPWM_SOCA/B output  
ns  
ns  
P - 3(1)  
(1) P = sysclk period in ns.  
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PWM1  
EHRPWM_A/B  
PWM1  
PWM2  
EHRPWM_SYNCO  
EHRPWM_SOCA/B  
PWM5  
EPERIPHERALS_TIMNG_04  
Figure 7-30. EHRPWM Switching Characteristics  
PWM3  
EHRPWM_A/B  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMING_05  
Figure 7-31. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics  
PWM4  
EHRPWM_A/B  
EHRPWM_TZn_IN  
Figure 7-32. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in  
the device TRM.  
7.10.5.5 EQEP  
Table 7-39, Table 7-40, Figure 7-33, and Table 7-41 present timing conditions, requirements, and switching  
characteristics for EQEP.  
Table 7-39. EQEP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
Table 7-40. EQEP Timing Requirements  
see Figure 7-33  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2 + 2P(1)  
2 + 2P(1)  
MAX  
UNIT  
ns  
QEP1  
QEP2  
tw(QEP)  
Pulse duration, QEP_A/B  
Pulse duration, QEP_I high  
tw(QEPIH)  
ns  
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Table 7-40. EQEP Timing Requirements (continued)  
see Figure 7-33  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
MAX  
UNIT  
ns  
QEP3  
QEP4  
QEP5  
tw(QEPIL)  
tw(QEPSH)  
tw(QEPSL)  
Pulse duration, QEP_I low  
Pulse duration, QEP_S high  
Pulse duration, QEP_S low  
ns  
ns  
(1) P = sysclk period in ns  
QEP1  
QEP_A/B  
QEP2  
QEP_I  
QEP3  
QEP4  
QEP_S  
QEP5  
EPERIPHERALS_TIMNG_03  
Figure 7-33. EQEP Timing Requirements  
Table 7-41. EQEP Switching Characteristics  
NO.  
PARAMETER  
td(QEP-CNTR)  
DESCRIPTION  
MIN  
MAX  
UNIT  
QEP6  
Delay time, external clock to counter increment  
24  
ns  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter  
in the device TRM.  
7.10.5.6 FSI  
Table 7-42, Table 7-43, Figure 7-34, Table 7-44, Figure 7-35, Table 7-45, and Figure 7-36 present timing  
conditions, requirements, and switching characteristics for FSI.  
Table 7-42. FSI Timing Conditions  
PARAMETER  
MIN  
0.8  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
Table 7-43. FSI Timing Requirements  
see Figure 7-34  
NO.  
MIN  
MAX  
UNIT  
ns  
FSIR1 tc(RX_CLK)  
Cycle time, FSI_RXn_CLK  
20  
FSIR2 tw(RX_CLK)  
Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high  
Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK  
Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK  
0.5P - 1(1) 0.5P + 1(1)  
ns  
FSIR3 tsu(RX_D-RX_CLK)  
FSIR4 th(RX_CLK-RX_D)  
3
ns  
2.5  
ns  
(1) P = FSI_RXn_CLK period in ns.  
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FSIR1  
FSIR2  
FSIR2  
FSI_RXn_CLK  
FSI_RXn_D0  
FSI_RXn_D1  
FSIR3  
FSIR4  
Figure 7-34. FSI Timing Requirements  
Table 7-44. FSI Switching Characteristics - FSI Mode  
see Figure 7-35  
NO.  
PARAMETER  
MODE  
MIN  
20  
0.5p + 1(1)  
0.25P - 2(1)  
MAX UNIT  
FSIT1 tc(TX_CLK)  
Cycle time, FSI_TXn_CLK  
FSI Mode  
FSI Mode  
FSI Mode  
ns  
FSIT2 tw(TX_CLK)  
FSIT3 td(TX_CLK-TX_D)  
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high  
0.5P - 1(1)  
ns  
ns  
Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK  
high or FSI_TXn_CLK low  
0.25P +  
2.5(1)  
(1) P = FSI_TXn_CLK period in ns.  
FSIT1  
FSIT2  
FSIT2  
FSI_TXn_CLK  
FSI_TXn_D0  
FSI_TXn_D1  
FSIT3  
Figure 7-35. FSI Switching Characteristics - FSI Mode  
Table 7-45. FSI Switching Characteristics - SPI Mode  
see Figure 7-36  
NO.  
PARAMETER  
MODE  
MIN  
20  
0.5P + 1(1)  
MAX UNIT  
FSIT4 tc(TX_CLK)  
FSIT5 tw(TX_CLK)  
Cycle time, FSI_TXn_CLK  
SPI Mode  
SPI Mode  
SPI Mode  
SPI Mode  
SPI Mode  
ns  
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high  
0.5P - 1(1)  
ns  
ns  
ns  
ns  
FSIT6 td(TX_CLKH-TX_D0) Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid  
3
FSIT7 td(TX_D1-TX_CLK)  
FSIT8 td(TX_CLK-TX_D1)  
Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high  
Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high  
P - 3(1)  
P - 2(1)  
(1) P = FSI_TXn_CLK period in ns.  
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FSIT4  
FSIT5  
FSIT5  
FSI_TXn_CLK  
FSIT6  
FSI_TXn_D0  
FSI_TXn_D1  
FSIT8  
FSIT7  
Figure 7-36. FSI Switching Characteristics - SPI Mode  
For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.  
7.10.5.7 GPIO  
Table 7-46, Table 7-47, and Table 7-48 present timing conditions, requirements, and switching characteristics for  
GPIO.  
For more details about features and additional description information on the device GPIO, see the  
corresponding subsections within Signal Descriptions and Detailed Description sections.  
Note  
The device has multiple GPIO modules. GPIOn_x is generic name used to describe a GPIO signal,  
where n represents the specific GPIO module and x represents one of the input/output signals  
associated with the module.  
Table 7-46. GPIO Timing Conditions  
PARAMETER  
BUFFER TYPE  
MIN  
MAX UNIT  
INPUT CONDITIONS  
LVCMOS  
0.75  
TBD  
6.6 V/ns  
SRI  
Input slew rate  
I2C OD FS  
TBD V/ns  
OUTPUT CONDITIONS  
LVCMOS  
3
3
10  
pF  
pF  
CL  
Output load capacitance  
I2C OD FS  
100  
Table 7-47. GPIO Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
BUFFER TYPE  
MIN  
MAX UNIT  
LVCMOS  
2P + 2.6(1)  
2P + 2.6(1)  
ns  
ns  
GPIO1 tw(GPIO_IN)  
Pulse width, GPIOn_x  
I2C OD FS  
(1) P = functional clock period in ns.  
Table 7-48. GPIO Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
BUFFER TYPE  
MIN  
MAX UNIT  
-3.6 +  
LVCMOS  
ns  
ns  
0.975P(1)  
GPIO2 tw(GPIO_OUT)  
Pulse width, GPIOn_x  
I2C OD FS  
160  
(1) P = functional clock period in ns.  
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.  
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7.10.5.8 GPMC  
For more details about features and additional description information on the device General-Purpose Memory  
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-49 presents timing conditions for GPMC.  
Table 7-49. GPMC Timing Conditions  
PARAMETER  
MIN  
1.65  
5
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
PCB CONNECTIVITY REQUIREMENTS  
133 MHz Synchronous Mode  
All other modes  
140  
140  
360  
720  
ps  
ps  
td(Trace Delay)  
Propagation delay of each trace  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
200  
ps  
Delay)  
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the  
device TRM.  
7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode  
Table 7-50 and Table 7-51 present timing requirements and switching characteristics for GPMC and NOR Flash -  
Synchronous Mode.  
Table 7-50. GPMC and NOR Flash Timing Requirements — Synchronous Mode  
see Figure 7-37, Figure 7-38, and Figure 7-41  
MIN  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(4)  
UNIT  
GPMC_FCLK = GPMC_FCLK =  
100 MHz(1)  
133 MHz(1)  
F12 tsu(dV-clkH)  
F13 th(clkH-dV)  
F21 tsu(waitV-clkH)  
F22 th(clkH-waitV)  
Setup time, input data  
GPMC_AD[15:0] valid before output  
clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.81  
1.11  
ns  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.06  
2.28  
2.28  
1.81  
1.06  
2.28  
2.8  
3.50  
2.28  
2.28  
1.11  
3.50  
2.28  
2.28  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Hold time, input data  
GPMC_AD[15:0] valid after output  
clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Setup time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_WAIT[j](2) (3) valid before  
output clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Hold time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_WAIT[j](2) (3) valid after  
output clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
(1) GPMC_FCLK select  
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•
•
gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK  
gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK  
(2) In GPMC_WAIT[j], j is equal to 0 or 1.  
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-  
Purpose Memory Controller (GPMC) section in the device TRM.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
GPMC_CLK frequency = GPMC_FCLK frequency  
For not_div_by_1_mode:  
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:  
GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
–
•
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
Table 7-51. GPMC and NOR Flash Switching Characteristics – Synchronous Mode  
see Figure 7-37, Figure 7-38, Figure 7-39, Figure 7-40, and Figure 7-41  
MIN  
100 MHz  
10.00  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(2)  
133 MHz  
F0 1 / tc(clk)  
F1 tw(clkH)  
F1 tw(clkL)  
tdc(clk)  
Period, output clock GPMC_CLK(15)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
7.52  
ns  
Typical pulse duration, output clock  
GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
0.475P  
- 0.3(14)  
0.475P  
ns  
ns  
- 0.3(14)  
Typical pulse duration, output clock  
GPMC_CLK low  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
0.475P  
- 0.3(14)  
0.475P  
- 0.3(14)  
Duty cycle error, output clock  
GPMC_CLK  
div_by_1_mode;  
GPMC_FCLK_MUX;  
-500.00 500.00 -500.00 500.00 ps  
TIMEPARAGRANULARITY_X1  
tJ(clk)  
Jitter standard deviation, output clock  
GPMC_CLK(16)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
33.33  
2.0  
33.33 ps  
2.0 ns  
2.0 ns  
2.0 ns  
2.0 ns  
tR(clk)  
Rise time, output clock GPMC_CLK  
Fall time, output clock GPMC_CLK  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
tF(clk)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.0  
tR(do)  
Rise time, output data  
GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.0  
tF(do)  
Fall time, output data  
GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.0  
TIMEPARAGRANULARITY_X1  
F2 td(clkH-csnV)  
Delay time, output clock GPMC_CLK  
rising edge to output chip select  
GPMC_CSn[i] transition(13)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
F - 2.2  
F + F - 2.2  
3.75  
F + ns  
3.75  
(5)  
(5)  
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Table 7-51. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)  
see Figure 7-37, Figure 7-38, Figure 7-39, Figure 7-40, and Figure 7-41  
MIN  
100 MHz  
E - 2.2  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(2)  
133 MHz  
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK  
rising edge to output chip select  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
E + E - 2.2 E + 4.5 ns  
(4)  
(4)  
1.31  
GPMC_CSn[i] invalid(13)  
F4 td(aV-clk)  
Delay time, output address  
GPMC_A[27:1] valid to output clock  
GPMC_CLK first edge  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
B - 2.3 B + 4.5 B - 2.3 B + 4.5 ns  
(2)  
(2)  
F5 td(clkH-aIV)  
Delay time, output clock GPMC_CLK  
rising edge to output address  
GPMC_A[27:1] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
-2.3  
4.5  
-2.3  
4.5 ns  
F6 td(be[x]nV-clk)  
Delay time, output lower byte  
enable and command latch enable  
div_by_1_mode;  
GPMC_FCLK_MUX;  
B - 2.3 B + 1.9 B - 2.3 B + 1.9 ns  
(2)  
(2)  
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1  
enable GPMC_BE1n valid to output  
clock GPMC_CLK first edge  
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK  
rising edge to output lower byte  
div_by_1_mode;  
GPMC_FCLK_MUX;  
D - D + 1.9 D - 2.3 D + 1.9 ns  
2.3(3)  
(3)  
enable and command latch enable  
TIMEPARAGRANULARITY_X1  
GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n invalid(10)  
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
invalid(11)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns  
(3)  
(3)  
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
invalid(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns  
(3)  
(3)  
F8 td(clkH-advn)  
F9 td(clkH-advnIV)  
F10 td(clkH-oen)  
F11 td(clkH-oenIV)  
F14 td(clkH-wen)  
Delay time, output clock GPMC_CLK  
rising edge to output address  
valid and address latch enable  
GPMC_ADVn_ALE transition  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
G - G + 4.5 G - 2.3 G + 4.5 ns  
2.3(6)  
(6)  
Delay time, output clock GPMC_CLK  
rising edge to output address  
valid and address latch enable  
GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
D - 2.3 D + 4.5 D - 2.3 D + 4.5 ns  
(3)  
(3)  
Delay time, output clock GPMC_CLK  
rising edge to output enable  
GPMC_OEn_REn transition  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3H H + 3.5 H - 2.3 H + 3.5 ns  
(7)  
(7)  
Delay time, output clock GPMC_CLK  
rising edge to output enable  
GPMC_OEn_REn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
E - 2.3 E + 3.5 E - 2.3 E + 3.5 ns  
(7)  
(7)  
Delay time, output clock GPMC_CLK  
rising edge to output write enable  
GPMC_WEn transition  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
I - 2.3 I + 4.5 I - 2.3 I + 4.5 ns  
(8)  
(8)  
F15 td(clkH-do)  
F15 td(clkL-do)  
F15 td(clkL-do).  
Delay time, output clock GPMC_CLK  
rising edge to output data  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(9)  
(9)  
GPMC_AD[15:0] transition(10)  
Delay time, GPMC_CLK falling  
edge to GPMC_AD[15:0] data bus  
transition(11)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(9)  
(9)  
Delay time, GPMC_CLK falling  
edge to GPMC_AD[15:0] data bus  
transition(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(9)  
(9)  
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Table 7-51. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)  
see Figure 7-37, Figure 7-38, Figure 7-39, Figure 7-40, and Figure 7-41  
MIN  
100 MHz  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(2)  
133 MHz  
F17 td(clkH-be[x]n)  
Delay time, output clock GPMC_CLK  
rising edge to output lower byte  
enable and command latch enable  
GPMC_BE0n_CLE transition(10)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
(9)  
(9)  
F17 td(clkL-be[x]n)  
Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
transition(11)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
(9)  
(9)  
F17 td(clkL-be[x]n).  
Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
transition(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
(9)  
(9)  
F18 tw(csnV)  
Pulse duration, output chip select  
GPMC_CSn[i](13) low  
Read  
Write  
Read  
Write  
A
A
C
C
A
A
C
C
ns  
ns  
ns  
ns  
F19 tw(be[x]nV)  
Pulse duration, output lower byte  
enable and command latch enable  
GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n low  
F20 tw(advnV)  
Pulse duration, output address  
valid and address latch enable  
GPMC_ADVn_ALE low  
Read  
Write  
K
K
K
K
ns  
ns  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
With n being the page burst access number.  
(2) B = ClkActivationTime × GPMC_FCLK(14)  
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(5) For csn falling edge (CS activated):  
•
Case GPMCFCLKDIVIDER = 0:  
F = 0.5 × CSExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and  
CSOnTime are even)  
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)  
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)  
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)  
(6) For ADV falling edge (ADV activated):  
•
Case GPMCFCLKDIVIDER = 0:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and  
ADVOnTime are even)  
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)  
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For ADV rising edge (ADV deactivated) in Reading mode:  
•
Case GPMCFCLKDIVIDER = 0:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Writing mode:  
•
Case GPMCFCLKDIVIDER = 0:  
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)  
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)  
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)  
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):  
•
Case GPMCFCLKDIVIDER = 0:  
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and  
OEOnTime are even)  
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)  
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)  
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
H = 0.5 × OEExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and  
OEOffTime are even)  
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)  
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)  
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(8) For WE falling edge (WE activated):  
•
Case GPMCFCLKDIVIDER = 0:  
I = 0.5 × WEExtraDelay × GPMC_FCLK(14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and  
WEOnTime are even)  
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)  
–
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–
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)  
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
I = 0.5 × WEExtraDelay × GPMC_FCLK (14)  
Case GPMCFCLKDIVIDER = 1:  
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and  
WEOffTime are even)  
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise  
•
Case GPMCFCLKDIVIDER = 2:  
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)  
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)  
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(9) J = GPMC_FCLK(14)  
(10) First transfer only for CLK DIV 1 mode.  
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.  
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.  
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
(14) P = GPMC_CLK period in ns  
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the  
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.  
(16) The jitter probability density can be approximated by a Gaussian function.  
(17) For div_by_1_mode:  
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:  
GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
For no extra_delay:  
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed  
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed  
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed  
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
GPMC_A[MSB:1]  
Valid Address  
F19  
F6  
F7  
GPMC_BE0n_CLE  
F19  
GPMC_BE1n  
F6  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F12  
D 0  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_01  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-37. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F4  
F6  
GPMCA[MSB:1]  
Valid Address  
F7  
F7  
F9  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F13  
F12  
D 0  
F22  
F12  
D 3  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
D 1  
D 2  
F21  
GPMC_02  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-38. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)  
F1  
F1  
F0  
GPMC_CLK  
GPMC_CSn[i]  
F2  
F3  
F4  
F6  
Valid Address  
GPMC_A[MSB:1]  
F17  
F17  
F17  
F17  
F17  
F17  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_WEn  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
D 0  
D 3  
GPMC_03  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
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B. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-39. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)  
F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F6  
F6  
F4  
F7  
GMPC_BE0n_CLE  
Valid  
F7  
Valid  
GPMC_BE1n  
GPMC_A[27:17]  
Address (MSB)  
F5  
F12  
F13  
F4  
F12  
GPMC_AD[15:0]  
Address (LSB)  
D0  
D1  
D2  
D3  
F8  
F8  
F9  
GPMC_ADVn_ALE  
F10  
F11  
GPMC_OEn_REn  
GPMC_WAIT[j]  
GPMC_04  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-40. GPMC and Multiplexed NOR Flash — Synchronous Burst Read  
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F1  
F1  
F0  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
F6  
F6  
GPMC_A[27:17]  
Address (MSB)  
F17  
F17  
F17  
F17  
GPMC_BE1n  
F17  
F17  
BPMC_BE0n_CLE  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
F14  
F14  
GPMC_WEn  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
Address (LSB)  
D 0  
D 3  
F22  
F21  
GPMC_WAIT[j]  
GPMC_05  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-41. GPMC and Multiplexed NOR Flash — Synchronous Burst Write  
7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode  
Table 7-52 and Table 7-53 present timing requirements and switching characteristics for GPMC and NOR Flash  
— Asynchronous Mode.  
Table 7-52. GPMC and NOR Flash Timing Requirements – Asynchronous Mode  
see Figure 7-42, Figure 7-43, Figure 7-44, and Figure 7-46  
NO. PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
FA5(1) tacc(d)  
Data access time  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H(4) ns  
TIMEPARAGRANULARITY_X1  
FA2 tacc1-pgmode(d)  
0(2)  
Page mode successive data access time  
Page mode first data access time  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
P(3) ns  
FA2 tacc2-pgmode(d)  
1(1)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H(4) ns  
TIMEPARAGRANULARITY_X1  
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active  
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional  
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
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Table 7-53. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode  
see Figure 7-42, Figure 7-43, Figure 7-44, Figure 7-45, Figure 7-46, and Figure 7-47  
MIN  
MAX  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
UNIT  
133 MHz  
tR(d)  
Rise time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.0 ns  
TIMEPARAGRANULARITY_X1  
tF(d)  
Fall time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.0 ns  
TIMEPARAGRANULARITY_X1  
FA0 tw(be[x]nV)  
Pulse duration, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid time  
Read  
Write  
N (12) ns  
N (12)  
FA1 tw(csnV)  
Pulse duration, output chip select GPMC_CSn[i](13)  
low  
Read  
Write  
Read  
A (1) ns  
A (1)  
B - 2.1 B + 2.1 ns  
FA3 td(csnV-advnIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
(2)  
(2)  
Write  
B - 2.1 B + 2.1  
(2)  
(2)  
FA4 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Single read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
C - 2.1 C + 2.1 ns  
(3)  
(3)  
FA9 td(aV-csnV)  
Delay time, output address GPMC_A[27:1] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
TIMEPARAGRANULARITY_X1  
FA10 td(be[x]nV-csnV)  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid to output  
chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
FA12 td(csnV-advnV)  
FA13 td(csnV-oenV)  
FA16 tw(aIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
K - 2.1 K + 2.1 ns  
(10)  
(10)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
L - 2.1  
L + 2.1 ns  
(11)  
(11)  
Pulse duration output address GPMC_A[26:1]  
invalid between 2 successive read and write  
accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
G (7)  
ns  
FA18 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Burst read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
I - 2.1 (8) I + 2.1 (8) ns  
FA20 tw(aV)  
Pulse duration, output address GPMC_A[27:1]  
valid - 2nd, 3rd, and 4th accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
D (4)  
ns  
TIMEPARAGRANULARITY_X1  
FA25 td(csnV-wenV)  
FA27 td(csnV-wenIV)  
FA28 td(wenV-dV)  
FA29 td(dV-csnV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
E - 2.1 E + 2.1 ns  
(5)  
(5)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
F - 2.1 (6) F + 2.1 ns  
(6)  
Delay time, output write enable GPMC_WEn valid  
to output data GPMC_AD[15:0] valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.1 ns  
Delay time, output data GPMC_AD[15:0] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
TIMEPARAGRANULARITY_X1  
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Table 7-53. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode (continued)  
see Figure 7-42, Figure 7-43, Figure 7-44, Figure 7-45, Figure 7-46, and Figure 7-47  
MIN  
MAX  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
UNIT  
133 MHz  
FA37 td(oenV-aIV)  
Delay time, output enable GPMC_OEn_REn valid  
to output address GPMC_AD[15:0] phase end  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.1 ns  
TIMEPARAGRANULARITY_X1  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
with n being the page burst access number  
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)  
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))  
× GPMC_FCLK(14)  
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)  
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
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GPMC_FCLK  
GPMC_CLK  
FA5  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
Valid  
FA0  
GPMC_BE0n_CLE  
Valid  
GPMC_BE1n  
FA10  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data IN 0  
Data IN 0  
GPMC_WAIT[j]  
GPMC_06  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 7-42. GPMC and NOR Flash — Asynchronous Read — Single Word  
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GPMC_FCLK  
GPMC_CLK  
GPMC_CSn[i]  
FA5  
FA5  
FA1  
FA1  
FA16  
FA9  
FA9  
Address 0  
FA0  
Address 1  
FA0  
GPMC_A[MSB:1]  
FA10  
FA10  
Valid  
FA0  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
Valid  
FA10  
FA10  
FA3  
FA3  
FA12  
FA12  
GPMC_ADCn_ALE  
FA4  
FA4  
FA13  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data Upper  
GPMC_WAIT[j]  
GPMC_07  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 7-43. GPMC and NOR Flash — Asynchronous Read — 32–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA20  
Add3  
FA20  
Add1  
FA21  
FA20  
Add2  
FA1  
GPMC_CSn[i]  
FA9  
Add0  
Add4  
GPMC_A[MSB:1]  
FA0  
FA10  
GPMC_BE0n_CLE  
FA0  
FA10  
GPMC_BE1n  
FA12  
GPMC_ADVn_ALE  
FA18  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
D3  
D0  
D1  
D2  
D3  
GPMC_WAIT[j]  
GPMC_08  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by  
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.  
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC  
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock  
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first  
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.  
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 7-44. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid Address  
FA0  
FA10  
FA10  
FA0  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
FA29  
Data OUT  
GPMC_09  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-45. GPMC and NOR Flash — Asynchronous Write — Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
FA5  
GPMC_CSn[i]  
FA9  
Address (MSB)  
FA0  
GPMC_A[27:17]  
FA10  
GPMC_BE0n_CLE  
Valid  
FA0  
FA10  
GPMC_BE1n  
Valid  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_10  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
Figure 7-46. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word  
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GPMC_FCLK  
GPMC_CLK  
GPMC_CSn[i]  
FA1  
FA9  
GPMC_A[27:17]  
Address (MSB)  
FA0  
FA10  
FA10  
GPMC_BE0n_CLE  
GPMC_BE1n  
FA0  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
FA28  
GPMC_AD[15:0]  
Valid Address (LSB)  
Data OUT  
GPMC_WAIT[j]  
GPMC_11  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-47. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word  
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7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode  
Table 7-54 and Table 7-55 present timing requirements and switching characteristics for GPMC and NAND Flash  
— Asynchronous Mode.  
Table 7-54. GPMC and NAND Flash Timing Requirements – Asynchronous Mode  
see Figure 7-50  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(4)  
UNIT  
133 MHz  
GNF12(1) tacc(d)  
Access time, input data GPMC_AD[15:0](3)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
J(2) ns  
TIMEPARAGRANULARITY_X1  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
–
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
Table 7-55. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode  
see Figure 7-48, Figure 7-49, Figure 7-50 and Figure 7-51  
NO.  
PARAMETER  
MODE(4)  
MIN  
MAX UNIT  
tR(d)  
Rise time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.0 ns  
TIMEPARAGRANULARITY_X1  
tF(d)  
Fall time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.0 ns  
TBD ns  
B + 2 ns  
C + 2 ns  
D + 2 ns  
E + 2 ns  
F + 2 ns  
GNF0 tw(wenV)  
Pulse duration, output write enable GPMC_WEn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
A
B - 2  
C - 2  
D - 2  
E - 2  
F - 2  
GNF1 td(csnV-wenV)  
GNF2 tw(cleH-wenV)  
GNF3 tw(wenV-dV)  
GNF4 tw(wenIV-dIV)  
GNF5 tw(wenIV-cleIV)  
Delay time, output chip select GPMC_CSn[i](2)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE high to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output data GPMC_AD[15:0] valid to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output data GPMC_AD[15:0] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output lower-byte enable and command  
latch enable GPMC_BE0n_CLE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
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Table 7-55. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode (continued)  
see Figure 7-48, Figure 7-49, Figure 7-50 and Figure 7-51  
NO.  
PARAMETER  
MODE(4)  
MIN  
MAX UNIT  
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn  
invalid to output chip select GPMC_CSn[i](2)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
G - 2  
G + 2 ns  
GNF7 tw(aleH-wenV)  
GNF8 tw(wenIV-aleIV)  
GNF9 tc(wen)  
Delay time, output address valid and address latch  
enable GPMC_ADVn_ALE high to output write  
enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
C - 2  
F - 2  
C + 2 ns  
F + 2 ns  
Delay time, output write enable GPMC_WEn  
invalid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Cycle time, write  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H
ns  
TIMEPARAGRANULARITY_X1  
GNF10 td(csnV-oenV)  
Delay time, output chip select GPMC_CSn[i](2)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
I - 2  
I + 2 ns  
TIMEPARAGRANULARITY_X1  
GNF13 tw(oenV)  
Pulse duration, output enable GPMC_OEn_REn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
K
ns  
ns  
GNF14 tc(oen)  
Cycle time, read  
div_by_1_mode;  
GPMC_FCLK_MUX;  
L
TIMEPARAGRANULARITY_X1  
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn  
invalid to output chip select GPMC_CSn[i](2)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
M - 2  
M + 2 ns  
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
–
•
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
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GPMC_FCLK  
GPMC_CSn[i]  
GNF1  
GNF2  
GNF6  
GNF5  
GPMC_BE0n_CLE  
GPMC_ADCn_ALE  
GPMC_OEn_REn  
GPMC_WEn  
GNF0  
GNF3  
GNF4  
GPMC_AD[15:0]  
Command  
GPMC_12  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
Figure 7-48. GPMC and NAND Flash — Command Latch Cycle  
GPMC_FCLK  
GPMC_CSn[i]  
GNF1  
GNF6  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF7  
GNF8  
GPMC_OEn_REn  
GPMC_WEn  
GNF9  
GNF0  
GNF3  
GNF4  
Address  
GPMC_AD[15:0]  
GPMC_13  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
Figure 7-49. GPMC and NAND Flash — Address Latch Cycle  
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GPMC_FCLK  
GNF12  
GNF10  
GNF15  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF14  
GNF13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
DATA  
GPMC_14  
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional  
clock edge. GNF12 value must be stored inside AccessTime register bits field.  
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
Figure 7-50. GPMC and NAND Flash — Data Read Cycle  
GPMC_FCLK  
GNF1  
GNF6  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
GNF9  
GNF0  
GPMC_WEn  
GNF3  
GNF4  
GPMC_AD[15:0]  
DATA  
GPMC_15  
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
Figure 7-51. GPMC and NAND Flash — Data Write Cycle  
7.10.5.9 I2C  
For more details about features and additional description information on the device Inter-Integrated Circuit, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Section 7.10.5.9.1, Table 7-56 and Figure 7-52 assume testing over the recommended operating conditions and  
electrical characteristic conditions.  
7.10.5.9.1 Timing Requirements for I2C Input Timings  
NO.(1) (6) PARAMETER  
I1 tc(SCL)  
DESCRIPTION  
MODE  
Standard  
Fast  
MIN  
10000  
2500  
MAX  
UNIT  
ns  
Cycle time, SCL  
ns  
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NO.(1) (6) PARAMETER  
DESCRIPTION  
MODE  
Standard  
Fast  
MIN  
4700  
600  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
I2  
I3  
I4  
I5  
I6  
I7  
I8  
I9  
tsu(SCLH-SDAL)  
th(SDAL-SCLL)  
tw(SCLL)  
Setup time, SCL high before SDA low (for a repeated START  
condition)  
Hold time, SCL low after SDA low (for a START and a repeated Standard  
START condition)  
4000  
900  
Fast  
Pulse duration, SCL low  
Standard  
Fast  
4700  
1300  
4000  
600  
tw(SCLH)  
Pulse duration, SCL high  
Standard  
Fast  
tsu(SDAV-SCLH)  
th(SCLL-SDAV)  
tw(SDAH)  
Setup time, SDA valid before SCL high  
Hold time, SDA valid after SCL low  
Standard  
Fast  
250  
100 (2)  
0(3)  
Standard  
Fast  
3450(4)  
900 (4)  
0(3)  
Pulse duration, SDA high between STOP and START  
conditions  
Standard  
Fast  
4700  
1300  
tr(SDA)  
Rise time, SDA  
Rise time, SCL  
Fall time, SDA  
Fall time, SCL  
Standard  
Fast  
1000  
20*(Vdd/ 300 (3)(7)  
5.5V)(5)(7)  
I10  
I11  
I12  
tr(SCL)  
tf(SDA)  
tf(SCL)  
Standard  
Fast  
1000  
20*(Vdd/ 300 (3)(7)  
ns  
ns  
5.5V)(5)(7)  
Standard  
Fast  
300  
ns  
ns  
20*(Vdd/ 300 (3)(7)  
5.5V)(5)(7)  
Standard  
Fast  
300  
ns  
ns  
20*(Vdd/  
5.5V)  
300  
I13  
I14  
I15  
I16  
tsu(SCLH-SDAH)  
Setup time, SCL high before SDA high (for STOP condition)  
Pulse duration, spike (must be supressed)  
Skew  
Standard  
Fast  
4000  
600  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
tw(SP)  
Standard  
Fast  
0
50  
3
tskew  
Standard  
Fast  
3
Cb  
Capacitive load for each bus line  
Standard  
Fast  
400  
400  
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered  
down.  
(2) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be  
met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the  
low period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to  
the Standard-mode I2C-Bus Specification) before the SCL line is released.  
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the  
undefined region of the falling edge of SCL.  
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.  
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed  
(6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details.  
(7) These timings apply only to I2C0 and MCU_I2C0. I2C[3:1] and MCU_I2C1 use standard LVCMOS buffers to emulate open-drain  
buffers and their rise/fall times should be referenced in the device IBIS model.  
Table 7-56. Timing Requirements for I2C HS–Mode  
NO.  
PARAMETER  
DESCRIPTION  
CAPACITANCE  
MIN  
294  
588  
MAX UNIT  
I1  
tc(SCL)  
Cycle time, SCL  
100 pF Max  
ns  
ns  
400 pF Max  
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Table 7-56. Timing Requirements for I2C HS–Mode (continued)  
NO.  
PARAMETER  
DESCRIPTION  
CAPACITANCE  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
100 pF Max  
400 pF Max  
MIN  
160  
160  
160  
160  
160  
320  
60  
MAX UNIT  
I2  
tsu(SCLH-SDAL)  
th(SDAL-SCLL)  
tw(SCLL)  
Setup time, SCL high before SDA low (for a  
repeated START condition)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
I3  
I4  
Hold time, SCL low after SDA low (for a START  
and a repeated START condition)  
Pulse duration, SCL low  
I5  
tw(SCLH)  
Pulse duration, SCL high  
120  
10  
I6  
tsu(SDAV-SCLH)  
th(SCLL-SDAV)  
tw(SDAH)  
Setup time, SDA valid before SCL high  
Hold time, SDA valid after SCL low  
10  
I7  
0
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
0
150  
I13  
I14  
Setup time, SCL high before SDA high (for  
STOP condition)  
160  
160 (2)  
0
tr(SDA)  
Pulse duration, spike (must be suppressed)  
10 (2)  
I15  
I16  
tskew  
Skew  
Cb(1)  
Capacitive Load for SDA and SCL Lines  
100 pF Max  
400 pF Max  
100  
400  
(1) For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.  
(2) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH  
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.  
I11  
I9  
I2C[i]_SDA  
I2C[i]_SCL  
I8  
I6  
I14  
I4  
I13  
I5  
I10  
I12  
I1  
I3  
I7  
I2  
I3  
Stop  
Start  
Repeated  
Start  
Stop  
A. i = 0 to 1 for MCU domain  
i = 0 to 3 for MAIN domain  
Figure 7-52. I2C Receive Timing  
7.10.5.10 MCAN  
Table 7-57 and Table 7-58 presents timing conditions and switching characteristics for MCAN.  
For more details about features and additional description information on the device Controller Area Network  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
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Note  
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,  
where n represents the specific MCAN module.  
Table 7-57. MCAN Timing Conditions  
PARAMETER  
MIN  
2
MAX  
15  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
5
20  
Table 7-58. MCAN Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
Delay time, transmit shift register to MCANn_TX  
Delay time, MCANn_RX to receive shift register  
MIN  
MAX  
10  
UNIT  
ns  
MCAN1 td(MCAN_TX)  
MCAN2 td(MCAN_RX)  
10  
ns  
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.  
7.10.5.11 MCSPI  
For more details about features and additional description information on the device Serial Port Interface, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-59 presents timing conditions for MCSPI.  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
Table 7-59. MCSPI Timing Conditions  
PARAMETER  
MIN  
2
MAX  
8.5  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
6
12  
7.10.5.11.1 MCSPI — Master Mode  
Table 7-60, Figure 7-53, Table 7-61, and Figure 7-54 present timing requirements and switching characteristics  
for SPI – Master Mode.  
Table 7-60. MCSPI Timing Requirements – Master Mode  
see Figure 7-53  
NO.  
SM4  
SM5  
PARAMETER  
tsu(MISO-SPICLK)  
th(SPICLK-MISO)  
DESCRIPTION  
MIN  
2.8  
3
MAX  
UNIT  
ns  
Setup time, SPIn_D[x] valid before SPIn_CLK active edge  
Hold time, SPIn_D[x] valid after SPIn_CLK active edge  
ns  
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PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SM5  
SM5  
SM4  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM2  
SM1  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SM5  
SM4  
SM5  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_02  
Figure 7-53. SPI Master Mode Receive Timing  
Table 7-61. MCSPI Switching Characteristics - Master Mode  
see Figure 7-54  
NO.  
PARAMETER  
MIN  
MAX UNIT  
SM1  
SM2  
SM3  
SM6  
SM7  
SM8  
tc(SPICLK)  
Cycle time, SPIn_CLK  
20  
ns  
ns  
ns  
tw(SPICLKL)  
tw(SPICLKH)  
td(SPICLK-SIMO)  
td(CS-SIMO)  
Pulse duration, SPIn_CLK low  
0.5P - 1(1)  
0.5P - 1(1)  
-3  
Pulse duration, SPIn_CLK high  
Delay time, SPIn_CLK active edge to SPIn_D[x]  
Delay time, SPIn_CSi active edge to SPIn_D[x]  
Delay time, SPIn_CSi active to SPIn_CLK first edge  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
5
td(CS-SPICLK)  
PHA = 0  
PHA = 1  
PHA = 0  
PHA = 1  
B - 4 (3)  
A - 4 (2)  
A - 4(2)  
B - 4(3)  
SM9  
td(SPICLK-CS)  
Delay time, SPIn_CLK last edge to SPIn_CSi inactive  
(1) P = SPI_CLK period in ns.  
(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =  
(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.  
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(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.  
PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SPI_D[x] (OUT)  
SM7  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM1  
SM2  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SPI_D[x] (OUT)  
SM6  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
SM6  
Bit 1  
Bit0  
SPRSP08_TIMING_McSPI_01  
Figure 7-54. SPI Master Mode Transmit Timing  
7.10.5.11.2 MCSPI — Slave Mode  
Table 7-62, Figure 7-55, Table 7-63, and Figure 7-56 present timing requirements and switching characteristics  
for SPI – Slave Mode.  
Table 7-62. MCSPI Timing Requirements – Slave Mode  
see Figure 7-55  
NO.  
SS1  
SS2  
SS3  
SS4  
SS5  
SS8  
SS9  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
tc(SPICLK)  
Cycle time, SPIn_CLK  
20  
0.45P(1)  
0.45P(1)  
tw(SPICLKL)  
Pulse duration, SPIn_CLK low  
ns  
tw(SPICLKH)  
Pulse duration, SPIn_CLK high  
ns  
tsu(SIMO-SPICLK)  
th(SPICLK-SIMO)  
tsu(CS-SPICLK)  
th(SPICLK-CS)  
Setup time, SPIn_D[x] valid before SPIn_CLK active edge  
Hold time, SPIn_D[x] valid after SPIn_CLK active edge  
Setup time, SPIn_CSi valid before SPIn_CLK first edge  
Hold time, SPIn_CSi valid after SPIn_CLK last edge  
5
5
5
5
ns  
ns  
ns  
ns  
(1) P = SPIn_CLK period in ns.  
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PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
POL=1  
SPI_SCLK (IN)  
SPI_SCLK (IN)  
SS1  
SS2  
SS5  
SS4  
SS5  
Bit n-2  
SS4  
Bit n-1  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
SPI_CS[i] (IN)  
PHA=1  
EPOL=1  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
POL=1  
SPI_SCLK (IN)  
SPI_SCLK (IN)  
SS1  
SS3  
SS4  
SS5  
SS4  
SS5  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_04  
Figure 7-55. SPI Slave Mode Receive Timing  
Table 7-63. MCSPI Switching Characteristics – Slave Mode  
see Figure 7-56  
NO.  
SS6  
SS7  
PARAMETER  
td(SPICLK-SOMI)  
tsk(CS-SOMI)  
DESCRIPTION  
Delay time, SPIn_CLK active edge to SPIn_D[x]  
Delay time, SPIn_CSi active edge to SPIn_D[x]  
MIN  
2
MAX  
UNIT  
ns  
17.12  
20.95  
ns  
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PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS2  
POL=1  
SPI_SCLK (IN)  
SS7  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (OUT)  
PHA=1  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS3  
POL=1  
SPI_SCLK (IN)  
SS6  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
SS6  
Bit 1  
Bit 0  
SPI_D[x] (OUT)  
SPRSP08_TIMING_McSPI_03  
Figure 7-56. SPI Slave Mode Transmit Timing  
7.10.5.12 MMCSD  
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),  
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at  
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking  
for syntactical correctness.  
For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal  
Descriptions and Detailed Description sections.  
Note  
Some operating modes require software configuration of the MMC DLL delay settings, as shown in  
Table 7-64 and Table 7-73.  
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in  
the device TRM.  
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7.10.5.12.1 MMC0 - eMMC Interface  
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the  
following eMMC applications:  
•
•
•
•
Legacy speed  
High speed SDR  
High speed DDR  
HS200  
Table 7-64 presents the required DLL software configuration settings for MMC0 timing modes.  
Table 7-64. MMC0 DLL Delay Mapping for All Timing Modes  
REGISTER NAME  
BIT FIELD  
MMCSD0_SS_PHY_CTRL_4_REG  
MMCSD0_SS_PHY_CTRL_5_REG  
[31:24]  
[20]  
[15:12]  
[8]  
[4:0]  
[17:16]  
[10:8]  
[2:0]  
SELDLYTXCLK  
SELDLYRXCLK  
BIT FIELD NAME  
STRBSEL  
OTAPDLYENA  
OTAPDLYSEL  
ITAPDLYENA  
ITAPDLYSEL  
FRQSEL  
CLKBUFSEL  
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL  
DELAY CHAIN  
SELECT  
DELAY  
BUFFER  
DURATION  
STROBE  
DELAY  
DLL REF  
FREQUENCY  
MODE DESCRIPTION  
8-bit PHY  
Legacy  
operating 1.8 V,  
SDR  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x1  
0x1  
NA  
NA  
0x1  
0x1  
0x1  
0x1  
0x10  
0xA  
0x1  
0x1  
0x0  
0x0  
0x0  
0x0  
0x4  
0x0  
0x7  
0x7  
0x7  
0x7  
25 MHz  
High  
8-bit PHY  
Speed operating 1.8 V,  
SDR  
High  
50 MHz  
8-bit PHY  
Speed operating 1.8 V,  
0x6  
0x7  
0x3  
DDR  
50 MHz  
8-bit PHY  
HS200 operating 1.8 V,  
200 MHz  
Tuning  
Table 7-65 presents timing conditions for MMC0.  
Table 7-65. MMC0 Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
Legacy SDR  
0.14  
0.3  
1.44 V/ns  
0.9 V/ns  
0.9 V/ns  
0.9 V/ns  
High Speed SDR  
SRI  
Input slew rate  
High Speed DDR (CMD)  
High Speed DDR (DAT[7:0])  
0.3  
0.45  
OUTPUT CONDITIONS  
Legacy SDR  
1
1
1
1
12  
12  
12  
6
pF  
pF  
pF  
pF  
High Speed SDR  
CL  
Output load capacitance  
High Speed DDR  
HS200  
PCB CONNECTIVITY REQUIREMENTS  
All modes  
td(Trace Delay)  
Propagation delay of each trace  
126  
756  
100  
8
ps  
ps  
ps  
Legacy SDR, High Speed SDR  
High Speed DDR, HS200  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
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7.10.5.12.1.1 Legacy SDR Mode  
Table 7-66, Figure 7-57, Table 7-67, and Figure 7-58 present timing requirements and switching characteristics  
for MMC0 – Legacy SDR Mode.  
Table 7-66. MMC0 Timing Requirements – Legacy SDR Mode  
see Figure 7-57  
NO.  
MIN  
9.69  
MAX  
UNIT  
ns  
LSDR1 tsu(cmdV-clkH)  
LSDR2 th(clkH-cmdV)  
LSDR3 tsu(dV-clkH)  
LSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
27.97  
9.69  
ns  
ns  
27.97  
ns  
Figure 7-57. MMC0 – Legacy SDR – Receive Mode  
Table 7-67. MMC0 Switching Characteristics – Legacy SDR Mode  
see Figure 7-58  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
25  
LSDR5  
LSDR6  
LSDR7  
LSDR8  
LSDR9  
tc(clk)  
Cycle time, MMC0_CLK  
40  
18.7  
tw(clkH)  
Pulse duration, MMC0_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC0_CLK low  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
-16.1  
-16.1  
16.1  
16.1  
ns  
ns  
Figure 7-58. MMC0 – Legacy SDR – Transmit Mode  
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7.10.5.12.1.2 High Speed SDR Mode  
Table 7-68, Figure 7-59, Table 7-69, and Figure 7-60 present timing requirements and switching characteristics  
for MMC0 – High Speed SDR Mode.  
Table 7-68. MMC0 Timing Requirements – High Speed SDR Mode  
see Figure 7-59  
NO.  
MIN  
2.99  
2.67  
2.99  
2.67  
MAX  
UNIT  
ns  
HSSDR1 tsu(cmdV-clkH)  
HSSDR2 th(clkH-cmdV)  
HSSDR3 tsu(dV-clkH)  
HSSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
ns  
ns  
ns  
Figure 7-59. MMC0 – High Speed SDR Mode – Receive Mode  
Table 7-69. MMC0 Switching Characteristics – High Speed SDR Mode  
see Figure 7-60  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
50  
HSSDR5 tc(clk)  
Cycle time, MMC0_CLK  
20  
9.2  
HSSDR6 tw(clkH)  
HSSDR7 tw(clkL)  
HSSDR8 td(clkL-cmdV)  
HSSDR9 td(clkL-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
9.2  
ns  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
-6.35  
-6.35  
6.35  
6.35  
ns  
ns  
Figure 7-60. MMC0 – High Speed SDR Mode – Transmit Mode  
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7.10.5.12.1.3 High Speed DDR Mode  
Table 7-70, Figure 7-61, Table 7-71, and Figure 7-62 present timing requirements and switching characteristics  
for MMC0 – High Speed DDR Mode.  
Table 7-70. MMC0 Timing Requirements – High Speed DDR Mode  
see Figure 7-61  
NO.  
MIN  
3.88  
2.67  
0.83  
1.76  
MAX  
UNIT  
ns  
HSDDR1 tsu(cmdV-clk)  
HSDDR2 th(clk-cmdV)  
HSDDR3 tsu(dV-clk)  
HSDDR4 th(clk-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition  
ns  
ns  
ns  
Figure 7-61. MMC0 – High Speed DDR Mode – Receive Mode  
Table 7-71. MMC0 Switching Characteristics – High Speed DDR Mode  
see Figure 7-62  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
HSDDR5 tc(clk)  
Operating frequency, MMC0_CLK  
50  
Cycle time, MMC0_CLK  
20  
9.2  
HSDDR6 tw(clkH)  
HSDDR7 tw(clkL)  
HSDDR8 td(clk-cmdV)  
HSDDR9 td(clk-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
9.2  
ns  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition  
3.31  
2.81  
16.19  
6.94  
ns  
ns  
Figure 7-62. MMC0 – High Speed DDR Mode – Transmit Mode  
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7.10.5.12.1.4 HS200 Mode  
Table 7-72 and Figure 7-63 present switching characteristics for MMC0 – HS200 Mode.  
Table 7-72. MMC0 Switching Characteristics – HS200 Mode  
see Figure 7-63  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
200  
HS2005  
HS2006  
HS2007  
HS2008  
HS2009  
tc(clk)  
Cycle time, MMC0_CLK  
5
2.08  
2.08  
0.99  
0.99  
tw(clkH)  
Pulse duration, MMC0_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC0_CLK low  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition  
3.28  
3.28  
ns  
ns  
Figure 7-63. MMC0 – HS200 Mode – Transmit Mode  
7.10.5.12.2 MMC1 - SD/SDIO Interface  
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer  
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:  
•
•
•
•
•
•
•
Default speed  
High speed  
UHS–I SDR12  
UHS–I SDR25  
UHS–I SDR50  
UHS–I SDR104  
UHS–I DDR50  
Table 7-73 presents the required DLL software configuration settings for MMC1 timing modes.  
Table 7-73. MMC1 DLL Delay Mapping for All Timing Modes  
REGISTER NAME  
BIT FIELD  
MMCSD1_SS_PHY_CTRL_4_REG  
[15:12] [8]  
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL  
MMCSD1_SS_PHY_CTRL_5_REG  
[20]  
[4:0]  
[2:0]  
BIT FIELD NAME  
CLKBUFSEL  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DELAY  
BUFFER  
DURATION  
DELAY  
ENABLE  
DELAY  
VALUE  
MODE  
DESCRIPTION  
Default  
Speed  
4-bit PHY operating  
3.3 V, 25 MHz  
0x0  
0x0  
0x1  
0x1  
0x1  
0x0  
0x0  
0xF  
0xF  
0xC  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x0  
0x7  
0x7  
0x7  
0x7  
0x7  
High  
Speed  
4-bit PHY operating  
3.3 V, 50 MHz  
UHS-I  
SDR12  
4-bit PHY operating  
1.8 V, 25 MHz  
0x0  
UHS-I  
SDR25  
4-bit PHY operating  
1.8 V, 50 MHz  
0x0  
UHS-I  
SDR50  
4-bit PHY operating  
1.8 V, 100 MHz  
Tuning  
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Table 7-73. MMC1 DLL Delay Mapping for All Timing Modes (continued)  
REGISTER NAME  
MMCSD1_SS_PHY_CTRL_4_REG  
[15:12] [8]  
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL  
MMCSD1_SS_PHY_CTRL_5_REG  
BIT FIELD  
[20]  
[4:0]  
[2:0]  
BIT FIELD NAME  
CLKBUFSEL  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DELAY  
BUFFER  
DURATION  
DELAY  
ENABLE  
DELAY  
VALUE  
MODE  
DESCRIPTION  
UHS-I  
DR50  
4-bit PHY operating  
1.8 V, 50 MHz  
0x1  
0x1  
0x9  
0x6  
0x1  
0x1  
Tuning  
Tuning  
0x7  
0x7  
UHS-I  
SDR104  
4-bit PHY operating  
1.8, V 200 MHz  
Table 7-74 presents timing conditions for MMC1.  
Table 7-74. MMC1 Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
Input Conditions  
Default Speed, High Speed  
UHS–I SDR12, UHS–I SDR25  
UHS–I DDR50  
0.69  
0.34  
1
2.06 V/ns  
1.34 V/ns  
SRI  
Input slew rate  
2
V/ns  
Output Conditions  
UHS–I DDR50  
All other modes  
3
1
10  
10  
pF  
pF  
CL  
Output load capacitance  
PCB Connectivity Requirements  
UHS–I DDR50  
240  
126  
1134  
1386  
20  
ps  
ps  
ps  
ps  
td(Trace Delay)  
Propagation delay of each trace  
All other modes  
UHS–I DDR50, UHS–I SDR104  
All other modes  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
100  
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7.10.5.12.2.1 Default Speed Mode  
Table 7-75, Figure 7-64, Table 7-76, and Figure 7-65 present timing requirements and switching characteristics  
for MMC1 – Default Speed Mode.  
Table 7-75. Timing Requirements for MMC1 – Default Speed Mode  
see Figure 7-64  
NO.  
DS1  
DS2  
DS3  
DS4  
MIN  
2.55  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC1_CMD valid before MMCi_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
19.67  
2.55  
ns  
ns  
19.67  
ns  
MMC[x]_CLK  
DS2  
DS4  
DS1  
DS3  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
Figure 7-64. MMC1 – Default Speed – Receive Mode  
Table 7-76. Switching Characteristics for MMC1 – Default Speed Mode  
see Figure 7-65  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
25  
DS5  
DS6  
DS7  
DS8  
DS9  
tc(clk)  
Cycle time, MMC1_CLK  
40  
18.7  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
- 14.1  
- 14.1  
14.1  
14.1  
ns  
ns  
DS5  
DS6  
DS7  
MMC[x]_CLK  
MMC[x]_CMD  
DS8  
DS9  
MMC[x]_DAT[3:0]  
Figure 7-65. MMC1 – Default Speed – Transmit Mode  
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7.10.5.12.2.2 High Speed Mode  
Table 7-77, Figure 7-66, Table 7-78, and Figure 7-67 present timing requirements and switching characteristics  
for MMC1 – High Speed Mode.  
Table 7-77. Timing Requirements for MMC1 – High Speed Mode  
see Figure 7-66  
NO.  
HS1  
HS2  
HS3  
HS4  
MIN  
2.55  
2.67  
2.55  
2.67  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
ns  
ns  
MMC[x]_CLK  
HS1  
HS3  
HS2  
HS4  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
Figure 7-66. MMC1 – High Speed – Receive Mode  
Table 7-78. Switching Characteristics for MMC1 – High Speed Mode  
see Figure 7-67  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
50  
HS5  
HS6  
HS7  
HS8  
HS9  
tc(clk)  
Cycle time. MMC1_CLK  
20  
9.2  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
9.2  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
-7.35  
-7.35  
3.35  
3.35  
ns  
ns  
HS5  
HS6  
HS7  
MMC[x]_CLK  
HS8  
HS9  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
Figure 7-67. MMC1 – High Speed – Transmit Mode  
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7.10.5.12.2.3 UHS–I SDR12 Mode  
Table 7-79, Figure 7-68, Table 7-80, and Figure 7-69 present timing requirements and switching characteristics  
for MMC1 – UHS-I SDR12 Mode.  
Table 7-79. Timing Requirements for MMC1 – UHS-I SDR12 Mode  
see Figure 7-68  
NO.  
MIN  
21.65  
1.67  
MAX  
UNIT  
ns  
SDR121 tsu(cmdV-clkH)  
SDR122 th(clkH-cmdV)  
SDR123 tsu(dV-clkH)  
SDR124 th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
21.65  
1.67  
ns  
ns  
MMC[x]_CLK  
SDR122  
SDR124  
SDR121  
SDR123  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
Figure 7-68. MMC1 – UHS-I SDR12 – Receive Mode  
Table 7-80. Switching Characteristics for MMC1 – UHS-I SDR12 Mode  
see Figure 7-69  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
25  
SDR125 tc(clk)  
Cycle time, MMC1_CLK  
40  
18.7  
SDR126 tw(clkH)  
SDR127 tw(clkL)  
SDR128 td(clkL-cmdV)  
SDR129 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
18.7  
ns  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
-13.6  
-13.6  
13.6  
13.6  
ns  
ns  
SDR125  
SDR126  
SDR127  
MMC[x]_CLK  
SDR128  
SDR128  
MMC[x]_CMD  
SDR129  
SDR129  
MMC[x]_DAT[3:0]  
Figure 7-69. MMC1 – UHS-I SDR12 – Transmit Mode  
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7.10.5.12.2.4 UHS–I SDR25 Mode  
Table 7-81, Figure 7-70, Table 7-82, and Figure 7-71 present timing requirements and switching characteristics  
for MMC1 – UHS-I SDR25 Mode.  
Table 7-81. Timing Requirements for MMC1 – UHS-I SDR25 Mode  
see Figure 7-70  
NO.  
MIN  
2.15  
1.67  
2.15  
1.67  
MAX  
UNIT  
ns  
SDR251 tsu(cmdV-clkH)  
SDR252 th(clkH-cmdV)  
SDR253 tsu(dV-clkH)  
SDR254 th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
ns  
ns  
MMC[x]_CLK  
SDR252  
SDR254  
SDR251  
SDR253  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
Figure 7-70. MMC1 – UHS-I SDR25 – Receive Mode  
Table 7-82. Switching Characteristics for MMC1 – UHS-I SDR25 Mode  
see Figure 7-71  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
50  
SDR255 tc(clk)  
Cycle time, MMC1_CLK  
20  
9.2  
SDR256 tw(clkH)  
SDR257 tw(clkL)  
SDR258 td(clkL-cmdV)  
SDR259 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
9.2  
ns  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
-7.1  
-7.1  
3.1  
3.1  
ns  
ns  
SDR255  
SDR256  
SDR257  
MMC[x]_CLK  
SDR258  
SDR258  
MMC[x]_CMD  
SDR259  
SDR259  
MMC[x]_DAT[3:0]  
Figure 7-71. MMC1 – UHS-I SDR25 – Transmit Mode  
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7.10.5.12.2.5 UHS–I SDR50 Mode  
Table 7-83, and Figure 7-72 presents switching characteristics for MMC1 – UHS-I SDR50 Mode.  
Table 7-83. Switching Characteristics for MMC1 – UHS-I SDR50 Mode  
see Figure 7-72  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
100  
SDR505 tc(clk)  
Cycle time, MMC1_CLK  
10  
4.45  
4.45  
1.2  
SDR506 tw(clkH)  
SDR507 tw(clkL)  
SDR508 td(clkL-cmdV)  
SDR509 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
6.35  
6.35  
ns  
1.2  
ns  
SDR505  
SDR506  
SDR507  
MMC[x]_CLK  
SDR508  
SDR508  
MMC[x]_CMD  
SDR509  
SDR509  
MMC[x]_DAT[3:0]  
Figure 7-72. MMC1 – UHS-I SDR50 – Transmit Mode  
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7.10.5.12.2.6 UHS–I DDR50 Mode  
Table 7-84, Figure 7-73, Table 7-85, and Figure 7-74 present timing requirements and switching characteristics  
for MMC1 – UHS-I DDR50 Mode.  
Table 7-84. Timing Requirements for MMC1 – UHS-I DDR50 Mode  
see Figure 7-73  
NO.  
MIN  
2.99  
1.91  
-0.06  
1.91  
MAX  
UNIT  
ns  
DDR501  
DDR502  
DDR503  
DDR504  
tsu(cmdV-clk)  
th(clk-cmdV)  
tsu(dV-clk)  
th(clk-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition  
ns  
ns  
ns  
MMC[x]_CLK  
MMC[x]_CMD  
DDR501  
DDR502  
DDR503  
DDR504  
DDR503  
DDR504  
MMC[x]_DAT[3:0]  
Figure 7-73. MMC1 – UHS-I DDR50 – Receive Mode  
Table 7-85. Switching Characteristics for MMC1 – UHS-I DDR50 Mode  
see Figure 7-74  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
tc(clk)  
Operating frequency, MMC1_CLK  
50  
DDR505  
DDR506  
DDR507  
DDR508  
DDR509  
Cycle time, MMC1_CLK  
20  
9.2  
9.2  
1.2  
1.2  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
ns  
td(clk-cmdV)  
td(clk-dV)  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition  
13.1  
6.35  
ns  
ns  
DDR505  
DDR506  
DDR507  
MMC[x]_CLK  
MMC[x]_CMD  
DDR508  
DDR509  
DDR509  
MMC[x]_DAT[3:0]  
Figure 7-74. MMC1 – UHS-I DDR50 – Transmit Mode  
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7.10.5.12.2.7 UHS–I SDR104 Mode  
Table 7-86, and Figure 7-75 present switching characteristics for MMC1 – UHS-I SDR104 Mode.  
Table 7-86. Switching Characteristics for MMC1 – UHS-I SDR104 Mode  
see Figure 7-75  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
200  
SDR1045 tc(clk)  
Cycle time, MMC1_CLK  
5
2.08  
2.08  
1.12  
1.12  
SDR1046 tw(clkH)  
SDR1047 tw(clkL)  
SDR1048 td(clkL-cmdV)  
SDR1049 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
3.16  
3.16  
ns  
ns  
SDR1045  
SDR1046  
SDR1047  
MMC[x]_CLK  
SDR1048  
SDR1048  
MMC[x]_CMD  
SDR1049  
SDR1049  
MMC[x]_DAT[3:0]  
Figure 7-75. MMC1 – UHS-I SDR104 – Transmit Mode  
7.10.5.13 CPTS  
Table 7-87, Table 7-88, Figure 7-76, Table 7-89, and Figure 7-77 present timing conditions, requirements, and  
switching characteristics for CPTS.  
Table 7-87. CPTS Timing Conditions  
PARAMETER  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
Table 7-88. CPTS Timing Requirements  
see Figure 7-76  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CPTS_HWn_TS_PUSH high  
Pulse duration, CPTS_HWn_TS_PUSH low  
Cycle time, CPTS_RFT_CLK  
MIN  
2 + 12P(1)  
2 + 12P(1)  
5
MAX  
UNIT  
ns  
T1  
tw(HWTSPUSHH)  
tw(HWTSPUSHL)  
tc(RFT_CLK)  
T2  
ns  
T3  
8
ns  
T4  
tw(RFT_CLKH)  
Pulse duration, CPTS_RFT_CLK high  
0.45 ×  
ns  
tc(RFT_CLK)  
T5  
tw(RFT_CLKL)  
Pulse duration, CPTS_RFT_CLK low  
0.45 ×  
ns  
tc(RFT_CLK)  
(1) P = functional clock period in ns.  
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T1  
T2  
CPTS_HWn_TS_PUSH  
CPTS_RFT_CLK  
T3  
T4  
T5  
Figure 7-76. CPTS Timing Requirements  
Table 7-89. CPTS Switching Characteristics  
see Figure 7-77  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CPTS_TS_COMP high  
Pulse duration, CPTS_TS_COMP low  
Pulse duration, CPTS_TS_SYNC high  
Pulse duration, CPTS_TS_SYNC low  
MIN  
MAX  
UNIT  
ns  
T6  
tw(TS_COMPH)  
-2+36P(1)  
-2+36P(1)  
-2+36P(1)  
-2+36P(1)  
-2+36P(1)  
T7  
tw(TS_COMPL)  
tw(TS_SYNCH)  
tw(TS_SYNCL)  
tw(SYNC_OUTH)  
ns  
T10  
T11  
T14  
ns  
ns  
Pulse duration, CPTS_TS_SYNC sourcing  
CPTS_SYNCn_OUT high  
ns  
T15  
tw(SYNC_OUTL)  
Pulse duration, CPTS_TS_SYNC sourcing  
CPTS_SYNCn_OUT low  
-2+36P(1)  
ns  
T16  
T17  
tw(SYNC_OUTH)  
tw(SYNC_OUTL)  
Pulse duration, GENF sourcing CPTS_SYNCn_OUT high  
Pulse duration, GENF sourcing CPTS_SYNCn_OUT low  
-2+5P(1)  
-2+5P(1)  
ns  
ns  
(1) P = functional clock period in ns.  
T6  
T7  
CPTS_TS_COMP  
T8  
T9  
CPTS_TS_SYNC  
T10  
T11  
CPTS_SYNC_OUT  
Figure 7-77. CPTS Switching Characteristics  
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter  
in the device TRM.  
7.10.5.14 OSPI  
For more details about features and additional description information on the device Octal Serial Peripheral  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-90 presents timing conditions for OSPI.  
Table 7-90. OSPI Timing Conditions  
PARAMETER  
MIN  
1
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
6
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
3
10  
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Table 7-90. OSPI Timing Conditions (continued)  
PARAMETER  
MIN  
MAX UNIT  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
450  
60  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device  
TRM.  
7.10.5.14.1 OSPI With Data Training  
7.10.5.14.1.1 OSPI Switching Characteristics – Data Training  
Table 7-91 presents switching characteristics for OSPI with Data Training.  
Table 7-91. OSPI Switching Characteristics – Data Training  
PARAMETER  
MODE  
MIN  
6.02  
7.52  
6.02  
7.52  
MAX  
UNIT  
ns  
1.8V, SDR  
3.3V, SDR  
1.8V, DDR  
3.3V, DDR  
ns  
tc(CLK)  
Cycle time, CLK  
ns  
ns  
7.10.5.14.2 OSPI Without Data Training  
Note  
The I/O Timings provided in this section are only applicable when data training is not implemented.  
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL  
Delays are configured as described in Table 7-92.  
Table 7-92. OSPI DLL Delay Mapping for Timing Modes  
MODE  
OSPI_PHY_CONFIGURATION_REG BIT FIELD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
DELAY VALUE  
0x45  
1.8V, OSPI0 DDR TX  
3.3V, OSPI0 DDR TX  
1.8V, OSPI0 DQS  
3.3V, OSPI0 DQS  
All other modes  
0x46  
0x14  
0x3A  
PHY_CONFIG_TX_DLL_DELAY_FLD,  
PHY_CONFIG_RX_DLL_DELAY_FLD  
0x0  
7.10.5.14.2.1 OSPI SDR Timing  
Table 7-93, Figure 7-78, Figure 7-79, Table 7-94, and Figure 7-80 present timing requirements and switching  
characteristics for OSPI SDR Mode.  
Table 7-93. OSPI Timing Requirements – SDR Mode  
see Figure 7-78 and Figure 7-79  
NO.  
MODE  
MIN  
MAX UNIT  
(1)  
1.8V, No Loopback  
3.3V, No Loopback  
-2.19  
-1.71  
7.62  
8.1  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, D[i:0] valid before active CLK  
edge  
O19 tsu(D-CLK)  
1.8V, No Loopback  
O20 th(CLK-D)  
Hold time, D[i:0] valid after active CLK edge  
3.3V, No Loopback  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
-3.1  
Setup time, D[i:0] valid before active LBCLK  
input (DQS) edge  
O21 tsu(D-LBCLK)  
-3.47  
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Table 7-93. OSPI Timing Requirements – SDR Mode (continued)  
see Figure 7-78 and Figure 7-79  
NO.  
MODE  
MIN  
(1)  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
3.31  
4.33  
ns  
ns  
Hold time, D[i:0] valid after active LBCLK  
input (DQS) edge  
O22 th(LBCLK-D)  
(1) i in [i:0] = 7 for OSPI0  
OSPI_CLK  
O19  
O20  
OSPI_D[i:0]  
OSPI_TIMING_05  
Figure 7-78. OSPI Timing Requirements – SDR, No Loopback Clock and Internal Pad Loopback Clock  
OSPI_DQS  
O21  
O22  
OSPI_D[i:0]  
OSPI_TIMING_06  
Figure 7-79. OSPI Timing Requirements – SDR, External Loopback Clock  
Table 7-94. OSPI Switching Characteristics – SDR Mode  
see Figure 7-80  
NO.(1)  
PARAMETER  
Cycle time, CLK  
MODE  
1.8V  
MIN  
7
MAX  
UNIT  
ns  
O7 tc(CLK)  
3.3V  
6.03  
ns  
0.475P - 0.3  
O8 tw(CLKL)  
O9 tw(CLKH)  
Pulse duration, CLK low  
Pulse duration, CLK high  
ns  
ns  
(2)  
0.475P - 0.3  
(2)  
- 0.475P –  
- 0.475P –  
O10 td(CLK-CSn)  
Delay time, CLK rising edge to CSn active edge  
0.975(N)(R) - 0.975(N)(R) +  
ns  
ns  
1 (2) (3) (4)  
1 (2) (3) (4)  
0.475P +  
0.475P +  
Delay time, CLK rising edge to CSn inactive  
edge  
O11 td(CLK-CSn)  
0.975(N)(R) - 0.975(N)(R) +  
1 (2) (3) (4)  
1 (2) (3) (4)  
1.8V  
3.3V  
-1.16  
1.25  
ns  
ns  
O12 td(CLK-D)  
Delay time, CLK active edge to D[i:0] transition  
-1.33  
1.51  
(1) i in [i:0] = 7 for OSPI0  
(2) P = CLK cycle time = SCLK period in ns  
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(4) R = refclk cycle time in ns  
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OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
Figure 7-80. OSPI Switching Characteristics – SDR  
7.10.5.14.2.2 OSPI DDR Timing  
Table 7-95, Figure 7-81, Figure 7-82, Table 7-96, and Figure 7-83 present timing requirements and switching  
characteristics for OSPI DDR Mode.  
Table 7-95. OSPI Timing Requirements – DDR Mode  
see Figure 7-81 and Figure 7-82  
NO.  
MODE  
MIN  
5.23  
5.44  
1.34  
1.44  
MAX  
UNIT  
ns  
(1)  
1.8V, No Loopback or Internal  
Pad Loopback  
O13 tsu(D-CLK)  
Setup time, D[i:0] valid before active CLK edge  
Hold time, D[i:0] valid after active CLK edge  
3.3V, No Loopback or Internal  
Pad Loopback  
ns  
1.8V, No Loopback or Internal  
Pad Loopback  
ns  
O14 th(CLK-D)  
3.3V, No Loopback or Internal  
Pad Loopback  
ns  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
1.8V, DQS  
TBD  
TBD  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, D[i:0] valid before active LBCLK (DQS)  
edge  
O15 tsu(D-LBCLK)  
O16 th(LBCLK-D)  
O17 tsu(D-DQS)  
O18 th(DQS-D)  
TBD (2)  
TBD (2)  
-0.46  
-0.66  
3.59  
Hold time, D[i:0] valid after active LBCLK (DQS)  
edge  
Setup time, D[i:0] valid before active DQS edge  
Hold time, D[i:0] valid after active DQS edge  
3.3V, DQS  
1.8V, DQS  
3.3V, DQS  
7.92  
(1) i in [i:0] = 7 for OSPI0  
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC  
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external  
loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.  
OSPI_CLK  
O13 O14  
OSPI_D[i:0]  
OSPI_TIMING_03  
Figure 7-81. OSPI Timing Requirements – DDR, No Loopback Clock and Internal Pad Loopback Clock  
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OSPI_DQS  
OSPI_D[i:0]  
O15 O16  
OSPI_TIMING_04  
Figure 7-82. OSPI Timing Requirements – DDR, External Loopback Clock and DQS  
Table 7-96. OSPI Switching Characteristics – DDR Mode  
see Figure 7-83  
NO.(1)  
PARAMETER  
Cycle time, CLK  
MODE  
MIN  
MAX  
UNIT  
O1 tc(CLK)  
19  
ns  
0.475P - 0.3  
O2 tw(CLKL)  
O3 tw(CLKH)  
Pulse duration, CLK low  
Pulse duration, CLK high  
ns  
ns  
(2)  
0.475P - 0.3  
(2)  
-0.475P –  
0.975(N)(R) -  
7 (2) (3) (4)  
-0.475P –  
O4 td(CLK-CSn)  
Delay time, CLK rising edge to CSn active edge  
0.975(N)(R)  
ns  
ns  
(2) (3) (4)  
0.475P +  
0.475P +  
Delay time, CLK rising edge to CSn inactive  
edge  
O5 td(CLK-CSn)  
0.975(N)(R)  
0.975(N)(R)  
(2) (3) (4)  
(2) (3) (4)  
1.8V  
3.3V  
-7.71  
-7.71  
-1.56  
-1.56  
ns  
ns  
O6 td(CLK-D)  
Delay time, CLK active edge to D[i:0] transition  
(1) i in [i:0] = 7 for OSPI0  
(2) P = CLK cycle time = SCLK period in ns  
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(4) R = refclk cycle time in ns  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O6  
O6  
O1  
OSPI_D[i:0]  
OSPI_TIMING_01  
Figure 7-83. OSPI Switching Characteristics – DDR  
7.10.5.15 PCIe  
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the  
specification for timing details.  
For more details about features and additional description information on the device Peripheral Component  
Interconnect Express, see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals  
chapter in the device TRM.  
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7.10.5.16 PRU_ICSSG  
The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication  
Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU  
cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast  
real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks  
from the other processor cores in the device.  
For more details about features and additional description information on the device PRU_ICSSG, see the  
corresponding subsections within Signal Descriptions and Detailed Description sections.  
Note  
The PRU_ICSSG0 and PRU_ICSSG1 support an internal wrapper multiplexing that expands the  
device top-level multiplexing.  
7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)  
Note  
The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The  
signal naming in this section matches the naming used in the PRU Module Interface section in the  
device TRM.  
Table 7-97. PRU_ICSSG PRU Timing Conditions  
PARAMETER  
MIN  
MAX  
3
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
30  
7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing  
Table 7-98. PRU_ICSSG PRU Switching Characteristics – Direct Output Mode  
see Figure 7-84  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRDO1 tsk(GPO-GPO)  
Skew, GPO to GPO  
3
ns  
GPO[n:0]  
PRDO1  
PRU_TIMING_02  
A. n in GPO[n:0] = 19.  
Figure 7-84. PRU_ICSSG PRU Direct Output Timing  
7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing  
Table 7-99. PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode  
see Figure 7-85 and Figure 7-86  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
20  
10  
10  
4
MAX  
UNIT  
ns  
PRPC1 tc(CLOCK)  
Cycle time, CLOCKIN  
PRPC2 tw(CLOCKL)  
PRPC3 tw(CLOCKH)  
PRPC4 tsu(DATAIN-CLOCK)  
Pulse duration, CLOCKIN low  
ns  
Pulse duration, CLOCKIN high  
ns  
Setup time, DATAIN valid before CLOCKIN active edge  
ns  
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Table 7-99. PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode (continued)  
see Figure 7-85 and Figure 7-86  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRPC5 th(CLOCK-DATAIN)  
Hold time, DATAIN valid after CLOCKIN active edge  
0
ns  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
PRU_TIMING_03  
Figure 7-85. PRU_ICSSG PRU Parallel Capture Timing Requirements – Rising Edge Mode  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
PRU_TIMING_04  
Figure 7-86. PRU_ICSSG PRU Parallel Capture Timing Requirements – Falling Edge Mode  
7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing  
Table 7-100. PRU_ICSSG PRU Timing Requirements – Shift In Mode  
see Figure 7-87  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, DATAIN high  
Pulse duration, DATAIN low  
MIN  
2+2*P(1)  
2+2*P(1)  
MAX  
UNIT  
ns  
PRSI1 tw(DATAINH)  
PRSI2 tw(DATAINL)  
ns  
(1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.  
PRUn represents the respective PRU0 or PRU1 instance.  
PRSI1  
PRSI2  
DATAIN  
PRU_TIMING_05  
Figure 7-87. PRU_ICSSG PRU Shift In Timing  
Table 7-101. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode  
see Figure 7-88  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRSO1  
tc(CLOCKOUT)  
Cycle time, CLOCKOUT  
10  
ns  
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Table 7-101. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode (continued)  
see Figure 7-88  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CLOCKOUT low  
MIN  
MAX  
UNIT  
PRSO2L tw(CLOCKOUTL)  
-0.3 +  
ns  
0.475*P*Z(1)(2)  
PRSO2H tw(CLOCKOUTH)  
Pulse duration, CLOCKOUT high  
-0.3 +  
ns  
ns  
0.475*P*Y(1)(3)  
PRSO3  
td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid  
-1  
4
(1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the  
ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance.  
(2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.  
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is  
an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).  
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 + 0.5).  
c. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 + 0.5).  
d. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0). If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals  
(PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0).  
(3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.  
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1  
is an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). If PRUn_GPI_DIV0 is a NON-INTEGER and  
PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5).  
b. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).  
c. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *  
PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high  
pulse and Y2 is the second high pulse.  
PRSO1  
PRSO2H  
PRSO2L  
CLOCKOUT  
DATAOUT  
PRSO3  
PRU_TIMING_06  
Figure 7-88. PRU_ICSSG PRU Shift Out Timing  
7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface  
Table 7-102. PRU_ICSSG PRU Sigma Delta and Peripheral InterfaceTiming Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
18  
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7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing  
Table 7-103. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode  
see Figure 7-89 and Figure 7-90  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
40  
20  
20  
10  
5
MAX  
UNIT  
ns  
PRSD1  
tc(SD_CLK)  
Cycle time, SDx_CLK  
PRSD2L tw(SD_CLKL)  
PRSD2H tw(SD_CLKH)  
Pulse duration, SDx_CLK low  
ns  
Pulse duration, SDx_CLK high  
ns  
PRSD3  
PRSD4  
tsu(SD_D-SD_CLK)  
Setup time, SDx_D valid before SDx_CLK active edge  
Hold time, SDx_D valid before SDx_CLK active edge  
ns  
th(SD_CLK-SD_D)  
ns  
PRSD1  
PRSD2H  
SDx_CLK  
SDx_D  
PRSD2L  
PRSD4  
PRSD3  
PRU_TIMING_07  
Figure 7-89. PRU_ICSSG PRU SD_CLK Falling Active Edge  
PRSD2L  
SDx_CLK  
SDx_D  
PRSD4  
PRSD3  
PRU_TIMING_08  
Figure 7-90. PRU_ICSSG PRU SD_CLK Rising Active Edge  
Table 7-104. PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode  
see Figure 7-91  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, PIF_DATA_IN high  
MIN  
MAX  
UNIT  
PRPIF1 tw(PIF_DATA_INH)  
2 +  
ns  
0.475*(4*P)(1)  
PRPIF2 tw(PIF_DATA_INL)  
Pulse duration, PIF_DATA_IN low  
2 +  
ns  
0.475*(4*P)(1)  
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the  
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.  
PRPIF1  
PRPIF2  
PIF_DATA_IN  
PRUPIF_TIMING_01  
Figure 7-91. PRU_ICSSG PRU Peripheral Interface Timing Requirements  
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Table 7-105. PRU_ICSSG PRU Switching Characteristics – Peripheral Interface Mode  
see Figure 7-92  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
30  
0.475*P(1)  
0.475*P(1)  
-5  
MAX  
UNIT  
ns  
PRPIF3 tc(PIF_CLK)  
PRPIF4 tw(PIF_CLKH)  
PRPIF5 tw(PIF_CLKL)  
Cycle time, PIF_CLK  
Pulse duration, PIF_CLK high  
ns  
Pulse duration, PIF_CLK low  
ns  
PRPIF6 td(PIF_CLK-  
Delay time, PIF_CLK fall to PIF_DATA_OUT  
5
5
ns  
PIF_DATA_OUT)  
PRPIF7 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN  
-5  
ns  
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the  
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.  
PRPIF3  
PRPIF4  
PRPIF5  
PIF_CLK  
PRPIF6  
PIF_DATA_OUT  
PRPIF7  
PIF_DATA_EN  
Figure 7-92. PRU_ICSSG PRU Peripheral Interface Switching Characteristics  
7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)  
Table 7-106. PRU_ICSSG PWM Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
2
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
7.10.5.16.2.1 PRU_ICSSG PWM Timing  
Table 7-107. PRU_ICSSG PWM Switching Characteristics  
see Figure 7-93  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRPWM1 tsk(PWM_A-PWM_B)  
Skew, PWM_A to PWM_B  
5
ns  
PWM_A/B  
PRPWM1  
PRU_PWM_TIMING_01  
Figure 7-93. PRU_ICSSG PWM Timing  
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7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)  
Table 7-108. PRU_ICSSG IEP Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.10.5.16.3.1 PRU_ICSSG IEP Timing  
Table 7-109. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC  
see Figure 7-94  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDC_SYNC_OUTx low  
Pulse duration, EDC_SYNC_OUTx high  
MIN  
-2+20*P(1)  
-2+20*P(1)  
20  
MAX  
UNIT  
ns  
PRIEP1 tw(EDC_SYNC_OUTxL)  
PRIEP2 tw(EDC_SYNC_OUTxH)  
ns  
PRIEP3 tsu(EDIO_DATA_IN-  
Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active  
edge  
ns  
EDC_SYNC_OUTx)  
PRIEP4 th(EDC_SYNC_OUTx-  
Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active  
edge  
20  
ns  
EDIO_DATA_IN)  
(1) P = PRU_ICSSG IEP clock source period in ns.  
EDC_SYNC_OUTx  
PRIEP2  
PRIEP1  
PRIEP3  
PRIEP4  
EDIO_DATA_IN[7:0]  
PRU_IEP_TIMING_01  
Figure 7-94. PRU_ICSSG IEP SYNC Timing Requirements  
Table 7-110. PRU_ICSSG IEP Timing Requirements – Digital IOs  
see Figure 7-95  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDIO_OUTVALID low  
MIN  
MAX  
UNIT  
ns  
IEPIO1 tw(EDIO_OUTVALIDL)  
IEPIO2 tw(EDIO_OUTVALIDH)  
-2+14*P(1)  
-2+32*P(1)  
0
Pulse duration, EDIO_OUTVALID high  
ns  
IEPIO3 td(EDIO_OUTVALID-  
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT  
18*P(1)  
ns  
EDIO_DATA_OUT)  
IEPIO4 tsk(EDIO_DATA_OUT)  
EDIO_DATA_OUT skew  
5
ns  
(1) P = PRU_ICSSG IEP clock source period in ns.  
EDIO_DATA_OUT  
IEPIO4  
PRU_EDIO_DATA_OUT_TIMING_00  
Figure 7-95. PRU_ICSSG IEP Digital IOs Timing Requirements  
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Table 7-111. PRU_ICSSG IEP Timing Requirements – LATCH_INx  
see Figure 7-96  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDC_LATCH_INx low  
Pulse duration, EDC_LATCH_INx high  
MIN  
2+3*P(1)  
2+3*P(1)  
MAX  
UNIT  
ns  
PRLA1 tw(EDC_LATCH_INxL)  
PRLA2 tw(EDC_LATCH_INxH)  
ns  
(1) P = PRU_ICSSG IEP clock source period in ns.  
PRLA1  
EDC_LATCH_INx  
PRLA2  
PRU_IEP_TIMING_02  
Figure 7-96. PRU_ICSSG IEP LATCH_INx Timing Requirements  
7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)  
Table 7-112. PRU_ICSSG UART Timing Conditions  
PARAMETER  
MIN  
0.01  
1
MAX  
0.33  
30  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
7.10.5.16.4.1 PRU_ICSSG UART Timing  
Table 7-113. PRU_ICSSG UART Timing Requirements  
see Figure 7-97  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, receive start, stop, data bit high  
Pulse duration, receive start, stop, data bit low  
MIN  
U(1)  
-2+U(1)  
MAX  
UNIT  
ns  
PRUR1H tw(RXH)  
PRUR1L tw(RXL)  
ns  
(1) U = UART baud time in ns = 1/programmed baud rate.  
Table 7-114. PRU_ICSSG UART Switching Characteristics  
see Figure 7-97  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
Mbps  
ns  
f(baud)  
Programmed baud rate  
12  
PRUR3H tw(TXH)  
PRUR3L tw(TXL)  
Pulse duration, transmit start, stop, data bit high  
Pulse duration, transmit start, stop, data bit low  
U (1)  
-2+U (1)  
ns  
(1) U = UART baud time in ns = 1/programmed baud rate.  
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PRUR1L  
PRUR1H  
Start  
Bit  
PRGi_UART0_RXD(1)  
Data Bits  
PRUR3L  
PRUR3H  
Start  
Bit  
PRGi_UART0_TXD(1)  
Data Bits  
PRU_UART_TIMING_01  
(1) i in PRGi_UART0_RXD and PRGi_UART0_TXD = 0, 1 or 2  
Figure 7-97. PRU_ICSSG UART Timing Requirements and Switching Characteristics  
7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)  
Table 7-115. PRU_ICSSG ECAP Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.10.5.16.5.1 PRU_ICSSG ECAP Timing  
Table 7-116. PRU_ICSSG ECAP Timing Requirements  
see Figure 7-98  
NO.  
PARAMETER  
DESCRIPTION  
Pulse Duration, CAP (asynchronous)  
Pulse Duration, SYNCI (asynchronous)  
MIN  
2+2*P(1)  
2+2*P(1)  
MAX  
UNIT  
ns  
PREP1 tw(CAP)  
PREP2 tw(SYNCI)  
ns  
(1) P = CORE_CLK period in ns.  
PREP1  
PREP2  
CAP  
SYNCI  
Figure 7-98. PRU_ICSSG ECAP Timing  
Table 7-117. PRU_ICSSG ECAP Switching Characteristics  
see Figure 7-99  
NO.  
PARAMETER  
DESCRIPTION  
Pulse Duration, APWM high/low  
MIN  
2*P(1)  
P(1)  
MAX  
UNIT  
ns  
PREP3 tw(APWM)  
PREP4 tw(SYNCO)  
Pulse Duration, SYNCO (asynchronous)  
ns  
(1) P = CORE_CLK period in ns.  
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PREP3  
PREP4  
APWM  
SYNCO  
Figure 7-99. PRU_ICSSG ECAP Switching Characteristics  
7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch  
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -  
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.  
7.10.5.16.6.1 PRU_ICSSG MDIO Timing  
Table 7-118, Table 7-119, Table 7-120, and Figure 7-100 present timing conditions, requirements, and switching  
characteristics for PRU_ICSSG MDIO.  
Table 7-118. PRU_ICSSG MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
Table 7-119. PRU_ICSSG MDIO Timing Requirements  
see Figure 7-100  
NO.  
PARAMETER  
MIN  
90  
0
MAX  
UNIT  
ns  
MDIO1 tsu(MDIO_MDC)  
MDIO2 th(MDC_MDIO)  
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high  
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high  
ns  
Table 7-120. PRU_ICSSG MDIO Switching Characteristics  
see Figure 7-100  
NO.  
PARAMETER  
Cycle time, MDIO[x]_MDC  
MIN  
MAX  
UNIT  
ns  
MDIO3 tc(MDC)  
400  
160  
160  
-150  
MDIO4 tw(MDCH)  
MDIO5 tw(MDCL)  
MDIO7 td(MDC_MDIO)  
Pulse Duration, MDIO[x]_MDC high  
ns  
Pulse Duration, MDIO[x]_MDC low  
ns  
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid  
150  
ns  
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MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
Figure 7-100. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics  
7.10.5.16.6.2 PRU_ICSSG MII Timing  
Note  
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the  
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz,  
225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1  
register must be set to 0h (default value).  
Table 7-121, Table 7-122, Figure 7-101, Table 7-123, Figure 7-102, Table 7-124, Figure 7-103, Table 7-125, and  
Figure 7-104 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MII.  
Table 7-121. PRU_ICSSG MII Timing Conditions  
PARAMETER  
MIN  
0.9  
2
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
Table 7-122. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK  
see Figure 7-101  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, MII[x]_RX_CLK  
MODE  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
MIN  
MAX UNIT  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
PMIR1 tc(RX_CLK)  
PMIR2 tw(RX_CLKH)  
PMIR3 tw(RX_CLKL)  
140  
14  
260  
26  
Pulse Duration, MII[x]_RX_CLK High  
Pulse Duration, MII[x]_RX_CLK Low  
140  
14  
260  
26  
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PMIR1  
PMIR2  
PMIR3  
MII_RX_CLK  
PRU_MII_RT_TIMING_04  
Figure 7-101. PRU_ICSSG MII[x]_RX_CLK Timing  
Table 7-123. PRU_ICSSG MII Timing Requirements – MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER  
see Figure 7-102  
NO.  
PARAMETER  
tsu(RXD-RX_CLK)  
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
tsu(RXD-RX_CLK)  
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
th(RX_CLK-RXD)  
DESCRIPTION  
MODE  
MIN  
8
MAX  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK  
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK  
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK  
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK  
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK  
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK  
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK  
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK  
10 Mbps  
8
8
PMIR4  
8
100  
Mbps  
8
8
8
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
th(RX_CLK-RXD)  
10 Mbps  
8
8
PMIR5  
8
100  
Mbps  
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
8
8
PMIR4  
PMIR5  
MII_RX_CLK  
MII_RXD[3:0],  
MII_RX_DV, MII_RX_ER  
Figure 7-102. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing  
Table 7-124. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK  
see Figure 7-103  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, MII[x]_TX_CLK  
MODE  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
MIN  
MAX UNIT  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
PMIT1 tc(TX_CLK)  
PMIT2 tw(TX_CLKH)  
PMIT3 tw(TX_CLKL)  
140  
14  
260  
26  
Pulse Duration, MII[x]_TX_CLK High  
Pulse Duration, MII[x]_TX_CLK Low  
140  
14  
260  
26  
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PMIT1  
PMIT2  
PMIT3  
MII_TX_CLK  
Figure 7-103. PRU_ICSSG MII[x]_TX_CLK Timing  
Table 7-125. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN  
see Figure 7-104  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
0
MAX  
25  
UNIT  
ns  
td(TX_CLK-TXD)  
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid  
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid  
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid  
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid  
10 Mbps  
td(TX_CLK-TX_EN)  
td(TX_CLK-TXD)  
0
25  
ns  
PMIT4  
0
25  
ns  
100  
Mbps  
td(TX_CLK-TX_EN)  
0
25  
ns  
PMIT4  
MII_TX_CLK  
MII_TXD[3:0], MII_TX_EN  
Figure 7-104. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing  
7.10.5.16.6.3 PRU_ICSSG RGMII Timing  
Table 7-126, Table 7-127, Table 7-128, Figure 7-105, Table 7-129, Table 7-130, and Figure 7-106 present timing  
conditions, requirements, and switching characteristics for PRU_ICSSG RGMII.  
Table 7-126. PRU_ICSSG RGMII Timing Conditions  
PARAMETER  
MIN  
2.65  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
Table 7-127. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RXC  
see Figure 7-105  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_RXC  
MODE  
10 Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII1 tc(RXC)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
240  
24  
RGMII2 tw(RXCH)  
Pulse duration, RGMII[x]_RXC high  
Pulse duration, RGMII[x]_RXC low  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
RGMII3 tw(RXCL)  
100 Mbps  
1000 Mbps  
3.6  
4.4  
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Table 7-128. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RD[3:0] and RGMII[x]_RX_CTL  
see Figure 7-105  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
1
MAX UNIT  
RGMII4 tsu(RD-RXC)  
Setup time, RGMII[x]_RD[3:0] valid before RXC high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
tsu(RX_CTL-RXC)  
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
RGMII5 th(RXC-RD)  
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
th(RXC-RX_CTL)  
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
1
1
RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
RGMII[x]_RX_CTL(B)  
1st Half-byte  
RXDV  
2nd Half-byte  
RXERR  
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of  
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.  
Figure 7-105. PRU_ICSSG RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements -  
RGMII Mode  
Table 7-129. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TXC  
see Figure 7-106  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_TXC  
MODE  
10 Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII6 tc(TXC)  
RGMII7 tw(TXCH)  
RGMII8 tw(TXCL)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_TXC high  
Pulse duration, RGMII[x]_TXC low  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
100 Mbps  
1000 Mbps  
3.6  
4.4  
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Table 7-130. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL  
see Figure 7-106  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
MAX UNIT  
RGMII9 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
10 Mbps  
RGMII10 toh(TXC-TD)  
Output setup time, RGMII[x]_TD[3:0] valid after  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
10 Mbps  
toh(TXC-TX_CTL)  
Output setup time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of  
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.  
Figure 7-106. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching  
Characteristics - RGMII Mode  
7.10.5.17 Timers  
For more details about features and additional description information on the device Timers, see the  
corresponding subsections within Signal Descriptions and Detailed Description sections.  
Table 7-131. Timer Timing Conditions  
PARAMETER  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
Table 7-132. Timer Input Timing Requirements  
see Figure 7-107  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
T1  
tw(TINPH)  
Pulse duration, high  
CAPTURE 2 + 4P(1)  
ns  
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Table 7-132. Timer Input Timing Requirements (continued)  
see Figure 7-107  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
T2  
tw(TINPL)  
Pulse duration, low  
CAPTURE 2 + 4P(1)  
ns  
(1) P = functional clock period in ns.  
Table 7-133. Timer Output Switching Characteristics  
see Figure 7-107  
NO.  
PARAMETER  
tw(TOUTH)  
tw(TOUTL)  
DESCRIPTION  
MODE  
PWM  
PWM  
MIN  
-2 + 4P(1)  
-2 + 4P(1)  
MAX  
UNIT  
ns  
T3  
Pulse duration, high  
Pulse duration, low  
T4  
ns  
(1) P = functional clock period in ns.  
T1  
T2  
TIMER_IOx (inputs)  
T3  
T4  
TIMER_IOx (outputs)  
TIMER_01  
Figure 7-107. Timer Timing Requirements and Switching Characteristics  
For more information, see Timers section in Peripherals chapter in the device TRM.  
7.10.5.18 UART  
For more details about features and additional description information on the device Universal Asynchronous  
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
Table 7-134. UART Timing Conditions  
PARAMETER  
MIN  
0.5  
1
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30  
Table 7-135. UART Timing Requirements  
see Figure 7-108  
NO.  
PARAMETER  
DESCRIPTION  
Pulse width, receive data bit, high or low  
Pulse width, receive start bit, high or low  
MIN  
0.95U(1)  
0.95U(1)  
MAX  
1.05U(1)  
UNIT  
ns  
4
tw(RX)  
5
tw(CTS)  
ns  
(1) U = UART baud time in ns = 1/programmed baud rate.  
Table 7-136. UART Switching Characteristics  
see Figure 7-108  
NO.  
PARAMETER  
DESCRIPTION  
Programmable baud rate  
MODE  
15 pF  
30 pF  
MIN  
MAX UNIT  
TDB Mbps  
0.115 Mbps  
ns  
f(baud)  
1
2
td(CTS-TX)  
tw(TX)  
Delay time, CTS bit to transmit data  
30  
Pulse width, transmit data bit, high or low  
U - 2.2(1) U + 2.2(1)  
ns  
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Table 7-136. UART Switching Characteristics (continued)  
see Figure 7-108  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
U - 2.2(1)  
MAX UNIT  
ns  
3
tw(RTS)  
Pulse width, transmit start bit, high or low  
(1) U = UART baud time in ns = 1/programmed baud rate.  
Figure 7-108. UART Timing Requirements and Switching Characteristics  
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter  
in the device TRM.  
7.10.5.19 USB  
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the  
specification for timing details.  
The USB 3.1 GEN1 subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0.  
Refer to the specification for timing details.  
For more details about features and additional description information on the device Universal Serial Bus  
Subsystem (USB), see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
7.10.6 Emulation and Debug  
For more details about features and additional description information on the device Trace and JTAG interfaces,  
see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
7.10.6.1 Trace  
Table 7-137. Trace Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
OUTPUT CONDITIONS  
CL Output load capacitance  
PCB CONNECTIVITY REQUIREMENTS  
2
5
pF  
VDDSHV3 = 1.8V  
VDDSHV3 =3.3V  
200  
100  
ps  
ps  
td(Trace Mismatch)  
Propagation delay mismatch across all traces  
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Table 7-138. Trace Switching Characteristics  
PARAMETER  
MIN  
MAX  
UNIT  
1.8V Mode  
DBTR1 tc(TRC_CLK)  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Cycle time, TRC_CLK  
6.50  
2.50  
2.50  
ns  
ns  
ns  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
tosu(TRC_DATAV-  
DBTR4  
Output setup time, TRC_DATA valid to TRC_CLK edge  
0.81  
ns  
TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid  
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge  
0.81  
0.81  
0.81  
ns  
ns  
ns  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
3.3V Mode  
DBTR1 tc(TRC_CLK)  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Cycle time, TRC_CLK  
8.67  
3.58  
3.58  
ns  
ns  
ns  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
tosu(TRC_DATAV-  
DBTR4  
Output setup time, TRC_DATA valid to TRC_CLK edge  
1.08  
ns  
TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid  
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge  
1.08  
1.08  
1.08  
ns  
ns  
ns  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
DBTR1  
DBTR2  
DBTR3  
TRC_CLK  
(Worst Case 1)  
(Ideal)  
(Worst Case 2)  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
TRC_DATA  
TRC_CTL  
SPRSP08_Debug_01  
Figure 7-109. Trace Switching Characteristics  
Table 7-139. JTAG Timing Conditions  
7.10.6.2 JTAG  
PARAMETER  
MIN  
0.5  
5
MAX  
2.0  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
15  
Table 7-140. JTAG Timing Requirements  
see Figure 7-110  
NO.  
MIN  
45.5  
18.2  
18.2  
4
MAX  
UNIT  
ns  
J1  
J2  
J3  
tc(TCK)  
Cycle time minimum, TCK  
tw(TCKH)  
Pulse width minimum, TCK high  
ns  
tw(TCKL)  
Pulse width minimum, TCK low  
ns  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
Input setup time minimum, TDI valid to TCK high  
Input setup time minimum, TMS valid to TCK high  
ns  
J4  
4
ns  
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Table 7-140. JTAG Timing Requirements (continued)  
see Figure 7-110  
NO.  
MIN  
2
MAX  
UNIT  
ns  
th(TCK-TDI)  
th(TCK-TMS)  
Input hold time minimum, TDI valid from TCK high  
Input hold time minimum, TMS valid from TCK high  
J5  
2
ns  
Table 7-141. JTAG Switching Characteristics  
see Figure 7-110  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
J6  
J7  
td(TCKL-TDOI)  
Delay time minimum, TCK low to TDO invalid  
Delay time maximum, TCK low to TDO valid  
0
td(TCKL-TDOV)  
14  
ns  
J1  
J2  
J3  
TCK  
TDI / TMS  
TDO  
J4  
J5  
J4  
J5  
J7  
J6  
Figure 7-110. JTAG Timing Requirements and Switching Characteristics  
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8 Detailed Description  
8.1 Overview  
AM243x is an extension of the Sitara’s industrial-grade family of heterogeneous Arm processors. AM243x  
is built for industrial applications, such as motor drives and programmable logic controllers (PLCs), which  
require a unique combination of real-time processing and communications with applications processing. AM243x  
combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG, up to four Cortex-R5F MCUs and a  
Cortex-M4F MCU.  
AM243x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled  
Memory banks, configurable SRAM partitioning, and low-latency paths to and from peripherals for rapid data  
movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control  
loops found in servo drives, while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and  
absolute encoder interfaces help enable a number of different architectures found in these systems.  
The PRU-ICSSG in AM243x provides the flexible industrial communications capability necessary to run gigabit  
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU-ICSSG also enables  
additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.  
Functional safety features can be enabled through the integrated Cortex-M4F along with its dedicated  
peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.  
Note  
For more information on features, subsystems, and architecture of superset device System on Chip  
(SoC), see the device TRM.  
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8.2 Processor Subsystems  
8.2.1 Arm Cortex-R5F Subsystem (R5FSS)  
The R5FSSSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for dual/  
single-core operation. It also includes accompanying memories (L1 caches and tightly-coupled memories),  
standard Arm® CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC  
Aggregators, and various wrappers for protocol conversion and address translation for easy integration into the  
SoC.  
Note  
The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit  
(FPU) extension.  
For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the  
device TRM.  
8.2.2 Arm Cortex-M4F (M4FSS)  
The M4FSS module on the AM243x device provides a safety channel (secondary channel - working in  
conjunction with an external microcontroller)- or- a general purpose MCU.  
The M4FSS module supports the following features:  
•
•
•
•
•
•
•
•
Cortex M4F With MPU  
ARMv7-M architecture  
Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs  
Ability to executed code from internal or external memories  
192 KB of SRAM (I-Code)  
64 KB of SRAM (D-Code)  
External access to internal memories if allowed  
Debug Support Including:  
– DAP based Debug to the CPU Core  
– Full Debug Features of CPU Core are enabled  
– Standard ITM trace  
– CTM Cross Trigger  
– ETM Trace Support  
•
Fault Detection and Correction  
– SECDED ECC protection on I-CODE  
– SECDED ECC protection on D-CODE  
– Fault Error Interrupt Output  
For more information, see Arm Cortex M4F Subsystem (M4FSS) section in Processors and Accelerators chapter  
in the device TRM.  
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8.3 Accelerators and Coprocessors  
8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)  
The PRU_ICSSG module supports the following main features:  
•
3x PRUs  
– General-Purpose PRU (PRU)  
– Real-Time PRU(RTU_PRU)  
– Transmit PRU (TX_PRU)  
•
2x Ethernet MII_G_RT configurable connection to PRUs  
– Up to 2x RGMII ports  
– Up to 2x MII ports  
– RX Classifier  
•
•
2x Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions  
2x Industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast  
compensation.  
•
•
•
1x MDIO  
1x UART, with a dedicated 192-MHz clock input  
Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable PWM  
outputs.  
•
•
•
Supports up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.  
1x Enhanced Capture Module (ECAP)  
1x Interrupt Controller (INTC)  
– 160 input events supported – 96 external, 64 internal  
Flexible power management support  
Integrated switched central resource with programmable priority  
All memories support ECC  
•
•
•
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -  
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.  
8.4 Other Subsystems  
8.4.1 PDMA Controller  
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer  
needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard  
non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which  
require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and  
supporting only statically configured Transfer Request (TR) operations.  
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals  
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data  
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of  
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to  
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.  
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer  
complexity at each point in the system to match the requirements of whatever is being transferred to or  
from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO  
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically  
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.  
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous  
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and  
employs round-robin scheduling between channels in order to share the underlying DMA hardware.  
There are five PDMA modules in the device.  
For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.  
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8.4.2 Peripherals  
8.4.2.1 ADC  
The analog-to-digital converter (ADC) module is an eight-channel general purpose analog-to-digital converter,  
which supports 12-bit conversion samples from an analog front end (AFE).  
There is one ADC module in the device.  
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.  
8.4.2.2 DCC  
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time  
execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.  
The desired accuracy can be programed based on calculation for each application. The DCC measures the  
frequency of a selectable clock source using another input clock as a reference.  
The device has seven instances of DCC modules.  
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.  
8.4.2.3 Dual Date Rate (DDR) External Memory Interface (DDRSS)  
Integrated in MAIN domain: one instance of DDR Subsystem (DDRSS) is used as an interface to external RAM  
devices which can be utilized for storing program or data. DDRSS provides the following main features:  
•
•
•
•
•
•
•
•
•
•
Support of DDR4 / LPDDR4 memory types  
16-bit memory bus interface with in-line ECC  
Up to 2 GB memory address range  
System bus interface: little endian only with 128-bit data width  
Configuration bus Interface: little endian only with 32-bit data width  
Support of dual rank configuration  
Support of automatic idle power saving mode when no or low activity is detected  
Class of Service (CoS) - three latency classes supported  
Prioritized refresh scheduling  
Statistical counters for performance management  
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.  
8.4.2.4 ECAP  
This section describes the Enhanced Capture (ECAP) module for the device.  
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.  
8.4.2.5 EPWM  
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU  
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand  
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and  
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;  
instead, the EPWM is built up from smaller single channel modules with separate resources and that can  
operate together as required to form a system. This modular approach results in an orthogonal architecture and  
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.  
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance  
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x  
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so  
forth.  
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral  
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules  
can also operate stand-alone.  
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The device has six instances of EPWM modules.  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in  
the device TRM.  
8.4.2.6 ELM  
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when  
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then  
correct the data block by flipping the bits to which the ELM error-location outputs point.  
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND  
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is  
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.  
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses  
this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome  
polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits,  
and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on  
a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome  
polynomials.  
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.  
8.4.2.7 ESM  
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device  
into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event  
and/or manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an  
external controller is able to reset the device or keep the system in safe, known state.  
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.  
8.4.2.8 GPIO  
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be  
configured as either inputs or outputs. When configured as an output, user can write to an internal register  
to control the state driven on the output pin. When configured as an input, user can obtain the state of the input  
by reading the state of an internal register.  
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different  
interrupt/event generation modes.  
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.  
8.4.2.9 EQEP  
The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary  
incremental encoder to get position, direction and speed information from a rotating machine for use in high  
performance motion and position control system. The disk of an incremental encoder is patterned with a single  
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is  
defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second  
track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used  
to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as  
index, marker, home position and zero reference.  
To derive direction information, the lines on the disk are read out by two different photo-elements that "look"  
at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized  
with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the  
disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other.  
These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders  
is defined as the QEPA channel going positive before the QEPB channel and vise versa.  
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The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at a  
geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the  
QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder  
directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so  
by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the  
motor.  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter  
in the device TRM.  
8.4.2.10 GPMC  
The GPMC module supports the following features:  
•
•
Data path to external memory device can be 32, 16 or 8 bits wide  
Support for the following memory types:  
– Asynchronous or synchronous 8-bit memory or device (non-burst device)  
– Asynchronous or synchronous 16-bit memory or device  
– Asynchronous or synchronous 32-bit memory or device  
– 16-bit non-multiplexed NOR Flash device  
– 16-bit address and 32-bit address and data multiplexed NOR Flash device  
– 8-bit and 16-bit NAND flash device  
– 16-bit and 32bit pSRAM device  
•
Supports Error Code detection using BCH code (t=4, 8 or 16) or Hamming code for 8-bit or 16-bit NAND-  
flash, organized with page size of 512 Byte, 1Kbytes, or more. • Supports 1 GByte maximum addressing  
capability, which can be divided into 8 independent chip-select with programmable bank size and base  
address on 16 MByte, 32 MByte, 64 MByte, or 128 MByte boundary.  
Fully-pipelined operation for optimal memory bandwidth usage  
Supports external device clock frequency of /1, /2, /3, and /4 divide of interface clock  
Supports programmable auto-clock gating when there is no access  
Supports MIdlereq/SIdleAck protocol  
•
•
•
•
•
Supports the following interface protocols when communicating with external memory or external devices:  
– Asynchronous read/write access  
– Asynchronous read page access (4-8-16 Word16), 4-8-16 Word32  
– Synchronous read/write access  
– Synchronous read burst access without wrap capability (4-8-16-32 Word16, 4-8-16 Word32)  
– Synchronous read burst access with wrap capability (4-8-16-32 Word16, 4-8-16 Word32)  
Address and data multiplexed access  
Each chip-select has independent and programmable control signal timing parameters for Setup and Hold  
time. Parameters are set according to the memory device timing parameters, with one interface clock cycle  
timing granularity.  
•
•
•
•
•
•
Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin  
Supports bus keeping  
Supports bus turn around  
Pre-fetch and write posting engine associated with system DMA, to get full performance from NAND device,  
and with minimum impact on NOR/SRAM concurrent access monitoring (up to 4 WAIT pins)  
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the  
device TRM.  
8.4.2.11 I2C  
The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the  
multi-master I2C bus, which allows serial transfer of 8-bit data to and from other I2C master and slave devices,  
through a two-wire interface.  
The I2C module supports the following main features:  
•
Compliant with Philips I2C specification version 2.1  
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•
Supports standard mode (up to 100K bits/s), fast mode (up to 400K bits/s), and high-speed mode (up to  
3.4Mb/s).  
•
•
•
•
•
Multi-master transmitter and slave receiver mode  
Multi-master receiver and slave transmitter mode  
Combined master transmit/receive and receive/transmit modes  
7-bit and 10-bit device addressing modes  
Built-in FIFO for buffered read or write  
– Parameterizable size of 8 to 64 bytes  
•
•
•
•
Programmable multi-slave channel (responds to 4 separates addresses)  
Programmable clock generation  
Support for asynchronous wake-up  
One interrupt line  
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device  
TRM.  
8.4.2.12 MCAN  
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed  
real-time control with a high level of security. CAN has high immunity to electrical interference and the ability  
to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire  
network, which provides for data consistency in every node of the system.  
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN  
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices  
can coexist on the same network without any conflict.  
The device supports 2 MCAN modules  
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device  
TRM.  
8.4.2.13 MCRC Controller  
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the  
integrity of a memory system. A signature representing the contents of the memory is obtained when the  
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate  
the signature for a set of data and then compare the calculated signature value against a pre-determined good  
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in  
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC  
controller compresses each data being read through CPU read data bus.  
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device  
TRM.  
8.4.2.14 MCSPI  
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.  
There are total of seven MCSPI modules in the device.  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
8.4.2.15 MMCSD  
There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1.  
Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and  
MMCSD1 is associated with MMC1.  
The MMCSD Host Controller supports:  
•
•
One controller with 8-bit wide data bus  
One controller with 4-bit wide data bus  
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•
•
•
•
•
Support of eMMC5.1 Host Specification (JESD84-B51)  
Support of SD Host Controller Standard Specification - SDIO 3.00  
Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3  
eMMC Electrical Standard 5.1 (JESD84-B51)  
Multi-Media card features:  
– Backward compatible with earlier eMMC standards  
– Legacy MMC SDR: 1.8 V, 8/4/1-bit bus width, 0-25 MHz, 25/12.5/3.125 MB/s  
– High Speed SDR: 1.8 V, 8/4/1-bit bus width, 0-50 MHz, 50/25/6.25 MB/s  
– High Speed DDR: 1.8 V, 8/4-bit bus width, 0-50 MHz, 100/50 MB/s  
– HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s  
SD card support: SDIO, SDR12, SDR25, SDR50, DDR50  
•
•
System bus interface: CBA 4.0 VBUSM master port with 64-bit data width and 64-bit address, little endian  
only  
•
Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear  
incrementing addressing mode, little endian only  
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in  
the device TRM.  
8.4.2.16 OSPI  
The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which  
allows single, dual, quad or octal read and write access to external flash devices. This module has a memory  
mapped register interface, which provides a direct memory interface for accessing data from external flash  
devices, simplifying software requirements.  
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor  
wishing to execute code directly from external flash memory), or in an indirect mode where the module is  
set-up to silently perform some requested operation, signalling its completion via interrupts or status registers.  
For indirect operations, data is transferred between system memory and external flash memory via an internal  
SRAM which is loaded for writes and unloaded for reads by a device master at low latency system speeds.  
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using  
user programmable configuration registers.  
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device  
TRM.  
8.4.2.17 Peripheral Component Interconnect Express (PCIe)  
ThePCIe subsystem supports the following main features:  
•
•
•
•
•
•
•
•
•
•
•
•
Dual mode – root port (RP) or end point (EP) modes. Selectable through bootstrap pins.  
1-lane configuration with up to 5.0GT/lane.  
62.5/125 MHz operation on PIPE interface for Gen1/Gen2 respectively  
Constant 32-bit PIPE width for Gen1/Gen2 modes  
Maximum outbound payload size of 128 bytes  
Maximum inbound payload size of 128 bytes  
Maximum remote read request size of 4K bytes  
Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.  
Four virtual channels (4VC)  
Resizable BAR capability  
SRIS support  
Power Management  
– L1 Power Management Substate support  
– D1 support  
– L1 Power Shutoff support  
•
•
•
Legacy, MSI, and MSI-X interrupt support  
32 outbound address translation regions  
Precision time measurement (PTM)  
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For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals  
chapter in the device TRM.  
8.4.2.18 Serializer/Deserializer (SerDes)  
Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/  
Deserializer (SERDES) Multi-protocol Multi-link modules with the following main blocks:  
•
•
Single-lane PHY with common module for peripheral and Tx clocking handling  
Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/  
decoding and symbol alignment  
•
•
MUX module for device interface multiplexing into a single SERDES lane (Tx and Rx)  
A wrapper for sending control and reporting status signals from the SerDes and muxes  
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.  
8.4.2.19 RTI  
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)  
functionality for the device.  
For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.  
8.4.2.20 DMTIMER  
The DMTIMER module supports the following main features:  
•
•
•
Interrupts generated on overflow, compare and capture  
Free running 32-bit upward counter  
Supported modes:  
– Compare and capture modes  
– Auto-reload mode  
– Start-stop mode  
•
•
•
•
Programmable divider clock source (2n with n=[0:8])  
Dedicated input trigger for capture mode, and dedicated output trigger/PWM (pulse width modulation) signal  
On the fly read/write register (while counting)  
Generate 1-ms tick with 32768-Hz functional clock  
For more information, see Timers section in Peripherals chapter in the device TRM.  
8.4.2.21 UART  
The UART module supports the following main features:  
•
•
•
•
16C750 compatibility  
Baud rate from 300 bps up to 3.6864 Mbps (subject to functional clock frequency)  
Auto-baud between 1200 bps and 115.2 Kbps  
Software/hardware flow control  
– Programmable Xon/Xoff characters  
– Programmable Auto-RTS and Auto CTS  
Programmable serial interface characteristics  
– 5, 6, 7, or 8-bit characters  
•
– Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and  
detection  
– 1-, 1.5-, or 2-stop bit generation  
•
•
•
•
•
•
•
•
Optional multi-drop transmission  
Configurable time-guard feature  
False start bit detection  
Line break generation and detection  
Modem control functions on UART0 (CTS, RTS, DSR, DTR, RI, and DCD)  
Fully prioritized interrupt system controls  
Internal test and loopback capabilities  
RS-485 External transceiver auto flow control support  
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For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in  
Peripherals chapter in the device TRM.  
8.4.2.22 Universal Serial Bus Subsystem(USBSS)  
The Universal Serial Bus Subsystem (USBSS) module supports the following main features:  
USB interface:  
•
•
•
•
•
•
Compliant with USB 3.1 Gen1 specification  
Compliant with xHCI 1.1 specification  
Limited USB 2.0 on-the-go support  
SuperSpeed Gen1 (5 Gbps), high speed (480 Mbps), and full (12Mbps) Device  
SuperSpeed Gen1 (5 Gbps), high speed (480 Mbps), full (12Mbps), and low speed (1.5 Mbps) Host  
Shared USB3.1/USB2.0 port  
Dual mode operation:  
•
•
OTG 2.0 host negotiation protocol (HNP) support  
OTG 2.0 session request support (SRP) support  
Host mode:  
•
•
•
•
•
64 slots supported  
Up to 96 periodic endpoints supported simultaneously  
256 primary streams supported  
MSI support  
Root hub functionality  
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device  
TRM.  
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9 Applications, Implementation, and Layout  
Note  
Information in the following applications sections is not part of the TI component specification,  
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for  
determining suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
9.1 Power Supply Mapping  
Note  
NOTE TO USERS:  
The content of this section is UNDER DEVELOPMENT!  
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9.2 Device Connection and Layout Fundamentals  
9.2.1 Power Supply Decoupling and Bulk Capacitors  
9.2.1.1 Power Distribution Network Implementation Guidance  
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for  
successful implementation of the power distribution network. This includes PCB stackup guidance as well as  
guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that  
follow the board design guidelines contained in the application report.  
9.2.2 External Oscillator  
For more information about External Oscillators, see the Clock Specifications section.  
9.2.3 JTAG and EMU  
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various  
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target  
Connection Guide.  
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual  
9.2.4 Unused Pins  
For more information about Unused Pins, see the Connections for Unused Pins section.  
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9.3 Peripheral- and Interface-Specific Design Information  
9.3.1 General Routing Guidelines  
The following paragraphs detail the routing guidelines that must be observed when routing the various functional  
LVCMOS interfaces.  
•
Line spacing:  
– For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the  
crosstalk between switching signals between the different lines. On the PCB, this is not achievable  
everywhere (for example, when breaking signals out from the device package), but it is recommended  
to follow this rule as much as possible. When violating this guideline, minimize the length of the traces  
running parallel to each other (see Figure 9-1).  
W
D+  
S = 2 W = 200 µm  
SWPS040-185  
Figure 9-1. Ground Guard Illustration  
Length matching (unless otherwise specified):  
•
– For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length difference  
between the longest and the shortest lines) must be less than 25 mm.  
– For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length  
difference between the longest and the shortest lines) must be less than 2.5 mm.  
Characteristic impedance  
– Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to  
be between 35-Ω and 65-Ω.  
Multiple peripheral support  
•
•
– For interfaces where multiple peripherals have to be supported in the star topology, the length of each  
branch has to be balanced. Before closing the PCB design, it is highly recommended to verify signal  
integrity based on simulations including actual PCB extraction.  
9.3.2 DDR Board Design and Layout Guidelines  
The goal of the AM64x DDR Board Design and Layout Guidelines is to make the DDR system implementation  
straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that  
allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports  
board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.  
9.3.3 OSPI and QSPI Board Design and Layout Guidelines  
The following section details the routing guidelines that must be observed when routing the OSPI and QSPI  
interfaces.  
9.3.3.1 No Loopback and Internal Pad Loopback  
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm  
as stripline or ~8cm as microstrip)  
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in OSPI Interface High Level  
Schematic  
Propagation delays and matching:  
– A to B < 450 ps  
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– Matching skew: < 60 ps  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
OSPI_Board_01  
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.  
Figure 9-2. OSPI Interface High Level Schematic  
9.3.3.2 External Board Loopback  
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input  
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to  
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.  
•
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must  
be approximately equal to the signal propagation delay of the control and data signals between the flash  
device and the SoC device (E to F, or F to E)  
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in OSPI Interface High Level  
Schematic  
Propagation delays and matching:  
– A to B = E to F = (C to D) / 2  
– Matching skew: < 60 ps  
Note  
The OSPI Board Loopback Hold time requirement (described in Section 7.10.5.14, OSPI) is larger  
than the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO  
pin to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.  
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A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
C
R1  
0 Ω*  
MCU_OSPI[x]_LBCLKO  
D
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
OSPI_Board_02  
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine  
tuning, if needed.  
Figure 9-3. OSPI Interface High Level Schematic  
9.3.3.3 DQS (only available in Octal Flash devices)  
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal  
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS  
output pin (C to D)  
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in OSPI Interface High Level  
Schematic  
Propagation delays and matching:  
– A to B = C to D  
– Matching skew: < 60 ps  
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A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
C
D
OSPI device DQS  
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
J7ES_OSPI_Board_03  
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.  
Figure 9-4. OSPI Interface High Level Schematic  
9.3.4 USB VBUS Design Guidelines  
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as  
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to  
be 30 V.  
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in  
the Figure 9-5), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these  
external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be  
less than 100 nA.  
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Device  
USBn_VBUS  
16.5 kΩ  
1%  
3.5 kΩ  
1%  
VBUS signal  
10 kΩ  
1%  
6.8V  
(BZX84C6V8 or equivalent)  
VSS  
VSS  
J7ES_USB_VBUS_01  
A. USBn_VBUS, where n = 0.  
Figure 9-5. USB VBUS Detect Voltage Divider / Clamp Circuit  
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 9-5 limits the input  
current to the actual device pin in a case where VBUS is applied while the device is powered off.  
9.3.5 System Power Supply Monitor Design Guidelines  
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a  
single pre-regulated power source for the entire system. This supply is monitored by comparing the output of an  
external voltage divider circuit sourced by this supply with an internal voltage reference, with a power fail event  
being triggered when the voltage applied to VMON_VSYS drops below the internal reference voltage. The actual  
system power supply voltage trip point is determined by the system designer when selecting component values  
used to implement the external resistor voltage divider circuit.  
When designing the resistor divider circuit it is important to understand various factors which contribute to  
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of  
the VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision  
1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider.  
This minimizes variability contributed by resistor value tolerances. Input leakage current associated with  
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the  
voltage divider output. The VMON_VSYS input leakage current may be in the range of 10 nA to 2.5 µA when  
applying 0.45 V.  
Note  
The resistor voltage divider shall be designed such that its output voltage never exceeds the  
maximum value defined in the Recommended Operating Conditions section, during normal operating  
conditions.  
Figure 9-6 presents an example, where the system power supply is nominally 5 V and the maximum trigger  
threshold is 5 V - 10%, or 4.5 V.  
For this example, it is important to understand which variables effect the maximum trigger threshold when  
selecting resistor values. It is obvious a device which has a VMON_VSYS input threshold of 0.45 V + 3% needs  
to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The  
effect of resistor tolerance and input leakage also needs to be considered, but how these contributions effect  
the maximum trigger point may not be obvious. When selecting component values which produce a maximum  
trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of  
R2 is 1% high combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When  
implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold  
of 4.523 V.  
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Once component values have been selected to satisfy the maximum trigger voltage as described above, the  
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an  
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input  
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result  
is a minimum trigger threshold of 4.008 V.  
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523  
V. Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,  
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV  
of this range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.  
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor  
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to  
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor  
divider bias current vs loading error is something the system designer needs to consider when selecting  
component values.  
The system designer should also consider implementing a noise filter on the voltage divider output since  
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done by  
installing a capacitor across R1 as shown in Figure 9-6. However, the system designer must determine the  
response time of this filter based on system supply noise and expected response to transient events.  
Device  
VMON_VSYS  
R2  
VSYS  
40.2 kΩ 1%  
C1  
Value = Determined by system designer  
(System Power Supply)  
4.81 kΩ  
1%  
R1  
VSS  
SPRSP56_VMON_ER_MON_01  
Figure 9-6. System Supply Monitor Voltage Divider Circuit  
VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8 V power supplies. An  
internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can  
program each internal resistor divider to create appropriate under voltage and over voltage interrupts.  
VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3 V power supplies. An  
internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can  
program each internal resistor divider to create appropriate under voltage and over voltage interrupts.  
9.3.6 High Speed Differential Signal Routing Guidance  
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed  
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and  
spacing limits. TI supports only designs that follow the board design guidelines contained in the application  
report.  
9.3.7 Thermal Solution Guidance  
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful  
implementation of a thermal solution for system designs containing this device. This document provides  
background information on common terms and methods related to thermal solutions. TI only supports designs  
that follow system design guidelines contained in the application report.  
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10 Device and Documentation Support  
10.1 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for  
example, AM2434_ALV, AM2432_ALV, AM2431_ALV). Texas Instruments recommends two of three possible  
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of  
product development from engineering prototypes (TMDX) through fully qualified production devices and tools  
(TMDS).  
Device development evolutionary flow:  
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and  
may not use production assembly flow.  
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical  
specifications.  
null Production version of the silicon die that is fully qualified.  
Support tool development evolutionary flow:  
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.  
TMDS Fully-qualified development-support product.  
X and P devices and TMDX development-support tools are shipped against the following disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
Production devices and TMDS development-support tools have been characterized fully, and the quality and  
reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system because their  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
For orderable part numbers of AM243x devices in the ALV package type, see the Package Option Addendum of  
this document, the TI website (ti.com), or contact your TI sales representative.  
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10.1.1 Standard Package Symbolization  
Note  
Some devices may have a cosmetic circular marking visible on the top of the device package which  
results from the production test process. In addition, some devices may also show a color variation in  
the package substrate which results from the substrate manufacturer. These differences are cosmetic  
only with no reliability impact.  
aBBBBBBrZfYytPPPQ1  
A1 (PIN ONE INDICATOR)  
XXXXXXX  
G1  
ZZZ  
YYY  
O
Figure 10-1. Printed Device Reference  
10.1.2 Device Naming Convention  
Table 10-1. Nomenclature Description  
FIELD PARAMETER FIELD DESCRIPTION  
VALUE  
DESCRIPTION  
X
Prototype  
a(1)  
Device evolution stage  
P
Preproduction (production test flow, no reliability data)  
Production  
BLANK  
AM2434  
Base production part  
number  
BBBBBB  
AM2432  
See Table 5-1 , Device Comparison  
AM2431  
r
Device revision  
A
S
C
D
E
SR 1.0  
Z
Device Speed Grades  
See Table 7-2, Speed Grade Maximum Frequency  
No Additional Features Enabled  
ICSS Enabled  
Features  
(see Table 5-1)  
f
ICSS + EtherCAT HW Accelerator + CAN-FD Enabled  
ICSS + EtherCAT HW Accelerator + CAN-FD + Pre-integrated Stacks  
Enabled  
F
G
Non-Functional Safety  
Functional Safety  
Y
Functional Safety  
F(2)  
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Table 10-1. Nomenclature Description (continued)  
FIELD PARAMETER FIELD DESCRIPTION  
VALUE  
DESCRIPTION  
G
Non-Secure  
Secure  
y
Security  
Other  
-40°C to 105°C - Extended Industrial (see Recommended Operating  
Conditions)  
t(3)  
Temperature  
Package Designator  
A
ALV  
ALX  
ALV FCBGA-N441 (17.2 mm × 17.2 mm) Package  
ALX FC/CSP-N293 (11.0 mm × 11.0 mm) Package  
Lot Trace Code (LTC)  
PPP  
XXXXXXX  
YYY  
ZZZ  
Production Code; For TI use only  
Production Code; For TI use only  
Pin one designator  
O
G1  
ECAT—Green package designator  
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent  
evolutionary stages of product development from engineering prototypes through fully qualified production devices.  
Prototype devices are shipped against the following disclaimer:  
“This product is still in development and is intended for internal evaluation purposes.”  
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of  
merchantability of fitness for a specific purpose, of this device.  
(2) Functional Safety features are not supported by ALX package.  
(3) Applies to device max junction temperature.  
Note  
BLANK in the symbol or part number is collapsed so there are no gaps between characters.  
10.2 Tools and Software  
The following products support development for AM243x platforms:  
Development Tools  
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated  
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded  
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded  
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,  
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each  
step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever  
before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced  
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for  
embedded developers.  
SysConfig-PinMux Tool The SysConfig-PinMux Utility is a software tool which provides a Graphical User  
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI  
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration  
to satisfy entered system requirements. The tool will generate output C header/code files that can be imported  
into software development kits (SDKs) and used to configure customer's software to meet custom hardware  
requirements.  
Power Estimation Tool (PET) Power Estimation Tool (PET) provides users the ability to gain insight in to  
the power consumption of select TI processors. The tool includes the ability for the user to choose multiple  
application scenarios and understand the power consumption as well as how advanced power saving techniques  
can be applied to further reduce overall power consumption.  
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments  
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized  
distributor.  
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10.3 Documentation Support  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
The current documentation that describes the processor, related peripherals, and other technical collateral is  
listed below.  
The following documents describe the AM243x family of devices.  
Technical Reference Manual  
AM64x/AM243x Processors Silicon Revision 1.0 Technical Reference Manual Details the integration, the  
environment, the functional description, and the programming models for each peripheral and subsystem in the  
AM243x family of devices.  
Errata  
AM64x/AM243x Processors Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the  
functional specifications for the device.  
Tip: Search TI.com using literature numbers.  
10.4 Support Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
10.5 Trademarks  
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
Code Composer Studio™ is a trademark of TI.  
TI E2E™ is a trademark of Texas Instruments.  
Arm®, Cortex®, TrustZone® are registered trademarks of Arm Limited.  
PCI-Express® are registered trademarks of PCI-SIG.  
EtherCAT® is a registered trademark of Beckhoff Automation GmbH.  
All trademarks are the property of their respective owners.  
10.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
10.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
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11 Mechanical, Packaging, and Orderable Information  
11.1 Packaging Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
XAM2431ASFGGAALV  
XAM2431ASFGGAALX  
XAM2432ASFGGAALV  
XAM2432ASFGGAALX  
XAM2434ASFGGAALV  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FCBGA  
FC/CSP  
FCBGA  
FC/CSP  
FCBGA  
ALV  
ALX  
ALV  
ALX  
ALV  
441  
293  
441  
293  
441  
84  
96  
84  
96  
1
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
Call TI  
Call TI  
Call TI  
Call TI  
Non-RoHS &  
Non-Green  
(SFGGAALV, XAM2434  
A)  
709  
XAM2434ASFGGAALX  
ACTIVE  
FC/CSP  
ALX  
293  
1
Non-RoHS &  
Non-Green  
Call TI  
Call TI  
-40 to 105  
XAM2434A  
SFGGAALX  
709  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Jul-2021  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE OUTLINE  
ALV0441A  
FCBGA - 2.657 mm max height  
SCALE 0.900  
BALL GRID ARRAY  
17.3  
17.1  
A
B
BALL A1 CORNER  
PIN 1 ID  
(OPTIONAL)  
17.3  
17.1  
(
12.8)  
0.1 C  
(
(
10.8)  
16.8)  
(1.45)  
2.652  
2.332  
0.2 C  
C
SEATING PLANE  
0.15 C  
(0.662)  
0.5  
TYP  
0.3  
16 TYP  
SYMM  
(0.6) TYP  
(0.6) TYP  
0.8 TYP  
AA  
Y
W
V
U
T
R
P
N
M
L
SYMM  
16  
K
J
TYP  
H
G
F
E
D
C
B
A
0.55  
0.45  
C A B  
441X  
0.25  
0.1  
1
2
3
4
5
6 7 8 9 10 12 14 16 18 20  
11 13 15 17 19 21  
C
0.8 TYP  
4225999/A 06/2020  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
ALV0441A  
FCBGA - 2.657 mm max height  
BALL GRID ARRAY  
441X ( 0.4)  
(0.8) TYP  
1
2 3  
4
5
6
7
8
9
10 11 12 13 14 15 16  
20 21  
17 18 19  
A
(0.8) TYP  
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
LAND PATTERN EXAMPLE  
EXPOSED METAL SNOWN  
SCALE:6X  
0.07 MAX  
0.07 MIN  
METAL UNDER  
SOLDER MASK  
(
0.4)  
METAL  
EXPOSED METAL  
(
0.4)  
SOLDER MASK  
OPENING  
EXPOSED METAL  
SOLDER MASK  
OPENING  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4225999/A 06/2020  
NOTES: (continued)  
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
ALV0441A  
FCBGA - 2.657 mm max height  
BALL GRID ARRAY  
441X 0.4  
(0.8) TYP  
1
2 3  
4
5
6
7
8
9
10 11 12 13 14 15 16  
20 21  
17 18 19  
A
(0.8) TYP  
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.15 mm THICK STENCIL  
SCALE: 6X  
4225999/A 06/2020  
NOTES: (continued)  
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
www.ti.com  
PACKAGE OUTLINE  
ALX0293A  
FCBGA - 1 mm max height  
S
C
A
L
E
1
.
5
0
0
PLASTIC BALL GRID ARRAY  
11.1  
10.9  
A
B
BALL A1  
CORNER  
11.1  
10.9  
0.15 C  
0.2 C  
1 MAX  
C
SEATING PLANE  
0.1 C  
0.29  
0.15  
10 TYP  
SYMM  
(0.5)  
AA  
Y
W
V
(0.5)  
U
T
R
P
N
M
L
SYMM  
10 TYP  
K
J
H
G
F
E
D
C
0.37  
293X  
0.27  
B
A
0.15  
C A B  
C
0.05  
7
3
8
9
13 14 15 16 17 18  
21  
19 20  
5
6
10 11 12  
1
2
4
0.5 TYP  
0.5 TYP  
4226368/A 10/2020  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
ALX0293A  
FCBGA - 1 mm max height  
PLASTIC BALL GRID ARRAY  
(0.5) TYP  
293X ( 0.3)  
(0.5) TYP  
1
2
3
4
5
6
7
9
10 11  
12 13 14 15 16 17 18 19 20 21  
8
A
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 10X  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
METAL UNDER  
SOLDER MASK  
EXPOSED METAL  
(
0.3)  
(
0.3)  
SOLDER MASK  
OPENING  
EXPOSED METAL  
SOLDER MASK  
OPENING  
METAL EDGE  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4226368/A 10/2020  
NOTES: (continued)  
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
ALX0293A  
FCBGA - 1 mm max height  
PLASTIC BALL GRID ARRAY  
(0.5) TYP  
293X ( 0.3)  
(0.5) TYP  
1
2
3
4
5
6
7
9
10 11  
12 13 14 15 16 17 18 19 20 21  
8
A
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE: 10X  
4226368/A 10/2020  
NOTES: (continued)  
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party  
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,  
costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either  
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s  
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2021, Texas Instruments Incorporated  

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