AM2732ADRFGQZCERQ1_技术文档

AM2732

SWRS245 – DECEMBER 2021

AM273x Sitara™ Microcontrollers

•

Digital Connectivity

– 4x Serial Peripheral Interface (SPI) controllers

operating up to 25 MHz

1 Features

Processor Cores:

– 3x Inter-Integrated Circuit (I2C) ports

– 4x Universal Asynchronous Receiver-

Transmitters (UART)

•

Dual-core Arm^®Cortex^®-R5F MCU subsystem

operating up to 400 MHz, highly-integrated for

real-time processing

Industrial and control interfaces:

– Dual-core Arm® Cortex®-R5F cluster supports

dual-core and single-core operation

– 32KB ICache and 32KB DCache per R5F core

with SECDED ECC on all memories

– Single-core: 128KB TCM per cluster (128KB

TCM per R5F core)

– Dual-core: 128KB TCM per cluster (64KB TCM

per R5F core)

TMS320C66x DSP core

•

3x Enhanced Pulse-Width Modulator (ePWM)

1x Enhanced Capture Module (eCAP)

2x Modular Controller Area Network (MCAN)

modules with CAN-FD support

Power Management:

•

Simplified power sequencing and reduced number

of power supply rails

•

Dual voltage digital I/O supporting 3.3V and 1.8V

operation

– Single core, 32-bit, floating point DSP

– Operating at 450 MHz (14.4 GMAC)

Security:

Memory subsystem:

•

Device Security

•

Up to 5.0 MB On Chip RAM (OCSRAM)

– Programmable embedded Hardware Security

Module (HSM)

– Secure authenticated and encrypted boot

support

– Customer programmable root keys, symmetric

keys (256 bit), Asymmetric keys (up to RSA-4K

or ECC-512) with Key revocation capability

– Crypto hardware accelerators - PKA with ECC,

AES (up to 256 bit), TRNG/DRBG

– Memory space sharable between DSP, MCU,

and shared L3

– 3.5625MB shared L3 memory

– 960KB dedicated to Main subsystem

– 384KB dedicated to DSP subsystem

External Memory Interfaces (EMIF)

– QSPI interface operating up to 67 MHz

•

System on Chip (SoC) Services and Architecture:

•

12x EDMA for various subsystems, MCU, DSP

and Accelerator cores

5x Real-Time Interrupt (RTI) modules

Mailbox system for Interprocessor Communication

(IPC)

JTAG/Trace interfaces for device debugging

Clock source

– 40.0 MHz crystal with internal oscillator

– Supports external oscillator at 40/50 MHz

– Supports externally driven clock (Square/Sine)

at 40/50 MHz

Functional Safety:

•

Functional Safety-Compliant targeted

•

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Hardware integrity up to ASIL B targeted

– Safety-related certification

•

ISO 26262 certification by TÜV SÜD

planned

•

AEC-Q100 qualification targeted

Operating Conditions

High-speed Serial Interfaces:

– Automotive grade temperature range supported

– Industrial grade temperature range supported

•

10/100 Mbps Ethernet (RGMII/RMII/MII)

Input: 2x 4-lane MIPI D-PHY CSI 2.0 Data

Output: 4-lane Aurora/LVDS

Package options:

•

ZCE (285-pin) nFBGA package 13mm x 13mm,

0.65 mm pitch

General Connectivity Peripherals:

•

45-nm technology

Compact solution size

•

General Purpose Analog to Digital Converters

(GPADC)

– 1x 9-channel ADC supporting up to 625 Ksps

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

AM2732

SWRS245 – DECEMBER 2021

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2 Applications

•

Robotics

Factory Automation Safety Guards

Building Automation

Automotive Audio

Traffic Monitoring

Machine Vision

Avionics

Industrial Transport

3 Description

The AM273x family of microcontrollers is a highly-integrated, high-performance microcontroller based on the

Arm Cortex-R5F and a C66x floating-point DSP cores. The device enables Original-Equipment Manufacturers

(OEM) and Original-Design Manufacturers (ODM) to quickly bring to market devices with robust software

support, rich user interfaces, and high performance, through the maximum flexibility of a fully integrated, mixed

processor solution.

With an integrated Hardware Security Module (HSM) and functional safety support built in, large, integrated RAM

on die and a wide temperature range, the AM273x offers a safe, secure and cost effective solution for many

industrial and automotive applications.

The AM273x device is provided as part of a complete platform solution including hardware reference designs,

software drivers, DSP library, sample software configurations/applications, API guide, and user documentation.

Device Information

PART NUMBER

AM2732ADRFGAZCER

AM2732ADRFGQZCERQ1

PACKAGE⁽¹⁾

nFBGA (285)

BODY SIZE

13 mm x 13 mm

(1) For more information, see Section 11, Mechanical, Packaging, and Orderable Information.

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3.1 Functional Block Diagram

Figure 3-1. AM273x Functional Block Diagram

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................2

3 Description.......................................................................2

3.1 Functional Block Diagram...........................................3

4 Revision History.............................................................. 4

5 Device Comparison.........................................................5

5.1 Related Products........................................................ 6

6 Terminal Configuration and Functions..........................7

6.1 Pin Diagram................................................................ 7

6.2 Pin Attributes.............................................................12

6.3 Signal Descriptions................................................... 33

7 Specifications................................................................ 42

7.1 Absolute Maximum Ratings...................................... 42

7.2 ESD Ratings............................................................. 42

7.3 Power-On Hours (POH)............................................42

7.4 Recommended Operating Conditions.......................43

7.5 Operating Performance Points .................................44

7.6 Power Supply Specifications ....................................44

7.7 I/O Buffer Type and Voltage Rail Dependency......... 44

7.8 CPU Specifications................................................... 45

7.9 Thermal Resistance Characteristics for nFBGA

7.10 Power Consumption Summary............................... 45

7.11 Timing and Switching Characteristics..................... 46

8 Detailed Description......................................................72

8.1 Overview...................................................................72

8.2 Main Subsystem....................................................... 72

8.3 DSP Subsystem........................................................72

8.4 Radar Control Subsystem.........................................72

8.5 Other Subsystems.................................................... 72

8.6 Boot Modes...............................................................75

9 Applications, Implementation, and Layout................. 77

9.1 Typical Application.................................................... 77

10 Device and Documentation Support..........................83

10.1 Device Nomenclature..............................................83

10.2 Tools and Software................................................. 87

10.3 Documentation Support.......................................... 88

10.4 Support Resources................................................. 88

10.5 Trademarks.............................................................88

10.6 Electrostatic Discharge Caution..............................88

10.7 Glossary..................................................................88

11 Mechanical, Packaging, and Orderable

Information.................................................................... 89

Package [ZCE285A] ...................................................45

4 Revision History

DATE

REVISION

NOTES

December 2021

*

Initial Release

4

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5 Device Comparison

Table 5-1. Device Comparison

AM2732

FUNCTION

ADRFGAZCER

3.625 Mbytes

ADRFGQZCERQ1

On-chip memory

3.625 Mbytes

ASIL

B-Targeted

PROCESSORS

MCU Arm Cortex (R5F)

Yes

DSP (C66x)

RADAR FEATURES

Hardware Accelerator 2.0

No

PERIPHERALS

Ethernet Interface RGMII, RMII, MII (10/100 ONLY)

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

Inter-Integrated Circuit (I²C) Interface

Modular Controller Area Network (MCAN) modules with CAN-FD

Universal Asynchronous Receiver-Transmitters (UART)

Enhanced Pulse-Width Modulator (ePWM)

Enhanced Capture Module (eCAP)

Hardware in Loop (HIL/DMM)

General Purpose ADC (9 Channels)

4-lane Aurora/LVDS Debug

Yes

4

1

3

2

4

3

Yes

1

Yes

2

4-lane MIPI D-PHY CSI2.0 (CSI2_RX0 and CSI2_RX1)

JTAG/Trace

Yes

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5.1 Related Products

Sitara™ processors Broad family of scalable processors based on Arm® Cortex® cores with flexible

accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara^™

processors have the reliability needed for use in industrial applications.

AM273x Sitara™ microcontrollers AM273x microcontrollers enable industrial Ethernet networks, robust

operation with extensive ECC on memories, and enhanced security features.

Sitara™ processors - Evaluation Modules TI provides Evaluation Modules (EVM) are also provided to help

kick-start product development. See the AM273x GP EVM for more information.

Products to complete your design Review products that are frequently purchased or used in conjunction with

this product to complete your design. See the following:

•

4x 5-A (20-A) multiphase buck converter PMIC with functional safety features for automotive SoCs

LP8764-Q1

•

Extended temperature, robust low-latency gigabit Ethernet PHY transceiver DP83867E

Automotive high-speed CAN transceiver TCAN1044-Q1

6

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6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the pin locations for the 285-pin NanoFree^™(nFBGA) package (ZCE). Figure 6-2, Figure 6-3,

Figure 6-4, and Figure 6-5 show the same pins, but split into four quadrants.

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

MSS

_MIBSPIB

_MISO

MSS

_MIBSPIB

_CS0

MSS

_MIBSPIA

_CS0

MSS

_MIBSPIA

_CLK

RCSS

_MIBSPIA

_CS0

RCSS

_MIBSPIB

_MOSI

RCSS

_MIBSPIB

_CLK

RCSS_GPIO

_49

DSS_UARTA DSS_UARTA MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

MSS_MDIO

_DATA

MSS_MDIO

_CLK

19

18

17

16

15

14

13

12

11

10

9

VSS

MSS_GPIO_9

VSS

_RX

_TX

_TCLK

_RD3

_RCLK

_RD1

MSS

_MIBSPIB

_MOSI

MSS

_MIBSPIB

_CLK

MSS

_MIBSPIB

_CS1

MSS

_MIBSPIA

_HOSTIRQ

MSS

_MIBSPIA

_MOSI

RCSS

_MIBSPIA

_MOSI

RCSS

_MIBSPIA

_CLK

RCSS

_MIBSPIA

_HOSTIRQ

RCSS

_MIBSPIB

_MISO

RCSS

_MIBSPIB

_HOSTIRQ

MSS_GPIO

_12

MSS_GPIO

_10

MSS_I2CA

_SCL

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

MSS_RGMII

_RD0

VNWA

_TCTL

_TD3

_TD0

_RD2

MSS

_MIBSPIB

_CS2

MSS

_MIBSPIA

_MISO

RCSS

_MIBSPIA

_MISO

RCSS

_MIBSPIB

_CS0

RCSS_UARTA MSS_GPIO

_TX _13

MSS_GPIO

_11

MSS_RGMII

_RCTL

MSS_RGMII

_TD1

HW_SYNC

_FE1

HW_SYNC

_FE2

VDD_SRAM1

NERRORIN RCSS_UARTA

_FE2 _RX

MSS_I2CA

_SDA

MSS_RGMII

_TD2

TRACE_DATA TRACE_DATA

_0 _2

VSS

VIOIN

VSS

TDO

TMS

VIOIN

VIOIN_18

VIOIN

VSS

VIOIN_18

VIOIN

NERRORIN

_FE1

TRACE_DATA TRACE_DATA TRACE_DATA

_1 _3 _4

NRESET_FE2 NRESET_FE1

VIOIN_18

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

NWARMRESET

_IN_FE1

TRACE_DATA TRACE_DATA

_5 _7

VSS

VDD

VSS

VDD

NWARMRESET

_IN_FE2

TRACE_DATA TRACE_DATA TRACE_DATA

_6 _8 _9

CSI2_RX1M0 CSI2_RX1P0

CSI2_RX1P1 CSI2_RX1M1

VSS

VDD

VSS

VDD

TRACE_CTL TRACE_CLK

CSI2

_RX1CLKM

CSI2

_RX1CLKP

VIOIN

_18CSI

TRACE_DATA TRACE_DATA TRACE_DATA

_10

_11

_12

TRACE_DATA

_15

TRACE_DATA TRACE_DATA

_13

CSI2_RX1M2 CSI2_RX1P2

CSI2_RX1M3 CSI2_RX1P3

CSI2_RX0M0 CSI2_RX0P0

CSI2_RX0M1 CSI2_RX0P1

_14

VIOIN

_18CSI

MSS_UARTB

_TX

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VPP

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

8

VDD_SRAM3

VIOIN

_18LVDS

7

VSS

LVDS_CLKP LVDS_CLKM

LVDS_TXM0 LVDS_TXP0

LVDS_TXM1 LVDS_TXP1

LVDS_TXM2 LVDS_TXP2

LVDS_TXM3 LVDS_TXP3

CSI2

_RX0CLKP

CSI2

_RX0CLKM

6

VSS

VIOIN

_18LVDS

5

CSI2_RX0P2 CSI2_RX0M2

CSI2_RX0P3 CSI2_RX0M3

TDI

VSS

VIOIN

TEMP

_SENSOR_1

OSC_CLK

_OUT_AUDIO

4

VIOIN

VIOIN_18

VIOIN

VIOIN_18

MSS_GPIO

_28

TEMP

_SENSOR_2

VIOIN

_18ADC

MSS_UARTA

_RX

3

VSS

MSS_GPIO_8

TCK

MSS_EPWMA0

VDD_SRAM2

NERROR_IN

NRESET

MSS_MCANA MSS_MCANA MSS_QSPI

MSS_QSPI

_D1

MSS_QSPI

_D3

MSS_QSPI

_CS

MSS_RS232

_RX

VIOIN

_18CLK

MSS_UARTA

2

MSS_GPIO_2 FE2_REFCLK XREF_CLK1

ADC5

ADC9

ADC7

ADC8

ADC2

ADC4

ADC1

ADC3

ADC6

VSS

_TX

_RX

_D0

MSS_MCANB MSS_MCANB MSS_QSPI

_TX _RX _D2

MSS_QSPI

_CLK

PMIC

_CLKOUT

MSS_RS232

_TX

1

VSS

FE1_REFCLK XREF_CLK0 WARM_RESETNERROR_OUT

VBGAP

CLKM

CLKP

VSS

Not to scale

Figure 6-1. Pin Diagram (Top View)

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A

B

C

D

E

F

G

H

J

MSS

_MIBSPIB

_MISO

MSS

_MIBSPIB

_CS0

MSS

_MIBSPIA

_CS0

MSS

_MIBSPIA

_CLK

RCSS_GPIO

_49

DSS_UARTA DSS_UARTA

19

18

17

16

15

14

13

12

11

VSS

MSS_GPIO_9

_RX

_TX

MSS

_MIBSPIB

_MOSI

MSS

_MIBSPIB

_CLK

MSS

_MIBSPIB

_CS1

MSS

_MIBSPIA

_HOSTIRQ

MSS

_MIBSPIA

_MOSI

MSS_GPIO

_12

MSS_GPIO

_10

MSS_I2CA

_SCL

MSS_RGMII

_TCTL

MSS

_MIBSPIB

_CS2

MSS

_MIBSPIA

_MISO

RCSS_UARTA MSS_GPIO

_TX _13

MSS_GPIO

_11

MSS_RGMII

_RCTL

NERRORIN RCSS_UARTA

_FE2 _RX

MSS_I2CA

_SDA

VSS

VIOIN

VSS

VIOIN

NERRORIN

_FE1

NRESET_FE2 NRESET_FE1

VIOIN_18

VDD

VSS

VDD

VSS

NWARMRESET

VSS

VDD

_IN_FE1

NWARMRESET

_IN_FE2

CSI2_RX1M0 CSI2_RX1P0

CSI2_RX1P1 CSI2_RX1M1

VSS

VDD

VSS

CSI2

_RX1CLKM

CSI2

_RX1CLKP

VIOIN

_18CSI

VSS

Not to scale

1

2

4

3

Figure 6-2. Top Left Quadrant (Top View)

8

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K

L

M

N

P

R

T

U

V

W

RCSS

_MIBSPIA

_CS0

RCSS

_MIBSPIB

_MOSI

RCSS

_MIBSPIB

_CLK

MSS_RGMII MSS_RGMII MSS_RGMII MSS_RGMII

MSS_MDIO

_DATA

MSS_MDIO

_CLK

19

18

17

16

15

14

13

12

11

VSS

_TCLK

_RD3

_RCLK

_RD1

RCSS

_MIBSPIA

_MOSI

RCSS

_MIBSPIA

_CLK

RCSS

_MIBSPIA

_HOSTIRQ

RCSS

_MIBSPIB

_MISO

RCSS

_MIBSPIB

_HOSTIRQ

MSS_RGMII MSS_RGMII MSS_RGMII

MSS_RGMII

_RD0

VNWA

_TD3

_TD0

_RD2

RCSS

_MIBSPIA

_MISO

RCSS

_MIBSPIB

_CS0

MSS_RGMII

_TD1

HW_SYNC

_FE1

HW_SYNC

_FE2

VDD_SRAM1

MSS_RGMII

_TD2

TRACE_DATA TRACE_DATA

_0 _2

VIOIN_18

VIOIN

VSS

VIOIN_18

VIOIN

TRACE_DATA TRACE_DATA TRACE_DATA

_1 _3 _4

VDD

VSS

VDD

VSS

TRACE_DATA TRACE_DATA

_5 _7

VSS

VDD

TRACE_DATA TRACE_DATA TRACE_DATA

_6 _8 _9

VSS

VDD

TRACE_CTL TRACE_CLK

TRACE_DATA TRACE_DATA TRACE_DATA

_10

_11

_12

Not to scale

1

2

4

3

Figure 6-3. Top Right Quadrant (Top View)

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A

B

C

D

E

F

G

H

J

10

9

8

7

6

5

4

3

2

1

CSI2_RX1M2 CSI2_RX1P2

CSI2_RX1M3 CSI2_RX1P3

CSI2_RX0M0 CSI2_RX0P0

CSI2_RX0M1 CSI2_RX0P1

VSS

VDD

VIOIN

_18CSI

VDD

VSS

VDD

VSS

VDD

VSS

TDO

TMS

VSS

CSI2

_RX0CLKP

CSI2

_RX0CLKM

CSI2_RX0P2 CSI2_RX0M2

CSI2_RX0P3 CSI2_RX0M3

TDI

VSS

VIOIN

VIOIN_18

MSS_GPIO

_28

VSS

MSS_GPIO_8

TCK

MSS_EPWMA0

VDD_SRAM2

MSS_MCANA MSS_MCANA MSS_QSPI

MSS_QSPI

_D1

MSS_QSPI

_D3

MSS_QSPI

_CS

MSS_RS232

_RX

MSS_GPIO_2 FE2_REFCLK

_TX

_RX

_D0

MSS_MCANB MSS_MCANB MSS_QSPI

_TX _RX _D2

MSS_QSPI

_CLK

PMIC

_CLKOUT

MSS_RS232

_TX

VSS

FE1_REFCLK XREF_CLK0

Not to scale

1

3

2

4

Figure 6-4. Bottom Left Quadrant (Top View)

10

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K

L

M

N

P

R

T

U

V

W

TRACE_DATA

_15

TRACE_DATA TRACE_DATA

10

9

8

7

6

5

4

3

2

1

VSS

_13

_14

MSS_UARTB

_TX

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VPP

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

VDD_SRAM3

VIOIN

_18LVDS

LVDS_CLKP LVDS_CLKM

LVDS_TXM0 LVDS_TXP0

LVDS_TXM1 LVDS_TXP1

LVDS_TXM2 LVDS_TXP2

LVDS_TXM3 LVDS_TXP3

VSS

VIOIN

_18LVDS

VIOIN

TEMP

_SENSOR_1

OSC_CLK

_OUT_AUDIO

VIOIN

VIOIN_18

TEMP

_SENSOR_2

VIOIN

_18ADC

MSS_UARTA

_RX

NERROR_IN

NRESET

VIOIN

_18CLK

MSS_UARTA

XREF_CLK1

ADC5

ADC9

ADC7

ADC8

ADC2

ADC4

ADC1

ADC3

ADC6

VSS

_TX

WARM_RESETNERROR_OUT

VBGAP

CLKM

CLKP

VSS

Not to scale

1

3

2

4

Figure 6-5. Bottom Right Quadrant (Top View)

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6.2 Pin Attributes

The following list describes the contents of each column in Table 6-1, Pin Attributes:

1. BALL NUMBER: BGA coordinate of signal

2. PAD NAME: Associated pinmux pad coordinate for each BGA. The specific PINCNTL address register will

be prefixed with this name. See the associated device-specific TRM for more information.

3. BALL NAME: Default signal name of BGA. Based on the default MUXMODE selection after reset release.

4. SIGNAL NAME: Each specific MUXMODE signal name.

5. PINCNTL ADDRESS: MSS_IOMUX register address for each pad control register.

6. MUX MODE: Supported FUNC_SEL field names in associated MSS_IOMUX configuration register.

7. TYPE: IO buffer type and direction associated with specific MSS_IOMUX FUNC_SEL field selection.

8. BALL RESET STATE: State of the terminal at power-on reset, during while NRESET is asserted.

9. PULL TYPE (UP/DOWN): IO buffer default internal pull direction and type.

10. Modes and values marked RSVD are reserved and not available for customer configuration.

Table 6-1. Pin Attributes (ZCE285A Package)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

E18

PADAA

MSS_MIBSPIB_CS1

MSS_GPIO_12

0x020C 0000

0

1

IO

I

Output Disabled

Pull Down

MSS_MIBSPIA_HOSTIRQ

RSVD

2

RSVD

O

RSVD

3

RSVD

4

RSVD

5

MSS_MIBSPIB_CS1

MSS_GPIO_13

MSS_GPIO_0

PMIC_CLKOUT

MSS_EPWM_TZ2

RSVD

6

H1

PADAB

FE1_REFCLK

0x020C 0004

0

IO

Output Disabled

Pull Down

1

IO

2

O

3

O

4

RSVD

I

RSVD

5

RSVD

6

FE1_REFCLK

RSVD

7

8

RSVD

O

RSVD

9

MSS_EPWMA1

MSS_EPWMB0

MSS_GPIO_16

MSS_GPIO_1

RSVD

10

11

0

O

J2

PADAC

FE2_REFCLK

0x020C 0008

IO

Output Disabled

Pull Down

1

IO

2

RSVD

I

MSS_EPWM_TZ1

RSVD

3

4

RSVD

I

RSVD

5

RSVD

6

FE2_REFCLK

RSVD

7

8

RSVD

I

RSVD

9

RSVD

10

11

12

13

14

15

0

RSVD

DMM_MUX_IN

MSS_MIBSPIB_CS1

MSS_MIBSPIB_CS2

MSS_EPWMA_SYNCI

MSS_GPIO_19

MSS_MIBSPIA_MOSI

MSS_MCANA_RX

O

I

C1

PADAD

MSS_MCANB_RX

0x020C 000C

IO

Output Disabled

Pull Up

1

O

2

I

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

RSVD

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

RSVD

O

RSVD

DSS_UARTA_TX

MSS_MCANB_RX

MSS_I2CA_SCL

MSS_GPIO_20

MSS_MIBSPIA_MISO

MSS_MCANA_TX

RSVD

IO

B1

PADAE

MSS_MCANB_TX

0x020C 0010

IO

Output Disabled

Pull Up

I

O

RSVD

IO

RSVD

MSS_MCANB_TX

MSS_I2CA_SDA

MSS_GPIO_3

MSS_MIBSPIA_CLK

RCOSC_CLK

RSVD

IO

B2

PADAF

MSS_MCANA_RX

0x020C 0014

IO

Output Disabled

Pull Up

O

RSVD

IO

RSVD

MSS_MCANB_RX

DSS_UARTA_TX

RSVD

O

RSVD

I

MSS_MCANA_RX

MSS_GPIO_30

MSS_MIBSPIA_CS0

RCOSC_CLK

RSVD

A2

PADAG

MSS_MCANA_TX

0x020C 0018

IO

Output Disabled

Pull Up

O

RSVD

O

RSVD

MSS_MCANB_TX

RSVD

IO

RSVD

MSS_MCANA_TX

MSS_GPIO_21

MSS_MIBSPIB_MOSI

MSS_I2CA_SDA

MSS_EPWMA0

RSVD

C18

PADAH

MSS_MIBSPIB_MOSI

0x020C 001C

IO

Output Disabled

Pull Up

O

IO

O

RSVD

I

RSVD

MSS_MCANB_RX

MSS_GPIO_22

MSS_MIBSPIB_MISO

MSS_I2CA_SCL

MSS_EPWMB0

RSVD

C19

PADAI

MSS_MIBSPIB_MISO

0x020C 0020

IO

Output Disabled

Pull Up

I

IO

O

RSVD

O

RSVD

DSS_UARTA_TX

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

MSS_MCANB_TX

7

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

O

IO

D18

PADAJ

MSS_MIBSPIB_CLK

MSS_GPIO_5

MSS_MIBSPIB_CLK

MSS_UARTA_RX

MSS_EPWMC0

RSVD

0x020C 0024

Output Disabled

Pull Up

O

I

O

RSVD

O

RSVD

MSS_UARTB_TX

RSVD

I

MSS_MCANA_RX

MSS_GPIO_4

MSS_MIBSPIB_CS0

MSS_UARTA_TX

RSVD

D19

PADAK

MSS_MIBSPIB_CS0

0x020C 0028

IO

Output Disabled

Pull Up

O

RSVD

O

RSVD

MSS_UARTB_TX

RSVD

O

RSVD

MSS_MCANA_TX

MSS_GPIO_8

MSS_QSPI_D0

MSS_MIBSPIB_MISO

RSVD

C2

PADAL

MSS_QSPI_D0

0x020C 002C

IO

Output Disabled

Pull Down

IO

I

RSVD

IO

RSVD

D2

PADAM

MSS_QSPI_D1

MSS_GPIO_9

MSS_QSPI_D1

MSS_MIBSPIB_MOSI

RSVD

0x020C 0030

Output Disabled

Pull Down

IO

O

RSVD

O

RSVD

MSS_MIBSPIB_CS2

MSS_GPIO_10

MSS_QSPI_D2

RSVD

D1

PADAN

MSS_QSPI_D2

0x020C 0034

IO

Output Disabled

Pull Up

IO

RSVD

O

RSVD

MSS_MCANA_TX

MSS_GPIO_11

MSS_QSPI_D3

RSVD

E2

PADAO

MSS_QSPI_D3

0x020C 0038

IO

Output Disabled

Pull Up

IO

RSVD

14

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

MSS_MCANA_RX

8

0

1

2

3

4

5

6

0

1

2

0

I

IO

E1

PADAP

MSS_QSPI_CLK

MSS_GPIO_7

MSS_QSPI_CLK

MSS_MIBSPIB_CLK

RSVD

0x020C 003C

Output Disabled

Pull Down

O

RSVD

O

RSVD

DSS_UARTA_TX

MSS_GPIO_6

MSS_QSPI_CS

MSS_MIBSPIB_CS0

NERROR_IN

F2

PADAQ

MSS_QSPI_CS

0x020C 0040

IO

Output Disabled

Pull Up

O

Pull

Disabled

L3

K1

L1

C3

PADAR

PADAS

PADAT

PADAU

NERROR_IN

WARM_RESET

NERROR_OUT

TCK

0x020C 0044

0x020C 0048

0x020C 004C

0x020C 0050

I

Hi-Z (Open-Drain)

Output Disabled

WARM_RESET

NERROR_OUT

0

IO

O

Pull

Disabled

Pull

Disabled

MSS_GPIO_17

TCK

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

0

1

2

3

IO

I

Pull Down

MSS_UARTB_TX

RSVD

O

RSVD

O

RSVD

MSS_MCANA_TX

MSS_GPIO_18

TMS

D4

PADAV

TMS

0x020C 0054

IO

Output Disabled

Pull Up

I

RSVD

I

RSVD

MSS_MCANA_RX

MSS_GPIO_23

TDI

C5

PADAW

TDI

0x020C 0058

IO

Output Disabled

Pull Up

I

MSS_UARTA_RX

RSVD

I

RSVD

I

RSVD

DSS_UARTA_RX

MSS_GPIO_24

TDO

D6

PADAX

TDO

0x020C 005C

IO

Output Enabled

Pull

Disabled

O

MSS_UARTA_TX

RSVD

O

RSVD

O

RSVD

MSS_UARTB_TX

RSVD

I

RSVD

NDMM_EN

MSS_GPIO_25

MCU_CLKOUT

RSVD

E3

PADAY

MSS_EPWMA0

0x020C 0060

IO

Output Disabled

Pull Down

O

RSVD

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

RSVD

4

5

RSVD

IO

RSVD

6

RSVD

7

RSVD

8

RSVD

9

RSVD

10

11

12

13

14

15

0

RSVD

MSS_EPWMA0

RSVD

O

RSVD

OBS_CLKOUT

MSS_GPIO_26

MSS_GPIO_2

RSVD

H2

PADAZ

MSS_GPIO_2

0x020C 0064

IO

Output Disabled

Pull Down

1

IO

2

RSVD

O

RSVD

3

RSVD

4

RSVD

5

RSVD

6

MSS_UARTB_TX

RCSS_GPIO_34

RSVD

7

8

IO

9

RSVD

O

PMIC_CLKOUT

RSVD

10

11

12

13

14

0

RSVD

I

RSVD

MSS_EPWM_TZ0

MSS_GPIO_27

PMIC_CLKOUT

OBS_CLKOUT

RSVD

F1

PADBA

PMIC_CLKOUT

0x020C 0068

IO

Output Disabled

Pull Down

1

O

2

O

3

RSVD

O

RSVD

4

RSVD

5

RSVD

6

RSVD

7

RSVD

8

RSVD

9

RSVD

10

11

12

0

MSS_EPWMA1

MSS_EPWMB0

MSS_GPIO_28

SYNC_IN

RSVD

O

G3

PADBB

MSS_GPIO_28

0x020C 006C

IO

Output Disabled

Pull Down

1

I

2

RSVD

I

RCSS_MCASPB_AHCLKR

RSVD

3

4

RSVD

I

RSVD

5

MSS_UARTB_RX

DMM_MUX_IN

DSS_UARTA_RX

MSS_GPIO_29

RSVD

6

7

I

8

I

E17

PADBC

MSS_MIBSPIB_CS2

0x020C 0070

0

IO

Output Disabled

Pull Down

1

RSVD

I

RCOSC_CLK

RSVD

2

3

RSVD

4

16

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

RSVD

5

6

RSVD

7

RSVD

8

RSVD

DMM_MUX_IN

MSS_MIBSPIB_CS1

MSS_MIBSPIB_CS2

MSS_EPWMB0

MSS_EPWMB1

MSS_GPIO_15

MSS_RS232_RX

MSS_UARTA_RX

RSVD

9

I

10

11

12

13

0

O

G2

PADBD

MSS_RS232_RX

0x020C 0074

IO

Output Disabled

Pull Up

1

I

2

I

3

RSVD

4

RSVD

5

RSVD

6

RSVD

MSS_UARTB_RX

MSS_MCANA_RX

MSS_I2CA_SCL

MSS_EPWMB0

MSS_EPWMB1

MSS_EPWMC0

MSS_GPIO_14

MSS_RS232_TX

RSVD

7

I

8

I

9

IO

10

11

12

0

O

G1

PADBE

MSS_RS232_TX

0x020C 0078

IO

Output Enabled

Pull

Disabled

1

O

2

RSVD

3

RSVD

4

RSVD

MSS_UARTA_TX

MSS_UARTB_TX

RSVD

5

O

6

O

7

RSVD

8

RSVD

9

RSVD

MSS_MCANA_TX

MSS_I2CA_SDA

MSS_EPWMA0

MSS_EPWMA1

NDMM_EN

10

11

12

13

14

15

0

O

IO

O

I

MSS_EPWMB0

TRACE_DATA_0

MSS_GPIO_31

DMM0

O

V16

PADBF

TRACE_DATA_0

0x020C 007C

IO

Output Disabled

Pull Down

1

IO

2

I

RSVD

3

RSVD

MSS_UARTA_TX

RSVD

4

O

5

RSVD

6

RSVD

RCSS_MCASPC_DAT1

RSVD

7

IO

8

RSVD

9

RSVD

MSS_I2CA_SDA

TRACE_DATA_1

RCSS_GPIO_32

DMM1

10

0

IO

I

U15

PADBG

TRACE_DATA_1

0x020C 0080

Output Disabled

Pull Down

1

2

MSS_EPWMC_SYNCI

MSS_UARTA_RX

3

I

4

I

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

RSVD

5

6

7

8

9

10

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

RSVD

RCSS_MCASPC_DAT0

RSVD

IO

RSVD

MSS_I2CA_SCL

TRACE_DATA_2

RCSS_GPIO_33

DMM2

IO

W16

V15

W15

V14

U13

W14

PADBH

TRACE_DATA_2

0x020C 0084

0x020C 0088

0x020C 008C

0x020C 0090

0x020C 0094

0x020C 0098

IO

Output Disabled

Pull Down

IO

I

MSS_EPWMB_SYNCI

RSVD

I

RSVD

RCSS_MCASPC_FSR

TRACE_DATA_3

RCSS_GPIO_34

DMM3

IO

PADBI

PADBJ

PADBK

PADBL

PADBM

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

IO

I

RSVD

MSS_EPWMC_SYNCO

RSVD

O

RSVD

RCSS_MCASPC_ACLKR

TRACE_DATA_4

RCSS_GPIO_35

DMM4

I

IO

I

RSVD

MSS_EPWMB_SYNCO

RSVD

O

RSVD

RCSS_MCASPC_FSX

TRACE_DATA_5

RCSS_GPIO_36

DMM5

IO

I

RSVD

MSS_EPWM_TZ2

MSS_UARTB_TX

RSVD

I

O

RSVD

RCSS_MCASPC_ACLKX

TRACE_DATA_6

RCSS_GPIO_37

DMM6

IO

I

RSVD

MSS_EPWM_TZ1

RSVD

I

RSVD

O

RSVD

RCSS_MCASPC_AHCLKX

TRACE_DATA_7

RCSS_GPIO_38

DMM7

IO

I

RSVD

I

MSS_EPWM_TZ0

DSS_UARTA_TX

RSVD

O

RSVD

IO

RCSS_MCASPB_ACLKX

18

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

V13

W13

U11

V11

W11

V10

W10

PADBN

TRACE_DATA_8

0x020C 009C

0x020C 00A0

0x020C 00A4

0x020C 00A8

0x020C 00AC

0x020C 00B0

0x020C 00B4

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

IO

Output Disabled

Pull Down

RCSS_GPIO_39

DMM8

IO

I

RSVD

MSS_MCANA_TX

MSS_EPWMA_SYNCI

RSVD

O

I

RSVD

RCSS_MCASPB_FSX

TRACE_DATA_9

RCSS_GPIO_40

DMM9

IO

PADBO

PADBP

PADBQ

PADBR

PADBS

PADBT

TRACE_DATA_9

TRACE_DATA_10

TRACE_DATA_11

TRACE_DATA_12

TRACE_DATA_13

TRACE_DATA_14

IO

I

RSVD

MSS_MCANA_RX

MSS_EPWMA_SYNCO

RSVD

I

O

RSVD

RCSS_MCASPB_ACLKR

TRACE_DATA_10

RCSS_GPIO_41

DMM10

I

IO

I

RSVD

O

RSVD

MSS_EPWMC0

RSVD

IO

RSVD

RCSS_MCASPB_FSR

TRACE_DATA_11

RCSS_GPIO_42

DMM11

IO

I

RSVD

O

MSS_EPWMC1

RSVD

IO

RSVD

RCSS_MCASPB_DAT0

TRACE_DATA_12

RCSS_GPIO_43

DMM12

IO

I

RSVD

O

MSS_EPWMA0

MSS_MCANB_TX

RSVD

O

RSVD

IO

RCSS_MCASPB_DAT1

TRACE_DATA_13

RCSS_GPIO_44

DMM13

IO

I

RSVD

O

MSS_EPWMA1

MSS_MCANB_RX

RSVD

I

RSVD

IO

RCSS_MCASPB_DAT2

TRACE_DATA_14

RCSS_GPIO_45

DMM14

IO

I

RSVD

O

MSS_EPWMB0

RSVD

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

RSVD

6

7

0

1

2

3

4

5

6

7

8

9

10

11

0

1

2

3

4

5

6

7

8

9

10

11

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

RSVD

RCSS_MCASPB_DAT3

TRACE_DATA_15

RCSS_GPIO_46

DMM15

IO

T10

PADBU

TRACE_DATA_15

0x020C 00B8

0x020C 00BC

0x020C 00C0

IO

Output Disabled

Pull Down

IO

I

RSVD

MSS_EPWMB1

RSVD

O

RSVD

RCSS_MCASPB_DAT4

RSVD

IO

RSVD

RCSS_I2CA_SDA

TRACE_CLK

RCSS_GPIO_47

DMM_CLK

IO

W12

PADBV

TRACE_CLK

O

IO

I

HW_SYNC_FE1

HW_SYNC_FE2

RSVD

O

RSVD

RCSS_MCASPB_DAT5

RSVD

IO

RSVD

DSS_UARTA_RX

RCSS_I2CA_SCL

TRACE_CTL

RCSS_GPIO_48

DMM_SYNC

HW_SYNC_FE2

HW_SYNC_FE1

RSVD

I

IO

V12

PADBW

TRACE_CTL

IO

I

O

RSVD

RCSS_MCASPB_AHCLKX

RSVD

O

RSVD

DSS_UARTA_TX

RCSS_GPIO_49

MSS_MII_COL

MSS_RMII_REFCLK

RSVD

O

E19

F16

F18

PADBX

PADBY

PADBZ

RCSS_GPIO_49

MSS_I2CA_SDA

MSS_I2CA_SCL

0x020C 00C4

0x020C 00C8

0x020C 00CC

IO

Output Disabled

Pull Down

I

RSVD

RCSS_MCASPA_DAT3

RSVD

IO

RSVD

MSS_EPWMA1

RCSS_GPIO_50

MSS_MII_CRS

MSS_RMII_CRS_DV

MSS_I2CA_SDA

RCSS_MCASPA_DAT2

RSVD

O

IO

I

IO

RSVD

MSS_EPWMB1

RCSS_GPIO_51

MSS_MII_RXER

MSS_RMII_RXER

O

IO

I

20

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

MSS_I2CA_SCL

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

5

0

1

2

3

4

5

0

1

IO

RCSS_MCASPA_DAT1

RSVD

IO

RSVD

MSS_EPWMC1

RCSS_GPIO_52

MSS_MII_TXEN

MSS_RMII_TXEN

MSS_RGMII_TCTL

RCSS_MCASPA_DAT0

RSVD

O

J18

J17

K18

PADCA

MSS_RGMII_TCTL

MSS_RGMII_RCTL

MSS_RGMII_TD3

0x020C 00D0

0x020C 00D4

0x020C 00D8

IO

Output Disabled

Pull Down

O

IO

RSVD

MSS_EPWMA0

RCSS_GPIO_53

MSS_MII_RXDV

RSVD

O

PADCB

IO

I

RSVD

MSS_RGMII_RCTL

RCSS_MCASPA_FSR

MSS_UARTB_RX

MSS_EPWMB0

RCSS_GPIO_54

MSS_MII_TXD3

RSVD

O

IO

I

O

PADCC

IO

O

RSVD

O

MSS_RGMII_TD3

RCSS_MCASPA_ACLKR

MSS_UARTB_TX

MSS_EPWMC0

RCSS_GPIO_55

MSS_MII_TXD2

RSVD

I

O

K16

L17

L18

K19

PADCD

PADCE

PADCF

PADCG

MSS_RGMII_TD2

MSS_RGMII_TD1

MSS_RGMII_TD0

MSS_RGMII_TCLK

0x020C 00DC

0x020C 00E0

0x020C 00E4

0x020C 00E8

IO

O

Output Disabled

Pull Down

RSVD

O

MSS_RGMII_TD2

RCSS_MCASPA_FSX

RCSS_GPIO_56

MSS_MII_TXD1

MSS_RMII_TXD1

MSS_RGMII_TD1

RCSS_MCASPA_ACLKX

RCSS_GPIO_57

MSS_MII_TXD0

MSS_RMII_TXD0

MSS_RGMII_TD0

RCSS_MCASPA_AHCLKX

RCSS_GPIO_58

MSS_MII_TXCLK

RSVD

IO

O

IO

O

IO

O

RSVD

O

MSS_RGMII_TCLK

RCSS_MCASPB_AHCLKX

RCSS_I2CA_SDA

RCSS_GPIO_59

MSS_MII_RXCLK

RSVD

O

IO

I

M19

PADCH

MSS_RGMII_RCLK

0x020C 00EC

Output Disabled

Pull Down

RSVD

I

MSS_RGMII_RCLK

RCSS_MCASPB_AHCLKR

RCSS_I2CA_SCL

RCSS_GPIO_60

MSS_MII_RXD3

I

IO

I

L19

PADCI

MSS_RGMII_RD3

0x020C 00F0

Output Disabled

Pull Down

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

RSVD

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

RSVD

MSS_RGMII_RD3

RCSS_MCASPB_ACLKX

RCSS_I2CB_SDA

RCSS_GPIO_61

MSS_MII_RXD2

RSVD

I

IO

M18

PADCJ

MSS_RGMII_RD2

0x020C 00F4

IO

Output Disabled

Pull Down

I

RSVD

MSS_RGMII_RD2

RCSS_MCASPB_FSX

RCSS_I2CB_SCL

RCSS_GPIO_62

MSS_MII_RXD1

MSS_RMII_RXD1

MSS_RGMII_RD1

RCSS_MCASPB_ACLKR

RCSS_GPIO_63

MSS_MII_RXD0

MSS_RMII_RXD0

MSS_RGMII_RD0

RCSS_MCASPB_FSR

MSS_GPIO_30

MSS_MDIO_DATA

RSVD

I

IO

N19

P18

P19

R19

R18

PADCK

PADCL

PADCM

PADCN

PADCO

MSS_RGMII_RD1

MSS_RGMII_RD0

MSS_MDIO_DATA

MSS_MDIO_CLK

RCSS_MIBSPIA_MOSI

0x020C 00F8

0x020C 00FC

0x020C 0100

0x020C 0104

0x020C 0108

IO

Output Disabled

Pull Down

Pull Up

I

IO

I

IO

RSVD

IO

RSVD

RCSS_MCASPB_DAT0

MSS_GPIO_31

MSS_MDIO_CLK

RSVD

IO

Pull Up

IO

RSVD

IO

RSVD

RCSS_MCASPB_DAT1

RCSS_GPIO_32

RCSS_MIBSPIA_MOSI

RCSS_I2CA_SDA

RSVD

IO

Pull Up

O

IO

RSVD

O

RSVD

MSS_MIBSPIA_MOSI

RCSS_GPIO_33

RCSS_MIBSPIA_MISO

RCSS_I2CA_SCL

RSVD

R17

T18

T19

PADCP

PADCQ

PADCR

RCSS_MIBSPIA_MISO

RCSS_MIBSPIA_CLK

RCSS_MIBSPIA_CS0

0x020C 010C

0x020C 0110

0x020C 0114

IO

Output Disabled

Pull Up

I

IO

RSVD

I

RSVD

MSS_MIBSPIA_MISO

RCSS_GPIO_34

RCSS_MIBSPIA_CLK

RCSS_I2CB_SDA

RSVD

IO

RSVD

O

RSVD

MSS_MIBSPIA_CLK

RCSS_GPIO_35

RCSS_MIBSPIA_CS0

RCSS_I2CB_SCL

RSVD

IO

RSVD

O

RSVD

MSS_MIBSPIA_CS0

22

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

U18

PADCS

RCSS_MIBSPIA_HOSTIRQ

RCSS_GPIO_36

0x020C 0118

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

0

1

2

IO

O

Output Disabled

Pull Down

RCSS_MIBSPIA_CS1

MSS_GPIO_2

IO

MSS_GPIO_8

IO

RSVD

I

MSS_MIBSPIA_HOSTIRQ

MSS_MIBSPIB_CS2

RCSS_GPIO_34

RSVD

O

IO

RSVD

IO

RSVD

RCSS_GPIO_40

RCSS_GPIO_37

RCSS_MIBSPIB_MOSI

RCSS_I2CA_SDA

MSS_CPTS0_HW1TSPUSH

RSVD

U19

V18

V19

U17

W18

PADCT

PADCU

PADCV

PADCW

PADCX

RCSS_MIBSPIB_MOSI

RCSS_MIBSPIB_MISO

RCSS_MIBSPIB_CLK

RCSS_MIBSPIB_CS0

RCSS_MIBSPIB_HOSTIRQ

0x020C 011C

0x020C 0120

0x020C 0124

0x020C 0128

0x020C 012C

IO

Output Disabled

Pull Up

Pull Down

O

IO

I

RSVD

O

MSS_MIBSPIB_MOSI

RCSS_GPIO_38

RCSS_MIBSPIB_MISO

RCSS_I2CA_SCL

MSS_CPTS0_HW2TSPUSH

RSVD

IO

I

IO

I

RSVD

I

MSS_MIBSPIB_MISO

RCSS_GPIO_39

RCSS_MIBSPIB_CLK

RCSS_I2CB_SDA

MSS_CPTS0_TS_SYNC

RSVD

IO

O

IO

O

RSVD

O

MSS_MIBSPIB_CLK

RCSS_GPIO_40

RCSS_MIBSPIB_CS0

RCSS_I2CB_SCL

MSS_CPTS0_TS_COMP

RCSS_MCASPC_DAT5

MSS_MIBSPIB_CS0

RCSS_GPIO_41

RCSS_MIBSPIB_CS1

RSVD

IO

O

IO

O

IO

O

RSVD

O

MSS_CPTS0_TS_GENF

RCSS_MCASPC_DAT4

MSS_MIBSPIB_CS1

MSS_GPIO_3

IO

O

IO

MSS_GPIO_9

IO

RSVD

IO

RSVD

RCSS_GPIO_35

RCSS_GPIO_43

MSS_CPTS0_TS_COMP

HW_SYNC_FE1

HW_SYNC_FE2

RCSS_MCASPC_DAT2

RCSS_GPIO_43

MSS_CPTS0_TS_COMP

HW_SYNC_FE1

V17

PADCY

PADCZ

HW_SYNC_FE1

HW_SYNC_FE2

0x020C 0130

IO

Output Disabled

Pull Down

O

IO

W17

0x020C 0134

IO

Output Disabled

Pull Down

O

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

HW_SYNC_FE2

3

4

0

1

2

4

5

6

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

0

1

2

3

4

5

6

7

8

9

10

O

IO

RCSS_MCASPC_DAT2

RCSS_GPIO_44

MSS_CPTS0_TS_SYNC

RSVD

U3

PADDA

MSS_UARTA_RX

MSS_UARTA_TX

DSS_UARTA_TX

DSS_UARTA_RX

MSS_UARTB_TX

0x020C 0138

0x020C 013C

0x020C 0140

0x020C 0144

0x020C 0148

IO

Output Disabled

Pull Up

O

RSVD

O

RSVD

MSS_UARTB_TX

MSS_UARTA_RX

DSS_UARTA_TX

RCSS_GPIO_45

MSS_CPTS0_HW2TSPUSH

RSVD

I

O

W2

J19

H19

V9

PADDB

PADDC

PADDD

PADDE

IO

RSVD

MSS_UARTB_RX

MSS_UARTA_TX

DSS_UARTA_RX

RCSS_GPIO_46

MSS_CPTS0_HW1TSPUSH

RSVD

I

O

I

IO

I

RSVD

IO

RSVD

DSS_UARTA_TX

RCSS_UARTA_RX

MSS_UARTA_RX

RCSS_GPIO_47

DSS_UARTA_RX

RSVD

I

IO

RSVD

O

RSVD

RCSS_UARTA_TX

MSS_UARTA_TX

MSS_GPIO_0

DSS_UARTA_TX

RSVD

O

IO

O

RSVD

I

MSS_EPWMB_SYNCI

FE1_REFCLK

MSS_UARTA_TX

MSS_UARTB_TX

RSVD

I

O

RSVD

IO

RSVD

RCSS_GPIO_32

MSS_GPIO_1

XREF_CLK0

RSVD

J1

PADDF

XREF_CLK0

0x020C 014C

IO

Output Disabled

Pull Down

I

RSVD

I

RSVD

FE2_REFCLK

RSVD

O

MCU_CLKOUT

RSVD

24

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

RSVD

11

12

0

RSVD

IO

RCSS_GPIO_33

MSS_GPIO_2

XREF_CLK1

K2

PADDG

XREF_CLK1

0x020C 0150

0x020C 0154

0x020C 0158

0x020C 015C

IO

Output Disabled

Pull Down

Pull Up

1

I

RSVD

2

RSVD

O

RCSS_ECAPA_CAPIN_PWMO

RSVD

3

RSVD

O

4

RSVD

5

RSVD

6

PMIC_CLKOUT

RSVD

7

8

RSVD

IO

RSVD

9

RSVD

10

11

12

0

RSVD

RCSS_GPIO_34

MSS_GPIO_3

OBS_CLKOUT

RCSS_ATL_CLK0

RSVD

H18

G17

G19

PADDH

PADDI

PADDJ

MSS_MIBSPIA_MOSI

MSS_MIBSPIA_MISO

MSS_MIBSPIA_CLK

IO

1

O

2

I

3

RSVD

IO

RCSS_I2CB_SDA

MSS_EPWMA1

RSVD

4

5

O

6

RSVD

O

RSVD

7

RSVD

8

RCSS_UARTA_RTS

MSS_MIBSPIA_MOSI

RSVD

9

10

11

12

0

O

RSVD

IO

RCSS_GPIO_35

MSS_GPIO_4

HW_SYNC_FE1

MSS_CPTS0_TS_GENF

RCSS_ATL_CLK1

RCSS_I2CB_SCL

MSS_EPWMB1

MSS_EPWMB0

HW_SYNC_FE2

OBS_CLKOUT

RCSS_UARTA_CTS

MSS_MIBSPIA_MISO

RSVD

IO

1

O

2

O

3

I

4

O

5

O

6

O

7

O

8

O

9

I

10

11

12

0

IO

RSVD

IO

RCSS_GPIO_36

MSS_GPIO_5

HW_SYNC_FE2

MSS_CPTS0_TS_COMP

MSS_EPWMB1

RCSS_ECAPA_CAPIN_PWMO

RCSS_I2CA_SDA

MSS_UARTB_TX

HW_SYNC_FE1

RSVD

IO

1

O

2

O

3

O

4

O

IO

5

6

O

7

O

8

RSVD

O

RSVD

9

MSS_MIBSPIA_CLK

RSVD

10

11

12

RSVD

IO

RCSS_GPIO_37

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

F19

PADDK

MSS_MIBSPIA_CS0

MSS_MIBSPIA_HOSTIRQ

MSS_GPIO_8

MSS_GPIO_6

0x020C 0160

0x020C 0164

0x020C 0168

0x020C 016C

0x020C 0170

0

1

IO

Output Disabled

Pull Up

MSS_EPWMA_SYNCI

RSVD

I

2

RSVD

HW_SYNC_FE1

MSS_EPWMA0

RCSS_I2CA_SCL

MSS_UARTB_RX

MSS_CPTS0_TS_GENF

RSVD

3

O

4

O

5

O

6

I

7

O

8

RSVD

HW_SYNC_FE2

MSS_MIBSPIA_CS0

RSVD

9

O

10

11

12

0

O

RSVD

RCSS_GPIO_38

MSS_GPIO_7

IO

G18

PADDL

PADDM

PADDN

PADDO

IO

Pull Down

MSS_EPWMA_SYNCO

MSS_EPWMC1

HW_SYNC_FE2

MSS_EPWMB0

RCSS_I2CB_SDA

MSS_UARTA_RX

MSS_CPTS0_TS_COMP

RCSS_ECAPA_SYNCIN

HW_SYNC_FE1

MSS_MIBSPIA_HOSTIRQ

RSVD

1

O

2

O

3

O

4

O

5

IO

6

I

7

O

8

I

9

O

10

11

12

0

I

RSVD

RCSS_GPIO_39

MSS_GPIO_8

IO

B3

IO

FE1_REFCLK

1

I

MSS_EPWMA_SYNCO

MSS_EPWMB_SYNCI

MSS_EPWMC0

RCSS_I2CB_SCL

MSS_UARTA_TX

MSS_CPTS0_TS_SYNC

RCSS_ECAPA_SYNCOUT

RSVD

2

O

3

I

4

O

5

O

6

7

O

8

O

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_40

MSS_GPIO_9

B19

MSS_GPIO_9

IO

FE2_REFCLK

1

O

RCSS_UARTA_TX

MSS_EPWMB_SYNCO

MSS_EPWMA1

RSVD

2

O

3

O

4

O

5

RSVD

O

DSS_UARTA_TX

MSS_CPTS0_HW2TSPUSH

RCSS_MCASPA_AHCLKX

RSVD

6

7

I

8

O

9

RSVD

I

RSVD

10

11

12

0

RCSS_ATL_CLK0

RCSS_GPIO_41

MSS_GPIO_10

RSVD

IO

B18

MSS_GPIO_10

IO

1

RSVD

26

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

RCSS_UARTA_RX

2

3

I

MSS_EPWMC_SYNCI

MSS_EPWMB1

RSVD

I

4

O

5

RSVD

DSS_UARTA_RX

MSS_CPTS0_HW1TSPUSH

RCSS_MCASPA_ACLKX

RSVD

6

I

7

I

IO

8

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_42

MSS_GPIO_11

RSVD

C17

A18

B17

A17

PADDP

MSS_GPIO_11

0x020C 0174

0x020C 0178

0x020C 017C

0x020C 0180

IO

Output Disabled

Pull Down

Pull Up

1

RSVD

O

RCSS_UARTA_RTS

MSS_EPWMC_SYNCO

MSS_EPWMC1

MSS_I2CA_SDA

MSS_UARTB_TX

RSVD

2

4

O

5

O

6

IO

7

O

8

RSVD

IO

RCSS_MCASPA_FSX

RSVD

9

10

11

12

13

0

RSVD

IO

RSVD

RCSS_GPIO_43

MSS_GPIO_12

MSS_I2CA_SCL

RCSS_UARTA_CTS

HW_SYNC_FE1

RCSS_ECAPA_CAPIN_PWMO

MSS_CPTS0_TS_GENF

MSS_UARTB_RX

RCSS_ECAPA_CAPIN_PWMO

RCSS_MCASPA_ACLKR

RSVD

PADDQ

PADDR

PADDS

MSS_GPIO_12

MSS_GPIO_13

RCSS_UARTA_TX

IO

1

O

2

I

3

O

4

O

5

O

6

I

7

O

8

I

9

RSVD

I

RSVD

10

11

12

0

MSS_RS232_RX

RCSS_GPIO_44

MSS_GPIO_13

MSS_I2CA_SDA

MSS_CPTS0_TS_COMP

HW_SYNC_FE2

RCSS_UARTA_TX

MSS_UARTA_TX

MSS_UARTB_TX

DSS_UARTA_TX

RCSS_MCASPA_FSR

RSVD

IO

1

IO

2

O

3

O

4

O

5

O

6

O

7

O

8

IO

9

RSVD

O

RSVD

10

11

12

0

MSS_RS232_TX

RCSS_GPIO_45

MSS_GPIO_14

RSVD

IO

1

RSVD

O

RCSS_UARTA_TX

RCSS_I2CB_SDA

2

3

IO

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

RESET

STATE[8]

BALL

PAD

BALL

PINCNTL

MUX

PULL

SIGNAL NAME[4] [10]

TYPE[7]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

TYPE[9]

RSVD

4

5

RSVD

IO

RSVD

6

RCSS_MCASPA_DAT8

RCSS_MCASPA_DAT0

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_46

MSS_GPIO_15

RSVD

B16

C15

A16

B15

PADDT

RCSS_UARTA_RX

NERRORIN_FE1

NERRORIN_FE2

NRESET_FE1

0x020C 0184

0x020C 0188

0x020C 018C

0x020C 0190

IO

Output Disabled

Pull Up

1

RSVD

I

RCSS_UARTA_RX

RCSS_I2CB_SCL

RSVD

2

3

O

4

RSVD

IO

RSVD

5

RSVD

6

RCSS_MCASPA_DAT9

RCSS_MCASPA_DAT1

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_47

MSS_GPIO_16

RSVD

PADDU

PADDV

PADDW

IO

Pull Down

1

RSVD

IO

RSVD

2

RSVD

3

RSVD

4

RSVD

5

RSVD

6

RCSS_MCASPA_DAT10

RCSS_MCASPA_DAT2

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_48

MSS_GPIO_17

RSVD

IO

1

RSVD

IO

RSVD

2

RSVD

3

RSVD

4

RSVD

5

RSVD

6

RCSS_MCASPA_DAT11

RCSS_MCASPA_DAT3

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_49

MSS_GPIO_18

RSVD

IO

1

RSVD

2

RSVD

3

RSVD

4

RSVD

5

28

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Table 6-1. Pin Attributes (ZCE285A Package) (continued)

BALL

PULL

BALL

PAD

BALL

PINCNTL

MUX

SIGNAL NAME[4] [10]

TYPE[7]

RESET

TYPE[9]

STATE[8]

NUMBER[1]

NAME[2]

NAME[3]

ADDRESS[5]

MODE[6] [10]

RSVD

6

7

RSVD

IO

RCSS_MCASPA_DAT12

RCSS_MCASPA_DAT4

RSVD

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_50

MSS_GPIO_19

RSVD

A15

B14

C13

PADDX

NRESET_FE2

0x020C 0194

0x020C 0198

0x020C 019C

IO

Output Disabled

Pull Down

1

RSVD

IO

RSVD

2

RCSS_I2CA_SDA

RSVD

3

4

RSVD

IO

RSVD

5

RSVD

6

RCSS_MCASPA_DAT13

RCSS_MCASPA_DAT5

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_51

MSS_GPIO_20

RSVD

PADDY

NWARMRESET_IN_FE1

IO

1

RSVD

IO

RSVD

2

RCSS_I2CA_SCL

RSVD

3

4

RSVD

IO

RSVD

5

RSVD

6

RCSS_MCASPA_DAT14

RCSS_MCASPA_DAT6

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

0

RSVD

RCSS_GPIO_52

MSS_GPIO_21

RSVD

PADDZ

NWARMRESET_IN_FE2

IO

1

RSVD

O

RSVD

2

RSVD

3

RCSS_ECAPA_CAPIN_PWMO

RSVD

4

5

RSVD

IO

RSVD

6

RCSS_MCASPA_DAT15

RCSS_MCASPA_DAT7

RSVD

7

8

IO

9

RSVD

IO

RSVD

10

11

12

RSVD

RCSS_GPIO_53

The MSS_IOMUX registers contol the individual pin states and MUX mapping described in Table 6-1. The

following Table 6-2 provides a reference for these registers and power on reset values. For more information on

programming the MSS_IOMUX registers, see the device-specific TRM.

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Table 6-2. PAD IO Configuration Registers (MSS_IOMUX)

Register Width

(Bits)

Register

Reset

Address

Offset

Physical

Address

Register Name

Type

PADAA_CFG_REG

PADAB_CFG_REG

PADAC_CFG_REG

PADAD_CFG_REG

PADAE_CFG_REG

PADAF_CFG_REG

PADAG_CFG_REG

PADAH_CFG_REG

PADAI_CFG_REG

PADAJ_CFG_REG

PADAK_CFG_REG

PADAL_CFG_REG

PADAM_CFG_REG

PADAN_CFG_REG

PADAO_CFG_REG

PADAP_CFG_REG

PADAQ_CFG_REG

PADAR_CFG_REG

PADAS_CFG_REG

PADAT_CFG_REG

PADAU_CFG_REG

PADAV_CFG_REG

PADAW_CFG_REG

PADAX_CFG_REG

PADAY_CFG_REG

PADAZ_CFG_REG

PADBA_CFG_REG

PADBB_CFG_REG

PADBC_CFG_REG

PADBD_CFG_REG

PADBE_CFG_REG

PADBF_CFG_REG

PADBG_CFG_REG

PADBH_CFG_REG

PADBI_CFG_REG

PADBJ_CFG_REG

PADBK_CFG_REG

PADBL_CFG_REG

PADBM_CFG_REG

PADBN_CFG_REG

PADBO_CFG_REG

PADBP_CFG_REG

PADBQ_CFG_REG

PADBR_CFG_REG

PADBS_CFG_REG

RW

32

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 02C1

0x0000 0100

0x0000 00C1

0x0000 02C1

0x0000 0101

0x0000 00C1

0x0000 02C1

0x0000 0301

0x0000 00C1

0x0000 0000

0x0000 0004

0x0000 0008

0x0000 000C

0x0000 0010

0x0000 0014

0x0000 0018

0x0000 001C

0x0000 0020

0x0000 0024

0x0000 0028

0x0000 002C

0x0000 0030

0x0000 0034

0x0000 0038

0x0000 003C

0x0000 0040

0x0000 0044

0x0000 0048

0x0000 004C

0x0000 0050

0x0000 0054

0x0000 0058

0x0000 005C

0x0000 0060

0x0000 0064

0x0000 0068

0x0000 006C

0x0000 0070

0x0000 0074

0x0000 0078

0x0000 007C

0x0000 0080

0x0000 0084

0x0000 0088

0x0000 008C

0x0000 0090

0x0000 0094

0x0000 0098

0x0000 009C

0x0000 00A0

0x0000 00A4

0x0000 00A8

0x0000 00AC

0x0000 00B0

0x020C 0000

0x020C 0004

0x020C 0008

0x020C 000C

0x020C 0010

0x020C 0014

0x020C 0018

0x020C 001C

0x020C 0020

0x020C 0024

0x020C 0028

0x020C 002C

0x020C 0030

0x020C 0034

0x020C 0038

0x020C 003C

0x020C 0040

0x020C 0044

0x020C 0048

0x020C 004C

0x020C 0050

0x020C 0054

0x020C 0058

0x020C 005C

0x020C 0060

0x020C 0064

0x020C 0068

0x020C 006C

0x020C 0070

0x020C 0074

0x020C 0078

0x020C 007C

0x020C 0080

0x020C 0084

0x020C 0088

0x020C 008C

0x020C 0090

0x020C 0094

0x020C 0098

0x020C 009C

0x020C 00A0

0x020C 00A4

0x020C 00A8

0x020C 00AC

0x020C 00B0

30

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Table 6-2. PAD IO Configuration Registers (MSS_IOMUX) (continued)

Register Width

(Bits)

Register

Reset

Address

Offset

Physical

Address

Register Name

Type

PADBT_CFG_REG

PADBU_CFG_REG

PADBV_CFG_REG

PADBW_CFG_REG

PADBX_CFG_REG

PADBY_CFG_REG

PADBZ_CFG_REG

PADCA_CFG_REG

PADCB_CFG_REG

PADCC_CFG_REG

PADCD_CFG_REG

PADCE_CFG_REG

PADCF_CFG_REG

PADCG_CFG_REG

PADCH_CFG_REG

PADCI_CFG_REG

PADCJ_CFG_REG

PADCK_CFG_REG

PADCL_CFG_REG

PADCM_CFG_REG

PADCN_CFG_REG

PADCO_CFG_REG

PADCP_CFG_REG

PADCQ_CFG_REG

PADCR_CFG_REG

PADCS_CFG_REG

PADCT_CFG_REG

PADCU_CFG_REG

PADCV_CFG_REG

PADCW_CFG_REG

PADCX_CFG_REG

PADCY_CFG_REG

PADCZ_CFG_REG

PADDA_CFG_REG

PADDB_CFG_REG

PADDC_CFG_REG

PADDD_CFG_REG

PADDE_CFG_REG

PADDF_CFG_REG

PADDG_CFG_REG

PADDH_CFG_REG

PADDI_CFG_REG

PADDJ_CFG_REG

PADDK_CFG_REG

PADDL_CFG_REG

RW

32

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 00B4

0x0000 00B8

0x0000 00BC

0x0000 00C0

0x0000 00C4

0x0000 00C8

0x0000 00CC

0x0000 00D0

0x0000 00D4

0x0000 00D8

0x0000 00DC

0x0000 00E0

0x0000 00E4

0x0000 00E8

0x0000 00EC

0x0000 00F0

0x0000 00F4

0x0000 00F8

0x0000 00FC

0x0000 0100

0x0000 0104

0x0000 0108

0x0000 010C

0x0000 0110

0x0000 0114

0x0000 0118

0x0000 011C

0x0000 0120

0x0000 0124

0x0000 0128

0x0000 012C

0x0000 0130

0x0000 0134

0x0000 0138

0x0000 013C

0x0000 0140

0x0000 0144

0x0000 0148

0x0000 014C

0x0000 0150

0x0000 0154

0x0000 0158

0x0000 015C

0x0000 0160

0x0000 0164

0x020C 00B4

0x020C 00B8

0x020C 00BC

0x020C 00C0

0x020C 00C4

0x020C 00C8

0x020C 00CC

0x020C 00D0

0x020C 00D4

0x020C 00D8

0x020C 00DC

0x020C 00E0

0x020C 00E4

0x020C 00E8

0x020C 00EC

0x020C 00F0

0x020C 00F4

0x020C 00F8

0x020C 00FC

0x020C 0100

0x020C 0104

0x020C 0108

0x020C 010C

0x020C 0110

0x020C 0114

0x020C 0118

0x020C 011C

0x020C 0120

0x020C 0124

0x020C 0128

0x020C 012C

0x020C 0130

0x020C 0134

0x020C 0138

0x020C 013C

0x020C 0140

0x020C 0144

0x020C 0148

0x020C 014C

0x020C 0150

0x020C 0154

0x020C 0158

0x020C 015C

0x020C 0160

0x020C 0164

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Table 6-2. PAD IO Configuration Registers (MSS_IOMUX) (continued)

Register Width

(Bits)

Register

Reset

Address

Offset

Physical

Address

Register Name

Type

PADDM_CFG_REG

PADDN_CFG_REG

PADDO_CFG_REG

PADDP_CFG_REG

PADDQ_CFG_REG

PADDR_CFG_REG

PADDS_CFG_REG

PADDT_CFG_REG

PADDU_CFG_REG

PADDV_CFG_REG

PADDW_CFG_REG

PADDX_CFG_REG

PADDY_CFG_REG

PADDZ_CFG_REG

RW

32

0x0000 00C1

0x0000 02C1

0x0000 00C1

0x0000 0168

0x0000 016C

0x0000 0170

0x0000 0174

0x0000 0178

0x0000 017C

0x0000 0180

0x0000 0184

0x0000 0188

0x0000 018C

0x0000 0190

0x0000 0194

0x0000 0198

0x0000 019C

0x020C 0168

0x020C 016C

0x020C 0170

0x020C 0174

0x020C 0178

0x020C 017C

0x020C 0180

0x020C 0184

0x020C 0188

0x020C 018C

0x020C 0190

0x020C 0194

0x020C 0198

0x020C 019C

32

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6.3 Signal Descriptions

Note

All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are

non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply

being present to the device

Note

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low, a tri-state buffer should

be used to isolate the GPIO output from any attached device. An additional pull resister should be

used to define the required state in the application. The NRESET signal could be used to control the

output enable (OE) of the tri-state buffer.

Table 6-3. Signal Descriptions

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

ADC Input Channel 1

ADC Interface

Clocking

R2

P2

R1

P1

M2

T2

N2

N1

M1

U1

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

CLKM

I

–

ADC Input

Clock Input

–

ADC Input Channel 2

ADC Input Channel 3

ADC Input Channel 4

ADC Input Channel 5

ADC Input Channel 6

ADC Input Channel 7

ADC Input Channel 8

ADC Input Channel 9

Primary crystal or oscillator input

clock negative polarity.

I

Clocking

V1

CLKP

–

Clock Input

Primary crystal or oscillator input

clock positive polarity.

I

Clocking

T4

J1

OSC_CLK_OUT_AUDIO

XREF_CLK0

O

–

Clock Output Oscillator output reference clock

LVCMOS

Optional external reference input

clock 0. Can be used as dedicated

peripheral clock source for system

synchronization. See TRM for

details.

IO

Clocking

K2

XREF_CLK1

–

LVCMOS

Optional external reference input

clock 1. Can be used as dedicated

peripheral clock source for system

synchronization. See TRM for

details.

Clocking

F1

B6

PMIC_CLKOUT

CSI2_RX0CLKM

IO

I

–

LVCMOS

PMIC output reference clock

CSI2.0 Interface

MIPI D-PHY

CSI2.0 Receiver #1, Clock Input

Negative Polarity

CSI2.0 Interface

A6

A8

A7

B5

CSI2_RX0CLKP

CSI2_RX0M0

CSI2_RX0M1

CSI2_RX0M2

–

MIPI D-PHY

CSI2.0 Receiver #1, Clock Input

Positive Polarity

I

CSI2.0 Receiver #1, Negative

Polarity Lane 0

CSI2.0 Receiver #1, Negative

Polarity Lane 1

CSI2.0 Receiver #1, Negative

Polarity Lane 2

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

CSI2.0 Interface

Debug Trace

TYPE

DESCRIPTION

B4

CSI2_RX0M3

–

MIPI D-PHY

CSI2.0 Receiver #1, Negative

Polarity Lane 3

I

B8

B7

CSI2_RX0P0

CSI2_RX0P1

CSI2_RX0P2

CSI2_RX0P3

CSI2_RX1CLKM

CSI2_RX1CLKP

CSI2_RX1M0

CSI2_RX1M1

CSI2_RX1M2

CSI2_RX1M3

CSI2_RX1P0

CSI2_RX1P1

CSI2_RX1P2

CSI2_RX1P3

TRACE_CLK

TRACE_CTL

–

CSI2.0 Receiver #1, Positive Polarity

Lane 0

I

CSI2.0 Receiver #1, Positive Polarity

Lane 1

I

A5

CSI2.0 Receiver #1, Positive Polarity

Lane 2

I

A4

CSI2.0 Receiver #1, Positive Polarity

Lane 3

I

A11

B11

A13

B12

A10

A9

CSI2.0 Receiver #2, Clock Input

Negative Polarity

I

CSI2.0 Receiver #2, Clock Input

Positive Polarity

I

CSI2.0 Receiver #2, Negative

Polarity Lane 0

I

CSI2.0 Receiver #2, Negative

Polarity Lane 1

I

CSI2.0 Receiver #2, Negative

Polarity Lane 2

I

CSI2.0 Receiver #2, Negative

Polarity Lane 3

B13

A12

B10

B9

CSI2.0 Receiver #2, Positive Polarity

Lane 0

I

CSI2.0 Receiver #2, Positive Polarity

Lane 1

I

CSI2.0 Receiver #2, Positive Polarity

Lane 2

I

CSI2.0 Receiver #2, Positive Polarity

Lane 3

I

W12

V12

Pull Down LVCMOS

ARM/DSP Trace Debug Interface

Clock

IO

Debug Trace

ARM/DSP Trace Debug Interface

Control

Debug Trace

V16

U15

U11

V11

W11

V10

W10

T10

W16

V15

W15

V14

U13

W14

V13

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_10

TRACE_DATA_11

TRACE_DATA_12

TRACE_DATA_13

TRACE_DATA_14

TRACE_DATA_15

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

TRACE_DATA_8

IO

Pull Down LVCMOS

ARM/DSP Trace Debug Interface I/O

34

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

Debug Trace

DSS UART A

Error Interface

W13

H19

J19

L3

TRACE_DATA_9

DSS_UARTA_RX

DSS_UARTA_TX

NERROR_IN

IO

Pull Down LVCMOS

ARM/DSP Trace Debug Interface I/O

DSS UART A Receiver

Pull Up

LVCMOS

DSS UART A Receiver

Pull

Disabled

LVCMOS,

Open-Drain,

Failsafe

Error Interface Input

I

Error Interface

L1

NERROR_OUT

Pull

Disabled

LVCMOS,

Open-Drain,

Failsafe

Error Interface Output

O

Ground

W1

A1

C7

V2

A3

E5

T6

P6

F6

R7

P7

N7

M7

L7

VSS

–

Power

Ground Return

K7

J7

H7

G7

F7

E7

R8

P8

N8

M8

L8

K8

J8

H8

G8

F8

E8

D8

W9

N9

M9

L9

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

Ground

TYPE

DESCRIPTION

Ground Return

K9

J9

VSS

–

Power

Ground

–

Power

Ground Return

H9

G9

N10

M10

L10

K10

J10

H10

G10

D10

N11

M11

L11

K11

J11

H11

G11

R12

P12

N12

M12

L12

K12

J12

H12

G12

F12

E12

D12

R13

P13

N13

M13

L13

K13

J13

H13

G13

F13

E13

P14

F14

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

Ground

JTAG

A14

R15

T16

D16

W19

A19

C3

VSS

TCK

TDI

–

Power

Ground Return

–

Power

Ground Return

–

Ground Return

–

Ground Return

–

Ground Return

–

Ground Return

IO

Pull Down LVCMOS

JTAG Test Clock

JTAG Test Data Input

JTAG Test Data Output

JTAG

C5

Pull Up

LVCMOS

JTAG

D6

TDO

Pull

Disabled

IO

O

JTAG

D4

TMS

Pull Up

–

LVCMOS

LVDS

JTAG Test Data Mode Select

LVDS Interface

W7

LVDS_CLKM

LVDS_CLKP

LVDS_FRCLKM

LVDS_FRCLKP

LVDS_TXM0

LVDS_TXM1

LVDS_TXM2

LVDS_TXM3

LVDS_TXP0

LVDS_TXP1

LVDS_TXP2

LVDS_TXP3

LVDS/Aurora Transmitter, Clock,

Negative Polarity

LVDS Interface

V7

W8

V8

–

LVDS

LVDS/Aurora Transmitter, Clock,

Positive Polarity

O

LVDS/Aurora Transmitter, Frame

Clock, Negative Polarity

LVDS/Aurora Transmitter, Frame

Clock, Positive Polarity

V6

LVDS/Aurora Transmitter, Data

Output, Negative Polarity, Lane 0

V5

LVDS/Aurora Transmitter, Data

Output, Negative Polarity, Lane 1

V4

LVDS/Aurora Transmitter, Data

Output, Negative Polarity, Lane 2

V3

LVDS/Aurora Transmitter, Data

Output, Negative Polarity, Lane 3

W6

W5

W4

W3

LVDS/Aurora Transmitter, Data

Output, Positive Polarity, Lane 0

LVDS/Aurora Transmitter, Data

Output, Positive Polarity, Lane 1

LVDS/Aurora Transmitter, Data

Output, Positive Polarity, Lane 2

LVDS/Aurora Transmitter, Data

Output, Positive Polarity, Lane 3

MSS CAN A

MSS CAN B

MSS EPWM

MSS Ethernet

B2

A2

MSS_MCANA_RX

MSS_MCANA_TX

MSS_MCANB_RX

MSS_MCANB_TX

MSS_EPWMA0

IO

Pull Up

LVCMOS

MSS CAN Channel A, Receiver

MSS CAN Channel A, Transmitter

MSS CAN Channel B, Receiver

MSS CAN Channel B, Transmitter

MSS Enhanced PWM A, Channel 0

C1

B1

E3

Pull Down LVCMOS

R19

MSS_MDIO_CLK

Pull Up

LVCMOS

MSS Ethernet Manage Data Input/

Output Clock

IO

MSS Ethernet

P19

M19

P18

N19

MSS_MDIO_DATA

MSS_RGMII_RCLK

MSS_RGMII_RD0

MSS_RGMII_RD1

Pull Up

LVCMOS

MSS Ethernet Manage Data Input/

Output Data

Pull Down LVCMOS

MSS Ethernet RGMII/GMII/MII

Receive Clock

MSS Ethernet RGMII/GMII/MII

Receive Data 0

MSS Ethernet RGMII/GMII/MII

Receive Data 1

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

MSS Ethernet

TYPE

DESCRIPTION

M18

MSS_RGMII_RD2

MSS_RGMII_RD3

MSS_RGMII_TCLK

MSS_RGMII_TD0

MSS_RGMII_TD1

MSS_RGMII_TD2

MSS_RGMII_TD3

MSS_RGMII_RCTL

MSS_RGMII_TCTL

Pull Down LVCMOS

MSS Ethernet RGMII/GMII/MII

Receive Data 2

IO

L19

K19

L18

L17

K16

K18

J17

J18

MSS Ethernet RGMII/GMII/MII

Receive Data 3

MSS Ethernet RGMII/GMII/MII

Transmit Clock

MSS Ethernet RGMII/GMII/MII

Transmit Data 0

MSS Ethernet RGMII/GMII/MII

Transmit Data 1

MSS Ethernet RGMII/GMII/MII

Transmit Data 2

MSS Ethernet RGMII/GMII/MII

Transmit Data 3

MSS Ethernet RGMII/GMII/MII

Transmit Data 3

MSS Ethernet RGMII/GMII/MII

Transmit Data 3

MSS GPIO

MSS I2CA

MSS SPI A

B18

C17

A18

B17

H2

MSS_GPIO_10

MSS_GPIO_11

MSS_GPIO_12

MSS_GPIO_13

MSS_GPIO_2

IO

Pull Down LVCMOS

MSS GPIO

G3

MSS_GPIO_28

MSS_GPIO_8

MSS GPIO

B3

MSS GPIO

B19

F16

F18

G19

F19

G18

MSS_GPIO_9

MSS GPIO

MSS_I2CA_SDA

MSS_I2CA_SCL

MSS_MIBSPIA_CLK

MSS_MIBSPIA_CS0

12C A, Data

I2C A, Clock

Pull Up

LVCMOS

MSS SPI A, Clock Output

MSS SPI A, Chip-Select Output

MSS SPI A ,Host Interrupt Input

MSS_MIBSPIA_HOSTIR

Q

Pull Down LVCMOS

IO

MSS SPI A

G17

H18

MSS_MIBSPIA_MISO

Pull Up

LVCMOS

MSS SPI A, Host Master Input, Slave

Output

MSS_MIBSPIA_MOSI

MSS SPI A, Host Master Output,

Slave Input

MSS SPI B

D18

D19

E18

E17

C19

MSS_MIBSPIB_CLK

MSS_MIBSPIB_CS0

MSS_MIBSPIB_CS1

MSS_MIBSPIB_CS2

MSS_MIBSPIB_MISO

IO

Pull Up

LVCMOS

MSS SPI B, Clock Output

MSS SPI B, Chip-Select 0 Output

MSS SPI B, Chip-Select 1 Output

MSS SPI B, Chip-Select 2Output

Pull Down LVCMOS

Pull Up

LVCMOS

MSS SPI B, Host Master Input, Slave

Output

IO

MSS SPI B

C18

MSS_MIBSPIB_MOSI

Pull Up

LVCMOS

MSS SPI B, Host Master Output,

Slave Input

MSS UART A

MSS UART B

U3

W2

V9

MSS_UARTA_RX

MSS_UARTA_TX

MSS_UARTB_TX

VDD

IO

Pull Up

–

LVCMOS

Power

MSS UART A, Receive

MSS UART A, Transmit

MSS UART B, Transmit

1.2V Core Digital Power

Power, 1.2V

Core Digital

N5

–

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

Power, 1.2V

Core Digital

L5

J5

VDD

–

Power

1.2V Core Digital Power

–

Power, 1.2V

Core Digital

–

Power

1.2V Core Digital Power

1.2V SRAM Digital Power

Power, 1.2V

Core Digital

G5

Power, 1.2V

Core Digital

N6

Power, 1.2V

Core Digital

L6

Power, 1.2V

Core Digital

J6

Power, 1.2V

Core Digital

G6

Power, 1.2V

Core Digital

R9

Power, 1.2V

Core Digital

P9

Power, 1.2V

Core Digital

F9

Power, 1.2V

Core Digital

E9

Power, 1.2V

Core Digital

R11

P11

F11

E11

N14

L14

J14

G14

N15

L15

J15

G15

N17

J3

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

VDD_SRAM1

VDD_SRAM2

VDD_SRAM3

Power, 1.2V

Core Digital

Power, 1.2V

Core Digital

T8

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

1.2V N-well bias

Power, 1.2V

Core Digital

N18

VNWA

–

Power

–

Power, 1.8V

ADC

R3

U2

VIOIN_18ADC

VIOIN_18CLK

–

Power

1.8V ADC Power

1.8V Clock Power

Power, 1.8V

Clocking

Power, 1.8V I/O

M4

H4

VIOIN_18

VIOIN_18LVDS

–

Power

1.8V Digital I/O Power

1.8V LVDS I/O Power

T14

E15

M16

U5

Power, 1.8V I/O

LVDS

–

Power, 1.8V I/O

LVDS

U7

C9

VIOIN_18LVDS

VIOIN_18CSI

VIOIN

–

Power

1.8V LVDS I/O Power

1.8V CSI2 I/O Power

Power, 1.8V I/O

MIPI D-PHY

Power, 1.8V I/O

MIPI D-PHY

C11

K4

Power, 1.8V/3.3V

I/O

1.8V/3.3V Digital I/O Power

Bandgap Output

Power, 1.8V/3.3V

I/O

F4

VIOIN

Power, 1.8V/3.3V

I/O

R5

VIOIN

Power, 1.8V/3.3V

I/O

T12

D14

P16

H16

T1

VIOIN

Power, 1.8V/3.3V

I/O

VIOIN

Power, 1.8V/3.3V

I/O

VIOIN

Power, 1.8V/3.3V

I/O

VIOIN

Power, Bandgap

Output

VBGAP

Power, E-fuse

MSS QSPI

MSS UART

U9

E1

F2

C1

D2

D1

E2

G1

VPP

–

E-fuse Programming Voltage

MSS QSPI Clock Output

MSS_QSPI_CLK

MSS_QSPI_CS

MSS_QSPI_D0

MSS_QSPI_D1

MSS_QSPI_D2

MSS_QSPI_D3

MSS_RS232_TX

IO

Pull Down LVCMOS

Pull Up

LVCMOS

MSS QSPI Chip-Select Output

MSS QSPI Data Input/Output 0

MSS QSPI Data Input/Output 1

MSS QSPI Data Input/Output 2

MSS QSPI Data Input/Output 3

MSS Debug UART - Transmit Signal

Pull Down LVCMOS

Pull Up

LVCMOS

Pull

Disabled

IO

MSS UART

G2

H1

MSS_RS232_RX

FE1_REFCLK

Pull Up

LVCMOS

MSS Debug UART - Receive Signal

Radar Front-End

Pull Down Clocking

Radar Front-End 1, Reference Clock

Input

Radar Front-End

J2

FE2_REFCLK

Pull Down Clocking

Radar Front-End 2, Reference Clock

Input

IO

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Table 6-3. Signal Descriptions (continued)

DEFAULT

PULL

STATUS

BALL

NUMBER

SIGNAL

NAME

BUFFER

TYPE

FUNCTION

TYPE

DESCRIPTION

Radar Front-End

V17

W17

C15

A16

B15

A15

B14

C13

HW_SYNC_FE1

Pull Down Clocking

Radar Front-End 1, Frame Sync

Output

IO

HW_SYNC_FE2

Radar Front-End 2, Frame Sync

Output

NERRORIN_FE1

NERRORIN_FE2

NRESET_FE1

Pull Down LVCMOS,

Open-Drain

Radar Front-End 1, Error Input

Pull Down LVCMOS,

Open-Drain

Radar Front-End 2, Error Input

Pull Down LVCMOS

Radar Front-End 1, Power-on-Reset

Output

NRESET_FE2

Radar Front-End 2, Power-on-Reset

Output

NWARMRESET_IN_FE1

NWARMRESET_IN_FE2

Radar Front-End 1, Warm-Reset

Output

Radar Front-End 2, Warm-Reset

Output

RCSS GPIO

RCSS SPI A

E19

T18

T19

RCSS_GPIO_49

IO

General-purpose I/O

RCSS_MIBSPIA_CLK

RCSS_MIBSPIA_CS0

Pull Up

LVCMOS

Radar Control SPI A, Clock Output

Radar Control SPI A, Chip-Select

Output

IO

RCSS SPI A

U18

R17

R18

RCSS_MIBSPIA_HOSTI

RQ

Pull Down LVCMOS

Radar Control SPI A, Host Interrupt

Input

RCSS_MIBSPIA_MISO

Pull Up

LVCMOS

Radar Control SPI A, Master Input,

Slave Output

RCSS_MIBSPIA_MOSI

Radar Control SPI A, Master Output,

Slave Input

IO

RCSS SPI B

V19

U17

RCSS_MIBSPIB_CLK

RCSS_MIBSPIB_CS0

Pull Up

LVCMOS

Radar Control SPI B, Clock Output

Radar Control SPI B, Chip-Select

Output

RCSS SPI B

W18

V18

U19

RCSS_MIBSPIB_HOSTI

RQ

Pull Down LVCMOS

Radar Control SPI B, Host Interrupt

Input

IO

RCSS_MIBSPIB_MISO

Pull Up

LVCMOS

Radar Control SPI B, Master Input,

Slave Output

RCSS_MIBSPIB_MOSI

Radar Control SPI B, Master Output,

Slave Input

RCSS UART A

Reset

A17

B16

L2

RCSS_UARTA_TX

RCSS_UARTA_RX

NRESET

IO

Pull Up

–

LVCMOS

Radar Control UART A, Transmitter

Radar Control UART A, Receiver

AM273x Power-on-Reset Input

LVCMOS,

Open-Drain,

Failsafe

I

Reset

K1

WARM_RESET

Pull

Disabled

LVCMOS,

Open-Drain

AM273x Warm-Reset Input

IO

Reserved

P4

N3

Reserved1

Reserved2

–

Reserved. Short to VSS on PCB.

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7 Specifications

7.1 Absolute Maximum Ratings

PARAMETER/PIN^{(1) (2)}

DESCRIPTION

1.2V digital power supply

1.2V power rail for internal SRAM

MIN

-0.5

MAX

1.4

UNIT

VDD

V

VIN_SRAM

VNWA

1.4

1.2V power rail for SRAM array back bias

1.4

I/O Supply (3.3V or 1.8V): All LVCMOS1833 I/O would

operate on this supply

VIOIN

-0.5

3.8

V

VIOIN_18

1.8V supply for CMOS I/O

-0.5

2

V

VIN_18CLK

VIOIN_18DIFF

1.8V supply for clock module

1.8V supply for CSI2 and LVDS ports

Dual-voltage LVCMOS inputs, operated at 3.3V or 1.8V

(Steady State)

-0.3V to VIOIN +0.3V

V

Input Voltage

Dual-voltage LVCMOS inputs, operated at 3.3V/1.8V

(Transient Overshoot/Undershoot)

VIOIN +20% up to 20% of

Signal Period

CLKP/CLKN

-0.5

-20

-40

-55

2

20

V

Clamp Current

Limit clamp current⁽³⁾

mA

Automotive

Operating junction temperature range

Industrial

140

105

150

T_J

°C

T_stg

Storage temperature range after soldered onto PC Board

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal GND.

(3) Specifies clamp current that will flow through the internal diode protection cells of the I/O in an overvoltage or undervoltage condition.

7.2 ESD Ratings

VALUE

±1500

±500

UNIT

ESD stress voltage HBM, per AEC Q100-002⁽¹⁾All pins

All pins

Electrostatic

discharge

V_(ESD)

V

ESD stress voltage CDM, per AEC Q100-011

Corner Pins

±750

(A1, A19, W1, W19)

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Power-On Hours (POH)

JUNCTION

OPERATING

CONDITION

TEMPERATURE (T_j)

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

(1)

–40°C

75°C

1200 (6%)

4000 (20%)

13000 (65%)

1600 (8%)

200 (1%)

95°C

100% duty cycle

1.2

130°C

140°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

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7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME

Power Supply Conditions

VDD

DESCRIPTION

MIN

NOM

MAX

UNIT

1.2-V digital power supply

1.14

1.2

1.32

V

VIN-SRAM

1.2-V power rail for internal SRAM

VNWA

1.2-V power rail for SRAM array back bias

I/O Supply (3.3-V mode): ALL LVCMOS1833 I/O

would operate on this supply

VIOIN

3.135

1.71

3.3

1.8

3.465

1.89

V

I/O Supply (1.8-V mode): ALL LVCMOS1833 I/O

would operate on this supply

VIOIN_18

1.8V supply for LVCMOS1833 I/O

1.8V supply for clock module

1.8V supply for ADC module

1.8V supply for CSI-2 D-PHY buffers

1.8V supply for LVDS buffers

1.7V supply for e-Fuse array

1.71

1.65

1.8

1.7

1.9

V

VIN_18CLK

VIN_18ADC

VIN_18CSI

VIOIN_18LVDS

VPP

1.9

1.75

I/O Conditions

LVCMOS18/33 (1.8V mode) Voltage Input High

LVCMOS18/33 (3.3V mode) Voltage Input High

1.71

2.25

V

LVCMOS V_IH

LVCMOS V_IL

0.3 ×

VIOIN

LVCMOS18/33 (1.8V mode) Voltage Input Low

LVCMOS18/33 (3.3V mode) Voltage Input Low

V

0.8 ×

VIOIN

LVCMOS18/33 (1.8 and 3.3V mode) Voltage Output

High (I_OH= 6 ma)

LVCMOS V_OH

LVCMOS V_OL

VIOIN - 0.450

LVCMOS18/33 (1.8V and 3.3V mode) Voltage Output

Low(I_OL= 6 ma)

0.45

NRESET, SOP[4:0], (1.8V mode) Voltage Input High

NRESET, SOP[4:0], (3.3V mode) Voltage Input High

NRESET, SOP[4:0], (1.8V mode) Voltage Input Low

NRESET, SOP[4:0], (3.3V mode) Voltage Input Low

Voltage Output High

0.96

1.57

V

NRESET, SOP[4:0] V_IH

NRESET, SOP[4:0] V_IL

0.2

0.3

1.5

LVDS TX V_OH

LVDS TX V_OL

Voltage Output Low

0.9

(1)

CSI2 RX V_IH

Voltage Input High - LP Mode

0.74

(1)

CSI2 RX V_IL

Voltage Input Low - LP Mode

0.55

0.46

(1)

CSI2 RX V_IH

Voltage Input High - HS Mode

(1)

CSI2 RX V_IL

Voltage Input Low - HS Mode

-0.04

Voltage Output High

1.4

OSC_CLKOUT

Voltage Output Low

VSS

(1) CSI2 receivers compatible with MIPI D-PHY standard version 2.1.

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7.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each

Operating Performance Point (OPP) for processor clocks and device core clocks.

Note

The OPP voltage and frequency values may change following the silicon characterization result.

Table 7-1 describes the maximum supported frequency per speed grade for the device.

Table 7-1. Device Speed and Memory Grade

RAM

(MB)

DSP

(MHz)

R5FSS

(MHz)

DEVICE

GRADE

AM2732-Q1, AM2732

D

3.625

450

400

7.6 Power Supply Specifications

Table 7-2 describes the four power rails provided from an external power supply and how they map to major

sub-systems and power nets of the AM273x device.

Table 7-2. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT INPUT POWER NETS ON THE DEVICE

Input: VIN18CLK, VIN_18ADC, VIOIN_18DIFF,

APLL, crystal oscillator, ADC, CSI2, LVDS

1.8 V

VIOIN_18LVDS, VIOIN_18CSI

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/O

Input: VIOIN

Input: VDD, VIN_SRAM1, VIN_SRAM2, VIN_SRAM3,

VNWA

1.2 V

Core Digital and SRAMs

7.7 I/O Buffer Type and Voltage Rail Dependency

Table 7-3. Buffer Type

BUFFER TYPE

(STANDARD)

DESCRIPTION

VOLTAGE RAIL

PERIPHERALS

VIOIN, VIOIN_18

Resets, QSPI, UART, SPI, I²C,

CAN-FD, GPIO, RGMII, MDIO,

ePWM, eCAP, JTAG, Trace,

SOP, Safety, DMM

LVCMOS

Dual voltage 1.8V/3.3V LVCMOS I/O buffer

General Purpose ADC Input

GPADC

VIN_18ADC

VIN_18CLK

GPADC

Clock subsystem crystal or 1.8V single-

ended input buffer

CLKP/CLKM

Clock Subsystem

Analog, low-jitter output from clock

subsystem

VIN_18CLK

OSC_CLKOUT

Aurora LVDS

CSI2

Clock Subsystem Output

LVDS TX

LVDS high-speed data, differential output

buffer

VIOIN_18DIFF

MIPI D-PHY CSI2.0 high-speed data,

differential input buffer

CSI2.0 RX

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7.8 CPU Specifications

Table 7-4. CPU and Hardware Accelerator Specifications

PARAMETER

MIN

NOM

MAX UNIT

Dual-Core Cortex-R5F, ARMv7 ⁽²⁾

L1 Program Memory Cache

L1 Data Memory Chache

L1 Tightly Coupled Memory⁽³⁾(TCM) with

32-bit ECC

16

64

kB

Main Subsystem

(MSS)

L2 Memory

960

kB

Single Core C66x DSP

Clock Speed

450

32

MHz

kB

DSP Subsystem

(DSS)

L1 Program Memory

L1 Data Memory

L2 Memory⁽¹⁾

32

kB

384

3625

kB

Shared Memory

Shared L3 Memory ⁽⁴⁾

2000

kB

(1) C66x L2 memory includes up to 256kB configuration as RAM or cache

(2) R5F dual-cores configuration as single, redundant, lock-step device, or two independent cores

(3) L1 64kB tightly coupled memory shared between lock-step devices, or 32kB L1 for each core when operating in dual-core mode.

(4) Sharable across R5F, C66x, and HWA subsystems

7.9 Thermal Resistance Characteristics for nFBGA Package [ZCE285A]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

6.2

RΘ_JC

RΘ_JB

RΘ_JA

Psi_JT

Psi_JB

Junction-to-case

Junction-to-board

5.7

Junction-to-free air

Junction-to-package top

Junction-to-board

17.3

1.0

5.6

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on

a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

7.10 Power Consumption Summary

Table Table 7-5 summarizes average power consumption of the AM273x device for a set of typical application

utilization and thermal parameters. Table Table 7-6 shows hypothetical peak current for the device. Both of these

tables can be used to scale power regulator and PCB design. However, specific power utilization of the device

is dependent on the software utilization of device cores, accelerators and peripherals and operating temperature.

To facilitate accurate power planning, TI provides a power estimation tool (PET) spreadsheet which can be

used for estimating device power utilization across a wide number of scenarios. Please see sprad10 for more

information.

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Table 7-5. Average Power and Current

SUPPLY

DESCRIPTION

AVERAGE

POWER (mW)

AVERAGE

CURRENT (mA)

PARAMETER

SUPPLY NAME

VDD

1.2V Core

Digital Power

692

3

576

VDD_SRAM

VIOIN

1.2V SRAM

Power

3

4

Average Power and Current Consumption for Typical Control and

Processing Use-Case:

1.8V or 3.3V

Digital I/O

Power

•

C66x DSP: 450 MHz, 50% Utilization

R5F Dual Core: 400 MHz, 70% Utilization

CSI2-A/B: 4-Lane, 600 Mbps Operation

SPI: 10% Utilization

12

VIOIN_18

1.8V Digital I/O

Power

0

Ethernet: 100Mbps Operation, 70% Utilization

CAN: 8Mbps Operation, 10% Utilization

SPI: 25 Mbps Operation, 10% Utilization

T_J= 25 C

VIOIN_18CLK 1.8V Clocking

Power

32

18

VIOIN_18ADC 1.8V ADC

Power

3

2

VIOIN_18CSI

1.8V CSI Power

40

22

69

VIOIN_18LVDS 1.8V LVDS

Power

125

907

Total Power

Table 7-6. Peak Current

SUPPLY NAME

VDD

SUPPLY DESCRIPTION

PEAK CURRENT (mA)

1.2V Core Digital Power

1.2V SRAM Power

2315

75

74

1

VDD_SRAM

VIOIN

1.8V or 3.3V Digital I/O Power

1.8V Digital I/O Power

1.8V Clocking Power

1.8V ADC Power

VIOIN_18

VIOIN_18CLK

VIOIN_18ADC

VIOIN_18CSI

VIOIN_18LVDS

18

2

1.8V CSI Power

23

70

1.8V LVDS Power

7.11 Timing and Switching Characteristics

7.11.1 Power Supply Sequencing and Reset Timing

The AM273x device expects all external voltage rails and SOP boot mode select lines to be stable before reset

is deasserted. Figure 7-1 describes the device wake-up sequence.

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Figure 7-1. Device Wake-up Sequence

7.11.2 Clock Specifications

An external crystal is connected to the device pins. Figure 7-2 shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

Figure 7-2. Crystal Implementation

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Note

The load capacitors, C_f1and C_f2in Figure 7-2, should be chosen such that Equation 1 is satisfied.

C_Lin the equation is the load specified by the crystal manufacturer. All discrete components used

to implement the oscillator circuit should be placed as close as possible to the associated oscillator

CLKP and CLKM pins. Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

Table 7-7 lists the electrical characteristics of the clock crystal.

Table 7-7. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

40

8

MAX

UNIT

MHz

pF

f_P

Parallel resonance crystal frequency

C_L

Crystal load capacitance

Crystal ESR

5

12

50

ESR

Ω

Temperature range Expected temperature range of operation

–40

150

°C

Frequency

Crystal frequency tolerance^{(1) (2) (3)}

tolerance

-200

200

ppm

µW

Drive level

50

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

(3) Crystal tolerance affects sensor accuracy if AM273x used as clock source for attached sensors.

A non-crystal oscillator can also be used as the clock reference source. In this case the signal is fed to the CLKP

pin only and CLKM is grounded. Table 7-8 lists the electrical, AC timing, and phase noise requirements of the

external oscillator input signal.

Table 7-8. External Clock Mode Input Requirements

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

40

MHz

mV (pp)

V

AC-Amplitude

700

0.00

1.40

1200

0.02

1.95

10

DC-V_IL

DC-V_IH

V

Input Clock:

DC-t_rise/fall

ns

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise referrenced to 40 MHz

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

–132

–143

–152

–153

65

dBc/Hz

%

35

Freq Tolerance

–50

50

ppm

7.11.3 Peripheral Information

Initial peripheral descriptions and features are provided in the following sections. Additional peripheral details

and interface timing information shall be provided in a later product preview or datasheet release.

7.11.3.1 QSPI Flash Memory Peripheral

AM273x includes a Quad-Serial Peripheral Interface for external flash memory access. Flash memory can be

be utilized for many purposes including: Secondary boot-loader memory, application program memory, security

keys storage, and long-term data logs for security and error conditions.

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•

ROM bootloader auto identification of supported flash through flash device ID (DEVID) register

Loopback skew cancellation for clock signal to supported faster flash interface clock rates

Two chip-select signals to connect two external flash devices

Memory mapped 'direct' mode and software triggered 'indirect' mode of operation for performing flash data

transfers

•

67 MHz operating clock supported

7.11.3.1.1 QSPI Timing Conditions

SPECIFIC

ATION

PARAMETER

MIN

TYP

MAX

UNIT

NUMBER

Input Conditions

1

2

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

3

2

15

pF

7.11.3.1.2 QSPI Timing Requirements

(2) (3)

PARAMETER⁽¹⁾

MIN

TYP

MAX

UNIT

,

SPECIFIC

ATION

NUMBER

Q12

Q13

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

Setup time, D[3:0] valid before falling SCLK edge

Hold time, D[3:0] valid after falling SCLK edge

5

0

ns

Setup time, final D[3:0] bit valid before final falling

SCLK edge

Q14

Q15

5-P

t_h(SCLK-D)

Hold time, final D[3:0] bit valid after final falling SCLK

edge

ns

0+P

(1) Clock Mode 0 (clock polarity = 0 ; clockk phase = 0 ) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although

nonstandard, The falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(3) P = SCLK period in ns.

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7.11.3.1.3 QSPI Switching Characteristics

(2)

PARAMETER⁽¹⁾

MIN

TYP

MAX

,

SPECIFIC

ATION

NUMBER

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

t_c(SCLK)

Cycle time, sclk

14.9

0.5*P – 1.5

–M*P – 1

N*P – 1

–3

ns

t_w(SCLKL)

Pulse duration, sclk low

Pulse duration, sclk high

t_w(SCLKH)

t_d(CS-SCLK)

t_d(SCLK-CS)

t_d(SCLK-D0)

t_ena(CS-D0LZ)

t_dis(CS-D0Z)

t_d(SCLK-D0)

Delay time, sclk falling edge to cs active edge

Delay time, sclk falling edge to cs inactive edge

Delay time, sclk falling edge to d[0] transition

Enable time, cs active edge to d[0] driven (lo-z)

Disable time, cs active edge to d[0] tri-stated (hi-z)

–M*P + 2.5

N*P + 2.5

5.2

–P – 4

–P +3.5

–P – 4

Delay time, sclk first falling edge to first d[0] transition

(for PHA = 0 only)

Q9

–3– P

3.5 – P

(1) P = SCLK period in ns.

(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

Figure 7-3. QSPI Read (Clock Mode 0)

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PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q8

Q6

Q7

Q9

Q6

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

Figure 7-4. QSPI Write (Clock Mode 0)

7.11.3.2 MIBSPI Peripheral

AM273x includes four, Multi-Buffered Serial Peripheral Interface (MIBSPI) master interfaces. Two of these

interfaces are intended for external MCU, PMIC, EEPROM, Watchdog, and other system-level communication.

The other two interfaces are intended for independently mastering SPI device sensors.

•

Maximum clock rate supported over each MIBSPI module is 25 MHz.

7.11.3.2.1 SPI Timing Conditions

NO.

PARAMETER

MIN

TYP

MAX UNIT

Input Conditions

1

2

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

3

Output load capacitance

2

15

pF

7.11.3.2.2 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

The following tables and figures present timing requirements and switching characteristics for SPI – Master

Mode.

Table 7-9. SPI Master Mode Switching Characteristics (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)⁽¹⁾⁽³⁾

see Figure 7-5 and Figure 7-6

NO.

PARAMETER

Cycle time, SPICLK⁽²⁾

MIN

40

TYP

MAX UNIT

1

t_c(SPC)M

256_tc(VCLK)

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M+ 4

2

3

ns

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Table 7-9. SPI Master Mode Switching Characteristics (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)⁽¹⁾⁽³⁾(continued)

see Figure 7-5 and Figure 7-6

NO.

PARAMETER

MIN

TYP

MAX UNIT

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M– 13

SIMO)M

4

5

ns

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M– 13

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

ns

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

CSHOLD = 0

(C2TDELAY+2)*

t_c(VCLK)– 7.5

(C2TDELAY+2)

Setup time CS active until SPICLK

high

* t_c(VCLK)+ 7

(clock polarity = 0)⁽⁵⁾

CSHOLD = 1

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

6

t_C2TDELAY

ns

CSHOLD = 0

(C2TDELAY+2)*

t_c(VCLK)– 7.5

(C2TDELAY+2)

* t_c(VCLK)+ 7

Setup time CS active until SPICLK low

(clock polarity = 1)⁽⁵⁾

CSHOLD = 1

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

Hold time, SPICLK low until CS inactive (clock polarity =

0)⁽⁵⁾

0.5*t_c(SPC)M

(T2CDELAY +

1) *t_c(VCLK)– 7

+

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

7.5

+

7

t_T2CDELAY

ns

Hold time, SPICLK high until CS inactive (clock polarity =

1)⁽⁵⁾

0.5*t_c(SPC)M

(T2CDELAY +

1) *t_c(VCLK)– 7

+

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

+

7.5

Table 7-10. SPI Master Mode Timing Requirements (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)⁽¹⁾⁽³⁾

see Figure 7-5

NO.

PARAMETER

MIN

TYP

MAX UNIT

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)⁽⁴⁾

5

SPCL)M

8

9

ns

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)⁽⁴⁾

5

3

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)⁽⁴⁾

SOMI)M

ns

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)⁽⁴⁾

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

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11

SPICLK

(clock polarity = 0)

2

1

3

SPICLK

(clock polarity = 1

4

5

Master Out Data Is Valid

SPISIMO

1

8

9

Master In Data

Must Be Valid

SPISOMI

Figure 7-5. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

6

7

Figure 7-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

7.11.3.2.3 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO =

output, and SPISOMI = input)

Table 7-11. SPI Master Mode Switching Characteristics (CLOCK PHASE = 1, SPICLK = output, SPISIMO =

output, and SPISOMI = input)⁽¹⁾⁽³⁾

see Figure 7-5 and Figure 7-8

NO.

PARAMETER

Cycle time, SPICLK⁽²⁾

MIN

40

TYP

MAX UNIT

1

t_c(SPC)M

256t_c(VCLK)

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M+ 4

2

3

ns

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock polarity

= 0)

0.5t_c(SPC)M

–

13

SIMO)M

4

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

13

SIMO)M

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Table 7-11. SPI Master Mode Switching Characteristics (CLOCK PHASE = 1, SPICLK = output, SPISIMO =

output, and SPISOMI = input)⁽¹⁾⁽³⁾(continued)

see Figure 7-5 and Figure 7-8

NO.

PARAMETER

MIN

TYP

MAX UNIT

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

5

ns

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

t_C2TDELAY

Setup time CS active until SPICLK

high

CSHOLD = 0

0.5*t_c(SPC)M

(C2TDELAY +

2)*t_c(VCLK)

+

0.5*t_c(SPC)M

+

(C2TDELAY+2

) * t_c(VCLK)+ 7

(clock polarity = 0)⁽⁵⁾

–

7.5

CSHOLD = 1

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M+

(C2TDELAY +

(C2TDELAY+2

) * t_c(VCLK)+ 7

2)*t_c(VCLK)

–

6

ns

7.5

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

+

(C2TDELAY+2

)*t_c(VCLK)– 7.5

0.5*t_c(SPC)M+

(C2TDELAY+2

) * t_c(VCLK)+ 7

Setup time CS active until SPICLK

low

(clock polarity = 1)⁽⁵⁾

0.5*t_c(SPC)M

(C2TDELAY+3

)*t_c(VCLK)– 7.5

+

0.5*t_c(SPC)M+

(C2TDELAY+3

) * t_c(VCLK)+ 7

Hold time, SPICLK low until CS inactive (clock polarity = 0)⁽⁵⁾

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

7

t_T2CDELAY

ns

Hold time, SPICLK high until CS inactive (clock polarity = 1)⁽⁵⁾(T2CDELAY +

1) *t_c(VCLK)

7.5

(T2CDELAY +

1) *t_c(VCLK)+ 7

–

Table 7-12. SPI Master Mode Timing Requirements (CLOCK PHASE = , SPICLK = output, SPISIMO =

output, and SPISOMI = input)⁽¹⁾⁽³⁾

see Figure 7-5 and Figure 7-8

NO.

PARAMETER

MIN

TYP

MAX UNIT

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)⁽⁴⁾

5

SPCL)M

8

ns

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)⁽⁴⁾

5

3

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)⁽⁴⁾

SOMI)M

9

ns

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)⁽⁴⁾

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

8

9

Master In Data

Must Be Valid

SPISOMI

Figure 7-7. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

6

7

Figure 7-8. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

7.11.3.2.4 SPI Slave Mode Timing and Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI =

output)

Table 7-13. SPI Slave Mode Timing Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)

(1)(2)

see Figure 7-9 and Figure 7-10

NO.

PARAMETER

Cycle time, SPICLK ⁽²⁾

MIN

25

TYP

MAX

UNIT

1

t_c(SPC)S

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

10

2

3

ns

10

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)⁽³⁾

11

4

ns

t_{d(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)⁽³⁾

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Table 7-13. SPI Slave Mode Timing Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)

⁽¹⁾⁽²⁾(continued)

see Figure 7-9 and Figure 7-10

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_{h(SPCH-SOMI)S}

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)⁽³⁾

2

5

ns

t_{h(SPCL-SOMI)S}

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)⁽³⁾

2

Table 7-14. SPI Slave Mode Switching Characteristics (SPICLK = input, SPISIMO = input, and SPISOMI =

output)⁽¹⁾⁽²⁾

see Figure 7-9 and Figure 7-10

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity =

1; clock phase = 1)⁽⁴⁾

t_{su(SIMO-SPCL)S}

4.5

6

ns

Setup time, SPISIMO before SPICLK high (clock

t_{su(SIMO-SPCH)S}polarity = 1; clock phase = 0) OR (clock polarity =

4.5

1

0; clock phase = 1)⁽⁴⁾

Hold time, SPISIMO data valid after SPICLK low

t_{h(SPCL-SIMO)S}

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)⁽⁴⁾

7

ns

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)⁽⁴⁾

t_{h(SPCL-SIMO)S}

1

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_{c(MSS_VCLK)}, where PS = prescale value set in SPIFMTx.

[15:8].

(3) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns, where

PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥ 25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 7-9. SPI Slave Mode External Timing (CLOCK PHASE = 0)

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 7-10. SPI Slave Mode External Timing (CLOCK PHASE = 1)

7.11.3.3 Ethernet Switch (RGMII/RMII/MII) Peripheral

AM273x integrates a two port Ethernet switch with one external RGMII/RMII/MII port and another port servicing

the Master Sub-System (MSS). This interface is intended to operate primarily as a 100Mbps ECU interface. It

can also be used as an instrumentation interface.

•

Full Duplex 10/100Mbps wire rate interface to Ethernet PHY over RGMII, RMII, or MII parallel interface

MDIO Clause 22 and 45 PHY management interface

IEEE 1588 Synchronous Ethernet support

Synchronous trigger output allowing Ethernet to trigger CSI data frames

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7.11.3.3.1 RGMII/GMII/MII Timing Conditions

SPECIFIC

ATION

PARAMETER

MIN

TYP

MAX

NUMBER

Input Conditions

1

2

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

3

2

20

pF

7.11.3.3.2 RGMII Transmit Clock Switching Characteristics

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

MAX

440

44

UNIT

ns

1

t_c(TXC)

Cycle time, rgmiin_txc

360

36

ns

2

3

4

t_w(TXCH)

t_w(TXCL)

t_t(TXC)

Pulse duration, rgmiin_txc high

Pulse duration, rgmiin_txc low

Transition time, rgmiin_txc

160

16

240

24

ns

160

16

240

24

ns

0.75

ns

7.11.3.3.3 RGMII Transmit Data and Control Switching Characteristics

NO.⁽¹⁾PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

5

t_osu(TXD-TXC)

Output Setup time, transmit selected signals valid to

MSS_RGMII_TCLK high/low

RGMII, Internal Delay

Enabled, 10/100 Mbps

1.2

ns

6

t_oh(TXC-TXD)

Output Hold time, transmit selected signals valid

after MSS_RGMII_TCLK high/low

RGMII, Internal Delay

Enabled, 10/100 Mbps

1.2

ns

(1) For RGMII, transmit selected signals include: MSS_RGMII_TXD[3:0] and MSS_RGMII_TCTL.

1

4

2

4

3

rgmiin_txc^(A)

[internal delay enabled]

5

rgmiin_txd[3:0]^(B)

rgmiin_txctl^(B)

1st Half-byte

TXEN

2nd Half-byte

TXERR

6

A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.

B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the rising edge of

rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on rising edge of rgmiin_txc and

TXERR of falling edge of rgmiin_txc.

Figure 7-11. RGMII Transmit Interface Switching Characteristics

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7.11.3.3.4 RGMII Recieve Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

360

36

MAX

440

44

UNIT

ns

1

t_c(RXC)

Cycle time, rgmiin_rxc

ns

2

3

4

t_w(RXCH)

t_w(RXCL)

t_t(RXC)

Pulse duration, rgmiin_rxc high

Pulse duration, rgmiin_rxc low

Transition time, rgmiin_rxc

160

16

240

24

ns

160

16

240

24

ns

0.75

ns

7.11.3.3.5 RGMII Recieve Data and Control Timing Requirements

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

5

t_su(RXD-RXCH)

Setup time, receive selected signals valid before MSS_RGMII_RCLK

high/low

2

ns

6

t_h(RXCH-RXD)

Hold time, receive selected signals valid after MSS_RGMII_RCLK

high/low

2

ns

1

4

2

4

3

rgmiin_rxc^(A)

5

1st Half-byte

6

2nd Half-byte

rgmiin_rxd[3:0]^(B)

rgmiin_rxctl^(B)

RGRXD[3:0]

RXDV

RGRXD[7:4]

RXERR

A. rgmiin_rxc must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. MSS_RGMII_RXD[3:0] carries data bits 3-0 on the rising edge

of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and

RXERR on falling edge of rgmiin_rxc.

Figure 7-12. GMAC Receive Interface Timing, RGMIIn operation

7.11.3.3.6 RMII Transmit Clock Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

20

7

MAX

UNIT

ns

RMII7 t_{c(REF_CLK)}

RMII8 t_{w(REF_CLKH)}

RMII9 t_{w(REF_CLKL)}

RMII10 t_{t(REF_CLK)}

Cycle time, REF_CLK

Pulse duration, REF_CLK high

Pulse duration, REF_CLK low

Transistion time, REF_CLK

13

3

ns

7

ns

7.11.3.3.7 RMII Transmit Data and Control Switching Characteristics

NO.

RMII11 t_{d(REF_CLK-TXD)}

t_{dd(REF_CLK-TXEN)}

PARAMETER

DESCRIPTION

MIN

MAX

14.2

UNIT

Delay time, REF_CLK high to selected transmit signals valid

2

ns

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RMII7

RMII8

RMII11

RMII9

RMII10

REF_CLK (PRCM)

rmiin_txd1−rmiin_txd0,

rmiin_txen (Outputs)

SPRS8xx_GMAC_RMIITX_06

Figure 7-13. GMAC Transmit Interface Timing RMIIn Operation

7.11.3.3.8 RMII Receive Clock Timing Requirements

NO.

MIN

20

7

MAX

UNIT

ns

RMII1 t_{c(REF_CLK)}

RMII2 t_{w(REF_CLKH)}

RMII3 t_{w(REF_CLKL)}

RMII4 t_{tt(REF_CLK)}

Cycle time, REF_CLK

Pulse duration, REF_CLK high

Pulse duration, REF_CLK low

Transistion time, REF_CLK

13

3

ns

7

ns

7.11.3.3.9 RMII Receive Data and Control Timing Requirements

NO.

MIN

MAX

UNIT

t_{su(RXD-REF_CLK)}

RMII5

RMII6

t_{su(CRS_DV-REF_CLK)}

t_{su(RX_ER-REF_CLK)}

t_{h(REF_CLK-RXD)}

Setup time, receive selected signals valid before REF_CLK

Hold time, receive selected signals valid after REF_CLK

4

2

ns

t_{h(REF_CLK-CRS_DV)}

t_{h(REF_CLK-RX_ER)}

ns

RMII1

RMII3

RMII2

RMII4

RMII6

RMII5

REF_CLK (PRCM)

rmiin_rxd1−rmiin_rxd0,

rmiin_crs, rmin_rxer (inputs)

SPRS8xx_GMAC_RMIIRX_05

Figure 7-14. GMAC Receive Interface Timing RMIIn operation

7.11.3.3.10 MII Transmit Switching Characteristics

NO.

PARAMETER

t_{d(TX_CLK-TXD)}

t_{d(TX_CLK-TX_EN)}

t_{d(TX_CLK-TX_ER)}

DESCRIPTION

MIN

MAX

25

UNIT

1

Delay time, miin_txclk to transmit selected signals valid

0

ns

60

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miin_txclk (input)

miin_txd3 − miin_txd0,

miin_txen, miin_txer (outputs)

Figure 7-15. GMAC Transmit Interface Timing MIIn operation

7.11.3.3.11 MII Receive Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

400

40

MAX

UNIT

ns

1

t_{c(RX_CLK)}

Cycle time, miin_rxclk

ns

2

3

4

t_{w(RX_CLKH)}

t_{w(RX_CLKL)}

t_{t(RX_CLK)}

Pulse duration, miin_rxclk high

Pulse duration, miin_rxclk low

Transition time, miin_rxclk

140

14

260

26

260

26

3

ns

140

14

ns

3

ns

1

4

2

3

miin_rxclk

4

Figure 7-16. Clock Timing (GMAC Receive) - MIIn operation

7.11.3.3.12 MII Receive Timing Requirements

NO.

PARAMETER

t_{su(RXD-RX_CLK)}

DESCRIPTION

MIN

MAX

UNIT

1

Setup time, receive selected signals valid before miin_rxclk

8

ns

t_{su(RX_DV-RX_CLK)}

t_{su(RX_ER-RX_CLK)}

t_{h(RX_CLK-RXD)}

2

Hold time, receive selected signals valid after miin_rxclk

8

ns

t_{h(RX_CLK-RX_DV)}

t_{h(RX_CLK-RX_ER)}

1

2

miin_rxclk (Input)

miin_rxd3−miin_rxd0,

miin_rxdv, miin_rxer (Inputs)

Figure 7-17. GMAC Receive Interface Timing MIIn operation

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7.11.3.3.13 MII Transmit Clock Timing Requirements

NO.

PARAMETER

DESCRIPTION

SPEED

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

MIN

400

40

MAX

UNIT

ns

1

t_{c(TX_CLK)}

Cycle time, miin_txclk

ns

2

3

4

t_{w(TX_CLKH)}

t_{w(TX_CLKL)}

t_{t(TX_CLK)}

Pulse duration, miin_txclk high

Pulse duration, miin_txclk low

Transition time, miin_txclk

140

14

260

26

260

26

3

ns

140

14

ns

3

ns

1

4

2

3

miin_txclk

4

Figure 7-18. Clock Timing (GMAC Transmit) - MIIn operation

7.11.3.3.14 MDIO Interface Timings

CAUTION

The IO Timings provided in this section are only valid for some GMAC usage modes when the

corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables

found in this section.

Table 7-15, Table 7-16 and Figure 7-19 present switching characteristics and timing requirements for the MDIO

interface.

Table 7-15. Timing Requirements for MDIO Input

No

PARAMETER

t_c(MDC)

DESCRIPTION

MIN

400

160

90

MAX

UNIT

ns

MDIO1

MDIO2

MDIO3

MDIO4

MDIO5

Cycle time, MDC

t_w(MDCH)

Pulse Duration, MDC High

ns

t_w(MDCL)

Pulse Duration, MDC Low

ns

t_su(MDIO-MDC)

t_{h(MDIO_MDC)}

Setup time, MDIO valid before MDC High

Hold time, MDIO valid from MDC High

ns

0

ns

Table 7-16. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

NO

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

MDIO6

MDIO7

t_t(MDC)

Transition time, MDC

Delay time, MDC low to MDIO valid

5

ns

t_d(MDC-MDIO)

10

(P * 0.5) - 10

ns

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MDIO2

MDIO3

MDCLK

MDIO6

MDIO4

MDIO5

MDIO

(input)

MDIO7

MDIO

(output)

Figure 7-19. GMAC MDIO diagrams

7.11.3.4 LVDS/Aurora Instrumentation and Measurement Peripheral

The AM273x supports a set of LVDS STM-TWP Aurora interface for exporting raw IF ADC sensor data. The

LVDS transmitters are shared between the two measurement interface options.

•

4-data lane LVDS interface (two additional lanes for Data Clock and Frame Clock) at 1 Gbps/lane

6-lane STM-TWP-Aurora-LVDS interface mode

Please see the AM273x TRM for information regarding programming options for both LVDS interfaces.

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7.11.3.4.1 LVDS Interface Configuration

The supported AM273x LVDS lane configuration is four Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following

data rates:

•

900 Mbps (450 MHz DDR Clock)

600 Mbps (300 MHz DDR Clock)

450 Mbps (225 MHz DDR Clock)

400 Mbps (200 MHz DDR Clock)

300 Mbps (150 MHz DDR Clock)

225 Mbps (112.5 MHz DDR Clock)

150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

Figure 7-20. LVDS Interface Lane Configuration And Relative Timings

7.11.3.4.2 LVDS Interface Timings

Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

Figure 7-21. Timing Parameters

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Table 7-17. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty Cycle Requirements

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

450

mV

Output Offset Voltage

Trise and Tfall

1125

1275

mV

ps

20%-80%, 900 Mbps

900 Mbps

Jitter (pk-pk)

80

ps

7.11.3.5 UART Peripheral

AM273x includes four UART interfaces. One UART is intended as a secondary boot loader source, one is

intended for use as a register debug interface (with XDS110 class emulator) and two are meant for general

UART communication support.

•

Maximum baud-rate supported shall be at least 1536Kbaud in all the different clock frequency modes

UART interfaces multiplexed with other I/O to allow for widest peripheral use flexibility

7.11.3.5.1 UART Timing Requirements

MIN

TYP

MAX

UNIT

f(baud)

Supported baud rate at 20 pF

921.6

kHz

7.11.3.6 I²C Protocol Definition

AM273x supports three master or slave Inter-integrated Circuit interfaces (I2C). One I2C interface is intended to

be connected to an external PMIC or EEPROM device (alternatively controlled by SPI). The other two I2C are

intended as alternative control for sensor devices or other external IC.

•

Standard/fast mode I2C interface compliant with Philips I2C specification version 2.1

Maximum clock rate of 100Kbps in Standard mode and 400Kbps in Fast mode

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7.11.3.6.1 I2C Timing Requirements⁽¹⁾

STANDARD MODE

FAST MODE

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

(1)

t_h(SCLL-SDA)

3.45

0.9

t_w(SDAH)

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 7-22. I2C Timing Diagram

Note

•

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW

period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-

mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such

a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

.

7.11.3.7 Controller Area Network - Flexible Data-Rate (CAN-FD)

The AM273x integrates two CAN-FD interfaces, MSS_MCANA and MSS_MCANB. This enables support of a

typical use case where one CAN-FD interface is used as ECU network interface while the other interface is used

as a local network interface, providing communication with the neighboring sensors.

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•

Support CAN-FD according to ISO 11898-7 protocol with data rate up to 8Mbps

Multiplexed GPIO can be used for CAN-FD external driver control

Synchronous trigger output allows CAN-FD to trigger CSI2 data frames

7.11.3.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins

PARAMETER⁽¹⁾

MIN

TYP

MAX

UNIT

t_{d(MSS_CANA_TX)}

t_{d(MSS_CANB_TX)}

t_{d(MSS_MCANA_RX)}

t_{d(MSS_MCANB_RX)}

Delay time, transmit shift register to

MSS_CANA_TX pin

15

ns

Delay time, transmit shift register to

MSS_CANB_TX pin

15

10

ns

Delay time, MSS_MCANA_RX pin to receive

shift register

Delay time, MSS_MCANB_RX pin to receive

shift register

(1) These values do not include rise/fall times of the output buffer.

7.11.3.8 CSI-2 Peripheral

AM273x integrates two, 4-lane MIPI CSI-2, D-PHY receiver peripherals: CSI2 receiver 0 (CSI2_RX0) and CSI2

receiver 1 (CSI2_RX1). Each peripheral can be used for capturing sensor data samples. The CSI2 interface is

also capable of operating as a hardware-in-the-loop (HIL) interface, allowing for the playback of recorded data

for development or diagnostic purposes.

•

Interface is compliant with the MIPI CSI-2 D-PHY standard revision 1.2

2, 4-lane CSI2 receiver interfaces, working simultaneously at 600 Mbps/lane

4-lane, 3-lane, 2-lane, or 1-lane CSI2 configurations

Support for virtual channels (minimum 4) and data types (minimum 4)

Support for 8/10/12/14/16-bit RAW data mode with capability of sign extension or zero padding to align with

16-bit memory addressing for RAW 10/12/14 modes

•

Support for user defined data types

Please reference the MIPI CSI-2 D-PHY standard revision 1.2 for full receiver timing requirements. Please

reference the AM273x TRM for a complete description of all programmable options.

7.11.3.9 General Purpose ADC (GPADC)

AM273x device implements a GPADC module for safety monitoring device and system analog signals such as

temperature sensor and voltage regulators.

•

Up to 9 external or internal channels supported

7.5 ENOB, 625Ksps ADC

Full-scale range of GPADC input between VSS and 1.8V

Single or continuous conversion modes

Data RAM to store the conversion results (1Kbyte results)

7.11.3.10 Enhanced Pulse-Width Modulator (ePWM)

AM273x includes three Enhanced Pulse-Width Modulation (ePWM) modules. These modules can be used to

generate duty-cycled controlled waveforms for a power regulator, or a power management systems, or more

complex waveforms for motor control applications.

•

Dedicated 16-bit time-base counter with period and frequency control for each PWM module

Each module contains two PWM outputs (EPWMxA and EPWMxB) that shall be usable in the following

configurations:

– Two independent PWM outputs with single-edge operation

– Two independent PWM outputs with dual-edge symmetric operation

– One independent PWM output with dual-edge asymmetric operation

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7.11.3.11 Enhanced Capture (eCAP)

AM273x device includes one enhanced capture (eCAP) module. The eCAP module is used to capture external

timing events. It is a general-purpose module which has a complementary function to ePWM. Uses include

speed measurements of rotating machinery (e.g., toothed sprockets sensed via Hall sensors)

•

Elapsed time measurements between position sensor pulses

Period and duty cycle measurements of pulse train signals

Decoding current or voltage amplitude derviced from duty cycle encoded current/voltage sensor

eCAP shall be working on operating clock of minimum 100mHz

4-event time-stamp registers (each 32 bits)

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7.11.3.12 General-Purpose Input/Output

Section 7.11.3.12.1 lists the switching characteristics of output timing relative to load capacitance.

7.11.3.12.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)^{(1) (2)}

PARAMETER

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

10.2

2.8

6.6

9.8

3.3

7.2

10.5

3.1

6.6

9.6

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

ns

Slew control = 1

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

7.11.4 Emulation and Debug

7.11.4.1 Emulation and Debug Description

7.11.4.2 JTAG Interface

The JTAG interface implements the IEEE1149.1 standard interface for processor debug and boundary scan

testing.

Section 7.11.4.2.1 and Section 7.11.4.2.2 assume the operating conditions stated in Figure 7-23.

7.11.4.2.1 Timing Requirements for IEEE 1149.1 JTAG

Table 7-18. JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

Table 7-19. JTAG Timing Requirements

NO.

1

MIN

TYP

MAX

UNIT

ns

t_c(TCK)

Cycle time TCK

66.66

26.67

1a

t_w(TCKH)

Pulse duration

TCK high (40% of

tc)

ns

1b

3

t_w(TCKL)

Pulse duration

TCK low (40% of

tc)

26.67

2.5

ns

t_su(TDI-TCK)

Input setup time

TDI valid to TCK

high

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Table 7-19. JTAG Timing Requirements (continued)

NO.

MIN

TYP

MAX

UNIT

3

4

t_su(TMS-TCK)

Input setup time

TMS valid to TCK

high

2.5

ns

t_h(TCK-TDI)

Input hold time

TDI valid from

TCK high

18

ns

t_h(TCK-TMS)

Input hold time

TMS valid from

TCK high

7.11.4.2.2 Switching Characteristics for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

25

ns

1

1a

1b

TCK

TDO

2

3

4

TDI/TMS

SPRS91v_JTAG_01

Figure 7-23. JTAG Timing

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7.11.4.3 ETM Trace Interface

The ETM Trace interface provides a means of exporting real time processor debug information to a host PC

through a compatible emulator toolset.

Section 7.11.4.3.1 and Section 7.11.4.3.2 describe the operating conditions shown in Figure 7-24 and Figure

7-25.

7.11.4.3.1 ETM TRACE Timing Requirements

MIN

TYP

MAX

UNIT

Output Conditions

C_LOAD

Output load capacitance

2

20

pF

7.11.4.3.2 ETM TRACE Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_cyc(ETM)

t_h(ETM)

t_l(ETM)

Cycle time, TRACECLK

period

16

ns

1

Pulse Duration, TRACECLK

High

7

ns

2

3

Pulse Duration, TRACECLK

Low

4

5

t_r(ETM)

Clock and data rise time

Clock and data fall time

3.3

7

ns

t_f(ETM)

t_{d(ETMTRACECLKH-ETMDATAV)}

Delay time, ETM trace clock

high to ETM data valid

1

6

7

t_{d(ETMTRACECLKl-ETMDATAV)}

Delay time, ETM trace clock

low to ETM data valid

7

ns

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

Figure 7-24. ETMTRACECLKOUT Timing

Figure 7-25. ETMDATA Timing

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8 Detailed Description

8.1 Overview

The AM273x is a high performance microcontroller with an integrated C66x DSP and is ideally suited for

applications needing requiring conditioning and processing functions. Two R5F cores (with optional lockstep

capability) running at 400 MHz with 5MB of internal memory coupled along with a broad range of automotive and

industrial connectivity peripherals and an easy to use SDK enables our customers to address a wide range of

use cases in automotive and industrial markets. Functional safety and security (HSM) features are integrated to

address emerging market trends.

One representative use case is for the AM273x to operate as the MCU host in an automotive radar system.

In this role AM273x provides data aggregation, FFT, CFAR, range, velocity and angle estimation and tracking

processing. The AM273x can operate as a host in single or dual (cascaded) front-end radar application.

As seen in Figure 3-1 the AM273x is divided into a few high level functional subsystems. Each subsystem

contains specific control, signal processing, and digital communication peripherals.

•

Main Subsystem (MSS): MCU Core, Cryptographic Core, Mailbox, EDMA, RTI, QSPI, SPI, CAN-FD, I2C,

UART, Ethernet and GPIO

•

DSP Subsystem (DSS): C66x Core, HWA2.0 Accelerator, Mailbox, EDMA, RTI

Radar Controller Subsystem (RCSS): EDMA, CSI2A/B, SPIA/B, I2C and GPIO

Each primary subsystem is then interconnected through an ECC enabled, switch interconnect bus, allowing for

EDMA transfer of data between peripherals and processing cores.

8.2 Main Subsystem

The main subsystem (MSS) is the primary controller of the device and controls all the other device subsystem

cores and peripherals. The MSS contains the Cortex-R5F (MSS R5F) processor and associated peripherals and

associated EDMA and Mailbox IPC functions. The MSS also controls wider system connectivity and network

peripherals such as the I2C, UART, SPI, CAN-FD, EPWM, and Ethernet. The MSS is connected to the primary

interconnect through the Main Subsystem (MSS) Interconnect which is ECC enabled.

The MSS contrains its own dedicated functional safety block consisting of DCC, ESM, LBIST/PBIST, CRC

Watchdog Timer and GPADC for safety monitoring of critical system signals such as power supply and

temperature monitors.

8.3 DSP Subsystem

The DSP subsystem (DSS) contains the TI high performance C66x DSP, HWA 2.0, and a high-bandwidth

interconnect for high performance (128-bit, 150MHz), and associated data transfer peripherals: 6x EDMA for

data transfer, 2x RTI and Mailbox IPC. The Aurora/LVDS measurement data output interface is also mastered by

the C66x DSP. L3 shared memory is available on the DSS interconnect which is also ECC enabled.

For more information on DSP functionality, see the

8.4 Radar Control Subsystem

The radar control subsystem (RCSS) integrates a high-bandwidth interconnect with a pair of 4-lane, CSI 2.0

receivers (CSI2_RX0 and CSI2_RX1), two SPI controllers (RCSS_SPIA and RCSS_SPIB), I2C controllers and

a set of GPIO. The SPI, I2C and GPIO peripherals can be utilized for controlling and configuring the attached

sensor devices. The CSI 2.0 receivers allow for receiveing high-speed sensor data samples such as samples.

8.5 Other Subsystems

8.5.1 Radar A2D Data Format Over CSI2 Interface

The AM273x device uses MIPI D-PHY / CSI2-based format to receive the raw A2D samples from an external

radar transceiver. This is shown in Figure 8-1.

•

Supports four data lanes

CSI-2 data rate scalable from 150 Mbps to 600 Mbps per lane

Virtual channel based

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•

CRC generation

Normal Mode

Frame Period

Acquisition Period

Frame

Ramp/Chirp

Data Ready

1

2

3

N

F

L

H

L

H

L

H

L

H

L

F

S

E

S

E

S

E

S

E

Short

Packet

Short

Packet

Long

Packet

Short

Packet

ST SP ET

LPS

ST SP ET

.5μs-.8μs

ST PH

DATA

PF ET LPS

ST SP ET

LPS

Chirp 1 data

Data rate/Lane should be such that "Chirp + Interchirp" period

should be able to accommodate the data transfer

Frame Start – CSI2 VSYNC Start Short PacketLine Start – CSI2 HSYNC Start Short PacketLine End – CSI2 HSYNC End Short

PacketFrame End – CSi2 VSYNC End Short Packet

Figure 8-1. CSI-2 Transmission Format

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The data payload is constructed with the following three types of information:

•

Chirp profile information

The actual chirp number

A2D data corresponding to chirps of all four channels

– Interleaved fashion

•

Chirp quality data (configurable)

The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The data

packet packing format is shown in Figure 8-2.

First

11

5

1

0

11

0

CH Chirp

Profile

Channel

Number

NU

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

5

1

11

CH Chirp

Profile

Channel

Number

Chirp Num

11

Channel 0 Sample 0 i

Channel 1 Sample 0 i

Channel 2 Sample 0 i

Channel 3 Sample 0 i

Channel 0 Sample 1 i

Channel 1 Sample 1 i

Channel 2 Sample 1 i

Channel 3 Sample 1 i

CQ Data [11:0]

Channel 0 Sample 0 q

11

Channel 1 Sample 0 q

11

Channel 2 Sample 0 q

11

Channel 3 Sample 0 q

11

Channel 0 Sample 1 q

11

Channel 1 Sample 1 q

11

Channel 2 Sample 1 q

11

Channel 3 Sample 1 q

Continues till the

last sample. Max 1023

11

CQ Data [23:12]

11

CQ Data [35:24]

CQ Data [47:36]

11

CQ Data [59:48]

NU

CQ Data [63:60]

Last

Figure 8-2. Data Packet Packing Format for 12-Bit Complex Configuration

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8.5.2 ADC Channels (Service) for User Application

The AM273x device includes provision for an ADC service for user application, where the GPADC engine

present inside the device can be used to measure up to nine external and internal voltages. The ADC1, ADC2,

ADC3, ADC4, ADC5, ADC6, ADC7, ADC8 and ADC9 pins are used for this purpose.

Note

GPADC structures are used for measuring the output of internal temperature sensors.

GPADC Specifications:

•

625Ksps SAR ADC

0 to 1.8-V input range

10-bit resolution

Table 8-1. GPADC Parameters

PARAMETER

TYP

1.8

UNIT

V

ADC supply

ADC unbuffered input voltage range

0 – 1.8

0.4 – 1.3

10

V

ADC buffered input voltage range⁽¹⁾

V

ADC resolution

bits

LSB

Ksps

ns

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

ADC INL

ADC sample rate

ADC sampling time

ADC internal cap

400

10

pF

ADC buffer input capacitance

ADC input leakage current

2

pF

3

uA

(1) Outside of given range, the buffer output will become nonlinear.

8.6 Boot Modes

AM273x bootloader functionality is controlled by a set of start on power (SOP) pins. These pins states are

latched on de-assertion of the NRESET pin after power on of the device. The SOP pins are multiplexed with

functional mode signals before and during NRESET de-assertion. After bootloader execution the functional

mode operation is then restored. See the power on reset timing sequence for more details. The following tables

describe the SOP pin operation.

Host hardware should provide a means for driving these SOP pins to their required states during NRESET

de-assertion, but also allow for their functional mode operation if required by the intended application.

Table 8-2. SOP Pins

D6

SOP Mode Signal Name

Pinlist Signal Name

SOP[0]

SOP[1]

SOP[2]

SOP[3]

SOP[4]

TDO

E17

F1

MSS_MIBSPIB_CS2

PMIC_CLKOUT

V9

MSS_UARTB_TX

MSS_UARTA_TX

W2

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Table 8-3. SOP Pin Modes

Boot Options

SOP Mode

•

SOP[2:0] = 0b011 selects SOP_MODE2

SOP[2:0] = 0b001 selects SOP_MODE4

SOP[2:0] = 0b101 selects SOP_MODE5

All other states reserved and should not be selected.

Bootmode SOP Modes

Crystal Detect SOP Modes

Bootmode SOP Modes

•

SOP[4:3] = 0b00 selects 40 MHz Crystal Mode

SOP[4:3] = 0b01 selects 45.1584 MHz Crystal Mode

SOP[4:3] = 0b10 selects 49.152 MHz Crystal Mode

SOP[4:3] = 0b11 selects 50 MHz Crystal Mode

Table 8-4. Bootmode SOP Descriptions

Function

Description

SOP_MODE2

Development Mode

Development boot mode. The

AM273x ROM bootloader will

setup the device to wait for a

JTAG debugger connection.

Functional boot mode of the

AM273x device. In this mode, the

ROM bootloader will attempt to

load a valid secondary bootloader

image from primarily the QSPI

interface and secondarily the SPI

host interface.

SOP_MODE4

SOP_MODE5

Functional Mode

Device Management Mode

QSPI flash programming boot

mode of the AM273x device. In

this mode the ROM bootloader

will attempt to receive a

valid QSPI secondary bootloader

image over MSS_UARTA_TX/RX

(pins W2, U3) and attempt to

flash an attached QSPI memory

with this image.

Table 8-5. Crystal Detect SOP Mode Description

Crystal Detect SOP Modes

40 MHz Crystal Crystal Mode

ROM bootloader image expects a 40 MHz nominal crystal clock source.

45.1584 MHz Crystal Mode

49.152 MHz Crystal Mode

50 MHz Crystal Mode

ROM bootloader image expects a 45.1584 MHz nominal crystal clock source.

ROM bootloader image expects a 49.152 MHz nominal crystal clock source.

ROM bootloader image expects a 50 MHz nominal crystal clock source.

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9 Applications, Implementation, and Layout

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Typical Application

9.1.1 Schematic

The below AM273x Example Schematic shows an exerpt the AM273x EVM schematic. The exerpt focuses only

on the AM273x device schematic symbols to show the device pin usage.

Figure 9-1. AM273x Example Schematic

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9.1.2 Layout

9.1.2.1 Layout Example

The following figures are exerpts from the AM273x EVM PCB layout, assembly and layer stack-up.

78

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Figure 9-2. AM273x EVM - Layer 1 (Top)

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Figure 9-3. AM273x EVM - Layer 10 (Bottom)

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Figure 9-4. AM273x EVM - Top Assembly

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Figure 9-5. AM273x EVM - Layer Stackup

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

10.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microcontrollers (MCU) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AM273x). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP

devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS

(for example, AM273x). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMX and TMDX) through fully qualified production devices and tools (TMS and TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

TMS Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, ZCE), the temperature range (for example, blank is the default commercial temperature range),

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and the device speed range, in megahertz (for example, 400 MHz). Table 10-1 and Figure 10-1 provides a

legend for reading the complete device name for any AM273x device.

For orderable part numbers of AM273x devices in the AM273x package types, see the Package Option

Addendum of this document, ti.com, or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the Silicon Errata .

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10.1.1 Standard Package Symbolization

Note

Some devices may have a cosmetic circular marking visible on the top of the device package which

results from the production test process. In addition, some devices may also show a color variation in

the package substrate which results from the substrate manufacturer. These differences are cosmetic

only with no reliability impact.

aBBBBBBr

ZfYytPPPQ1

G1

A1 (PIN ONE INDICATOR)

XXXXXXX

ZZZ

YYY

O

Figure 10-1. Printed Device Reference

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10.1.2 Device Naming Convention

Table 10-1. Nomenclature Description

FIELD PARAMETER

FIELD DESCRIPTION

VALUE

DESCRIPTION

X

P

Prototype

a⁽¹⁾

Device evolution stage

Preproduction (production test flow, no reliability data)

BLANK

AM2732

A

Production

BBBBBB

r

Base production part number

Device revision

See Table 5-1, Device Comparison

SR 1.0

Device Speed and Memory

Grades

Z

D

See Table 7-1, Speed and Memory Grade

R

S

General Purpose Device

Features

(see Table 5-1, Device

Comparison)

f

Programmable DSP (Single Core)

DSP Blackbox

T

G

Non-Functional Safety Device

Functional Safety Device

Y

y

Functional Safety

Security

F

G

Non-Secure

1

Dummy Key Device

M

A

Production Key HS Device

–40°C to 105°C - Extended Industrial

–40°C to 125°C - Automotive

–40°C to 140°C - Extended Automotive

ZCE NFBGA-N285 (13 mm × 13 mm) Package

Auto Qualified (AEC-Q100)

Enhanced Product

Temperature

(see Section 7.4, ROC)

t⁽²⁾

I

Q

PPP

Q1

Package Designator

ZCE

Q1

EP

Automotive Designator

XXXXXXX

YYY

ZZZ

Lot Trace Code (LTC)

Production Code; For TI use only

Pin one designator

O

G1

ECAT—Green package designator

(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent

evolutionary stages of product development from engineering prototypes through fully qualified production devices.

Prototype devices are shipped against the following disclaimer:

“This product is still in development and is intended for internal evaluation purposes.”

Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of

merchantability of fitness for a specific purpose, of this device.

(2) Applies to device max junction temperature.

Note

BLANK in the symbol or part number is collapsed so there are no gaps between characters.

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10.2 Tools and Software

The following products support development for AM273x platforms:

Development Tools

Code Composer Studio^™Integrated Development Environment Code Composer Studio (CCS) Integrated

Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded

Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded

applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,

profiler, and many other features. The intuitive IDE provides a single user interface taking you through each

step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever

before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced

embedded debug capabilities from TI resulting in a compelling feature-rich development environment for

embedded developers.

SYSCONFIG The SYSCONFIG Pin MUX Utility is a software tool which provides a Graphical User Interface

for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.

Results are output as C header/code files that can be imported into software development kits (SDKs) or used to

configure customer's custom software.

AM273x Power Estimation Tool (PET) AM273x Power Estimation Tool (PET) provides users the ability to gain

insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose

multiple application scenarios and understand the power consumption as well as how advanced power saving

techniques can be applied to further reduce overall power consumption.

For a complete listing of development-support tools for the processor platform, visit the Texas Instruments

website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized

distributor.

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10.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

The current documentation that describes the processor, related peripherals, and other technical collateral is

listed below.

The following documents describe the AM273x family of devices.

Technical Reference Manual

AM273x Microntrollers Silicon Revision 1.0 Technical Reference Manual Details the integration, the

environment, the functional description, and the programming models for each peripheral and subsystem in

the AM273x family of devices.

Errata

AM273x Microntrollers Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the functional

specifications for the device.

Tip: Search TI.com using literature numbers.

10.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

Sitara^™, NanoFree^™, and TI E2E^™are trademarks of Texas Instruments.

Code Composer Studio^™is a trademark of TI.

Arm^®and Cortex^®are registered trademarks of Arm Limited.

All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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IMPORTANT NOTICE AND DISCLAIMER

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AM2732ADRFGQZCERQ1
厂家：	TEXAS INSTRUMENTS
描述：	AM273x Sitaraâ¢ Microcontrollers 微控制器
文件：	总94页 (文件大小：6082K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM2732ADRFGQZCERQ1 [TI]

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