AM3351 [TI]
Sitara 处理器：Arm Cortex-A8、1Gb 以太网、支持显示效果;
| 型号： | AM3351 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sitara 处理器：Arm Cortex-A8、1Gb 以太网、支持显示效果 以太网 |
| 文件： | 总258页 (文件大小：4405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
AM335x Sitara™ 处理器
1 器件概述
1.1 特性
1
• 高达 1GHz Sitara™ ARM® Cortex®-A8 32 位精简
指令集计算机 (RISC) 处理器
– 具有 64 位累加器的单周期 32 位乘法器
– 增强型 GPIO 模块为外部信号提供移入/移出支
持以及并行锁断
– NEON™单指令流多数据流 (SIMD) 协处理器
– 12KB 带有单位检错（奇偶校验）的共享 RAM
– 三个 120 字节寄存器组，可被每个 PRU 访问
– 用于处理系统输入事件的中断控制器 (INTC)
– 用于将内部和外部主机连接到 PRU-ICSS 内部资
源的本地互连总线
– 32KB L1 指令和 32KB 带有单位检错（奇偶校
验）的数据缓存
– 带有错误校正码 (ECC) 的 256KB L2 缓存
– 176KB 片载启动 ROM
– 64KB 专用 RAM
– PRU-ICSS 内的外设：
– 仿真和调试 - JTAG
– 一个带有流控制引脚的通用异步收发器
(UART) 端口，支持高达 12Mbps 的数据速率
– 一个增强型捕捉 (eCAP) 模块
– 2 个支持工业用以太网的 MII 以太网端口，例
如EtherCAT
– 1 个 MDIO 端口
– 中断控制器（最多可控制 128 个中断请求）
• 片上存储器（共享 L3 RAM）
– 64KB 通用片上存储器控制器 (OCMC) 随机存取
存储器 (RAM)
– 可访问所有主机
– 支持保持以实现快速唤醒
• 外部存储器接口 (EMIF)
• 电源、复位和时钟管理 (PRCM) 模块
– 控制待机模式和深度休眠模式的进入和退出
– mDDR(LPDDR)、DDR2、DDR3、DDR3L 控制
器：
– 负责休眠排序、电源域关闭排序、唤醒排序和电
源域打开排序
– mDDR：200MHz 时钟（400MHz 数据速率）
– DDR2：266MHz 时钟（532MHz 数据速率）
– DDR3：400MHz 时钟（800MHz 数据速率）
– DDR3L：400MHz 时钟（800MHz 数据速率）
– 16 位数据总线
– 时钟
– 集成了 15MHz 至 35MHz 的高频振荡器，用
于为各种系统和外设时钟生成参考时钟
– 支持子系统和外设的单独时钟使能和禁用控
制，帮助降低功耗
– 1GB 全部可寻址空间
– 五个用于生成系统时钟的 ADPLL（MPU 子系
统、DDR 接口、USB 和外设 [MMC 和 SD、
UART、SPI、I2C]、L3、L4、以太网、GFX
[SGX530]、LCD 像素时钟）
– 支持一个 x16 或两个 x8 存储器件配置
– 通用存储器控制器 (GPMC)
– 灵活的 8 位和 16 位异步存储器接口，具有多
达七个片选（NAND、NOR、复用 NOR 和
SRAM）
– 电源
– 两个不可切换的电源域（实时时钟 [RTC] 和唤
醒逻辑 [WAKEUP]）
– 三个可切换的电源域（MPU 子系统 [MPU]、
SGX530 [GFX]、外设和基础设施 [PER]）
– 执行 SmartReflex™ 2B 类，基于芯片温度、
过程变化和性能实现内核电压调节（自适应电
压调节 [AVS]）
– 使用 BCH 代码，支持 4 位、8 位或 16 位
ECC
– 使用海明码来支持 1 位 ECC
– 错误定位器模块 (ELM)
– 与 GPMC 一起使用时，可通过 BCH 算法确定
所生成的伴随多项式中数据错误的地址
– 根据 BCH 算法，支持 4 位、8 位和 16 位每
512 字节块错误定位
• 可编程实时单元子系统和工业通信子系统 (PRU-
– 动态电压频率缩放 (DVFS)
• 实时时钟 (RTC)
– 实时日期（年、月、日和星期几）和时间（小
时、分钟和秒）信息
ICSS)
– 支持的协议如 EtherCAT®、PROFIBUS、
PROFINET、EtherNet/IP™ 等
– 内部 32.768kHz 振荡器，RTC 逻辑和 1.1V 内部
低压降稳压器 (LDO)
– 独立的加电复位 (RTC_PWRONRSTn) 输入
– 2个可编程实时单元(PRU)
– 32位可运行在200MHz的负载/存储RISC处理
器
– 用于外部唤醒事件的专用输入引脚(EXT_
WAKEUP)
– 8KB 带有单位检错（奇偶校验）的指令 RAM
– 8KB 带有单位检错（奇偶校验）的数据 RAM
– 可编程警报可用于生成 PRCM 内部中断（用于唤
醒）或 Cortex-A8 内部中断（用于事件通知）
1
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
– 可编程警报可与外部输出 (PMIC_POWER_EN)
一起用来使能电源管理 IC，从而恢复非 RTC 电
源域
– 1 位、4 位和 8 位 MMC、SD 和 SDIO 模式
– MMCSD0 具有专用于 1.8V 或 3.3V 操作的电
源轨
• 外设
– 高达 48MHz 的数据传输速率
– 支持卡检测和写保护
– 符合 MMC4.3、SD 和 SDIO 2.0 规范
– 多达三个 I2C 主从接口
– 标准模式（高达 100kHz）
– 快速模式（高达 400kHz）
– 多达四组通用 I/O (GPIO) 引脚
– 最多两个带集成 PHY 的 USB 2.0 高速 DRD（双
角色器件）端口
– 多达两个工业千兆位以太网 MAC（10、100 和
1000Mbps）
– 集成开关
– 每个 MAC 都支持 MII、RMII、RGMII 和
MDIO 接口
– 每组包含 32 个 GPIO 引脚（与其他功能引脚
复用）
– 以太网 MAC 和交换机可独立于其它功能运行
– IEEE 1588v2 精密时间协议 (PTP)
– 多达 2 个控制器局域网 (CAN) 端口
– 支持 CAN 版本 2 部分 A 和 B
– 多达两个多通道音频串行端口 (McASP)
– 高达 50MHz 的发送和接收时钟
– GPIO 引脚可作为中断输入（每组多达两个中
断输入）
– 多达三个外部直接存储器访问 (DMA) 事件输入也
可用作中断输入
– 8 个 32 位通用计时器
– 每个具有独立 TX 和 RX 时钟的 McASP 端口
对应多达四个串行数据引脚
– DMTIMER1 是用于操作系统 (OS) 节拍的 1ms
计时器
– 支持时分多路复用 (TDM)、内部 IC 声音 (I2S)
和类似格式
– DMTIMER4–DMTIMER7 为引脚输出
– 一个安全装置计时器
– SGX530 3D 图形引擎
– 支持数字音频接口传输（SPDIF、IEC60958-1
和 AES-3 格式）
– 用于发送和接收的 FIFO 缓冲器（256 字节）
– 最多 6 个 UART
– 拼图架构每秒可提供最多 2000 万个多边形
– 通用可扩展着色引擎 (USSE) 是一款包含像素
和顶点着色功能的多线程引擎
– 所有 UART 支持 IrDA 和 CIR 模式
– 所有 UART 支持 RTS 和 CTS 流量控制
– UART1 支持完整的调制解调器控制
– 多达两个主从 McSPI 串行接口
– 最多 2 个芯片选择
– 超过 Microsoft VS3.0、PS3.0 和 OGL2.0 的
高级着色功能集
– Direct3D Mobile、OGL-ES 1.1 和 2.0 以及
OpenMax 的行业标准 API 支持
– 精细的任务切换、负载均衡和电源管理
– 高达48 MHz
– 多达三个 MMC、SD 和 SDIO 端口
– 高级几何 DMA 驱动型操作，最大程度地减少
CPU 交互
2
器件概述
版权 © 2011–2018, Texas Instruments Incorporated
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
– 可编程高质量图像防锯齿
– 用于统一存储器架构中操作系统运行的完全虚
拟化存储器寻址
– 多达 3 个 32 位增强型正交编码脉冲 (eQEP) 模
块
• 器件标识
– LCD 控制器
– 包含电子熔丝组 (FuseFarm)，其中一些位厂家可
编程
– 最多 24 位数据输出；每像素 8 位 (RGB)
– 生产 ID
– 分辨率最高可达 2048 x 2048 （具有最高
126MHz 的像素时钟）
– 集成 LCD 接口显示驱动器 (LIDD) 控制器
– 集成光栅控制器
– 器件部件号（唯一的 JTAG ID）
– 设备版本（可由主机 ARM 读取）
• 调试接口支持
– 集成 DMA 引擎可通过中断或固件计时器从外
部帧缓冲器获取数据，无需加重处理器的负担
– 用于 ARM（Cortex-A8 和 PRCM）和 PRU-
ICSS 调试的 JTAG 和 cJTAG
– 512 字深内部 FIFO
– 支持的显示类型：
– 支持器件边界扫描
– 支持 IEEE1500
• DMA
–
字符显示器 - 使用 LIDD 控制器对这些显示
器进行编程
– 片上增强型 DMA 控制器 (EDMA) 搭载三个第三
方传送控制器 (TPTC) 和一个第三方通道控制器
(TPCC)，支持多达 64 个可编程逻辑通道和 8 个
QDMA 通道。EDMA 用于：
–
无源矩阵 LCD 显示-使用 LCD 光栅显示控
制器来为到无源显示的持续图形刷新提供
定时和数据
– 向/从片上存储器传送
– 向/从外部存储器（EMIF、GPMC 和从外设）
传送
–
有源矩阵 LCD 显示-使用外部帧缓冲器空
间和内部 DMA 引擎来驱动到控制面板的流
数据
– 12 位逐次逼近寄存器 (SAR) ADC
– 每秒采集 200K 个样本
• 处理器间通信 (IPC)
– 集成了基于硬件的 IPC 邮箱，以及用于 Cortex-
A8、PRCM 和 PRU-ICSS 之间进程同步的
Spinlock
– 可从 8:1 模拟开关复用的八个模拟输入中任意
选择输入
– 生成中断的邮箱寄存器
– 可配置为用作 4 线、5 线或 8 线电阻式触摸屏
控制器 (TSC) 接口
– 多达三个 32 位 eCAP 模块
–
4 个初启程序 （Cortex-A8、PRCM、
PRU0、PRU1）
– 自旋锁具有128个软件指定的锁寄存器
• 安全性
– 可配置为三个捕捉输入或者三个备用 PWM 输
出
– 多达三个增强型高分辨率 PWM 模块 (eHRPWM)
– 密码硬件加速器（AES、SHA、RNG）
– 具有时间和频率控制功能的 16 位专用时基计
数器
– 安全引导
• 启动模式
– 可配置为 6 个单端，6 个双边对称，或者 3
个双边不对称输出
– 通过锁存在 PWRONRSTn 复位输入引脚上升沿
的启动配置引脚来选择启动模式
• 封装：
– 298 引脚 S-PBGA-N298 过孔通道封装
（后缀 ZCE），0.65mm 焊球间距
– 324 引脚 S-PBGA-N324 封装
（后缀 ZCZ），0.80mm 焊球间距
版权 © 2011–2018, Texas Instruments Incorporated
器件概述
3
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
1.2 应用范围
•
•
•
•
•
游戏外设
•
•
•
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联网贩售机
电子秤
家庭和工业自动化
消费类医疗器械
打印机
教育控制台
高级玩具
智能收费系统
1.3 说明
AM335x 微处理器基于 ARM Cortex-A8 处理器，在图像、图形处理、外设以及 EtherCAT 和 PROFIBUS 等
工业接口选项方面得到了增强。该器件支持高级操作系统 (HLOS)。处理器 SDK Linux®和 TI-RTOS 可从德
州仪器 (TI) 免费获取。
AM335x 微处理器包含 功能框图中显示的子系统，并简要介绍了 简要 说明：
包含 功能框图中显示的子系统，并简要介绍了 简要 说明：
微处理器单元 (MPU) 子系统基于 ARM Cortex-A8 处理器， PowerVR SGX™图形加速器子系统提供 3D 图
形加速功能以支持显示和游戏特效。
可编程实时单元子系统和工业通信子系统 (PRU-ICSS) 与 ARM 内核彼此独立，允许单独操作和计时，以实
现更高的效率和灵活性。PRU-ICSS 支持附加外设接口以及 EtherCAT、PROFINET、EtherNet/IP、
PROFIBUS、以太网 POWERLINK、串行实时通信协议 (Sercos) 等实时协议。此外，凭借 PRU-ICSS 的可
编程特性及其对引脚、事件和所有片上系统 (SoC) 资源的访问权限，该子系统可以灵活地实现快速实时响
应、专用数据处理操作以及自定义外设接口，并减轻 SoC 其他处理器内核的任务负载。
器件信息(1)
封装
器件型号
封装尺寸
AM3359ZCZ
AM3358ZCZ
AM3357ZCZ
NFBGA (324)
15.0mm x 15.0mm
NFBGA (324)
15.0mm x 15.0mm
NFBGA (324)
15.0mm x 15.0mm
AM3356ZCZ、AM3356ZCE
AM3354ZCZ、AM3354ZCE
AM3352ZCZ、AM3352ZCE
AM3351ZCE
NFBGA (324)、NFBGA (298)
NFBGA (324)、NFBGA (298)
NFBGA (324)、NFBGA (298)
NFBGA (298)
15.0mm x 15.0mm、13.0mm x 13.0mm
15.0mm x 15.0mm、13.0mm x 13.0mm
15.0mm x 15.0mm、13.0mm x 13.0mm
13.0mm x 13.0mm
(1) 更多信息，请参阅节 9，机械、封装和可订购产品信息。
4
器件概述
版权 © 2011–2018, Texas Instruments Incorporated
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
1.4 功能框图
图 1-1 给出了 Am335x 微处理器功能框图。
Display
ARM®
Graphics
Cortex®-A8
Up to 1 Ghz
PowerVR
SGX
3D GFX
24-bit LCD controller
Touch screen controller
PRU-ICSS
Crypto
32KB and 32KB L1 + SED
256KB L2 + ECC
EtherCAT, PROFINET,
EtherNet/IP,
and more
64KB
shared
RAM
176KB ROM 64KB RAM
L3 and L4 interconnect
Serial
System
Parallel
eCAP x3
ADC (8 channel)
12-bit SAR
UART x6
SPI x2
I2C x3
eDMA
Timers x8
WDT
MMC, SD and
SDIO x3
GPIO
McASP x2
(4 channel)
JTAG
RTC
eHRPWM x3
eQEP x3
PRCM
Crystal
Oscillator x2
CAN x2
(Ver. 2 A and B)
USB 2.0 HS
DRD + PHY x2
Memory interface
mDDR(LPDDR), DDR2,
DDR3, DDR3L
(16-bit; 200, 266, 400, 400 MHz)
EMAC (2-port) 10M, 100M, 1G
IEEE 1588v2, and switch
(MII, RMII, RGMII)
NAND and NOR (16-bit ECC)
图 1-1. AM335x 功能方框图
版权 © 2011–2018, Texas Instruments Incorporated
器件概述
5
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
内容
7.2
Recommended Clock and Control Signal Transition
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 4
1.3 说明 ................................................... 4
1.4 功能框图 ............................................. 5
修订历史记录............................................... 7
Device Comparison ..................................... 8
3.1 Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1 Pin Diagram ......................................... 10
4.2 Pin Attributes ........................................ 18
4.3 Signal Descriptions.................................. 50
Specifications ........................................... 79
5.1 Absolute Maximum Ratings......................... 79
5.2 ESD Ratings ........................................ 80
5.3 Power-On Hours (POH)............................. 81
5.4 Operating Performance Points (OPPs) ............. 81
5.5 Recommended Operating Conditions............... 84
5.6 Power Consumption Summary...................... 86
5.7 DC Electrical Characteristics........................ 88
Behavior............................................ 115
7.3 OPP50 Support .................................... 115
7.4 Controller Area Network (CAN) .................... 116
7.5 DMTimer ........................................... 117
7.6
Ethernet Media Access Controller (EMAC) and
Switch .............................................. 118
2
3
7.7 External Memory Interfaces........................ 126
7.8 I2C.................................................. 189
7.9 JTAG Electrical Data and Timing.................. 190
7.10 LCD Controller (LCDC) ............................ 192
7.11 Multichannel Audio Serial Port (McASP) .......... 208
7.12 Multichannel Serial Port Interface (McSPI) ........ 213
7.13 Multimedia Card (MMC) Interface ................. 219
4
5
7.14 Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-ICSS) 222
7.15 Universal Asynchronous Receiver Transmitter
(UART) ............................................. 231
8
Device and Documentation Support.............. 234
8.1 Device Nomenclature.............................. 234
8.2 Tools and Software ................................ 235
8.3 Documentation Support............................ 239
8.4 Related Links ...................................... 242
8.5 Community Resources............................. 242
8.6 商标 ................................................ 243
8.7 静电放电警告....................................... 243
8.8 Glossary............................................ 243
Mechanical, Packaging, and Orderable
Information............................................. 244
9.1 Via Channel........................................ 244
9.2 Packaging Information ............................. 244
5.8
Thermal Resistance Characteristics for ZCE and
ZCZ Packages ...................................... 92
5.9 External Capacitors ................................. 93
5.10 Touch Screen Controller and Analog-to-Digital
Subsystem Electrical Parameters................... 96
6
7
Power and Clocking ................................... 98
6.1 Power Supplies...................................... 98
6.2 Clock Specifications................................ 106
Peripheral Information and Timings .............. 115
7.1 Parameter Information ............................. 115
9
6
内容
版权 © 2011–2018, Texas Instruments Incorporated
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from April 1, 2016 to December 15, 2018 (from J Revision (April 2016) to K Revision)
Page
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将 OTG 更新/更改为 DRD（双角色器件） ........................................................................................ 2
删除了 OpenVG 1.0 .................................................................................................................. 2
更新了 “说明” 文本 ................................................................................................................... 4
将 OTG 更新/更改为 DRD ........................................................................................................... 5
Removed 600 MHz from Frequency and 1200 from MIPS for AM3359....................................................... 8
Added DEV_FEATURE register value to Device Comparison ................................................................. 9
Added 125°C Latch-up performance info ........................................................................................ 79
Updated DDR3/DDR3L maximum frequency for industrial extended temperature......................................... 82
Added Industrial Extended operating temperature range...................................................................... 85
Updated/Changed footnote for Output Capacitor Characteristics from "RTC_KLDO_ENn" to "RTC_KALDO_ENn".. 94
Added ADC clock frequency to TSC_ADC Electrical Parameters............................................................ 97
Updated Sampling Dynamics section of TSC_ADC Electrical Parameters table........................................... 97
Added new footnotes ............................................................................................................... 99
Added DCAN Timing Conditions................................................................................................. 116
Added DMTimer Timing Conditions ............................................................................................. 117
Remove NO. 4, Transition time, MDC .......................................................................................... 118
Updated Switching Characteristics for MDIO_DATA.......................................................................... 119
Removed content from Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode............ 123
Removed Transition time, RD and Transition time, RX_CTL from Timing Requirements for RGMII[x]_RD[3:0],
and RGMII[x]_RCTL - RGMII Mode............................................................................................. 124
Removed Transition time, TXC from Switching Characteristics for RGMII[x]_TCLK - RGMII Mode ................... 125
Removed Transition time, TD and Transition time, TX_CTL from Switching Characteristics for RGMII[x]_TD[3:0],
and RGMII[x]_TCTL - RGMII Mode ............................................................................................. 125
Removed content from GPMC and NOR Flash Switching Characteristics—Synchronous Mode ...................... 127
Updated No. F11 values .......................................................................................................... 127
Swapped F22 and F21 in GPMC and NOR Flash—Synchronous Burst Read—4x16-Bit (GpmcFCLKDivider = 0) . 132
Removed content from GPMC and NOR Flash Switching Characteristics—Asynchronous Mode ..................... 136
Removed content from GPMC and NAND Flash Switching Characteristics—Asynchronous Mode ................... 145
Removed Rise time and Fall time info from Switching Characteristics for I2C Output Timings ......................... 190
Added JTAG Timing Conditions ................................................................................................. 191
Added content to LCD Controller Timing Conditions.......................................................................... 192
Removed content from Switching Characteristics for LCD LIDD Mode .................................................... 193
Removed content from Switching Characteristics for LCD Raster Mode .................................................. 202
Removed content from Switching Characteristics for McSPI Output Timings – Master Mode .......................... 216
Removed content from Switching Characteristics for MMC[x]_CLK ........................................................ 220
Removed content from PRU-ICSS PRU Switching Requirements – Direct Output Mode ............................... 222
Removed content from PRU-ICSS PRU Switching Requirements - Shift Out Mode ..................................... 224
Removed content from PRU-ICSS ECAT Switching Requirements - Digital I/Os ........................................ 227
Removed transition time, MDC from PRU-ICSS MDIO Switching Characteristics - MDIO_CLK ....................... 227
Updated PRU-ICSS MDIO Switching Characteristics - MDIO_DATA ...................................................... 228
Updated Note in PRU-ICSS MII_RT Electrical Data and Timing............................................................ 228
Added UART Timing Conditions................................................................................................. 230
Added UART Timing Conditions................................................................................................. 231
已添加 Carrier Type to 图 8-1, AM335x Device Nomenclature .............................................................. 235
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
版权 © 2011–2018, Texas Instruments Incorporated
修订历史记录
7
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
3 Device Comparison
表 3-1 lists the features supported across different AM335x devices.
表 3-1. Device Features Comparison
FUNCTION
AM3351
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
ARM Cortex-A8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
300 MHz
600 MHz
800 MHz
1000 MHz
600 MHz
800 MHz
1000 MHz
300 MHz
600 MHz
800 MHz
300 MHz
600 MHz
800 MHz
600 MHz
800 MHz
1000 MHz
300 MHz
600 MHz
Frequency(1)
MIPS(2)
800 MHz
1600
600
1200
1600
2000
600
1200
1600
600
1200
1600
1200
1600
2000
600
1200
1200
1600
2000
On-chip L1 cache
On-chip L2 cache
64KB
64KB
64KB
64KB
64KB
64KB
64KB
256KB
256KB
256KB
256KB
256KB
256KB
256KB
Graphics accelerator
(SGX530)
—
—
3D
—
—
3D
3D
Crypto
accelerator
Crypto
accelerator
Crypto
accelerator
Crypto
accelerator
Crypto
accelerator
Crypto
accelerator
Crypto
accelerator
Hardware acceleration
Features
including basic
Industrial
Programmable real-time
unit subsystem and
industrial communication
subsystem (PRU-ICSS)
Features
including all
Industrial
Features
including basic
Industrial
Features
including all
Industrial
—
—
—
protocols;
ZCE: Limited
PRU I/Os pinned
out
protocols
protocols
protocols
On-chip memory
Display options
128KB
LCD
128KB
LCD
128KB
LCD
128KB
LCD
128KB
LCD
128KB
LCD
128KB
LCD
1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC, 1 16-bit (GPMC,
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
NAND flash,
NOR flash,
SRAM)
General-purpose memory
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
1 16-bit
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
(LPDDR-400,
DDR2-532,
DDR3-800)
DRAM(3)
No ZCE
Available
ZCZ: 2 ports
No ZCE
Available
ZCZ: 2 ports
No ZCE
Available
ZCZ: 2 ports
ZCE: 1 port
ZCZ: 2 ports
ZCE: 1 port
ZCZ: 2 ports
ZCE: 1 port
ZCZ: 2 ports
Universal serial bus (USB)
ZCE: 1 port
10/100/1000
No ZCE
Available
10/100/1000
No ZCE
Available
10/100/1000
No ZCE
Available
Ethernet media access
controller (EMAC) with 2-
port switch
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
10/100/1000
ZCE: 1 port
ZCZ: 2 ports
ZCZ: 2 ports
ZCZ: 2 ports
Multimedia card (MMC)
3
3
2
3
2
3
2
3
2
3
2
3
2
Controller-area network
(CAN)
—
Universal asynchronous
receiver and transmitter
(UART)
6
6
6
6
6
6
6
Analog-to-digital converter
(ADC)
8-ch 12-bit
8-ch 12-bit
8-ch 12-bit
8-ch 12-bit
8-ch 12-bit
8-ch 12-bit
8-ch 12-bit
Enhanced high-resolution
PWM modules
(eHRPWM)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Enhanced capture
modules (eCAP)
Enhanced quadrature
encoder pulse (eQEP)
3
1
3
3
1
3
3
1
3
3
1
3
3
1
3
3
1
3
3
1
3
Real-time clock (RTC)
Inter-integrated circuit
(I2C)
8
Device Comparison
版权 © 2011–2018, Texas Instruments Incorporated
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
FUNCTION
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 3-1. Device Features Comparison (continued)
AM3351
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
Multichannel audio serial
port (McASP)
2
2
2
2
2
2
2
Multichannel serial port
interface (McSPI)
2
2
2
2
2
2
2
Enhanced direct memory
access (EDMA)
64-Ch
64-Ch
64-Ch
64-Ch
64-Ch
64-Ch
64-Ch
Input/output (I/O) supply
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
1.8 V, 3.3 V
-40 to 125°C(4)
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
Operating temperature
range
0 to 90°C
–40 to 105°C
–40 to 105°C
–40 to 90°C
–40 to 105°C
–40 to 90°C
DEV_FEATURE register
value(5)
0x00FC0302
0x00FC0382
0x20FC0382
0x00FD0383
0x00FF0383
0x20FD0383
0x20FF0383
(1) Frequencies listed correspond to silicon revision 2.x. Earlier silicon revisions support 275 MHz, 500 MHz, 600 MHz, and 720 MHz.
(2) MIPS listed correspond to silicon revision 2.x. Earlier silicon revisions support 560, 1000, 1200, and 1440.
(3) DRAM speeds listed are data rates.
(4) Industrial extended temperature only supported for 300-MHz and 600-MHz frequencies.
(5) For more details about the DEV_FEATURE register, see the AM335x TRM.
3.1 Related Products
For information about other devices in this family of products, see the following links:
Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals,
connectivity and unified software support – perfect for sensors to servers.
TI's ARM Cortex-A8 Advantage The ARM Cortex-A8 core is highly-optimized by ARM for performance
and power efficiency. With the ability to scale in speed from 300 MHz to 1.35 GHz, the ARM
Cortex-A8-based processor can meet the requirements for power optimized devices with a
power budget of less than the Cortex-A8 core a dual-issue superscalar, achieving twice the
instructions executed per clock cycle at 2 DMIPS/MHz.
AM335x Sitara Processors Scalable ARM Cortex-A8-based core from 300 MHz up to 1 GHz, 3D
graphics option for enhanced user interface, dual-core PRU-ICSS for industrial Ethernet
protocols and position feedback control, and premium secure boot option.
Companion Products for AM335x Sitara Processors Review products that are frequently purchased or
used with this product.
TI Designs for AM335x Sitara Processors The TI Designs Reference Design Library is a robust
reference design library spanning analog, embedded processor and connectivity. Created by
TI experts to help you jump start your system design, all TI Designs include schematic or
block diagrams, BOMs and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
版权 © 2011–2018, Texas Instruments Incorporated
Device Comparison
9
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagram
注
The terms 'ball', 'pin', and 'terminal' are used interchangeably throughout the document. An
attempt is made to use 'ball' only when referring to the physical package.
4.1.1 ZCE Package Pin Maps (Top View)
The pin maps that follow show the pin assignments on the ZCE package in three sections (left, middle,
and right).
10
Terminal Configuration and Functions
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Table 4-1. ZCE Pin Map [Section Left - Top View]
A
B
C
D
E
F
19
18
17
16
15
14
13
12
11
10
9
VSS
SPI0_SCLK
SPI0_CS0
WARMRSTn
EMU0
I2C0_SCL
SPI0_D0
UART1_TXD
UART1_RTSn
UART0_RXD
ECAP0_IN_PWM0_OUT
UART1_CTSn
XXXX
UART0_CTSn
UART0_RTSn
UART0_TXD
VDDS
I2C0_SDA
EXTINTn
UART1_RXD
XXXX
SPI0_D1
SPI0_CS1
XDMA_EVENT_INTR1
TCK
XXXX
XXXX
XDMA_EVENT_INTR0
TMS
XXXX
PWRONRSTn
XXXX
XXXX
TDO
EMU1
VDDSHV6
VSS
TRSTn
TDI
CAP_VBB_MPU
VDDS_SRAM_MPU_BB
XXXX
CAP_VDD_SRAM_MPU
VDDS
VDDSHV6
VDDSHV6
VDDSHV6
VSS
AIN7
AIN5
VSS
AIN1
AIN3
XXXX
VDD_CORE
XXXX
AIN6
CAP_VDD_SRAM_CORE
VREFN
VDDS_SRAM_CORE_BG
XXXX
VSS
VREFP
XXXX
VSS
VDD_CORE
VSS
8
AIN2
AIN0
AIN4
VSSA_ADC
VDDA_ADC
CAP_VDD_RTC
XXXX
VSS
7
RTC_KALDO_ENn
RTC_XTALIN
RTC_XTALOUT
DDR_WEn
DDR_BA0
DDR_A5
VSS
RTC_PWRONRSTn
RESERVED
EXT_WAKEUP
DDR_BA2
DDR_A3
PMIC_POWER_EN
VDDS_RTC
VDDS_PLL_DDR
XXXX
VSS
VSS
6
XXXX
VSS
5
DDR_A4
XXXX
4
XXXX
XXXX
DDR_A12
DDR_A0
DDR_RASn
DDR_CASn
3
DDR_A8
XXXX
DDR_A15
DDR_A10
DDR_BA1
2
DDR_A9
DDR_CK
DDR_A7
DDR_A2
1
DDR_A6
DDR_CKn
Pin map section location
Left
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Terminal Configuration and Functions
11
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
ZCE Pin Map [Section Middle - Top View]
G
MMC0_CLK
MMC0_DAT0
MMC0_CMD
USB0_DRVVBUS
VDDSHV4
XXXX
H
J
K
L
M
19
18
17
16
15
14
13
12
11
10
9
MMC0_DAT3
MMC0_DAT2
MMC0_DAT1
VDDS_PLL_MPU
VDDSHV4
VDDSHV4
VDD_CORE
VDD_CORE
VSS
MII1_COL
MII1_RX_ER
MII1_RX_DV
MII1_TXD0
XXXX
MII1_RX_CLK
MII1_CRS
XXXX
RMII1_REF_CLK
MII1_TX_EN
VDD_CORE
VDD_CORE
XXXX
MII1_TXD1
MII1_TXD3
VDDS
XXXX
XXXX
VSS
VSS
VDDSHV5
VDDSHV5
VDD_CORE
VDD_CORE
VSS
VSS
VSS
XXXX
VDD_CORE
VDD_CORE
VSS
XXXX
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VDD_CORE
XXXX
VSS
VSS
XXXX
XXXX
XXXX
VSS
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VSS
8
VDD_CORE
VDD_CORE
VDDS_DDR
VDDS_DDR
DDR_VREF
DDR_A14
DDR_CSn0
DDR_A13
VDD_CORE
VDD_CORE
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VDD_CORE
VDDS_DDR
VDDS_DDR
DDR_D11
DDR_D10
DDR_D12
DDR_D13
7
XXXX
XXXX
6
XXXX
XXXX
5
VDDS_DDR
DDR_A11
DDR_CKE
DDR_RESETn
DDR_ODT
VSS
VDDS_DDR
VDDS_DDR
DDR_DQM1
DDR_D8
DDR_D9
VSS
4
XXXX
XXXX
3
XXXX
XXXX
2
DDR_A1
DDR_VTP
DDR_DQSn1
DDR_DQS1
1
Pin map section location
Middle
12
Terminal Configuration and Functions
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
ZCE Pin Map [Section Right - Top View]
N
P
R
MDC
T
USB0_VBUS
USB0_CE
XXXX
U
V
W
19
18
17
16
15
14
13
12
11
10
9
MII1_TX_CLK
MII1_RXD1
MII1_RXD0
MDIO
USB0_DP
USB0_ID
VSS
MII1_TXD2
MII1_RXD3
MII1_RXD2
VDDSHV5
XXXX
VDDA3P3V_USB0
VDDA1P8V_USB0
XXXX
USB0_DM
GPMC_CSn3
XXXX
GPMC_BEn1
GPMC_AD15
GPMC_CLK
GPMC_AD8
GPMC_CSn1
GPMC_AD4
GPMC_AD2
VSS_OSC
GPMC_WPn
GPMC_AD14
GPMC_AD9
GPMC_AD7
GPMC_AD5
GPMC_AD3
XTALOUT
VSSA_USB
XXXX
XXXX
GPMC_WAIT0
XXXX
XXXX
GPMC_CSn2
GPMC_AD6
GPMC_AD12
GPMC_AD11
XXXX
VSS
VDDS
XXXX
VSS
VDDSHV1
VDDSHV1
VDDSHV1
VSS
GPMC_AD13
GPMC_AD10
XXXX
VSS
VSS
VDD_CORE
XXXX
VDD_CORE
XXXX
XTALIN
VSS
VDDS_OSC
XXXX
GPMC_ADVn_ALE
GPMC_AD1
GPMC_BEn0_CLE
LCD_DATA15
LCD_DATA12
LCD_DATA11
LCD_DATA8
LCD_DATA6
LCD_DATA3
LCD_DATA2
GPMC_AD0
GPMC_OEn_REn
GPMC_CSn0
LCD_AC_BIAS_EN
LCD_DATA14
LCD_PCLK
LCD_DATA9
LCD_DATA5
LCD_DATA4
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV1
VDDSHV1
VDDSHV6
XXXX
XXXX
8
VDDS_PLL_CORE_LCD
LCD_HSYNC
VDDS
GPMC_WEn
LCD_VSYNC
LCD_DATA13
LCD_DATA10
XXXX
7
XXXX
VSS
6
XXXX
VDDSHV6
XXXX
5
VDDS_DDR
DDR_D0
DDR_DQM0
DDR_D14
DDR_D15
VPP
XXXX
4
DDR_D1
DDR_D4
DDR_D2
DDR_D3
XXXX
XXXX
3
DDR_D7
XXXX
LCD_DATA7
LCD_DATA1
LCD_DATA0
2
DDR_DQSn0
DDR_DQS0
DDR_D6
DDR_D5
1
Pin map section location
Right
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Terminal Configuration and Functions
13
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
4.1.2 ZCZ Package Pin Maps (Top View)
The pin maps that follow show the pin assignments on the ZCZ package in three sections (left, middle,
and right).
14
Terminal Configuration and Functions
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
ZCZ Pin Map [Section Left - Top View]
A
B
EXTINTn
C
ECAP0_IN_PWM0_OUT
I2C0_SDA
I2C0_SCL
D
UART1_CTSn
UART1_RTSn
UART1_RXD
E
UART0_CTSn
UART0_RTSn
UART0_TXD
UART0_RXD
VDDS
F
18
17
16
15
14
13
12
11
10
9
VSS
SPI0_SCLK
SPI0_CS0
MMC0_DAT2
MMC0_DAT3
USB0_DRVVBUS
USB1_DRVVBUS
VDDSHV6
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDDS
SPI0_D0
SPI0_D1
XDMA_EVENT_INTR0
MCASP0_AHCLKX
MCASP0_ACLKX
TCK
PWRONRSTn
EMU1
SPI0_CS1
EMU0
UART1_TXD
XDMA_EVENT_INTR1
MCASP0_AXR1
MCASP0_AXR0
CAP_VDD_SRAM_MPU
VDDS_SRAM_MPU_BB
CAP_VDD_SRAM_CORE
VDDA_ADC
MCASP0_FSX
MCASP0_ACLKR
TDI
MCASP0_FSR
MCASP0_AHCLKR
TMS
VDDSHV6
VDDSHV6
TDO
VDDSHV6
WARMRSTn
VREFN
TRSTn
CAP_VBB_MPU
AIN7
VDDSHV6
VREFP
VDDS_SRAM_CORE_BG
VSSA_ADC
VDDS_PLL_DDR
VDDS
8
AIN6
AIN5
AIN4
VSS
7
AIN3
AIN2
AIN1
VDDS_RTC
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_A10
6
RTC_XTALIN
VSS_RTC
AIN0
PMIC_POWER_EN
EXT_WAKEUP
DDR_BA0
CAP_VDD_RTC
DDR_A6
5
RTC_PWRONRSTn
RTC_KALDO_ENn
DDR_BA2
DDR_WEn
DDR_A5
VDDS_DDR
DDR_A2
4
RTC_XTALOUT
RESERVED
VDD_MPU_MON
VSS
DDR_A8
3
DDR_A3
DDR_A15
DDR_A12
DDR_A0
2
DDR_A4
DDR_CK
DDR_A7
DDR_A11
1
DDR_A9
DDR_CKn
DDR_BA1
DDR_CASn
Pin map section location
Left
Copyright © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
ZCZ Pin Map [Section Middle - Top View]
G
H
J
K
L
M
MDC
18
17
16
15
14
13
12
11
10
9
MMC0_CMD
MMC0_CLK
MMC0_DAT0
MMC0_DAT1
VDDSHV6
VDD_MPU
VSS
RMII1_REF_CLK
MII1_CRS
MII1_COL
VDDS_PLL_MPU
VDDSHV4
VDD_MPU
VSS
MII1_TXD3
MII1_TX_CLK
MII1_RX_CLK
MII1_RXD3
MII1_RXD2
MII1_RXD1
VDDSHV5
VSS
MII1_RX_DV
MII1_TX_EN
MII1_RX_ER
VDDSHV4
VDD_MPU
VDD_CORE
VSS
MII1_TXD0
MII1_TXD1
MII1_TXD2
VDDSHV5
VDDS
MDIO
MII1_RXD0
USB0_CE
VSSA_USB
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_D14
DDR_D13
DDR_DQSn1
DDR_DQS1
VSS
8
VSS
VSS
VSS
VDD_CORE
VSS
VSS
7
VDD_CORE
VDD_CORE
VDDS_DDR
DDR_RASn
DDR_CKE
DDR_RESETn
DDR_ODT
VSS
VSS
VSS
6
VSS
VSS
VDD_CORE
VDDS_DDR
DDR_D12
DDR_D11
DDR_D10
DDR_D9
VSS
5
VDDS_DDR
DDR_A14
DDR_A13
DDR_CSn0
DDR_A1
VDDS_DDR
DDR_VREF
DDR_VTP
DDR_DQM1
DDR_D8
VPP
4
DDR_D1
DDR_D0
DDR_DQM0
DDR_D15
3
2
1
Pin map section location
Middle
16
Terminal Configuration and Functions
Copyright © 2011–2018, Texas Instruments Incorporated
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
ZCZ Pin Map [Section Right - Top View]
N
P
R
USB1_DM
T
U
V
18
17
16
15
14
13
12
11
10
9
USB0_DM
USB0_DP
VDDA1P8V_USB0
VDDA3P3V_USB0
VSSA_USB
VDD_CORE
VDD_CORE
VSS
USB1_CE
USB1_ID
USB0_ID
USB0_VBUS
VDDS
USB1_VBUS
GPMC_WAIT0
GPMC_A10
GPMC_BEn1
GPMC_WPn
GPMC_A9
VSS
USB1_DP
GPMC_A11
GPMC_A8
GPMC_A5
GPMC_A1
GPMC_AD14
GPMC_CLK
VSS_OSC
XTALIN
VDDA1P8V_USB1
VDDA3P3V_USB1
GPMC_A4
GPMC_A7
GPMC_A6
GPMC_A3
GPMC_A2
VDDSHV3
VDDSHV3
VDDSHV2
VDDSHV2
VDDS
GPMC_A0
GPMC_CSn3
GPMC_AD12
GPMC_AD10
GPMC_AD9
GPMC_AD7
GPMC_AD3
GPMC_OEn_REn
GPMC_BEn0_CLE
LCD_DATA15
LCD_DATA7
LCD_DATA6
LCD_DATA5
LCD_DATA4
GPMC_AD15
GPMC_AD11
XTALOUT
GPMC_AD13
VDDS_OSC
VSS
VDDS_PLL_CORE_LCD
GPMC_AD6
GPMC_AD8
GPMC_CSn1
GPMC_AD4
GPMC_AD0
GPMC_WEn
LCD_VSYNC
LCD_DATA11
LCD_DATA10
LCD_DATA9
LCD_DATA8
VDD_CORE
VDD_CORE
VSS
GPMC_CSn2
GPMC_AD5
GPMC_AD1
GPMC_CSn0
LCD_PCLK
LCD_DATA14
LCD_DATA13
LCD_DATA12
VSS
8
VDDSHV1
VDDSHV1
VDDSHV6
VDDSHV6
DDR_D7
GPMC_AD2
7
GPMC_ADVn_ALE
LCD_AC_BIAS_EN
LCD_HSYNC
LCD_DATA3
6
VDDS
5
VDDSHV6
DDR_D5
4
3
DDR_D4
DDR_D6
LCD_DATA2
2
DDR_D3
DDR_DQSn0
DDR_DQS0
LCD_DATA1
1
DDR_D2
LCD_DATA0
Pin map section location
Right
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Terminal Configuration and Functions
17
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4.2 Pin Attributes
The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may
reference internal signal names when discussing peripheral input and output signals because many of the
AM335x package terminals can be multiplexed to one of several peripheral signals. The following table
has a Pin Name column that lists all device terminal names and a Signal Name column that lists all
internal signal names multiplexed to each terminal which provides a cross reference of internal signal
names to terminal names. This table also identifies other important terminal characteristics.
(1) BALL NUMBER: Package ball numbers associated with each signals.
(2) PIN NAME: The name of the package pin or terminal.
Note: The table does not take into account subsystem terminal multiplexing options.
(3) SIGNAL NAME: The signal name for that pin in the mode being used.
(4) MODE: Multiplexing mode number.
a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the terminal corresponds to the name of
the terminal. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default
mode.
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column.
b. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are effectively used for alternate
functions, while some modes are not used and do not correspond to a functional configuration.
(5) TYPE: Signal direction
–
–
–
–
–
–
–
–
I = Input
O = Output
I/O = Input and Output
D = Open drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
(6) BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
–
0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z: High-impedance
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
(7) BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal transitions from low to high.
–
0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z: High-impedance.
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
(8) RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal transitions from low to high.
(9) POWER: The voltage supply that powers the I/O buffers of the terminal.
(10) HYS: Indicates if the input buffer is with hysteresis.
(11) BUFFER STRENGTH: Drive strength of the associated output buffer.
(12) PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can
be enabled or disabled via software.
(13) I/O CELL: I/O cell information.
Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected results. This can be easily prevented
with the proper software configuration.
18
Terminal Configuration and Functions
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
Analog
STATE [6](25)
B8
B6
C7
B7
A7
C8
B8
A8
C9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
0
A (22)
Z
Z
0
0
0
0
0
0
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
NA
NA
NA
25
NA
A11
A8
0
0
0
0
0
0
0
A (21)
A (21)
A (20)
A (20)
A
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VDDA_ADC /
VDDA_ADC
25
NA
NA
NA
NA
NA
NA
NA
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B11
C8
VDDA_ADC /
VDDA_ADC
25
Analog
VDDA_ADC /
VDDA_ADC
25
Analog
B12
A10
A12
VDDA_ADC /
VDDA_ADC
NA
NA
NA
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
A
VDDA_ADC /
VDDA_ADC
Analog
C13
D6
C10
D6
CAP_VBB_MPU
CAP_VBB_MPU
CAP_VDD_RTC
NA
NA
NA
NA
0
A
A
A
A
O
CAP_VDD_RTC
B10
D13
F3
D9
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
DDR_A0
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
ddr_a0
D11
F3
H
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
J2
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
ddr_a1
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
ddr_a10
ddr_a11
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
O
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
D1
B3
E5
A2
B1
D2
C3
B2
E2
G4
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
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Terminal Configuration and Functions
19
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I/O CELL [13]
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_A12
SIGNAL NAME [3]
MODE [4]
STATE [6](25)
F4
H1
H3
E3
A3
E1
B4
F1
C2
G3
C1
H2
N4
P4
P2
P1
P3
T1
T2
R3
K2
K1
M3
E3
H3
H4
D3
C4
E1
B3
F1
D2
G3
D1
H2
M3
M4
N1
N2
N3
N4
P3
P4
J1
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
ddr_ck
0
O
O
O
O
O
O
O
O
O
O
O
O
H
1
1
1
1
1
1
1
1
0
0
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_DDR /
VDDS_DDR
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CASn
DDR_CK
DDR_CKE
DDR_CKn
DDR_CSn0
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H
H
H
H
H
H
H
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
ddr_cke
ddr_nck
ddr_csn0
ddr_d0
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
H
H
L
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS/SSTL/
HSTL
ddr_d1
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d2
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d3
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d4
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d5
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d6
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d7
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d8
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
K1
K2
ddr_d9
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
ddr_d10
L
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
20
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
DDR_D11
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
M4
M2
M1
N2
N1
N3
K3
R1
L1
K3
K4
L3
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_dqm0
ddr_dqm1
ddr_dqs0
ddr_dqs1
ddr_dqsn0
ddr_dqsn1
ddr_odt
0
I/O
L
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
Yes
NA
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
NA
LVCMOS/SSTL/
HSTL
DDR_D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I/O
I/O
I/O
I/O
O
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_D13
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
L4
DDR_D14
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
M1
M2
J2
DDR_D15
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_DQM0
DDR_DQM1
DDR_DQS0
DDR_DQS1
DDR_DQSn0
DDR_DQSn1
DDR_ODT
H
H
L
1
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
O
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
P1
L1
I/O
I/O
I/O
I/O
O
Z
0
VDDS_DDR /
VDDS_DDR
Yes
Yes
Yes
Yes
NA
LVCMOS/SSTL/
HSTL
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
R2
L2
P2
L2
H
H
L
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
Z
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
G1
F2
G1
G4
G2
J4
0
0
VDDS_DDR /
VDDS_DDR
LVCMOS/SSTL/
HSTL
DDR_RASn
DDR_RESETn
DDR_VREF
DDR_VTP
ddr_rasn
ddr_resetn
ddr_vref
ddr_vtp
O
H
L
1
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
G2
H4
J1
O
0
0
VDDS_DDR /
VDDS_DDR
NA
LVCMOS/SSTL/
HSTL
A (18) NA
NA
NA
1
NA
NA
0
VDDS_DDR /
VDDS_DDR
NA
NA
NA
8
Analog
J3
I (19)
O
NA
H
VDDS_DDR /
VDDS_DDR
NA
NA
Analog
A4
E18
B2
C18
DDR_WEn
ddr_wen
VDDS_DDR /
VDDS_DDR
NA
PU/PD
PU/PD
LVCMOS/SSTL/
HSTL
ECAP0_IN_PWM0_OUT
eCAP0_in_PWM0_out
uart3_txd
0
1
2
3
4
5
6
7
0
7
I/O
O
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
4
LVCMOS
spi1_cs1
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
spi1_sclk
mmc0_sdwp
xdma_event_intr2
gpio0_7
I
I/O
I/O
I/O
A15
C14
EMU0
EMU0
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpio3_7
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Terminal Configuration and Functions
21
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
D14
B14
EMU1
EMU1
gpio3_8
nNMI
0
I/O
H
H
0
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
7
0
I/O
I
C17
B5
B18
C5
EXTINTn
Z
L
L
H
Z
L
0
0
7
VDDSHV6 /
VDDSHV6
Yes
Yes
NA
NA
6
PU/PD
NA
LVCMOS
LVCMOS
LVCMOS
EXT_WAKEUP
GPMC_A0
EXT_WAKEUP
0
I
VDDS_RTC /
VDDS_RTC
NA
R13
gpmc_a0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
O
O
O
O
I
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
PU/PD
gmii2_txen
rgmii2_tctl
rmii2_txen
gpmc_a16
pr1_mii_mt1_clk
ehrpwm1_tripzone_input
gpio1_16
I
I/O
O
I
NA
NA
NA
V14
U14
T14
GPMC_A1
GPMC_A2
GPMC_A3
gpmc_a1
L
L
L
L
L
L
7
7
7
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
gmii2_rxdv
rgmii2_rctl
I
mmc2_dat0
gpmc_a17
pr1_mii1_txd3
ehrpwm0_synco
gpio1_17
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
O
O
O
I/O
gpmc_a2
gmii2_txd3
rgmii2_td3
mmc2_dat1
gpmc_a18
pr1_mii1_txd2
ehrpwm1A
gpio1_18
gpmc_a3
gmii2_txd2
rgmii2_td2
mmc2_dat2
gpmc_a19
pr1_mii1_txd1
ehrpwm1B
gpio1_19
22
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_A4
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
NA
NA
NA
NA
R14
V15
U15
T15
gpmc_a4
0
O
O
O
O
O
O
I
L
L
7
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gmii2_txd1
rgmii2_td1
rmii2_txd1
gpmc_a20
pr1_mii1_txd0
eQEP1A_in
gpio1_20
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
O
O
O
O
O
I
GPMC_A5
GPMC_A6
GPMC_A7
gpmc_a5
L
L
L
L
L
L
7
7
7
LVCMOS
LVCMOS
LVCMOS
gmii2_txd0
rgmii2_td0
rmii2_txd0
gpmc_a21
pr1_mii1_rxd3
eQEP1B_in
gpio1_21
I
I/O
O
I
gpmc_a6
gmii2_txclk
rgmii2_tclk
mmc2_dat4
gpmc_a22
pr1_mii1_rxd2
eQEP1_index
gpio1_22
O
I/O
O
I
I/O
I/O
O
I
gpmc_a7
gmii2_rxclk
rgmii2_rclk
mmc2_dat5
gpmc_a23
pr1_mii1_rxd1
eQEP1_strobe
gpio1_23
I
I/O
O
I
I/O
I/O
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
23
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_A8
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
NA
NA
NA
NA
V16
U16
T16
V17
gpmc_a8
0
O
I
L
L
L
L
L
7
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
NA / VDDSHV3 Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gmii2_rxd3
rgmii2_rd3
mmc2_dat6
gpmc_a24
pr1_mii1_rxd0
mcasp0_aclkx
gpio1_24
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
7
0
1
7
I
I/O
O
I
I/O
I/O
O
(10)
GPMC_A9
gpmc_a9
L
L
L
7
7
7
LVCMOS
LVCMOS
LVCMOS
gmii2_rxd2
rgmii2_rd2
I
I
mmc2_dat7 / rmii2_crs_dv
gpmc_a25
I/O
O
pr1_mii_mr1_clk
mcasp0_fsx
gpio1_25
I
I/O
I/O
O
GPMC_A10
gpmc_a10
gmii2_rxd1
rgmii2_rd1
rmii2_rxd1
I
I
I
gpmc_a26
O
pr1_mii1_rxdv
mcasp0_axr0
gpio1_26
I
I/O
I/O
O
GPMC_A11
gpmc_a11
gmii2_rxd0
rgmii2_rd0
rmii2_rxd0
I
I
I
gpmc_a27
O
pr1_mii1_rxer
mcasp0_axr1
gpio1_27
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W10
V9
U7
V7
GPMC_AD0
GPMC_AD1
gpmc_ad0
L
L
L
L
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
mmc1_dat0
gpio1_0
gpmc_ad1
VDDSHV1 /
VDDSHV1
mmc1_dat1
gpio1_1
24
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD2
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
V12
W13
V13
W14
U14
W15
V15
R8
gpmc_ad2
mmc1_dat2
gpio1_2
0
I/O
L
L
7
7
7
7
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
6
6
6
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
T8
GPMC_AD3
GPMC_AD4
GPMC_AD5
GPMC_AD6
GPMC_AD7
GPMC_AD8
gpmc_ad3
mmc1_dat3
gpio1_3
L
L
L
L
L
L
L
L
L
L
L
L
VDDSHV1 /
VDDSHV1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
U8
V8
R9
T9
gpmc_ad4
mmc1_dat4
gpio1_4
VDDSHV1 /
VDDSHV1
gpmc_ad5
mmc1_dat5
gpio1_5
VDDSHV1 /
VDDSHV1
gpmc_ad6
mmc1_dat6
gpio1_6
VDDSHV1 /
VDDSHV1
gpmc_ad7
mmc1_dat7
gpio1_7
VDDSHV1 /
VDDSHV1
U10
gpmc_ad8
lcd_data23
mmc1_dat0
mmc2_dat4
ehrpwm2A
VDDSHV1 /
VDDSHV2
I/O
I/O
O
pr1_mii_mt0_clk
gpio0_22
I
I/O
I/O
O
W16
T10
GPMC_AD9
gpmc_ad9
lcd_data22
mmc1_dat1
mmc2_dat5
ehrpwm2B
pr1_mii0_col
gpio0_23
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
I/O
I/O
O
I
I/O
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Terminal Configuration and Functions
25
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD10
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
T12
U12
U13
T11
U12
T12
gpmc_ad10
lcd_data21
mmc1_dat2
mmc2_dat6
0
I/O
L
L
L
L
7
7
7
VDDSHV1 /
VDDSHV2
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I/O
I/O
I
ehrpwm2_tripzone_input
pr1_mii0_txen
gpio0_26
O
I/O
I/O
O
GPMC_AD11
gpmc_ad11
L
VDDSHV1 /
VDDSHV2
LVCMOS
lcd_data20
mmc1_dat3
I/O
I/O
O
mmc2_dat7
ehrpwm0_synco
pr1_mii0_txd3
gpio0_27
O
I/O
I/O
O
GPMC_AD12
gpmc_ad12
L
VDDSHV1 /
VDDSHV2
LVCMOS
lcd_data19
mmc1_dat4
I/O
I/O
I
mmc2_dat0
eQEP2A_in
pr1_mii0_txd2
pr1_pru0_pru_r30_14
gpio1_12
O
O
I/O
I/O
O
T13
R12
GPMC_AD13
gpmc_ad13
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_data18
mmc1_dat5
I/O
I/O
I
mmc2_dat1
eQEP2B_in
pr1_mii0_txd1
pr1_pru0_pru_r30_15
gpio1_13
O
O
I/O
I/O
O
W17
V13
GPMC_AD14
gpmc_ad14
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_data17
mmc1_dat6
I/O
I/O
I/O
O
mmc2_dat2
eQEP2_index
pr1_mii0_txd0
pr1_pru0_pru_r31_14
gpio1_14
I
I/O
26
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD15
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
V17
U13
gpmc_ad15
lcd_data16
0
I/O
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
2
7
0
2
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
7
O
mmc1_dat7
mmc2_dat3
eQEP2_strobe
I/O
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
pr1_pru0_pru_r31_15
gpio1_15
I/O
O
V10
V8
R7
GPMC_ADVn_ALE
GPMC_BEn0_CLE
GPMC_BEn1
gpmc_advn_ale
timer4
H
H
H
H
H
H
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
I/O
I/O
O
gpio2_2
T6
gpmc_be0n_cle
timer5
VDDSHV1 /
VDDSHV1
I/O
I/O
O
gpio2_5
V18
U18
gpmc_be1n
gmii2_col
VDDSHV1 /
VDDSHV3
I
gpmc_csn6
mmc2_dat3
gpmc_dir
O
I/O
O
pr1_mii1_rxlink
mcasp0_aclkr
gpio1_28
I
I/O
I/O
I/O
O
V16
V12
GPMC_CLK
gpmc_clk
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_memory_clk
gpmc_wait1
mmc2_clk
I
I/O
I
pr1_mii1_crs
pr1_mdio_mdclk
mcasp0_fsr
gpio2_1
O
I/O
I/O
O
W8
V6
GPMC_CSn0
gpmc_csn0
gpio1_29
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
I/O
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
27
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_CSn1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
V14
U15
U17
U9
gpmc_csn1
gpmc_clk
mmc1_clk
0
O
H
H
H
H
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
2
7
0
1
2
3
4
5
6
7
0
2
7
I/O
I/O
I
pr1_edio_data_in6
pr1_edio_data_out6
pr1_pru1_pru_r30_12
pr1_pru1_pru_r31_12
gpio1_30
O
O
I
I/O
O
O
I/O
I
V9
GPMC_CSn2
gpmc_csn2
H
VDDSHV1 /
VDDSHV1
LVCMOS
gpmc_be1n
mmc1_cmd
pr1_edio_data_in7
pr1_edio_data_out7
pr1_pru1_pru_r30_13
pr1_pru1_pru_r31_13
gpio1_31
O
O
I
I/O
O
O
I
T13
GPMC_CSn3 (6)
gpmc_csn3
H
VDDSHV1 /
VDDSHV2
LVCMOS
gpmc_a3
rmii2_crs_dv
mmc2_cmd
I/O
I
pr1_mii0_crs
pr1_mdio_data
EMU4
I/O
I/O
I/O
O
I/O
I/O
I
gpio2_0
W9
T7
GPMC_OEn_REn
GPMC_WAIT0
gpmc_oen_ren
timer7
H
H
H
H
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
gpio2_3
R15
T17
gpmc_wait0
gmii2_crs
VDDSHV1 /
VDDSHV3
I
gpmc_csn4
O
I
rmii2_crs_dv
mmc1_sdcd
pr1_mii1_col
uart4_rxd
I
I
I
gpio0_30
I/O
O
I/O
I/O
U8
U6
GPMC_WEn
gpmc_wen
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
timer6
gpio2_4
28
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
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www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_WPn
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
W18
U17
gpmc_wpn
gmii2_rxerr
gpmc_csn5
rmii2_rxerr
mmc2_sdcd
pr1_mii1_txen
uart4_txd
0
O
I
H
H
7
VDDSHV1 /
VDDSHV3
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
O
I
I
O
O
gpio0_31
I/O
I/OD
I/O
I
C18
B19
W7
C17
C16
R6
I2C0_SDA
I2C0_SDA
timer4
Z
Z
Z
H
H
L
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
4
4
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
uart2_ctsn
eCAP2_in_PWM2_out
gpio3_5
I/O
I/O
I/OD
I/O
O
I2C0_SCL
I2C0_SCL
VDDSHV6 /
VDDSHV6
timer7
uart2_rtsn
eCAP1_in_PWM1_out
gpio3_6
I/O
I/O
O
LCD_AC_BIAS_EN
lcd_ac_bias_en
gpmc_a11
VDDSHV6 /
VDDSHV6
O
pr1_mii1_crs
I
pr1_edio_data_in5
pr1_edio_data_out5
pr1_pru1_pru_r30_11
pr1_pru1_pru_r31_11
gpio2_25
I
O
O
I
I/O
I/O
O
(5)
U1
R1
LCD_DATA0
lcd_data0
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a0
pr1_mii_mt0_clk
ehrpwm2A
I
O
pr1_pru1_pru_r30_0
pr1_pru1_pru_r31_0
gpio2_6
O
I
I/O
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Terminal Configuration and Functions
29
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
(5)
U2
V1
V2
W2
W3
R2
R3
R4
T1
T2
LCD_DATA1
lcd_data1
0
I/O
Z
Z
Z
Z
Z
Z
7
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
Yes
6
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
gpmc_a1
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
O
O
O
O
I
pr1_mii0_txen
ehrpwm2B
pr1_pru1_pru_r30_1
pr1_pru1_pru_r31_1
gpio2_7
I/O
I/O
O
O
I
(5)
(5)
(5)
(5)
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
lcd_data2
Z
Z
Z
Z
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpmc_a2
pr1_mii0_txd3
ehrpwm2_tripzone_input
pr1_pru1_pru_r30_2
pr1_pru1_pru_r31_2
gpio2_8
O
I
I/O
I/O
O
O
O
O
I
lcd_data3
VDDSHV6 /
VDDSHV6
gpmc_a3
pr1_mii0_txd2
ehrpwm0_synco
pr1_pru1_pru_r30_3
pr1_pru1_pru_r31_3
gpio2_9
I/O
I/O
O
O
I
lcd_data4
VDDSHV6 /
VDDSHV6
gpmc_a4
pr1_mii0_txd1
eQEP2A_in
pr1_pru1_pru_r30_4
pr1_pru1_pru_r31_4
gpio2_10
O
I
I/O
I/O
O
O
I
lcd_data5
VDDSHV6 /
VDDSHV6
gpmc_a5
pr1_mii0_txd0
eQEP2B_in
pr1_pru1_pru_r30_5
pr1_pru1_pru_r31_5
gpio2_11
O
I
I/O
30
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
(5)
V3
U3
V4
W4
T3
T4
U1
U2
LCD_DATA6
lcd_data6
gpmc_a6
0
I/O
Z
Z
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I
pr1_edio_data_in6
eQEP2_index
pr1_edio_data_out6
pr1_pru1_pru_r30_6
pr1_pru1_pru_r31_6
gpio2_12
I/O
O
O
I
I/O
I/O
O
I
(5)
(5)
(5)
LCD_DATA7
LCD_DATA8
LCD_DATA9
lcd_data7
Z
Z
Z
Z
Z
Z
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
gpmc_a7
pr1_edio_data_in7
eQEP2_strobe
pr1_edio_data_out7
pr1_pru1_pru_r30_7
pr1_pru1_pru_r31_7
gpio2_13
I/O
O
O
I
I/O
I/O
O
I
lcd_data8
VDDSHV6 /
VDDSHV6
gpmc_a12
ehrpwm1_tripzone_input
mcasp0_aclkx
uart5_txd
I/O
O
I
pr1_mii0_rxd3
uart2_ctsn
I
gpio2_14
I/O
I/O
O
O
I/O
I
lcd_data9
VDDSHV6 /
VDDSHV6
gpmc_a13
ehrpwm0_synco
mcasp0_fsx
uart5_rxd
pr1_mii0_rxd2
uart2_rtsn
I
O
I/O
gpio2_15
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
31
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产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA10 (5)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
U5
U3
lcd_data10
gpmc_a14
ehrpwm1A
mcasp0_axr0
pr1_mii0_rxd1
uart3_ctsn
gpio2_16
0
I/O
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
1
2
3
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
O
I/O
I
I
I/O
I/O
O
V5
U4
LCD_DATA11 (5)
LCD_DATA12 (5)
LCD_DATA13 (5)
lcd_data11
gpmc_a15
ehrpwm1B
Z
Z
Z
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
O
mcasp0_ahclkr
mcasp0_axr2
pr1_mii0_rxd0
uart3_rtsn
I/O
I/O
I
O
gpio2_17
I/O
I/O
O
V6
V2
lcd_data12
gpmc_a16
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
eQEP1A_in
mcasp0_aclkr
mcasp0_axr2
pr1_mii0_rxlink
uart4_ctsn
I
I/O
I/O
I
I
gpio0_8
I/O
I/O
O
U6
V3
lcd_data13
gpmc_a17
Z
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
eQEP1B_in
mcasp0_fsr
mcasp0_axr3
pr1_mii0_rxer
uart4_rtsn
I
I/O
I/O
I
O
gpio0_9
I/O
32
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
LCD_DATA14 (5)
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
W6
V4
T5
R5
V5
lcd_data14
gpmc_a18
0
I/O
Z
Z
7
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
I/O
I/O
I
eQEP1_index
mcasp0_axr1
uart5_rxd
pr1_mii_mr0_clk
uart5_ctsn
I
I
gpio0_10
I/O
I/O
O
I/O
I/O
I/O
I
V7
LCD_DATA15 (5)
LCD_HSYNC (7)
LCD_PCLK
lcd_data15
Z
Z
Z
Z
L
L
VDDSHV6 /
VDDSHV6
LVCMOS
LVCMOS
LVCMOS
gpmc_a19
eQEP1_strobe
mcasp0_ahclkx
mcasp0_axr3
pr1_mii0_rxdv
uart5_rtsn
O
I/O
O
O
O
I
gpio0_11
T7
lcd_hsync
VDDSHV6 /
VDDSHV6
gpmc_a9
gpmc_a2
pr1_edio_data_in3
pr1_edio_data_out3
pr1_pru1_pru_r30_9
pr1_pru1_pru_r31_9
gpio2_23
O
O
I
I/O
O
O
I
W5
lcd_pclk
VDDSHV6 /
VDDSHV6
gpmc_a10
pr1_mii0_crs
pr1_edio_data_in4
pr1_edio_data_out4
pr1_pru1_pru_r30_10
pr1_pru1_pru_r31_10
gpio2_24
I
O
O
I
I/O
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
33
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
(7)
U7
U5
LCD_VSYNC
lcd_vsync
gpmc_a8
gpmc_a1
0
O
O
O
I
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
pr1_edio_data_in2
pr1_edio_data_out2
pr1_pru1_pru_r30_8
pr1_pru1_pru_r31_8
gpio2_22
O
O
I
I/O
I/O
O
NA
B13
MCASP0_FSX
mcasp0_fsx
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
ehrpwm0B
spi1_d0
I/O
I
mmc1_sdcd
pr1_pru0_pru_r30_1
pr1_pru0_pru_r31_1
gpio3_15
O
I
I/O
I/O
I
NA
B12
MCASP0_ACLKR
mcasp0_aclkr
eQEP0A_in
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
mcasp0_axr2
I/O
I/O
I
mcasp1_aclkx
mmc0_sdwp
pr1_pru0_pru_r30_4
pr1_pru0_pru_r31_4
gpio3_18
O
I
I/O
I/O
I
NA
C12
MCASP0_AHCLKR
mcasp0_ahclkr
ehrpwm0_synci
mcasp0_axr2
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
I/O
I/O
I/O
O
spi1_cs0
eCAP2_in_PWM2_out
pr1_pru0_pru_r30_3
pr1_pru0_pru_r31_3
gpio3_17
I
I/O
34
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
NA
A14
MCASP0_AHCLKX
mcasp0_ahclkx
0
I/O
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
eQEP0_strobe
mcasp0_axr3
mcasp1_axr1
EMU4
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
3
4
5
6
7
I/O
I/O
I/O
I/O
O
pr1_pru0_pru_r30_7
pr1_pru0_pru_r31_7
gpio3_21
I
I/O
I/O
O
NA
A13
MCASP0_ACLKX
mcasp0_aclkx
ehrpwm0A
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
spi1_sclk
I/O
I
mmc0_sdcd
pr1_pru0_pru_r30_0
pr1_pru0_pru_r31_0
gpio3_14
O
I
I/O
I/O
I
NA
C13
MCASP0_FSR
mcasp0_fsr
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
eQEP0B_in
mcasp0_axr3
mcasp1_fsx
I/O
I/O
I/O
O
EMU2
pr1_pru0_pru_r30_5
pr1_pru0_pru_r31_5
gpio3_19
I
I/O
I/O
I
NA
D12
MCASP0_AXR0
mcasp0_axr0
ehrpwm0_tripzone_input
spi1_d1
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
I/O
I
mmc2_sdcd
pr1_pru0_pru_r30_2
pr1_pru0_pru_r31_2
gpio3_16
O
I
I/O
I/O
I/O
I/O
I/O
O
NA
D13
MCASP0_AXR1
mcasp0_axr1
eQEP0_index
mcasp1_axr0
EMU3
L
L
7
NA / VDDSHV6 Yes
6
PU/PD
LVCMOS
pr1_pru0_pru_r30_6
pr1_pru0_pru_r31_6
gpio3_20
I
I/O
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
35
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
R19
P17
L19
K17
M18
M17
J17
MDC
mdio_clk
0
O
H
H
H
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
timer5
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
O
uart5_txd
uart3_rtsn
mmc0_sdwp
mmc1_clk
mmc2_clk
gpio0_1
O
I
I/O
I/O
I/O
I/O
I/O
I
MDIO
mdio_data
timer6
H
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
uart5_rxd
uart3_ctsn
mmc0_sdcd
mmc1_cmd
mmc2_cmd
gpio0_0
I
I
I/O
I/O
I/O
I
MII1_RX_DV
gmii1_rxdv
VDDSHV5 /
VDDSHV5
lcd_memory_clk
rgmii1_rctl
uart5_txd
O
I
O
mcasp1_aclkx
mmc2_dat0
mcasp0_aclkr
gpio3_4
I/O
I/O
I/O
I/O
O
J16
MII1_TX_EN
gmii1_txen
rmii1_txen
rgmii1_tctl
timer4
L
VDDSHV5 /
VDDSHV5
O
O
I/O
I/O
I/O
I/O
I/O
mcasp1_axr0
eQEP0_index
mmc2_cmd
gpio3_3
36
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_RX_ER
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
K19
M19
N19
J19
J15
L18
K18
H16
gmii1_rxerr
rmii1_rxerr
spi1_d1
0
I
I
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I/OD
I/O
O
I2C1_SCL
mcasp1_fsx
uart5_rtsn
uart2_txd
O
gpio3_2
I/O
I
MII1_RX_CLK
MII1_TX_CLK
MII1_COL
gmii1_rxclk
uart2_txd
L
L
L
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
O
rgmii1_rclk
mmc0_dat6
mmc1_dat1
uart1_dsrn
mcasp0_fsx
gpio3_10
I
I/O
I/O
I
I/O
I/O
I
gmii1_txclk
uart2_rxd
VDDSHV5 /
VDDSHV5
I
rgmii1_tclk
mmc0_dat7
mmc1_dat0
uart1_dcdn
mcasp0_aclkx
gpio3_9
O
I/O
I/O
I
I/O
I/O
I
gmii1_col
VDDSHV5 /
VDDSHV5
rmii2_refclk
spi1_sclk
I/O
I/O
I
uart5_rxd
mcasp1_axr2
mmc2_dat3
mcasp0_axr2
gpio3_0
I/O
I/O
I/O
I/O
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
37
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_CRS
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
J18
P18
P19
N16
H17
M16
L15
L16
gmii1_crs
rmii1_crs_dv
spi1_d0
0
I
I
L
L
L
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I/OD
I/O
I
I2C1_SDA
mcasp1_aclkx
uart5_ctsn
uart2_rxd
I
gpio3_1
I/O
I
MII1_RXD0
MII1_RXD1
MII1_RXD2
gmii1_rxd0
rmii1_rxd0
rgmii1_rd0
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
I
I
mcasp1_ahclkx
mcasp1_ahclkr
mcasp1_aclkr
mcasp0_axr3
gpio2_21
I/O
I/O
I/O
I/O
I/O
I
gmii1_rxd1
rmii1_rxd1
VDDSHV5 /
VDDSHV5
I
rgmii1_rd1
mcasp1_axr3
mcasp1_fsr
eQEP0_strobe
mmc2_clk
I
I/O
I/O
I/O
I/O
I/O
I
gpio2_20
gmii1_rxd2
uart3_txd
VDDSHV5 /
VDDSHV5
O
rgmii1_rd2
mmc0_dat4
mmc1_dat3
uart1_rin
I
I/O
I/O
I
mcasp0_axr1
gpio2_19
I/O
I/O
38
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_RXD3
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
N17
L18
M18
N18
L17
K17
K16
K15
gmii1_rxd3
uart3_rxd
0
I
I
I
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
rgmii1_rd3
mmc0_dat5
mmc1_dat2
uart1_dtrn
mcasp0_axr0
gpio2_18
I/O
I/O
O
I/O
I/O
O
MII1_TXD0
MII1_TXD1
MII1_TXD2
gmii1_txd0
rmii1_txd0
rgmii1_td0
mcasp1_axr2
mcasp1_aclkr
eQEP0B_in
mmc1_clk
gpio0_28
L
L
L
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
O
O
I/O
I/O
I
I/O
I/O
O
gmii1_txd1
rmii1_txd1
rgmii1_td1
mcasp1_fsr
mcasp1_axr1
eQEP0A_in
mmc1_cmd
gpio0_21
VDDSHV5 /
VDDSHV5
O
O
I/O
I/O
I
I/O
I/O
O
gmii1_txd2
dcan0_rx
VDDSHV5 /
VDDSHV5
I
rgmii1_td2
uart4_txd
O
O
mcasp1_axr0
mmc2_dat2
I/O
I/O
I/O
I/O
mcasp0_ahclkx
gpio0_17
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
39
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_TXD3
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
M17
G17
G19
G18
J18
gmii1_txd3
dcan0_tx
0
O
O
O
I
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
rgmii1_td3
uart4_rxd
mcasp1_fsx
mmc2_dat1
mcasp0_fsr
gpio0_16
I/O
I/O
I/O
I/O
I/O
O
O
O
I
G18
G17
G16
MMC0_CMD
MMC0_CLK
MMC0_DAT0
mmc0_cmd
gpmc_a25
uart3_rtsn
uart2_txd
H
H
H
H
H
H
VDDSHV4 /
VDDSHV4
LVCMOS
LVCMOS
LVCMOS
dcan1_rx
pr1_pru0_pru_r30_13
pr1_pru0_pru_r31_13
gpio2_31
O
I
I/O
I/O
O
I
mmc0_clk
VDDSHV4 /
VDDSHV4
gpmc_a24
uart3_ctsn
uart2_rxd
I
dcan1_tx
O
O
I
pr1_pru0_pru_r30_12
pr1_pru0_pru_r31_12
gpio2_30
I/O
I/O
O
O
O
I
mmc0_dat0
VDDSHV4 /
VDDSHV4
gpmc_a23
uart5_rtsn
uart3_txd
uart1_rin
pr1_pru0_pru_r30_11
pr1_pru0_pru_r31_11
gpio2_29
O
I
I/O
40
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MMC0_DAT1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
H17
H18
H19
G15
F18
F17
mmc0_dat1
gpmc_a22
uart5_ctsn
uart3_rxd
0
I/O
H
H
7
7
7
VDDSHV4 /
VDDSHV4
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
O
I
I
uart1_dtrn
O
O
I
pr1_pru0_pru_r30_10
pr1_pru0_pru_r31_10
gpio2_28
I/O
I/O
O
O
I/O
I
MMC0_DAT2
mmc0_dat2
H
H
VDDSHV4 /
VDDSHV4
LVCMOS
gpmc_a21
uart4_rtsn
timer6
uart1_dsrn
pr1_pru0_pru_r30_9
pr1_pru0_pru_r31_9
gpio2_27
O
I
I/O
I/O
O
I
MMC0_DAT3
mmc0_dat3
H
H
VDDSHV4 /
VDDSHV4
LVCMOS
gpmc_a20
uart4_ctsn
timer5
I/O
I
uart1_dcdn
pr1_pru0_pru_r30_8
pr1_pru0_pru_r31_8
gpio2_26
O
I
I/O
O
C7
C6
PMIC_POWER_EN
PWRONRSTn
PMIC_POWER_EN
H
1
0
VDDS_RTC /
VDDS_RTC
NA
NA
LVCMOS
LVCMOS
Analog
E15
B6
B15
A3
porz
0
0
I
Z
Z
0
VDDSHV6 /
Yes
NA
NA
NA
6
NA
VDDSHV6 (12)
(3)
RESERVED
testout
O
NA
L
NA
L
NA
7
VDDSHV6 /
VDDSHV6
NA
K18
H18
RMII1_REF_CLK
rmii1_refclk
0
1
2
3
4
5
6
7
0
I/O
I
VDDSHV5 /
VDDSHV5
Yes
PU/PD
LVCMOS
xdma_event_intr2
spi1_cs0
I/O
O
uart5_txd
mcasp1_axr3
mmc0_pow
I/O
O
mcasp1_ahclkx
gpio0_29
I/O
I/O
I
A7
B4
RTC_KALDO_ENn
ENZ_KALDO_1P8V
Z
Z
0
VDDS_RTC /
VDDS_RTC
NA
NA
NA
Analog
版权 © 2011–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
41
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
www.ti.com.cn
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
RTC_PWRONRSTn
RTC_XTALIN
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
LVCMOS
STATE [6](25)
B7
B5
RTC_PORz
OSC1_IN
0
I
Z
Z
0
0
0
7
VDDS_RTC /
VDDS_RTC
Yes
Yes
NA
NA
NA
(1)
A6
A6
0
0
I
H
H
VDDS_RTC /
VDDS_RTC
NA
PU
NA
LVCMOS
A5
A4
RTC_XTALOUT
SPI0_SCLK
OSC1_OUT
O
Z (23)
Z
Z (23)
H
VDDS_RTC /
VDDS_RTC
NA (15)
6
LVCMOS
A18
A17
spi0_sclk
uart2_rxd
I2C2_SDA
ehrpwm0A
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I
VDDSHV6 /
VDDSHV6
Yes
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
I/OD
O
pr1_uart0_cts_n
pr1_edio_sof
EMU2
I
O
I/O
I/O
I/O
I
gpio0_2
A17
B16
B18
A16
C15
B17
SPI0_CS0
SPI0_CS1
SPI0_D0
spi0_cs0
Z
Z
Z
H
H
H
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
6
6
6
LVCMOS
LVCMOS
LVCMOS
mmc2_sdwp
I2C1_SCL
I/OD
I
ehrpwm0_synci
pr1_uart0_txd
pr1_edio_data_in1
pr1_edio_data_out1
gpio0_5
O
I
O
I/O
I/O
I
spi0_cs1
VDDSHV6 /
VDDSHV6
uart3_rxd
eCAP1_in_PWM1_out
mmc0_pow
xdma_event_intr2
mmc0_sdcd
EMU4
I/O
O
I
I
I/O
I/O
I/O
O
gpio0_6
spi0_d0
VDDSHV6 /
VDDSHV6
uart2_txd
I2C2_SCL
I/OD
O
ehrpwm0B
pr1_uart0_rts_n
pr1_edio_latch_in
EMU3
O
I
I/O
I/O
gpio0_3
42
Terminal Configuration and Functions
版权 © 2011–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
www.ti.com.cn
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SPI0_D1
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
B17
B16
spi0_d1
0
I/O
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
6
PU/PD
LVCMOS
mmc1_sdwp
I2C1_SDA
1
2
3
4
5
6
7
0
I
I/OD
ehrpwm0_tripzone_input
pr1_uart0_rxd
pr1_edio_data_in0
pr1_edio_data_out0
gpio0_4
I
I
I
O
I/O
I
B14
B13
A14
C14
A13
F17
A12
B11
A11
C11
B10
E16
TCK
TCK
H
H
H
H
L
H
H
H
H
L
0
0
0
0
0
7
VDDSHV6 /
VDDSHV6
Yes
Yes
NA
NA
NA
4
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TDI
TDI
0
0
0
0
I
VDDSHV6 /
VDDSHV6
TDO
TDO
TMS
nTRST
O
I
VDDSHV6 /
VDDSHV6
TMS
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
NA
NA
4
TRSTn
UART0_TXD
I
VDDSHV6 /
VDDSHV6
uart0_txd
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
Z
H
VDDSHV6 /
VDDSHV6
spi1_cs1
I/O
I
dcan0_rx
I2C2_SCL
I/OD
I/O
O
eCAP1_in_PWM1_out
pr1_pru1_pru_r30_15
pr1_pru1_pru_r31_15
gpio1_11
I
I/O
I
F19
E18
UART0_CTSn
uart0_ctsn
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
uart4_rxd
I
dcan1_tx
O
I2C1_SDA
I/OD
I/O
I/O
O
spi1_d0
timer7
pr1_edc_sync0_out
gpio1_8
I/O
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表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
UART0_RXD
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
E19
E15
uart0_rxd
spi1_cs0
dcan0_tx
I2C2_SDA
0
I
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
6
7
I/O
O
I/OD
I/O
O
eCAP2_in_PWM2_out
pr1_pru1_pru_r30_14
pr1_pru1_pru_r31_14
gpio1_10
I
I/O
O
F18
E17
UART0_RTSn
uart0_rtsn
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
uart4_txd
O
dcan1_rx
I
I2C1_SCL
I/OD
I/O
I/O
O
spi1_d1
spi1_cs0
pr1_edc_sync1_out
gpio1_9
I/O
O
C19
D18
D19
D15
D16
D17
UART1_TXD
UART1_RXD
UART1_RTSn
uart1_txd
Z
Z
Z
H
H
H
7
7
7
VDDSHV6 /
VDDSHV6
Yes
Yes
Yes
4
4
4
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
mmc2_sdwp
dcan1_rx
I
I
I2C1_SCL
I/OD
O
pr1_uart0_txd
pr1_pru0_pru_r31_16
gpio0_15
I
I/O
I
uart1_rxd
VDDSHV6 /
VDDSHV6
mmc1_sdwp
dcan1_tx
I
O
I2C1_SDA
I/OD
I
pr1_uart0_rxd
pr1_pru1_pru_r31_16
gpio0_14
I
I/O
O
uart1_rtsn
VDDSHV6 /
VDDSHV6
timer5
I/O
I
dcan0_rx
I2C2_SCL
I/OD
I/O
O
spi1_cs1
pr1_uart0_rts_n
pr1_edc_latch1_in
gpio0_13
I
I/O
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表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
UART1_CTSn
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
STATE [6](25)
E17
D18
uart1_ctsn
timer6
0
I
Z
H
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
I/O
O
dcan0_tx
I2C2_SDA
spi1_cs0
I/OD
I/O
I
pr1_uart0_cts_n
pr1_edc_latch0_in
gpio0_12
I
I/O
A
T18
T19
U18
M15
P15
N18
USB0_CE
USB0_CE
Z
Z
Z
Z
Z
Z
0
0
0
VDDA*_USB0 / NA
NA
NA
NA
NA
NA
Analog
Analog
Analog
VDDA*_USB0
(26)
USB0_VBUS
USB0_DM
USB0_VBUS
USB0_DM
0
0
A
A
VDDA*_USB0 / NA
VDDA*_USB0
(26)
(13)
(16)
VDDA*_USB0 / Yes
8
(16)
VDDA*_USB0
(26)
G16
V19
F16
P16
USB0_DRVVBUS
USB0_ID
USB0_DRVVBUS
gpio0_18
0
7
0
O
L
Z
0(PD)
Z
0
0
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
NA
LVCMOS
Analog
I/O
A
USB0_ID
VDDA*_USB0 / NA
NA
VDDA*_USB0
(26)
(13)
(16)
U19
NA
NA
NA
NA
N17
P18
P17
T18
R17
USB0_DP
USB1_CE
USB1_ID
USB0_DP
USB1_CE
USB1_ID
0
0
0
0
0
A
A
A
A
A
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
VDDA*_USB0 / Yes
8
NA
NA
NA
NA
NA
Analog
Analog
Analog
Analog
Analog
(16)
VDDA*_USB0
(26)
NA /
NA
NA
NA
NA
NA
NA
VDDA*_USB1
(27)
NA /
VDDA*_USB1
(27)
USB1_VBUS
USB1_DP
USB1_VBUS
USB1_DP
NA /
VDDA*_USB1
(27)
(14)
(17)
NA /
Yes
8
(17)
VDDA*_USB1
(27)
NA
NA
F15
R18
USB1_DRVVBUS
USB1_DM
USB1_DRVVBUS
gpio3_13
0
7
0
O
L
Z
0(PD)
Z
0
0
NA / VDDSHV6 Yes
4
8
PU/PD
NA
LVCMOS
Analog
I/O
A
(14)
(17)
USB1_DM
NA /
VDDA*_USB1
Yes
(17)
(27)
R17
NA
N16
R16
N15
R15
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
NA
NA
NA
NA
PWR
PWR
PWR
PWR
R18
NA
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I/O CELL [13]
表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
NUMBER [1] NUMBER [1]
STATE [6](25)
D7
D8
VDDA_ADC
VDDA_ADC
VDDS
NA
PWR
PWR
D12, F16,
M16, T6, T14 K13, N6, P9,
P14
E6, E14, F9, VDDS
NA
NA
R8, R9, R11, P7, P8
R12, R13
VDDSHV1
VDDSHV1
PWR
NA
NA
P10, P11
P12, P13
H14, J14
VDDSHV2
VDDSHV3
VDDSHV4
VDDSHV2
VDDSHV3
VDDSHV4
NA
NA
NA
PWR
PWR
PWR
G15, H14,
H15
M14, M15,
N15
K14, L14
E10, E11,
VDDSHV5
VDDSHV6
VDDSHV5
VDDSHV6
NA
NA
PWR
PWR
E11, E12,
E13, F14, P6, E12, E13,
R7
F14, G14, N5,
P5, P6
G5, H5, H6,
K4, K5, M5,
M6, N5
E5, F5, G5,
H5, J5, K5, L5
VDDS_DDR
VDDS_DDR
VDDS_OSC
NA
PWR
U10
T8
R11
R10
E7
VDDS_OSC
NA
NA
NA
NA
NA
NA
NA
NA
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_RTC
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
C5
H16
C6
H15
D7
VDDS_PLL_MPU
VDDS_RTC
C10
C12
E9
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDD_CORE
D10
F9, F11, G9, F6, F7, G6,
G11, H7, H8, G7, G10,
H12, H13, J7, H11, J12, K6,
J8, J12, J13, K8, K12, L6,
K15, K16, L7, L7, L8, L9,
L8, L12, L13, M11, M13,
M7, M8, M12, N8, N9, N12,
M13, N9,
N13
N11, P9, P11
NA
F10, F11,
F12, F13,
G13, H13,
J13
VDD_MPU
VDD_MPU (30)
NA
PWR
NA
R5
B9
A2
M5
A9
VDD_MPU_MON
VPP
VDD_MPU_MON (31)
VPP
NA
NA
0
A
PWR
AP
VREFN
VREFN
Z
Z
Z
0
0
VDDA_ADC /
VDDA_ADC
NA
NA
NA
NA
NA
NA
Analog
Analog
A9
B9
VREFP
VREFP
0
AP
Z
VDDA_ADC /
VDDA_ADC
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表 4-2. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
[5]
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
NA
I/O CELL [13]
STATE [6](25)
A1, A19, D10, A1, A18, F8, VSS
VSS
GND
E7, E8, E9,
G8, G9, G11,
E10, F6, F7, G12, H6, H7,
F8, F12, F13, H8, H9, H10,
G8, G12, H9, H12, J6, J7,
H10, H11, J5, J8, J9, J10,
J6, J9, J11,
J11, K7, K9,
J14, J15, K8, K10, K11,
K9, K11, K12, L10, L11, L12,
L5, L6, L9,
L13, M6, M7,
L11, L14, L15, M8, M9, M10,
M9, M10,
M11, N8,
M12, N7,
N10, N11, V1,
N12, P7, P8, V18
P12, P13,
P14, R10,
T10, W1, W19
D8
E8
VSSA_ADC
VSSA_ADC
VSSA_USB
VSS_OSC (28)
NA
NA
NA
NA
0
GND
GND
A
P16
V11
NA
M14, N14
V11
VSSA_USB
VSS_OSC
VSS_RTC
(29)
A5
VSS_RTC
A
A16
A10
WARMRSTn
nRESETIN_OUT
I/OD
0
0(PU) (11)
0
VDDSHV6 /
VDDSHV6
Yes
Yes
4
4
PU/PD
PU/PD
LVCMOS
LVCMOS
(8)
(4)
(9)
C15
A15
XDMA_EVENT_INTR0
xdma_event_intr0
timer4
0
2
3
4
5
6
7
0
2
3
4
5
6
7
0
I
Z
VDDSHV6 /
VDDSHV6
I/O
O
I/O
I
clkout1
spi1_cs1
pr1_pru1_pru_r31_16
EMU2
I/O
I/O
I
gpio0_19
B15
D14
XDMA_EVENT_INTR1
xdma_event_intr1
tclkin
Z
L
7
VDDSHV6 /
VDDSHV6
Yes
4
PU/PD
LVCMOS
I
clkout2
O
I/O
I
timer7
pr1_pru0_pru_r31_16
EMU3
I/O
I/O
I
gpio0_20
(2)
W11
W12
V10
U11
XTALIN
OSC0_IN
Z
Z
0
0
VDDS_OSC /
VDDS_OSC
Yes
NA
NA
PD
LVCMOS
LVCMOS
(24)
(24)
XTALOUT
OSC0_OUT
0
O
VDDS_OSC /
VDDS_OSC
NA (15)
NA
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(1) An internal 10 kohm pullup is turned on when the oscillator is disabled. The oscillator is disabled by default after power is applied.
(2) An internal 15 kohm pulldown is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
(3) Do not connect anything to this terminal.
(4) If sysboot[5] is low on the rising edge of PWRONRSTn, this terminal has an internal pulldown turned on after reset is released. If sysboot[5] is high on the rising edge or PWRONRSTn,
this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the XTALIN terminal.
(5) LCD_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
(6) Mode1 and Mode2 signal assignments for this terminal are only available with silicon revision 2.0 or newer devices.
(7) Mode2 signal assignment for this terminal is only available with silicon revision 2.0 or newer devices.
(8) Refer to the External Warm Reset section of the AM335x Technical Reference Manual for more information related to the operation of this terminal.
(9) Reset Release Mode = 7 if sysboot[5] is low. Mode = 3 if sysboot[5] is high.
(10) Silicon revision 1.0 devices only provide the MMC2_DAT7 signal when Mode3 is selected. Silicon revision 2.0 and newer devices implement another level of pin multiplexing which
provides the original MMC2_DAT7 signal or RMII2_CRS_DV signal when Mode3 is selected. This new level of of pin multiplexing is selected with bit zero of the SMA2 register. For more
details refer to Section 1.2 of the AM335x Technical Reference Manual.
(11) The 0(PU) indicates that this terminal is initially low based on the description in the AM335x Technical Reference Manual. However, it is also has a weak internal pullup applied.
(12) The input voltage thresholds for this input are not a function of VDDSHV6. Please refer to the DC Electrical Characteristics section for details related to electrical parameters associated
with this input terminal.
(13) The internal USB PHY can be configured to multiplex the UART2_TX or UART2_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x Technical
Reference Manual.
(14) The internal USB PHY can be configured to multiplex the UART3_TX or UART3_RX signals to this terminal. For more details refer to USB GPIO Details section of the AM335x Technical
Reference Manual.
(15) This output should only be used to source the recommended crystal circuit.
(16) This parameter only applies when this USB PHY terminal is operating in UART2 mode.
(17) This parameter only applies when this USB PHY terminal is operating in UART3 mode.
(18) This terminal is a analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
(19) This terminal is a analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
(20) This terminal is analog input that may also be configured as an open-drain output.
(21) This terminal is analog input that may also be configured as an open-source or open-drain output.
(22) This terminal is analog input that may also be configured as an open-source output.
(23) This terminal is high-Z when the oscillator is disabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a
unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
(24) This terminal is high-Z when the oscillator is disabled. This terminal is driven high if XTALIN is less than VIL, driven low if XTALIN is greater than VIH, and driven to a unknown value if
XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is enabled by default after power is applied.
(25) For all pins with content in the Ball Reset State column of this table, the terminal is not defined until all the supplies are ramped.
(26) This terminal requires two power supplies, VDDA3p3v_USB0 and VDDA1p8v_USB0. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
(27) This terminal requires two power supplies, VDDA3p3v_USB1 and VDDA1p8v_USB1. The "*" character in the power supply name is a wild card that represents "3p3v" and "1p8v".
(28) Refer to 节 6.2.2 for additional details about VSS_OSC.
(29) Refer to 节 6.2.2 for additional details about VSS_RTC.
(30) This power rail is connected to VDD_CORE in the ZCE package.
(31) This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the
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PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.
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4.3 Signal Descriptions
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The
Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin-
multiplexing configuration selected for a design only uses valid I/O Sets supported by the AM335x device.
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(1) SIGNAL NAME: The signal name
(2) DESCRIPTION: Description of the signal
(3) TYPE: Ball type for this specific function:
–
–
–
–
–
–
I = Input
O = Output
I/O = Input/Output
D = Open drain
DS = Differential
A = Analog
(4) BALL: Package ball location
Table 4-3. ADC Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
Analog Input/Output
ZCE BALL [4]
B8
ZCZ BALL [4]
B6
AIN0
A
A
A
A
A
A
A
A
AIN1
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input
A11
A8
C7
B7
A7
C8
B8
A8
C9
A9
B9
AIN2
AIN3
B11
C8
AIN4
AIN5
B12
A10
A12
B9
AIN6
Analog Input
AIN7
Analog Input
VREFN
VREFP
Analog Negative Reference Input
Analog Positive Reference Input
AP
AP
A9
Table 4-4. Debug Subsystem Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
A15
ZCZ BALL [4]
EMU0
EMU1
EMU2
EMU3
EMU4
nTRST
TCK
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
JTAG TEST RESET (ACTIVE LOW)
JTAG TEST CLOCK
I/O
I/O
I/O
I/O
I/O
I
C14
D14
B14
A18, C15
B15, B18
B16, U17
A13
A15, A17, C13
B17, D13, D14
A14, C15, T13
B10
I
B14
A12
TDI
JTAG TEST DATA INPUT
JTAG TEST DATA OUTPUT
JTAG TEST MODE SELECT
I
B13
B11
TDO
O
I
A14
A11
TMS
C14
C11
Table 4-5. LCD Controller Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
lcd_ac_bias_en
lcd_data0
LCD AC bias enable chip select
LCD data bus
O
W7
U1
U2
U5
V5
R6
R1
R2
U3
U4
V2
V3
V4
T5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
lcd_data1
LCD data bus
lcd_data10
lcd_data11
lcd_data12
lcd_data13
lcd_data14
lcd_data15
lcd_data16
LCD data bus
LCD data bus
LCD data bus
V6
LCD data bus
U6
W6
V7
LCD data bus
LCD data bus
LCD data bus
V17
U13
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ZCZ BALL [4]
Table 4-5. LCD Controller Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
lcd_data17
DESCRIPTION [2]
ZCE BALL [4]
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
LCD data bus
O
W17
V13
lcd_data18
lcd_data19
lcd_data2
lcd_data20
lcd_data21
lcd_data22
lcd_data23
lcd_data3
lcd_data4
lcd_data5
lcd_data6
lcd_data7
lcd_data8
lcd_data9
lcd_hsync
lcd_memory_clk
lcd_pclk
O
T13
U13
V1
R12
T12
R3
O
I/O
O
U12
T12
W16
V15
V2
U12
T11
T10
U10
R4
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
W2
W3
V3
T1
T2
T3
U3
T4
V4
U1
W4
T7
U2
LCD Horizontal Sync
LCD MCLK
R5
O
L19, V16
W5
U7
J17, V12
V5
LCD pixel clock
LCD Vertical Sync
O
lcd_vsync
O
U5
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
4.3.1 External Memory Interfaces
Table 4-6. External Memory Interfaces/DDR Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
F3
ZCZ BALL [4]
F3
ddr_a0
ddr_a1
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
J2
H1
F4
F2
E3
H3
H4
D3
E4
C3
C2
B1
D5
E2
D4
C1
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
E2
G4
F4
H1
H3
E3
D1
B3
E5
A2
B1
D2
C3
B2
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
DDR SDRAM ROW/COLUMN ADDRESS
OUTPUT
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
DDR SDRAM BANK ADDRESS OUTPUT
O
O
O
O
A3
E1
B4
F1
C4
E1
B3
F1
DDR SDRAM COLUMN ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_ck
DDR SDRAM CLOCK OUTPUT (Differential+)
DDR SDRAM CLOCK ENABLE OUTPUT
DDR SDRAM CHIP SELECT OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
O
C2
G3
H2
N4
P4
M3
M4
M2
M1
N2
N1
P2
P1
D2
G3
H2
M3
M4
K2
K3
K4
L3
ddr_cke
ddr_csn0
ddr_d0
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ddr_d1
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d2
L4
M1
N1
N2
ddr_d3
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ZCZ BALL [4]
Table 4-6. External Memory Interfaces/DDR Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ddr_d4
ddr_d5
ddr_d6
ddr_d7
ddr_d8
ddr_d9
ddr_dqm0
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
DDR SDRAM DATA INPUT/OUTPUT
I/O
P3
N3
I/O
I/O
I/O
I/O
I/O
O
T1
T2
R3
K2
K1
N3
N4
P3
P4
J1
K1
M2
DDR WRITE ENABLE / DATA MASK FOR
DATA[7:0]
ddr_dqm1
ddr_dqs0
ddr_dqs1
DDR WRITE ENABLE / DATA MASK FOR
DATA[15:8]
O
K3
R1
L1
R2
L2
J2
P1
L1
P2
L2
DDR DATA STROBE FOR DATA[7:0]
(Differential+)
I/O
I/O
I/O
I/O
DDR DATA STROBE FOR DATA[15:8]
(Differential+)
ddr_dqsn0
ddr_dqsn1
DDR DATA STROBE FOR DATA[7:0]
(Differential-)
DDR DATA STROBE FOR DATA[15:8]
(Differential-)
ddr_nck
ddr_odt
ddr_rasn
DDR SDRAM CLOCK OUTPUT (Differential-)
ODT OUTPUT
O
O
O
C1
G1
F2
D1
G1
G4
DDR SDRAM ROW ADDRESS STROBE
OUTPUT (ACTIVE LOW)
ddr_resetn
ddr_vref
ddr_vtp
DDR3/DDR3L RESET OUTPUT (ACTIVE LOW)
Voltage Reference Input
O
A
I
G2
H4
J1
G2
J4
VTP Compensation Resistor
J3
ddr_wen
DDR SDRAM WRITE ENABLE OUTPUT
(ACTIVE LOW)
O
A4
B2
Table 4-7. External Memory Interfaces/General-Purpose Memory Controller Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
U1
ZCZ BALL [4]
gpmc_a0
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
R1, R13
R2, U5, V14
T16, V5
R6, V17
U1
gpmc_a1
U2, U7
W5
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a2
W7
V4
W4
U2
U5
U3
V5
U4
V6
R13, V2
V14, V3
U14, V4
T14, T5
R3, R5, U14
F17, R14
F18, V15
G15, U15
G16, T15
G17, V16
U6
W6
V7
T7, V1
H19
H18
H17
G18
G19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
54
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Table 4-7. External Memory Interfaces/General-Purpose Memory Controller Signals
Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a3
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
O
O
O
O
O
O
O
O
O
O
G17
G18, U16
T16
NA
NA
V17
U17, V2
W2
R4, T13, T14
R14, T1
T2, V15
T3, U15
T15, T4
U5, V16
R5, U16
U7
gpmc_a4
gpmc_a5
W3
gpmc_a6
V3
gpmc_a7
U3
gpmc_a8
U7
gpmc_a9
T7
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_advn_ale
gpmc_be0n_cle
gpmc_be1n
gpmc_clk
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address Valid / Address Latch Enable
GPMC Byte Enable 0 / Command Latch Enable
GPMC Byte Enable 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
W10
V9
V7
T12
U12
U13
T13
W17
V17
V12
W13
V13
W14
U14
W15
V15
W16
V10
V8
T11
U12
T12
R12
V13
U13
R8
T8
U8
V8
R9
T9
U10
T10
R7
O
T6
O
U15, V18
V14, V16
W8
U18, V9
U9, V12
V6
GPMC Clock
I/O
O
gpmc_csn0
gpmc_csn1
gpmc_csn2
gpmc_csn3
gpmc_csn4
gpmc_csn5
gpmc_csn6
gpmc_dir
GPMC Chip Select
GPMC Chip Select
O
V14
U15
U17
R15
W18
V18
V18
W9
U9
GPMC Chip Select
O
V9
GPMC Chip Select
O
T13
GPMC Chip Select
O
T17
GPMC Chip Select
O
U17
GPMC Chip Select
O
U18
GPMC Data Direction
GPMC Output / Read Enable
GPMC Wait 0
O
U18
gpmc_oen_ren
gpmc_wait0
gpmc_wait1
gpmc_wen
gpmc_wpn
O
T7
I
R15
V16
U8
T17
GPMC Wait 1
I
V12
GPMC Write Enable
O
U6
GPMC Write Protect
O
W18
U17
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4.3.2 General-Purpose IOs
Table 4-8. General-Purpose IOs/GPIO0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
P17
ZCZ BALL [4]
M17
gpio0_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
gpio0_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R19
W6
M18
V4
gpio0_10
gpio0_11
gpio0_12
gpio0_13
gpio0_14
gpio0_15
gpio0_16
gpio0_17
gpio0_18
gpio0_19
gpio0_2
V7
T5
E17
D19
D18
C19
M17
N18
G16
C15
A18
B15
M18
V15
W16
T12
U12
L18
K18
B18
R15
W18
B17
A17
B16
E18
V6
D18
D17
D16
D15
J18
K15
F16
A15
A17
D14
K16
U10
T10
T11
U12
K17
H18
B17
T17
U17
B16
A16
C15
C18
V2
gpio0_20
gpio0_21
gpio0_22
gpio0_23
gpio0_26
gpio0_27
gpio0_28
gpio0_29
gpio0_3
gpio0_30
gpio0_31
gpio0_4
gpio0_5
gpio0_6
gpio0_7
gpio0_8
gpio0_9
U6
V3
Table 4-9. General-Purpose IOs/GPIO1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio1_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
W10
V9
U7
gpio1_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V7
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
E19
F17
U13
T13
W17
V17
NA
E15
E16
T12
R12
V13
U13
R13
V14
U14
NA
NA
56
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Table 4-9. General-Purpose IOs/GPIO1 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
T14
gpio1_19
gpio1_2
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_3
gpio1_30
gpio1_31
gpio1_4
gpio1_5
gpio1_6
gpio1_7
gpio1_8
gpio1_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
NA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V12
NA
R8
R14
V15
U15
T15
V16
U16
T16
V17
U18
V6
NA
NA
NA
NA
NA
NA
NA
V18
W8
W13
V14
U15
V13
W14
U14
W15
F19
F18
T8
U9
V9
U8
V8
R9
T9
E18
E17
Table 4-10. General-Purpose IOs/GPIO2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio2_0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
U17
V16
W2
W3
V3
T13
V12
T1
gpio2_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_2
T2
T3
U3
T4
V4
U1
W4
U5
U2
U3
V5
U4
N17
N16
V10
P19
P18
U7
L17
L16
R7
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
L15
M16
U5
T7
R5
W5
W7
H19
H18
H17
V5
R6
F17
F18
G15
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ZCZ BALL [4]
Table 4-10. General-Purpose IOs/GPIO2 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
gpio2_29
gpio2_3
gpio2_30
gpio2_31
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
G18
G16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W9
G19
G17
U8
T7
G17
G18
U6
T6
V8
U1
R1
R2
R3
R4
U2
V1
V2
Table 4-11. General-Purpose IOs/GPIO3 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gpio3_0
gpio3_1
gpio3_10
gpio3_13
gpio3_14
gpio3_15
gpio3_16
gpio3_17
gpio3_18
gpio3_19
gpio3_2
gpio3_20
gpio3_21
gpio3_3
gpio3_4
gpio3_5
gpio3_6
gpio3_7
gpio3_8
gpio3_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
J19
J18
M19
NA
H16
H17
L18
F15
A13
B13
D12
C12
B12
C13
J15
D13
A14
J16
J17
C17
C16
C14
B14
K18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NA
NA
NA
NA
NA
NA
K19
NA
NA
K17
L19
C18
B19
A15
D14
N19
58
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4.3.3 Miscellaneous
Table 4-12. Miscellaneous/Miscellaneous Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
C15
ZCZ BALL [4]
A15
clkout1
Clock out1
Clock out2
O
clkout2
O
I
B15
A7
D14
B4
ENZ_KALDO_1P8V
Active low enable input for internal
CAP_VDD_RTC voltage regulator
EXT_WAKEUP
nNMI
EXT_WAKEUP input
I
B5
C5
External Interrupt to ARM Cortex-A8 core
Active low Warm Reset
I
C17
A16
W11
W12
A6
B18
A10
V10
U11
A6
nRESETIN_OUT
OSC0_IN
I/OD
High frequency oscillator input
High frequency oscillator output
I
OSC0_OUT
OSC1_IN
O
I
Low frequency (32.768 kHz) Real Time Clock
oscillator input
OSC1_OUT
Low frequency (32.768 kHz) Real Time Clock
oscillator output
O
A5
A4
PMIC_POWER_EN
porz
PMIC_POWER_EN output
Active low Power on Reset
Active low RTC reset input
Timer Clock In
O
I
C7
C6
E15
B15
RTC_PORz
I
B7
B5
tclkin
I
B15
D14
xdma_event_intr0
xdma_event_intr1
xdma_event_intr2
External DMA Event or Interrupt 0
External DMA Event or Interrupt 1
External DMA Event or Interrupt 2
I
C15
A15
I
B15
D14
I
B16, E18, K18
C15, C18, H18
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4.3.3.1 eCAP
Table 4-13. eCAP/eCAP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
eCAP0_in_PWM0_out
DESCRIPTION [2]
ZCE BALL [4]
E18
ZCZ BALL [4]
C18
Enhanced Capture 0 input or Auxiliary PWM0
output
I/O
Table 4-14. eCAP/eCAP1 Signals Description
TYPE
SIGNAL NAME [1]
eCAP1_in_PWM1_out
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Enhanced Capture 1 input or Auxiliary PWM1
output
I/O
B16, B19, F17
C15, C16, E16
Table 4-15. eCAP/eCAP2 Signals Description
TYPE
SIGNAL NAME [1]
eCAP2_in_PWM2_out
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Enhanced Capture 2 input or Auxiliary PWM2
output
I/O
C18, E19
C12, C17, E15
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4.3.3.2 eHRPWM
Table 4-16. eHRPWM/eHRPWM0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM0 A output.
ZCE BALL [4]
A18
ZCZ BALL [4]
ehrpwm0A
O
A13, A17
B13, B17
A16, C12
ehrpwm0B
eHRPWM0 B output.
O
I
B18
A17
ehrpwm0_synci
Sync input to eHRPWM0 module from an
external pin
ehrpwm0_synco
Sync Output from eHRPWM0 module to an
external pin
O
I
U12, V2, W4
B17
R4, U12, U2, V14
B16, D12
ehrpwm0_tripzone_input
eHRPWM0 trip zone input
Table 4-17. eHRPWM/eHRPWM1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM1 A output.
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm1A
O
O
I
U5
V5
V4
U14, U3
T14, U4
R13, U1
ehrpwm1B
eHRPWM1 B output.
ehrpwm1_tripzone_input
eHRPWM1 trip zone input
Table 4-18. eHRPWM/eHRPWM2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
eHRPWM2 A output.
ZCE BALL [4]
ZCZ BALL [4]
ehrpwm2A
O
O
I
U1, V15
U2, W16
T12, V1
R1, U10
R2, T10
R3, T11
ehrpwm2B
eHRPWM2 B output.
ehrpwm2_tripzone_input
eHRPWM2 trip zone input
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4.3.3.3 eQEP
Table 4-19. eQEP/eQEP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
eQEP0A_in
DESCRIPTION [2]
eQEP0A quadrature input
ZCE BALL [4]
M18
ZCZ BALL [4]
I
I
B12, K16
C13, K17
D13, J16
A14, L15
eQEP0B_in
eQEP0B quadrature input
eQEP0 index.
L18
K17
P19
eQEP0_index
eQEP0_strobe
I/O
I/O
eQEP0 strobe.
Table 4-20. eQEP/eQEP1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
eQEP1A_in
eQEP1A quadrature input
eQEP1B quadrature input
eQEP1 index.
I
V6
U6
W6
V7
R14, V2
V15, V3
U15, V4
T15, T5
eQEP1B_in
I
eQEP1_index
eQEP1_strobe
I/O
I/O
eQEP1 strobe.
Table 4-21. eQEP/eQEP2 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
eQEP2A_in
eQEP2A quadrature input
eQEP2B quadrature input
eQEP2 index.
I
U13, W2
T13, W3
V3, W17
U3, V17
T1, T12
R12, T2
T3, V13
T4, U13
eQEP2B_in
I
eQEP2_index
eQEP2_strobe
I/O
I/O
eQEP2 strobe.
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4.3.3.4 Timer
Table 4-22. Timer/Timer4 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
timer4
timer5
timer6
timer7
Timer trigger event / PWM out
I/O
C15, C18, K17,
V10
A15, C17, J16,
R7
Table 4-23. Timer/Timer5 Signals Description
TYPE
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
D19, H19, R19,
V8
D17, F17, M18,
T6
Table 4-24. Timer/Timer6 Signals Description
TYPE
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
E17, H18, P17,
U8
D18, F18, M17,
U6
Table 4-25. Timer/Timer7 Signals Description
TYPE
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
Timer trigger event / PWM out
I/O
B15, B19, F19,
W9
C16, D14, E18,
T7
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4.3.4 PRU-ICSS
Table 4-26. PRU-ICSS/eCAP Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_ecap0_ecap_capin_apwm_o
Enhanced capture input or Auxiliary PWM out
I/O
E18, V17
C18, U13
Table 4-27. PRU-ICSS/ECAT Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_edc_latch0_in
pr1_edc_latch1_in
pr1_edc_sync0_out
pr1_edc_sync1_out
pr1_edio_data_in0
pr1_edio_data_in1
pr1_edio_data_in2
pr1_edio_data_in3
pr1_edio_data_in4
pr1_edio_data_in5
pr1_edio_data_in6
pr1_edio_data_in7
pr1_edio_data_out0
pr1_edio_data_out1
pr1_edio_data_out2
pr1_edio_data_out3
pr1_edio_data_out4
pr1_edio_data_out5
pr1_edio_data_out6
pr1_edio_data_out7
pr1_edio_latch_in
pr1_edio_sof
Data In
I
E17
D18
D17
E18
E17
B16
A16
U5
Data In
I
D19
F19
Data Out
Data Out
Data In
O
O
I
F18
B17
Data In
I
A17
Data In
I
U7
Data In
I
T7
R5
Data In
I
W5
V5
Data In
I
W7
R6
Data In
I
V14, V3
U15, U3
B17
T3, U9
T4, V9
B16
A16
U5
Data In
I
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Latch In
Start of Frame
O
O
O
O
O
O
O
O
I
A17
U7
T7
R5
W5
V5
W7
R6
V14, V3
U15, U3
B18
T3, U9
T4, V9
B17
A17
O
A18
Table 4-28. PRU-ICSS/MDIO Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mdio_data
pr1_mdio_mdclk
MDIO Data
MDIO Clk
I/O
O
U17
V16
T13
V12
Table 4-29. PRU-ICSS/MII0 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii0_col
pr1_mii0_crs
pr1_mii0_rxd0
pr1_mii0_rxd1
pr1_mii0_rxd2
pr1_mii0_rxd3
pr1_mii0_rxdv
pr1_mii0_rxer
MII Collision Detect
I
I
I
I
I
I
I
I
W16
U17, W5
V5
T10
T13, V5
U4
MII Carrier Sense
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
U5
U3
W4
U2
V4
U1
V7
T5
U6
V3
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Table 4-29. PRU-ICSS/MII0 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
V2
pr1_mii0_rxlink
pr1_mii0_txd0
pr1_mii0_txd1
pr1_mii0_txd2
pr1_mii0_txd3
pr1_mii0_txen
pr1_mii_mr0_clk
pr1_mii_mt0_clk
MII Receive Link
I
V6
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
W17, W3
T13, W2
U13, V2
U12, V1
T12, U2
W6
T2, V13
R12, T1
R4, T12
R3, U12
R2, T11
V4
MII Transmit Clock
I
U1, V15
R1, U10
Table 4-30. PRU-ICSS/MII1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_mii1_col
MII Collision Detect
MII Carrier Sense
I
R15
V16, W7
NA
T17
pr1_mii1_crs
I
R6, V12
V16
T15
pr1_mii1_rxd0
pr1_mii1_rxd1
pr1_mii1_rxd2
pr1_mii1_rxd3
pr1_mii1_rxdv
pr1_mii1_rxer
pr1_mii1_rxlink
pr1_mii1_txd0
pr1_mii1_txd1
pr1_mii1_txd2
pr1_mii1_txd3
pr1_mii1_txen
pr1_mii_mr1_clk
pr1_mii_mt1_clk
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Receive Link
I
I
NA
I
NA
U15
V15
T16
I
NA
I
NA
I
NA
V17
U18
R14
T14
I
V18
NA
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
NA
NA
U14
V14
U17
U16
R13
NA
W18
NA
MII Transmit Clock
I
NA
Table 4-31. PRU-ICSS/UART0 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
pr1_uart0_cts_n
pr1_uart0_rts_n
pr1_uart0_rxd
pr1_uart0_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
A18, E17
B18, D19
B17, D18
A17, C19
A17, D18
B17, D17
B16, D16
A16, D15
O
I
O
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4.3.4.1 PRU0
Table 4-32. PRU0/General-Purpose Inputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
pr1_pru0_pru_r31_0
DESCRIPTION [2]
ZCE BALL [4]
NA
ZCZ BALL [4]
A13
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
PRU0 Data In
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
pr1_pru0_pru_r31_1
pr1_pru0_pru_r31_10
pr1_pru0_pru_r31_11
pr1_pru0_pru_r31_12
pr1_pru0_pru_r31_13
pr1_pru0_pru_r31_14
pr1_pru0_pru_r31_15
pr1_pru0_pru_r31_16
pr1_pru0_pru_r31_2
pr1_pru0_pru_r31_3
pr1_pru0_pru_r31_4
pr1_pru0_pru_r31_5
pr1_pru0_pru_r31_6
pr1_pru0_pru_r31_7
pr1_pru0_pru_r31_8
pr1_pru0_pru_r31_9
NA
B13
H17
G18
G19
G17
W17
V17
B15, C19
NA
G15
G16
G17
G18
V13
U13
D14, D15
D12
C12
B12
PRU0 Data In Capture Enable
PRU0 Data In
PRU0 Data In
NA
PRU0 Data In
NA
PRU0 Data In
NA
C13
D13
A14
PRU0 Data In
NA
PRU0 Data In
NA
PRU0 Data In
H19
H18
F17
PRU0 Data In
F18
Table 4-33. PRU0/General-Purpose Outputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru0_pru_r30_0
pr1_pru0_pru_r30_1
pr1_pru0_pru_r30_10
pr1_pru0_pru_r30_11
pr1_pru0_pru_r30_12
pr1_pru0_pru_r30_13
pr1_pru0_pru_r30_14
pr1_pru0_pru_r30_15
pr1_pru0_pru_r30_2
pr1_pru0_pru_r30_3
pr1_pru0_pru_r30_4
pr1_pru0_pru_r30_5
pr1_pru0_pru_r30_6
pr1_pru0_pru_r30_7
pr1_pru0_pru_r30_8
pr1_pru0_pru_r30_9
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
PRU0 Data Out
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
NA
A13
B13
G15
G16
G17
G18
T12
R12
D12
C12
B12
C13
D13
A14
F17
F18
NA
H17
G18
G19
G17
U13
T13
NA
NA
NA
NA
NA
NA
H19
H18
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4.3.4.2 PRU1
Table 4-34. PRU1/General-Purpose Inputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
U1
ZCZ BALL [4]
R1
pr1_pru1_pru_r31_0
pr1_pru1_pru_r31_1
pr1_pru1_pru_r31_10
pr1_pru1_pru_r31_11
pr1_pru1_pru_r31_12
pr1_pru1_pru_r31_13
pr1_pru1_pru_r31_14
pr1_pru1_pru_r31_15
pr1_pru1_pru_r31_16
pr1_pru1_pru_r31_2
pr1_pru1_pru_r31_3
pr1_pru1_pru_r31_4
pr1_pru1_pru_r31_5
pr1_pru1_pru_r31_6
pr1_pru1_pru_r31_7
pr1_pru1_pru_r31_8
pr1_pru1_pru_r31_9
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
PRU1 Data In
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
U2
R2
W5
W7
V14
U15
E19
F17
C15, D18
V1
V5
R6
U9
V9
E15
E16
A15, D16
R3
PRU1 Data In Capture Enable
PRU1 Data In
PRU1 Data In
V2
R4
PRU1 Data In
W2
W3
V3
T1
PRU1 Data In
T2
PRU1 Data In
T3
PRU1 Data In
U3
T4
PRU1 Data In
U7
U5
PRU1 Data In
T7
R5
Table 4-35. PRU1/General-Purpose Outputs Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
pr1_pru1_pru_r30_0
pr1_pru1_pru_r30_1
pr1_pru1_pru_r30_10
pr1_pru1_pru_r30_11
pr1_pru1_pru_r30_12
pr1_pru1_pru_r30_13
pr1_pru1_pru_r30_14
pr1_pru1_pru_r30_15
pr1_pru1_pru_r30_2
pr1_pru1_pru_r30_3
pr1_pru1_pru_r30_4
pr1_pru1_pru_r30_5
pr1_pru1_pru_r30_6
pr1_pru1_pru_r30_7
pr1_pru1_pru_r30_8
pr1_pru1_pru_r30_9
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
PRU1 Data Out
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
U1
R1
R2
V5
R6
U9
V9
E15
E16
R3
R4
T1
U2
W5
W7
V14
U15
E19
F17
V1
V2
W2
W3
V3
T2
T3
U3
T4
U7
U5
R5
T7
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4.3.5 Removable Media Interfaces
Table 4-36. Removable Media Interfaces/MMC0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
mmc0_clk
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
G19
ZCZ BALL [4]
G17
I/O
mmc0_cmd
mmc0_dat0
mmc0_dat1
mmc0_dat2
mmc0_dat3
mmc0_dat4
mmc0_dat5
mmc0_dat6
mmc0_dat7
mmc0_pow
mmc0_sdcd
mmc0_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD Power Switch Control
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
G17
G18
G18
G16
H17
G15
H18
F18
H19
F17
N16
L16
N17
L17
M19
L18
N19
K18
B16, K18
B16, P17
E18, R19
C15, H18
A13, C15, M17
B12, C18, M18
I
SD Write Protect
I
Table 4-37. Removable Media Interfaces/MMC1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
ZCZ BALL [4]
mmc1_clk
I/O
L18, R19, V14
M18, P17, U15
N19, V15, W10
M19, V9, W16
N17, T12, V12
N16, U12, W13
U13, V13
K17, M18, U9
K16, M17, V9
K18, U10, U7
L18, T10, V7
L17, R8, T11
L16, T8, U12
T12, U8
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
mmc1_sdcd
mmc1_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
T13, W14
R12, V8
U14, W17
R9, V13
V17, W15
T9, U13
R15
B13, T17
SD Write Protect
I
B17, D18
B16, D16
Table 4-38. Removable Media Interfaces/MMC2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
ZCE BALL [4]
ZCZ BALL [4]
mmc2_clk
I/O
P19, R19, V16
K17, P17, U17
L19, U13
M17, T13
N18, W17
J19, V17, V18
V15
L15, M18, V12
J16, M17, T13
J17, T12, V14
J18, R12, U14
K15, T14, V13
H16, U13, U18
U10, U15
mmc2_cmd
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_sdcd
mmc2_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
W16
T10, T15
T12
T11, V16
U12
U12
W18
D12, U17
SD Write Protect
I
A17, C19
A16, D15
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4.3.6 Serial Communication Interfaces
4.3.6.1 CAN
Table 4-39. CAN/DCAN0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
dcan0_rx
dcan0_tx
DCAN0 Receive Data
DCAN0 Transmit Data
I
D19, F17, N18
E17, E19, M17
D17, E16, K15
D18, E15, J18
O
Table 4-40. CAN/DCAN1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
dcan1_rx
dcan1_tx
DCAN1 Receive Data
DCAN1 Transmit Data
I
C19, F18, G17
D18, F19, G19
D15, E17, G18
D16, E18, G17
O
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4.3.6.2 GEMAC_CPSW
Table 4-41. GEMAC_CPSW/MDIO Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
mdio_clk
MDIO Clk
O
R19
P17
M18
M17
mdio_data
MDIO Data
I/O
Table 4-42. GEMAC_CPSW/MII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gmii1_col
gmii1_crs
MII Colision
I
J19
H16
H17
L18
M16
L15
L16
L17
J17
J15
K18
K17
K16
K15
J18
J16
MII Carrier Sense
I
J18
gmii1_rxclk
gmii1_rxd0
gmii1_rxd1
gmii1_rxd2
gmii1_rxd3
gmii1_rxdv
gmii1_rxer
gmii1_txclk
gmii1_txd0
gmii1_txd1
gmii1_txd2
gmii1_txd3
gmii1_txen
MII Receive Clock
I
M19
P18
P19
N16
N17
L19
K19
N19
L18
M18
N18
M17
K17
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 4-43. GEMAC_CPSW/MII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
gmii2_col
MII Colision
I
V18
R15
NA
NA
NA
NA
NA
NA
W18
NA
NA
NA
NA
NA
NA
U18
T17
T15
V17
T16
U16
V16
V14
U17
U15
V15
R14
T14
U14
R13
gmii2_crs
MII Carrier Sense
I
gmii2_rxclk
gmii2_rxd0
gmii2_rxd1
gmii2_rxd2
gmii2_rxd3
gmii2_rxdv
gmii2_rxer
gmii2_txclk
gmii2_txd0
gmii2_txd1
gmii2_txd2
gmii2_txd3
gmii2_txen
MII Receive Clock
I
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 4-44. GEMAC_CPSW/RGMII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
rgmii1_rclk
70 Terminal Configuration and Functions
DESCRIPTION [2]
ZCE BALL [4]
M19
ZCZ BALL [4]
L18
RGMII Receive Clock
I
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Table 4-44. GEMAC_CPSW/RGMII1 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
J17
rgmii1_rctl
rgmii1_rd0
rgmii1_rd1
rgmii1_rd2
rgmii1_rd3
rgmii1_tclk
rgmii1_tctl
rgmii1_td0
rgmii1_td1
rgmii1_td2
rgmii1_td3
RGMII Receive Control
I
I
I
I
I
L19
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
P18
P19
N16
N17
N19
K17
L18
M18
N18
M17
M16
L15
L16
L17
K18
J16
K17
K16
K15
J18
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 4-45. GEMAC_CPSW/RGMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Clock
ZCE BALL [4]
ZCZ BALL [4]
rgmii2_rclk
rgmii2_rctl
rgmii2_rd0
rgmii2_rd1
rgmii2_rd2
rgmii2_rd3
rgmii2_tclk
rgmii2_tctl
rgmii2_td0
rgmii2_td1
rgmii2_td2
rgmii2_td3
I
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
T15
V14
V17
T16
U16
V16
U15
R13
V15
R14
T14
U14
RGMII Receive Control
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
I
I
I
I
I
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
Table 4-46. GEMAC_CPSW/RMII1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii1_crs_dv
rmii1_refclk
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
J18
K18
P18
P19
K19
L18
M18
K17
H17
H18
M16
L15
J15
K17
K16
J16
I/O
I
RMII Receive Data bit 0
RMII Receive Data bit 1
RMII Receive Data Error
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
I
I
O
O
O
Table 4-47. GEMAC_CPSW/RMII2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
rmii2_crs_dv
rmii2_refclk
rmii2_rxd0
rmii2_rxd1
RMII Carrier Sense / Data Valid
RMII Reference Clock
I
R15, U17
J19
T13, T17
H16
I/O
RMII Receive Data bit 0
RMII Receive Data bit 1
I
I
NA
V17
NA
T16
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ZCZ BALL [4]
Table 4-47. GEMAC_CPSW/RMII2 Signals Description (continued)
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
rmii2_rxer
rmii2_txd0
rmii2_txd1
rmii2_txen
RMII Receive Data Error
I
W18
U17
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
O
O
O
NA
NA
NA
V15
R14
R13
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
4.3.6.3 I2C
Table 4-48. I2C/I2C0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C0_SCL
I2C0_SDA
I2C0 Clock
I2C0 Data
I/OD
I/OD
B19
C18
C16
C17
Table 4-49. I2C/I2C1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C1_SCL
I2C1_SDA
I2C1 Clock
I2C1 Data
I/OD
A17, C19, F18,
K19
A16, D15, E17,
J15
I/OD
B17, D18, F19,
J18
B16, D16, E18,
H17
Table 4-50. I2C/I2C2 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
I2C2_SCL
I2C2_SDA
I2C2 Clock
I2C2 Data
I/OD
I/OD
B18, D19, F17
A18, E17, E19
B17, D17, E16
A17, D18, E15
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4.3.6.4 McASP
Table 4-51. McASP/MCASP0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
mcasp0_aclkr
DESCRIPTION [2]
McASP0 Receive Bit Clock
ZCE BALL [4]
ZCZ BALL [4]
I/O
L19, V18, V6
B12, J17, U18,
V2
mcasp0_aclkx
McASP0 Transmit Bit Clock
I/O
N19, V4
A13, K18, U1,
V16
mcasp0_ahclkr
mcasp0_ahclkx
mcasp0_axr0
McASP0 Receive Master Clock
McASP0 Transmit Master Clock
McASP0 Serial Data (IN/OUT)
I/O
I/O
I/O
V5
C12, U4
N18, V7
N17, U5
A14, K15, T5
D12, L17, T16,
U3
mcasp0_axr1
mcasp0_axr2
mcasp0_axr3
mcasp0_fsr
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Receive Frame Sync
McASP0 Transmit Frame Sync
I/O
I/O
I/O
I/O
I/O
N16, W6
D13, L16, V17,
V4
J19, V5, V6
P18, U6, V7
M17, U6, V16
M19, W4
B12, C12, H16,
U4, V2
A14, C13, M16,
T5, V3
C13, J18, V12,
V3
mcasp0_fsx
B13, L18, U16,
U2
Table 4-52. McASP/MCASP1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
mcasp1_aclkr
mcasp1_aclkx
mcasp1_ahclkr
mcasp1_ahclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_fsr
McASP1 Receive Bit Clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L18, P18
J18, L19
P18
K17, M16
B12, H17, J17
M16
McASP1 Transmit Bit Clock
McASP1 Receive Master Clock
McASP1 Transmit Master Clock
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Receive Frame Sync
McASP1 Transmit Frame Sync
K18, P18
K17, N18
M18
H18, M16
D13, J16, K15
A14, K16
J19, L18
K18, P19
M18, P19
K19, M17
H16, K17
H18, L15
K16, L15
mcasp1_fsx
C13, J15, J18
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
4.3.6.5 SPI
Table 4-53. SPI/SPI0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
A17
ZCZ BALL [4]
A16
spi0_cs0
spi0_cs1
spi0_d0
spi0_d1
spi0_sclk
SPI Chip Select
SPI Chip Select
SPI Data
I/O
I/O
I/O
I/O
I/O
B16
B18
B17
A18
C15
B17
B16
A17
SPI Data
SPI Clock
Table 4-54. SPI/SPI1 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
ZCZ BALL [4]
spi1_cs0
spi1_cs1
SPI Chip Select
SPI Chip Select
I/O
E17, E19, F18,
K18
C12, D18, E15,
E17, H18
I/O
C15, D19, E18,
F17
A15, C18, D17,
E16
spi1_d0
spi1_d1
spi1_sclk
SPI Data
SPI Data
SPI Clock
I/O
I/O
I/O
F19, J18
F18, K19
E18, J19
B13, E18, H17
D12, E17, J15
A13, C18, H16
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4.3.6.6 UART
Table 4-55. UART/UART0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
UART Clear to Send
ZCE BALL [4]
F19
ZCZ BALL [4]
E18
uart0_ctsn
uart0_rtsn
uart0_rxd
uart0_txd
I
UART Request to Send
UART Receive Data
UART Transmit Data
O
I
F18
E19
F17
E17
E15
E16
O
Table 4-56. UART/UART1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart1_ctsn
UART Clear to Send
I
E17
D18
uart1_dcdn
uart1_dsrn
uart1_dtrn
uart1_rin
UART Data Carrier Detect
UART Data Set Ready
UART Data Terminal Ready
UART Ring Indicator
I
H19, N19
H18, M19
H17, N17
G18, N16
D19
F17, K18
F18, L18
G15, L17
G16, L16
D17
I
O
I
uart1_rtsn
uart1_rxd
uart1_txd
UART Request to Send
UART Receive Data
O
I
D18
D16
UART Transmit Data
O
C19
D15
Table 4-57. UART/UART2 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart2_ctsn
uart2_rtsn
uart2_rxd
UART Clear to Send
UART Request to Send
UART Receive Data
I
C18, V4
B19, W4
C17, U1
C16, U2
O
I
A18, G19, J18,
N19
A17, G17, H17,
K18
uart2_txd
UART Transmit Data
O
B18, G17, K19,
M19
B17, G18, J15,
L18
Table 4-58. UART/UART3 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart3_ctsn
uart3_rtsn
uart3_rxd
uart3_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
G19, P17, U5
G17, R19, V5
B16, H17, N17
E18, G18, N16
G17, M17, U3
G18, M18, U4
C15, G15, L17
C18, G16, L16
O
I
O
Table 4-59. UART/UART4 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
uart4_ctsn
uart4_rtsn
uart4_rxd
uart4_txd
UART Clear to Send
UART Request to Send
UART Receive Data
UART Transmit Data
I
H19, V6
F17, V2
O
I
H18, U6
F18, V3
F19, M17, R15
F18, N18, W18
E18, J18, T17
E17, K15, U17
O
76
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Table 4-60. UART/UART5 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
UART Clear to Send
ZCE BALL [4]
ZCZ BALL [4]
uart5_ctsn
uart5_rtsn
uart5_rxd
I
H17, J18, W6
G18, K19, V7
G15, H17, V4
G16, J15, T5
UART Request to Send
UART Receive Data
O
I
J19, P17, W4,
W6
H16, M17, U2, V4
uart5_txd
UART Transmit Data
O
K18, L19, R19,
V4
H18, J17, M18,
U1
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Terminal Configuration and Functions
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4.3.6.7 USB
Table 4-61. USB/USB0 Signals Description
TYPE
[3]
SIGNAL NAME [1]
DESCRIPTION [2]
ZCE BALL [4]
T18
ZCZ BALL [4]
M15
USB0_CE
USB0_DM
USB0_DP
USB0 Active high Charger Enable output
USB0 Data minus
A
A
A
O
A
A
U18
U19
G16
V19
T19
N18
N17
F16
P16
P15
USB0 Data plus
USB0_DRVVBUS
USB0_ID
USB0 Active high VBUS control output
USB0 ID (Micro-A or Micro-B Plug)
USB0 VBUS
USB0_VBUS
Table 4-62. USB/USB1 Signals Description
TYPE
SIGNAL NAME [1]
DESCRIPTION [2]
[3]
ZCE BALL [4]
ZCZ BALL [4]
USB1_CE
USB1 Active high Charger Enable output
USB1 Data minus
A
A
A
O
A
A
NA
NA
NA
NA
NA
NA
P18
R18
R17
F15
P17
T18
USB1_DM
USB1_DP
USB1 Data plus
USB1_DRVVBUS
USB1_ID
USB1 Active high VBUS control output
USB1 ID (Micro-A or Micro-B Plug)
USB1 VBUS
USB1_VBUS
78
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5 Specifications
5.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)(2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.3
MAX
1.5
1.5
1.5
2.2
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
3.8
3.8
3.8
3.8
3.8
3.8
4
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_MPU(3)
VDD_CORE
CAP_VDD_RTC(4)
VPP(5)
Supply voltage for the MPU core domain
Supply voltage for the core domain
Supply voltage for the RTC core domain
Supply voltage for the FUSE ROM domain
Supply voltage for the RTC domain
VDDS_RTC
VDDS_OSC
Supply voltage for the System oscillator
VDDS_SRAM_CORE_BG Supply voltage for the Core SRAM LDOs
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_DDR
Supply voltage for the MPU SRAM LDOs
Supply voltage for the DPLL DDR
Supply voltage for the DPLL Core and LCD
Supply voltage for the DPLL MPU
Supply voltage for the DDR I/O domain
Supply voltage for all dual-voltage I/O domains
Supply voltage for USBPHY
VDDS
VDDA1P8V_USB0
VDDA1P8V_USB1(6)
VDDA_ADC
Supply voltage for USBPHY
Supply voltage for ADC
VDDSHV1
VDDSHV2(6)
VDDSHV3(6)
Supply voltage for the dual-voltage I/O domain
Supply voltage for the dual-voltage I/O domain
Supply voltage for the dual-voltage I/O domain
Supply voltage for the dual-voltage I/O domain
Supply voltage for the dual-voltage I/O domain
Supply voltage for the dual-voltage I/O domain
Supply voltage for USBPHY
VDDSHV4
VDDSHV5
VDDSHV6
VDDA3P3V_USB0
VDDA3P3V_USB1(6)
USB0_VBUS(7)
USB1_VBUS(6)(7)
DDR_VREF
Supply voltage for USBPHY
4
Supply voltage for USB VBUS comparator input
Supply voltage for USB VBUS comparator input
Supply voltage for the DDR SSTL and HSTL reference voltage
5.25
5.25
1.1
Steady state max voltage
at all I/O pins(8)
–0.5 V to I/O supply voltage + 0.3 V
USB0_ID(9)
USB1_ID(6)(9)
Steady state maximum voltage for the USB ID input
Steady state maximum voltage for the USB ID input
–0.5
–0.5
2.1
2.1
V
V
Transient overshoot and
undershoot specification at
I/O terminal
25% of corresponding I/O supply
voltage for up to 30% of signal
period
Class II (105°C)
1.8-V mode
45
mA
mA
–100
–100
100
100
3.3-V mode; applies to all I/O pins except those
included in latch-up pin groups A(12), B(13), and C(14)
3.3-V mode; applies to latch-up pin group A(12)
3.3-V mode; applies to latch-up pin group B(13)
3.3-V mode; applies to latch-up pin group C(14)
Latch-up performance(10)
Class II (125°C)
–35
–45
100
75
–100
70
Storage temperature,
Tstg
–55
155
°C
(11)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
(3) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
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Absolute Maximum Ratings (continued)
over junction temperature range (unless otherwise noted)(1)(2)
(5) During functional operation, this pin is a no connect.
(6) Not available on the ZCE package.
(7) This terminal is connected to a fail-safe I/O and does not have a dependence on any I/O supply voltage.
(8) This parameter applies to all I/O terminals which are not fail-safe and the requirement applies to all values of I/O supply voltage. For
example, if the voltage applied to a specific I/O supply is 0 volts the valid input voltage range for any I/O powered by that supply will be
–0.5 to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources used to power the
respective I/O supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including
power supply ramp-up and ramp-down sequences.
(9) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal
should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to
any external voltage source.
(10) Based on JEDEC JESD78D [IC Latch-Up Test].
(11) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
(12) Latch-up pin group A: V7, R8, T8, U8, V8, R9, T9, U10, T10, T11, U12, T12, R12, V13, U13, R13, V14, U14, T14, R14, V15, U15, T15,
V16, U16, T16, V17, U17, U18, U9, V9, T13, V12, V4
(13) Latch-up pin group B: R1, R2, R3, R4, T1, T2, T3, V2, V3
(14) Latch-up pin group C: T4, U1, U2, U3, U4, V5, F17, F18, G15, G16, G17, G18, H16, H17, J15, J16, J17, J18, K15, K16, K17, K18,
L18, L17, L16, L15, M16, H18, M17, M18
Fail-safe I/O terminals are designed such they do not have dependencies on the respective I/O power supply voltage. This allows
external voltage sources to be connected to these I/O terminals when the respective I/O power supplies are turned off. The USB0_VBUS
and USB1_VBUS are the only fail-safe I/O terminals. All other I/O terminals are not fail-safe and the voltage applied to them should be
limited to the value defined by the steady state max. Voltage at all I/O pins parameter in Section 5.1.
5.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged Device Model (CDM), per JESD22-C101(2)
Electrostatic discharge
(ESD) performance:
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
80
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5.3 Power-On Hours (POH)
表 5-1. Reliability Data(1)(2)(3)(4)
COMMERCIAL
OPERATING
CONDITION
INDUSTRIAL
EXTENDED
INDUSTRIAL EXTENDED
JUNCTION
TEMP (TJ)
LIFETIME
(POH)(5)
JUNCTION
LIFETIME
(POH)(5)
JUNCTION
LIFETIME
(POH)(5)
JUNCTION
TEMP (TJ)
LIFETIME
(POH)(5)
TEMP (TJ)
TEMP (TJ)
Nitro
0°C to 90°C
0°C to 90°C
0°C to 90°C
0°C to 90°C
0°C to 90°C
100K
100K
100K
100K
100K
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
100K
100K
100K
100K
100K
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
37K
80K
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–
–
Turbo
OPP120
OPP100
OPP50
100K
100K
100K
–
35K
95K
(1) The power-on hours (POH) information in this table is provided solely for your convenience and does not extend or modify the warranty
provided under TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited as described in this table.
(3) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
(4) The previous notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and
conditions for TI semiconductor products.
(5) POH = Power-on hours when the device is fully functional.
5.4 Operating Performance Points (OPPs)
Device OPPs are defined in 表 5-2 through 表 5-9.
表 5-2. VDD_CORE OPPs for ZCZ Package
Device Rev. "A or Newer"(1)
VDD_CORE
NOM
VDD_CORE OPP
Device Rev. "A or Newer"
DDR3,
DDR2(2)
mDDR(2)
L3 and L4
DDR3L(2)
MIN
MAX
200 and 100
MHz
OPP100
OPP50
1.056 V
1.100 V
0.950 V
1.144 V
400 MHz
—
266 MHz
125 MHz
200 MHz
90 MHz
100 and 50
MHz
0.912 V
0.988 V
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
表 5-3. VDD_MPU OPPs for ZCZ Package
With Device Revision Code "Blank"(1)
VDD_MPU
NOM
VDD_MPU OPP
Device Rev. "Blank"
ARM (A8)
MIN
MAX
Turbo
1.210 V
1.152 V
1.056 V
1.056 V
1.260 V
1.200 V
1.100 V
1.100 V
1.326 V
1.248 V
1.144 V
1.144 V
720 MHz
600 MHz
500 MHz
275 MHz
OPP120
OPP100(2)
OPP100(3)
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335__ZCZ_50 (500-MHz speed grade) or higher devices.
(3) Applies to all orderable AM335__ZCZ_27 (275-MHz speed grade) devices.
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表 5-4. Valid Combinations of VDD_CORE and
VDD_MPU OPPs for ZCZ Package
With Device Revision Code "Blank"
VDD_CORE
OPP50
VDD_MPU
OPP100
OPP100
OPP120
Turbo
OPP100
OPP100
OPP100
表 5-5. VDD_CORE OPPs for ZCE Package
With Device Revision Code "Blank"(1)
VDD_CORE
OPP
Device Rev.
"Blank"
VDD_MPU(2)
DDR3,
ARM (A8)
DDR2(3)
mDDR(3)
L3 and L4
DDR3L(3)
MIN
NOM
MAX
200 and 100
MHz
OPP100
OPP100
1.056 V
1.056 V
1.100 V
1.100 V
1.144 V
1.144 V
500 MHz
275 MHz
400 MHz
400 MHz
266 MHz
266 MHz
200 MHz
200 MHz
200 and 100
MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
表 5-6. VDD_CORE OPPs for ZCZ Package
With Device Revision Code "A" or Newer(1)
VDD_CORE
NOM
VDD_CORE OPP
Rev "A" or Newer
DDR3,
DDR2(2)
mDDR(2)
L3 and L4
DDR3L(2)
MIN
MAX
Industrial extended
temperature (–40°C
to 125°C)
333 MHz
400 MHz
200 and 100
MHz
OPP100
OPP50
1.056 V
1.100 V
0.950 V
1.144 V
266 MHz
200 MHz
All other
temperature ranges
Industrial extended
temperature (–40°C
to 125°C)
100 and 50
MHz
0.912 V
0.988 V
—
125 MHz
90 MHz
All other
temperature ranges
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
表 5-7. VDD_MPU OPPs for ZCZ Package
With Device Revision Code "A" or Newer(1)
VDD_MPU
NOM
VDD_MPU OPP
Rev "A" or Newer
ARM (A8)
MIN
MAX
Nitro
1.272 V
1.210 V
1.152 V
1.056 V
1.056 V
0.912 V
1.325 V
1.260 V
1.200 V
1.100 V
1.100 V
0.950 V
1.378 V
1.326 V
1.248 V
1.144 V
1.144 V
0.988 V
1 GHz
Turbo
800 MHz
720 MHz
600 MHz
300 MHz
300 MHz
OPP120
OPP100(2)
OPP100(3)
OPP50
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(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335__ZCZ_60 (600-MHz speed grade) or higher devices.
(3) Applies to all orderable AM335__ZCZ_30 (300-MHz speed grade) devices.
表 5-8. Valid Combinations of VDD_CORE and
VDD_MPU OPPs for ZCZ Package With Device
Revision Code "A" or Newer
VDD_CORE
OPP50
VDD_MPU
OPP50
OPP100
OPP50
OPP100
OPP120
Turbo
OPP50
OPP100
OPP100
OPP100
OPP100
OPP100
Nitro
表 5-9. VDD_CORE OPPs for ZCE Package
With Device Revision Code "A" or Newer(1)
VDD_CORE
OPP
Rev "A" or
newer
VDD_MPU(2)
DDR3,
ARM (A8)
DDR2(3)
mDDR(3)
L3 and L4
DDR3L(3)
MIN
NOM
MAX
200 and 100
MHz
OPP100
OPP100
OPP50
1.056 V
1.056 V
0.912 V
1.100 V
1.100 V
0.950 V
1.144 V
1.144 V
0.988 V
600 MHz
300 MHz
300 MHz
400 MHz
400 MHz
–
266 MHz
266 MHz
125 MHz
200 MHz
200 MHz
90 MHz
200 and 100
MHz
100 and 50
MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
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5.5 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
NOM
MAX
UNIT
Supply voltage range for core
domain; OPP100
1.056
1.100
1.144
0.988
1.378
1.326
1.248
1.144
0.988
1.250
1.890
1.890
1.575
1.418
1.890
1.890
1.890
1.890
1.890
1.890
1.890
VDD_CORE(1)
V
Supply voltage range for core
domain; OPP50
0.912
1.272
1.210
1.152
1.056
0.912
0.900
1.710
1.710
1.425
1.283
1.710
1.710
1.710
1.710
1.710
1.710
1.710
0.950
1.325
1.260
1.200
1.100
0.950
1.100
1.800
1.800
1.500
1.350
1.800
1.800
1.800
1.800
1.800
1.800
1.800
Supply voltage range for MPU
domain, Nitro
Supply voltage range for MPU
domain; Turbo
Supply voltage range for MPU
domain; OPP120
VDD_MPU(1)(2)
V
Supply voltage range for MPU
domain; OPP100
Supply voltage range for MPU
domain; OPP50
Supply voltage range for RTC
domain input
CAP_VDD_RTC(3)
VDDS_RTC
V
V
Supply voltage range for RTC
domain
Supply voltage range for DDR
I/O domain (DDR2)
Supply voltage range for DDR
I/O domain (DDR3)
VDDS_DDR
V
Supply voltage range for DDR
I/O domain (DDR3L)
Supply voltage range for all dual-
voltage I/O domains
VDDS(4)
V
V
V
V
V
V
V
Supply voltage range for Core
SRAM LDOs, analog
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR(5)
VDDS_PLL_CORE_LCD(5)
VDDS_PLL_MPU(5)
VDDS_OSC
Supply voltage range for MPU
SRAM LDOs, analog
Supply voltage range for DPLL
DDR, analog
Supply voltage range for DPLL
CORE and LCD, analog
Supply voltage range for DPLL
MPU, analog
Supply voltage range for system
oscillator I/Os, analog
Supply voltage range for
USBPHY and PER DPLL,
analog, 1.8 V
VDDA1P8V_USB0(5)
1.710
1.800
1.890
V
Supply voltage range for USB
PHY, analog, 1.8 V
VDDA1P8V_USB1(6)
VDDA3P3V_USB0
VDDA3P3V_USB1(6)
VDDA_ADC
1.710
3.135
3.135
1.710
1.800
3.300
3.300
1.800
1.890
3.465
3.465
1.890
V
V
V
V
Supply voltage range for USB
PHY, analog, 3.3 V
Supply voltage range for USB
PHY, analog, 3.3 V
Supply voltage range for ADC,
analog
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
VDDSHV1
1.710
1.710
1.800
1.800
1.890
1.890
V
V
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
VDDSHV2(6)
84
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Recommended Operating Conditions (continued)
over junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
NOM
MAX
UNIT
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
VDDSHV3(6)
1.710
1.800
1.890
V
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
VDDSHV4
VDDSHV5
VDDSHV6
VDDSHV1
VDDSHV2(6)
VDDSHV3(6)
VDDSHV4
VDDSHV5
VDDSHV6
DDR_VREF
1.710
1.710
1.710
3.135
3.135
3.135
3.135
3.135
3.135
1.800
1.800
1.800
3.300
3.300
3.300
3.300
3.300
3.300
1.890
1.890
1.890
3.465
3.465
3.465
3.465
3.465
3.465
V
V
V
V
V
V
V
V
V
V
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
Supply voltage range for dual-
voltage I/O domain (1.8-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Supply voltage range for dual-
voltage I/O domain (3.3-V
operation)
Voltage range for DDR SSTL and
HSTL reference input (DDR2,
DDR3, DDR3L)
0.49 × VDDS_DDR 0.50 × VDDS_DDR 0.51 × VDDS_DDR
Voltage range for USB VBUS
comparator input
USB0_VBUS
USB1_VBUS(6)
USB0_ID
0.000
0.000
5.000
5.000
5.250
5.250
V
V
V
V
Voltage range for USB VBUS
comparator input
Voltage range for the USB ID
input
(7)
(7)
Voltage range for the USB ID
input
USB1_ID(6)
Commercial temperature
Industrial temperature
0
–40
–40
–40
90
90
Operating temperature
range, TJ
°C
Extended temperature
105
125
Industrial Extended temperature
(1) The supply voltage defined by OPP100 should be applied to this power domain before the device is released from reset.
(2) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(4) VDDS should be supplied irrespective of 1.8- or 3.3-V mode of operation of the dual-voltage I/Os.
(5) For more details on power supply requirements, see 节 6.1.4.
(6) Not available on the ZCE package.
(7) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal
should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to
any external voltage source.
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Specifications
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5.6 Power Consumption Summary
表 5-10 summarizes the power consumption at the AM335x power terminals.
表 5-10. Maximum Current Ratings at AM335x Power Terminals(1)
SUPPLY NAME
VDD_CORE(2)
DESCRIPTION
Maximum current rating for the core domain; OPP100
Maximum current rating for the core domain; OPP50
Maximum current rating for the MPU domain; Nitro
MAX UNIT
400
mA
250
at 1 GHz
1000
800
720
720
600
at 800 MHz
at 720 MHz
at 720 MHz
at 600 MHz
at 600 MHz
at 500 MHz
at 300 MHz
at 275 MHz
at 300 MHz
at 275 MHz
Maximum current rating for the MPU domain; Turbo
Maximum current rating for the MPU domain; OPP120
VDD_MPU(2)
600
500
380
350
330
300
2
mA
Maximum current rating for the MPU domain; OPP100
Maximum current rating for the MPU domain; OPP50
CAP_VDD_RTC(3)
VDDS_RTC
Maximum current rating for RTC domain input and LDO output
Maximum current rating for the RTC domain
Maximum current rating for DDR I/O domain
Maximum current rating for all dual-voltage I/O domains
Maximum current rating for core SRAM LDOs
Maximum current rating for MPU SRAM LDOs
Maximum current rating for the DPLL DDR
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
VDDS_DDR
250
50
10
10
10
20
10
5
VDDS
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_OSC
Maximum current rating for the DPLL Core and LCD
Maximum current rating for the DPLL MPU
Maximum current rating for the system oscillator I/Os
Maximum current rating for USBPHY 1.8 V
VDDA1P8V_USB0
VDDA1P8V_USB1(4)
VDDA3P3V_USB0
VDDA3P3V_USB1(4)
VDDA_ADC
VDDSHV1(5)
VDDSHV2(4)
25
25
40
40
10
50
50
50
50
50
100
Maximum current rating for USBPHY 1.8 V
Maximum current rating for USBPHY 3.3 V
Maximum current rating for USBPHY 3.3 V
Maximum current rating for ADC
Maximum current rating for dual-voltage I/O domain
Maximum current rating for dual-voltage I/O domain
Maximum current rating for dual-voltage I/O domain
Maximum current rating for dual-voltage I/O domain
Maximum current rating for dual-voltage I/O domain
Maximum current rating for dual-voltage I/O domain
VDDSHV3(4)
VDDSHV4
VDDSHV5
VDDSHV6
(1) Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more
information, see AM335x Power Consumption Summary.
(2) VDD_MPU is merged with VDD_CORE and is not available separately on the ZCE package. The maximum current rating for
VDD_CORE on the ZCE package is the sum of VDD_CORE and VDD_MPU shown in this table.
(3) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(4) Not available on the ZCE package.
(5) VDDSHV1 and VDDSHV2 are merged in the ZCE package. The maximum current rating for VDDSHV1 on the ZCE package is the sum
of VDDSHV1 and VDDSHV2 shown in this table.
86
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 5-11 summarizes the power consumption of the AM335x low-power modes.
表 5-11. AM335x Low-Power Modes Power Consumption Summary
POWER
MODES
POWER DOMAINS, CLOCKS, AND
VOLTAGE SUPPLY STATES
APPLICATION STATE
NOM
MAX UNIT
Power supplies:
•
•
•
All power supplies are ON.
VDD_MPU = 0.95 V (nom)
VDD_CORE = 0.95 V (nom)
DDR memory is in self-refresh and
contents are preserved. Wake up
from any GPIO. Cortex-A8
context/register contents are lost
and must be saved before entering
standby. On exit, context must be
restored from DDR. For wakeup,
boot ROM executes and branches
to system resume.
Clocks:
•
Main Oscillator (OSC0) = ON
Standby
16.5
22.0
10.0
4.3
mW
mW
mW
•
All DPLLs are in bypass.
Power domains:
•
•
•
•
PD_PER = ON
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
DDR is in self-refresh.
Power supplies:
•
•
•
All power supplies are ON.
VDD_MPU = 0.95 V (nom)
VDD_CORE = 0.95 V (nom)
On-chip peripheral registers are
preserved. Cortex-A8
Clocks:
context/registers are lost, so the
application must save them to the
L3 OCMC RAM or DDR before
entering DeepSleep. DDR is in self-
refresh. For wakeup, boot ROM
executes and branches to system
resume.
•
•
Main Oscillator (OSC0) = OFF
All DPLLs are in bypass.
Deepsleep1
6.0
Power domains:
•
•
•
•
PD_PER = ON
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
DDR is in self-refresh.
Power supplies:
•
•
•
All power supplies are ON.
VDD_MPU = 0.95 V (nom)
VDD_CORE = 0.95 V (nom)
PD_PER peripheral and Cortex-
A8/MPU register information will be
lost. On-chip peripheral register
(context) information of PD-PER
domain must be saved by
application to SDRAM before
entering this mode. DDR is in self-
refresh. For wakeup, boot ROM
executes and branches to
Clocks:
•
•
Main Oscillator (OSC0) = OFF
All DPLLs are in bypass.
Deepsleep0
3.0
Power domains:
•
•
•
•
PD_PER = OFF
PD_MPU = OFF
PD_GFX = OFF
PD_WKUP = ON
peripheral context restore followed
by system resume.
DDR is in self-refresh.
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Specifications
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5.7 DC Electrical Characteristics
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
NOM
MAX UNIT
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (mDDR - LVCMOS Mode)
0.65 ×
VDDS_DDR
VIH
High-level input voltage
V
0.35 ×
VDDS_DDR
VIL
Low-level input voltage
V
V
V
VHYS
VOH
Hysteresis voltage at an input
0.07
0.25
High level output voltage, driver enabled, pullup or
pulldown disabled
VDDS_DDR –
0.4
IOH = 8 mA
IOL = 8 mA
Low level output voltage, driver enabled, pullup or
pulldown disabled
VOL
0.4
V
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
10
–80
240
II
–240
80
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
10
µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (DDR2 - SSTL Mode)
DDR_VREF +
VIH
High-level input voltage
V
V
V
0.125
VHYS
VOH
Hysteresis voltage at an input
N/A
High-level output voltage, driver enabled, pullup or
pulldown disabled
VDDS_DDR –
0.4
IOH = 8 mA
IOL = 8 mA
Low-level output voltage, driver enabled, pullup or
pulldown disabled
VOL
0.4
V
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
10
–80
240
II
–240
80
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
10
µA
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,DDR_A0,DDR_A1,DDR_A
2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DD
R_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM
0,DDR_DQM1,DDR_DQS0,DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (DDR3, DDR3L - HSTL Mode)
VDDS_DDR =
1.5 V
DDR_VREF +
0.1
VIH
High-level input voltage
V
V
VDDS_DDR =
1.35 V
DDR_VREF +
0.09
VDDS_DDR =
1.5 V
DDR_VREF –
0.1
VIL
Low-level input voltage
VDDS_DDR =
1.35 V
DDR_VREF –
0.09
VHYS
VOH
Hysteresis voltage at an input
N/A
V
V
High-level output voltage, driver enabled, pullup or
pulldown disabled
VDDS_DDR –
0.4
IOH = 8 mA
IOL = 8 mA
Low-level output voltage, driver enabled, pullup or
pulldown disabled
VOL
0.4
V
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
10
–80
240
II
–240
80
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
10
µA
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
DC Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
NOM
MAX UNIT
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_TXD,I2C0_SDA,I2C0_
SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,USB0_DRVVBUS,USB1_DRVVBUS (VDDSHV6 = 1.8 V)
VIH
High-level input voltage
Low-level input voltage
0.65 × VDDSHV6
V
V
V
VIL
0.35 × VDDSHV6
0.305
VHYS
Hysteresis voltage at an input
0.18
High-level output voltage, driver enabled, pullup or
pulldown disabled
VOH
VOL
IOH = 4 mA
IOL = 4 mA
VDDSHV6 – 0.45
V
V
Low-level output voltage, driver enabled, pullup or
pulldown disabled
0.45
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
8
–52
170
II
–161
52
–100
100
µA
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
8
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,UART1_TXD,I2C0_SDA,I2C0_
SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,USB0_DRVVBUS,USB1_DRVVBUS (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
Low-level input voltage
2
V
V
V
VIL
0.8
VHYS
Hysteresis voltage at an input
0.265
0.44
High-level output voltage, driver enabled, pullup or
pulldown disabled
VOH
VOL
IOH = 4 mA
IOL = 4 mA
VDDSHV6 – 0.45
V
V
Low-level output voltage, driver enabled, pullup or
pulldown disabled
0.45
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
18
–19
210
II
–243
51
–100
110
µA
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
18
TCK (VDDSHV6 = 1.8 V)
VIH
High-level input voltage
1.45
0.4
V
V
V
VIL
Low-level input voltage
0.46
VHYS
Hysteresis voltage at an input
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
8
–52
170
II
–161
52
–100
100
µA
TCK (VDDSHV6 = 3.3 V)
VIH
High-level input voltage
2.15
0.4
V
V
V
VIL
Low-level input voltage
0.46
VHYS
Hysteresis voltage at an input
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
18
–19
210
II
–243
51
–100
110
µA
PWRONRSTn (VDDSHV6 = 1.8 or 3.3 V)(2)
VIH
High-level input voltage
Low-level input voltage
1.35
0.07
V
V
V
VIL
0.5
VHYS
Hysteresis voltage at an input
VI = 1.8 V
VI = 3.3 V
0.1
2
II
Input leakage current
µA
RTC_PWRONRSTn
0.65 ×
VDDS_RTC
VIH
High-level input voltage
V
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Specifications
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DC Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
NOM
MAX UNIT
0.35 ×
V
VIL
Low-level input voltage
VDDS_RTC
VHYS
II
Hysteresis voltage at an input
Input leakage current
0.065
–1
V
1
µA
PMIC_POWER_EN
High-level output voltage, driver enabled, pullup or
pulldown disabled
VDDS_RTC –
0.45
VOH
VOL
IOH = 6 mA
IOL = 6 mA
V
V
Low-level output voltage, driver enabled, pullup or
pulldown disabled
0.45
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–1
–200
40
1
–40
200
II
µA
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
–1
1
EXT_WAKEUP
0.65 ×
VDDS_RTC
VIH
High-level input voltage
V
0.35 ×
VDDS_RTC
VIL
Low-level input voltage
V
V
VHYS
Hysteresis voltage at an input
0.15
–1
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
1
–40
200
II
–200
40
µA
XTALIN (OSC0)
0.65 ×
VDDS_OSC
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.35 ×
VDDS_OSC
RTC_XTALIN (OSC1)
0.65 ×
VDDS_RTC
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
0.35 ×
VDDS_RTC
All other LVCMOS pins (VDDSHVx = 1.8 V; x = 1 to 6)
VIH
High-level input voltage
Low-level input voltage
0.65 × VDDSHVx
V
V
V
VIL
0.35 × VDDSHVx
0.305
VHYS
Hysteresis voltage at an input
0.18
High-level output voltage, driver enabled, pullup or
pulldown disabled
VOH
VOL
IOH = 6 mA
IOL = 6 mA
VDDSHVx – 0.45
V
V
Low-level output voltage, driver enabled, pullup or
pulldown disabled
0.45
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
8
–52
170
II
–161
52
–100
100
µA
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
8
All other LVCMOS pins (VDDSHVx = 3.3 V; x = 1 to 6)
VIH
High-level input voltage
Low-level input voltage
2
V
V
V
VIL
0.8
VHYS
Hysteresis voltage at an input
0.265
0.44
High-level output voltage, driver enabled, pullup or
pulldown disabled
VOH
VOL
IOH = 6 mA
IOL = 6 mA
VDDSHVx – 0.45
V
V
Low-level output voltage, driver enabled, pullup or
pulldown disabled
0.45
90
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DC Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
NOM
MAX UNIT
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
18
II
–243
51
–100
110
–19
210
µA
µA
Total leakage current through the terminal connection of a driver-receiver
combination that may include a pullup or pulldown. The driver output is
disabled and the pullup or pulldown is inhibited.
IOZ
18
(1) The interfaces or signals described in this table correspond to the interfaces or signals available in multiplexing mode 0. All interfaces or
signals multiplexed on the terminals described in this table have the same DC electrical characteristics.
(2) The input voltage thresholds for this input are not a function of VDDSHV6.
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5.8 Thermal Resistance Characteristics for ZCE and ZCZ Packages
Failure to maintain a junction temperature within the range specified in Section 5.5 reduces operating
lifetime, reliability, and performance—and may cause irreversible damage to the system. Therefore, the
product design cycle should include thermal analysis to verify the maximum operating junction
temperature of the device. It is important this thermal analysis is performed using specific system use
cases and conditions. TI provides an application report to aid users in overcoming some of the existing
challenges of producing a good thermal design. For more information, see AM335x Thermal
Considerations.
表 5-12 provides thermal characteristics for the packages used on this device.
注
表 5-12 provides simulation data and may not represent actual use-case values.
表 5-12. Thermal Resistance Characteristics (PBGA Package) [ZCE and ZCZ]
ZCE (°C/W)(1)
ZCZ (°C/W)(1)
AIR FLOW
(m/s)(3)
(2)
(2)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
10.3
11.6
24.7
20.5
19.7
19.2
0.4
10.2
12.1
24.2
20.1
19.3
18.8
0.3
N/A
N/A
0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
RΘJA
Junction-to-free air
Junction-to-package top
Junction-to-board
0.6
0.6
φJT
0.7
0.7
0.9
0.8
11.9
11.7
11.7
11.6
12.7
12.3
12.3
12.2
φJB
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(2) °C/W = degrees Celsius per watt.
(3) m/s = meters per second.
92
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5.9 External Capacitors
To improve module performance, decoupling capacitors are required to suppress the switching noise
generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective
when it is close to the device, because this minimizes the inductance of the circuit board wiring and
interconnects.
5.9.1 Voltage Decoupling Capacitors
表 5-13 summarizes the Core voltage decoupling characteristics.
5.9.1.1 Core Voltage Decoupling Capacitors
To improve module performance, decoupling capacitors are required to suppress high-frequency switching
noise and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to
the AM335x device, because this minimizes the inductance of the circuit board wiring and interconnects.
表 5-13. Core Voltage Decoupling Characteristics
PARAMETER
TYP
10.08
10.05
UNIT
μF
(1)
CVDD_CORE
(2)(3)
CVDD_MPU
μF
(1) The typical value corresponds to one capacitor of 10 μF and eight capacitors of 10 nF.
(2) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) The typical value corresponds to one capacitor of 10 μF and five capacitors of 10 nF.
5.9.1.2 I/O and Analog Voltage Decoupling Capacitors
表 5-14 summarizes the power-supply decoupling capacitor recommendations.
表 5-14. Power-Supply Decoupling Capacitor Characteristics
PARAMETER
TYP
10
UNIT
nF
CVDDA_ADC
CVDDA1P8V_USB0
CCVDDA3P3V_USB0
10
nF
10
nF
(1)
CVDDA1P8V_USB1
10
nF
(1)
CVDDA3P3V_USB1
10
nF
(2)
CVDDS
10.04
μF
(3)
CVDDS_DDR
CVDDS_OSC
10
10
nF
nF
nF
μF
μF
nF
nF
μF
μF
μF
μF
μF
μF
CVDDS_PLL_DDR
CVDDS_PLL_CORE_LCD
10
(4)
CVDDS_SRAM_CORE_BG
10.01
10.01
10
(5)
CVDDS_SRAM_MPU_BB
CVDDS_PLL_MPU
CVDDS_RTC
10
(6)
CVDDSHV1
10.02
10.02
10.02
10.02
10.02
10.06
(1)(6)
CVDDSHV2
(1)(6)
CVDDSHV3
(6)
CVDDSHV4
(6)
CVDDSHV5
(7)
CVDDSHV6
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(1) Not available on the ZCE package.
(2) Typical values consist of one capacitor of 10 μF and four capacitors of 10 nF.
(3) For more details on decoupling capacitor requirements for the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, see 节
7.7.2.1.2.6 and 节 7.7.2.1.2.7 when using mDDR(LPDDR) memory devices, 节 7.7.2.2.2.6 and 节 7.7.2.2.2.7 when using DDR2
memory devices, or 节 7.7.2.3.3.6 and 节 7.7.2.3.3.7 when using DDR3 or DDR3L memory devices.
(4) VDDS_SRAM_CORE_BG supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_CORE_BG supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_CORE_BG terminals. A 10 µF is
recommended to be placed close to the terminal and routed with widest traces possible to minimize the voltage drop on
VDDS_SRAM_CORE_BG terminals.
(5) VDDS_SRAM_MPU_BB supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals. A 10 µF is
recommended to be placed close to the terminal and routed with widest traces possible to minimize the voltage drop on
VDDS_SRAM_MPU_BB terminals.
(6) Typical values consist of one capacitor of 10 μF and two capacitors of 10 nF.
(7) Typical values consist of one capacitor of 10 μF and six capacitors of 10 nF.
5.9.2 Output Capacitors
Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These
capacitors should be placed as close as possible to the respective terminals of the AM335x device
. 表 5-15 summarizes the LDO output capacitor recommendations.
表 5-15. Output Capacitor Characteristics
PARAMETER
TYP
UNIT
μF
(1)
CCAP_VDD_SRAM_CORE
1
1
1
1
(1)(2)
CCAP_VDD_RTC
μF
(1)
CCAP_VDD_SRAM_MPU
μF
(1)
CCAP_VBB_MPU
μF
(1) LDO regulator outputs should not be used as a power source for any external components.
(2) The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KALDO_ENn terminal is high.
94
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图 5-1 shows an example of the external capacitors.
AM335x Device
VDDS_PLL_MPU
CVDDS_PLL_MPU
MPU
PLL
VDD_MPU
CVDD_MPU
MPU
VDDS_PLL_CORE_LCD
CVDDS_PLL_CORE_LCD
CORE
PLL
LCD
PLL
VDD_CORE
CORE
CAP_VBB_MPU
CCAP_VBB_MPU
CVDD_CORE
VDDS
I/O
CVDDS
VDDS_SRAM_MPU_BB
CVDDS_SRAM_MPU_BB
VDDSHV1
I/Os
MPU SRAM
LDO
CVDDSHV1
Back Bias
LDO
CAP_VDD_SRAM_MPU
CCAP_VDD_SRAM_MPU
VDDSHV2
I/Os
CVDDSHV2
CVDDSHV3
CVDDSHV4
CVDDSHV5
CVDDSHV6
CVDDS_DDR
CVDDS_RTC
VDDS_SRAM_CORE_BG
CVDDS_SRAM_CORE_BG
VDDSHV3
I/Os
CORE SRAM
LDO
Band Gap
Reference
CAP_VDD_SRAM_CORE
CCAP_VDD_SRAM_CORE
VDDSHV4
I/Os
VDDA_3P3V_USBx
CVDDA_3P3V_USBx
VDDSHV5
I/Os
VSSA_USB
USB PHYx
VDDA_1P8V_USBx
VDDSHV6
I/Os
CVDDA_1P8V_USBx
VSSA_USB
VDDA_ADC
VDDS_DDR
I/Os
CVDDA_ADC
ADC
VDDS_RTC
I/Os
VSSA_ADC
VDDS_OSC
CVDDS_OSC
VDDS_PLL_DDR
CVDDS_PLL_DDR
DDR
PLL
CAP_VDD_RTC
CCAP_VDD_RTC
RTC
A. Decoupling capacitors must be placed as closed as possible to the power terminal. Choose the ground closest to the
power pin for each decoupling capacitor. In case of interconnecting powers, first insert the decoupling capacitor and
then interconnect the powers.
B. The decoupling capacitor value depends on the characteristics of the board.
图 5-1. External Capacitors
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5.10 Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
The touch screen controller (TSC) and analog-to-digital converter (ADC) subsystem (TSC_ADC) is an 8-
channel general-purpose ADC with optional support for interleaving TSC conversions for 4-wire, 5-wire, or
8-wire resistive panels. The TSC_ADC subsystem can be configured for use in one of the following
applications:
•
•
•
•
8 general-purpose ADC channels
4-wire TSC with 4 general-purpose ADC channels
5-wire TSC with 3 general-purpose ADC channels
8-wire TSC.
表 5-16 summarizes the TSC_ADC subsystem electrical parameters.
表 5-16. TSC_ADC Electrical Parameters
PARAMETER
Analog Input
TEST CONDITIONS
MIN
NOM
MAX UNIT
(0.5 × VDDA_ADC) +
0.25
VREFP(1)
VDDA_ADC
V
(0.5 × VDDA_ADC) –
0.25
VREFN(1)
0
V
V
VREFP + VREFN(1)
VDDA_ADC
Internal voltage reference
External voltage reference
0
VDDA_ADC
VREFP
Full-scale input range
V
VREFN
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Differential nonlinearity
(DNL)
–1
–2
0.5
±1
1
LSB
Source impedance = 50 Ω
Internal voltage reference:
VDDA_ADC = 1.8 V
2
External voltage reference:
VREFP – VREFN = 1.8 V
Integral nonlinearity (INL)
LSB
LSB
Source impedance = 1 kΩ
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
±1
±2
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Gain error
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Offset error
±2
LSB
pF
Input sampling capacitance
5.5
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave at
–0.5-dB full scale
Signal-to-noise ratio (SNR)
70
75
dB
dB
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave at
–0.5-dB full scale
Total harmonic distortion
(THD)
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表 5-16. TSC_ADC Electrical Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
Internal voltage reference:
VDDA_ADC = 1.8 V
Spurious free dynamic
range
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave at
–0.5-dB full scale
80
dB
Internal voltage reference:
VDDA_ADC = 1.8 V
Signal-to-noise plus
distortion
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave at
–0.5-dB full scale
69
20
dB
VREFP and VREFN input impedance
Input impedance of
kΩ
ƒ = Input frequency
[1 / ((65.97 × 10–12) × ƒ)]
Ω
AIN[7:0](2)
Sampling Dynamics
ADC clock frequency
3
MHz
ADC
clock
cycles
Conversion time
Acquisition time
13
ADC
257 clock
cycles
2
Sampling rate
ADC clock = 3 MHz
200 kSPS
dB
Channel-to-channel isolation
100
2
Touch Screen Switch Drivers
Pullup and pulldown switch ON resistance (Ron)
Ω
Pullup and pulldown switch
current leakage Ileak
Drive current
Source impedance = 500 Ω
0.5
uA
25
6
mA
kΩ
kΩ
Touch screen resistance
Pen touch detect
2
(1) VREFP and VREFN must be tied to ground if the internal voltage reference is used.
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
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6 Power and Clocking
6.1 Power Supplies
6.1.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate for powering on the supplies to be less than 1.0E +5 V/s. For instance, as shown in 图
6-1, TI recommends a value greater than 18 µs for the supply ramp slew for a 1.8-V supply.
Supply value
t
slew rate < 1E + 5 V/s
slew > (supply value) / (1E + 5V/s)
supply value ´ 10 µs
0
图 6-1. Power Supply Slew and Slew Rate
98
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1.8 V
1.8 V
VDDS_RTC
RTC_PWRONRSTn
1.8 V
1.8 V
PMIC_POWER_EN
All 1.8-V Supplies
1.8 V/1.5 V/1.35 V
3.3 V
VDDS_DDR
I/O 3.3-V Supplies
1.1 V
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to
reach a valid level before RTC reset is released.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
G. If all the 1.8-V supplies are not sourced from the same power supply, it is required to power up VDDS before other
1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V
from the same power supply.
图 6-2. Preferred Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V
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1.8 V
VDDS_RTC
1.8 V
1.8 V
RTC_PWRONRSTn
PMIC_POWER_EN
3.3 V
1.8 V
See Notes Below
All 1.8-V Supplies
All 3.3-V Supplies
1.8 V/1.5 V/1.35 V
VDDS_DDR
1.1 V
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to
reach a valid level before RTC reset is released.
B. The 3.3-V I/O power supplies may be ramped simultaneously with the 1.8-V I/O power supplies if the voltage sourced
by any 3.3-V power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V.
Serious reliability issues may occur if the system power supply design allows any 3.3-V I/O power supplies to exceed
any 1.8-V I/O power supplies by more than 2 V.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
F. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
H. If all the 1.8-V supplies are not sourced from the same power supply, it is required to power up VDDS before other
1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V
from the same power supply.
图 6-3. Alternate Power-Supply Sequencing With Dual-Voltage I/Os Configured as 3.3 V
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1.8 V
1.8V
VDDS_RTC
RTC_PWRONRSTn
1.8 V
1.8 V
PMIC_POWER_EN
All 1.8-V Supplies
1.8 V/1.5 V/1.35 V
VDDS_DDR
3.3 V
1.1 V
All 3.3-V Supplies
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to
reach a valid level before RTC reset is released.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
G. If all the 1.8-V supplies are not sourced from the same power supply, it is required to power up VDDS before other
1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V
from the same power supply.
图 6-4. Power-Supply Sequencing With Dual-Voltage I/Os Configured as 1.8 V
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1.8 V
1.1 V
VDDS_RTC,
CAP_VDD_RTC
1.8 V
RTC_PWRONRSTn
PMIC_POWER_EN
1.8 V
1.8 V
VDDSHV 1-6
All other 1.8-V Supplies
1.8 V/1.5 V/1.35 V
VDDS_DDR
3.3 V
1.1 V
All 3.3-V Supplies
VDD_CORE, VDD_MPU
PWRONRSTn
CLK_M_OSC
A. RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to
reach a valid level before RTC reset is released.
B. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply.
C. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
F. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped
after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
H. If all the 1.8-V supplies are not sourced from the same power supply, it is required to power up VDDS before other
1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V
from the same power supply.
图 6-5. Power-Supply Sequencing With Internal RTC LDO Disabled
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1.8 V
VDDS_RTC,
All other 1.8-V Supplies
1.8 V/1.5 V/1.35 V
3.3 V
VDDS_DDR
All 3.3-V Supplies
1.1 V
VDD_CORE, VDD_MPU
CAP_VDD_RTC
PWRONRSTn
CLK_M_OSC
A. CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled,
CAP_VDD_RTC should be sourced from an external 1.1-V power supply. The PMIC_POWER_EN output cannot be
used when the RTC is disabled.
B. When using the ZCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same
source if the application only uses operating performance points (OPPs) that define a common power supply voltage
for VDD_MPU and VDD_CORE. The ZCE package option has the VDD_MPU domain merged with the VDD_CORE
domain.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and
the respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a
3.3-V power supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V
I/O power supplies.
E. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped
after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence
shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended
sequence. To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the
recommended sequence.
G. If all the 1.8-V supplies are not sourced from the same power supply, it is required to power up VDDS before other
1.8-V supplies. Further, it is also recommended to source VDDS and VDDSHvx [x = 1-6] when configured as 1.8V
from the same power supply.
图 6-6. Power-Supply Sequencing With RTC Feature Disabled
6.1.2 Power-Down Sequencing
PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies
are turned off. All other external clocks to the device should be shut off.
The preferred way to sequence power down is to have all the power supplies ramped down sequentially in
the exact reverse order of the power-up sequencing. In other words, the power supply that has been
ramped up first should be the last one that should be ramped down. This ensures there would be no
spurious current paths during the power-down sequence. The VDDS power supply must ramp down after
all 3.3-V VDDSHVx [1-6] power supplies.
If it is desired to ramp down VDDS and VDDSHVx [1-6] simultaneously, it should always be ensured that
the difference between VDDS and VDDSHVx [1-6] during the entire power-down sequence is <2 V. Any
violation of this could cause reliability risks for the device. TI recommends maintaining VDDS ≥1.5V as all
the other supplies fully ramp down to minimize in-rush currents.
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If none of the VDDSHVx [1-6] power supplies are configured as 3.3 V, the VDDS power supply may ramp
down along with the VDDSHVx [1-6] supplies or after all the VDDSHVx [1-6] supplies have ramped down.
TI recommends maintaining VDDS ≥1.5V as all the other supplies fully ramp down to minimize in-rush
currents.
6.1.3 VDD_MPU_MON Connections
图 6-7 shows the VDD_MPU_MON connectivity. VDD_MPU_MON connectivity is available only on the
ZCZ package.
VDD_MPU
Power
Management
IC
AM335x Device
VDD_MPU_MON
Vfeedback
Connection for VDD_MPU_MON if voltage monitoring is used
VDD_MPU
Power
Source
VDD_MPU_MON
AM335x Device
Preferred connection for VDD_MPU_MON if voltage monitoring is NOT used
VDD_MPU
Power
Source
AM335x Device
VDD_MPU_MON
N/C
Optional connection for VDD_MPU_MON if voltage monitoring is NOT used
图 6-7. VDD_MPU_MON Connectivity
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6.1.4 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AM335x device. The AM335x device integrates five different DPLLs—Core DPLL, Per DPLL, LCD
DPLL, DDR DPLL, MPU DPLL.
图 6-8 shows the power supply connectivity implemented in the AM335x device. 表 6-1 provides the power
supply requirements for the DPLL.
MPU
PLL
PER
PLL
VDDS_PLL_MPU
VDDA1P8V_USB0
CORE
PLL
DDR
PLL
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
LCD
PLL
图 6-8. DPLL Power Supply Connectivity
表 6-1. DPLL Power Supply Requirements
SUPPLY NAME
DESCRIPTION
MIN NOM MAX
UNIT
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V
Max peak-to-peak supply noise
1.71 1.8
1.71 1.8
1.71 1.8
1.71 1.8
1.89
V
VDDA1P8V_USB0
50 mV (p-p)
Supply voltage range for DPLL MPU, analog
Max peak-to-peak supply noise
1.89
V
VDDS_PLL_MPU
50 mV (p-p)
Supply voltage range for DPLL CORE and LCD, analog
Max peak-to-peak supply noise
1.89
V
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
50 mV (p-p)
Supply voltage range for DPLL DDR, analog
Max peak-to-peak supply noise
1.89
V
50 mV (p-p)
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6.2 Clock Specifications
6.2.1 Input Clock Specifications
The AM335x device has two clock inputs. Each clock input passes through an internal oscillator which can
be connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock
source (bypass mode). The oscillators automatically operate in bypass mode when their input is
connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a
specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass
mode.
The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected
to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator
(CLK_32K_RTC) in the AM335x and AMIC110 Sitara Processors Technical Reference Manual. OSC1 is
disabled by default after power is applied. This clock input is optional and may not be required if the RTC
is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL
(CLK_32KHZ) which receives a reference clock from the OSC0 input.
The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to
clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is
referred to as the master oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara Processors
Technical Reference Manual. OSC0 is enabled by default after power is applied.
For more information related to recommended circuit topologies and crystal oscillator circuit requirements
for these clock inputs, see 节 6.2.2.
6.2.2 Input Clock Requirements
6.2.2.1 OSC0 Internal Oscillator Clock Source
图 6-9 shows the recommended crystal circuit. TI recommends that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required
and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating
oscillator performance with production crystal circuit components installed on preproduction PCBs.
The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
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AM335x
XTALIN
VSS_OSC
XTALOUT
C1
C2
Crystal
Optional Rd
Optional Rbias
Copyright © 2016, Texas Instruments Incorporated
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the VSS_OSC and respective crystal circuit component grounds should be connected directly
to the nearest PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1
×
C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus
any mutual capacitance (Cpkg + CPCB) seen across the AM335x XTALIN and XTALOUT signals. For recommended
values of crystal circuit components, see 表 6-2.
图 6-9. OSC0 Crystal Circuit Schematic
表 6-2. OSC0 Crystal Circuit Requirements
PARAMETER
MIN
TYP
MAX
UNIT
Crystal parallel resonance
frequency
Fundamental mode oscillation only
19.2, 24,
25, or 26
MHz
ƒxtal
Crystal frequency stability
and tolerance(1)
–50
50
ppm
pF
C
shunt ≤ 5 pF
Cshunt > 5 pF
shunt ≤ 5 pF
12
18
12
18
24
24
24
24
7
CC1
C1 capacitance
C
CC2
C2 capacitance
pF
pF
Cshunt > 5 pF
Cshunt
Shunt capacitance
ƒxtal = 19.2 MHz, oscillator has nominal
negative resistance of 272 Ω and worst-
case negative resistance of 163 Ω
54.4
48.0
46.6
45.3
ƒxtal = 24 MHz, oscillator has nominal
negative resistance of 240 Ω and worst-
case negative resistance of 144 Ω
Crystal effective series
resistance
ESR
Ω
ƒxtal = 25 MHz, oscillator has nominal
negative resistance of 233 Ω and worst-
case negative resistance of 140 Ω
ƒxtal = 26 MHz, oscillator has nominal
negative resistance of 227 Ω and worst-
case negative resistance of 137 Ω
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
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表 6-3. OSC0 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
0.01
0.01
MAX
UNIT
ZCE package
ZCZ package
Shunt capacitance of
package
Cpkg
pF
The actual values of the ESR, ƒxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, ƒxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π ƒxtal
Pxtal
CL VDDS_OSC)2
tsX
Start-up time
1.5
ms
VDD_CORE (min.)
VDD_CORE
VSS
VDDS_OSC (min.)
VDDS_OSC
XTALOUT
VSS
tsX
Time
图 6-10. OSC0 Start-Up Time
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6.2.2.2 OSC0 LVCMOS Digital Clock Source
图 6-11 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-
wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. The ground
for the LVCMOS clock source and VSS_OSC should be connected directly to the nearest PCB digital
ground (VSS). In this mode of operation, the XTALOUT terminal should not be used to source any
external components. The PCB design should provide a mechanism to disconnect the XTALOUT terminal
from any external components or signal traces that may couple noise into OSC0 via the XTALOUT
terminal.
The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
AM335x
XTALIN
VSS_OSC
XTALOUT
VDDS_OSC
LVCMOS
Digital
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
图 6-11. OSC0 LVCMOS Circuit Schematic
表 6-4. OSC0 LVCMOS Reference Clock Requirements
NAME
ƒ(XTALIN)
DESCRIPTION
Frequency, LVCMOS reference clock
MIN
TYP
MAX
UNIT
MHz
ppm
19.2, 24, 25,
or 26
Frequency, LVCMOS reference clock stability and tolerance(1)
Duty cycle, LVCMOS reference clock period
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
–50
45%
–1%
50
55%
1%
5
tdc(XTALIN)
tjpp(XTALIN)
tR(XTALIN)
tF(XTALIN)
ns
ns
Time, LVCMOS reference clock fall
5
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
6.2.2.3 OSC1 Internal Oscillator Clock Source
图 6-12 shows the recommended crystal circuit for OSC1 of the ZCE package and 图 6-13 shows the
recommended crystal circuit for OSC1 of the ZCZ package. TI recommends that preproduction PCB
designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required
and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating
oscillator performance with production crystal circuit components installed on preproduction PCBs.
The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is
disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level
which may increase leakage current through the oscillator input buffer.
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AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
Optional Rbias
Optional Rd
Crystal
C1
C2
Copyright © 2016, Texas Instruments Incorporated
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the
oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest
PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1
×
C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus
any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see 表 6-5.
图 6-12. OSC1 (ZCE Package) Crystal Circuit Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
C1
C2
Crystal
Optional Rd
Optional Rbias
Copyright © 2016, Texas Instruments Incorporated
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the AM335x package.
Parasitic capacitance to the PCB ground and other signals should be minimized to reduce noise coupled into the
oscillator. VSS_RTC and respective crystal circuit component grounds should be connected directly to the nearest
PCB digital ground (VSS).
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL = [(C1
×
C2) / (C1 + C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer plus
any mutual capacitance (Cpkg + CPCB) seen across the AM335x RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see 表 6-5.
图 6-13. OSC1 (ZCZ Package) Crystal Circuit Schematic
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表 6-5. OSC1 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Crystal parallel resonance
frequency
Fundamental mode oscillation only
32.768
kHz
Maximum RTC error = 10.512 minutes
per year
ƒxtal
–20.0
–50.0
20.0
50.0
ppm
ppm
Crystal frequency stability
and tolerance(1)
Maximum RTC error = 26.28 minutes per
year
CC1
C1 capacitance
C2 capacitance
Shunt capacitance
12.0
12.0
24.0
24.0
1.5
pF
pF
pF
CC2
Cshunt
ƒxtal = 32.768 kHz, oscillator has nominal
negative resistance of 725 kΩ and worst-
case negative resistance of 250 kΩ
Crystal effective series
resistance
ESR
80
kΩ
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
表 6-6. OSC1 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
0.17
0.01
MAX
UNIT
pF
ZCE package
ZCZ package
Shunt capacitance of
package
Cpkg
pF
The actual values of the ESR, ƒxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, ƒxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π ƒxtal CL
Pxtal
VDDS_RTC)2
tsX
Start-up time
2
s
CAP_VDD_RTC (min.)
CAP_VDD_RTC
VSS_RTC
VDDS_RTC (min.)
VDDS_RTC
RTC_XTALOUT
VSS_RTC
tsX
Time
图 6-14. OSC1 Start-up Time
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6.2.2.4 OSC1 LVCMOS Digital Clock Source
图 6-15 shows the recommended oscillator connections when OSC1 of the ZCE package is connected to
an LVCMOS square-wave digital clock source and 图 6-16 shows the recommended oscillator
connections when OSC1 of the ZCZ package is connected to an LVCMOS square-wave digital clock
source. The LVCMOS clock source is connected to the RTC_XTALIN terminal. The ground for the
LVCMOS clock source and VSS_RTC of the ZCZ package should be connected directly to the nearest
PCB digital ground (VSS). In this mode of operation, the RTC_XTALOUT terminal should not be used to
source any external components. The PCB design should provide a mechanism to disconnect the
RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1
through the RTC_XTALOUT terminal.
The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is
disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level
which may increase leakage current through the oscillator input buffer.
AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
VDDS_RTC
LVCMOS
Digital
Clock
N/C
Source
Copyright © 2016, Texas Instruments Incorporated
图 6-15. OSC1 (ZCE Package) LVCMOS Circuit Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
VDDS_RTC
LVCMOS
Digital
Clock
N/C
Source
Copyright © 2016, Texas Instruments Incorporated
图 6-16. OSC1 (ZCZ Package) LVCMOS Circuit Schematic
表 6-7. OSC1 LVCMOS Reference Clock Requirements
NAME
DESCRIPTION
MIN
TYP MAX
32.768
UNIT
Frequency, LVCMOS reference clock
kHz
Maximum RTC error =
10.512 minutes/year
–20
–50
20
50
ppm
ppm
ƒ(RTC_XTALIN)
Frequency, LVCMOS reference clock
stability and tolerance(1)
Maximum RTC error = 26.28
minutes/year
tdc(RTC_XTALIN)
tjpp(RTC_XTALIN)
tR(RTC_XTALIN)
tF(RTC_XTALIN)
Duty cycle, LVCMOS reference clock period
45%
–1%
55%
1%
5
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
ns
ns
Time, LVCMOS reference clock fall
5
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
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6.2.2.5 OSC1 Not Used
图 6-17 shows the recommended oscillator connections when OSC1 of the ZCE package is not used and
图 6-18 shows the recommended oscillator connections when OSC1 of the ZCZ package is not used. An
internal 10-kΩ pullup on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this
input from floating to an invalid logic level which may increase leakage current through the oscillator input
buffer. OSC1 is disabled by default after power is applied. Therefore, both RTC_XTALIN and
RTC_XTALOUT terminals should be a no connect (NC) when OSC1 is not used.
AM335x
(ZCE Package)
RTC_XTALIN
RTC_XTALOUT
N/C
N/C
Copyright © 2016, Texas Instruments Incorporated
图 6-17. OSC1 (ZCE Package) Not Used Schematic
AM335x
(ZCZ Package)
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
N/C
N/C
Copyright © 2016, Texas Instruments Incorporated
图 6-18. OSC1 (ZCZ Package) Not Used Schematic
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6.2.3 Output Clock Specifications
The AM335x device has two clock output signals. The CLKOUT1 signal is always a replica of the OSC0
input clock which is referred to as the master oscillator (CLK_M_OSC) in the AM335x and AMIC110 Sitara
Processors Technical Reference Manual. The CLKOUT2 signal can be configured to output the OSC1
input clock, which is referred to as the 32K oscillator (CLK_32K_RTC) in the AM335x and AMIC110 Sitara
Processors Technical Reference Manual, or four other internal clocks. For more information related to
configuring these clock output signals, see the CLKOUT Signals section of the AM335x and AMIC110
Sitara Processors Technical Reference Manual.
6.2.4 Output Clock Characteristics
注
The AM335x CLKOUT1 and CLKOUT2 clock outputs should not be used as a synchronous
clock for any of the peripheral interfaces because they were not timing closed to any other
signals. These clock outputs also were not designed to source any time critical external
circuits that require a low jitter reference clock. The jitter performance of these outputs is
unpredictable due to complex combinations of many system variables. For example,
CLKOUT2 may be sourced from several PLLs with each PLL supporting many configurations
that yield different jitter performance. There are also other unpredictable contributors to jitter
performance such as application specific noise or crosstalk into the clock circuits. Therefore,
there are no plans to specify jitter performance for these outputs.
6.2.4.1 CLKOUT1
The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must be
configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.
The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level
applied to the LCD_DATA5 terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0
multiplexer is configured to Mode 7 if the LCD_DATA5 terminal is low on the rising edge of PWRONRSTn
or Mode 3 if the LCD_DATA5 terminal is high on the rising edge of PWRONRSTn. This allows the
CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this
mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is
released.
6.2.4.2 CLKOUT2
The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one
of seven internal signals via configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must be
configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.
The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must
configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the
XDMA_EVENT_INTR1 terminal.
114
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7 Peripheral Information and Timings
The AM335x device contains many peripheral interfaces. In order to reduce package size and lower
overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex
up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,
only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O Sets were
carefully chosen to provide many possible application scenarios for the user.
Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system
designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The
Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin-
multiplexing configuration selected for a design only uses valid I/O Sets supported by the AM335x device.
7.1 Parameter Information
The data provided in the following Timing Requirements and Switching Characteristics tables assumes the
device is operating within the Recommended Operating Conditions defined in 节 5, unless otherwise
noted.
7.1.1 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control
register is configured for fast mode (0b).
For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS
models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the
routing rules to ensure the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface timings are met.
7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
7.3 OPP50 Support
Some peripherals and features have limited support when the device is operating in OPP50. A complete
list of these limitations follows.
Not supported when operating in OPP50:
Reduced performance when operating in
OPP50:
•
•
•
•
•
•
•
CPSW
•
•
•
•
•
•
•
•
DDR2
DDR3
DEBUGSS-JTAG
GPMC Synchronous Mode
LCDC Raster Mode
LPDDR
DEBUGSS-Trace
GPMC Asynchronous Mode
LCDC LIDD Mode
MDIO
McASP
PRU-ICSS MII
McSPI
MMCSD
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7.4 Controller Area Network (CAN)
For more information, see the Controller Area Network (CAN) section of the AM335x and AMIC110 Sitara
Processors Technical Reference Manual.
7.4.1 DCAN Electrical Data and Timing
表 7-1. DCAN Timing Conditions
(see 图 7-1)
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
10
10
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
10
pF
表 7-2. Timing Requirements for DCANx Receive
(see 图 7-1)
NO.
MIN
MAX
1
H + 2(1)
UNIT
Mbps
ns
ƒbaud(baud)
tw(RX)
(1) H = Period of baud rate, 1 / programmed baud rate
Maximum programmable baud rate
1
Pulse duration, receive data bit
H – 2(1)
表 7-3. Switching Characteristics for DCANx Transmit
(see 图 7-1)
NO.
PARAMETER
Maximum programmable baud rate
Pulse duration, transmit data bit
MIN
MAX
1
H + 2(1)
UNIT
Mbps
ns
ƒbaud(baud)
tw(TX)
2
H – 2(1)
(1) H = Period of baud rate, 1 / programmed baud rate
1
DCANx_RX
2
DCANx_TX
图 7-1. DCANx Timings
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7.5 DMTimer
7.5.1 DMTimer Electrical Data and Timing
表 7-4. DMTimer Timing Conditions
(see 图 7-1)
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
10
10
ns
ns
Output Conditions
CLOAD
Output load capacitance
2
10
pF
表 7-5. Timing Requirements for DMTimer [1-7]
(see 图 7-2)
NO.
MIN
MAX
UNIT
1
tc(TCLKIN)
Cycle time, TCLKIN
4P + 1(1)
ns
(1) P = Period of PICLKOCP (interface clock).
表 7-6. Switching Characteristics for DMTimer [4-7]
(see 图 7-2)
NO.
PARAMETER
MIN
4P – 3(1)
4P – 3(1)
MAX
UNIT
ns
2
3
tw(TIMERxH)
tw(TIMERxL)
Pulse duration, high
Pulse duration, low
ns
(1) P = Period of PICLKTIMER (functional clock).
1
TCLKIN
2
3
TIMER[x]
图 7-2. Timer Timing
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7.6 Ethernet Media Access Controller (EMAC) and Switch
7.6.1 EMAC and Switch Electrical Data and Timing
The EMAC and Switch implemented in the AM335x device supports GMII mode, but the AM335x design
does not pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals.
Therefore, the AM335x device does not support GMII mode. MII mode is supported with the remaining
GMII signals.
The AM335x and AMIC110 Sitara Processors Technical Reference Manual and this document may
reference internal signal names when discussing peripheral input and output signals because many of the
AM335x package terminals can be multiplexed to one of several peripheral signals. For example, the
AM335x terminal names for port 1 of the EMAC and switch have been changed from GMII to MII to
indicate their Mode 0 function, but the internal signal is named GMII. However, documents that describe
the Ethernet switch reference these signals by their internal signal name. For a cross-reference of internal
signal names to terminal names, see 表 4-2.
Operation of the EMAC and switch is not supported for OPP50.
表 7-7. EMAC and Switch Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
5(1)
5(1)
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
(1) Except when specified otherwise.
7.6.1.1 EMAC/Switch MDIO Electrical Data and Timing
表 7-8. Timing Requirements for MDIO_DATA
(see 图 7-3)
NO.
1
MIN
TYP
MAX
UNIT
ns
tsu(MDIO-MDC) Setup time, MDIO valid before MDC high
90
0
2
th(MDIO-MDC)
Hold time, MDIO valid from MDC high
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
图 7-3. MDIO_DATA Timing - Input Mode
表 7-9. Switching Characteristics for MDIO_CLK
(see 图 7-4)
NO.
1
PARAMETER
Cycle time, MDC
MIN
400
160
160
TYP
MAX
UNIT
ns
tc(MDC)
2
tw(MDCH)
tw(MDCL)
Pulse duration, MDC high
Pulse duration, MDC low
ns
3
ns
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1
2
3
MDIO_CLK
图 7-4. MDIO_CLK Timing
表 7-10. Switching Characteristics for MDIO_DATA
(see 图 7-5)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
(P*0.5)
-10(1)
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
10
ns
(1) P = MDIO_CLK Period
1
MDIO_CLK (Output)
MDIO_DATA (Output)
图 7-5. MDIO_DATA Timing - Output Mode
7.6.1.2 EMAC and Switch MII Electrical Data and Timing
表 7-11. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see 图 7-6)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, RX_CLK high
Pulse duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
5
5
1
4
2
3
GMII[x]_RXCLK
4
图 7-6. GMII[x]_RXCLK Timing - MII Mode
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表 7-12. Timing Requirements for GMII[x]_TXCLK - MII Mode
(see 图 7-7)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
1
2
3
4
tc(TX_CLK)
Cycle time, TX_CLK
40.004
ns
ns
ns
ns
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
26
26
5
140
260
14
5
1
4
2
3
GMII[x]_TXCLK
4
图 7-7. GMII[x]_TXCLK Timing - MII Mode
表 7-13. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
(see 图 7-8)
10 Mbps
TYP
100 Mbps
TYP
NO
.
UNIT
MIN
MAX
MIN
MAX
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
1
2
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
8
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
ns
1
2
GMII[x]_MRCLK (Input)
GMII[x]_RXD[3:0], GMII[x]_RXDV,
GMII[x]_RXER (Inputs)
图 7-8. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode
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表 7-14. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
(see 图 7-9)
10 Mbps
TYP
100 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
1
5
25
5
25 ns
1
GMII[x]_TXCLK (input)
GMII[x]_TXD[3:0],
GMII[x]_TXEN (outputs)
图 7-9. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode
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7.6.1.3 EMAC and Switch RMII Electrical Data and Timing
表 7-15. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see 图 7-10)
NO.
MIN
TYP
MAX
UNIT
ns
1
2
3
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
Cycle time, REF_CLK
19.999
20.001
13
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
7
7
ns
13
ns
1
2
RMII[x]_REFCLK
(Input)
3
图 7-10. RMII[x]_REFCLK Timing - RMII Mode
表 7-16. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see 图 7-11)
NO.
MIN
TYP
MAX
UNIT
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, RXD[1:0] valid before REF_CLK
Setup time, CRS_DV valid before REF_CLK
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
1
4
ns
2
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
1
2
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
图 7-11. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
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表 7-17. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
(see 图 7-12)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
td(REF_CLK-TXD)
td(REF_CLK-TXEN)
Delay time, REF_CLK high to TXD[1:0] valid Delay time,
REF_CLK to TXEN valid
1
2
13
ns
1
RMII[x]_REFCLK (Input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (Outputs)
图 7-12. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode
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7.6.1.4 EMAC and Switch RGMII Electrical Data and Timing
表 7-18. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see 图 7-13)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
1
2
tc(RXC)
Cycle time, RXC
360
440
36
44
7.2
8.8 ns
Pulse duration, RXC
high
tw(RXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(RXCL)
tt(RXC)
Pulse duration, RXC low
Transition time, RXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
2
3
RGMII[x]_RCLK
图 7-13. RGMII[x]_RCLK Timing - RGMII Mode
表 7-19. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see 图 7-14)
10 Mbps
TYP MAX
100 Mbps
1000 Mbps
MIN TYP MAX
NO.
UNIT
MIN
MIN
TYP MAX
Setup time, RD[3:0] valid
before RXC high or low
tsu(RD-RXC)
tsu(RX_CTL-RXC)
th(RXC-RD)
1
1
1
1
1
1
1
1
1
1
2
ns
Setup time, RX_CTL valid
before RXC high or low
1
1
1
Hold time, RD[3:0] valid after
RXC high or low
ns
Hold time, RX_CTL valid after
RXC high or low
th(RXC-RX_CTL)
RGMII[x]_RCLK(A)
1
1st Half-byte
2nd Half-byte
2
RGMII[x]_RD[3:0](B)
RGMII[x]_RCTL(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
图 7-14. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
表 7-20. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see 图 7-15)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
tc(TXC)
Cycle time, TXC
360
440
36
44
7.2
8.8 ns
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表 7-20. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode (continued)
(see 图 7-15)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
160
160
MAX
240
MIN
16
MAX
24
MIN
3.6
MAX
Pulse duration, TXC
high
2
3
tw(TXCH)
tw(TXCL)
4.4 ns
Pulse duration, TXC low
240
16
24
3.6
4.4 ns
1
2
3
RGMII[x]_TCLK
图 7-15. RGMII[x]_TCLK Timing - RGMII Mode
表 7-21. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see 图 7-16)
10 Mbps
TYP MAX
100 Mbps
1000 Mbps
MIN TYP MAX
NO.
PARAMETER
UNIT
MIN
–0.5
–0.5
MIN
TYP MAX
tsk(TD-TXC)
TD to TXC output skew
0.5
0.5
–0.5
–0.5
0.5
0.5
–0.5
–0.5
0.5
0.5
1
ns
tsk(TX_CTL-TXC)
TX_CTL to TXC output skew
RGMII[x]_TCLK(A)
1
1
RGMII[x]_TD[3:0](B)
RGMII[x]_TCTL(B)
1st Half-byte
2nd Half-byte
TXEN
TXERR
A. The EMAC and switch implemented in the AM335x device supports internal delay mode, but timing closure was not
performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
图 7-16. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
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7.7 External Memory Interfaces
The device includes the following external memory interfaces:
•
•
General-purpose memory controller (GPMC)
mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface (EMIF)
7.7.1 General-Purpose Memory Controller (GPMC)
注
For more information, see the Memory Subsystem and General-Purpose Memory Controller
section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
The GPMC is the unified memory controller used to interface external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
7.7.1.1 GPMC and NOR Flash—Synchronous Mode
表 7-23 and 表 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in 表 7-22 (see 图 7-17 through 图 7-21).
表 7-22. GPMC and NOR Flash Timing Conditions—Synchronous Mode
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
表 7-23. GPMC and NOR Flash Timing Requirements—Synchronous Mode
OPP100
MIN
OPP50
NO.
UNIT
MAX
MIN
MAX
Setup time, input data gpmc_ad[15:0] valid before output clock
gpmc_clk high
F12 tsu(dV-clkH)
3.2
13.2
ns
Industrial extended
Hold time, input data gpmc_ad[15:0]
temperature
4.74
4.74
F13 th(clkH-dV)
valid after output clock gpmc_clk
(-40°C to 125°C)
ns
ns
ns
high
All other temperature ranges
4.74
3.2
2.75
13.2
Setup time, input wait gpmc_wait[x](1) valid before output clock
gpmc_clk high
F21 tsu(waitV-clkH)
Industrial extended
Hold time, input wait gpmc_wait[x](1)
temperature
4.74
4.74
4.74
2.75
F22 th(clkH-waitV)
valid after output clock gpmc_clk
(-40°C to 125°C)
high
All other temperature ranges
(1) In gpmc_wait[x], x is equal to 0 or 1.
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表 7-24. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
100
MAX
F0
F1
F1
1 / tc(clk)
Frequency(18), output clock gpmc_clk
50 MHz
tw(clkH)
tw(clkL)
tdc(clk)
tJ(clk)
Typical pulse duration, output clock gpmc_clk high
Typical pulse duration, output clock gpmc_clk low
Duty cycle error, output clock gpmc_clk
0.5P(15)
0.5P(15)
0.5P(15)
500
0.5P(15)
0.5P(15)
–500
0.5P(15)
0.5P(15)
ns
ns
ps
ps
0.5P(15)
–500
500
Jitter standard deviation(19), output clock gpmc_clk
33.33
33.33
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x](14) transition
F2
F3
F4
F5
td(clkH-csnV)
td(clkH-csnIV)
td(aV-clk)
F(6) - 2.2 F(6) + 4.5
F(6) - 3.2
F(6) + 9.5
E(5) + 9.5
ns
ns
ns
ns
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x](14) invalid
E(5) – 2.2 E(5) + 4.5 E(5) – 3.2
Delay time, output address gpmc_a[27:1] valid to
output clock gpmc_clk first edge
B(2) – 4.5 B(2) + 2.3 B(2) – 5.5 B(2) + 12.3
–2.3 4.5 –3.3 14.5
Delay time, output clock gpmc_clk rising edge to
output address gpmc_a[27:1] invalid
td(clkH-aIV)
Delay time, output lower byte enable and command
latch enable gpmc_be0n_cle, output upper byte
enable gpmc_be1n valid to output clock gpmc_clk
first edge
F6
F7
td(be[x]nV-clk)
B(2) – 1.9 B(2) + 2.3 B(2) – 2.9 B(2) + 12.3
ns
ns
Delay time, output clock gpmc_clk rising edge to
output lower byte enable and command latch enable
gpmc_be0n_cle, output upper byte enable
gpmc_be1n invalid(11)
td(clkH-be[x]nIV)
D(4) – 2.3 D(4) + 1.9 D(4) – 3.3
D(4) – 2.3 D(4) + 1.9 D(4) – 3.3
D(4) + 6.9
D(4) + 6.9
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid(12)
F7
F7
td(clkL-be[x]nIV)
td(clkL-be[x]nIV)
ns
ns
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid(13)
D(4) – 2.3 D(4) + 1.9 D(4) – 3.3 D(4) + 11.9
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale transition
F8
F9
td(clkH-advn)
G(7) – 2.3 G(7) + 4.5 G(7) – 3.3
D(4) – 2.3 D(4) + 3.5 D(4) – 3.3
G(7) + 9.5
D(4) + 9.5
ns
ns
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale invalid
td(clkH-advnIV)
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen transition
F10
F11
F14
F15
F15
F15
td(clkH-oen)
td(clkH-oenIV)
td(clkH-wen)
td(clkH-do)
td(clkL-do)
H(8) – 2.3 H(8) + 3.5 H(8) – 3.3
H(8) – 2.3 H(8) + 3.5 H(8) – 3.3
H(8) + 8.5
H(8) + 8.5
I(9) + 9.5
ns
ns
ns
ns
ns
ns
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen invalid
Delay time, output clock gpmc_clk rising edge to
output write enable gpmc_wen transition
I(9) – 2.3
I(9) + 4.5
I(9) – 3.3
Delay time, output clock gpmc_clk rising edge to
output data gpmc_ad[15:0] transition(11)
J(10) – 2.3 J(10) + 1.9 J(10) – 3.3
J(10) – 2.3 J(10) + 1.9 J(10) – 3.3
J(10) + 6.9
J(10) + 6.9
Delay time, gpmc_clk falling edge to gpmc_ad[15:0]
data bus transition(12)
Delay time, gpmc_clk falling edge to gpmc_ad[15:0]
data bus transition(13)
td(clkL-do)
J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 11.9
Delay time, output clock gpmc_clk rising edge to
F17
td(clkH-be[x]n)
output lower byte enable and command latch enable J(10) – 2.3 J(10) + 1.9 J(10) – 3.3
gpmc_be0n_cle transition(11)
J(10) + 6.9
J(10) + 6.9
ns
Delay time, gpmc_clk falling edge to
J(10) – 2.3 J(10) + 1.9 J(10) – 3.3
gpmc_nbe0_cle, gpmc_nbe1 transition(12)
F17
F17
td(clkL-be[x]n)
td(clkL-be[x]n)
ns
ns
Delay time, gpmc_clk falling edge to
J(10) – 2.3 J(10) + 1.9 J(10) – 3.3 J(10) + 11.9
gpmc_nbe0_cle, gpmc_nbe1 transition(13)
Read
Write
Read
Write
A(1)
A(1)
C(3)
A(1)
A(1)
C(3)
ns
ns
ns
Pulse duration, output chip select
gpmc_csn[x](14) low
F18
F19
tw(csnV)
Pulse duration, output lower byte enable
and command latch enable
gpmc_be0n_cle, output upper byte enable
gpmc_be1n low
tw(be[x]nV)
C(3)
C(3)
ns
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表 7-24. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2) (continued)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Read
Write
K(16)
K(16)
K(16)
K(16)
ns
ns
Pulse duration, output address valid and
address latch enable gpmc_advn_ale low
F20
tw(advnV)
(1) For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK (17)
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(5) For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
–
Case GpmcFCLKDivider = 0:
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
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(8) For OE falling edge (OE activated) and I/O DIR rising edge (Data Bus input direction):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
–
Case GpmcFCLKDivider = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
–
Case GpmcFCLKDivider = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
(14) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
(15) P = gpmc_clk period in ns
(16) For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(19) The jitter probability density can be approximated by a Gaussian function.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csn[x]
gpmc_a[10:1]
F4
F6
Valid Address
F7
F19
F19
gpmc_be0n_cle
gpmc_be1n
F6
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
图 7-17. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
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F1
F1
F0
gpmc_clk
gpmc_csn[x]
gpmc_a[10:1]
gpmc_be0n_cle
gpmc_be1n
F2
F3
F4
F6
Valid Address
F7
F7
F6
F8
F8
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F13
F12
D 0
F21
F12
D 3
gpmc_ad[15:0]
gpmc_wait[x]
D 1
D 2
F22
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
图 7-18. GPMC and NOR Flash—Synchronous Burst Read—4x16-Bit (GpmcFCLKDivider = 0)
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F1
F1
F0
gpmc_clk
gpmc_csn[x]
gpmc_a[10:1]
F2
F3
F4
F6
Valid Address
F17
F17
F17
F17
F17
F17
gpmc_be0n_cle
gpmc_be1n
gpmc_advn_ale
gpmc_wen
F6
F8
F8
F9
F14
F14
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
gpmc_wait[x]
D 0
D 3
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
图 7-19. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x]
gpmc_be0n_cle
gpmc_be1n
F6
F6
F4
F7
Valid
F7
Valid
gpmc_a[27:17]
Address (MSB)
F5
F12
F13
F4
F12
gpmc_ad[15:0]
gpmc_advn_ale
gpmc_oen
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
F10
F11
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
图 7-20. GPMC and Multiplexed NOR Flash—Synchronous Burst Read
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csn[x]
F4
F6
F6
gpmc_a[27:17]
Address (MSB)
F17
F17
F17
F17
F17
F17
gpmc_be1n
gpmc_be0n_cle
gpmc_advn_ale
F8
F8
F20
F9
F14
F14
gpmc_wen
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
Address (LSB)
D 0
D 3
F22
F21
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
B. In gpmc_wait[x], x is equal to 0 or 1.
图 7-21. GPMC and Multiplexed NOR Flash—Synchronous Burst Write
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7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
表 7-26 and 表 7-27 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in 表 7-25 (see 图 7-22 through 图 7-27).
表 7-25. GPMC and NOR Flash Timing Conditions—Asynchronous Mode
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
表 7-26. GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
FI1
FI2
FI3
FI4
FI5
6.5
6.5
ns
ns
ns
ns
ns
Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
4
6.5
6.5
6.5
4
6.5
6.5
6.5
Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle,
FI6 output upper-byte enable gpmc_be1n generation from internal functional clock
6.5
6.5
6.5
6.5
ns
ns
GPMC_FCLK(3)
Delay time, output enable gpmc_oen generation from internal functional clock
FI7
GPMC_FCLK(3)
Delay time, output write enable gpmc_wen generation from internal functional
FI8
6.5
6.5
ns
ps
clock GPMC_FCLK(3)
FI9 Skew, internal functional clock GPMC_FCLK(3)
100
100
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
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表 7-27. GPMC and NOR Flash Timing Requirements—Asynchronous Mode
NO.
OPP100
MIN
OPP50
MIN
UNIT
MAX
H(5)
P(4)
MAX
H(5)
P(4)
H(5)
FA5(1)
FA20(2) tacc1-pgmode(d)
FA21(3) tacc2-pgmode(d)
tacc(d)
Data access time
ns
ns
ns
Page mode successive data access time
Page mode first data access time
H(5)
(1) The FA5 parameter shows the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter shows amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter shows amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
表 7-28. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
FA0
FA1
FA3
PARAMETER
UNIT
ns
MAX
N(12)
MAX
N(12)
Pulse duration, output lower-byte
enable and command latch enable
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
Read
Write
tw(be[x]nV)
N(12)
N(12)
Read
Write
Read
A(1)
A(1)
A(1)
A(1)
B(2) + 5
Pulse duration, output chip select
gpmc_csn[x](13) low
tw(csnV)
ns
Delay time, output chip select
gpmc_csn[x](13) valid to output
address valid and address latch
enable gpmc_advn_ale invalid
B(2) – 0.2
B(2) – 0.2
B(2) + 2.0
B(2) – 5
B(2) – 5
td(csnV-advnIV)
ns
Write
B(2) + 2.0
B(2) + 5
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Single
read)
FA4
FA9
td(csnV-oenIV)
C(3) – 0.2
J(9) – 0.2
C(3) + 2.0
J(9) + 2.0
C(3) – 5
J(9) – 5
C(3) + 5
J(9) + 5
ns
ns
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_csn[x](13) valid
td(aV-csnV)
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle, output
upper-byte enable gpmc_be1n valid to output
chip select gpmc_csn[x](13) valid
FA10 td(be[x]nV-csnV)
J(9) – 0.2
J(9) + 2.0
J(9) – 5
J(9) + 5
ns
Delay time, output chip select gpmc_csn[x](13)
valid to output address valid and address latch
enable gpmc_advn_ale valid
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
K(10) – 0.2 K(10) + 2.0
L(11) – 0.2 L(11) + 2.0
G(7)
K(10) – 5
K(10) + 5
L(11) + 5
ns
ns
ns
L
(11) – 5
G(7)
Pulse durationm output address gpmc_a[26:1]
invalid between 2 successive read and write
accesses
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen invalid (Burst
read)
FA18 td(csnV-oenIV)
I(8) – 0.2
I(8) + 2.0
I(8) – 5
I(8) + 5
ns
Pulse duration, output address gpmc_a[27:1]
valid - 2nd, 3rd, and 4th accesses
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen invalid
FA20 tw(aV)
D(4)
E(5) – 0.2
F(6) – 0.2
D(4)
E(5) – 5
F(6) – 5
ns
ns
ns
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
E(5) + 2.0
F(6) + 2.0
E(5) + 5
F(6) + 5
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表 7-28. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued)
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Delay time, output write enable gpmc_ wen
valid to output data gpmc_ad[15:0] valid
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
2.0
5
ns
ns
ns
Delay time, output data gpmc_ad[15:0] valid to
output chip select gpmc_csn[x](13) valid
J(9) – 0.2
J(9) + 2.0
J(9) – 5
J(9) + 5
5
Delay time, output enable gpmc_oen valid to
output address gpmc_ad[15:0] phase end
2.0
(1) For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csn[x]
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen
Data IN 0
Data IN 0
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图 7-22. GPMC and NOR Flash—Asynchronous Read—Single Word
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csn[x]
gpmc_a[10:1]
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
FA10
FA10
Valid
FA0
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen
Data Upper
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图 7-23. GPMC and NOR Flash—Asynchronous Read—32-Bit
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GPMC_FCLK
gpmc_clk
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
gpmc_csn[x]
FA9
Add0
Add4
gpmc_a[10:1]
FA0
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen
D3
D0
D1
D2
D3
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图 7-24. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
gpmc_a[10:1]
FA9
Valid Address
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_wait[x]
FA29
Data OUT
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
图 7-25. GPMC and NOR Flash—Asynchronous Write—Single Word
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csn[x]
FA9
Address (MSB)
FA0
gpmc_a[27:17]
gpmc_be0n_cle
gpmc_be1n
FA10
FA10
Valid
FA0
Valid
FA3
FA12
gpmc_advn_ale
gpmc_oen
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
gpmc_ad[15:0]
gpmc_wait[x]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图 7-26. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word
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gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x]
gpmc_a[27:17]
FA9
Address (MSB)
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_wait[x]
FA29
FA28
Valid Address (LSB)
Data OUT
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
图 7-27. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word
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7.7.1.3 GPMC and NAND Flash—Asynchronous Mode
表 7-30 and 表 7-31 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in 表 7-29 (see 图 7-28 through 图 7-31).
表 7-29. GPMC and NAND Flash Timing Conditions—Asynchronous Mode
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
表 7-30. GPMC and NAND Flash Internal Timing Requirements—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
Delay time, output data gpmc_ad[15:0] generation from internal
functional clock GPMC_FCLK(3)
GNFI1
GNFI2
GNFI3
6.5
6.5
ns
ns
ns
Delay time, input data gpmc_ad[15:0] capture from internal functional
clock GPMC_FCLK(3)
4.0
6.5
4.0
6.5
Delay time, output chip select gpmc_csn[x] generation from internal
functional clock GPMC_FCLK(3)
Delay time, output address valid and address latch enable
GNFI4 gpmc_advn_ale generation from internal functional clock
6.5
6.5
ns
GPMC_FCLK(3)
Delay time, output lower-byte enable and command latch enable
GNFI5 gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
Delay time, output enable gpmc_oen generation from internal functional
GNFI6
clock GPMC_FCLK(3)
Delay time, output write enable gpmc_wen generation from internal
GNFI7
6.5
6.5
ns
ps
functional clock GPMC_FCLK(3)
GNFI8 Skew, functional clock GPMC_FCLK(3)
100
100
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
表 7-31. GPMC and NAND Flash Timing Requirements—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
J(2)
MAX
J(2)
GNF12(1) tacc(d)
Access time, input data gpmc_ad[15:0]
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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表 7-32. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Pulse duration, output write enable gpmc_wen
valid
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
GNF0 tw(wenV)
A(1)
A(1)
ns
ns
GNF1 td(csnV-wenV)
B(2) – 0.2
B(2) + 2.0
B(2) – 5
B(2) + 5
C(3) + 5
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle high to
output write enable gpmc_wen valid
GNF2 tw(cleH-wenV)
C(3) – 0.2 C(3) + 2.0
D(4) – 0.2 D(4) + 2.0
C(3) – 5
ns
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
D(4) – 5
E(5) – 5
D(4) + 5
E(5) + 5
ns
ns
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E(5) – 0.2
F(6) – 0.2
E(5) + 5
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable and command
latch enable gpmc_be0n_cle invalid
GNF5 tw(wenIV-cleIV)
GNF6 tw(wenIV-csnIV)
GNF7 tw(aleH-wenV)
GNF8 tw(wenIV-aleIV)
F(6) + 2.0
F(6) – 5
G(7) – 5
C(3) – 5
F(6) – 5
F(6) + 5
G(7) + 5
C(3) + 5
F(6) + 5
ns
ns
ns
ns
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x](13)
invalid
G(7) – 0.2 G(7) + 2.0
C(3) – 0.2 C(3) + 2.0
Delay time, output address valid and address
latch enable gpmc_advn_ale high to output write
enable gpmc_wen valid
Delay time, output write enable gpmc_wen
invalid to output address valid and address latch
enable gpmc_advn_ale invalid
F(6) – 0.2
F(6) + 2.0
GNF9 tc(wen)
Cycle time, write
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
H(8)
I(9) + 2.0
K(10)
H(8)
I(9) + 5
K(10)
ns
ns
GNF10 td(csnV-oenV)
I(9) – 0.2
I(9) – 5
GNF13 tw(oenV)
GNF14 tc(oen)
Pulse duration, output enable gpmc_oen valid
Cycle time, read
ns
ns
L(11)
L(11)
Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x](13) invalid
GNF15 tw(oenIV-csnIV)
M(12) – 0.2 M(12) + 2.0
M(12) – 5
M(12) + 5
ns
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK(14)
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(5) E = ((WrCycleTime – WEOffTime) × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(6) F = ((ADVWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay)) × GPMC_FCLK(14)
(7) G = ((CSWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay)) × GPMC_FCLK(14)
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(9) I = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(12) M = ((CSRdOffTime – OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay)) × GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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GPMC_FCLK
GNF1
GNF6
GNF5
gpmc_csn[x]
GNF2
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Command
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
图 7-28. GPMC and NAND Flash—Command Latch Cycle
GPMC_FCLK
gpmc_csn[x]
GNF1
GNF7
GNF6
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF8
GNF9
GNF0
gpmc_wen
GNF3
GNF4
Address
gpmc_ad[15:0]
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
图 7-29. GPMC and NAND Flash—Address Latch Cycle
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
GNF14
GNF13
gpmc_oen
gpmc_ad[15:0]
DATA
gpmc_wait[x]
(1) GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
图 7-30. GPMC and NAND Flash—Data Read Cycle
GPMC_FCLK
GNF1
GNF6
gpmc_csn[x]
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
(1) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
图 7-31. GPMC and NAND Flash—Data Write Cycle
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7.7.2 mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
The device has a dedicated interface to mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM. It supports
JEDEC standard compliant mDDR(LPDDR), DDR2, DDR3, and DDR3L SDRAM devices with a 16-bit
data path to external SDRAM memory.
For more details on the mDDR(LPDDR), DDR2, DDR3, and DDR3L memory interface, see the EMIF
section of the AM335x and AMIC110 Sitara Processors Technical Reference Manual.
7.7.2.1 mDDR (LPDDR) Routing Guidelines
It is common to find industry references to mobile double data rate (mDDR) when discussing JEDEC
defined low-power double-data rate (LPDDR) memory devices. The following guidelines use LPDDR when
referencing JEDEC defined low-power double-data rate memory devices.
7.7.2.1.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the LPDDR memory interface are shown in 表 7-33 and 图 7-32.
表 7-33. Switching Characteristics for LPDDR Memory Interface
NO.
PARAMETER
MIN
MAX
UNIT
tc(DDR_CK)
tc(DDR_CKn)
(1)
1
Cycle time, DDR_CK and DDR_CKn
5
ns
(1) The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR memory
devices. To determine the maximum clock period, see the respective LPDDR memory data sheet.
1
DDR_CK
DDR_CKn
图 7-32. LPDDR Memory Interface Clock Timing
7.7.2.1.2 LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the
need for a complex timing closure process. For more information regarding the guidelines for using this
LPDDR specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This
application report provides generic guidelines and approach. All the specifications provided in the data
manual take precedence over the generic guidelines and must be adhered to for a reliable LPDDR
interface operation.
7.7.2.1.2.1 LPDDR Interface Schematic
图 7-33 shows the schematic connections for 16-bit interface on the AM335x device using one x16
LPDDR device. The AM335x LPDDR memory interface only supports 16-bit-wide mode of operation. The
AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and one
load connected to the CK and ADDR_CTRL net class signals. For more information related to net classes,
see 节 7.7.2.1.2.8.
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16-Bit LPDDR
Device
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
NC(A)
DDR_DQSn0
DDR_D8
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ15
UDM
UDQS
NC(A)
NC
DDR_ODT
DDR_BA0
DDR_BA1
DDR_BA2
T
BA0
BA1
T
NC
DDR_A0
T
A0
DDR_A15
T
T
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
RAS
T
T
T
T
T
T
WE
CKE
CK
CK
DDR_CKn
DDR_VREF
NC
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
A. Enable internal weak pulldown on these pins. For details, see the EMIF section of the AM335x and AMIC110 Sitara
Processors Technical Reference Manual.
B. For all the termination requirements, see 节 7.7.2.1.2.9.
图 7-33. 16-Bit LPDDR Interface Using One 16-Bit LPDDR Device
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7.7.2.1.2.2 Compatible JEDEC LPDDR Devices
表 7-34 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.
Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.
表 7-34. Compatible JEDEC LPDDR Devices (Per Interface)(1)
NO.
1
PARAMETER
JEDEC LPDDR device speed grade
MIN
LPDDR400
x16
MAX
UNIT
2
JEDEC LPDDR device bit width
JEDEC LPDDR device count
x16
1
Bits
3
Devices
4
JEDEC LPDDR device terminal count
60 Terminals
(1) If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if the
minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x
LPDDR interface.
7.7.2.1.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in 表 7-35.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
表 7-35. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross
splits in the power plane.
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Complete stackup specifications are provided in 表 7-36.
表 7-36. PCB Stackup Specifications(1)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
2
3
4
5
PCB routing and plane layers
Signal routing layers
4
2
1
Full ground layers under LPDDR routing region
Number of ground plane cuts allowed within LPDDR routing region
Full VDDS_DDR power reference layers under LPDDR routing region
0
0
1
Number of layers between LPDDR routing layer and reference ground
plane
6
7
8
9
PCB routing feature size
PCB trace width, w
PCB BGA escape via pad size(2)
4
4
mils
mils
mils
mils
Ω
18
10
50
Zo
20
10 PCB BGA escape via hole size(2)
11 Single-ended impedance, Zo(3)
12 Impedance control(4)(5)
75
Zo-5
Zo+5
Ω
(1) For the LPDDR device BGA pad size, see the LPDDR device manufacturer documentation.
(2) A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to the
AM335x device.
(3) Zo is the nominal singled-ended impedance selected for the PCB.
(4) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(5) Tighter impedance control is required to ensure flight time skew is minimal.
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7.7.2.1.2.4 Placement
图 7-34 shows the required placement for the LPDDR devices. The dimensions for this figure are defined
in 表 7-37. The placement does not restrict the side of the PCB on which the devices are mounted. The
ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing
space. For single-memory LPDDR systems, the second LPDDR device is omitted from the placement.
X
A1
Y
OFFSET
LPDDR
Y
Device
Y
OFFSET
AM335x
A1
Recommended LPDDR
Device Orientation
图 7-34. AM335x Device and LPDDR Device Placement
表 7-37. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1750
1280
650
UNIT
mils
mils
mils
w
X(2)(3)
Y(2)(3)
Y Offset(2)(3)(4)
2
3
4
Clearance from non-LPDDR signal to LPDDR keepout region(5)(6)
4
(1) LPDDR keepout region to encompass entire LPDDR routing area.
(2) For dimension definitions, see 图 7-34.
(3) Measurements from center of the AM335x device to center of LPDDR device.
(4) For single-memory systems, TI recommends that Y offset be as small as possible.
(5) w is defined as the signal trace width.
(6) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.
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7.7.2.1.2.5 LPDDR Keepout Region
The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR
keepout region is defined for this purpose and is shown in 图 7-35. This region should encompass all
LPDDR circuitry and the region size varies with component placement and LPDDR routing. Additional
clearances required for the keepout region are shown in 表 7-37. Non-LPDDR signals must not be routed
on the same signal layer as LPDDR signals within the LPDDR keepout region. Non-LPDDR signals may
be routed in the region provided they are routed on layers separated from LPDDR signal layers by a
ground layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this
region. In addition, the VDDS_DDR power plane should cover the entire keepout region.
A1
LPDDR
Device
A1
图 7-35. LPDDR Keepout Region
7.7.2.1.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the LPDDR and other circuitry. 表 7-
38 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the AM335x LPDDR interface and LPDDR devices. Additional bulk
bypass capacitance may be needed for other circuitry.
表 7-38. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
MIN
1
MAX
UNIT
Devices
μF
2
AM335x VDDS_DDR bulk bypass total capacitance
LPDDR#1 bulk bypass capacitor count
10
1
3
Devices
μF
4
LPDDR#1 bulk bypass total capacitance
LPDDR#2 bulk bypass capacitor count(2)
LPDDR#2 bulk bypass total capacitance(2)
10
1
5
Devices
μF
6
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors.
(2) Only used when two LPDDR devices are used.
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7.7.2.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device
LPDDR power, and the AM335x device LPDDR ground connections. 表 7-39 contains the specification for
the HS bypass capacitors as well as for the power connections on the PCB.
表 7-39. High-Speed Bypass Capacitors
NO.
1
PARAMETER
MIN
MAX
UNIT
HS bypass capacitor package size(1)
0402 10 mils
2
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
250
30
mils
Vias
mils
3
2
1
1
4
Trace length from bypass capacitor contact to connection via
5
Number of connection vias for each AM335x VDDS_DDR and VSS terminal
Trace length from AM335x VDDS_DDR and VSS terminal to connection via
Number of connection vias for each LPDDR device power and ground terminal
Trace length from LPDDR device power and ground terminal to connection via
AM335x VDDS_DDR HS bypass capacitor count(3)
Vias
mils
6
35
7
Vias
mils
8
35
9
10
0.6
8
Devices
μF
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 LPDDR device HS bypass capacitor count(3)(4)
12 LPDDR device HS bypass capacitor total capacitance(4)
Devices
μF
0.4
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per LPDDR device.
7.7.2.1.2.8 Net Classes
表 7-40 lists the clock net classes for the LPDDR interface. 表 7-41 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
表 7-40. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK and DDR_CKn
DDR_DQS0
DQS0
DQS1
DDR_DQS1
表 7-41. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
DDR_BA[1:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE
ADDR_CTRL
CK
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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7.7.2.1.2.9 LPDDR Signal Termination
There is no specific need for adding terminations on the LPDDR interface. However, system designers
may evaluate the need for serial terminators for EMI and overshoot reduction. Placement of serial
terminations for DQS[x] and DQ[x] net class signals should be determined based on PCB analysis.
Placement of serial terminations for ADDR_CTRL net class signals should be close to the AM335x device.
表 7-42 shows the specifications for the serial terminators in such cases.
表 7-42. LPDDR Signal Terminations
NO.
1
PARAMETER
MIN
0
TYP
22
MAX UNIT
CK net class(1)
ADDR_CTRL net class(1)(3)(4)
Zo(2)
Zo(2)
Zo(2)
Ω
Ω
Ω
2
0
22
3
DQS0, DQS1, DQ0, and DQ1 net classes
0
22
(1) Only series termination is permitted.
(2) Zo is the LPDDR PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
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7.7.2.1.3 LPDDR CK and ADDR_CTRL Routing
图 7-36 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal
path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the
majority of the total length of signal path AB and AC.
A1
A
AM335x
A1
图 7-36. CK and ADDR_CTRL Routing and Topology
表 7-43. CK and ADDR_CTRL Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
2w
UNIT
Center-to-center CK spacing
2
CK differential pair skew length mismatch(2)(3)
25
mils
mils
3
CK B-to-CK C skew length mismatch
25
4
Center-to-center CK to other LPDDR trace spacing(4)
CK and ADDR_CTRL nominal trace length(5)
4w
5
CACLM-50
CACLM
CACLM+50
100
mils
mils
mils
6
ADDR_CTRL-to-CK skew length mismatch
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
Center-to-center ADDR_CTRL to other LPDDR trace spacing(4)
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)
ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch(2)
ADDR_CTRL B-to-C skew length mismatch
100
8
4w
3w
9
10
11
100
100
mils
mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AM335x device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in 表 7-36.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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图 7-37 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
DQ[0]
A1
DQ[1]
AM335x
图 7-37. DQS[x] and DQ[x] Routing and Topology
表 7-44. DQS[x] and DQ[x] Routing Specification(1)
NO.
1
PARAMETER
Center-to-center DQS[x] spacing
MIN
TYP
MAX
UNIT
2w
2
Center-to-center DDR_DQS[x] to other LPDDR trace spacing(2)
DQS[x] and DQ[x] nominal trace length(3)
4w
3
DQLM-50
DQLM
DQLM+50
100
mils
mils
mils
4
DQ[x]-to-DQS[x] skew length mismatch(3)
5
DQ[x]-to-DQ[x] skew length mismatch(3)
100
6
Center-to-center DQ[x] to other LPDDR trace spacing(2)(4)
Center-to-center DQ[x] to other DQ[x] trace spacing(2)(5)
4w
3w
7
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1 and DQ1.
(4) Signals from one DQ net class should be considered other LPDDR traces to another DQ net class.
(5) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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7.7.2.2 DDR2 Routing Guidelines
7.7.2.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. 表 7-45 and 图 7-38
show the switching characteristics and timing diagram for the DDR2 memory interface.
表 7-45. Switching Characteristics for DDR2 Memory Interface
NO.
PARAMETER
MIN
MAX
UNIT
tc(DDR_CK)
tc(DDR_CKn)
1
Cycle time, DDR_CK and DDR_CKn
3.75
8(1)
ns
(1) The JEDEC JESD79-2F specification defines the maximum clock period of 8 ns for all standard-speed bin DDR2 memory devices.
Therefore, all standard-speed bin DDR2 memory devices are required to operate at 125 MHz.
1
DDR_CK
DDR_CKn
图 7-38. DDR2 Memory Interface Clock Timing
7.7.2.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application
report provides generic guidelines and approach. All the specifications provided in the data manual take
precedence over the generic guidelines and must be adhered to for a reliable DDR2 interface operation.
7.7.2.2.2.1 DDR2 Interface Schematic
图 7-39 shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR2
device and 图 7-40 shows the schematic connections for 16-bit interface on the AM335x device using two
x8 DDR2 devices. The AM335x DDR2 memory interface only supports 16-bit-wide mode of operation. The
AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two
loads connected to the CK and ADDR_CTRL net class signals. For more information related to net
classes, see 节 7.7.2.2.2.8.
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16-Bit DDR2
Device
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DDR_D8
LDQS
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ15
UDM
UDQS
UDQS
DDR_ODT
T
ODT
DDR_BA0
DDR_BA1
DDR_BA2
T
T
T
BA0
BA1
BA2
DDR_A0
T
A0
DDR_A15
T
T
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
T
T
T
T
T
T
VDDS_DDR(A)
RAS
WE
CKE
CK
1 kΩ 1%
0.1 µF
0.1 µF
CK
DDR_CKn
DDR_VREF
DDR_VREF
VREF
0.1 µF(B)
0.1 µF(B)
1 kΩ 1%
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
Copyright © 2016, Texas Instruments Incorporated
A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.
C. For all the termination requirements, see 节 7.7.2.2.2.9.
图 7-39. 16-Bit DDR2 Interface Using One 16-Bit DDR2 Device
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8-Bit DDR2
Devices
AM335x
DDR_D0
DQ0
DDR_D7
DQ7
DM
DDR_DQM0
DDR_DQS0
DQS
DDR_DQSn0
DQS
DDR_D8
DQ0
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DQ7
DM
DQS
DQS
DDR_ODT
T
ODT
ODT
DDR_BA0
DDR_BA1
DDR_BA2
T
T
T
BA0
BA1
BA2
BA0
BA1
BA2
DDR_A0
T
A0
A0
DDR_A15
T
T
A15
CS
A15
CS
DDR_CSn0
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_CK
CAS
RAS
CAS
RAS
T
T
T
T
T
T
VDDS_DDR(A)
WE
WE
CKE
CKE
CK
CK
CK
CK
1 kΩ 1%
0.1 µF
0.1 µF
DDR_CKn
DDR_VREF
DDR_VREF
1 kΩ 1%
VREF
VREF
0.1 µF(B) 0.1 µF(B)
0.1 µF(B)
DDR_RESETn
DDR_VTP
NC
49.9 Ω
( 1%, 20 mW)
Copyright © 2016, Texas Instruments Incorporated
A. VDDS_DDR is the power supply for the DDR2 memories and the AM335x DDR2 interface.
B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a DDR_VREF pin.
C. For all the termination requirements, see 节 7.7.2.2.2.9.
图 7-40. 16-Bit DDR2 Interface Using Two 8-Bit DDR2 Devices
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7.7.2.2.2.2 Compatible JEDEC DDR2 Devices
表 7-46 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 or x8 DDR2-533 speed grade DDR2 devices.
表 7-46. Compatible JEDEC DDR2 Devices (Per Interface)(1)
NO.
1
PARAMETER
JEDEC DDR2 device speed grade(2)
MIN
MAX
UNIT
DDR2-533
2
JEDEC DDR2 device bit width
JEDEC DDR2 device count
x8
1
x16
2
bits
3
devices
4
JEDEC DDR2 device terminal count(3)
60
84 terminals
(1) If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if the
minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the AM335x DDR2
interface.
(2) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backward compatibility.
(3) 92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically, the 92-
and 84-terminal DDR2 devices are the same.
7.7.2.2.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in 表 7-47.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
表 7-47. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split power plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross
splits in the power plane.
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Complete stackup specifications are provided in 表 7-48.
表 7-48. PCB Stackup Specifications(1)
NO.
1
PARAMETER
MIN
4
TYP
MAX
UNIT
PCB routing and plane layers
Signal routing layers
2
2
3
Full ground layers under DDR2 routing region
Number of ground plane cuts allowed within DDR2 routing region
Full VDDS_DDR power reference layers under DDR2 routing region
Number of layers between DDR2 routing layer and reference ground plane
PCB routing feature size
1
4
0
0
5
1
6
7
4
4
mils
mils
mils
mils
Ω
8
PCB trace width, w
PCB BGA escape via pad size(2)
9
18
10
50
Zo
20
10 PCB BGA escape via hole size(2)
11 Single-ended impedance, Zo(3)
12 Impedance control(4)(5)
75
Zo-5
Zo+5
Ω
(1) For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.
(2) A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to the
AM335x device.
(3) Zo is the nominal singled-ended impedance selected for the PCB.
(4) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(5) Tighter impedance control is required to ensure flight time skew is minimal.
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7.7.2.2.2.4 Placement
图 7-41 shows the required placement for the DDR2 devices. The dimensions for this figure are defined in
表 7-49. The placement does not restrict the side of the PCB on which the devices are mounted. The
ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing
space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement.
X
A1
Y
OFFSET
DDR2
Y
Device
Y
OFFSET
AM335x
A1
Recommended DDR2
Device Orientation
图 7-41. AM335x Device and DDR2 Device Placement
表 7-49. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1750
1280
650
UNIT
mils
mils
mils
w
X(2)(3)
Y(2)(3)
Y Offset(2)(3)(4)
2
3
4
Clearance from non-DDR2 signal to DDR2 keepout region(5)(6)
4
(1) DDR2 keepout region to encompass entire DDR2 routing area.
(2) For dimension definitions, see 图 7-41.
(3) Measurements from center of the AM335x device to center of the DDR2 device.
(4) For single-memory systems, it is recommended that Y offset be as small as possible.
(5) w is defined as the signal trace width.
(6) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
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7.7.2.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in 图 7-42. This region should encompass all
DDR2 circuitry and the region size varies with component placement and DDR2 routing. Additional
clearances required for the keepout region are shown in 表 7-49. Non-DDR2 signals must not be routed
on the same signal layer as DDR2 signals within the DDR2 keepout region. Non-DDR2 signals may be
routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground
layer. No breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In
addition, the VDDS_DDR power plane should cover the entire keepout region.
A1
DDR2
Device
A1
图 7-42. DDR2 Keepout Region
7.7.2.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. 表 7-
50 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the AM335x DDR2 interface and DDR2 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
表 7-50. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
AM335x VDDS_DDR bulk bypass total capacitance
DDR2 number 1 bulk bypass capacitor count
DDR2 number 1 bulk bypass total capacitance
DDR2 number 2 bulk bypass capacitor count(2)
DDR2 number 2 bulk bypass total capacitance(2)
MIN
1
MAX
UNIT
devices
μF
2
10
1
3
devices
μF
4
10
1
5
devices
μF
6
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors.
(2) Only used when two DDR2 devices are used.
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7.7.2.2.2.7 High-Speed (HS) Bypass Capacitors
HS bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to
minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device DDR2 power,
and the AM335x device DDR2 ground connections. 表 7-51 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.
表 7-51. HS Bypass Capacitors
NO.
1
PARAMETER
MIN
MAX
UNIT
HS bypass capacitor package size(1)
0402 10 mils
2
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
250
30
mils
vias
3
2
1
1
4
Trace length from bypass capacitor contact to connection via
mils
5
Number of connection vias for each AM335x VDDS_DDR and VSS terminal
Trace length from AM335x VDDS_DDR and VSS terminal to connection via
Number of connection vias for each DDR2 device power and ground terminal
Trace length from DDR2 device power and ground terminal to connection via
AM335x VDDS_DDR HS bypass capacitor count(3)
vias
6
35
mils
7
vias
8
35
mils
9
10
0.6
8
devices
μF
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 DDR2 device HS bypass capacitor count(3)(4)
12 DDR2 device HS bypass capacitor total capacitance(4)
devices
μF
0.4
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per DDR2 device.
7.7.2.2.2.8 Net Classes
表 7-52 lists the clock net classes for the DDR2 interface. 表 7-53 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
表 7-52. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK and DDR_CKn
DQS0
DQS1
DDR_DQS0 and DDR_DQSn0
DDR_DQS1 and DDR_DQSn1
表 7-53. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
AM335x PIN NAMES
NET CLASS
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
ADDR_CTRL
CK
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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7.7.2.2.2.9 DDR2 Signal Termination
Signal terminations are required on the CK and ADDR_CTRL net class signals. Serial terminations should
be used on the CK and ADDR_CTRL lines and is the preferred termination scheme. On-device
terminations (ODTs) are required on the DQS[x] and DQ[x] net class signals. They should be enabled to
ensure signal integrity. 表 7-54 shows the specifications for the series terminators. Placement of serial
terminations for ADDR_CTRL net class signals should be close to the AM335x device.
表 7-54. DDR2 Signal Terminations
NO.
1
PARAMETER
MIN
0
TYP
MAX
10
UNIT
Ω
CK net class(1)
2
ADDR_CTRL net class(1)(2)(3)
0
22
Zo(4)
Ω
3
DQS0, DQS1, DQ0, and DQ1 net classes(5)
N/A
N/A
Ω
(1) Only series termination is permitted.
(2) Series termination values larger than typical only recommended to address EMI issues.
(3) Series termination values should be uniform across net class.
(4) Zo is the DDR2 PCB trace characteristic impedance.
(5) No external termination resistors are allowed and ODT must be used for these net classes.
If the DDR2 interface is operated at a lower frequency (<200-MHz clock rate), on-device terminations are
not specifically required for the DQS[x] and DQ[x] net class signals and serial terminations for the CK and
ADDR_CTRL net class signals are not mandatory. System designers may evaluate the need for serial
terminators for EMI and overshoot reduction. Placement of serial terminations for DQS[x] and DQ[x] net
class signals should be determined based on PCB analysis. Placement of serial terminations for
ADDR_CTRL net class signals should be close to the AM335x device. 表 7-55 shows the specifications
for the serial terminators in such cases.
表 7-55. Lower-Frequency DDR2 Signal Terminations
NO. PARAMETER
MIN
0
TYP
22
MAX
Zo(2)
Zo(2)
Zo(2)
UNIT
Ω
1
2
3
CK net class(1)
ADDR_CTRL net class(1)(3)(4)
0
22
Ω
DQS0, DQS1, DQ0, and DQ1 net classes
0
22
Ω
(1) Only series termination is permitted.
(2) Zo is the DDR2 PCB trace characteristic impedance.
(3) Series termination values larger than typical only recommended to address EMI issues.
(4) Series termination values should be uniform across net class.
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7.7.2.2.2.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM335x
device. DDR_VREF is intended to be half the DDR2 power supply voltage and should be created using a
resistive divider as shown in 图 7-39 and 图 7-40. TI does not recommend other methods of creating
DDR_VREF. 图 7-43 shows the layout guidelines for DDR_VREF.
DDR_VREF Bypass Capacitor
DDR2 Device
A1
DDR_VREF Nominal Minimum
Trace Width is 20 Mils
AM335x
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accommodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of DDR_VREF is maximized.
图 7-43. DDR_VREF Routing and Topology
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7.7.2.2.3 DDR2 CK and ADDR_CTRL Routing
图 7-44 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of signal
path AB and AC should be minimized with emphasis to minimize lengths C and D such that length A is the
majority of the total length of signal path AB and AC.
A1
T
A
AM335x
A1
图 7-44. CK and ADDR_CTRL Routing and Topology
表 7-56. CK and ADDR_CTRL Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
2w
UNIT
Center-to-center CK spacing
2
CK differential pair skew length mismatch(2)(3)
25
mils
mils
3
CK B-to-CK C skew length mismatch
25
4
Center-to-center CK to other DDR2 trace spacing(4)
CK and ADDR_CTRL nominal trace length(5)
4w
5
CACLM-50
CACLM
CACLM+50
100
mils
mils
mils
6
ADDR_CTRL-to-CK skew length mismatch
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
Center-to-center ADDR_CTRL to other DDR2 trace spacing(4)
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)
ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch(2)
ADDR_CTRL B-to-C skew length mismatch
100
8
4w
3w
9
10
11
100
100
mils
mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AM335x device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in 表 7-48.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
图 7-45 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
DQ[0]
A1
DQ[1]
AM335x
图 7-45. DQS[x] and DQ[x] Routing and Topology
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表 7-57. DQS[x] and DQ[x] Routing Specification(1)
NO.
PARAMETER
MIN
TYP
MAX
2w
UNIT
1
2
3
4
5
6
7
8
Center-to-center DQS[x] spacing
DQS[x] differential pair skew length mismatch(2)
Center-to-center DDR_DQS[x] to other DDR2 trace spacing(3)
DQS[x] and DQ[x] nominal trace length(4)
DQ[x]-to-DQS[x] skew length mismatch(4)
DQ[x]-to-DQ[x] skew length mismatch(4)
25
mils
4w
DQLM-50
DQLM
DQLM+50
100
mils
mils
mils
100
Center-to-center DQ[x] to other DDR2 trace spacing(3)(5)
Center-to-center DQ[x] to other DQ[x] trace spacing(3)(6)
4w
3w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in 表 7-48.
(3) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1 and DQ1.
(5) Signals from one DQ net class should be considered other DDR2 traces to another DQ net class.
(6) DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
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7.7.2.3 DDR3 and DDR3L Routing Guidelines
注
All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise
noted.
7.7.2.3.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory interface are shown in 表 7-58 and 图
7-46.
表 7-58. Switching Characteristics for DDR3 Memory Interface
NO.
PARAMETER
MIN
MAX
UNIT
tc(DDR_CK)
tc(DDR_CKn)
1
Cycle time, DDR_CK and DDR_CKn
2.5
3.3(1)
ns
(1) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory
devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.
1
DDR_CK
DDR_CKn
图 7-46. DDR3 Memory Interface Clock Timing
7.7.2.3.1.1 DDR3 versus DDR2
This specification only covers AM335x PCB designs that use DDR3 memory. Designs using DDR2
memory should use the DDR2 routing guidleines described in 节 7.7.2.2. While similar, the two memory
systems have different requirements. It is currently not possible to design one PCB that meets the
requirements of both DDR2 and DDR3.
7.7.2.3.2 DDR3 Device Combinations
Because there are several possible combinations of device counts and single-side or dual-side mounting,
表 7-59 summarizes the supported device configurations.
表 7-59. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
16
8
N
Y(1)
16
16
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
7.7.2.3.3 DDR3 Interface
This section provides the timing specification for the DDR3 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR3 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR3
specification, see Understanding TI's PCB Routing Rule-Based DDR Timing Specification. This application
report provides generic guidelines and approach. All the specifications provided in the data manual take
precedence over the generic guidelines and must be adhered to for a reliable DDR3 interface operation.
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7.7.2.3.3.1 DDR3 Interface Schematic
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. 图 7-47
shows the schematic connections for 16-bit interface on the AM335x device using one x16 DDR3 device
and 图 7-49 shows the schematic connections for 16-bit interface on the AM335x device using two x8
DDR3 devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The
AM335x device can only source one load connected to the DQS[x] and DQ[x] net class signals and two
loads connected to the CK and ADDR_CTRL net class signals. For more information related to net
classes, see 节 7.7.2.3.3.8.
16-Bit DDR3
Interface
16-Bit DDR3
Device
DDR_D15
DQU7
8
DDR_D8
DQU0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSU#
DDR_D7
DQL7
8
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSL#
0.1 µF
Zo
Zo
DDR_CK
CK
VDDS_DDR
DDR_CKn
CK#
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CS#
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
A0
15
DDR_A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CAS#
RAS#
WE#
DDR_CKE
CKE
DDR_RESETn
DDR_VREF
RESET#
ZQ
ZQ
VREFDQ
VREFCA
DDR_VREF
0.1 µF
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR3 memory device data sheet.
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图 7-47. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device with VTT Termination
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16-Bit DDR3
Interface
16-Bit DDR3
Device
DDR_D15
DQU7
8
DDR_D8
DQU0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSU#
DDR_D7
DQL7
8
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSL#
DDR_CK
CK
DDR_CKn
CK#
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CS#
BA0
BA1
BA2
DDR_A0
A0
15
DDR_A15
A15
VDDS_DDR(A)
DDR_CASn
DDR_RASn
DDR_WEn
CAS#
RAS#
WE#
DDR_CKE
CKE
DDR_RESETn
RESET#
ZQ
1 kΩ 1%
0.1 µF
0.1 µF
ZQ
VREFDQ
VREFCA
DDR_VREF
DDR_VREF
1 kΩ 1%
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
ZQ
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
A. VDDS_DDR is the power supply for the DDR3 memories and the AM335x DDR3 interface.
图 7-48. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device without VTT Termination
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16-Bit DDR3
Interface
8-Bit DDR3
Devices
DDR_D15
DQ7
8
DDR_D8
DQ0
DDR_DQM1
DM/TDQS
TDQS#
DQS
NC
DDR_DQS1
DDR_DQSn1
DQS#
DDR_D7
DQ7
DQ0
8
DDR_D0
DDR_DQM0
DM/TDQS
TDQS#
DQS
NC
DDR_DQS0
DDR_DQSn0
DQS#
0.1 µF
Zo
Zo
DDR_CK
CK
CK
VDDS_DDR
DDR_CKn
CK#
CK#
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
ODT
CS#
BA0
BA1
BA2
CS#
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
A0
A0
15
DDR_A15
A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CAS#
RAS#
WE#
CAS#
RAS#
WE#
DDR_CKE
CKE
CKE
DDR_RESETn
DDR_VREF
RESET#
ZQ
RESET#
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
DDR_VREF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
图 7-49. 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices
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7.7.2.3.3.2 Compatible JEDEC DDR3 Devices
表 7-60 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
表 7-60. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tC(DDR_CK) and tC(DDR_CKn)
= 3.3 ns
DDR3-800
1
JEDEC DDR3 device speed grade
tC(DDR_CK) and tC(DDR_CKn)
= 2.5 ns
DDR3-1600
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(1)
x8
1
x16
2
bits
devices
(1) For valid DDR3 device configurations and device counts, see 节 7.7.2.3.3.1, 图 7-47, and 图 7-49.
7.7.2.3.3.3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in 表 7-61.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
表 7-61. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross
splits in the power plane.
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表 7-62. PCB Stackup Specifications(1)
NO.
PARAMETER
MIN
4
TYP
MAX
UNIT
1
2
3
4
5
6
7
8
9
PCB routing and plane layers
Signal routing layers
2
Full ground reference layers under DDR3 routing region(2)
Full VDDS_DDR power reference layers under the DDR3 routing region(2)
Number of reference plane cuts allowed within DDR3 routing region(3)
Number of layers between DDR3 routing layer and reference plane(4)
PCB routing feature size
1
1
0
0
4
4
mils
mils
mils
mils
Ω
PCB trace width, w
PCB BGA escape via pad size(5)
18
10
50
Zo
20
10 PCB BGA escape via hole size
11 Single-ended impedance, Zo(6)
12 Impedance control(7)(8)
75
Zo-5
Zo+5
Ω
(1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
(2) Ground reference layers are preferred over power reference layers. Be sure to include bypass capacitors to accommodate reference
layer return current as the trace routes switch routing layers.
(3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(6) Zo is the nominal singled-ended impedance selected for the PCB.
(7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(8) Tighter impedance control is required to ensure flight time skew is minimal.
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7.7.2.3.3.4 Placement
图 7-50 shows the required placement for the AM335x device as well as the DDR3 devices. The
dimensions for this figure are defined in 表 7-63. The placement does not restrict the side of the PCB on
which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space.
X1
X2
DDR3
Interface
Y
图 7-50. Placement Specifications
表 7-63. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1000
600
UNIT
mils
mils
mils
w
X1(2)(3)(4)
X2(2)(3)
Y Offset(2)(3)(4)
2
3
1500
4
Clearance from non-DDR3 signal to DDR3 keepout region(5)(6)
4
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) For dimension definitions, see 图 7-50.
(3) Measurements from center of the AM335x device to center of the DDR3 device.
(4) Minimizing X1 and Y improves timing margins.
(5) w is defined as the signal trace width.
(6) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
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7.7.2.3.3.5 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in 图 7-51. This region should encompass all DDR3
circuitry and the region size varies with component placement and DDR3 routing. Additional clearances
required for the keepout region are shown in 表 7-63. Non-DDR3 signals must not be routed on the same
signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in the
region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No
breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition,
the VDDS_DDR power plane should cover the entire keepout region.
DDR3 Interface
DDR3 Keepout Region
Encompasses Entire
DDR3 Routing Area
图 7-51. DDR3 Keepout Region
7.7.2.3.3.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. 表 7-
64 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the AM335x DDR3 interface and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
表 7-64. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
AM335x VDDS_DDR bulk bypass capacitor count
AM335x VDDS_DDR bulk bypass total capacitance
DDR3 number 1 bulk bypass capacitor count
DDR3 number 1 bulk bypass total capacitance
DDR3 number 2 bulk bypass capacitor count(2)
DDR3 number 2 bulk bypass total capacitance(2)
MIN
2
MAX
UNIT
devices
μF
2
20
2
3
devices
μF
4
20
2
5
devices
μF
6
20
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
(2) Only used when two DDR3 devices are used.
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7.7.2.3.3.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, the AM335x device
DDR3 power, and the AM335x device DDR3 ground connections. 表 7-65 contains the specification for
the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good
to:
•
•
•
•
Fit as many HS bypass capacitors as possible.
Minimize the distance from the bypass capacitor to the power terminals being bypassed.
Use the smallest physical sized capacitors possible with the highest capacitance readily available.
Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
•
Minimize via sharing. Note the limits on via sharing shown in 表 7-65.
表 7-65. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
HS bypass capacitor package size(1)
0201
0402 10 mils
Distance, HS bypass capacitor to AM335x VDDS_DDR and VSS terminal
being bypassed(2)(3)(4)
2
400
mils
3
4
AM335x VDDS_DDR HS bypass capacitor count
20
1
devices
AM335x VDDS_DDR HS bypass capacitor total capacitance
μF
Trace length from AM335x VDDS_DDR and VSS terminal to connection
via(2)
5
35
70
mils
6
7
8
9
Distance, HS bypass capacitor to DDR3 device being bypassed(5)
DDR3 device HS bypass capacitor count(6)
DDR3 device HS bypass capacitor total capacitance(6)
Number of connection vias for each HS bypass capacitor(7)(8)
150
mils
devices
μF
12
0.85
2
vias
10 Trace length from bypass capacitor connect to connection via(2)(8)
35
35
100
60
mils
Number of connection vias for each DDR3 device power and ground
11
1
vias
mils
terminal(9)
Trace length from DDR3 device power and ground terminal to connection
12
via(2)(7)
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer and shorter is better.
(3) Measured from the nearest AM335x VDDS_DDR and ground terminal to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the AM335x device, between the cluster of VDDS_DDR and ground terminals,
between the DDR3 interfaces on the package.
(5) Measured from the DDR3 device power and ground terminal to the center of the capacitor package.
(6) Per DDR3 device.
(7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(8) An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for
the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
(9) Up to two pairs of DDR3 power and ground terminals may share a via.
7.7.2.3.3.7.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
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7.7.2.3.3.8 Net Classes
表 7-66 lists the clock net classes for the DDR3 interface. 表 7-67 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
表 7-66. Clock Net Class Definitions
CLOCK NET CLASS AM335x PIN NAMES
CK
DDR_CK and DDR_CKn
DQS0
DQS1
DDR_DQS0 and DDR_DQSn0
DDR_DQS1 and DDR_DQSn1
表 7-67. Signal Net Class Definitions
ASSOCIATED CLOCK NET
SIGNAL NET CLASS
AM335x PIN NAMES
CLASS
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE, DDR_ODT
ADDR_CTRL
CK
DQ0
DQ1
DQS0
DQS1
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
7.7.2.3.3.9 DDR3 Signal Termination
Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations
(ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are
covered in the routing rules in the following sections.
图 7-48 provides an example DDR3 schematic with a single 16-bit DDR3 memory device that does not
have VTT termination on the address and control signals. A typical DDR3 point-to-point topology may
provide acceptable signal integrity without VTT termination. System performance should be verified by
performing signal integrity analysis using specific PCB design details before implementing this topology.
7.7.2.3.3.10 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the AM335x
device. DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with
a voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide
trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to
accommodate routing congestion.
7.7.2.3.3.11 VTT
Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike
DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the
ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should
be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.
7.7.2.3.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in 表 7-68.
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7.7.2.3.4.1 Two DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank. These two devices may be mounted on a single side of the PCB, or may be mirrored in a
pair to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
7.7.2.3.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
图 7-52 shows the topology of the CK net classes and 图 7-53 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR3 Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
AM335x
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
图 7-52. CK Topology for Two DDR3 Devices
DDR3 Address and Control Input Buffers
Address and Control
Terminator
Rtt
AM335x
Address and Control
Output Buffer
A1
A2
A3
AT
Vtt
图 7-53. ADDR_CTRL Topology for Two DDR3 Devices
7.7.2.3.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
图 7-54 shows the CK routing for two DDR3 devices placed on the same side of the PCB. 图 7-55 shows
the corresponding ADDR_CTRL routing.
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VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
图 7-54. CK Routing for Two Single-Sided DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
图 7-55. ADDR_CTRL Routing for Two Single-Sided DDR3 Devices
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To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. 图 7-56 and 图 7-57 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
图 7-56. CK Routing for Two Mirrored DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
图 7-57. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
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7.7.2.3.4.2 One DDR3 Device
One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as
one 16-bit bank.
7.7.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
图 7-58 shows the topology of the CK net classes and 图 7-59 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR3 Differential CK Input Buffer
–
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
AT
AT
Cac
AM335x
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
图 7-58. CK Topology for One DDR3 Device
DDR3 Address and Control Input Buffers
Address and Control
Terminator
Rtt
AM335x
Address and Control
Output Buffer
A1
A2
AT
Vtt
图 7-59. ADDR_CTRL Topology for One DDR3 Device
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7.7.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
图 7-60 shows the CK routing for one DDR3 device. 图 7-61 shows the corresponding ADDR_CTRL
routing.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
图 7-60. CK Routing for One DDR3 Device
Rtt
A2
AT
Vtt
=
图 7-61. ADDR_CTRL Routing for One DDR3 Device
7.7.2.3.5 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
7.7.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point single-ended. 图 7-62 and 图
7-63 show these topologies.
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Am335x
DQS[x]
DDR3
DQS[x]+
DQS[x]
DQS[x]-
I/O Buffer
I/O Buffer
Routed Differentially
x = 0, 1
图 7-62. DQS[x] Topology
AM335x
DQ[x]
DDR3
DQ[x]
DQ[x]
I/O Buffer
I/O Buffer
x = 0, 1
图 7-63. DQ[x] Topology
7.7.2.3.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
图 7-64 and 图 7-65 show the DQS[x] and DQ[x] routing.
DQS[x]
DQS[x]+
DQS[x]-
Routed Differentially
x = 0, 1
图 7-64. DQS[x] Routing With Any Number of Allowed DDR3 Devices
DQ[x]
x = 0, 1
图 7-65. DQ[x] Routing With Any Number of Allowed DDR3 Devices
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7.7.2.3.6 Routing Specification
7.7.2.3.6.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the AM335x device and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-66 shows this distance for two
loads. The specifications on the lengths of the transmission lines for the address bus are determined from
this distance. CACLM is determined similarly for other address bus configurations; that is, it is based on
the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing, these
specifications are contained in 表 7-68.
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
Vtt
=
A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the
DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net
class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.
The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Nonincluded lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-66. CACLM for Two Address Loads on One Side of PCB
表 7-68. CK and ADDR_CTRL Routing Specification(1)(2)(3)
NO.
1
PARAMETER
MIN
TYP
MAX
2500
25
UNIT
mils
mils
mils
mils
mils
mils
A1 + A2 length
A1 + A2 skew
A3 length
A3 skew(4)
A3 skew(5)
AS length
2
3
660
25
4
5
125
100
6
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表 7-68. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued)
NO.
PARAMETER
MIN
TYP
MAX
25
UNIT
mils
mils
mils
mils
mils
mils
mils
7
8
9
AS skew
AS+ and AS– length
AS+ and AS– skew
70
5
10 AT length(6)
11 AT skew(7)
12 AT skew(8)
500
100
5
13 CK and ADDR_CTRL nominal trace length(9)
14 Center-to-center CK to other DDR3 trace spacing(10)
15 Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11)
16 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10)
17 CK center-to-center spacing(12)
CACLM-50
CACLM
CACLM+50
4w
4w
3w
18 CK spacing to other net(10)
19 Rcp(13)
20 Rtt(13)(14)
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
Ω
Ω
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump
between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(5) Nonmirrored configuration (all DDR3 memories on same side of PCB).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see 节 7.7.2.3.6.1 and 图
7-66.
(10) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
(11) Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
(12) CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended
impedance defined in 表 7-62.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification
Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ
Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs,
DQLM0-DQLM1.
注
Matching the lengths across all bytes is not required, nor is it recommended. Length
matching is only required within each byte.
Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-67 shows this distance for a
two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in 表 7-69.
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DQLMX0
DQ[0:7], DM0, DQS0
DQ0
DQ1
DQ[8:15], DM1, DQS1
DQLMX1
DQLMY0
DQLMY1
1
0
DQ0 - DQ1 represent data bytes 0 - 1.
There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte;
therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
图 7-67. DQLM for Any Number of Allowed DDR3 Devices
表 7-69. DQS[x] and DQ[x] Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
DQLM0
DQLM1
25
UNIT
mils
mils
mils
mils
mils
DQ0 nominal length(3)(4)
DQ1 nominal length(3)(5)
DQ[x] skew(6)
2
3
4
DQS[x] skew
DQS[x]-to-DQ[x] skew(6)(7)
5
5
25
6
Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)
Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)
DQS[x] center-to-center spacing(11)
4w
3w
7
8
9
DQS[x] center-to-center spacing to other net(8)
4w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte. For definition, see 节 7.7.2.3.6.2 and 图 7-67.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) Length matching is only done within a byte. Length matching across bytes is not required.
(7) Each DQS clock net class is length matched to its associated DQ signal net class.
(8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
(9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
(10) This applies to spacing within same DQ[x] signal net class.
(11) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-
ended impedance defined in 表 7-62.
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7.8 I2C
For more information, see the Inter-Integrated Circuit (I2C) section of the AM335x and AMIC110 Sitara
Processors Technical Reference Manual.
7.8.1 I2C Electrical Data and Timing
表 7-70. I2C Timing Conditions – Slave Mode
STANDARD MODE
MIN MAX
FAST MODE
MIN
PARAMETER
UNIT
MAX
Output Condition
Cb
Capacitive load for each bus line
400
400
pF
表 7-71. Timing Requirements for I2C Input Timings
(see 图 7-68)
STANDARD MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated
START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
3
th(SDAL-SCLL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(1)
0(2)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(2)
3.45(3)
0.9(3) µs
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
µs
9
tr(SDA)
Rise time, SDA
1000
1000
300
300 ns
300 ns
300 ns
300 ns
µs
10 tr(SCL)
Rise time, SCL
11 tf(SDA)
Fall time, SDA
12 tf(SCL)
Fall time, SCL
300
13 tsu(SCLH-SDAH)
Setup time, high before SDA high (for STOP condition)
4
0
0.6
0
14 tw(SP)
Pulse duration, spike (must be suppressed)
50
50 ns
(1) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the
standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
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9
11
I2C[x]_SDA
6
8
14
4
13
5
10
I2C[x]_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
图 7-68. I2C Receive Timing
表 7-72. Switching Characteristics for I2C Output Timings
(see 图 7-69)
NO.
STANDARD MODE
PARAMETER
FAST MODE
UNIT
MIN
MAX
MIN
MAX
15 tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated
START condition)
16 tsu(SCLH-SDAL)
17 th(SDAL-SCLL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
µs
18 tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
19 tw(SCLH)
Pulse duration, SCL high
20 tsu(SDAV-SCLH)
21 th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45
0.9 µs
Pulse duration, SDA high between STOP and START
conditions
22 tw(SDAH)
4.7
4
1.3
0.6
µs
µs
27 tsu(SCLH-SDAH)
Setup time, high before SDA high (for STOP condition)
I2C[x]_SDA
I2C[x]_SCL
20
22
18
27
19
15
17
21
16
17
Stop
Start
Repeated
Start
Stop
图 7-69. I2C Transmit Timing
7.9 JTAG Electrical Data and Timing
表 7-73. JTAG Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
190
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表 7-73. JTAG Timing Conditions (continued)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tR
tF
Input signal rise time
Input signal fall time
1
1
5
5
ns
Output Conditions
CLOAD
Output load capacitance
5
15
pF
表 7-74. Timing Requirements for JTAG
(see 图 7-70)
OPP100
OPP50
NO.
UNIT
MIN
81.5
32.6
32.6
3
MAX
MIN
104.5
41.8
41.8
3
MAX
1
tc(TCK)
1a tw(TCKH)
1b tw(TCKL)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
tsu(TDI-TCKH)
3
4
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
3
8.05
8.05
8.05
8.05
表 7-75. Switching Characteristics for JTAG
(see 图 7-70)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
3
27.6
4
36.8
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
图 7-70. JTAG Timing
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7.10 LCD Controller (LCDC)
The LCDC consists of two independent controllers, the raster controller and the LCD interface display
driver (LIDD) controller. Each controller operates independently from the other and only one of them is
active at any given time.
•
The raster controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale and
serializer. Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous
memory block in the system. A built-in DMA engine supplies the graphics data to the raster engine
which, in turn, outputs to the external LCD device.
•
The LIDD controller supports the asynchronous LCD interface. It provides full-timing programmability of
control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 2048 × 2048 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate.
表 7-76. LCD Controller Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
TR
TF
Input signal fall time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
LIDD mode
5
3
60
30
CLOAD Output load capacitance
pF
Raster mode
7.10.1 LCD Interface Display Driver (LIDD Mode)
表 7-77. Timing Requirements for LCD LIDD Mode
(see 图 7-72 through 图 7-80)
OPP100
MIN
NO.
UNIT
MAX
Setup time, LCD_DATA[15:0] valid before
LCD_MEMORY_CLK high
16
tsu(LCD_DATA-LCD_MEMORY_CLK)
th(LCD_MEMORY_CLK-LCD_DATA)
tt(LCD_DATA)
18
ns
Hold time, LCD_DATA[15:0] valid after
LCD_MEMORY_CLK high
17
18
0
1
ns
ns
Transition time, LCD_DATA[15:0]
3
表 7-78. Switching Characteristics for LCD LIDD Mode
(see 图 7-72 through 图 7-80)
OPP100
MIN
NO.
PARAMETER
UNIT
MAX
1
2
3
tc(LCD_MEMORY_CLK)
tw(LCD_MEMORY_CLKH)
tw(LCD_MEMORY_CLKL)
Cycle time, LCD_MEMORY_CLK
23.7
ns
ns
ns
Pulse duration, LCD_MEMORY_CLK high
Pulse duration, LCD_MEMORY_CLK low
Delay time, LCD_MEMORY_CLK high to
0.45tc
0.55tc
0.55tc
0.45tc
4
5
6
8
td(LCD_MEMORY_CLK-LCD_DATAV)
td(LCD_MEMORY_CLK-LCD_DATAI)
td(LCD_MEMORY_CLK-LCD_AC_BIAS_EN)
td(LCD_MEMORY_CLK-LCD_VSYNC)
7
ns
ns
ns
ns
LCD_DATA[15:0] valid (write)
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] invalid (write)
0
0
0
Delay time, LCD_MEMORY_CLK high to
LCD_AC_BIAS_EN
6.8
7
Delay time, LCD_MEMORY_CLK high to
LCD_VSYNC
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表 7-78. Switching Characteristics for LCD LIDD Mode (continued)
(see 图 7-72 through 图 7-80)
OPP100
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, LCD_MEMORY_CLK high to
LCD_HSYNC
10
12
14
td(LCD_MEMORY_CLK-LCD_HYSNC)
td(LCD_MEMORY_CLK-LCD_PCLK)
td(LCD_MEMORY_CLK-LCD_DATAZ)
0
7
7
7
ns
ns
ns
Delay time, LCD_MEMORY_CLK high to LCD_PCLK
0
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] high-Z
0
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] driven
15
td(LCD_MEMORY_CLK-LCD_DATA)
0
7
ns
CS_DELAY
(0 to 3)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
4
8
5
8
LCD_DATA[7:0]
Write Instruction
LCD_VSYNC
(RS)
10
10
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
图 7-71. Command Write in Hitachi Mode
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CS_DELAY
(0 to 3)
W_SU
(0 to 31)
W_STROBE
(1 to 63)
W_HOLD
(1 to 15)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
4
5
LCD_DATA[15:0]
Write Data
LCD_VSYNC
(RS)
10
10
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
图 7-72. Data Write in Hitachi Mode
R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
17
16
15
8
14
8
LCD_DATA[15:0]
Read Command
18
LCD_VSYNC
(RS)
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
图 7-73. Command Read in Hitachi Mode
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R_SU
(0 to 31)
R_HOLD
(1 to 15)
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
LCD_MEMORY_CLK
6
6
LCD_MEMORY_CLK
(E1)
17
16
15
14
LCD_DATA[15:0]
Read Data
18
LCD_VSYNC
(RS)
LCD_HSYNC
(R/W)
6
6
LCD_AC_BIAS_EN
(E0)
A. Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals.
The second LCD_MEMORY_CLK waveform is shown as E1 because the LCD_MEMORY_CLK signal is used to
implement the E1 function in Hitachi mode.
图 7-74. Data Read in Hitachi Mode
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_SU
(0−31)
1
W_STROBE
(1−63)
W_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
4
5
4
5
LCD_DATA[15:0]
Write Address
Write Data
6
8
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
9
10
10
10
10
LCD_HSYNC
(DIR)
12
12
12
12
LCD_PCLK
(EN)
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-75. Micro-Interface Graphic Display Motorola Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
R_HOLD
(1−15)
1
W_STROBE
(1−63)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
16
18
4
5
14
15
17
LCD_DATA[15:0]
Write Address
Read
Data
6
8
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
9
10
10
LCD_HSYNC
(DIR)
12
12
12
12
LCD_PCLK
(EN)
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-76. Micro-Interface Graphic Display Motorola Read
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R_SU
(0−31)
1
R_HOLD
(1−15)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
16
14
15
17
LCD_DATA[15:0]
Read
Status
18
6
8
6
8
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
LCD_HSYNC
(DIR)
12
12
LCD_PCLK
(EN)
A. Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured
in asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-77. Micro-Interface Graphic Display Motorola Status
198
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W_HOLD
(1−15)
W_HOLD
(1−15)
W_SU
(0−31)
W_SU
(0−31)
1
W_STROBE
W_STROBE
2
(1−63)
Write Address
10
(1−63)
Write Data
10
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
4
5
4
5
LCD_DATA[15:0]
6
8
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
10
10
LCD_HSYNC
(WS)
LCD_PCLK
(RS)
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-78. Micro-Interface Graphic Display Intel Write
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W_HOLD
(1−15)
R_SU
(0−31)
W_SU
(0−31)
R_HOLD
(1−15)
1
W_STROBE
(1−63)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
6
6
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
16
18
4
5
14
15
17
LCD_DATA[15:0]
Write Address
Read
Data
6
8
6
8
6
6
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
10
10
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-79. Micro-Interface Graphic Display Intel Read
200
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R_SU
(0−31)
1
R_HOLD
(1−15)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
16
14
15
17
LCD_DATA[15:0]
Read
Status
18
6
8
6
8
LCD_AC_BIAS_EN
(CS0)
LCD_VSYNC
(ALE)
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
图 7-80. Micro-Interface Graphic Display Intel Status
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7.10.2 LCD Raster Mode
表 7-79. Switching Characteristics for LCD Raster Mode
(see 图 7-82 through 图 7-85)
OPP50
MIN
OPP100
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
3
tc(LCD_PCLK)
tw(LCD_PCLKH)
tw(LCD_PCLKL)
Cycle time, pixel clock
15.8
0.45tc
0.45tc
7.9
ns
Pulse duration, pixel clock high
Pulse duration, pixel clock low
0.55tc
0.55tc
0.45tc
0.55tc
0.55tc
ns
ns
0.45tc
Delay time, LCD_PCLK to LCD_DATA[23:0] valid
(write)
4
5
td(LCD_PCLK-LCD_DATAV)
td(LCD_PCLK-LCD_DATAI)
3.0
1.9
ns
ns
Delay time, LCD_PCLK to LCD_DATA[23:0] invalid
(write)
–3.0
–1.7
6
8
td(LCD_PCLK-LCD_AC_BIAS_EN) Delay time, LCD_PCLK to LCD_AC_BIAS_EN
–3.0
–3.0
–3.0
3.0
3.0
3.0
–1.7
–1.7
–1.7
1.9
1.9
1.9
ns
ns
ns
td(LCD_PCLK-LCD_VSYNC)
Delay time, LCD_PCLK to LCD_VSYNC
Delay time, LCD_PCLK to LCD_HSYNC
10 td(LCD_PCLK-LCD_HSYNC)
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
•
•
•
•
Vertical front porch (VFP)
Vertical sync pulse width (VSW)
Vertical back porch (VBP)
Lines per panel (LPP_B10 + LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
•
•
•
•
Horizontal front porch (HFP)
Horizontal sync pulse width (HSW)
Horizontal back porch (HBP)
Pixels per panel (PPLMSB + PPLLSB)
LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
•
AC bias frequency (ACB)
The display format produced in raster mode is shown in 图 7-81. An entire frame is delivered one line at a
time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered
starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the
activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O
signal LCD_HSYNC.
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Data Pixels (From 1 to P)
P−2,
1
P−1,
1
1, 1
1, 2
1, 3
2, 1
2, 2
3, 1
P, 1
P, 2
P, 3
P−1,
2
LCD
1,
L−2
P,
L−2
1,
L−1
2,
L−1
P−1,
L−1
P,
L−1
P−2,
L
P−1,
L
1, L
2, L
3, L
P, L
图 7-81. LCD Raster-Mode Display Format
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Frame Time
LPP_B10 + LPP
(1 to 2048)
VSW
VBP
VFP
VSW
(1 to 64)
(0 to 255)
(1 to 64)
(0 to 255)
Line
Time
LCD_HSYNC
LCD_VSYNC
LCD_DATA[23:0]
1, 1 1, 2
P, 1 P, 2
1, L-1 1, L
P, L-1 P, L
LCD_AC_BIAS_EN
(ACTVID)
10
10
LCD_HSYNC
LCD_PCLK
LCD_DATA[23:0]
2, 1
1, 2
P, 2
P, 1
1, 1
2, 2
LCD_AC_BIAS_EN
(ACTVID)
PPLMSB + PPLLSB
16 × (1 to 2048)
Line 2
PPLMSB + PPLLSB
16 × (1 to 2048)
Line 1
HFP
(1 to 256)
HSW
HBP
(1 to 256)
(1 to 64)
图 7-82. LCD Raster-Mode Active
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Frame Time
VBP = 0
VFP = 0
VSW = 1
LPP_B10 + LPP
(1 to 2048)
Line
Time
LCD_HSYNC
LCD_VSYNC
1, L
Data
1, L:
P, L
1, 1:
P, 1
1, 2:
P, 2
1, 3:
P, 3
1, 4:
P, 4
1, 5:
P, 5
1, 6:
P, 6
1, L
P, L
1, 1
P, 1
1, 2
P, 2
LCD_DATA[7:0]
1, L−1
P, L−1
1, L−4
P, L−4
1, L−3 1, L−2 1, L−1
P, L−1
P, L−3 P, L−2
LCD_AC_BIAS_EN
ACB
ACB
(0 to 255)
(0 to 255)
10
10
LCD_HSYNC
LCD_PCLK
1, 5 2, 5
P, 5
1, 6 2, 6
P, 6
LCD_DATA[7:0]
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 5
HFP
HSW
HBP
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 6
(1 to 256)
(1 to 64)
(1 to 256)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
图 7-83. LCD Raster-Mode Passive
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6
LCD_AC_BIAS_EN
LCD_VSYNC
8
10
10
LCD_HSYNC
1
3
2
LCD_PCLK
(passive mode)
4
5
LCD_DATA[7:0]
(passive mode)
1, L 2, L
P, L
1, 1 2, 1
P, 1
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
(active mode)
1, L 2, L
P, L
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
Line L
Line 1 (Passive Only)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
图 7-84. LCD Raster-Mode Control Signal Activation
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LCD_AC_BIAS_EN
LCD_VSYNC
ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
6
8
10
10
LCD_HSYNC
1
3
2
LCD_PCLK
(passive mode)
4
5
LCD_D[7:0]
(passive mode)
1, 1 2, 1
P, 1
1, 2 2, 2
P, 2
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
(active mode)
1, 1 2, 1
P, 1
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
Line 1
Line 1 for active
Line 2 for passive
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
图 7-85. LCD Raster-Mode Control Signal Deactivation
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7.11 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
7.11.1 McASP Device-Specific Information
The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and
McASP1). The McASP module consists of a transmit and receive section. These sections can operate
completely independently with different data formats, separate master clocks, bit clocks, and frame syncs
or, alternatively, the transmit and receive sections may be synchronized. The McASP module also
includes shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
SPDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports
the TDM synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format; however, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode, which is useful for nonaudio data (for example,
passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling,
as well as error management.
The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size
is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to
better manage DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel
Audio Serial Port (McASP) section of the AM335x and AMIC110 Sitara Processors Technical Reference
Manual.
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7.11.2 McASP Electrical Data and Timing
表 7-80. McASP Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
4(1)
4(1)
ns
ns
Output Condition
CLOAD
Output load capacitance
15
30
pF
(1) Except when specified otherwise.
表 7-81. Timing Requirements for McASP(1)
(see 图 7-86)
OPP100
MIN
OPP50
NO.
UNIT
MAX
MIN
MAX
Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
20
40
ns
ns
ns
ns
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
0.5P - 2.5(2)
0.5P - 2.5(2)
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
20
40
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
0.5R - 2.5(3)
0.5R - 2.5(3)
ACLKR and
ACLKX int
11.5
4
15.5
6
Setup time, McASP[x]_AFSR and
McASP[x]_AFSX input valid before
McASP[x]_ACLKR and
tsu(AFSRX-
ACLKRX)
ACLKR and
ACLKX ext in
5
6
7
8
ns
ns
ns
ns
McASP[x]_ACLKX
ACLKR and
ACLKX ext out
4
6
ACLKR and
ACLKX int
-1
-1
Hold time, McASP[x]_AFSR and
McASP[x]_AFSX input valid after
McASP[x]_ACLKR and
th(ACLKRX-
AFSRX)
ACLKR and
ACLKX ext in
0.4
0.4
11.5
4
0.4
0.4
15.5
6
McASP[x]_ACLKX
ACLKR and
ACLKX ext out
ACLKR and
ACLKX int
Setup time, McASP[x]_AXR input
tsu(AXR-ACLKRX) valid before McASP[x]_ACLKR and
McASP[x]_ACLKX
ACLKR and
ACLKX ext in
ACLKR and
ACLKX ext out
4
6
ACLKR and
ACLKX int
-1
-1
Hold time, McASP[x]_AXR input
th(ACLKRX-AXR) valid after McASP[x]_ACLKR and
McASP[x]_ACLKX
ACLKR and
ACLKX ext in
0.4
0.4
0.4
0.4
ACLKR and
ACLKX ext out
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in nanoseconds (ns).
(3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns.
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2
1
2
McASP[x]_ACLKR/X (Falling Edge Polarity)
McASP[x]_AHCLKR/X (Rising Edge Polarity)
4
4
3
McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
6
5
McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
8
7
McASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
图 7-86. McASP Input Timing
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表 7-82. Switching Characteristics for McASP(1)
(see 图 7-87)
OPP100
OPP50
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
9
tc(AHCLKRX)
20(2)
40
ns
ns
ns
ns
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
0.5P – 2.5(3)
0.5P – 2.5(3)
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
20
40
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
0.5P – 2.5(3)
0.5P – 2.5(3)
ACLKR and
ACLKX int
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
0
2
6
0
2
6
ACLKR and
ACLKX ext in
13.5
18
McASP[x]_AFSX output valid
13 td(ACLKRX-AFSRX)
ns
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to ACLKR and
McASP[x]_AFSR and
McASP[x]_AFSX output valid with
Pad Loopback
ACLKX ext
out
2
13.5
2
18
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid
ACLKX int
0
2
6
0
2
6
ACLKX ext in
13.5
18
14 td(ACLKX-AXR)
ns
ns
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid with Pad Loopback
ACLKX ext
out
2
13.5
2
18
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance
ACLKX int
0
2
6
0
2
6
ACLKX ext in
13.5
18
15 tdis(ACLKX-AXR)
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance with pad
loopback
ACLKX ext
out
2
13.5
2
18
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) 50 MHz
(3) P = AHCLKR and AHCLKX period.
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10
10
9
McASP[x]_ACLKR/X (Falling Edge Polarity)
McASP[x]_AHCLKR/X (Rising Edge Polarity)
12
11
12
McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
13
13
13
McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
McASP[x]_AXR[x] (Data Out/Transmit)
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
图 7-87. McASP Output Timing
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7.12 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x and
AMIC110 Sitara Processors Technical Reference Manual.
7.12.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for
any McSPI and any channel (n).
7.12.1.1 McSPI—Slave Mode
表 7-83. McSPI Timing Conditions – Slave Mode
PARAMETER
MIN
MAX UNIT
Input Conditions
tr
Input signal rise time
Input signal fall time
5
5
ns
ns
tf
Output Condition
Cload
Output load capacitance
20
pF
表 7-84. Timing Requirements for McSPI Input Timings—Slave Mode
(see 图 7-88)
OPP100
OPP50
MIN
NO.
UNIT
MIN
MAX
MAX
1
2
tc(SPICLK)
Cycle time, SPI_CLK
62.5
124.8
ns
ns
0.5P –
3.12(1)
0.5P +
3.12(1)
0.5P –
3.12(1)
0.5P +
3.12(1)
tw(SPICLKL)
Typical pulse duration, SPI_CLK low
0.5P –
3.12(1)
0.5P +
3.12(1)
0.5P –
3.12(1)
0.5P +
3.12(1)
3
4
5
tw(SPICLKH)
Typical pulse duration, SPI_CLK high
ns
ns
ns
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK
active edge(2)(3)
tsu(SIMO-SPICLK)
th(SPICLK-SIMO)
tsu(CS-SPICLK)
th(SPICLK-CS)
12.92
12.92
12.92
12.92
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
active edge(2)(3)
Setup time, SPI_CS valid before SPI_CLK first
edge(2)
Hold time, SPI_CS valid after SPI_CLK last edge(2)
8
9
12.92
12.92
12.92
12.92
ns
ns
(1) P = SPI_CLK period.
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
表 7-85. Switching Characteristics for McSPI Output Timings—Slave Mode
(see 图 7-89)
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Delay time, SPI_CLK active edge to
SPI_D[x] (SOMI) transition(1)(2)
6
7
td(SPICLK-SOMI)
td(CS-SOMI)
–4.00
17.12
–4.00
17.12
ns
ns
Delay time, SPI_CS active edge to
SPI_D[x] (SOMI) transition(1)(2)
17.12
17.12
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
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PHA=0
EPOL=1
SPI_CS[x] (In)
1
3
3
8
2
2
9
POL=0
POL=1
SPI_SCLK (In)
1
SPI_SCLK (In)
4
4
5
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
SPI_SCLK (In)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (In)
4
4
5
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
图 7-88. SPI Slave Mode Receive Timing
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PHA=0
EPOL=1
SPI_CS[x] (In)
1
3
8
2
2
9
POL=0
POL=1
SPI_SCLK (In)
1
3
SPI_SCLK (In)
6
7
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
SPI_SCLK (In)
1
1
3
2
8
2
3
9
POL=0
POL=1
SPI_SCLK (In)
6
6
6
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
图 7-89. SPI Slave Mode Transmit Timing
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7.12.1.2 McSPI—Master Mode
表 7-86. McSPI Timing Conditions – Master Mode
LOW LOAD
MIN
HIGH LOAD
MIN
PARAMETER
UNIT
MAX
MAX
Input Conditions
tr
Input signal rise time
8
8
8
8
ns
ns
tf
Input signal fall time
Output Condition
Cload
Output load capacitance
5
25
pF
表 7-87. Timing Requirements for McSPI Input Timings – Master Mode
(see 图 7-90)
OPP100
LOW LOAD HIGH LOAD
OPP50
LOW LOAD
NO.
HIGH LOAD
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tsu(SOMI-
Setup time, SPI_D[x] (SOMI) valid before
SPI_CLK active edge(1)
4
2.29
3.02
2.29
3.02
ns
SPICLKH)
Industrial extended
temperature
(-40°C to 125°C)
7.1
4.7
7.1
4.7
7.1
4.7
7.1
4.7
Hold time, SPI_D[x]
(SOMI) valid after
th(SPICLKH-
5
ns
SPI_CLK active edge(1)
SOMI)
All other
temperature ranges
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
表 7-88. Switching Characteristics for McSPI Output Timings – Master Mode
(see 图 7-91)
OPP100
OPP50
NO.
PARAMETER
LOW LOAD
MIN
HIGH LOAD
MIN
LOW LOAD
MIN
HIGH LOAD
MIN MAX
UNIT
MAX
MAX
MAX
1
2
tc(SPICLK)
Cycle time, SPI_CLK
20.8
20.8
41.6
41.6
ns
ns
Typical pulse duration,
SPI_CLK low
0.5P –
1.04(1)
0.5P +
1.04(1)
0.5P –
2.08(1)
0.5P +
2.08(1)
0.5P –
1.04(1)
0.5P +
1.04(1)
0.5P –
2.08(1)
0.5P +
2.08(1)
tw(SPICLKL)
Typical pulse duration,
SPI_CLK high
0.5P –
1.04(1)
0.5P +
1.04(1)
0.5P –
2.08(1)
0.5P +
2.08(1)
0.5P –
1.04(1)
0.5P +
1.04(1)
0.5P –
2.08(1)
0.5P +
2.08(1)
3
6
tw(SPICLKH)
ns
ns
Delay time, SPI_CLK
td(SPICLK-SIMO) active edge to SPI_D[x]
–3.57
3.57
3.57
–4.62
4.62
4.62
–3.57
3.57
3.57
–4.62
4.62
4.62
(SIMO) transition(2)
Delay time, SPI_CS active
7
8
td(CS-SIMO)
edge to SPI_D[x] (SIMO)
ns
transition(2)
Mode 1
A – 4.2(4)
B – 4.2(5)
B – 4.2(5)
A – 2.54(4)
B – 2.54(5)
B – 2.54(5)
A – 4.2(4)
B – 4.2(5)
B – 4.2(5)
A – 2.54(4)
B – 2.54(5)
B – 2.54(5)
ns
ns
ns
Delay time,
SPI_CS active
and 3(3)
td(CS-SPICLK)
to SPI_CLK
first edge
Mode 0
and 2(3)
Delay time,
SPI_CLK last
edge to
SPI_CS
inactive
Mode 1
and 3(3)
9
td(SPICLK-CS)
Mode 0
and 2(3)
A – 4.2(4)
A – 2.54(4)
A – 4.2(4)
A – 2.54(4)
ns
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
–
–
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
(4) Case P = 20.8 ns, A = (TCS + 1) × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
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(5) B = (TCS + 0.5) × TSPICLKREF × Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even ≥ 2).
PHA=0
EPOL=1
SPI_CS[x] (Out)
1
3
8
2
3
9
POL=0
POL=1
SPI_SCLK (Out)
1
2
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
SPI_SCLK (Out)
1
2
1
3
3
2
8
9
POL=0
POL=1
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
图 7-90. SPI Master Mode Receive Timing
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PHA=0
EPOL=1
SPI_CS[x] (Out)
1
3
2
8
2
3
9
POL=0
POL=1
SPI_SCLK (Out)
1
SPI_SCLK (Out)
6
7
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
SPI_SCLK (Out)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (Out)
6
6
6
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
图 7-91. SPI Master Mode Transmit Timing
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7.13 Multimedia Card (MMC) Interface
For more information, see the Multimedia Card (MMC) section of the AM335x and AMIC110 Sitara
Processors Technical Reference Manual.
7.13.1 MMC Electrical Data and Timing
表 7-89. MMC Timing Conditions
PARAMETER
MIN
TYP
MAX UNIT
Input Conditions
tr
tf
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
Cload
Output load capacitance
3
30
pF
表 7-90. Timing Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0]
(see 图 7-92)
1.8-V MODE
MIN TYP MAX
3.3-V MODE
NO.
UNIT
MIN
TYP MAX
1
2
3
4
tsu(CMDV-CLKH) Setup time, MMC_CMD valid before MMC_CLK rising clock edge
4.1
4.1
ns
Industrial extended
temperature
MMC0-2
3.76
3.76
(–40°C to 125°C)
Hold time, MMC_CMD valid after
MMC_CLK rising clock edge
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
ns
ns
ns
MMC0
MMC1
MMC2
3.76
3.76
3.76
4.1
2.52
3.03
3.0
All other
temperature ranges
Setup time, MMC_DATx valid before MMC_CLK rising clock edge
4.1
Industrial extended
temperature
(–40°C to 125°C)
MMC0-2
3.76
3.76
Hold time, MMC_DATx valid after
MMC_CLK rising clock edge
MMC0
MMC1
MMC2
3.76
3.76
3.76
2.52
3.03
3.0
All other
temperature ranges
1
2
MMC[x]_CLK (Output)
MMC[x]_CMD (Input)
MMC[x]_DAT[7:0] (Inputs)
3
4
图 7-92. MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing
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表 7-91. Switching Characteristics for MMC[x]_CLK
(see 图 7-93)
NO.
STANDARD MODE
MIN TYP MAX
HIGH-SPEED MODE
MIN TYP MAX
PARAMETER
UNIT
ƒop(CLK)
Operating frequency, MMC_CLK
Operating period: MMC_CLK
24
48 MHz
ns
tcop(CLK)
41.7
20.8
5
fid(CLK)
Identification mode frequency, MMC_CLK
Identification mode period: MMC_CLK
400
400 kHz
ns
tcid(CLK)
2500
2500
(0.5 × P) –
(0.5 × P) –
6
7
tw(CLKL)
tw(CLKH)
Pulse duration, MMC_CLK low
Pulse duration, MMC_CLK high
ns
ns
(1)
(1)
tf(CLK)
tf(CLK)
(0.5 × P) –
(0.5 × P) –
(1)
(1)
tr(CLK)
tr(CLK)
(1) P = MMC_CLK period
5
6
7
RMII[x]_REFCLK
(Input)
图 7-93. MMC[x]_CLK Timing
表 7-92. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
(see 图 7-94)
OPP100
TYP
OPP50
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Delay time, MMC_CLK falling clock
edge to MMC_CMD transition
10 td(CLKL-CMD)
11 td(CLKL-DAT)
–4
14
–4
17.5
ns
ns
Delay time, MMC_CLK falling clock
edge to MMC_DATx transition
–4
14
–4
17.5
10
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
11
图 7-94. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode
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表 7-93. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
(see 图 7-95)
OPP100
TYP
OPP50
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td(CLKL-
CMD)
Delay time, MMC_CLK rising clock edge to
MMC_CMD transition
12
3
14
3
17.5
ns
ns
Delay time, MMC_CLK rising clock edge to
MMC_DATx transition
13 td(CLKL-DAT)
3
14
3
17.5
12
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
13
图 7-95. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—High-Speed Mode
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7.14 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
(PRU-ICSS)
For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem Interface (PRU-ICSS) section of the AM335x and AMIC110 Sitara Processors Technical
Reference Manual.
7.14.1 Programmable Real-Time Unit (PRU-ICSS PRU)
表 7-94. PRU-ICSS PRU Timing Conditions
PARAMETER
MIN
MAX
UNIT
Output Condition
Cload
Capacitive load for each bus line
30
pF
7.14.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
表 7-95. PRU-ICSS PRU Timing Requirements - Direct Input Mode
(see 图 7-96)
NO.
MIN
2 × P(1)
MAX
UNIT
ns
1
tw(GPI)
tr(GPI)
tf(GPI)
Pulse width, GPI
Rise time, GPI
Fall time, GPI
1.00
3.00
3.00
1.00
3.00
ns
2
1.00
ns
PRU0
PRU1
3
tsk(GPI)
Internal skew between GPI[n:0] signals(2)
ns
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
(2) n = 16
2
1
GPI[m:0]
3
图 7-96. PRU-ICSS PRU Direct Input Timing
表 7-96. PRU-ICSS PRU Switching Requirements – Direct Output Mode
(see 图 7-69)
NO.
PARAMETER
Pulse width, GPO
MIN
2 × P(1)
MAX
UNIT
1
tw(GPO)
tsk(GPO)
ns
PRU0
PRU1
1.00
5.00
3
Internal skew between GPO[n:0] signals(2)
ns
(1) P = L3_CLK (PRU-ICSS ocp clock) period
(2) n = 15
1
GPO[n:0]
3
图 7-97. PRU-ICSS PRU Direct Output Timing
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7.14.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
表 7-97. PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
(see 图 7-98 and 图 7-99)
NO.
1
MIN
20.00
10.00
10.00
1.00
MAX
UNIT
ns
tc(CLOCKIN)
Cycle time, CLOCKIN
2
tw(CLOCKIN_L)
tw(CLOCKIN_H)
tr(CLOCKIN)
Pulse duration, CLOCKIN low
Pulse duration, CLOCKIN high
Rising time, CLOCKIN
ns
3
ns
4
3.00
3.00
ns
5
tf(CLOCKIN)
Falling time, CLOCKIN
1.00
ns
6
tsu(DATAIN-CLOCKIN)
th(CLOCKIN-DATAIN)
tr(DATAIN)
Setup time, DATAIN valid before CLOCKIN
Hold time, DATAIN valid after CLOCKIN
Rising time, DATAIN
5.00
ns
7
0.00
ns
1.00
3.00
3.00
ns
8
tf(DATAIN)
Falling time, DATAIN
1.00
ns
1
3
5
4
2
CLOCKIN
DATAIN
7
6
8
图 7-98. PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode
1
3
4
5
2
CLOCKIN
DATAIN
7
6
8
图 7-99. PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode
7.14.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
表 7-98. PRU-ICSS PRU Timing Requirements – Shift In Mode
(see 图 7-100)
NO.
MIN
10.00
0.45 × P(1)
MAX
UNIT
ns
1
2
3
4
tc(DATAIN)
tw(DATAIN)
tr(DATAIN)
tf(DATAIN)
Cycle time, DATAIN
Pulse width, DATAIN
Rising time, DATAIN
Falling time, DATAIN
0.55 × P(1)
3.00
ns
1.00
ns
1.00
3.00
ns
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
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1
2
3
4
DATAIN
图 7-100. PRU-ICSS PRU Shift In Timing
表 7-99. PRU-ICSS PRU Switching Requirements - Shift Out Mode
(see 图 7-101)
NO.
MIN
MAX
UNIT
ns
1
2
5
tc(CLOCKOUT)
Cycle time, CLOCKOUT
10.00
0.45 × P(1)
0.00
tw(CLOCKOUT)
Pulse width, CLOCKOUT
0.55 × P(1)
3.00
ns
td(CLOCKOUT-DATAOUT)
Delay time, CLOCKOUT to DATAOUT valid
ns
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
1
2
CLOCKOUT
DATAOUT
5
6
图 7-101. PRU-ICSS PRU Shift Out Timing
7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
表 7-100. PRU-ICSS ECAT Timing Conditions
PARAMETER
MIN
MAX
UNIT
Output Condition
Cload
Capacitive load for each bus line
30
pF
7.14.2.1 PRU-ICSS ECAT Electrical Data and Timing
表 7-101. PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
(see 图 7-102)
NO.
MIN
100.00
1.00
MAX
UNIT
ns
1
2
3
tw(EDIO_LATCH_IN)
tr(EDIO_LATCH_IN)
tf(EDIO_LATCH_IN)
Pulse width, EDIO_LATCH_IN
Rising time, EDIO_LATCH_IN
Falling time, EDIO_LATCH_IN
3.00
3.00
ns
1.00
ns
tsu(EDIO_DATA_IN-
EDIO_LATCH_IN)
th(EDIO_LATCH_IN-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN
active edge
4
5
20.00
20.00
ns
ns
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active
edge
tr(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
ns
ns
6
tf(EDIO_DATA_IN)
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2
3
EDIO_LATCH_IN
1
4
5
EDIO_DATA_IN[7:0]
6
图 7-102. PRU-ICSS ECAT Input Validated With LATCH_IN Timing
表 7-102. PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
(see 图 7-103)
NO.
MIN
MAX
UNIT
ns
1
2
3
tw(EDC_SYNCx_OUT)
tr(EDC_SYNCx_OUT)
tf(EDC_SYNCx_OUT)
Pulse width, EDC_SYNCx_OUT
Rising time, EDC_SYNCx_OUT
Falling time, EDC_SYNCx_OUT
100.00
1.00
3.00
3.00
ns
1.00
ns
tsu(EDIO_DATA_IN-
EDC_SYNCx_OUT)
th(EDC_SYNCx_OUT-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before
EDC_SYNCx_OUT active edge
4
5
20.00
20.00
ns
ns
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT
active edge
tr(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
ns
ns
6
tf(EDIO_DATA_IN)
2
3
EDC_SYNCx_OUT
1
4
5
EDIO_DATA_IN[7:0]
6
图 7-103. PRU-ICSS ECAT Input Validated With SYNCx Timing
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表 7-103. PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
(see 图 7-104)
NO.
1
MIN
4 × P(1)
1.00
MAX
5 × P(1)
3.00
UNIT
ns
tw(EDIO_SOF)
tr(EDIO_SOF)
tf(EDIO_SOF)
Pulse duration, EDIO_SOF
Rising time, EDIO_SOF
Falling time, EDIO_SOF
2
ns
3
1.00
3.00
ns
tsu(EDIO_DATA_IN-
EDIO_SOF)
Setup time, EDIO_DATA_IN valid before EDIO_SOF
active edge
4
5
20.00
20.00
ns
ns
Hold time, EDIO_DATA_IN valid after EDIO_SOF active
edge
th(EDIO_SOF-EDIO_DATA_IN)
tr(EDIO_DATA_IN)
tf(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
ns
ns
6
(1) P = PRU-ICSS IEP clock source period.
2
3
EDIO_SOF
1
4
5
EDIO_DATA_IN[7:0]
6
图 7-104. PRU-ICSS ECAT Input Validated With SOF
表 7-104. PRU-ICSS ECAT Timing Requirements - LATCHx_IN
(see 图 7-105)
NO.
MIN
3 × P(1)
MAX
UNIT
ns
1
2
3
tw(EDC_LATCHx_IN)
tr(EDC_LATCHx_IN)
tf(EDC_LATCHx_IN)
Pulse duration, EDC_LATCHx_IN
Rising time, EDC_LATCHx_IN
Falling time, EDC_LATCHx_IN
1.00
3.00
3.00
ns
1.00
ns
(1) P = PRU-ICSS IEP clock source period.
2
3
EDC_LATCHx_IN
1
图 7-105. PRU-ICSS ECAT LATCHx_IN Timing
226
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表 7-105. PRU-ICSS ECAT Switching Requirements - Digital I/Os
NO.
PARAMETER
MIN
MAX
UNIT
1
4
7
tw(EDIO_OUTVALID)
Pulse duration, EDIO_OUTVALID
14 × P(1)
32 × P(1)
ns
td(EDIO_OUTVALID-
EDIO_DATA_OUT)
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
EDIO_DATA_OUT skew
0.00
18 × P(1)
8.00
ns
ns
tsk(EDIO_DATA_OUT)
(1) P = PRU-ICSS IEP clock source period.
7.14.3 PRU-ICSS MII_RT and Switch
表 7-106. PRU-ICSS MII_RT Switch Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
3(1)
3(1)
ns
ns
Output Condition
CLOAD
Output load capacitance
3
20
pF
(1) Except when specified otherwise.
7.14.3.1 PRU-ICSS MDIO Electrical Data and Timing
表 7-107. PRU-ICSS MDIO Timing Requirements – MDIO_DATA
(see 图 7-106)
NO.
MIN
90
0
TYP
MAX
UNIT
ns
1
2
tsu(MDIO-MDC)
Setup time, MDIO valid before MDC high
Hold time, MDIO valid from MDC high
th(MDIO-MDC)
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
图 7-106. PRU-ICSS MDIO_DATA Timing - Input Mode
表 7-108. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
(see 图 7-107)
NO.
PARAMETER
Cycle time, MDC
MIN
400
160
160
TYP
MAX
UNIT
ns
1
2
3
tc(MDC)
tw(MDCH)
tw(MDCL)
Pulse duration, MDC high
Pulse duration, MDC low
ns
ns
1
2
3
MDIO_CLK
图 7-107. PRU-ICSS MDIO_CLK Timing
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表 7-109. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
(see 图 7-108)
NO.
MIN
TYP
MAX
UNIT
(P*0.5)
-10(1)
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
10
ns
(1) P = MDIO_CLK Period
1
MDIO_CLK (Output)
MDIO_DATA (Output)
图 7-108. PRU-ICSS MDIO_DATA Timing – Output Mode
7.14.3.2 PRU-ICSS MII_RT Electrical Data and Timing
注
In order to guarantee the MII_RT I/O timing values published in the device data manual, the
PRU ocp_clk clock must be configured for 200 MHz (default value) and the TX_CLK_DELAY
bit field in the PRUSS_MII_RT_TXCFG0/1 register must be configured as follows:
•
•
100 Mbps mode: 6h (non-default value)
10 Mbps mode: 0h (value)
表 7-110. PRU-ICSS MII_RT Timing Requirements – MII_RXCLK
(see 图 7-109)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
Pulse duration, RX_CLK high
Pulse duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
3
3
1
4
2
3
MII_RXCLK
4
图 7-109. PRU-ICSS MII_RXCLK Timing
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
表 7-111. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
(see 图 7-110)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Cycle time, TX_CLK
ns
ns
ns
ns
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
140
260
14
26
3
3
1
4
2
3
MII_TXCLK
4
图 7-110. PRU-ICSS MII_TXCLK Timing
表 7-112. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
(see 图 7-111)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
MAX
MIN
MAX
tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
Setup time, RXD[3:0] valid before RX_CLK
1
2
8
8
ns
ns
th(RX_CLK-RXD)
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
1
2
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
图 7-111. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
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表 7-113. PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
(see 图 7-112)
10 Mbps
TYP
100 Mbps
TYP
NO
.
UNIT
MAX
MIN
MAX
MIN
td(TX_CLK-TXD)
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
1
5
25
5
25 ns
td(TX_CLK-TX_EN)
1
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
图 7-112. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing
7.14.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
表 7-114. UART Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
10
10
ns
ns
Output Conditions
CLOAD
Output load capacitance
25
pF
表 7-115. Timing Requirements for PRU-ICSS UART Receive
(see 图 7-113)
NO.
MIN
0.96U(1)
MAX
1.05U(1)
UNIT
3
tw(RX)
Pulse duration, receive start, stop, data bit
ns
(1) U = UART baud time = 1/programmed baud rate.
表 7-116. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART
Transmit
(see 图 7-113)
NO.
1
PARAMETER
MIN
0
U – 2(1)
MAX
12
U + 2(1)
UNIT
MHz
ns
ƒbaud(baud)
tw(TX)
Maximum programmable baud rate
Pulse duration, transmit start, stop, data bit
2
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UART_TXD
Data Bits
5
4
Start
Bit
UART_RXD
Data Bits
图 7-113. PRU-ICSS UART Timing
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7.15 Universal Asynchronous Receiver Transmitter (UART)
For more information, see the Universal Asynchronous Receiver Transmitter (UART) section of the
AM335x and AMIC110 Sitara Processors Technical Reference Manual.
7.15.1 UART Electrical Data and Timing
表 7-117. UART Timing Conditions
PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
10
10
ns
ns
Output Conditions
CLOAD
Output load capacitance
25
pF
表 7-118. Timing Requirements for UARTx Receive
(see 图 7-114)
NO.
MIN
MAX
UNIT
3
tw(RX)
Pulse duration, receive start, stop, data bit
0.96U(1)
1.05U(1)
ns
(1) U = UART baud time = 1/programmed baud rate.
表 7-119. Switching Characteristics for UARTx Transmit
(see 图 7-114)
NO.
PARAMETER
Maximum programmable baud rate
MIN
MAX
3.6864
U + 2(1)
UNIT
MHz
ns
1
2
ƒbaud(baud)
tw(TX)
Pulse duration, transmit start, stop, data bit
U – 2(1)
(1) U = UART baud time = 1 / programmed baud rate
2
2
2
Start
Bit
UARTx_TXD
Stop Bit
Data Bits
3
3
3
Start
Bit
UARTx_RXD
Stop Bit
Data Bits
图 7-114. UART Timings
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7.15.2 UART IrDA Interface
The IrDA module operates in three different modes:
•
•
•
Slow infrared (SIR) (≤115.2 kbps)
Medium infrared (MIR) (0.576 Mbps and 1.152 Mbps)
Fast infrared (FIR) (4 Mbps).
图 7-115 shows the UART IrDA pulse parameters. 表 7-120 and 表 7-121 list the signaling rates and pulse
durations for UART IrDA receive and transmit modes.
Pulse Duration
Pulse Duration
50%
50%
50%
图 7-115. UART IrDA Pulse Parameters
表 7-120. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MIN
MAX
SIR
2.4 kbps
1.41
1.41
1.41
1.41
1.41
1.41
88.55
22.13
11.07
5.96
µs
µs
µs
µs
µs
µs
9.6 kbps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
MIR
4.34
2.23
0.576 Mbps
1.152 Mbps
FIR
297.2
149.6
518.8
258.4
ns
ns
4 Mbps (single pulse)
4 Mbps (double pulse)
67
164
289
ns
ns
190
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表 7-121. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
ELECTRICAL PULSE DURATION
MIN
SIGNALING RATE
UNIT
MAX
SIR
2.4 kbps
78.1
19.5
9.75
4.87
3.25
1.62
78.1
19.5
9.75
4.87
3.25
1.62
µs
µs
µs
µs
µs
µs
9.6 kbps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
MIR
0.576 Mbps
1.152 Mbps
FIR
414
206
419
211
ns
ns
4 Mbps (single pulse)
4 Mbps (double pulse)
123
248
128
253
ns
ns
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8 Device and Documentation Support
8.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, XAM3358AZCE). Texas Instruments recommends two of three possible prefix designators
for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices and tools
(TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCE), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, 27 is 275 MHz). 图 8-1
provides a legend for reading the complete device name for any AM335x device.
For orderable part numbers of AM335x devices in the ZCE and ZCZ package types, see the Package
Option Addendum of this document, ti.com, or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AM335x Sitara
Processors Silicon Errata.
234
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
(
)
X
(
)
(
)
AM3358
B
ZCZ
PREFIX
CARRIER TYPE
Blank = Tray
R = Tape and Reel
X = Experimental device
Blank = Qualified device
DEVICE(A)
ARM Cortex-A8 MPU:
AM3351
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
DEVICE SPEED RANGE
27 = 275-MHz Cortex-A8
30 = 300-MHz Cortex-A8
50 = 500-MHz Cortex-A8
60 = 600-MHz Cortex-A8
72 = 720-MHz Cortex-A8
80 = 800-MHz Cortex-A8
100 = 1-GHz Cortex-A8
TEMPERATURE RANGE
DEVICE REVISION CODE
Blank = silicon revision 1.0
A = silicon revision 2.0
Blank = 0°C to 90°C (commercial junction temperature)
A = -40°C to 105°C (extended junction temperature)
D = -40°C to 90°C (industrial junction temperature)
T = -40°C to 125°C (industrial extended junction temperature)
B = silicon revision 2.1
PACKAGE TYPE(B)
ZCE = 298-pin plastic BGA, with Pb-Free solder balls
ZCZ = 324-pin plastic BGA, with Pb-Free solder balls
A. The AM3358 device shown in this device nomenclature example is one of several valid part numbers for the AM335x
family of devices. For orderable device part numbers, see the Package Option Addendum of this document.
B. BGA = Ball grid array
图 8-1. AM335x Device Nomenclature
8.2 Tools and Software
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed below.
Design Kits and Evaluation Modules
AM335x Evaluation Module Enables developers to immediately start evaluating the AM335x processor
family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications such
as portable navigation, portable gaming, home/building automation and others.
AM335x Starter Kit Provides a stable and affordable platform to quickly start evaluation of Sitara ARM
Cortex-A8 AM335x Processors (AM3351, AM3352, AM3354, AM3356, AM3358) and
accelerate development for smart appliance, industrial and networking applications. It is a
low-cost development platform based on the ARM Cortex-A8 processor that is integrated
with options such as Dual Gigabit Ethernet, DDR3 and LCD touch screen.
BeagleBone Black Development Board Low-cost, open source, community-supported development
platform for ARM Cortex-A8 processor developers and hobbyists. Boot Linux in under 10-
seconds and get started on Sitara AM335x ARM Cortex-A8 processor development in less
than 5 minutes with just a single USB cable.
BeagleBone Development Board Low-cost, community-supported development platform for ARM
Cortex-A8 processor developers. Boot Linux in under 10-seconds and get started on Sitara
AM335x ARM Cortex-A8 processor development in less than 5 minutes with just a single
USB cable. For TI-supported hardware platforms, consider the Sitara ARM AM335x Starter
Kit or AM335x Evaluation Module.
Data Concentrator Evaluation Module Based on AM3359 as the main processor and has Power Line
Communication (PLC) Module to support various OFDM PLC communication standards.
TMDSDC3359 also has capability to support multiple interfaces, sub-1GHz and 2.4GHz RF,
Ethernet, RS-232, and RS-485. This evaluation module is ideal development platform for
smart grid infrastructure applications including data concentrator, convergent node of grid
sensor network, and control equipment of power automation.
WiLink™ 8 Dual Band 2.4 & 5 GHz Wi-Fi® + Bluetooth® COM8 Evaluation Module Enables customers
to add both Wi-Fi and Bluetooth to home and building automation, smart energy, gateways,
wireless audio, enterprise, wearables and many more industrial and Internet of Things (IoT)
applications. TI’s WiLink 8 modules are certified and offer high throughput and extended
range along with Wi-Fi and Bluetooth coexistence in a power-optimized design. Drivers for
the Linux and Android high-level operating systems (HLOSs) are available free of charge
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from TI for the Sitara AM335x microprocessor (Linux and Android version restrictions apply).
WiLink 8 Module 2.4 GHz WiFi + Bluetooth COM8 Evaluation Module Enables customers to add Wi-Fi
and Bluetooth (WL183x module only) to embedded applications based on TI's Sitara
microprocessors. TI’s WiLink 8 Wi-Fi + Bluetooth modules are pre-certified and offer high
throughput and extended range along with Wi-Fi and Bluetooth coexistence (WL183x
modules only) in a power-optimized design. Drivers for the Linux and Android high-level
operating systems (HLOSs) are available free of charge from TI for the Sitara AM335x
microprocessor (Linux and Android version restrictions apply).
TI Designs
EtherCAT Communications Development Platform Allows designers to implement real-time EtherCAT
communications standards in a broad range of industrial automation equipment. It enables
low foot print designs in applications such as industrial automation, factory automation or
industrial communication with minimal external components and with best in class low power
performance.
PROFIBUS Communications Development Platform Allows designers to implement PROFIBUS
communications standards in a broad range of industrial automation equipment. It enables
low foot print designs in applications such as industrial automation, factory automation or
industrial communication with minimal external components and with best in class low power
performance.
Ethernet/IP Communications Development Platform Allows designers to mplement Ethernet/IP
communications standards in a broad range of industrial automation equipment. It enables
low foot print designs in applications such as industrial automation, factory automation or
industrial communication with minimal external components and with best in class low power
performance.
Acontis EtherCAT Master Stack Reference Design Highly portable software stack that can be used on
various embedded platforms. The EC-Master supports the high performane TI Sitara MPUs,
it provides a sophisticated EtherCAT Master solution which customers can use to implement
EtherCAT communication interface boards, EtherCAT based PLC or motion control
applications. The EC-Master architectural design does not require additional tasks to be
scheduled, thus the full stack functionality is available even on an OS less platform such as
TI Starterware suported on AM335x. Due to this architecture combined with the high speed
Ethernet driver it is possible to implement EtherCAT master based applications on the Sitara
platform with short cycle times of 100 microseconds or even below.
Solar Inverter Gateway Development Platform Reference Design Adds communication functions to
solar energy generation systems to enable system monitoring, real-time feedback, system
updates, and more. The TIDEP0044 reference design describes the implementation of a
solar inverter gateway using display, Ethernet, USB, and CAN on the TMDXEVM3358
featuring TI's AM335x processor.
G3 Power Line Communications Data Concentrator on BeagleBone Black Platform
Offers
a
simplified approach for evaluating G3-PLC utilizing Beagle Bone Black powered by the Sitara
AM335x processor. Users can establish a G3-PLC network with one service node. Single
phase coupling is supported.
IEC 61850 Demonstration of Substation Bay Controller on Beaglebone Cape and Starter Kit
Low-
cost, simplified implementation of an IEC 61850 Substation Bay Controller is demonstrated
by running the Triangle MicroWorks IEC 61850 stack efficiently on the TI AM335X platform
with a Linux target layer definition. Many different substation automation applications can be
built on top of the AM335X platform and 61850 stack demonstration.
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PRU Real-Time I/O Evaluation Reference Design BeagleBone Black add-on board that allows users get
to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The
PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and
AM437x family of devices. The PRU core is optimized for deterministic, real-time processing,
direct access to I/Os and ultra-low-latency requirements. With LEDs and push buttons for
GPIO, audio, a temp sensor, optional character display and more, this add-on board includes
schematics, bill of materials (BOM), design files, and design guide to teach the basics of the
PRU.
Smart Home and Energy Gateway Reference Design
Provides
example
implementation
for
measurement, management and communication of energy systems for smart homes and
buildings. This example design is a bridge between different communication interfaces, such
as WiFi, Ethernet, ZigBee or Bluetooth, that are commonly found in residential and
commercial buildings. Since objects in the house and buildings are becoming more and
more connected, the gateway design needs to be flexible to accommodate different RF
standard, since no single RF standard is dominating the market. This example gateway
addresses this problem by supporting existing legacy RF standards (WiFi, Bluetooth) and
newer RF standards (ZigBee, BLE).
Streaming Audio Reference Design Minimizes design time for customers by offering small form factor
hardware and major software components, including streaming protocols and internet radio
services. With this reference design, TI offers a quick and easy transition path to the
AM335x and WiLink8 platform solution. This proven combo solution provides key
advantages in this market category that helps bring your products to the next level.
Software
Processor SDK for AM335X Sitara Processors - Linux and TI-RTOS Support
Unified
software
platform for TI embedded processors providing easy setup and fast out-of-the-box access to
benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad
portfolio, allowing developers to seamlessly reuse and migrate software across devices.
Developing scalable platform solutions has never been easier than with the Processor SDK
and TI’s embedded processor solutions.
G3 Data Concentrator Power-Line Communication Modem G3-PLC standard for narrowband OFDM
Power Line Communications. The data concentrator solution is designed for the head-end
systems which communicate with the end meters (“service node”) in the neighborhood area
network.
PRIME Data Concentrator Power-Line Communication Modem PRIME standard for narrowband
OFDM Power Line Communications. The data concentrator solution is designed for the
head-end systems which communicate with the end meters (“service node”) in the
neighborhood area network.
TI Dual-Mode Bluetooth Stack Comprised of Single-Mode and Dual-Mode offerings implementing the
Bluetooth 4.0 specification. The Bluetooth stack is fully Bluetooth Special Interest Group
(SIG) qualified, certified and royalty-free, provides simple command line sample applications
to speed development, and upon request has MFI capability.
Cryptography for TI Devices Enables encryption, crypto for TI devices. These files contain only
cryptographic modules that were part of a TI software release. For the complete software
release please search ti.com for your device part number, and download the Software
Development Kit (SDK).
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Development Tools
Clock Tree Tool for Sitara ARM Processors Interactive clock tree configuration software that provides
information about the clocks and modules in Sitara devices.
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM
Processors
Integrated development environment (IDE) that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and
debug embedded applications. It includes an optimizing C/C++ compiler, source code editor,
project build environment, debugger, profiler, and many other features. The intuitive IDE
provides a single user interface taking you through each step of the application development
flow. Familiar tools and interfaces allow users to get started faster than ever before. Code
Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich
development environment for embedded developers.
Pin Mux Tool Provides a Graphical User Interface for configuring pin multiplexing settings, resolving
conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C
header/code files that can be imported into software development kits (SDK) or used to
configure customer's custom software. Version 3 of the Pin Mux utility adds the capability of
automatically selecting a mux configuration that satisfies the entered requirements.
Power Estimation Tool (PET) Provides users the ability to gain insight in to the power consumption of
select TI processors. The tool includes the ability for the user to choose multiple application
scenarios and understand the power consumption as well as how advanced power saving
techniques can be applied to further reduce overall power consumption.
Uniflash Standalone Flash Tool for TI Microcontrollers (MCU), Sitara Processors and SimpleLink
devices
Programs on-chip flash memory on TI MCUs and onboard flash memory for Sitara
processors. Uniflash has a GUI, command line, and scripting interface. CCS Uniflash is
available free of charge.
XDS200 USB Debug Probe Connects to the target board via a TI 20-pin connector (with multiple
adapters for TI 14-pin, ARM 10-pin and ARM 20-pin) and to the host PC via USB2.0 High
Speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the
host PC.
XDS560v2 System Trace USB and Ethernet Debug Probe Adds system pin trace in its large external
memory buffer. Available for selected TI devices, this external memory buffer captures
device-level information that allows obtaining accurate bus performance activity and
throughput, as well as power management of core and peripherals. Also, all XDS debug
probes support Core and System Trace in all ARM and DSP processors that feature an
Embedded Trace Buffer (ETB).
XDS560v2 System Trace USB Debug Probe Adds system pin trace in its large external memory buffer.
Available for selected TI devices, this external memory buffer captures device-level
information that allows obtaining accurate bus performance activity and throughput, as well
as power management of core and peripherals. Also, all XDS debug probes support Core
and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer
(ETB).
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Models
AM335x ZCE IBIS Model ZCE package IBIS model
AM335x ZCZ IBIS Model ZCZ package IBIS model
AM335x ZCE Rev. 2.1 BSDL Model ZCE package BSDL model for the revision 2.1 TI F781962A Fixed-
and Floating-Point DSP with Boundary Scan
AM335x ZCZ Rev. 2.1 BSDL Model ZCZ package BSDL model for the revision 2.1 TI F781962A Fixed-
and Floating-Point DSP with Boundary Scan
8.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
AM335x Sitara Processors Silicon Errata
Describes the known exceptions to the functional specifications for the AM335x Sitara
Processors.
Application Reports
Processor SDK RTOS Customization: Modifying Board Library to Change UART Instance on
AM335x
Describes the procedure to modify the default UART0 example in the AM335x Processor
SDK RTOS package to enable UART1. On the BeagleBone Black (BBB) P9 header, pins
24(TX) and 26(RX) are connected to UART1. This procedure shows a test to verify that
UART1 is enabled on the BBB.
High-Speed Layout GuidelinesAs modern bus interface frequencies scale higher, care must be taken in
the printed circuit board (PCB) layout phase of a design to ensure a robust solution.
AM335x Reliability Considerations in PLC ApplicationsProgrammable Logic Controllers (PLC) are
used as the main control in an automation system with high- reliability expectations and long
life in harsh environments. Processors used in these applications require an assessment of
performance verses expected power on hours to achieve the optimal performance for the
application.
AM335x Thermal ConsiderationsDiscusses the thermal considerations of the AM335x devices. It offers
guidance on analysis of the processor's thermal performance, suggests improvements for an
end system to aid in overcoming some of the existing challenges of producing a good
thermal design, and provides real power/thermal data measured with AM335x EVMs for user
evaluation.
User's Guides
TPS65910Ax User's Guide for AM335x Processors User's Guide A reference for connectivity between
the TPS65910Ax power-management integrated circuit (PMIC) and the AM335x processor.
AM335x and AMIC110 Sitara Processors Technical Reference Manual
Details the integration, the environment, the functional description, and the programming
models for each peripheral and subsystem in the device.
G3 Power Line Communications Data Concentrator on BeagleBone Black Platform Design Guide
Provide the foundation that you need including methodology, testing, and design files to
quickly evaluate and customize the system. TI Designs help you accelerate your time to
market.
Powering the AM335x with the TPS65217x A reference for connectivity between the TPS65217 power
management IC and the AM335x processor.
Powering the AM335x With the TPS650250 Details a power solution for the AM335x application
processor with a TPS650250 Power Management Unit (PMU) or Power Management IC
(PMIC).
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Selection and Solution Guides
Connected Sensors Building Automation Systems Guide The use of connected sensors has a wide
range of uses in building automation applications, from monitoring human safety and
security, controlling the environment and ambience specified by the comfort preferences of
the end user, or either periodic or continuous data logging of environmental and system data
to detect irregular system conditions.
White Papers
Building Automation for Enhanced Energy And Operational Efficiency Discusses building automation
solutions, focusing on aspects of the Building Control System. TI’s Sitara processors
facilitate intelligent automation of the control systems. The scalable Sitara processor portfolio
offers an opportunity to build a platform solution that also spans beyond Building Control
Systems.
POWERLINK on TI Sitara Processors Supports Ethernet standard features such as cross-traffic, hot-
plugging and different types of network configurations such as star, ring and mixed
topologies.
EtherNet/IP on TI's Sitara AM335x Processors EtherNet/IP™ (EtherNet/Industrial Protocol) is an
industrial automation networking protocol based on the IEEE 802.3 Ethernet standard that
has dominated the world of IT networking for the past three decades.
PROFINET on TI’s Sitara AM335x Processors To integrate PROFINET into the Sitara AM335x
processor, TI has built upon its programmable realtime unit (PRU) technology to create an
industrial communication sub-system (ICSS).
Profibus on AM335x and AM1810 Sitara ARM Microprocessor PROFIBUS, one of the most used
communication technologies, is installed in more than 35 million industrial nodes worldwide
and is growing at a rate of approximately 10 percent each year.
EtherCAT on Sitara AM335x ARM Cortex-A8 Microprocessors Emerging real-time industrial Ethernet
standard for industrial automation applications, such as input/output (I/O) devices, sensors
and programmable logic controllers (PLCs).
Mainline Linux Ensures Stability and Innovation Enabling and empowering the rapid development of
new functionality starts at the foundational level of the system’s software environment – that
is, at the level of the Linux kernel – and builds upward from there.
Complete Solutions for Next-Generation Wireless Connected Audio Robust, feature-rich and high-
performance connectivity technology for Wi-Fi and Bluetooth.
Data Concentrators: The Core of Energy and Data Management With a large install base, it is
essential to establish an automated metering infrastructure (AMI). With automated meter
reading (AMR) measurement, the communication of meter data to the central billing station
will be seamless.
Linaro Speeds Development in TI Linux SDKs Linaro’s software is not a Linux distribution; in fact, it is
distribution neutral. The focus of the organization’s 120 engineers is on optimizing base-level
open-source software in areas that interact directly with the silicon such as multimedia,
graphics, power management, the Linux kernel and booting processes.
Getting Started on TI ARM Embedded Processor Development Beginning with an overview of ARM
technology and available processor platforms, this paper will then explore the fundamentals
of embedded design that influence a system’s architecture and, consequently, impact
processor selection.
Power Optimization Techniques for Energy-Efficient Systems The TI Sitara processor solutions offer
the flexibility to design application-specific systems. The latest Sitara AM335x processors
provide a scalable architecture with speed ranging from 300 MHz to 1 GHz.
The Yocto Project: Changing the Way Embedded Linux Software Solutions are Developed Enabling
complex silicon devices such as SoC with operating firmware and application software can
be a challenge for equipment manufacturers who often are more comfortable with hardware
than software issues.
Smart Thermostats are a Cool Addition to the Connected Home Because of the pervasiveness of
residential broadband connectivity and the explosion in options, the key to the connected
home is – connectivity.
BeagleBone Low-Cost Development Board Provides a Clear Path to Open-source Resources
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
Ready-to-use open-source hardware platform for rapid prototyping and firmware and
software development.
Enable Security and Amp Up Chip Performance With Hardware-Accelerated Cryptography
Cryptography is one of several techniques or methodologies that are typically implemented
in contemporary electronic systems to construct a secure perimeter around a device where
information or digital content is being protected.
Gesture Recognition: Enabling Natural Interactions With Electronics Enabling humans and machines
to interface more easily in the home, the automobile, and at work.
Developing Android Applications for ARM Cortex-A8 Cores The flexibility, power, versatility and
ubiquity of the Android operating system (OS) and associated ecosystem have been a boon
to developers of applications for ARM processor cores.
Other Documents
Industrial Communication with Sitara AM335x ARM Cortex-A8 Microprocessors The industry’s first
low- power ARM Cortex-A8 devices to incorporate multiple industrial communication
protocols on a single chip. The six pin-to-pin and software-compatible devices in this
generation of processors, along with industrial hardware development tools, software and
analog complements, provide a total industrial system solution.
Sitara Processors Using the ARM Cortex-A series of cores, are optimized system solutions that go
beyond the core, delivering products that support rich graphics capabilities, LCD displays
and multiple industrial protocols.
Industrial Communication with Sitara AM335x ARM Cortex-A8 Microprocessors Describes the key
features and benefits of multiple, on-chip, production-ready industrial Ethernet and field bus
communication protocols with master and slave functionality.
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8.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表 8-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
AM3359
AM3358
AM3357
AM3356
AM3354
AM3352
AM3351
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
242
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ZHCS488K –OCTOBER 2011–REVISED DECEMBER 2018
8.6 商标
Sitara, SmartReflex, WiLink, E2E are trademarks of Texas Instruments.
NEON is a trademark of ARM Ltd or its subsidiaries.
ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries.
Bluetooth is a registered trademark of Bluetooth SIG.
EtherCAT is a registered trademark of EtherCAT Technology Group.
PowerVR SGX is a trademark of Imagination Technologies Limited.
Linux is a registered trademark of Linus Torvalds.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
All other trademarks are the property of their respective owners.
8.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
9.1 Via Channel
The ZCE package has been specially engineered with Via Channel technology. This allows larger than
normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design with the 0.65-
mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two signal layers
(four layers total) due to the increased layer efficiency of the Via Channel BGA technology.
Via Channel technology implemented on the ZCE package makes it possible to build an AM335x-based
product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals. Therefore,
system performance using a 4-layer PCB design must be evaluated during product design.
9.2 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
244
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM3351BZCE30
AM3351BZCE30R
AM3351BZCE60
AM3351BZCE60R
AM3351BZCEA30
AM3351BZCEA30R
AM3351BZCEA60
AM3352BZCE30
AM3352BZCE30R
AM3352BZCE60
AM3352BZCEA30
AM3352BZCEA30R
AM3352BZCEA60
AM3352BZCEA60R
AM3352BZCED30
AM3352BZCED60
AM3352BZCZ100
AM3352BZCZ30
AM3352BZCZ60
AM3352BZCZ80
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCE
ZCZ
ZCZ
ZCZ
ZCZ
298
298
298
298
298
298
298
298
298
298
298
298
298
298
298
298
324
324
324
324
160
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 90
0 to 90
AM3351BZCE30
1000 RoHS & Green
160 RoHS & Green
1000 RoHS & Green
160 RoHS & Green
1000 RoHS & Green
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Call TI
AM3351BZCE30
AM3351BZCE60
AM3351BZCE60
AM3351BZCEA30
AM3351BZCEA30
AM3351BZCEA60
AM3352BZCE30
AM3352BZCE30
AM3352BZCE60
AM3352BZCEA30
AM3352BZCEA30
AM3352BZCEA60
AM3352BZCEA60
AM3352BZCED30
AM3352BZCED60
AM3352BZCZ100
AM3352BZCZ30
AM3352BZCZ60
AM3352BZCZ80
0 to 90
0 to 90
-40 to 105
-40 to 105
-40 to 105
0 to 90
160
160
RoHS & Green
RoHS & Green
1000 RoHS & Green
SNAGCU
SNAGCU
SNAGCU
Call TI
160
160
RoHS & Green
RoHS & Green
0 to 90
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 90
-40 to 90
0 to 90
1000 RoHS & Green
160 RoHS & Green
1000 RoHS & Green
SNAGCU
Call TI
160
160
126
126
126
126
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
0 to 90
0 to 90
0 to 90
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM3352BZCZA100
AM3352BZCZA30
AM3352BZCZA60
AM3352BZCZA80
AM3352BZCZD30
AM3352BZCZD60
AM3352BZCZD80
AM3352BZCZT60
AM3352BZCZT60R
AM3354BZCE60
AM3354BZCEA60
AM3354BZCED60
AM3354BZCZ100
AM3354BZCZ30
AM3354BZCZ60
AM3354BZCZ80
AM3354BZCZA100
AM3354BZCZA60
AM3354BZCZA80
AM3354BZCZA80R
AM3354BZCZD60
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCE
ZCE
ZCE
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
324
324
324
324
324
324
324
324
324
298
298
298
324
324
324
324
324
324
324
324
324
126
126
126
126
126
126
126
126
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 90
-40 to 90
-40 to 90
-40 to 125
-40 to 125
0 to 90
AM3352BZCZA100
AM3352BZCZA30
AM3352BZCZA60
AM3352BZCZA80
AM3352BZCZD30
AM3352BZCZD60
AM3352BZCZD80
AM3352BZCZT60
AM3352BZCZT60
AM3354BZCE60
AM3354BZCEA60
AM3354BZCED60
AM3354BZCZ100
AM3354BZCZ30
AM3354BZCZ60
AM3354BZCZ80
AM3354BZCZA100
AM3354BZCZA60
AM3354BZCZA80
AM3354BZCZA80
AM3354BZCZD60
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
1000 RoHS & Green
160
160
160
126
126
126
126
126
126
126
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
-40 to 105
-40 to 90
0 to 90
0 to 90
0 to 90
0 to 90
-40 to 105
-40 to 105
-40 to 105
1000 RoHS & Green
126
RoHS & Green
-40 to 90
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM3354BZCZD80
AM3356BZCEA60
AM3356BZCZ30
AM3356BZCZ60
AM3356BZCZ80
AM3356BZCZA30
AM3356BZCZA60
AM3356BZCZA80
AM3356BZCZD30
AM3356BZCZD60
AM3357BZCZA30
AM3357BZCZA60
AM3357BZCZA80
AM3357BZCZD30
AM3357BZCZD60
AM3358BZCE60
AM3358BZCZ100
AM3358BZCZ60
AM3358BZCZ80
AM3358BZCZA100
AM3358BZCZA80
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
ZCZ
ZCE
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCE
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
324
298
324
324
324
324
324
324
324
324
324
324
324
324
324
298
324
324
324
324
324
126
160
126
126
126
126
126
126
126
126
126
126
126
126
126
160
126
126
126
126
126
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 90
AM3354BZCZD80
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
AM3356BZCEA60
AM3356BZCZ30
AM3356BZCZ60
AM3356BZCZ80
AM3356BZCZA30
AM3356BZCZA60
AM3356BZCZA80
AM3356BZCZD30
AM3356BZCZD60
AM3357BZCZA30
AM3357BZCZA60
AM3357BZCZA80
AM3357BZCZD30
AM3357BZCZD60
AM3358BZCE60
AM3358BZCZ100
AM3358BZCZ60
AM3358BZCZ80
AM3358BZCZA100
AM3358BZCZA80
0 to 90
0 to 90
0 to 90
-40 to 105
-40 to 105
-40 to 105
-40 to 90
-40 to 90
-40 to 105
-40 to 105
-40 to 105
-40 to 90
-40 to 90
0 to 90
0 to 90
0 to 90
0 to 90
-40 to 105
-40 to 105
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM3359BZCZA80
ACTIVE
NFBGA
ZCZ
324
126
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
AM3359BZCZA80
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AM3358 :
Enhanced Product : AM3358-EP
•
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM3352BZCE30R
NFBGA
ZCE
298
1000
330.0
24.4
13.3
13.3
2.35
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZCE 298
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
AM3352BZCE30R
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AM3352BZCZ100
AM3352BZCZ30
AM3352BZCZ60
AM3352BZCZ80
AM3352BZCZA100
AM3352BZCZA30
AM3352BZCZA60
AM3352BZCZA80
AM3352BZCZD30
AM3352BZCZD60
AM3352BZCZD80
AM3352BZCZT60
AM3354BZCZ100
AM3354BZCZ30
AM3354BZCZ60
AM3354BZCZ80
AM3354BZCZA100
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
Device
Package Package Pins SPQ Unit array
Max
L (mm)
W
K0
P1
CL
CW
Name
Type
matrix temperature
(°C)
(mm) (µm) (mm) (mm) (mm)
AM3354BZCZA60
AM3354BZCZA80
AM3354BZCZD60
AM3354BZCZD80
AM3356BZCZ30
AM3356BZCZ60
AM3356BZCZ80
AM3356BZCZA30
AM3356BZCZA60
AM3356BZCZA80
AM3356BZCZD30
AM3356BZCZD60
AM3357BZCZA30
AM3357BZCZA60
AM3357BZCZA80
AM3357BZCZD30
AM3357BZCZD60
AM3358BZCZ100
AM3358BZCZ60
AM3358BZCZ80
AM3358BZCZA100
AM3358BZCZA80
AM3359BZCZA80
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
ZCZ
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
324
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
126
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
7 X 18
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
315 135.9 7620 17.2
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
11.3 16.35
Pack Materials-Page 4
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
ZCZ0324A
PLASTIC BALL GRID ARRAY
A
15.1
14.9
B
BALL A1 CORNER
15.1
14.9
1.4 MAX
C
SEATING PLANE
BALL TYP
0.45
0.35
0.12 C
13.6 TYP
V
U
T
R
P
N
M
L
SYMM
K
J
13.6
TYP
H
G
F
0.55
0.45
324X Ø
0.15
0.05
C
C
A B
E
D
C
B
(0.7) TYP
A
0.8 TYP
1
2
3
4
5
6
7
8
9
10 11 12 13
18
14 15 16 17
(0.7) TYP
SYMM
0.8 TYP
4226659/A 03/2021
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZCZ0324A
SYMM
(0.8) TYP
324X (Ø 0.4)
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
18
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED
METAL UNDER
SOLDER MASK
METAL
(Ø 0.40)
SOLDER MASK
OPENING
(Ø 0.40)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4226659/A 03/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
ZCZ0324A
SYMM
(0.8) TYP
324X (Ø 0.4)
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 8X
4226659/A 03/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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