AM3894_技术文档

AM3894

AM3892

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

AM389x Sitara

ARM Microprocessors (MPUs)

Check for Samples: AM3894, AM3892

1 Device Summary

1.1 Features

1234567891011

• High-Performance Sitara™ ARM^®

Microprocessors (MPUs)

•

One 16/24/30-Bit and One 16-bit Channel

– Simultaneous SD and HD Analog Output

– Digital HDMI 1.3 transmitter with HDCP up to

165-MHz pixel clock

– Advanced Video Processing Features Such

as Scan/Format/Rate Conversion

– ARM^®Cortex™-A8 RISC MPU

•

Up to 1.5 GHz

• ARM^®Cortex™-A8 Core

– ARMv7 Architecture

– Three Graphics Layers and Compositors

• Dual 32-bit DDR2/3 SDRAM Interfaces

– Supports up to DDR2-800 and DDR3-1600

– Up to Eight x8 Devices Total

•

In-Order, Dual-Issue, Superscalar

Microprocessor Core

NEON™ Multimedia Architecture

•

– Supports Integer and Floating Point

(VFPv3-IEEE754 compliant)

– 2 GB Total Address Space

– Dynamic Memory Manager (DMM)

•

Jazelle^®RCT Execution Environment

• ARM^®Cortex™-A8 Memory Architecture

– 32K-Byte Instruction and Data Caches

– 256K-Byte L2 Cache

•

Programmable Multi-Zone Memory

Mapping and Interleaving

•

Enables Efficient 2D Block Accesses

Supports Tiled Objects in 0°, 90°, 180°, or

270 Orientation and Mirroring

– 64K-Byte RAM, 48K-Byte Boot ROM

• 512K-Bytes On-Chip Memory Controller

(OCMC) RAM

• SGX530 3D Graphics Engine (available only on

the AM3894 device)

•

Optimizes Interlaced Accesses

• One PCI Express^®(PCIe^®) 2.0 Port With

Integrated PHY

– Single Port With 1 or 2 Lanes at 5.0 GT/s

– Configurable as Root Complex or Endpoint

• Serial ATA (SATA) 3.0 Gbps Controller With

Integrated PHYs

– Delivers up to 30 MTriangles/s

– Universal Scalable Shader Engine

– Direct3D^®Mobile, OpenGL^®ES 1.1 and 2.0,

OpenVG™ 1.0, OpenMax™ API Support

– Direct Interface for Two Hard Disk Drives

– Hardware-Assisted Native Command

Queuing (NCQ) from up to 32 Entries

– Supports Port Multiplier and

Command-Based Switching

– Advanced Geometry DMA Driven Operation

– Programmable HQ Image Anti-Aliasing

• Endianness

– ARM Instructions/Data – Little Endian

• HD Video Processing Subsystem (HDVPSS)

– Two 165 MHz HD Video Capture Channels

• Two 10/100/1000 Mbps Ethernet MACs (EMAC)

– IEEE 802.3 Compliant (3.3V I/O Only)

– MII and GMII Media Independent I/Fs

– Management Data I/O (MDIO) Module

• Dual USB 2.0 Ports With Integrated PHYs

•

One 16/24-bit and One 16-bit Channel

Each Channel Splittable Into Dual 8-bit

Capture Channels

– Two 165 MHz HD Video Display Channels

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Sitara, SmartReflex, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.

Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.

ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.

USSE, POWERVR are trademarks of Imagination Technologies Limited.

2

3

4

5

6

7

8

9

OpenVG, OpenMax are trademarks of Khronos Group Inc.

Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.

I²C BUS is a registered trademark of NXP B.V. Corporation Netherlands.

PCI Express, PCIe are registered trademarks of PCI-SIG.

10OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries.

11All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative

or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right

to change or discontinue these products without notice.

AM3894

AM3892

SPRS681A–OCTOBER 2010–REVISED MARCH 2011

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– USB 2.0 High-/Full-Speed Client

– USB 2.0 High-/Full-/Low-Speed Host

– Supports End Points 0-15

– Two Dual-Serializer Transmit/Receive Ports

– DIT-Capable For S/PDIF (All Ports)

• Multichannel Buffered Serial Port (McBSP)

– Transmit/Receive Clocks up to 48 MHz

– Two Clock Zones and Two Serial Data Pins

– Supports TDM, I2S, and Similar Formats

• Real-Time Clock (RTC)

• General Purpose Memory Controller (GPMC)

– 8-/16-bit Multiplexed Address/Data Bus

– Up to 6 Chip Selects With up to 256M-Byte

Address Space per Chip Select Pin

– Glueless Interface to NOR Flash, NAND

Flash (With BCH and Hamming Error Code

Detection), SRAM and Pseudo-SRAM

– Error Locator Module (ELM) Outside of

GPMC to Provide Up to 16-Bit/512-Bytes

Hardware ECC for NAND

– One-Time or Periodic Interrupt Generation

• Up to 64 General-Purpose I/O (GPIO) Pins

• On-Chip ARM^®ROM Bootloader (RBL)

• Power, Reset, and Clock Management

– SmartReflex™ Technology (Level 2)

– Seven Independent Core Power Domains

– Clock Enable/Disable Control For

Subsystems and Peripherals

• IEEE-1149.1 (JTAG) and IEEE-1149.7 (cJTAG)

Compatible

– Flexible Asynchronous Protocol Control for

Interface to FPGA, CPLD, ASICs, etc.

• Enhanced Direct-Memory-Access (EDMA)

Controller

– Four Transfer Controllers

• 1031-Pin Pb-Free BGA Package (CYG Suffix),

0.65-mm Ball Pitch

• Via Channel™ Technology Enables use of

0.8-mm Design Rules

– 64/8 Independent DMA/QDMA Channels

• Seven 32-bit General-Purpose Timers

• One System Watchdog Timer

• Three Configurable UART/IrDA/CIR Modules

– UART0 With Modem Control Signals

– Supports up to 3.6864 Mbps UART

– SIR, MIR, FIR (4.0 MBAUD), and CIR

• 40-nm CMOS Technology

• 3.3-V Single-Ended LVCMOS I/Os (except for

DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN

at 1.8 V)

• One 40-MHz Serial Peripheral Interface (SPI)

With Four Chip-Selects

• Applications

– Single-Board Computing

– Network and Communications Processing

– Industrial Automation

– Human Machine Interface

– Interactive Point-of-Service Kiosks

• SD/SDIO serial interface (1-/4-Bit)

• Dual Inter-Integrated Circuit ( I²C BUS^®) Ports

• Three Multichannel Audio Serial Ports

– One Six-Serializer Transmit/Receive Port

2

Device Summary

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1.2 Description

The AM389x Sitara™ ARM^®MPUs are a highly-integrated, programmable platform that leverages TI's

Sitara™ technology to meet the processing needs of the following applications: Single-Board Computing,

Network and Communications Processing, Industrial Automation, Human Machine Interface, and

Interactive Point-of-Service Kiosks.

The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, and high processing performance through the maximum flexibility of

a fully integrated mixed processor solution. The device combines high-performance ARM^®processing with

a highly-integrated peripheral set.

The ARM^®Cortex™-A8 32-bit RISC microprocessor with NEON™ floating-point extension includes: 32K

bytes (KB) of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections in this document and

the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem

(HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up

to two Gigabit Ethernet MACs (10/100/1000 Mbps) with GMII and MDIO interface; two USB ports with

integrated 2.0 PHY; PCIe^®port x2 lanes GEN2 compliant interface, which allows the device to act as a

PCIe^®root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two

dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port;

three UARTs with IrDA and CIR support; SPI serial interface; SD/SDIO serial interface; two I2C

master/slave interfaces; up to 64 General-Purpose I/O (GPIO); seven 32-bit timers; system watchdog

timer; dual DDR2/3 SDRAM interface; flexible 8/16-bit asynchronous memory interface; and up to two

SATA interfaces for external storage on two disk drives, or more with the use of a port multiplier.

The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to

off-load many video and imaging processing tasks from the core. Additionally, it has a complete set of

development tools for the ARM which include C compilers and a Microsoft ^®Windows^®debugger interface

for visibility into source code execution.

The device package has been specially engineered with Via Channel™ technology. This technology

allows 0.8-mm pitch PCB feature sizes to be used in this 0.65-mm pitch package, and substantially

reduces PCB costs. It also allows PCB routing in only two signal layers due to the increased layer

efficiency of the Via Channel™ BGA technology.

Device Summary

3

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

HD Video Processing

Subsystem (HDVPSS)

ARM Subsystem

Cortex™-A8

CPU

NEON

FPU

Video Capture

32KB

Display Processing

I-Cache

D-Cache

HD OSD

HD VENC

HD DACs

SD OSD

SD VENC

SD DACs

256KB L2 Cache

Boot ROM

48KB

RAM

64KB

ICECrusher™

Software

HDMI Xmt

System Interconnect

Peripherals

Serial Interfaces

System Control

Program/Data Storage

Connectivity

DMA

Real-Time

Clock

DDR3

32-bit

(2)

EMAC

GMII/MII

(2)

PRCM

JTAG

GPMC

and

ELM

McASP

(3)

McBSP

EDMA

MDIO

GP Timer

(7)

I2C

(2)

USB 2.0

Ctrl/PHY

(2)

SPI

SATA

3 Gbps

(2)

PCIe 2.0

(One Port,

x2 Lanes)

SD/SDIO

Watchdog

Timer

UART

(3)

A. SGX530 is available only on the AM3894 device.

Figure 1-1. AM389x Functional Block Diagram

4

Device Summary

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1

Device Summary ........................................ 1

7.2 Reset .............................................. 126

7.3 Clocking ........................................... 131

7.4 Interrupts .......................................... 141

Peripheral Information and Timings ............. 149

8.1 Parameter Information ............................ 149

1.1 Features .............................................. 1

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 4

8

Revision History .............................................. 6

2

8.2

Recommended Clock and Control Signal Transition

Device Overview ........................................ 8

2.1 Device Comparison .................................. 8

2.2 Device Characteristics ............................... 9

2.3 ARM Subsystem .................................... 10

Behavior ........................................... 150

8.3 DDR2/3 Memory Controller ....................... 151

8.4 Emulation Features and Capability ............... 184

8.5

Enhanced Direct Memory Access (EDMA)

Controller .......................................... 188

2.4 Media Controller .................................... 12

2.5 Inter-Processor Communication .................... 12

8.6

8.7

8.8

Ethernet Media Access Controller (EMAC) ....... 194

General-Purpose Input/Output (GPIO) ............ 203

2.6

Power, Reset and Clock Management (PRCM)

General-Purpose Memory Controller (GPMC) and

Module .............................................. 13

Error Locator Module (ELM) ...................... 206

2.7 SGX530 (AM3894 only) ............................ 18

2.8 Memory Map Summary ............................. 19

Device Pins ............................................. 28

3.1 Pin Assignments .................................... 28

3.2 Terminal Functions ................................. 44

Device Configurations .............................. 102

4.1 Control Module .................................... 102

4.2 Debugging Considerations ........................ 105

4.3 Boot Sequence .................................... 106

4.4 Pin Multiplexing Control ........................... 107

8.9

High-Definition Multimedia Interface (HDMI) ...... 227

8.10 High-Definition Video Processing Subsystem

(HDVPSS) ......................................... 236

8.11 Inter-Integrated Circuit (I2C) ...................... 244

8.12 Multichannel Audio Serial Port (McASP) .......... 248

8.13 Multichannel Buffered Serial Port (McBSP) ....... 256

8.14 Peripheral Component Interconnect Express (PCIe)

..................................................... 260

8.15 Real-Time Clock (RTC) ........................... 264

8.16 Secure Digital/Secure Digital Input Output

(SD/SDIO) ......................................... 266

8.17 Serial ATA Controller (SATA) ..................... 269

8.18 Serial Peripheral Interface (SPI) .................. 273

8.19 Timers ............................................. 280

8.20 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 283

8.21 Universal Serial Bus (USB2.0) .................... 287

Device and Documentation Support ............. 294

9.1 Device Support .................................... 294

3

4

4.5 How to Handle Unused Pins ...................... 114

System Interconnect ................................ 115

5.1 L3 Interconnect .................................... 115

5

6

5.2 L4 Interconnect .................................... 117

Device Operating Conditions ...................... 119

6.1

Absolute Maximum Ratings Over Operating Case

Temperature Range

9

(Unless Otherwise Noted) ......................... 119

9.2 Documentation Support ........................... 295

9.3 Community Resources ............................ 295

6.2 Recommended Operating Conditions ............. 120

6.3

Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating

10 Mechanical Packaging and Orderable

Temperature (Unless Otherwise Noted) .......... 122

Information ............................................ 296

10.1 Thermal Data for CYG ............................ 296

10.2 Packaging Information ............................ 296

7

Power, Reset, Clocking, and Interrupts ......... 123

7.1 Power Supplies .................................... 123

Contents

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This revision history highlights the technical changes made to the document in this revision.

AM389x Revisions

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 1.1

Features:

Modified GPMC Chip Selects feature item

Description:

Section 1.2

Section 2.5

Modified last paragraph

Added new section: Inter-Processor Communication

Moved Section 2.5.1, Mailbox Module, and Section 2.5.2, Spinlock Module, under Inter-Processor

Communication

Section 2.5.1.1

Section 2.5.2

Added new section: Mailbox Registers

Spinlock Module:

Modified number of spinlocks in last paragraph

Added new section: Spinlock Registers

L3 Memory Map:

Section 2.5.2.1

Section 2.8.1

Change Block for Address 0x47C0 0000 - 0x47FF FFFF to Reserved in Table 2-19, L3 Memory Map

Deleted L4 Firewall Peripheral section

Section 2.8.4

Section 3.2.1

Cortex™-A8 Memory Map:

Changed Region for Address 0x47C0 0000 - 0x47FF FFFF to Reserved in Table 2-23, Cortex™-A8 Memory

Map

Boot Configuration:

Modified GPMC_A[7]/GP0[15]/CS0MUX[1] and GPMC_A[6]/GP0[14]/CS0MUX[0] Signal Description in

Table 3-1

Section 3.2.11

Section 3.2.23

Section 4.1

Peripheral Component Interconnect Express (PCIe) Signals:

Modified PCIE_TXP|N0/1 and PCIE_RXP|N0/1 Signal Descriptions in Table 3-14, PCIe Terminal Functions

Supply Voltages:

Modified DVDD1P8 Signal Description in Table 3-30, Supply Terminal Functions

Control Module:

Modified Acronym and Register Name for Hex Address 0x4814 0608 and 0x4814 060C in Table 4-4, Device

Configuration Registers Summary

Section 4.4

Pin Multiplexing Control:

Modified first paragraph

Section 4.5

Section 5

Moved How to Handle Unused Pins up to this section

System Interconnect:

Modified second paragraph

Section 5.1

Section 5.2

L3 Interconnect:

Modified Figure 5-1, Interconnect Overview

Modified Table 5-1, L3 Master/Slave Connectivity

L4 Interconnect:

Modified second paragraph

Modified Figure 5-2, L4 Architecture

Modified Table 5-2, L4 Peripheral Connectivity

Device Operating Conditions:

Section 6

Added MIN and MAX columns, modified ESD parameters, added Footnote (6), modified Footnotes (7) and

(8) in Section 6.1, Absolute Maximum Ratings Over Operating Case Temperature Range

Section 7.1.4

SmartReflex:

Modified first paragraph

6

Contents

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AM389x Revisions (continued)

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 7.3

Clocking:

Modified Figure 7-4, System Clocking Overview

Interrupt Summary List:

Section 7.4.1

Section 7.4.2

Section 8.1.3

Modified Table 7-17, Interrupts By Module

Cortex™-A8 Interrupts:

Changed Interrupt Number 8 in Table 7-18, Cortex™-A8 Interrupt Controller Connections

Timing Parameters and Board Routing Analysis:

Modified second paragraph

Section 8.3.2

Added new section: DDR3 Routing Guidelines

JTAG Electrical Data/Timing:

Section 8.4.3.2

Changed DPn/EMUn to EMUx in Parameter names and descriptions in Table 8-33, Switching Characteristics

Over Recommended Operating Conditions for STM Trace

Changed DPn/EMUn to EMUx in Figure 8-43, STM Trace Timing

General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM):

Modified chip selects list item

Section 8.8

Section 8.8.1

Section 8.9.1.1

Section 8.9.1.2

Section 8.9.1.3

GPMC and ELM Peripheral Register Descriptions:

Added Table 8-53, ELM Registers

HDMI Interface Schematic:

Modified Figure 8-67, HDMI Interface High-Level Schematic

TMDS Routing:

Modified second and third paragraphs

DDC Signals:

Modified paragraph

Section 8.9.2

Section 8.10.2

Added new section: HDMI Peripheral Register Descriptions

HDVPSS Electrical Data/Timing:

Modified Figure 8-70, HDVPSS Output Timing

McASP0, McASP1, and McASP2 Peripheral Register Descriptions:

Section 8.12.2

Added PDIN (0x4803 801C/0x4803 C01C/0x4805 0100) and DIT (0x4803 8100/0x4803 C100/0x4805 0100 -

0x4803 815C/0x4803 C15C/0x4805 015C) registers to Table 8-77, McASP0/1/2 Registers

Section 8.14.1.3.2 Routing Specifications:

Modified paragraph

Section 8.15

Section 8.17.1.4

Section 8.21.1

Section 9.1.2

Real-Time Clock (RTC):

Modified second paragraph

Routing Specifications:

Modified first paragraph

USB2.0 Peripheral Register Descriptions:

Changed address 0x4740 4004 to Reserved in Table 8-115, CPPI DMA Queue Manager Registers

Device Nomenclature:

Modified section

Added Figure 9-1, Device Nomenclature

Contents

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2 Device Overview

2.1 Device Comparison

There are variations in the availability of some functions of the AM389x devices. A comparison of the

devices, highlighting the differences, is shown in Table 2-1. For more detailed information on the

significant device features, see Section 2.2, Device Characteristics.

Table 2-1. Device Comparison

DEVICES

FEATURES

AM3894

AM3892

SGX530

Y

N

8

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2.2 Device Characteristics

Table 2-2 provides an overview of the significant features of the AM389x devices, including the capacity of

on-chip RAM, peripherals, and the package type with pin count.

Table 2-2. Characteristics of the Processor

HARDWARE FEATURES

AM3894/AM3892

1 16-/24-bit HD Capture Channel or

2 8-bit SD Capture Channels

and

1 16-bit HD Capture Channel or

2 8-bit SD Capture Channels

and

HD Video Processing Subsystem (HDVPSS)

1 16-/24-/32-bit HD Display Channel

and

1 16-bit HD Display Channel

and

3 HD and 4 SD Video DACs

and

1 HDMI 1.3 Transmitter

DDR2/3 Memory Controller

GPMC and ELM

2 (32-bit Bus Widths)

Asynchronous (8-/16-bit bus width) RAM, NOR,

NAND

64 Independent Channels

8 QDMA Channels

EDMA

10/100/1000 Ethernet MAC with Management Data

Input/Output (MDIO)

Peripherals

Up to 2 (with MII/GMII Interface)

Not all peripherals pins are

available at the same time (for

more detail, see Section 4,

Device Configurations).

2 (Supports High- and Full-Speed as a Device and

High-, Full-, and Low-Speed as a Host)

USB 2.0

PCI Express 2.0

1 Port (2 5.0GT/s lanes)

7 (32-bit General purpose)

and

Timers

UART

1 (Watchdog)

3 (with SIR, MIR, CIR support and RTS/CTS flow

control)

(UART0 Supports Modem Interface)

SPI

1 (Supports 4 slave devices)

1 (1-bit or 4-bit)

SD/SDIO

I2C

2 (Master/Slave)

3 (6/2/2 Serializers, Each with Transmit/Receive and

DIT capability)

McASP

McBSP

1 (2 Data Pins, Transmit/Receive)

Serial ATA (SATA)

RTC

Supports 2 Interfaces

1

GPIO

Up to 64 pins

ARM

32KB I-cache

32KB D-cache

256KB L2 Cache

64KB RAM

On-Chip Memory

Organization

48KB Boot ROM

MEDIA CONTROLLER

32KB Shared L1 Cache

256KB L2 RAM

ADDITIONAL SHARED MEMORY

512KB On-chip RAM

CPU ID + CPU Rev ID

JTAG BSDL_ID

Control Status Register (CSR.[31:16])

0x1003

JTAGID Register

MHz

0x0B81 E02F

Up to 1.5 GHz

CPU Frequency

Device Overview

9

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Table 2-2. Characteristics of the Processor (continued)

HARDWARE FEATURES

AM3894/AM3892

Cycle Time

Voltage

ns

0.67 ns

Core Logic (V)

USB Logic (V)

RAM (V)

I/O (V)

1.0 V with Required AVS Capability

0.9 V

1.0 V

1.5 V, 1.8 V, 3.3 V

1031-Pin BGA (CYG)

0.04 µm

Package

25 x 25 mm

µm

Process Technology

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽¹⁾

PP

(1) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

2.3 ARM Subsystem

The ARM subsystem is designed to give the ARM Cortex-A8 master control of the device. In general, the

ARM Cortex-A8 is responsible for configuration and control of the various subsystem, peripherals, and

external memories.

The ARM subsystem includes the following features:

•

ARM Cortex-A8 RISC processor:

–

ARMv7 ISA plus Thumb^®-2, Jazelle-X, and media extensions

NEON floating-point unit

Enhanced memory management unit (MMU)

Little Endian

32KB L1 instruction cache

32KB L1 data cache

256KB L2 cache

•

Foresight embedded trace module (ETM)

ARM Cortex-A8 interrupt controller (AINTC)

64KB internal RAM

48KB internal public ROM.

L3

DMM

System Events

128

DEVOSC

SYSCLK2

64

64 128

Arbiter

128

32

64

ARM Cortex™-A8

ARM Cortex-A8

Interrupt Controller

(AINTC)

128

32KB L1I$ 32KB L1D$

256KB L2$

48KB ROM

64KB RAM

Trace

ETM

NEON

64

Debug

ICECrusher

Figure 2-1. ARM Cortex-A8 Subsystem Block Diagram

10

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2.3.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor

is a member of ARM Cortex family of general-purpose microprocessors. This processor is targeted at

multi-tasking applications where full memory management, high performance, low die size, and low power

are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic

to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture

and provides a complete high-performance subsystem, including:

•

ARM Cortex-A8 integer core

Superscalar ARMv7 instruction set

Thumb-2 instruction set

Jazelle RCT acceleration

CP14 debug coprocessor

CP15 system control coprocessor

NEON 64-/128-bit hybrid SIMD engine for multimedia

Enhanced memory management unit (MMU)

Separate level-1 instruction and data caches

Integrated level-2 cache

128-bit interconnect to system memories and peripherals

Embedded trace module (ETM).

2.3.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an

embedded trace module (ETM). The ETM consists of two parts:

•

The Trace port provides real-time trace capability for the ARM Cortex-A8.

Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB

has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace

data.

For more details on the ETB, see Section 8.4.2.

2.3.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests

from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more

details on the AINTC, see Section 7.4.

2.3.4 System Interconnect

The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a

DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR

memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device

modules.

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2.4 Media Controller

The Media Controller has the responsibility of managing the HDVPSS module.

2.5 Inter-Processor Communication

This device is a multi-core device that requires software to efficiently manage and communicate between

the cores. The following are the main features that need to be implemented by such software:

1. Device management of the slave processors from the host processor.

2. Inter-processor communication between the cores for transfer and exchange of information between

them.

For implementing efficient inter-processor communication between the multiple cores on the device, the

following hardware features are provided:

•

Mailbox interrupts

Hardware spinlocks

Mailboxes provide a mechanism for one processor to write a value to a register and send an interrupt to

another processor. Spinlocks facilitate access to shared resources in the system.

2.5.1 Mailbox Module

The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media

Controller. It consists of twelve mailboxes, each supporting communication between two of the above

processors. The sender sends information to the receiver by writing a message to the mailbox registers.

Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender

about an overflow situation.

The Mailbox module supports the following features (see Figure 2-2):

•

12 mailboxes

Four-message FIFO depth for each message queue

32-bit message width

Message reception and queue-not-full notification using interrupts

Three interrupts (one to ARM Cortex-A8, two to Media Controller).

Mailbox Module

Mailbox

L4

Interconnect

Interrupt

ARM Cortex-A8

Media Controller

Figure 2-2. Mailbox Module Block Diagram

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2.5.1.1 Mailbox Registers

Table 2-3 lists the Mailboxes available on this device. The register set below is applicable to these

mailboxes. Table 2-4 lists the Mailbox registers.

Table 2-3. Mailboxes

MAILBOX TYPE

USER NUMBER (u)

MAILBOX NUMBER (m)

MESSAGES PER MAILBOX

System Mailbox

0 to 3

0 to 11

4

Table 2-4. Mailbox Registers Summary⁽¹⁾

HEX ADDRESS

ACRONYM

REGISTER NAME

0x480C 8000

MAILBOX_REVISION

Mailbox Revision

0x480C 8010

MAILBOX_SYSCONFIG

MAILBOX_MESSAGE_m

MAILBOX_FIFOSTATUS_m

MAILBOX_MSGSTATUS_m

Mailbox System Configuration

Mailbox Message

0x480C 8040 + (0x4 * m)

0x480C 8080 + (0x4 * m)

0x480C 80C0 + (0x4 * m)

0x480C 8100 + (0x10 * u)

0x480C 8104 + (0x10 * u)

0x480C 8108 + (0x10 * u)

0x480C 810C + (0x10 * u)

0x480C 8140

Mailbox FIFO Status

Mailbox Message Status

MAILBOX_IRQSTATUS_RAW_u Mailbox IRQ RAW Status

MAILBOX_IRQSTATUS_CLR_u Mailbox IRQ Clear Status

MAILBOX_IRQENABLE_SET_u Mailbox IRQ Enable Set

MAILBOX_IRQENABLE_CLR_u Mailbox IRQ Enable Clear

-

Reserved

(1) For the range of m and u, see Table 2-3.

2.5.2 Spinlock Module

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple

processors in the device:

•

ARM Cortex-A8 processor

Media Controller processors.

The Spinlock module implements 64 spinlocks (or hardware semaphores) that provide an efficient way to

perform a lock operation of a device resource using a single read-access, avoiding the need for a

read-modify-write bus transfer of which the programmable cores are not capable.

2.5.2.1 Spinlock Registers

Table 2-5. Spinlock Registers Summary⁽¹⁾

HEX ADDRESS

0x480C A000

ACRONYM

REGISTER NAME

Revision

SPINLOCK_REV

0x480C A010h

SPINLOCK_SYSCFG

SPINLOCK_SYSSTAT

SPINLOCK_LOCK_REG_i

System Configuration

System Status

Lock

0x480C A014h

0x480C A800 + (0x4*i)

(1) i = 0 to 63

2.6 Power, Reset and Clock Management (PRCM) Module

The PRCM module is the centralized management module for the power, reset, and clock control signals

of the device. It interfaces with all the components on the device for power, clock, and reset management

through power-control signals. It integrates enhanced features to allow the device to adapt energy

consumption dynamically, according to changing application and performance requirements. The

innovative hardware architecture allows a substantial reduction in leakage current.

The PRCM module is composed of two main entities:

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•

Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock

source control (oscillator)

Clock manager (CM): Handles the clock generation, distribution, and management.

Table 2-6 lists the physical addresses of the PRM and CM modules. Table 2-7 through Table 2-18 provide

register mapping summaries of the PRM and CM registers.

For more details on the PRCM, see Section 7 of this data sheet, Power, Reset, Clocking and Interrupts,

and the PRCM chapter of the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual

(literature number SPRUGX7).

Table 2-6. PRCM Register Address Summary

ADDRESS OFFSET

0x0000

MODULE NAME

PRM_DEVICE

CM_DEVICE

CM_DPLL

SIZE

SEE

256 Bytes

1 KBytes

Table 2-7

Table 2-8

Table 2-10

Table 2-11

Table 2-12

Table 2-13

Table 2-14

Table 2-15

Table 2-16

Table 2-17

Table 2-18

0x0100

0x0300

0x0400

CM_ACTIVE

CM_DEFAULT

CM_SGX

0x0500

0x0900

0x0A00

PRM_ACTIVE

PRM_DEFAULT

PRM_SGX

0x0B00

0x0F00

0x1400

CM_ALWON

PRM_ALWON

0x1800

Table 2-7. PRM_DEVICE Register Summary

HEX ADDRESS

0x4818 00A0

0x4818 00A4

0x4818 00A8

ACRONYM

PRM_RSTCTRL

PRM_RSTTIME

PRM_RSTST

REGISTER NAME

Global software cold and warm reset control

Reset duration control

Global reset sources log

Table 2-8. CM_DEVICE Register Summary

HEX ADDRESS

ACRONYM

REGISTER NAME

0x4818 0100

CM_CLKOUT_CTRL

SYS_CCCLKOUT output control

Table 2-9. OCP_SOCKET_PRM Register Summary

HEX ADDRESS

ACRONYM

REGISTER NAME

0x4818 0200

REVISION_PRM

PRCM IP revision code

Table 2-10. CM_DPLL Register Summary

HEX ADDRESS

0x4818 0300

0x4818 0304

0x4818 0308

0x4818 030C

0x4818 0310

0x4818 0314

0x4818 0318

0x4818 0324

0x4818 032C

ACRONYM

REGISTER NAME

CM_SYSCLK1_CLKSEL

CM_SYSCLK2_CLKSEL

CM_SYSCLK3_CLKSEL

CM_SYSCLK4_CLKSEL

CM_SYSCLK5_CLKSEL

CM_SYSCLK6_CLKSEL

CM_SYSCLK7_CLKSEL

CM_SYSCLK10_CLKSEL

CM_SYSCLK11_CLKSEL

SYSCLK1 clock divider value select

SYSCLK2 clock divider value select

SYSCLK3 clock divider value select

SYSCLK4 clock divider value select

SYSCLK5 clock divider value select

SYSCLK6 clock divider value select

SYSCLK7 clock divider value select

SYSCLK10 clock divider value select

SYSCLK11 clock divider value select

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Table 2-10. CM_DPLL Register Summary (continued)

HEX ADDRESS

ACRONYM

CM_SYSCLK13_CLKSEL

CM_SYSCLK15_CLKSEL

CM_VPB3_CLKSEL

REGISTER NAME

0x4818 0334

0x4818 0338

0x4818 0340

0x4818 0344

0x4818 0348

0x4818 034C

0x4818 0350

0x4818 0354

0x4818 0358

0x4818 035C

0x4818 0370

0x4818 0374

0x4818 0378

0x4818 037C

0x4818 0380

0x4818 0384

0x4818 0388

0x4818 0390

0x4818 0394

0x4818 0398

0x4818 039C

0x4818 03A0

0x4818 03A4

0x4818 03A8

0x4818 03B0

0x4818 03B4

SYSCLK13 clock divider value select

SYSCLK15 clock divider value select

Video PLL B3 clock divider value select

Video PLL C1 clock divider value select

Video PLL D1 clock divider value select

SYSCLK19 clock divider value select

SYSCLK20 clock divider value select

SYSCLK21 clock divider value select

SYSCLK22 clock divider value select

Audio PLL A clock divider value select

SYSCLK14 clock mux select line

SYSCLK16 clock mux select line

SYSCLK18 clock mux select line

McASP0 audio clock mux select line

McASP1 audio clock mux select line

McASP2 audio clock mux select line

McBSP audio clock mux select line

Timer1 clock mux select line

CM_VPC1_CLKSEL

CM_VPD1_CLKSEL

CM_SYSCLK19_CLKSEL

CM_SYSCLK20_CLKSEL

CM_SYSCLK21_CLKSEL

CM_SYSCLK22_CLKSEL

CM_APA_CLKSEL

CM_SYSCLK14_CLKSEL

CM_SYSCLK16_CLKSEL

CM_SYSCLK18_CLKSEL

CM_AUDIOCLK_MCASP0_CLKSEL

CM_AUDIOCLK_MCASP1_CLKSEL

CM_AUDIOCLK_MCASP2_CLKSEL

CM_AUDIOCLK_MCBSP_CLKSEL

CM_TIMER1_CLKSEL

CM_TIMER2_CLKSEL

Timer2 clock mux select line

CM_TIMER3_CLKSEL

Timer3 clock mux select line

CM_TIMER4_CLKSEL

Timer4 clock mux select line

CM_TIMER5_CLKSEL

Timer5 clock mux select line

CM_TIMER6_CLKSEL

Timer6 clock mux select line

CM_TIMER7_CLKSEL

Timer7 clock mux select line

CM_SYSCLK23_CLKSEL

CM_SYSCLK24_CLKSEL

SYSCLK23 clock divider value select

SYSCLK24 clock divider value select

Table 2-11. CM_ACTIVE Register Summary

HEX ADDRESS

0x4818 0404

0x4818 0408

0x4818 0424

0x4818 0428

ACRONYM

REGISTER NAME

CM_HDDSS_CLKSTCTRL

CM_HDMI_CLKSTCTRL

HDVPSS clock domain power state transition

HDMI clock domain power state transition

CM_ACTIVE_HDDSS_CLKCTRL HDVPSS clock management control

CM_ACTIVE_HDMI_CLKCTRL HDMI clock management control

Table 2-12. CM_DEFAULT Register Summary

HEX ADDRESS

0x4818 0504

0x4818 0508

0x4818 0510

0x4818 0514

0x4818 0520

0x4818 0524

0x4818 0528

0x4818 052C

0x4818 0558

0x4818 0560

0x4818 0578

ACRONYM

REGISTER NAME

CM_DEFAULT_L3_MED_CLKSTCTRL L3 clock domain power state transition

CM_DEFAULT_L3_FAST_CLKSTCTRL L3 clock domain power state transition

CM_DEFAULT_PCI_CLKSTCTRL

PCI clock domain power state transition

CM_DEFAULT_L3_SLOW_CLKSTCTRL L3 clock domain power state transition

CM_DEFAULT_EMIF_0_CLKCTRL

CM_DEFAULT_EMIF_1_CLKCTRL

CM_DEFAULT_DMM_CLKCTRL

CM_DEFAULT_FW_CLKCTRL

CM_DEFAULT_USB_CLKCTRL

CM_DEFAULT_SATA_CLKCTRL

CM_DEFAULT_PCI_CLKCTRL

EMIF0 clock management control

EMIF1 clock management control

DMM clock management control

EMIF FW clock management control

USB clock management control

SATA clock management control

PCI clock management control

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Table 2-13. CM_SGX Register Summary

HEX ADDRESS

0x4818 0900

0x4818 0920

ACRONYM

REGISTER NAME

CM_SGX_CLKSTCTRL

CM_SGX_SGX_CLKCTRL

SGX530 clock domain power state transition

SGX530 clock management control

Table 2-14. PRM_ACTIVE Register Summary

HEX ADDRESS

0x4818 0A00

0x4818 0A04

0x4818 0A10

0x4818 0A14

ACRONYM

REGISTER NAME

PM_ACTIVE_PWRSTCTRL

PM_ACTIVE_PWRSTST

RM_ACTIVE_RSTCTRL

RM_ACTIVE_RSTST

Active power state control

Active power domain state status

Active domain reset control release

Active domain reset source log

Table 2-15. PRM_DEFAULT Register Summary

HEX ADDRESS

0x4818 0B00

0x4818 0B04

0x4818 0B10

0x4818 0B14

ACRONYM

REGISTER NAME

PM_DEFAULT_PWRSTCTRL

PM_DEFAULT_PWRSTST

RM_DEFAULT_RSTCTRL

RM_DEFAULT_RSTST

Default power state

Default power domain state 0 status

Default subsystem reset control release

Default domain reset source log

Table 2-16. PRM_SGX Register Summary

HEX ADDRESS

0x4818 0F00

0x4818 0F04

0x4818 0F10

0x4818 0F14

ACRONYM

REGISTER NAME

PM_SGX_PWRSTCTRL

RM_SGX_RSTCTRL

PM_SGX_PWRSTST

RM_SGX_RSTST

SGX530 power state control

SGX530 domain reset control release

SGX530 power domain state status

SGX530 domain reset source log

Table 2-17. CM_ALWON Register Summary

HEX ADDRESS

0x4818 1400

0x4818 1404

0x4818 1408

0x4818 1414

0x4818 1418

0x4818 141C

0x4818 1420

0x4818 1424

0x4818 1428

0x4818 142C

0x4818 1430

0x4818 1540

0x4818 1544

0x4818 1548

0x4818 154C

0x4818 1550

0x4818 1554

0x4818 1558

0x4818 155C

0x4818 1560

ACRONYM

REGISTER NAME

CM_ALWON_L3_SLOW_CLKSTCTRL L3 clock domain power state transition

CM_ETHERNET_CLKSTCTRL

CM_ALWON_L3_MED_CLKSTCTRL

CM_ALWON_OCMC_0_CLKSTCTRL

CM_ALWON_OCMC_1_CLKSTCTRL

CM_ALWON_MPU_CLKSTCTRL

CM_ALWON_SYSCLK4_CLKSTCTRL

CM_ALWON_SYSCLK5_CLKSTCTRL

CM_ALWON_SYSCLK6_CLKSTCTRL

CM_ALWON_RTC_CLKSTCTRL

CM_ALWON_L3_FAST_CLKSTCTRL

CM_ALWON_MCASP0_CLKCTRL

CM_ALWON_MCASP1_CLKCTRL

CM_ALWON_MCASP2_CLKCTRL

CM_ALWON_MCBSP_CLKCTRL

CM_ALWON_UART_0_CLKCTRL

CM_ALWON_UART_1_CLKCTRL

CM_ALWON_UART_2_CLKCTRL

CM_ALWON_GPIO_0_CLKCTRL

CM_ALWON_GPIO_1_CLKCTRL

EMAC clock domain power state transition

L3 clock domain power state transition

OCMC 0 clock domain power state transition

OCMC 1 clock domain power state transition

MPU clock domain power state transition

SYSCLK4 clock domain power state transition

SYSCLK5 clock domain power state transition

SYSCLK6 clock domain power state transition

RTC clock domain power state transition

L3 clock domain power state transition

McASP 0 clock management control

McASP 1 clock management control

McASP 2 clock management control

McBSP clock management control

UART 0 clock management control

UART 1 clock management control

UART 2 clock management control

GPIO 0 clock management control

GPIO 1 clock management control

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Table 2-17. CM_ALWON Register Summary (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

0x4818 1564

0x4818 1568

0x4818 1570

0x4818 1574

0x4818 1578

0x4818 157C

0x4818 1580

0x4818 1584

0x4818 1588

0x4818 158C

0x4818 1590

0x4818 1594

0x4818 1598

0x4818 15B0

0x4818 15B4

0x4818 15B8

0x4818 15C4

0x4818 15D0

0x4818 15D4

0x4818 15D8

0x4818 15DC

0x4818 15E0

0x4818 15E4

0x4818 15E8

0x4818 15EC

0x4818 15F0

0x4818 15F4

0x4818 15F8

0x4818 15FC

0x4818 1600

0x4818 1604

0x4818 1608

0x4818 160C

0x4818 1628

CM_ALWON_I2C_0_CLKCTRL

CM_ALWON_I2C_1_CLKCTRL

CM_ALWON_TIMER_1_CLKCTRL

CM_ALWON_TIMER_2_CLKCTRL

CM_ALWON_TIMER_3_CLKCTRL

CM_ALWON_TIMER_4_CLKCTRL

CM_ALWON_TIMER_5_CLKCTRL

CM_ALWON_TIMER_6_CLKCTRL

CM_ALWON_TIMER_7_CLKCTRL

CM_ALWON_WDTIMER_CLKCTRL

CM_ALWON_SPI_CLKCTRL

I2C 0 clock management control

I2C 1 clock management control

Timer1 clock management control

Timer2 clock management control

Timer3 clock management control

Timer4 clock management control

Timer5 clock management control

Timer6 clock management control

Timer7 clock management control

WDTIMER clock management control

SPI clock management control

CM_ALWON_MAILBOX_CLKCTRL

CM_ALWON_SPINBOX_CLKCTRL

CM_ALWON_SDIO_CLKCTRL

CM_ALWON_OCMC_0_CLKCTRL

CM_ALWON_OCMC_1_CLKCTRL

CM_ALWON_CONTROL_CLKCTRL

CM_ALWON_GPMC_CLKCTRL

MAILBOX clock management control

SPINBOX clock management control

SDIO clock management control

OCMC 0 clock management control

OCMC 1 clock management control

Control clock management control

GPMC clock management control

CM_ALWON_ETHERNET_0_CLKCTRL Ethernet 0 clock management control

CM_ALWON_ETHERNET_1_CLKCTRL Ethernet 1 clock management control

CM_ALWON_MPU_CLKCTRL

CM_ALWON_DEBUGSS_CLKCTRL

CM_ALWON_L3_CLKCTRL

MPU clock management control

Debug clock management control

L3 clock management control

CM_ALWON_L4HS_CLKCTRL

CM_ALWON_L4LS_CLKCTRL

CM_ALWON_RTC_CLKCTRL

CM_ALWON_TPCC_CLKCTRL

CM_ALWON_TPTC0_CLKCTRL

CM_ALWON_TPTC1_CLKCTRL

CM_ALWON_TPTC2_CLKCTRL

CM_ALWON_TPTC3_CLKCTRL

CM_ALWON_SR_0_CLKCTRL

CM_ALWON_SR_1_CLKCTRL

L4HS clock management control

L4LS clock management control

RTC clock management control

TPCC clock management control

TPTC0 clock management control

TPTC1 clock management control

TPTC2 clock management control

TPTC3 clock management control

SmartReflex 0 clock management control

SmartReflex 1 clock management control

CM_ALWON_CUST_EFUSE_CLKCTRL Customer e-Fuse clock management control

Table 2-18. PRM_ALWON Register Summary

HEX ADDRESS

0x4818 1810

0x4818 1814

ACRONYM

REGISTER NAME

RM_ALWON_RSTCTRL

RM_ALWON_RSTST

ALWAYS ON domain resets control

ALWAYS ON reset sources

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2.7 SGX530 (AM3894 only)

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications.

The SGX530 graphics accelerator efficiently processes a number of various multimedia data types

concurrently:

•

Pixel data

Vertex data

Video data.

This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning

enabling zero overhead task switching.

The SGX530 has the following major features:

•

Vector graphics and 3D graphics.

Tile-based architecture.

Universal Scalable Shader Engine ( USSE™) - multi-threaded engine incorporating pixel and vertex

shader functionality.

•

Advanced shader feature set - in excess of Microsoft^®VS3.0, PS3.0, and OpenGL 2.0.

Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1.

Fine-grained task switching, load balancing, and power management.

Advanced geometry direct memory access (DMA) driven operation for minimum CPU interaction.

Programmable high-quality image anti-aliasing.

POWERVR™ SGX core MMU for address translation from the core virtual address to the external

physical address (up to 4GB address range).

•

Fully-virtualized memory addressing for OS operation in a unified memory architecture.

Advanced and standard 2D operations [e.g., vector graphics, block level transfers (BLTs), raster

operations (ROPs)].

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2.8 Memory Map Summary

The device has multiple on-chip memories associated with its processors and various subsystems. To

help simplify software development a unified memory map is used where possible to maintain a consistent

view of device resources across all bus masters.

The device system memory mapping is broken into four 1-GB quadrants for target address spaces

allocation. The four quadrants are labeled Q0, Q1, Q2 and Q3 for a total of 4-GB 32-bit address space.

(HDVPSS includes a thirty-third address bit for an additional 4GB of address range; this is for virtual

addressing and not physical memory addressing.) Inside each quadrant, system targets are mapped on

4-MB boundary (except EDMA targets which are decreased to 1-MB regions).

2.8.1 L3 Memory Map

The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure.

The NoC uses an internal packet-based protocol for forward (read command, write command with data

payload) and backward (read response with data payload, write response) transactions. All exposed

interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference

standard.

Table 2-19 shows the general device level-3 (L3) memory map. The table represents the physical

addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM)

may re-map these targets to different virtual addresses through an internal or external MMU. Processors

without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all

masters have access to all L3 regions, but only those with defined connectivity, as shown in Table 5-1.

For a list of the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 5.2.

The L3 interconnect returns an address-hole error if any initiator attempts to access a target to which it

has no connection.

Table 2-19. L3 Memory Map

START ADDRESS

(HEX)

END ADDRESS

(HEX)

QUAD

BLOCK NAME

SIZE

DESCRIPTION

Q0

Q1

GPMC

PCIe Gen2

Reserved

L3 OCMC0

Reserved

L3 OCMC1

Reserved

L3 CFG Regs

Reserved

McASP0

0x0000 0000

0x2000 0000

0x3000 0000

0x4000 0000

0x4030 0000

0x4034 0000

0x4040 0000

0x4044 0000

0x4050 0000

0x4080 0000

0x4084 0000

0x40E0 0000

0x40E0 8000

0x40F0 0000

0x40F0 8000

0x4100 0000

0x4200 0000

0x4400 0000

0x44C0 0000

0x4600 0000

0x4640 0000

0x4680 0000

0x1FFF FFFF

0x2FFF FFFF

0x3FFF FFFF

0x402F FFFF

0x4033 FFFF

0x403F FFFF

0x4043 FFFF

0x404F FFFF

0x407F FFFF

0x4083 FFFF

0x40DF FFFF

0x40E0 7FFF

0x40EF FFFF

0x40F0 7FFF

0x40FF FFFF

0x41FF FFFF

0x43FF FFFF

0x44BF FFFF

0x45FF FFFF

0x463F FFFF

0x467F FFFF

0x46BF FFFF

512MB GPMC

256MB PCIe Gen2 Targets

256MB Reserved

3MB

Reserved

256KB OCMC SRAM

768KB Reserved (OCMC RAM0)

256KB OCMC SRAM

768KB Reserved (OCMC RAM1)

3MB

Reserved

256KB Reserved

5888KB Reserved

32KB

992KB Reserved

32KB Reserved

992KB Reserved

Reserved

16MB

32MB

12MB

20MB

4MB

Reserved

L3 configuration registers

Reserved

McASP0

McASP1

4MB

McASP1

McASP2

4MB

McASP2

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Table 2-19. L3 Memory Map (continued)

START ADDRESS

(HEX)

END ADDRESS

(HEX)

QUAD

BLOCK NAME

SIZE

DESCRIPTION

Q1

HDMI 1.3 Tx

McBSP

0x46C0 0000

0x4700 0000

0x4740 0000

0x4780 0000

0x47C0 0000

0x4800 0000

0x46FF FFFF

0x473F FFFF

0x477F FFFF

0x47BF FFFF

0x47FF FFFF

0x48FF FFFF

4MB

16MB

HDMI 1.3 Tx

McBSP

USB2.0

USB2.0 Registers / CPPI

Reserved

L4 Standard domain

Standard Peripheral domain (see

Table 2-20)

Q1

EDMA TPCC

Reserved

0x4900 0000

0x4910 0000

0x4980 0000

0x4990 0000

0x49A0 0000

0x49B0 0000

0x49C0 0000

0x4A00 0000

0x490F FFFF

0x497F FFFF

0x498F FFFF

0x499F FFFF

0x49AF FFFF

0x49BF FFFF

0x49FF FFFF

0x4AFF FFFF

1MB

7MB

1MB

4MB

16MB

EDMA TPCC Registers

Reserved

EDMA TPTC0

EDMA TPTC1

EDMA TPTC2

EDMA TPTC3

Reserved

EDMA TPTC0 Registers

EDMA TPTC1 Registers

EDMA TPTC2 Registers

EDMA TPTC3 Registers

Reserved

L4 High-Speed

Domain

High-Speed Peripheral domain (see

Table 2-21)

Q1

Instrumentation

0x4B00 0000

0x4C00 0000

0x4BFF FFFF

0x4CFF FFFF

16MB

EMU Subsystem region

Configuration registers

DDR EMIF0

registers⁽¹⁾

Q1

DDR EMIF1

registers⁽¹⁾

0x4D00 0000

0x4E00 0000

0x4DFF FFFF

0x4FFF FFFF

16MB

32MB

Configuration registers

DDR DMM

Registers⁽¹⁾

Q1

GPMC Registers

PCIe Gen2 Registers

Reserved

0x5000 0000

0x5100 0000

0x5200 0000

0x5500 0000

0x5600 0000

0x50FF FFFF

0x51FF FFFF

0x54FF FFFF

0x55FF FFFF

0x56FF FFFF

16MB

48MB

16MB

Configuration registers

Reserved

SGX530

SGX530 Slave Port

AM3894 only)

Q1

Reserved

0x5600 0000

0x56FF FFFF

16MB

Reserved

(AM3892 only)

Q1

Q

Reserved

Tiler

0x5700 0000

0x5800 0000

0x5C00 0000

0x5E00 0000

0x6000 0000

0x8000 0000

0x57FF FFFF

0x5BFF FFFF

0x5DFF FFFF

0x5FFF FFFF

0x7FFF FFFF

0xBFFF FFFF

16MB

64MB

32MB

Reserved

512MB Virtual Tiled Address Space

DDR EMIF0/1

1GB

4GB

DDR

(2)

SDRAM

Q3

DDR EMIF0/1

SDRAM⁽²⁾

0xC000 0000

0xFFFF FFFF

DDR

Q4-7

DDR DMM

0x1 0000 0000

0x1 FFFF FFFF

DDR DMM Tiler Extended address map –

Virtual Views (HDVPSS only)

(1) These accesses occur through the DDR DMM Tiler Ports. The DMM will split address ranges internally to address DDR EMIF and DDR

DMM control registers.

(2) DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM. See the

DDR DMM documentation for more details.

20

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2.8.2 L4 Memory Map

2.8.2.1 L4 Standard Peripheral

The L4 standard peripheral bus accesses standard peripherals and IP configuration registers. The

memory map is shown in Table 2-20.

Table 2-20. L4 Standard Peripheral Memory Map

START ADDRESS

DEVICE NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

L4 Standard

Configuration

0x4800 0000

0x4800 0800

0x4800 1000

0x4800 1400

0x4800 1800

0x4800 2000

0x4800 8000

0x4800 9000

0x4800 A000

0x4801 2000

0x4802 0000

0x4802 1000

0x4802 2000

0x4802 3000

0x4802 4000

0x4802 5000

0x4802 6000

0x4802 8000

0x4802 9000

0x4802 A000

0x4802 B000

0x4802 C000

0x4802 E000

0x4802 F000

0x4803 0000

0x4803 1000

0x4803 2000

0x4803 3000

0x4803 4000

0x4803 8000

0x4803 A000

0x4803 B000

0x4803 C000

0x4803 E000

0x4803 F000

0x4804 0000

0x4804 1000

0x4804 2000

0x4804 3000

0x4804 4000

0x4804 5000

0x4800 07FF

0x4800 0FFF

0x4800 13FF

0x4800 17FF

0x4800 1FFF

0x4800 7FFF

0x4800 8FFF

0x4800 9FFF

0x4800 FFFF

0x4801 FFFF

0x4802 0FFF

0x4802 1FFF

0x4802 2FFF

0x4802 3FFF

0x4802 4FFF

0x4802 5FFF

0x4802 7FFF

0x4802 8FFF

0x4802 9FFF

0x4802 AFFF

0x4802 BFFF

0x4802 DFFF

0x4802 EFFF

0x4802 FFFF

0x4803 0FFF

0x4803 1FFF

0x4803 2FFF

0x4803 3FFF

0x4803 7FFF

0x4803 9FFF

0x4803 AFFF

0x4803 BFFF

0x4803 DFFF

0x4803 EFFF

0x4803 FFFF

0x4804 0FFF

0x4804 1FFF

0x4804 2FFF

0x4804 3FFF

0x4804 4FFF

0x4804 5FFF

2KB

1KB

2KB

24KB

4KB

24KB

56KB

4KB

8KB

4KB

8KB

4KB

16KB

8KB

4KB

8KB

4KB

Address/Protection (AP)

Link Agent (LA)

Initiator Port (IP0)

Initiator Port (IP1)

Reserved (IP2 – IP3)

Reserved

e-Fuse Controller

Peripheral Registers

Support Registers

Reserved

UART0

Reserved

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

UART1

UART2

Reserved

I2C0

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

I2C1

Reserved

TIMER1

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

SPIOCP

GPIO0

Reserved

McASP0 CFG

Peripheral Registers

Support Registers

Reserved

McASP1 CFG

Peripheral Registers

Support Registers

Reserved

TIMER2

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

TIMER3

TIMER4

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Table 2-20. L4 Standard Peripheral Memory Map (continued)

START ADDRESS

(HEX)

DEVICE NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

TIMER5

0x4804 6000

0x4804 7000

0x4804 8000

0x4804 9000

0x4804 A000

0x4804 B000

0x4804 C000

0x4804 D000

0x4804 E000

0x4805 0000

0x4805 2000

0x4805 3000

0x4806 0000

0x4807 0000

0x4807 1000

0x4808 0000

0x4809 0000

0x4809 1000

0x480C 0000

0x480C 1000

0x480C 2000

0x480C 3000

0x480C 4000

0x480C 8000

0x480C 9000

0x480C A000

0x480C B000

0x480C C000

0x4810 0000

0x4812 0000

0x4812 1000

0x4812 2000

0x4812 3000

0x4812 4000

0x4814 0000

0x4816 0000

0x4816 1000

0x4818 0000

0x4818 3000

0x4818 4000

0x4818 8000

0x4818 9000

0x4818 A000

0x4818 B000

0x4818 C000

0x4818 D000

0x4804 6FFF

0x4804 7FFF

0x4804 8FFF

0x4804 9FFF

0x4804 AFFF

0x4804 BFFF

0x4804 CFFF

0x4804 DFFF

0x4804 FFFF

0x4805 1FFF

0x4805 2FFF

0x4805 FFFF

0x4806 FFFF

0x4807 0FFF

0x4807 FFFF

0x4808 FFFF

0x4809 0FFF

0x480B FFFF

0x480C 0FFF

0x480C 1FFF

0x480C 2FFF

0x480C 3FFF

0x480C 7FFF

0x480C 8FFF

0x480C 9FFF

0x480C AFFF

0x480C BFFF

0x480F FFFF

0x4811 FFFF

0x4812 0FFF

0x4812 1FFF

0x4812 2FFF

0x4812 3FFF

0x4813 FFFF

0x4815 FFFF

0x4816 0FFF

0x4817 FFFF

0x4818 2FFF

0x4818 3FFF

0x4818 7FFF

0x4818 8FFF

0x4818 9FFF

0x4818 AFFF

0x4818 BFFF

0x4818 CFFF

0x4818 DFFF

4KB

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

TIMER6

TIMER7

GPIO1

4KB

Reserved

8KB

McASP2 CFG

8KB

Peripheral Registers

Support Registers

Reserved

4KB

Reserved

SD/SDIO

52KB

64KB

4KB

Registers

Support Registers

Reserved

ELM

60KB

64KB

4KB

Error Location Module

Support Registers

Reserved

RTC

188KB

4KB

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

4KB

WDT1

4KB

Reserved

Mailbox

16KB

4KB

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

4KB

Spinlock

4KB

Reserved

HDVPSS

208KB

128KB

4KB

Peripheral Registers

Support Registers

Reserved

4KB

HDMI 1.3 Tx

4KB

Peripheral Registers

Support Registers

Reserved

4KB

Reserved

112KB

128KB

4KB

Control Module

Peripheral Registers

Support Registers

Reserved

PRCM

124KB

12KB

4KB

Peripheral Registers

Support Registers

Reserved

16KB

4KB

SmartReflex0

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

4KB

SmartReflex1

4KB

OCP Watchpoint

4KB

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Table 2-20. L4 Standard Peripheral Memory Map (continued)

START ADDRESS

(HEX)

DEVICE NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

Reserved

0x4818 E000

0x4818 F000

0x4819 0000

0x4819 1000

0x4819 2000

0x4819 3000

0x4819 4000

0x4819 5000

0x4819 6000

0x4819 7000

0x4819 8000

0x4819 9000

0x4819 A000

0x4819 B000

0x4819 C000

0x4820 0000

0x4820 1000

0x4824 0000

0x4818 EFFF

0x4818 FFFF

0x4819 0FFF

0x4819 1FFF

0x4819 2FFF

0x4819 3FFF

0x4819 4FFF

0x4819 5FFF

0x4819 6FFF

0x4819 7FFF

0x4819 8FFF

0x4819 9FFF

0x4819 AFFF

0x4819 BFFF

0x481F FFFF

0x4820 0FFF

0x4823 FFFF

0x4824 0FFF

4KB

400KB

4KB

252KB

4KB

Reserved

DDR0 Phy Ctrl Regs

DDR1 Phy Ctrl Regs

Peripheral Registers

Support Registers

Peripheral Registers

Support Registers

Reserved

Interrupt controller⁽¹⁾

Reserved⁽¹⁾

Cortex™-A8 Accessible Only

MPUSS config

register⁽¹⁾

Reserved⁽¹⁾

Reserved

0x4824 1000

0x4828 1000

0x4830 0000

0x4827 FFFF

0x482F FFFF

0x48FF FFFF

252KB

508KB

13MB

Cortex™-A8 Accessible Only

Reserved

(1) These regions (highlighted in yellow) are decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4

standard. They are included here only for reference when considering the Cortex™-A8 memory map. For masters other than the

Cortex™-A8, these regions are reserved.

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2.8.2.2 L4 High-Speed Peripheral

The L4 high-speed peripheral bus accesses the IP configuration registers of high-speed peripherals in L3.

The memory map is shown in Table 2-21.

Table 2-21. L4 High-Speed Peripheral Memory Map

START ADDRESS

DEVICE NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

L4 High Speed

configuration

0x4A00 0000

0x4A00 0800

0x4A00 1000

0x4A00 1400

0x4A00 1800

0x4A00 2000

0x4A08_0000

0x4A0A 1000

0x4A10 0000

0x4A10 4000

0x4A10 5000

0x4A12 0000

0x4A12 4000

0x4A12 5000

0x4A14 0000

0x4A15 0000

0x4A15 1000

0x4A18 0000

0x4A1A 0000

0x4A1A 1000

0x4A00 07FF

0x4A00 0FFF

0x4A00 13FF

0x4A00 17FF

0x4A00 1FFF

0x4A07 FFFF

0x4A0A_0FFF

0x4A0F FFFF

0x4A10 3FFF

0x4A10 4FFF

0x4A11 FFFF

0x4A12 3FFF

0x4A12 4FFF

0x4A13 FFFF

0x4A14 FFFF

0x4A15 0FFF

0x4A17 FFFF

0x4A19 FFFF

0x4A1A 0FFF

0x4AFF FFFF

2KB

Address/Protection (AP)

Link Agent (LA)

Initiator Port (IP0)

Initiator Port (IP1)

Reserved (IP2 – IP3)

Reserved

1KB

2KB

Reserved

EMAC0

504KB

132KB

380KB

16KB

4KB

Reserved

Peripheral Registers

Support Registers

Reserved

EMAC1

108KB

16KB

4KB

Peripheral Registers

Support Registers

Reserved

SATA

108KB

64KB

4KB

Peripheral Registers

Support Registers

Reserved

188KB

128KB

4KB

Reserved

14716KB Reserved

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2.8.3 TILER Extended Addressing Map

The Tiling and Isometric Lightweight Engines for Rotation (TILER) ports are mainly used for optimized 2-D

block accesses. The TILER also supports rotation of the image buffer at 0º, 90º, 180º, and 270º, with

vertical and horizontal mirroring.

The TILER includes an additional 4-GB addressing range to access the frame buffer in these rotated and

mirrored views. This range requires a thirty-third bit of address and is only accessible to peripherals that

require access to the multiple views. On the device, this is limited to the HD Video Processing Subsystem

(HDVPSS). (Other peripherals, based on ConnID, may access any one single view through the 512-MB

TILER window region located in the base 4-GB range.)

The HDVPSS may use the virtual address space of 4GB (0x1:0000:0000 – 0x1:FFFF:FFFF) since various

VPDMA clients of the HDVPSS may need to simultaneously access multiple 2-D images with different

orientations of the image buffers.

The top 4-GB address space is divided into eight sections of 512MB each. These eight sections

correspond to the eight different orientations as shown in Table 2-22.

Table 2-22. TILER Extended Address Memory Map

START ADDRESS

BLOCK NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

Tiler View 0

Tiler View 1

Tiler View 2

Tiler View 3

Tiler View 4

Tiler View 5

Tiler View 6

Tiler View 7

0x1 0000 0000

0x1 2000 0000

0x1 4000 0000

0x1 6000 0000

0x1 8000 0000

0x1 A000 0000

0x1 C000 0000

0x1 E000 0000

0x1 1FFF FFFF

0x1 3FFF FFFF

0x1 5FFF FFFF

0x1 7FFF FFFF

0x1 9FFF FFFF

0x1 BFFF FFFF

0x1 DFFF FFFF

0x1 FFFF FFFF

512MB

Natural 0° View

0° with Vertical Mirror View

0° with Horizontal Mirror View

180° View

90° with Vertical Mirror View

270° View

90° View

90° with Horizontal Mirror View

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2.8.4 Cortex™-A8 Memory Map

The Cortex™-A8 includes an memory management unit (MMU) to translate virtual addresses to physical

addresses which are then decoded within the Host ARM Subsystem. The subsystem includes its own

ROM and RAM, as well as configuration registers for its interrupt controller and secure state machine.

These addresses are hard-coded within the subsystem. In addition, the upper 2GB of address space is

routed to a special port (Master 0) intended for low-latency access to DDR memory. All other physical

addresses are routed to the L3 port (Master 1) where they are decoded by the device infrastructure. The

Cortex™-A8 memory map is shown in Table 2-23.

Table 2-23. Cortex™-A8 Memory Map

START ADDRESS

REGION NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

(HEX)

Boot Space

0x0000 0000

0x2000 0000

0x3000 0000

0x4000 0000

0x4002 0000

0x4002 C000

0x4010 0000

0x4020 0000

0x402F 0000

0x4030 0000

0x4034 0000

0x4040 0000

0x4044 0000

0x4050 0000

0x4080 0000

0x4084 0000

0x40E0 0000

0x40E0 8000

0x40F0 0000

0x40F0 8000

0x4100 0000

0x4200 0000

0x4400 0000

0x44C0 0000

0x4600 0000

0x4640 0000

0x4680 0000

0x46C0 0000

0x4700 0000

0x4740 0000

0x4780 0000

0x47C0 0000

0x4800 0000

0x4820 0000

0x000F FFFF

0x1FFF FFFF

0x2FFF FFFF

0x3FFF FFFF

0x4001 FFFF

0x4002 BFFF

0x400F FFFF

0x401F FFFF

0x402E FFFF

0x402F FFFF

0x4033 FFFF

0x403F FFFF

0x4043 FFFF

0x404F FFFF

0x407F FFFF

0x4083 FFFF

0x40DF FFFF

0x40E0 7FFF

0x40EF FFFF

0x40F0 7FFF

0x40FF FFFF

0x41FF FFFF

0x43FF FFFF

0x44BF FFFF

0x45FF FFFF

0x463F FFFF

0x467F FFFF

0x46BF FFFF

0x46FF FFFF

0x473F FFFF

0x477F FFFF

0x47BF FFFF

0x47FF FFFF

0x481F FFFF

0x4820 0FFF

1MB

512MB

256MB

128KB

48KB

Boot Space

GPMC

L3 Target Space

PCIe Gen2 Targets

Reserved

Public

ROM internal⁽¹⁾

848KB

1MB

Reserved

OCMC SRAM

Reserved

OCMC SRAM

Reserved

Reserved⁽¹⁾

960KB

64KB

Reserved

L3 Target Space

256KB

768KB

256KB

768KB

3MB

256KB

5888KB Reserved

32KB

992KB

32KB

992KB

16MB

32MB

12MB

20MB

4MB

Reserved

L3 configuration registers

Reserved

McASP0

4MB

McASP1

4MB

McASP2

4MB

HDMI 1.3 Tx

4MB

McBSP

4MB

USB2.0 Registers / CPPI

Reserved

4MB

Reserved

2MB

Standard Peripheral domain (see Table 2-20)

Cortex™-A8 Interrupt Controller

ARM Subsystem

INTC⁽¹⁾

4KB

Reserved⁽¹⁾

0x4820 1000

0x4823 FFFF

252KB

Reserved

(1) These addresses are decoded within the Cortex™-A8 subsystem.

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Table 2-23. Cortex™-A8 Memory Map (continued)

START ADDRESS

(HEX)

REGION NAME

END ADDRESS (HEX)

SIZE

DESCRIPTION

Reserved⁽¹⁾

0x4824 1000

0x4830 0000

0x4900 0000

0x4910 0000

0x4980 0000

0x4990 0000

0x49A0 0000

0x49B0 0000

0x49C0 0000

0x4A00 0000

0x4B00 0000

0x4C00 0000

0x4D00 0000

0x4E00 0000

0x5000 0000

0x5100 0000

0x5200 0000

0x5600 0000

0x4827 FFFF

0x48FF FFFF

0x490F FFFF

0x497F FFFF

0x498F FFFF

0x499F FFFF

0x49AF FFFF

0x49BF FFFF

0x49FF FFFF

0x4AFF FFFF

0x4BFF FFFF

0x4CFF FFFF

0x4DFF FFFF

0x4FFF FFFF

0x50FF FFFF

0x51FF FFFF

0x55FF FFFF

0x56FF FFFF

252KB

13MB

1MB

Reserved

L3 Target Space

Standard Peripheral domain (see Table 2-20)

EDMA TPCC Registers

7MB

Reserved

1MB

EDMA TPTC0 Registers

EDMA TPTC1 Registers

EDMA TPTC2 Registers

EDMA TPTC3 Registers

Reserved

1MB

4MB

16MB

32MB

16MB

64MB

16MB

High Speed Peripheral domain (see Table 2-21)

EMU Subsystem region

DDR EMIF0⁽²⁾Configuration registers

DDR EMIF1⁽²⁾Configuration registers

DDR DMM⁽²⁾Configuration registers

GPMC Configuration registers

PCIE Configuration registers

Reserved

SGX530 Slave Port

(AM3894 only)

0x5600 0000

0x56FF FFFF

16MB

Reserved

(AM3892 only)

0x5700 0000

0x5800 0000

0x6000 0000

0x8000 0000

0x57FF FFFF

0x5FFF FFFF

0x7FFF FFFF

0xBFFF FFFF

16MB

128MB

512MB

1GB

Reserved

TILER Window

DDR

DDR EMIF0/1

SDRAM⁽³⁾⁽⁴⁾

DDR EMIF0/1

SDRAM⁽³⁾⁽⁴⁾

0xC000 0000

0xFFFF FFFF

1GB

DDR

(2) These accesses occur through the DDR DMM TILER ports. The DDR DMM splits address ranges internally to address DDR EMIF and

DDR DMM control registers based on DDR DMM tie-offs.

(3) These addresses are routed to the Master 0 port for direct connection to the DDR DMM ELLA port.

(4) DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved, depending on configuration of the DDR DMM.

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3 Device Pins

3.1 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in

the smallest possible package. Pin multiplexing is controlled using a combination of hardware

configuration at device reset and software programmable register settings. For more information on pin

muxing, see Section 4.4, Pin Multiplexing Control.

3.1.1 Pin Map (Bottom View)

Figure 3-1 through Figure 3-15 show the bottom view of the package pin assignments in 15 sections (A,

B, C, D, E, F, G, H, I, J, K, L, M, N, and O).

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

SD_SDWP/

GPMC_A[15]/

GP1[8]

R

P

N

M

L

SPI_SCS[0]

SPI_SCLK

VSS

SPI_SCS[3]/

GPMC_A[21]/

GP1[22]

SPI_SCS[1]/

GPMC_A[23]

SPI_SCS[2]/

GPMC_A[22]

DVDD_3P3

UART0_TXD

VSS

UART0_RIN/

GPMC_A[17]/

GPMC_A[22]/

GP1[19]

UART0_DSR/

GPMC_A[19]/

GPMC_A[24]/

GP1[17]

UART0_DCD/

GPMC_A[18]/

GPMC_A[23]/

GP1[18]

UART0_DTR/

GPMC_A[20]/

GPMC_A[12]/

GP1[16]

UART1_RXD/

GPMC_A[26]/

GPMC_A[20]

UART1_TXD/

GPMC_A[25]/

GPMC_A[19]

UART0_CTS

GP1[28]

UART1_RTS/

GPMC_A[14]/

GPMC_A[18]/

GP1[25]

UART2_RXD

DVDD_3P3

VSS

UART1_CTS/

GPMC_A[13]/

GPMC_A[17]/

GP1[26]

UART2_TXD

DVDD_3P3

VSS

UART2_CTS/

GPMC_A[16]/

GPMC_A[25]/

GP1[24]

GPMC_A[22]/

GP1[10]

GPMC_A[27]/

GP1[9]

K

J

GPMC_A[15]/

GP0[22]

GPMC_A[16]/

GP0[21]

GPMC_A[24]/

GP1[15]

GPMC_A[23]/

GP1[14]

GPMC_A[26]/

GP1[11]

GPMC_A[25]/

GP1[12]

GP1[13]

TIM6_OUT/

GPMC_A[24]/

GP0[30]

GPMC_A[12]/

GP0[27]

GPMC_A[21]/

GP0[26]

GP0[25]

GPMC_A[14]/

GP0[23]

GPMC_A[13]/

GP0[24]

H

G

F

TIM7_OUT/

GPMC_A[12]/

GP0[31]

GP0[5]/

MCA[2]_AMUTEIN/

GPMC_A[24]

GP0[6]/

MCA[1]_AMUTEIN/

GPMC_A[23]

DDR[0]_D[3]

VSS

DDR[0]_D[1]

DDR[0]_D[2]

DDR[0]_D[4]

DDR[0]_DQM[0]

DDR[0]_D[5]

DDR[0]_D[6]

DDR[0]_DQS[0]

DDR[0]_D[20]

DDR[0]_D[27]

DDR[0]_D[21]

DDR[0]_D[16]

DDR[0]_DQS[2]

CLKOUT

DVDD_DDR[0]

DDR[0]_D[23]

DDR[0]_D[9]

E

D

C

B

A

DDR[0]_DQS[0]

DDR[0]_D[11]

DDR[0]_D[10]

DDR[0]_D[13]

VSS

DDR[0]_D[7]

DDR[0]_D[0]

DDR[0]_D[8]

DDR[0]_D[15]

DDR[0]_DQS[1] DDR[0]_DQM[1]

DDR[0]_D[19]

DVDD_DDR[0]

DDR[0]_D[14]

DDR[0]_D[12]

DDR[0]_VTP

DDR[0]_D[17]

DDR[0]_DQS[1]

DDR[0]_DQS[2]

VSS

1

2

3

4

5

6

7

8

Figure 3-1. Pin Map [Section A]

Device Pins

29

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

SD_SDCD/

GPMC_A[16]/

GP1[7]

R

P

N

M

L

DVDD_3P3

UART0_RXD

DVDD_3P3

SPI_D[0]

VSS

CVDDC

CVDD

SPI_D[1]

CVDDC

UART0_RTS/

GP1[27]

DDR[0]_A[8]

DDR[0]_BA[2]

DDR[0]_A[12]

UART2_RTS/

GPMC_A[15]/

GPMC_A[26]/

GP1[23]

DDR[0]_A[6]

DDR[0]_A[9]

DDR[0]_A[5]

DDR0_A[4]

DVDD_DDR[0]

VSS

DVDD_DDR[0]

VSS

K

J

DDR[0]_D[30]

DDR0_D[18]

DDR[0]_D[28]

H

G

F

VSS

DDR[0]_DQM[2]

DDR0_D[22]

DDR[0]_A[3]

DDR[0]_BA[0]

DDR[0]_WE

DDR[0]_RAS

DDR[0]_CAS

DDR[0]_A[11]

VSS

DDR[0]_D[24]

DDR[0]_DQM[3]

DDR[0]_D[31]

DDR[0]_DQS[3]

DVDD_DDR[0]

E

D

C

B

A

VSS

DDR[0]_A[2]

RSV20

DDR[0]_D[29]

DDR[0]_D[25]

DDR[0]_A[10]

DDR[0]_BA[1]

VSS

DDR[0]_D[26]

DDR[0]_CLK[0]

DDR[0]_A[13]

DDR[0]_CLK[1]

DVDD_DDR[0]

DDR[0]_A[0]

13

DDR[0]_A[7]

14

DDR[0]_CLK[1] DDR[0]_ODT[1]

DDR[0]_DQS[3]

DDR[0]_CLK[0]

12

VSS

10

9

11

15

16

Figure 3-2. Pin Map [Section B]

30

Device Pins

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

R

P

CVDD

VSS

CVDD

RSV3

CVDD

RSV4

CVDD

CVDDC

DDR[0]_A[1]

DDR[1]_A[1]

DDR[1]_A[12]

DDR[1]_BA[2]

DDR[1]_A[8]

N

M

L

DVDD_DDR[0]

VSS

DVDD_DDR[0]

VSS

DVDD_DDR[0]

DVDD_DDR[1]

VSS

DVDD_DDR[1]

VSS

DVDD_DDR[1]

VSS

DVDD_DDR[1]

VSS

DVDD_DDR[1]

VSS

DVDD_DDR[1]

K

J

H

G

F

VSS

DDR[0]_CS[1]

DDR[1]_CS[1]

VSS

DDR[0]_ODT[0] DEVOSC_DVDD18 DDR[1]_ODT[0]

E

D

C

B

A

VSS

DDR[0]_A[14]

DDR[0]_RST

DDR[0]_CKE

VDDA_PLL

DDR[1]_RST

DDR[1]_CKE

VSSA_PLL

DDR[1]_A[14]

DDR[1]_A[2]

RSV8

DEV_MXO

DDR[1]_A[10]

DDR[1]_BA[1]

VSS

DEVOSC_VSS

DDR[1]_A[13]

DDR[0]_CS[0]

DDR[1]_CS[0]

DDR[1]_CLK[1]

DEV_MXI/

DEV_CLKIN

VREFSSTL_DDR[0]

VDDA_PLL

18

VSSA_PLL

20

VREFSSTL_DDR[1] DDR[1]_ODT[1] DDR[1]_CLK[1]

DDR[1]_A[7]

24

17

19

21

22

23

Figure 3-3. Pin Map [Section C]

Device Pins

31

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

R

P

N

M

L

VDD_USB0_1P8

DVDD_3P3

VDD_USB_0P9

VSS

DVDD_3P3

RSV10

VDD_USB0_3P3 VDD_USB1_3P3

VSS

TMS

VSS

DVDD_3P3

RSV11

DVDD_3P3

RSV2

RSV19

I2C[0]_SCL

CVDDC

TDO

DDR[1]_A[6]

DDR[1]_A[9]

DDR[1]_A[5]

DDR[1]_A[4]

DDR[1]_A[3]

DDR[1]_BA[0]

DDR[1]_WE

DDR[1]_RAS

DDR[1]_CAS

DDR[1]_A[11]

GP0[1]

DVDD_3P3

GP0[2]

VSS

GP0[0]

K

J

GP1[30]/

SATA_ACT0_LED

GP0[3]/

TCLKIN

DDR[1]_D[30]

DDR[1]_D[18]

DDR[1]_D[28]

GP0[4]

VSS

H

G

F

VSS

DDR[1]_DQM[2]

DDR[1]_D[22]

DDR[1]_D[24]

DDR[1]_DQM[3]

DDR[1]_D[31]

VSS

DDR[1]_D[20]

DDR[1]_D[27]

DDR[1]_D[21]

DDR[1]_D[16]

DVDD_DDR[1]

DDR[1]_D[23]

DDR[1]_D[9]

E

D

C

B

A

DDR[1]_D[11]

DDR[1]_D[10]

DDR[1]_D[13]

DDR[1]_D[29]

DDR[1]_D[25]

DDR[1]_CLK[0]

DDR[1]_D[26]

DDR[1]_DQS[3] DDR[1]_DQS[2]

DDR[1]_D[19]

DDR[1]_A[0]

25

DVDD_DDR[1]

DDR[1]_D[17]

31

DDR[1]_VTP

32

DDR[1]_CLK[0]

26

VSS

28

27

29

30

Figure 3-4. Pin Map [Section D]

32

Device Pins

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AM3892

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

R

P

N

M

L

USB1_DRVVBUS

USB0_DRVVBUS

I2C[1]_SDA

USB1_DN

USB0_DN

VDD_USB0_VBUS

EMU3

USB1_DP

USB0_DP

USB0_R1

VSS

RSV16

RSV17

RSV18

I2C[0]_SDA

I2C[1]_SCL

EMU4

EMU2

DVDD_3P3

VSS

EMU1

K

J

VSS

TRST

RTCK

GP1[31]/

SATA_ACT1_LED

TDI

EMU0

TCLK

TIM4_OUT/

GP0[28]

TIM5_OUT/

GP0[29]

GP0[7]/

MCA[0]_AMUTEIN

WD_OUT

H

G

F

CLKIN32

RSTOUT

POR

DDR[1]_D[3]

RESET

NMI

DDR[1]_DQS[0]

DDR[1]_D[6]

DDR[1]_D[1]

DDR[1]_D[2]

DDR[1]_D[4]

E

D

C

B

A

DDR[1]_DQS[0]

VSS

DVDD_DDR[1]

DDR[1]_D[7]

DDR[1]_D[0]

DDR[1]_D[8]

DDR[1]_DQM[0]

DDR[1]_D[5]

DDR[1]_DQM[1] DDR[1]_DQS[1]

DDR[1]_D[15]

DDR[1]_D[12]

33

DDR[1]_D[14]

35

DVDD_DDR[1]

DDR[1]_DQS[1]

34

VSS

37

36

Figure 3-5. Pin Map [Section E]

Device Pins

33

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AM3892

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

VIN[0]A_D[19]/

VIN[1]A_DE/

VOUT[1]_C[9]

VIN[0]A_D[18]/

VIN[1]A_FLD/

VOUT[1]_C[8]

VOUT[1]_C[2]/

VIN1A_D[8]

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

RSV31

RSV42

RSV43

RSV45

RSV46

RSV47

VOUT[1]_Y_YC[5]/

VIN[1]A_D[3]

RSV48

RSV49

RSV50

GPMC_CS[1]

GPMC_CS[2]

GPMC_WE

GPMC_OE_RE

GPMC_CS[0]

RSV44

VSS

GPMC_CS[5]/

GPMC_A[12]

GPMC_CS[4]/

GP1[21]

VSS

GPMC_BE1

GPMC_A[4]/

GP0[12]/

BTMODE[3]

GPMC_A[5]/

GP0[13]/

BTMODE[4]

GPMC_A[3]/

GP0[11]/

BTMODE[2]

GPMC_A[2]/

GP0[10]/

BTMODE[1]

GPMC_A[1]/

GP0[9]/

BTMODE[0]

GPMC_A[0]/

GP0[8]

GPMC_DIR/

GP1[20]

GPMC_WAIT

GPMC_A[7]/

GP0[15]/

CS0MUX[1]

GPMC_A[6]/

GP0[14]/

CS0MUX[0]

GPMC_A[9]/

GP0[17]/

CS0WAIT

GPMC_A[8]/

GP0[16]/

CS0BW

GPMC_A[10]/

GP0[18]

VSS

GPMC_A[11]/

GP0[19]

GPMC_A[27]/

GP0[20]

GPMC_D[0]

VSS

GPMC_D[2]

GPMC_D[5]

GPMC_D[7]

GPMC_D[12]

GPMC_D[15]

VSS

DVDD_3P3

GPMC_D[9]

GPMC_D[11]

GPMC_D[3]

GPMC_D[4]

GPMC_D[10]

GPMC_D[14]

GPMC_D[1]

VSS

GPMC_D[8]

W

GPMC_CLK/

GP1[29]

V

VSS

SD_DAT[0]/

GPMC_A[20]/

GP1[3]

SD_CLK/

GPMC_A[13]/

GP1[1]

SD_CMD/

GPMC_A[21]/

GP1_[2]

SD_POW/

GPMC_A[14]/

GP1[0]

U

SD_DAT[1]_SDIRQ/ SD_DAT[2]_SDRW/

GPMC_A[18]/

GP1[5]

GPMC_A[19]/

GP1[4]

T

VSS

6

VSS

7

VSS

8

1

2

3

4

5

Figure 3-6. Pin Map [Section F]

34

Device Pins

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AM3892

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

VOUT[0]_R_CR[8]/

VOUT[0]_B_CB_C[0]/

VOUT[1]_Y_YC[8]

AK

AJ

VOUT[0]_B_CB_C[5]

VOUT[0]_B_CB_C[6]

VSS

VOUT[0]_R_CR[0]/

VOUT[1]_C[8]/

VOUT[1]_CLK

DVDD_3P3

VOUT[0]_B_CB_C[8]

AH

VOUT[0]_R_CR[4]/

VOUT[0]_FLD/

VOUT[1]_Y_YC[4]

AG

AF

AE

AD

AC

AB

AA

Y

GPMC_CS[3]

VSS

VOUT[0]_G_Y_YC[6] VOUT[0]_G_Y_YC[2]

VIN[0]A_D[9]

CVDD

VSS

GPMC_WP

DVDD_3P3

GPMC_ADV_ALE GPMC_BE0_CLE

CVDDC

VOUT[1]_C[7]/

VIN[1]A_D[13]

DVDD_3P3

GPMC_D[6]

DVDD_3P3

CVDDC

CVDD

VSS

CVDDC

CVDD

VSS

VOUT[1]_Y_YC[6]/

VIN[1]A_D[4]

RSV51

VSS

W

VSS

GPMC_D[13]

DVDD_3P3

V

VSS

DVDD_3P3

U

VSS

SD_DAT[3]/

GPMC_A[17]/

GP1[6]

DVDD_3P3

10

DVDD_3P3

11

T

CVDD

14

CVDD

15

CVDD

16

9

12

13

Figure 3-7. Pin Map [Section G]

Device Pins

35

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AM3892

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AK

VSSA_HD

DVDD1P8

VSSA_HD

VSS

RSV57

VSS

DVDD1P8

RSV15

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

DVDD_3P3

VIN[0]A_D[0]

VDAC_VREF

VDDA_SD_1P8 VDDA_HD_1P8

RSV56

RSV55

RSV54

VIN[0]A_D[2]

VDDA_SD_1P8 VDDA_SD_1P8 VDDA_HD_1P8

VDDA_SD_1P0 VDDA_HD_1P0

RSV53

RSV13

VDAC_RBIAS_HD

CVDD

VSS

HDMI_HPDET

CVDDC

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

RSV52

CVDD

VSS

RSV7

CVDDC

CVDD

VSS

W

VSS

V

VSS

VSSA_PLL

U

VSS

T

CVDD

17

CVDD

18

CVDD

19

CVDD

20

CVDD

21

CVDD

22

CVDD

23

CVDD

24

Figure 3-8. Pin Map [Section H]

36

Device Pins

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AM3892

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

HDMI_SDA

MCA[0]_ACLKR

MCA[1]_AXR[1]

MCA[0]_AXR[1]

VSS

MCA[0]_AHCLKR

MCA[0]_AFSX

MCA[0]_ACLKX MCA[0]_AHCLKX

VSS

RSV14

RSV12

EMAC[0]_TXD[4] MCA[0]_AFSR

VSS

DVDD_3P3

VDDT_PCIE

DVDD_3P3

PCIE_TXN1

DVDD_3P3

VDDT_PCIE

EMAC[0]_TXD[3] EMAC[0]_TXD[2] EMAC[0]_TXD[1]

CVDDC

EMAC[0]_RXD[5]

EMAC[0]_RXD[6]

EMAC[0]_COL

EMAC[0]_CRS

VDDR_PCIE

VSS

PCIE_TXN0

PCIE_TXP0

VDDT_PCIE

PCIE_TXP1

VDDT_PCIE

PCIE_RXP0

VDDT_PCIE

VSS

VDDR_PCIE

W

VDDR_SATA

PCIE_RXN0

PCIE_RXN1

PCIE_RXP1

VDDT_SATA

V

VSS

U

VDD_USB1_1P8

VDD_USB0_3P3 VDD_USB1_3P3

SATA_TXN0

31

SATA_TXP0

32

T

RSV6

27

RSV5

28

25

26

29

30

Figure 3-9. Pin Map [Section I]

Device Pins

37

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AM3892

SPRS681A–OCTOBER 2010–REVISED MARCH 2011

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AK

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

MCA[1]_AMUTE

MCA[1]_AFSX

MCA[1]_AFSR

MCA[1]_ACLKR MCA[0]_AXR[0]

MCA[0]_AXR[4]/ MCA[0]_AXR[5]/

MCA[0]_AXR[2]/ MCA[0]_AXR[3]/

MCB_FSX MCB_FSR

MCA[0]_AMUTE

MCB_DX

MCB_DR

MDIO_MDIO

MDIO_MCLK

DVDD_3P3

EMAC[0]_TXD[7] EMAC[0]_TXD[6] EMAC[0]_TXEN

EMAC[0]_TXD[5] EMAC[0]_TXCLK

EMAC[0]_TXD[0] EMAC[0]_RXER EMAC[0]_RXDV EMAC[0]_RXD[7] EMAC[0]_RXCLK

EMAC[0]_RXD[3] EMAC[0]_RXD[1] EMAC[0]_RXD[0]

VSS

EMAC[0]_GMTCLK

EMAC[0]_RXD[4] EMAC[0]_RXD[2]

SERDES_CLKN SERDES_CLKP

VSS

RSV1

VSS

VDDT_SATA

VSS

SATA_RXP1

SATA_RXN1

W

SATA_TXP1

SATA_TXN1

VDDT_SATA

SATA_RXP0

SATA_RXN0

V

U

VDD_USB1_VBUS

USB1_R1

37

T

VSS

33

VSS

34

VSS

35

36

Figure 3-10. Pin Map [Section J]

38

Device Pins

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AM3892

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

VOUT[0]_G_Y_YC[1]/

VOUT[1]_FLD/

VIN[1]B_FLD

VOUT[1]_Y_YC[2]/

VIN[1]A_D[0]

VOUT[1]_Y_YC[4]/

VIN[1]A_D[2]

VIN[0]A_D[21]/

VIN[0]B_FLD

AU

AT

DVDD_3P3

RSV24

VSS

VIN[0]A_HSYNC

VIN[0]A_D[16]/

VIN[1]A_HSYNC/

VOUT[1]_FLD

VOUT[1]_Y_YC[8]/

VIN[1]A_D[6]

VOUT[1]_CLK/

VIN[1]A_CLK

VIN[0]A_D[23]/

VIN[0]B_HSYNC

VOUT[1]_AVID/

VIN[1]B_CLK

VOUT[0]_R_CR[1]

VOUT[0]_AVID

RSV26

RSV27

VIN[0]A_DE

VIN[0]A_D[22]/

VIN[0]B_VSYNC

VOUT[1]_HSYNC/

VIN[1]A_D[15]

VOUT[1]_Y_YC[7]/

VIN[1]A_D[5]

AR

AP

VOUT[1]_Y_YC[9]/

VIN[1]A_D[7]

VOUT[1]_Y_YC[3]/

VIN[1]A_D[1]

VOUT[1]_C[5]/

VIN[1]A_D[11]

RSV23

RSV25

RSV29

RSV28

VOUT[1]_C[4]/

VIN[1]A_D[10]

VOUT[1]_C[6]/

VIN[1]A_D[12]

VIN[0]A_D[20]/

VIN[0]B_DE

DVDD_3P3

AN

AM

AL

VOUT[1]_C[3]/

VIN[1]A_D[9]

VSS

VIN[1]A_D[14]

VIN[0]A_VSYNC

VSS

VIN[0]A_D[17]/

VIN[1]A_VSYNC/

VOUT[1]_VSYNC

VIN[0]A_FLD

VSS

6

VSS

7

RSV32

1

RSV30

2

3

4

5

8

Figure 3-11. Pin Map [Section K]

Device Pins

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

VOUT[0]_R_CR[9]/

VOUT[0]_R_CR[6]/

AU VOUT[0]_B_CB_C[1]/ VOUT[0]_G_Y_YC[0]/

VOUT[0]_G_Y_YC[8]

DVDD_3P3

VIN[0]A_D[15]

VOUT[0]_CLK

VIN[0]A_CLK

VIN[0]A_D[14]

VIN[0]A_D[13]

VSS

VIN[0]A_D[12]

VIN[0]A_D[10]

VSS

VOUT[1]_Y_YC[9]

VOUT[1]_Y_YC[6]

VOUT[0]_R_CR[5]/

VOUT[0]_AVID/

VOUT[1]_Y_YC[5]

VOUT[0]_R_CR[2]/

VOUT[0]_HSYNC/ VOUT[0]_B_CB_C[9] VOUT[0]_G_Y_YC[7]

VOUT[1]_Y_YC[2]

VOUT[0]_B_CB_C[1]/

VOUT[1]_HSYNC/

VOUT[1]_AVID

AT

AR

AP

VOUT[0]_R_CR[3]/

VOUT[0]_VSYNC/

VOUT[1]_Y_YC[3]

VOUT[0]_B_CB_C[0]/

VOUT[1]_C[9]/

VIN[1]B_HSYNC_DE

VOUT[0]_G_Y_YC[9]

VOUT[0]_G_Y_YC[0]/

VOUT[1]_VSYNC/

VIN[1]B_VSYNC

VOUT[0]_B_CB_C[2] VOUT[0]_G_Y_YC[3]

VSS

VOUT[0]_B_CB_C[4]

VSS

DVDD_3P3

AN VOUT[0]_VSYNC

VSS

VOUT[0]_HSYNC

VOUT[0]_B_CB_C[7] VOUT[0]_G_Y_YC[5]

VOUT[0]_B_CB_C[3] VOUT[0]_G_Y_YC[4]

AM

AL

VSS

VOUT[0]_R_CR[7]/

VOUT[0]_G_Y_YC[1]/

VOUT[1]_Y_YC[7]

VOUT[0]_FLD

VSS

15

VSS

16

9

10

11

12

13

14

Figure 3-12. Pin Map [Section L]

40

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AU

AT

HDMI_TMDSCLKN

HDMI_TMDSCLKP

VIN[0]A_D[11]

VIN[0]A_D[5]

VIN[0]A_D[7]

VIN[0]A_D[8]

VIN[0]A_D[1]

VIN[0]A_D[4]

VIN[0]A_D[3]

VIN[0]A_D[6]

RSV21

VSSA_SD

VSSA_REF_1P8

VDDA_REF_1P8

IOUTG

IOUTF

IOUTD

RSV41

IOUTA

IOUTB

IOUTC

RSV61

RSV60

VSS

IOUTE

VIN[0]B_CLK

VDAC_RBIAS_SD

AR

AP

AN

AM

AL

VSS

VDDA_HDMI

VSSA_SD

RSV22

VSS

RSV59

VSS

VSSA_SD

20

VSSA_HD

21

VSS

17

VSS

18

VSS

19

RSV58

22

VSS

23

VSS

24

Figure 3-13. Pin Map [Section M]

Device Pins

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AU

HDMI_TMDSDN0 HDMI_TMDSDN1 HDMI_TMDSDN2

VSS

DVDD_3P3

RSV39

EMAC[1]_TXEN EMAC[1]_TXD[4] EMAC[1]_TXD[3]

EMAC[1]_TXCLK EMAC[1]_TXD[5] EMAC[1]_TXD[2]

AT HDMI_TMDSDP0 HDMI_TMDSDP1 HDMI_TMDSDP2

RSV40

VDDA_HDMI

AR

AP

AN

AM

AL

VSS

EMAC[1]_COL

EMAC[1]_TXD[1]

RSV38

RSV37

HDMI_CEC

HDMI_EXTSWING

EMAC[1]_TXD[6] EMAC[1]_TXD[0] EMAC1_RXD[7]

EMAC[1]_RXER EMAC[1]_CRS

DVDD_3P3

RSV36

RSV33

EMAC[1]_TXD[7]

VSS

HDMI_SCL

RSV34

28

RSV35

29

VSS

31

VSS

32

25

26

27

30

Figure 3-14. Pin Map [Section N]

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K

F

A

L

G

B

M

H

C

N

I

O

J

D

E

AU

AT

EMAC[1]_GMTCLK EMAC[1]_RXD[6] EMAC[1]_RXD[4] EMAC[1]_RXD[2]

RSV9

EMAC[1]_RXDV EMAC1_RXD[3] EMAC1_RXD[1] EMAC1_RXD[0] EMAC[1]_RXCLK

MCA[2]_AXR[1]/

MCB_DX

EMAC[1]_RXD[5]

MCA[2]_AXR[0]

MCA[2]_AMUTE

AR

AP

AN

AM

AL

VSS

MCA[2]_AFSX/

MCB_CLKS/

MCB_FSX

MCA[2]_AHCLKX/

MCB_CLKR

DVDD_3P3

MCA[2]_AFSR/

MCB_CLKX/

MCB_FSR

MCA[2]_AHCLKR/

MCB_CLKS

MCA[2]_ACLKX/

MCB_CLKX

MCA[1]_AHCLKX

MCA[2]_ACLKR/

MCB_CLKR/

MCB_DR

MCA[1]_AXR[0]

MCA[1]_ACLKX MCA[1]_AHCLKR

33

34

35

36

37

Figure 3-15. Pin Map [Section O]

Device Pins

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3.2 Terminal Functions

The terminal functions tables identify the external signal names, the associated pin (ball) numbers along

with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown

resistors, and a functional pin description. Bolded pin names denote the muxed pin function being

described in each table. For more detailed information on device configurations, peripheral selection,

multiplexed/shared pin, and see Section 4, Device Configurations.

3.2.1 Boot Configuration

Table 3-1. Boot Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

BOOT

Boot Mode inputs. Select the peripheral over which the Host ARM Cortex™-A8 will boot.

GPMC_A[5]/GP0[13]/

BTMODE[4]

GPMC, GP0

PINCTRL226

AE2

AE1

AE3

AE4

AE5

GPMC_A[4]/GP0[12]/

BTMODE[3]

GPMC, GP0

PINCTRL225

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[3]/GP0[11]/

BTMODE[2]

GPMC, GP0

PINCTRL224

Boot Mode Selection pins. For boot mode information,

see Table 4-5.

I

GPMC_A[2]/GP0[10]/

BTMODE[1]

GPMC, GP0

PINCTRL223

GPMC_A[1]/GP0[9]/

BTMODE[0]

GPMC, GP0

PINCTRL222

DEVICE CONTROL

GPMC CS0 default Data Bus Width input

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[8]/GP0[16]/

CS0BW

GPMC, GP0

PINCTRL229

AD4

AD3

I

0 = 8-bit data bus

1 = 16-bit data bus

GPMC_A[7]/GP0[15]/

CS0MUX[1]

GPMC, GP0

PINCTRL228

GPMC CS0 default Address/Data multiplexing mode

input

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

00 = Not multiplexed

01 = A/A/D muxed

10 = A/D muxed

11 = Reserved

GPMC_A[6]/GP0[14]/

CS0MUX[0]

GPMC, GP0

PINCTRL227

AD8

AD2

GPMC CS0 default GPMC_Wait enable input

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[9]/GP0[17]/

CS0WAIT

GPMC, GP0

PINCTRL230

0 = Wait disabled

1 = Wait enabled

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.2 DDR2/3 Memory Controller Signals

Table 3-2. DDR2/3 Memory Controller 0 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

B12

A12

A15

B15

C18

E13

B17

F18

D13

C13

D9

DDR[0]_CLK[0]

DDR[0]_CLK[1]

DDR[0]_CKE

O

DVDD_DDR[0] DDR[0] Clock 0

DVDD_DDR[0] DDR[0] Negative Clock 0

DVDD_DDR[0] DDR[0] Clock 1

O

DVDD_DDR[0] DDR[0] Negative Clock 1

DVDD_DDR[0] DDR[0] Clock Enable

DVDD_DDR[0] DDR[0] Write Enable

DVDD_DDR[0] DDR[0] Chip Select 0

DVDD_DDR[0] DDR[0] Chip Select 1

O

DDR[0]_WE

O

DDR[0]_CS[0]

DDR[0]_CS[1]

DDR[0]_RAS

O

DVDD_DDR[0] DDR[0] Row Address Strobe output

DVDD_DDR[0] DDR[0] Column Address Strobe output

DDR[0]_CAS

O

DDR[0]_DQM[3]

DDR[0]_DQM[2]

DDR[0]_DQM[1]

DDR[0]_DQM[0]

DDR[0]_DQS[3]

DDR[0]_DQS[2]

DDR[0]_DQS[1]

O

DVDD_DDR[0]

DDR[0] Data Mask outputs

DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24]

DDR[0]_DQM[2]: For DDR[0]_D[23:16]

DDR[0]_DQM[1]: For DDR[0]_D[15:8]

G9

O

B5

O

DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0]

C2

O

B9

I/O

DVDD_DDR[0] Data strobe input/outputs for each byte of the 32-bit data bus. They are

outputs to the DDR[0] memory when writing and inputs when reading.

They are used to synchronize the data transfers.

DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]

DDR[0]_DQS[2]: For DDR[0]_D[23:16]

DDR[0]_DQS[1]: For DDR[0]_D[15:8]

B8

DVDD_DDR[0]

B4

DVDD_DDR[0]

DDR[0]_DQS[0]

F4

I/O

DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

DDR[0]_DQS[3]

DDR[0]_DQS[2]

DDR[0]_DQS[1]

A9

A8

A4

I/O

DVDD_DDR[0] Complimentary data strobe input/outputs for each byte of the 32-bit data

bus. They are outputs to the DDR[0] memory when writing and inputs

when reading. They are used to synchronize the data transfers.

DVDD_DDR[0]

DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24]

DDR[0]_DQS[2]: For DDR[0]_D[23:16]

DDR[0]_DQS[1]: For DDR[0]_D[15:8]

DDR[0]_DQS[0]

E3

I/O

DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

DDR[0]_ODT[0]

DDR[0]_ODT[1]

DDR[0]_RST

E18

A16

D18

N15

B14

F13

O

DVDD_DDR[0] DDR[0] On-Die Termination for Chip Select 0.

DVDD_DDR[0] DDR[0] On-Die Termination for Chip Select 1.

DVDD_DDR[0] DDR[0] Reset output

DVDD_DDR[0]

DDR[0]_BA[2]

DDR[0]_BA[1]

DDR[0]_BA[0]

DVDD_DDR[0] DDR[0] Bank Address outputs

DVDD_DDR[0]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) Specifies the operating I/O supply voltage for each signal.

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Table 3-2. DDR2/3 Memory Controller 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

D17

B16

N16

B13

C14

K13

N14

A14

L13

J13

H13

G13

D15

N17

A13

C9

DDR[0]_A[14]

DDR[0]_A[13]

DDR[0]_A[12]

DDR[0]_A[11]

DDR[0]_A[10]

DDR[0]_A[9]

DDR[0]_A[8]

DDR[0]_A[7]

DDR[0]_A[6]

DDR[0]_A[5]

DDR[0]_A[4]

DDR[0]_A[3]

DDR[0]_A[2]

DDR[0]_A[1]

DDR[0]_A[0]

DDR[0]_D[31]

DDR[0]_D[30]

DDR[0]_D[29]

DDR[0]_D[28]

DDR[0]_D[27]

DDR[0]_D[26]

DDR[0]_D[25]

DDR[0]_D[24]

DDR[0]_D[23]

DDR[0]_D[22]

DDR[0]_D[21]

DDR[0]_D[20]

DDR[0]_D[19]

DDR[0]_D[18]

DDR[0]_D[17]

DDR[0]_D[16]

O

DVDD_DDR[0]

DVDD_DDR[0] DDR[0] Address Bus

DVDD_DDR[0]

O

I/O

J11

C11

G10

E8

B10

B11

E9

DVDD_DDR[0]

DDR[0] Data Bus

DVDD_DDR[0]

E7

F9

DVDD_DDR[0]

D8

F8

B7

H10

A7

C8

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Table 3-2. DDR2/3 Memory Controller 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

B3

A3

B6

A5

D6

C6

D7

C5

C1

F3

B2

D2

G4

E2

F2

B1

A6

DDR[0]_D[15]

DDR[0]_D[14]

DDR[0]_D[13]

DDR[0]_D[12]

DDR[0]_D[11]

DDR[0]_D[10]

DDR[0]_D[9]

DDR[0]_D[8]

DDR[0]_D[7]

DDR[0]_D[6]

DDR[0]_D[5]

DDR[0]_D[4]

DDR[0]_D[3]

DDR[0]_D[2]

DDR[0]_D[1]

DDR[0]_D[0]

DDR[0]_VTP

I/O

I

DVDD_DDR[0]

DDR[0] Data Bus

DVDD_DDR[0] DDR VTP Compensation Resistor Connection

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Table 3-3. DDR2/3 Memory Controller 1 Terminal Functions

SIGNAL

NAME

DDR[1]_CLK[0]

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

B26

A26

A23

B23

C20

E25

B21

F20

D25

C25

D29

G29

B33

C36

B29

B30

B34

O

DVDD_DDR[1] DDR[1] Clock 0

DDR[1]_CLK[0]

DDR[1]_CLK[1]

DDR[1]_CKE

DVDD_DDR[1] DDR[1] Negative Clock 0

DVDD_DDR[1] DDR[1] Clock 1

O

DVDD_DDR[1] DDR[1] Negative Clock 1

DVDD_DDR[1] DDR[1] Clock Enable

DVDD_DDR[1] DDR[1] Write Enable

DVDD_DDR[1] DDR[1] Chip Select 0

DVDD_DDR[1] DDR[1] Chip Select 1

O

DDR[1]_WE

O

DDR[1]_CS[0]

DDR[1]_CS[1]

DDR[1]_RAS

O

DVDD_DDR[1] DDR[1] Row Address Strobe output

DVDD_DDR[1] DDR[1] Column Address Strobe output

DDR[1]_CAS

O

DDR[1]_DQM[3]

DDR[1]_DQM[2]

DDR[1]_DQM[1]

DDR[1]_DQM[0]

DDR[1]_DQS[3]

DDR[1]_DQS[2]

DDR[1]_DQS[1]

O

DVDD_DDR[1]

DDR[1] Data Mask outputs

DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24]

DDR[1]_DQM[2]: For DDR[1]_D[23:16]

DDR[1]_DQM[1]: For DDR[1]_D[15:8]

O

DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0]

O

DVDD_DDR[1] Data strobe input/outputs for each byte of the 32-bit data bus. They are

outputs to the DDR[1] memory when writing and inputs when reading.

They are used to synchronize the data transfers.

DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]

DDR[1]_DQS[2]: For DDR[1]_D[23:16]

DDR[1]_DQS[1]: For DDR[1]_D[15:8]

I/O

DVDD_DDR[1]

DDR[1]_DQS[0]

F34

I/O

DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]

DDR[1]_DQS[3]

DDR[1]_DQS[2]

DDR[1]_DQS[1]

A29

A30

A34

I/O

DVDD_DDR[1] Complimentary data strobe input/outputs for each byte of the 32-bit

data bus. They are outputs to the DDR[1] memory when writing and

inputs when reading. They are used to synchronize the data transfers.

DVDD_DDR[1]

DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24]

DDR[1]_DQS[2]: For DDR[1]_D[23:16]

DDR[1]_DQS[1]: For DDR[1]_D[15:8]

DDR[1]_DQS[0]

E35

I/O

DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]

DDR[1]_ODT[0]

DDR[1]_ODT[1]

DDR[1]_RST

E20

A22

D20

N23

B24

F25

O

DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 0.

DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 1.

DVDD_DDR[1] DDR[1] Reset output

DVDD_DDR[1]

DDR[1]_BA[2]

DDR[1]_BA[1]

DDR[1]_BA[0]

DVDD_DDR[1] DDR[1] Bank Address outputs

DVDD_DDR[1]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) Specifies the operating I/O supply voltage for each signal.

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Table 3-3. DDR2/3 Memory Controller 1 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

D21

B22

N22

B25

C24

K25

N24

A24

L25

J25

DDR[1]_A[14]

DDR[1]_A[13]

DDR[1]_A[12]

DDR[1]_A[11]

DDR[1]_A[10]

DDR[1]_A[9]

DDR[1]_A[8]

DDR[1]_A[7]

DDR[1]_A[6]

DDR[1]_A[5]

DDR[1]_A[4]

DDR[1]_A[3]

DDR[1]_A[2]

DDR[1]_A[1]

DDR[1]_A[0]

DDR[1]_D[31]

DDR[1]_D[30]

DDR[1]_D[29]

DDR[1]_D[28]

DDR[1]_D[27]

DDR[1]_D[26]

DDR[1]_D[25]

DDR[1]_D[24]

DDR[1]_D[23]

DDR[1]_D[22]

DDR[1]_D[21]

DDR[1]_D[20]

DDR[1]_D[19]

DDR[1]_D[18]

DDR[1]_D[17]

DDR[1]_D[16]

O

DVDD_DDR[1]

DVDD_DDR[1] DDR[1] Address Bus

DVDD_DDR[1]

O

H25

G25

D23

N21

A25

C29

J27

O

I/O

C27

G28

E30

B28

B27

E29

E31

F29

D30

F30

B31

H28

A31

C30

DVDD_DDR[1]

DDR[1] Data Bus

DVDD_DDR[1]

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Table 3-3. DDR2/3 Memory Controller 1 Terminal Functions (continued)

SIGNAL

NAME

DDR[1]_D[15]

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NO.

B35

A35

B32

A33

D32

C32

D31

C33

C37

F35

B36

D36

G34

E36

F36

B37

A32

I/O

I

DVDD_DDR[1]

DDR[1]_D[14]

DDR[1]_D[13]

DDR[1]_D[12]

DDR[1]_D[11]

DDR[1]_D[10]

DDR[1]_D[9]

DDR[1]_D[8]

DDR[1]_D[7]

DDR[1]_D[6]

DDR[1]_D[5]

DDR[1]_D[4]

DDR[1]_D[3]

DDR[1]_D[2]

DDR[1]_D[1]

DDR[1]_D[0]

DDR[1]_VTP

DDR[1] Data Bus

DVDD_DDR[1] DDR VTP Compensation Resistor Connection

50

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3.2.3 Ethernet Media Access Controller (EMAC) Signals

Table 3-4. EMAC Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

MDIO_MCLK

AH37

O

Management Data Serial Clock output

PINCTRL275

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

MDIO_MDIO

AH36

I/O

Management Data I/O

PINCTRL276

EMAC0

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

EMAC[0]_COL

AB25

AA25

AC37

AE37

I

[G]MII Collision Detect (Sense) input

[G]MII Carrier Sense input

PINCTRL251

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

EMAC[0]_CRS

PINCTRL252

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

EMAC[0]_GMTCLK

EMAC[0]_RXCLK

O

I

GMII Source Asynchronous Transmit Clock

[G]MII Receive Clock

PINCTRL253

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL254

-

EMAC[0]_RXD[7]

EMAC[0]_RXD[6]

EMAC[0]_RXD[5]

EMAC[0]_RXD[4]

EMAC[0]_RXD[3]

EMAC[0]_RXD[2]

EMAC[0]_RXD[1]

EMAC[0]_RXD[0]

AE36

AC25

AD25

AC35

AD35

AC36

AD36

AD37

PINCTRL262

-

PINCTRL261

-

PINCTRL260

-

[G]MII Receive Data [7:0]. For 1000 EMAC GMII

operation, EMAC[0]_RXD[7:0] are used. For 10/100

EMAC MII operation, only EMAC[0]_RXD[3:0] are

used.

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

PINCTRL259

I

-

PINCTRL258

-

PINCTRL257

-

PINCTRL256

-

PINCTRL255

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

EMAC[0]_RXDV

EMAC[0]_RXER

EMAC[0]_TXCLK

AE35

AE34

AF37

I

[G]MII Receive Data Valid input

[G]MII Receive Data Error input

[G]MII Transmit Clock input

PINCTRL263

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL264

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL265

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-4. EMAC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

-

EMAC[0]_TXD[7]

EMAC[0]_TXD[6]

EMAC[0]_TXD[5]

EMAC[0]_TXD[4]

EMAC[0]_TXD[3]

EMAC[0]_TXD[2]

EMAC[0]_TXD[1]

EMAC[0]_TXD[0]

AG35

PINCTRL273

-

AG36

AF36

AG28

AE30

AE31

AE32

AE33

PINCTRL272

-

PINCTRL271

-

[G]MII Transmit Data [7:0]. For 1000 EMAC GMII

operation, EMAC[0]_TXD[7:0] are used. For 10/100

EMAC MII operation, only EMAC[0]_TXD[3:0] are

used.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

PINCTRL270

O

-

PINCTRL269

-

PINCTRL268

-

PINCTRL267

-

PINCTRL266

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

EMAC[0]_TXEN

AG37

O

[G]MII Transmit Data Enable output

PINCTRL274

EMAC1

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

EMAC[1]_COL

AR30

AN31

AU33

AT37

I

[G]MII Collision Detect (Sense) input

[G]MII Carrier Sense input

PINCTRL72

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

EMAC[1]_CRS

PINCTRL73

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

-

EMAC[1]_GMTCLK

EMAC[1]_RXCLK

O

I

GMII Source Asynchronous Transmit Clock

[G]MII Receive Clock

PINCTRL61

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL51

-

EMAC[1]_RXD[7]

EMAC[1]_RXD[6]

EMAC[1]_RXD[5]

EMAC[1]_RXD[4]

EMAC[1]_RXD[3]

EMAC[1]_RXD[2]

EMAC[1]_RXD[1]

EMAC[1]_RXD[0]

AP32

AU34

AR33

AU35

AT34

AU36

AT35

AT36

PINCTRL59

-

PINCTRL58

-

PINCTRL57

-

[G]MII Receive Data [7:0]. For 1000 EMAC GMII

operation, EMAC[1]_RXD[7:0] are used. For 10/100

EMAC MII operation, only EMAC[1]_RXD[3:0] are

used.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

PINCTRL56

I

-

PINCTRL55

-

PINCTRL54

-

PINCTRL53

-

PINCTRL52

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

EMAC[1]_RXDV

EMAC[1]_RXER

AT33

AN30

I

[G]MII Receive Data Valid input

[G]MII Receive Data Error input

PINCTRL60

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL74

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Table 3-4. EMAC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

EMAC[1]_TXCLK

AT30

I

[G]MII Transmit Clock input

PINCTRL71

-

EMAC[1]_TXD[7]

EMAC[1]_TXD[6]

EMAC[1]_TXD[5]

EMAC[1]_TXD[4]

EMAC[1]_TXD[3]

EMAC[1]_TXD[2]

EMAC[1]_TXD[1]

EMAC[1]_TXD[0]

AM30

AP30

AT31

AU31

AU32

AT32

AR32

AP31

PINCTRL69

-

PINCTRL68

-

PINCTRL67

-

[G]MII Transmit Data [7:0]. For 1000 EMAC GMII

operation, EMAC[1]_TXD[7:0] are used. For 10/100

EMAC MII operation, only EMAC[1]_TXD[3:0] are

used.

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

PINCTRL66

O

-

PINCTRL65

-

PINCTRL64

-

PINCTRL63

-

PINCTRL62

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

-

EMAC[1]_TXEN

AU30

O

[G]MII Transmit Data Enable output

PINCTRL70

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3.2.4 General-Purpose Input/Output (GPIO) Signals

Table 3-5. GPIO Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

GPIO0

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

TIM7_OUT/

GPMC_A[12]/

GP0[31]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM7, GPMC

PINCTRL206

G1

H1

I/O

General-Purpose Input/Output (I/O) 0 [GP0] pin 31.

General-Purpose Input/Output (I/O) 0 [GP0] pin 30.

General-Purpose Input/Output (I/O) 0 [GP0] pin 29.

General-Purpose Input/Output (I/O) 0 [GP0] pin 28.

General-Purpose Input/Output (I/O) 0 [GP0] pin 27.

General-Purpose Input/Output (I/O) 0 [GP0] pin 26.

General-Purpose Input/Output (I/O) 0 [GP0] pin 25.

General-Purpose Input/Output (I/O) 0 [GP0] pin 24.

General-Purpose Input/Output (I/O) 0 [GP0] pin 23.

General-Purpose Input/Output (I/O) 0 [GP0] pin 22.

General-Purpose Input/Output (I/O) 0 [GP0] pin 21.

General-Purpose Input/Output (I/O) 0 [GP0] pin 20.

General-Purpose Input/Output (I/O) 0 [GP0] pin 19.

General-Purpose Input/Output (I/O) 0 [GP0] pin 18.

TIM6_OUT/

GPMC_A[24]/

GP0[30]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM6, GPMC

PINCTRL205

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM5_OUT/

GP0[29]

TIM5

PINCTRL204

H34

H33

H2

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM4_OUT/

GP0[28]

TIM4

PINCTRL203

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[12]/

GP0[27]

GPMC

PINCTRL202

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[21]/

GP0[26]

GPMC

PINCTRL201

H3

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

-

GP0[25]

H4

PINCTRL200

PULL: IPU / IPD

DRIVE: H / L

DVDD_3P3

GPMC_A[13]/

GP0[24]

GPMC

PINCTRL199

H6

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_A[14]/

GP0[23]

GPMC

PINCTRL198

H5

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

GPMC_A[15]/

GP0[22]

GPMC

PINCTRL197

J1

PULL: DIS / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC_A[16]/

GP0[21]

GPMC

PINCTRL196

J2

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[27]/

GP0[20]

GPMC

PINCTRL233

AC5

AC2

AD1

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[11]/

GP0[19]

GPMC

PINCTRL232

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[10]/

GP0[18]

GPMC

PINCTRL231

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

54

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

Table 3-5. GPIO Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

GPMC_A[9]/

GP0[17]/

CS0WAIT

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL230

AD2

I/O

General-Purpose Input/Output (I/O) 0 [GP0] pin 17.

GPMC_A[8]/

GP0[16]/

CS0BW

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL229

AD4

AD3

AD8

AE2

AE1

AE3

AE4

AE5

AE6

H35

G5

I/O

General-Purpose Input/Output (I/O) 0 [GP0] pin 16.

General-Purpose Input/Output (I/O) 0 [GP0] pin 15.

General-Purpose Input/Output (I/O) 0 [GP0] pin 14.

General-Purpose Input/Output (I/O) 0 [GP0] pin 13.

General-Purpose Input/Output (I/O) 0 [GP0] pin 12.

General-Purpose Input/Output (I/O) 0 [GP0] pin 11.

General-Purpose Input/Output (I/O) 0 [GP0] pin 10.

General-Purpose Input/Output (I/O) 0 [GP0] pin 9.

General-Purpose Input/Output (I/O) 0 [GP0] pin 8.

General-Purpose Input/Output (I/O) 0 [GP0] pin 7.

General-Purpose Input/Output (I/O) 0 [GP0] pin 6.

General-Purpose Input/Output (I/O) 0 [GP0] pin 5.

General-Purpose Input/Output (I/O) 0 [GP0] pin 4.

General-Purpose Input/Output (I/O) 0 [GP0] pin 3.

General-Purpose Input/Output (I/O) 0 [GP0] pin 2.

General-Purpose Input/Output (I/O) 0 [GP0] pin 1.

General-Purpose Input/Output (I/O) 0 [GP0] pin 0.

GPMC_A[7]/

GP0[15]/

CS0MUX[1]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL228

GPMC_A[6]/

GP0[14]/

CS0MUX[0]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL227

GPMC_A[5]/

GP0[13]/

BTMODE[4]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL226

GPMC_A[4]/

GP0[12]/

BTMODE[3]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL225

GPMC_A[3]/

GP0[11]/

BTMODE[2]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL224

GPMC_A[2]/

GP0[10]/

BTMODE[1]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL223

GPMC_A[1]/

GP0[9]/

BTMODE[0]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, BOOT

PINCTRL222

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[0]/

GP0[8]

GPMC

PINCTRL221

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0[7]/

MCA[0]_AMUTEIN

MCA[0]

PINCTRL298

GP0[6]/

MCA[1]_AMUTEIN/

GPMC_A[23]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[1], GPMC

PINCTRL297

GP0[5]/

MCA[2]_AMUTEIN/

GPMC_A[24]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], GPMC

PINCTRL296

G2

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

GP0[4]

H32

J31

PINCTRL295

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0[3]/

TCLKIN

Timer CLKIN

PINCTRL294

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

GP0[2]

GP0[1]

GP0[0]

K30

L29

K31

PINCTRL293

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL292

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL291

Device Pins

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Table 3-5. GPIO Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

GPIO1

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP1[31]/

SATA_ACT1_LED

SATA

PINCTRL300

J33

J32

V1

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 31.

General-Purpose Input/Output (I/O) 1 [GP1] pin 30.

General-Purpose Input/Output (I/O) 1 [GP1] pin 29.

General-Purpose Input/Output (I/O) 1 [GP1] pin 28.

General-Purpose Input/Output (I/O) 1 [GP1] pin 27.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP1[30]/

SATA_ACT0_LED

SATA

PINCTRL299

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_CLK/

GP1[29]

GPMC

PINCTRL250

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART0_CTS/

GP1[28]

UART0

PINCTRL176

N7

N9

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART0_RTS/

GP1[27]

UART0

PINCTRL175

UART1_CTS/

GPMC_A[13]/

GPMC_A[17]/

GP1[26]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART1, GPMC

PINCTRL184

L3

M2

K7

L9

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 26.

General-Purpose Input/Output (I/O) 1 [GP1] pin 25.

General-Purpose Input/Output (I/O) 1 [GP1] pin 24.

General-Purpose Input/Output (I/O) 1 [GP1] pin 23.

UART1_RTS/

GPMC_A[14]/

GPMC_A[18]/

GP1[25]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART1, GPMC

PINCTRL183

UART2_CTS/

GPMC_A[16]/

GPMC_A[25]/

GP1[24]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART2, GPMC

PINCTRL188

UART2_RTS/

GPMC_A[15]/

GPMC_A[26]/

GP1[23]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART2, GPMC

PINCTRL187

SPI_SCS[3]/

GPMC_A[21]/

GP1[22]

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI, GPMC

PINCTRL170

P1

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 22.

General-Purpose Input/Output (I/O) 1 [GP1] pin 21.

General-Purpose Input/Output (I/O) 1 [GP1] pin 20.

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

GPMC_CS[4]/

GP1[21]

GPMC

PINCTRL211

AG3

AE7

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_DIR/

GP1[20]

GPMC

PINCTRL218

UART0_RIN/

GPMC_A[17]/

GPMC_A[22]/

GP1[19]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART0, GPMC

PINCTRL180

N3

N5

N4

N6

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 19.

General-Purpose Input/Output (I/O) 1 [GP1] pin 18.

General-Purpose Input/Output (I/O) 1 [GP1] pin 17.

General-Purpose Input/Output (I/O) 1 [GP1] pin 16.

UART0_DCD/

GPMC_A[18]/

GPMC_A[23]/

GP1[18]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART0, GPMC

PINCTRL179

UART0_DSR/

GPMC_A[19]/

GPMC_A[24]/

GP1[17]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART0, GPMC

PINCTRL178

UART0_DTR/

GPMC_A[20]/

GPMC_A[12]/

GP1[16]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART0, GPMC

PINCTRL177

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Table 3-5. GPIO Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[24]/

GP1[15]

GPMC

PINCTRL195

J3

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 15.

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[23]/

GP1[14]

GPMC

PINCTRL194

J4

J5

I/O

General-Purpose Input/Output (I/O) 1 [GP1] pin 14.

General-Purpose Input/Output (I/O) 1 [GP1] pin 13.

General-Purpose Input/Output (I/O) 1 [GP1] pin 12.

General-Purpose Input/Output (I/O) 1 [GP1] pin 11.

General-Purpose Input/Output (I/O) 1 [GP1] pin 10.

General-Purpose Input/Output (I/O) 1 [GP1] pin 9.

General-Purpose Input/Output (I/O) 1 [GP1] pin 8.

General-Purpose Input/Output (I/O) 1 [GP1] pin 7.

General-Purpose Input/Output (I/O) 1 [GP1] pin 6.

General-Purpose Input/Output (I/O) 1 [GP1] pin 5.

General-Purpose Input/Output (I/O) 1 [GP1] pin 4.

General-Purpose Input/Output (I/O) 1 [GP1] pin 3.

General-Purpose Input/Output (I/O) 1 [GP1] pin 2.

General-Purpose Input/Output (I/O) 1 [GP1] pin 1.

General-Purpose Input/Output (I/O) 1 [GP1] pin 0.

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

-

GP1[13]

PINCTRL193

PULL: IPU / IPD

DRIVE: H / L

DVDD_3P3

GPMC_A[25]/

GP1[12]

GPMC

PINCTRL192

J7

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_A[26]/

GP1[11]

GPMC

PINCTRL191

J6

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

GPMC_A[22]/

GP1[10]

GPMC

PINCTRL190

K2

K8

R5

R13

T13

T2

PULL: DIS / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC_A[27]/

GP1[9]

GPMC

PINCTRL189

SD_SDWP/

GPMC_A[15]/

GP1[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL165

SD_SDCD/

GPMC_A[16]/

GP1[7]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL164

SD_DAT[3]/

GPMC_A[17]/

GP1[6]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL163

SD_DAT[2]_SDRW/

GPMC_A[18]/

GP1[5]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL162

SD_DAT[1]_SDIRQ/

GPMC_A[19]/

GP1[4]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL161

T1

SD_DAT[0]/

GPMC_A[20]/

GP1[3]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL160

U1

U3

U2

U4

SD_CMD/

GPMC_A[21]/

GP1[2]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

SD, GPMC

PINCTRL159

SD_CLK/

GPMC_A[13]/

GP1[1]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

SD, GPMC

PINCTRL158

SD_POW/

GPMC_A[14]/

GP1[0]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

SD, GPMC

PINCTRL157

Device Pins

57

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3.2.5 General-Purpose Memory Controller (GPMC) Signals

Table 3-6. GPMC Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_CLK/

GP1[29]

V1

O

GP1

GPMC Clock output

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

GPMC_CS[5] /

GPMC_A[12]

GPMC

PINCTRL212

AG1

AG3

AG9

AH2

AH1

AH7

AG2

AF2

O

I

GPMC Chip Select 5

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

GPMC_CS[4] /

GP1[21]

GP1

PINCTRL211

GPMC Chip Select 4

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

GPMC_CS[3]

GPMC_CS[2]

GPMC_CS[1]

GPMC_CS[0]

GPMC_WE

GPMC Chip Select 3

PINCTRL210

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

GPMC Chip Select 2

PINCTRL209

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

GPMC Chip Select 1

PINCTRL208

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

GPMC Chip Select 0

PINCTRL207

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

GPMC Write Enable output

GPMC Output Enable output

GPMC Upper Byte Enable output

PINCTRL213

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

-

GPMC_OE_RE

GPMC_BE1

PINCTRL214

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

-

AF1

PINCTRL216

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

-

GPMC Lower Byte Enable output or Command Latch

Enable output

GPMC_BE0_CLE

GPMC_ADV_ALE

AE11

AE10

AE7

AE9

AE8

PINCTRL215

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

-

GPMC Address Valid output or Address Latch Enable

output

PINCTRL217

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_DIR/

GP1[20]

GP1

PINCTRL218

GPMC Direction Control for External Transceivers

GPMC Write Protect output

PULL: IPU / IPD

DRIVE: H / L

DVDD_3P3

-

GPMC_WP

PINCTRL219

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

GPMC_WAIT

GPMC Wait input

PINCTRL220

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

58

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Table 3-6. GPMC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[27]/

GP0[20]

GP0

PINCTRL233

AC5

O

GPMC Address 27

PULL: DIS / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC_A[27]/

GP1[9]

GP1

PINCTRL189

K8

N1

O

UART1_RXD/

GPMC_A[26]/

GPMC_A[20]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

UART1, GPMC

PINCTRL181

UART2_RTS/

GPMC_A[15]/

GPMC_A[26]/

GP1[23]

PULL: IPU / DIS UART2, GPMC,

L9

O

DRIVE: H / H

DVDD_3P3

GP1

PINCTRL187

GPMC Address 26

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_A[26]/

GP1[11]

GP1

PINCTRL191

J6

O

UART1_TXD/

GPMC_A[25]/

GPMC_A[19]

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

UART1, GPMC

PINCTRL182

N2

UART2_CTS/

GPMC_A[16]/

GPMC_A[25]/

GP1[24]

PULL: IPU / IPU UART2, GPMC,

K7

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL188

GPMC Address 25

PULL: IPU / IPD

DRIVE: H / L

DVDD_3P3

GPMC_A[25]/

GP1[12]

GP1

PINCTRL192

J7

G2

J3

O

GP0[5]/

MCA[2]_AMUTEIN/

GPMC_A[24]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0, MCA[2]

PINCTRL296

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[24]/

GP1[15]

GP1

PINCTRL195

GPMC Address 24

TIM6_OUT/

GPMC_A[24]/

GP0[30]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM6, GP0

PINCTRL205

H1

UART0_DSR/

GPMC_A[19]/

GPMC_A[24]/

GP1[17]

PULL: IPU / IPU UART0, GPMC,

N4

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL178

GP0[6]/

MCA[1]_AMUTEIN/

GPMC_A[23]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0, MCA[1]

PINCTRL297

G5

P2

O

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI_SCS[1]/

GPMC_A[23]

SPI

PINCTRL168

GPMC Address 23

UART0_DCD/

GPMC_A[18]/

GPMC_A[23]/

GP1[18]

PULL: IPU / IPU UART0, GPMC,

N5

J4

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL179

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[23]/

GP1[14]

GP1

PINCTRL194

Device Pins

59

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Table 3-6. GPMC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI_SCS[2]/

GPMC_A[22]

SPI

PINCTRL169

P3

O

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

GPMC_A[22]/

GP1[10]

GP1

PINCTRL190

K2

N3

O

GPMC Address 22

GPMC Address 21

GPMC Address 20

UART0_RIN/

GPMC_A[17]/

GPMC_A[22]/

GP1[19]

PULL: IPU / IPU UART0, GPMC,

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL180

SPI_SCS[3]/

GPMC_A[21]/

GP1[22]

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI, GP1

PINCTRL170

P1

U3

H3

U1

O

SD_CMD/

GPMC_A[21]/

GP1[2]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL159

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[21]/

GP0[26]

GP0

PINCTRL201

SD_DAT[0]/

GPMC_A[20]/

GP1[3]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL160

UART0_DTR/

GPMC_A[20]/

GPMC_A[12]/

GP1[16]

PULL: IPU / DIS UART0, GPMC,

DRIVE: H / H

DVDD_3P3

N6

N1

N4

O

GP1

PINCTRL177

UART1_RXD/

GPMC_A[26]/

GPMC_A[20]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

UART12, GPMC

PINCTRL181

UART0_DSR/

GPMC_A[19]/

GPMC_A[24]/

GP1[17]

PULL: IPU / IPU UART0, GPMC,

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL178

SD_DAT[1]_SDIRQ/

GPMC_A[19]/

GP1[4]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL161

GPMC Address 19

T1

N2

T2

O

UART1_TXD/

GPMC_A[25]/

GPMC_A[19]

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

UART1, GPMC

PINCTRL182

SD_DAT[2]_SDRW/

GPMC_A[18]/

GP1[5]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL162

UART0_DCD/

GPMC_A[18]/

GPMC_A[23]/

GP1[18]

PULL: IPU / IPU UART0, GPMC,

N5

M2

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL179

GPMC Address 18

UART1_RTS/

GPMC_A[14]/

GPMC_A[18]/

GP1[25]

PULL: IPU / DIS UART1, GPMC,

DRIVE: H / H

DVDD_3P3

GP1

PINCTRL183

60

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Table 3-6. GPMC Terminal Functions (continued)

SIGNAL

NAME

SD_DAT[3]/

GPMC_A[17]/

GP1[6]

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL163

T13

O

UART0_RIN/

GPMC_A[17]/

GPMC_A[22]/

GP1[19]

PULL: IPU / IPU UART0, GPMC,

N3

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL180

GPMC Address 17

UART1_CTS/

GPMC_A[13]/

GPMC_A[17]/

GP1[26]

PULL: IPU / IPU UART1, GPMC,

L3

R13

K7

O

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL184

SD_SDCD/

GPMC_A[16]/

GP1[7]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL164

UART2_CTS/

GPMC_A[16]/

GPMC_A[25]/

GP1[24]

PULL: IPU / IPU UART2, GPMC,

DRIVE: Z / Z

DVDD_3P3

GP1

PINCTRL188

GPMC Address 16

GPMC Address 15

GPMC Address 14

GPMC Address 13

PULL: DIS / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC_A[16]/

GP0[21]

GPMC, GP0

PINCTRL196

J2

O

SD_SDWP/

GPMC_A[15]/

GP1[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

SD, GP1

PINCTRL165

R5

UART2_RTS/

GPMC_A[15]/

GPMC_A[26]/

GP1[23]

PULL: IPU / DIS UART2, GPMC,

DRIVE: H / H

DVDD_3P3

L9

O

GP1

PINCTRL187

PULL: IPU / DIS

DRIVE: H / L

DVDD_3P3

GPMC_A[15]/

GP0[22]

GP0

PINCTRL197

J1

O

SD_POW/

GPMC_A[14]/

GP1[0]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

SD, GPMC,

GP1

PINCTRL157

U4

UART1_RTS/

GPMC_A[14]/

GPMC_A[18]/

GP1[25]

PULL: IPU / DIS UART1, GPMC,

DRIVE: H / H

DVDD_3P3

M2

O

GP1

PINCTRL183

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC_A[14]/

GP0[23]

GP0

PINCTRL198

H5

U2

O

SD_CLK/

GPMC_A[13] /

GP1[1]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

SD, GP1

PINCTRL158

UART1_CTS/

GPMC_A[13]/

GPMC_A[17]/

GP1[26]

PULL: IPU / IPU UART1, GPMC,

DRIVE: Z / Z

DVDD_3P3

L3

O

GP1

PINCTRL184

PULL: IPU / IPD

DRIVE: H / L

DVDD_3P3

GPMC_A[13]/

GP0[24]

GP0

PINCTRL199

H6

Device Pins

61

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Table 3-6. GPMC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

UART0_DTR/

GPMC_A[20]/

GPMC_A[12]/

GP1[16]

PULL: IPU / DIS UART0, GPMC,

N6

O

DRIVE: H / H

DVDD_3P3

GP1

PINCTRL177

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC_A[12]/

GP0[27]

GP0

PINCTRL202

H2

O

GPMC Address 12

TIM7_OUT/

GPMC_A[12]/

GP0[31]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM7, GP0

PINCTRL206

G1

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

GPMC_CS[5]/

GPMC_A[12]

GPMC

PINCTRL212

AG1

AC2

AD1

AD2

AD4

AD3

AD8

AE2

AE1

AE3

AE4

AE5

AE6

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[11]/

GP0[19]

GP0

PINCTRL232

GPMC Address 11

GPMC Address 10

GPMC Address 9

GPMC Address 8

GPMC Address 7

GPMC Address 6

GPMC Address 5

GPMC Address 4

GPMC Address 3

GPMC Address 2

GPMC Address 1

GPMC Address 0

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[10]/

GP0[18]

GP0

PINCTRL231

GPMC_A[9]/

GP0[17]/

CS0WAIT

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL230

GPMC_A[8]/

GP0[16]/

CS0BW

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL229

GPMC_A[7]/

GP0[15]/

CS0MUX[1]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL228

GPMC_A[6]/

GP0[14]/

CS0MUX[0]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL227

GPMC_A[5]/

GP0[13]/

BTMODE[4]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL226

GPMC_A[4]/

GP0[12]/

BTMODE[3]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL225

GPMC_A[3]/

GP0[11]/

BTMODE[2]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL224

GPMC_A[2]/

GP0[10]/

BTMODE[1]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL223

GPMC_A[1]/

GP0[9]/

BTMODE[0]

PULL: IPU / DIS

DRIVE: Z / Z

DVDD_3P3

GP0, BOOT

PINCTRL222

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC_A[0]/

GP0[8]

GP0

PINCTRL221

62

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Table 3-6. GPMC Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

GPMC_D[15]

GPMC_D[14]

GPMC_D[13]

GPMC_D[12]

GPMC_D[11]

GPMC_D[10]

GPMC_D[9]

GPMC_D[8]

GPMC_D[7]

GPMC_D[6]

GPMC_D[5]

GPMC_D[4]

GPMC_D[3]

GPMC_D[2]

GPMC_D[1]

GPMC_D[0]

V2

I/O

PINCTRL249

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

V3

V10

W2

W1

W3

Y1

I/O

PINCTRL248

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL247

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL246

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL245

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL244

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL243

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

W4

Y2

PINCTRL242

GPMC Data I/Os. Only D[7:0] are used for 8-bit

interfaces

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL241

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

Y10

AA2

Y3

PINCTRL240

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL239

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL238

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

AA3

AB2

AA4

AC1

PINCTRL237

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL236

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL235

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL234

Device Pins

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3.2.6 High-Definition Multimedia Interface (HDMI) Signals

Table 3-7. HDMI Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

-

HDMI Clock Output.

HDMI_TMDSCLKP

AT24

O

-

VDDA_HDMI

When the HDMI PHY is powered down, these pins

should be left unconnected.

-

HDMI_TMDSCLKN

HDMI_TMDSDN2

HDMI_TMDSDP2

HDMI_TMDSDN1

HDMI_TMDSDP1

HDMI_TMDSDN0

HDMI_TMDSDP0

AU24

AU27

AT27

AU26

AT26

AU25

AT25

VDDA_HDMI

-

HDMI Data 2 output.

VDDA_HDMI

When the HDMI PHY is powered down, these pins

should be left unconnected.

-

VDDA_HDMI

-

HDMI Data 1 output.

VDDA_HDMI

When the HDMI PHY is powered down, these pins

should be left unconnected.

-

VDDA_HDMI

-

HDMI Data 0 output.

VDDA_HDMI

When the HDMI PHY is powered down, these pins

should be left unconnected.

-

VDDA_HDMI

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

HDMI_SCL

HDMI_SDA

HDMI_CEC

HDMI_HPDET

AL25

AK25

AP25

AE24

O

I/O

I

HDMI I2C Serial Clock Output

HDMI I2C Serial Data I/O

PINCTRL301

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL302

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

HDMI Consumer Electronics Control I/O

PINCTRL303

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

HDMI Hot Plug Detect Input. Signals the

connection / removal of an HDMI cable at the

connector.

-

PINCTRL304

HDMI Voltage Reference. When HDMI is used,

this pin must be connected via an external 698-Ω

(±1% tolerance) resistor to V_SS

.

HDMI_EXTSWING

AN25

A

-

When the HDMI PHY is powered down, this pin

should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.7 Inter-Integrated Circuit (I2C) Signals

Table 3-8. I2C Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

I2C0

DESCRIPTION

NO.

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

I2C[0]_SCL

N32

N33

I/O

I2C0 Clock I/O

PINCTRL287

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

I2C[0]_SDA

I2C0 Data I/O

PINCTRL288

I2C1

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

I2C[1]_SCL

I2C[1]_SDA

N34

N35

I/O

I2C1 Clock I/O

I2C1 Data I/O

PINCTRL289

PULL: DIS / DIS

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL290

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.8 Multichannel Audio Serial Port Signals

Table 3-9. McASP0 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[0]_ACLKR

MCA[0]_AHCLKR

MCA[0]_AFSR

AK28

I/O

McASP0 Receive Bit Clock I/O

PINCTRL126

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

AJ27

AG29

H35

I/O

O

McASP0 Receive High-Frequency Master Clock I/O

McASP0 Receive Frame Sync I/O

McASP0 Mute Input

PINCTRL127

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL128

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0[7]/

MCA[0]_AMUTEIN

GP0

PINCTRL298

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[0]_ACLKX

MCA[0]_AHCLKX

MCA[0]_AFSX

AH30

AH31

AJ31

AJ35

AJ37

AJ36

AJ34

AJ33

AJ32

AK37

McASP0 Transmit Bit Clock I/O

PINCTRL129

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

McASP0 Transmit High-Frequency Master Clock I/O

McASP0 Transmit Frame Sync I/O

McASP0 Mute Output

PINCTRL130

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL131

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[0]_AMUTE

PINCTRL132

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[5]/

MCB_DR

MCB

PINCTRL138

I/O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[4]/

MCB_DX

MCB

PINCTRL137

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[3]/

MCB_FSR

MCB

PINCTRL136

McASP0 Transmit/Receive Data I/Os

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[2]/

MCB_FSX

MCB

PINCTRL135

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[0]_AXR[1]

MCA[0]_AXR[0]

PINCTRL134

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL133

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-10. McASP1 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[1]_ACLKR

MCA[1]_AHCLKR

MCA[1]_AFSR

AK36

I/O

McASP1 Receive Bit Clock I/O

PINCTRL139

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

AL37

AK35

G5

I/O

I

McASP1 Receive High-Frequency Master Clock I/O

McASP1 Receive Frame Sync I/O

McASP1 Mute Input

PINCTRL140

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL141

GP0[6]/

MCA[1]_AMUTEIN/

GPMC_A[23]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0, GPMC

PINCTRL297

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[1]_ACLKX

MCA[1]_AHCLKX

MCA[1]_AFSX

AL36

AM37

AK34

AK33

AK32

AL33

I/O

O

McASP1 Transmit Bit Clock I/O

PINCTRL142

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

McASP1 Transmit High-Frequency Master Clock I/O

McASP1 Transmit Frame Sync I/O

McASP1 Mute Output

PINCTRL143

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL144

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[1]_AMUTE

MCA[1]_AXR[1]

MCA[1]_AXR[0]

PINCTRL145

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

I/O

PINCTRL147

McASP1 Transmit/Receive Data I/Os

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL146

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-11. McASP2 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

MCA[2]_ACLKR/

MCB_CLKR/

MCB_DR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCB

PINCTRL148

AL34

I/O

McASP2 Receive Bit Clock I/O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AHCLKR/

MCB_CLKS

MCB

PINCTRL149

AM34

AM35

G2

I/O

I

McASP2 Receive High-Frequency Master Clock I/O

McASP2 Receive Frame Sync I/O

McASP2 Mute Input

MCA[2]_AFSR/

MCB_CLKX/

MCB_FSR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCB

PINCTRL150

GP0[5]/

MCA[2]_AMUTEIN/

GPMC_A[24]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0, GPMC

PINCTRL296

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_ACLKX/

MCB_CLKX

MCB

PINCTRL151

AM36

AN36

AN35

AP36

AR37

AR36

I/O

O

McASP2 Transmit Bit Clock I/O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AHCLKX/

MCB_CLKR

MCB

PINCTRL152

McASP2 Transmit High-Frequency Master Clock I/O

McASP2 Transmit Frame Sync I/O

McASP2 Mute Output

MCA[2]_AFSX/

MCB_CLKS/

MCB_FSX

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCB

PINCTRL153

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[2]_AMUTE

PINCTRL154

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AXR[1]/

MCB_DX

MCB

PINCTRL156

I/O

McASP2 Transmit/Receive Data I/Os

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

MCA[2]_AXR[0]

PINCTRL155

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.9 Multichannel Buffered Serial Port Signals

Table 3-12. McBSP Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

MCA[2]_ACLKR/

MCB_CLKR/

MCB_DR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL148

AL34

I/O

McBSP Receive Clock I/O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AHCLKX/

MCB_CLKR

MCA[2]

PINCTRL152

AN36

AJ34

AM35

AJ37

AL34

AM35

AM36

AJ33

AN35

AJ36

AR37

AM34

AN35

I/O

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[3]/

MCB_FSR

MCA[0]

PINCTRL136

McBSP Receive Frame Sync I/O

McBSP Receive Data Input

McBSP Transmit Clock I/O

MCA[2]_AFSR/

MCB_CLKX/

MCB_FSR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL150

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[5]/

MCB_DR

MCA[0]

PINCTRL138

MCA[2]_ACLKR/

MCB_CLKR/

MCB_DR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL148

I

MCA[2]_AFSR/

MCB_CLKX/

MCB_FSR

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL150

I/O

O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_ACLKX/

MCB_CLKX

MCA[2]

PINCTRL151

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[2]/

MCB_FSX

MCA[0]

PINCTRL135

McBSP Transmit Frame Sync I/O

McBSP Transmit Data Output

McBSP Source Clock Input

MCA[2]_AFSX/

MCB_CLKS/

MCB_FSX

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL153

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[0]_AXR[4]/

MCB_DX

MCA[0]

PINCTRL137

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AXR[1]/

MCB_DX

MCA[2]

PINCTRL156

O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2]_AHCLKR/

MCB_CLKS

MCA[2]

PINCTRL149

I

MCA[2]_AFSX/

MCB_CLKS/

MCB_FSX

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

MCA[2], MCB

PINCTRL153

I

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.10 Oscillator/Phase-Locked Loop (PLL) Signals

Table 3-13. Oscillator/PLL and Clock Generator Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

CLOCK GENERATOR

PULL: IPU / DIS

DRIVE: L / L

DVDD_3P3

-

Device Clock output. Can be used as a system clock

for other devices

CLKOUT

F1

O

PINCTRL320

OSCILLATOR/PLL

Device Crystal input. Crystal connection to internal

oscillator for system clock. Functions as CLKINDEV

clock input when an external oscillator is used.

DEV_MXI/

DEV_CLKIN

DIS

DEV_DVDD18

A19

C19

E19

B19

H37

I

O

-

Device Crystal output. Crystal connection to internal

oscillator for system clock. When device oscillator is

BYPASSED, leave this pin unconnected.

DIS

DEV_DVDD18

DEV_MXO

-

1.8 V Power Supply for Device (DEV) Oscillator. If the

internal oscillator is bypassed, DEVOSC_DVDD18

should still be connected to the 1.8-V power supply.

DEVOSC_DVDD18

DEVOSC_VSS

CLKIN32

S

-

Supply Ground for DEV Oscillator. If the internal

oscillator is bypassed, DEVOSC_VSS should be

connected to ground (VSS).

GND

I

PULL: IPU / IPD

DRIVE: Z / Z

DVDD_3P3

-

RTC Clock input. Optional 32.768 KHz clock for RTC

reference.

PINCTRL321

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.11 Peripheral Component Interconnect Express (PCIe) Signals

Table 3-14. PCIe Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER⁽²⁾

DESCRIPTION

NAME

PCIE_TXP0

NO.

AB31

O

I

PCIE Transmit Data Lane 0.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

these pins should be left unconnected.

PCIE_TXN0

PCIE_RXP0

PCIE_RXN0

PCIE_TXP1

PCIE_TXN1

PCIE_RXP1

PCIE_RXN1

AB30

Y29

PCIE Receive Data Lane 0.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

these pins should be left unconnected.

V29

I

Y27

O

I

PCIE Transmit Data Lane 1.

When the PCIe SERDES are powered down, or if this lane is not used,

these pins should be left unconnected.

AB28

V31

PCIE Receive Data Lane 1.

When the PCIe SERDES are powered down, or if this lane is not used,

these pins should be left unconnected.

V30

I

SERDES_CLKP

SERDES_CLKN

AB34

AB33

I

VDD_LJCB

PCIE Serdes Reference Clock Inputs. Shared between PCI Express and

Serial ATA. When neither PCI Express nor Serial ATA are used, these

pins should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) Specifies the operating I/O supply voltage for each signal.

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3.2.12 Reset, Interrupts, and JTAG Interface Signals

Table 3-15. RESET, Interrupts, and JTAG Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

RESET

DESCRIPTION

NO.

PULL: IPD / IPU

DRIVE: Z / Z

DVDD_3P3

-

RESET

POR

G33

F37

G37

I

Device Reset input

PINCTRL316

IPU

DVDD_3P3

-

Power-On Reset input

Reset output

PULL: IPU / IPU

DRIVE: H / L

DVDD_3P3

-

RSTOUT

O

PINCTRL318

INTERRUPTS

PULL: IPD / IPU

DRIVE: Z / Z

DVDD_3P3

-

NMI

G36

I

Non-Maskable Interrupt input

PINCTRL317

Interrupt-capable general-purpose I/Os.

NOTE: All pins are multiplexed with other pin

functions. For muxing and internal

pullup/pulldown/disable details, see Table 3-5, GPIO

Terminal Functions.

see

Table 3-5

GP0[31:3]

I/O

see NOTE

-

Interrupt-capable general-purpose I/Os.

NOTE: All pins are multiplexed with other pin

functions. For muxing and internal

pullup/pulldown/disable details, see Table 3-5, GPIO

Terminal Functions.

see

Table 3-5

GP1[31:0]

I/O

JTAG

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

TCLK

RTCK

TDI

J37

J36

J34

N30

N31

K36

M37

I

O

I

JTAG test clock input

JTAG return clock output

JTAG test data input

PINCTRL305

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

-

PINCTRL306

PULL: IPU / IPU

DRIVE: H / H

DVDD_3P3

-

PINCTRL307

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

-

TDO

O

I

JTAG test port data output

PINCTRL308

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

JTAG test port mode select input. For proper

operation, do not oppose the IPU on this pin.

TMS

PINCTRL309

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

-

TRST

EMU4

I

JTAG test port reset input

Emulator pin 4

PINCTRL310

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

I/O

PINCTRL315

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

72

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Table 3-15. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

EMU3

EMU2

EMU1

EMU0

M36

I/O

Emulator pin 3

Emulator pin 2

Emulator pin 1

Emulator pin 0

PINCTRL314

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

L37

L36

J35

I/O

PINCTRL313

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL312

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

-

PINCTRL311

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3.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals

Table 3-16. SD/SDIO Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

SD_CLK/

GPMC_A[13]/

GP1[1]

NO.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC, GP1

PINCTRL158

U2

O

SD Clock output

SD_CMD/

GPMC_A[21]/

GP1_[2]

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL159

U3

U1

O

I/O

O

SD Command output

SD_DAT[0]/

GPMC_A[20]/

GP1[3]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL160

SD Data0 I/O. Functions as data bit 0 for 4-bit SD

mode and single data bit for 1-bit SD mode.

SD_DAT[1]_SDIRQ/

GPMC_A[19]/

GP1[4]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GMPC, GP1

PINCTRL161

SD Data1 I/O. Functions as data bit 1 for 4-bit SD

mode and as an IRQ input for 1-bit SD mode

T1

SD_DAT[2]_SDRW/

GPMC_A[18]/

GP1[5]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL162

SD Data2 I/O. Functions as data bit 2 for 4-bit SD

mode and as a Read Wait input for 1-bit SD mode.

T2

SD_DAT[3]/

GPMC_A[17]/

GP1[6]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL163

SD Data3 I/O. Functions as data bit 3 for 4-bit SD

mode.

T13

U4

SD_POW/

GPMC_A[14]/

GP1[0]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

GPMC, GP1

PINCTRL157

SD Card Power Enable output

SD Card Detect input

SD_SDCD/

GPMC_A[16]/

GP1[7]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL164

R13

R5

I

SD_SDWP/

GPMC_A[15]/

GP1[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GMC, GP1

PINCTRL165

I

SD Card Write Protect input

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

74

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3.2.14 Serial ATA Signals

Table 3-17. Serial ATA Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

-

Serial ATA Data Transmit for disk 0.

SATA_TXN0

T31

O

I

-

VDDR_SATA

When the SATA SERDES are powered down, these

pins should be left unconnected.

-

SATA_TXP0

SATA_TXN1

SATA_TXP1

SATA_RXN0

SATA_RXP0

SATA_RXN1

SATA_RXP1

T32

U33

V33

V37

V36

V35

W35

VDDR_SATA

-

Serial ATA Data Transmit for disk 1.

VDDR_SATA

When the SATA SERDES are powered down, these

pins should be left unconnected.

-

VDDR_SATA

-

Serial ATA Data Receive for disk 0.

VDDR_SATA

When the SATA SERDES are powered down, these

pins should be left unconnected.

-

I

VDDR_SATA

-

Serial ATA Data Receive for disk 1.

I

VDDR_SATA

When the SATA SERDES are powered down, these

pins should be left unconnected.

-

I

VDDR_SATA

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP1[30]/

SATA_ACT0_LED

GP1

PINCTRL299

J32

J33

O

Serial ATA disk 0 Activity LED output

Serial ATA disk 1 Activity LED output

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP1[31]/

SATA_ACT1_LED

GP1

PINCTRL300

-

SERDES_CLKP

SERDES_CLKN

AB34

AB33

I

-

VDD_LJCB

PCIE Serdes Reference Clock Input. Shared between

PCI Express and Serial ATA.

-

VDD_LJCB

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals

Table 3-18. SPI Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

SPI_SCLK

R2

I/O

SPI Clock I/O

PINCTRL166

SPI_SCS[3] /

GPMC_A[21]/

GP1[22]

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL170

P1

P3

I/O

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI_SCS[2] /

GPMC_A[22]

GPMC

PINCTRL169

SPI Chip Select I/O

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

SPI_SCS[1] /

GPMC_A[23]

GPMC

PINCTRL168

P2

PULL: DIS / IPU

DRIVE: Z / Z

DVDD_3P3

-

SPI_SCS[0]

SPI_D[1]

R1

PINCTRL167

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

P13

N11

PINCTRL172

SPI Data I/O. Can be configured as either MISO or

MOSI

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

SPI_D[0]

PINCTRL171

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

76

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3.2.16 Timer Signals

Table 3-19. Timer Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

General-Purpose Timers7-1 and Watchdog Timer

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

GP0[3]/

TCLKIN

GP0

J31

G1

I

Timer external clock input

PINCTRL294

Timer7

TIM7_OUT/

GPMC_A[12]/

GP0[31]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

GPMC, GP0

PINCTRL206

I/O

Timer7 capture event input or PWM output

Timer6 capture event input or PWM output

Timer5 capture event input or PWM output

Timer4 capture event input or PWM output

Timer6

TIM6_OUT/

GPMC_A[24]/

GP0[30]

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

GPMC, GP0

PINCTRL205

H1

Timer5

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM5_OUT/

GP0[29]

GP0

PINCTRL204

H34

H33

Timer4

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

TIM4_OUT/

GP0[28]

GP0

PINCTRL203

Timer3-1

There are no external pins on these timers for this device.

Watchdog Timer

PULL: IPU / IPU

DRIVE: H / L

DVDD_3P3

-

WD_OUT

H36

O

Watchdog timer event output

PINCTRL319

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals

Table 3-20. UART0 Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NAME

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

UART0 Receive Data Input. Functions as IrDA

receive input in IrDA modes and CIR receive input in

CIR mode.

-

UART0_RXD

N10

I

PINCTRL173

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

-

UART0 Transmit Data Output. Functions as transmit

output in CIR and IrDA modes.

UART0_TXD

N8

N9

N7

O

I

PINCTRL174

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART0 Request to Send Output. Indicates module is

ready to receive data. Functions as SD output in IrDA

mode.

UART0_RTS /

GP1[27]

GP1

PINCTRL175

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

UART0_CTS /

GP1[28]

GP1

PINCTRL176

UART0 Clear to Send Input. Has no function in IrDA

and CIR modes.

UART0_DTR /

GPMC_A[20]/

GPMC_A[12]/

GP1[16]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

GPMC, GP1

PINCTRL177

N6

N4

N5

N3

O

I

UART0 Data Terminal Ready Output

UART0 Data Set Ready Input

UART0 Data Carrier Detect Input

UART0 Ring Indicator Input

UART0_DSR /

GPMC_A[19]/

GPMC_A[24]/

GP1[17]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL178

UART0_DCD /

GPMC_A[18]/

GPMC_A[23]/

GP1[18]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL179

I

UART0_RIN/

GPMC_A[17]/

GPMC_A[22]/

GP1[19]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL180

I

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-21. UART1 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

UART1_RXD/

GPMC_A[26]/

GPMC_A[20]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

UART1 Receive Data Input. Functions as IrDA

receive input in IrDA modes and CIR receive input in

CIR mode.

GPMC

PINCTRL181

N1

I

UART1_TXD/

GPMC_A[25]/

GPMC_A[19]

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

GPMC

PINCTRL182

UART1 Transmit Data Output. Functions as transmit

output in CIR and IrDA modes.

N2

M2

O

UART1_RTS /

GPMC_A[14]/

GPMC_A[18]/

GP1[25]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART1 Request to Send Output. Indicates module is

ready to receive data. Functions as SD output in IrDA

mode.

GPMC, GP1

PINCTRL183

UART1_CTS /

GPMC_A[13]/

GPMC_A[17]/

GP1[26]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL184

UART1 Clear to Send Input. Has no function in IrDA

and CIR modes.

L3

I/O

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-22. UART2 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

UART2 Receive Data Input. Functions as IrDA

receive input in IrDA modes and CIR receive input in

CIR mode.

-

UART2_RXD

M1

I

PINCTRL185

PULL: IPD / IPD

DRIVE: L / H

DVDD_3P3

-

UART2 Transmit Data Output. Functions as transmit

output in CIR and IrDA modes.

UART2_TXD

L2

L9

O

PINCTRL186

UART2_RTS /

GPMC_A[15]/

GPMC_A[26]/

GP1[23]

PULL: IPU / DIS

DRIVE: H / H

DVDD_3P3

UART2 Request to Send Output. Indicates module is

ready to receive data. Functions as SD output in IrDA

mode.

GPMC, GP1

PINCTRL187

UART2_CTS /

GPMC_A[16]/

GPMC_A[25]/

GP1[24]

PULL: IPU / IPU

DRIVE: Z / Z

DVDD_3P3

GPMC, GP1

PINCTRL188

UART2 Clear to Send Input. Has no function in IrDA

and CIR modes.

K7

I/O

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.18 Universal Serial Bus (USB) Signals

Table 3-23. USB Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

USB0

DESCRIPTION

NO.

USB0_DP

P37

P36

A I/O

-

USB0 bidirectional Data Differential signal pair

[positive/negative].

USB0_DN

-

When the USB0 PHY is powered down, these pins

should be left unconnected.

USB0 current reference output. When the USB0

peripheral is used, this pin must be connected via a

10-kΩ ±1% resistor to VSS.

USB0_R1

N37

A O

-

When the USB0 PHY is powered down, this pin

should be left unconnected.

When this pin is used as USB0_DRVVBUS and the

USB0 Controller is operating as a Host, this signal is

used by the USB0 Controller to enable the external

VBUS charge pump.

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

-

USB0_DRVVBUS

VDD_USB0_VBUS

P35

N36

O

PINCTRL322

When the USB0 PHY is powered down, this pin

should be left unconnected.

USB0 VBUS input (5 V).

The voltage level on this pin is sampled to determine

session status.

I

-

When the USB0 PHY is powered down, this pin

should be left unconnected.

USB1

USB1_DP

USB1_DN

R37

R36

A I/O

-

USB1 bidirectional Data Differential signal pair

[positive/negative].

When the USB1 PHY is powered down, these pins

should be left unconnected.

USB1 current reference output. When the USB1

peripheral is used, this pin must be connected via a

10-kΩ ±1% resistor to VSS.

USB1_R1

T37

A O

-

When the USB1 PHY is powered down, this pin

should be left unconnected.

When this pin is used as USB1_DRVVBUS and the

USB1 Controller is operating as a Host, this signal is

used by the USB1 Controller to enable the external

VBUS charge pump.

PULL: IPD / IPD

DRIVE: L / L

DVDD_3P3

-

USB1_DRVVBUS

VDD_USB1_VBUS

R35

T36

O

PINCTRL323

When the USB1 PHY is powered down, this pin

should be left unconnected.

USB1 VBUS input (5 V).

The voltage level on this pin is sampled to determine

session status.

I

-

When the USB1 PHY is powered down, this pin

should be left unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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3.2.19 Video Input Signals

Table 3-24. Video Input 0 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

Video Input 0 Port A Clock input. Input clock for 8-bit,

16-bit, or 24-bit Port A video capture.

VIN[0]A_CLK

AR14

I

PINCTRL83

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

Video Input 0 Port B Clock input. Input clock for 8-bit

Port B video capture. This signal is not used in 16-bit

and 24-bit capture modes.

-

VIN[0]B_CLK

AR19

AT2

AR2

AU4

AN3

AK4

AK5

AL5

AT5

I

PINCTRL84

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[23]/

VIN[0]B_HSYNC

VIN[0]B

PINCTRL15

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[22]/

VIN[0]B_VSYNC

VIN[0]B

PINCTRL14

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[21]/

VIN[0]B_FLD

VIN[0]B

PINCTRL13

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

Video Input 0 Port A Data inputs. For 16-bit capture,

D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For

8-bit capture, D[7:0] are Port A YCbCr data inputs

and D[15:8] are Port B YCbCr data inputs. For RGB

capture, D[23:16] are R, D[15:8] are G, and D[7:0] are

B data inputs.

VIN[0]A_D[20]/

VIN[0]B_DE

VIN[0]B

PINCTRL12

VIN[0]A_D[19]/

VIN[1]A_DE[0]/

VOUT[1]_C[9]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[1]A,

VOUT[1]

PINCTRL25

VIN[0]A_D[18]/

VIN[1]A_FLD/

VOUT[1]_C[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[1]A,

VOUT[1]

PINCTRL24

VIN[0]A_D[17]/

VIN[1]A_VSYNC/

VOUT[1]_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[1]A,

VOUT[1]

PINCTRL23

VIN[0]A_D[16]/

VIN[1]A_HSYNC/

VOUT[1]_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[1]A,

VOUT[1]

PINCTRL22

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

82

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SPRS681A–OCTOBER 2010–REVISED MARCH 2011

Table 3-24. Video Input 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

VIN[0]A_D[15]

VIN[0]A_D[14]

VIN[0]A_D[13]

VIN[0]A_D[12]

VIN[0]A_D[11]

VIN[0]A_D[10]

VIN[0]A_D[9]

VIN[0]A_D[8]

VIN[0]A_D[7]

VIN[0]A_D[6]

VIN[0]A_D[5]

VIN[0]A_D[4]

VIN[0]A_D[3]

VIN[0]A_D[2]

AU14

I

PINCTRL100

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

AU15

AT15

AU16

AU17

AT16

AE16

AP17

AR17

AP18

AT17

AT18

AR18

AH18

I

PINCTRL99

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL98

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL97

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL96

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL95

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL94

Video Input 0 Port A Data inputs. For 16-bit capture,

D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For

8-bit capture, D[7:0] are Port A YCbCr data inputs

and D[15:8] are Port B YCbCr data inputs. For RGB

capture, D[23:16] are R, D[15:8] are G, and D[7:0] are

B data inputs.

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL93

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL92

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL91

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL90

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL89

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL88

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

PINCTRL87

PULL: IPD / IPD

DRIVE: Z /Z

DVDD_3P3

-

VIN[0]A_D[1]

VIN[0]A_D[0]

AU18

AJ19

I

PINCTRL86

IPD

DVDD_3P3

-

PINCTRL85

Video Input 0 Port B Horizontal Sync input. Discrete

horizontal synchronization signal for Port B 8-bit

YCbCr capture without embedded syncs ("BT.601"

modes). Not used in RGB or 16-bit YCbCr capture

modes

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[23]/

VIN[0]B_HSYNC

VIN[0]A

PINCTRL15

AT2

AU5

I

Video Input 0 Port A Horizontal Sync input. Discrete

horizontal synchronization signal for Port A RGB

capture mode or YCbCr capture without embedded

syncs ("BT.601" modes).

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VIN[0]A_HSYNC

PINCTRL32

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Table 3-24. Video Input 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

Video Input 0 Port B Vertical Sync input. Discrete

vertical synchronization signal for Port B 8-bit YCbCr

capture without embedded syncs ("BT.601" modes).

Not used in RGB or 16-bit YCbCr capture modes.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[22]/

VIN[0]B_VSYNC

VIN[0]A

PINCTRL14

AR2

I

Video Input 0 Port A Vertical Sync input. Discrete

vertical synchronization signal for Port A RGB capture

mode or YCbCr capture without embedded syncs

("BT.601" modes).

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VIN[0]A_VSYNC

AM4

AU4

AL4

I

PINCTRL33

Video Input 0 Port B Field ID input. Discrete field

identification signal for Port B 8-bit YCbCr capture

without embedded syncs ("BT.601" modes). Not used

in RGB or 16-bit YCbCr capture modes

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A_D[21]/

VIN[0]B_FLD

VIN[0]A

PINCTRL13

Video Input 0 Port A Field ID input. Discrete field

identification signal for Port A RGB capture mode or

YCbCr capture without embedded syncs ("BT.601"

modes).

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VIN[0]A_FLD

PINCTRL34

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

Video Input 0 Port B Data Enable input. Discrete data

valid signal for Port B RGB capture mode or YCbCr

capture without embedded syncs ("BT.601" modes).

VIN[0]A_D[20]/

VIN[0]B_DE

VIN[0]A

PINCTRL12

AN3

AT3

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

Video Input 0 Port A Data Enable input. Discrete data

valid signal for Port A RGB capture mode or YCbCr

capture without embedded syncs ("BT.601" modes).

-

VIN[0]A_DE

PINCTRL35

84

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Table 3-25. Video Input 1 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

Video Input 1 Port A Clock input. Input clock for

8-bit or 16-bit Port A video capture. Input data is

sampled on the CLK0 edge.

VOUT[1]_CLK/

VIN[1]A_CLK

VOUT[1]

PINCTRL46

AT7

I

Video Input 1 Port B Clock input. Input clock for

8-bit Port B video capture. Input data is sampled

on the CLK1 edge. This signal is not used in

16-bit capture modes.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_AVID/

VIN[1]B_CLK

VOUT[1]

PINCTRL31

AT4

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_HSYNC/

VIN[1]A_D[15]

VOUT[1]

PINCTRL21

AR5

AM3

AD13

AN8

AP8

AN7

AM8

AK6

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VIN[1]A_D[14]

PINCTRL11

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[7]/

VIN[1]A_D[13]

VOUT[1]

PINCTRL10

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[6]

VIN[1]A_D[12]

VOUT[1]

PINCTRL9

Video Input 1 Port A Data inputs. For 16-bit

capture, D[7:0] are Cb/Cr and [15:8] are Y Port A

inputs. For 8-bit capture, D[7:0] are Port A YCbCr

data inputs and D[15:8] are Port B YCbCr data

inputs. For VIN[1], only D[15:0] are available.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[5]/

VIN[1]A_D[11]

VOUT[1]

PINCTRL8

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[4]/

VIN[1]A_D[10]

VOUT[1]

PINCTRL7

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[3]/

VIN[1]A_D[9]

VOUT[1]

PINCTRL6

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[2]/

VIN[1]A_D[8]

VOUT[1]

PINCTRL20

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-25. Video Input 1 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[9]/

VIN[1]A_D[7]

VOUT[1]

PINCTRL19

AP6

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[8]/

VIN[1]A_D[6]

VOUT[1]

PINCTRL18

AT6

AR6

AC13

AJ7

I

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[7]/

VIN[1]A_D[5]

VOUT[1]

PINCTRL17

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[6]/

VIN[1]A_D[4]

VOUT[1]

PINCTRL16

Video Input 1 Port A Data inputs. For 16-bit

capture, D[7:0] are Cb/Cr and [15:8] are Y Port A

inputs. For 8-bit capture, D[7:0] are Port A YCbCr

data inputs and D[15:8] are Port B YCbCr data

inputs. For VIN[1], only D[15:0] are available.

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[5]/

VIN[1]A_D[3]

VOUT[1]

PINCTRL50

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[4]/

VIN[1]A_D[2]

VOUT[1]

PINCTRL49

AU6

AP7

AU7

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[3]/

VIN[1]A_D[1]

VOUT[1]

PINCTRL48

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[2]/

VIN[1]A_D[0]

VOUT[1]

PINCTRL47

Video Input 1 Port B Horizontal Sync or Data Valid

signal input. Discrete horizontal synchronization

signal for Port B 8-bit YCbCr capture without

embedded syncs ("BT.601" modes). Not used in

16-bit YCbCr capture mode.

VOUT[0]_B_CB_C[0]/

VOUT[1]_C[9]/

VIN[1]B_HSYNC_DE

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL27

AR9

I

Video Input 1 Port A Horizontal Sync input.

Discrete horizontal synchronization signal for Port

A YCbCr capture modes without embedded syncs

("BT.601" modes).

VIN[0]A_D[16]/

VIN[1]A_HSYNC/

VOUT[1]_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VOUT[1]

PINCTRL22

AT5

AP9

I

Video Input 1 Port B Vertical Sync input. Discrete

vertical synchronization signal for Port B 8-bit

YCbCr capture without embedded syncs ("BT.601"

modes). Not used in 16-bit YCbCr capture mode.

VOUT[0]_G_Y_YC[0]/

VOUT[1]_VSYNC/

VIN[1]B_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL29

Video Input 1 Port A Vertical Sync input. Discrete

vertical synchronization signal for Port A YCbCr

capture modes without embedded syncs ("BT.601"

modes).

VIN[0]A_D[17]/

VIN[1]A_VSYNC/

VOUT[1]_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VOUT[1]

PINCTRL23

AL5

AK4

AK5

I

VIN[0]A_D[19]/

VIN[1]A_DE/

VOUT[1]_C[9]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VOUT[1]

PINCTRL25

Video Input 1 Port A Data Enable input. Discrete

data valid signal for Port A YCbCr capture modes

without embedded syncs ("BT.601" modes).

Video Input 1Port A Field ID input. Discrete field

identification signal for Port A YCbCr capture

modes without embedded syncs ("BT.601"

modes).

VIN[0]A_D[18]/

VIN[1]A_FLD/

VOUT[1]_C[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VOUT[1]

PINCTRL24

Video Input 1 Port B Field ID input. Discrete field

identification signal for Port B 8-bit YCbCr capture

without embedded syncs ("BT.601" modes). Not

used in 16-bit YCbCr capture mode.

VOUT[0]_G_Y_YC[1]/

VOUT[1]_FLD/

VIN[1]B_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL30

AU8

I

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3.2.20 Digital Video Output Signals

Table 3-26. Video Output 0 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: L / H

DVDD_3P3

-

VOUT[0]_CLK

AT14

O

Video Output 0 Clock output.

PINCTRL101

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

VOUT[0]_G_Y_YC[9]

VOUT[0]_G_Y_YC[8]

VOUT[0]_G_Y_YC[7]

VOUT[0]_G_Y_YC[6]

VOUT[0]_G_Y_YC[5]

VOUT[0]_G_Y_YC[4]

VOUT[0]_G_Y_YC[3]

VOUT[0]_G_Y_YC[2]

AR13

AU13

AT13

AE14

AM14

AL14

AP14

AE15

AU8

O

PINCTRL109

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL108

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL107

Video Output 0 Data. These signals represent the

8 MSBs of G/Y/YC video data. For RGB mode

they are green data bits, for YUV444 mode they

are Y data bits, for Y/C mode they are Y (Luma)

data bits and for BT.656 mode they are

multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL106

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL105

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL104

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL103

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL102

VOUT[0]_G_Y_YC[1]/

VOUT[1]_FLD/

VIN[1]B_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT,[1]

VIN[1]B

PINCTRL30

Video Output 0 Data. These signals represent the

2 LSBs of G/Y/YC video data for 10-bit, 20-bit and

30-bit video modes (VOUT0 only). For RGB mode

they are green data bits, for YUV444 mode they

are Y data bits, for Y/C mode they are Y (Luma)

data bits and for BT.656 mode they are

multiplexed Y/Cb/Cr (Luma and Chroma) data

bits. These signals are not used in 8/16/24-bit

modes

VOUT[0]_G_Y_YC[0]/

VOUT[1]_VSYNC/

VIN[1]B_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1],

VIN[1]B

PINCTRL29

AP9

O

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-26. Video Output 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

VOUT[0]_B_CB_C[9]

VOUT[0]_B_CB_C[8]

VOUT[0]_B_CB_C[7]

VOUT[0]_B_CB_C[6]

VOUT[0]_B_CB_C[5]

VOUT[0]_B_CB_C[4]

VOUT[0]_B_CB_C[3]

VOUT[0]_B_CB_C[2]

AT12

O

PINCTRL117

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

AH13

AM13

AJ13

AK13

AN13

AL13

AP13

AT9

O

PINCTRL116

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL115

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

Video Output 0 Data. These signals represent the

8 MSBs of B/CB/C video data. For RGB mode

they are blue data bits, for YUV444 mode they are

Cb (Chroma) data bits, for Y/C mode they are

multiplexed Cb/Cr (Chroma) data bits and for

BT.656 mode they are unused

-

PINCTRL114

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL113

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL112

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL111

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

-

PINCTRL110

VOUT[0]_B_CB_C[1]/

VOUT[1]_HSYNC/

VOUT[1]_AVID

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]

PINCTRL28

Video Output 0 Data. These signals represent the

2 LSBs of B/CB/C video data for 20-bit and 30-bit

video modes (VOUT[0] only). For RGB mode they

are blue data bits, for YUV444 mode they are Cb

(Chroma) data bits, for Y/C mode they are

multiplexed Cb/Cr (Chroma) data bits and for

BT.656 mode they are unused. These signals are

not used in 16/24-bit modes.

VOUT[0]_R_CR[9]/

VOUT[0]_B_CB_C[1]/

VOUT[1]_Y_YC[9]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL125

AU9

VOUT[0]_B_CB_C[0]/

VOUT[1]_C[9]/

VIN[1]B_HSYNC_DE

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1],

VIN[1]B

PINCTRL27

AR9

VOUT[0]_R_CR[8]/

VOUT[0]_B_CB_C[0]/

VOUT[1]_Y_YC[8]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL124

AK10

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Table 3-26. Video Output 0 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

VOUT[0]_R_CR[9]/

VOUT[0]_B_CB_C[1]/

VOUT[1]_Y_YC[9]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL125

AU9

O

VOUT[0]_R_CR[8]/

VOUT[0]_B_CB_C[0]/

VOUT[1]_Y_YC[8]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL124

AK10

AL10

AU10

AT10

AG13

AR11

AT11

AT8

O

VOUT[0]_R_CR[7]/

VOUT[0]_G_Y_YC[1]/

VOUT[1]_Y_YC[7]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL123

VOUT[0]_R_CR[6]/

VOUT[0]_G_Y_YC[0]/

VOUT[1]_Y_YC[6]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL122

Video Output 0 Data. These signals represent the

8 MSBs of R/CR video data. For RGB mode they

are red data bits, for YUV444 mode they are Cr

(Chroma) data bits, for Y/C mode and BT.656

modes they are unused.

VOUT[0]_R_CR[5]/

VOUT[0]_AVID/

VOUT[1]_Y_YC[5]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL121

VOUT[0]_R_CR[4]/

VOUT[0]_FLD/

VOUT[1]_Y_YC[4]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL120

VOUT[0]_R_CR[3]/

VOUT[0]_VSYNC/

VOUT[1]_Y_YC[3]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL119

VOUT[0]_R_CR[2]/

VOUT[0]_HSYNC/

VOUT[1]_Y_YC[2]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL118

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

Video Output 0 Data. These signals represent the

2 LSBs of R/CR video data for 30-bit video modes

(VOUT[0] only). For RGB mode they are red data

bits, for YUV444 mode they are Cr (Chroma) data

bits, for Y/C mode and BT.656 modes they are

unused. These signals are not used in 24-bit

mode.

-

VOUT[0]_R_CR[1]

PINCTRL40

VOUT[0]_R_CR[0]/

VOUT[1]_C[8]/

VOUT[1]_CLK

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]

PINCTRL26

AJ11

O

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VOUT[0]_VSYNC

AN9

AR11

AM9

AT11

AL9

O

PINCTRL37

Video Output 0 Vertical Sync output. This is the

discrete vertical synchronization output. This

signal is not used for embedded sync modes.

VOUT[0]_R_CR[3]/

VOUT[0]_VSYNC/

VOUT[1]_Y_YC[3]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL119

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VOUT[0]_HSYNC

PINCTRL36

Video Output 0 Horizontal Sync output. This is the

discrete horizontal synchronization output. This

signal is not used for embedded sync modes.

VOUT[0]_R_CR[2]/

VOUT[0]_HSYNC/

VOUT[1]_Y_YC[2]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL118

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VOUT[0]_FLD

PINCTRL38

Video Output 0 Field ID output. This is the discrete

field identification output. This signal is not used

for embedded sync modes.

VOUT[0]_R_CR[4]/

VOUT[0]_FLD/

VOUT[1]_Y_YC[4]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL120

AG13

AR8

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

-

VOUT[0]_AVID

PINCTRL39

Video Output 0 Active Video output. This is the

discrete active video indicator output. This signal

is not used for embedded sync modes.

VOUT[0]_R_CR[5]/

VOUT[0]_AVID/

VOUT[1]_Y_YC[5]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL121

AT10

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Table 3-27. Video Output 1 Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

VOUT[0]_R_CR[0]/

VOUT[1]_C[8]/

VOUT[1]_CLK

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL26

AJ11

O

Video Output 1 Clock output

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_CLK/

VIN[1]A_CLK

VIN[1]A

PINCTRL46

AT7

AU9

O

VOUT[0]_R_CR[9]/

VOUT[0]_B_CB_C[1]/

VOUT[1]_Y_YC[9]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL125

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[9]/

VIN[1]A_D[7]

VIN[1]A

PINCTRL19

AP6

VOUT[0]_R_CR[8]/

VOUT[0]_B_CB_C[0]/

VOUT[1]_Y_YC[8]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL124

AK10

AT6

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[8]/

VIN[1]A_D[6]

VIN[1]A

PINCTRL18

Video Output 1 Data. These signals represent the

8 bits of Y/YC video data. For Y/C mode they are

Y (Luma) data bits and for BT.656 mode they are

multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

VOUT[0]_R_CR[7]/

VOUT[0]_G_Y_YC[1]/

VOUT[1]_Y_YC[7]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL123

AL10

AR6

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[7]/

VIN[1]A_D[5]

VIN[1]A

PINCTRL17

VOUT[0]_R_CR[6]/

VOUT[0]_G_Y_YC[0]/

VOUT[1]_Y_YC[6]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL122

AU10

AC13

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[6]/

VIN[1]A_D[4]

VIN[1]A

PINCTRL16

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-27. Video Output 1 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

VOUT[0]_R_CR[5]/

VOUT[0]_AVID/

VOUT[1]_Y_YC[5]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL121

AT10

O

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[5]/

VIN[1]A_D[3]

VIN[1]A

PINCTRL50

AJ7

AG13

AU6

AR11

AP7

O

VOUT[0]_R_CR[4]/

VOUT[0]_FLD/

VOUT[1]_Y_YC[4]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL120

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[4]/

VIN[1]A_D[2]

VIN[1]A

PINCTRL49

Video Output 1 Data. These signals represent the

8 bits of Y/YC video data. For Y/C mode they are

Y (Luma) data bits and for BT.656 mode they are

multiplexed Y/Cb/Cr (Luma and Chroma) data

bits.

VOUT[0]_R_CR[3]/

VOUT[0]_VSYNC /

VOUT[1]_Y_YC[3]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL119

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[3]

VIN[1]A_D[1]

VIN[1]A

PINCTRL48

VOUT[0]_R_CR[2]/

VOUT[0]_HSYNC/

VOUT[1]_Y_YC[2]

PULL: IPD / DIS

DRIVE: L / L

DVDD_3P3

VOUT[0]

PINCTRL118

AT11

AU7

AR9

AK4

PULL: IPD / DIS

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_Y_YC[2]/

VIN[1]A_D[0]

VIN[1]A

PINCTRL47

VOUT[0]_B_CB_C[0]/

VOUT[1]_C[9]/

VIN[1]B_HSYNC_DE

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VIN[1]B

PINCTRL27

VIN[0]A_D[19]/

VIN[1]A_DE/

VOUT[1]_C[9]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VIN[1]A

VIN[0]A_D[18]/

VIN[1]A_FLD/

VOUT[1]_C[8]

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VIN[1]A

PINCTRL24

AK5

VOUT[0]_R_CR[0]/

VOUT[1]_C[8]/

VOUT[1]_CLK

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL26

AJ11

AD13

AN8

AP8

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[7]/

VIN[1]A_D[13]

VIN[1]A

PINCTRL10

Video Output 1 Data. These signals represent the

8 bits of C video data. For Y/C mode they are

multiplexed Cb/Cr (Chroma) data bits, and for

BT.656 mode they are unused.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[6]/

VIN[1]A_D[12]

VIN[1]A

PINCTRL9

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[5]/

VIN[1]A_D[11]

VIN[1]A

PINCTRL8

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[4]/

VIN[1]A_D[10]

VIN[1]A

PINCTRL7

AN7

AM8

AK6

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[3]/

VIN[1]A_D[9]/

VIN[1]A

PINCTRL6

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_C[2]/

VIN[1]A_D[8]

VIN[1]A

PINCTRL20

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Table 3-27. Video Output 1 Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

MUXED

DESCRIPTION

NO.

VOUT[0]_G_Y_YC[0]/

VOUT[1]_VSYNC/

VIN[1]B_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VIN[1]B

PINCTRL29

AP9

O

Video Output 1 Vertical Sync output. This is the

discrete vertical synchronization output. This

signal is not used for embedded sync modes

VIN[0]A_D[17]/

VIN[1]A_VSYNC/

VOUT[1]_VSYNC

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VIN[1]A

PINCTRL23

AL5

AT9

AR5

AT5

AU8

AT9

AT4

O

VOUT[0]_B_CB_C[1]/

VOUT[1]_HSYNC/

VOUT[1]_AVID

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL28

Video Output 1 Horizontal Sync output. This is the

discrete horizontal synchronization output. This

signal is not used for embedded sync modes.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_HSYNC/

VIN[1]A_D[15]

VIN[1]A

PINCTRL21

VIN[0]A_D[16]/

VIN[1]A_HSYNC/

VOUT[1]_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VIN[0]A,

VIN[1]A

PINCTRL22

Video Output 1 Field ID output. This is the discrete

field identification output. This signal is not used

for embedded sync modes.

VOUT[0]_G_Y_YC[1]/

VOUT[1]_FLD/

VIN[1]B_FLD

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VIN[1]B

PINCTRL30

VOUT[0]_B_CB_C[1]/

VOUT[1]_HSYNC/

VOUT[1]_AVID

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[0],

VOUT[1]

PINCTRL28

Video Output 1 Active Video output. This is the

discrete active video indicator output. This signal

is not used for embedded sync modes.

PULL: IPD / IPD

DRIVE: Z / Z

DVDD_3P3

VOUT[1]_AVID/

VIN[1]B_CLK

VIN[1]B

PINCTRL31

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3.2.21 Analog Video Output Signals

Table 3-28. Analog Video Output Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER

DESCRIPTION

NO.

When a specific Video DAC output [IOUTA - IOUTG] is powered down, the corresponding Analog Video Output terminal functions

should be left unconnected.

IOUTA

IOUTB

IOUTC

IOUTD

IOUTE

IOUTF

IOUTG

AT21

AR21

AP21

AR20

AT19

AT20

AU20

O

-

Video DAC A output. Analog HD Video DAC (G/Y)

Video DAC B output. Analog HD Video DAC (B/Pb)

Video DAC C output. Analog HD Video DAC (R/Pr)

Video DAC D output. Analog SD Video DAC

Video DAC E output. Analog SD Video DAC

Video DAC F output. Analog SD Video DAC

Video DAC G output. Analog SD Video DAC

Video DAC reference voltage (0.5 V).

VDAC_VREF

AH19

I

-

When the video DACs are powered down, this pin should be left

unconnected.

Video DAC HD current bias connection. This pin must be connected via

an external 1.2-kΩ resistor to VSSA_HD.

VDAC_RBIAS_HD

AE22

I/O

-

When the HD DACs are powered down, this pin should be left

unconnected.

Video DAC SD current bias connection. This pin must be connected via

an external 1.2-kΩ resistor to VSSA_SD.

VDAC_RBIAS_SD

AP19

I/O

-

When the SD DACs are powered down, this pin should be left

unconnected.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

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3.2.22 Reserved Pins

Table 3-29. Reserved Terminal Functions

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

DESCRIPTION

NO.

AB36

P25

RSV1

RSV2

RSV3

RSV4

RSV5

RSV6

RSV7

RSV8

RSV9

RSV10

RSV11

O

-

Reserved. (Leave unconnected, do not connect to power or ground.)

N19

N20

T28

O

I/O

O

T27

AE23

D24

AU37

N28

N29

O

I

I/O

Reserved. For proper device operation, this pin must be tied directly to

the 1.8-V supply.

RSV12

RSV13

RSV14

RSV15

AG25

AG24

AH25

AH24

S

-

Reserved. For proper device operation, this pin must be tied directly to

the 1.8-V supply.

Reserved. For proper device operation, this pin must be tied directly to

the 1.8-V supply.

Reserved. For proper device operation, this pin must be tied directly to

the 1.8-V supply.

Reserved. For proper device operation, this pin must be tied directly to

RSV16

RSV17

RSV18

R34

P34

P33

I

-

V_SS

.

O

S

Reserved. (Leave unconnected, do not connect to power or ground.)

Reserved. For proper device operation, this pin must be tied directly to

the 1.8-V supply.

Reserved. For proper device operation, this pin must be tied directly to

RSV19

P32

GND

-

V_SS

.

RSV20

RSV21

RSV22

D14

O

-

Reserved. (Leave unconnected, do not connect to power or ground.)

AN18

AN19

IPD

DVDD_3P3

RSV23

RSV24

RSV25

RSV26

RSV27

RSV28

RSV29

RSV30

AP2

AU3

AN2

AT1

AR1

AP1

AM2

AL2

I

Reserved. (Leave unconnected, do not connect to power or ground.)

IPD

DVDD_3P3

IPD

DVDD_3P3

I

IPD

DVDD_3P3

I

IPD

DVDD_3P3

I

DIS

DVDD_3P3

O

DIS

DVDD_3P3

DIS

DVDD_3P3

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2) IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled. This represents the default state of the

internal pull after reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown

resistors are required, see Section 4.2.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal.

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Table 3-29. Reserved Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

DESCRIPTION

NO.

DIS

DVDD_3P3

RSV31

RSV32

RSV33

RSV34

RSV35

RSV36

RSV37

RSV38

RSV39

AK1

O

I

Reserved. (Leave unconnected, do not connect to power or ground.)

DIS

DVDD_3P3

AL1

IPD

DVDD_3P3

AM29

AL28

AL29

AN29

AP29

AR29

AT29

IPD

DVDD_3P3

I

IPD

DVDD_3P3

I

IPD

DVDD_3P3

I

IPD

DVDD_3P3

I

DIS

DVDD_3P3

O

DIS

DVDD_3P3

DIS

DVDD_3P3

RSV40

RSV41

RSV42

AT28

AU21

AJ1

O

Reserved. (Leave unconnected, do not connect to power or ground.)

-

IPU

DVDD_3P3

I/O

IPU

DVDD_3P3

RSV43

RSV44

RSV45

RSV46

RSV47

RSV48

RSV49

RSV50

RSV51

RSV52

RSV53

RSV54

RSV55

RSV56

RSV57

RSV58

AK2

AH8

AJ2

I/O

Reserved. (Leave unconnected, do not connect to power or ground.)

DIS

DVDD_3P3

O

DIS

DVDD_3P3

O

DIS

DVDD_3P3

AK3

O

DIS

DVDD_3P3

AJ3

O

IPD

DVDD_3P3

AJ4

I

IPD

DVDD_3P3

AJ5

I

IPD

DVDD_3P3

AJ6

I

IPD

DVDD_3P3

AB13

AE21

AG22

AG23

AH23

I

S

Reserved. For proper device operation, this pin should be connected to a

1.0-V power supply.

-

Reserved. For proper device operation, this pin should be connected to a

1.8-V power supply.

S

Reserved. For proper device operation, this pin should be connected to a

1.8-V power supply.

S

Reserved. For proper device operation, this pin should be connected to a

1.8-V power supply.

S

Reserved. For proper device operation, this pin should be connected to a

1.8-V power supply.

AJ23

AK22

S

Reserved. For proper device operation, this pin must be tied directly to

GND

V_SS

Reserved. For proper device operation, this pin must be tied directly to

V_SS

.

AL22

.

Device Pins

95

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Table 3-29. Reserved Terminal Functions (continued)

SIGNAL

NAME

TYPE⁽¹⁾

OTHER^{(2) (3)}

DESCRIPTION

NO.

AM22

Reserved. For proper device operation, this pin must be tied directly to

RSV59

RSV60

RSV61

GND

-

V_SS

Reserved. For proper device operation, this pin must be tied directly to

V_SS

.

AM21

AN21

.

Reserved. For proper device operation, this pin must be tied directly to

V_SS

.

96

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3.2.23 Supply Voltages

Table 3-30. Supply Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER

DESCRIPTION

Reference Power Supply DDR[0]:

NAME

NO.

VREFSSTL_DDR[0]

A17

A21

S

-

•

0.75-V for DDR3 memory type

0.9-V for DDR2 memory type

Reference Power Supply DDR[1]

VREFSSTL_DDR[1]

S

-

•

0.75-V for DDR3 memory type

0.9-V for DDR2 memory type

AD22, AD21,

AD20, AD19,

AD18, AD17,

AD16, AC22,

AC21, AC20,

AC19, AC18,

AC17, AC16,

AB24, AB23,

AB22, AB21,

AB20, AB19,

AB18, AB17,

AB16, AB15,

AB14, T24,

CVDD

S

-

Variable Core Voltage Supply for the Always ON Domain

T23, T22, T21,

T20, T19, T18,

T17, T16, T15,

T14, R22, R21,

R20, R19, R18,

R17, R16, P22,

P21, P20, P19,

P18, P17, P16

AE25, AE13,

AD24, AD23,

AD15, AD14,

AC24, AC23,

AC15, AC14,

R24, R23, R15,

R14, P24, P23,

P15, P14, N25,

N13

CVDDC

S

-

1.0-V Constant Power Supply for Memories and PLLs

0.9-V Power Supply for USB PHYs.

VDD_USB_0P9

VDDT_SATA

N27

S

-

Note: If the USB is not used, for proper device operation, this pin

must be connected to a power supply (0.9 V or CVDDC).

1.0-V Power Supply for SATA Termination and Analog Front End

Note: If the SATA is not used, for proper device operation, these

pins must be connected to a 1.0-V power supply.

Y34, Y33, V34,

V32

1.0-V Power Supply for PCIe Termination and Analog Front End

Note: If the PCIe is not used, these pins should be connected to

a 1.0-V power supply.

Y30, Y28, AB32,

AB29, AB27

VDDT_PCIE

VDDA_PLL

VDDA_HDMI

S

-

B18, A18

1.5-V Analog Power Supply for PLLs

AR27, AP24,

AP23,

AN24, AN23

1.0-V Analog Power Supply for HDMI

Note: If the HDMI is not used, these pins should be connected to

a 1.0-V power supply.

1.0-V Analog Power Supply for VDAC HD DAC

Note: If the HD DAC is not used, this pin should be connected to

a 1.0-V power supply.

VDDA_HD_1P0

VDDA_SD_1P0

AG21

AG20

S

-

1.0-V Analog Power Supply for VDAC SD DAC

Note: If the SD DAC is not used, this pin should be connected to

a 1.0-V power supply.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

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Table 3-30. Supply Terminal Functions (continued)

SIGNAL

TYPE⁽¹⁾

OTHER

DESCRIPTION

NAME

VDDR_SATA

NO.

1.5-V Regulator Power Supply for SATA

Note: If the SATA is not used, for proper device operation, these

pins must be connected to a 1.5-V power supply.

V25, U25

S

-

1.5-V Regulator Power Supply for PCIe

VDDR_PCIE

Y25, W25

S

-

Note: If the PCIe is not used, for proper device operation, these

pins must be connected to a 1.5-V power supply.

L19, L18, L17,

L16, L15, L14,

K19, K18, K17,

K16, K15, K14,

J18, J17, J16,

J15, J14, E11,

A11, E1, A2

Power Supply for DDR[0] I/Os:

DVDD_DDR[0]

•

1.5-V for DDR3 memory type

1.8-V for DDR2 memory type

L24, L23, L22,

L21, L20, K24,

K23, K22, K21,

K20, J24, J23,

J22, J21, J20,

J19, E27, D37,

A36, A27

1.5-V Power Supply for DDR[1] I/Os:

DVDD_DDR[1]

S

-

•

1.5-V for DDR3 memory type

1.8-V for DDR2 memory type

1.8-V Power Supply for Device Oscillator

DEVOSC_DVDD18

VDD_USB0_1P8

E19

S

-

Note: If the oscillator is not used, this pin should be connected to

the 1.8-V power supply (DVDD1P8).

1.8-V Power Supply for USB0

Note: If the USB is not used, for proper device operation, this pin

must be connected to a 1.8-V power supply, or when the USB

PHY is not used, this pin can be optionally connected to CVDDC.

R25

1.8-V Power Supply for USB1

Note: If the USB is not used, for proper device operation, this pin

must be connected to a 1.8-V power supply, or when the USB

PHY is not used, this pin can be optionally connected to CVDDC.

VDD_USB1_1P8

T25

S

-

DVDD1P8

AJ20, AJ24

AT22

S

-

1.8-V Power Supply

1.8-V Reference Power Supply for VDAC

Note: If the VDAC is not used, these pins should be connected

to a 1.8-V power supply.

VDDA_REF_1P8

1.8-V Analog Power Supply for VDAC HD DAC

Note: If the HD DAC is not used, these pins should be

connected to a 1.8-V power supply.

VDDA_HD_1P8

VDDA_SD_1P8

AJ22, AH22

S

-

1.8-V Analog Power Supply for VDAC SD DAC

Note: If the SD DAC is not used, these pins should be connected

to a 1.8-V power supply.

AJ21, AH21,

AH20

98

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Table 3-30. Supply Terminal Functions (continued)

SIGNAL

TYPE⁽¹⁾

OTHER

DESCRIPTION

NAME

NO.

AU29, AU11,

AU2,

AN37, AN27,

AN11,

AN1, AJ17,

AJ16,

AJ15, AJ14,

AH17,

AH16, AH15,

AH14,

AG33, AG17,

AG16,

AG15, AG14,

AE29,

AE28, AE27,

AD29,

AD28, AD27,

AD11,

AD10, AD9,

AC29,

DVDD_3P3

S

-

3.3-V Power Supply

AC28, AC27,

AC11,

AC10, AC9,

AB11,

AB10, AB9,

AA11,

AA10, AA9,

AA1,

Y9, U11, U10,

U9, T11, T10,

T9, R28, R27,

R11, R10, R9,

P30, P29, P28,

P27, P11, P10,

P9, P8, L35,

L30, L5, L1

VDD_USB0_3P3

VDD_USB1_3P3

T29, R29

T30, R30

S

-

3.3-V Power Supply for USB0

3.3-V Power Supply for USB1

Device Pins

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3.2.24 Ground Pins (V_SS)

Table 3-31. Ground Terminal Functions

SIGNAL

TYPE⁽¹⁾

OTHER

DESCRIPTION

NAME

NO.

AU28, AU23, AU12,

AU1, AT23, AR25,

AR24, AR23, AR15,

AP37, AP15, AN15,

AN14, AM31, AM25,

AM24, AM23, AM19,

AM18, AM17, AM16,

AM15, AM7, AM1,

AL32, AL31, AL24,

AL23, AL19, AL18,

AL17, AL16, AL15,

AL7, AL6, AK27, AK24,

AK23, AK19, AK18,

AK17, AK16, AK15,

AK11, AJ25, AJ18,

AG30, AG26, AG12,

AG8, AG5, AF27,

AF11, AE20, AE19,

AE18, AE17, AD34,

AD33, AD32, AD31,

AD30, AD7, AD6, AD5,

AC34, AC33, AC32,

AC31, AC30, AC8,

AC7, AC6, AC4, AC3,

AB37, AB35, AB8, AB7,

AB6, AB1, AA24, AA23,

AA22, AA21, AA20,

AA19, AA18, AA17,

AA16, AA15, AA14,

AA13, AA8, AA7, AA6,

AA5, Y37, Y36, Y32,

Y31, Y24, Y23, Y22,

Y21, Y20, Y19, Y18,

Y17, Y16, Y15, Y14,

Y13, Y8, Y7, Y6, Y5,

Y4, W24, W23, W22,

W21, W20, W19, W18,

W17, W16

VSS

GND

-

Ground (GND)

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

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Table 3-31. Ground Terminal Functions (continued)

SIGNAL

TYPE⁽¹⁾

OTHER

DESCRIPTION

NAME

NO.

W15, W14, W13, W9,

W8, W7, W6, V28, V27,

V24, V23, V22, V21,

V20, V19, V18, V17,

V16, V15, V14, V13,

V9, V8, V7, V6, V5, V4,

U24, U23, U22, U21,

U20, U18, U17, U16,

U15, U14, U13, U8, U7,

U6, U5, T35, T34, T33,

T8, T7, T6, R33, R32,

R31, R8, R7, R6, R4,

R3, P31, P7, P6, P5,

P4, N18, M27, M11,

L33, L26, L12, L8, K37,

K1, H27, H24, H23,

H22, H21, H20, H19,

H18, H17, H16, H15,

H14, H11, G32, G31,

G24, G23, G22, G21,

G20, G18, G17, G16,

G15, G14, G7, G6,

F31, F24, F23, F22,

F21, F17, F16, F15,

F14, F7, E37, E24,

E14, D1, C23, C21,

C17, C15, A37, A28,

A10, A1

VSS

GND

-

Ground (GND)

VSSA_PLL

VSSA_HD

U19, B20, A20

GND

-

Analog GND for PLLs

AK21, AK20, AL21

Analog GND for VDAC HD DAC

AU19, AM20, AN20,

AL20

VSSA_SD

GND

-

Analog GND for VDAC SD DAC

VSSA_REF_1P8

DEVOSC_VSS

AU22

B19

GND

-

Reference GND for VDAC (1.8 V)

Ground for Device Oscillator

Device Pins

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4 Device Configurations

4.1 Control Module

The device control module includes status and control logic not addressed within the peripherals or the

remainder of the device infrastructure. This module is the primary point of control for the following areas of

the device:

•

Functional I/O multiplexing

Device status

Static device configuration

OCP interface for standard and customer programmable e-Fuse bit shift registers.

The control module primarily implements a bank of registers accessible (read/write) by the software along

with some read-only registers carrying status information. Most register bits are exported as control

signals for other logic blocks on the device. Certain control module registers have default values based

upon the device type as decoded from e-Fuse.

The read/write registers can be divided into the following classes:

•

Static device configuration registers

Status and configuration registers

Boot registers

Table 4-1 shows the general register groupings and Table 4-2 through Table 4-4 provide register

summaries for each group.

Table 4-1. Control Module Register Map

ADDRESS OFFSET

0x0000 - 0x0020

0x0024 - 0x003C

0x0040 – 0x00FC

0x0300 - 0x03FC

0x0400 - 0x05FC

0x0600 - 0x07FC

0x0800 - 0x0FFC

REGISTER GROUP

OCP Configuration registers

Reserved

SEE

Table 4-2

Device Boot registers

Reserved

Table 4-6

PLL Control registers

Device Configuration registers

PAD Control registers

Table 4-3

Table 4-4

Section 4.4

Table 4-2. OCP Configuration Registers Summary

HEX ADDRESS

0x4814 0000

ACRONYM

REGISTER NAME

CONTROL_REVISION

Control module Revision number

Reserved

0x4814 0004 - 0x4814 000C

0x4814 0010

-

CONTROL_SYSCONFIG

-

Idle mode parameters

Reserved

0x4814 0014 - 0x4814 003C

Table 4-3. PLL Control Registers Summary

HEX ADDRESS

0x4814 0400

0x4814 0404

0x4814 0408

0x4814 040C

0x4814 0410

0x4814 0414

ACRONYM

REGISTER NAME

MAINPLL_CTRL

MAINPLL_PWD

MAINPLL_FREQ1

MAINPLL_DIV1

MAINPLL_FREQ2

MAINPLL_DIV2

Main PLL base frequency control

Main PLL clock output powerdown

Main Clock 1 fractional divider

Main Clock 1 post divider

Main Clock 2 fractional divider

Main Clock 2 post divider

102

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Table 4-3. PLL Control Registers Summary (continued)

HEX ADDRESS

0x4814 0418

0x4814 041C

0x4814 0420

0x4814 0424

0x4814 0428

0x4814 042C

0x4814 0430

0x4814 0434

0x4814 0438

0x4814 043C

0x4814 0440

0x4814 0444

0x4814 0448

0x4814 044C

0x4814 0450

0x4814 0454

0x4814 0458

0x4814 045C

0x4814 0460

0x4814 0464

0x4814 0468

0x4814 046C

0x4814 0470

0x4814 0474

0x4814 0478

0x4814 047C

0x4814 0480

0x4814 0484

0x4814 0488

0x4814 048C

ACRONYM

MAINPLL_FREQ3

MAINPLL_DIV3

MAINPLL_FREQ4

MAINPLL_DIV4

MAINPLL_FREQ5

MAINPLL_DIV5

-

REGISTER NAME

Main Clock 3 fractional divider

Main Clock 3 post divider

Main Clock 4 fractional divider

Main Clock 4 post divider

Main Clock 5 fractional divider

Main Clock 5 post divider

Reserved

MAINPLL_DIV6

-

Main Clock 6 post divider

Reserved

MAINPLL_DIV7

DDRPLL_CTRL

DDRPLL_PWD

-

Main Clock 7 post divider

DDR PLL base frequency control

DDR PLL clock output powerdown

Reserved

DDR_PLL_DIV1

DDRPLL_FREQ2

DDR_PLL_DIV2

DDRPLL_FREQ3

DDR_PLL_DIV3

DDRPLL_FREQ4

DDR_PLL_DIV4

DDRPLL_FREQ5

DDR_PLL_DIV5

VIDEOPLL_CTRL

VIDEOPLL_PWD

VIDEOPLL_FREQ1

VIDEOPLL_DIV1

VIDEOPLL_FREQ2

VIDEOPLL_DIV2

VIDEOPLL_FREQ3

VIDEOPLL_DIV3

-

DDR Clock 1 post divider

DDR Clock 2 fractional divider

DDR Clock 2 post divider

DDR Clock 3 fractional divider

DDR Clock 3 post divider

DDR Clock 4 fractional divider

DDR Clock 4 post divider

DDR Clock 5 fractional divider

DDR Clock 5 post divider

Video PLL base frequency control

Video PLL clock output powerdown

Video Clock 1 fractional divider

Video Clock 1 post divider

Video Clock 2 fractional divider

Video Clock 2 post divider

Video Clock 3 fractional divider

Video Clock 3 post divider

Reserved

0x4814 0490 - 0x4814 049C

0x4814 04A0

AUDIOPLL_CTRL

AUDIOPLL_PWD

-

Audio PLL base frequency control

Audio PLL clock output powerdown

Reserved

0x4814 04A4

0x4814 04A8

0x4814 04AC

-

Reserved

0x4814 04B0

AUDIOPLL_FREQ2

AUDIOPLL_DIV2

AUDIOPLL_FREQ3

AUDIOPLL_DIV3

AUDIOPLL_FREQ4

AUDIOPLL_DIV4

AUDIOPLL_FREQ5

AUDIOPLL_DIV5

-

Audio Clock 2 fractional divider

Audio Clock 2 post divider

Audio Clock 3 fractional divider

Audio Clock 3 post divider

Audio Clock 4 fractional divider

Audio Clock 4 post divider

Audio Clock 5 fractional divider

Audio Clock 5 post divider

Reserved

0x4814 04B4

0x4814 04B8

0x4814 04BC

0x4814 04C0

0x4814 04C4

0x4814 04C8

0x4814 04CC

0x4814 04D0 - 0x4814 05FC

Device Configurations

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Table 4-4. Device Configuration Registers Summary

HEX ADDRESS

0x4814 0600

ACRONYM

DEVICE_ID

REGISTER NAME

Device Identification

Reserved

0x4814 0604

-

0x4814 0608

INIT_PRESSURE_0

INIT_PRESSURE_1

TPTC_CFG

L3 Initiator Pressure

Transfer Controller Configuration

DDR Interface Control

Reserved

0x4814 060C

0x4814 0614

0x4814 0618

DDR_CTRL

0x4814 061C

0x4814 0620

-

USB_CTRL

USB Control

0x4814 0624

USBPHY_CTRL0

-

USB0 Phy Control

0x4814 0628

Reserved

0x4814 062C

0x4814 0630

USBPHY_CTRL1

MAC_ID0_LO

MAC_ID0_HI

MAC_ID1_LO

MAC_ID1_HI

PCIE_CFG

USB1 Phy Control

Ethernet MAC Address 0

Ethernet MAC Address 1

PCIe Module Configuration

Reserved

0x4814 0634

0x4814 0638

0x4814 063C

0x4814 0640

0x4814 0644

-

0x4814 0648

CLK_CTRL

Input Oscillator Control

Audio Control

0x4814 064C

0x4814 0650

AUDIO_CTRL

-

Reserved

0x4814 0654

OCMEM_SLEEP

-

On-Chip Memory Sleep Mode Configuration

Reserved

0x4814 0658 - 0x4814 065C

0x4814 0660

HD_DAC_CTRL

HD_DACA_CAL

HD_DACB_CAL

HD_DACC_CAL

SD_DAC_CTRL

SD_DACA_CAL

SD_DACB_CAL

SD_DACC_CAL

SD_DACD_CAL

BANDGAP_CTRL

HW_EVT_SEL_GRP1

HW_EVT_SEL_GRP2

HW_EVT_SEL_GRP3

HW_EVT_SEL_GRP4

-

HD DAC Control

0x4814 0664

HD DAC A Calibration

HD DAC B Calibration

HD DAC C Calibration

SD DAC Control

0x4814 0668

0x4814 066C

0x4814 0670

0x4814 0674

SD DAC A Calibration

SD DAC B Calibration

SD DAC C Calibration

SD DAC D Calibration

DAC Band-gap Control

System Trace Hardware Event Select Group 1

System Trace Hardware Event Select Group 2

System Trace Hardware Event Select Group 3

System Trace Hardware Event Select Group 4

Reserved

0x4814 0678

0x4814 067C

0x4814 0680

0x4814 068C

0x4814 0690

0x4814 0694

0x4814 0698

0x4814 069C

0x4814 06A0 - 0x4814 06F4

0x4814 06F8

0x4814 06FC

0x4814 0700

HDMI_OBSCLK_CTRL

SERDES_CTRL

UCB_CLK_CTL

PLL_OBSCLK_CTRL

-

HDMI Observe Clock Control

Serdes Control

USB Clock Control

0x4814 0704

PLL Observe Clock Control

Reserved

0x4814 0708

0x4814 070C

0x4814 0710 - 0x4814 07FC

DDR_RCD

RCD Power Enable/Disable

Reserved

-

104

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4.2 Debugging Considerations

4.2.1 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not

floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and

internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external

pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

•

Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external

pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired

value/state.

•

Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external

pullup/pulldown resistor to pull the signal to the opposite rail.

For the boot and configuration pins (listed in Table 3-1, Boot Terminal Functions), if they are both routed

out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be

implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the

desired configuration value, providing external connectivity can help ensure that valid logic levels are

latched on these device boot and configuration pins. In addition, applying external pullup/pulldown

resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in

switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

•

Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure

to include the leakage currents of all the devices connected to the net, as well as any internal pullup or

pulldown resistors.

•

Decide a target value for the net. For a pulldown resistor, this should be below the lowest V_ILlevel of

all inputs connected to the net. For a pullup resistor, this should be above the highest V_IHlevel of all

inputs on the net. A reasonable choice would be to target the V_OLor V_OHlevels for the logic family of

the limiting device; which, by definition, have margin to the V_ILand V_IHlevels.

•

Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net

will reach the target pulled value when maximum current from all devices on the net is flowing through

the resistor. The current to be considered includes leakage current plus, any other internal and

external pullup/pulldown resistors on the net.

For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance

value of the external resistor. Verify that the resistance is small enough that the weakest output buffer

can drive the net to the opposite logic level (including margin).

•

Remember to include tolerances when selecting the resistor value.

For pullup resistors, also remember to include tolerances on the DV_DDrail.

For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.

Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration

pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific

application.

For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have

IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users

should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I_I), and the low-/high-level input voltages (V_ILand V_IH), see

Section 6.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature.

Device Configurations

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For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal

functions tables in Section 3.2.

4.3 Boot Sequence

The boot sequence is a process by which the device's memory is loaded with program and data sections,

and by which some of the device's internal registers are programmed with predetermined values. The boot

sequence is started automatically after each device-level global reset. For more details on device-level

global resets, see Section 7.2. There are several methods by which the memory and register initialization

can take place. Each of these methods is referred to as a boot mode. The boot mode to be used is

selected at reset. The device is booted through multiple means—primary bootloaders within internal ROM

or EMIF4, and secondary user bootloaders from peripherals or external memories. The maximum size of

the boot image is 255KB (ROM uses 1KB internally). Boot modes, pin configurations, and register

configurations required for booting the device, are described in the following subsections.

The following boot modes are supported:

•

NOR Flash boot (muxed and non-muxed, 8-bit or 16-bit)

NAND Flash boot (SLC and MLC with BCH ECC, 8-bit or 16-bit)

SPI boot (EEPROM or Flash, SPI mode 3, 24-bit)

SD boot (SD cards)

EMAC boot (TFTP client)

UART boot (X-modem client)

PCIe boot (client mode, PCIe 32 and PCIe 64).

The state of the device after boot is determined by sampling the input states of the BTMODE[4:0] pins

when device reset (POR or RESET) is deasserted. The sampled values are latched into the

CONTROL_STATUS register, which is part of the system configuration (SYSCFG) module.

The BTMODE [4:0] values determine the boot mode order according to Table 4-5. The first boot mode

listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the primary boot

mode fails, the second, third, and fourth boot modes are executed, in that order, until a successful boot is

completed.

Additional boot configuration pins determine the following system boot settings as shown in Table 3-1:

•

GPMC CS0 Default Bus Width

GPMC Wait Enable

GPMC Address/Data Multiplexing.

The GPMC CS0 default operation is determined by the CS0BW, CS0WAIT, and CS0MUX[1:0] inputs.

For more detailed information on booting the device, see the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

106

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Table 4-5. Boot Mode Order

BTMODE[4] = 1

MEMORY BOOTING PREFERRED

BTMODE[4] = 0

PERIPHERAL BOOTING PREFERRED

BTMODE[3:0]

FIRST

XIP⁽¹⁾

XIPWAIT⁽¹⁾

NAND

NANDI2C

SPI

SECOND

UART

NANDI2C

SD

THIRD

EMAC

SPI

FOURTH

SD

FIRST SECOND THIRD FOURTH

RESERVED RESERVED RESERVED RESERVED

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

SD

UART

EMAC

XIPWAIT⁽¹⁾

SD

SPI

NANDI2C

SD

UART

SPI

NAND

XIP⁽¹⁾

NAND

SD

UART

SPI

EMAC

SPI

NANDI2C

EMAC

UART

PCIE_32

PCIE_64

UART

RESERVED RESERVED RESERVED RESERVED

SD

EMAC

SD

SPI

EMAC

SD

SPI

XIP⁽¹⁾

SPI

SD

RESERVED

PCIE_32

PCIE_64

RESERVED RESERVED RESERVED

SPI

SD

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

GP Fast

EMAC

UART

PCIE_32

GP Fast

UART

EMAC

PCIE_64

External Boot

(1) GPMC CS0 eXecute In Place (XIP) and eXecute In Place with Wait Monitoring (XIPWAIT) boot for NOR/OneNAND/ROM. For details,

see the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

4.3.1 Boot Mode Registers

For details on the boot mode registers, see the AM38x Sitara ARM Microprocessors (MPUs) Technical

Reference Manual (literature number SPRUGX7).

Table 4-6. Device Boot Registers Summary

HEX ADDRESS

0x4814 0040

ACRONYM

CONTROL_STATUS

BOOTSTAT

-

REGISTER NAME

Device Status

0x4814 0044

Device Boot Status

Reserved

0x4814 0048 - 0x4814 007C

4.4 Pin Multiplexing Control

Device-level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCTRL1 -

PINCTRL321 registers in the SYSCFG module. The default state for each multiplexed pin is MUXMODE =

0x000.

Pin multiplexing selects which of several peripheral pin functions control the pin's IO buffer output data

values.

The input from each pin is routed to all of the peripherals that share the pin, regardless of the MUXMODE

setting. For details, see the table below and the MUXED column in the each of the Terminal Functions

tables in Section 3.2.

4.4.1 PINCTRLx Register Descriptions

Table 4-7. PINCTRLx Register Definition

Bit

Field

Value Description

Reserved; Read returns 0

31:5

Reserved

Device Configurations

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Table 4-7. PINCTRLx Register Definition (continued)

Bit

Field

Value Description

4

PULLTYPESEL

Pad Pullup/Pulldown Type Selection

Pulldown selected

0

1

Pullup selected

3

PULLDIS

Pad Pullup/Pulldown Disable

Pullup/Pulldown enabled

Pullup/Pulldown disabled

Pad Functional Signal Mux Select

0

1

2:0

MUXMODE

Table 4-8. PINCTRLx Registers

MUXMODE[2:0]

HEX ADDRESS

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 0800

0x4814 0804

0x4814 0808

0x4814 080C

0x4814 0810

0x4814 0814

0x4814 0818

0x4814 081C

0x4814 0820

0x4814 0824

0x4814 0828

0x4814 082C

0x4814 0830

0x4814 0834

0x4814 0838

0x4814 083C

0x4814 0840

0x4814 0844

0x4814 0848

0x4814 084C

0x4814 0850

0x4814 0854

0x4814 0858

0x4814 085C

0x4814 0860

0x4814 0864

0x4814 0868

0x4814 086C

0x4814 0870

0x4814 0874

0x4814 0878

0x4814 087C

0x4814 0880

0x4814 0884

0x4814 0888

0x4814 088C

0x4814 0890

0x4814 0894

0x4814 0898

0x4814 089C

0x4814 08A0

0x4814 08A4

PINCTRL1

PINCTRL2

PINCTRL3

PINCTRL4

PINCTRL5

PINCTRL6

PINCTRL7

PINCTRL8

PINCTRL9

PINCTRL10

PINCTRL11

PINCTRL12

PINCTRL13

PINCTRL14

PINCTRL15

PINCTRL16

PINCTRL17

PINCTRL18

PINCTRL19

PINCTRL20

PINCTRL21

PINCTRL22

PINCTRL23

PINCTRL24

PINCTRL25

PINCTRL26

PINCTRL27

PINCTRL28

PINCTRL29

PINCTRL30

PINCTRL31

PINCTRL32

PINCTRL33

PINCTRL34

PINCTRL35

PINCTRL36

PINCTRL37

PINCTRL38

PINCTRL39

PINCTRL40

PINCTRL41

PINCTRL42

0

1

VOUT[1]_C[3]

VOUT[1]_C[4]

VIN[1]A_D[9]

VIN[1]A_D[10]

VIN[1]A_D[11]

VIN[1]A_D[12]

VIN[1]A_D[13]

VOUT[1]_C[5]

VOUT[1]_C[6]

VOUT[1]_C[7]

VIN[1]A_D[14]

VIN[0]A_D[20]

VIN[0]B_DE

VIN[0]B_FLD

VIN[0]A_D[21]

VIN[0]A_D[22]

VIN[0]B_VSYNC

VIN[0]B_HSYNC

VIN[1]A_D[4]

VIN[0]A_D[23]

VOUT[1]_Y_YC[6]

VOUT[1]_Y_YC[7]

VOUT[1]_Y_YC[8]

VOUT[1]_Y_YC[9]

VOUT[1]_C[2]

VIN[1]A_D[5]

VIN[1]A_D[6]

VIN[1]A_D[7]

VIN[1]A_D[8]

VOUT[1]_HSYNC

VIN[0]A_D[16]

VIN[1]A_D[15]

VIN[1]A_HSYNC

VIN[1]A_VSYNC

VIN[1]A_FLD

VOUT[1]_FLD

VOUT[1]_VSYNC

VOUT[1]_C[8]

VIN[0]A_D[17]

VIN[0]A_D[18]

VIN[0]A_D[19]

VIN[1]A_DE

VOUT[1]_C[9]

VOUT[0]_R_CR[0]

VOUT[0]_B_CB_C[0]

VOUT[0]_B_CB_C[1]

VOUT[0]_G_Y_YC[0]

VOUT[0]_G_Y_YC[1]

VOUT[1]_AVID

VIN[0]A_HSYNC

VIN[0]A_VSYNC

VIN[0]A_FLD

VOUT[1]_C[8]

VOUT[1]_C[9]

VOUT[1]_HSYNC

VOUT[1]_VSYNC

VOUT[1]_FLD

VIN[1]B_CLK

VOUT[1]_CLK

VIN[1]B_HSYNC_DE

VOUT[1]_AVID

VIN[1]B_VSYNC

VIN[1]B_FLD

VIN[0]A_DE

VOUT[0]_HSYNC

VOUT[0]_VSYNC

VOUT[0]_FLD

VOUT[0]_AVID

VOUT[0]_R_CR[1]

108

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Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 08A8

0x4814 08AC

0x4814 08B0

0x4814 08B4

0x4814 08B8

0x4814 08BC

0x4814 08C0

0x4814 08C4

0x4814 08C8

0x4814 08CC

0x4814 08D0

0x4814 08D4

0x4814 08D8

0x4814 08DC

0x4814 08E0

0x4814 08E4

0x4814 08E8

0x4814 08EC

0x4814 08F0

0x4814 08F4

0x4814 08F8

0x4814 08FC

0x4814 0900

0x4814 0904

0x4814 0908

0x4814 090C

0x4814 0910

0x4814 0914

0x4814 0918

0x4814 091C

0x4814 0920

0x4814 0924

0x4814 0928

0x4814 092C

0x4814 0930

0x4814 0934

0x4814 0938

0x4814 093C

0x4814 0940

0x4814 0944

0x4814 0948

0x4814 094C

0x4814 0950

0x4814 0954

0x4814 0958

0x4814 095C

0x4814 0960

0x4814 0964

0x4814 0968

0x4814 096C

0x4814 0970

0x4814 0974

0x4814 0978

0x4814 097C

0x4814 0980

PINCTRL43

PINCTRL44

PINCTRL45

PINCTRL46

PINCTRL47

PINCTRL48

PINCTRL49

PINCTRL50

PINCTRL51

PINCTRL52

PINCTRL53

PINCTRL54

PINCTRL55

PINCTRL56

PINCTRL57

PINCTRL58

PINCTRL59

PINCTRL60

PINCTRL61

PINCTRL62

PINCTRL63

PINCTRL64

PINCTRL65

PINCTRL66

PINCTRL67

PINCTRL68

PINCTRL69

PINCTRL70

PINCTRL71

PINCTRL72

PINCTRL73

PINCTRL74

PINCTRL75

PINCTRL76

PINCTRL77

PINCTRL78

PINCTRL79

PINCTRL80

PINCTRL81

PINCTRL82

PINCTRL83

PINCTRL84

PINCTRL85

PINCTRL86

PINCTRL87

PINCTRL88

PINCTRL89

PINCTRL90

PINCTRL91

PINCTRL92

PINCTRL93

PINCTRL94

PINCTRL95

PINCTRL96

PINCTRL97

0

1

0

1

0

1

0

1

0

VOUT[1]_CLK

VOUT[1]_Y_YC[2]

VOUT[1]_Y_YC[3]

VOUT[1]_Y_YC[4]

VOUT[1]_Y_YC[5]

EMAC[1]_RXCLK

EMAC[1]_RXD[0]

EMAC[1]_RXD[1]

EMAC[1]_RXD[2]

EMAC[1]_RXD[3]

EMAC[1]_RXD[4]

EMAC[1]_RXD[5]

EMAC[1]_RXD[6]

EMAC[1]_RXD[7]

EMAC[1]_RXDV

EMAC[1]_GMTCLK

EMAC[1]_TXD[0]

EMAC[1]_TXD[1]

EMAC[1]_TXD[2]

EMAC[1]_TXD[3]

EMAC[1]_TXD[4]

EMAC[1]_TXD[5]

EMAC[1]_TXD[6]

EMAC[1]_TXD[7]

EMAC[1]_TXEN

EMAC[1]_TXCLK

EMAC[1]_COL

VIN[1]A_CLK

VIN[1]A_D[0]

VIN[1]A_D[1]

VIN[1]A_D[2]

VIN[1]A_D[3]

EMAC[1]_CRS

EMAC[1]_RXER

VIN[0]A_CLK

VIN[0]B_CLK

VIN[0]A_D[0]

VIN[0]A_D[1]

VIN[0]A_D[2]

VIN[0]A_D[3]

VIN[0]A_D[4]

VIN[0]A_D[5]

VIN[0]A_D[6]

VIN[0]A_D[7]

VIN[0]A_D[8]

VIN[0]A_D[9]

VIN[0]A_D[10]

VIN[0]A_D[11]

VIN[0]A_D[12]

Device Configurations

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Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

HEX ADDRESS

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 0984

0x4814 0988

0x4814 098C

0x4814 0990

0x4814 0994

0x4814 0998

0x4814 099C

0x4814 09A0

0x4814 09A4

0x4814 09A8

0x4814 09AC

0x4814 09B0

0x4814 09B4

0x4814 09B8

0x4814 09BC

0x4814 09C0

0x4814 09C4

0x4814 09C8

0x4814 09CC

0x4814 09D0

0x4814 09D4

0x4814 09D8

0x4814 09DC

0x4814 09E0

0x4814 09E4

0x4814 09E8

0x4814 09EC

0x4814 09F0

0x4814 09F4

0x4814 09F8

0x4814 09FC

0x4814 0A00

0x4814 0A04

0x4814 0A08

0x4814 0A0C

0x4814 0A10

0x4814 0A14

0x4814 0A18

0x4814 0A1C

0x4814 0A20

0x4814 0A24

0x4814 0A28

0x4814 0A2C

0x4814 0A30

0x4814 0A34

0x4814 0A38

0x4814 0A3C

0x4814 0A40

0x4814 0A44

0x4814 0A48

0x4814 0A4C

0x4814 0A50

0x4814 0A54

0x4814 0A58

0x4814 0A5C

PINCTRL98

PINCTRL99

0

1

0

VIN[0]A_D[13]

VIN[0]A_D[14]

PINCTRL100

PINCTRL101

PINCTRL102

PINCTRL103

PINCTRL104

PINCTRL105

PINCTRL106

PINCTRL107

PINCTRL108

PINCTRL109

PINCTRL110

PINCTRL111

PINCTRL112

PINCTRL113

PINCTRL114

PINCTRL115

PINCTRL116

PINCTRL117

PINCTRL118

PINCTRL119

PINCTRL120

PINCTRL121

PINCTRL122

PINCTRL123

PINCTRL124

PINCTRL125

PINCTRL126

PINCTRL127

PINCTRL128

PINCTRL129

PINCTRL130

PINCTRL131

PINCTRL132

PINCTRL133

PINCTRL134

PINCTRL135

PINCTRL136

PINCTRL137

PINCTRL138

PINCTRL139

PINCTRL140

PINCTRL141

PINCTRL142

PINCTRL143

PINCTRL144

PINCTRL145

PINCTRL146

PINCTRL147

PINCTRL148

PINCTRL149

PINCTRL150

PINCTRL151

PINCTRL152

VIN[0]A_D[15]

VOUT[0]_CLK

VOUT[0]_G_Y_YC[2]

VOUT[0]_G_Y_YC[3]

VOUT[0]_G_Y_YC[4]

VOUT[0]_G_Y_YC[5]

VOUT[0]_G_Y_YC[6]

VOUT[0]_G_Y_YC[7]

VOUT[0]_G_Y_YC[8]

VOUT[0]_G_Y_YC[9]

VOUT[0]_B_CB_C[2]

VOUT[0]_B_CB_C[3]

VOUT[0]_B_CB_C[4]

VOUT[0]_B_CB_C[5]

VOUT[0]_B_CB_C[6]

VOUT[0]_B_CB_C[7]

VOUT[0]_B_CB_C[8]

VOUT[0]_B_CB_C[9]

VOUT[0]_R_CR[2]

VOUT[0]_R_CR[3]

VOUT[0]_R_CR[4]

VOUT[0]_R_CR[5]

VOUT[0]_R_CR[6]

VOUT[0]_R_CR[7]

VOUT[0]_R_CR[8]

VOUT[0]_R_CR[9]

MCA[0]_ACLKR

MCA[0]_AHCLKR

MCA[0]_AFSR

VOUT[0]_HSYNC

VOUT[0]_VSYNC

VOUT[0]_FLD

VOUT[1]_Y_YC[2]

VOUT[1]_Y_YC[3]

VOUT[1]_Y_YC[4]

VOUT[1]_Y_YC[5]

VOUT[1]_Y_YC[6]

VOUT[1]_Y_YC[7]

VOUT[1]_Y_YC[8]

VOUT[1]_Y_YC[9]

VOUT[0]_AVID

VOUT[0]_G_Y_YC[0]

VOUT[0]_G_Y_YC[1]

VOUT[0]_B_CB_C[0]

VOUT[0]_B_CB_C[1]

MCA[0]_ACLKX

MCA[0]_ACLKHX

MCA[0]_AFSX

MCA[0]_AMUTE

MCA[0]_AXR[0]

MCA[0]_AXR[1]

MCA[0]_AXR[2]

MCB_FSX

MCB_FSR

MCB_DX

MCB_DR

MCA[0]_AXR[3]

MCA[0]_AXR[4]

MCA[0]_AXR[5]

MCA[1]_ACLKR

MCA[1]_AHCLKR

MCA[1]_AFSR

MCA[1]_ACLKX

MCA[1]_ACLKHX

MCA[1]_AFSX

MCA[1]_AMUTE

MCA[1]_AXR[0]

MCA[1]_AXR[1]

MCA[2]_ACLKR

MCA[2]_AHCLKR

MCA[2]_AFSR

MCB_CLKR

MCB_CLKS

MCB_CLKX

MCB_CLKR

MCB_DR

MCB_FSR

MCA[2]_ACLKX

MCA[2]_ACLKHX

110

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Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

REGISTER NAME

PULLTYPESEL

PULLDIS

000

MCA[2]_AFSX

MCA[2]_AMUTE

MCA[2]_AXR[0]

MCA[2]_AXR[1]

SD_POW

001

010

011

0x4814 0A60

0x4814 0A64

0x4814 0A68

0x4814 0A6C

0x4814 0A70

0x4814 0A74

0x4814 0A78

0x4814 0A7C

0x4814 0A80

0x4814 0A84

0x4814 0A88

0x4814 0A8C

0x4814 0A90

0x4814 0A94

0x4814 0A98

0x4814 0A9C

0x4814 0AA0

0x4814 0AA4

0x4814 0AA8

0x4814 0AAC

0x4814 0AB0

0x4814 0AB4

0x4814 0AB8

0x4814 0ABC

0x4814 0AC0

0x4814 0AC4

0x4814 0AC8

0x4814 0ACC

0x4814 0AD0

0x4814 0AD4

0x4814 0AD8

0x4814 0ADC

0x4814 0AE0

0x4814 0AE4

0x4814 0AE8

0x4814 0AEC

0x4814 0AF0

0x4814 0AF4

0x4814 0AF8

0x4814 0AFC

0x4814 0B00

0x4814 0B04

0x4814 0B08

0x4814 0B0C

0x4814 0B10

0x4814 0B14

0x4814 0B18

0x4814 0B1C

0x4814 0B20

0x4814 0B24

0x4814 0B28

0x4814 0B2C

0x4814 0B30

0x4814 0B34

0x4814 0B38

PINCTRL153

PINCTRL154

PINCTRL155

PINCTRL156

PINCTRL157

PINCTRL158

PINCTRL159

PINCTRL160

PINCTRL161

PINCTRL162

PINCTRL163

PINCTRL164

PINCTRL165

PINCTRL166

PINCTRL167

PINCTRL168

PINCTRL169

PINCTRL170

PINCTRL171

PINCTRL172

PINCTRL173

PINCTRL174

PINCTRL175

PINCTRL176

PINCTRL177

PINCTRL178

PINCTRL179

PINCTRL180

PINCTRL181

PINCTRL182

PINCTRL183

PINCTRL184

PINCTRL185

PINCTRL186

PINCTRL187

PINCTRL188

PINCTRL189

PINCTRL190

PINCTRL191

PINCTRL192

PINCTRL193

PINCTRL194

PINCTRL195

PINCTRL196

PINCTRL197

PINCTRL198

PINCTRL199

PINCTRL200

PINCTRL201

PINCTRL202

PINCTRL203

PINCTRL204

PINCTRL205

PINCTRL206

PINCTRL207

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

MCB_CLKS

MCB_FSX

MCB_DX

GPMC_A[14]

GPMC_A[13]

GPMC_A[21]

GPMC_A[20]

GPMC_A[19]

GPMC_A[18]

GPMC_A[17]

GPMC_A[16]

GPMC_A[15]

GP1[0]

GP1[1]

GP1[2]

GP1[3]

GP1[4]

GP1[5]

GP1[6]

GP1[7]

GP1[8]

SD_CLK

SD_CMD

SD_DAT[0]

SD_DAT[1]_SDIRQ

SD_DAT[2]_SDRW

SD_DAT[3]

SD_SDCD

SD_SDWP

SPI_SCLK

SPI_SCS[0]

SPI_SCS[1]

SPI_SCS[2]

SPI_SCS[3]

SPI_D[0]

GPMC_A[23]

GPMC_A[22]

GPMC_A[21]

GP1[22]

SPI_D[1]

UART0_RXD

UART0_TXD

UART0_RTS

UART0_CTS

UART0_DTR

UART0_DSR

UART0_DCD

UART0_RIN

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS

GP1[27]

GP1[28]

GPMC_A[20]

GPMC_A[19]

GPMC_A[18]

GPMC_A[17]

GPMC_A[26]

GPMC_A[25]

GPMC_A[14]

GPMC_A[13]

GPMC_A[12]

GPMC_A[24]

GPMC_A[23]

GPMC_A[22]

GPMC_A[20]

GPMC_A[19]

GPMC_A[18]

GPMC_A[17]

GP1[16]

GP1[17]

GP1[18]

GP1[19]

GP1[25]

GP1[26]

GPMC_A[15]

GPMC_A[16]

GPMC_A[27]

GPMC_A[22]

GPMC_A[26]

GPMC_A[25]

GP1[13]

GPMC_A[26]

GPMC_A[25]

GP1[9]

GP1[23]

GP1[24]

GP1[10]

GP1[11]

GP1[12]

GPMC_A[23]

GPMC_A[24]

GPMC_A[16]

GPMC_A[15]

GPMC_A[14]

GPMC_A[13]

GP0[25]

GP1[14]

GP1[15]

GP0[21]

GP0[22]

GP0[23]

GP0[24]

GPMC_A[21]

GPMC_A[12]

GP0[28]

GP0[26]

GP0[27]

TIM4_OUT

TIM5_OUT

TIM6_OUT

TIM7_OUT

GPMC_CS[0]

GP0[29]

GPMC_A[24]

GPMC_A[12]

GP0[30]

GP0[31]

Device Configurations

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Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

HEX ADDRESS

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 0B3C

0x4814 0B40

0x4814 0B44

0x4814 0B48

0x4814 0B4C

0x4814 0B50

0x4814 0B54

0x4814 0B58

0x4814 0B5C

0x4814 0B60

0x4814 0B64

0x4814 0B68

0x4814 0B6C

0x4814 0B70

0x4814 0B74

0x4814 0B78

0x4814 0B7C

0x4814 0B80

0x4814 0B84

0x4814 0B88

0x4814 0B8C

0x4814 0B90

0x4814 0B94

0x4814 0B98

0x4814 0B9C

0x4814 0BA0

0x4814 0BA4

0x4814 0BA8

0x4814 0BAC

0x4814 0BB0

0x4814 0BB4

0x4814 0BB8

0x4814 0BBC

0x4814 0BC0

0x4814 0BC4

0x4814 0BC8

0x4814 0BCC

0x4814 0BD0

0x4814 0BD4

0x4814 0BD8

0x4814 0BDC

0x4814 0BE0

0x4814 0BE4

0x4814 0BE8

0x4814 0BEC

0x4814 0BF0

0x4814 0BF4

0x4814 0BF8

0x4814 0BFC

0x4814 0C00

0x4814 0C04

0x4814 0C08

0x4814 0C0C

0x4814 0C10

0x4814 0C14

PINCTRL208

PINCTRL209

PINCTRL210

PINCTRL211

PINCTRL212

PINCTRL213

PINCTRL214

PINCTRL215

PINCTRL216

PINCTRL217

PINCTRL218

PINCTRL219

PINCTRL220

PINCTRL221

PINCTRL222

PINCTRL223

PINCTRL224

PINCTRL225

PINCTRL226

PINCTRL227

PINCTRL228

PINCTRL229

PINCTRL230

PINCTRL231

PINCTRL232

PINCTRL233

PINCTRL234

PINCTRL235

PINCTRL236

PINCTRL237

PINCTRL238

PINCTRL239

PINCTRL240

PINCTRL241

PINCTRL242

PINCTRL243

PINCTRL244

PINCTRL245

PINCTRL246

PINCTRL247

PINCTRL248

PINCTRL249

PINCTRL250

PINCTRL251

PINCTRL252

PINCTRL253

PINCTRL254

PINCTRL255

PINCTRL256

PINCTRL257

PINCTRL258

PINCTRL259

PINCTRL260

PINCTRL261

PINCTRL262

1

0

1

0

1

0

1

0

1

0

1

0

GPMC_CS[1]

GPMC_CS[2]

GPMC_CS[3]

GPMC_CS[4]

GPMC_CS[5]

GPMC_WE

GP1[21]

GPMC_A[12]

GPMC_OE_RE

GPMC_BE0_CLE

GPMC_BE1

GPMC_ADV_ALE

GPMC_DIR

GP1[20]

GPMC_WP

GPMC_WAIT

GPMC_A[0]

GP0[8]

GP0[9]

GPMC_A[1]

GPMC_A[2]

GP0[10]

GP0[11]

GP0[12]

GP0[13]

GP0[14]

GP0[15]

GP0[16]

GP0[17]

GP0[18]

GP0[19]

GP0[20]

GPMC_A[3]

GPMC_A[4]

GPMC_A[5]

GPMC_A[6]

GPMC_A[7]

GPMC_A[8]

GPMC_A[9]

GPMC_A[10]

GPMC_A[11]

GPMC_A[27]

GPMC_D[0]

GPMC_D[1]

GPMC_D[2]

GPMC_D[3]

GPMC_D[4]

GPMC_D[5]

GPMC_D[6]

GPMC_D[7]

GPMC_D[8]

GPMC_D[9]

GPMC_D[10]

GPMC_D[11]

GPMC_D[12]

GPMC_D[13]

GPMC_D[14]

GPMC_D[15]

GPMC_CLK

GP1[29]

EMAC[0]_COL

EMAC[0]_CRS

EMAC[0]_GMTCLK

EMAC[0]_RXCLK

EMAC[0]_RXD[0]

EMAC[0]_RXD[1]

EMAC[0]_RXD[2]

EMAC[0]_RXD[3]

EMAC[0]_RXD[4]

EMAC[0]_RXD[5]

EMAC[0]_RXD[6]

EMAC[0]_RXD[7]

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HEX ADDRESS

SPRS681A–OCTOBER 2010–REVISED MARCH 2011

Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 0C18

0x4814 0C1C

0x4814 0C20

0x4814 0C24

0x4814 0C28

0x4814 0C2C

0x4814 0C30

0x4814 0C34

0x4814 0C38

0x4814 0C3C

0x4814 0C40

0x4814 0C44

0x4814 0C48

0x4814 0C4C

0x4814 0C50

0x4814 0C54

0x4814 0C58

0x4814 0C5C

0x4814 0C60

0x4814 0C64

0x4814 0C68

0x4814 0C6C

0x4814 0C70

0x4814 0C74

0x4814 0C78

0x4814 0C7C

0x4814 0C80

0x4814 0C84

0x4814 0C88

0x4814 0C8C

0x4814 0C90

0x4814 0C94

0x4814 0C98

0x4814 0C9C

0x4814 0CA0

0x4814 0CA4

0x4814 0CA8

0x4814 0CAC

0x4814 0CB0

0x4814 0CB4

0x4814 0CB8

0x4814 0CBC

0x4814 0CC0

0x4814 0CC4

0x4814 0CC8

0x4814 0CCC

0x4814 0CD0

0x4814 0CD4

0x4814 0CD8

0x4814 0CDC

0x4814 0CE0

0x4814 0CE4

0x4814 0CE8

0x4814 0CEC

0x4814 0CF0

PINCTRL263

PINCTRL264

PINCTRL265

PINCTRL266

PINCTRL267

PINCTRL268

PINCTRL269

PINCTRL270

PINCTRL271

PINCTRL272

PINCTRL273

PINCTRL274

PINCTRL275

PINCTRL276

PINCTRL277

PINCTRL278

PINCTRL279

PINCTRL280

PINCTRL281

PINCTRL282

PINCTRL283

PINCTRL284

PINCTRL285

PINCTRL286

PINCTRL287

PINCTRL288

PINCTRL289

PINCTRL290

PINCTRL291

PINCTRL292

PINCTRL293

PINCTRL294

PINCTRL295

PINCTRL296

PINCTRL297

PINCTRL298

PINCTRL299

PINCTRL300

PINCTRL301

PINCTRL302

PINCTRL303

PINCTRL304

PINCTRL305

PINCTRL306

PINCTRL307

PINCTRL308

PINCTRL309

PINCTRL310

PINCTRL311

PINCTRL312

PINCTRL313

PINCTRL314

PINCTRL315

PINCTRL316

PINCTRL317

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

EMAC[0]_RXDV

EMAC[0]_RXER

EMAC[0]_TXCLK

EMAC[0]_TXD[0]

EMAC[0]_TXD[1]

EMAC[0]_TXD[2]

EMAC[0]_TXD[3]

EMAC[0]_TXD[4]

EMAC[0]_TXD[5]

EMAC[0]_TXD[6]

EMAC[0]_TXD[7]

EMAC[0]_TXEN

MDIO_MCLK

MDIO_MDIO

I2C[0]_SCL

I2C[0]_SDA

I2C[1]_SCL

I2C[1]_SDA

GP0[0]

GP0[1]

GP0[2]

GP0[3]

TCLKIN

GP0[4]

GP0[5]

MCA[2]_AMUTEIN

MCA[1]_AMUTEIN

MCA[0]_AMUTEIN

SATA_ACT0_LED

SATA_ACT1_LED

GPMC_A[24]

GPMC_A[23]

GP0[6]

GP0[7]

GP1[30]

GP1[31]

HDMI_SCL

HDMI_SDA

HDMI_CEC

HDMI_HPDET

TCLK

RTCK

TDI

TDO

TMS

TRST

EMU0

EMU1

EMU2

EMU3

EMU4

RESET

NMI

Device Configurations

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Table 4-8. PINCTRLx Registers (continued)

MUXMODE[2:0]

HEX ADDRESS

REGISTER NAME

PULLTYPESEL

PULLDIS

000

001

010

011

0x4814 0CF4

0x4814 0CF8

0x4814 0CFC

0x4814 0D00

0x4814 0D04

0x4814 0D08

PINCTRL318

PINCTRL319

PINCTRL320

PINCTRL321

PINCTRL322

PINCTRL323

Reserved

1

0

1

0

RSTOUT

WD_OUT

CLKOUT

CLKIN32

USB0_DRVVBUS

USB1_DRVVBUS

0x4814 0D0C -

0x4814 0FFF

4.5 How to Handle Unused Pins

When device signal pins are unused in the system, they can be left unconnected unless otherwise

instructed in the Terminal Functions tables. For unused input pins, the internal pull resistor should be

enabled, or an external pull resistor should be used, to prevent floating inputs. All supply pins must always

be connected to the correct voltage, even when their associated signal pins are unused, as instructed in

the Terminal Functions tables in Section 3.2.

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5 System Interconnect

The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip

memories, between all the initiators of the platform. The L4 interconnects control access to the

peripherals.

Transfers between initiators and targets across the platform are physically conditioned by the chip

interconnect.

5.1 L3 Interconnect

The L3 topology is driven by performance requirements, bus types, and clocking structure. Figure 5-1

shows the interconnect of the device and the main modules and subsystems in the platform. Arrows

indicate the master/slave relationship, not data flow. Master/slave connectivity is shown in Table 5-1.

Initiator Ports

Target Ports

L4 Periph

High Speed

USB 2.0

0/1

Debug

DAP

L4 Periph

Standard

SATA

Debug

USB 2.0

EMAC0

EMAC1

HDMI 1.3

Tx

McBSP

McASP0

McASP2

GPMC

PCIe

Gen2

Media

Ctrl

McASP1

SGX530^(A)

HDVPSS

OCMC

RAM0

EDMA

4 Channels

OCMC

RAM1

PCIe

Gen2

Media

Ctrl

SGX530^(A)

EDMA

Config

Cortex™-

A8

DMM

DDR

A. SGX530 is available only on the AM3894 device.

Figure 5-1. Interconnect Overview

System Interconnect

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Table 5-1. L3 Master/Slave Connectivity⁽¹⁾⁽²⁾

SLAVES

MASTERS

ARM Cortex-A8 M1

(128-bit)

X

ARM Cortex-A8 M2

(64-bit)

X

HDVPSS Mstr0

HDVPSS Mstr1

SGX530 BIF

X

SATA

X

EMAC0 Rx/Tx

EMAC1 Rx/Tx

USB2.0 DMA

USB2.0 Queue Mgr

PCIe Gen2

X

EDMA TPTC0

EDMA TPTC1

EDMA TPTC2

EDMA TPTC3

X

(1) X = Connection exists.

(2) SGX530 is available only on the AM3894 device.

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5.2 L4 Interconnect

The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large

number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to

four initiators and can distribute those communication requests to and collect related responses from up to

63 targets.

The device provides three interfaces with L3 interconnect for high-speed peripheral and standard

peripheral. Figure 5-2 and Table 5-2 show the L4 bus architecture and memory-mapped peripherals.

L3 Interconnect

L4 High Speed

L4 Standard

Spinlock

PRCM

EMAC0

EMAC1

SATA

I2C0

I2C1

SPI

Control

ELM

UART0

UART1

Timer1

Timer2

Timer3

Timer4

Timer5

Timer6

Timer7

GPIO0

HDMIphy

OCPWP

McASP0

McASP1

McASP2

Mailbox

GPIO1

SD/SDIO

WDT

RTC

SmartReflex0

SmartReflex1

DDR_CFG0

DDR_CFG1

250-MHz CLK domain

125-MHz CLK domain

A. SGX530 is available only on the AM3894 device.

Figure 5-2. L4 Architecture

System Interconnect

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Table 5-2. L4 Peripheral Connectivity⁽¹⁾

MASTERS

L4 PERIPHERALS

Cortex-A8 M2

(64-bit)

EDMA TPTC0

EDMA TPTC1

EDMA TPTC2

EDMA TPTC3

L4 High-Speed Peripherals Port 0/1

EMAC0

Port0

Port1

Port0

Port1

Port0

EMAC1

SATA

L4 Standard-Speed Peripherals Port 0/1

I2C0

Port0

Port1

Port0

Port1

Port0

I2C1

SPI

UART0

UART1

Timer1

Timer2

Timer3

Timer4

Timer5

Timer6

Timer7

GPIO0

GPIO1

SD/SDIO

WDT

RTC

SmartReflex0

SmartReflex1

DDR_CFG0

DDR_CFG1

Spinlock

PRCM

Control/Top Regs

ELM

HDMIphy

OCPWP

McASP0

McASP1

McASP2

Mailbox

Port1

Port0

Port1

Port0

(1) X, Port0, Port1 = Connection exists.

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6 Device Operating Conditions

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(Unless Otherwise Noted)^(1)(2)(3)

MIN

MAX

1.35

1.2

UNIT

V

USB PHYs, 0.9 V (VDD_USB_0P9)

-0.3

Core (CVDD, CVDDC, VDDT_SATA,

VDDT_PCIE, VDDA_HDMI,

VDDA_HD_1P0, VDDA_SD_1P0)

V

I/O, 1.5 V (VDDA_PLL, VDDR_SATA,

VDDR_PCIE, DVDD_DDR0,

DVDD_DDR1)⁽⁴⁾

-0.3

2.45

V

Steady State Supply voltage

ranges:

I/O, 1.8 V (DVDD1P8,

DEVOSC_DVDD18, VDD_USB0_1P8,

VDD_USB1_1P8, VDDA_REF_1P8,

VDDA_HD_1P8, VDDA_SD_1P8,

DVDD_DDR0, DVDD_DDR1)⁽⁴⁾

I/O, 3.3 V (DVDD_3P3,

VDD_USB0_3P3, VDD_USB1_3P3)

0

3.8

V

V I/O, 1.5-V pins

V I/O, 1.8-V pins

-0.3

2.45

-0.3 DVDD_DDRx + 0.3⁽⁴⁾

-0.3

2.45

DVDD1P8 + 0.3

-0.3 DVDD_DDRx + 0.3⁽⁴⁾

Input and Output voltage ranges:

V I/O, 3.3-V pins

(Steady State)

-0.3

3.8

V

DVDD_3P3 + 0.3

V I/O, 3.3-V pins

(Transient Overshoot/Undershoot)

20% of DVDD_3P3 for up to 20% of the

signal period

Operating junction temperature

range, T_J:⁽⁵⁾

(default)

0

95

85

°C

Operating case temperature

range, T_c:⁽⁵⁾

(default)

0

Storage temperature range, T_stg

:

(default)

-55

150

±2000

±500

°C

V

HBM (Human Body Model)⁽⁷⁾

CDM (Charged-Device Model)⁽⁸⁾

(6)

ESD stress voltage, V_ESD

:

V

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS.

(3) Data in this table is based on device operation at 1.0 GHz for the ARM Cortex-A8.

(4) For supply voltage pins, DVDD_DDRx:

•

1.5 V is used for DDR3 SDRAM.

1.8 V is used for DDR2 SDRAM.

(5) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully

considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with

the help of heat sinks, heat spreaders, and/or airflow. SmartReflex can significantly lower the power consumption of this device and its

use is required for proper device operation.

(6) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(7) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows

safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary

precautions are taken. Pins listed as 2000 V may actually have higher performance.

(8) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance.

Device Operating Conditions

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6.2 Recommended Operating Conditions⁽¹⁾

PARAMETER

MIN

NOM

MAX UNIT

Supply voltage, Variable Core, Adaptive Voltage

CVDD

0.8

1.05

V

Scaling (CVDD)⁽²⁾

Supply voltage, Constant Core (CVDDC,

CVDDC

VDDT_SATA, VDDT_PCIE, VDDA_HDMI,

VDDA_HD_1P0, VDDA_SD_1P0)

0.95

1

1.05

V

Supply voltage, I/O, 3.3 V (DVDD_3P3,

VDD_USB0_3P3, VDD_USB1_3P3)

(except I2C pins)

3.13

3.3

3.47

V

Supply voltage, I/O, I2C (DVDD_3P3)

Supply voltage, I/O, 1.8 V (DVDD1P8,

DEVOSC_DVDD18, VDD_USB0_1P8,

VDD_USB1_1P8, VDDA_REF_1P8,

VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0,

DVDD_DDR1)⁽³⁾

DVDD

1.71

1.8

1.89

V

Supply voltage, I/O, 1.5 V (VDDA_PLL,

VDDR_SATA, VDDR_PCIE, DVDD_DDR0,

DVDD_DDR1)⁽³⁾

1.43

1.5

1.58

V

Supply voltage, I/O, 0.9 V (VDD_USB_0P9)

0.85

0

0.9

0

0.95

0

V

Supply ground (VSS, VSSA_PLL, VSSA_HD,

VSSA_SD, VSSA_REF_1P8, DEVOSC_VSS)⁽⁴⁾

VSS

DDR_VREF

DDR2/3 reference voltage⁽⁵⁾

High-level input voltage, 3.3 V (except I2C pins)

High-level input voltage, I2C

High-level input voltage, 1.8 V

Low-level input voltage, 3.3 V (except I2C pins)

Low-level input voltage, I2C

Low-level input voltage, 1.8 V

4-mA I/O buffers

0.48DVDD_DDRx

2

0.5DVDD_DDRx 0.52DVDD_DDRx

V_IH

0.7DVDD_3P3

0.65DVDD1P8

V

0.8

0.3DVDD_3P3

0.35DVDD1P8

-4

V_IL

6-mA I/O buffers

-6

I_OH

High-level output current

mA

DDR[0], DDR[1]

buffers @ 50-Ω

impedance setting

-8

4-mA I/O buffers

4

6

6-mA I/O buffers

I_OL

Low-level output current

DDR[0], DDR[1]

buffers @ 50-Ω

8

impedance setting

Differential input voltage (SERDES_CLKN/P),

[AC coupled]

0.25

V_ID

t_t

2.0

V

Transition time, 10%-90%, All Inputs (unless

otherwise specified in the electrical data sections)

Lesser of 0.25P or

ns

(6)

10

(1) Data in this table is based on device operation at 1.0 GHz for the ARM Cortex-A8.

(2) This device supports, and requires the use of, SmartReflex technology with Adaptive Voltage Scaling based on die temperature and

performance. The SmartReflex codes output from the device correspond to up to 32 linear voltage steps within the specified voltage

range, with the option to use fewer steps if desired, with a minimum of eight steps. TI requires that users design-in a supply that can

handle multiple voltage steps within this range with ± 5% tolerances. Not incorporating a flexible supply may limit the system's ability to

use the power saving capabilities of the SmartReflex technology.

(3) For supply voltage pins, DVDD_DDRx:

•

1.5 V is used for DDR3 SDRAM.

1.8 V is used for DDR2 SDRAM.

(4) Oscillator ground (DEVOSC_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor

ground.

(5) DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx.

(6) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input

signals.

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Recommended Operating Conditions (continued)

PARAMETER

MIN

0

NOM

MAX UNIT

T_J

Operating junction temperature range⁽¹⁾

Operating case temperature range⁽¹⁾

ARM Operating Frequency (SYSCLK1)

95

85

1

°C

T_c

0

FSYSCLK

20

GHz

(1) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully

considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with

the help of heat sinks, heat spreaders, and/or airflow. SmartReflex can significantly lower the power consumption of this device and its

use is required for proper device operation.

Device Operating Conditions

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6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Temperature (Unless Otherwise Noted)⁽¹⁾

PARAMETER

TEST CONDITIONS⁽²⁾

MIN

TYP

MAX

UNIT

Low/full speed: USB_DN

and USB_DP

2.8

VDD_USBx_3P3

V

High speed: USB_DN and

USB_DP

360

2.4

0.0

-10

440

mV

V

V_OH

High-level output voltage

(3.3-V I/O)

DVDD_3P3 = MIN,

I_OH= MAX

Low/full speed: USB_DN

and USB_DP

0.3

10

V

High speed: USB_DN and

USB_DP

mV

V

V_OL

Low-level output voltage

(3.3-V I/O except I2C pins)

DVDD_3P3 = MIN,

I_OL= MAX

0.4

±1

Low-level output voltage

(3.3-V I/O I2C pins)

IO = 3 mA

V

VI = VSS to DVDD_3P3

without opposing

µA

internal resistor

VI = VSS to DVDD_3P3

with opposing internal

pullup resistor⁽⁴⁾

100

µA

Input current [DC]

(except I2C pins)

I_I⁽³⁾

VI = VSS to DVDD_3P3

with opposing internal

pulldown resistor⁽⁴⁾

-100

Input current [DC] (I2C)

VI = VSS to DVDD_3P3

±20

±5

µA

VO = DVDD_3P3 or

VSS; internal pull

disabled

(5)

I_OZ

I/O Off-state output current

VO = DVDD_3P3 or

VSS; internal pull

enabled

±100

µA

Core (CVDD, CVDDC) CDD TBD

supply current⁽⁶⁾

TBD

mA

I_CDD

3.3-V I/O (DVDD_3P3,

USB_VDDA3P3) supply

current⁽⁶⁾

TBD

1.8-V I/O (DVDD1P8,

DVDD_DDRx) supply

current⁽⁶⁾⁽⁷⁾

TBD

mA

I_DDD

1.5-V I/O (DVDD_DDRx)

supply current⁽⁶⁾⁽⁷⁾

C_I

Input capacitance

Output capacitance

2.8

pF

C_o

(1) Data in this table is based on device operation at 1.0 GHz for the ARM Cortex-A8.

(2) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(3) I_Iapplies to input-only pins and bi-directional pins. For input-only pins, I_Iindicates the input leakage current. For bi-directional pins, I_I

indicates the input leakage current and off-state (Hi-Z) output leakage current.

(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(5) I_OZapplies to output-only pins, indicating off-state (Hi-Z) output leakage current.

(6) Measured under the following conditions: TBD. The actual current draw varies across manufacturing processes and is highly

application-dependent.

(7) For supply voltage pins, DVDD_DDRx:

•

1.5 V is used for DDR3 SDRAM.

1.8 V is used for DDR2 SDRAM.

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7 Power, Reset, Clocking, and Interrupts

7.1 Power Supplies

7.1.1 Voltage and Power Domains

The device has the following voltage domains:

•

1-V adaptive voltage scaling (AVS) domain - Main voltage domain for all modules

1-V constant domain - Memories, PLLs, DACs, DDR IOs, HDMI, and USB PHYs

1.8-V constant domain - PLLs, DACs, HDMI, and USB PHYs

3.3-V constant domain - IOs and USB PHY

1.5-V constant domain - DDR IOs, PCIe, and SATA SERDES

0.9-V constant domain - USB PHY

These domains define groups of modules that share the same supply voltage for their core logic. Each

voltage domain is powered by dedicated supply voltage rails. For the mapping between voltage domains

and the supply pins associated with each, see Table 3-30.

Note: A regulated supply voltage must be supplied to each voltage domain at all times, regardless of the

power domain states.

7.1.2 Power Domains

The device's 1-V AVS and 1-V constant voltage domains have seven power domains that supply power to

both the core logic and SRAM within their associated modules. All other voltage domains have only

always-on power domain.

Within the 1-V AVS and 1-V constant voltage domains, each power domain, except for the always-on

domain, has an internal power switch that can completely remove power from that domain. At power-up,

all domains, except always-on, come-up as power gated. Since there is an always-on domain in each

voltage domain, all power supplies are expected to be ON all the time (as long as the device is in use).

For details on powering up/down the device power domains, see the AM38x Sitara ARM Microprocessors

(MPUs) Technical Reference Manual (literature number SPRUGX7).

Note: All modules within a power domain are unavailable when the domain is powered OFF. For

instructions on powering ON/OFF the domains, see the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

7.1.3 1-V AVS and 1-V Constant Power Domains

•

Graphics Domain

This domain contains the SGX530 (available only on the AM8394 device).

•

Active Domain

The active domain has all modules that are only needed when the system is in "active" state. In any of

the standby states, these modules are not needed. This domain contains the HDVPSS peripheral.

•

Default Domain

The default domain contains modules that might be required even in standby mode. Having them in a

separate power domain allows customers to power gate these modules when in standby mode. This

domain has the DDR, SATA, PCIe, Media Controller and USB peripherals.

Always-On Domain

The always-on domain contains all modules that are required even when the system goes to standby

mode. This includes the host ARM and modules that generate wake-up interrupts (e.g., UART, RTC,

GPIO, EMAC) as well as other low-power I/Os.

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7.1.4 SmartReflex™

The device contains SmartReflex modules that are required to minimize power consumption on the

voltage domains using external variable-voltage power supplies. Based on the device process,

temperature, and desired performance, the SmartReflex modules advise the host processor to raise or

lower the supply voltage to each domain for minimal power consumption. The communication link between

the host processor and the external regulators is a system-level decision and can be accomplished using

GPIOs or I2C.

The major technique employed by SmartReflex in the device is adaptive voltage scaling (AVS). Based on

the silicon process and temperature, the SmartReflex modules guide software in adjusting the core 1-V

supply voltage within the desired range. This technique is called adaptive voltage scaling (AVS). AVS

occurs continuously and in real time, helping to minimize power consumption in response to changing

operating conditions.

NOTE

Implementation of SmartReflex AVS is required for proper device operation.

7.1.5 Memory Power Management

The device memories offer three different modes to save power when memories are not being used;

Table 7-1 provides the details.

Table 7-1. Memory Power Management Modes

MODE

POWER SAVING

~60%

WAKE-UP LATENCY

MEMORY CONTENTS

Preserved

Light Sleep (LS)

Deep Sleep (DS)

Shut Down (SD)

Low

Medium

High

~75%

Preserved

~95%

Lost

The device provides a feature that allows the software to put the chip-level memories (OCMC RAMs) in

any of the three (LS, DS, and SD) modes. There are control registers in the control module to control the

power-down state of OCMC RAM0 and OCMC RAM1. There are also status registers that can be used

during power-up to check if memories are powered-up. For detailed instructions on entering and exiting

from light sleep and deep sleep modes, see the AM38x Sitara ARM Microprocessors (MPUs) Technical

Reference Manual (literature number SPRUGX7).

Memories inside switchable domains go to the shut down (SD) state whenever the power domain goes to

the OFF state. Memories come back to functional state along with the domain power-up.

In order to reduce SRAM leakage, many SRAM blocks can be switched from active mode to shut-down

mode. When SRAM is put in shut-down mode, the voltage supplied to it is automatically removed and all

data in that SRAM is lost.

All SRAM located in a switchable power domain (all domains except always-on) automatically enters

shut-down mode whenever its assigned associated power domain goes to the OFF state. The SRAM

returns to the active state when the corresponding power domain returns to the ON state.

For detailed instructions on powering up/down the various device SRAM, see the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.1.6 I/O Power-Down Modes

The DDR3 I/Os are put into power-down mode automatically when the default power domain is turned

OFF.

The HDMI PHY controller is in the always-on power domain, so software must configure the PHY into

power-down mode.

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There is no power-down mode for the other 3.3-V I/Os.

7.1.7 Supply Sequencing

The device power supplies must be sequenced in the following order:

1. 3.3 V

2. 1-V AVS

3. 1-V Constant

4. 1.8 V

5. 1.5 V

6. 0.9 V

Each supply (represented by VDD_Bin Figure 7-1) must begin actively ramping between 0 ms and 50 ms

after the previous supply (represented by VDD_Ain Figure 7-1) in the sequence has reached 80% of its

nominal value, as shown in Figure 7-1.

80%

VDD_A

VDD_B

t_d= 0-50 ms

Figure 7-1. Power Sequencing Requirements

NOTE

The device pins are not fail-safe. They should not be externally driven before their

corresponding supply rail has been powered up. The corresponding supply rail for each pin

can be found in Section 3.2, Terminal Functions.

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7.2 Reset

7.2.1 System-Level Reset Sources

The device has several types of system-level resets. Table 7-2 lists these reset types, along with the reset

initiator and the effects of each reset on the device.

Table 7-2. System-Level Reset Types

RESETS ALL

MODULES,

EXCLUDING

EMULATION

RESETS

EMULATION

LATCHES BOOT

PINS

ASSERTS

RSTOUT PIN

TYPE

INITIATOR

Power-On Reset (POR)

External Warm Reset

Emulation Warm Reset

POR pin

Yes

No

Yes

No

Yes

RESET pin

On-Chip Emulation

Logic

No

Watchdog Reset

Watchdog Timer

Yes

No

Yes

No

Yes

Software Global Cold Reset Software

Software Global Warm

Reset

Software

Test Reset

TRST pin

No

Yes

No

7.2.2 Power-On Reset (POR pin)

Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test

and emulation logic. POR is also referred to as a cold reset since it is required to be asserted when the

devices goes through a power-up cycle. However, a device power-up cycle is not required to initiate a

power-on reset.

The following sequence must be followed during a power-on reset:

1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.

2. Wait for the input clock sources SERDES_CLKN/P to be stable (if used by the system) while keeping

the POR pin asserted (low).

3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted

(low) for a minimum of 32 DEV_MXI cycles. Within the low period of the POR pin, the following

happens:

(a) All pins enter a Hi-Z mode.

(b) The PRCM asserts reset to all modules within the device.

(c) The PRCM begins propagating these clocks to the chip with the PLLs in bypass mode.

4. The POR pin may now be deasserted (driven high). When the POR pin is deasserted (high):

(a) The BOOT pins are latched.

(b) Reset to the ARM Cortex-A8 is de-asserted, provided the MPU clock is running.

(c) All other domain resets are released, provided the domain clocks are running.

(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of

the PRCM.

(e) The ARM Cortex-A8 begins executing from the default address (either Boot ROM or GPMC).

7.2.3 External Warm Reset (RESET pin)

An external warm reset is activated by driving the RESET pin active-low. This resets everything in the

device, except the ARM Cortex-A8 interrupt controller, test, and emulation. An emulator session stays

alive during warm reset.

The following sequence must be followed during a warm reset:

1. Power supplies and input clock sources should already be stable.

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2. The RESET pin must be asserted (low) for a minimum of 32 DEV_MXI cycles. Within the low period of

the RESET pin, the following happens:

(a) All pins, except test and emulation pins, enter a Hi-Z mode.

(b) The PRCM asserts reset to all modules within the device, except for the ARM Cortex-A8 interrupt

controller, test, and emulation.

(c) RSTOUT is asserted.

3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):

(a) The BOOT pins are latched.

(b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the

exception of the ARM Cortex-A8 interrupt controller, test, and emulation.

(c) RSTOUT is de-asserted.

(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of

the PRCM.

(e) The ARM Cortex-A8 begins executing from the default address (Boot ROM).

(f) Since the ARM Cortex-A8 interrupt controller is not impacted by warm reset, application software

needs to explicitly clear all pending interrupts in the ARM Cortex-A8 interrupt controller.

7.2.4 Emulation Warm Reset

An emulation warm reset is activated by the on-chip emulation module. It has the same effect and

requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT

pins.

The emulator initiates an emulation warm reset via the ICEPick module. To invoke the emulation warm

reset via the ICEPick module, the user can perform the following from the Code Composer Studio™ IDE

menu:

Debug → Advanced Resets → System Reset.

7.2.5 Watchdog Reset

A watchdog reset is initiated when the watchdog timer counter reaches zero. It has the same effect and

requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT

pins. In addition, a watchdog reset always results in RSTOUT being asserted.

7.2.6 Software Global Cold Reset

A software global cold reset is initiated under software control. It has the same effect and requirements as

a power-on reset (POR), with the exception that it does not re-latch the BOOT pins.

Software initiates a software global cold reset by writing to RST_GLOBAL_COLD_SW in the

PRM_RST_CTRL register.

7.2.7 Software Global Warm Reset

A software global warm reset is initiated under software control. It has the same effect and requirements

as a external warm reset (RESET), with the exception that it does not re-latch the BOOT pins.

Software initiates a software global warm reset by writing to RST_GLOBAL_WARM_SW in the

PRM_RST_CTRL register.

7.2.8 Test Reset (TRST pin)

A test reset is activated by the emulator asserting the TRST pin. The only effect of a test reset is to reset

the emulation logic.

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7.2.9 Local Reset

The local reset for various modules within the device is controlled by programming the PRCM and/or the

module's internal registers. Only the associated module is reset when a local reset is asserted, leaving the

rest of the device unaffected.

For details on local reset, see the PRCM chapter of the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7) and individual subsystem and peripheral

user's guides.

7.2.10 Reset Priority

If any of the above reset sources occur simultaneously, the device only processes the highest-priority

reset request. The reset request priorities, from high to low, are as follows:

1. Power-on reset (POR)

2. Test reset (TRST)

3. External warm reset (RESET)

4. Emulation warm resets

5. Watchdog reset

6. Software global cold/warm resets.

7.2.11 Reset Status Register

The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the

system. For more information on this register, see the PRCM chapter of the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.2.12 PCIe Reset Isolation

The device supports reset isolation for the PCI Express (PCIe) module. This means that the PCI Express

subsystem can be reset without resetting the rest of the device.

When the device is a PCI Express Root Complex (RC), the PCIe subsystem can be reset by software

through the PRCM. Software should ensure that there are no ongoing PCIe transactions before asserting

this reset by first taking the PCIe subsystem into the IDLE state by programming the register

CM_DEFAULT_PCI_CLKCTRL inside the PRCM. After bringing the PCIe subsystem out of reset, bus

enumeration should be performed again and should treat all endpoints (EP) as if they had just been

connected.

When the device is a PCI Express Endpoint (EP), the PCIe subsystem generates an interrupt when an

in-band reset is received. Software should process this interrupt by putting the PCIe subsystem in the

IDLE state and then asserting the PCIe local reset through the PRCM.

All device-level resets mentioned in the previous sections, except Test Reset, also reset the PCIe

subsystem. Therefore, the device should issue a Hot Reset to all downstream devices and re-enumerate

the bus upon coming out of reset.

7.2.13 RSTOUT

The RSTOUT pin on the device reflects device reset status. This output is always asserted when any of

the following resets occur:

•

Power-on reset (POR)

External warm reset

Emulation warm reset (RESET)

Software global cold/warm reset

Watchdog timer reset.

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The RSTOUT pin remains asserted until PRCM releases the host ARM Cortex-A8 processor for reset.

7.2.14 Effect of Reset on Emulation and Trace

The device emulation and trace is only reset by the following sources:

•

Power-on reset (POR)

Software global cold reset

Test reset (TRST).

Other than these three, none of the other resets affect emulation and trace functionality.

7.2.15 Reset During Power Domain Switching

Each power domain has a dedicated warm reset and cold reset. Warm reset for a power domain is

asserted under either of the following two conditions:

1. A power-on reset, external warm reset, emulation warm reset, or software global cold/warm reset

occurs.

2. When that power domain switches from the ON state to the OFF state.

Cold reset for a power domain is asserted under either of the following two conditions:

1. A power-on reset or software global cold reset occurs.

2. When that power domain switches from the OFF state to the ON state.

7.2.16 Pin Behaviors at Reset

When any reset (other than test reset) described in Section 7.2.1 is asserted, all device pins are put into a

Hi-Z state except for:

•

Emulation pins. These pins are only put into a Hi-Z state when POR or global software cold reset is

asserted.

•

RSTOUT pin.

In addition, the PINCNTL registers, which control pin multiplexing, slew control, enabling the

pullup/pulldown, and enabling the receiver, are reset to their default state. For a description of the

RESET_ISO register, see the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual

(literature number SPRUGX7).

Internal pullup/pulldown (IPU/IPD) resistors are enabled during and immediately after reset as described in

the OTHER column in the tables in Section 3.2, Terminal Functions.

7.2.17 Reset Electrical Data/Timing

NOTE

If a configuration pin must be routed out from the device, the internal pullup/pulldown

(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external

pullup/pulldown resistor.

Table 7-3. Timing Requirements for Reset

(see Figure 7-2 and Figure 7-3)

NO.

1

MIN

12C⁽¹⁾

MAX

UNIT

ns

t_w(RESET)

Pulse duration, POR low or RESET low

2

t_su(CONFIG)

Setup time, boot and configuration pins valid before POR high or RESET

high⁽²⁾

ns

(1) C = 1/DEV_MXI clock frequency, in ns. The device clock source must be stable and at a valid frequency prior to meeting the t_w(RESET)

requirement.

(2) For the list of boot and configuration pins, see , Boot Terminal Functions.

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Table 7-3. Timing Requirements for Reset (continued)

(see Figure 7-2 and Figure 7-3)

NO.

MIN

MAX

UNIT

3

t_h(CONFIG)

Hold time, boot and configuration pins valid after POR high or RESET

high⁽²⁾

0

ns

Table 7-4. Switching Characteristics Over Recommended Operating Conditions During Reset

(see Figure 7-2)

NO.

PARAMETER

Pulse width, RESET low

MIN

10C⁽¹⁾

MAX

UNIT

ns

t_w(RSTL)

4

5

t_{d(RSTL_IORST)}

Delay time, RESET falling to all IO entering their reset state

Delay time, RESET rising to IO exiting their reset state

0

14

ns

t_{d(RSTL_IOFUNC)}

ns

(1) C = 1/DEV_CLKIN clock frequency, in ns.

Power

Supplies

Ramping

Power Supplies Stable

Clock Source Stable

DEV_CLKIN

1

POR

RESET

5

2

3

Hi-Z

BTMODE[4:0]

Config

5

Other I/O Pins^(A)

RESET STATE

A. For more detailed information on the reset state of each pin, see Section 7.2.16, Pin Behaviors at Reset. For the

IPU/IPD settings during reset, see Section 3.2, Terminal Functions.

Figure 7-2. Power-Up Timing

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Power Supplies Stable

DEV_CLKIN

POR

1

RESET

4

5

2

3

Hi-Z

BTMODE[4:0]

Config

5

Other I/O Pins^(A)

RESET STATE

A. For more detailed information on the reset state of each pin, see Section 7.2.16, Pin Behaviors at Reset. For the

IPU/IPD settings during reset, see Section 3.2, Terminal Functions.

Figure 7-3. Warm Reset (RESET) Timing

7.3 Clocking

The device clocks are generated from several external reference clocks that are fed to on-chip PLLs and

dividers (both inside and outside of the PRCM Module). Figure 7-4 shows a high-level overview of the

device clocking structure. Note that to reduce complexity, all clocking connections are not shown. For

detailed information on the device clocks, see the Clocking chapter of the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

NOTE

Frequency and timing data in this section is based on device operation at 1.0 GHz for the

ARM Cortex-A8.

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SATA SS

PCIe SS

100-MHz

Differential Clock

To USB

To ARM Cortex-A8

To L3, HDVPSS

To EMAC

Main

PLL

27-MHz

XTAL

OSC 27

DEVCLKIN

Clocks

To SGX530^(A)

432 MHz

Audio Clock1

Audio Clock2

Audio

PLL

Audio Clock3

Clocks

To RTC

32.768-kHz

Clock

Video

PLL

HD, SD, TMDS Clocks

Clocks

To DDR PHYs

To CEC, UART, etc.

To L3P, EMIF and DMM

DDR

PLL

Clocks

DDR Clock4 (Spare)

DDR Clock5 (Spare)

A. SGX530 is available only on the AM3894 device.

Figure 7-4. System Clocking Overview

7.3.1 Device Clock Inputs

The device has four on-chip PLLs and two reference clocks which are generated by on-chip oscillators. In

addition to the 27-MHz reference clock, a 100-MHz differential clock input is required for SATA and PCIe.

A third clock input is an optional 32.768-kHz clock input (no on-chip oscillator) for the RTC.

The device clock input (DEV_MXI/DEV_CLKIN) is used to generate the majority of the internal reference

clocks. An external square-wave clock can be supplied to DEV_CLKIN instead of using a crystal input.

The device clock should be 27 MHz.

Section 7.3.1.1 provides details on using the on-chip oscillators with external crystals for the 27-MHz

system oscillator.

7.3.1.1 Using the Internal Oscillators

When the internal oscillators are used to generate the device clock, external crystals are required to be

connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 7-5. The

external crystal load capacitors should also be connected to the associated oscillator ground pin

(DEVOSC_VSS). The capacitors should not be connected to board ground (VSS).

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DEV_MXI/

DEV_CLKIN

DEV_MXO DEVOSC_VSS

DEVOSC_DVDD18

DEVOSC_VSS

Crystal

27 MHz

R_d

(Optional)

C1

C2

1.8 V

Figure 7-5. 27-MHz System Oscillator

The load capacitors, C1 and C2 in Figure 7-5, should be chosen such that the equation below is satisfied.

C_Lin the equation is the load specified by the crystal manufacturer. R_dis an optional damping resistor. All

discrete components used to implement the oscillator circuit should be placed as close as possible to the

associated oscillator MXI, MXO, and VSS pins.

C₁C₂

=

C_L

(C₁+ C₂)

Table 7-5. Input Requirements for Crystal Circuit on the Device Oscillator

PARAMETER

Start-up time (from power up until oscillating at stable frequency of 27 MHz)

Crystal Oscillation frequency

MIN

NOM

MAX

UNIT

ms

4

27

MHz

pF

Parallel Load Capacitance (C1 and C2)

Crystal ESR

12

24

60

5

Ohm

pF

Crystal Shunt Capacitance

Crystal Oscillation Mode

Fundamental Only

Crystal Frequency stability

±50

ppm

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Table 7-6. DEV_CLKIN Clock Source Requirements^(1)(2)(3)

(see Figure 7-6)

NO.

MIN

NOM

MAX

UNIT

ns

1

2

3

4

5

t_c(DCK)

t_w(DCKH)

t_w(DCKL)

t_t(DCK)

Cycle time, DEV_CLKIN

37.037

Pulse duration, DEV_CLKIN high

Pulse duration, DEV_CLKIN low

Transition time, DEV_CLKIN

0.45C

0.55C

7

ns

t_J(DCK)

Period jitter, DEV_CLKIN (VDACs not used)

Period jitter, DEV_CLKIN (VDACs used)

Frequency stability, DEV_CLKIN

150

A

ps

s

S_f

±50

ppm

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) C = DEV_CLKIN cycle time in ns.

(3)

-S N R

20

10

B W

(_s)

Α = 10 *

*

2 * p * B W

Where SNR is the desired signal-to-noise ratio and BW is the highest DAC signal bandwidth used in the system (SD = 6 MHz,

720p/1080i = 30 MHz, 1080p = 60 MHz).

27 M H z

1

5

4

1

2

DEV_CLKIN

3

4

Figure 7-6. DEV_CLKIN Timing

7.3.2 SERDES_CLKN/P Input Clock

A high-quality, low-jitter differential clock source is required for the PCIe and SATA PHYs. The clock is

required to be AC coupled to the device's SERDES_CLKP and SERDES_CLKN pins according to the

specifications in Table 7-10. Both the clock source and the coupling capacitors should be placed

physically as close as possible to the processor.

When the PCIe interface is used, the SERDES_CLKN/P clock is required to meet the REFCLK AC

specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and Gen.2). When

the SATA interface is used, the SERDES_CLKN/P clock is required to meet the specifications in

Table 7-7. When both the PCIe and SATA interfaces are used, both sets of specifications must be met

simultaneously.

Table 7-7. SERDES_CLKN/P Clock Source Requirements for SATA

PARAMETER

MIN

TYP

MAX

UNIT

Clock Frequency

Jitter

100

MHz

50 Ps pk-pk

Duty Cycle

Rise/Fall Time

40

60

%

700

ps

An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI

Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In

addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown

in Table 7-8, are also acceptable.

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Table 7-8. Exceptions to REFCLK AC Specification for LVDS Clock Sources

SYMBOL

V_IH

PARAMETER

Differential input high voltage (V_IH

Differential input high voltage (V_IL)

MIN

125

MAX

1000

-125

UNIT

mV

)

V_IL

-1000

mV

Table 7-9. SERDES_CLKN/P Routing Specifications

PARAMETER

MIN

TYP

MAX

0

UNIT

Stubs

Mils

Number of stubs allowed on SERDES_CLKN/P traces

SERDES_CLKN/P trace length from oscillator to device

SERDES_CLKN/P pair differential impedance

2000

100

Ohms

Vias

Number of vias on each SERDES_CLKN/P trace⁽¹⁾

3

SERDES_CLKN/P differential pair to any other trace spacing

2*DS⁽²⁾

(1) Vias must be used in pairs with their distance minimized.

(2) DS is the differential spacing of the SERDES_CLKN/P traces.

AC coupling capacitors are required on the SERDES_CLKN/P pair. Table 7-10 shows the requirements

for these capacitors.

Table 7-10. SERDES_CLKN/P AC Coupling Capacitors Requirements

PARAMETER

SERDES_CLKN/P AC coupling capacitor value

SERDES_CLKN/P AC coupling capacitor package size

MIN

TYP

MAX

12

UNIT

1

10

nF

0402

10

Mils⁽¹⁾⁽²⁾

(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor.

(2) The physical size of the capacitor should be as small as possible

7.3.3 CLKIN32 Input Clock

An external 32.768-kHz clock input can optionally be provided at the CLKIN32 pin to serve as a reference

clock in place of the RTCDIVIDER clock for the RTC and Timer modules. The CLKIN32 source must meet

the timing requirements shown in Table 7-11.

Table 7-11. Timing Requirements for CLKIN32⁽¹⁾⁽²⁾

(see Figure 7-7)

NO.

1

MIN

1/32768

0.45C

NOM

MAX UNIT

t_c(CLKIN32)

Cycle time, CLKIN32

s

2

t_w(CLKIN32H)Pulse duration, CLKIN32 high

0.55C

7

ns

3

t_w(CKIN32L)

t_t(CLKIN32)

t_J(CLKIN32)

Pulse duration, CLKIN32 low

Transition time, CLKIN32

Period jitter, CLKIN32

0.45C

4

5

0.02C

(1) The reference points for the rise and fall transitions are measured at V _ILMAX and V _IHMIN.

(2) C = CLKIN32 cycle time, in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.

5

1

4

1

2

CLKIN32

3

4

Figure 7-7. CLKIN32 Timing

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7.3.4 PLLs

The device contains four embedded PLLs (Main, Audio, Video and DDR) that provide clocks to different

parts of the system. For a high-level view of the device clock architecture, including the PLL reference

clock sources and connections, see Figure 7-4.

The reference clock for most of the PLLs comes from the DEV_CLKIN input clock. Also, each PLL

supports a bypass mode in which the reference clock can be directly passed to the PLL CLKOUT. All

device PLLs (except the DDR PLL) come-up in bypass mode after reset.

Flying-adder PLLs are used for all the on-chip PLLs. Figure 7-8 shows the basic structure of the

flying-adder PLL.

fs

fo

Flying-Adder

Synthesizer

FREQ

/M

K

fp

fr

fvco

/P

PFD

CP

VCO

/N

Figure 7-8. Flying-Adder PLL

The flying-adder PLL has two main components: a multi-phase PLL and the flying-adder synthesizer. The

multi-phase PLL takes an input reference clock (fr), multiplies it with factor, N, and provides a K-phase

output to the flying-adder synthesizer. The flying-adder synthesizer takes this multi-phase clock input and

produces a variable frequency clock (fs). There can be a post divider on this clock which takes in clock fs

and drives out clock fo. The frequency of the clock driven out is given by:

é

ù

ú

(

)

FREQ * P * M

Ν * Κ

fo =

* fr

ê

(

)

ë

û

There can be multiple flying-adder synthesizers attached to one multi-phase PLL to generate different

frequencies. In this case, FREQ (4 bits of integer and 24 bits of fractional value) and M (1 to 255) values

can be adjusted for each clock separately, based on the frequency needed. A multi-phase PLL used in

this device has a value of K = 8.

For details on programming the device PLLs, see the PLL chapter of the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

7.3.4.1 PLL Programming Limits

When programming the PLLs, the result of the following equation must be greater than the value shown in

the corresponding PLL table (this determines if the chosen PLL frequency is a valid one).

6

æ

ç

è

ö

÷

ø

Floor(M * FREQ) * P * 10

PLL_CLKIN * 8 * N

A * M * FREQ

8

-

- Η

Where:

•

PLL_CLKIN is the input clock frequency (in MHz) to the PLL before the P divider

Floor( ) = round down

M = PLL divider

FREQ = PLL frequency setting

A = 169 for all PLLs with the following exception: A = 218 for the audio PLL when its input is sourced

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from the main PLL output

•

H = 10 if M * FREQ is a multiple of 8; otherwise, H = 0

800 MHz ≤ PLL_CLKIN * N / P ≤ 1600 MHz

10 MHz ≤ PLL_CLKIN / P ≤ 60 MHz

Table 7-12. PLL Clock Frequencies

CLOCK

Main PLL

Clock1

MIN CYCLE

MAX FREQUENCY

985

842

987

1152

532

Clock2

Clock3

1847

1991

Clock4

494

DDR PLL

Clock 2

Clock 3

Video PLL

Clock 1

Clock 2

Clock 3

Audio PLL

Clock 2

Clock 3

Clock 4

Clock 5

18447

2443

54

405

1485

660

6290

5041

158

197

100

10000

7.3.4.2 PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be

added on the PLL supply pins to ensure that the requirements in Table 7-13 are met.

Table 7-13. Power Supply Requirements

PARAMETER

MIN

MAX

UNIT

Dynamic noise at VDDA_PLL pins

50

mV p-p

7.3.4.3 PLL Locking Sequence

All of the flying-adder PLLs (except the DDR PLL) come-up in bypass mode at reset. All of the registers

(P, N, FREQ, and M) need to be programmed appropriately and then wait approximately 8 µs for

PLL_Audio and 5 µs for the other PLLS to be locked. Verification that the PLL is locked can be checked

by accessing the lock status bit in the PLL control register for each PLL (bit = 1 when the PLL is locked).

Once the PLL is locked, then the FA-PLL can be taken out of bypass mode. Control for bypass mode is

through chip-level registers. For more details on the PLL registers and bypass logic, see the PLL chapter

of the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number

SPRUGX7).

7.3.4.4 PLL Registers

The PLL control registers reside in the control module and are listed in Table 4-3.

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7.3.5 SYSCLKs

In some cases, the system clock inputs and PLL outputs are sent to the PRCM module for division and

multiplexing before being routed to the various device modules. These clock outputs from the PRCM

module are called SYSCLKs. Table 7-14 lists the main device SYSCLKs along with their maximum

supported clock frequencies. In addition, limits shown in the table may be further restricted by the clock

frequency limitations of the device modules using these clocks. Frequency data in this table is based on

device operation at 1.0 GHz for the ARM Cortex-A8. For more details on module clock frequency limits,

see Section 7.3.6.

Table 7-14. SYSCLK Frequencies

SYSCLK

SYSCLK2

SYSCLK4

FREQUENCY

~1 GHz

DESTINATION

To ARM Cortex-A8

~500 MHz

L3, OCP clock for HDVPSS, TPTCs, TPCC, DMM, Unicache clock for Media

Controller, EDMA

SYSCLK5

SYSCLK6

~250 MHz

~125 MHz

L3, L4_HS, OCP clock for EMAC, SATA, PCIe, Media Controller, OCMC RAM

L3, L4_STD, UART, I2C, SPI, SD/SDIO, TIMER, GPIO, PRCM, McASP, McBSP,

GPMC, ELM, HDMI, WDT, Mailbox, RTC, Spinlock, SmartReflex and USB.

SYSCLK8

SYSCLK23

SYSCLK24

800 MHz

Max 333 MHz

125 MHz

DDR clock, DMM

SGX530 OCP clock

GMII clock

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7.3.6 Module Clocks

Device modules receive their clock directly from an external clock input, directly from a PLL, or from a

PRCM SYSCLK output. Table 7-15 lists the clock source options for each module, along with the

maximum frequency that module can accept. Frequency data in this table is based on device operation at

1.0 GHz for the ARM Cortex-A8. The device PLLs and dividers must be programmed not to exceed the

maximum frequencies listed in this table to ensure proper module functionality.

Table 7-15. Module Clock Frequencies

MODULE

Cortex-A8

DMM

CLOCK SOURCE(S)

PLL_MAIN, SYSCLK2

PLL_DDR, SYSCLK4

PLL_DDR, SYSCLK8

SYSCLK4

MAX. FREQUENCY (MHz)

1000

500

800

500

125

250

DDR

EDMA

ELM

SYSCLK6

EMAC

GPIO0/1

SYSCLK5

SYSCLK6

125

SYSCLK18

32.768

GPMC

SYSCLK6

125

50

HDMI

PLL_VIDEO, SYSCLK6

PLL_AUDIO

HDMI I2S

HDMI CEC

SYSCLK9

48

HDVPSS VPDMA

HDVPSS

PLL_MAIN, SYSCLK4

SYSCLK5

500

250

125

165

54

HDVPSS Interface

HDVPSS HD VENCD

HDVPSS HD VENCA

HDVPSS SD VENC

I2C0/1

SYSCLK6

PLL_VIDEO, SYSCLK13

PLL_VIDEO, SYSCLK15

PLL_VIDEO, SYSCLK17

SYSCLK6

SYSCLK10

125

48

L3

PLL_MAIN, SYSCLK4

PLL_MAIN, SYSCLK5

PLL_MAIN, SYSCLK6

PLL_MAIN, SYSCLK5

PLL_MAIN, SYSCLK6

SYSCLK6

500

250

125

250

125

500

250

L3

L4 HS

L4 STD

Mailbox

McASP0/1/2

McBSP

Media Controller

OCMC RAM

PCIe

PLL_AUDIO, SYSCLK6

SYSCLK4

SYSCLK5

RTC

SYSCLK6

125

SYSCLK18

32.768

SATA

SYSCLK5

250

SD/SDIO

SYSCLK6

SYSCLK10

125

48

SGX530

SmartReflex

SPI

SYSCLK23

SYSCLK6

333

125

SYSCLK6

SYSCLK10

125

48

Spinlock

SYSCLK6

125

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Table 7-15. Module Clock Frequencies (continued)

MODULE

CLOCK SOURCE(S)

MAX. FREQUENCY (MHz)

Timers, WDT

SYSCLK6

125

SYSCLK18

32.768

UART0/1/2

USB0/1

SYSCLK6

SYSCLK10

125

48

SYSCLK6

125

7.3.7 Output Clock Select Logic

The device includes one selectable general-purpose clock output (CLKOUT). The source for these output

clocks is controlled by the CLKOUT_MUX register in the control module and shown in Figure 7-9.

Main PLL Clock5

DDR PLL Clock1

Video PLL Clock1

Audio PLL Clock1

0

1

2

3

/n

(n=1...8)

CLKOUT

Figure 7-9. CLKOUT Source Selection Logic

As shown in the figure, there are four possible sources for CLKOUT, one clock from each of the four

PLLs. The selected clock can be further divided by any ratio from 1 to 1/8 before going out on the

CLKOUT pin. The default selection is to select main PLL clock5, divider set to 1/1, and clock disabled.

Table 7-16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT⁽¹⁾⁽²⁾

(see Figure 7-10)

NO

.

PARAMETER

MIN

MAX UNIT

1

2

3

4

t_c(CLKOUT)Cycle time, CLKOUT

10

0.45P

ns

t_w(CLKOUTH)Pulse duration, CLKOUT high

t_w(CLKOUTL)Pulse duration, CLKOUT low

0.55P

0.05P

ns

t_t(CLKOUT)

Transition time, CLKOUT

(1) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(2) P = 1/CLKOUT clock frequency in nanoseconds (ns). For example, when CLKOUT frequency is 100 MHz, use P = 10 ns.

2

4

1

CLKOUT

(Divide-by-1)

3

4

Figure 7-10. CLKOUT Timing

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7.4 Interrupts

The device has a large number of interrupts. It also has the ARM Cortex™-A8 master capable of servicing

interrupts. Specific details, such as the processing flow, configuration steps, and interrupt controller

registers, for each of these masters are found in their respective subsystem documentation.

7.4.1 Interrupt Summary List

Table 7-17 lists all the device interrupts by module and indicates the interrupt destination: ARM

Cortex™-A8.

Table 7-17. Interrupts By Module

DESTINATION

MODULE

INTERRUPT

DESCRIPTION

Cortex™-A8

INTRQ

Serial ATA

SATA Module interrupt

INTRQ_PEND_N

X

C0_RX_THRESH_INTR_REQ

C0_RX_THRESH_INTR_PEND

C0_RX_INTR_REQ

C0_RX_INTR_PEND

C0_TX_INTR_REQ

Receive threshold (non paced)

Receive pending interrupt (paced)

Transmit pending interrupt (paced)

Stat, Host, MDIO LINKINT or MDIO USERINT

Receive threshold (non paced)

Receive pending interrupt (paced)

Transmit pending interrupt (paced)

Stat, Host, MDIO LINKINT or MDIO USERINT

Queue MGR or CPPI Completion interrupt

EMAC SS0

C0_TX_INTR_PEND

C0_MISC_INTR_REQ

C0_MISC_INTR_PEND

C0_RX_THRESH_INTR_REQ

C0_RX_THRESH_INTR_PEND

C0_RX_INTR_REQ

C0_RX_INTR_PEND

C0_TX_INTR_REQ

EMAC SS1

C0_TX_INTR_PEND

C0_MISC_INTR_REQ

C0_MISC_INTR_PEND

USBSS_INTR_REQ

USBSS_INTR_PEND

USB0_INTR_REQ

USB2.0 SS

USB0_INTR_PEND

USB1_INTR_REQ

RX/TX DMA, Endpoint ready/error, or USB2.0

interrupt

USB1_INTR_PEND

SLV0P_SWAKEUP

X

USB wakeup

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Table 7-17. Interrupts By Module (continued)

DESTINATION

Cortex™-A8

MODULE

INTERRUPT

DESCRIPTION

PCIE_INT_I_INTR0

Legacy interrupt (RC mode only)

MSI interrupt (RC mode only)

Error interrupt

PCIE_INT_I_INTR_PEND_N0

PCIE_INT_I_INTR1

X

PCIE_INT_I_INTR_PEND_N1

PCIE_INT_I_INTR2

PCIE_INT_I_INTR_PEND_N2

PCIE_INT_I_INTR3

Power Management interrupt

PCIE_INT_I_INTR_PEND_N3

PCIE_INT_I_INTR4

PCIE_INT_I_INTR_PEND_N4

PCIE_INT_I_INTR5

PCIE_INT_I_INTR_PEND_N5

PCIE_INT_I_INTR6

PCIE_INT_I_INTR_PEND_N6

PCIE_INT_I_INTR7

PCIE_INT_I_INTR_PEND_N7

PCIE_INT_I_INTR8

PCIe Gen2

PCIE_INT_I_INTR_PEND_N8

PCIE_INT_I_INTR9

PCIE_INT_I_INTR_PEND_N9

PCIE_INT_I_INTR10

Reserved

PCIE_INT_I_INTR_PEND_N10

PCIE_INT_I_INTR11

PCIE_INT_I_INTR_PEND_N11

PCIE_INT_I_INTR12

X

PCIE_INT_I_INTR_PEND_N12

PCIE_INT_I_INTR13

PCIE_INT_I_INTR_PEND_N13

PCIE_INT_I_INTR14

PCIE_INT_I_INTR_PEND_N14

PCIE_INT_I_INTR15

PCIE_INT_I_INTR_PEND_N15

SLE_IDLEP_SWAKEPUP

X

PCIe wakeup

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Table 7-17. Interrupts By Module (continued)

DESTINATION

Cortex™-A8

INTERRUPT

DESCRIPTION

TPCC_INT_PO[0]

TPCC_INT_PEND_N[0]

TPCC_INT_PO[1]

TPCC_INT_PEND_N[1]

TPCC_INT_PO[2]

TPCC_INT_PEND_N[2]

TPCC_INT_PO[3]

TPCC_INT_PEND_N[3]

TPCC_INT_PO[4]

TPCC_INT_PEND_N[4]

TPCC_INT_PO[5]

TPCC_INT_PEND_N[5]

TPCC_INT_PO[6]

TPCC_INT_PEND_N[6]

TPCC_INT_PO[7]

TPCC_INT_PEND_N[7]

TPCC_MPINT_PO

TPCC_MPINT_PEND_N

TPCC_ERRINT_PO

TPCC_ERRINT_PEND_N

TPCC_INTG_PO

Region 0 DMA completion

Region 1 DMA completion

Region 2 DMA completion

Region 3 DMA completion

Region 4 DMA completion

Region 5 DMA completion

Region 6 DMA completion

Region 7 DMA completion

Memory protection error

TPCC error

X

TPCC

X

DMA Global completion

TPTC0 error

TPCC_INTG_PEND_N

TPTC_ERRINT_PO

TPTC_LERRINT_PO

TPTC_INT_PO

X

TPTC 0

TPTC 1

TPTC 2

TPTC 3

TPTC0 completion

TPTC1 error

TPTC_LINT_PO

TPTC_ERRINT_PO

TPTC_LERRINT_PO

TPTC_INT_PO

TPTC1 completion

TPTC2 error

TPTC_LINT_PO

TPTC_ERRINT_PO

TPTC_LERRINT_PO

TPTC_INT_PO

TPTC2 completion

TPTC3 error

TPTC_LINT_PO

TPTC_ERRINT_PO

TPTC_LERRINT_PO

TPTC_INT_PO

TPTC3 completion

TPTC_LINT_PO

SYS_ERR_INTR

DDR EMIF4d 0

DDR EMIF4d 1

SYS_ERR_INTR_PEND_N

SYS_ERR_INTR

EMIF error

SYS_ERR_INTR_PEND_N

GPMC_SINTERRUPT

NIRQ

X

GPMC

GPMC interrupt

UART 0

UART 1

UART 2

UART/IrDA 0 interrupt

UART/IrDA 1 interrupt

UART/IrDA 2 interrupt

NIRQ

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Table 7-17. Interrupts By Module (continued)

DESTINATION

Cortex™-A8

MODULE

Timer1

Timer2

Timer3

Timer4

Timer5

Timer6

INTERRUPT

DESCRIPTION

POINTR_REQ

32-bit Timer1 interrupt

32-bit Timer2 interrupt

32-bit Timer3 interrupt

32-bit Timer4 interrupt

32-bit Timer5 interrupt

32-bit Timer6 interrupt

POINTR_PEND

X

POINTR_REQ

POINTR_PEND

POINTR_REQ

POINTR_PEND

POINTR_REQ

POINTR_PEND

POINTR_REQ

POINTR_PEND

POINTR_REQ

POINTR_PEND

POINTR_REQ

Timer7

WDTimer1

I2C0

32-bit Timer7 interrupt

Watchdog Timer

POINTR_PEND

X

PO_INT_REQ

POINTRREQ

POINTRPEND

X

I2C Bus interrupt

POINTRREQ

I2C1

POINTRPEND

X

SPI

SINTERRUPTN

SPI Interrupt

SDIO

IRQOQN

SDIO interrupt

MCASP_X_INTR_REQ

MCASP_X_INTR_PEND

MCASP_R_INTR_REQ

MCASP_R_INTR_PEND

MCASP_X_INTR_REQ

MCASP_X_INTR_PEND

MCASP_R_INTR_REQ

MCASP_R_INTR_PEND

MCASP_X_INTR_REQ

MCASP_X_INTR_PEND

MCASP_R_INTR_REQ

MCASP_R_INTR_PEND

PORRINTERRUPT

PORXINTERRUPT

PORROVFLINTERRUPT

PORCOMMONIRQ

TIMER_INTR_REQ

TIMER_INTR_PEND

ALARM_INTR_REQ

ALARM_INTR_PEND

POINTRREQ1

McASP 0 Transmit interrupt

McASP 0 Receive interrupt

McASP 1 Transmit interrupt

McASP 1 Receive interrupt

McASP 2 Transmit interrupt

McASP 2 Receive interrupt

X

McASP 0

McASP 1

McASP 2

McBSP

RTC

McBSP Receive Int (legacy mode)

McBSP Transmit Int (legacy mode)

McBSP Receive Overflow Int (legacy mode)

McBSP Common Int

X

Timer interrupt

Alarm interrupt

GPIO 0 interrupt 1

GPIO 0 interrupt 2

POINTRPEND1

GPIO 0

POINTRREQ2

POINTRPEND2

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Table 7-17. Interrupts By Module (continued)

DESTINATION

Cortex™-A8

INTERRUPT

DESCRIPTION

POINTRREQ1

POINTRPEND1

POINTRREQ2

POINTRPEND2

GPIO 1 interrupt 1

GPIO 1 interrupt 2

X

GPIO 1

PRCM

Reserved

INTR0_INTR

Intr0 pulse version

INTR0_INTR_PEND_N

INTR1_INTR

X

Intr0 level version

Intr1 pulse version

INTR1_INTR_PEND_N

INTR2_INTR

Intr1 level version

HDVPSS

Intr2 pulse version

INTR2_INTR_PEND_N

INTR3_INTR

Intr2 level version

Intr3 pulse version

INTR3_INTR_PEND_N

THALIAIRQ

Intr3 level version

X

Error in the IMG bus

SGX530

(AM3894 only)

TARGETSINTERRUPT

INITMINTERRUPT

INTR0_INTR

Target slave error interrupt

Initiator master error interrupt

Intr0 pulse version

HDMI 1.3

Transmit

INTR0_INTR_PEND_N

INTRREQ

X

Intr0 level version

SVT SmartReflex interrupt pulse version

SVT SmartReflex interrupt level version

HVT SmartReflex interrupt pulse version

HVT SmartReflex interrupt level version

Reserved

SmartReflex0

INTRPEND

INTRREQ

SmartReflex1

PBIST

INTRPEND

MAIL_U0_IRQ

MAIL_U1_IRQ

MAIL_U2_IRQ

MAIL_U3_IRQ

NMI_INT

Mailbox

Mailbox interrupt

NMI

X

NMI Interrupt

L3 debug error

L3 application error

PAT fault

L3_DBG_IRQ

L3_APP_IRQ

DMM_HIGH_INTRPEND

COMMTX

Infrastructure

DMM

ARM ICECrusher interrupt

COMMRX

Cortex™-A8 SS

BENCH

ARM NPMUIRQ

ELM_IRQ

Error Location process completion

E2ICE interrupt

EMUINT

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7.4.2 Cortex™-A8 Interrupts

The Cortex™-A8 Interrupt Controller (AINTC) takes ARM device interrupts and maps them to either the

interrupt request (IRQ) or fast interrupt request (FIQ) of the ARM with an individual priority level. The

AINTC interrupts must be active low-level interrupts.

The AINTC is responsible for prioritizing all service requests from the system peripherals directed to the

Cortex™-A8 SS and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or nFIQ)

and the priority of the interrupt inputs are programmable. It has the capability to handle up to 128 requests

which can be steered/prioritized as nFIQ or nIRQ interrupt requests.

The general features of the AINTC are:

•

Up to 128 level-sensitive interrupts inputs

Individual priority for each interrupt input

Each interrupt can be steered to nFIQ or nIRQ

Independent priority sorting for nFIQ and nIRQ

Secure mask flag.

Table 7-18. Cortex™-A8 Interrupt Controller Connections

INTERRUPT

NUMBER

ACRONYM

SOURCE

0

1

EMUINT

COMMTX

COMMRX

BENCH

Internal

ELM

2

3

4

ELM_IRQ

-

5-6

7

NMI

External Pin

8

-

9

L3DEBUG

L3APPINT

-

L3

10

11

12

13

14

15

16

17

18

19

20-33

34

35

36

37

EDMACOMPINT

EDMAMPERR

EDMAERRINT

-

TPCC

SATAINT

USBSSINT

USBINT0

USBINT1

-

SATA

USBSS

USBWAKEUP

PCIeWAKEUP

DSSINT

GFXINT

USBSS

PCIe

HDVPSS

SGX530

(AM8394 only)

38

39

40

41

42

HDMIINT

-

HDMI

MACRXTHR0

MACRXINT0

MACTXINT0

EMAC0

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Table 7-18. Cortex™-A8 Interrupt Controller Connections (continued)

INTERRUPT

NUMBER

ACRONYM

SOURCE

43

44

MACMISC0

MACRXTHR1

MACRXINT1

MACTXINT1

MACMISC1

PCIINT0

PCIINT1

PCIINT2

PCIINT3

-

EMAC0

EMAC1

PCIe

45

46

47

48

49

PCIe

50

PCIe

51

PCIe

52-63

64

SDINT

SD/SDIO

SPI

65

SPIINT

66

-

67

TINT1

Timer1

Timer2

Timer3

I2C0

68

TINT2

69

TINT3

70

I2CINT0

I2CINT1

UARTINT0

UARTINT1

UARTINT2

RTCINT

71

I2C1

72

UART0

UART1

UART2

RTC

73

74

75

76

RTCALARMINT

MBINT

RTC

77

Mailbox

78-79

80

-

MCATXINT0

MCARXINT0

MCATXINT1

MCARXINT1

MCATXINT2

MCARXINT2

MCBSPINT

-

McASP0

McASP1

McASP2

McBSP

81

82

83

84

85

86

87-90

91

WDTINT

TINT4

WDTIMER1

Timer4

92

93

TINT5

Timer5

94

TINT6

Timer6

95

TINT7

Timer7

96

GPIOINT0A

GPIOINT0B

GPIOINT1A

GPIOINT1B

GPMCINT

DDRERR0

DDRERR1

-

GPIO 0

97

GPIO 0

98

GPIO 1

99

GPIO 1

100

101

102

103-111

112

GPMC

DDR EMIF0

DDR EMIF1

TCERRINT0

TPTC0

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Table 7-18. Cortex™-A8 Interrupt Controller Connections (continued)

INTERRUPT

NUMBER

ACRONYM

SOURCE

113

114

TCERRINT1

TPTC1

TPTC2

TPTC3

TCERRINT2

115

TCERRINT3

116-119

120

-

SMRFLX0

SmartReflex0

SmartReflex1

121

SMRFLX1

123

-

124

DMMINT

-

DMM

125-127

148

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8 Peripheral Information and Timings

8.1 Parameter Information

Tester Pin Electronics

Data Sheet Timing Reference Point

42 Ω

3.5 nH

Output

Under

Test

Transmission Line

Z0 = 50 Ω

(see Note)

Device Pin

(see Note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be

taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is

intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 8-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

8.1.1 1.8-V and 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to V_reffor both "0" and "1" logic levels. For 3.3-V I/O,

V_ref= 1.5 V. For 1.8-V I/O, V_ref= 0.9 V.

V_ref

Figure 8-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks, V_OL

MAX and V_OHMIN for output clocks.

V_ref= V_IHMIN (or V_OHMIN)

V_ref= V_ILMAX (or V_OLMAX)

Figure 8-3. Rise and Fall Transition Time Voltage Reference Levels

8.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

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8.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

For the DDR2/3, PCIe, SATA, USB, and HDMI interfaces, IBIS models are not used for timing

specification. TI provides, in this document, a PCB routing rule solution for each interface that describes

the routing rules used to ensure the interface timings are met. Video DAC guidelines (Section 8.10.3) are

also included to discuss important layout considerations.

8.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IHand V_IL(or between V_ILand V_IH) in a monotonic

manner.

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8.3 DDR2/3 Memory Controller

The device has a dedicated interface to DDR3 and DDR2 SDRAM. It supports JEDEC standard-compliant

DDR2 and DDR3 SDRAM devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, and 2Gb devices

Support for two independent chip selects, with their corresponding register sets, and independent page

tracking

•

Two interfaces with associated DDR2/3 PHYs

Dynamic memory manager allows for interleaving of data between the two DDR interfaces.

For details on the DDR2/3 Memory Controller, see the DDR2/3 Memory Controller chapter in the AM38x

Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.3.1 DDR2 Routing Guidelines

CAUTION

The DDR2 Routing Guidelines are preliminary and are being verified by design

simulations.

8.3.1.1 Board Designs

TI only supports board designs that follow the guidelines outlined in this document. The switching

characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-1 and

Figure 8-4.

Table 8-1. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller

-1G

NO.

PARAMETER

UNIT

MIN

MAX

1

t_{c(DDR_CLK)}

Cycle time, DDR_CLK

2.5

8

ns

1

DDR_CLK

Figure 8-4. DDR2 Memory Controller Clock Timing

8.3.1.2 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding the guidelines for using this DDR2

specification, see Understanding TI’s PCB Routing Rule-Based DDR2 Timing Specification Application

Report (SPRAAV0).

8.3.1.2.1 DDR2 Interface Schematic

Figure 8-5 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-6 the x16

DDR2 system schematic is identical except that the high-word DDR2 device is deleted.

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DDR2

DQ0

DDR[x]_D[0]

DDR[x]_D[7]

DQ7

LDM

LDQS

DDR[x]_DQM[0]

DDR[x]_DQS[0]

DDR[x]_D[8]

LDQS

DQ8

DDR[x]_D[15]

DDR[x]_DQM[1]

DDR[x]_DQS[1]

DQ15

UDM

UDQS

DDR[x]_DQS[1]

UDQS

ODT

DDR[x]_ODT[0]

T0

DDR2

ODT

DDR_ODT1

DDR_D16

NC

DQ0

DDR[x]_D[23

DDR[x]_DQM[2]

DDR[x]_DQS[2]

DQ7

LDM

LDQS

DDR[x]_DQS[2]

DDR[x]_D[24]

LDQS

DQ8

DDR[x]_D[31]

DDR[x]_DQM[3]

DDR[x]_DQS[3]

DQ15

UDM

UDQS

DDR[x]_BA[0]

T0

BA0

DDR[x]_BA[2]

DDR[x]_A[0]

T0

BA2

A0

BA2

A0

DDR[x]_A[14]

DDR[x]_CS[0]

T0

A14

CS

A14

CS

DDR[x]_CS[1]

DDR[x]_CAS

DDR[x]_RAS

NC

CAS

RAS

Vio 1.8^(A)

CAS

RAS

T0

DDR[x]_WE

DDR[x]_CKE

WE

CKE

0.1 µF

1 K Ω 1%

DDR[x]_CLK[x]

CK

DDR[x]_CLK[x]

VREF VREF

VREFSSTL_DDR[x]

VREF

0.1 µF^(B)

1 K Ω 1%

DDR[x]_RST

DDR[x]_VTP

NC

50 Ω ( 2%)

T0

Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the AM389x DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-5. 32-Bit DDR2 High-Level Schematic

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DDR2

DQ0

DDR[x]_D[0]

DDR[x]_D[7]

DQ7

LDM

LDQS

DDR[x]_DQM[0]

DDR[x]_DQS[0]

DDR[x]_D[8]

LDQS

DQ8

DDR[x]_D[15]

DDR[x]_DQM[1]

DDR[x]_DQS[1]

DQ15

UDM

UDQS

DDR[x]_ODT[0]

DDR[x]_ODT[1]

DDR[x]_D[16]

T0

NC

ODT

NC

Vio 1.8^(A)

DDR[x]_D[23]

NC

DDR[x]_DQM[2]

1 KΩ

DDR[x]_DQS[2]

NC

DDR[x]_D[24]

Vio 1.8^(A)

DDR[x]_D[31]

DDR[x]_DQM[3]

DDR[x]_DQS[3]

NC

1 KΩ

DDR[x]_BA[0]

T0

BA0

DDR[x]_BA[2]

DDR[x]_A[0]

T0

BA2

A0

DDR[x]_A[14]

DDR[x]_CS[0]

DDR[x]_CS[1]

DDR[x]_CAS

DDR[x]_RAS

DDR[x]_WE

T0

A14

CS

NC

CAS

RAS

T0

Vio 1.8^(A)

WE

DDR[x]_CKE

DDR[x]_CLK[x]

CKE

CK

1 K Ω 1%

VREF

0.1 µF

DDR[x]_CLK[x]

VREFSSTL_DDR[x]

VREF VREF

0.1 µF^(B)

1 K Ω 1%

DDR[x]_RST

DDR[x]_VTP

NC

50 Ω ( 2%)

T0

Termination is required. See terminator comments.

A. Vio1.8 is the power supply for the DDR2 memories and the AM389x DDR2 interface.

B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.

Figure 8-6. 16-Bit DDR2 High-Level Schematic

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8.3.1.2.2 Compatible JEDEC DDR2 Devices

Table 8-2 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.

Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.

Table 8-2. Compatible JEDEC DDR2 Devices

NO.

1

PARAMETER

MIN

MAX

UNIT

JEDEC DDR2 device speed grade⁽¹⁾

JEDEC DDR2 device bit width

JEDEC DDR2 device count⁽²⁾

JEDEC DDR2 device ball count⁽³⁾

DDR2-800

2

x16

1

x16

2

Bits

Devices

Balls

3

4

84

92

(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.

(2) One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.

(3) The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball

DDR2 devices are the same.

8.3.1.2.3 PCB Stackup

The minimum stackup required for routing the AM389x device is a six-layer stackup as shown in

Table 8-3. Additional layers may be added to the PCB stackup to accommodate other circuitry or to

reduce the size of the PCB footprint.

Table 8-3. Minimum PCB Stackup

LAYER

TYPE

Signal

Plane

Signal

Plane

Signal

DESCRIPTION

Top routing mostly horizontal

Ground

1

2

3

4

5

6

Power

Internal routing

Ground

Bottom routing mostly vertical

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Complete stackup specifications are provided in Table 8-4.

Table 8-4. PCB Stackup Specifications

NO.

1

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing/plane layers

Signal routing layers

6

3

2

3

Full ground layers under DDR2 routing region

Number of ground plane cuts allowed within DDR routing region

Number of ground reference planes required for each DDR2 routing layer

Number of layers between DDR2 routing layer and reference ground plane

PCB routing feature size

4

0

5

1

6

7

4

Mils

8

PCB trace width, w

9

PCB BGA escape via pad size⁽¹⁾

18

10

20

10 PCB BGA escape via hole size⁽¹⁾

11 MPU BGA pad size

12 DDR2 device BGA pad size⁽²⁾

13 Single-ended impedance, Zo

14 Impedance control⁽³⁾

50

75

Ω

Z-5

Z

Z+5

(1) A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the

MPU.

(2) For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.

(3) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

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8.3.1.2.4 Placement

Figure 8-7 shows the required placement for the MPU as well as the DDR2 devices. The dimensions for

this figure are defined in Table 8-5. The placement does not restrict the side of the PCB on which the

devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and

allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device is omitted

from the placement.

Recommended DDR2 Device

Orientation

X

1

X

A1

1

X

OFFSET OFFSET

Y

Figure 8-7. AM389x Device and DDR2 Device Placement

Table 8-5. Placement Specifications

NO.

1

PARAMETER

MIN

MAX

1660

1280

650

UNIT

Mils

X + Y⁽¹⁾⁽²⁾

X^'(1)(2)

X^'Offset^{(1)(2) (3)}

DDR2 keepout region⁽⁴⁾

2

3

4

5

Clearance from non-DDR2 signal to DDR2 keepout region⁽⁵⁾

4

w

(1) For dimension definitions, see Figure 8-5.

(2) Measurements from center of MPU to center of DDR2 device.

(3) For 16-bit memory systems, it is recommended that X^'offset be as small as possible.

(4) DDR2 keepout region to encompass entire DDR2 routing area.

(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.

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8.3.1.2.5 DDR2 Keepout Region

The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2

keepout region is defined for this purpose and is shown in Figure 8-8. The size of this region varies with

the placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 8-5.

A1

DDR2 Device

A1

Figure 8-8. DDR2 Keepout Region

NOTE

The region shown in should encompass all the DDR2 circuitry and varies depending on

placement. Non-DDR2 signals should not be routed on the DDR signal layers within the

DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided t hey are

routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be

allowed in the reference ground layers in this region. In addition, the 1.8V power plane

should cover the entire keepout region. Routes for the two DDR interfaces must be

separated by at least 4x; the more separation, the better.

8.3.1.2.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 8-6 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk

bypass capacitance may be needed for other circuitry.

Table 8-6. Bulk Bypass Capacitors

No. Parameter

Min

6

Max

Unit

Devices

μF

1

2

3

4

5

6

DVDD18 bulk bypass capacitor count⁽¹⁾

DVDD18 bulk bypass total capacitance

DDR#1 bulk bypass capacitor count⁽¹⁾

DDR#1 bulk bypass total capacitance⁽¹⁾

DDR#2 bulk bypass capacitor count⁽²⁾

DDR#2 bulk bypass total capacitance⁽¹⁾⁽²⁾

60

1

Devices

μF

10

1

Devices

μF

10

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].

(2) Only used on 32-bit wide DDR2 memory systems.

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8.3.1.2.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, MPU/DDR power, and

MPU/DDR ground connections. Table 8-7 contains the specification for the HS bypass capacitors as well

as for the power connections on the PCB.

Table 8-7. High-Speed Bypass Capacitors

NO.

1

PARAMETER

MIN

MAX

UNIT

HS bypass capacitor package size⁽¹⁾

0402 10 Mils

2

Distance from HS bypass capacitor to device being bypassed

Number of connection vias for each HS bypass capacitor⁽²⁾

Trace length from bypass capacitor contact to connection via

Number of connection vias for each MPU power/ground ball

Trace length from MPU power/ground ball to connection via

Number of connection vias for each DDR2 device power/ground ball

Trace length from DDR2 device power/ground ball to connection via

DVDD18 HS bypass capacitor count⁽³⁾⁽⁴⁾

250

30

Mils

Vias

Mils

3

2

1

4

5

Vias

Mils

6

35

7

1

Vias

Mils

8

35

9

40

2.4

8

Devices

μF

10 DVDD18 HS bypass capacitor total capacitance⁽⁵⁾

11 DDR device HS bypass capacitor count⁽⁶⁾⁽⁷⁾

12 DDR device HS bypass capacitor total capacitance⁽⁷⁾

Devices

μF

0.4

(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.

(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3) These devices should be placed as close as possible to the device being bypassed.

(4) Use half of these capacitors for DDR[0] and half for DDR[1].

(5) Use half of these capacitors for DDR[0] and half for DDR[1].

(6) These devices should be placed as close as possible to the device being bypassed.

(7) Per DDR device.

8.3.1.2.8 Net Classes

Table 8-8 lists the clock net classes for the DDR2 interface. Table 8-9 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-8. Clock Net Class Definitions

CLOCK NET CLASS MPU PIN NAMES

CK

DDR[x]_CLK[x]/DDR[x]_CLK[x]

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DDR[x]_DQS[3]/DDR[x]_DQS[3]

DQS0

DQS1

DQS2⁽¹⁾

DQS3⁽¹⁾

(1) Only used on 32-bit wide DDR2 memory systems.

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Table 8-9. Signal Net Class Definitions

ASSOCIATED CLOCK

CLOCK NET CLASS

MPU PIN NAMES

NET CLASS

ADDR_CTRL

CK

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE

DQ0

DQ1

DQ2⁽¹⁾

DQ3⁽¹⁾

DQS0

DQS1

DQS2

DQS3

DDR[x]_D[7:0], DDR[x]_DQM[0]

DDR[x]_D[15:8], DDR[x]_DQM[1]

DDR[x]_D[23:16], DDR[x]_DQM[2]

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1) Only used on 32-bit wide DDR2 memory systems.

8.3.1.2.9 DDR2 Signal Termination

Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on

data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODT's are

integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-10

shows the specifications for the series terminators.

Table 8-10. DDR2 Signal Terminations

No. Parameter

Min

0

Typ

Max Unit

1

2

3

CK net class⁽¹⁾

ADDR_CTRL net class^(1)(2)(3)

Data byte net classes (DQS0-DQS3, DQ0-DQ3)^(1)(2)(3)(4)

10

Zo

Ω

0

22

0

(1) Only series termination is permitted, parallel or SST specifically disallowed on board.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

(4) Only required for GMI reduction.

8.3.1.2.10 VREFSSTL_DDR Routing

VREFSSTL_DDR is used as a reference by the input buffers of the DDR2 memories as well as the MPU.

VREF is intended to be half the DDR2 power supply voltage and should be created using a resistive

divider as shown in Figure 8-6. Other methods of creating VREF are not recommended. Figure 8-9 shows

the layout guidelines for VREF.

VREF Nominal Max Trace

width is 20 mils

DDR2 Device

VREF Bypass Capacitor

A1

+

DDR2 Controller

Neck down to minimum in BGA escape

regions is acceptable. Narrowing to

accomodate via congestion for short

distances is also acceptable. Best

performance is obtained if the width

of VREF is maximized.

Figure 8-9. VREF Routing and Topology

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8.3.1.3 DDR2 CK and ADDR_CTRL Routing

Figure 8-10 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

(A'+A'') should be maximized.

A1

B

C

A´´

T

A´

A = A´ + A´´

Figure 8-10. CK and ADDR_CTRL Routing and Topology

(1)

Table 8-11. CK and ADDR_CTRL Routing Specification

NO.

1

PARAMETER

MIN

TYP

MAX

2w

UNIT

Center-to-center CK-CK spacing

CK/CK skew⁽¹⁾

2

25

Mils

3

CK B-to-C skew length mismatch

25

4

Center-to-center CK to other DDR2 trace spacing⁽²⁾

CK/ADDR_CTRL nominal trace length⁽³⁾

4w

5

CACLM-50

CACLM

CACLM+50

100

Mils

6

ADDR_CTRL-to-CK skew length mismatch

7

ADDR_CTRL-to-ADDR_CTRL skew length mismatch

Center-to-center ADDR_CTRL to other DDR2 trace spacing⁽²⁾

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽²⁾

ADDR_CTRL B-to-C skew length mismatch

100

8

4w

3w

9

10

100

Mils

(1) The length of segment A=A'+A′′ as shown in Figure 8-10.

(2) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

Figure 8-11 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

T

A1

E2

E3

E0

E1

Figure 8-11. DQS and DQ Routing and Toplogy

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Table 8-12. DQS and DQ Routing Specification

PARAMETER

MIN

TYP

MAX

2w

UNIT

1

2

3

4

5

6

7

8

9

Center-to-center DQS-DQSn spacing in E0|E1|E2|E3

DQS-DQSn skew in E0|E1|E2|E3

Center-to-center DQS to other DDR2 trace spacing⁽¹⁾

25

Mils

4w

(2)(3)(4)

DQS/DQ nominal trace length

DQ-to-DQS skew length mismatch^(2)(3)(4)

DQ-to-DQ skew length mismatch^(2)(3)(4)

DQ-to-DQ/DQS via count mismatch^(2)(3)(4)

Center-to-center DQ to other DDR2 trace spacing⁽¹⁾⁽⁵⁾

Center-to-center DQ to other DQ trace spacing^(1)(6)(7)

DQLM-50

DQLM

DQLM+50

Mils

Vias

100

1

4w

3w

10 DQ/DQS E skew length mismatch^(2)(3)(4)

100

Mils

(1) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs) per DDR EMIF used.

(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS

(4 DQSs) per DDR EMIF used.

(4) There is no need, and it is not recommended, to skew match across data bytes; i.e., from DQS0 and data byte 0 to DQS1 and data

byte 1.

(5) DQs from other DQS domains are considered other DDR2 trace.

(6) DQs from other data bytes are considered other DDR2 trace.

(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

8.3.2 DDR3 Routing Guidelines

CAUTION

The DDR3 Routing Guidelines are preliminary and are being verified by design

simulations.

8.3.2.1 Board Designs

TI only supports board designs utilizing DDR3 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-13 and

Figure 8-12.

Table 8-13. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Controller

-1G

NO.

PARAMETER

UNIT

MIN

MAX

1

t_{c(DDR_CLK)}

Cycle time, DDR_CLK

1.25

3.3⁽¹⁾

ns

(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and

operating frequency (see the DDR3 memory device data sheet).

1

DDR_CLK

Figure 8-12. DDR3 Memory Controller Clock Timing

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8.3.2.1.1 DDR3 versus DDR2

This specification only covers AM389x MPU PCB designs that utilize DDR3 memory. Designs using DDR2

memory should use the PCB design specifications for DDR2 memory in Section 8.3.1. While similar, the

two memory systems have different requirements. It is currently not possible to design one PCB that

covers both DDR2 and DDR3.

8.3.2.2 DDR3 Device Combinations

Since there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-14 summarizes the supported device configurations.

Table 8-14. Supported DDR3 Device Combinations⁽¹⁾

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

1

2

4

16

8

N

Y⁽²⁾

N

16

32

16

8

Y⁽²⁾

N

Y⁽³⁾

8

(1) This table is per EMIF.

(2) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(3) This is two mirrored pairs of DDR3 devices.

8.3.2.2.1 DDR3 EMIFs

The MPU contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (DDR[0])

and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be

a semi-mirror with DDR[1] being a flipped version of DDR[0]; the only exception being the DDR3 devices

themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical

between the two EMIFs.

8.3.2.3 DDR3 Interface Schematic

8.3.2.3.1 32-Bit DDR3 Interface

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 8-13 and Figure 8-14 show the schematic connections for 32-bit

interfaces using x16 devices.

8.3.2.3.2 16-Bit DDR3 Interface

Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-13

and Figure 8-14); only the high-word DDR memories are removed and the unused DQS inputs are tied off.

The MPU DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to the DDR supply via 1-kΩ

resistors. Similarly, the DDR[x]_DQS[2] and DDR[x]_DQS[3] pins should be pulled to ground via 1-kΩ

resistors.

When not using a DDR interface, the proper method of handling the unused pins is to tie off the DQS pins

by pulling the non-inverting DQS pin to the DDR_1V5 supply via a 1k-Ω resistor and pulling the inverting

DQSn pin to ground via a 1k-Ω resistor. This needs to be done for each byte not used. Also, include the

50-Ω pulldown for DDR[x]_VTP. All other DDR interface pins can be left unconnected. Note that the

supported modes for use of the DDR EMIF are 32 bits wide, 16 bits wide, or not used.

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32-bit DDR3 EMIF

DDR[0] or DDR[1]

DDR[x]_CLK[1]

DDR[x]_ODT[1]

DDR[x]_CS[1]

NC

16-Bit DDR3

Devices

DDR[x]_D[31]

DQ15

8

DDR[x]_D[24]

DQ8

DDR[x]_DQM[3]

DDR[x]_DQS[3]

UDM

UDQS

DDR[x]_D[23]

DQ7

8

DDR[x]_D[16]

D08

DDR[x]_DQM[2]

DDR[x]_DQS[2]

LDM

LDQS

DDR[x]_D[15]

DQ15

DQ8

8

DDR[x]_D[8]

DDR[x]_DQM[1]

DDR[x]_DQS[1]

UDM

UDQS

DDR[x]_D[7]

DQ7

8

DDR[x]_D[0]

DQ0

DDR[x]_DQM[0]

DDR[x]_DQS[0]

LDM

LDQS

0.1 µF

Zo

DDR[x]_CLK[0]

CK

DDR_1V5

DDR[x]_ODT[0]

DDR[x]_CS[0]

DDR[x]_BA[0]

DDR[x]_BA[1]

DDR[x]_BA[2]

ODT

CS

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

Zo

DDR[x]_A[0]

A0

15

DDR[x]_A[14]

A14

DDR[x]_CAS

DDR[x]_RAS

DDR[x]_WE

DDR[x]_CKE

DDR[x]_RST

CAS

RAS

WE

RAS

WE

CKE

RST

DDR_VREF

RST

ZQ

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFSSTL_DDR[x]

0.1 µF

DDR[x]_VTP

50 Ω ( 2%)

Zo

ZQ

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

Figure 8-13. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices

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32-bit DDR3 EMIF

DDR[0] or DDR[1]

DDR[x]_CLK[1]

DDR[x]_ODT[1]

DDR[x]_CS[1]

NC

8-Bit DDR3

Devices

8-Bit DDR3

Devices

DDR[x]_D[31]

DQ7

DQ0

8

DDR[x]_D[24]

DDR[x]_DQM[3]

DM/TQS

TDQS

DQS

NC

DDR[x]_DQS[3]

DQS

DDR[x]_D[23]

DQ7

DQ0

8

DDR[x]_D[16]

DDR[x]_DQM[2]

DM/TQS

TDQS

DQS

NC

DDR[x]_DQS[2]

DQS

DDR[x]_D[15]

DQ7

DQ0

8

DDR[x]_D[8]

DDR[x]_DQM[1]

DM/TQS

TDQS

DQS

NC

DDR[x]_DQS[1]

DQS

DDR[x]_D[7]

DQ7

DQ0

8

DDR[x]_D[0]

DDR[x]_DQM[0]

DM/TQS

TDQS

DQS

NC

DDR[x]_DQS[0]

DQS

0.1 µF

Zo

DDR[x]_CLK[0]

CK

DDR_1V5

DDR[x]_ODT[0]

DDR[x]_CS[0]

DDR[x]_BA[0]

DDR[x]_BA[1]

DDR[x]_BA[2]

ODT

CS

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

BA0

BA1

BA2

DDR_VTT

Zo

DDR[x]_A[0]

A0

15

DDR[x]_A[14]

A14

DDR[x]_CAS

DDR[x]_RAS

DDR[x]_WE

DDR[x]_CKE

DDR[x]_RST

CAS

RAS

WE

CAS

RAS

WE

RAS

WE

CKE

RST

CKE

RST

DDR_VREF

ZQ

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFDQ

VREFCA

VREFSSTL_DDR[x]

0.1 µF

DDR[x]_VTP

50 Ω ( 2%)

Zo

ZQ

Termination is required. See terminator comments.

Value determined according to the DDR memory device data sheet.

Figure 8-14. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices

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8.3.2.4 Compatible JEDEC DDR3 Devices

Table 8-15 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

Generally, the DDR3 interface is compatible with DDR3-1600 devices in the x8 or x16 widths.

Table 8-15. Compatible JEDEC DDR3 Devices

NO.

1

PARAMETER

MIN

MAX

UNIT

JEDEC DDR3 device speed grade⁽¹⁾

JEDEC DDR3 device bit width

JEDEC DDR3 device count⁽²⁾

DDR3-800

DDR3-1600

2

x8

2

x16

8

Bits

3

Devices

(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-1600, the clock rate is 800 MHz.

(2) For valid DDR3 device configurations and device counts, see Section 8.3.2.3, Figure 8-13, and Figure 8-14.

8.3.2.5 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-16.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI

performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-17.

Complete stackup specifications are provided in Table 8-18.

Table 8-16. Minimum PCB Stackup

LAYER

TYPE

Signal

Plane

Signal

DESCRIPTION

1

2

3

4

Top routing mostly vertical

Split power plane

Full ground plane

Bottom routing mostly horizontal

Table 8-17. Six-Layer PCB Stackup Suggestion

LAYER

TYPE

Signal

Plane

Signal

DESCRIPTION

1

2

3

4

5

6

Top routing mostly vertical

Ground

Split power plane

Split power plane or Internal routing

Ground

Bottom routing mostly horizontal

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UNIT

Table 8-18. PCB Stackup Specifications

NO.

1

PARAMETER

MIN

4

TYP

MAX

PCB routing/plane layers

Signal routing layers

6

2

3

Full ground reference layers under DDR3 routing region⁽¹⁾

Full 1.5-V power reference layers under the DDR3 routing region⁽¹⁾

Number of reference plane cuts allowed within DDR routing region⁽²⁾

Number of layers between DDR3 routing layer and reference plane⁽³⁾

PCB routing feature size

1

4

1

5

0

6

7

4

Mils

mm

8

PCB trace width, w

PCB BGA escape via pad size⁽⁴⁾

9

18

10

0.3

20

10 PCB BGA escape via hole size

11 MPU BGA pad size

12 DDR3 device BGA pad size⁽⁵⁾

13 Single-ended impedance, Zo

14 Impedance control⁽⁶⁾

50

75

Ω

Z-5

Z

Z+5

(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(5) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.

(6) Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

8.3.2.6 Placement

Figure 8-15 shows the required placement for the MPU as well as the DDR3 devices. The dimensions for

this figure are defined in Table 8-19. The placement does not restrict the side of the PCB on which the

devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and

allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 device(s) are

omitted from the placement.

X1

X2

DDR3

Controller

Y

Figure 8-15. Placement Specifications

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Table 8-19. Placement Specifications

PARAMETER

MIN

MAX

1000

600

UNIT

Mils

1

2

3

4

5

X1^(1)(2)(3)

X2⁽¹⁾⁽²⁾

Y Offset^(1)(2)(3)

1500

DDR3 keepout region

Clearance from non-DDR3 signal to DDR3 keepout region^(4)(5)(6)

4

w

(1) For dimension definitions, see Figure 8-15.

(2) Measurements from center of MPU to center of DDR3 device.

(3) Minimizing X1 and Y improves timing margins.

(4) w is defined as the signal trace width.

(5) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

(6) Note that DDR3 signals from one DDR3 controller are considered non-DDR3 to the other controller. In other words, keep the two DDR3

interfaces separated by this specification.

8.3.2.7 DDR3 Keepout Region

The region of the PCB used for DDR3 circutry must be isolated from other signals. The DDR3 keepout

region is defined for this purpose and is shown in Figure 8-16. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keepout region are shown in

Table 8-19. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout

region. Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from

the DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in

this region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note

that the two DDR3 controller's signals should be separated from each other by the specification in

Table 8-19, item 5.

DDR3 Controllers

DDR[1] Keep Out Region

DDR[0] Keep Out Region

Encompasses Entire DDR[1] Routing Area

Encompasses Entire DDR[0] Routing Area

Figure 8-16. DDR3 Keepout Region

8.3.2.8 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.

Table 8-20 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR3 controllers and DDR3 device(s). Additional bulk

bypass capacitance may be needed for other circuitry. Also note that Table 8-20 is per DDR3 controller;

thus, systems using both controllers have to meet the needs of Table 8-20 twice, once for each controller.

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Table 8-20. Bulk Bypass Capacitors

NO.

PARAMETER

DDR_1V5 bulk bypass capacitor count⁽¹⁾

MIN

6

MAX

UNIT

Devices

μF

1

2

DDR_1V5 bulk bypass total capacitance

140

(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the

high-speed (HS) bypass capacitors and DDR3 signal routing.

8.3.2.9 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass capacitors, MPU/DDR power, and

MPU/DDR ground connections. Table 8-21 contains the specification for the HS bypass capacitors as well

as for the power connections on the PCB. Generally speaking, it is good to:

1. Fit as many HS bypass capacitors as possible.

2. Minimize the distance from the bypass cap to the pins/balls being bypassed.

3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.

4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest

hole size via possible.

5. Minimize via sharing. Note the limites on via sharing shown in Table 8-21.

Table 8-21. High-Speed Bypass Capacitors

NO.

1

PARAMETER

HS bypass capacitor package size⁽¹⁾

MIN

TYP

MAX

UNIT

201

402 10 Mils

2

Distance, HS bypass capacitor to MPU being bypassed^(2)(3)(4)

400

Mils

Devices

μF

3

MPU DDR_1V5 HS bypass capacitor count

70

5

4

MPU DDR_1V5 HS bypass capacitor total capacitance

Number of connection vias for each device power/ground ball⁽⁵⁾

Trace length from device power/ground ball to connection via⁽²⁾

Distance, HS bypass capacitor to DDR device being bypassed⁽⁶⁾

DDR3 device HS bypass capacitor count⁽⁷⁾

5

Vias

Mils

6

35

70

7

150

Mils

8

12

0.85

2

Devices

μF

9

DDR3 device HS bypass capacitor total capacitance⁽⁷⁾

10 Number of connection vias for each HS capacitor⁽⁸⁾⁽⁹⁾

Vias

Mils

11 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁹⁾

12 Number of connection vias for each DDR3 device power/ground ball⁽¹⁰⁾

13 Trace length from DDR3 device power/ground ball to connection via⁽²⁾⁽⁸⁾

35

100

60

1

Vias

Mils

(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.

(2) Closer/shorter is better.

(3) Measured from the nearest MPU power/ground ball to the center of the capacitor package.

(4) Three of these capacitors should be located underneath the MPU, between the cluster of DDR_1V5 balls and ground balls, between the

DDR interfaces on the package.

(5) See the Via Channel™ escape for the MPU package.

(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.

(7) Per DDR3 device.

(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of

vias is permitted on the same side of the board.

(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the

connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.

(10) Up to a total of two pairs of DDR power/ground balls may share a via.

8.3.2.9.1 Return Current Bypass Capacitors

Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals

hopping from one signal layer to another. The bypass capacitor here provides a path for the return current

to hop planes along with the signal. As many of these return current bypass capacitors should be used as

possible. Since these are returns for signal current, the signal via size may be used for these capacitors.

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8.3.2.10 Net Classes

Table 8-22 lists the clock net classes for the DDR3 interface. Table 8-23 lists the signal net classes, and

associated clock net classes, for signals in the DDR3 interface. These net classes are used for the

termination and routing rules that follow.

Table 8-22. Clock Net Class Definitions

CLOCK NET CLASS MPU PIN NAMES

CK

DDR[x]_CLK[x]/DDR[x]_CLK[x]

DDR[x]_DQS[0]/DDR[x]_DQS[0]

DDR[x]_DQS[1]/DDR[x]_DQS[1]

DDR[x]_DQS[2]/DDR[x]_DQS[2]

DDR[x]_DQS[3]/DDR[x]_DQS[3]

DQS0

DQS1

DQS2⁽¹⁾

DQS3⁽¹⁾

(1) Only used on 32-bit wide DDR3 memory systems.

Table 8-23. Signal Net Class Definitions

ASSOCIATED CLOCK

MPU PIN NAMES

NET CLASS

CLOCK NET CLASS

ADDR_CTRL

CK

DDR[x]_BA[2:0], DDR[x]_A[14:0], DDR[x]_CS[x], DDR[x]_CAS, DDR[x]_RAS,

DDR[x]_WE, DDR[x]_CKE

DQ0

DQ1

DQ2⁽¹⁾

DQ3⁽¹⁾

DQS0

DQS1

DQS2

DQS3

DDR[x]_D[7:0], DDR[x]_DQM[0]

DDR[x]_D[15:8], DDR[x]_DQM[1]

DDR[x]_D[23:16], DDR[x]_DQM[2]

DDR[x]_D[31:24], DDR[x]_DQM[3]

(1) Only used on 32-bit wide DDR3 memory systems.

8.3.2.11 DDR3 Signal Termination

Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by

ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in

the routing rules in the following sections.

8.3.2.12 VREFSSTL_DDR Routing

VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as

the MPU. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the

DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF bypass

capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing

congestion.

8.3.2.13 VTT

Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is

expected to source and sink current, specifically the termination current for the ADDR_CTRL net class

Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power

sub-plane. VTT should be bypassed near the terminator resistors.

8.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition

The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew

between them. CK is a bit more complicated because it runs at a higher transition rate and is differiential.

The following subsections show the topology and routing for various DDR3 configurations for CK and

ADDR_CTRL. The figures in the following subsections define the terms for the routing specification

detailed in Table 8-24.

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8.3.2.14.1 Four DDR3 Devices

Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one

bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two

pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.

8.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices

Figure 8-17 shows the topology of the CK net classes and Figure 8-18 shows the topology for the

corresponding ADDR_CTRL net classes.

DDR Differential CK Input Buffers

–

+

Clock Parallel

Terminator

DDR_1V5

Rcp

A1

A2

A3

A4

A3

AT

Cac

MPU

Differential Clock

Output Buffer

+

–

0.1 µF

Rcp

Routed as Differential Pair

Figure 8-17. CK Topology for Four x8 DDR3 Devices

DDR Address/Control Input Buffers

Address/Control

Terminator

Rtt

MPU

Address/Control

Output Buffer

A1

A2

A3

A4

A3

AT

Vtt

Figure 8-18. ADDR_CTRL Topology for Four x8 DDR3 Devices

8.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices

Figure 8-19 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-20

shows the corresponding ADDR_CTRL routing.

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DDR_1V5

Cac

Rcp

A2

A3

A4

A3

AT

0.1 µF

=

Figure 8-19. CK Routing for Four Single-Side DDR3 Devices

Rtt

A2

A3

A4

A3

AT

Vtt

=

Figure 8-20. ADDR_CTRL Routing for Four Single-Side DDR3 Devices

To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of

increased routing and assembly complexity. Figure 8-21 and Figure 8-22 show the routing for CK and

ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.

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DDR_1V5

Cac

Rcp

A2

A3

A4

A3

AT

0.1 µF

=

Figure 8-21. CK Routing for Four Mirrored DDR3 Devices

Rtt

A2

A3

A4

A3

AT

Vtt

=

Figure 8-22. ADDR_CTRL Routing for Four Mirrored DDR3 Devices

8.3.2.14.2 Two DDR3 Devices

Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one

bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two

devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at

a cost of increased routing complexity and parts on the backside of the PCB.

8.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices

Figure 8-23 shows the topology of the CK net classes and Figure 8-24 shows the topology for the

corresponding ADDR_CTRL net classes.

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DDR Differential CK Input Buffers

–

+

Clock Parallel

Terminator

DDR_1V5

Rcp

A1

A2

A3

AT

Cac

MPU

+

–

Differential Clock

Output Buffer

0.1 µF

Rcp

AT

Routed as Differential Pair

Figure 8-23. CK Topology for Two DDR3 Devices

DDR Address/Control Input Buffers

Address/Control

Terminator

Rtt

MPU

Address/Control

Output Buffer

A1

A2

A3

AT

Vtt

Figure 8-24. ADDR_CTRL Topology for Two DDR3 Devices

8.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices

Figure 8-25 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-26

shows the corresponding ADDR_CTRL routing.

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DDR_1V5

Cac

Rcp

A2

A3

AT

0.1 µF

=

Figure 8-25. CK Routing for Two Single-Side DDR3 Devices

Rtt

A2

A3

AT

Vtt

=

Figure 8-26. ADDR_CTRL Routing for Two Single-Side DDR3 Devices

To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased

routing and assembly complexity. Figure 8-27 and Figure 8-28 show the routing for CK and ADDR_CTRL,

respectively, for two DDR3 devices mirrored in a single-pair configuration.

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DDR_1V5

Cac

Rcp

A2

A3

AT

0.1 µF

=

Figure 8-27. CK Routing for Two Mirrored DDR3 Devices

Rtt

A2

A3

AT

Vtt

=

Figure 8-28. ADDR_CTRL Routing for Two Mirrored DDR3 Devices

8.3.2.14.3 One DDR3 Device

A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as

one bank (CS), 16 bits wide.

8.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device

Figure 8-29 shows the topology of the CK net classes and Figure 8-30 shows the topology for the

corresponding ADDR_CTRL net classes.

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DDR Differential CK Input Buffer

–

+

Clock Parallel

Terminator

DDR_1V5

Rcp

A1

A2

AT

Cac

MPU

Differential Clock

Output Buffer

+

–

0.1 µF

Rcp

Routed as Differential Pair

Figure 8-29. CK Topology for One DDR3 Device

DDR Address/Control Input Buffers

Address/Control

Terminator

Rtt

MPU

Address/Control

Output Buffer

A1

A2

AT

Vtt

Figure 8-30. ADDR_CTRL Topology for One DDR3 Device

8.3.2.14.3.2 CK and ADDR/CTRL Routing, One DDR3 Device

Figure 8-31 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-32

shows the corresponding ADDR_CTRL routing.

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DDR_1V5

Cac

Rcp

A2

AT

0.1 µF

=

Figure 8-31. CK Routing for One DDR3 Device

Rtt

A2

AT

Vtt

=

Figure 8-32. ADDR_CTRL Routing for One DDR3 Device

8.3.2.15 Data Topologies and Routing Definition

No matter the number of DDR3 devices used, the data line topology is always point to point, so its

definition is simple.

8.3.2.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices

DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-33

and Figure 8-34 show these topologies.

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MPU

DQS

DDR

DQSn+

DQSn-

DQS

I/O Buffer

Routed Differentially

n = 0, 1, 2, 3

Figure 8-33. DQS Topology

MPU

DQ/DM

DDR

Dn

DQ/DM

I/O Buffer

n = 0, 1, 2, 3

Figure 8-34. DQ/DM Topology

8.3.2.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices

Figure 8-35 and Figure 8-36 show the DQS and DQ/DM routing.

DQS

DQSn+

DQSn-

Routed Differentially

n = 0, 1, 2, 3

Figure 8-35. DQS Routing With Any Number of Allowed DDR3 Devices

DQ/DM

Dn

n = 0, 1, 2, 3

Figure 8-36. DQ/DM Routing With Any Number of Allowed DDR3 Devices

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8.3.2.16 Routing Specification

8.3.2.16.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this

skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter

traces up to the length of the longest net in the net class and its associated clock. A metric to establish

this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the

length between the points when connecting them only with horizontal or vertical segments. A reasonable

trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address

Control Longest Manhattan distance.

Given the clock and address pin locations on the MPU and the DDR3 memories, the maximum possible

Manhattan distance can be determined given the placement. Figure 8-37 and Figure 8-38 show this

distance for four loads and two loads, respectively. It is from this distance that the specifications on the

lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for

other address bus configurations; i.e., it is based on the longest net of the CK/ADDR_CTRL net class. For

CK and ADDR_CTRL routing, these specifications are contained in Table 8-24.

A8^(A)

CACLMY

CACLMX

A8^(A)

Rtt

A2

A3

A4

A3

AT

Vtt

=

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3

memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that

satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length caculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-37. CACLM for Four Address Loads on One Side of PCB

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A8^(A)

CACLMY

CACLMX

A8^(A)

Rtt

A2

A3

AT

Vtt

=

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3

memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that

satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this

length caculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.

The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-38. CACLM for Two Address Loads on One Side of PCB

Table 8-24. CK and ADDR_CTRL Routing Specification⁽¹⁾⁽²⁾

NO.

1

PARAMETER

MIN

TYP

MAX

2500

25

UNIT

mils

A1+A2 length

A1+A2 skew

A3 length

A3 skew⁽³⁾

A3 skew⁽⁴⁾

A4 length

A4 skew

2

3

660

25

4

5

125

660

25

6

7

8

AS length

AS skew

100

70

9

10 AS+/AS- length

11 AS+/AS- skew

12 AT length⁽⁵⁾

13 AT skew⁽⁶⁾

14 AT skew⁽⁷⁾

15 CK/ADDR_CTRL nominal trace length⁽⁸⁾

5

500

100

5

CACLM-50

CACLM

CACLM+50

(1) The use of vias should be minimized.

(2) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump

between the DDR_1V5 plane and the ground plane when the net class swtiches layers at a via.

(3) Non-mirrored configuration (all DDR3 memories on same side of PCB).

(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

(5) While this length can be increased for convienience, its length should be minimized.

(6) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.

(7) CK net class only.

(8) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 8.3.2.16.1,

Figure 8-37, and Figure 8-38.

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Table 8-24. CK and ADDR_CTRL Routing Specification (continued)

PARAMETER

MIN

4w

TYP

MAX

UNIT

16 Center-to-center CK to other DDR3 trace spacing⁽⁹⁾

17 Center-to-center ADDR_CTRL to other DDR3 trace spacing^(9)(10)

18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing⁽⁹⁾

19 CK center-to-center spacing⁽¹¹⁾

4w

3w

20 CK spacing to other net⁽⁹⁾

21 Rcp⁽¹²⁾

22 Rtt^(12)(13)

4w

Zo-1

Zo-5

Zo

Zo+

Ω

Zo+5

(9) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.

(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.

(11) CK spacing set to ensure proper differential impedance.

(12) Source termination (series resistor at driver) is specifically not allowed.

(13) Termination values should be uniform across the net class.

8.3.2.16.2 DQS and DQ Routing Specification

Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew

must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces

up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,

a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as

DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four

DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

It is not required, nor is it recommended, to match the lengths across all bytes. Length

matching is only required within each byte.

Given the DQS and DQ/DM pin locations on the MPU and the DDR3 memories, the maximum possible

Manhattan distance can be determined given the placement. Figure 8-39 shows this distance for four

loads. It is from this distance that the specifications on the lengths of the transmission lines for the data

bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-25.

DQLMX0

DQ[0:7]/DM0/DQS0

DB0

DQ[8:15]/DM1/DQS1

DB1

DQLMX1

DQ[16:23]/DM2/DQS2

DB2

DQLMY0

DQLMX2

DQLMY1

DQLMY3 DQLMY2

DQ[23:31]/DM3/DQS3

DB3

DQLMX3

3

2

1

0

DB0 - DB3 represent data bytes 0 - 3.

There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the

byte; therefore:

DQLM0 = DQLMX0 + DQLMY0

DQLM1 = DQLMX1 + DQLMY1

DQLM2 = DQLMX2 + DQLMY2

DQLM3 = DQLMX3 + DQLMY3

Figure 8-39. DQLM for Any Number of Allowed DDR3 Devices

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Table 8-25. Data Routing Specification⁽¹⁾

NO.

1

PARAMETER

MIN

TYP

MAX

DQLM0

DQLM1

DQLM2

DQLM3

25

UNIT

mils

DB0 nominal length⁽²⁾⁽³⁾

DB1 nominal length⁽²⁾⁽⁴⁾

DB2 nominal length⁽²⁾⁽⁵⁾

DB3 nominal length⁽²⁾⁽⁶⁾

DBn skew⁽⁷⁾

2

3

4

5

6

DQSn+ to DQSn- skew

DQSn to DBn skew⁽⁷⁾⁽⁸⁾

5

7

25

8

Center-to-center DBn to other DDR3 trace spacing^(9)(10)

Center-to-center DBn to other DBn trace spacing^(9)(11)

4w

3w

9

10 DQSn center-to-center spacing⁽¹²⁾

11 DQSn center-to-center spacing to other net⁽⁹⁾

4w

(1) External termination disallowed. Data termination should use built-in ODT functionality.

(2) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 8.3.2.16.2 and Figure 8-39.

(3) DQLM0 is the longest Manhattan length for the net classes of Byte 0.

(4) DQLM1 is the longest Manhattan length for the net classes of Byte 1.

(5) DQLM2 is the longest Manhattan length for the net classes of Byte 2.

(6) DQLM3 is the longest Manhattan length for the net slasses of Byte 3.

(7) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.

(8) Each DQS pair is length matched to its associated byte.

(9) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.

(10) Other DDR3 trace spacing means other DDR3 net classes not within the byte.

(11) This applies to spacing within the net classes of a byte.

(12) DQS pair spacing is set to ensure proper differential impedance.

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8.3.3 DDR2/3 Memory Controller Register Descriptions

Table 8-26. DDR2/3 Memory Controller Registers

DDR0 HEX ADDRESS

0x4819 8004

0x4819 8008

0x4819 8010

0x4819 8014

0x4819 8018

0x4819 801C

0x4819 8020

0x4819 8024

0x4819 8028

0x4819 802C

0x4819 8038

0x4819 803C

0x4819 8054

0x4819 80A0

0x4819 80A4

0x4819 80AC

0x4819 80B4

0x4819 80BC

0x4819 80C8

0x4819 80DC

0x4819 80E4

0x4819 80E8

DDR1 HEX ADDRESS

0x4819 A004

0x4819 A008

0x4819 A010

0x4819 A014

0x4819 A018

0x4819 A01C

0x4819 A020

0x4819 A024

0x4819 A028

0x4819 A02C

0x4819 A038

0x4819 A03C

0x4819 A054

0x4819 A0A0

0x4819 A0A4

0x4819 A0AC

0x4819 A0B4

0x4819 A0BC

0x4819 A0C8

0x4819 A0DC

0x4819 A0E4

0x4819 A0E8

ACRONYM

SDRSTAT

SDRCR

REGISTER NAME

SDRAM Status

SDRAM Config

SDRRCR

SDRRCSR

SDRTIM1

SDRTIM1SR

SDRTIM2

SDRTIM2SR

SDRTIM3

SDRTIM3SR

PMCR

SDRAM Refresh Control

SDRAM Refresh Control Shadow

SDRAM Timing 1

SDRAM Timing 1 Shadow

SDRAM Timing 2

SDRAM Timing 2 Shadow

SDRAM Timing 3

SDRAM Timing 3 Shadow

Power Management Control

Power Management Control Shadow

Peripheral Bus Burst Priority

End of Interrupt

PMCSR

PBBPR

EOI

SOIRSR

System OCP Interrupt Raw Status

System OCP Interrupt Status

System OCP Interrupt Enable Set

System OCP Interrupt Enable Clear

SDRAM output Impedance Calibration Config

Read-Write Leveling Control

DDR PHY Control

SOISR

SOIESR

SOIECR

ZQCR

RWLCR

DDRPHYCR

DDRPHYCSR

DDR PHY Control Shadow

8.3.4 DDR2/3 Memory Controller Electrical Data/Timing

Section 8.3.1, DDR2 Routing Guidelines and Section 8.3.2, DDR3 Routing Guidelines specify a complete

DDR2/3 interface solution for the device. TI has performed the simulation and system characterization to

ensure all DDR2/3 interface timings in this solution are met.

TI only supports board designs that follow the guidelines outlined in the DDR2 Routing Guidelines and

DDR3 Routing Guidelines sections of this data sheet.

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8.4 Emulation Features and Capability

8.4.1 Advanced Event Triggering (AET)

The device supports Advanced Event Triggering (AET). This capability can be used to debug complex

problems as well as understand performance characteristics of user applications. AET provides the

following capabilities:

•

Hardware Program Breakpoints: specify addresses or address ranges that can generate events such

as halting the processor or triggering the trace capture.

•

Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate

events such as halting the processor or triggering the trace capture.

•

Counters: count the occurrence of an event or cycles for performance monitoring.

State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to

precisely generate events for complex sequences.

For more information on AET, see the following documents:

•

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report

(literature number SPRA753)

•

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded

Microprocessor Systems application report (literature number SPRA387)

8.4.2 Trace

The device supports Trace at the Cortex™-A8 and System levels. Trace is a debug technology that

provides a detailed, historical account of application code execution, timing, and data accesses. Trace

collects, compresses, and exports debug information for analysis. The debug information can be exported

to the Embedded Trace Buffer (ETB), or to the 5-pin Trace Interface (system trace only). Trace works in

real-time and does not impact the execution of the system.

For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and

Trace Headers Technical Reference Manual (literature number SPRU655).

8.4.3 IEEE 1149.1 JTAG

The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)

interface is used for BSDL testing and emulation of the device. The TRST pin only needs to be released

when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan

functionality. For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to

ensure that TRST is always asserted upon power up and the device's internal emulation logic is always

properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some

third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary-scan operations.

The main JTAG features include:

•

32KB embedded trace buffer (ETB)

5-pin system trace interface for debug

Supports Advanced Event Triggering (AET)

All processors can be emulated via JTAG ports

All functions on EMU pins of the device:

–

EMU[1:0] - cross-triggering, boot mode (WIR), STM trace

EMU[4:2] - STM trace only (single direction)

184

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8.4.3.1 JTAG ID (JTAGID) Register Description

Table 8-27. JTAG ID Register⁽¹⁾

HEX ADDRESS

ACRONYM

REGISTER NAME

JTAG Identification Register⁽²⁾

0x4814 0600

JTAGID

(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

(2) Read-only. Provides the device 32-bit JTAG ID.

The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this

device, the JTAG ID register resides at address location 0x4814 0600. The register hex value for the

device is: 0x0B81 E02F. For the actual register bit names and their associated bit field descriptions, see

Figure 8-40 and Table 8-28.

31

28 27

12 11

1

0

VARIANT

(4-bit)

PART NUMBER (16-bit)

R-1011 1000 0001 1110

MANUFACTURER (11-bit)

R-0000 0010 111

LSB

R-1

R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 8-40. JTAG ID Register Description - Device Register Value: 0x0B81 E02F

Table 8-28. JTAG ID Register Selection Bit Descriptions

Bit

31:28

27:12

11:1

0

Field

Description

VARIANT

Variant (4-bit) value. Device value: 0x0

PART NUMBER

Part Number (16-bit) value. Device value: 0xB81E

MANUFACTURER Manufacturer (11-bit) value. Device value: 0x017

LSB LSB. This bit is read as a 1 for this device.

8.4.3.2 JTAG Electrical Data/Timing

Table 8-29. Timing Requirements for IEEE 1149.1 JTAG

(see Figure 8-41)

NO.

MIN

51.15

20.46

5.115

10

MAX UNIT

1

t_c(TCK)

1a t_w(TCKH)

1b t_w(TCKL)

Cycle time, TCK

ns

Pulse duration, TCK high (40% of t_c)

Pulse duration, TCK low (40% of t_c)

3

t_su(TDI-TCK)

Input setup time, TDI valid to TCK high (20% of (t_c* 0.5))

Input setup time, TMS valid to TCK high (20% of (t_c* 0.5))

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

4

10

Table 8-30. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

(see Figure 8-41)

NO.

PARAMETER

MIN

MAX UNIT

23.575⁽¹⁾

ns

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

(1) (0.5 * t_c) - 2

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1

1a

1b

TCK

2

TDO

3

4

TDI/TMS

Figure 8-41. JTAG Timing

Table 8-31. Timing Requirements for IEEE 1149.1 JTAG With RTCK

(see Figure 8-41)

NO.

MIN

51.15

MAX UNIT

1

t_c(TCK)

1a t_w(TCKH)

1b t_w(TCKL)

Cycle time, TCK

ns

Pulse duration, TCK high (40% of t_c)

20.46

5.115

10

Pulse duration, TCK low (40% of t_c)

3

t_su(TDI-TCK)

Input setup time, TDI valid to TCK high (20% of (t_c* 0.5))

Input setup time, TMS valid to TCK high (20% of (t_c* 0.5))

Input hold time, TDI valid from TCK high

Input hold time, TMS valid from TCK high

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

4

10

Table 8-32. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

With RTCK

(see Figure 8-42)

NO.

PARAMETER

MIN

MAX UNIT

Delay time, TCK to RTCK with no selected subpaths (i.e., ICEPick

module is the only tap selected - when the ARM is in the scan

chain, the delay time is a function of the ARM functional clock.)

5

t_d(TCK-RTCK)

0

21

ns

6

7

8

t_c(RTCK)

Cycle time, RTCK

51.15

20.46

ns

t_w(RTCKH)

t_w(RTCKL)

Pulse duration, RTCK high (40% of t_c)

Pulse duration, RTCK low (40% of t_c)

5

TCK

6

7

8

RTCK

Figure 8-42. JTAG With RTCK Timing

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Table 8-33. Switching Characteristics Over Recommended Operating Conditions for STM Trace

(see Figure 8-43)

NO.

PARAMETER

MIN

5-1⁽¹⁾

3.5

MAX UNIT

Pulse duration, EMUx high detected at 50% V_OHwith 60/40 duty

cycle

t_w(EMUxH50)

t_w(EMUxH90)

t_w(EMUxL50)

t_w(EMUxL10)

t_sko(EMUx)

ns

1

Pulse duration, EMUx high detected at 90% V_OH

Pulse duration, EMUx low detected at 50% V_OHwith 60/40 duty

cycle

5-1⁽¹⁾

3.5

2

3

Pulse duration, EMUx low detected at 10% V_OH

Output skew time, time delay difference between EMUx pins

configured as trace.

-500

500

1⁽¹⁾

ps

Pulse skew, magnitude of difference between high-to-low (t_phl) and

low-to-high (t_plh) propagation delays

t_skp(EMUx)

ps

t_{sldp_o(EMUx)}

Output slew rate EMUx

3.3

V/ns

(1) This parameter applies to the maximum trace export frequency operating in a 40/60 duty cycle.

A

Buffer

Inputs

Buffers

EMUx Pins

t_PHL

t_PLH

1

2

B

C

B

C

A

3

Figure 8-43. STM Trace Timing

8.4.4 IEEE 1149.7 cJTAG

Besides the standard (legacy) JTAG mode of operation, the target debug interface can also be switched to

a compressed JTAG (cJTAG) mode of operation, commonly referred to as IEEE1149.7 standard. An

IEEE1149.7 adapter module runs a 2-pin communication protocol on top of an IEEE1149.1 JTAG TAP.

The debug-IP logic serializes the IEEE1149.1 transactions, using a variety of compression formats, to

reduce the number of pins needed to implement a JTAG debug port. This device implements only a

subset of the IEEE1149.7 protocol; it supports Class 0/1 operation. On this device the cJTAG ID[7:0] is

tied to 0x00.

NOTE

The default setting of the scan port is IEEE 1149.1. A cJTAG emulator connected only to

TCLK and TMS can re-configure the port to cJTAG by scanning in a special command

sequence. For the scan sequence required to switch modes, see the IEEE1149.7

specification.

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8.5 Enhanced Direct Memory Access (EDMA) Controller

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the device. These data transfers include cache servicing, non-cacheable memory accesses,

user-programmed data transfers, and host accesses.

8.5.1 EDMA Channel Synchronization Events

The EDMA channel controller supports up to 64 channels that service peripherals and memory. Each

EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-34. By default,

each event uses the parameter entry that matches its event number. However, because the device

includes a channel mapping feature, each event may be mapped to any of 512 parameter table entries.

For more detailed information on the EDMA module and how EDMA events are enabled, captured,

processed, linked, chained, and cleared, etc., see the EDMA chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

Table 8-34. EDMA Default Synchronization Events

EVENT NUMBER

DEFAULT EVENT NAME

-

DEFAULT EVENT DESCRIPTION

Unused

0 - 7

8

AXEVT0

AREVT0

AXEVT1

AREVT1

AXEVT2

AREVT2

BXEVT

McASP0 Transmit

McASP0 Receive

McASP1 Transmit

McASP1 Receive

McASP2 Transmit

McASP2 Receive

McBSP Transmit

McBSP Receive

SPI0 Transmit 0

SPI0 Receive 0

SPI0 Transmit 1

SPI0 Receive 1

SPI0 Transmit 2

SPI0 Receive 2

SPI0 Transmit 3

SPI0 Receive 3

SD0 Transmit

SD0 Receive

9

10

11

12

13

14

15

BREVT

16

SPIXEVT0

SPIREVT0

SPIXEVT1

SPIREVT1

SPIXEVT2

SPIREVT2

SPIXEVT3

SPIREVT3

SDTXEVT

SDRXEVT

UTXEVT0

URXEVT0

UTXEVT1

URXEVT1

UTXEVT2

URXEVT2

-

17

18

19

20

21

22

23

24

25

26

UART0 Transmit

UART0 Receive

UART1 Transmit

UART1 Receive

UART2 Transmit

UART2 Receive

Unused

27

28

29

30

31

32 - 47

48

TINT4

TIMER4

49

TINT5

TIMER5

50

TINT6

TIMER6

51

TINT7

TIMER7

52

GPMCEVT

HDMIEVT

-

GPMC

53

HDMI

54 - 57

58

Unused

I2CTXEVT0

I2C0 Transmit

188

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Table 8-34. EDMA Default Synchronization Events (continued)

EVENT NUMBER

DEFAULT EVENT NAME

I2CRXEVT0

I2CTXEVT1

I2CRXEVT1

-

DEFAULT EVENT DESCRIPTION

59

60

I2C0 Receive

I2C1 Transmit

I2C1 Receive

Unused

61

62 - 63

8.5.2 EDMA Peripheral Register Descriptions

Table 8-35. EDMA Channel Controller (EDMA TPCC) Control Registers

HEX ADDRESS

0x4900 0000

0x4900 0004

0x4900 0100 - 0x4900 01FC

0x4900 0200

0x4900 0204

0x4900 0208

0x4900 020C

0x4900 0210

0x4900 0214

0x4900 0218

0x4900 021C

0x4900 0240

0x4900 0244

0x4900 0248

0x4900 024C

0x4900 0250

0x4900 0254

0x4900 0258

0x4900 025C

0x4900 0260

0x4900 0284

0x4900 0300

0x4900 0304

0x4900 0308

0x4900 030C

0x4900 0310

0x4900 0314

0x4900 0318

0x4900 031C

0x4900 0320

0x4900 0340

0x4900 0344

0x4900 0348

0x4900 034C

0x4900 0350

0x4900 0354

0x4900 0358

0x4900 035C

ACRONYM

PID

REGISTER NAME

Peripheral Identification

CCCFG

EDMA3CC Configuration

DMA Channel 0-63 Mappings

QDMA Channel 0 Mapping

QDMA Channel 1 Mapping

QDMA Channel 2 Mapping

QDMA Channel 3 Mapping

QDMA Channel 4 Mapping

QDMA Channel 5 Mapping

QDMA Channel 6 Mapping

QDMA Channel 7 Mapping

DMA Queue Number 0

DCHMAP0-63

QCHMAP0

QCHMAP1

QCHMAP2

QCHMAP3

QCHMAP4

QCHMAP5

QCHMAP6

QCHMAP7

DMAQNUM0

DMAQNUM1

DMAQNUM2

DMAQNUM3

DMAQNUM4

DMAQNUM5

DMAQNUM6

DMAQNUM7

QDMAQNUM

QUEPRI

DMA Queue Number 1

DMA Queue Number 2

DMA Queue Number 3

DMA Queue Number 4

DMA Queue Number 5

DMA Queue Number 6

DMA Queue Number 7

QDMA Queue Number

Queue Priority

EMR

Event Missed

EMRH

Event Missed High

EMCR

Event Missed Clear

EMCRH

Event Missed Clear High

QDMA Event Missed

QEMR

QEMCR

QDMA Event Missed Clear

EDMA3CC Error

CCERR

CCERRCLR

EEVAL

EDMA3CC Error Clear

Error Evaluate

DRAE0

DMA Region Access Enable for Region 0

DMA Region Access Enable High for Region 0

DMA Region Access Enable for Region 1

DMA Region Access Enable High for Region 1

DMA Region Access Enable for Region 2

DMA Region Access Enable High for Region 2

DMA Region Access Enable for Region 3

DMA Region Access Enable High for Region 3

DRAEH0

DRAE1

DRAEH1

DRAE2

DRAEH2

DRAE3

DRAEH3

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Table 8-35. EDMA Channel Controller (EDMA TPCC) Control Registers (continued)

HEX ADDRESS

0x4900 0360

ACRONYM

DRAE4

DRAEH4

DRAE5

DRAEH5

DRAE6

DRAEH6

DRAE7

DRAEH7

QRAE0-7

Q0E0-Q3E15

QSTAT0-3

QWMTHRA

CCSTAT

MPFAR

MPFSR

MPFCR

MPPAG

MPPA0-7

ER

REGISTER NAME

DMA Region Access Enable for Region 4

DMA Region Access Enable High for Region 4

DMA Region Access Enable for Region 5

DMA Region Access Enable High for Region 5

DMA Region Access Enable for Region 6

DMA Region Access Enable High for Region 6

DMA Region Access Enable for Region 7

DMA Region Access Enable High for Region 7

QDMA Region Access Enable for Region 0-7

Event Queue Entry Q0E0-Q3E15

Queue Status 0-3

0x4900 0364

0x4900 0368

0x4900 036C

0x4900 0370

0x4900 0374

0x4900 0378

0x4900 037C

0x4900 0380 - 0x4900 039C

0x4900 0400 - 0x4900 04FC

0x4900 0600 - 0x4900 060C

0x4900 0620

Queue Watermark Threshold A

EDMA3CC Status

0x4900 0640

0x4900 0800

Memory Protection Fault Address

Memory Protection Fault Status

Memory Protection Fault Command

Memory Protection Page Attribute Global

Memory Protection Page Attribute 0-7

Event

0x4900 0804

0x4900 0808

0x4900 080C

0x4900 0810 - 0x4900 082C

0x4900 1000

0x4900 1004

ERH

Event High

0x4900 1008

ECR

Event Clear

0x4900 100C

0x4900 1010

ECRH

Event Clear High

ESR

Event Set

0x4900 1014

ESRH

Event Set High

0x4900 1018

CER

Chained Event

0x4900 101C

0x4900 1020

CERH

Chained Event High

EER

Event Enable

0x4900 1024

EERH

Event Enable High

0x4900 1028

EECR

Event Enable Clear

0x4900 102C

0x4900 1030

EECRH

EESR

Event Enable Clear High

Event Enable Set

0x4900 1034

EESRH

SER

Event Enable Set High

0x4900 1038

Secondary Event

0x4900 103C

0x4900 1040

SERH

Secondary Event High

SECR

Secondary Event Clear

0x4900 1044

SECRH

IER

Secondary Event Clear High

Interrupt Enable

0x4900 1050

0x4900 1054

IERH

Interrupt Enable High

0x4900 1058

IECR

Interrupt Enable Clear

0x4900 105C

0x4900 1060

IECRH

IESR

Interrupt Enable Clear High

Interrupt Enable Set

0x4900 1064

IESRH

IPR

Interrupt Enable Set High

Interrupt Pending

0x4900 1068

0x4900 106C

0x4900 1070

IPRH

Interrupt Pending High

ICR

Interrupt Clear

0x4900 1074

ICRH

Interrupt Clear High

0x4900 1078

IEVAL

Interrupt Evaluate

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Table 8-35. EDMA Channel Controller (EDMA TPCC) Control Registers (continued)

HEX ADDRESS

0x4900 1080

0x4900 1084

0x4900 1088

0x4900 108C

0x4900 1090

0x4900 1094

ACRONYM

QER

REGISTER NAME

QDMA Event

QEER

QDMA Event Enable

QEECR

QEESR

QSER

QDMA Event Enable Clear

QDMA Event Enable Set

QDMA Secondary Event

QDMA Secondary Event Clear

QSECR

Shadow Region 0 Channel Registers

0x4900 2000

0x4900 2004

0x4900 2008

0x4900 200C

0x4900 2010

0x4900 2014

0x4900 2018

0x4900 201C

0x4900 2020

0x4900 2024

0x4900 2028

0x4900 202C

0x4900 2030

0x4900 2034

0x4900 2038

0x4900 203C

0x4900 2040

0x4900 2044

0x4900 2050

0x4900 2054

0x4900 2058

0x4900 205C

0x4900 2060

0x4900 2064

0x4900 2068

0x4900 206C

0x4900 2070

0x4900 2074

0x4900 2078

0x4900 2080

0x4900 2084

0x4900 2088

0x4900 208C

0x4900 2090

0x4900 2094

ER

ERH

Event

Event High

ECR

Event Clear

ECRH

ESR

Event Clear High

Event Set

ESRH

CER

Event Set High

Chained Event

CERH

EER

Chained Event High

Event Enable

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable High

Event Enable Clear

Event Enable Clear High

Event Enable Set

Event Enable Set High

Secondary Event

SERH

SECR

SECRH

IER

Secondary Event High

Secondary Event Clear

Secondary Event Clear High

Interrupt Enable

IERH

IECR

IECRH

IESR

IESRH

IPR

Interrupt Enable High

Interrupt Enable Clear

Interrupt Enable Clear High

Interrupt Enable Set

Interrupt Enable Set High

Interrupt Pending

IPRH

ICR

Interrupt Pending High

Interrupt Clear

ICRH

IEVAL

QER

Interrupt Clear High

Interrupt Evaluate

QDMA Event

QEER

QEECR

QEESR

QSER

QSECR

-

QDMA Event Enable

QDMA Event Enable Clear

QDMA Event Enable Set

QDMA Secondary Event

QDMA Secondary Event Clear

Shadow Region 1 Channels

Shadow Region 2 Channels

...

0x4900 2200 - 0x4900 2294

0x4900 2400 - 0x4900 2494

...

-

0x4900 2E00 - 0x4900 2E94

-

Shadow Channels for MP Space 7

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Table 8-36. EDMA Transfer Controller (EDMA TPTC) Control Registers

TPTC0 HEX

ADDRESS

TPTC1 HEX

ADDRESS

TPTC2 HEX

ADDRESS

TPTC3 HEX

ADDRESS

ACRONYM

REGISTER NAME

0x4980 0000

0x4980 0004

0x4980 0100

0x4980 0120

0x4980 0124

0x4980 0128

0x4980 012C

0x4980 0130

0x4980 0140

0x4980 0240

0x4980 0244

0x4980 0248

0x4980 024C

0x4990 0000

0x4990 0004

0x4990 0100

0x4990 0120

0x4990 0124

0x4990 0128

0x4990 012C

0x4990 0130

0x4990 0140

0x4990 0240

0x4990 0244

0x4990 0248

0x4990 024C

0x49A0 0000

0x49A0 0004

0x49A0 0100

0x49A0 0120

0x49A0 0124

0x49A0 0128

0x49A0 012C

0x49A0 0130

0x49A0 0140

0x49A0 0240

0x49A0 0244

0x49A0 0248

0x49A0 024C

0x49B0 0000

0x49B0 0004

0x49B0 0100

0x49B0 0120

0x49B0 0124

0x49B0 0128

0x49B0 012C

0x49B0 0130

0x49B0 0140

0x49B0 0240

0x49B0 0244

0x49B0 0248

0x49B0 024C

PID

Peripheral Identification

EDMA3TC Configuration

EDMA3TC Channel Status

Error Status

TCCFG

TCSTAT

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

RDRATE

SAOPT

Error Enable

Error Clear

Error Details

Error Interrupt Command

Read Rate Register

Source Active Options

Source Active Source Address

Source Active Count

SASRC

SACNT

SADST

Source Active Destination

Address

0x4980 0250

0x4980 0254

0x4990 0250

0x4990 0254

0x49A0 0250

0x49A0 0254

0x49B0 0250

0x49B0 0254

SABIDX

Source Active Source B-Index

SAMPPRXY

Source Active Memory

Protection Proxy

0x4980 0258

0x4980 025C

0x4990 0258

0x4990 025C

0x49A0 0258

0x49A0 025C

0x49B0 0258

0x49B0 025C

SACNTRLD

Source Active Count Reload

SASRCBREF

Source Active Source Address

B-Reference

0x4980 0260

0x4980 0280

0x4980 0284

0x4990 0260

0x4990 0280

0x4990 0284

0x49A0 0260

0x49A0 0280

0x49A0 0284

0x49B0 0260

0x49B0 0280

0x49B0 0284

SADSTBREF

DFCNTRLD

DFSRCBREF

Source Active Destination

Address B-Reference

Destination FIFO Set Count

Reload

Destination FIFO Set

Destination Address B

Reference

0x4980 0288

0x4990 0288

0x49A0 0288

0x49B0 0288

DFDSTBREF

Destination FIFO Set

Destination Address B

Reference

0x4980 0300

0x4980 0304

0x4990 0300

0x4990 0304

0x49A0 0300

0x49A0 0304

0x49B0 0300

0x49B0 0304

DFOPT0

DFSRC0

Destination FIFO Options 0

Destination FIFO Source

Address 0

0x4980 0308

0x4980 030C

0x4990 0308

0x4990 030C

0x49A0 0308

0x49A0 030C

0x49B0 0308

0x49B0 030C

DFCNT0

DFDST0

Destination FIFO Count 0

Destination FIFO Destination

Address 0

0x4980 0310

0x4980 0314

0x4990 0310

0x4990 0314

0x49A0 0310

0x49A0 0314

0x49B0 0310

0x49B0 0314

DFBIDX0

Destination FIFO BIDX 0

DFMPPRXY0

Destination FIFO Memory

Protection Proxy 0

0x4980 0340

0x4980 0344

0x4990 0340

0x4990 0344

0x49A0 0340

0x49A0 0344

0x49B0 0340

0x49B0 0344

DFOPT1

DFSRC1

Destination FIFO Options 1

Destination FIFO Source

Address 1

0x4980 0348

0x4980 034C

0x4990 0348

0x4990 034C

0x49A0 0348

0x49A0 034C

0x49B0 0348

0x49B0 034C

DFCNT1

DFDST1

Destination FIFO Count 1

Destination FIFO Destination

Address 1

0x4980 0350

0x4980 0354

0x4990 0350

0x4990 0354

0x49A0 0350

0x49A0 0354

0x49B0 0350

0x49B0 0354

DFBIDX1

Destination FIFO BIDX 1

DFMPPRXY1

Destination FIFO Memory

Protection Proxy 1

0x4980 0380

0x4980 0384

0x4990 0380

0x4990 0384

0x49A0 0380

0x49A0 0384

0x49B0 0380

0x49B0 0384

DFOPT2

DFSRC2

Destination FIFO Options 2

Destination FIFO Source

Address 2

0x4980 0388

0x4990 0388

0x49A0 0388

0x49B0 0388

DFCNT2

Destination FIFO Count 2

192

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Table 8-36. EDMA Transfer Controller (EDMA TPTC) Control Registers (continued)

TPTC0 HEX

ADDRESS

TPTC1 HEX

ADDRESS

TPTC2 HEX

ADDRESS

TPTC3 HEX

ADDRESS

ACRONYM

REGISTER NAME

0x4980 038C

0x4990 038C

0x49A0 038C

0x49B0 038C

DFDST2

Destination FIFO Destination

Address 2

0x4980 0390

0x4980 0394

0x4990 0390

0x4990 0394

0x49A0 0390

0x49A0 0394

0x49B0 0390

0x49B0 0394

DFBIDX2

Destination FIFO BIDX 2

DFMPPRXY2

Destination FIFO Memory

Protection Proxy 2

0x4980 03C0

0x4980 03C4

0x4990 03C0

0x4990 03C4

0x49A0 03C0

0x49A0 03C4

0x49B0 03C0

0x49B0 03C4

DFOPT3

DFSRC3

Destination FIFO Options 3

Destination FIFO Source

Address 3

0x4980 03C8

0x4980 03CC

0x4990 03C8

0x4990 03CC

0x49A0 03C8

0x49A0 03CC

0x49B0 03C8

0x49B0 03CC

DFCNT3

DFDST3

Destination FIFO Count 3

Destination FIFO Destination

Address 3

0x4980 03D0

0x4980 03D4

0x4990 03D0

0x4990 03D4

0x49A0 03D0

0x49A0 03D4

0x49B0 03D0

0x49B0 03D4

DFBIDX3

Destination FIFO BIDX 3

DFMPPRXY3

Destination FIFO Memory

Protection Proxy 3

Peripheral Information and Timings

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8.6 Ethernet Media Access Controller (EMAC)

The device includes two Ethernet Media Access Controller (EMAC) modules which provide an efficient

interface between the device and the networked community. The EMAC supports 10Base-T (10

Mbits/second [Mbps]) and 100Base-TX (100 Mbps) in either half- or full-duplex mode, and 1000Base-T

(1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The

EMAC controls the flow of packet data from the device to an external PHY. A single MDIO interface is

pinned out to control the PHY configuration and status monitoring. Multiple external PHYs can be

controlled by the MDIO interface.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple

Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE

802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviating from this standard, the EMAC module does not use the transmit coding error signal, MTXER.

Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC

intentionally generates an incorrect checksum by inverting the frame CRC so that the transmitted frame is

detected as an error by the network. In addition, the EMAC I/Os operate at 3.3 V and are not compatible

with 2.5-V I/O signaling; therefore, only Ethernet PHYs with 3.3-V I/O interface should be used. The

EMAC module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors and contains the

necessary components to enable the EMAC to make efficient use of device memory and control device

interrupts.

The EMAC module on the device supports two interface modes: Media Independent Interface (MII) and

Gigabit Media Independent Interface (GMII). The MII and GMII interface modes are defined in the IEEE

802.3-2002 standard. The EMAC uses the same pins for the MII and GMII modes of operation. Only one

mode can be used at a time.

The MII and GMII modes-of-operation pins are as follows:

•

MII: EMAC[1:0]_TXCLK, EMAC[1:0]_RXCLK, EMAC[1:0]_TXD[3:0], EMAC[1:0]_RXD[3:0],

EMAC[1:0]_TXEN, EMAC[1:0]_RXDV, EMAC[1:0]_RXER, EMAC[1:0]_COL, EMAC[1:0]_CRS,

MDIO_MCLK, and MDIO_MDIO.

•

GMII: EMAC[1:0]_GMTCLK, EMAC[1:0]_TXCLK, EMAC[1:0]_RXCLK, EMAC[1:0]_TXD[7:0],

EMAC[1:0]_RXD[7:0], EMAC[1:0]_TXEN, EMAC[1:0]_RXDV, EMAC[1:0]_RXER, EMAC[1:0]_COL,

EMAC[1:0]_CRS, MDIO_MCLK, and MDIO_MDIO.

For more detailed information on the EMAC module, see the EMAC/MDIO chapter in the AM38x Sitara

ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.6.1 EMAC Peripheral Register Descriptions

Table 8-37. EMAC Control Registers

EMAC0 HEX ADDRESS

0x4A10 0000

0x4A10 0004

0x4A10 0008

0x4A10 0010

0x4A10 0014

0x4A10 0018

0x4A10 0080

0x4A10 0084

0x4A10 0088

0x4A10 008C

0x4A10 0090

0x4A10 0094

0x4A10 00A0

EMAC1 HEX ADDRESS

0x4A12 0000

0x4A12 0004

0x4A12 0008

0x4A12 0010

0x4A12 0014

0x4A12 0018

0x4A12 0080

0x4A12 0084

0x4A12 0088

0x4A12 008C

0x4A12 0090

0x4A12 0094

0x4A12 00A0

ACRONYM

TXIDVER

REGISTER NAME

Transmit Identification and Version

Transmit Control

TXCONTROL

TXTEARDOWN

RXIDVER

Transmit Teardown

Receive Identification and Version

Receive Control

RXCONTROL

RXTEARDOWN

TXINTSTATRAW

TXINTSTATMASKED

TXINTMASKSET

TXINTMASKCLEAR

MACINVECTOR

MACEOIVECTOR

RXINTSTATRAW

Receive Teardown

Transmit Interrupt Status (Unmasked)

Transmit Interrupt Status (Masked)

Transmit Interrupt Mask Set

Transmit Interrupt Clear

MAC Input Vector

MAC End of Interrupt Vector

Receive Interrupt Status (Unmasked)

194

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Table 8-37. EMAC Control Registers (continued)

EMAC0 HEX ADDRESS

EMAC1 HEX ADDRESS

0x4A12 00A4

0x4A12 00A8

0x4A12 00AC

0x4A12 00B0

0x4A12 00B4

0x4A12 00B8

0x4A12 00BC

0x4A12 0100

ACRONYM

REGISTER NAME

0x4A10 00A4

0x4A10 00A8

0x4A10 00AC

0x4A10 00B0

0x4A10 00B4

0x4A10 00B8

0x4A10 00BC

0x4A10 0100

RXINTSTATMASKED

RXINTMASKSET

Receive Interrupt Status (Masked)

Receive Interrupt Mask Set

Receive Interrupt Mask Clear

MAC Interrupt Status (Unmasked)

MAC Interrupt Status (Masked)

MAC Interrupt Mask Set

RXINTMASKCLEAR

MACINTSTATRAW

MACINTSTATMASKED

MACINTMASKSET

MACINTMASKCLEAR

RXMBPENABLE

MAC Interrupt Mask Clear

Receive

Multicast/Broadcast/Promiscuous

Channel Enable

0x4A10 0104

0x4A10 0108

0x4A10 010C

0x4A10 0110

0x4A10 0114

0x4A12 0104

0x4A12 0108

0x4A12 010C

0x4A12 0110

0x4A12 0114

RXUNICASTSET

RXUNICASTCLEAR

RXMAXLEN

Receive Unicast Enable Set

Receive Unicast Clear

Receive Maximum Length

Receive Buffer Offset

RXBUFFEROFFSET

RXFILTERLOWTHRESH Receive Filter Low Priority Frame

Threshold

0x4A10 0120

0x4A10 0124

0x4A10 0128

0x4A10 012C

0x4A10 0130

0x4A10 0134

0x4A10 0138

0x4A10 013C

0x4A12 0120

0x4A12 0124

0x4A12 0128

0x4A12 012C

0x4A12 0130

0x4A12 0134

0x4A12 0138

0x4A12 013C

RX0FLOWTHRESH

RX1FLOWTHRESH

RX2FLOWTHRESH

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

RX7FLOWTHRESH

Receive Channel 0 Flow Control

Threshold

Receive Channel 1 Flow Control

Threshold

Receive Channel 2 Flow Control

Threshold

Receive Channel 3 Flow Control

Threshold

Receive Channel 4 Flow Control

Threshold

Receive Channel 5 Flow Control

Threshold

Receive Channel 6 Flow Control

Threshold

Receive Channel 7 Flow Control

Threshold

0x4A10 0140

0x4A10 0144

0x4A10 0148

0x4A10 014C

0x4A10 0150

0x4A10 0154

0x4A10 0158

0x4A10 015C

0x4A10 0160

0x4A10 0164

0x4A10 0168

0x4A10 016C

0x4A10 0170

0x4A10 0174

0x4A10 01D0

0x4A10 01D4

0x4A10 01D8

0x4A10 01DC

0x4A10 01E0

0x4A12 0140

0x4A12 0144

0x4A12 0148

0x4A12 014C

0x4A12 0150

0x4A12 0154

0x4A12 0158

0x4A12 015C

0x4A12 0160

0x4A12 0164

0x4A12 0168

0x4A12 016C

0x4A12 0170

0x4A12 0174

0x4A12 01D0

0x4A12 01D4

0x4A12 01D8

0x4A12 01DC

0x4A12 01E0

RX0FREEBUFFER

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

Receive Channel 0 Free Buffer Count

Receive Channel 1 Free Buffer Count

Receive Channel 2 Free Buffer Count

Receive Channel 3 Free Buffer Count

Receive Channel 4 Free Buffer Count

Receive Channel 5 Free Buffer Count

Receive Channel 6 Free Buffer Count

Receive Channel 7 Free Buffer Count

MAC Control

MAC Status

EMCONTROL

Emulation Control

FIFOCONTROL

MACCONFIG

FIFO Control

MAC Configuration

SOFTRESET

Soft Reset

MACSRCADDRLO

MACSRCADDRHI

MACHASH1

MAC Source Address Low Bytes

MAC Source Address High Bytes

MAC Hash Address 1

MACHASH2

MAC Hash Address 2

BOFFTEST

Back Off Test

Peripheral Information and Timings

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Table 8-37. EMAC Control Registers (continued)

EMAC0 HEX ADDRESS

0x4A10 01E4

EMAC1 HEX ADDRESS

0x4A12 01E4

ACRONYM

TPACETEST

RXPAUSE

REGISTER NAME

Transmit Pacing Algorithm Test

Receive Pause Timer

0x4A10 01E8

0x4A12 01E8

0x4A10 01EC

0x4A12 01EC

TXPAUSE

Transmit Pause Timer

0x4A10 0200 - 0x4A10 02FC

0x4A10 0500

0x4A12 0200 - 0x4A12 02FC

0x4A12 0500

(see Table 8-38)

MACADDRLO

EMAC Network Statistics Registers

MAC Address Low Bytes, Used in

Receive Address Matching

0x4A10 0504

0x4A12 0504

MACADDRHI

MAC Address High Bytes, Used in

Receive Address Matching

0x4A10 0508

0x4A10 0600

0x4A12 0508

0x4A12 0600

MACINDEX

TX0HDP

MAC Index

Transmit Channel 0 DMA Head

Descriptor Pointer

0x4A10 0604

0x4A10 0608

0x4A10 060C

0x4A10 0610

0x4A10 0614

0x4A10 0618

0x4A10 061C

0x4A10 0620

0x4A10 0624

0x4A10 0628

0x4A10 062C

0x4A10 0630

0x4A10 0634

0x4A10 0638

0x4A10 063C

0x4A10 0640

0x4A10 0644

0x4A10 0648

0x4A10 064C

0x4A10 0650

0x4A10 0654

0x4A10 0658

0x4A12 0604

0x4A12 0608

0x4A12 060C

0x4A12 0610

0x4A12 0614

0x4A12 0618

0x4A12 061C

0x4A12 0620

0x4A12 0624

0x4A12 0628

0x4A12 062C

0x4A12 0630

0x4A12 0634

0x4A12 0638

0x4A12 063C

0x4A12 0640

0x4A12 0644

0x4A12 0648

0x4A12 064C

0x4A12 0650

0x4A12 0654

0x4A12 0658

TX1HDP

TX2HDP

TX3HDP

TX4HDP

TX5HDP

TX6HDP

TX7HDP

RX0HDP

RX1HDP

RX2HDP

RX3HDP

RX4HDP

RX5HDP

RX6HDP

RX7HDP

TX0CP

Transmit Channel 1 DMA Head

Descriptor Pointer

Transmit Channel 2 DMA Head

Descriptor Pointer

Transmit Channel 3 DMA Head

Descriptor Pointer

Transmit Channel 4 DMA Head

Descriptor Pointer

Transmit Channel 5 DMA Head

Descriptor Pointer

Transmit Channel 6 DMA Head

Descriptor Pointer

Transmit Channel 7 DMA Head

Descriptor Pointer

Receive Channel 0 DMA Head

Descriptor Pointer

Receive Channel 1 DMA Head

Descriptor Pointer

Receive Channel 2 DMA Head

Descriptor Pointer

Receive Channel 3 DMA Head

Descriptor Pointer

Receive Channel 4 DMA Head

Descriptor Pointer

Receive Channel 5 DMA Head

Descriptor Pointer

Receive Channel 6 DMA Head

Descriptor Pointer

Receive Channel 7 DMA Head

Descriptor Pointer

Transmit Channel 0 Completion

Pointer

TX1CP

Transmit Channel 1 Completion

Pointer

TX2CP

Transmit Channel 2 Completion

Pointer

TX3CP

Transmit Channel 3 Completion

Pointer

TX4CP

Transmit Channel 4 Completion

Pointer

TX5CP

Transmit Channel 5 Completion

Pointer

TX6CP

Transmit Channel 6 Completion

Pointer

196

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Table 8-37. EMAC Control Registers (continued)

EMAC0 HEX ADDRESS

EMAC1 HEX ADDRESS

ACRONYM

REGISTER NAME

0x4A10 065C

0x4A12 065C

TX7CP

Transmit Channel 7 Completion

Pointer

0x4A10 0660

0x4A10 0664

0x4A10 0668

0x4A10 066C

0x4A10 0670

0x4A10 0674

0x4A10 0678

0x4A10 067C

0x4A12 0660

0x4A12 0664

0x4A12 0668

0x4A12 066C

0x4A12 0670

0x4A12 0674

0x4A12 0678

0x4A12 067C

RX0CP

RX1CP

RX2CP

RX3CP

RX4CP

RX5CP

RX6CP

RX7CP

Receive Channel 0 Completion Pointer

Receive Channel 1 Completion Pointer

Receive Channel 2 Completion Pointer

Receive Channel 3 Completion Pointer

Receive Channel 4 Completion Pointer

Receive Channel 5 Completion Pointer

Receive Channel 6 Completion Pointer

Receive Channel 7 Completion Pointer

Table 8-38. EMAC Network Statistics Registers

EMAC0 HEX ADDRESS

0x4A10 0200

0x4A10 0204

0x4A10 0208

0x4A10 020C

0x4A10 0210

0x4A10 0214

0x4A10 0218

0x4A10 021C

0x4A10 0220

0x4A10 0224

0x4A10 0228

0x4A10 022C

0x4A10 0230

0x4A10 0234

0x4A10 0238

0x4A10 023C

0x4A10 0240

0x4A10 0244

0x4A10 0248

0x4A10 024C

0x4A10 0250

0x4A10 0254

0x4A10 0258

0x4A10 025C

0x4A10 0260

0x4A10 0264

0x4A10 0268

0x4A10 026C

0x4A10 0270

0x4A10 0274

0x4A10 0278

0x4A10 027C

EMAC1 HEX ADDRESS

0x4A12 0200

0x4A12 0204

0x4A12 0208

0x4A12 020C

0x4A12 0210

0x4A12 0214

0x4A12 0218

0x4A12 021C

0x4A12 0220

0x4A12 0224

0x4A12 0228

0x4A12 022C

0x4A12 0230

0x4A12 0234

0x4A12 0238

0x4A12 023C

0x4A12 0240

0x4A12 0244

0x4A12 0248

0x4A12 024C

0x4A12 0250

0x4A12 0254

0x4A12 0258

0x4A12 025C

0x4A12 0260

0x4A12 0264

0x4A12 0268

0x4A12 026C

0x4A12 0270

0x4A12 0274

0x4A12 0278

0x4A12 027C

ACRONYM

REGISTER NAME

RXGOODFRAMES

RXBCASTFRAMES

RXMCASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

Good Receive Frames

Broadcast Receive Frames

Multicast Receive Frames

Pause Receive Frames

Receive CRC Errors

RXALIGNCODEERRORS Receive Alignment/Code Errors

RXOVERSIZED

RXJABBER

Receive Oversized Frames

Receive Jabber Frames

RXUNDERSIZED

RXFRAGMENTS

RXFILTERED

Receive Undersized Frames

Receive Frame Fragments

Filtered Receive Frames

RXQOSFILTERED

RXOCTETS

Receive QOS Filtered Frames

Receive Octet Frames

TXGOODFRAMES

TXBCASTFRAMES

TXMCASTFRAMES

TXPAUSEFRAMES

TXDEFERRED

TXCOLLISION

Good Transmit Frames

Broadcast Transmit Frames

Multicast Transmit Frames

Pause Transmit Frames

Deferred Transmit Frames

Transmit Collision Frames

TXSINGLECOLL

TXMULTICOLL

TXEXCESSIVECOLL

TXLATECOLL

Transmit Single Collision Frames

Transmit Multiple Collision Frames

Transmit Excessive Collision Frames

Transmit Late Collision Frames

Transmit Underrun Error

TXUNDERRUN

TXCARRIERSENSE

TXOCTETS

Transmit Carrier Sense Errors

Transmit Octet Frames

FRAME64

Transmit and Receive 64 Octet Frames

Transmit and Receive 65 to 127 Octet Frames

Transmit and Receive 128 to 255 Octet Frames

Transmit and Receive 256 to 511 Octet Frames

Transmit and Receive 512 to 1023 Octet Frames

FRAME65T127

FRAME128T255

FRAME256T511

FRAME512T1023

FRAME1024TUP

Transmit and Receive 1024 to RXMAXLEN Octet

Frames

0x4A10 0280

0x4A10 0284

0x4A12 0280

0x4A12 0284

NETOCTETS

Network Octet Frames

RXSOFOVERRUNS

Receive FIFO or DMA Start of Frame Overruns

Peripheral Information and Timings

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Table 8-38. EMAC Network Statistics Registers (continued)

EMAC0 HEX ADDRESS

0x4A10 0288

EMAC1 HEX ADDRESS

0x4A12 0288

ACRONYM

REGISTER NAME

RXMOFOVERRUNS

RXDMAOVERRUNS

Receive FIFO or DMA Middle of Frame Overruns

Receive DMA Overruns

0x4A10 028C

0x4A12 028C

Table 8-39. EMAC Control Module Registers

EMAC0 HEX ADDRESS

0x4A10 0900

0x4A10 0904

0x4A10 0908

0x4A10 090C

0x4A10 0910

0x4A10 0914

0x4A10 0918

0x4A10 091C

0x4A10 0940

0x4A10 0944

0x4A10 0948

0x4A10 094C

0x4A10 0970

0x4A10 0974

EMAC1 HEX ADDRESS

0x4A12 0900

0x4A12 0904

0x4A12 0908

0x4A12 090C

0x4A12 0910

0x4A12 0914

0x4A12 0918

0x4A12 091C

0x4A12 0940

0x4A12 0944

0x4A12 0948

0x4A12 094C

0x4A12 0970

0x4A12 0974

ACRONYM

CMIDVER

REGISTER NAME

Identification and Version

Software Reset

CMSOFTRESET

CMEMCONTROL

CMINTCTRL

Emulation Control

Interrupt Control

CMRXTHRESHINTEN

CMRXINTEN

Receive Threshold Interrupt Enable

Receive Interrupt Enable

Transmit Interrupt Enable

Miscellaneous Interrupt Enable

CMTXINTEN

CMMISCINTEN

CMRXTHRESHINTSTAT Receive Threshold Interrupt Status

CMRXINTSTAT

CMTXINTSTAT

CMMISCINTSTAT

CMRXINTMAX

CMTXINTMAX

Receive Interrupt Status

Transmit Interrupt Status

Miscellaneous Interrupt Status

Receive Interrupts Per Millisecond

Transmit Interrupts Per Millisecond

Table 8-40. EMAC Descriptor Memory RAM

EMAC0 HEX ADDRESS

EMAC1 HEX ADDRESS

DESCRIPTION

0x4A10 2000 - 0x4A10 3FFF

0x4A12 2000 - 0x4A12 3FFF

EMAC Control Module Descriptor Memory

198

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8.6.2 EMAC Electrical Data/Timing

Table 8-41. Timing Requirements for EMAC[1:0]_RXCLK - [G]MII Operation

(see Figure 8-44)

1000 Mbps (1 Gbps)

(GMII Only)

100 Mbps

10 Mbps

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time,

EMAC[1:0]_RXCLK

1

2

3

4

t_c(RXCLK)

t_w(RXCLKH)

t_w(RXCLKL)

t_t(RXCLK)

8

40

400

ns

Pulse duration,

EMAC1:0]_RXCLK high

2.8

14

140

Pulse duration,

EMAC[1:0]_RXCLK low

Transition time,

EMAC[1:0]_RXCLK

1

3

1

4

2

3

EMAC[1:0]_RXCLK

4

Figure 8-44. EMAC[1:0]_RXCLK Timing

Table 8-42. Timing Requirements for EMAC[1:0]_TXCLK - [G]MII Operation

(see Figure 8-45)

1000 Mbps (1 Gbps)

(GMII Only)

100 Mbps

10 Mbps

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time,

EMAC[1:0]_TXCLK

1

2

3

4

t_c(TXCLK)

t_w(TXCLKH)

t_w(TXCLKL)

t_t(TXCLK)

8

40

400

ns

Pulse duration,

EMAC[1:0]_TXCLK high

2.8

14

140

Pulse duration,

EMAC[1:0]_TXCLK low

Transition time,

EMAC[1:0]_TXCLK

1

3

1

4

2

3

EMAC[1:0]_TXCLK

4

Figure 8-45. EMAC[1:0]_TXCLK Timing

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Table 8-43. Timing Requirements for EMAC [G]MII Receive 10/100/1000 Mbit/s

(see Figure 8-46)

1000 Mbps (1

Gbps)

100/10 Mbps

NO.

UNIT

MIN

MAX

MIN

MAX

t_{su(RXD-RXCLK)}

Setup time, receive selected signals valid before

EMAC[1:0]_RXCLK

1

2

t_{su(RXDV-RXCLK)}

t_{su(RXER-RXCLK)}

t_h(RXCLK-RXD)

t_{h(RXCLK-RXDV)}

t_{h(RXCLK-RXER)}

2

8

ns

Hold time, receive selected signals valid after

EMAC[1:0]_RXCLK

0

8

ns

1

2

EMAC[1:0]_RXCLK (input)

EMAC[1:0]_RXD7−EMAC[1:0]_RXD0,

EMAC[1:0]_RXDV, EMAC[1:0]_RXER (inputs)

Figure 8-46. EMAC Receive Timing

Table 8-44. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII

Transmit 10/100 Mbits/s

(see Figure 8-47)

100/10 Mbps

MIN

NO.

PARAMETER

UNIT

MAX

t_d(TXCLK-TXD)

t_{d(TXCLK-TXEN)}

1

Delay time, EMAC[1:0]_TXCLK to transmit selected signals valid

5

25

ns

Table 8-45. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII

Transmit 1000 Mbits/s

(see Figure 8-47)

1000 Mbps (1 Gbps)

NO.

PARAMETER

UNIT

MIN

MAX

t_{d(GMTCLK-TXD)}

1

Delay time, EMAC[1:0]_GMTCLK to transmit selected signals valid

0.5

5

ns

t_{d(GMTCLK-TXEN)}

1

EMAC[1:0]_TXCLK (input)

EMAC[1:0]_TXD7−EMAC[1:0]_TXD0,

EMAC[1:0]_TXEN (outputs)

Figure 8-47. EMAC Transmit Timing

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8.6.3 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system.

The MDIO module implements the 802.3 serial management interface to interrogate and control Ethernet

PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the

auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and

configure required parameters in the EMAC module for correct operation. The module is designed to allow

almost transparent operation of the MDIO interface, with very little maintenance from the core processor.

A single MDIO interface is pinned out to control the PHY configuration and status monitoring. Multiple

external PHYs can be controlled by the MDIO interface.

For more detailed information on the MDIO peripheral, see the EMAC/MDIO chapter in the AM38x Sitara

ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.6.3.1 MDIO Peripheral Register Descriptions

Table 8-46. MDIO Registers

HEX ADDRESS

0x4A10 0800

ACRONYM

VERSION

REGISTER NAME

MDIO Version

0x4A10 0804

CONTROL

MDIO Control

0x4A10 0808

ALIVE

PHY Alive Status

0x4A10 080C

0x4A10 0810

LINK

PHY Link Status

LINKINTRAW

LINKINTMASKED

-

MDIO Link Status Change Interrupt (Unmasked)

MDIO Link Status Change Interrupt (Masked)

Reserved

0x4A10 0814

0x4A10 0818

0x4A10 081C

0x4A10 0820

USERINTRAW

USERINTMASKED

USERINTMASKSET

USERINTMASKCLEAR

-

MDIO User Command Complete Interrupt (Unmasked)

MDIO User Command Complete Interrupt (Masked)

MDIO User Command Complete Interrupt Mask Set

MDIO User Command Complete Interrupt Mask Clear

Reserved

0x4A10 0824

0x4A10 0828

0x4A10 082C

0x4A10 0830 - 0x4A10 087C

0x4A10 0880

USERACCESS0

USERPHYSEL0

USERACCESS1

USERPHYSEL1

MDIO User Access 0

MDIO User PHY Select 0

0x4A10 0884

MDIO User Access 1

0x4A10 0888

MDIO User PHY Select 1

8.6.3.2 MDIO Electrical Data/Timing

Table 8-47. Timing Requirements for MDIO Input

(see Figure 8-48)

NO.

MIN

400

180

20

MAX UNIT

1

t_c(MCLK)

Cycle time, MDIO_MCLK

ns

t_w(MCLK)

Pulse duration, MDIO_MCLK high or low

4

5

t_{su(MDIO-MCLKH)}

t_{h(MCLKH-MDIO)}

Setup time, MDIO_MDIO data input valid before MDIO_MCLK high

Hold time, MDIO_MDIO data input valid after MDIO_MCLK high

0

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1

MDIO_MCLK

4

5

MDIO_MDIO

(input)

Figure 8-48. MDIO Input Timing

Table 8-48. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

(see Figure 8-49)

NO.

PARAMETER

MIN

MAX UNIT

100 ns

7

t_{d(MCLKL-MDIO)}

Delay time, MDIO_MCLK low to MDIO_MDIO data output valid

1

MDIO_MCLK

7

MDIO_MDIO

(output)

Figure 8-49. MDIO Output Timing

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8.7 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register controls the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt generation

modes. The GPIO peripheral provides generic connections to external devices.

The device contains two GPIO modules and each GPIO module is made up of 32 identical channels.

The device GPIO peripheral supports the following:

•

Up to 64 3.3-V GPIO pins, GP0[31:0] and GP1[31:0] (the exact number available varies as a function

of the device configuration). Each channel can be configured to be used in the following applications:

–

Data input/output

Keyboard interface with a de-bouncing cell

Synchronous interrupt generation (in active mode) upon the detection of external events (signal

transition(s) and/or signal level(s)).

•

Synchronous interrupt requests from each channel are processed by two identical interrupt generation

sub-modules to be used independently by the ARM. Interrupts can be triggered by rising and/or falling

edge, specified for each interrupt-capable GPIO signal.

Shared registers can be accessed through "Set & Clear" protocol. Software writes 1 to corresponding

bit position(s) to set or to clear GPIO signal(s). This allows multiple software processes to toggle GPIO

output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts,

to prevent context switching to another process during GPIO programming).

•

Separate input/output registers.

Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic to be implemented.

For more detailed information on GPIOs, see the GPIO chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.7.1 GPIO Peripheral Register Descriptions

Table 8-49. GPIO Registers

GPIO0 HEX ADDRESS

0x4803 2000

0x4803 2010

0x4803 2020

0x4803 2024

0x4803 2028

0x4803 202C

0x4803 2030

0x4803 2034

0x4803 2038

0x4803 203C

0x4803 2040

0x4803 2044

0x4803 2048

0x4803 2114

0x4803 2130

0x4803 2134

GPIO1 HEX ADDRESS

0x4804 C000

0x4804 C010

0x4804 C020

0x4804 C024

0x4804 C028

0x4804 C02C

0x4804 C030

0x4804 C034

0x4804 C038

0x4804 C03C

0x4804 C040

0x4804 C044

0x4804 C048

0x4804 C114

0x4804 C130

0x4804 C134

ACRONYM

GPIO_REVISION

REGISTER NAME

GPIO Revision

GPIO_SYSCONFIG

GPIO_EOI

System Configuration

End of Interrupt

GPIO_IRQSTATUS_RAW_0

GPIO_IRQSTATUS_RAW_1

GPIO_IRQSTATUS_0

GPIO_IRQSTATUS_1

GPIO_IRQSTATUS_SET_0

GPIO_IRQSTATUS_SET_1

GPIO_IRQSTATUS_CLR_0

GPIO_IRQSTATUS_CLR_1

GPIO_IRQWAKEN_0

GPIO_IRQWAKEN_1

GPIO_SYSSTATUS

GPIO_CTRL

Status Raw for Interrupt 1

Status Raw for Interrupt 2

Status for Interrupt 1

Status for Interrupt 2

Enable Set for Interrupt 1

Enable Set for Interrupt 2

Enable Clear for Interrupt 1

Enable Clear for Interrupt 2

Wakeup Enable for Interrupt 1

Wakeup Enable for Interrupt 2

System Status

Module Control

GPIO_OE

Output Enable

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Table 8-49. GPIO Registers (continued)

GPIO0 HEX ADDRESS

0x4803 2138

0x4803 213C

0x4803 2140

0x4803 2144

0x4803 2148

0x4803 214C

0x4803 2150

0x4803 2154

0x4803 2190

0x4803 2194

GPIO1 HEX ADDRESS

0x4804 C138

0x4804 C13C

0x4804 C140

0x4804 C144

0x4804 C148

0x4804 C14C

0x4804 C150

0x4804 C154

0x4804 C190

0x4804 C194

ACRONYM

REGISTER NAME

Data Input

GPIO_DATAIN

GPIO_DATAOUT

Data Output

GPIO_LEVELDETECT0

GPIO_LEVELDETECT1

GPIO_RISINGDETECT

GPIO_FALLINGDETECT

GPIO_DEBOUNCENABLE

GPIO_DEBOUNCINGTIME

GPIO_CLEARDATAOUT

GPIO_SETDATAOUT

Detect Low Level

Detect High Level

Detect Rising Edge

Detect Falling Edge

Debouncing Enable

Debouncing Value

Clear Data Output

Set Data Output

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8.7.2 GPIO Electrical Data/Timing

Table 8-50. Timing Requirements for GPIO Inputs

(see Figure 8-50)

NO.

MIN

12P⁽¹⁾

MAX UNIT

1

2

t_w(GPIH)

t_w(GPIL)

Pulse duration, GP[x] input high

Pulse duration, GP[x] input low

ns

(1) P = Module clock.

Table 8-51. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs

(see Figure 8-50)

NO.

3

PARAMETER

MIN

36P-8⁽¹⁾

MAX UNIT

t_w(GPOH)

t_w(GPOL)

Pulse duration, GP[x] output high

Pulse duration, GP[x] output low

ns

4

(1) P = Module clock.

2

1

GP[1:0][x]

input

4

3

GP[1:0][x]

output

Figure 8-50. GPIO Port Timing

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8.8 General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)

The GPMC is a device memory controller used to provide a glueless interface to external memory devices

such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND

Flash), SRAM, and Pseudo-SRAM. It includes flexible asynchronous protocol control for interface to

SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).

Other supported features include:

•

8-/16-bit wide multiplexed address/data bus

Up to 6 chip selects with up to 256M-byte address space per chip select pin

Non-multiplexed address/data mode

Pre-fetch and write posting engine associated with system DMA to get full performance from NAND

device with minimum impact on NOR/SRAM concurrent access.

The device also contains an Error Locator Module (ELM) which is used to extract error addresses from

syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the

read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus

optionally spare area information. The ELM has the following features:

•

4-bit, 8-bit, and 16-bit per 512-byte block error location based on BCH algorithms

Eight simultaneous processing contexts

Page-based and continuous modes

Interrupt generation on error location process completion

–

When the full page has been processed in page mode

For each syndrome polynomial in continuous mode.

For more detailed information on the GPMC, see the GPMC chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.8.1 GPMC and ELM Peripheral Register Descriptions

Table 8-52. GPMC Registers⁽¹⁾⁽²⁾

HEX ADDRESS

0x5000 0000

ACRONYM

GPMC_REVISION

REGISTER NAME

GPIO Revision

0x5000 0010

GPMC_SYSCONFIG

GPMC_SYSSTATUS

GPMC_IRQSTATUS

GPMC_IRQENABLE

GPMC_TIMEOUT_CONTROL

GPMC_ERR_ADDRESS

GPMC_ERR_TYPE

GPMC_CONFIG

System Configuration

System Status

0x5000 0014

0x5000 0018

Status for Interrupt

Interrupt Enable

0x5000 001C

0x5000 0040

Timeout Counter Start Value

Error Address

0x5000 0044

0x5000 0048

Error Type

0x5000 0050

GPMC Global Configuration

GPMC Global Status

Parameter Configuration 1_0-5

0x5000 0054

GPMC_STATUS

0x5000 0060 + (0x0000 0030 * i)

GPMC_CONFIG1_0 -

GPMC_CONFIG1_5

0x5000 0064 + (0x0000 0030 * i)

0x5000 0068 + (0x0000 0030 * i)

0x5000 006C + (0x0000 0030 * i)

0x5000 0070 + (0x0000 0030 * i)

GPMC_CONFIG2_0 -

GPMC_CONFIG2_5

Parameter Configuration 2_0-5

Parameter Configuration 3_0-5

Parameter Configuration 4_0-5

Parameter Configuration 5_0-5

GPMC_CONFIG3_0 -

GPMC_CONFIG3_5

GPMC_CONFIG4_0 -

GPMC_CONFIG4_5

GPMC_CONFIG5_0 -

GPMC_CONFIG5_5

(1) i = 0 to 5.

(2) j = 0 to 8.

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Table 8-52. GPMC Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

0x5000 0074 + (0x0000 0030 * i)

0x5000 0078 + (0x0000 0030 * i)

0x5000 007C + (0x0000 0030 * i)

0x5000 0080 + (0x0000 0030 * i)

0x5000 0084 + (0x0000 0030 * i)

GPMC_CONFIG6_0 -

GPMC_CONFIG6_5

Parameter Configuration 6_0-5

GPMC_CONFIG7_0 -

GPMC_CONFIG7_5

Parameter Configuration 7_0-5

NAND Command 0-5

NAND Address 0-5

GPMC_NAND_COMMAND_0 -

GPMC_NAND_COMMAND_5

GPMC_NAND_ADDRESS_0 -

GPMC_NAND_ADDRESS_5

GPMC_NAND_DATA_0 -

GPMC_NAND_DATA_5

NAND Data 0-5

0x5000 01E0

0x5000 01E4

GPMC_PREFETCH_CONFIG1

GPMC_PREFETCH_CONFIG2

GPMC_PREFETCH_CONTROL

GPMC_PREFETCH_STATUS

GPMC_ECC_CONFIG

Prefetch Configuration 1

Prefetch Configuration 2

Prefetch Control

0x5000 01EC

0x5000 01F0

Prefetch Status

0x5000 01F4

ECC Configuration

ECC Control

0x5000 01F8

GPMC_ECC_CONTROL

0x5000 01FC

GPMC_ECC_SIZE_CONFIG

ECC Size Configuration

ECC0-8 Result

0x5000 0200 + (0x0000 0004 * j)

GPMC_ECC0_RESULT -

GPMC_ECC8_RESULT

0x5000 0240 + (0x0000 0010 * i)

0x5000 0244 + (0x0000 0010 * i)

0x5000 0248 + (0x0000 0010 * i)

0x5000 024C + (0x0000 0010 * i)

0x5000 0300 + (0x0000 0010 * i)

0x5000 0304 + (0x0000 0010 * i)

0x5000 0308 + (0x0000 0010 * i)

0x5000 02D0

GPMC_BCH_RESULT0_0 -

GPMC_BCH_RESULT0_5

BCH Result 0_0-5

BCH Result 1_0-5

BCH Result 2_0-5

BCH Result 3_0-5

BCH Result 4_0-5

BCH Result 5_0-5

BCH Result 6_0-5

BCH Data

GPMC_BCH_RESULT1_0 -

GPMC_BCH_RESULT1_5

GPMC_BCH_RESULT2_0 -

GPMC_BCH_RESULT2_5

GPMC_BCH_RESULT3_0 -

GPMC_BCH_RESULT3_5

GPMC_BCH_RESULT4_0 -

GPMC_BCH_RESULT4_5

GPMC_BCH_RESULT5_0 -

GPMC_BCH_RESULT5_5

GPMC_BCH_RESULT6_0 -

GPMC_BCH_RESULT6_5

GPMC_BCH_SWDATA

Table 8-53. ELM Registers⁽¹⁾

HEX ADDRESS

0x4808 0000

ACRONYM

REGISTER NAME

ELM_REVISION

Revision

0x4808 0010

ELM_SYSCONFIG

Configuration

0x4808 0014

ELM_SYSSTATUS

Status

0x4808 0018

ELM_IRQSTATUS

Interrupt status

0x4808 001C

ELM_IRQENABLE

Interrupt enable

0x4808 0020

ELM_LOCATION_CONFIG

ELM_PAGE_CTRL

ECC algorithm parameters

Page definition

0x4808 0080

0x4808 0400 + (0x40 * i)

0x4808 0404 + (0x40 * i)

0x4808 0408 + (0x40 * i)

0x4808 040C + (0x40 * i)

0x4808 0410 + (0x40 * i)

0x4808 0414 + (0x40 * i)

ELM_SYNDROME_FRAGMENT_0_i

ELM_SYNDROME_FRAGMENT_1_i

ELM_SYNDROME_FRAGMENT_2_i

ELM_SYNDROME_FRAGMENT_3_i

ELM_SYNDROME_FRAGMENT_4_i

ELM_SYNDROME_FRAGMENT_5_i

Input syndrome polynomial bits 0 to 31

Input syndrome polynomial bits 32 to 63

Input syndrome polynomial bits 64 to 95

Input syndrome polynomial bits 96 to 127

Input syndrome polynomial bits 128 to 159

Input syndrome polynomial bits 160 to 191

(1) i = 0 to 7.

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Table 8-53. ELM Registers (continued)

HEX ADDRESS

ACRONYM

REGISTER NAME

Input syndrome polynomial bits 192 to 207

Exit status

0x4808 0418 + (0x40 * i)

0x4808 0800 + (0x100 * i)

0x4808 0880 + (0x100 * i)

0x4808 0884 + (0x100 * i)

0x4808 0888 + (0x100 * i)

0x4808 088C + (0x100 * i)

0x4808 0890 + (0x100 * i)

0x4808 0894 + (0x100 * i)

0x4808 0898 + (0x100 * i)

0x4808 089C + (0x100 * i)

0x4808 08A0 + (0x100 * i)

0x4808 08A4 + (0x100 * i)

0x4808 08A8 + (0x100 * i)

0x4808 08AC + (0x100 * i)

0x4808 08B0 + (0x100 * i)

0x4808 08B4 + (0x100 * i)

0x4808 08B8 + (0x100 * i)

0x4808 08BC + (0x100 * i)

ELM_SYNDROME_FRAGMENT_6_i

ELM_LOCATION_STATUS_i

ELM_ERROR_LOCATION_0_i

ELM_ERROR_LOCATION_1_i

ELM_ERROR_LOCATION_2_i

ELM_ERROR_LOCATION_3_i

ELM_ERROR_LOCATION_4_i

ELM_ERROR_LOCATION_5_i

ELM_ERROR_LOCATION_6_i

ELM_ERROR_LOCATION_7_i

ELM_ERROR_LOCATION_8_i

ELM_ERROR_LOCATION_9_i

ELM_ERROR_LOCATION_10_i

ELM_ERROR_LOCATION_11_i

ELM_ERROR_LOCATION_12_i

ELM_ERROR_LOCATION_13_i

ELM_ERROR_LOCATION_14_i

ELM_ERROR_LOCATION_15_i

Error location

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8.8.2 GPMC Electrical Data/Timing

8.8.2.1 GPMC/NOR Flash Interface Synchronous Mode Timing

Table 8-54. Timing Requirements for GPMC/NOR Flash Interface - Synchronous Mode

(see Figure 8-51, Figure 8-52, Figure 8-53, Figure 8-54, Figure 8-55, Figure 8-56)

NO.

MIN

3.2

2.5

3.2

2.5

MAX

UNIT

ns

13 t_su(DV-CLKH)

14 t_h(CLKH-DV)

22 t_{su(WAITV-CLKH)}

23 t_{h(CLKH-WAITV)}

Setup time, read GPMC_D[15:0] valid before GPMC_CLK high

Hold time, read GPMC_D[15:0] valid after GPMC_CLK high

Setup time, GPMC_WAIT valid before GPMC_CLK high

Hold time, GPMC_WAIT valid after GPMC_CLK high

ns

Table 8-55. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Synchronous Mode

(see Figure 8-51, Figure 8-52, Figure 8-53, Figure 8-54, Figure 8-55, Figure 8-56)

NO.

PARAMETER

MIN

16⁽¹⁾

0.5P⁽²⁾

F - 2.2⁽³⁾

E - 2.2⁽⁴⁾

MAX

UNIT

1

t_c(CLK)

Cycle time, output clock GPMC_CLK period

Pulse duration, output clock GPMC_CLK high

Pulse duration, output clock GPMC_CLK low

Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition

Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid

ns

t_w(CLKH)

2

ns

t_w(CLKL)

3

4

t_d(CLKH-nCSV)

t_{d(CLKH-nCSIV)}

F + 4.5⁽³⁾

E + 4.5⁽⁴⁾

ns

Delay time, GPMC_A[27:0] address bus valid to GPMC_CLK first

edge

5

6

7

8

t_d(ADDV-CLK)

t_{d(CLKH-ADDIV)}

t_d(nBEV-CLK)

t_{d(CLKH-nBEIV)}

B - 4.5⁽⁵⁾

B + 2.3⁽⁵⁾

ns

Delay time, GPMC_CLK rising edge to GPMC_A[27:0] GPMC

address bus invalid

-2.3

Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK

first edge

B - 1.9⁽⁵⁾

D - 2.3⁽⁶⁾

B + 2.3⁽⁵⁾

D + 1.9⁽⁶⁾

Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE,

GPMC_BE1 invalid

(1) Sync mode = 62.5 MHz; Async mode = 125 MHz.

(2) P = GPMC_CLK period.

(3) For nCS falling edge (CS activated):

•

For GpmcFCLKDivider = 0:

F = 0.5 * CSExtraDelay * GPMC_FCLK

For GpmcFCLKDivider = 1:

•

F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are

even)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise

•

For GpmcFCLKDivider = 2:

F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)

F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

(4) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(5) B = ClkActivationTime * GPMC_FCLK

(6) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

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Table 8-55. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Synchronous Mode (continued)

(see Figure 8-51, Figure 8-52, Figure 8-53, Figure 8-54, Figure 8-55, Figure 8-56)

NO.

PARAMETER

MIN

G - 2.3⁽⁷⁾

D - 2.3⁽⁶⁾

H - 2.3⁽⁸⁾

E - 2.3⁽⁴⁾

MAX

G + 4.5⁽⁷⁾

D + 4.5⁽⁶⁾

H + 3.5⁽⁸⁾

E + 3.5⁽⁴⁾

UNIT

ns

9

t_d(CLKH-nADV)

Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE transition

Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE invalid

Delay time, GPMC_CLK rising edge to GPMC_OE_RE transition

Delay time, GPMC_CLK rising edge to GPMC_OE_RE invalid

10 t_{d(CLKH-nADVIV)}

11 t_d(CLKH-nOE)

12 t_{d(CLKH-nOEIV)}

ns

(7) For ADV falling edge (ADV activated):

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

•

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are

even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

•

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)

(8) For OE falling edge (OE activated) / IO DIR rising edge (IN direction) :

•

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are

even)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

•

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are

even)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

210

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Table 8-55. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Synchronous Mode (continued)

(see Figure 8-51, Figure 8-52, Figure 8-53, Figure 8-54, Figure 8-55, Figure 8-56)

NO.

PARAMETER

MIN

MAX

UNIT

15 t_d(CLKH-nWE)

Delay time, GPMC_CLK rising edge to GPMC_WE transition

I - 2.3⁽⁹⁾

I + 4.5⁽⁹⁾

ns

Delay time, GPMC_CLK rising edge to GPMC_D[15:0] data bus

transition

16 t_d(CLKH-Data)

18 t_d(CLKH-nBE)

J - 2.3⁽¹⁰⁾

J + 1.9⁽¹⁰⁾

ns

Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE,

GPMC_BE1 transition

19 t_w(nCSV)

20 t_w(nBEV)

21 t_w(nADVV)

Pulse duration, GPMC_CS[x] low

A⁽¹¹⁾

C⁽¹²⁾

K⁽¹³⁾

ns

Pulse duration, GPMC_BE0_CLE, GPMC_BE1 low

Pulse duration, GPMC_ADV_ALE low

Delay time, GPMC_CLK rising edge to GPMC_DIR high (IN

direction)

24 t_d(CLKH-DIR)

25 t_{d(CLKH-DIRIV)}

H - 2.3⁽⁸⁾

H + 4.5⁽⁸⁾

ns

Delay time, GPCM_CLK rising edge to GPMC_DIR low (OUT

direction)

M - 2.3⁽¹⁴⁾

M + 4.5⁽¹⁴⁾

(9) For WE falling edge (WE activated):

•

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

•

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are

even)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

•

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

•

Case GpmcFCLKDivider = 1:

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are

even)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

•

Case GpmcFCLKDivider = 2:

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(10) J = GPMC_FCLK period.

(11) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n

= page burst access number]

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n

= page burst access number]

(12) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: C = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst access

number]

For Burst write: C = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst

access number]

(13) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(14) M = ( RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK.

Parameter M expression is given as one example of GPMC programming. The IO DIR signal goes from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of the IO direction signal depends on the kind of successive read/write

accesses performed to the memory and multiplexed or non-multiplexed memory addressing scheme, whether the bus keeping feature is

enabled or not. The IO DIR behavior is automatically handled by the GPMC controller.

Peripheral Information and Timings

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2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

5

GPMC_A[27:0]

Address

7

8

20

GPMC_BE1

7

20

GPMC_BE0_CLE

9

21

10

12

GPMC_ADV_ALE

GPMC_OE

11

14

13

GPMC_D[15:0]

GPMC_WAIT

GPMC_DIR

D0

22

23

24

25

OUT

IN

OUT

Figure 8-51. GPMC Non-Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

212

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2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

GPMC_A[27:0]

GPMC_BE1

5

7

Address

20

8

Valid

7

20

Valid

GPMC_BE0_CLE

9

10

21

GPMC_ADV_ALE

GPMC_OE

11

12

13

14

D0

13

GPMC_D[15:0]

GPMC_WAIT

D1

D2

D3

23

22

24

25

OUT

IN

GPMC_DIR

Figure 8-52. GPMC Non-Multiplexed NOR Flash - 4x16-bit Synchronous Burst Read

(GPMCFCLKDIVIDER = 0)

2

1

GPMC_CLK

GPMC_CS[x]

3

4

19

5

7

GPMC_A[27:0]

GPMC_BE1

Address

18

7

GPMC_BE0_CLE

9

10

21

GPMC_ADV_ALE

15

GPMC_WE

GPMC_D[15:0]

GPMC_WAIT

16

D0

23

D1

D2

D3

22

OUT

GPMC_DIR

Figure 8-53. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

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2

1

2

GPMC_CLK

GPMC_CS[x]

4

3

19

5

GPMC_A[27:16]

Address (MSB)

20

8

7

GPMC_BE1

8

7

20

GPMC_BE0_CLE

9

10

12

21

GPMC_ADV_ALE

GPMC_OE

11

14

6

5

13

D0

Address (LSB)

GPMC_D[15:0]

23

22

GPMC_WAIT

GPMC_DIR

24

25

OUT

IN

OUT

Figure 8-54. GPMC Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)

214

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2

1

2

GPMC_CLK

3

4

19

GPMC_CS[x]

GPMC_A[27:16]

GPMC_BE1

5

7

Address (MSB)

8

20

Valid

7

20

Valid

GPMC_BE0_CLE

9

10

12

21

GPMC_ADV_ALE

GPMC_OE

11

6

13

14

D0

13

5

GPMC_D[15:0]

GPMC_WAIT

Address (LSB)

D1

D2

D3

23

22

24

25

OUT

IN

GPMC_DIR

Figure 8-55. GPMC Multiplexed NOR Flash - 4x16-bit Synchronous Burst Read (GPMCFCLKDIVIDER = 0)

2

1

GPMC_CLK

GPMC_CS[x]

3

4

19

5

7

Address (MSB)

GPMC_A[27:16]

GPMC_BE1

18

7

GPMC_BE0_CLE

9

10

21

GPMC_ADV_ALE

15

GPMC_WE

GPMC_D[15:0]

GPMC_WAIT

16

Address (LSB)

D0

D1

D2

D3

23

22

OUT

GPMC_DIR

Figure 8-56. GPMC Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

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8.8.2.2 GPMC/NOR Flash Interface Asynchronous Mode Timing

Table 8-56. GPMC/NOR Flash Interface Asynchronous Mode Timing - Internal Parameters

NO.

1

MIN

MAX UNIT

Max. output data generation delay from internal functional clock

Max. input data capture delay by internal functional clock

Max. chip select generation delay from internal functional clock

Max. address generation delay from internal functional clock

Max. address valid generation delay from internal functional clock

Max. byte enable generation delay from internal functional clock

Max. output enable generation delay from internal functional clock

Max. write enable generation delay from internal functional clock

Max. functional clock skew

6.5

4

ns

ps

2

3

6.5

100

4

5

6

7

8

9

Table 8-57. Timing Requirements for GPMC/NOR Flash Interface - Asynchronous Mode

(see Figure 8-57, Figure 8-58, Figure 8-59, Figure 8-61)

NO.

MIN

MAX

UNIT

6

t_acc(DAT)

21 t_{acc1-pgmode(DAT)}

22 t_{acc2-pgmode(DAT)}

Data maximum access time (GPMC_FCLK cycles)

H⁽¹⁾cycles

Page mode successive data maximum access time (GPMC_FCLK

cycles)

P⁽²⁾

H⁽¹⁾

cycles

Page mode first data maximum access time (GPMC_FCLK cycles)

(1) H = AccessTime * (TimeParaGranularity + 1)

(2) P = PageBurstAccessTime * (TimeParaGranularity + 1).

Table 8-58. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Asynchronous Mode

(see Figure 8-57, Figure 8-58, Figure 8-59, Figure 8-60, Figure 8-61, Figure 8-62)

NO.

1

PARAMETER

MIN

MAX

N⁽¹⁾

A⁽²⁾

UNIT

ns

t_w(nBEV)

Pulse duration, GPMC_BE0_CLE, GPMC_BE1 valid time

Pulse duration, GPMC_CS[x] low

2

t_w(nCSV)

ns

4

t_{d(nCSV-nADVIV)}

Delay time, GPMC_CS[x] valid to GPMC_NADV_ALE invalid

B - 0.2⁽³⁾

C - 0.2⁽⁴⁾

J - 0.2⁽⁵⁾

B + 2.0⁽³⁾

ns

Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (single

read)

5

t_{d(nCSV-nOEIV)}

C + 2.0⁽⁴⁾

J + 2.0⁽⁵⁾

ns

10 t_d(AV-nCSV)

Delay time, address bus valid to GPMC_CS[x] valid

Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CS[x]

valid

11 t_d(nBEV-nCSV)

13 t_{d(nCSV-nADVV)}

14 t_d(nCSV-nOEV)

Delay time, GPMC_CS[x] valid to GPMC_ADV_ALE valid

Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid

K - 0.2⁽⁶⁾

L - 0.2⁽⁷⁾

K + 2.0⁽⁶⁾

L + 2.0⁽⁷⁾

ns

(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(3) = B - nCS Max Delay + nADV Min Delay

For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

(4) = C - nCS Max Delay + nOE Min Delay

C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(5) = J - Address Max Delay + nCS Min Delay

J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(6) = K - nCS Max Delay + nADV Min Delay

K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK

(7) = L - nCS Max Delay + nOE Min Delay

L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

216

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Table 8-58. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash

Interface - Asynchronous Mode (continued)

(see Figure 8-57, Figure 8-58, Figure 8-59, Figure 8-60, Figure 8-61, Figure 8-62)

NO.

PARAMETER

MIN

L - 0.2⁽⁷⁾

M - 0.2⁽⁸⁾

G⁽⁹⁾

MAX

L + 2.0⁽⁷⁾

M + 2.0⁽⁸⁾

UNIT

ns

15 t_d(nCSV-DIR)

16 t_d(nCSV-DIR)

17 t_w(AIV)

Delay time, GPMC_CS[x] valid to GPMC_DIR high

Delay time, GPMC_CS[x] valid to GPMC_DIR low

Address invalid duration between 2 successive R/W accesses

ns

Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst

read)

19 t_{d(nCSV-nOEIV)}

I - 0.2⁽¹⁰⁾

I + 2.0⁽¹⁰⁾

ns

21 t_w(AV)

Pulse duration, address valid: second, third and fourth accesses

Delay time, GPMC_CS[x] valid to GPMC_WE valid

Delay time, GPMC_CS[x] valid to GPMC_WE invalid

Delay time, GPMC_WE valid to data bus valid

D⁽¹¹⁾

E - 0.2⁽¹²⁾

F - 0.2⁽¹³⁾

ns

26 t_d(nCSV-nWEV)

28 t_{d(nCSV-nWEIV)}

29 t_d(nWEV-DV)

30 t_d(DV-nCSV)

E + 2.0⁽¹²⁾

F + 2.0⁽¹³⁾

2.0

Delay time, data bus valid to GPMC_CS[x] valid

J - 0.2⁽⁵⁾

J + 2.0⁽⁵⁾

Delay time, GPMC_OE_RE valid to GPMC_A[16:1]_D[15:0]

address phase end

38 t_d(nOEV-AIV)

2.0

ns

(8) = M - nCS Max Delay + nOE Min Delay

M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK.

Parameter M expression is given as one example of GPMC programming. The IO DIR signal goes from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of the IO direction signal depends on the kind of successive read/write

accesses performed to the memory and multiplexed or non-multiplexed memory addressing scheme, whether the bus keeping feature is

enabled or not. The IO DIR behavior is automatically handled by the GPMC controller.

(9) G = Cycle2CycleDelay * GPMC_FCLK

(10) = I - nCS Max Delay + nOE Min Delay

I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *

GPMC_FCLK

(11) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK

(12) = E - nCS Max Delay + nWE Min Delay

E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(13) = F - nCS Max Delay + nWE Min Delay

F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

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GPMC_FCLK

GPMC_CLK

6

2

GPMC_CS[x]

10

GPMC_A[10:1]

Valid Address

1

11

GPMC_BE1

11

1

GPMC_BE0_CLE

4

13

GPMC_ADV_ALE

5

14

GPMC_OE

GPMC_D[15:0]

Data In 0

GPMC_WAIT

16

15

GPMC_DIR

OUT

IN

OUT

Figure 8-57. GPMC Non-Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

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GPMC_FCLK

GPMC_CLK

6

2

GPMC_CS[x]

17

10

11

10

11

GPMC_A[10:1]

Address 2

1

Address 1

1

GPMC_BE1

GPMC_BE0_CLE

GPMC_ADV_ALE

11

1

4

13

5

14

GPMC_OE

GPMC_D[15:0]

Data Upper

GPMC_WAIT

16

15

GPMC_DIR

OUT

IN

OUT

IN

OUT

Figure 8-58. GPMC Non-Multiplexed NOR Flash - Asynchronous Read - 32-Bit Timing

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GPMC_FCLK

GPMC_CLK

22

21

2

GPMC_CS[x]

10

GPMC_A[10:1]

11

Add0

Add1

Add2

Add3

Add4

1

GPMC_BE1

11

GPMC_BE0_CLE

13

GPMC_ADV_ALE

19

14

GPMC_OE

GPMC_D[15:0]

D0

D1

D2

D3

GPMC_WAIT

16

15

GPMC_DIR

OUT

IN

OUT

Figure 8-59. GPMC Non-Multiplexed Only NOR Flash - Asynchronous Read - Page Mode 4x16-Bit Timing

220

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GPMC_FCLK

GPMC_CLK

2

GPMC_CS[x]

10

11

GPMC_A[10:1]

Valid Address

1

GPMC_BE1

GPMC_BE0_CLE

GPMC_ADV_ALE

11

1

4

13

28

26

GPMC_WE

30

GPMC_D[15:0]

Data OUT

GPMC_WAIT

GPMC_DIR

OUT

Figure 8-60. GPMC Non-Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

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GPMC_FCLK

GPMC_CLK

2

6

GPMC_CS[x]

10

Address (MSB)

1

GPMC_A[26:17]

11

GPMC_BE1

11

1

GPMC_BE0_CLE

13

4

GPMC_ADV_ALE

5

14

GPMC_OE

30

GPMC_A[16:1]

GPMC_D[15:0]

Address (LSB)

Data IN

GPMC_WAIT

16

15

GPMC_DIR

OUT

IN

OUT

Figure 8-61. GPMC Multiplexed NOR Flash - Asynchronous Read - Single Word Timing

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GPMC_FCLK

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GPMC_CLK

GPMC_CS[x]

2

10

11

Address (MSB)

1

GPMC_A[26:17]

GPMC_BE1

11

1

GPMC_BE0_CLE

13

4

GPMC_ADV_ALE

GPMC_WE

28

26

30

Valid Address (LSB)

29

GPMCA[16:1]

GPMC_D[15:0]

Data OUT

GPMC_WAIT

GPMC_DIR

OUT

Figure 8-62. GPMC Multiplexed NOR Flash - Asynchronous Write - Single Word Timing

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8.8.2.3 GPMC/NAND Flash Interface Asynchronous Mode Timing

Table 8-59. GPMC/NAND Flash Interface Asynchronous Mode Timing - Internal Parameters

NO.

1

MIN

MAX

6.5

UNIT

ns

Max. output data generation delay from internal functional clock

Max. input data capture delay by internal functional clock

Max. chip select generation delay from internal functional clock

Max. address latch enable generation delay from internal functional clock

Max. command latch enable generation delay from internal functional clock

Max. output enable generation delay from internal functional clock

Max. write enable generation delay from internal functional clock

Max. functional clock skew

2

4.0

ns

3

6.5

ns

4

6.5

ns

5

6.5

ns

6

6.5

ns

7

6.5

ns

8

100.0

ps

Table 8-60. Timing Requirements for GPMC/NAND Flash Interface

(see Figure 8-65)

NO.

MIN

MAX

J⁽¹⁾

UNIT

cycles

13 t_acc(DAT)

Data maximum access time (GPMC_FCLK cycles)

(1) J = AccessTime * (TimeParaGranularity + 1)

Table 8-61. Switching Characteristics Over Recommended Operating Conditions for GPMC/NAND Flash

Interface

(see Figure 8-63, Figure 8-64, Figure 8-65, Figure 8-66)

NO.

1

PARAMETER

MIN

MAX

A⁽¹⁾

UNIT

ns

t_w(nWEV)

Pulse duration, GPMC_WE valid time

2

t_d(nCSV-nWEV)

t_d(CLEH-nWEV)

t_d(nWEV-DV)

Delay time, GPMC_CS[x] valid to GPMC_WE valid

Delay time, GPMC_BE0_CLE high to GPMC_WE valid

Delay time, GPMC_D[15:0] valid to GPMC_WE valid

Delay time, GPMC_WE invalid to GPMC_D[15:0] invalid

Delay time, GPMC_WE invalid to GPMC_BE0_CLE invalid

Delay time, GPMC_WE invalid to GPMC_CS[x] invalid

Delay time, GPMC_ADV_ALE High to GPMC_WE valid

Delay time, GPMC_WE invalid to GPMC_ADV_ALE invalid

Cycle time, write cycle time

B - 0.2⁽²⁾

C - 0.2⁽³⁾

D - 0.2⁽⁴⁾

E - 0.2⁽⁵⁾

F - 0.2⁽⁶⁾

G - 0.2⁽⁷⁾

C - 0.2⁽³⁾

F - 0.2⁽⁶⁾

B + 2.0⁽²⁾

C + 2.0⁽³⁾

D + 2.0⁽⁴⁾

E + 2.0⁽⁵⁾

F + 2.0⁽⁶⁾

G + 2.0⁽⁷⁾

C + 2.0⁽³⁾

F + 2.0⁽⁶⁾

H⁽⁸⁾

3

4

5

t_d(nWEIV-DIV)

t_{d(nWEIV-CLEIV)}

t_{d(nWEIV-nCSIV)}

t_d(ALEH-nWEV)

t_{d(nWEIV-ALEIV)}

6

7

8

9

10 t_c(nWE)

11 t_d(nCSV-nOEV)

12 t_w(nOEV)

13 t_c(nOE)

Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid

Pulse duration, GPMC_OE_RE valid time

I - 0.2⁽⁹⁾

I + 2.0⁽⁹⁾

K⁽¹⁰⁾

Cycle time, read cycle time

L⁽¹¹⁾

(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) = B + nWE Min Delay - nCS Max Delay

B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(3) = C + nWE Min Delay - CLE Max Delay

C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK

(4) = D + nWE Min Delay - Data Max Delay

D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK

(5) =E + Data Min Delay - nWE Max Delay

E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK

(6) = F + CLE Min Delay - nWE Max Delay

F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )) * GPMC_FCLK

(7) =G + nCS Min Delay - nWE Max Delay

G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay )) * GPMC_FCLK

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(9) = I + nOE Min Delay - nCS Max Delay

I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK

(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

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Table 8-61. Switching Characteristics Over Recommended Operating Conditions for GPMC/NAND Flash

Interface (continued)

(see Figure 8-63, Figure 8-64, Figure 8-65, Figure 8-66)

NO.

PARAMETER

MIN

MAX

UNIT

14 t_{d(nOEIV-nCSIV)}

Delay time, GPMC_OE_RE invalid to GPMC_CS[x] invalid

M - 0.2⁽¹²⁾

M + 2.0⁽¹²⁾

ns

(12) =M + nCS Min Delay - nOE Max Delay

M = ((CSRdOffTime - OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ))* GPMC_FCLK

GPMC_FCLK

2

7

GPMC_CS[x]

3

6

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

1

GPMC_WE

4

5

GPMC_A[16:1]

GPMC_D[15:0]

Command

Figure 8-63. GPMC/NAND Flash - Command Latch Cycle Timing

GPMC_FCLK

GPMC_CS[x]

2

7

GPMC_BE0_CLE

8

9

GPMC_ADV_ALE

GPMC_OE

10

1

GPMC_WE

5

4

GPMC_A[16:1]

GPMC_D[15:0]

Address

Figure 8-64. GPMC/NAND Flash - Address Latch Cycle Timing

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GPMC_FCLK

13

11

16

GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

15

14

GPMC_A[16:1]

GPMC_D[15:0]

Data

GPMC_WAIT

Figure 8-65. GPMC/NAND Flash - Data Read Cycle Timing

GPMC_FCLK

2

7

GPMC_CS[x]

GPMC_BE0_CLE

GPMC_ADV_ALE

GPMC_OE

10

1

GPMC_WE

4

5

GPMC_A[16:1]

GPMC_D[15:0]

Data

Figure 8-66. GPMC/NAND Flash - Data Write Cycle Timing

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8.9 High-Definition Multimedia Interface (HDMI)

The device includes an HDMI 1.3a-compliant transmitter for digital video and audio data to display

devices. The HDMI interface consists of a digital HDMI transmitter core with TMDS encoder, a core

wrapper with interface logic and control registers, and a transmit PHY, with the following features:

•

Hot-plug detection

Consumer electronics control (CEC) messages

DVI 1.0 compliant (only RGB pixel format)

CEA 861-D and VESA DMT formats

Supports up to 165-MHz pixel clock:

–

1920 x 1080p @75 Hz with 8-bit/component color depth

1600 x 1200 @60 Hz with 8-bit/component color depth

•

Support for deep-color mode:

–

10-bit/component color depth up to 1080p @60 Hz (maximum pixel clock = 148.5 MHz)

12-bit/component color depth at 720p/1080i @60 Hz (maximum pixel clock = 123.75 MHz)

•

Uncompressed multichannel (up to eight channels) audio (L-PCM) support

Master I2C interface for display data channel (DDC) connection

TMDS clock to the HDMI-PHY is up to 185.625 MHz

Maximum supported pixel clock:

–

165 MHz for 8-bit color depth

148.5 MHz for 10-bit color depth

123.75 MHz for 12-bit color depth

•

Options available to support HDCP encryption engine for transmitting protected audio and video

(contact local TI sales representative for information).

For more details on the HDMI, see the HDMI chapter in the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

8.9.1 HDMI Interface Design Guidelines

This section provides PCB design and layout guidelines for the HDMI interface. The design rules constrain

PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system

design work has been done to ensure the HDMI interface requirements are met.

8.9.1.1 HDMI Interface Schematic

The HDMI bus is separated into three main sections:

1. Transition Minimized Differential Signaling (TMDS) high-speed digital video interface

2. Display Data Channel (I2C bus for configuration and status exchange between two devices)

3. Consumer Electronics Control (optional) for remote control of connected devices.

The DDC and CEC are low-speed interfaces, so nothing special is required for PCB layout of these

signals. Their connection is shown in Figure 8-67.

The TMDS channels are high-speed differential pairs and, therefore, require the most care in layout.

Specifications for TMDS layout are below.

Figure 8-67 shows the HDMI interface schematic. The specific pin numbers can be obtained from

Table 3-7, HDMI Terminal Functions.

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Device

HDMI Connector

TD0

Shld

HDMI_TMDSDP0

HDMI_TMDSDN0

TD0+

TD0-

TD1

Shld

HDMI_TMDSDP1

HDMI_TMDSDN1

TD1+

TD1-

TPD12S521

or other

ESD Protection

w/I2C-Level

Translation

TD2

Shld

HDMI_TMDSDP2

HDMI_TMDSDN2

TD2+

TD2-

HDMI_TMDSCLKP

HDMI_TMDSCLKN

TCLK

Shld

TCLK+

HDMI_CEC

CEC

DDC

Gnd

DVDD_3P3

Rpullup^(A)

HDMI_SDA

HDMI_SCL

SDA

SCL

A. 5K-10K Ω pullup resistors are required if not integrated in the ESD protection chip.

Figure 8-67. HDMI Interface High-Level Schematic

8.9.1.2 TMDS Routing

The TMDS signals are high-speed differential pairs. Care must be taken in the PCB layout of these signals

to ensure good signal integrity.

The TMDS differential signal traces must be routed to achieve 100 Ω (±10%) differential impedance and

60 Ω (±10%) single-ended impedance. Single-ended impedance control is required because differential

signals are extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes

important.

These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric

material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as

close to 60 Ω impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure

this impedance is met.

In general, closely coupled differential signal traces are not an advantage on PCBs. When differential

signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing

variations affect impedance dramatically, so tight impedance control can be more problematic to maintain

in production.

Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing

make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it

is easier to maintain an accurate impedance over the length of the signal. The wider traces also show

reduced skin effect and, therefore, often result in better signal integrity.

Table 8-62 shows the routing specifications for the TMDS signals.

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Table 8-62. TMDS Routing Specifications

PARAMETER

MIN

TYP

MAX

7000

0

UNIT

Mils

Stubs

Ω

MPU-to-HDMI header trace length

Number of stubs allowed on TMDS traces

TX/RX pair differential impedance

90

54

100

60

110

66

TX/RX single ended impedance

Ω

Number of vias on each TMDS trace

TMDS differential pair to any other trace spacing

2

Vias⁽¹⁾

2*DS⁽²⁾

(1) Vias must be used in pairs with their distance minimized.

(2) DS = differential spacing of the HDMI traces.

8.9.1.3 DDC Signals

As shown in Figure 8-67, the DDC connects just like a standard I2C bus. As such, resistor pullups must

be used to pull up the open drain buffer signals unless they are integrated into the ESD protection chip

used. If used, these pullup resistors should be connected to a 3.3-V supply.

8.9.1.4 HDMI ESD Protection Device (Required)

Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built

into the processor's outputs. Therefore, this HDMI interface requires the use of an ESD protection chip to

provide adequate ESD protection and to translate I2C voltage levels from the 3.3 V supplied by the device

to the 5 volts required by the HDMI specification.

When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to

minimize signal degradation. In no case should the ESD protection circuit capacitance be more than 5 pF.

TI manufactures devices that provide ESD protection for HDMI signals such as the TPD12S521. For more

information see the www.ti.com website.

8.9.1.5 PCB Stackup Specifications

Table 8-63 shows the stackup and feature sizes required for HDMI.

Table 8-63. HDMI PCB Stackup Specifications

PARAMETER

MIN

TYP

6

MAX

UNIT

Layers

Cuts

PCB routing/plane layers

Signal routing layers

4

2

-

3

Number of ground plane cuts allowed within HDMI routing region

Number of layers between HDMI routing region and reference ground plane

PCB trace width

-

0

-

Layers

Mils

-

4

PCB BGA escape via pad size

-

20

10

0.4

-

Mils

PCB BGA escape via hole size

MPU device BGA pad size⁽¹⁾⁽²⁾

-

Mils

mm

(1) Non-solder mask defined pad.

(2) Per IPC-7351A BGA pad size guideline.

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8.9.1.6 Grounding

Each TMDS channel has its own shield pin which should be grounded to provide a return current path for

the TMDS signal.

8.9.2 HDMI Peripheral Register Descriptions

Table 8-64. HDMI Wrapper Registers

HEX ADDRESS

0x46C0 0000

0x46C0 0010

0x46C0 0024

0x46C0 0028

0x46C0 002C

0x46C0 0030

0x46C0 0034

0x46C0 0050

0x46C0 0070

0x46C0 0080

0x46C0 0084

0x46C0 0088

0x46C0 008C

ACRONYM

REGISTER NAME

HDMI_WP_REVISION

HDMI_WP_SYSCONFIG

IP Revision Identifier

Clock Management Configuration

HDMI_WP_IRQSTATUS_RAW Raw Interrupt Status

HDMI_WP_IRQSTATUS

Interrupt Status

Interrupt Enable

HDMI_WP_IRQENABLE_SET

HDMI_WP_IRQENABLE_CLR Interrupt Disable

HDMI_WP_IRQWAKEEN

HDMI_WP_VIDEO_CFG

HDMI_WP_CLK

IRQ Wakeup

Configuration of HDMI Wrapper Video

Configuration of Clocks

Audio Configuration in FIFO

Audio Configuration of DMA

Audio FIFO Control

HDMI_WP_AUDIO_CFG

HDMI_WP_AUDIO_CFG2

HDMI_WP_AUDIO_CTRL

HDMI_WP_AUDIO_DATA

TX Data of FIFO

Table 8-65. HDMI Core System Registers

HEX ADDRESS

ACRONYM

VND_IDL

REGISTER NAME

Vendor ID

0x46C0 0400

0x46C0 0404

0x46C0 0408

0x46C0 040C

0x46C0 0410

0x46C0 0414

0x46C0 0420

0x46C0 0424

0x46C0 0428

0x46C0 0434

0x46C0 043C

VND_IDH

Vendor ID

DEV_IDL

Device ID

DEV_IDH

Device ID

DEV_REV

SRST

Device Revision

Software Reset

System Control 1

System Status

Legacy

SYS_CTRL1

SYS_STAT

SYS_CTRL3

DCTL

Data Control

HDCP Control

HDCP BKSV

HDCP_CTRL

BKSV__0 - BKSV__4

0x46C0 0440 - 0x46C0 0450

(0x4 byte increments)

0x46C0 0454 - 0x46C0 0470

(0x4 byte increments)

AN__0 - AN__7

HDCP AN

0x46C0 0474 - 0x46C0 0484

(0x4 byte increments)

AKSV__0 - AKSV__4

HDCP AKSV

0x46C0 0488

0x46C0 048C

0x46C0 0490

0x46C0 0494

0x46C0 0498

0x46C0 049C

0x46C0 04A0

0x46C0 04A4

0x46C0 04A8

RI1

RI2

HDCP Ri

RI_128_COMP

I_CNT

HDCP Ri 128 Compare

HDCP I Counter

Ri Status

RI_STAT

RI_CMD

RI_START

RI_RX_L

RI_RX_H

Ri Command

Ri Line Start

Ri From RX

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Table 8-65. HDMI Core System Registers (continued)

HEX ADDRESS

0x46C0 04AC

0x46C0 04C8

0x46C0 04CC

0x46C0 04D0

0x46C0 04D8

0x46C0 04DC

0x46C0 04E0

0x46C0 04E4

0x46C0 04E8

0x46C0 04EC

0x46C0 04F0

0x46C0 04F4

0x46C0 04F8

0x46C0 04FC

0x46C0 0500

0x46C0 0504

0x46C0 0508

0x46C0 050C

0x46C0 0510

0x46C0 0514

0x46C0 0518

0x46C0 051C

0x46C0 0520

0x46C0 0524

0x46C0 0528

0x46C0 052C

0x46C0 0530

0x46C0 0534

0x46C0 0538

0x46C0 053C

0x46C0 0540

0x46C0 0544

0x46C0 0548

0x46C0 054C

0x46C0 0550

0x46C0 0554

0x46C0 0558

0x46C0 055C

0x46C0 0560

0x46C0 0564

0x46C0 0568

0x46C0 056C

0x46C0 0570

0x46C0 0574

0x46C0 0578

0x46C0 057C

ACRONYM

RI_DEBUG

REGISTER NAME

Ri Debug

DE_DLY

VIDEO DE Delay

DE_DLY

VIDEO DE Delay

DE_CTRL

VIDEO DE Control

DE_TOP

VIDEO DE Top

DE_CNTL

VIDEO DE Count

DE_CNTH

VIDEO DE Count

DE_LINL

VIDEO DE Line

DE_LINH_1

VIDEO DE Line

HRES_L

Video H Resolution

HRES_H

Video H Resolution

VRES_L

Video V Resolution

VRES_H

Video V Resolution

IADJUST

Video Interlace Adjustment

Video SYNC Polarity Detection

Video Hbit to HSYNC

POL_DETECT

HBIT_2HSYNC1

HBIT_2HSYNC2

FLD2_HS_OFSTL

FLD2_HS_OFSTH

HWIDTH1

Video Hbit to HSYNC

Video Field2 HSYNC Offset

Video HSYNC Length

HWIDTH2

Video HSYNC Length

VBIT_TO_VSYNC

VWIDTH

Video Vbit to VSYNC

Video VSYNC Length

VID_CTRL

Video Control

VID_ACEN

Video Action Enable

VID_MODE

Video Mode1

VID_BLANK1

VID_BLANK2

VID_BLANK3

DC_HEADER

VID_DITHER

RGB2XVYCC_CT

R2Y_COEFF_LOW

R2Y_COEFF_UP

G2Y_COEFF_LOW

G2Y_COEFF_UP

B2Y_COEFF_LOW

B2Y_COEFF_UP

R2CB_COEFF_LOW

R2CB_COEFF_UP

G2CB_COEFF_LOW

G2CB_COEFF_UP

B2CB_COEFF_LOW

B2CB_COEFF_UP

R2CR_COEFF_LOW

R2CR_COEFF_UP

G2CR_COEFF_LOW

Video Blanking

Deep Color Header

Video Mode2

RGB_2_xvYCC control

RGB_2_xvYCC Conversion R_2_Y

RGB_2_xvYCC Conversion G_2_Y

RGB_2_xvYCC Conversion B_2_Y

RGB_2_xvYCC Conversion R_2_Cb

RGB_2_xvYCC Conversion G_2_Cb

RGB_2_xvYCC Conversion B_2_Cb

RGB_2_xvYCC Conversion R_2_Cr

RGB_2_xvYCC Conversion G_2_Cr

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Table 8-65. HDMI Core System Registers (continued)

HEX ADDRESS

0x46C0 0580

0x46C0 0584

0x46C0 0588

0x46C0 058C

0x46C0 0590

0x46C0 0594

0x46C0 0598

0x46C0 059C

0x46C0 05A0

0x46C0 05C0

0x46C0 05C4

0x46C0 05C8

0x46C0 05CC

0x46C0 05D0

0x46C0 05D4

0x46C0 05D8

0x46C0 05DC

0x46C0 05E0

0x46C0 05E4

0x46C0 0640

0x46C0 0644

0x46C0 0648

0x46C0 064C

0x46C0 0650

0x46C0 0654

0x46C0 0658

0x46C0 065C

0x46C0 0660

0x46C0 0664

0x46C0 0668

0x46C0 066C

0x46C0 0670

0x46C0 0674

0x46C0 0678

0x46C0 067C

0x46C0 0680

0x46C0 0684

0x46C0 0688

0x46C0 068C

0x46C0 07B0

0x46C0 07B4

0x46C0 07B8

0x46C0 07BC

0x46C0 07C0

0x46C0 07C4

0x46C0 07C8

0x46C0 07CC

ACRONYM

G2CR_COEFF_UP

B2CR_COEFF_LOW

B2CR_COEFF_UP

RGB_OFFSET_LOW

RGB_OFFSET_UP

Y_OFFSET_LOW

Y_OFFSET_UP

CBCR_OFFSET_LOW

CBCR_OFFSET_UP

INTR_STATE

REGISTER NAME

RGB_2_xvYCC Conversion G_2_Cr

RGB_2_xvYCC Conversion B_2_Cr

RGB_2_xvYCC RGB Input Offset

RGB_2_xvYCC Conversion Y Output Offset

RGB_2_xvYCC Conversion CbCr Output Offset

Interrupt State

INTR1

Interrupt Source

INTR2

Interrupt Source

INTR3

Interrupt Source

INTR4

Interrupt Source

INT_UNMASK1

INT_UNMASK2

INT_UNMASK3

INT_UNMASK4

INT_CTRL

Interrupt Unmask

Interrupt Control

XVYCC2RGB_CTL

Y2R_COEFF_LOW

Y2R_COEFF_UP

CR2R_COEFF_LOW

CR2R_COEFF_UP

CB2B_COEFF_LOW

CB2B_COEFF_UP

CR2G_COEFF_LOW

CR2G_COEFF_UP

CB2G_COEFF_LOW

CB2G_COEFF_UP

YOFFSET1_LOW

YOFFSET1_UP

OFFSET1_LOW

OFFSET1_MID

OFFSET1_UP

xvYCC_2_RGB Control

xvYCC_2_RGB Conversion Y_2_R

xvYCC_2_RGB Conversion Cr_2_R

xvYCC_2_RGB Conversion Cb_2_B

xvYCC_2_RGB Conversion Cr_2_G

xvYCC_2_RGB Conversion Cb_2_G

xvYCC_2_RGB Conversion Y Offset

xvYCC_2_RGB Conversion Offset1

xvYCC_2_RGB Conversion Offset2

xvYCC_2_RGB Conversion DC Level

DDC I2C Manual

OFFSET2_LOW

OFFSET2_UP

DCLEVEL_LOW

DCLEVEL_UP

DDC_MAN

DDC_ADDR

DDC I2C Target Slave Address

DDC I2C Target Segment Address

DDC I2C Target Offset Address

DDC I2C Data Count

DDC_SEGM

DDC_OFFSET

DDC_COUNT1

DDC_COUNT2

DDC_STATUS

DDC_CMD

DDC I2C Data Count

DDC I2C Status

DDC I2C Command

232

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Table 8-65. HDMI Core System Registers (continued)

HEX ADDRESS

0x46C0 07D0

0x46C0 07D4

0x46C0 07E4

0x46C0 07E8

ACRONYM

DDC_DATA

DDC_FIFOCNT

EPST

REGISTER NAME

DDC I2C Data

DDC I2C FIFO Count

ROM Status

EPCM

ROM Command

Table 8-66. HDMI IP Core Gamut Registers

HEX ADDRESS

0x46C0 0800

0x46C0 0804

0x46C0 0808

ACRONYM

REGISTER NAME

Gamut Metadata

GAMUT_HEADER1

GAMUT_HEADER2

GAMUT_HEADER3

0x46C0 080C - 0x46C0 0878

(0x4 byte increments)

GAMUT_DBYTE__0 -

GAMUT_DBYTE__27

Table 8-67. HDMI IP Core Audio Video Registers

HEX ADDRESS

0x46C0 0904

0x46C0 0908

0x46C0 090C

0x46C0 0910

0x46C0 0914

0x46C0 0918

0x46C0 091C

0x46C0 0920

0x46C0 0924

0x46C0 0928

0x46C0 092C

0x46C0 0950

0x46C0 0954

0x46C0 0960

0x46C0 0964

0x46C0 096C

0x46C0 0970

0x46C0 0974

0x46C0 0978

0x46C0 097C

0x46C0 0980

0x46C0 0984

0x46C0 0988

0x46C0 098C

0x46C0 0990

0x46C0 09BC

0x46C0 09C0

0x46C0 09CC

0x46C0 09D0

0x46C0 09D4

0x46C0 09F0

0x46C0 09F4

ACRONYM

ACR_CTRL

REGISTER NAME

ACR Control

FREQ_SVAL

N_SVAL1

ACR Audio Frequency

ACR N Software Value

ACR CTS Software Value

ACR CTS Hardware Value

Audio In Mode

N_SVAL2

N_SVAL3

CTS_SVAL1

CTS_SVAL2

CTS_SVAL3

CTS_HVAL1

CTS_HVAL2

CTS_HVAL3

AUD_MODE

SPDIF_CTRL

HW_SPDIF_FS

SWAP_I2S

Audio In S/PDIF Control

Audio In S/PDIF Extracted Fs and Length

Audio In I2S Channel Swap

Audio Error Threshold

SPDIF_ERTH

I2S_IN_MAP

I2S_IN_CTRL

I2S_CHST0

Audio In I2S Data In Map

Audio In I2S Control

Audio In I2S Channel Status

Audio Sample Rate Conversion

Audio I2S Input Length

HDMI Control

I2S_CHST1

I2S_CHST2

I2S_CHST4

I2S_CHST5

ASRC

I2S_IN_LEN

HDMI_CTRL

AUDO_TXSTAT

AUD_PAR_BUSCLK_1

AUD_PAR_BUSCLK_2

AUD_PAR_BUSCLK_3

TEST_TXCTRL

DPD

Audio Path Status

Audio Input Data Rate Adjustment

Test Control

Diagnostic Power Down

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Table 8-67. HDMI IP Core Audio Video Registers (continued)

HEX ADDRESS

0x46C0 09F8

0x46C0 09FC

0x46C0 0A00

0x46C0 0A04

0x46C0 0A08

0x46C0 0A0C

ACRONYM

PB_CTRL1

PB_CTRL2

AVI_TYPE

AVI_VERS

AVI_LEN

REGISTER NAME

Packet Buffer Control 1

Packet Buffer Control 2

Packet

AVI_CHSUM

Packet

0x46C0 0A10 - 0x46C0 0A48

(0x4 byte increments)

AVI_DBYTE__0 -

AVI_DBYTE__14

Packet

0x46C0 0A80

0x46C0 0A84

0x46C0 0A88

0x46C0 0A8C

SPD_TYPE

SPD_VERS

SPD_LEN

SPD InfoFrame

SPD_CHSUM

0x46C0 0A90 - 0x46C0 0AF8

(0x4 byte increments)

SPD_DBYTE__0 -

SPD_DBYTE__26

0x46C0 0B00

0x46C0 0B04

0x46C0 0B08

0x46C0 0B0C

AUDIO_TYPE

AUDIO_VERS

AUDIO_LEN

Audio InfoFrame

AUDIO_CHSUM

0x46C0 0B10 - 0x46C0 0B34

(0x4 byte increments)

AUDIO_DBYTE__0 -

AUDIO_DBYTE__9

0x46C0 0B80

0x46C0 0B84

0x46C0 0B88

0x46C0 0B8C

MPEG_TYPE

MPEG_VERS

MPEG_LEN

MPEG InfoFrame

MPEG_CHSUM

0x46C0 0B90 - 0x46C0 0BF8

(0x4 byte increments)

MPEG_DBYTE__0 -

MPEG_DBYTE__26

0x46C0 0C00 - 0x46C0 0C78

(0x4 byte increments)

GEN_DBYTE__0 -

GEN_DBYTE__30

Generic Packet

0x46C0 0C7C

CP_BYTE1

General Control Packet

Generic Packet 2

0x46C0 0C80 - 0x46C0 0CF8

(0x4 byte increments)

GEN2_DBYTE__0 -

GEN2_DBYTE__30

0x46C0 0CFC

CEC_ADDR_ID

CEC Slave ID

Table 8-68. HDMI IP Core CEC Registers

HEX ADDRESS

0x46C0 0D00

0x46C0 0D04

0x46C0 0D08

0x46C0 0D0C

0x46C0 0D10

0x46C0 0D14

0x46C0 0D18

0x46C0 0D1C

0x46C0 0D20

0x46C0 0D24

0x46C0 0D38

0x46C0 0D3C

ACRONYM

CEC_DEV_ID

CEC_SPEC

REGISTER NAME

CEC Device ID

CEC Specification

CEC Specification Suffix

CEC Firmware Revision

CEC Debug 0

CEC_SUFF

CEC_FW

CEC_DBG_0

CEC_DBG_1

CEC_DBG_2

CEC_DBG_3

CEC_TX_INIT

CEC_TX_DEST

CEC_SETUP

CEC_TX_COMMAND

CEC Debug 1

CEC Debug 2

CEC Debug 3

CEC Tx Initialization

CEC Tx Destination

CEC Set Up

CEC Tx Command

CEC Tx Operand

0x46C0 0D40 - 0x46C0 0D78

(0x4 byte increments)

CEC_TX_OPERAND__0 -

CEC_TX_OPERAND__14

234

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Table 8-68. HDMI IP Core CEC Registers (continued)

HEX ADDRESS

0x46C0 0D7C

0x46C0 0D88

0x46C0 0D8C

0x46C0 0D90

0x46C0 0D94

0x46C0 0D98

0x46C0 0D9C

0x46C0 0DB0

0x46C0 0DB4

0x46C0 0DB8

0x46C0 0DBC

ACRONYM

REGISTER NAME

CEC_TRANSMIT_DATA

CEC_CA_7_0

CEC Transmit Data

CEC Capture ID0

CEC_CA_15_8

CEC Capture ID0

CEC_INT_ENABLE_0

CEC_INT_ENABLE_1

CEC_INT_STATUS_0

CEC_INT_STATUS_1

CEC_RX_CONTROL

CEC_RX_COUNT

CEC Interrupt Enable 0

CEC Interrupt Enable 1

CEC Interrupt Status 0

CEC Interrupt Status 1

CEC RX Control

CEC Rx Count

CEC_RX_CMD_HEADER

CEC_RX_COMMAND

CEC Rx Command Header

CEC Rx Command

0x46C0 0DC0 - 0x46C0 0DF8

(0x4 byte increments)

CEC_RX_OPERAND__0 - CEC Rx Operand

CEC_RX_OPERAND__14

Table 8-69. HDMI PHY Registers

HEX ADDRESS

0x4812 2004

0x4812 2008

0x4812 200C

0x4812 2020

ACRONYM

TMDS_CNTL2

TMDS_CNTL3

BIST_CNTL

REGISTER NAME

TMDS Control

BIST Control

TMDS_CNTL9

TMDS Control

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8.10 High-Definition Video Processing Subsystem (HDVPSS)

The device High-Definition Video Processing Subsystem (HDVPSS) provides a video input interface for

external imaging peripherals (i.e., image sensors, video decoders, etc.) and a video output interface for

display devices, such as analog SDTV displays, analog/digital HDTV displays, digital LCD panels, etc. It

includes HD and SD video encoders, and an HDMI transmitter interface.

The device HDVPSS features include:

•

High quality (HD) and medium quality (SD) display processing pipelines with de-interlacing, scaling,

noise reduction, alpha blending, chroma keying, color space conversion, flicker filtering, and pixel

format conversion.

•

HD/SD compositor features for PIP support and video mosaic support.

Format conversions (up to 1080p 60 Hz) include scan format conversion, scan rate conversion,

aspect-ratio conversion, and frame size conversion.

•

Supports additional video processing capabilities by using the subsystem's memory-to-memory feature.

Two parallel video processing pipelines support HD (up to 1080p60) and SD (NTSC/PAL)

simultaneous outputs.

–

HD analog component output with OSD and embedded timing codes (BT.1120)

3-channel HD-DAC with 12-bit resolution.

SD analog output with OSD with embedded timing codes (BT.656)

•

–

•

Simultaneous component, S-video and composite

4-channel SD-DAC with 10-bit resolution

Options available to support MacroVision and CGMS-A (contact local TI Sales rep for

information).

–

Digital HDMI 1.3a compliant transmitter (for details, see Section 8.9, High-Definition Multimedia

Interface (HDMI)).

•

Up to two (one 16/24/30-bit and one 16-bit) digital video outputs (up to 165 MHz).

–

VOUT[0] can output up to 30-bit video and supports RGB, YUV444, Y/C and BT.656 modes.

VOUT[1] can output up to 16-bit video and supports Y/C and BT.656 modes.

Two (one 16/24-bit and one 16-bit) independently configurable external video input capture ports (up to

165 MHz).

–

16/24-bitHD digital video input or dual clock independent 8-bit SD inputs on each capture port.

•

VIN[0] can accept single-channel 16/24-bit (YCbCr/RGB) video or dual-channel 8-bit (YCbCr)

video.

•

VIN[1] can accept single-channel 16-bit (YCbCr) video or dual-channel 8-bit (YCbCr) video.

–

Embedded sync and external sync modes are supported for all input configurations.

De-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams, effectively supporting up

to 16 simultaneous SD inputs with a glueless interface to an external multiplexer such as the

TVP5158.

–

Additional features include: programmable color space conversion, scaler and chroma

downsampler, ancillary VANC/VBI data capture (decoded by software), noise reduction.

•

Availability of a combination of these digital video input/output port configurations, control signals for

multiple 8-bit ports, as well as separate synchronization signals is limited by the device pin multiplexing

(for details, see Section 4.4). The following video inputs/outputs are not multiplexed and are always

available:

–

SD DAC composite, S-video, component out

HD DAC component out

HDMI output (same as VOUT[1])

16-bit VOUT[0] (embedded sync)

Single 16-bit/dual 8-bit VIN[0] (embedded sync).

•

Graphics features:

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–

Three independently-generated region-based graphics layers.

Each supports full-screen resolution graphics in HD, SD or both.

Up/down scaler optimized for graphics, region based.

Global and pixel-level alpha blending supported.

For more detailed information on specific features and registers, see the HDVPSS chapter in the AM38x

Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.10.1 HDVPSS Peripheral Register Descriptions

Table 8-70. HDVPSS Submodule Register Address Summary

HEX ADDRESS

0x4810 0000

0x4810 0100

0x4810 0200

0x4810 0300

0x4810 0400

0x4810 0500

0x4810 0600

0x4810 0700

0x4810 0800

0x4810 0900

0x4810 0A00

0x4810 0B00

0x4810 0C00

0x4810 0D00

0x4810 0E00

0x4810 0F00

0x4810 1000

0x4810 5000

0x4810 5100

0x4810 5200

0x4810 5300

0x4810 5400

0x4810 5480

0x4810 5500

0x4810 5700

0x4810 5800

0x4810 5900

0x4810 5A00

0x4810 5C00

0x4810 5D00

0x4810 5E00

0x4810 6000

0x4810 8000

0x4810 A000

0x4810 C000

0x4810 C200

0x4810 C400

SUBMODULE NAME

INTC

SIZE

256 Bytes

16384 Bytes

256 Bytes

128 Bytes

512 Bytes

256 Bytes

512 Bytes

256 Bytes

512 Bytes

8192 Bytes

512 Bytes

256 Bytes

CLKC

Reserved

CHR_US_HQ

DRN_HQ

DEI_HQ

SC_1 (HQ)

CHR_US_LC

DRN_LC

Reserved

DEI

SC

CSC_Y2R_1

CSC_Y2R_2

VCOMP

EDE

CPROC

SC_WRBK

CIG

COMP

CSC_R2Y

CHR_US_IND1

CHR_US_IND2

VIN0_PARSER

VIN0_CSC_R2Y

VIN0_SC

Reserved

VIN1_PARSER

VIN1_CSC_R2Y

VIN1_SC

SD_VENC

HD_VENC_D_VOUT1

HD_VENC_A

HD_VENC_D_VOUT0

NTSC_RF

NF

Reserved

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Table 8-70. HDVPSS Submodule Register Address Summary (continued)

HEX ADDRESS

0x4810 C500

0x4810 C600

0x4810 C700

0x4810 C800

0x4810 C900

0x4810 CA00

0x4810 CB00

0x4810 CC00

0x4810 CD00

0x4810 D000

SUBMODULE NAME

COMPRESS_TOP_HQ

COMPRESS_BOT_HQ

DECOMPRESS1_HQ

DECOMPRESS2_HQ

DECOMPRESS3_HQ

COMPRESS_LC

SIZE

256 Bytes

768 Bytes

4096 Bytes

DECOMPRESS1_LC

DECOMPRESS2_LC

Reserved

VPDMA

For detailed register information, see the HDVPSS chapter in the AM38x Sitara ARM Microprocessors

(MPUs) Technical Reference Manual (literature number SPRUGX7).

238

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8.10.2 HDVPSS Electrical Data/Timing

Table 8-71. Timing Requirements for HDVPSS Input

(see Figure 8-68 and Figure 8-69)

NO.

MIN

MAX UNIT

VIN[x]A_CLK

1

2

3

7

t_c(CLK)

Cycle time, VIN[x]A_CLK

6.06⁽¹⁾

2.73

ns

t_w(CLKH)

Pulse duration, VIN[x]A_CLK high (45% of t_c)

Pulse duration, VIN[x]A_CLK low (45% of t_c)

Transition time, VIN[x]A_CLK (10%-90%)

t_w(CLKH)

2.73

t_t(CLK)

2.64

ns

t_su(DE-CLK)

t_{su(VSYNC-CLK)}

t_su(FLD-CLK)

t_{su(HSYNC-CLK)}

t_su(D-CLK)

Input setup time, control valid to VIN[x]A_CLK high

Input setup time, data valid to VIN[x]A_CLK high

Input hold time, control valid from VIN[x]A_CLK high

3.11

4

5

ns

t_h(CLK-DE)

t_h(CLK-VSYNC)

t_h(CLK-FLD)

t_h(CLK-HSYNC)

t_h(CLK-D)

-0.05

ns

Input hold time, data valid from VIN[x]A_CLK high

VIN[x]B_CLK

1

2

3

7

t_c(CLK)

Cycle time, VIN[x]B_CLK

6.06⁽¹⁾

2.73

ns

t_w(CLKH)

Pulse duration, VIN[x]B_CLK high (45% of t_c)

Pulse duration, VIN[x]B_CLK low (45% of t_c)

Transition time, VIN[x]B_CLK (10%-90%)

t_w(CLKH)

2.73

t_t(CLK)

2.64

t_su(DE-CLK)

t_{su(VSYNC-CLK)}

t_su(FLD-CLK)

t_{su(HSYNC-CLK)}

t_su(D-CLK)

Input setup time, control valid to VIN[x]B_CLK high

Input setup time, data valid to VIN[x]B_CLK high

Input hold time, control valid from VIN[x]B_CLK high

Input hold time, data valid from VIN[x]B_CLK high

3.11

4

5

ns

t_h(CLK-DE)

t_h(CLK-VSYNC)

t_h(CLK-FLD)

t_h(CLK-HSYNC)

t_h(CLK-D)

-0.05

(1) For maximum frequency of 165 MHz.

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Table 8-72. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output

(see Figure 8-68 and Figure 8-70)

NO.

1

PARAMETER

MIN

6.06⁽¹⁾

2.73

MAX UNIT

t_c(CLK)

Cycle time, VOUT[x]_CLK

ns

2

t_w(CLKH)

Pulse duration, VOUT[x]_CLK high (45% of t_c)

Pulse duration, VOUT[x]_CLK low (45% of t_c)

Transition time, VOUT[x]_CLK (10%-90%)

3

t_w(CLKL)

2.73

7

t_t(CLK)

2.64

ns

t_d(CLK-AVID)

t_d(CLK-FLD)

t_d(CLK-VSYNC)

t_d(CLK-HSYNC)

t_d(CLK-RCR)

t_d(CLK-GYYC)

t_d(CLK-BCBC)

t_d(CLK-YYC)

t_d(CLK-C)

Delay time, VOUT[x]_CLK to control valid

1.64⁽²⁾

4.18⁽³⁾

ns

6

Delay time, VOUT[0]_CLK to data valid

Delay time, VOUT[1]_CLK to data valid

1.64⁽²⁾

4.18⁽³⁾

ns

(1) For maximum frequency of 165 MHz.

(2) Min Delay Time = T_c* 0.27, where T_cis the clock cycle time. Note: Must match board trace length delay for clock and data to within

0.34 ns.

(3) Max Delay Time = T_c* 0.69, where T_cis the clock cycle time. Note:Must match board trace length delay for clock and data to within

0.34 ns.

3

2

1

VIN[x]A_CLK/

VIN[x]B_CLK/

VOUT[x]_CLK

7

Figure 8-68. HDVPSS Clock Timing

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VIN[x]A_CLK/

VIN[x]B_CLK

(positive-edge clocking)

VIN[x]A_CLK/

VIN[x]B_CLK

(negative-edge clocking)

5

4

VIN[x]A/

VIN[x]B

Figure 8-69. HDVPSS Input Timing

VOUT[x]_CLK

VOUT[x]

6

Figure 8-70. HDVPSS Output Timing

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8.10.3 Video DAC Guidelines and Electrical Data/Timing

The device's analog video DAC outputs are designed to drive a 37.5-Ω load. Figure 8-71 describes a

typical circuit that permits connecting the analog video output from the device to standard 75-Ω impedance

video systems. The device requires the use of a buffer to drive the actual video outputs, so one solution is

to use a video amplifier with integrated buffer and internal filter, such as the Texas Instruments THS7360,

which provides a complete solution for the typical output circuit shown in Figure 8-71.

75 W

Amplifier

Reconstruction

Filter

IOUTx

SD: 5.6 V/V

HD: 4.5 V/V

SD:

9.5 MHZ

18 MHZ

36 MHz

ED:

HD:

R_LOAD

1080p: 72 MHz

Figure 8-71. Typical Output Circuits for Analog Video from DACs

During board design, the onboard traces and parasitics must be matched for the channel. The video DAC

output pin (IOUTx) is a very high-frequency analog signal and must be routed with extreme care. As a

result, the path of this signal must be as short as possible, and as isolated as possible from other

interfering signals. The load resistor and amplifier/buffer should be placed close together and as close as

possible to the device pins. Other layout guidelines include:

•

Take special care to bypass the DAC power supply pin with a capacitor.

Place the 75-Ω resistor as close as possible (<0.5") to the amplifier/buffer (THS7360) output pin.

To maintain a high quality video signal, 75-Ω (±10%) characteristic impedance traces should be used

after the 75-Ω series resistor.

•

Minimize input trace lengths to the device to reduce parasitic capacitance.

Include solid ground return paths.

Match trace lengths as close as possible within a video format group (i.e., Y, Pb, and Pr for component

output, and Y and C for s-video output should match each other).

For additional video DAC design guidelines, see the HDVPSS chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

Table 8-73. DAC Specifications

PARAMETER

CONDITIONS

HD DACs

MIN

TYP

12

MAX

UNIT

Bits

Resolution

SD DACs

10

Bits

DC Accuracy - HD DACs

Integral Non-Linearity (INL), best fit

HD DACs

SD DACs

HD DACs

SD DACs

1.5

1.0

0.5

LSB

Differential Non-Linearity (DNL)

Analog Output

Output Resistor (R_LOAD

)

HD and SD DACs

-1%

0

37.5

13.3

+1%

Vref

Ω

Full-Scale Output Current (IFS)

HD and SD DACs

R_LOAD

mA

Output Compliance Range

HD and SD DACs

IFS = 13.3 mA,

R_LOAD= 37.5 Ω

V

Zero Scale Offset Error (ZSET)

Gain Error

HD and SD DACs

0.5

LSB

%

-10

10

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Table 8-73. DAC Specifications (continued)

PARAMETER

Channel matching

Recommended External Amplification

CONDITIONS

HD and SD DACs

HD DACs

MIN

TYP

MAX

UNIT

%

2

4.5

5.6

V/V

SD DACs

Reference

Reference Voltage Range (VREF)

Input with External

Reference

-5%

-1%

0.5

1.2

+5%

+1%

V

Full-Scale Current Adjust Resistors

Dynamic Specifications

R_{BIAS_HD}and R_{BIAS_SD}

kΩ

Output Update Rate (FCLK)

HD DACs at 1080i60

HD DACs at 1080p60

SD DACs

74.25

148.5

27

MHz

dB

54

Signal Bandwidth

HD DACs at 1080i60

HD DACs at 1080p60

SD DACs

30

60

6

Spurious - Free Dynamic Range (SFDR)

HD DACs at 1080i60

FCLK = 74.25 MHz,

FOUT = 30 MHz

60

HD DACs at 1080p60

FCLK = 148.5 MHz,

FOUT = 60 MHz

60

dB

SD DACs

FCLK = 27 MHz / 54 MHz,

FOUT = 6 MHz

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8.11 Inter-Integrated Circuit (I2C)

The device includes two inter-integrated circuit (I2C) modules which provide an interface to other devices

compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External

components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through

the I2C module. The I2C port does not support CBUS compatible devices.

The I2C port supports the following features:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)

Noise filter to remove noise 50 ns or less

Seven- and ten-bit device addressing modes

Multimaster transmitter/slave receiver mode

Multimaster receiver/slave transmitter mode

Combined master transmit/receive and receive/transmit modes

Two DMA channels, one interrupt line

Built-in FIFO (32 byte) for buffered read or write.

For more detailed information on the I2C peripheral, see the I2C chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.11.1 I2C Peripheral Register Descriptions

Table 8-74. I2C Registers

I2C0 HEX ADDRESS

0x4802 8000

0x4802 8004

0x4802 8010

0x4802 8020

0x4802 8024

0x4802 8028

0x4802 802C

0x4802 8030

0x4802 8034

0x4802 8038

0x4802 803C

0x4802 8040

0x4802 8044

0x4802 8048

0x4802 804C

0x4802 8090

0x4802 8094

0x4802 8098

0x4802 809C

0x4802 80A4

0x4802 80A8

0x4802 80AC

0x4802 80B0

0x4802 80B4

0x4802 80B8

0x4802 80BC

I2C1 HEX ADDRESS

0x4802 A000

0x4802 A004

0x4802 A010

0x4802 A020

0x4802 A024

0x4802 A028

0x4802 A02C

0x4802 A030

0x4802 A034

0x4802 A038

0x4802 A03C

0x4802 A040

0x4802 A044

0x4802 A048

0x4802 A04C

0x4802 A090

0x4802 A094

0x4802 A098

0x4802 A09C

0x4802 A0A4

0x4802 A0A8

0x4802 A0AC

0x4802 A0B0

0x4802 A0B4

0x4802 A0B8

0x4802 A0BC

ACRONYM

I2C_REVNB_LO

I2C_REVNB_HI

I2C_SYSC

REGISTER NAME

Module Revision (LOW BYTES)

Module Revision (HIGH BYTES)

System configuration

I2C End of Interrupt

I2C Status Raw

I2C_EOI

I2C_IRQSTATUS_RAW

I2C_IRQSTATUS

I2C_IRQENABLE_SET

I2C_IRQENABLE_CLR

I2C_WE

I2C Status

I2C Interrupt Enable Set

I2C Interrupt Enable Clear

I2C Wakeup Enable

Receive DMA Enable Set

Transmit DMA Enable Set

Receive DMA Enable Clear

Transmit DMA Enable Clear

Receive DMA Wakeup

Transmit DMA Wakeup

System Status

I2C_DMARXENABLE_SET

I2C_DMATXENABLE_SET

I2C_DMARXENABLE_CLR

I2C_DMATXENABLE_CLR

I2C_DMARXWAKE_EN

I2C_DMATXWAKE_EN

I2C_SYSS

I2C_BUF

Buffer Configuration

Data Counter

I2C_CNT

I2C_DATA

Data Access

I2C_CON

I2C Configuration

I2C_OA

I2C Own Address

I2C_SA

I2C Slave Address

I2C_PSC

I2C Clock Prescaler

I2C SCL Low Time

I2C SCL High Time

System Test

I2C_SCLL

I2C_SCLH

I2C_SYSTEST

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Table 8-74. I2C Registers (continued)

I2C0 HEX ADDRESS

I2C1 HEX ADDRESS

0x4802 A0C0

0x4802 A0C4

0x4802 A0C8

0x4802 A0CC

0x4802 A0D0

0x4802 A0D4

ACRONYM

I2C_BUFSTAT

I2C_OA1

REGISTER NAME

I2C Buffer Status

0x4802 80C0

0x4802 80C4

0x4802 80C8

0x4802 80CC

0x4802 80D0

0x4802 80D4

I2C Own Address 1

I2C Own Address 2

I2C Own Address 3

Active Own Address

I2C Clock Blocking Enable

I2C_OA2

I2C_OA3

I2C_ACTOA

I2C_SBLOCK

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8.11.2 I2C Electrical Data/Timing

Table 8-75. Timing Requirements for I2C Input

(see Figure 8-72)

NO.

MIN

10

2.5

4.7

0.6

4

MAX UNIT

Standard_IC

Fast_IC

1

2

3

4

5

6

7

8

t_c(SCL)

Cycle time, SCL

µs

Standard_IC

Fast_IC

Setup time, SCL high before SDA low (for a

repeated Start condition)

t_{su(SCLH-SDAL)}

t_h(SDAL-SCLL)

t_w(SCLL)

µs

ns

Standard_IC

Fast_IC

Hold time, SCL low after SDA low (for a Start

and a repeated Start condition)

0.6

4.7

1.3

4

Standard_IC

Fast_IC

Pulse duration, SCL low

Standard_IC

Fast_IC

t_w(SCLH)

Pulse duration, SCL high

0.6

250

100

0

Standard_IC

Fast_IC

t_{su(SDAV-SCLH)}

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Standard_IC

Fast_IC

3.45

µs

Hold time, SDA valid after SCL low (for I2C

bus devices)

0

0.9

Standard_IC

Fast_IC

4.7

1.3

4

Pulse duration, SDA high between Stop and

Start conditions

µs

Standard_IC

Fast_IC

Setup time, high before SDA high (for Stop

condition)

13 t_{su(SCLH-SDAH)}

0.6

0

t_w(SDA)

Fast_IC

50

ns

50

14

Pulse duration, spike (must be suppressed)

t_w(SCL)

Fast_IC

0

9

11

I2C[x]_SDA

I2C[x]_SCL

6

8

14

4

13

5

10

1

12

3

7

2

3

Stop

Start

Repeated

Start

Stop

Figure 8-72. I2C Receive Timing

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Table 8-76. Switching Characteristics Over Recommended Operating Conditions for I2C Output

(see Figure 8-73)

NO.

PARAMETER

Cycle time, SCL

MIN

10

2.5

4.7

0.6

4

MAX UNIT

Standard_OC

Fast_OC

16 t_c(SCL)

µs

Standard_OC

Fast_OC

Setup Time, SCL high before SDA low (for a

repeated START condition)

17 t_{su(SCLH-SDAL)}

18 t_h(SDAL-SCLL)

19 t_w(SCLL)

µs

ns

Standard_OC

Fast_OC

Hold time, SCL low after SDA low (for a

START and a repeated START condition

0.6

4.7

1.3

4

Standard_OC

Fast_OC

Pulse duration, SCL low

Standard_OC

Fast_OC

20 t_w(SCLH)

Pulse duration, SCL high

0.6

250

100

0

Standard_OC

Fast_OC

21 t_{su(SDAV-SCLH)}

22 t_h(SCLL-SDA)

23 t_w(SDAH)

Setup time, SDA valid before SCL high

Standard_OC

Fast_OC

3.45

µs

Hold time, SDA valid after SCL low (For IIC

bus devices)

0

0.9

Standard_OC

Fast_OC

4.7

1.3

4

Pulse duration, SDA high between STOP and

START conditions

µs

Standard_OC

Fast_OC

Setup time, high before SDA high (for STOP

condition)

28 t_{su(SCLH-SDAH)}

0.6

26

24

I2C[x]_SDA

I2C[x]_SCL

21

23

19

28

20

25

27

16

18

22

17

18

Stop

Start

Repeated

Start

Stop

Figure 8-73. I2C Transmit Timing

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8.12 Multichannel Audio Serial Port (McASP)

The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for

the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)

stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission

(DIT).

8.12.1 McASP Device-Specific Information

The device includes three multichannel audio serial port (McASP) interface peripherals (McASP0,

McASP1, and McASP2). The McASP module consists of a transmit and receive section. These sections

can operate completely independently with different data formats, separate master clocks, bit clocks, and

frame syncs or, alternatively, the transmit and receive sections may be synchronized. The McASP module

also includes shift registers that may be configured to operate as either transmit data or receive data. The

transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous

serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF,

AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports the TDM

synchronous serial format.

The McASP module can support one transmit data format (either a TDM format or DIT format) and one

receive format at a time. All transmit shift registers use the same format and all receive shift registers use

the same format; however, the transmit and receive formats need not be the same. Both the transmit and

receive sections of the McASP also support burst mode, which is useful for non-audio data (for example,

passing control information between two devices).

The McASP peripheral has additional capability for flexible clock generation and error detection/handling,

as well as error management.

The device McASP0 module has six serial data pins, while McASP1 and McASP2 are limited to two serial

data pins each.

The McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are

used transparently to better manage DMA, which can be leveraged to manage data flow more efficiently.

For more detailed information on and the functionality of the McASP peripheral, see the McASP chapter in

the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number

SPRUGX7).

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8.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions

Table 8-77. McASP0/1/2 Registers

MCASP0 ADDRESS

0x4803 8000

MCASP1 ADDRESS

0x4803 C000

MCASP2 ADDRESS

0x4805 0000

ACRONYM

REGISTER NAME

Peripheral ID

PID

0x4803 8004

0x4803 C004

0x4805 0004

PWRIDLE

Power Idle SYSCONFIG

SYSCONFIG

0x4803 8010

0x4803 8014

0x4803 8018

0x4803 C010

0x4803 C014

0x4803 C018

0x4805 0010

0x4805 0014

0x4805 0018

PFUNC

PDIR

Pin Function

Pin Direction

Pin Data Out

PDOUT

PDIN

Pin Data Input (Read)

Read returns pin data input

PDSET

Pin Data Set (Write)

Writes effect pin data set

(alternate write address

PDOUT)

0x4803 801C

0x4803 C01C

0x4803 8020

0x4803 8044

0x4803 8048

0x4803 804C

0x4803 8050

0x4803 8060

0x4803 C020

0x4803 C044

0x4803 C048

0x4803 C04C

0x4803 C050

0x4803 C060

0x4805 0020

0x4805 0044

0x4805 0048

0x4805 004C

0x4805 0050

0x4805 0060

PDCLR

GBLCTL

AMUTE

Pin Data Clear

Global Control

Mute Control

LBCTL

Loop-Back Test Control

Transmit DIT Mode Control

TXDITCTL

GBLCTLR

Alias of GBLCTL containing

only receiver reset bits;

allows transmit to be reset

independently from receive

0x4803 8064

0x4803 8068

0x4803 806C

0x4803 C064

0x4803 C068

0x4803 C06C

0x4805 0064

0x4805 0068

0x4805 006C

RXMASK

RXFMT

Receiver Bit Mask

Receive Bitstream Format

RXFMCTL

Receive Frame Sync

Control

0x4803 8070

0x4803 8074

0x4803 C070

0x4803 C074

0x4805 0070

0x4805 0074

ACLKRCTL

Receive Clock Control

AHCLKRCTL

High Frequency Receive

Clock Control

0x4803 8078

0x4803 807C

0x4803 8080

0x4803 8084

0x4803 8088

0x4803 C078

0x4803 C07C

0x4803 C080

0x4803 C084

0x4803 C088

0x4805 0078

0x4805 007C

0x4805 0080

0x4805 0084

0x4805 0088

RXTDM

EVTCTLR

RXSTAT

Receive TDM Slot 0-31

Receiver Interrupt Control

Status Receiver

RXTDMSLOT

RXCLKCHK

Current Receive TDM Slot

Receiver Clock Check

Control

0x4803 808C

0x4803 80A0

0x4803 C08C

0x4803 C0A0

0x4805 008C

0x4805 00A0

REVTCTL

GBLCTLX

Receiver DMA Event

Control

Alias of GBLCTL containing

only transmit reset bits;

allows transmit to be reset

independently from receive

0x4803 80A4

0x4803 C0A4

0x4805 00A4

TXMASK

Transmit Format Unit Bit

Mask

0x4803 80A8

0x4803 80AC

0x4803 C0A8

0x4803 C0AC

0x4805 00A8

0x4805 00AC

TXFMT

Transmit Bitstream Format

TXFMCTL

Transmit Frame Sync

Control

0x4803 80B0

0x4803 80B4

0x4803 C0B0

0x4803 C0B4

0x4805 00B0

0x4805 00B4

ACLKXCTL

Transmit Clock Control

AHCLKXCTL

High Frequency Transmit

Clock Control

0x4803 80B8

0x4803 80BC

0x4803 80C0

0x4803 C0B8

0x4803 C0BC

0x4803 C0C0

0x4805 00B8

0x4805 00BC

0x4805 00C0

TXTDM

EVTCTLX

TXSTAT

Transmit TDM Slot 0-31

Transmitter Interrupt Control

Status Transmitter

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Table 8-77. McASP0/1/2 Registers (continued)

MCASP0 ADDRESS

0x4803 80C4

MCASP1 ADDRESS

0x4803 C0C4

MCASP2 ADDRESS

0x4805 00C4

ACRONYM

TXTDMSLOT

TXCLKCHK

REGISTER NAME

Current Transmit TDM Slot

0x4803 80C8

0x4803 C0C8

0x4805 00C8

Transmit Clock Check

Control

0x4803 80CC

0x4803 80D0

0x4803 C0CC

0x4803 C0D0

0x4805 00CC

0x4805 00D0

XEVTCTL

Transmitter DMA Control

CLKADJEN

One-shot Clock Adjust

Enable

0x4803 8100

0x4803 8104

0x4803 8108

0x4803 810C

0x4803 8110

0x4803 8114

0x4803 8118

0x4803 811C

0x4803 8120

0x4803 8124

0x4803 8128

0x4803 812C

0x4803 C100

0x4803 C104

0x4803 C108

0x4803 C10C

0x4803 C110

0x4803 C114

0x4803 C118

0x4803 C11C

0x4803 C120

0x4803 C124

0x4803 C128

0x4803 C12C

0x4805 0100

0x4805 0104

0x4805 0108

0x4805 010C

0x4805 0110

0x4805 0114

0x4805 0118

0x4805 011C

0x4805 0120

0x4805 0124

0x4805 0128

0x4805 012C

DITCSRA0

DITCSRA1

DITCSRA2

DITCSRA3

DITCSRA4

DITCSRA5

DITCSRB0

DITCSRB1

DITCSRB2

DITCSRB3

DITCSRB4

DITCSRB5

Left (Even TDM Slot)

Channel Status Register

File

Left (Even TDM Slot)

Channel Status Register

File

Left (Even TDM Slot)

Channel Status Register

File

Left (Even TDM Slot)

Channel Status Register

File

Left (Even TDM Slot)

Channel Status Register

File

Left (Even TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

Right (Odd TDM Slot)

Channel Status Register

File

0x4803 8130

0x4803 8134

0x4803 8138

0x4803 813C

0x4803 8140

0x4803 8144

0x4803 8148

0x4803 814C

0x4803 C130

0x4803 C134

0x4803 C138

0x4803 C13C

0x4803 C140

0x4803 C144

0x4803 C148

0x4803 C14C

0x4805 0130

0x4805 0134

0x4805 0138

0x4805 013C

0x4805 0140

0x4805 0144

0x4805 0148

0x4805 014C

DITUDRA0

DITUDRA1

DITUDRA2

DITUDRA3

DITUDRA4

DITUDRA5

DITUDRB0

DITUDRB1

Left (Even TDM Slot) User

Data Register File

Left (Even TDM Slot) User

Data Register File

Left (Even TDM Slot) User

Data Register File

Left (Even TDM Slot) User

Data Register File

Left (Even TDM Slot) User

Data Register File

Left (Even TDM Slot) User

Data Register File

Right (Odd TDM Slot) User

Data Register File

Right (Odd TDM Slot) User

Data Register File

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Table 8-77. McASP0/1/2 Registers (continued)

MCASP0 ADDRESS

MCASP1 ADDRESS

MCASP2 ADDRESS

ACRONYM

REGISTER NAME

0x4803 8150

0x4803 8154

0x4803 8158

0x4803 815C

0x4803 C150

0x4805 0150

DITUDRB2

Right (Odd TDM Slot) User

Data Register File

0x4803 C154

0x4803 C158

0x4803 C15C

0x4805 0154

0x4805 0158

0x4805 015C

DITUDRB3

DITUDRB4

DITUDRB5

Right (Odd TDM Slot) User

Data Register File

Right (Odd TDM Slot) User

Data Register File

Right (Odd TDM Slot) User

Data Register File

0x4803 8180 -

0x4803 81BC

0x4803 C180 -

0x4803 C1BC

0x4805 0180 - 0x4805

01BC

XRSRCTL0 -

XRSRCTL15

Serializer 0 Control -

Serializer 15 Control

0x4803 8200 -

0x4803 8 23C

0x4803 C200 -

0x4803 C23C

0x4805 0200 - 0x4805 023C

TXBUF0 -

TXBUF15

Transmit Buffer for

Serializer 0 - Transmit

Buffer for Serializer 15

0x4803 8280 -

0x4803 82BC

0x4803 C280 -

0x4803 C2BC

0x4805 0280 - 0x4805

02BC

RXBUF0 -

RXBUF15

Receive Buffer for Serializer

0 - Receive Buffer for

Serializer 15

0x4803 9000

0x4803 9004

0x4803 9008

0x4803 900C

0x4803 D000

0x4803 D004

0x4803 D008

0x4803 D00C

0x4805 1000

0x4805 1004

0x4805 1008

0x4805 100C

BUFFER_CFGRD Write FIFO Control

_WFIFOCTL

BUFFER_CFGRD Write FIFO Status

_WFIFOSTS

BUFFER_CFGRD Read FIFO Control

_RFIFOCTL

BUFFER_CFGRD Read FIFO Status

_RFIFOSTS

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8.12.3 McASP Electrical Data/Timing

Table 8-78. Timing Requirements for McASP⁽¹⁾

(see Figure 8-74)

NO.

MIN

20

10

20

10

11.5

4

MAX UNIT

1

2

3

4

t_c(AHCLKRX)

t_w(AHCLKRX)

t_c(ACLKRX)

t_w(ACLKRX)

Cycle time, MCA[x]_AHCLKR/X

ns

Pulse duration, MCA[x]_AHCLKR/X high or low

Cycle time, MCA[x]_ACLKR/X

Pulse duration, MCA[x]_ACLKR/X high or low

ACLKR/X int

Setup time, MCA[x]_AFSR/X input valid before

MCA[x]_ACLKR/X

5

6

7

8

t_{su(AFSRX-ACLKRX)}

t_{h(ACLKRX-AFSRX)}

t_{su(AXR-ACLKRX)}

t_{h(ACLKRX-AXR)}

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

ns

4

-1

Hold time, MCA[x]_AFSR/X input valid after

MCA[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

0.4

11.5

4

Setup time, MCA[x]_AXR input valid before

MCA[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

ACLKR/X int

4

-1

Hold time, MCA[x]_AXR input valid after

MCA[x]_ACLKR/X

ACLKR/X ext in

ACLKR/X ext out

0.4

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

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2

1

2

MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

4

3

MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)^(A)

MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)^(B)

6

5

MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

8

7

MCA[x]_AXR[x] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 8-74. McASP Input Timing

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Table 8-79. Switching Characteristics Over Recommended Operating Conditions for McASP⁽¹⁾

(see Figure 8-75)

NO.

PARAMETER

MIN

MAX UNIT

9

t_c(AHCLKRX)

Cycle time, MCA[x]_AHCLKR/X

20⁽²⁾

ns

0.5P -

2.5⁽³⁾

10 t_w(AHCLKRX)

11 t_c(ACLKRX)

12 t_w(ACLKRX)

Pulse duration, MCA[x]_AHCLKR/X high or low

Cycle time, MCA[x]_ACLKR/X

ns

20

ns

0.5P -

2.5⁽³⁾

Pulse duration, MCA[x]_ACLKR/X high or low

ns

ACLKR/X int

0

2

6

Delay time, MCA[x]_ACLKR/X transmit edge to

MCA[x]_AFSR/X output valid

ACLKR/X ext in

13.5

ns

13 t_{d(ACLKRX-AFSRX)}

Delay time, MCA[x]_ACLKR/X transmit edge to

MCA[x]_AFSR/X output valid with Pad Loopback

ACLKR/X ext out

2

13.5

ACLKX int

0

2

6

Delay time, MCA[x]_ACLKX transmit edge to

MCA[x]_AXR output valid

ACLKX ext in

13.5

ns

14 t_d(ACLKX-AXR)

Delay time, MCA[x]_ACLKX transmit edge to

MCA[x]_AXR output valid with Pad Loopback

ACLKX ext out

2

13.5

ACLKX int

0

2

6

Disable time, MCA[x]_ACLKX transmit edge to

MCA[x]_AXR output high impedance

ACLKX ext in

13.5

ns

15 t_{dis(ACLKX-AXR)}

Disable time, MCA[x]_ACLKX transmit edge to

MCA[x]_AXR output high impedance with Pad

Loopback

ACLKX ext out

2

13.5

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2) 50 MHz

(3) P = AHCLKR/X period.

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10

9

MCA[x]_ACLKR/X (Falling Edge Polarity)

MCA[x]_AHCLKR/X (Rising Edge Polarity)

12

11

12

MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)^(A)

MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)^(B)

13

MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)

13

MCA[x]_AXR[x] (Data Out/Transmit)

14

15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

Figure 8-75. McASP Output Timing

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8.13 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

•

Full-duplex communication

Double-buffered data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

Supports TDM, I2S, and similar formats

External shift clock or an internal, programmable frequency shift clock for data transfer

5KB Tx and Rx buffer

Supports three interrupt and two DMA requests.

The McBSP module may support two types of data transfer at the system level:

•

The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge

and captured on the same edge (one clock period later).

•

The half-cycle mode, for which one half clock period is used to transfer the data, generated on one

edge and captured on the opposite edge (one half clock period later). Note that a new data is

generated only every clock period, which secures the required hold time. The interface clock

(CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured

accordingly with the external peripheral (activation edge capability) and the type of data transfer

required at the system level.

For more detailed information on the McBSP peripheral, see the McBSP chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

The following sections describe the timing characteristics for applications in normal mode (that is, the

McBSP connected to one peripheral) and TDM applications in multipoint mode.

8.13.1 McBSP Peripheral Register Descriptions

Table 8-80. McBSP Registers⁽¹⁾

HEX ADDRESS

0x4700 0000

0x4700 0008

0x4700 0010

0x4700 0014

0x4700 0018

0x4700 001C

0x4700 0020

0x4700 0024

0x4700 0028

0x4700 002C

0x4700 0030

0x4700 0034

0x4700 0038

0x4700 003C

0x4700 0040

0x4700 0044

0x4700 0048

0x4700 004C

ACRONYM

DRR_REG

REGISTER NAME

McBSP data receive

DXR_REG

McBSP data transmit

SPCR2_REG

SPCR1_REG

RCR2_REG

RCR1_REG

XCR2_REG

XCR1_REG

SRGR2_REG

SRGR1_REG

MCR2_REG

MCR1_REG

RCERA_REG

RCERB_REG

XCERA_REG

XCERB_REG

PCR_REG

McBSP serial port control 2

McBSP serial port control 1

McBSP receive control 2

McBSP receive control 1

McBSP transmit control 2

McBSP transmit control 1

McBSP sample rate generator 2

McBSP sample rate generator 1

McBSP multichannel 2

McBSP multichannel 1

McBSP receive channel enable partition A

McBSP receive channel enable partition B

McBSP transmit channel enable partition A

McBSP transmit channel enable partition B

McBSP pin control

RCERC_REG

McBSP receive channel enable partition C

(1) Note that the McBSP registers are 32-bit aligned.

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Table 8-80. McBSP Registers (continued)

HEX ADDRESS

ACRONYM

RCERD_REG

XCERC_REG

XCERD_REG

RCERE_REG

RCERF_REG

XCERE_REG

XCERF_REG

RCERG_REG

RCERH_REG

XCERG_REG

XCERH_REG

REV_REG

REGISTER NAME

0x4700 0050

0x4700 0054

0x4700 0058

0x4700 005C

0x4700 0060

0x4700 0064

0x4700 0068

0x4700 006C

0x4700 0070

0x4700 0074

0x4700 0078

0x4700 007C

0x4700 0080

0x4700 0084

0x4700 0088

0x4700 008C

0x4700 0090

0x4700 0094

0x4700 00A0

0x4700 00A4

0x4700 00A8

0x4700 00AC

0x4700 00B0

0x4700 00B4

0x4700 00B8

0x4700 00C0

McBSP receive channel enable partition D

McBSP transmit channel enable partition C

McBSP transmit channel enable partition D

McBSP receive channel enable partition E

McBSP receive channel enable partition F

McBSP transmit channel enable partition E

McBSP transmit channel enable partition F

McBSP receive channel enable partition G

McBSP receive channel enable partition H

McBSP transmit channel enable partition G

McBSP transmit channel enable partition H

McBSP revision number

RINTCLR_REG

XINTCLR_REG

ROVFLCLR_REG

SYSCONFIG_REG

THRSH2_REG

THRSH1_REG

IRQSTATATUS

IRQENABLE

McBSP receive interrupt clear

McBSP transmit interrupt clear

McBSP receive overflow interrupt clear

McBSP system configuration

McBSP transmit buffer threshold (DMA or IRQ trigger)

McBSP receive buffer threshold (DMA or IRQ trigger)

McBSP interrupt status (OCP compliant IRQ line)

McBSP interrupt enable (OCP compliant IRQ line)

McBSP wakeup enable

WAKEUPEN

XCCR_REG

McBSP transmit configuration control

McBSP receive configuration control

McBSP transmit buffer status

RCCR_REG

XBUFFSTAT_REG

RBUFFSTAT_REG

STATUS_REG

McBSP receive buffer status

McBSP status

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8.13.2 McBSP Electrical Data/Timing

Table 8-81. Timing Requirements for McBSP - Master Mode⁽¹⁾

(see Figure 8-76)

NO.

MIN

3.5

MAX UNIT

6

7

t_{su(DRV-CLKAE)}

t_h(CLKAE-DRV)

Setup time, MCB_DR valid before MCB_CLK active edge⁽²⁾

Hold time, MCB_DR valid after MCB_CLK active edge⁽²⁾

ns

0.1

(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.

Table 8-82. Switching Characteristics Over Recommended Operating Conditions for McBSP - Master

Mode⁽¹⁾

(see Figure 8-76)

NO.

1

PARAMETER

MIN

20.83

0.5*P - 1⁽³⁾

MAX UNIT

t_c(CLK)

Cycle time, output MCB_CLK period⁽²⁾

Pulse duration, output MCB_CLK low⁽²⁾

Pulse duration, output MCB_CLK high⁽²⁾

ns

2

t_w(CLKL)

t_w(CLKH)

3

Delay time, output MCB_CLK active edge to output MCB_FS

valid⁽²⁾⁽⁴⁾

4

5

t_d(CLKAE-FSV)

0.7

9.4

ns

Delay time, output MCB_CLKX active edge to output MCB_DX

valid

t_{d(CLKXAE-DXV)}

(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.

(3) P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP

frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.

(4) MCB_FS corresponds to either MCB_FSX or MCB_FSR.

2

1

3

MCB_CLK

4

MCB_FS

MCB_DX

5

MCB_DX7

MCB_DX6

MCB_DX0

MCB_DR0

7

6

MCB_DR

MCB_DR7

MCB_DR6

A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive

output data and capture input data.

B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either

MCBSP_FSX

or

MCBSP_FSR.

McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.

McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are

internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.

C. The polarity of McBSP frame synchronization is software configurable.

D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and

MCBSP_DR data is sampled is software configurable.

E. Timing diagrams are for data delay set to 1.

F. For further details about the registers used to configure McBSP, see the McBSP chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

Figure 8-76. McBSP Master Mode Timing

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Table 8-83. Timing Requirements for McBSP - Slave Mode⁽¹⁾

(see Figure 8-77)

NO.

MIN

MAX UNIT

1

2

3

4

5

7

8

t_c(CLK)

Cycle time, MCB_CLK period⁽²⁾

Pulse duration, MCB_CLK low⁽²⁾

Pulse duration, MCB_CLK high⁽²⁾

Setup time, MCB_FS valid before MCB_CLK active edge⁽²⁾⁽⁴⁾

Hold time, MCB_FS valid after MCB_CLK active edge⁽²⁾⁽⁴⁾

Setup time, MCB_DR valid before MCB_CLK active edge⁽²⁾

Hold time, MCB_DR valid after MCB_CLK active edge⁽²⁾

20.83

0.5*P - 1⁽³⁾

ns

t_w(CLKL)

t_w(CLKH)

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

t_{su(DRV-CLKAE)}

t_h(CLKAE-DRV)

3.8

0

3.8

0

(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) MCB_CLK corresponds to either MCB_CLKX or MCB_CLKR.

(3) P = MCB_CLKX/MCB_CLKR output CLK period, in ns; use whichever value is greater. This parameter applies to the maximum McBSP

frequency. Operate serial clocks (CLKX/R) in the reasonable range of 40/60 duty cycle.

(4) MCB_FS corresponds to either MCB_FSX or MCB_FSR.

Table 8-84. Switching Characteristics Over Recommended Operating Conditions for McBSP - Slave

Mode⁽¹⁾

(see Figure 8-77)

NO.

PARAMETER

MIN

MAX UNIT

12.5 ns

6

t_{d(CLKXAE-DXV)}

Delay time, input MCB_CLKx active edge to output MCB_DX valid

0.5

(1) The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive output data and capture

input data.

2

1

3

MCB_CLK

4

5

MCB_FS

6

8

6

MCB_DX

MCB_DR

MCB_DX7

MCB_DX6

MCB_DX0

MCB_DR0

7

MCB_DR7

MCB_DR6

A. The timings apply to all configurations regardless of MCB_CLK polarity and which clock edges are used to drive

output data and capture input data.

B. MCBSP_CLK corresponds to either MCBSP_CLKX or MCBSP_CLKR; MCBSP_FS corresponds to either

MCBSP_FSX

or

MCBSP_FSR.

McBSP in 6-pin mode: DX and DR as data pins; CLKX, CLKR, FSX and FSR as control pins.

McBSP in 4-pin mode: DX and DR as data pins; CLKX and FSX pins as control pins. The CLKX and FSX pins are

internally looped back via software configuration, respectively to the CLKR and FSR internal signals for data receive.

C. The polarity of McBSP frame synchronization is software configurable.

D. The active clock edge selection of MCBSP_CLK (rising or falling) on which MCBSP_DX data is latched and

MCBSP_DR data is sampled is software configurable.

E. Timing diagrams are for data delay set to 1.

F. For further details about the registers used to configure McBSP, see the McBSP chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

Figure 8-77. McBSP Slave Mode Timing

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8.14 Peripheral Component Interconnect Express (PCIe)

The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus

interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device

implements a single two-lane PCIe 2.0 (5.0 GT/s) endpoint/root complex port.

The device PCIe supports the following features:

•

Supports Gen1/Gen2 in x1 or x2 mode

One port with up to 2 x 5 GT/s lanes

Single virtual channel (VC), single traffic class (TC)

Single function in end-point mode

Automatic width and speed negotiation and lane reversal

Max payload: 128 byte outbound, 256 byte inbound

Automatic credit management

ECRC generation and checking

Configurable BAR filtering

Supports PCIe messages

Legacy interrupt reception (RC) and generation (EP)

MSI generation and reception

PCI device power management, except D3 cold with vaux

Active state power management state L0 and L1.

For more detailed information on the PCIe port peripheral module, see the PCIe chapter in the AM38x

Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

The PCIe peripheral on the device conforms to the PCI Express Base 2.0 Specification.

8.14.1 PCIe Design and Layout Guidelines

8.14.1.1 Clock Source

A standard 100-MHz PCIe differential clock source must be used for PCIe operation (for details, see

Section 7.3.2).

8.14.1.2 PCIe Connections and Interface Compliance

The PCIe interface on the device is compliant with the PCI Express Base 2.0 Specification. Refer to the

PCIe specifications for all connections that are described in it. For coupling capacitor selection, see

Section 8.14.1.2.1.

The use of PCIe-compatible bridges and switches is allowed for interfacing with more than one other

processor or PCIe device.

8.14.1.2.1 Coupling Capacitors

AC coupling capacitors are required on the transmit data pair. Table 8-85 shows the requirements for

these capacitors.

Table 8-85. AC Coupling Capacitors Requirements

PARAMETER

MIN

TYP

MAX

200

UNIT

nF

EIA⁽²⁾

PCIe AC coupling capacitor value

PCIe AC coupling capacitor package size⁽¹⁾

75

0402

0603

(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.

(2) EIA LxW units; i.e., a 0402 is a 40x20 mil (thousandths of an inch) surface-mount capacitor.

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8.14.1.2.2 Polarity Inversion

The PCIe specification requires polarity inversion support. This means, for layout purposes, polarity is

unimportant since each signal can change its polarity on-die inside the chip. This means polarity within a

lane is unimportant for layout.

8.14.1.2.3 Lane Reversal

The device supports lane reversal. Since there are two lanes, this means the lanes can be switched in

layout for better PCB routing.

8.14.1.3 Non-Standard PCIe Connections

The following sections contain suggestions for any PCIe connection that is not described in the official

PCIe specification, such as an on-board device-to-device connection, or device-to-other PCIe-compliant

processor connection.

8.14.1.3.1 PCB Stackup Specifications

Table 8-86 shows the stackup and feature sizes required for these types of PCIe connections.

Table 8-86. PCIe PCB Stackup Specifications

PARAMETER

MIN

TYP

6

MAX

UNIT

Layers

Cuts

Layers

Mils

PCB Routing/Plane Layers

Signal Routing Layers

4

2

-

3

Number of ground plane cuts allowed within PCIe routing region

Number of layers between PCIe routing area and reference plane⁽¹⁾

PCB Routing clearance

-

0

-

4

PCB Trace width⁽²⁾

-

4

-

Mils

PCB BGA escape via pad size

-

20

10

0.4

-

Mils

PCB BGA escape via hole size

MPU BGA pad size⁽³⁾⁽⁴⁾

-

Mils

mm

(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.

(2) In breakout area.

(3) Non-solder mask defined pad.

(4) Per IPC-7351A BGA pad size guideline.

8.14.1.3.2 Routing Specifications

The PCIe data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω

(±15%) single-ended impedance. The single-ended impedance is required because differential signals are

extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.

These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0

document, available from PCI-SIG.

These impedances are impacted by trace width, trace spacing, distance between signals and referencing

planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal

pairs result in as close to 100 Ω differential impedance and 60 Ω single-ended impedance as possible. For

best accuracy, work with your PCB fabricator to ensure this impedance is met.

In general, closely coupled differential signal traces are not an advantage on PCBs. When differential

signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing

variations affect impedance dramatically, so tight impedance control can be more problematic to maintain

in production.

Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing

make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it

is easier to maintain an accurate impedance over the length of the signal. The wider traces also show

reduced skin effect and, therefore, often result in better signal integrity.

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Table 8-87 shows the routing specifications for the PCIe data signals.

Table 8-87. PCIe Routing Specifications

PARAMETER

MIN

TYP

MAX

UNIT

PCIe signal trace length

10⁽¹⁾Inches

Differential pair trace matching

10⁽²⁾

0

Mils

Stubs

Ω

Number of stubs allowed on PCIe traces⁽³⁾

TX/RX pair differential impedance

TX/RX single ended impedance

80

51

100

60

120

69

Ω

Pad size of vias on PCIe trace

25⁽⁴⁾

Mils

Vias⁽⁵⁾

Hole size of vias on PCIe trace

14

Number of vias on each PCIe trace

PCIe differential pair to any other trace spacing

3

2*DS⁽⁶⁾

(1) Beyond this, signal integrity may suffer.

(2) For example, RXP0 within 10 Mils of RXN0.

(3) In-line pads may be used for probing.

(4) 35-Mil antipad max recommended.

(5) Vias must be used in pairs with their distance minimized.

(6) DS = differential spacing of the PCIe traces.

8.14.2 PCIe Peripheral Register Descriptions

Table 8-88. PCIe Registers

HEX ADDRESS

0x5100 0000

0x5100 0004

0x5100 0008

0x5100 000C

0x5100 0010

0x5100 0014

0x5100 0020

0x5100 0024

0x5100 0028

0x5100 0030

0x5100 0034

0x5100 0038

0x5100 003C

0x5100 0050

0x5100 0054

0x5100 0064

0x5100 0068

0x5100 006C

0x5100 0070

0x5100 0074

0x5100 0078

0x5100 007C

0x5100 0100

0x5100 0104

0x5100 0108

0x5100 010C

0x5100 0180

ACRONYM

PID

REGISTER NAME

Peripheral Version and ID

Command Status

CMD_STATUS

CFG_SETUP

IOBASE

Config Transaction Setup

IO TLP Base

TLPCFG

TLP Attribute Configuration

Reset Command and Status

Power Management Command

Power Management Configuration

Activity Status

RSTCMD

PMCMD

PMCFG

ACT_STATUS

OB_SIZE

Outbound Size

DIAG_CTRL

ENDIAN

Diagnostic Control

Endian Mode

PRIORITY

CBA Transaction Priority

End of Interrupt

IRQ_EOI

MSI_IRQ

MSI Interrupt IRQ

EP_IRQ_SET

EP_IRQ_CLR

EP_IRQ_STATUS

GPRO

Endpoint Interrupt Request Set

Endpoint Interrupt Request Clear

Endpoint Interrupt Status

General Purpose 0

GPR1

General Purpose 1

GPR2

General Purpose 2

GPR3

General Purpose 3

MSI0_IRQ_STATUS_RAW

MSI0_IRQ_STATUS

MSI0_IRQ_ENABLE_SET

MSI0_IRQ_ENABLE_CLR

IRQ_STATUS_RAW

MSI 0 Interrupt Raw Status

MSI 0 Interrupt Enabled Status

MSI 0 Interrupt Enable Set

MSI 0 Interrupt Enable Clear

Raw Interrupt Status

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Table 8-88. PCIe Registers (continued)

HEX ADDRESS

ACRONYM

IRQ_STATUS

REGISTER NAME

0x5100 0184

0x5100 0188

0x5100 018C

0x5100 01C0

0x5100 01C4

0x5100 01C8

0x5100 01CC

0x5100 01D0

0x5100 01D4

0x5100 01D8

0x5100 01DC

0x5100 0200

0x5100 0204

0x5100 0300

0x5100 0304

0x5100 0308

0x5100 030C

0x5100 0310

0x5100 0314

0x5100 0318

0x5100 031C

0x5100 0320

0x5100 0324

0x5100 0328

0x5100 032C

0x5100 0330

0x5100 0334

0x5100 0338

0x5100 033C

0x5100 0380

0x5100 0384

0x5100 0388

0x5100 0390

0x5100 0394

Interrupt Enabled Status

IRQ_ENABLE_SET

IRQ_ENABLE_CLR

ERR_IRQ_STATUS_RAW

ERR_IRQ_STATUS

ERR_IRQ_ENABLE_SET

ERR_IRQ_ENABLE_CLR

PMRST_IRQ_STATUS_RAW

PMRST_IRQ_STATUS

PMRST_ENABLE_SET

PMRST_ENABLE_CLR

OB_OFFSET_INDEXn

OB_OFFSETn_HI

IB_BAR0

Interrupt Enable Set

Interrupt Enable Clear

Raw ERR Interrupt Status

ERR Interrupt Enabled Status

ERR Interrupt Enable Set

ERR Interrupt Enable Clear

Power Management and Reset Interrupt Status

Power Management and Reset Interrupt Enabled Status

Power Management and Reset Interrupt Enable Set

Power Management and Reset Interrupt Enable Clear

Outbound Translation Region N Offset Low and Index

Outbound Translation Region N Offset High

Inbound Translation Bar Match 0

Inbound Translation 0 Start Address Low

Inbound Translation 0 Start Address High

Inbound Translation 0 Address Offset

Inbound Translation Bar Match 1

Inbound Translation 1 Start Address Low

Inbound Translation 1 Start Address High

Inbound Translation 1 Address Offset

Inbound Translation Bar Match 2

Inbound Translation 2 Start Address Low

Inbound Translation 2 Start Address High

Inbound Translation 2 Address Offset

Inbound Translation Bar Match 3

Inbound Translation 3 Start Address Low

Inbound Translation 3 Start Address High

Inbound Translation 3 Address Offset

PCS Configuration 0

IB_START0_LO

IB_START0_HI

IB_OFFSET0

IB_BAR1

IB_START1_LO

IB_START1_HI

IB_OFFSET1

IB_BAR2

IB_START2_LO

IB_START2_HI

IB_OFFSET2

IB_BAR3

IB_START3_LO

IB_START3_HI

IB_OFFSET3

PCS_CFG0

PCS_CFG1

PCS Configuration 1

PCS_STATUS

PCS Status

SERDES_CFG0

SERDES_CFG1

SerDes Configuration for Lane 0

SerDes Configuration for Lane 1

8.14.3 PCIe Electrical Data/Timing

Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCIe

peripheral meets all AC timing specifications as required by the PCI Express Base 2.0 Specification.

Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing

specifications, see Sections 4.3.3.5 and 4.3.4.4 of the PCI Express Base 2.0 Specification.

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8.15 Real-Time Clock (RTC)

The real-time clock is a precise timer that can generate interrupts on intervals specified by the user.

Interrupts can occur every second, minute, hour, or day. The clock, itself, can track the passage of real

time for durations of several years, provided it has a sufficient power source the whole time.

The basic purpose for the RTC is to keep time of day. The other equally important purpose of the RTC is

for Digital Rights management. Some degree of tamper-proofing is needed to ensure that simply stopping,

resetting, or corrupting the RTC does not go unnoticed; so, if this occurs, the application can re-acquire

the time of day from a trusted source. The final purpose of RTC is to wake up the rest of the device from a

power-down state. The RTC features include:

•

Time information (hours/minutes/seconds) directly in binary coded decimal (BCD), for easy decoding.

Calendar information (day/month/year/day of week) directly in BCD code up to year 2099.

Shadow time and calendar access; ease of reading time.

Interrupt generation, periodically (1d/1h/1m/1s) or at a precise time of day and/or date.

30-second time correction (crystal frequency compensation).

OCP slave port for register access.

Supports power idle protocol with SWakeUp capable on alarm or timer events.

The RTC is driven by SYSCLK18 (32.768 kHz) or an optional 32.768-kHz clock can be input on the

CLKIN32 clock input pin for RTC reference.

Figure 8-78 shows the major components of the RTC.

32.768 kHz

Counter

32 kHz

Compensation

Week Days

Control

Years

Minutes

Hours

Days

Month

Seconds

IRQ_ALARM

NIRQ_TIMER

Interrupt

Alarm

Figure 8-78. Real-Time Clock Block Diagram

8.15.1 RTC Register Descriptions

Table 8-89. RTC Registers

HEX ADDRESS

0x480C 0000

0x480C 0004

0x480C 0008

0x480C 000C

0x480C 0010

0x480C 0014

ACRONYM

SECONDS_REG

REGISTER NAME

Seconds

Minutes

Hours

MINUTES_REG

HOURS_REG

DAYS_REG

Day of the Month

Month

MONTHS_REG

YEARS_REG

Year

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Table 8-89. RTC Registers (continued)

HEX ADDRESS

ACRONYM

WEEK_REG

REGISTER NAME

Day of the Week

Alarm Seconds

Alarm Minutes

Alarm Hours

0x480C 0018

0x480C 0020

0x480C 0024

0x480C 0028

0x480C 002C

0x480C 0030

0x480C 0034

0x480C 0040

0x480C 0044

0x480C 0048

0x480C 004C

0x480C 0050

0x480C 0054

0x480C 0060

0x480C 0064

0x480C 0068

0x480C 006C

0x480C 0070

0x480C 0074

0x480C 0078

0x480C 007A

ALARM_SECONDS_REG

ALARM_MINUTES_REG

ALARM_HOURS_REG

ALARM_DAYS_REG

ALARM_MONTHS_REG

ALARM_YEARS_REG

RTC_CTRL_REG

Alarm Days

Alarm Months

Alarm Years

Control

RTC_STATUS_REG

RTC_INTERRUPTS_REG

RTC_COMP_LSB_REG

RTC_COMP_MSB_REG

RTC_OSC_REG

Status

Interrupt Enable

Compensation (LSB)

Compensation (MSB)

Oscillator

RTC_SCRATCH0_REG

RTC_SCRATCH1_REG

RTC_SCRATCH2_REG

KICK0

Scratch 0 (general-purpose)

Scratch 1 (general-purpose)

Scratch 2 (general-purpose)

Kick 0 (write protect)

KICK1

Kick 1 (write protect)

RTC_REVISION

Revision

RTC_SYSCONFIG

RTC_IRQWAKEEN_0

Clock Management Configuration

Wakeup Generation

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8.16 Secure Digital/Secure Digital Input Output (SD/SDIO)

The device SD/SDIO Controller has following features:

•

Secure Digital (SD) memory card with Secure Data I/O (SDIO)

Supports SDHC (SD high capacity)

SD/SDIO protocol support

Programmable clock frequency

1024 byte read/write FIFO to lower system overhead

Slave DMA transfer capability

Full compliance with SD command/response sets, as defined in the SD physical layer specification

v2.00

•

Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume

operations, as defined in the SD part E1 specification v 2 .00

Full compliance with SD host controller standard specification sets as defined in the SD card

specification part A2 v2.00.

For more detailed information on SD/SDIO, see the SD/SDIO chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.16.1 SD/SDIO Peripheral Register Descriptions

Table 8-90. SD/SDIO Registers⁽¹⁾

HEX ADDRESS

0x4806 0000

0x4806 0004

0x4806 0010

0x4806 0110

0x4806 0114

0x4806 0124

0x4806 0128

0x4806 012C

0x4806 0130

0x4806 0200

0x4806 0204

0x4806 0208

0x4806 020C

0x4806 0210

0x4806 0214

0x4806 0218

0x4806 021C

0x4806 0220

0x4806 0224

0x4806 0228

0x4806 022C

0x4806 0230

0x4806 0234

0x4806 0238

0x4806 023C

0x4806 0240

0x4806 0248

ACRONYM

SD_HL_REV

SD_HL_HWINFO

SD_HL_SYSCONFIG

SD_SYSCONFIG

SD_SYSSTATUS

SD_CSRE

REGISTER NAME

IP Revision Identifier

Hardware Configuration

Clock Management Configuration

System Configuration

System Status

Card status response error

System Test

SD_SYSTEST

SD_CON

Configuration

SD_PWCNT

SD_SDMASA

SD_BLK

Power counter

SDMA System address:

Transfer Length Configuration

Command argument

Command and transfer mode

Command Response 0 and 1

Command Response 2 and 3

Command Response 4 and 5

Command Response 6 and 7

Data

SD_ARG

SD_CMD

SD_RSP10

SD_RSP32

SD_RSP54

SD_RSP76

SD_DATA

SD_PSTATE

SD_HCTL

Present state

Host Control

SD_SYSCTL

SD_STAT

SD system control

Interrupt status

SD_IE

Interrupt SD enable

SD_ISE

SD_AC12

Auto CMD12 Error Status

Capabilities

SD_CAPA

SD_CUR_CAPA

Maximum current capabilities

(1) SD/SDIO registers are limited to 32-bit data accesses; 16-bit and 8-bit accesses are not allowed and can corrupt register content.

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Table 8-90. SD/SDIO Registers (continued)

HEX ADDRESS

ACRONYM

SD_FE

REGISTER NAME

Force Event

0x4806 0250

0x4806 0254

0x4806 0258

0x4806 025C

0x4806 02FC

SD_ADMAES

SD_ADMASAL

SD_ADMASAH

SD_REV

ADMA Error Status

ADMA System address Low bits

ADMA System address High bits

Versions

8.16.2 SD/SDIO Electrical Data/Timing

Table 8-91. Timing Requirements for SD/SDIO

(see Figure 8-80, Figure 8-82)

NO.

MIN

4.1

1.9

4.1

1.9

MAX UNIT

1

2

3

4

t_{su(CMDV-CLKH)}

t_h(CLKH-CMDV)

t_{su(DATV-CLKH)}

t_h(CLKH-DATV)

Setup time, SD_CMD valid before SD_CLK rising clock edge

Hold time, SD_CMD valid after SD_CLK rising clock edge

Setup time, SD_DATx valid before SD_CLK rising clock edge

Hold time, SD_DATx valid after SD_CLK rising clock edge

ns

Table 8-92. Switching Characteristics Over Recommended Operating Conditions for SD/SDIO

(see Figure 8-79, Figure 8-80, Figure 8-81, Figure 8-82)

NO.

PARAMETER

MIN

MAX UNIT

f_op(CLK)

t_c(CLK)

Operating frequency, SD_CLK

48

MHz

ns

7

Operating period: SD_CLK

20.8

f_op(CLKID)

t_c(CLKID)

t_w(CLKL)

Identification mode frequency, SD_CLK

Identification mode period: SD_CLK

Pulse duration, SD_CLK low

400

kHz

ns

8

9

2500.0

0.5*P⁽¹⁾

ns

10 t_w(CLKH)

11 t_r(CLK)

Pulse duration, SD_CLK high

ns

Rise time, All Signals (10% to 90%)

Fall time, All Signals (10% to 90%)

Delay time, SD_CLK rising clock edge to SD_CMD transition

Delay time, SD_CLK rising clock edge to SD_DATx transition

2.2

ns

12 t_f(CLK)

ns

13 t_d(CLKL-CMD)

14 t_d(CLKL-DAT)

2.5

13.9

ns

(1) P = SD_CLK period.

10

7

9

SD_CLK

SD_CMD

13

Valid

13

START

XMIT

Valid

END

Figure 8-79. SD Host Command Timing

9

10

7

SD_CLK

1

2

Valid

START

XMIT

SD_CMD

Valid

END

Figure 8-80. SD Card Response Timing

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10

9

7

SD_CLK

14

D0

14

START

D1

Dx

END

SD_DATx

Figure 8-81. SD Host Write Timing

9

10

7

SD_CLK

4

3

Start

SD_DATx

D0

D1

Dx

End

Figure 8-82. SD Host Read and Card CRC Status Timing

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8.17 Serial ATA Controller (SATA)

The Serial ATA (SATA) peripheral provides a direct interface for up to two hard disk drives (SATA) and

supports the following features:

•

Serial ATA 1.5 Gbps and 3 Gbps speeds

Integrated PHY

Integrated Rx and Tx data buffers

Supports all SATA power management features

Hardware-assisted native command queuing (NCQ) for up to 32 entries

Supports port multiplier with command-based switching for connection to multiple hard disk drives

Activity LED support.

For more detailed information on the SATA, see the SATA chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.17.1 SATA Interface Design Guidelines

This section provides PCB design and layout guidelines for the SATA interface. The design rules constrain

PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system

design work has been done to ensure the SATA interface requirements are met.

A standard 100-MHz differential clock source must be used for SATA operation (for details, see

Section 7.3.2).

8.17.1.1 SATA Interface Schematic

Figure 8-83 shows the data portion of the SATA interface schematic. The specific pin numbers can be

obtained from Table 3-17, Serial ATA Terminal Functions.

SATA Interface (Processor)

SATA Connector

10 nF

SATA_TXN

TX-

SATA_TXP

TX+

10 nF

SATA_RXN

SATA_RXP

RX-

RX+

10 nF

Figure 8-83. SATA Interface High-Level Schematic

8.17.1.2 Compatible SATA Components and Modes

Table 8-93 shows the compatible SATA components and supported modes. Note that the only supported

configuration is an internal cable from the processor host to the SATA device.

Table 8-93. SATA Supported Modes

PARAMETER

MIN

MAX

UNIT

SUPPORTED

Transfer Rates

eSATA

1.5

3.0

Gbps

-

No

xSATA

Backplane

Internal Cable

No

Yes

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8.17.1.3 PCB Stackup Specifications

Table 8-94 shows the PCB stackup and feature sizes required for SATA.

Table 8-94. SATA PCB Stackup Specifications

PARAMETER

MIN

TYP

6

MAX

UNIT

Layers

Cuts

PCB routing/plane layers

Signal routing layers

4

2

-

3

Number of ground plane cuts allowed within SATA routing region

Number of layers between SATA routing region and reference ground plane

PCB trace width, w

-

0

-

Layers

Mils

-

4

PCB BGA escape via pad size

-

20

10

0.4

-

Mils

PCB BGA escape via hole size

MPU BGA pad size⁽¹⁾

-

Mils

mm

(1) NSMD pad, per IPC-7351A BGA pad size guideline.

8.17.1.4 Routing Specifications

The SATA data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω

(±15%) single-ended impedance. The single-ended impedance is required because differential signals are

extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.

60 Ω is chosen for the single-ended impedance to minimize problems caused by too low an impedance.

These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric

material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as

close to 100 Ω differential impedance and 60 Ω single-ended impedance traces as possible. For best

accuracy, work with your PCB fabricator to ensure this impedance is met.

Table 8-95 shows the routing specifications for the SATA data signals.

Table 8-95. SATA Routing Specifications

PARAMETER

MIN

TYP

MAX

UNIT

MPU-to-SATA header trace length

10⁽¹⁾Inches

Number of stubs allowed on SATA traces⁽²⁾

0

120

69

Stubs

Ω

TX/RX pair differential impedance

80

51

100

60

TX/RX single ended impedance

Ω

Number of vias on each SATA trace

SATA differential pair to any other trace spacing

3

Vias⁽³⁾

2*DS⁽⁴⁾

(1) Beyond this, signal integrity may suffer.

(2) In-line pads may be used for probing.

(3) Vias must be used in pairs with their distance minimized.

(4) DS = differential spacing of the SATA traces.

8.17.1.5 Coupling Capacitors

AC coupling capacitors are required on the receive data pair. Table 8-96 shows the requirements for these

capacitors.

Table 8-96. SATA AC Coupling Capacitors Requirements

PARAMETER

MIN

TYP

10

MAX

12

UNIT

nF

EIA⁽²⁾

SATA AC coupling capacitor value

SATA AC coupling capacitor package size⁽¹⁾

1

0402

0603

(1) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.

(2) EIA LxW units; i.e., a 0402 is a 40x20 mil surface-mount capacitor.

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8.17.2 SATA Peripheral Register Descriptions

Table 8-97. SATA Registers

HEX ADDRESS

0x4A14 0000

ACRONYM

REGISTER NAME

HBA Capabilities

CAP

GHC

0x4A14 0004

Global HBA Control

Interrupt Status

0x4A14 0008

IS

0x4A14 000C

0x4A14 0010

PI

Ports Implemented

AHCI Version

VS

0x4A14 0014

CCC_CTL

CCC_PORTS

-

Command Completion Coalescing Control

Command Completion Coalescing Ports

Reserved

0x4A14 0018

0x4A14 001C - 0x4A14 009C

0x4A14 00A0

0x4A14 00A4

0x4A14 00A8

0x4A14 00AC

0x4A14 00B0

0x4A14 00B4 - 0x4A14 00DF

0x4A14 00E0

0x4A14 00E4

0x4A14 00E8

0x4A14 00EC

0x4A14 00F0

0x4A14 00F4

0x4A14 00F8

0x4A14 00FC

0x4A14 0100

BISTAFR

BISTCR

BISTFCTR

BISTSR

BISTDECR

-

BIST Active FIS

BIST Control

BIST FIS Count

BIST Status

BIST DWORD Error Count

Reserved

TIMER1MS

-

BIST DWORD Error Count

Reserved

GPARAM1R

GPARAM2R

PPARAMR

TESTR

VERSIONR

IDR (PID)

P0CLB

-

Global Parameter 1

Global Parameter 2

Port Parameter

Test

Version

ID

Port 0 Command List Base Address

Reserved

0x4A14 0104

0x4A14 0108

P0FB

Port 0 FIS Base Address

Reserved

0x4A14 010C

0x4A14 0110

-

P0IS

Port 0 Interrupt Status

Port 0 Interrupt Enable

Port 0 Command

0x4A14 0114

P0IE

0x4A14 0118

P0CMD

-

0x4A14 011C

0x4A14 0120

Reserved

P0TFD

P0SIG

P0SSTS

P0SCTL

P0SERR

P0SACT

P0CI

Port 0 Task File Data

Port 0 Signature

0x4A14 0124

0x4A14 0128

Port 0 Serial ATA Status (SStatus)

Port 0 Serial ATA Control (SControl)

Port 0 Serial ATA Error (SError)

Port 0 Serial ATA Active (SActive)

Port 0 Command Issue

Port 0 Serial ATA Notification

Reserved

0x4A14 012C

0x4A14 0130

0x4A14 0134

0x4A14 0138

0x4A14 013C

0x4A14 0140 - 0x4A14 016C

0x4A14 0170

P0SNTF

-

P0DMACR

-

Port 0 DMA Control

Reserved

0x4A14 0174

0x4A14 0178

P0PHYCR

P0PHYSR

P1CLB

-

Port 0 PHY Control

Port 0 PHY Status

Port 1 Command List Base Address

Reserved

0x4A14 017C

0x4A14 0180

0x4A14 0184

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Table 8-97. SATA Registers (continued)

HEX ADDRESS

0x4A14 0188

ACRONYM

P1FB

REGISTER NAME

Port 1 FIS Base Address

Reserved

0x4A14 018C

0x4A14 0190

-

P1IS

Port 1 Interrupt Status

Port 1 Interrupt Enable

Port 1 Command

0x4A14 0194

P1IE

0x4A14 0198

P1CMD

-

0x4A14 019C

0x4A14 01A0

0x4A14 01A4

0x4A14 01A8

0x4A14 01AC

0x4A14 01B0

0x4A14 01B4

0x4A14 01B8

0x4A14 01BC

0x4A14 01C0 - 0x4A14 01EC

0x4A14 01F0

0x4A14 01F4

0x4A14 01F8

0x4A14 01FC

0x4A14 1100

Reserved

P1TFD

P1SIG

P1SSTS

P1SCTL

P1SERR

P1SACT

P1CI

Port 1 Task File Data

Port 1 Signature

Port 1 Serial ATA Status (SStatus)

Port 1 Serial ATA Control (SControl)

Port 1 Serial ATA Error (SError)

Port 1 Serial ATA Active (SActive)

Port 1 Command Issue

Port 1 Serial ATA Notification

Reserved

P1SNTF

-

P1DMACR

-

Port 1 DMA Control

Reserved

P1PHYCR

P1PHYSR

IDLE

Port 1 PHY Control

Port 1 PHY Status

Idle and Standby Modes

PHY Configuration 2

0x4A14 1104

PHYCFGR2

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8.18 Serial Peripheral Interface (SPI)

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed

length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is

normally used for communication between the device and external peripherals. Typical applications

include an interface-to-external I/O or peripheral expansion via devices such as shift registers, display

drivers, SPI EEPROMs, and analog-to-digital converters (ADCs).

The SPI supports the following features:

•

Master/slave operation

Four chip selects for interfacing/control to up to four SPI slave devices and connection to a single

external master

•

32-bit shift register

Buffered receive/transmit data register per channel (1 word deep), FIFO size is 64 bytes

Programmable SPI configuration per channel (clock definition, enable polarity and word width)

Supports one interrupt request and two DMA requests per channel.

For more detailed information on the SPI, see the SPI chapter in the AM38x Sitara ARM Microprocessors

(MPUs) Technical Reference Manual (literature number SPRUGX7).

8.18.1 SPI Peripheral Register Descriptions

Table 8-98. SPI Registers

HEX ADDRESS

0x4803 0000

ACRONYM

MCSPI_HL_REV

MCSPI_HL_HWINFO

-

REGISTER NAME

SPI REVISION

0x4803 0004

SPI HARDWARE INFORMATION

RESERVED

0x4803 0008 - 0x4803 000C

0x4803 0010

MCSPI_HL_SYSCONFIG

-

SPI SYSTEM CONFIGURATION

RESERVED

0x4803 0014 - 0x4803 00FF

0x4803 0100

MCSPI_REVISION

-

REVISION

0x4803 0104 - 0x4803 010C

0x4803 0110

RESERVED

MCSPI_SYSCONFIG

MCSPI_SYSSTATUS

MCSPI_IRQSTATUS

MCSPI_IRQENABLE

SYSTEM CONFIGURATION

SYSTEM STATUS

INTERRUPT STATUS

INTERRUPT ENABLE

0x4803 0114

0x4803 0118

0x4803 011C

0x4803 0120

MCSPI_WAKEUPENABLE WAKEUP ENABLE

0x4803 0124

MCSPI_SYST

MCSPI_MODULCTRL

MCSPI_CH0CONF

MCSPI_CH0STAT

MCSPI_CH0CTRL

MCSPI_TX0

SYSTEM TEST

0x4803 0128

MODULE CONTROL

0x4803 012C

CHANNEL 0 CONFIGURATION

CHANNEL 0 STATUS

0x4803 0130

0x4803 0134

CHANNEL 0 CONTROL

CHANNEL 0 TRANSMITTER

CHANNEL 0 RECEIVER

CHANNEL 1 CONFIGURATION

CHANNEL 1 STATUS

0x4803 0138

0x4803 013C

MCSPI_RX0

0x4803 0140

MCSPI_CH1CONF

MCSPI_CH1STAT

MCSPI_CH1CTRL

MCSPI_TX1

0x4803 0144

0x4803 0148

CHANNEL 1 CONTROL

CHANNEL 1 TRANSMITTER

CHANNEL 1 RECEIVER

CHANNEL 2 CONFIGURATION

CHANNEL 2 STATUS

0x4803 014C

0x4803 0150

MCSPI_RX1

0x4803 0154

MCSPI_CH2CONF

MCSPI_CH2STAT

MCSPI_CH2CTRL

MCSPI_TX2

0x4803 0158

0x4803 015C

CHANNEL 2 CONTROL

CHANNEL 2 TRANSMITTER

0x4803 0160

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Table 8-98. SPI Registers (continued)

HEX ADDRESS

0x4803 0164

ACRONYM

MCSPI_RX2

MCSPI_CH3CONF

MCSPI_CH3STAT

MCSPI_CH3CTRL

MCSPI_TX3

REGISTER NAME

CHANNEL 2 RECEIVER

CHANNEL 3 CONFIGURATION

CHANNEL 3 STATUS

0x4803 0168

0x4803 016C

0x4803 0170

CHANNEL 3 CONTROL

CHANNEL 3 TRANSMITTER

CHANNEL 3 RECEIVER

TRANSFER LEVELS

0x4803 0174

0x4803 0178

MCSPI_RX3

MCSPI_XFERLEVEL

MCSPI_DAFTX

-

0x4803 017C

0x4803 0180

DMA ADDRESS ALIGNED FIFO TRANSMITTER

RESERVED

0x4803 0184 - 0x4803 019C

0x4803 01A0

MCSPI_DAFRX

-

DMA ADDRESS ALIGNED FIFO RECEIVER

RESERVED

0x4803 01A4 - 0x4803 01FF

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8.18.2 SPI Electrical/Data Timing

Table 8-99. Timing Requirements for SPI - Master Mode

(see Figure 8-84 and Figure 8-85)

NO.

MIN

MAX UNIT

MASTER: 1 LOAD AT A MAXIMUM OF 5 pF

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

1

2

3

4

5

6

7

t_c(SPICLK)

20.8⁽³⁾

0.5*P - 1⁽⁴⁾

2.29

ns

t_w(SPICLKL)

t_w(SPICLKH)

Pulse duration, SPI_CLK high⁽¹⁾

t_{su(MISO-SPICLK)}

t_{h(SPICLK-MISO)}

t_{d(SPICLK-MOSI)}

t_d(SCS-MOSI)

Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

Delay time, SPI_SCS[x] active edge to SPI_D[x] transition

2.67

-3.57

3.57

ns

MASTER_PHA0⁽⁵⁾

B-4.2⁽⁶⁾

A-4.2⁽⁷⁾

B-4.2⁽⁶⁾

Delay time, SPI_SCS[x] active to SPI_CLK

first edge⁽¹⁾

8

9

t_{d(SCS-SPICLK)}

MASTER_PHA1⁽⁵⁾

MASTER_PHA0⁽⁵⁾

MASTER_PHA1⁽⁵⁾

Delay time, SPI_CLK last edge to SPI_SCS[x]

inactive⁽¹⁾

t_{d(SPICLK-SCS)}

MASTER: UP TO 4 LOADS AT A MAXIMUM TOTAL OF 25 pF

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

1

2

3

4

5

6

7

t_c(SPICLK)

41.7⁽⁸⁾

0.5*P - 2⁽⁴⁾

3.02

ns

t_w(SPICLKL)

t_w(SPICLKH)

Pulse duration, SPI_CLK high⁽¹⁾

t_{su(MISO-SPICLK)}

t_{h(SPICLK-MISO)}

t_{d(SPICLK-MOSI)}

t_d(SCS-MOSI)

Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

Delay time, SPI_SCS[x] active edge to SPI_D[x] transition

2.76

-4.62

4.62

MASTER_PHA0⁽⁵⁾

B-2.54⁽⁶⁾

A-2.54⁽⁷⁾

B-2.54⁽⁶⁾

Delay time, SPI_SCS[x] active to SPI_CLK

first edge⁽¹⁾

8

9

t_{d(SCS-SPICLK)}

MASTER_PHA1⁽⁵⁾

MASTER_PHA0⁽⁵⁾

MASTER_PHA1⁽⁵⁾

Delay time, SPI_CLK last edge to SPI_SCS[x]

inactive⁽¹⁾

t_{d(SPICLK-SCS)}

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the SPI_CLK maximum frequency.

(3) Maximum frequency = 48 MHz

(4) P = SPICLK period.

(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

(6) B = (TCS + 0.5) * TSPICLKREF * F_ratio, where TCS is a bit field of the SPI_CH(i)CONF register and F_ratio= Even ≥2.

(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS

+ 0.5) * F_ratio* TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

(8) Maximum frequency = 24 MHz

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PHA=0

EPOL=1

SPI_SCS[x] (Out)

1

3

2

8

2

3

9

POL=0

SPI_SCLK (Out)

POL=1

SPI_SCLK (Out)

6

7

6

SPI_D[x] (Out)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (Out)

SPI_SCLK (Out)

1

3

2

8

2

3

9

POL=0

POL=1

1

SPI_SCLK (Out)

SPI_D[x] (Out)

6

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-84. SPI Master Mode Transmit Timing

276

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PHA=0

EPOL=1

SPI_SCS[x] (Out)

1

3

2

8

2

3

9

POL=0

POL=1

SPI_SCLK (Out)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (Out)

SPI_SCLK (Out)

1

2

1

3

2

8

9

POL=0

POL=1

SPI_SCLK (Out)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-85. SPI Master Mode Receive Timing

Table 8-100. Timing Requirements for SPI - Slave Mode

(see Figure 8-86 and Figure 8-87)

NO.

MIN

62.5⁽³⁾

0.5*P - 3⁽⁴⁾

12.92

MAX

UNIT

ns

1

2

3

4

5

6

t_c(SPICLK)

Cycle time, SPI_CLK⁽¹⁾⁽²⁾

Pulse duration, SPI_CLK low⁽¹⁾

Pulse duration, SPI_CLK high⁽¹⁾

Setup time, SPI_D[x] valid before SPI_CLK active edge⁽¹⁾

Hold time, SPI_D[x] valid after SPI_CLK active edge⁽¹⁾

Delay time, SPI_CLK active edge to SPI_D[x] transition⁽¹⁾

t_w(SPICLKL)

ns

t_w(SPICLKH)

ns

t_{su(MOSI-SPICLK)}

t_{h(SPICLK-MOSI)}

t_{d(SPICLK-MISO)}

ns

12.92

ns

-4.00

17.1

ns

Delay time, SPI_SCS[x] active edge to SPI_D[x]

transition⁽⁵⁾

7

t_d(SCS-MISO)

ns

8

9

t_{su(SCS-SPICLK)}

t_{h(SPICLK-SCS)}

Setup time, SPI_SCS[x] valid before SPI_CLK first edge⁽¹⁾

Hold time, SPI_SCS[x] valid after SPI_CLK last edge⁽¹⁾

12.92

ns

(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture

input data.

(2) Related to the input maximum frequency supported by the SPI module.

(3) Maximum frequency = 16 MHz

(4) P = SPICLK period.

(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

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PHA=0

EPOL=1

SPI_SCS[x] (In)

1

3

8

2

9

POL=0

SPI_SCLK (In)

POL=1

SPI_SCLK (In)

6

7

6

SPI_D[x] (Out)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (In)

SPI_SCLK (In)

1

3

2

8

2

3

9

POL=0

POL=1

SPI_SCLK (In)

SPI_D[x] (Out)

6

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-86. SPI Slave Mode Transmit Timing

278

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PHA=0

EPOL=1

SPI_SCS[x] (In)

1

3

8

2

9

POL=0

POL=1

SPI_SCLK (In)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

PHA=1

EPOL=1

SPI_SCS[x] (In)

SPI_SCLK (In)

1

3

2

8

2

3

9

POL=0

POL=1

1

SPI_SCLK (In)

SPI_D[x] (In)

4

5

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

Figure 8-87. SPI Slave Mode Receive Timing

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8.19 Timers

The device has seven 32-bit general-purpose (GP) timers that have the following features:

•

Timers 1-3 are for software use and do not have an external connection

Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)

signal

•

Interrupts generated on overflow, compare, and capture

Free-running 32-bit upward counter

Supported modes:

–

Compare and capture modes

Auto-reload mode

Start-stop mode

•

Timer[7:1] functional clock is sourced from either the 27-MHz system clock, 32.768-kHz RTC clock or

the TCLKIN external timer input clock, as selected within the PRCM

•

On-the-fly read/write register (while counting)

Generates interrupts to the ARM CPUs.

The device has one system watchdog timer that has the following features:

•

Free-running 32-bit upward counter

On-the-fly read/write register (while counting)

Reset upon occurrence of a timer overflow condition

Two possible clock sources:

–

Internal 32.768-kHz clock derived from 27-MHz system clock.

External clock input on the CLKIN32 input pin.

The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault

condition, such as a non-exiting code loop.

For more detailed information, see the Timers chapter in the AM38x Sitara ARM Microprocessors (MPUs)

Technical Reference Manual (literature number SPRUGX7).

8.19.1 Timer Peripheral Register Descriptions

Table 8-101. Timer1-7 Registers⁽¹⁾

TIMER1 HEX

ADDRESS

TIMER2 HEX

ADDRESS

TIMER3 HEX

ADDRESS

TIMER4 HEX

ADDRESS

TIMER5 HEX

ADDRESS

TIMER6 HEX

ADDRESS

TIMER7 HEX

ADDRESS

ACRONYM

REGISTER NAME

0x4802 E000

0x4802 E010

0x4804 0000

0x4804 0010

0x4804 2000

0x4804 2010

0x4804 4000

0x4804 4010

0x4804 6000

0x4804 6010

0x4804 8000

0x4804 8010

0x4804 A000

0x4804 A010

TIDR

Identification

TIOCP_CFG Timer OCP

Configuration

0x4802 E020

0x4802 E024

0x4804 0020

0x4804 0024

0x4804 2020

0x4804 2024

0x4804 4020

0x4804 4024

0x4804 6020

0x4804 6024

0x4804 8020

0x4804 8024

0x4804 A020

0x4804 A024

0x4804 A028

IRQ_EOI

Timer IRQ

End-Of-Interrupt

IRQSTATUS_ Timer IRQSTATUS

RAW Raw

0x4802 E028

0x4802 E02C

0x4804 0028

0x4804 002C

0x4804 2028

0x4804 202C

0x4804 4028

0x4804 402C

0x4804 6028

0x4804 602C

0x4804 8028

0x4804 802C

IRQSTATUS Timer IRQSTATUS

0x4804 A02C IRQSTATUS_ Timer IRQENABLE

SET Set

0x4802 E030

0x4802 E034

0x4804 0030

0x4804 0034

0x4804 2030

0x4804 2034

0x4804 4030

0x4804 4034

0x4804 6030

0x4804 6034

0x4804 8030

0x4804 8034

0x4804 A030

IRQSTATUS_ Timer IRQENABLE

CLR Clear

0x4804 A034

IRQWAKEEN Timer IRQ Wakeup

Enable

0x4802 E038

0x4802 E03C

0x4802 E040

0x4802 E044

0x4804 0038

0x4804 003C

0x4804 0040

0x4804 0044

0x4804 2038

0x4804 203C

0x4804 2040

0x4804 2044

0x4804 4038

0x4804 403C

0x4804 4040

0x4804 4044

0x4804 6038

0x4804 603C

0x4804 6040

0x4804 6044

0x4804 8038

0x4804 803C

0x4804 8040

0x4804 8044

0x4804 A038

0x4804 A03C

0x4804 A040

0x4804 A044

TCLR

TCRR

TLDR

TTGR

Timer Control

Timer Counter

Timer Load

Timer Trigger

(1) All Timer registers are: 32-bit register accessible in 16-bit mode and use little-endian addressing.

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Table 8-101. Timer1-7 Registers (continued)

TIMER1 HEX

ADDRESS

TIMER2 HEX

ADDRESS

TIMER3 HEX

ADDRESS

TIMER4 HEX

ADDRESS

TIMER5 HEX

ADDRESS

TIMER6 HEX

ADDRESS

TIMER7 HEX

ADDRESS

ACRONYM

REGISTER NAME

0x4802 E048

0x4804 0048

0x4804 2048

0x4804 4048

0x4804 6048

0x4804 8048

0x4804 A048

TWPS

Timer Write Posted

Status

0x4802 E04C

0x4802 E050

0x4802 E054

0x4804 004C

0x4804 0050

0x4804 0054

0x4804 204C

0x4804 2050

0x4804 2054

0x4804 404C

0x4804 4050

0x4804 4054

0x4804 604C

0x4804 6050

0x4804 6054

0x4804 804C

0x4804 8050

0x4804 8054

0x4804 A04C

0x4804 A050

0x4804 A054

TMAR

TCAR1

TSICR

Timer Match

Timer Capture

Timer Synchronous

Interface Control

0x4802 E058

0x4804 0058

0x4804 2058

0x4804 4058

0x4804 6058

0x4804 8058

0x4804 A058

TCAR2

Timer Capture

Table 8-102. Watchdog Timer Registers

HEX ADDRESS

0x480C 2000

0x480C 2010

0x480C 2014

0x480C 2018

0x480C 201C

0x480C 2020

0x480C 2024

0x480C 2028

0x480C 202C

0x480C 2030

0x480C 2034

0x480C 2044

0x480C 2048

0x480C 2050

0x480C 2054

0x480C 2058

0x480C 205C

0x480C 2060

0x480C 2064

ACRONYM

WIDR

REGISTER NAME

IP Revision Identifier

OCP interface parameters

Status information

WDSC

WDST

WISR

Interrupt events pending

Interrupt events control

Wakeup events control

Counter prescaler control

Internal counter value

Timer load value

WIER

WWER

WCLR

WCRR

WLDR

WTGR

Watchdog counter reload

Write posting bits

WWPS

WDLY

Event detection delay value

Start-stop value

WSPR

WIRQEOI

WIRQSTATRAW

WIRQSTAT

WIRQENSET

WIRQENCLR

WIRQWAKEEN

Software End Of Interrupt

IRQ unmasked status

IRQ masked status

IRQ enable

IRQ enable clear

IRQ wakeup events control

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8.19.2 Timer Electrical/Data Timing

Table 8-103. Timing Requirements for Timer

(see Figure 8-88)

NO.

MIN

4P⁽¹⁾

MAX UNIT

1

2

t_w(EVTIH)

t_w(EVTIL)

Pulse duration, high

Pulse duration, low

ns

(1) P = module clock.

Table 8-104. Switching Characteristics Over Recommended Operating Conditions for Timer

(see Figure 8-88)

NO.

3

PARAMETER

Pulse duration, high

MIN

4P-3⁽¹⁾

MAX UNIT

t_w(EVTOH)

t_w(EVTOL)

ns

4

Pulse duration, low

(1) P = module clock.

1

2

TCLKIN

3

4

TIMx_OUT

Figure 8-88. Timer Timing

282

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8.20 Universal Asynchronous Receiver/Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from a peripheral device and

parallel-to-serial conversion on data received from the CPU. The device provides up to three UART

peripheral interfaces, depending on the selected pin multiplexing.

Each UART has the following features:

•

Selectable UART/IrDA (SIR/MIR)/CIR modes

Dual 64-entry FIFOs for received and transmitted data payload

Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt

generation

•

Baud-rate generation based upon programmable divisors N (N=1…16384)

Two DMA requests and one interrupt request to the system

Can connect to any RS-232 compliant device.

UART functions include:

•

Baud-rate up to 3.6 Mbit/s

Programmable serial interfaces characteristics

–

5, 6, 7, or 8-bit characters

Even, odd, or no parity-bit generation and detection

1, 1.5, or 2 stop-bit generation

Flow control: hardware (RTS/CTS) or software (XON/XOFF)

•

Additional modem control functions (UART0_DTR, UART0_DSR, UART0_DCD, and UART0_RIN) for

UART0 only; UART1 and UART2 do not support full-flow control signaling.

IR-IrDA functions include:

•

Support of IrDA 1.4 slow infrared (SIR, baud-rate up to 115.2 Kbits/s), medium infrared (MIR,

baud-rate up to 1.152 Mbits/s) and fast infrared (FIR baud-rate up to 4.0 Mbits/s) communications

Supports framing error, cyclic redundancy check (CRC) error, illegal symbol (FIR), and abort pattern

(SIR, MIR) detection

8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors.

IR-CIR functions include:

•

Consumer infrared (CIR) remote control mode with programmable data encoding

Free data format (supports any remote control private standards)

Selectable bit rate and configurable carrier frequency.

For more detailed information on the UART peripheral, see the UART chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

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8.20.1 UART Peripheral Register Descriptions

Table 8-105 lists the UART register name summary. Table 8-106 shows the UART registers along with

their configuration requirements.

Table 8-105. UART Register Summary

ACRONYM

RHR

REGISTER NAME

Receive Holding

Transmit Holding

Interrupt Enable

ACRONYM

RXFLH

BLR

REGISTER NAME

Receive Frame Length High

BOF Control

THR

IER

ACREG

SCR

Auxilliary Control

IIR

Interrupt Identification

FIFO Control

Supplementary Control

Supplementary Status

BOF Length

FCR

SSR

LCR

Line Control

EBLR

MVR

MCR

Modem Control

Module Version

LSR

Line Status

SYSC

SYSS

WER

System Configuration

System Status

MSR

Modem Status

SPR

Scratchpad

Wake-up Enable

TCR

Transmission Control

Trigger Level

CFPS

DLL

Carrier Frequency Prescaler

Divisor Latch Low

TLR

MDR1

MDR2

SFLSR

RESUME

SFREGL

SFREGH

TXFLL

TXFLH

RXFLL

Mode Definition 1

Mode Definition 2

Status FIFO Line Status

Resume

DLH

Divisor Latch High

UART Autobauding Status

Enhanced Feature

UART XON1 Character

UART XON2 Character

UART XOFF1 Character

UART XOFF2 Character

IrDA Address 1

UASR

EFR

XON1

XON2

XOFF1

XOFF2

ADDR1

ADDR2

Status FIFO Low

Status FIFO High

Transmit Frame Length Low

Transmit Frame Length High

Receive Frame Length Low

IrDA Address 2

Table 8-106. UART Registers Configuration Requirements^(1)(2)(3)

REGISTER

UART0 HEX

ADDRESS

UART1 HEX

ADDRESS

UART2 HEX

ADDRESS

LCR[7] = 1 and LCR[7:0]

LCR[7] = 0

LCR[7:0] = 0xBF

≠ 0xBF

READ

WRITE

THR

IER

READ

DLL

WRITE

DLL

READ

DLL

WRITE

0x4802 0000

0x4802 0004

0x4802 0008

0x4802 000C

0x4802 0010

0x4802 2000

0x4802 2004

0x4802 2008

0x4802 200C

0x4802 2010

0x4802 4000

0x4802 4004

0x4802 4008

0x4802 400C

0x4802 4010

RHR

IER

DLL

DLH

EFR

LCR

DLH

IIR

DLH

EFR

LCR

IIR

FCR

LCR

FCR

LCR

MCR

LCR

MCR

XON1/

ADDR1

0x4802 0014

0x4802 0018

0x4802 001C

0x4802 2014

0x4802 2018

0x4802 201C

0x4802 4014

0x4802 4018

0x4802 401C

LSR

-

LSR

-

XON2/

ADDR2

XON2/

ADDR2

MSR/TCR

SPR/TLR

TCR

MSR/TCR

SPR/TLR

TCR

XOFF1/

TCR

XOFF1/

TCR

SPR/TLR

XOFF2/

TLR

XOFF2/

TLR

0x4802 0020

0x4802 0024

0x4802 0028

0x4802 2020

0x4802 2024

0x4802 2028

0x4802 4020

0x4802 4024

0x4802 4028

MDR1

MDR2

SFLSR

MDR1

MDR2

TXFLL

MDR1

MDR2

SFLSR

MDR1

MDR2

TXFLL

MDR1

MDR2

SFLSR

MDR1

MDR2

TXFLL

(1) The transmission control register (TCR) and the trigger level register (TLR) are accessible only when EFR[4]=1 and MCR[6]=1.

(2) MCR[7:5] and FCR[5:4] can only be written when EFR[4]=1.

(3) In UART modes, IER[7:4] can only be written when EFR[4]=1. In IrDA/CIR modes, EFR[4] has no impact on the access to IER[7:4].

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Table 8-106. UART Registers Configuration Requirements (continued)

REGISTER

UART0 HEX

ADDRESS

UART1 HEX

ADDRESS

UART2 HEX

ADDRESS

LCR[7] = 1 and LCR[7:0]

LCR[7] = 0

READ

LCR[7:0] = 0xBF

≠ 0xBF

WRITE

TXFLH

RXFLL

RXFLH

BLR

READ

RESUME

SFREGL

SFREGH

UASR

-

WRITE

READ

RESUME

SFREGL

SFREGH

UASR

-

WRITE

0x4802 002C

0x4802 0030

0x4802 0034

0x4802 0038

0x4802 003C

0x4802 0040

0x4802 0044

0x4802 0048

0x4802 004C

0x4802 0050

0x4802 0054

0x4802 0058

0x4802 005C

0x4802 0060

0x4802 202C

0x4802 2030

0x4802 2034

0x4802 2038

0x4802 203C

0x4802 2040

0x4802 2044

0x4802 2048

0x4802 204C

0x4802 2050

0x4802 2054

0x4802 2058

0x4802 205C

0x4802 2060

0x4802 402C

0x4802 4030

0x4802 4034

0x4802 4038

0x4802 403C

0x4802 4040

0x4802 4044

0x4802 4048

0x4802 404C

0x4802 4050

0x4802 4054

0x4802 4058

0x4802 405C

0x4802 4060

RESUME

SFREGL

SFREGH

BLR

TXFLH

RXFLL

RXFLH

-

ACREG

SCR

ACREG

SCR

-

SCR

SSR

SCR

SSR

SCR

SSR

SSR[2]

EBLR

-

SSR[2]

EBLR

-

MVR

-

MVR

SYSC

SYSS

WER

CFPS

-

MVR

SYSC

SYSS

WER

CFPS

-

SYSC

SYSS

WER

CFPS

-

SYSC

WER

CFPS

-

WER

CFPS

-

WER

CFPS

-

0x4802 0064 -

0x4802 00C4

0x4802 2064 -

0x4802 20C4

0x4802 4064 -

0x4802 40C4

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8.20.2 UART Electrical/Data Timing

Table 8-107. Timing Requirements for UART

(see Figure 8-89)

NO.

MIN

0.96U⁽¹⁾

P⁽²⁾

MAX UNIT

4

5

t_w(RX)

Pulse width, receive data bit, 15/30/100pF high or low

Pulse width, receive start bit, 15/30/100pF high or low

Delay time, transmit start bit to transmit data

1.05U⁽¹⁾

ns

t_w(CTS)

t_d(RTS-TX)

t_d(CTS-TX)

Delay time, receive start bit to transmit data

P⁽²⁾

(1) U = UART baud time = 1/programmed baud rate

(2) P = clock period of the reference clock (FCLK, usually 48 MHz).

Table 8-108. Switching Characteristics Over Recommended Operating Conditions for UART

(see Figure 8-89)

NO.

PARAMETER

MIN

MAX UNIT

15 pF

30 pF

100 pF

5

f_(baud)

Maximum programmable baud rate

0.23

0.115

MHz

2

3

t_w(TX)

Pulse width, transmit data bit, 15/30/100 pF high or low

Pulse width, transmit start bit, 15/30/100 pF high or low

U - 2⁽¹⁾

U + 2⁽¹⁾

ns

t_w(RTS)

(1) U = UART baud time = 1/programmed baud rate

3

2

Start

Bit

UARTx_TXD

Data Bits

5

4

Start

Bit

UARTx_RXD

Data Bits

Figure 8-89. UART Timing

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8.21 Universal Serial Bus (USB2.0)

The device includes two USB2.0 modules which support the Universal Serial Bus Specification Revision

2.0. The following are some of the major USB features that are supported:

•

USB 2.0 peripheral at high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)

USB 2.0 host at HS, FS, and low speed (LS: 1.5 Mbps)

Each endpoint (other than endpoint 0, control only) can support all transfer modes (control, bulk,

interrupt, and isochronous)

•

Supports high-bandwidth ISO mode

Supports 16 Transmit (TX) and 16 Receive (RX) endpoints including endpoint 0

FIFO RAM - 32K endpoint - Programmable size

Includes two integrated PHYs; requires a low-jitter 24-MHz source clock for its PLL

RNDIS-like mode for terminating RNDIS-type protocols without using short-packet termination for

support of MSC applications.

The USB2.0 modules do not support the following features:

•

On-chip charge pump (VBUS power must be generated external to the device)

RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes

Endpoint max USB packet sizes that do not conform to the USB2.0 spec (for FS/LS: 8, 16, 32, 64, and

1023 are defined; for HS: 64, 128, 512, and 1024 are defined).

For more detailed information on the USB2.0 peripheral, see the USB2.0 chapter in the AM38x Sitara

ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7). For detailed

information on USB board design and layout guidelines, see the USB 2.0 Board Design and Layout

Guidelines application report (literature number SPRAAR7)

8.21.1 USB2.0 Peripheral Register Descriptions

Table 8-109. USB2.0 Submodules

SUBMODULE

SUBMODULE NAME

ADDRESS OFFSET

0x0000

0x1000

0x1800

0x2000

0x3000

0x4000

USBSS registers

USB0 controller registers

USB1 controller registers

CPPI DMA controller registers

CPPI DMA scheduler registers

CPPI DMA Queue Manager registers

Table 8-110. USB Subsystem (USBSS) Registers⁽¹⁾

HEX ADDRESS

0x4740 0000

ACRONYM

REVREG

-

REGISTER NAME

USBSS REVISION

Reserved

0x4740 0004 - 0x4740 000C

0x4740 0010

SYSCONFIG

-

USBSS SYSCONFIG

Reserved

0x4740 0014 - 0x4740 001C

0x4740 0020

EOI

USBSS IRQ_EOI

0x4740 0024

IRQSTATRAW

IRQSTAT

IRQENABLER

IRQCLEARR

USBSS IRQ_STATUS_RAW

USBSS IRQ_STATUS

USBSS IRQ_ENABLE_SET

USBSS IRQ_ENABLE_CLR

0x4740 0028

0x4740 002C

0x4740 0030

(1) USBSS registers contain the registers that are used to control at the global level and apply to all submodules.

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Table 8-110. USB Subsystem (USBSS) Registers (continued)

HEX ADDRESS

0x4740 0034 - 0x4740 00FC

0x4740 0100

ACRONYM

REGISTER NAME

-

Reserved

IRQDMATHOLDTX00

IRQDMATHOLDTX01

IRQDMATHOLDTX02

IRQDMATHOLDTX03

IRQDMATHOLDRX00

IRQDMATHOLDRX01

IRQDMATHOLDRX02

IRQDMATHOLDRX03

IRQDMATHOLDTX10

IRQDMATHOLDTX11

IRQDMATHOLDTX12

IRQDMATHOLDTX13

IRQDMATHOLDRX10

IRQDMATHOLDRX11

IRQDMATHOLDRX12

IRQDMATHOLDRX13

IRQDMAENABLE0

USBSS IRQ_DMA_THRESHOLD_TX0_0

USBSS IRQ_DMA_THRESHOLD_TX0_1

USBSS IRQ_DMA_THRESHOLD_TX0_2

USBSS IRQ_DMA_THRESHOLD_TX0_3

USBSS IRQ_DMA_THRESHOLD_RX0_0

USBSS IRQ_DMA_THRESHOLD_RX0_1

USBSS IRQ_DMA_THRESHOLD_RX0_2

USBSS IRQ_DMA_THRESHOLD_RX0_3

USBSS IRQ_DMA_THRESHOLD_TX1_0

USBSS IRQ_DMA_THRESHOLD_TX1_1

USBSS IRQ_DMA_THRESHOLD_TX1_2

USBSS IRQ_DMA_THRESHOLD_TX1_3

USBSS IRQ_DMA_THRESHOLD_RX1_0

USBSS IRQ_DMA_THRESHOLD_RX1_1

USBSS IRQ_DMA_THRESHOLD_RX1_2

USBSS IRQ_DMA_THRESHOLD_RX1_3

USBSS IRQ_DMA_ENABLE_0

0x4740 0104

0x4740 0108

0x4740 010C

0x4740 0110

0x4740 0114

0x4740 0118

0x4740 011C

0x4740 0120

0x4740 0124

0x4740 0128

0x4740 012C

0x4740 0130

0x4740 0134

0x4740 0138

0x4740 013C

0x4740 0140

0x4740 0144

IRQDMAENABLE1

USBSS IRQ_DMA_ENABLE_1

0x4740 0148 - 0x4740 01FC

0x4740 0200

-

Reserved

IRQFRAMETHOLDTX00

IRQFRAMETHOLDTX01

IRQFRAMETHOLDTX02

IRQFRAMETHOLDTX03

IRQFRAMETHOLDRX00

IRQFRAMETHOLDRX01

IRQFRAMETHOLDRX02

IRQFRAMETHOLDRX03

IRQFRAMETHOLDTX10

IRQFRAMETHOLDTX11

IRQFRAMETHOLDTX12

IRQFRAMETHOLDTX13

IRQFRAMETHOLDRX10

IRQFRAMETHOLDRX11

IRQFRAMETHOLDRX12

IRQFRAMETHOLDRX13

IRQFRAMEENABLE0

IRQFRAMEENABLE1

-

USBSS IRQ_FRAME_THRESHOLD_TX0_0

USBSS IRQ_FRAME_THRESHOLD_TX0_1

USBSS IRQ_FRAME_THRESHOLD_TX0_2

USBSS IRQ_FRAME_THRESHOLD_TX0_3

USBSS IRQ_FRAME_THRESHOLD_RX0_0

USBSS IRQ_FRAME_THRESHOLD_RX0_1

USBSS IRQ_FRAME_THRESHOLD_RX0_2

USBSS IRQ_FRAME_THRESHOLD_RX0_3

USBSS IRQ_FRAME_THRESHOLD_TX1_0

USBSS IRQ_FRAME_THRESHOLD_TX1_1

USBSS IRQ_FRAME_THRESHOLD_TX1_2

USBSS IRQ_FRAME_THRESHOLD_TX1_3

USBSS IRQ_FRAME_THRESHOLD_RX1_0

USBSS IRQ_FRAME_THRESHOLD_RX1_1

USBSS IRQ_FRAME_THRESHOLD_RX1_2

USBSS IRQ_FRAME_THRESHOLD_RX1_3

USBSS IRQ_FRAME_ENABLE_0

0x4740 0204

0x4740 0208

0x4740 020C

0x4740 0210

0x4740 0214

0x4740 0218

0x4740 021C

0x4740 0220

0x4740 0224

0x4740 0228

0x4740 022C

0x4740 0230

0x4740 0234

0x4740 0238

0x4740 023C

0x4740 0240

0x4740 0244

USBSS IRQ_FRAME_ENABLE_1

0x4740 0248 - 0x4740 0FFC

Reserved

Table 8-111. USB0 Controller Registers

HEX ADDRESS

0x4740 1000

ACRONYM

USB0REV

-

REGISTER NAME

USB0 REVISION

Reserved

0x4740 1004 - 0x4740 1010

0x4740 1014

USB0CTRL

USB0STAT

-

USB0 Control

USB0 Status

Reserved

0x4740 1018

0x4740 101C

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Table 8-111. USB0 Controller Registers (continued)

HEX ADDRESS

0x4740 1020

0x4740 1024

0x4740 1028

0x4740 102C

0x4740 1030

0x4740 1034

0x4740 1038

0x4740 103C

0x4740 1040

0x4740 1044

ACRONYM

USB0IRQMSTAT

USB0IRQEOI

REGISTER NAME

USB0 IRQ_MERGED_STATUS

USB0 IRQ_EOI

USB0IRQSTATRAW0

USB0IRQSTATRAW1

USB0IRQSTAT0

USB0IRQSTAT1

USB0IRQENABLESET0

USB0IRQENABLESET1

USB0IRQENABLECLR0

USB0IRQENABLECLR1

-

USB0 IRQ_STATUS_RAW_0

USB0 IRQ_STATUS_RAW_1

USB0 IRQ_STATUS_0

USB0 IRQ_STATUS_1

USB0 IRQ_ENABLE_SET_0

USB0 IRQ_ENABLE_SET_1

USB0 IRQ_ENABLE_CLR_0

USB0 IRQ_ENABLE_CLR_1

Reserved

0x4740 1048 - 0x4740 106C

0x4740 1070

USB0TXMODE

USB0RXMODE

-

USB0 Tx Mode

0x4740 1074

USB0 Rx Mode

0x4740 1078 - 0x4740 107C

0x4740 1080

Reserved

USB0GENRNDISEP1

USB0GENRNDISEP2

USB0GENRNDISEP3

USB0GENRNDISEP4

USB0GENRNDISEP5

USB0GENRNDISEP6

USB0GENRNDISEP7

USB0GENRNDISEP8

USB0GENRNDISEP9

USB0GENRNDISEP10

USB0GENRNDISEP11

USB0GENRNDISEP12

USB0GENRNDISEP13

USB0GENRNDISEP14

USB0GENRNDISEP15

-

USB0 Generic RNDIS Size EP1

USB0 Generic RNDIS Size EP2

USB0 Generic RNDIS Size EP3

USB0 Generic RNDIS Size EP4

USB0 Generic RNDIS Size EP5

USB0 Generic RNDIS Size EP6

USB0 Generic RNDIS Size EP7

USB0 Generic RNDIS Size EP8

USB0 Generic RNDIS Size EP9

USB0 Generic RNDIS Size EP10

USB0 Generic RNDIS Size EP11

USB0 Generic RNDIS Size EP12

USB0 Generic RNDIS Size EP13

USB0 Generic RNDIS Size EP14

USB0 Generic RNDIS Size EP15

Reserved

0x4740 1084

0x4740 1088

0x4740 108C

0x4740 1090

0x4740 1094

0x4740 1098

0x4740 109C

0x4740 10A0

0x4740 10A4

0x4740 10A8

0x4740 10AC

0x4740 10B0

0x4740 10B4

0x4740 10B8

0x4740 10BC - 0x4740 10CC

0x4740 10D0

USB0AUTOREQ

USB0SRPFIXTIME

USB0TDOWN

USB0 Auto Req

0x4740 10D4

USB0 SRP Fix Time

0x4740 10D8

USB0 Teardown

0x4740 10DC

-

Reserved

0x4740 10E0

USB0UTMI

USB0 PHY UTMI

0x4740 10E4

USB0UTMILB

USB0 MGC UTMI Loopback

USB0 Mode

0x4740 10E8

USB0MODE

0x4740 10E8 - 0x4740 13FF

0x4740 1400 - 0x4740 159C

0x4740 15A0 - 0x4740 17FC

-

Reserved

-

USB0 Mentor Core Registers

Reserved

-

Table 8-112. USB1 Controller Registers

HEX ADDRESS

0x4740 1800

ACRONYM

USB1REV

-

REGISTER NAME

USB1 Revision

Reserved

0x4740 1804 - 0x4740 1810

0x4740 1814

USB1CTRL

USB1STAT

USB1 Control

USB1 Status

0x4740 1818

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Table 8-112. USB1 Controller Registers (continued)

HEX ADDRESS

0x4740 181C

ACRONYM

-

REGISTER NAME

Reserved

0x4740 1820

USB1IRQMSTAT

USB1IRQEOI

USB1 IRQ_MERGED_STATUS

USB1 IRQ_EOI

0x4740 1824

0x4740 1828

USB1IRQSTATRAW0

USB1IRQSTATRAW1

USB1IRQSTAT0

USB1IRQSTAT1

USB1IRQENABLESET0

USB1IRQENABLESET1

USB1IRQENABLECLR0

USB1IRQENABLECLR1

-

USB1 IRQ_STATUS_RAW_0

USB1 IRQ_STATUS_RAW_1

USB1 IRQ_STATUS_0

USB1 IRQ_STATUS_1

USB1 IRQ_ENABLE_SET_0

USB1 IRQ_ENABLE_SET_1

USB1 IRQ_ENABLE_CLR_0

USB1 IRQ_ENABLE_CLR_1

Reserved

0x4740 182C

0x4740 1830

0x4740 1834

0x4740 1838

0x4740 183C

0x4740 1840

0x4740 1844

0x4740 1848 - 0x4740 186C

0x4740 1870

USB1TXMODE

USB1RXMODE

-

USB1 Tx Mode

0x4740 1874

USB1 Rx Mode

0x4740 1878 - 0x4740 187C

0x4740 1880

Reserved

USB1GENRNDISEP1

USB1GENRNDISEP2

USB1GENRNDISEP3

USB1GENRNDISEP4

USB1GENRNDISEP5

USB1GENRNDISEP6

USB1GENRNDISEP7

USB1GENRNDISEP8

USB1GENRNDISEP9

USB1GENRNDISEP10

USB1GENRNDISEP11

USB1GENRNDISEP12

USB1GENRNDISEP13

USB1GENRNDISEP14

USB1GENRNDISEP15

-

USB1 Generic RNDIS Size EP1

USB1 Generic RNDIS Size EP2

USB1 Generic RNDIS Size EP3

USB1 Generic RNDIS Size EP4

USB1 Generic RNDIS Size EP5

USB1 Generic RNDIS Size EP6

USB1 Generic RNDIS Size EP7

USB1 Generic RNDIS Size EP8

USB1 Generic RNDIS Size EP9

USB1 Generic RNDIS Size EP10

USB1 Generic RNDIS Size EP11

USB1 Generic RNDIS Size EP12

USB1 Generic RNDIS Size EP13

USB1 Generic RNDIS Size EP14

USB1 Generic RNDIS Size EP15

Reserved

0x4740 1884

0x4740 1888

0x4740 188C

0x4740 1890

0x4740 1894

0x4740 1898

0x4740 189C

0x4740 18A0

0x4740 18A4

0x4740 18A8

0x4740 18AC

0x4740 18B0

0x4740 18B4

0x4740 18B8

0x4740 18BC - 0x4740 18CC

0x4740 18D0

USB1AUTOREQ

USB1SRPFIXTIME

USB1TDOWN

USB1 Auto Req

0x4740 18D4

USB1 SRP Fix Time

0x4740 18D8

USB1 Teardown

0x4740 18DC

-

Reserved

0x4740 18E0

USB1UTMI

USB1 PHY UTMI

0x4740 18E4

USB1UTMILB

USB1 MGC UTMI Loopback

USB1 Mode

0x4740 18E8

USB1MODE

0x4740 18E8 - 0x4740 1BFF

0x4740 1C00 - 0x4740 1D9C

0x4740 1DA0 - 0x4740 1FFC

-

Reserved

-

USB1 Mentor Core Registers

Reserved

-

Table 8-113. CPPI DMA Controller Registers

HEX ADDRESS

0x4740 2000

0x4740 2004

0x4740 2008

ACRONYM

DMAREVID

TDFDQ

REGISTER NAME

Revision

Teardown Free Descriptor Queue Control

Emulation Control

DMAEMU

290

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Table 8-113. CPPI DMA Controller Registers (continued)

HEX ADDRESS

0x4740 2010

0x4740 2014

ACRONYM

REGISTER NAME

DMAMEM1BA

CPPI Mem1 Base Address

CPPI Mem1 Mask Address

Reserved

DMAMEM1MASK

0x4740 200C - 0x4740 27FF

0x4740 2800

-

TXGCR0

Tx Channel 0 Global Configuration

Reserved

0x4740 2804

-

RXGCR0

RXHPCRA0

RXHPCRB0

-

0x4740 2808

Rx Channel 0 Global Configuration

Rx Channel 0 Host Packet Configuration A

Rx Channel 0 Host Packet Configuration B

Reserved

0x4740 280C

0x4740 2810

0x4740 2814 - 0x4740 281C

0x4740 2820

TXGCR1

-

Tx Channel 1 Global Configuration

Reserved

0x4740 2824

0x4740 2828

RXGCR1

RXHPCRA1

RXHPCRB1

-

Rx Channel 1 Global Configuration

Rx Channel 1 Host Packet Configuration A

Rx Channel 1 Host Packet Configuration B

Reserved

0x4740 282C

0x4740 2830

0x4740 2834 - 0x4740 283C

0x4740 2840

TXGCR2

-

Tx Channel 2 Global Configuration

Reserved

0x4740 2844

0x4740 2848

RXGCR2

RXHPCRA2

RXHPCRB2

-

Rx Channel 2 Global Configuration

Rx Channel 2 Host Packet Configuration A

Rx Channel 2 Host Packet Configuration B

Reserved

0x4740 284C

0x4740 2850

0x4740 2854 - 0x4740 285F

0x4740 2860

TXGCR3

-

Tx Channel 3 Global Configuration

Reserved

0x4740 2864

0x4740 2868

RXGCR3

RXHPCRA3

RXHPCRB3

-

Rx Channel 3 Global Configuration

Rx Channel 3 Host Packet Configuration A

Rx Channel 3 Host Packet Configuration B

...

0x4740 286C

0x4740 2870

0x4740 2880 - 0x4740 2B9F

0x4740 2BA0

TXGCR29

-

Tx Channel 29 Global Configuration

Reserved

0x4740 2BA4

0x4740 2BA8

RXGCR29

RXHPCRA29

RXHPCRB29

-

Rx Channel 29 Global Configuration

Rx Channel 29 Host Packet Configuration A

Rx Channel 29 Host Packet Configuration B

Reserved

0x4740 2BAC

0x4740 2BB0

0x4740 2BB4 - 0x4740 2FFF

Table 8-114. CPPI DMA Scheduler Registers

HEX ADDRESS

0x4740 3000

ACRONYM

REGISTER NAME

DMA_SCHED_CTRL

CPPI DMA Scheduler Control Register

Reserved

0x4740 3804 - 0x4740 38FF

0x4740 3800

-

WORD0

WORD1

…

CPPI DMA Scheduler Table Word 0

CPPI DMA Scheduler Table Word 1

…

0x4740 3804

…

0x4740 38F8

WORD62

WORD63

-

CPPI DMA Scheduler Table Word 62

CPPI DMA Scheduler Table Word 63

Reserved

0x4740 38FC

0x4740 38FF - 0x4740 3FFF

Peripheral Information and Timings

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Table 8-115. CPPI DMA Queue Manager Registers

HEX ADDRESS

0x4740 4000

ACRONYM

QMGRREVID

-

REGISTER NAME

Queue Manager Revision

Reserved

0x4740 4004

0x4740 4008

DIVERSION

FDBSC0

FDBSC1

FDBSC2

FDBSC3

FDBSC4

FDBSC5

FDBSC6

FDBSC7

-

Queue Manager Queue Diversion

0x4740 4020

Queue Manager Free Descriptor/Buffer Starvation Count 0

Queue Manager Free Descriptor/Buffer Starvation Count 1

Queue Manager Free Descriptor/Buffer Starvation Count 2

Queue Manager Free Descriptor/Buffer Starvation Count 3

Queue Manager Free Descriptor/Buffer Starvation Count 4

Queue Manager Free Descriptor/Buffer Starvation Count 5

Queue Manager Free Descriptor/Buffer Starvation Count 6

Queue Manager Free Descriptor/Buffer Starvation Count 7

Reserved

0x4740 4024

0x4740 4028

0x4740 402C

0x4740 4030

0x4740 4034

0x4740 4038

0x4740 403C

0x4740 4030 - 0x4740 407C

0x4740 4080

LRAM0BASE

LRAM0SIZE

LRAM1BASE

-

Queue Manager Linking RAM Region 0 Base Address

Queue Manager Linking RAM Region 0 Size

Queue Manager Linking RAM Region 1 Base Address

Reserved

0x4740 4084

0x4740 4088

0x4740 408C

0x4740 4090

PEND0

PEND1

PEND2

PEND3

PEND4

-

Queue Manager Queue Pending 0

0x4740 4094

Queue Manager Queue Pending 1

0x4740 4098

Queue Manager Queue Pending 2

0x4740 409C

Queue Manager Queue Pending 3

0x4740 40A0

Queue Manager Queue Pending 4

0x4740 40A4 - 0x4740 4FFF

0x4740 5000 + 16xR

0x4740 5000 + 16xR + 4

0x4740 50F8 - 0x4740 5FFF

0x4740 6000 + 16xN

0x4740 6004 + 16xN

0x4740 6008 + 16xN

0x4740 600C + 16xN

0x4740 69C0 - 0x4740 6FFF

0x4740 7000 + 16xN

0x4740 7004 + 16xN

0x4740 7008 + 16xN

0x4740 700C + 16xN

0x4740 79C0 - 0x4740 7FFF

Reserved

QMEMRBASEr

QMEMRCTRLr

-

Memory Region R Base Address (R ranges from 0 to 15)

Memory Region R Control (R ranges from 0 to 15)

Reserved

CTRLAn

CTRLBn

CTRLCn

CTRLDn

-

Queue N Register A (N ranges from 0 to 155)

Queue N Register B (N ranges from 0 to 155)

Queue N Register C (N ranges from 0 to 155)

Queue N Register D (N ranges from 0 to 155)

Reserved

QSTATAn

QSTATBn

QSTATCn

-

Queue N Status A (N ranges from 0 to 155)

Queue N Status B (N ranges from 0 to 155)

Queue N Status C (N ranges from 0 to 155)

Reserved

-

Reserved

292

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8.21.2 USB2.0 Electrical Data/Timing

Table 8-116. Switching Characteristics Over Recommended Operating Conditions for USB2.0

(see Figure 8-90)

LOW SPEED

1.5 Mbps

FULL SPEED

12 Mbps

HIGH SPEED

480 Mbps

NO.

PARAMETER

UNIT

MIN

75

MAX

MIN

4

MAX

MIN

0.5

–

MAX

1

2

3

4

5

t_r(D)

Rise time, USB_DP and USB_DN signals⁽¹⁾

Fall time, USB_DP and USB_DN signals⁽¹⁾

Rise/Fall time, matching⁽²⁾

Output signal cross-over voltage⁽¹⁾

Source (Host) Driver jitter, next transition

Function Driver jitter, next transition

Source (Host) Driver jitter, paired transition⁽⁴⁾

Function Driver jitter, paired transition

Pulse duration, EOP transmitter

Pulse duration, EOP receiver

300

125

2

20

ns

%

t_f(D)

75

4

t_rfM

80

90 111.11

–

V_CRS

1.3

2

–

(3)

V

t_jr(source)NT

t_jr(FUNC)NT

t_jr(source)PT

t_jr(FUNC)PT

t_w(EOPT)

t_w(EOPR)

t_(DRATE)

2

ns

(3)

25

2

6

1

10

1

7

8

9

1250

670

1500

160

82

175

–

Data Rate

1.5

–

12

49.5

10.1

480 Mb/s

49.5

10.1 kΩ

10 Z_DRV

Driver Output Resistance

–

28

40.5

9.9

Ω

11 USB_R1

USB reference resistor

9.9

10.1

9.9

(1) Low Speed: C_L= 200 pF, Full Speed: C_L= 50 pF, High Speed: C_L= 50 pF

(2) t_RFM= (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]

(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7, Electrical.

(4) t_jr= t_px(1)- t_px(0)

t

per − jr

USB_DN

90% V

OH

V

CRS

10% V

OL

USB_DP

t

f

t

r

Figure 8-90. USB2.0 Integrated Transceiver Interface Timing

USB

USB_V_SSREF

USB_R1

10 K Ω 1ꢀ^(A)

A. Place the 10 K Ω 1ꢀ aꢁ clꢂꢁe tꢂ the ꢃeꢄvce aꢁ ꢅꢂꢁꢁvile.

Figure 8-91. USB Reference Resistor Routing

Peripheral Information and Timings

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the

processors, generate code, develop algorithm implementations, and fully integrate and debug software

and hardware modules. The tool's support documentation is electronically available within the Code

Composer Studio™ Integrated Development Environment (IDE).

The following products support development of AM389x MPU applications:

Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):

including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software ( DSP/BIOS™), which provides the basic run-time target

software needed to support any Sitara ARM MPU application.

Hardware Development Tools: Extended Development System ( XDS™) Emulator

For a complete listing of development-support tools for the AM389x Sitara™ ARM MPU platform, visit the

Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest

TI field sales office or authorized distributor.

9.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

MPUs and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (e.g.,

XAM3894CYG). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).

Device development evolutionary flow:

X

Experimental device that is not necessarily representative of the final device's electrical

specifications and may not use production assembly flow.

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications.

null

Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, CYG), the temperature range (for example, blank is the default commercial

operating case temperature range), and the device speed range (for example, blank is the default

[1.0-GHz ARM]). Figure 9-1 provides a legend for reading the complete device name for any AM389x

device.

For device part numbers and further ordering information of AM389x devices in the CYG package type,

see the TI website (www.ti.com) or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AM389x Sitara ARM

Microprocessors (MPUs) Silicon Errata (literature number SPRZ327).

(

)

(

)

AM3894

A

CYG

X

PREFIX

DEVICE SPEED RANGE

Blank = 1.0-GHz ARM (default)

120 = 1.2-GHz ARM

X = Experimental device

Blank = Qualified device

150 = 1.5-GHz ARM

DEVICE

TEMPERATURE RANGE

Blank = 0°C to 85°C (default commercial operating case temperature)

ARM Cortex-A8 MPU:

AM3894

AM3892

PACKAGE TYPE^(A)

CYG = 1031-pin plastic BGA, with Pb-Free solder balls

SILICON REVISION

Blank = silicon revision 1.0

A = silicon revision 1.1

A. BGA = Ball-Grid Array.

Figure 9-1. Device Nomenclature

9.2 Documentation Support

The following documents describe the AM389x Sitara™ ARM MPUs. Copies of these documents are

available on the Internet at www.ti.com. Tip: Enter the literature number in the search box.

SPRUGX7 AM38x Sitara ARM Microporcessors (MPUs) Technical Reference Manual.

9.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and

help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

Device and Documentation Support

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10 Mechanical Packaging and Orderable Information

Table 10-1 shows the thermal resistance characteristics for the PBGA–CYG mechanical package.

10.1 Thermal Data for CYG

Table 10-1. Thermal Resistance Characteristics (PBGA Package) [CYG]

NO.

1

°C/W⁽¹⁾

0.21

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

2

3.93

(1) For proper device operation, a heatsink is required.

10.2 Packaging Information

The following packaging information and addendum reflect the most current data available for the

designated device(s). This data is subject to change without notice and without revision of this document.

296

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AM3894
厂家：	TEXAS INSTRUMENTS
描述：	AM389x Sitara ARM Microprocessors (MPUs) AM389x ARM的Sitara微处理器（MPU ）微处理器
文件：	总299页 (文件大小：2254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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