AM4378 [TI]
Sitara 处理器：Arm Cortex-A9、PRU-ICSS、3D 图形;
| 型号： | AM4378 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sitara 处理器：Arm Cortex-A9、PRU-ICSS、3D 图形 |
| 文件： | 总266页 (文件大小：3373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
AM437x Sitara™ 处理器
1 器件概述
1.1 特性
1
可用）
– 仿真和调试
• 亮点
– Sitara™ ARM® Cortex®-A9 32 位 RISC 处理
器，处理速度高达 1000MHz
– JTAG
– NEON™单指令多数据流 (SIMD) 协处理器和
矢量浮点 (VFPv3) 协处理器
– 嵌入式跟踪缓冲器
– 中断控制器
– 32KB L1 指令缓存和数据缓存
– 256KB L2 缓存或 L3 RAM
– 32 位 LPDDR2、DDR3 和 DDR3L 支持
• 片上存储器（共享 L3 RAM）
– 256KB 通用片上存储器控制器 (OCMC) 随机存
取存储器 (RAM)
– 通用存储器支持（NAND、NOR、SRAM），支
持高达 16 位的 ECC
– 可访问所有主机
– 支持保持以实现快速唤醒
– SGX530 图形引擎
– 显示子系统
– 可编程实时单元子系统和工业通信子系统 (PRU-
– 多达 512KB 内部 RAM 总量
（256KB ARM 存储器配置为 L3 RAM + 256KB
OCMC RAM）
ICSS)
– 实时时钟 (RTC)
• 外部存储器接口 (EMIF)
– DDR 控制器：
– 多达两个带集成 PHY 的 USB 2.0 高速双角色
（主机或设备）端口
– LPDDR2：266MHz·时钟（LPDDR2-533 数据
速率）
– 支持多达 2 个端口的 10、100 和 1000 以太网交
换机
– DDR3 和 DDR3L：400MHz 时钟（DDR-800
数据速率）
– 串行接口：
– 32 位数据总线
– 两个控制器局域网 (CAN) 端口
– 2GB 全部可寻址空间
– 六个 UART、两个 McASP、五个 McSPI、三
个 I2C 端口、一个 QSPI 和一个 HDQ 或 1-
Wire
– 支持一个 x32、两个 x16 或四个 x8 存储器器
件配置
• 通用存储器控制器 (GPMC)
– 安全性
– 灵活的 8 位和 16 位异步存储器接口，具有多达
七个片选（NAND、NOR、Muxed-NOR 和
SRAM）
– 加密硬件加速器（AES、SHA、RNG、DES
和 3DES）
– 安全引导（仅在 AM437x 高安全性
[AM437xHS] 器件上可用）
– 使用 BCH 代码，支持 4 位、8 位或 16 位 ECC
– 使用海明码来支持 1 位 ECC
– 两个 12 位逐次逼近寄存器 (SAR) ADC
– 多达三个 32 位增强型捕捉 (eCAP) 模块
– 多达三个增强型正交编码器脉冲 (eQEP) 模块
– 多达六个增强型高分辨率 PWM (eHRPWM) 模块
• MPU 子系统
• 错误定位器模块 (ELM)
– 与 GPMC 配合使用，以找到来自伴随多项式的数
据错误（在使用 BCH 算法时生成）的地址
– 根据 BCH 算法，支持 4 位、8 位和 16 位每 512
字节块错误定位
• 可编程实时单元子系统和工业通信子系统 (PRU-
– 具有高达 1000MHz 处理速度的 ARM Cortex-A9
32 位 RISC 微处理器
– 32KB L1 指令缓存和数据缓存
– 256KB L2 缓存(也可配置为 L3 RAM）
– 256KB 片上引导 ROM
ICSS)
– 支持的协议如 EtherCAT®， PROFIBUS®,
PROFINET®和 EtherNet/IP™、EnDat 2.2 等
– 两个可编程实时单元 (PRU) 子系统，每个子系统
有两个 PRU 内核
– 64KB 片上 RAM
– 安全控制模块 (SCM)（仅在 AM437xHS 器件上
– 每个内核都是一个能以 200MHz 运行的 32 位
加载和存储 RISC 处理器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SPRS851
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
– 具有单错检测（奇偶校验）功能的 12KB
(PRU-ICSS1)、4KB (PRU-ICSS0) 指令 RAM
– 三个可切换电源域（MPU 子系统、SGX530
[GFX]、外设和基础设施 [PER]）
– 具有单错检测（奇偶校验）功能的 8KB (PRU-
ICSS1)、4KB (PRU-ICSS0) 数据 RAM
– 动态电压频率缩放 (DVFS)
• 实时时钟 (RTC)
– 具有 64 位累加器的单周期 32 位乘法器
– 增强型 GPIO 模块对外部信号提供移入和移出
支持以及并行锁断
– 实时日期（年、月、日和星期几）和时间（小
时、分钟和秒）信息
– 内部 32.768kHz 振荡器、RTC 逻辑和 1.1V 内部
– 具有单错检测（奇偶校验）功能的 12KB（仅限
PRU-ICSS1）共享 RAM
– 三个 120 字节寄存器组，可被每个 PRU 访问
– 用于处理系统输入事件的中断控制器模块 (INTC)
– 用于将内部和外部主机连接到 PRU-ICSS 内部资
源的本地互连总线
LDO
– 独立上电复位 (RTC_PWRONRSTn) 输入
– 外部唤醒事件专用输入引脚 (RTC_WAKEUP)
– 可编程警报可生成用于唤醒的 PRCM 内部中断或
用于事件通知的 Cortex-A9 内部中断
– 可编程警报可与外部输出 (RTC_PMIC_EN) 配合
使用，以启用电源管理 IC，从而恢复非 RTC 电
源域
– PRU-ICSS 内的外设
– 一个带有流控制引脚的通用异步收发器
(UART) 端口，支持高达 12Mbps 的数据速率
• 外设
– 一个 eCAP 模块
– 2 个支持工业用以太网的 MII 以太网端口，例
如EtherCAT
– 多达两个带集成 PHY 的 USB 2.0 高速双角色
（主机或设备）端口
– 多达两个工业千兆位以太网 MAC
（10、100 和 1000Mbps）
– 1 个 MDIO 端口
– 集成开关
– 每个 MAC 都支持 MII、RMII 和 RGMII 以及
MDIO 接口
– 两种 PRU-ICSS 子系统支持工业通信
• 电源、复位和时钟管理 (PRCM) 模块
– 控制深度休眠模式的进入和退出
– 以太网 MAC 和交换机可独立于其它功能运行
– IEEE 1588v2 精密时间协议 (PTP)
– 多达两个 CAN 端口
– 负责休眠排序、电源域关闭排序、唤醒排序和电
源域打开排序
– 时钟
– 支持 CAN 版本 2 部分 A 和 B
– 多达两个多通道音频串行端口 (McASP)
– 高达 50MHz 的发送和接收时钟
– 集成高频率振荡器，用于为各种系统和外设时
钟生成参考时钟（19.2、24、25 和 26MHz）
– 支持子系统和外设的单独时钟使能和禁用控
制，帮助降低功耗
– 每个 McASP 端口具有多达四个串行数据引脚
并具有独立的 TX 和 RX 时钟
– 支持时分多路复用 (TDM)、内部 IC 声音 (I2S)
和类似格式
– 五个用于生成系统时钟（MPU 子系统、DDR
接口、USB 和外设 [MMC 和 SD、UART、
SPI、I2C]、L3、L4、以太网、GFX [SGX530]
以及 LCD 像素时钟）的 ADPLL
– 支持数字音频接口传输（SPDIF、IEC60958-1
和 AES-3 格式）
– 电源
– 两个不可切换电源域（RTC 和唤醒逻辑
[WAKE-UP]）
– 用于发送和接收的 FIFO 缓冲器（256 字节）
– 最多 6 个 UART
– 所有 UART 支持 IrDA 和 CIR 模式
– 所有 UART 支持 RTS 和 CTS 流量控制
– UART1 支持完整的调制解调器控制
– 多达五个主 McSPI 和从 McSPI
– McSPI0–McSPI2 支持多达四个片选
2
器件概述
版权 © 2014–2016, Texas Instruments Incorporated
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
– McSPI3 和 McSPI4 支持多达两个片选
– 高达 48MHz
– 一个四通道 SPI
被动和主动单色
4 位和 8 位单色被动面板接口支持（通过
抖动块支持 15 个灰度级）
RGB 8 位彩色被动面板接口支持（使用抖
动块的彩色面板支持 3375 种颜色）
–
–
–
–
– 支持串行 NOR FLASH 就地执行 (XIP)
– 一个 Dallas 单线®和 HDQ 串行接口
– 多达三个 MMC、SD 和 SDIO 端口
– 1 位、4 位和 8 位 MMC、SD 和 SDIO 模式
– 所有端口均为 1.8V 或 3.3V 操作
– 高达 48MHz 的时钟
– 支持卡检测和写保护
– 符合 MMC4.3 以及 SD 和 SDIO 2.0 规范
– 多达三个 I2C 主从接口
RGB 12 位、16 位、18 位和 24 位主动面
板接口支持（重复或抖动的编码像素值）
通过 RFBI 模块支持远程帧缓冲器（嵌入在
LCD 面板中）
通过 RFBI 模块局部刷新远程帧缓冲器
局部显示
–
–
–
8 位、9 位、12 位和 16 位接口 (TDM) 上
的多周期输出格式
– 标准模式（高达 100kHz）
– 快速模式（高达 400kHz）
– 多达六组通用 I/O (GPIO)
– 信号处理
–
对一个图形层（RGB 或 CLUT）和两个视
频层（YUV 4:2:2、RGB16 和 RGB24）的
覆盖和窗口化支持
– 每组 32 个 GPIO（与其他功能引脚进行多路
复用）
–
在显示接口上支持 RGB 24 位，可选择抖
动至 RGB 18 位像素输出加上 6 位帧速率
控制（空间和时间）
– GPIO 可用作中断输入（每组多达两个中断输
入）
– 多达 3 个外部 DMA 事件输入，此输入也可被用
作中断输入
–
–
–
–
–
–
透明颜色键（源和目标）
同步缓冲器更新
伽玛曲线支持
– 十二个 32 位通用定时器
– DMTIMER1 是用于操作系统 (OS) 节拍的 1ms
定时器
多缓冲器支持
裁切支持
颜色相位旋转
– DMTIMER4–DMTIMER7 为引脚输出
– 一个公共看门狗定时器
– 一个自由运行的 32kHz 高分辨率计数器
(synctimer32K)
– 一个安全看门狗计时器（仅在 AM437xHS 器件
上可用）
– 两个 12 位 SAR ADC（ADC0、ADC1）
– 每秒 867K 次采样
– 可从 8:1 模拟开关复用的八个模拟输入中任意
选择输入
– 可以对 ADC0 进行配置，使其作为 4、5 或 8
线电阻式触摸屏控制器 (TSC) 运行
– 多达三个 32 位 eCAP 模块
– SGX530 3D 图形引擎
– 拼图架构，每秒可提供多达 20M 个多边形
– 通用可扩展着色引擎是一款包含像素和顶点着
色功能的多线程引擎
– 可配置为三个捕捉输入或者三个备用 PWM 输
出
– 超过 Microsoft VS3.0、PS3.0 和 OGL2.0 的
高级着色功能集
– 多达六个增强型 eHRPWM 模块
– 具有时间和频率控制功能的 16 位专用时基计
数器
– Direct3D Mobile、OGL-ES 1.1 和 2.0 以及
OpenVG 1.0 的行业标准 API 支持
– 精细的任务切换、负载均衡和电源管理
– 高级几何 DMA 驱动型操作，最大程度地减少
CPU 交互
– 可编程高质量图像防锯齿
– 可配置为 6 个单端，6 个双边对称，或者 3
个双边不对称输出
– 多达三个 32 位 eQEP 模块
• 器件标识
– 厂家可编程电子熔丝组 (FuseFarm)
– 生产 ID
– 用于统一存储器架构中操作系统运行的完全虚
拟化存储器寻址
– 器件部件号（唯一的 JTAG ID）
– 设备版本（可由主机 ARM 读取）
– 安全密钥（仅在 AM437xHS 器件上可用）
– 功能标识
– 显示子系统
– 显示模式
–
可编程像素存储器格式（调色板化：每个
像素 1 位、2 位、4 位和 8 位；每个像素
RGB 16 位和 24 位；以及 YUV 4:2:2）
• 调试接口支持
– 用于 ARM（Cortex-A9 和 PRCM）和 PRU-
ICSS 调试的 JTAG 和 cJTAG
–
–
256 × 24 位项调色板（采用 RGB 格式）
高达 2048 × 2048 的分辨率
– 支持实时跟踪引脚（对于 Cortex-A9）
– 64KB 嵌入式跟踪缓冲器 (ETB)
– 显示支持
–
支持四种类型的显示：被动和主动彩色；
版权 © 2014–2016, Texas Instruments Incorporated
器件概述
3
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
– 支持器件边界扫描
– 支持 IEEE1500
• DMA
• 启动模式
– 通过锁存在 PWRONRSTn 复位输入引脚上升沿
的启动配置引脚来选择启动模式
• 摄像机
– 片上增强型 DMA 控制器 (EDMA) 搭载三个第三
方传送控制器 (TPTC) 和一个第三方通道控制器
(TPCC)，支持多达 64 个可编程逻辑通道和 8 个
QDMA 通道
– 双端口 8 位和 10 位 BT656 接口
– 双端口 8 位和 10 位（包括外部同步）
– 单端口 12 位
– YUV422/RGB422 和 BT656 输入格式
– RAW 格式
– EDMA 用于：
– 向/从片上存储器传送
– 向/从外部存储器（EMIF、GPMC 和从外设）
传送
– 高达 75MHz 的像素时钟频率
• 封装
• 处理器间通信 (IPC)
– 491 引脚 BGA 封装 (17 × 17mm)（后缀为
ZDN），0.65mm 焊球间距，采用过孔通道阵列
技术实现低成本布线
– 集成了基于硬件的 IPC 邮箱，以及用于 Cortex-
A9、PRCM 和 PRU-ICSS 之间进程同步的
Spinlock
1.2 应用
•
•
•
•
病患监控
•
•
•
•
条形码扫描仪
服务点
导航设备
工业自动化
便携式数据终端
便携式移动无线电
测试和测量
4
器件概述
版权 © 2014–2016, Texas Instruments Incorporated
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1.3 说明
TI AM437x 高性能处理器基于 ARM Cortex-A9 内核。
这些处理器通过 3D 图形加速得到增强，可实现丰富的图形用户界面，还配备了协处理器，用于进行确定性
实时处理（包括 EtherCAT、PROFIBUS、EnDat 等工业通信协议）。该器件支持高级操作系统 (HLOS)。
基于 Linux 的®可从 TI 免费获取。其它 HLOS 可从 TI 的设计网络和生态系统合作伙伴处获取。
这些器件支持对采用较低性能 ARM 内核的系统升级，并提供更新外设，包括 QSPI-NOR 和 LPDDR2 等存
储器选项。
这些处理器包含 功能方框图中显示的子系统，并且后跟相应的 “说明”中添加了更多信息 说明。
处理器子系统基于 ARM Cortex-A9 内核， PowerVR SGX™图形加速器子系统提供 3D 图形加速功能以支
持显示和高级用户界面。
可编程实时单元子系统和工业通信子系统 (PRU-ICSS) 与 ARM 内核分离，允许单独操作和计时，以实现更
高的效率和灵活性。PRU-ICSS 支持更多外设接口和 EtherCAT、PROFINET、EtherNet/IP、PROFIBUS、
Ethernet Powerlink、Sercos、EnDat 等实时协议。PRU-ICSS 可并行支持 EnDat 和另一个工业通信协议。
此外，凭借 PRU-ICSS 的可编程特性及其对引脚、事件和所有片上系统 (SoC) 资源的访问权限，该子系统
可以灵活地实现快速实时响应、专用数据处理操作以及定制外设接口，并灵活地减轻 SoC 其他处理器内核
的任务负载。
高性能互连为多个初启程序提供到内部和外部存储器控制器以及到片上外设的高带宽数据传送。该器件还提
供全面的时钟管理机制。
一个片上模数转换器 (ADC0) 可以与显示子系统相结合，提供集成触摸屏解决方案。另一个 ADC (ADC1) 可
与脉宽模块结合，创建闭环电机控制解决方案。
实 RTC 提供独立电源域的时钟基准。该时钟基准实现了电池供电的时钟基准。
摄像头接口提供了适用于单摄像头或双摄像头并行端口的配置。
每个 AM437x 器件都具有加密加速功能。仅 AM437xHS 器件具有安全引导功能，用于实现防克隆和非法软
件更新保护。有关安全引导和 HS 器件的更多信息，请与您的 TI 销售代表联系。
器件信息(1)
封装
器件型号
封装尺寸
AM4372ZDN
AM4376ZDN
AM4377ZDN
AM4378ZDN
AM4379ZDN
NFBGA (491)
NFBGA (491)
NFBGA (491)
NFBGA (491)
NFBGA (491)
17.0mm × 17.0mm
17.0mm × 17.0mm
17.0mm × 17.0mm
17.0mm × 17.0mm
17.0mm × 17.0mm
(1) 更多信息，请参阅节 7，机械、封装和可订购产品信息。
版权 © 2014–2016, Texas Instruments Incorporated
器件概述
5
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
1.4 功能方框图
Graphics
ARM
Cortex-A9
Up to 1000 MHz
Display
PowerVR
SGX
3D GFX
20 MTri/s
24-bit LCDCtrl (WXGA)
Touch Screen Controller (TSC)(A)
Processing: Overlay,
Resizing,Color Space
Conversion, and more
Quad Core
PRU-ICSS
EtherCAT,
PROFINET,
EtherNet/IP,
EnDat
32KB, 32KB L1
256KB L2, L3 RAM
64KB RAM
Crypto
256KB
L3 RAM
Secure Boot
(HS device only)
and more
L3 and L4 Interconnect
System Interface
UART x6
SPI x5
QSPI
EDMA
Timers x12
WDT
Camera Interface
(2x Parallel)
EMAC
2-port switch
10, 100, 1G
with 1588
(MII, RMII,
RGMII
MMC, SD,
SDIO x3
I2C x3
RTC
CAN x2
eHRPWM x6
eQEP, eCAP x3
USB 2.0 Dual-Role
+ PHY x2
and MDIO)
HDQ, 1-Wire
JTAG, ETB
ADC0 (8 inputs)
12-bit SAR(A)
McASP x2
(4ch)
Memory Interface
32b LPDDR2, DDR3, DDR3L(B)
GPIO
NAND, NOR, Async
(16-bit ECC)
ADC1 (8 inputs)
12-bit SAR
Simplified Power
Sequencing
Copyright © 2016, Texas Instruments Incorporated
A. 使用 TSC 将限制可用的 ADC0 输入。
B. 最大时钟：LPDDR2 = 266MHz；DDR3/DDR3L = 400MHz。
图 1-1. 功能方框图
6
器件概述
版权 © 2014–2016, Texas Instruments Incorporated
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
内容
1
器件概述.................................................... 1
Digital Subsystem Electrical Parameters .......... 113
5.9
ADC1: Analog-to-Digital Subsystem Electrical
Parameters......................................... 115
5.10 VPP Specifications for One-Time Programmable
(OTP) eFuses ...................................... 118
1.1 特性 ................................................... 1
1.2 应用 ................................................... 4
1.3 说明 ................................................... 5
1.4 功能方框图............................................ 6
修订历史记录............................................... 8
Device Comparison ..................................... 9
3.1 Related Products.................................... 10
Terminal Configuration and Functions ............ 11
4.1 Pin Diagrams........................................ 11
4.2 Pin Attributes ........................................ 21
4.3 Signal Descriptions.................................. 65
Specifications ......................................... 103
5.1 Absolute Maximum Ratings........................ 103
5.2 ESD Ratings ....................................... 105
5.3 Power-On Hours (POH) ........................... 105
5.4 Operating Performance Points .................... 106
5.5 Recommended Operating Conditions ............. 107
5.6 Power Consumption Summary .................... 109
5.7 DC Electrical Characteristics ...................... 110
5.11 Thermal Resistance Characteristics ............... 119
5.12 External Capacitors ................................ 120
5.13 Timing and Switching Characteristics.............. 123
5.14 Emulation and Debug.............................. 253
Device and Documentation Support.............. 254
6.1 Device Nomenclature.............................. 254
6.2 Tools and Software ................................ 255
6.3 Documentation Support............................ 257
6.4 Related Links ...................................... 259
6.5 Community Resources............................. 259
6.6 商标 ................................................ 259
6.7 静电放电警告....................................... 259
6.8 术语表.............................................. 259
2
3
4
6
5
7
Mechanical, Packaging, and Orderable
Information............................................. 260
7.1 Via Channel........................................ 260
7.2 Packaging Information ............................. 260
5.8
ADC0: Touch Screen Controller and Analog-to-
版权 © 2014–2016, Texas Instruments Incorporated
内容
7
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (April 2015) to Revision D
Page
•
•
•
•
•
•
•
已添加 在文档中添加了 AM4372 器件信息 ........................................................................................ 1
已添加 在、“器件信息”中添加了 AM4372ZDN 部件号 ........................................................................... 5
已添加 表 3-1, Device Features Comparison ..................................................................................... 9
已添加 AM4372 Device and 600-MHz Device Speed Range to 图 6-1, Device Nomenclature ......................... 255
Updated Design Kits and Evaluation Modules list in 节 6.2, Tools and Software......................................... 255
Updated notification alert paragraph in 节 6.3, Documentation Support ................................................... 257
已添加 AM4372 part number information to 表 6-1, Related Links.......................................................... 259
8
修订历史记录
版权 © 2014–2016, Texas Instruments Incorporated
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
3 Device Comparison
表 3-1 shows the features supported across different AM437x devices.
表 3-1. Device Features Comparison
FUNCTION
AM4372
AM4376
AM4377
AM4378
AM4379
ARM Cortex-A9
Yes
Yes
Yes
Yes
Yes
300 MHz
800 MHz
1000 MHz
600 MHz
800 MHz
800 MHz
1000 MHz
800 MHz
1000 MHz
800 MHz
1000 MHz
Frequency
MIPS
750
2000
2500
1500
2000
2000
2500
2000
2500
2000
2500
On-chip L1 cache
64KB
256KB
64KB
256KB
64KB
256KB
64KB
256KB
64KB
256KB
On-chip L2 cache
Graphics accelerator (SGX530)
Hardware acceleration
—
—
—
3D
3D
Crypto accelerator
Crypto accelerator
Crypto accelerator
Crypto accelerator
Crypto accelerator
Programmable real-time unit
subsystem and industrial
communication subsystem (PRU-
ICSS)
Features including
basic Industrial
protocols
Features including
basic Industrial
protocols
Features including all
Industrial protocols
Features including all
Industrial protocols
—
On-chip memory
Display options
256KB
DSS
256KB
DSS
256KB
DSS
256KB
DSS
256KB
DSS
1 16-bit (GPMC,
NAND flash, NOR
flash, SRAM)
1 16-bit (GPMC,
NAND flash, NOR
flash, SRAM)
1 16-bit (GPMC,
NAND flash, NOR
flash, SRAM)
1 16-bit (GPMC,
NAND flash, NOR
flash, SRAM)
1 16-bit (GPMC,
NAND flash, NOR
flash, SRAM)
General-purpose memory
1 32-bit (DDR3-800,
DDR3L-800,
1 32-bit (DDR3-800,
DDR3L-800,
1 32-bit (DDR3-800,
DDR3L-800,
1 32-bit (DDR3-800,
DDR3L-800,
1 32-bit (DDR3-800,
DDR3L-800,
DRAM(1)
LPDDR2-532)
LPDDR2-532)
LPDDR2-532)
LPDDR2-532)
LPDDR2-532)
Universal serial bus (USB)
2 ports
2 ports
2 ports
2 ports
2 ports
Ethernet media access controller
(EMAC) with 2-port switch
10/100/1000
2 ports
10/100/1000
2 ports
10/100/1000
2 ports
10/100/1000
2 ports
10/100/1000
2 ports
Multimedia card (MMC)
3
2
3
2
3
2
3
2
3
2
Controller-area network (CAN)
Universal asynchronous receiver
and transmitter (UART)
6
6
6
6
6
Analog-to-digital converter (ADC)
2 8-ch 12-bit
2 8-ch 12-bit
2 8-ch 12-bit
2 8-ch 12-bit
2 8-ch 12-bit
Enhanced high-resolution PWM
modules (eHRPWM)
6
3
3
6
3
3
6
3
3
6
3
3
6
3
3
Enhanced capture modules (eCAP)
Enhanced quadrature encoder
pulse (eQEP)
Real-time clock (RTC)
1
3
1
3
1
3
1
3
1
3
Inter-integrated circuit (I2C)
Multichannel audio serial port
(McASP)
2
5
2
5
2
5
2
5
2
5
Multichannel serial port interface
(McSPI)
Enhanced direct memory access
(EDMA)
64-Ch
64-Ch
64-Ch
64-Ch
64-Ch
Camera (VPFE)
Sync timer (32K)
HDQ/1-Wire
QSPI
12-bit
12-bit
12-bit
12-bit
12-bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
版权 © 2014–2016, Texas Instruments Incorporated
Device Comparison
9
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
表 3-1. Device Features Comparison (continued)
FUNCTION
AM4372
12
AM4376
12
AM4377
12
AM4378
12
AM4379
12
Timers
DEV_FEATURE register value(2)
0x02FC20FE
1.8 V, 3.3 V
0x02FD20FF
1.8 V, 3.3 V
0x02FF20FF
1.8 V, 3.3 V
0x22FD20FF
1.8 V, 3.3 V
0x22FF20FF
1.8 V, 3.3 V
Input/output (I/O) supply
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 90°C
0 to 90°C
–40 to 105°C
–40 to 105°C
–40 to 90°C
Operating temperature range
–40 to 105°C
(1) DRAM speeds listed are data rates.
(2) For more details about the DEV_FEATURE register, see the AM437x Sitara Processors Technical Reference Manual.
3.1 Related Products
For information about other devices in this family of products or related products, see the following links:
Sitara Processors Scalable processors based on ARM Cortex-A cores with flexible peripherals,
connectivity and unified software support – perfect for sensors to servers.
Sitara AM437x Processors Scalable ARM Cortex-A9 from 300 MHz up to 1 GHz. 3D graphics option for
enhanced user interface. Quad core PRU-ICSS for industrial Ethernet protocols and position
feedback control. Dual camera support for barcode scanning, preview and still pictures.
Customer programmable secure boot option.
Companion Products for AM437x Devices Review products that are frequently used in conjunction with
this product.
Reference Designs for AM437x Devices TI Designs Reference Design Library is a robust reference
design library spanning analog, embedded processor and connectivity. Created by TI experts
to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
10
Device Comparison
版权 © 2014–2016, Texas Instruments Incorporated
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4 Terminal Configuration and Functions
4.1 Pin Diagrams
注
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An
attempt is made to use "ball" only when referring to the physical package.
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
11
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
ZDN Ball Map [Section Top Left - Top View]
A
B
C
D
E
F
G
H
25
24
VSS
XTALOUT
VSS_OSC
XTALIN
gpio5_8
gpio5_12
gpio5_13
USB1_DRVVBUS
gpio5_9
EXTINTn
uart3_rxd
uart3_txd
dss_ac_bias_en
xdma_event_intr1
xdma_event_intr0
eCAP0_in_PWM0_o
ut
23
22
21
20
19
18
dss_hsync
dss_pclk
dss_vsync
dss_data0
dss_data2
dss_data5
dss_data9
dss_data11
VDDS_OSC
VDDS_CLKOUT
gpio5_11
mcasp0_axr0
uart3_ctsn
Reserved
clkreq
VDDSHV5
WARMRSTn
USB0_DRVVBUS
gpio5_10
dss_data1
dss_data4
dss_data8
dss_data10
dss_data3
dss_data6
dss_data12
vdd_mpu_mon
dss_data13
VDDS
dss_data7
CAP_VBB_MPU
Reserved
VSS
Ball Map Position
1
4
7
2
5
8
3
6
9
12
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-1. ZDN Ball Map [Section Top Middle - Top View]
J
K
L
M
N
P
R
T
25
24
23
22
21
uart0_rtsn
uart0_txd
uart0_rxd
uart3_rtsn
mcasp0_fsr
uart1_ctsn
uart1_rxd
uart0_ctsn
mcasp0_ahclkx
mcasp0_aclkr
uart1_rtsn
mcasp0_axr1
mcasp0_ahclkr
spi4_cs0
spi4_sclk
spi4_d1
spi0_sclk
spi2_d0
VPP
spi0_cs1
spi4_d0
USB1_VBUS
EMU1
mcasp0_aclkx
EMU0
spi2_cs0
spi0_d0
spi0_d1
mcasp0_fsx
uart1_txd
VDDS_PLL_CORE_
LCD
20
19
18
VDD_MPU
VDD_MPU
VDDSHV3
VDD_MPU
VDD_MPU
VSS
spi2_sclk
VDDSHV3
VDDSHV3
spi2_d1
VDDS
spi0_cs0
VDD_CORE
VDD_CORE
VDDSHV3
VDD_MPU
VDDSHV3
VSS
Ball Map Position
1
4
7
2
5
8
3
6
9
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
13
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-2. ZDN Ball Map [Section Top Right - Top View]
U
V
W
Y
AA
AB
AC
AD
AE
25
24
23
22
USB1_ID
USB0_ID
USB0_VBUS
USB1_CE
USB1_DM
USB1_DP
USB0_DP
nTRST
TCK
TDO
VSS
cam1_wen
I2C0_SDA
cam1_field
cam1_data9
cam1_vd
cam1_hd
VSS
USB0_DM
TMS
cam1_data8
cam1_data6
cam1_data4
cam1_data2
cam0_data7
cam0_data5
cam0_vd
cam1_data7
cam1_data5
cam1_data3
cam1_pclk
cam0_data6
cam0_data4
cam0_data0
VSSA_USB
USB0_CE
PWRONRSTn
I2C0_SCL
21 VDDA1P8V_USB1
20 VDDA3P3V_USB1
VDDA1P8V_USB0
VDDA3P3V_USB0
cam1_data1
cam0_pclk
TDI
cam1_data0
cam0_data8
cam0_data1
19
18
VSS
VSS
VDDS
cam0_data9
cam0_data3
VSS
VDDSHV3
cam0_data2
cam0_field
Ball Map Position
1
4
7
2
5
8
3
6
9
14
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-3. ZDN Ball Map [Section Middle Left - Top View]
A
B
C
D
E
F
G
H
17
16
15
14
mdio_data
rmii1_ref_clk
mii1_rx_dv
mii1_txd1
mdio_clk
mii1_rxd1
mii1_txd0
mii1_crs
dss_data14
mii1_txd3
dss_data15
mii1_col
VDDS_PLL_MPU
mii1_rxd2
mii1_rxd0
VDDSHV7
VDDSHV6
VDDSHV6
VDDSHV6
VDD_MPU
VSS
mii1_rxd3
mii1_txd2
mii1_tx_clk
mii1_rx_clk
CAP_VDD_SRAM_ VDDS_SRAM_MPU
MPU _BB
VDDSHV8
VDDSHV8
VDD_MPU
13
mii1_tx_en
mii1_rx_er
CAP_VDD_SRAM_C VDDS_SRAM_COR
VDD_MPU
ORE
E_BG
12
11
10
gpmc_clk
gpmc_ad15
gpmc_ad9
gpmc_csn3
gpmc_ad14
gpmc_ad8
VDDS
gpmc_ad13
gpmc_ad11
gpmc_wen
gpmc_ad12
gpmc_ad10
gpmc_csn2
VDDSHV9
VDDSHV9
VDDSHV10
gpmc_be0n_cle
gpmc_oen_ren
VDDSHV10
Ball Map Position
1
4
7
2
5
8
3
6
9
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
15
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
ZDN Ball Map [Section Middle Middle - Top View]
J
K
L
M
VDD_MPU
VSS
N
VDD_CORE
VDD_CORE
VSS
P
VDD_CORE
VDD_CORE
VSS
R
T
17
16
15
14
13
12
11
10
VSS
VDDSHV3
VSS
VSS
VSS
VDD_MPU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_MPU
VDD_MPU
VSS
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
VSS
Ball Map Position
1
4
7
2
5
8
3
6
9
16
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
ZDN Ball Map [Section Middle Right - Top View]
U
V
VDDSHV2
VDDSHV2
VDD_CORE
VSS
W
Y
AA
AB
AC
AD
AE
17
16
15
14
13
12
11
10
VSS
VSS
cam0_wen
ADC1_AIN7
ADC1_VREFN
ADC0_VREFP
ADC0_AIN6
VDDS
cam0_hd
VDDSHV2
VDDS
VDDA_ADC1
ADC1_AIN5
ADC1_AIN2
ADC1_AIN4
ADC1_AIN1
ADC1_AIN3
ADC1_AIN0
VSSA_ADC
ADC1_AIN6
ADC1_VREFP
ADC0_VREFN
ADC0_AIN7
Reserved
VDD_CORE
VSS
VSS
VSS
VDD_CORE
VDD_CORE
ADC0_AIN2
ADC0_AIN1
ADC0_AIN3
ADC0_AIN0
ADC0_AIN4
ADC0_AIN5
Reserved
VSS
VSS
VDDA_ADC0
VSS
VSS
Reserved
Reserved
VSS
VSS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VSS
Ball Map Position
1
4
7
2
5
8
3
6
9
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
17
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-4. ZDN Ball Map [Section Bottom Left - Top View]
A
B
C
D
E
F
G
H
9
8
7
6
gpmc_advn_ale
gpmc_csn0
gpmc_ad5
gpmc_ad3
gpmc_csn1
gpmc_ad7
gpmc_ad4
gpmc_ad2
VDDSHV11
VDDSHV11
gpmc_ad6
gpmc_a11
gpmc_a4
gpmc_a6
gpmc_a5
VDDS3P3V_IOLDO
gpmc_a8
gpmc_a10
gpmc_a2
gpmc_a1
CAP_VDDS1P8V_IO
LDO
gpmc_a7
VDDS
5
4
3
2
1
gpmc_ad1
gpmc_a3
gpmc_be1n
gpmc_wait0
VSS
gpmc_ad0
gpmc_a9
VDDS_PLL_DDR
ddr_d4
ddr_dqm0
ddr_d3
gpmc_wpn
mmc0_dat2
mmc0_dat3
gpmc_a0
mmc0_dat1
mmc0_dat0
ddr_d0
ddr_d1
ddr_d2
ddr_d5
mmc0_cmd
mmc0_clk
ddr_dqs0
ddr_dqsn0
ddr_d6
ddr_dqm1
ddr_d8
ddr_d7
Ball Map Position
1
4
7
2
5
8
3
6
9
18
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-5. ZDN Ball Map [Section Bottom Middle - Top View]
J
K
L
M
N
P
R
T
9
8
7
6
5
4
3
2
1
VSS
VSS
VSS
VSS
VDD_CORE
VDDS_DDR
VDDS_DDR
ddr_a10
VDD_CORE
VDDS_DDR
VDDS_DDR
ddr_cke1
ddr_a13
VSS
VSS
VDD_CORE
VDDS_DDR
VDDS_DDR
VDDS_DDR
ddr_a5
VDD_CORE
VDDS_DDR
VDDS_DDR
ddr_vref
VDDSHV1
VDDSHV1
ddr_d9
VDDS_DDR
VDDS_DDR
ddr_d13
ddr_d14
ddr_d15
ddr_ba2
ddr_ba1
ddr_ba0
ddr_d10
ddr_d11
ddr_d12
ddr_dqs1
ddr_dqsn1
ddr_csn0
ddr_csn1
ddr_cke0
ddr_ck
ddr_a11
ddr_wen
ddr_a6
ddr_a12
ddr_casn
ddr_rasn
ddr_a0
ddr_a7
ddr_a14
ddr_a2
ddr_a1
ddr_a3
ddr_a4
ddr_a8
ddr_a15
ddr_nck
ddr_a9
ddr_resetn
Ball Map Position
1
4
7
2
5
8
3
6
9
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
19
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-6. ZDN Ball Map [Section Bottom Right - Top View]
U
V
W
Y
AA
AB
AC
AD
AE
Reserved
VSS
9
8
7
6
VSS
VSS
VSS
Reserved
Reserved
Reserved
VDD_CORE
VDDS
VDDS_DDR
VDDS_DDR
ddr_dqm2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VSS
ddr_d23
RTC_PMIC_EN RTC_PWRONRST
n
5
4
3
2
ddr_d16
ddr_d17
ddr_d18
ddr_d19
ddr_d22
ddr_d21
Reserved
VDDS_RTC
VSS_RTC
RTC_XTALIN
RTC_XTALOUT
RTC_WAKEUP
ddr_d26
ddr_d25
ddr_d24
ddr_d27
ddr_vtp
CAP_VDD_RTC
Reserved
ddr_odt1
ddr_odt0
ddr_dqsn2
ddr_dqs2
ddr_dqsn3
ddr_d28
ddr_d29
ddr_d31
RTC_KALDO_EN
n
1
ddr_d20
ddr_dqm3
ddr_dqs3
ddr_d30
Reserved
VSS
Ball Map Position
1
4
7
2
5
8
3
6
9
20
Terminal Configuration and Functions
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.2 Pin Attributes
1. BALL NUMBER: Package ball numbers associated with each signals.
2. PIN NAME: The name of the package pin.
Note: The table does not take into account subsystem terminal multiplexing options.
3. SIGNAL NAME: The signal name for that pin in the mode being used.
4. MODE: Multiplexing mode number.
a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the
terminal corresponds to the name of the terminal. There is always a function mapped on the
primary mode. Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE
column.
b. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are
effectively used for alternate functions, while some modes are not used and do not correspond to a
functional configuration.
5. TYPE: Signal direction
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input and Output
D = Open drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
–
0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z or OFF: High-impedance
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal
transitions from low to high.
–
0: The buffer drives VOL (pulldown or pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
1: The buffer drives VOH (pulldown or pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
Z or OFF: High-impedance.
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal
transitions from low to high.
9. POWER: The voltage supply that powers the terminal’s IO buffers.
10. HYS: Indicates if the input buffer is with hysteresis.
11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
13. IO CELL: IO cell information.
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
21
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration.
22
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AA12
Y12
ADC0_AIN0
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
0x0
A
A
A
A
A
A
A
A
Z
Z
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode7
VDDA_ADC0
NA
25
NA
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
LVCMOS
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
PD
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
PD
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC0
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDA_ADC1
VDDSHV2
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Yes
25
25
25
25
25
25
25
NA
NA
25
25
25
25
25
25
25
25
NA
NA
6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
PU/PD
Y13
AA13
AB13
AC13
AD13
AE13
AE14
AD14
AC16
AB16
AA16
AB15
AA15
Y15
ADC0_VREFN
ADC0_VREFP
ADC1_AIN0
ADC1_AIN1
ADC1_AIN2
ADC1_AIN3
ADC1_AIN4
ADC1_AIN5
ADC1_AIN6
ADC1_AIN7
ADC1_VREFN
ADC1_VREFP
cam0_data0
ADC0_VREFN
ADC0_VREFP
ADC1_AIN0
ADC1_AIN1
ADC1_AIN2
ADC1_AIN3
ADC1_AIN4
ADC1_AIN5
ADC1_AIN6
ADC1_AIN7
ADC1_VREFN
ADC1_VREFP
cam0_data0
cam1_data9
I2C1_SDA
AP
AP
A
A
A
A
A
A
AE16
AD16
AD15
AE15
AE18
A
A
AP
AP
I
I
IOD
O
I
pr0_pru1_gpo16
pr0_pru1_gpi16
ehrpwm0_synco
gpio5_19
O
IO
I
AB18
cam0_data1
cam0_data1
cam1_data8
I2C1_SCL
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
I
IOD
O
I
pr0_pru1_gpo17
pr0_pru1_gpi17
ehrpwm3_synco
gpio5_20
O
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
23
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
Y18
cam0_data2
cam0_data2
mmc1_clk
cam1_data10
qspi_clk
0x0
I
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x6
0x7
0x0
0x1
0x3
0x6
0x7
0x0
0x1
0x3
0x6
0x7
0x0
0x1
0x3
0x6
0x7
IO
I
IO
IO
I
gpio4_24
AA18
AE19
cam0_data3
cam0_data4
cam0_data3
mmc1_cmd
cam1_data11
qspi_csn
VDDSHV2
VDDSHV2
Yes
Yes
6
6
PU/PD
PU/PD
IO
I
O
IO
I
gpio4_25
cam0_data4
mmc1_dat0
cam1_wen
qspi_d0
IO
I
IO
O
IO
I
ehrpwm3A
gpio4_26
AD19
AE20
AD20
cam0_data5
cam0_data6
cam0_data7
cam0_data5
mmc1_dat1
qspi_d1
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
IO
I
ehrpwm3B
gpio4_27
O
IO
I
cam0_data6
mmc1_dat2
qspi_d2
IO
I
ehrpwm1A
gpio4_28
O
IO
I
cam0_data7
mmc1_dat3
qspi_d3
IO
I
ehrpwm1B
gpio4_29
O
IO
24
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AB19
cam0_data8
cam0_data8
dss_data18
0x0
I
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x8
O
O
IO
I
pr0_pru0_gpo15
spi2_cs2
pr0_pru0_gpi15
EMU7
IO
IO
gpio4_5
I2C2_SCL
cam0_data9
dss_data17
pr0_pru0_gpo16
spi2_cs3
IOD
I
AA19
AC18
AE17
AC20
cam0_data9
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
O
O
IO
I
pr0_pru0_gpi16
EMU8
IO
IO
IO
O
gpio4_6
cam0_field
cam0_field
dss_data21
cam0_data10
spi2_sclk
I
IO
I
cam1_data10
EMU4
IO
IO
IO
O
gpio4_2
cam0_hd
cam0_hd
dss_data23
pr1_edio_sof
spi2_cs1
O
IO
IO
IO
IO
I
EMU10
EMU2
gpio4_0
cam0_pclk
cam0_pclk
dss_data19
pr0_pru0_gpo14
spi2_cs0
O
O
IO
I
pr0_pru0_gpi14
EMU6
IO
IO
IOD
gpio4_4
I2C2_SDA
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
25
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AD18
cam0_vd
cam0_vd
0x0
IO
O
O
IO
IO
IO
IO
I
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
dss_data22
pr1_edio_outvalid
spi2_d1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x6
0x7
0x0
0x1
0x2
0x3
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
EMU11
EMU3
gpio4_1
AD17
cam0_wen
cam0_wen
dss_data20
cam0_data11
spi2_d0
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
O
I
IO
I
cam1_data11
EMU5
IO
IO
I
gpio4_3
AB20
AC21
AD21
cam1_data0
cam1_data1
cam1_data2
cam1_data0
uart1_rxd
PD
PU
PD
PD
PU
PD
Mode7
Mode7
Mode7
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
IO
IO
spi3_d0
I2C2_SDA
ehrpwm0_tripzone_input
gpio4_14
IOD
I
IO
I
cam1_data1
uart1_txd
IO
IO
IOD
I
spi3_d1
I2C2_SCL
ehrpwm0_synci
gpio4_15
IO
I
cam1_data2
uart1_ctsn
spi3_cs0
IO
IO
IO
O
I
mmc2_clk
pr0_pru1_gpo10
pr0_pru1_gpi10
ehrpwm1_tripzone_input
gpio4_16
I
IO
26
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AE22
cam1_data3
cam1_data3
uart1_rtsn
spi3_sclk
0x0
I
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
O
IO
IO
O
I
mmc2_cmd
pr0_pru1_gpo11
pr0_pru1_gpi11
pr1_edc_latch0_in
gpio4_17
I
IO
I
AD22
cam1_data4
cam1_data4
uart1_rin
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
I
uart2_rxd
IO
IO
O
I
mmc2_dat0
pr0_pru1_gpo12
pr0_pru1_gpi12
pr1_edc_latch1_in
gpio4_18
I
IO
I
uart0_dcdn
AE23
cam1_data5
cam1_data5
uart1_dsrn
I
PU
PU
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
I
uart2_txd
IO
IO
O
I
mmc2_dat1
pr0_pru1_gpo13
pr0_pru1_gpi13
pr1_edio_latch_in
gpio4_19
I
IO
I
AD23
cam1_data6
cam1_data6
uart1_dcdn
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
I
uart2_ctsn
IO
IO
O
I
mmc2_dat2
pr0_pru1_gpo14
pr0_pru1_gpi14
pr1_edio_data_in0
gpio4_20
I
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
27
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AE24
cam1_data7
cam1_data7
uart1_dtrn
0x0
I
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
O
O
IO
O
I
uart2_rtsn
mmc2_dat3
pr0_pru1_gpo15
pr0_pru1_gpi15
pr1_edio_data_in1
gpio4_21
I
IO
I
AD24
cam1_data8
cam1_data8
xdma_event_intr3
spi0_cs2
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
I
IO
O
IO
I
pr0_pru1_gpo0
spi2_d0
pr0_pru1_gpi0
EMU10
IO
IO
O
I
gpio4_8
uart0_rtsn
AC24
cam1_data9
cam1_data9
dss_data16
pr0_pru0_gpo17
spi2_cs3
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
O
O
IO
I
pr0_pru0_gpi17
EMU9
IO
IO
I
gpio4_7
uart0_ctsn
AC25
cam1_field
cam1_field
IO
I
PD
PD
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
xdma_event_intr7
ext_hw_trigger
cam0_data10
spi2_cs1
I
I
IO
I
cam1_data10
ehrpwm1B
O
IO
O
gpio4_12
ehrpwm3A
28
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AD25
AE21
AC23
AB25
cam1_hd
cam1_hd
0x0
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV2
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
xdma_event_intr4
spi0_cs3
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
NA
IO
O
IO
I
pr0_pru1_gpo1
spi2_cs0
pr0_pru1_gpi1
ehrpwm0A
O
IO
I
gpio4_9
cam1_pclk
cam1_pclk
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
xdma_event_intr6
spi1_cs3
I
IO
O
IO
I
pr0_pru1_gpo3
spi2_sclk
pr0_pru1_gpi3
ehrpwm1A
O
IO
IO
I
gpio4_11
cam1_vd
cam1_vd
xdma_event_intr5
spi1_cs2
IO
O
IO
I
pr0_pru1_gpo2
spi2_cs2
pr0_pru1_gpi2
ehrpwm0B
O
IO
I
gpio4_10
cam1_wen
cam1_wen
xdma_event_intr8
pr1_edio_sof
cam0_data11
spi2_d1
I
O
I
IO
I
cam1_data11
EMU11
IO
IO
O
A
gpio4_13
ehrpwm3B
F19
D6
CAP_VBB_MPU
CAP_VBB_MPU
CAP_VDDS1P8V_IOLDO
CAP_VDD_RTC
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CAP_VDDS1P8V_IOLDO
CAP_VDD_RTC
NA
POWER
AD3
E13
E14
NA
A
A
A
CAP_VDD_SRAM_CORE
CAP_VDD_SRAM_MPU
NA
NA
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
29
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
H20
clkreq
clkreq
0x0
O
OFF
PU
Mode0
VDDSHV3
Yes
6
PU/PD
LVCMOS
gpio0_24
ddr_a0
0x7
0x0
IO
O
N1
L1
ddr_a0
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PD
PD
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/HST
L/HSUL_12
ddr_a1
ddr_a1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LVCMOS/HST
L/HSUL_12
L2
ddr_a2
ddr_a2
LVCMOS/HST
L/HSUL_12
P2
P1
R5
R4
R3
R2
R1
M6
T5
T4
N5
T3
T2
K1
K2
K3
N3
M2
M3
ddr_a3
ddr_a3
LVCMOS/HST
L/HSUL_12
ddr_a4
ddr_a4
LVCMOS/HST
L/HSUL_12
ddr_a5
ddr_a5
LVCMOS/HST
L/HSUL_12
ddr_a6
ddr_a6
LVCMOS/HST
L/HSUL_12
ddr_a7
ddr_a7
LVCMOS/HST
L/HSUL_12
ddr_a8
ddr_a8
LVCMOS/HST
L/HSUL_12
ddr_a9
ddr_a9
LVCMOS/HST
L/HSUL_12
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
ddr_ck
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
ddr_ck
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
ddr_cke0
ddr_cke0
LVCMOS/HST
L/HSUL_12
30
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
N6
M5
M4
E3
E2
E1
F3
G4
G3
G2
G1
H1
J6
ddr_cke1
ddr_cke1
ddr_csn0
ddr_csn1
ddr_d0
0x0
O
PD
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
ddr_csn0
ddr_csn1
ddr_d0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
O
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/HST
L/HSUL_12
O
LVCMOS/HST
L/HSUL_12
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
LVCMOS/HST
L/HSUL_12
ddr_d1
ddr_d1
LVCMOS/HST
L/HSUL_12
ddr_d2
ddr_d2
LVCMOS/HST
L/HSUL_12
ddr_d3
ddr_d3
LVCMOS/HST
L/HSUL_12
ddr_d4
ddr_d4
LVCMOS/HST
L/HSUL_12
ddr_d5
ddr_d5
LVCMOS/HST
L/HSUL_12
ddr_d6
ddr_d6
LVCMOS/HST
L/HSUL_12
ddr_d7
ddr_d7
LVCMOS/HST
L/HSUL_12
ddr_d8
ddr_d8
LVCMOS/HST
L/HSUL_12
ddr_d9
ddr_d9
LVCMOS/HST
L/HSUL_12
J5
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d16
ddr_d17
ddr_d18
ddr_d19
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d16
ddr_d17
ddr_d18
ddr_d19
LVCMOS/HST
L/HSUL_12
J4
LVCMOS/HST
L/HSUL_12
J3
LVCMOS/HST
L/HSUL_12
K6
K5
K4
V5
V4
V3
V2
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
31
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
V1
ddr_d20
ddr_d20
0x0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
PU
PU
PD
PD
PD
PD
PU
PU
PU
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
W4
W5
W6
Y2
ddr_d21
ddr_d21
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Yes
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/HST
L/HSUL_12
ddr_d22
ddr_d22
LVCMOS/HST
L/HSUL_12
ddr_d23
ddr_d23
LVCMOS/HST
L/HSUL_12
ddr_d24
ddr_d24
LVCMOS/HST
L/HSUL_12
Y3
ddr_d25
ddr_d25
LVCMOS/HST
L/HSUL_12
Y4
ddr_d26
ddr_d26
LVCMOS/HST
L/HSUL_12
AA3
AB2
AB1
AC1
AC2
F4
ddr_d27
ddr_d27
LVCMOS/HST
L/HSUL_12
ddr_d28
ddr_d28
LVCMOS/HST
L/HSUL_12
ddr_d29
ddr_d29
LVCMOS/HST
L/HSUL_12
ddr_d30
ddr_d30
LVCMOS/HST
L/HSUL_12
ddr_d31
ddr_d31
LVCMOS/HST
L/HSUL_12
ddr_dqm0
ddr_dqm1
ddr_dqm2
ddr_dqm3
ddr_dqs0
ddr_dqs1
ddr_dqs2
ddr_dqs3
ddr_dqsn0
ddr_dqsn1
ddr_dqsn2
ddr_dqm0
ddr_dqm1
ddr_dqm2
ddr_dqm3
ddr_dqs0
ddr_dqs1
ddr_dqs2
ddr_dqs3
ddr_dqsn0
ddr_dqsn1
ddr_dqsn2
LVCMOS/HST
L/HSUL_12
H2
O
LVCMOS/HST
L/HSUL_12
V6
O
LVCMOS/HST
L/HSUL_12
Y1
O
LVCMOS/HST
L/HSUL_12
F2
IO
IO
IO
IO
IO
IO
IO
LVCMOS/HST
L/HSUL_12
J2
LVCMOS/HST
L/HSUL_12
W1
AA1
F1
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
LVCMOS/HST
L/HSUL_12
J1
Yes
LVCMOS/HST
L/HSUL_12
W2
Yes
LVCMOS/HST
L/HSUL_12
32
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AA2
M1
U1
ddr_dqsn3
ddr_dqsn3
ddr_nck
0x0
IO
O
O
O
O
O
PU
PU
PD
PD
PU
Mode0
Mode0
Mode0
Mode0
Mode0
VDDS_DDR
Yes
8
PU/PD
LVCMOS/HST
L/HSUL_12
ddr_nck
ddr_odt0
ddr_odt1
ddr_rasn
0x0
0x0
0x0
0x0
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
YES
YES
YES
YES
8
8
8
8
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS/HST
L/HSUL_12
ddr_odt0
ddr_odt1
ddr_rasn
LVCMOS/HST
L/HSUL_12
U2
LVCMOS/HST
L/HSUL_12
N2
LVCMOS/HST
L/HSUL_12
T1
ddr_resetn
ddr_vref
ddr_vtp
ddr_resetn
ddr_vref
ddr_vtp
0x0
0x0
0x0
0x0
PD
NA
NA
PU
Mode0
Mode0
Mode0
Mode0
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
YES
NA
8
PU/PD
NA
LVCMOS
Analog
T6
AP (19)
I (20)
O
NA
NA
NA
NA
8
AC3
N4
NA
NA
Analog
ddr_wen
ddr_wen
YES
PU/PD
LVCMOS/HST
L/HSUL_12
A24
dss_ac_bias_en
dss_ac_bias_en
gpmc_a11
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
O
O
O
I
OFF
OFF
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a4
pr1_edio_data_in5
pr1_edio_data_out5
pr0_pru1_gpo9
pr0_pru1_gpi9
gpio2_25
O
O
I
IO
IO
O
I
B22
dss_data0 (4)
dss_data0
OFF
OFF
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a0
pr1_mii_mt0_clk
ehrpwm2A
O
O
I
pr1_pru0_gpo0
pr1_pru0_gpi0
gpio2_6
IO
IO
O
O
O
O
I
A21
dss_data1 (4)
dss_data1
OFF
OFF
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
gpmc_a1
pr1_mii0_txen
ehrpwm2B
pr1_pru0_gpo1
pr1_pru0_gpi1
gpio2_7
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
33
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B21
dss_data2 (4)
dss_data2
0x0
IO
O
O
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Mode7
Mode7
Mode7
Mode7
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpmc_a2
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
pr1_mii0_txd3
ehrpwm2_tripzone_input
pr1_pru0_gpo2
pr1_pru0_gpi2
gpio2_8
O
I
IO
IO
O
O
O
O
I
C21
A20
B20
C20
dss_data3 (4)
dss_data4 (4)
dss_data5 (4)
dss_data6 (4)
dss_data3
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
gpmc_a3
pr1_mii0_txd2
ehrpwm0_synco
pr1_pru0_gpo3
pr1_pru0_gpi3
gpio2_9
IO
IO
O
O
I
dss_data4
gpmc_a4
pr1_mii0_txd1
eQEP2A_in
pr1_pru0_gpo4
pr1_pru0_gpi4
gpio2_10
O
I
IO
IO
O
O
I
dss_data5
gpmc_a5
pr1_mii0_txd0
eQEP2B_in
pr1_pru0_gpo5
pr1_pru0_gpi5
gpio2_11
O
I
IO
IO
O
I
dss_data6
gpmc_a6
pr1_edio_data_in6
eQEP2_index
pr1_edio_data_out6
pr1_pru0_gpo6
pr1_pru0_gpi6
gpio2_12
IO
O
O
I
IO
34
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
E19
A19
B19
A18
dss_data7 (4)
dss_data7
gpmc_a7
0x0
IO
O
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Mode7
Mode7
Mode7
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
pr1_edio_data_in7
eQEP2_strobe
pr1_edio_data_out7
pr1_pru0_gpo7
pr1_pru0_gpi7
gpio2_13
IO
O
O
I
IO
IO
O
I
dss_data8 (4)
dss_data8
VDDSHV6
VDDSHV6
VDDSHV6
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
gpmc_a12
ehrpwm1_tripzone_input
mcasp0_aclkx
uart5_txd
IO
O
I
pr1_mii0_rxd3
uart2_ctsn
IO
IO
IO
O
O
IO
I
gpio2_14
dss_data9 (4)
dss_data9
gpmc_a13
ehrpwm0_synco
mcasp0_fsx
uart5_rxd
pr1_mii0_rxd2
uart2_rtsn
I
O
IO
IO
O
O
IO
I
gpio2_15
dss_data10 (4)
dss_data10
gpmc_a14
ehrpwm1A
mcasp0_axr0
pr1_mii0_rxd1
uart3_ctsn
IO
IO
gpio2_16
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
35
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B18
dss_data11 (4)
dss_data11
gpmc_a15
ehrpwm1B
mcasp0_ahclkr
mcasp0_axr2
pr1_mii0_rxd0
uart3_rtsn
0x0
IO
O
O
IO
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Mode7
Mode7
Mode7
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
O
IO
IO
IO
O
I
gpio2_17
spi3_cs1
C19
D19
C17
dss_data12 (4)
dss_data13 (4)
dss_data14 (4)
dss_data12
gpmc_a16
eQEP1A_in
mcasp0_aclkr
mcasp0_axr2
pr1_mii0_rxlink
uart4_ctsn
gpio0_8
VDDSHV6
VDDSHV6
VDDSHV6
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
IO
IO
I
I
IO
IO
IO
O
I
spi3_sclk
dss_data13
gpmc_a17
eQEP1B_in
mcasp0_fsr
mcasp0_axr3
pr1_mii0_rxer
uart4_rtsn
IO
IO
I
O
IO
IO
IO
O
IO
IO
I
gpio0_9
spi3_d0
dss_data14
gpmc_a18
eQEP1_index
mcasp0_axr1
uart5_rxd
pr1_mii_mr0_clk
uart5_ctsn
gpio0_10
I
I
IO
IO
spi3_d1
36
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
D17
dss_data15 (4)
dss_data15
gpmc_a19
0x0
IO
O
IO
IO
IO
I
OFF
OFF
Mode7
VDDSHV6
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
eQEP1_strobe
mcasp0_ahclkx
mcasp0_axr3
pr1_mii0_rxdv
uart5_rtsn
O
IO
IO
O
O
O
I
gpio0_11
spi3_cs0
A23
A22
B23
dss_hsync (5)
dss_hsync
OFF
OFF
OFF
OFF
Mode7
Mode7
Mode7
VDDSHV6
VDDSHV6
VDDSHV6
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
gpmc_a9
gpmc_a2
pr1_edio_data_in3
pr1_edio_data_out3
pr0_pru1_gpo7
pr0_pru1_gpi7
gpio2_23
O
O
I
IO
O
O
O
I
dss_pclk
dss_pclk
PD
gpmc_a10
gpmc_a3
pr1_edio_data_in4
pr1_edio_data_out4
pr0_pru1_gpo8
pr0_pru1_gpi8
gpio2_24
O
O
I
IO
O
O
O
I
dss_vsync (6)
dss_vsync
OFF
gpmc_a8
gpmc_a1
pr1_edio_data_in2
pr1_edio_data_out2
pr0_pru1_gpo6
pr0_pru1_gpi6
gpio2_22
O
O
I
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
37
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
G24
eCAP0_in_PWM0_out
eCAP0_in_PWM0_out
uart3_txd
0x0
IO
IO
IO
IO
IO
I
OFF
PD
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x7
0x0
0x7
0x0
0x5
0x7
0x5
0x7
0x1
0x5
0x7
0x5
0x7
0x1
0x5
0x7
0x5
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
spi1_cs1
pr1_ecap0_ecap_capin_apwm_o
spi1_sclk
mmc0_sdwp
xdma_event_intr2
gpio0_7
I
IO
O
IO
IO
IO
IO
IO
I
ehrpwm2B
timer1
N23
T24
EMU0
EMU1
EMU0
PU
PU
PU
PU
Mode0
Mode0
VDDSHV3
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
gpio3_7
EMU1
gpio3_8
G25
D25
EXTINTn
gpio5_8
nNMI
OFF
OFF
PU
PD
Mode0
Mode7
VDDSHV3
VDDSHV3
Yes
Yes
NA
6
PU/PD
PU/PD
LVCMOS
LVCMOS
pr1_mii0_col
gpio5_8
I
IO
I
F24
G20
gpio5_9
pr1_mii1_col
gpio5_9
OFF
OFF
PD
PD
Mode7
Mode7
VDDSHV3
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
IO
gpio5_10
I2C1_SCL
IOD
I
pr1_mii0_crs
gpio5_10
IO
I
F23
E25
gpio5_11
gpio5_12
pr1_mii1_crs
gpio5_11
OFF
OFF
PD
PD
Mode7
Mode7
VDDSHV3
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
IO
IOD
I
I2C1_SDA
pr1_mii0_rxlink
gpio5_12
IO
I
E24
C3
gpio5_13
gpmc_a0
pr1_mii1_rxlink
gpio5_13
OFF
PD
PD
PD
Mode7
Mode7
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
IO
O
O
O
O
O
O
I
gpmc_a0
VDDSHV11
gmii2_txen
rgmii2_tctl
rmii2_txen
gpmc_a16
pr1_mii1_txen
ehrpwm1_tripzone_input
gpio1_16
IO
38
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
C5
C6
A4
D7
gpmc_a1
gpmc_a1
0x0
O
I
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gmii2_rxdv
rgmii2_rctl
mmc2_dat0
gpmc_a17
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
I
IO
O
I
pr1_mii1_rxdv
ehrpwm0_synco
gpio1_17
O
IO
O
O
O
IO
O
O
O
IO
O
O
O
IO
O
O
O
IO
O
O
O
O
O
O
I
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a2
VDDSHV11
VDDSHV11
VDDSHV11
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
gmii2_txd3
rgmii2_td3
mmc2_dat1
gpmc_a18
pr1_mii1_txd3
ehrpwm1A
gpio1_18
gpmc_a3
gmii2_txd2
rgmii2_td2
mmc2_dat2
gpmc_a19
pr1_mii1_txd2
ehrpwm1B
gpio1_19
gpmc_a4
gmii2_txd1
rgmii2_td1
rmii2_txd1
gpmc_a20
pr1_mii1_txd1
eQEP1A_in
gpio1_20
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
39
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
E7
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a5
0x0
O
O
O
O
O
O
I
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gmii2_txd0
rgmii2_td0
rmii2_txd0
gpmc_a21
pr1_mii1_txd0
eQEP1B_in
gpio1_21
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
IO
O
I
E8
F6
F7
gpmc_a6
VDDSHV11
VDDSHV11
VDDSHV11
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
gmii2_txclk
rgmii2_tclk
mmc2_dat4
gpmc_a22
pr1_mii_mt1_clk
eQEP1_index
gpio1_22
O
IO
O
I
IO
IO
O
I
gpmc_a7
gmii2_rxclk
rgmii2_rclk
mmc2_dat5
gpmc_a23
pr1_mii_mr1_clk
eQEP1_strobe
gpio1_23
I
IO
O
I
IO
IO
O
I
gpmc_a8
gmii2_rxd3
rgmii2_rd3
mmc2_dat6
gpmc_a24
pr1_mii1_rxd3
mcasp0_aclkx
gpio1_24
I
IO
O
I
IO
IO
40
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B4
gpmc_a9
gpmc_a9
0x0
O
I
PD
PD
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
gmii2_rxd2
rgmii2_rd2
mmc2_dat7
gpmc_a25
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x7
0x0
0x1
0x7
0x0
0x1
0x7
0x0
0x1
0x7
I
IO
O
I
pr1_mii1_rxd2
mcasp0_fsx
gpio1_25
IO
IO
I
rmii2_crs_dv
gpmc_a10
gmii2_rxd1
rgmii2_rd1
rmii2_rxd1
gpmc_a26
pr1_mii1_rxd1
mcasp0_axr0
gpio1_26
G8
gpmc_a10
O
I
PD
PD
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
I
I
O
I
IO
IO
O
I
D8
gpmc_a11
gpmc_a11
gmii2_rxd0
rgmii2_rd0
rmii2_rxd0
gpmc_a27
pr1_mii1_rxd0
mcasp0_axr1
gpio1_27
PD
PD
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
I
I
O
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B5
A5
B6
A6
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad0
mmc1_dat0
gpio1_0
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV10
VDDSHV10
VDDSHV10
VDDSHV10
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpmc_ad1
mmc1_dat1
gpio1_1
gpmc_ad2
mmc1_dat2
gpio1_2
gpmc_ad3
mmc1_dat3
gpio1_3
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
41
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B7
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad4
mmc1_dat4
gpio1_4
0x0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
Mode7
VDDSHV10
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
0x1
0x7
0x0
0x1
0x7
0x0
0x1
0x7
0x0
0x1
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
A7
gpmc_ad5
mmc1_dat5
gpio1_5
VDDSHV10
VDDSHV10
VDDSHV10
VDDSHV9
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
C8
B8
gpmc_ad6
mmc1_dat6
gpio1_6
gpmc_ad7
mmc1_dat7
gpio1_7
B10
gpmc_ad8
dss_data23
mmc1_dat0
mmc2_dat4
ehrpwm2A
pr1_mii_mt0_clk
spi3_sclk
IO
IO
O
I
IO
IO
IO
IO
IO
O
gpio0_22
spi3_cs1
gpio5_26
A10
gpmc_ad9
gpmc_ad9
dss_data22
mmc1_dat1
mmc2_dat5
ehrpwm2B
pr1_mii0_col
spi3_d0
PD
PD
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
IO
IO
O
I
IO
IO
IO
gpio0_23
gpio5_25
42
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
F11
D11
E11
gpmc_ad10
gpmc_ad10
dss_data21
mmc1_dat2
mmc2_dat6
0x0
IO
O
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
IO
IO
I
ehrpwm2_tripzone_input
pr1_mii0_txen
spi3_d1
O
IO
IO
IO
IO
O
gpio0_26
gpio5_24
gpmc_ad11
gpmc_ad11
dss_data20
mmc1_dat3
mmc2_dat7
ehrpwm0_synco
pr1_mii0_txd3
spi3_cs0
VDDSHV9
Yes
6
PU/PD
IO
IO
O
O
IO
IO
IO
IO
O
gpio0_27
gpio5_23
gpmc_ad12
gpmc_ad12
dss_data19
mmc1_dat4
mmc2_dat0
eQEP2A_in
pr1_mii0_txd2
pr1_pru0_gpi10
gpio1_12
VDDSHV9
Yes
6
PU/PD
IO
IO
I
O
I
IO
IO
O
mcasp0_aclkx
pr1_pru0_gpo10
gpmc_ad13
dss_data18
mmc1_dat5
mmc2_dat1
eQEP2B_in
pr1_mii0_txd1
pr1_pru0_gpi11
gpio1_13
C11
gpmc_ad13
IO
O
PD
PD
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
IO
IO
I
O
I
IO
IO
O
mcasp0_fsx
pr1_pru0_gpo11
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
43
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B11
gpmc_ad14
gpmc_ad14
dss_data17
mmc1_dat6
mmc2_dat2
eQEP2_index
pr1_mii0_txd0
pr1_pru0_gpi16
gpio1_14
0x0
IO
O
PD
PD
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
IO
IO
IO
O
I
IO
IO
IO
O
mcasp0_axr0
gpmc_ad15
dss_data16
mmc1_dat7
mmc2_dat3
eQEP2_strobe
pr1_ecap0_ecap_capin_apwm_o
gpio1_15
A11
gpmc_ad15
PD
PD
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
IO
IO
IO
IO
IO
IO
IO
O
mcasp0_axr1
spi3_cs1
A9
gpmc_advn_ale
gpmc_be0n_cle
gpmc_advn_ale
spi0_cs3
PU
PU
PU
PU
Mode7
Mode7
VDDSHV10
VDDSHV10
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
IO
IO
IO
IO
O
timer4
qspi_d0
gpio2_2
C10
gpmc_be0n_cle
spi1_cs3
IO
IO
I
timer5
qspi_d3
pr1_mii1_rxlink
gpmc_a5
I
O
spi3_cs1
IO
IO
gpio2_5
44
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
A3
gpmc_be1n
gpmc_be1n
gmii2_col
0x0
O
I
PU
PU
Mode7
VDDSHV11
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x3
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
gpmc_csn6
mmc2_dat3
gpmc_dir
O
IO
O
I
pr1_mii1_col
mcasp0_aclkr
gpio1_28
IO
IO
IO
I
A12
gpmc_clk
gpmc_clk
PD
PD
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
gpmc_wait1
mmc2_clk
IO
I
pr1_mii1_crs
pr1_mdio_mdclk
mcasp0_fsr
gpio2_1
O
IO
IO
IO
O
O
IO
O
IO
IO
I
gpio0_4
A8
B9
gpmc_csn0
gpmc_csn1
gpmc_csn0
PU
PU
PU
PU
Mode7
Mode7
VDDSHV10
VDDSHV10
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
qspi_csn
gpio1_29
gpmc_csn1
gpmc_clk
mmc1_clk
pr1_edio_data_in6
pr1_edio_data_out6
pr1_pru0_gpo8
pr1_pru0_gpi8
gpio1_30
O
O
I
IO
O
O
IO
I
F10
gpmc_csn2
gpmc_csn2
PU
PU
Mode7
VDDSHV10
Yes
6
PU/PD
LVCMOS
gpmc_be1n
mmc1_cmd
pr1_edio_data_in7
pr1_edio_data_out7
pr1_pru0_gpo9
pr1_pru0_gpi9
gpio1_31
O
O
I
IO
I
gmii2_crs
rmii2_crs_dv
I
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
45
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B12
gpmc_csn3
gpmc_csn3
gpmc_wait0
qspi_clk
0x0
O
I
PU
PU
Mode7
VDDSHV9
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
IO
IO
I
mmc2_cmd
pr1_mii0_crs
pr1_mdio_data
EMU4
IO
IO
IO
I
gpio2_0
gmii2_crs
rmii2_crs_dv
gpmc_oen_ren
spi0_cs2
I
E10
gpmc_oen_ren
O
IO
IO
I
PU
PU
PU
PU
Mode7
Mode7
VDDSHV10
VDDSHV11
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
timer7
qspi_d1
gpio2_3
IO
I
A2
gpmc_wait0
gpmc_wait0
gmii2_crs
gpmc_csn4
rmii2_crs_dv
mmc1_sdcd
pr1_mii1_crs
uart4_rxd
gpio0_30
I
O
I
I
I
I
IO
IO
O
IO
IO
I
gpio5_30
D10
gpmc_wen
gpmc_wpn
gpmc_wen
spi1_cs2
PU
PU
PU
PU
Mode7
Mode7
VDDSHV10
VDDSHV11
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
timer6
qspi_d2
gpio2_4
IO
O
I
B3
gpmc_wpn
gmii2_rxer
gpmc_csn5
rmii2_rxer
mmc2_sdcd
pr1_mii1_rxer
uart4_txd
gpio0_31
O
I
I
I
O
IO
IO
gpio5_31
46
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
Y22
I2C0_SCL
I2C0_SCL
timer7
0x0
IOD
OFF
OFF
OFF
PU
PU
PD
Mode7
Mode7
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
IO
O
uart2_rtsn
eCAP1_in_PWM1_out
gpio3_6
IO
IO
IOD
IO
IO
IO
IO
IO
I
AB24
I2C0_SDA
I2C0_SDA
VDDSHV3
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
timer4
uart2_ctsn
eCAP2_in_PWM2_out
gpio3_5
L23
mcasp0_aclkr
mcasp0_aclkr
eQEP0A_in
mcasp0_axr2
mcasp1_aclkx
mmc0_sdwp
pr0_pru0_gpo4
pr0_pru0_gpi4
gpio3_18
IO
IO
I
O
I
IO
IO
IO
O
gpio0_18
N24
mcasp0_aclkx
mcasp0_aclkx
ehrpwm0A
OFF
PD
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
spi0_cs3
IO
IO
I
spi1_sclk
mmc0_sdcd
pr0_pru0_gpo0
pr0_pru0_gpi0
gpio3_14
O
I
IO
IO
I
M24
mcasp0_ahclkr
mcasp0_ahclkr
ehrpwm0_synci
mcasp0_axr2
spi1_cs0
OFF
PD
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
IO
IO
IO
O
eCAP2_in_PWM2_out
pr0_pru0_gpo3
pr0_pru0_gpi3
gpio3_17
I
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
47
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
L24
mcasp0_ahclkx
mcasp0_ahclkx
eQEP0_strobe
mcasp0_axr3
mcasp1_axr1
EMU4
0x0
IO
IO
IO
IO
IO
O
OFF
PD
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
pr0_pru0_gpo7
pr0_pru0_gpi7
gpio3_21
I
IO
IO
IO
I
gpio0_3
H23
M25
K23
mcasp0_axr0
mcasp0_axr1
mcasp0_fsr
mcasp0_axr0
ehrpwm0_tripzone_input
spi1_cs3
OFF
OFF
OFF
PD
PD
PD
Mode7
Mode7
Mode7
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
IO
IO
I
spi1_d1
mmc2_sdcd
pr0_pru0_gpo2
pr0_pru0_gpi2
gpio3_16
O
I
IO
IO
IO
IO
IO
O
mcasp0_axr1
eQEP0_index
mcasp1_axr0
EMU3
pr0_pru0_gpo6
pr0_pru0_gpi6
gpio3_20
I
IO
IO
IO
I
gpio0_2
mcasp0_fsr
eQEP0B_in
mcasp0_axr3
mcasp1_fsx
EMU2
IO
IO
IO
O
pr0_pru0_gpo5
pr0_pru0_gpi5
gpio3_19
I
IO
IO
gpio0_19
48
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
N22
mcasp0_fsx
mcasp0_fsx
ehrpwm0B
spi1_cs2
0x0
IO
O
IO
IO
I
OFF
PD
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
spi1_d0
mmc1_sdcd
pr0_pru0_gpo1
pr0_pru0_gpi1
gpio3_15
O
I
IO
O
IO
O
O
I
B17
mdio_clk
mdio_data
mii1_col
mdio_clk
PU
PU
Mode7
VDDSHV7
VDDSHV7
VDDSHV8
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
timer5
uart5_txd
uart3_rtsn
mmc0_sdwp
mmc1_clk
mmc2_clk
gpio0_1
IO
IO
IO
O
IO
IO
I
pr1_mdio_mdclk
mdio_data
timer6
A17
PU
PU
Mode7
LVCMOS
uart5_rxd
uart3_ctsn
mmc0_sdcd
mmc1_cmd
mmc2_cmd
gpio0_0
IO
I
IO
IO
IO
IO
I
pr1_mdio_data
gmii1_col
D16
PD
PD
Mode7
LVCMOS
rmii2_refclk
spi1_sclk
IO
IO
I
uart5_rxd
mcasp1_axr2
mmc2_dat3
mcasp0_axr2
gpio3_0
IO
IO
IO
IO
IO
gpio0_0
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
49
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B14
mii1_crs
gmii1_crs
0x0
I
PD
PD
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
rmii1_crs_dv
spi1_d0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
I
IO
I2C1_SDA
mcasp1_aclkx
uart5_ctsn
uart2_rxd
IOD
IO
I
IO
IO
I
gpio3_1
F17
B16
E16
mii1_rxd0
mii1_rxd1
mii1_rxd2
gmii1_rxd0
rmii1_rxd0
rgmii1_rd0
mcasp1_ahclkx
mcasp1_ahclkr
mcasp1_aclkr
mcasp0_axr3
gpio2_21
VDDSHV8
VDDSHV8
VDDSHV8
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
I
I
IO
IO
IO
IO
IO
I
gmii1_rxd1
rmii1_rxd1
rgmii1_rd1
mcasp1_axr3
mcasp1_fsr
eQEP0_strobe
mmc2_clk
I
I
IO
IO
IO
IO
IO
I
gpio2_20
gmii1_rxd2
uart3_txd
IO
I
rgmii1_rd2
mmc0_dat4
mmc1_dat3
uart1_rin
IO
IO
I
mcasp0_axr1
gpio2_19
IO
IO
IO
gpio0_11
50
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
C14
mii1_rxd3
gmii1_rxd3
uart3_rxd
0x0
I
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
IO
I
rgmii1_rd3
mmc0_dat5
mmc1_dat2
uart1_dtrn
mcasp0_axr0
gpio2_18
IO
IO
O
IO
IO
IO
I
gpio0_10
D13
mii1_rx_clk
gmii1_rxclk
uart2_txd
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
IO
I
rgmii1_rclk
mmc0_dat6
mmc1_dat1
uart1_dsrn
mcasp0_fsx
gpio3_10
IO
IO
I
IO
IO
IO
I
gpio0_9
A15
mii1_rx_dv
gmii1_rxdv
rgmii1_rctl
uart5_txd
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
I
O
IO
IO
IO
IO
IO
I
mcasp1_aclkx
mmc2_dat0
mcasp0_aclkr
gpio3_4
gpio0_1
B13
mii1_rx_er
gmii1_rxer
rmii1_rxer
spi1_d1
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
I
IO
I2C1_SCL
mcasp1_fsx
uart5_rtsn
uart2_txd
IOD
IO
O
IO
IO
gpio3_2
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
51
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
B15
mii1_txd0
mii1_txd1
mii1_txd2
gmii1_txd0
rmii1_txd0
rgmii1_td0
mcasp1_axr2
mcasp1_aclkr
eQEP0B_in
mmc1_clk
gpio0_28
0x0
O
PD
PD
PD
PD
PD
PD
Mode7
Mode7
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
O
O
IO
IO
I
IO
IO
O
A14
gmii1_txd1
rmii1_txd1
rgmii1_td1
mcasp1_fsr
mcasp1_axr1
eQEP0A_in
mmc1_cmd
gpio0_21
VDDSHV8
Yes
6
PU/PD
O
O
IO
IO
I
IO
IO
O
C13
gmii1_txd2
dcan0_rx
VDDSHV8
Yes
6
PU/PD
I
rgmii1_td2
uart4_txd
O
O
mcasp1_axr0
mmc2_dat2
mcasp0_ahclkx
gpio0_17
IO
IO
IO
IO
IO
O
gpio3_12
C16
mii1_txd3
gmii1_txd3
dcan0_tx
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
O
rgmii1_td3
uart4_rxd
O
I
mcasp1_fsx
mmc2_dat1
mcasp0_fsr
gpio0_16
IO
IO
IO
IO
IO
gpio3_11
52
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
D14
mii1_tx_clk
gmii1_txclk
uart2_rxd
0x0
I
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
IO
O
IO
IO
I
rgmii1_tclk
mmc0_dat7
mmc1_dat0
uart1_dcdn
mcasp0_aclkx
gpio3_9
IO
IO
IO
O
O
O
IO
IO
IO
IO
IO
IO
O
IO
IO
O
O
I
gpio0_8
A13
mii1_tx_en
mmc0_clk
mmc0_cmd
gmii1_txen
rmii1_txen
rgmii1_tctl
timer4
PD
PD
Mode7
Mode7
Mode7
VDDSHV8
VDDSHV1
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
mcasp1_axr0
eQEP0_index
mmc2_cmd
gpio3_3
D1
mmc0_clk
gpmc_a24
uart3_ctsn
uart2_rxd
OFF
OFF
dcan1_tx
pr0_pru0_gpo12
pr0_pru0_gpi12
gpio2_30
IO
IO
O
O
IO
I
D2
mmc0_cmd
gpmc_a25
uart3_rtsn
uart2_txd
OFF
OFF
dcan1_rx
pr0_pru0_gpo13
pr0_pru0_gpi13
gpio2_31
O
I
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
53
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
C1
mmc0_dat0
mmc0_dat1
mmc0_dat2
mmc0_dat3
nTRST
mmc0_dat0
gpmc_a23
uart5_rtsn
uart3_txd
0x0
IO
O
O
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Mode7
Mode7
Mode7
Mode7
VDDSHV1
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x0
uart1_rin
pr0_pru0_gpo11
pr0_pru0_gpi11
gpio2_29
O
I
IO
IO
O
I
C2
B2
B1
mmc0_dat1
gpmc_a22
uart5_ctsn
uart3_rxd
VDDSHV1
VDDSHV1
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
IO
O
O
I
uart1_dtrn
pr0_pru0_gpo10
pr0_pru0_gpi10
gpio2_28
IO
IO
O
O
IO
I
mmc0_dat2
gpmc_a21
uart4_rtsn
timer6
uart1_dsrn
pr0_pru0_gpo9
pr0_pru0_gpi9
gpio2_27
O
I
IO
IO
O
I
mmc0_dat3
gpmc_a20
uart4_ctsn
timer5
IO
I
uart1_dcdn
pr0_pru0_gpo8
pr0_pru0_gpi8
gpio2_26
O
I
IO
I
Y25
Y23
nTRST
PD
Z
PD
Z
Mode0
Mode0
VDDSHV3
Yes
Yes
NA
NA
PU/PD
NA
LVCMOS
LVCMOS
PWRONRSTn
porz
I
VDDSHV3 (13)
54
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AA10, AA7,
AA9, AB10,
AB6, AB7,
AB9, AC10,
AC12, AC5,
AC6, AC7,
AC9, AD1,
AD10, AD11,
AD2, AD7,
AE11, AE12,
AE9, H19,
Reserved
Reserved (7)
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
H21, W10,
Y10, Y6, Y7
A16
rmii1_ref_clk
rmii1_refclk
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
IO
I
PD
PD
Mode7
VDDSHV8
Yes
6
PU/PD
LVCMOS
xdma_event_intr2
spi1_cs0
IO
O
IO
O
IO
IO
I
uart5_txd
mcasp1_axr3
mmc0_pow
mcasp1_ahclkx
gpio0_29
AE2
AD6
AE6
AE3
AE5
AE4
T20
RTC_KALDO_ENn
RTC_PMIC_EN
RTC_PWRONRSTn
RTC_WAKEUP
RTC_XTALIN
RTC_KALDO_ENn
RTC_PMIC_EN
RTC_PORz
RTC_WAKEUP
OSC1_IN
Z
Z
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
Mode7
VDDS_RTC
VDDS_RTC
VDDS_RTC
VDDS_RTC
VDDS_RTC
VDDS_RTC
VDDSHV3
NA
NA
6
NA
Analog
O
I
PU
Z
1
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Z
Yes
Yes
Yes
NA
NA
NA
NA
NA (14)
6
NA
I
PD
H
Z
NA
I
H
PU (2)
NA
RTC_XTALOUT
spi0_cs0
OSC1_OUT
spi0_cs0
O
IO
I
Z
Z (24)
PU
OFF
Yes
PU/PD
mmc2_sdwp
I2C1_SCL
IOD
I
ehrpwm0_synci
pr1_uart0_txd
pr0_uart0_txd
pr1_edio_data_out1
gpio0_5
O
O
O
IO
O
ehrpwm1B
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
55
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
R25
spi0_cs1
spi0_cs1
0x0
IO
IO
IO
O
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
uart3_rxd
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
eCAP1_in_PWM1_out
mmc0_pow
xdma_event_intr2
mmc0_sdcd
EMU4
I
I
IO
IO
O
gpio0_6
ehrpwm2A
timer0
IO
IO
IO
T22
spi0_d0
spi0_d0
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
uart2_txd
I2C2_SCL
IOD
O
ehrpwm0B
pr1_uart0_rts_n
pr0_uart0_rts_n
EMU3
O
O
IO
IO
IO
I
gpio0_3
T21
spi0_d1
spi0_d1
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
mmc1_sdwp
I2C1_SDA
ehrpwm0_tripzone_input
pr1_uart0_rxd
pr0_uart0_rxd
pr1_edio_data_out0
gpio0_4
IOD
I
I
I
O
IO
O
ehrpwm1A
spi0_sclk
P23
spi0_sclk
IO
IO
IOD
O
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
uart2_rxd
I2C2_SDA
ehrpwm0A
pr1_uart0_cts_n
pr0_uart0_cts_n
EMU2
I
I
IO
IO
gpio0_2
56
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
T23
spi2_cs0
spi2_cs0
0x0
IO
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
I2C1_SDA
0x1
0x6
0x7
0x9
0x0
0x6
0x7
0x9
0x0
0x6
0x7
0x9
0x0
0x1
0x6
0x7
0x9
0x0
0x6
0x7
0x0
0x6
0x7
0x0
0x6
0x7
0x0
0x6
0x7
0x0
0x0
0x0
0x0
IOD
I
ehrpwm2_tripzone_input
gpio3_25
IO
IO
IO
I
gpio0_23
P22
P20
N20
spi2_d0
spi2_d1
spi2_sclk
spi2_d0
OFF
OFF
OFF
PD
PU
PD
Mode7
Mode7
Mode7
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
ehrpwm5_tripzone_input
gpio3_22
IO
IO
IO
I
gpio0_20
spi2_d1
ehrpwm1_tripzone_input
gpio3_23
IO
IO
IO
IOD
I
gpio0_21
spi2_sclk
I2C1_SCL
ehrpwm4_tripzone_input
gpio3_24
IO
IO
IO
I
gpio0_22
N25
R24
P24
P25
spi4_cs0
spi4_d0
spi4_d1
spi4_sclk
spi4_cs0
OFF
OFF
OFF
OFF
PU
PD
PD
PD
Mode7
Mode7
Mode7
Mode7
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
ehrpwm3_tripzone_input
gpio5_7
IO
IO
I
spi4_d0
ehrpwm3_synci
gpio5_5
IO
IO
I
spi4_d1
ehrpwm0_tripzone_input
gpio5_6
IO
IO
I
spi4_sclk
ehrpwm0_synci
gpio5_4
IO
I
AA25
Y20
TCK
TDI
TCK
PU
PU
PU
PU
PU
PU
PU
PU
Mode0
Mode0
Mode0
Mode0
VDDSHV3
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
Yes
NA
NA
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TDI
I
AA24
Y24
TDO
TMS
TDO
O
I
TMS
6
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
57
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
L25
uart0_ctsn
uart0_rtsn
uart0_rxd
uart0_txd
uart0_ctsn
uart4_rxd
0x0
I
OFF
OFF
OFF
OFF
PU
PU
PU
PU
Mode7
Mode7
Mode7
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
I
dcan1_tx
O
I2C1_SDA
spi1_d0
IOD
IO
IO
O
timer7
pr1_edc_sync0_out
gpio1_8
IO
O
J25
K25
J24
uart0_rtsn
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
uart4_txd
O
dcan1_rx
I
I2C1_SCL
spi1_d1
IOD
IO
IO
O
spi1_cs0
pr1_edc_sync1_out
gpio1_9
IO
I
uart0_rxd
spi1_cs0
IO
O
dcan0_tx
I2C2_SDA
eCAP2_in_PWM2_out
pr0_pru1_gpo4
pr0_pru1_gpi4
gpio1_10
IOD
IO
O
I
IO
O
uart0_txd
spi1_cs1
IO
I
dcan0_rx
I2C2_SCL
eCAP1_in_PWM1_out
pr0_pru1_gpo5
pr0_pru1_gpi5
gpio1_11
IOD
IO
O
I
IO
58
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
K22
uart1_ctsn
uart1_ctsn
timer6
0x0
IO
IO
O
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x5
0x6
0x7
0x0
0x2
0x4
0x5
0x6
0x7
dcan0_tx
I2C2_SDA
spi1_cs0
IOD
IO
I
pr1_uart0_cts_n
pr1_edc_latch0_in
gpio0_12
I
IO
O
IO
I
L22
uart1_rtsn
uart1_rtsn
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
timer5
dcan0_rx
I2C2_SCL
IOD
IO
O
I
spi1_cs1
pr1_uart0_rts_n
pr1_edc_latch1_in
gpio0_13
IO
IO
I
K21
L21
H22
uart1_rxd
uart1_txd
uart3_ctsn
uart1_rxd
OFF
OFF
OFF
PU
PU
PU
Mode7
Mode7
Mode7
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
mmc1_sdwp
dcan1_tx
O
IOD
I
I2C1_SDA
pr1_uart0_rxd
pr1_pru0_gpi16
gpio0_14
I
IO
IO
I
uart1_txd
mmc2_sdwp
dcan1_rx
I
I2C1_SCL
IOD
O
I
pr1_uart0_txd
pr1_pru0_gpi16
gpio0_15
IO
IO
IO
O
I
uart3_ctsn
spi4_cs1
pr0_pru1_gpo18
pr0_pru1_gpi18
ehrpwm5A
gpio5_0
O
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
59
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
K24
uart3_rtsn
uart3_rtsn
0x0
O
OFF
PU
Mode7
VDDSHV3
Yes
6
PU/PD
LVCMOS
hdq_sio
0x1
0x4
0x5
0x6
0x7
0x0
0x4
0x5
0x6
0x7
0x0
0x4
0x5
0x6
0x7
0x0
IOD
O
I
pr0_pru1_gpo19
pr0_pru1_gpi19
ehrpwm5B
gpio5_1
O
IO
IO
O
I
H25
H24
uart3_rxd
uart3_txd
uart3_rxd
OFF
OFF
PU
PU
Mode7
Mode7
VDDSHV3
VDDSHV3
Yes
Yes
6
6
PU/PD
PU/PD
LVCMOS
LVCMOS
pr0_pru0_gpo18
pr0_pru0_gpi18
ehrpwm4A
gpio5_2
O
IO
IO
O
I
uart3_txd
pr0_pru0_gpo19
pr0_pru0_gpi19
ehrpwm4B
gpio5_3
O
IO
A
W22
W24
W25
G21
USB0_CE
USB0_DM
USB0_DP
USB0_CE
Z
Z
Mode0
Mode0
Mode0
Mode0
VDDA3P3V_USB0/V NA
DDA1P8V_USB0
NA
NA
Analog
Analog
Analog
LVCMOS
USB0_DM
USB0_DP
0x0
0x0
A
A
Z
Z
VDDA3P3V_USB0/V NA (15)
DDA1P8V_USB0
8 (15)
8 (15)
6
NA
Z
Z
VDDA3P3V_USB0/V NA (15)
DDA1P8V_USB0
NA
USB0_DRVVBUS
USB0_DRVVBUS
gpio0_18
0x0
0x7
0x9
0x0
O
PD
PD
VDDSHV3
Yes
PU/PD
IO
IO
A
gpio5_27
U24
U23
U22
V25
V24
F25
USB0_ID
USB0_ID
Z
Z
Mode0
Mode0
Mode0
Mode0
Mode0
Mode0
VDDA3P3V_USB0/V NA
DDA1P8V_USB0
NA
NA
Analog
Analog
Analog
Analog
Analog
LVCMOS
USB0_VBUS
USB1_CE
USB0_VBUS
USB1_CE
USB1_DM
USB1_DP
0x0
0x0
0x0
0x0
A
A
A
A
Z
Z
VDDA3P3V_USB0/V NA
DDA1P8V_USB0
NA
NA
Z
Z
VDDA3P3V_USB1/V NA
DDA1P8V_USB1
NA
NA
USB1_DM
Z
Z
VDDA3P3V_USB1/V NA (16)
DDA1P8V_USB1
8 (16)
8 (16)
6
NA
USB1_DP
Z
Z
VDDA3P3V_USB1/V NA (16)
DDA1P8V_USB1
NA
USB1_DRVVBUS
USB1_DRVVBUS
gpio3_13
0x0
0x7
0x9
0x0
O
PD
PD
VDDSHV3
Yes
PU/PD
IO
IO
A
gpio0_25
U25
USB1_ID
USB1_ID
Z
Z
Mode0
VDDA3P3V_USB1/V NA
DDA1P8V_USB1
NA
NA
Analog
60
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
T25
USB1_VBUS
VDDA1P8V_USB0
USB1_VBUS
0x0
A
Z
Z
Mode0
VDDA3P3V_USB1/V NA
DDA1P8V_USB1
NA
NA
Analog
W21
U21
W20
U20
AB12
Y16
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA_ADC0
NA
NA
NA
NA
NA
NA
NA
POWER
POWER
POWER
POWER
POWER
POWER
POWER
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA_ADC0
VDDA_ADC1
VDDA_ADC1
AD12, AD8,
F20, G6, H12,
P19, W15,
Y19
VDDS
VDDS (1)
F8
VDDS3P3V_IOLDO
VDDSHV1
VDDS3P3V_IOLDO
VDDSHV1
NA
NA
NA
POWER
POWER
POWER
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
J7, J8
V16, V17,
W16
VDDSHV2
VDDSHV2
J18, K17,
K18, N18,
N19, P18,
W18
VDDSHV3
VDDSHV3
NA
POWER
NA
NA
NA
NA
NA
NA
NA
NA
F22
VDDSHV5
VDDSHV6
VDDSHV5
VDDSHV6
NA
NA
POWER
POWER
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
G16, G17,
H17
F16
VDDSHV7
VDDSHV7
NA
NA
NA
NA
NA
NA
NA
POWER
POWER
POWER
POWER
POWER
POWER
POWER
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
G13, G14
G11, H11
G10, H10
H8, H9
E23
VDDSHV8
VDDSHV8
VDDSHV9
VDDSHV9
VDDSHV10
VDDSHV11
VDDS_CLKOUT
VDDS_DDR
VDDSHV10
VDDSHV11
VDDS_CLKOUT
VDDS_DDR
K7, K8, M7,
M8, N7, N8,
R6, R7, R8,
T7, T8, V7,
V8
C23
N21
G5
VDDS_OSC
VDDS_OSC
NA
NA
NA
NA
NA
NA
NA
POWER
POWER
POWER
POWER
POWER
POWER
POWER
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_RTC
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
VDDS_PLL_MPU
VDDS_RTC
E17
AD5
F13
F14
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
61
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
AD9, J10,
VDD_CORE
VDD_CORE (11)
NA
POWER
NA
NA
NA
NA
NA
NA
NA
NA
J11, L12, L14,
M12, M14,
M9, N16, N17,
N9, P16, P17,
R11, R14, R9,
T11, T14,
T18, T19, T9,
U15, V15,
W12, W13
H13, H14,
H16, J13, J14,
J16, K19,
K20, L19,
L20, M17,
M18
VDD_MPU
VDD_MPU
NA
POWER
NA
NA
NA
NA
NA
NA
NA
NA
D20
P21
vdd_mpu_mon
VPP
vdd_mpu_mon (25)
VPP (18)
NA
NA
NA
POWER
POWER
GROUND
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
A1, A25,
VSS
VSS (12)
AA23, AE1,
AE10, AE25,
AE7, AE8,
H15, H18,
J12, J15, J17,
J9, K11, K12,
K14, K15, K9,
L11, L15, L17,
L18, L8, L9,
M10, M11,
M13, M15,
M16, N10,
N11, N12,
N13, N14,
N15, P10,
P11, P12,
P13, P14,
P15, P8, P9,
R12, R15,
R17, R18,
T12, T15,
T17, U10,
U11, U12,
U13, U14,
U16, U17,
U18, U19, U8,
U9, V10, V11,
V12, V13,
V14, V18, V9
AC15
W23
B24
VSSA_ADC
VSSA_USB
VSS_OSC
VSS_RTC
VSSA_ADC
NA
NA
NA
NA
0x0
GROUND
GROUND
GROUND
GROUND
IOD (9)
NA
NA
NA
NA
OFF
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Yes
NA
NA
NA
NA
6
NA
NA
VSSA_USB
NA
NA
NA
NA
VSS_OSC (26)
VSS_RTC (27)
nRESETIN_OUT
NA
NA
NA
NA
AD4
G22
NA
NA
NA
NA
WARMRSTn
PU (17)
Mode0
VDDSHV3
PU/PD
LVCMOS
62
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-7. Pin Attributes (ZDN Package) (continued)
BALL
RESET
REL.
BALL
RESET
STATE [6]
BALL RESET
REL. MODE
[8]
BUFFER
STRENGTH
(mA) [11]
PULL
BALL
NUMBER [1]
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
POWER [9]
HYS [10]
UP/DOWN IO CELL [13]
TYPE [12]
STATE [7]
D24
xdma_event_intr0
xdma_event_intr0
0x0
I
OFF
PD (8)
Mode7
VDDSHV5
Yes
6
PU/PD
LVCMOS
ext_hw_trigger
timer4
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x0 (3)
0x0
I
IO
O
IO
I
clkout1
spi1_cs1
pr1_pru0_gpi16
EMU2
IO
IO
IO
IO
I
gpio0_19
pr1_mdio_data
gpio5_28
C24
xdma_event_intr1
xdma_event_intr1
spi0_cs2
OFF
PD
Mode7
VDDSHV5
Yes
6
PU/PD
LVCMOS
IO
I
tclkin
clkout2
O
IO
I
timer7
pr1_pru0_gpi16
EMU3
IO
IO
O
IO
I
gpio0_20
pr1_mdio_mdclk
gpio5_29
C25
B25
XTALIN
OSC0_IN
OSC0_OUT
Z
Z
Z
Z
Mode0
Mode0
VDDS_OSC
VDDS_OSC
Yes
NA
NA
PD
NA
LVCMOS
LVCMOS
XTALOUT
O
NA (14)
(1) AD12 and AD8 are not connected to VDDS in the device, but they are required to be connected to 1.8-V VDDS on the board.
(2) An internal 10-kΩ pullup is turned on when the oscillator is disabled. The oscillator is disabled by default after power is applied.
(3) An internal 15-kΩ pulldown is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
(4) DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
(5) DSS_HSYNC terminal is SYSBOOT[17] input, latched on the rising edge of PWRONRSTn.
(6) DSS_VSYNC terminal is SYSBOOT[16] input, latched on the rising edge of PWRONRSTn.
(7) Do not connect any signal, test point, or board trace to reserved signals.
(8) If sysboot[17] is low on the rising edge of PWRONRSTn, this terminal has an internal pulldown turned on after reset is released. If sysboot[17] is high on the rising edge or PWRONRSTn,
this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the OSC0_IN terminal.
(9) See the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this terminal.
(10) Reset Release Mode = 7 if sysboot[17] is low. Mode = 3 if sysboot[17] is high.
(11) Terminal AD9 is not connected to VDD_CORE in the device, but it is required to be connected to VDD_CORE on the board.
(12) Terminals AA23, AE10, AE7, AE8 are not connected to VSS in the device, but they are required to be connected to board ground.
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
63
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
(13) The input voltage thresholds for this input are not a function of VDDSHV3. See the DC Electrical Characteristics section for details related to electrical parameters associated with this
input terminal.
(14) This output should only be used to source the recommended crystal circuit.
(15) This parameter only applies when this USB PHY terminal is operating in UART2 mode.
(16) This parameter only applies when this USB PHY terminal is operating in UART3 mode.
(17) This pin is configured as open-drain and, hence, is expected to have an external pullup resistor. However, there is also an internal PU resistor by default enabled after reset is
deasserted.
(18) This signal is valid only for High-Security (AM437xHS) devices. For more details, see the VPP Specification for One-Time Programmable (OTP) eFUSEs section. This signal is reserved
for AM437x devices and, thus, do not connect any signal, test point, or board trace to this signal for AM437x devices.
(19) This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
(20) This terminal is an analog passive signal that connects to an external 49.9 Ω 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
(21) This terminal is analog input that may also be configured as an open-drain output.
(22) This terminal is analog input that may also be configured as an open-source or open-drain output.
(23) This terminal is analog input that may also be configured as an open-source output.
(24) This terminal is high-Z when the oscillator is disabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a
unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
(25) This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the
PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.
(26) This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC0_IN/OSC0_OUT terminals, the crystal circuit component
grounds should be connected to this terminal and also be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the OSC0_IN
terminal, this terminal should be connected to VSS.
(27) This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC1_IN/OSC1_OUT terminals, the crystal circuit component
grounds should be connected to this terminal and also should be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the
OSC1_IN terminal, this terminal should be connected to VSS.
64
Terminal Configuration and Functions
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3 Signal Descriptions
The device contains many peripheral interfaces. In order to reduce package size and lower overall system
cost while maintaining maximum functionality, many of the terminals can multiplex up to eight signal
functions. Although there are many combinations of pin multiplexing that are possible, only a certain
number of sets, called IO Sets, are valid due to timing limitations. These valid IO Sets were carefully
chosen to provide many possible application scenarios for the user.
TI has developed a Windows-based application called Pin Mux Utility that helps a system designer select
the appropriate pin-multiplexing configuration for their device-based product design. The Pin Mux Utility
provides a way to select valid IO Sets of specific peripheral interfaces to ensure the pin-multiplexing
configuration selected for a design only uses valid IO Sets supported by the device.
(1) SIGNAL NAME: The signal name
(2) DESCRIPTION: Description of the signal.
(3) TYPE: Ball type for this specific function:
–
–
–
–
–
–
I = Input
O = Output
I/O = Input/Output
D = Open drain
DS = Differential
A = Analog
(4) BALL: Package ball location.
4.3.1 ADC Interfaces
Table 4-8. ADC0 Signal Descriptions
SIGNAL NAME [1]
ADC0_AIN0
DESCRIPTION [2]
Analog Input/Output
TYPE [3]
ZDN [4]
AA12
Y12
A
A
ADC0_AIN1
Analog Input/Output
ADC0_AIN2
Analog Input/Output
A
Y13
ADC0_AIN3
Analog Input/Output
A
AA13
AB13
AC13
AD13
AE13
AE14
AD14
ADC0_AIN4
Analog Input/Output
A
ADC0_AIN5
Analog Input/Output
A
ADC0_AIN6
Analog Input/Output
A
ADC0_AIN7
Analog Input/Output
A
ADC0_VREFN
ADC0_VREFP
Analog Negative Reference Input
Analog Positive Reference Input
AP
AP
Table 4-9. ADC0/1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
ext_hw_trigger
External Hardware Trigger for ADC conversion
I
AC25, D24
Table 4-10. ADC1 Signal Descriptions
SIGNAL NAME [1]
ADC1_AIN0
DESCRIPTION [2]
Analog Input/Output
TYPE [3]
ZDN [4]
AC16
AB16
AA16
AB15
AA15
Y15
A
A
ADC1_AIN1
Analog Input/Output
ADC1_AIN2
Analog Input/Output
A
ADC1_AIN3
Analog Input/Output
A
ADC1_AIN4
Analog Input/Output
A
ADC1_AIN5
Analog Input/Output
A
ADC1_AIN6
Analog Input/Output
A
AE16
AD16
AD15
ADC1_AIN7
Analog Input/Output
A
ADC1_VREFN
Analog Negative Reference Input
AP
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
65
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-10. ADC1 Signal Descriptions (continued)
SIGNAL NAME [1]
ADC1_VREFP
DESCRIPTION [2]
Analog Positive Reference Input
TYPE [3]
ZDN [4]
AP
AE15
66
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.2 CAN Interfaces
Table 4-11. DCAN0 Signal Descriptions
SIGNAL NAME [1]
dcan0_rx
DESCRIPTION [2]
DCAN0 Receive Data
TYPE [3]
ZDN [4]
I
C13, J24, L22
C16, K22, K25
dcan0_tx
DCAN0 Transmit Data
O
Table 4-12. DCAN1 Signal Descriptions
SIGNAL NAME [1]
dcan1_rx
DESCRIPTION [2]
DCAN1 Receive Data
TYPE [3]
ZDN [4]
I
D2, J25, L21
D1, K21, L25
dcan1_tx
DCAN1 Transmit Data
O
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
67
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.3 Camera (VPFE) Interfaces
Table 4-13. Camera0 Input Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
AE18
cam0_data0
cam0_data1
cam0_data2
cam0_data3
cam0_data4
cam0_data5
cam0_data6
cam0_data7
cam0_data8
cam0_data9
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
Camera data
I
I
AB18
I
Y18
I
AA18
I
AE19
I
AD19
I
AE20
I
I
AD20
AB19
I
AA19
cam0_data10
cam0_data11
cam0_field
cam0_hd
I
AC18, AC25
AB25, AD17
AC18
I
CCD Data Field Indicator
CCD Data Horizontal Detect
CCD Data Pixel Clock
IO
IO
I
AE17
cam0_pclk
cam0_vd
AC20
CCD Data Vertical Detect
CCD Data Write Enable
IO
I
AD18
cam0_wen
AD17
Table 4-14. Camera1 Input Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
Camera data
TYPE [3]
ZDN [4]
AB20
cam1_data0
cam1_data1
cam1_data2
cam1_data3
cam1_data4
cam1_data5
cam1_data6
cam1_data7
cam1_data8
cam1_data9
cam1_data10
cam1_data11
cam1_field
cam1_hd
I
Camera data
I
AC21
Camera data
I
AD21
Camera data
I
AE22
Camera data
I
AD22
Camera data
I
AE23
Camera data
I
AD23
Camera data
I
I
AE24
Camera data
AB18, AD24
AC24, AE18
AC18, AC25, Y18
AA18, AB25, AD17
AC25
Camera data
I
Camera data
I
Camera data
I
CCD Data Field Indicator
CCD Data Horizontal Detect
CCD Data Pixel Clock
CCD Data Vertical Detect
CCD Data Write Enable
IO
IO
I
AD25
cam1_pclk
AE21
cam1_vd
IO
I
AC23
cam1_wen
AB25, AE19
68
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.4 Debug Subsystem Interface
Table 4-15. Debug Subsystem Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MISC EMULATION PIN
TYPE [3]
ZDN [4]
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
nTRST
TCK
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
N23
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
MISC EMULATION PIN
JTAG TEST RESET (ACTIVE LOW)
JTAG TEST CLOCK
T24
AE17, D24, K23, P23
AD18, C24, M25, T22
AC18, B12, L24, R25
AD17
AC20
AB19
AA19
AC24
AD24, AE17
AB25, AD18
Y25
I
AA25
TDI
JTAG TEST DATA INPUT
JTAG TEST DATA OUTPUT
JTAG TEST MODE SELECT
I
Y20
TDO
O
AA24
TMS
I
Y24
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
69
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.5 Display Subsystem (DSS) Interface
Table 4-16. Display Subsystem (DSS) Signal Descriptions
SIGNAL NAME [1]
dss_ac_bias_en
DESCRIPTION [2]
TYPE [3]
O
ZDN [4]
A24
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
DSS data
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
dss_data11
dss_data12
dss_data13
dss_data14
dss_data15
dss_data16
dss_data17
dss_data18
dss_data19
dss_data20
dss_data21
dss_data22
dss_data23
dss_hsync
dss_pclk
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
B22
A21
B21
C21
A20
B20
C20
E19
A19
B19
A18
B18
C19
D19
C17
D17
A11, AC24
AA19, B11
AB19, C11
AC20, E11
AD17, D11
AC18, F11
A10, AD18
AE17, B10
A23
O
O
O
O
O
O
O
DSS Horizontal Sync
DSS Pixel Clock
O
O
A22
dss_vsync
DSS Vertical Sync
O
B23
70
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.6 Ethernet (GEMAC_CPSW) Interfaces
Table 4-17. MDIO Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
B17
mdio_clk
MDIO Clk
O
mdio_data
MDIO Data
IO
A17
Table 4-18. MII1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MII Colision
TYPE [3]
ZDN [4]
D16
B14
D13
F17
gmii1_col
I
I
gmii1_crs
MII Carrier Sense
gmii1_rxclk
gmii1_rxd0
gmii1_rxd1
gmii1_rxd2
gmii1_rxd3
gmii1_rxdv
gmii1_rxer
gmii1_txclk
gmii1_txd0
gmii1_txd1
gmii1_txd2
gmii1_txd3
gmii1_txen
MII Receive Clock
I
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
B16
E16
C14
A15
B13
D14
B15
A14
C13
C16
A13
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 4-19. MII2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MII Colision
TYPE [3]
ZDN [4]
gmii2_col
I
I
A3
gmii2_crs
MII Carrier Sense
A2, B12, F10
gmii2_rxclk
gmii2_rxd0
gmii2_rxd1
gmii2_rxd2
gmii2_rxd3
gmii2_rxdv
gmii2_rxer
gmii2_txclk
gmii2_txd0
gmii2_txd1
gmii2_txd2
gmii2_txd3
gmii2_txen
MII Receive Clock
I
F6
D8
G8
B4
F7
C5
B3
E8
E7
D7
A4
C6
C3
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Transmit Clock
I
I
I
I
I
I
I
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
O
O
O
O
O
Table 4-20. RGMII1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Clock
TYPE [3]
ZDN [4]
D13
rgmii1_rclk
rgmii1_rctl
rgmii1_rd0
I
I
I
RGMII Receive Control
A15
RGMII Receive Data bit 0
F17
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
71
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-20. RGMII1 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Data bit 1
TYPE [3]
ZDN [4]
B16
rgmii1_rd1
rgmii1_rd2
rgmii1_rd3
rgmii1_tclk
rgmii1_tctl
rgmii1_td0
rgmii1_td1
rgmii1_td2
rgmii1_td3
I
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
I
E16
I
C14
D14
A13
O
O
O
O
O
O
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
B15
A14
C13
C16
Table 4-21. RGMII2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
RGMII Receive Clock
TYPE [3]
ZDN [4]
F6
rgmii2_rclk
rgmii2_rctl
rgmii2_rd0
rgmii2_rd1
rgmii2_rd2
rgmii2_rd3
rgmii2_tclk
rgmii2_tctl
rgmii2_td0
rgmii2_td1
rgmii2_td2
rgmii2_td3
I
I
RGMII Receive Control
C5
RGMII Receive Data bit 0
RGMII Receive Data bit 1
RGMII Receive Data bit 2
RGMII Receive Data bit 3
RGMII Transmit Clock
I
D8
I
G8
B4
I
I
F7
O
O
O
O
O
O
E8
RGMII Transmit Control
RGMII Transmit Data bit 0
RGMII Transmit Data bit 1
RGMII Transmit Data bit 2
RGMII Transmit Data bit 3
C3
E7
D7
A4
C6
Table 4-22. RMII1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
RMII Carrier Sense / Data Valid
RMII Reference Clock
TYPE [3]
ZDN [4]
B14
rmii1_crs_dv
rmii1_refclk
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
I
IO
I
A16
RMII Receive Data bit 0
RMII Receive Data bit 1
RMII Receive Data Error
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
F17
I
B16
I
B13
O
O
O
B15
A14
A13
Table 4-23. RMII2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
RMII Carrier Sense / Data Valid
RMII Reference Clock
TYPE [3]
ZDN [4]
rmii2_crs_dv
rmii2_refclk
rmii2_rxd0
rmii2_rxd1
rmii2_rxer
rmii2_txd0
rmii2_txd1
rmii2_txen
I
IO
I
A2, B12, B4, F10
D16
D8
G8
B3
RMII Receive Data bit 0
RMII Receive Data bit 1
RMII Receive Data Error
RMII Transmit Data bit 0
RMII Transmit Data bit 1
RMII Transmit Enable
I
I
O
O
O
E7
D7
C3
72
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.7 External Memory Interfaces
Table 4-24. DDR Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM ROW/COLUMN ADDRESS
DDR SDRAM BANK ADDRESS
TYPE [3]
ZDN [4]
N1
L1
ddr_a0
ddr_a1
ddr_a2
ddr_a3
ddr_a4
ddr_a5
ddr_a6
ddr_a7
ddr_a8
ddr_a9
ddr_a10
ddr_a11
ddr_a12
ddr_a13
ddr_a14
ddr_a15
ddr_ba0
ddr_ba1
ddr_ba2
ddr_casn
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
L2
P2
P1
R5
R4
R3
R2
R1
M6
T5
T4
N5
T3
T2
K1
K2
K3
N3
DDR SDRAM BANK ADDRESS
DDR SDRAM BANK ADDRESS
DDR SDRAM COLUMN ADDRESS STROBE. (ACTIVE
LOW)
ddr_ck
DDR SDRAM CLOCK (Differential+)
DDR SDRAM CLOCK ENABLE
DDR SDRAM CLOCK ENABLE1
DDR SDRAM CHIP SELECT0
DDR SDRAM CHIP SELECT1
DDR SDRAM DATA
O
O
M2
M3
N6
M5
M4
E3
E2
E1
F3
G4
G3
G2
G1
H1
J6
ddr_cke0
ddr_cke1
ddr_csn0
ddr_csn1
ddr_d0
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
ddr_d1
DDR SDRAM DATA
ddr_d2
DDR SDRAM DATA
ddr_d3
DDR SDRAM DATA
ddr_d4
DDR SDRAM DATA
ddr_d5
DDR SDRAM DATA
ddr_d6
DDR SDRAM DATA
ddr_d7
DDR SDRAM DATA
ddr_d8
DDR SDRAM DATA
ddr_d9
DDR SDRAM DATA
ddr_d10
ddr_d11
ddr_d12
ddr_d13
ddr_d14
ddr_d15
ddr_d16
ddr_d17
ddr_d18
ddr_d19
DDR SDRAM DATA
J5
DDR SDRAM DATA
J4
DDR SDRAM DATA
J3
DDR SDRAM DATA
K6
K5
K4
V5
V4
V3
V2
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
73
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-24. DDR Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
ZDN [4]
V1
ddr_d20
ddr_d21
ddr_d22
ddr_d23
ddr_d24
ddr_d25
ddr_d26
ddr_d27
ddr_d28
ddr_d29
ddr_d30
ddr_d31
ddr_dqm0
ddr_dqm1
ddr_dqm2
ddr_dqm3
ddr_dqs0
ddr_dqs1
ddr_dqs2
ddr_dqs3
ddr_dqsn0
ddr_dqsn1
ddr_dqsn2
ddr_dqsn3
ddr_nck
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
DDR SDRAM DATA
W4
W5
W6
Y2
Y3
Y4
AA3
AB2
AB1
AC1
AC2
F4
DDR WRITE ENABLE / DATA MASK FOR DATA[7:0]
DDR WRITE ENABLE / DATA MASK FOR DATA[15:8]
DDR WRITE ENABLE / DATA MASK FOR DATA[23:16]
DDR WRITE ENABLE / DATA MASK FOR DATA[31:24]
DDR DATA STROBE FOR DATA[7:0] (Differential+)
DDR DATA STROBE FOR DATA[15:8] (Differential+)
DDR DATA STROBE FOR DATA[23:16] (Differential+)
DDR DATA STROBE FOR DATA[31:24] (Differential+)
DDR DATA STROBE FOR DATA[7:0] (Differential-)
DDR DATA STROBE FOR DATA[15:8] (Differential-)
DDR DATA STROBE FOR DATA[23:16] (Differential-)
DDR DATA STROBE FOR DATA[31:24] (Differential-)
DDR SDRAM CLOCK (Differential-)
O
H2
O
V6
O
Y1
IO
IO
IO
IO
IO
IO
IO
IO
O
F2
J2
W1
AA1
F1
J1
W2
AA2
M1
U1
ddr_odt0
ddr_odt1
ddr_rasn
ddr_resetn
ddr_vref
ddr_vtp
DDR SDRAM ODT0
O
DDR SDRAM ODT1
O
U2
DDR SDRAM ROW ADDRESS STROBE (ACTIVE LOW)
DDR SDRAM RESET (only for DDR3)
O
N2
O
T1
Voltage Reference
AP (1)
I (2)
O
T6
External Resistor for Impedance Training
AC3
N4
ddr_wen
DDR SDRAM WRITE ENABLE (ACTIVE LOW)
(1) This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
(2) This terminal is an analog passive signal that connects to an external 49.9 Ω 1%, 20mW reference resistor which is used to calibrate the
DDR input/output buffers.
Table 4-25. General Purpose Memory Controller (GPMC) Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
B22, C3
gpmc_a0
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
O
O
O
O
O
O
O
O
O
A21, B23, C5
A23, B21, C6
A22, A4, C21
A20, A24, D7
B20, C10, E7
C20, E8
E19, F6
B23, F7
74
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-25. General Purpose Memory Controller (GPMC) Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
O
ZDN [4]
A23, B4
A22, G8
A24, D8
A19
gpmc_a9
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
GPMC Address
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
O
O
O
O
B19
O
A18
O
B18
O
C19, C3
C5, D19
C17, C6
A4, D17
B1, D7
B2, E7
C2, E8
C1, F6
D1, F7
B4, D2
G8
O
O
O
O
O
O
O
O
O
O
O
D8
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address and Data
GPMC Address Valid / Address Latch Enable
GPMC Byte Enable 0 / Command Latch Enable
GPMC Byte Enable 1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
B5
A5
B6
A6
B7
A7
C8
B8
B10
A10
F11
D11
E11
C11
B11
A11
gpmc_advn_ale
gpmc_be0n_cle
gpmc_be1n
gpmc_clk
A9
O
C10
O
A3, F10
A12, B9
A8
GPMC Clock
IO
O
gpmc_csn0
gpmc_csn1
gpmc_csn2
gpmc_csn3
gpmc_csn4
gpmc_csn5
gpmc_csn6
gpmc_dir
GPMC Chip Select
GPMC Chip Select
O
B9
GPMC Chip Select
O
F10
GPMC Chip Select
O
B12
GPMC Chip Select
O
A2
GPMC Chip Select
O
B3
GPMC Chip Select
O
A3
GPMC Data Direction
O
A3
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
75
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-25. General Purpose Memory Controller (GPMC) Signal Descriptions (continued)
SIGNAL NAME [1]
gpmc_oen_ren
DESCRIPTION [2]
GPMC Output / Read Enable
TYPE [3]
ZDN [4]
E10
O
I
gpmc_wait0
gpmc_wait1
gpmc_wen
gpmc_wpn
GPMC Wait 0
A2, B12
A12
GPMC Wait 1
I
GPMC Write Enable
GPMC Write Protect
O
O
D10
B3
76
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.8 General Purpose IOs
Table 4-26. GPIO0 Signal Descriptions
SIGNAL NAME [1]
gpio0_0
DESCRIPTION [2]
TYPE [3]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
ZDN [4]
A17, D16
A15, B17
M25, P23
L24, T22
A12, T21
T20
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
gpio0_1
gpio0_2
gpio0_3
gpio0_4
gpio0_5
gpio0_6
R25
gpio0_7
G24
gpio0_8
C19, D14
D13, D19
C14, C17
D17, E16
K22
gpio0_9
gpio0_10
gpio0_11
gpio0_12
gpio0_13
gpio0_14
gpio0_15
gpio0_16
gpio0_17
gpio0_18
gpio0_19
gpio0_20
gpio0_21
gpio0_22
gpio0_23
gpio0_24
gpio0_25
gpio0_26
gpio0_27
gpio0_28
gpio0_29
gpio0_30
gpio0_31
L22
K21
L21
C16
C13
G21, L23
D24, K23
C24, P22
A14, P20
B10, N20
A10, T23
H20
F25
F11
D11
B15
A16
A2
B3
Table 4-27. GPIO1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
B5
gpio1_0
gpio1_1
gpio1_2
gpio1_3
gpio1_4
gpio1_5
gpio1_6
gpio1_7
gpio1_8
gpio1_9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
A5
B6
A6
B7
A7
C8
B8
L25
J25
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
77
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-27. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
ZDN [4]
K25
J24
E11
C11
B11
A11
C3
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
IO
IO
C5
IO
C6
IO
A4
IO
D7
IO
E7
IO
E8
IO
F6
IO
F7
IO
B4
IO
G8
IO
D8
IO
A3
IO
A8
IO
B9
IO
F10
Table 4-28. GPIO2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
ZDN [4]
B12
A12
A9
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_20
gpio2_21
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
E10
D10
C10
B22
A21
B21
C21
A20
B20
C20
E19
A19
B19
A18
B18
C14
E16
B16
F17
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
78
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-28. GPIO2 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
B23
A23
A22
A24
B1
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
gpio2_29
gpio2_30
gpio2_31
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B2
C2
C1
D1
D2
Table 4-29. GPIO3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
ZDN [4]
D16
B14
B13
A13
A15
AB24
Y22
N23
T24
D14
D13
C16
C13
F25
N24
N22
H23
M24
L23
gpio3_0
gpio3_1
gpio3_2
gpio3_3
gpio3_4
gpio3_5
gpio3_6
gpio3_7
gpio3_8
gpio3_9
gpio3_10
gpio3_11
gpio3_12
gpio3_13
gpio3_14
gpio3_15
gpio3_16
gpio3_17
gpio3_18
gpio3_19
gpio3_20
gpio3_21
gpio3_22
gpio3_23
gpio3_24
gpio3_25
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
K23
M25
L24
IO
IO
IO
P22
P20
N20
T23
IO
IO
IO
Table 4-30. GPIO4 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
AE17
AD18
AC18
AD17
AC20
gpio4_0
gpio4_1
gpio4_2
gpio4_3
gpio4_4
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
79
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-30. GPIO4 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
ZDN [4]
AB19
AA19
AC24
AD24
AD25
AC23
AE21
AC25
AB25
AB20
AC21
AD21
AE22
AD22
AE23
AD23
AE24
Y18
gpio4_5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
gpio4_6
IO
gpio4_7
IO
gpio4_8
IO
gpio4_9
IO
gpio4_10
gpio4_11
gpio4_12
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_19
gpio4_20
gpio4_21
gpio4_24
gpio4_25
gpio4_26
gpio4_27
gpio4_28
gpio4_29
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA18
AE19
AD19
AE20
AD20
IO
IO
IO
IO
Table 4-31. GPIO5 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
IO
ZDN [4]
H22
K24
H25
H24
P25
R24
P24
N25
D25
F24
gpio5_0
gpio5_1
gpio5_2
gpio5_3
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
gpio5_10
gpio5_11
gpio5_12
gpio5_13
gpio5_19
gpio5_20
gpio5_23
gpio5_24
gpio5_25
gpio5_26
gpio5_27
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
G20
F23
IO
IO
E25
E24
AE18
AB18
D11
F11
IO
IO
IO
IO
IO
IO
A10
B10
G21
IO
IO
80
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-31. GPIO5 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
D24
C24
A2
gpio5_28
gpio5_29
gpio5_30
gpio5_31
GPIO
GPIO
GPIO
GPIO
IO
IO
IO
IO
B3
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
81
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.9 HDQ Interface
Table 4-32. HDQ Signal Description
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
hdq_sio
HDQ 1W Data IO
IOD
K24
82
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.10 I2C Interfaces
Table 4-33. I2C0 Signal Descriptions
SIGNAL NAME [1]
I2C0_SCL
DESCRIPTION [2]
TYPE [3]
IOD
ZDN [4]
Y22
I2C0 Clock
I2C0 Data
I2C0_SDA
IOD
AB24
Table 4-34. I2C1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
I2C1_SCL
I2C1 Clock
IOD
AB18, B13, G20, J25,
L21, N20, T20
I2C1_SDA
I2C1 Data
IOD
AE18, B14, E25, K21,
L25, T21, T23
Table 4-35. I2C2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
I2C2_SCL
I2C2 Clock
IOD
AB19, AC21, J24,
L22, T22
I2C2_SDA
I2C2 Data
IOD
AB20, AC20, K22,
K25, P23
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
83
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.11 McASP Interfaces
Table 4-36. McASP0 Signal Descriptions
SIGNAL NAME [1]
mcasp0_aclkr
DESCRIPTION [2]
McASP0 Receive Bit Clock
TYPE [3]
ZDN [4]
IO
IO
A15, A3, C19, L23
mcasp0_aclkx
McASP0 Transmit Bit Clock
A19, D14, E11, F7,
N24
mcasp0_ahclkr
mcasp0_ahclkx
mcasp0_axr0
McASP0 Receive Master Clock
McASP0 Transmit Master Clock
McASP0 Serial Data (IN/OUT)
IO
IO
IO
B18, M24
C13, D17, L24
A18, B11, C14, G8,
H23
mcasp0_axr1
mcasp0_axr2
mcasp0_axr3
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
McASP0 Serial Data (IN/OUT)
IO
IO
IO
A11, C17, D8, E16,
M25
B18, C19, D16, L23,
M24
D17, D19, F17, K23,
L24
mcasp0_fsr
mcasp0_fsx
McASP0 Receive Frame Sync
McASP0 Transmit Frame Sync
IO
IO
A12, C16, D19, K23
B19, B4, C11, D13,
N22
Table 4-37. McASP1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
McASP1 Receive Bit Clock
TYPE [3]
ZDN [4]
B15, F17
mcasp1_aclkr
mcasp1_aclkx
mcasp1_ahclkr
mcasp1_ahclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_fsr
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
McASP1 Transmit Bit Clock
A15, B14, L23
F17
McASP1 Receive Master Clock
McASP1 Transmit Master Clock
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Serial Data (IN/OUT)
McASP1 Receive Frame Sync
McASP1 Transmit Frame Sync
A16, F17
A13, C13, M25
A14, L24
B15, D16
A16, B16
A14, B16
mcasp1_fsx
B13, C16, K23
84
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.12 Miscellaneous
Table 4-38. Miscellaneous Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
D24
clkout1
Clock out1
Clock out2
O
clkout2
O
C24
clkreq
Clock Request Control
O
H20
nNMI
External Interrupt to ARM Cortex A9 core
Warm Reset Input/Output
I
G25
G22
C25
nRESETIN_OUT
OSC0_IN
OSC0_OUT
OSC1_IN
IOD (1)
High frequency oscillator input
High frequency oscillator output
I
O
I
B25
Low frequency (32.768 KHz) Real Time Clock oscillator
input
AE5
OSC1_OUT
Low frequency (32.768 KHz) Real Time Clock oscillator
output
O
AE4
porz
Power on Reset
I
I
I
I
I
I
I
I
I
I
I
I
Y23
AE6
RTC_PORz
RTC active low reset input
tclkin
Timer Clock In
C24
xdma_event_intr0
xdma_event_intr1
xdma_event_intr2
xdma_event_intr3
xdma_event_intr4
xdma_event_intr5
xdma_event_intr6
xdma_event_intr7
xdma_event_intr8
External DMA Event or Interrupt 0
External DMA Event or Interrupt 1
External DMA Event or Interrupt 2
External DMA Event or Interrupt 3
External DMA Event or Interrupt 4
External DMA Event or Interrupt 5
External DMA Event or Interrupt 6
External DMA Event or Interrupt 7
External DMA Event or Interrupt 8
D24
C24
A16, G24, R25
AD24
AD25
AC23
AE21
AC25
AB25
(1) Refer to the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this
terminal.
Table 4-39. Reserved Signals
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Reserved
NA
AA10, AA7, AA9,
AB10, AB6, AB7,
AB9, AC10, AC12,
AC5, AC6, AC7, AC9,
AD1, AD10, AD11,
AD2, AD7, AE11,
AE12, AE9, H19,
H21, W10, Y10, Y6,
Y7
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
85
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.13 PRU-ICSS0 Interface
Table 4-40. PRU-ICSS0-PRU0/General Purpose Inputs Signal Descriptions
SIGNAL NAME [1]
pr0_pru0_gpi0
DESCRIPTION [2]
PRU-ICSS0 PRU0 Data In
TYPE [3]
ZDN [4]
N24
N22
H23
M24
L23
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
pr0_pru0_gpi1
pr0_pru0_gpi2
pr0_pru0_gpi3
pr0_pru0_gpi4
pr0_pru0_gpi5
pr0_pru0_gpi6
pr0_pru0_gpi7
pr0_pru0_gpi8
pr0_pru0_gpi9
pr0_pru0_gpi10
pr0_pru0_gpi11
pr0_pru0_gpi12
pr0_pru0_gpi13
pr0_pru0_gpi14
pr0_pru0_gpi15
pr0_pru0_gpi16
pr0_pru0_gpi17
pr0_pru0_gpi18
pr0_pru0_gpi19
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In Capture Enable
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
PRU-ICSS0 PRU0 Data In
K23
M25
L24
B1
B2
C2
C1
D1
D2
AC20
AB19
AA19
AC24
H25
H24
Table 4-41. PRU-ICSS0-PRU0/General Purpose Outputs Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRU-ICSS0 PRU0 Data Out
TYPE [3]
ZDN [4]
N24
N22
H23
M24
L23
pr0_pru0_gpo0
pr0_pru0_gpo1
pr0_pru0_gpo2
pr0_pru0_gpo3
pr0_pru0_gpo4
pr0_pru0_gpo5
pr0_pru0_gpo6
pr0_pru0_gpo7
pr0_pru0_gpo8
pr0_pru0_gpo9
pr0_pru0_gpo10
pr0_pru0_gpo11
pr0_pru0_gpo12
pr0_pru0_gpo13
pr0_pru0_gpo14
pr0_pru0_gpo15
pr0_pru0_gpo16
pr0_pru0_gpo17
pr0_pru0_gpo18
pr0_pru0_gpo19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
PRU-ICSS0 PRU0 Data Out
K23
M25
L24
B1
B2
C2
C1
D1
D2
AC20
AB19
AA19
AC24
H25
H24
86
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-42. PRU-ICSS0-PRU1/General Purpose Inputs Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRU-ICSS0 PRU1 Data In
TYPE [3]
ZDN [4]
AD24
AD25
AC23
AE21
K25
pr0_pru1_gpi0
pr0_pru1_gpi1
pr0_pru1_gpi2
pr0_pru1_gpi3
pr0_pru1_gpi4
pr0_pru1_gpi5
pr0_pru1_gpi6
pr0_pru1_gpi7
pr0_pru1_gpi8
pr0_pru1_gpi9
pr0_pru1_gpi10
pr0_pru1_gpi11
pr0_pru1_gpi12
pr0_pru1_gpi13
pr0_pru1_gpi14
pr0_pru1_gpi15
pr0_pru1_gpi16
pr0_pru1_gpi17
pr0_pru1_gpi18
pr0_pru1_gpi19
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In Capture Enable
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
PRU-ICSS0 PRU1 Data In
J24
B23
A23
A22
A24
AD21
AE22
AD22
AE23
AD23
AE24
AE18
AB18
H22
K24
Table 4-43. PRU-ICSS0-PRU1/General Purpose Outputs Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRU-ICSS0 PRU1 Data Out
TYPE [3]
ZDN [4]
AD24
AD25
AC23
AE21
K25
pr0_pru1_gpo0
pr0_pru1_gpo1
pr0_pru1_gpo2
pr0_pru1_gpo3
pr0_pru1_gpo4
pr0_pru1_gpo5
pr0_pru1_gpo6
pr0_pru1_gpo7
pr0_pru1_gpo8
pr0_pru1_gpo9
pr0_pru1_gpo10
pr0_pru1_gpo11
pr0_pru1_gpo12
pr0_pru1_gpo13
pr0_pru1_gpo14
pr0_pru1_gpo15
pr0_pru1_gpo16
pr0_pru1_gpo17
pr0_pru1_gpo18
pr0_pru1_gpo19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
PRU-ICSS0 PRU1 Data Out
J24
B23
A23
A22
A24
AD21
AE22
AD22
AE23
AD23
AE24
AE18
AB18
H22
K24
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
87
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-44. PRU-ICSS0/UART0 Signal Descriptions
SIGNAL NAME [1]
pr0_uart0_cts_n
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
P23
I
pr0_uart0_rts_n
pr0_uart0_rxd
pr0_uart0_txd
UART Request to Send
UART Receive Data
UART Transmit Data
O
I
T22
T21
O
T20
88
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.14 PRU-ICSS1 Interface
Table 4-45. PRU-ICSS1-PRU0/General Purpose Inputs Signal Descriptions
SIGNAL NAME [1]
pr1_pru0_gpi0
DESCRIPTION [2]
PRU-ICSS1 PRU0 Data In
TYPE [3]
ZDN [4]
B22
A21
B21
C21
A20
B20
C20
E19
B9
I
I
I
I
I
I
I
I
I
I
I
I
I
pr1_pru0_gpi1
pr1_pru0_gpi2
pr1_pru0_gpi3
pr1_pru0_gpi4
pr1_pru0_gpi5
pr1_pru0_gpi6
pr1_pru0_gpi7
pr1_pru0_gpi8
pr1_pru0_gpi9
pr1_pru0_gpi10
pr1_pru0_gpi11
pr1_pru0_gpi16
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In
PRU-ICSS1 PRU0 Data In Capture Enable
F10
E11
C11
B11, C24, D24, K21,
L21
Table 4-46. PRU-ICSS1-PRU0/General Purpose Outputs Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRU-ICSS1 PRU0 Data Out
TYPE [3]
ZDN [4]
B22
A21
B21
C21
A20
B20
C20
E19
B9
pr1_pru0_gpo0
pr1_pru0_gpo1
pr1_pru0_gpo2
pr1_pru0_gpo3
pr1_pru0_gpo4
pr1_pru0_gpo5
pr1_pru0_gpo6
pr1_pru0_gpo7
pr1_pru0_gpo8
pr1_pru0_gpo9
pr1_pru0_gpo10
pr1_pru0_gpo11
O
O
O
O
O
O
O
O
O
O
O
O
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
PRU-ICSS1 PRU0 Data Out
F10
E11
C11
Table 4-47. PRU-ICSS1/ECAT Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
AE22, K22
AD22, L22
L25
pr1_edc_latch0_in
pr1_edc_latch1_in
pr1_edc_sync0_out
pr1_edc_sync1_out
pr1_edio_data_in0
pr1_edio_data_in1
pr1_edio_data_in2
pr1_edio_data_in3
pr1_edio_data_in4
pr1_edio_data_in5
pr1_edio_data_in6
pr1_edio_data_in7
pr1_edio_data_out0
Data In
Data In
Data Out
Data Out
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data Out
I
I
O
O
I
J25
AD23
AE24
I
I
B23
I
A23
I
A22
I
A24
I
B9, C20
E19, F10
T21
I
O
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
89
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-47. PRU-ICSS1/ECAT Signal Descriptions (continued)
SIGNAL NAME [1]
pr1_edio_data_out1
DESCRIPTION [2]
TYPE [3]
ZDN [4]
T20
Data Out
O
O
O
O
O
O
O
I
pr1_edio_data_out2
pr1_edio_data_out3
pr1_edio_data_out4
pr1_edio_data_out5
pr1_edio_data_out6
pr1_edio_data_out7
pr1_edio_latch_in
pr1_edio_outvalid
pr1_edio_sof
Data Out
B23
Data Out
A23
Data Out
A22
Data Out
A24
Data Out
B9, C20
E19, F10
AE23
Data Out
Latch In
Data Out Valid
Start of Frame
O
O
AD18
AB25, AE17
Table 4-48. PRU-ICSS1/MDIO Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
pr1_mdio_data
pr1_mdio_mdclk
MDIO Data
MDIO Clk
IO
O
A17, B12, D24
A12, B17, C24
Table 4-49. PRU-ICSS1/MII0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MII Collision Detect
TYPE [3]
ZDN [4]
A10, D25
B12, G20
B18
pr1_mii0_col
I
I
pr1_mii0_crs
MII Carrier Sense
pr1_mii0_rxd0
pr1_mii0_rxd1
pr1_mii0_rxd2
pr1_mii0_rxd3
pr1_mii0_rxdv
pr1_mii0_rxer
pr1_mii0_rxlink
pr1_mii0_txd0
pr1_mii0_txd1
pr1_mii0_txd2
pr1_mii0_txd3
pr1_mii0_txen
pr1_mii_mr0_clk
pr1_mii_mt0_clk
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Receive Link
I
I
A18
I
B19
I
A19
I
D17
I
D19
I
C19, E25
B11, B20
A20, C11
C21, E11
B21, D11
A21, F11
C17
MII Transmit Data bit 0
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
O
O
O
O
O
I
MII Transmit Clock
I
B10, B22
Table 4-50. PRU-ICSS1/MII1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MII Collision Detect
TYPE [3]
ZDN [4]
pr1_mii1_col
pr1_mii1_crs
pr1_mii1_rxd0
pr1_mii1_rxd1
pr1_mii1_rxd2
pr1_mii1_rxd3
pr1_mii1_rxdv
pr1_mii1_rxer
pr1_mii1_rxlink
I
I
I
I
I
I
I
I
I
A3, F24
MII Carrier Sense
A12, A2, F23
MII Receive Data bit 0
MII Receive Data bit 1
MII Receive Data bit 2
MII Receive Data bit 3
MII Receive Data Valid
MII Receive Data Error
MII Receive Link
D8
G8
B4
F7
C5
B3
C10, E24
90
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 4-50. PRU-ICSS1/MII1 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
MII Transmit Data bit 0
TYPE [3]
ZDN [4]
E7
pr1_mii1_txd0
pr1_mii1_txd1
pr1_mii1_txd2
pr1_mii1_txd3
pr1_mii1_txen
pr1_mii_mr1_clk
pr1_mii_mt1_clk
O
O
O
O
O
I
MII Transmit Data bit 1
MII Transmit Data bit 2
MII Transmit Data bit 3
MII Transmit Enable
MII Receive Clock
D7
A4
C6
C3
F6
MII Transmit Clock
I
E8
Table 4-51. PRU-ICSS1/UART0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
K22, P23
L22, T22
K21, T21
L21, T20
pr1_uart0_cts_n
pr1_uart0_rts_n
pr1_uart0_rxd
pr1_uart0_txd
I
UART Request to Send
UART Receive Data
O
I
UART Transmit Data
O
Table 4-52. PRU-ICSS1/eCAP Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
pr1_ecap0_ecap_capin_apwm_o
Enhanced capture input or Auxiliary PWM out
IO
A11, G24
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
91
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.15 QSPI Interface
Table 4-53. QSPI Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
B12, Y18
A8, AA18
A9, AE19
AD19, E10
AE20, D10
AD20, C10
qspi_clk
qspi_csn
qspi_d0
qspi_d1
qspi_d2
qspi_d3
QSPI Clock
QSPI Chip Select
QSPI Data
IO
O
IO
I
QSPI Data
QSPI Data
I
QSPI Data
I
92
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.16 RTC Subsystem Interface
Table 4-54. RTC Subsystem Signal Descriptions
SIGNAL NAME [1]
RTC_KALDO_ENn
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Active low enable input for internal CAP_VDD_RTC
voltage regulator
I
AE2
RTC_PMIC_EN
RTC_WAKEUP
PMIC Power Enable output generated from Generic
RTCSS
O
I
AD6
AE3
External Wakeup Pin when Generic RTC is used
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
93
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.17 Removable Media Interfaces
Table 4-55. MMC0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
TYPE [3]
ZDN [4]
mmc0_clk
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
D1
mmc0_cmd
mmc0_dat0
mmc0_dat1
mmc0_dat2
mmc0_dat3
mmc0_dat4
mmc0_dat5
mmc0_dat6
mmc0_dat7
mmc0_pow
mmc0_sdcd
mmc0_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD Power Switch Control
SD Card Detect
D2
C1
C2
B2
B1
E16
C14
D13
D14
A16, R25
A17, N24, R25
B17, G24, L23
I
SD Write Protect
I
Table 4-56. MMC1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
TYPE [3]
ZDN [4]
B15, B17, B9, Y18
A14, A17, AA18, F10
AE19, B10, B5, D14
A10, A5, AD19, D13
AE20, B6, C14, F11
A6, AD20, D11, E16
B7, E11
mmc1_clk
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
mmc1_sdcd
mmc1_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
A7, C11
B11, C8
A11, B8
A2, N22
SD Write Protect
I
K21, T21
Table 4-57. MMC2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MMC/SD/SDIO Clock
TYPE [3]
ZDN [4]
A12, AD21, B16, B17
A13, A17, AE22, B12
A15, AD22, C5, E11
AE23, C11, C16, C6
A4, AD23, B11, C13
A11, A3, AE24, D16
B10, E8
mmc2_clk
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
mmc2_cmd
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_sdcd
mmc2_sdwp
MMC/SD/SDIO Command
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
MMC/SD/SDIO Data Bus
SD Card Detect
A10, F6
F11, F7
B4, D11
B3, H23
SD Write Protect
I
L21, T20
94
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.18 SPI Interfaces
Table 4-58. SPI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
spi0_cs0
spi0_cs1
spi0_cs2
spi0_cs3
spi0_d0
spi0_d1
spi0_sclk
SPI Chip Select
SPI Chip Select
SPI Chip Select
SPI Chip Select
SPI Data
IO
IO
IO
IO
IO
IO
IO
T20
R25
AD24, C24, E10
A9, AD25, N24
T22
SPI Data
T21
SPI Clock
P23
Table 4-59. SPI1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
spi1_cs0
SPI Chip Select
IO
A16, J25, K22, K25,
M24
spi1_cs1
spi1_cs2
spi1_cs3
spi1_d0
spi1_d1
spi1_sclk
SPI Chip Select
SPI Chip Select
SPI Chip Select
SPI Data
IO
IO
IO
IO
IO
IO
D24, G24, J24, L22
AC23, D10, N22
AE21, C10, H23
B14, L25, N22
SPI Data
B13, H23, J25
SPI Clock
D16, G24, N24
Table 4-60. SPI2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI Chip Select
SPI Chip Select
SPI Chip Select
SPI Chip Select
SPI Data
TYPE [3]
ZDN [4]
spi2_cs0
spi2_cs1
spi2_cs2
spi2_cs3
spi2_d0
spi2_d1
spi2_sclk
IO
IO
IO
IO
IO
IO
IO
AC20, AD25, T23
AC25, AE17
AB19, AC23
AA19, AC24
AD17, AD24, P22
AB25, AD18, P20
AC18, AE21, N20
SPI Data
SPI Clock
Table 4-61. SPI3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI Chip Select
SPI Chip Select
SPI Data
TYPE [3]
ZDN [4]
spi3_cs0
spi3_cs1
spi3_d0
spi3_d1
spi3_sclk
IO
IO
IO
IO
IO
AD21, D11, D17
A11, B10, B18, C10
A10, AB20, D19
AC21, C17, F11
AE22, B10, C19
SPI Data
SPI Clock
Table 4-62. SPI4 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI Chip Select
SPI Chip Select
SPI Data
TYPE [3]
ZDN [4]
N25
spi4_cs0
spi4_cs1
spi4_d0
spi4_d1
spi4_sclk
IO
IO
IO
IO
IO
H22
R24
SPI Data
P24
SPI Clock
P25
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
95
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.19 Timer Interfaces
Table 4-63. Timer0 Signal Descriptions
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
SIGNAL NAME [1]
DESCRIPTION [2]
Timer trigger event / PWM out
TYPE [3]
ZDN [4]
timer0
timer1
timer4
timer5
timer6
timer7
IO
R25
Table 4-64. Timer1 Signal Descriptions
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Timer trigger event / PWM out
IO
G24
Table 4-65. Timer4 Signal Descriptions
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Timer trigger event / PWM out
IO
A13, A9, AB24, D24
Table 4-66. Timer5 Signal Descriptions
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Timer trigger event / PWM out
IO
B1, B17, C10, L22
Table 4-67. Timer6 Signal Descriptions
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Timer trigger event / PWM out
IO
A17, B2, D10, K22
Table 4-68. Timer7 Signal Descriptions
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Timer trigger event / PWM out
IO
C24, E10, L25, Y22
96
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.20 UART Interfaces
Table 4-69. UART0 Signal Descriptions
SIGNAL NAME [1]
uart0_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
AC24, L25
AD22
I
I
uart0_dcdn
UART Data Carrier Detect
UART Request to Send
UART Receive Data
uart0_rtsn
O
I
AD24, J25
K25
uart0_rxd
uart0_txd
UART Transmit Data
O
J24
Table 4-70. UART1 Signal Descriptions
SIGNAL NAME [1]
uart1_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
AD21, K22
IO
I
uart1_dcdn
UART Clear to Send
AD23, B1, D14
AE23, B2, D13
AE24, C14, C2
AD22, C1, E16
AE22, L22
uart1_dsrn
UART Request to Send
UART Receive Data
I
uart1_dtrn
O
I
uart1_rin
UART Transmit Data
uart1_rtsn
UART Request to Send
UART Receive Data
O
IO
IO
uart1_rxd
AB20, K21
uart1_txd
UART Transmit Data
AC21, L21
Table 4-71. UART2 Signal Descriptions
SIGNAL NAME [1]
uart2_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
IO
O
A19, AB24, AD23
AE24, B19, Y22
uart2_rtsn
UART Request to Send
UART Receive Data
uart2_rxd
IO
AD22, B14, D1, D14,
P23
uart2_txd
UART Transmit Data
IO
AE23, B13, D13, D2,
T22
Table 4-72. UART3 Signal Descriptions
SIGNAL NAME [1]
uart3_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
IO
O
A17, A18, D1, H22
B17, B18, D2, K24
C14, C2, H25, R25
C1, E16, G24, H24
uart3_rtsn
UART Request to Send
UART Receive Data
uart3_rxd
IO
IO
uart3_txd
UART Transmit Data
Table 4-73. UART4 Signal Descriptions
SIGNAL NAME [1]
uart4_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
B1, C19
I
uart4_rtsn
UART Request to Send
UART Receive Data
O
I
B2, D19
uart4_rxd
A2, C16, L25
B3, C13, J25
uart4_txd
UART Transmit Data
O
Table 4-74. UART5 Signal Descriptions
SIGNAL NAME [1]
uart5_ctsn
DESCRIPTION [2]
UART Clear to Send
TYPE [3]
ZDN [4]
I
B14, C17, C2
B13, C1, D17
uart5_rtsn
UART Request to Send
O
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
97
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 4-74. UART5 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
UART Receive Data
UART Transmit Data
TYPE [3]
ZDN [4]
uart5_rxd
uart5_txd
I
A17, B19, C17, D16
A15, A16, A19, B17
O
98
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.21 USB Interfaces
Table 4-75. USB0 Signal Descriptions
SIGNAL NAME [1]
USB0_CE
DESCRIPTION [2]
USB0 Active high Charger Enable output
USB0 Data minus
TYPE [3]
ZDN [4]
W22
W24
W25
G21
A
A
A
O
A
A
USB0_DM
USB0_DP
USB0 Data plus
USB0_DRVVBUS
USB0_ID
USB0 Active high VBUS control output
USB0 ID
U24
USB0_VBUS
USB0 VBUS
U23
Table 4-76. USB1 Signal Descriptions
SIGNAL NAME [1]
USB1_CE
DESCRIPTION [2]
USB1 Active high Charger Enable output
USB1 Data minus
TYPE [3]
ZDN [4]
U22
A
A
A
O
A
A
USB1_DM
V25
USB1_DP
USB1 Data plus
V24
USB1_DRVVBUS
USB1_ID
USB1 Active high VBUS control output
USB1 ID
F25
U25
USB1_VBUS
USB1 VBUS
T25
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
99
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.22 eCAP Interfaces
Table 4-77. eCAP0 Signal Descriptions
SIGNAL NAME [1]
eCAP0_in_PWM0_out
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Enhanced Capture 0 input or Auxiliary PWM0 output
IO
G24
Table 4-78. eCAP1 Signal Descriptions
SIGNAL NAME [1]
eCAP1_in_PWM1_out
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Enhanced Capture 1 input or Auxiliary PWM1 output
IO
J24, R25, Y22
Table 4-79. eCAP2 Signal Descriptions
SIGNAL NAME [1]
eCAP2_in_PWM2_out
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Enhanced Capture 2 input or Auxiliary PWM2 output
IO
AB24, K25, M24
100
Terminal Configuration and Functions
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
4.3.23 eHRPWM Interfaces
Table 4-80. eHRPWM0 Signal Descriptions
SIGNAL NAME [1]
ehrpwm0_synci
DESCRIPTION [2]
TYPE [3]
ZDN [4]
Sync input to eHRPWM0 module from an external pin
Sync Output from eHRPWM0 module to an external pin
I
AC21, M24, P25, T20
ehrpwm0_synco
O
AE18, B19, C21, C5,
D11
ehrpwm0_tripzone_input
ehrpwm0A
eHRPWM0 trip zone input
eHRPWM0 A output.
eHRPWM0 B output.
I
AB20, H23, P24, T21
AD25, N24, P23
O
O
ehrpwm0B
AC23, N22, T22
Table 4-81. eHRPWM1 Signal Descriptions
SIGNAL NAME [1]
ehrpwm1_tripzone_input
ehrpwm1A
DESCRIPTION [2]
eHRPWM1 trip zone input
eHRPWM1 A output.
TYPE [3]
ZDN [4]
I
A19, AD21, C3, P20
O
A18, AE20, AE21,
C6, T21
ehrpwm1B
eHRPWM1 B output.
O
A4, AC25, AD20,
B18, T20
Table 4-82. eHRPWM2 Signal Descriptions
SIGNAL NAME [1]
ehrpwm2_tripzone_input
ehrpwm2A
DESCRIPTION [2]
eHRPWM2 trip zone input
eHRPWM2 A output.
TYPE [3]
ZDN [4]
I
B21, F11, T23
B10, B22, R25
A10, A21, G24
O
O
ehrpwm2B
eHRPWM2 B output.
Table 4-83. eHRPWM3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
ZDN [4]
ehrpwm3_synci
Sync input to eHRPWM3 module or sync output to
external PWM
I
R24
ehrpwm3_synco
Sync input to eHRPWM3 module or sync output to
external PWM
O
AB18
ehrpwm3_tripzone_input
ehrpwm3A
eHRPWM3 trip zone input
eHRPWM3 A output.
eHRPWM3 B output.
I
N25
O
O
AC25, AE19
AB25, AD19
ehrpwm3B
Table 4-84. eHRPWM4 Signal Descriptions
SIGNAL NAME [1]
ehrpwm4_tripzone_input
ehrpwm4A
DESCRIPTION [2]
eHRPWM4 trip zone input
eHRPWM4 A output.
TYPE [3]
ZDN [4]
N20
I
O
O
H25
ehrpwm4B
eHRPWM4 B output.
H24
Table 4-85. eHRPWM5 Signal Descriptions
SIGNAL NAME [1]
ehrpwm5_tripzone_input
ehrpwm5A
DESCRIPTION [2]
eHRPWM5 trip zone input
eHRPWM5 A output.
TYPE [3]
ZDN [4]
P22
I
O
O
H22
ehrpwm5B
eHRPWM5 B output.
K24
Copyright © 2014–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
101
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
4.3.24 eQEP Interfaces
Table 4-86. eQEP0 Signal Descriptions
SIGNAL NAME [1]
eQEP0_index
DESCRIPTION [2]
TYPE [3]
ZDN [4]
A13, M25
B16, L24
A14, L23
B15, K23
eQEP0 index.
eQEP0 strobe.
IO
IO
I
eQEP0_strobe
eQEP0A_in
eQEP0B_in
eQEP0A quadrature input
eQEP0B quadrature input
I
Table 4-87. eQEP1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
eQEP1 index.
TYPE [3]
ZDN [4]
C17, E8
D17, F6
C19, D7
D19, E7
eQEP1_index
eQEP1_strobe
eQEP1A_in
IO
IO
I
eQEP1 strobe.
eQEP1A quadrature input
eQEP1B quadrature input
eQEP1B_in
I
Table 4-88. eQEP2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
eQEP2 index.
TYPE [3]
ZDN [4]
B11, C20
A11, E19
A20, E11
B20, C11
eQEP2_index
eQEP2_strobe
eQEP2A_in
IO
IO
I
eQEP2 strobe.
eQEP2A quadrature input
eQEP2B quadrature input
eQEP2B_in
I
102
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5 Specifications
5.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)(2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.3
MAX
1.5
1.5
1.5
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
4
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_MPU
Supply voltage for the MPU domain
VDD_CORE
CAP_VDD_RTC(3)
Supply voltage range for the CORE domain
Supply voltage range for the RTC domain
VDDS_RTC
Supply voltage range for the RTC domain
VDDS_OSC
Supply voltage range for the System oscillator
Supply voltage range for the Core SRAM and Bandgap LDOs
Supply voltage range for the MPU SRAM and BB LDOs
Supply voltage range for the DPLL DDR
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_DDR
Supply voltage range for the DPLL CORE, EXTDEV, and LCD
Supply voltage range for the DPLL MPU
Supply voltage range for the DDR IO domain
Supply voltage range for all dual-voltage IO domains
Supply voltage range for USBPHY and DPLL PER
Supply voltage range for USBPHY
VDDS
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA_ADC0
VDDA_ADC1
VDDSHV1
Supply voltage range for ADC0
Supply voltage range for ADC1
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the CLKOUT voltage domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for the dual-voltage IO domain
Supply voltage range for USBPHY
VDDSHV2
VDDSHV3
VDDSHV5
VDDSHV6
VDDSHV7
VDDSHV8
VDDSHV9
VDDSHV10
VDDSHV11
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDS3P3V_IOLDO
VDDS_CLKOUT
USB0_VBUS(4)
USB1_VBUS(4)
DDR_VREF
Supply voltage range for USBPHY
4
Supply voltage range for the dual-voltage IO LDO
Supply voltage range for CLKOUT domain
3.8
2.1
5.25
5.25
1.1
Supply voltage range for USB VBUS comparator input
Supply voltage range for USB VBUS comparator input
Supply voltage range for the DDR3/DDR3L HSTL, LPDDR2
HSUL_12 reference voltage
Steady State Max. Voltage at all
IO pins(5)
–0.5 V to IO supply voltage + 0.3 V
USB0_ID(6)
USB1_ID(6)
Steady state maximum voltage range for the USB ID input
Steady state maximum voltage range for the USB ID input
–0.5
–0.5
2.1
2.1
V
V
Transient Overshoot and
Undershoot specification at IO
terminal
20% of corresponding IO supply voltage for
up to 20% of signal period (see Figure 5-1)
Latch-up I-test performance current-pulse
injection on each IO pin
±100
±100
Latch-up Performance(7)
Class II (105°C)
mA
°C
Latch-up overvoltage performance voltage
injection on each IO pin
(8)
Tstg
Storage temperature
–55
155
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
103
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Absolute Maximum Ratings (continued)
over junction temperature range (unless otherwise noted)(1)(2)
(3) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(4) This terminal is connected to a fail-safe IO and does not have a dependence on any IO supply voltage.
(5) This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.5 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(6) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal
should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to
any external voltage source.
(7) For current pulse injection:
Pins stressed per JEDEC JESD78D (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78D (Class II) and passed specified voltage injection.
(8) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power
supply voltage. This allows external voltage sources to be connected to these IO terminals when the
respective IO power supplies are turned off. The USB0_VBUS, USB1_VBUS, and DDR_RESETn are the
only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should
be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 5.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
Figure 5-1. Tovershoot + Tundershoot < 20% of Tperiod
104
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JESD22-C101(2)
Electrostatic discharge
(ESD)
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Power-On Hours (POH)(1)(2)(3)(4)
COMMERCIAL
INDUSTRIAL
EXTENDED
OPERATING
CONDITION
JUNCTION TEMP
LIFETIME
(POH)(5)
JUNCTION TEMP
LIFETIME
(POH)(5)
JUNCTION TEMP
(Tj)
LIFETIME
(POH)(5)
(Tj)
(Tj)
Nitro
0°C to 90°C
0°C to 90°C
0°C to 90°C
0°C to 90°C
0°C to 90°C
100K
100K
100K
100K
100K
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
–40°C to 90°C
100K
100K
100K
100K
100K
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
84.4K
100K
100K
100K
100K
Turbo
OPP120
OPP100
OPP50
(1) The POH information in this table is provided solely for your convenience and does not extend or modify the warranty provided under
TI's standard terms and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device POH must be limited as described in this table.
(3) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
(4) The previous notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and
conditions for TI semiconductor products.
(5) POH = Power-on hours when the device is fully functional.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
105
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.4 Operating Performance Points
Device operating performance points (OPPs) are defined in 表 5-1, 表 5-2, and 表 5-3.
表 5-1. VDD_CORE OPPs(1)
VDD_CORE
VDD_CORE OPP
DDR3/DDR3L(2)
LPDDR2(2)
L3 and L4
MIN
NOM
MAX
OPP100
1.056 V
1.100 V
1.144 V
400 MHz
266 MHz
200 MHz and
100 MHz
OPP50
0.912 V
0.950 V
1 V
Not supported
133 MHz
100 MHz and
50 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Because data is transferred on both edges of the clock, double-data
rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
表 5-2. VDD_MPU OPPs(1)
VDD_MPU
VDD_MPU OPP
ARM (A9)
MIN
NOM
MAX
Nitro
1.272 V
1.210 V
1.152 V
1.056 V
0.912 V
1.325 V
1.260 V
1.200 V
1.100 V
0.950 V
1.378 V
1.326 V
1.248 V
1.144 V
1.000 V
1 GHz
Turbo
800 MHz
720 MHz
600 MHz
300 MHz
OPP120
OPP100
OPP50
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
表 5-3. Valid Combinations of VDD_CORE and
VDD_MPU OPPs(1)
VDD_CORE
OPP50
VDD_MPU
OPP50
OPP50
OPP100
OPP120
Turbo
OPP100
OPP100
OPP100
OPP100
OPP100
Nitro
(1) OPP combinations listed in this table have been tested. Other OPP combinations are not supported.
106
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.5 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
1.056
0.912
1.272
1.210
1.152
1.056
0.912
0.900
1.710
1.425
1.283
1.140
1.710
1.710
1.710
1.710
NOM
1.100
0.950
1.325
1.260
1.200
1.100
0.950
1.100
1.800
1.500
1.350
1.200
1.800
1.800
1.800
1.800
MAX
1.144
1.000
1.378
1.326
1.248
1.144
1.000
1.250
1.890
1.575
1.418
1.260
1.890
1.890
1.890
1.890
UNIT
Supply voltage range for core domain; OPP100
Supply voltage range for core domain; OPP50
Supply voltage range for MPU domain, Nitro
Supply voltage range for MPU domain; Turbo
Supply voltage range for MPU domain; OPP120
Supply voltage range for MPU domain; OPP100
Supply voltage range for MPU domain; OPP50
Supply voltage range for RTC core domain
Supply voltage range for RTC domain
VDD_CORE
V
VDD_MPU
V
CAP_VDD_RTC(1)
VDDS_RTC
V
V
Supply voltage range for DDR IO domain (DDR3)
Supply voltage range for DDR IO domain (DDR3L)
Supply voltage range for DDR IO domain (LPDDR2)
Supply voltage range for all dual-voltage IO domains
Supply voltage range for Core SRAM LDOs, Analog
Supply voltage range for MPU SRAM LDOs, Analog
Supply voltage range for DPLL DDR, Analog
VDDS_DDR
V
VDDS(2)
V
V
V
V
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR(3)
Supply voltage range for DPLL CORE, EXTDEV, and LCD,
Analog
VDDS_PLL_CORE_LCD(3)
1.710
1.800
1.890
V
VDDS_PLL_MPU(3)
VDDS_OSC
Supply voltage range for DPLL MPU, Analog
1.710
1.710
1.800
1.800
1.890
1.890
V
V
Supply voltage range for system oscillator, Analog
Supply voltage range for USBPHY and DPLL PER, Analog,
1.8 V
VDDA1P8V_USB0(3)
1.710
1.800
1.890
V
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDA_ADC0
Supply voltage range for USBPHY, Analog, 1.8 V
Supply voltage range for USBPHY, Analog, 3.3 V
Supply voltage range for USBPHY, Analog, 3.3 V
Supply voltage range for ADC0, Analog
1.710
3.135
3.135
1.710
1.710
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.710
3.135
1.800
3.300
3.300
1.800
1.800
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.800
3.300
1.890
3.465
3.465
1.890
1.890
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
1.890
3.465
V
V
V
V
V
VDDA_ADC1
Supply voltage range for ADC1, Analog
1.8-V operation
Supply voltage range for dual-voltage IO
VDDSHV1
VDDSHV2
VDDSHV3
VDDSHV5
VDDSHV6
VDDSHV7
VDDSHV8
VDDSHV9
VDDSHV10
V
V
V
V
V
V
V
V
V
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for CLKOUT voltage
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
domain
3.3-V operation
1.8-V operation
Supply voltage range for dual-voltage IO
VDDSHV11
DDR_VREF
V
V
domain
3.3-V operation
Supply voltage range for the DDR3/DDR3L HSTL, LPDDR2
HSUL_12 reference input
0.49 ×
VDDS_DDR
0.50 ×
VDDS_DDR
0.51 ×
VDDS_DDR
VDDS3P3V_IOLDO
VDDS_CLKOUT
Supply voltage range for the dual-voltage IO LDO
Supply voltage range for CLKOUT domain
3.135
1.71
3.3
1.8
3.465
1.89
V
V
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
107
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Recommended Operating Conditions (continued)
over junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
Voltage range for USB VBUS comparator input
Voltage range for USB VBUS comparator input
Voltage range for the USB ID input
Voltage range for the USB ID input
Commercial Temperature
MIN
0.000
0.000
NOM
5.000
5.000
MAX
5.250
5.250
UNIT
USB0_VBUS
V
V
V
V
USB1_VBUS
USB0_ID
(4)
(4)
USB1_ID
0
–40
–40
90
90
Operating Temperature
Range, Tj
Industrial Temperature
°C
Extended Temperature
105
(1) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
(2) VDDS should be supplied irrespective of 1.8-V or 3.3-V mode of operation of the dual-voltage IOs.
(3) For more details on power supply requirements, see 节 5.13.2.1.1.
(4) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The terminal
should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to
any external voltage source.
108
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.6 Power Consumption Summary
表 5-4 summarizes the maximum power consumption at each power terminal.
Note: Data in the Maximum Current Ratings table (表 5-4) represents worst-case power consumption
based on various applications of the device using practical operating conditions. The data primarily
benefits the power supply designer trying to understand the worst-case power consumption expected from
each power rail.
表 5-4. Maximum Current Ratings at Power Terminals(1)
PARAMETER
MAX UNIT
SUPPLY NAME
VDD_CORE
DESCRIPTION
Maximum current rating for the core domain; OPP100
Maximum current rating for the core domain; OPP50
Maximum current rating for the MPU domain; Nitro
Maximum current rating for the MPU domain; Turbo
Maximum current rating for the MPU domain; OPP120
Maximum current rating for the MPU domain; OPP100
Maximum current rating for the MPU domain; OPP50
Maximum current rating for RTC domain and LDO output
Maximum current rating for the RTC domain
600
400
1000
800
720
600
350
2
mA
mA
at 1 GHz
at 800 MHz
at 720 MHz
at 600 MHz
at 300 MHz
VDD_MPU
mA
CAP_VDD_RTC(2)
VDDS_RTC
mA
mA
mA
5
VDDS_DDR
Maximum current rating for DDR IO domain; DDR3/DDR3L
Maximum current rating for DDR IO domain; LPDDR2
Maximum current rating for all dual-voltage IO domains
Maximum current rating for core SRAM LDOs
300
150
70
VDDS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDDS_SRAM_CORE_BG
VDDS_SRAM_MPU_BB
VDDS_PLL_DDR
VDDS_PLL_CORE_LCD
VDDS_PLL_MPU
VDDS_OSC
10
Maximum current rating for MPU SRAM LDOs
10
Maximum current rating for the DPLL DDR
10
Maximum current rating for the DPLL CORE, EXTDEV, and LCD
Maximum current rating for the DPLL MPU
20
10
Maximum current rating for the system oscillator
Maximum current rating for USBPHY 1.8 V and DPLL PER
Maximum current rating for USBPHY 1.8 V
5
VDDA1P8V_USB0
VDDA1P8V_USB1
VDDA3P3V_USB0
VDDA3P3V_USB1
VDDS3P3V_IOLDO
VDDA_ADC0
25
25
Maximum current rating for USBPHY 3.3 V
40
Maximum current rating for USBPHY 3.3 V
40
Maximum current rating for the dual-voltage IO LDO
Maximum current rating for ADC0
30
10
VDDA_ADC1
Maximum current rating for ADC1
10
VDDSHV1
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for dual-voltage IO domain
Maximum current rating for CLKOUT domain
30
VDDSHV2
80
VDDSHV3
100
10
VDDSHV5
VDDSHV6
50
VDDSHV7
10
VDDSHV8
50
VDDSHV9
50
VDDSHV10
50
VDDSHV11
50
VDDS_CLKOUT
10
(1) Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more
information, see AM43xx Power Consumption Summary.
(2) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced
from an external power supply.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
109
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.7 DC Electrical Characteristics
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
TYP
MAX UNIT
DDR_CSn[1:0], DDR_CKE[1:0], DDR_CK, DDR_CKn, DDR_CASn, DDR_RASn, DDR_WEn, DDR_BA[2:0], DDR_A[15:0],
DDR_ODT[1:0], DDR_D[31:0], DDR_DQM[3:0], DDR_DQS[3:0], DDR_DQSn[3:0] pins (DDR3/DDR3L - HSTL mode)
VDDS_DDR =
1.5 V
DDR_VREF +
0.1
VIH
High-level input voltage
V
VDDS_DDR =
1.35 V
DDR_VREF +
0.09
VDDS_DDR =
1.5 V
DDR_VREF –
0.1
VIL
Low-level input voltage
V
VDDS_DDR =
1.35 V
DDR_VREF –
0.09
VHYS
VOH
Hysteresis voltage at an input
NA
V
V
High-level output voltage, driver enabled, pullup
or pulldown disabled
IOH = 8 mA
IOL = 8 mA
VDDS_DDR –
0.4
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.4
10
VOL
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–10
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–240
40
–40
240
10
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
–10
IOZ
µA
DDR_CSn[1:0], DDR_CKE[1:0], DDR_CK, DDR_CKn, DDR_CASn, DDR_RASn, DDR_WEn, DDR_BA[2:0], DDR_A[15:0],
DDR_D[31:0], DDR_DQM[3:0], DDR_DQS[3:0], DDR_DQSn[3:0] pins (LPDDR2 - HSUL_12 mode)(2)
VDDS_DDR =
1.2 V
DDR_VREF +
0.13
VIH
High-level input voltage
V
VDDS_DDR =
1.2 V
DDR_VREF –
0.13
VIL
Low-level input voltage
V
V
V
VHYS
VOH
Hysteresis voltage at an input
NA
High-level output voltage, driver enabled, pullup
or pulldown disabled
IOH = 8 mA
IOL = 8 mA
VDDS_DDR –
0.4
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.4
10
VOL
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–10
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–240
40
–40
240
10
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
–10
IOZ
µA
DDR_RESETn(3)
VIH
High-level input voltage
NA
NA
NA
VIL
Low-level input voltage
VHYS
Hysteresis voltage at an input
High-level output voltage, driver enabled, pullup
or pulldown disabled
IOH = 8 mA
IOL = 8 mA
VDDS_DDR –
0.4
VOH
VOL
V
V
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.4
10
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–10
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–240
24
–24
240
110
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
DC Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
MIN
TYP
MAX UNIT
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
–10
10
IOZ
µA
RTC_PWRONRSTn
0.65 ×
VDDS_RTC
VIH
VIL
High-level input voltage
V
0.35 ×
V
Low-level input voltage
VDDS_RTC
VHYS
II
RTC_PMIC_EN
Hysteresis voltage at an input
0.065
–1
V
Input leakage current
1
µA
High-level output voltage, driver enabled, pullup
or pulldown disabled
VDDS_RTC –
0.45
VOH
VOL
IOH = 6 mA
IOL = 6 mA
V
V
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.45
1
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–1
II
µA
µA
V
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–200
40
–40
200
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
IOZ
–1
1
RTC_WAKEUP
0.65 ×
VDDS_RTC
VIH
High-level input voltage
0.35 ×
VDDS_RTC
VIL
Low-level input voltage
V
V
VHYS
Hysteresis voltage at an input
0.15
–1
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
1
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–200
40
–40
200
TCK (VDDSHV3 = 1.8 V)
VIH
High-level input voltage
1.45
V
V
V
VIL
Low-level input voltage
0.46
8
VHYS
Hysteresis voltage at an input
0.4
–8
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–161
52
–100
100
–52
170
TCK (VDDSHV3 = 3.3 V)
VIH
High-level input voltage
2.15
V
V
V
VIL
Low-level input voltage
0.46
18
VHYS
Hysteresis voltage at an input
0.4
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–18
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–243
51
–100
110
–19
210
PWRONRSTn (VDDSHV3 = 1.8 V or 3.3 V)(4)
VIH
VIL
High-level input voltage
Low-level input voltage
1.35
V
V
0.5
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
111
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
DC Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating temperature (unless otherwise noted)(1)
PARAMETER
Hysteresis voltage at an input
MIN
TYP
MAX UNIT
VHYS
II
0.07
V
VI = 1.8 V
VI = 3.3 V
0.1
µA
2
Input leakage current
All other LVCMOS pins (VDDSHVx = 1.8 V; x=1–11)
High-level input voltage
VIH
0.65 ×
VDDSHVx
V
Low-level input voltage
VIL
0.35 ×
V
VDDSHVx
VHYS
VOH
Hysteresis voltage at an input
0.18
0.305
V
V
High-level output voltage, driver enabled, pullup
or pulldown disabled
IOH = 6 mA
IOL = 6 mA
VDDSHVx –
0.45
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.45
8.4
VOL
V
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–8.4
II
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–161
52
–100
100
–52
170
8.4
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
–8.4
IOZ
µA
All other LVCMOS pins (VDDSHVx = 3.3 V; x=1–11)
VIH
High-level input voltage
Low-level input voltage
2
V
V
V
VIL
0.8
VHYS
Hysteresis voltage at an input
0.265
0.44
High-level output voltage, driver enabled, pullup
or pulldown disabled
IOH = 6 mA
IOL = 6 mA
VDDSHVx –
0.45
VOH
VOL
V
V
Low-level output voltage, driver enabled, pullup
or pulldown disabled
0.45
18
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
–18
II
µA
µA
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
–243
51
–100
110
–19
210
18
Total leakage current through the terminal connection of a driver-
receiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
–18
IOZ
XTALIN (OSC0)
High-level input voltage
0.65 ×
VDDS_OSC
VIH
VIL
V
V
Low-level input voltage
0.35 ×
VDDS_OSC
RTC_XTALIN (OSC1)
High-level input voltage
0.65 ×
VDDS_RTC
VIH
VIL
V
V
Low-level input voltage
0.35 ×
VDDS_RTC
(1) The interfaces or signals described in this table correspond to the interfaces or signals available in multiplexing mode 0. All interfaces or
signals multiplexed on the terminals described in this table have the same DC electrical characteristics.
(2) For mapping to the LPDDR2 interface terminal name, see the AM437x Sitara Processors Technical Reference Manual.
(3) The DDR_RESETn terminal supports fail-safe operation.
(4) The input voltage thresholds for this input are not a function of VDDSHV3.
112
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.8 ADC0: Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
The touch screen controller (TSC) and analog-to-digital converter (ADC) subsystem (ADC0) contains a
single-channel ADC connected to an 8:1 analog multiplexer which operates as a general-purpose ADC
with optional support for interleaving TSC conversions for 4-wire, 5-wire, or 8-wire resistive panels. The
ADC0 subsystem can be configured for use in one of the following applications:
•
•
•
•
8 general-purpose ADC channels
4-wire TSC with 4 general-purpose ADC channels
5-wire TSC with 3 general-purpose ADC channels
8-wire TSC
Table 5-5 summarizes the ADC0 subsystem electrical parameters.
Table 5-5. ADC0 Electrical Parameters
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
NOM
MAX UNIT
(0.5 × VDDA_ADC0) +
0.25
ADC0_VREFP(1)
VDDA_ADC0
V
(0.5 × VDDA_ADC0) –
0.25
ADC0_VREFN(1)
0
V
V
ADC0_VREFP + ADC0_VREFN
VDDA_ADC0
Internal Voltage Reference
External Voltage Reference
0
VDDA_ADC0
ADC0_VREFP
Full-scale Input Range
V
ADC0_VREFN
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
External Voltage Reference:
VREFP – VREFN = 1.8 V
Differential Nonlinearity
(DNL)
–1
–2
0.5
±1
1
LSB
Source impedance = 50 Ω
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
2
External Voltage Reference:
VREFP – VREFN = 1.8 V
Integral Nonlinearity (INL)
LSB
LSB
Source Impedance = 1 kΩ
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
External Voltage Reference:
VREFP – VREFN = 1.8 V
±1
±2
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
External Voltage Reference:
VREFP – VREFN = 1.8 V
Gain Error
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
External Voltage Reference:
VREFP – VREFN = 1.8 V
Offset Error
±2
LSB
pF
Input Sampling Capacitance
5.5
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
Signal-to-Noise Ratio
(SNR)
External Voltage Reference:
VREFP – VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
70
75
dB
dB
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
External Voltage Reference:
VREFP – VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
Total Harmonic Distortion
(THD)
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
113
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-5. ADC0 Electrical Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
Spurious Free Dynamic
Range
External Voltage Reference:
VREFP – VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
80
dB
Internal Voltage Reference:
VDDA_ADC0 = 1.8 V
Signal-to-Noise Plus
Distortion
External Voltage Reference:
VREFP – VREFN = 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
69
20
dB
VREFP and VREFN Input Impedance
Input Impedance of
kΩ
f = input frequency
[1/((65.97 × 10–12) × f)]
Ω
AIN[7:0](2)
SAMPLING DYNAMICS
ADC Clock Frequency
13
MHz
ADC0
clock
Conversion Time
13
cycles
ADC0
Acquisition Time
2
257 clock
cycles
Sampling Rate(3)
ADC0 Clock = 13 MHz
867 kSPS
dB
Channel-to-Channel Isolation
100
2
TOUCH SCREEN SWITCH DRIVERS
Pullup and Pulldown Switch ON-Resistance (Ron)
Pullup and Pulldown Switch
Ω
Source impedance = 500 Ω
0.5
uA
Current Leakage Ileak
Drive Current
25
6
mA
kΩ
kΩ
Touch Screen Resistance
Pen Touch Detect
2
(1) The ADC0_VREFP and ADC0_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If
ADC0_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC0_VREFP is
not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC0. Connecting
ADC0_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC0 may couple more noise into the ADC than
VSSA_ADC.
(2) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
(3) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted
digital value.
114
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.9 ADC1: Analog-to-Digital Subsystem Electrical Parameters
The analog-to-digital converter (ADC) subsystem implements a basic general-purpose ADC1.
Table 5-6 summarizes the ADC1 subsystem electrical parameters.
Table 5-6. ADC1 Electrical Parameters
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
NOM
MAX UNIT
(0.5 × VDDA_ADC1) +
0.25
Bypass mode
VDDA_ADC1
ADC1_VREFP(1)
ADC1_VREFN(1)
V
(0.5 × VDDA_ADC1) +
0.25
Gain mode
Bypass mode
Gain mode
1.2(2)
VDDA_ADC1
(0.5 × VDDA_ADC1) –
0.25
0
0
V
V
(0.5 × VDDA_ADC1) –
0.25
0.5(2)
ADC1_VREFP + ADC1_VREFN
Bypass mode, Internal Voltage
VDDA_ADC1
0
ADC1_VREFN
VDDA_ADC1
ADC1_VREFP
Reference
Bypass mode, External Voltage
Reference
Full-scale Input Range
V
Gain mode, Internal Voltage
Reference
–(VDDA_ADC1 / Gain)
(VDDA_ADC1 / Gain)
Gain mode, External Voltage
Reference
–((ADC1_VREFP –
ADC1_VREFN) / Gain)
((ADC1_VREFP –
ADC1_VREFN) / Gain)
Preamp output
Gain mode (differential)
2.4
0.5
V
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Differential Nonlinearity
(DNL)
–1
1
LSB
GAIN_CTRLx[MSB:LSB] = 00b
GAIN_CTRLx[MSB:LSB] = 01b
GAIN_CTRLx[MSB:LSB] = 10b
GAIN_CTRLx[MSB:LSB] = 11b
Gain mode
12
14
16
18
50
Preamp Gain
Preamp Bandwidth
15
–2
kHz
LSB
Bypass mode
Source impedance = ≤ 1 kΩ
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
±1
±1
2
Integral Nonlinearity (INL)
Gain mode
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Gain Error
±2
±2
LSB
LSB
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Offset Error
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
115
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-6. ADC1 Electrical Parameters (continued)
PARAMETER
TEST CONDITIONS
Bypass mode
MIN
NOM
5.5
2
MAX UNIT
pF
pF
Input Capacitance
Gain mode
Differential Input
Impedance(3)
18
kΩ
Bypass mode
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
70
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
Signal-to-Noise Ratio
(SNR)
dB
Gain mode
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.2 V
Input Signal: 5 kHz sine wave at
Full Scale
70
75
75
80
80
69
Bypass mode
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
Total Harmonic Distortion
(THD)
dB
dB
dB
Gain mode
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.2 V
Input Signal: 5 kHz sine wave at
Full Scale
Bypass mode
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
Spurious Free Dynamic
Range
Gain mode
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.2 V
Input Signal: 5 kHz sine wave at
Full Scale
Bypass mode
Internal Voltage Reference:
VDDA_ADC1 = 1.8 V
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.8 V
Input Signal: 30 kHz sine wave at
–0.5 dB Full Scale
Signal-to-Noise Plus
Distortion
Gain mode
External Voltage Reference:
ADC1_VREFP – ADC1_VREFN
= 1.2 V
Input Signal: 5 kHz sine wave at
Full Scale
69
20
ADC1_VREFP and ADC1_VREFN Input Impedance
kΩ
Input Impedance of
f = input frequency
ADC1_AIN[7:0](4)
[1/((65.97 × 10–12) × f)]
Ω
116
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-6. ADC1 Electrical Parameters (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
SAMPLING DYNAMICS
ADC Clock Frequency
13
MHz
ADC
clock
cycles
Conversion Time
13
ADC
257 clock
cycles
Acquisition Time(5)
Sampling Rate(6)
2
ADC Clock = 13 MHz
867 kSPS
(1) The ADC1_VREFP and ADC1_VREFN terminals should not be allowed to float to prevent noise from coupling into the ADC. If
ADC1_VREFN is not used to connect an external negative voltage reference to the ADC, connect it to VSSA_ADC. If ADC1_VREFP is
not used to connect an external positive voltage reference to the ADC, connect it to VSSA_ADC or VDDA_ADC1. Connecting
ADC1_VREFP to VSSA_ADC in this use case is the preferred option because VDDA_ADC1 may couple more noise into the ADC than
VSSA_ADC.
(2) If the application using ADC1 requires low distortion when operating in Gain mode, the preamplifier output should be limited to ±1.2 volts
differential. To get the full dynamic range of the ADC for this use case it will be necessary to provide a 0.3 volt reference for
ADC1_VREFN and 1.5 volt reference for ADC1_VREFP.
(3) The differential input impedance of each preamplifier is biased to VDDA_ADC1 divided by 2 with a 22-kΩ to 50-kΩ source. See the AFE
Functional Description section of the device-specific TRM for more information.
(4) This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
(5) The maximum sample rate of ADC1 may be reduced when using the internal preamplifiers because the preamplifier outputs require 600
ns to settle. Sample Delay must be configured to provide a minimum acquisition time of 600 ns when using the preamplifiers.
An increase in acquisition time may reduce the maximum sample rate because the maximum sample rate is based on a minimum
acquisition time of 2 ADC clock cycles.
For example, the minimum Sample Delay value should be 6 when the preamplifiers are being used with a 13-MHz ADC clock. A Sample
Delay of 6 provides an acquisition time of 8 ADC clock cycles, which reduces the maximum single input sample rate to 619 kSPS when
the acquisition time is combined with the conversion time of 13 ADC clock cycles.
(6) The maximum sample rate assumes a conversion time of 13 ADC clock cycles with the acquisition time configured for the minimum of 2
ADC clock cycles, where it takes a total of 15 ADC clock cycles to sample the analog input and convert it to a positive binary weighted
digital value.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
117
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.10 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is
applicable only for high-security (AM437xHS) devices.
表 5-7. Recommended Operating Conditions for OTP eFuse Programming
PARAMETER
VDD_CORE
DESCRIPTION
MIN
NOM
MAX
UNIT
Supply voltage range for the core domain during OTP
operation; OPP100
1.056
1.1
1.144
V
Supply voltage range for the eFuse ROM domain during
normal operation
NC
1.7
VPP
Supply voltage range for the eFuse ROM domain during
OTP programming(1)(2)
1.65
0
1.75
V
I(VPP)
50
50
mA
ºC
Temperature (ambient)
30
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70717 from the TLV707x family
meet the supply voltage range needed for VPP.
(2) During normal operation, no voltage should be applied to VPP. This can be typically achieved by disabling the regulator attached to the
VPP terminal. For more details, see TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices.
5.10.1 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The VPP power supply must be disabled when not programming OTP registers.
The VPP power supply must be ramped up after the proper device power-up sequence (for more
details, see 节 5.13.1.2).
5.10.2 Programming Sequence
Programming sequence for OTP eFuses:
1. Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal
during power up and normal operation.
2. Load the OTP write software required to program the eFuse (contact your local TI representative for
the OTP software package).
3. Apply the voltage on the VPP terminal according to the specification in 表 5-7.
4. Run the software that programs the OTP registers.
5. After validating the content of the OTP registers, remove the voltage from the VPP terminal.
5.10.3 Impact to Your Hardware Warranty
You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You
acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a
failure may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI
device specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR
ANY TI DEVICES THAT HAVE BEEN eFUSED.
118
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.11 Thermal Resistance Characteristics
Failure to maintain a junction temperature within the range specified in Section 5.5 reduces operating
lifetime, reliability, and performance—and may cause irreversible damage to the system. Therefore, the
product design cycle should include thermal analysis to verify the maximum operating junction
temperature of the device. It is important this thermal analysis is performed using specific system use
cases and conditions. TI provides an application report to aid users in overcoming some of the existing
challenges of producing a good thermal design. For more information, see AM43xx Thermal
Considerations.
表 5-8 provides thermal characteristics for the packages used on this device.
注
This table provides simulation data and may not represent actual use-case values.
表 5-8. Thermal Resistance Characteristics (NFBGA Package) [ZDN]
over operating free-air temperature range (unless otherwise noted)
ZDN
AIR FLOW
(m/s)(1) (3)
NAME
DESCRIPTION
(°C/W)(1) (2)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
7.07
11.11
23.0
NA
NA
0.0
0.5
1.0
2.0
3.0
0.0
0.5
1.0
2.0
3.0
0.0
0.5
1.0
2.0
3.0
19.5
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
18.5
17.5
16.9
2.10
2.16
2.20
2.27
2.31
11.59
11.18
11.05
10.91
10.80
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(2) °C/W = degrees Celsius per watt.
(3) m/s = meters per second.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
119
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.12 External Capacitors
To improve module performance, decoupling capacitors are required to suppress the switching noise
generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective
when it is close to the device, because this minimizes the inductance of the circuit board wiring and
interconnects.
5.12.1 Voltage Decoupling Capacitors
表 5-9 summarizes the Core voltage decoupling characteristics.
5.12.1.1 Core Voltage Decoupling Capacitors
To improve module performance, decoupling capacitors are required to suppress high-frequency switching
noise and to stabilize the supply voltage. A decoupling capacitor is most effective when located close to
the device, because this minimizes the inductance of the circuit board wiring and interconnects.
表 5-9. Core Voltage Decoupling Characteristics
PARAMETER
TYP
10.08
10.05
UNIT
μF
(1)
CVDD_CORE
(2)
CVDD_MPU
μF
(1) The typical value corresponds to 1 capacitor of 10 μF and 8 capacitors of 10 nF.
(2) The typical value corresponds to 1 capacitor of 10 μF and 5 capacitors of 10 nF.
5.12.1.2 IO and Analog Voltage Decoupling Capacitors
表 5-10 summarizes the power-supply decoupling capacitor recommendations.
表 5-10. Power-Supply Decoupling Capacitor Characteristics
PARAMETER
TYP
UNIT
nF
CVDDA_ADC0
10
10
CVDDA_ADC1
nF
(1)
CVDDA1P8V_USB0
2.21
10
µF
CCVDDA3P3V_USB0
CVDDA1P8V_USB1
CVDDA3P3V_USB1
nF
10
nF
10
nF
(2)
CVDDS
10.04
μF
(3)
CVDDS_DDR
CVDDS_OSC
10
10
nF
nF
nF
µF
µF
nF
nF
nF
nF
μF
μF
μF
μF
μF
μF
CVDDS_PLL_DDR
CVDDS_PLL_CORE_LCD
CVDDS_SRAM_CORE_BG
10
(4)
(5)
10.01
10.01
10
CVDDS_SRAM_MPU_BB
CVDDS_PLL_MPU
CVDDS_RTC
10
CVDDS_CLKOUT
CVDDS3P3V_IOLDO
10
10
(6)
CVDDSHV1
10.02
10.06
10.06
10.02
10.06
10.02
(7)
CVDDSHV2
(7)
CVDDSHV3
(6)
CVDDSHV5
(7)
CVDDSHV6
(6)
CVDDSHV7
120
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
表 5-10. Power-Supply Decoupling Capacitor Characteristics (continued)
PARAMETER
TYP
UNIT
μF
(6)
CVDDSHV8
10.02
10.02
10.02
10.02
(6)
CVDDSHV9
μF
(6)
CVDDSHV10
μF
(6)
CVDDSHV11
μF
(1) Typical values consist of 1 capacitor of 10 μF and 4 capacitors of 10 nF.
(2) Typical values consist of 1 capacitor of 2.2 μF and 1 capacitor of 10 nF.
(3) For more details on decoupling capacitor requirements for the DDR3 and DDR3L memory interface, see Section 5.13.8.2.1.3.6 and
Section 5.13.8.2.1.3.7 when using DDR3 and DDR3L memory devices.
(4) VDDS_SRAM_CORE_BG supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_CORE_BG supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_CORE_BG terminals. TI
recommends placing a 10-μF capacitor close to the terminal and routing it with the widest traces possible to minimize the voltage drop
on VDDS_SRAM_CORE_BG terminals.
(5) VDDS_SRAM_MPU_BB supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals. TI
recommends placing a 10-μF capacitor close to the terminal and routing it with the widest traces possible to minimize the voltage drop
on VDDS_SRAM_MPU_BB terminals.
(6) Typical values consist of 1 capacitor of 10 μF and 2 capacitors of 10 nF.
(7) Typical values consist of 1 capacitor of 10 μF and 6 capacitors of 10 nF.
5.12.2 Output Capacitors
Internal low dropout output (LDO) regulators require external capacitors to stabilize their outputs. These
capacitors should be placed as close as possible to the respective terminals of the device. 表 5-11
summarizes the LDO output capacitor recommendations.
表 5-11. Output Capacitor Characteristics
PARAMETER
TYP
1
UNIT
μF
(1)
CCAP_VDD_SRAM_CORE
(1)(2)
CCAP_VDD_RTC
1
μF
(1)
CCAP_VDD_SRAM_MPU
1
μF
(1)
CCAP_VBB_MPU
1
μF
(1)(3)
CCAP_VDDS1P8V_IOLDO
2.2
μF
(1) LDO regulator outputs should not be used as a power source for any external components.
(2) The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KALDO_ENn terminal is high.
(3) The CAP_VDDS1P8V_IOLDO terminal is the output of the IO LDO and required for simplified power sequencing. For more details, see
图 5-8. If simplified power sequencing is not used, this terminal can be left floating.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
121
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
图 5-2 shows an example of the external capacitors.
Device
VDDS_PLL_MPU
CVDDS_PLL_MPU
MPU
PLL
VDD_MPU
CVDD_MPU
EXTDEV
PLL
MPU
VDDS_PLL_CORE_LCD
CVDDS_PLL_CORE_LCD
CORE
PLL
LCD
PLL
VDD_CORE
CORE
CAP_VBB_MPU
CCAP_VBB_MPU
CVDD_CORE
VDDS
IO
CVDDS
VDDS_SRAM_MPU_BB
CVDDS_SRAM_MPU_BB
VDDSHV1
IOs
MPU SRAM
LDO
CVDDSHV1
Back Bias
LDO
CAP_VDD_SRAM_MPU
CCAP_VDD_SRAM_MPU
VDDSHV2
IOs
CVDDSHV2
CVDDSHV3
VDDS_SRAM_CORE_BG
CVDDS_SRAM_CORE_BG
VDDSHV3
IOs
CORE SRAM
LDO
Band Gap
Reference
CAP_VDD_SRAM_CORE
CCAP_VDD_SRAM_CORE
VDDSHV5
IOs
CVDDSHV5
CVDDSHV6
VDDA_3P3V_USB0
CVDDA_3P3V_USB0
VDDSHV6
IOs
VSSA_USB
USBPHY0
VDDA_1P8V_USB0
VDDSHV7
IOs
CVDDSHV7
CVDDSHV8
CVDDSHV9
CVDDSHV10
PER PLL
CVDDA_1P8V_USB0
VSSA_USB
VDDSHV8
IOs
VDDA_3P3V_USB1
CVDDA_3P3V_USB1
VDDSHV9
IOs
VSSA_USB
USBPHY1
VDDA_1P8V_USB1
CVDDA_1P8V_USB1
VDDSHV10
IOs
VSSA_USB
VDDA_ADC0
CVDDA_ADC0
VDDSHV11
IOs
ADC0
CVDDSHV11
CVDDS_DDR
VSSA_ADC
VDDA_ADC1
VDDS_DDR
IOs
CVDDA_ADC1
ADC1
VDDS_OSC
RTC
VSSA_ADC
VDDS_RTC
IOs
CVDDS_RTC
CVDDS_OSC
VDDS_PLL_DDR
CVDDS_PLL_DDR
CAP_VDD_RTC
CCAP_VDD_RTC
DDR
PLL
VDDS3P3V_
IOLDO
CAP_VDDS1P8V_IOLDO
A. Decoupling capacitors must be placed as closed as possible to the power terminal. Choose the ground closest to the
power pin for each decoupling capacitor. In case of interconnecting powers, first insert the decoupling capacitor and
then interconnect the powers.
B. The decoupling capacitor value depends on the board characteristics.
图 5-2. External Capacitors
122
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13 Timing and Switching Characteristics
The data provided in the following timing requirements and switching characteristics tables assumes the
device is operating within the recommended operating conditions defined in Section 5.5, unless otherwise
noted.
5.13.1 Power Supply Sequencing
5.13.1.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 1.0E + 5 V/s. For instance, as shown in 图 5-3, TI
recommends having the supply ramp slew for a 1.8-V supply of more than 18 µs.
Supply value
t
slew rate < 1E + 5 V/s
slew > (supply value) / (1E + 5V/s)
supply value ´ 10 µs
0
图 5-3. Power Supply Slew and Slew Rate
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
123
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.1.2 Power-Up Sequencing
1.8V
1.8V
VDDS_RTC(A)
RTC_PWRONRSTn(B)
RTC_PMIC_EN
1.8V
1.8V
1.8V
VDDS,
VDDS_CLKOUT
VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR,
VDDS_PLL_CORE_LCD, VDDS_PLL_MPU,
VDDS_SRAM_MPU_BB,
VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1(C)
1.2V/1.35V/1.5V
VDDS_DDR
3.3V
1.1V
1.1V
VDDSHVx [x=1-11]
VDDA3P3V_USB0/1
VDD_CORE(D)
VDD_MPU(D)
CLK_32K_RTC
CLK_M_OSC
PWRONRSTn
1.8V/3.3V(E)
(F)
A. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If
CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE.
VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of
leakage current on VDD_CORE.
B. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable.
C. These supplies can be ramped together with VDDS, VDDS_CLKOUT supplies if powered from the same source only.
If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the
respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-
V supply, the VDDA3P3V_USB may be connected to ground.
D. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.
E. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe.
PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However,
PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input
terminal, see Section 5.7.
F. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock
CLK_M_OSC is stable.
图 5-4. Power Sequencing With RTC Feature Enabled, All Dual-Voltage IOs Configured as 3.3 V
124
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1.8V
1.8V
VDDS_RTC(A)
RTC_PWRONRSTn(B)
1.8V
1.8V
1.8V
RTC_PMIC_EN
VDDS, VDDSHVx [x=1-11]
VDDS_CLKOUT
VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR,
VDDS_PLL_CORE_LCD, VDDS_PLL_MPU,
VDDS_SRAM_MPU_BB,
VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1(C)
1.2V/1.35V/1.5V
VDDS_DDR
3.3V
1.1V
1.1V
VDDA3P3V_USB0/1
VDD_CORE(D)
VDD_MPU(D)
CLK_32K_RTC
CLK_M_OSC
PWRONRSTn
1.8V
(E)
A. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If
CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE.
B. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable.
C. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered
from the same source.
If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the
respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-
V supply, the VDDA3P3V_USB may be connected to ground.
D. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.
E. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock
CLK_M_OSC is stable.
图 5-5. Power Sequencing With RTC Feature Enabled, All Dual-Voltage IOs Configured as 1.8 V
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
125
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
1.8V
1.8V
VDDS_RTC(A)
RTC_PWRONRSTn(B)
RTC_PMIC_EN
1.8V
1.8V
1.8V
VDDS,
VDDS_CLKOUT
VDDSHVx [x=1-11]
VDDS_OSC, VDDA_ADC0/1, VDDS_PLL_DDR,
VDDS_PLL_CORE_LCD, VDDS_PLL_MPU,
VDDS_SRAM_MPU_BB,
VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1(C)
1.2V/1.35V/1.5V
VDDS_DDR
3.3V
1.1V
1.1V
VDDSHVx [x=1-11]
VDDA3P3V_USB0/1
VDD_CORE(D)
VDD_MPU(D)
CLK_32K_RTC
CLK_M_OSC
PWRONRSTn
1.8V/3.3V(E)
(F)
A. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If
CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE.
B. RTC_PWRONRSTn should be asserted for at least 1 ms and can be released before the 32-kHz clock is stable.
C. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered
from the same source.
If a USB port is not used, the respective VDDA1P8V_USB may be connected to any 1.8-V power supply and the
respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-
V supply, the VDDA3P3V_USB may be connected to ground.
D. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.
E. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe.
PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However,
PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input
terminal, see Section 5.7.
F. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock
CLK_M_OSC is stable.
图 5-6. Power Sequencing With RTC Feature Enabled, Dual-Voltage IOs Configured as 1.8 V, 3.3 V
126
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1.8V
VDDS,
VDDS_CLKOUT
VDDSHVx [x=1-11]
1.8V
VDDS_RTC, VDDS_OSC, VDDA_ADC0/1,
VDDS_PLL_DDR, VDDS_PLL_CORE_LCD,
VDDS_PLL_MPU, VDDS_SRAM_MPU_BB,
(A)
VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1
1.2V/1.35V/1.5V
VDDS_DDR
3.3V
1.1V
1.1V
VDDSHVx [x=1-11]
VDDA3P3V_USB0/1
(B)
VDD_CORE
,
(C)
CAP_VDD_RTC
(B)
VDD_MPU
CLK_M_OSC
(D)
1.8V/3.3V
(E)
PWRONRSTn
A. These supplies can be ramped together with the VDDS, VDDSHVx [x=1-11], VDDS_CLKOUT supplies if powered
from the same source.
If a USB port is not used, the repsective VDDA1P8V_USB may be connected to any 1.8-V power supply and the
respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-
V supply, the VDDA3P3V_USB may be connected to ground.
B. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.
C. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If
CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE.
VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of
leakage current on VDD_CORE.
D. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe.
PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However,
PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input
terminal, see Section 5.7.
E. It is required to hold the PWRONRSTn terminal low until all the supplies have ramped and the input clock
CLK_M_OSC is stable.
图 5-7. Power Sequencing With RTC Feature Disabled, Dual-Voltage IOs Configured as 1.8 V, 3.3 V
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
127
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
3.3V
VDDS3P3V_IOLDO,
VDDSHVx [x=1-11]
(A)
VDDA3P3V_USB0/1
1.8V
VDDS_RTC, VDDS_OSC, VDDA_ADC0/1,
VDDS_PLL_DDR, VDDS_PLL_CORE_LCD,
VDDS_PLL_MPU, VDDS_SRAM_MPU_BB,
(B)
VDDS_SRAM_CORE_BG, VDDA1P8V_USB0/1
1.2V/1.35V/1.5V
VDDS_DDR
1.1V
(C)
VDD_CORE
(D)
CAP_VDD_RTC
1.1V
(C)
VDD_MPU
CLK_M_OSC
(E)
1.8V/3.3V
(F)
PWRONRSTn
A. Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us.
CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered
by shorting them to CAP_VDDS1P8V_IOLDO on the board.
B. If a USB port is not used, the repsective VDDA1P8V_USB may be connected to any 1.8-V power supply and the
respective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If a system does not have a 3.3-
V supply, the VDDA3P3V_USB may be connected to ground.
C. VDD_MPU and VDD_CORE can be supplied from the same power source if OPPs higher than OPP100 are not used.
D. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is
disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC.
If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If
CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE.
VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of
leakage current on VDD_CORE.
E. PWRONRSTn input voltage thresholds are not dependent on VDDSHV3 voltage and the terminal is not fail-safe.
PWRONRSTn can accept 1.8-V or 3.3-V input levels when VDDSHV3 is configured as 3.3 V. However,
PWRONRSTn can only accept 1.8 V input levels when VDDSHV3 is configured as 1.8 V. For details on this input
terminal, see Section 5.7.
F. The PWRONRSTn terminal must be held low until all the supplies have ramped and the input clock CLK_M_OSC is
stable.
图 5-8. Simplified Power Sequencing With RTC Feature Disabled, Dual-Voltage IOs
Configured as 3.3 V
128
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.1.3 Power-Down Sequencing
PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies
are turned off. All other external clocks to the device should be shut off.
The preferred way to sequence power down is to have all the power supplies ramped down sequentially in
the exact reverse order of the power-up sequencing. In other words, the power supply that has been
ramped up first should be the last one that is ramped down. This ensures there would be no spurious
current paths during the power-down sequence. The VDDS, VDDS_CLKOUT power supply must ramp
down after all 3.3-V VDDSHVx [x=1-11] power supplies.
If it is desired to ramp down VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] simultaneously, it should
always be ensured that the difference between VDDS, VDDS_CLKOUT and VDDSHVx [x=1-11] during
the entire power-down sequence is <2 V. Any violation of this could cause reliability risks for the device.
Further, it is recommended to maintain VDDS, VDDS_CLKOUT ≥1.5V as all the other supplies fully ramp
down to minimize in-rush currents.
If none of the VDDSHVx [x=1-11] power supplies are configured as 3.3 V, the VDDS, VDDS_CLKOUT
power supply may ramp down along with the VDDSHVx [x=1-11] supplies or after all the VDDSHVx [x=1-
11] supplies have ramped down. TI recommends maintaining VDDS, VDDS_CLKOUT ≥1.5V as all the
other supplies fully ramp down to minimize in-rush currents.
When using simplified power-down sequence, there are no power-down requirements between the VDDS,
VDDS_CLKOUT and VDDSHVx [x=1-11] supplies and are ramped down together without any reliability
concerns.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
129
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.2 Clock
5.13.2.1 PLLs
5.13.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the device. The device integrates six different DPLLs:
•
•
•
•
•
•
Core DPLL
Per DPLL
Display DPLL
DDR DPLL
MPU DPLL
EXTDEV DPLL
图 5-9 shows the power supply connectivity implemented in the device. 表 5-12 provides the power supply
requirements for the DPLL.
MPU
PLL
PER
PLL
VDDS_PLL_MPU
VDDA1P8V_USB0
CORE
PLL
DDR
PLL
VDDS_PLL_DDR
EXTDEV
PLL
VDDS_PLL_CORE_LCD
LCD
PLL
图 5-9. DPLL Power Supply Connectivity
表 5-12. DPLL Power Supply Requirements
SUPPLY NAME
DESCRIPTION
MIN NOM MAX
UNIT
VDDA1P8V_USB0
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8V
Max. peak-to-peak supply noise
1.71 1.8
1.71 1.8
1.71 1.8
1.71 1.8
1.89
V
50 mV (p-p)
VDDS_PLL_MPU
Supply voltage range for DPLL MPU, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
Supply voltage range for DPLL CORE, EXTDEV, and LCD, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
Supply voltage range for DPLL DDR, Analog
Max. peak-to-peak supply noise
1.89
V
50 mV (p-p)
130
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.2.2 Input Clock Specifications
The device has two clock inputs. Each clock input passes through an internal oscillator which can be
connected to an external crystal circuit (oscillator mode) or external LVCMOS square-wave digital clock
source (bypass mode). The oscillators automatically operate in bypass mode when their input is
connected to an external LVCMOS square-wave digital clock source. The oscillator associated with a
specific clock input must be enabled when the clock input is being used in either oscillator mode or bypass
mode.
The OSC1 oscillator provides a 32.768-kHz reference clock to the real-time clock (RTC) and is connected
to the RTC_XTALIN and RTC_XTALOUT terminals. This clock source is referred to as the 32K oscillator
(CLK_32K_RTC) in the device-specific technical reference manual. OSC1 is disabled by default after
power is applied. This clock input is optional and may not be required if the RTC is configured to receive a
clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a
reference clock from the OSC0 input.
The OSC0 oscillator provides a 19.2-MHz, 24-MHz, 25-MHz, or 26-MHz reference clock which is used to
clock all non-RTC functions and is connected to the XTALIN and XTALOUT terminals. This clock source is
referred to as the master oscillator (CLK_M_OSC) in the device-specific technical reference manual.
OSC0 is enabled by default after power is applied.
For more information related to recommended circuit topologies and crystal oscillator circuit requirements
for these clock inputs, see 节 5.13.2.3.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
131
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.2.3 Input Clock Requirements
5.13.2.3.1 OSC0 Internal Oscillator Clock Source
图 5-10 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required
and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating
oscillator performance with production crystal circuit components installed on preproduction PCBs.
The XTALIN terminal has a 15-kΩ to 40-kΩ internal pulldown resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
Device
XTALIN
VSS_OSC
XTALOUT
C1
C2
Optional Rd
Crystal
Optional Rbias
Copyright © 2016, Texas Instruments Incorporated
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the package. Parasitic
capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled
into the oscillator. The external crystal component grounds should be connected to the VSS_OSC terminal. The
VSS_OSC terminal should be connected to the PCB ground plane as close as possible to the device.
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL
=
[(C1×C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the XTALIN and XTALOUT signals. For recommended values
of crystal circuit components, see 表 5-13.
图 5-10. OSC0 Crystal Circuit Schematic
132
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
表 5-13. OSC0 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Crystal parallel resonance
frequency
Fundamental mode oscillation only
19.2, 24.0,
25.0, or
26.0
MHz
fxtal
Crystal frequency stability
and tolerance
–50.0
50.0
ppm
CC1
C1 capacitance
C2 capacitance
Shunt capacitance
12.0
12.0
24.0
24.0
5.0
pF
pF
pF
CC2
Cshunt
Crystal effective series
resistance
fxtal = 19.2 MHz, oscillator has nominal
negative resistance of 272 Ω and worst-
case negative resistance of 163 Ω
54.4
fxtal = 24.0 MHz, oscillator has nominal
negative resistance of 240 Ω and worst-
case negative resistance of 144 Ω
48.0
46.6
45.3
ESR
Ω
fxtal = 25.0 MHz, oscillator has nominal
negative resistance of 233 Ω and worst-
case negative resistance of 140 Ω
fxtal = 26.0 MHz, oscillator has nominal
negative resistance of 227 Ω and worst-
case negative resistance of 137 Ω
表 5-14. OSC0 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Shunt capacitance of
package
ZDN package
0.01
Cpkg
pF
The actual values of the ESR, fxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, fxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π fxtal
CL VDDS_OSC)2
Pxtal
tsX
Start-up time
1.5
ms
VDD_CORE (min.)
VDD_CORE
VSS
VDDS_OSC (min.)
VDDS_OSC
XTALOUT
VSS
tsX
Time
图 5-11. OSC0 Start-up Time
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
133
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.2.3.2 OSC0 LVCMOS Digital Clock Source
图 5-12 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-
wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. In this mode
of operation, the XTALOUT terminal should not be used to source any external components. The printed
circuit board design should provide a mechanism to disconnect the XTALOUT terminal from any external
components or signal traces that may couple noise into OSC0 via the XTALOUT terminal.
The XTALIN terminal has a 15-kΩ to 40-kΩ internal pulldown resistor which is enabled when OSC0 is
disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which
may increase leakage current through the oscillator input buffer.
Device
XTALIN
VSS_OSC
XTALOUT
VDDS_OSC
LVCMOS
Digital
Clock
Source
Copyright © 2016, Texas Instruments Incorporated
图 5-12. OSC0 LVCMOS Circuit Schematic
表 5-15. OSC0 LVCMOS Reference Clock Requirements
NAME
f(XTALIN)
DESCRIPTION
Frequency, LVCMOS reference clock
MIN
TYP
MAX
UNIT
MHz
ppm
19.2, 24, 25,
or 26
Frequency, LVCMOS reference clock stability and tolerance(1)
Duty cycle, LVCMOS reference clock period
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
–50
45%
–1%
50
55%
1%
5
tdc(XTALIN)
tjpp(XTALIN)
tR(XTALIN)
tF(XTALIN)
ns
ns
Time, LVCMOS reference clock fall
5
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
134
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.2.3.3 OSC1 Internal Oscillator Clock Source
图 5-13 shows the recommended crystal circuit for OSC1 of the package. It is recommended that pre-
production printed circuit board (PCB) designs include the two optional resistors Rbias and Rd in case they
are required for proper oscillator operation when combined with production crystal circuit components. In
most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from
production PCB designs after evaluating oscillator performance with production crystal circuit components
installed on preproduction PCBs.
The RTC_XTALIN terminal has a 10-kΩ to 40-kΩ internal pullup resistor which is enabled when OSC1 is
disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level
which may increase leakage current through the oscillator input buffer.
Device
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
Optional Rbias
Optional Rd
Crystal
C1
C2
Copyright © 2016, Texas Instruments Incorporated
A. Oscillator components (Crystal, C1, C2, optional Rbias and Rd) must be located close to the package. Parasitic
capacitance to the printed circuit board (PCB) ground and other signals should be minimized to reduce noise coupled
into the oscillator.
B. C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other components
(excluding the crystal) connected to each crystal terminal. The value of capacitors C1 and C2 should be selected to
provide the total load capacitance, CL, specified by the crystal manufacturer. The total load capacitance is CL
=
[(C1×C2)/(C1+C2)] + Cshunt, where Cshunt is the crystal shunt capacitance (C0) specified by the crystal manufacturer
plus any mutual capacitance (Cpkg + CPCB) seen across the RTC_XTALIN and RTC_XTALOUT signals. For
recommended values of crystal circuit components, see 表 5-16.
图 5-13. OSC1 Crystal Circuit Schematic
表 5-16. OSC1 Crystal Circuit Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Crystal parallel resonance
frequency
Fundamental mode oscillation only
32.768
kHz
Crystal frequency stability
and tolerance
Maximum RTC error = 10.512 minutes
per year
–20.0
–50.0
20.0
50.0
fxtal
ppm
ppm
Maximum RTC error = 26.28 minutes per
year
CC1
C1 capacitance
C2 capacitance
Shunt capacitance
12.0
12.0
24.0
24.0
1.5
pF
pF
pF
CC2
Cshunt
Crystal effective series
resistance
fxtal = 32.768 kHz, oscillator has nominal
negative resistance of 725 kΩ and worst-
case negative resistance of 250 kΩ
80
ESR
kΩ
表 5-17. OSC1 Crystal Circuit Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Shunt capacitance of
package
ZDN package
0.17
Cpkg
pF
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
135
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
表 5-17. OSC1 Crystal Circuit Characteristics (continued)
NAME
Pxtal
tsX
DESCRIPTION
MIN
TYP
MAX
UNIT
The actual values of the ESR, fxtal, and CL should be used to yield a
typical crystal power dissipation value. Using the maximum values
specified for ESR, fxtal, and CL parameters yields a maximum power
dissipation value.
Pxtal = 0.5 ESR (2 π fxtal
CL VDDS_RTC)2
Start-up time
2
s
CAP_VDD_RTC (min.)
CAP_VDD_RTC
VSS_RTC
VDDS_RTC (min.)
VDDS_RTC
RTC_XTALOUT
VSS_RTC
tsX
Time
图 5-14. OSC1 Start-up Time
136
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.2.3.4 OSC1 LVCMOS Digital Clock Source
图 5-15 shows the recommended oscillator connections when OSC1 of the package is connected to an
LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the RTC_XTALIN
terminal. In this mode of operation, the RTC_XTALOUT terminal should not be used to source any
external components. The printed circuit board design should provide a mechanism to disconnect the
RTC_XTALOUT terminal from any external components or signal traces that may couple noise into OSC1
via the RTC_XTALOUT terminal.
The RTC_XTALIN terminal has a 10-kΩ to 40-kΩ internal pullup resistor which is enabled when OSC1 is
disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level
which may increase leakage current through the oscillator input buffer.
Device
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
VDDS_RTC
LVCMOS
Digital
Clock
N/C
Source
Copyright © 2016, Texas Instruments Incorporated
图 5-15. OSC1 LVCMOS Circuit Schematic
表 5-18. OSC1 LVCMOS Reference Clock Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Frequency, LVCMOS reference clock
32.768
kHz
Maximum RTC error =
10.512 minutes/year
–20
–50
20
50
ppm
ppm
f(RTC_XTALIN)
Frequency, LVCMOS reference clock
stability and tolerance(1)
Maximum RTC error = 26.28
minutes/year
tdc(RTC_XTALIN)
tjpp(RTC_XTALIN)
tR(RTC_XTALIN)
tF(RTC_XTALIN)
Duty cycle, LVCMOS reference clock period
45%
–1%
55%
1%
5
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
ns
ns
Time, LVCMOS reference clock fall
5
(1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
5.13.2.3.5 OSC1 Not Used
图 5-16 shows the recommended oscillator connections when OSC1 is not used. An internal 10-kΩ pullup
on the RTC_XTALIN terminal is turned on when OSC1 is disabled to prevent this input from floating to an
invalid logic level which may increase leakage current through the oscillator input buffer. OSC1 is disabled
by default after power is applied. Therefore, both RTC_XTALIN and RTC_XTALOUT terminals should be
a no connect (NC) when OSC1 is not used.
For more information on disabling OSC1, see the device-specific technical reference manual.
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
137
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Device
RTC_XTALIN
VSS_RTC
RTC_XTALOUT
N/C
N/C
Copyright © 2016, Texas Instruments Incorporated
图 5-16. OSC1 Not Used Schematic
5.13.2.4 Output Clock Specifications
The device has two clock output signals. The CLKOUT1 signal can be configured to output the master
oscillator (CLK_M_OSC), EXTDEV_PLL, 32-kHz, or several other internal clocks. See the device-specific
TRM for more details. The CLKOUT2 signal can be configured to output the OSC1 input clock, which is
referred to as the 32K oscillator (CLK_32K_RTC) in the device-specific technical reference manual, or four
other internal clocks. For more information related to configuring these clock output signals, see the
CLKOUT Signals section of the device-specific technical reference manual.
5.13.2.5 Output Clock Characteristics
5.13.2.5.1 CLKOUT1
The CLKOUT1 signal can be output on the XDMA_EVENT_INTR0 terminal. This terminal connects to one
of seven internal signals through configurable multiplexers. The XDMA_EVENT_INTR0 multiplexer must
be configured for Mode 3 to connect the CLKOUT1 signal to the XDMA_EVENT_INTR0 terminal.
The default reset configuration of the XDMA_EVENT_INTR0 multiplexer is selected by the logic level
applied to the DSS_HSYNC terminal on the rising edge of PWRONRSTn. The XDMA_EVENT_INTR0
multiplexer is configured to Mode 7 if the DSS_HSYNC terminal is low on the rising edge of PWRONRSTn
or Mode 3 if the DSS_HSYNC terminal is high on the rising edge of PWRONRSTn. This allows the
CLKOUT1 signal to be output on the XDMA_EVENT_INTR0 terminal without software intervention. In this
mode, the output is held low while PWRONRSTn is active and begins to toggle after PWRONRSTn is
released.
5.13.2.5.2 CLKOUT2
The CLKOUT2 signal can be output on the XDMA_EVENT_INTR1 terminal. This terminal connects to one
of seven internal signals through configurable multiplexers. The XDMA_EVENT_INTR1 multiplexer must
be configured for Mode 3 to connect the CLKOUT2 signal to the XDMA_EVENT_INTR1 terminal.
The default reset configuration of the XDMA_EVENT_INTR1 multiplexer is always Mode 7. Software must
configure the XDMA_EVENT_INTR1 multiplexer to Mode 3 for the CLKOUT2 signal to be output on the
XDMA_EVENT_INTR1 terminal.
5.13.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing or decreasing such delays. TI recommends using the available IO buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control
register is configured for fast mode (0b).
138
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
For the LPDDR2, DDR3, and DDR3L memory interfaces, it is not necessary to use the IBIS models to
analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to
ensure the memory interface timings are met.
5.13.4 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
139
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.5 Controller Area Network (CAN)
For more information, see the Controller Area Network (CAN) section of the AM437x Sitara Processors
Technical Reference Manual.
5.13.5.1 DCAN Electrical Data and Timing
Table 5-19. Timing Requirements for DCANx Receive
(see Figure 5-17)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
1
MAX
1
fbaud(baud)
tw(RX)
Maximum programmable baud rate
Pulse duration, receive data bit
Mbps
ns
1
H - 2(1)
H + 2(1)
H + 2(1)
H + 2(1)
(1) H = period of baud rate, 1/programmed baud rate.
Table 5-20. Switching Characteristics for DCANx Transmit
(see Figure 5-17)
NO.
OPP100
OPP50
PARAMETER
UNIT
MIN
MAX
1
MIN
MAX
1
fbaud(baud)
Maximum programmable baud rate
Pulse duration, transmit data bit
Mbps
ns
2
tw(TX)
H - 2(1)
H + 2(1)
H - 2(1)
H + 2(1)
(1) H = period of baud rate, 1/programmed baud rate.
1
2
DCANx_RX
DCANx_TX
Figure 5-17. DCANx Timings
140
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.6 DMTimer
5.13.6.1 DMTimer Electrical Data and Timing
Table 5-21. Timing Requirements for DMTimer [1-11]
(see Figure 5-18)
NO.
MIN
4P+1(1)
MAX
MAX
UNIT
1
tc(TCLKIN)
Cycle time, TCLKIN
ns
(1) P = period of PICLKOCP (interface clock).
Table 5-22. Switching Characteristics for DMTimer [4-7]
(see Figure 5-18)
NO.
PARAMETER
MIN
4P-3(1)
4P-3(1)
UNIT
ns
2
3
tw(TIMERxH)
tw(TIMERxL)
Pulse duration, high
Pulse duration, low
ns
(1) P = period of PICLKTIMER (functional clock).
1
TCLKIN
2
3
TIMER[x]
Figure 5-18. Timer Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
141
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.7 Ethernet Media Access Controller (EMAC) and Switch
5.13.7.1 Ethernet MAC and Switch Electrical Data and Timing
The Ethernet MAC and Switch implemented in the device supports GMII mode, but the design does not
pin out 9 of the 24 GMII signals. This was done to reduce the total number of package terminals.
Therefore, the device does not support GMII mode. MII mode is supported with the remaining GMII
signals.
The AM437x Sitara Processors Technical Reference Manual and this document may reference internal
signal names when discussing peripheral input and output signals because many of the package terminals
can be multiplexed to one of several peripheral signals. For example, the terminal names for port 1 of the
Ethernet MAC and switch have been changed from GMII to MII to indicate their Mode 0 function, but the
internal signal is named GMII. However, documents that describe the Ethernet switch reference these
signals by their internal signal name. For a cross-reference of internal signal names to terminal names,
see Table 4-7.
Operation of the Ethernet MAC and switch in RGMII mode is not supported for OPP50.
Table 5-23. Ethernet MAC and Switch Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
5(1)
5(1)
ns
ns
Output Condition
CLOAD Output load capacitance
3
30
pF
(1) Except when specified otherwise.
5.13.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
Table 5-24. Timing Requirements for MDIO_DATA
(see Figure 5-19)
NO.
MIN
TYP
MAX
UNIT
ns
1
tsu(MDIO-MDC) Setup time, MDIO valid before MDC high
90
0
2
th(MDIO-MDC)
Hold time, MDIO valid from MDC high
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
Figure 5-19. MDIO_DATA Timing - Input Mode
Table 5-25. Switching Characteristics for MDIO_CLK
(see Figure 5-20)
NO.
1
PARAMETER
Cycle time, MDC
MIN
400
160
160
TYP
MAX
UNIT
ns
tc(MDC)
tw(MDCH)
tw(MDCL)
tt(MDC)
2
Pulse duration, MDC high
Pulse duration, MDC low
Transition time, MDC
ns
3
ns
4
5
ns
142
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1
4
2
3
MDIO_CLK
4
Figure 5-20. MDIO_CLK Timing
Table 5-26. Switching Characteristics for MDIO_DATA
(see Figure 5-21)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
10
390
ns
1
MDIO_CLK (Output)
MDIO_DATA (Output)
Figure 5-21. MDIO_DATA Timing - Output Mode
5.13.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
Table 5-27. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see Figure 5-22)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
Pulse Duration, RX_CLK high
Pulse Duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
5
5
1
4
2
3
GMII[x]_RXCLK
4
Figure 5-22. GMII[x]_RXCLK Timing - MII Mode
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
143
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-28. Timing Requirements for GMII[x]_TXCLK - MII Mode
(see Figure 5-23)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
1
2
3
4
tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Cycle time, TX_CLK
40.004
ns
ns
ns
ns
Pulse Duration, TX_CLK high
Pulse Duration, TX_CLK low
Transition time, TX_CLK
26
26
5
140
260
14
5
1
4
2
3
GMII[x]_TXCLK
4
Figure 5-23. GMII[x]_TXCLK Timing - MII Mode
Table 5-29. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
(see Figure 5-24)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
MAX
MIN
MAX
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
1
tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
8
8
ns
th(RX_CLK-RXD)
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
2
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
ns
1
2
GMII[x]_MRCLK (Input)
GMII[x]_RXD[3:0], GMII[x]_RXDV,
GMII[x]_RXER (Inputs)
Figure 5-24. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode
144
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-30. Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
(see Figure 5-25)
10 Mbps
TYP
100 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td(TX_CLK-TXD)
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
1
5
25
5
25 ns
td(TX_CLK-TX_EN)
1
GMII[x]_TXCLK (input)
GMII[x]_TXD[3:0],
GMII[x]_TXEN (outputs)
Figure 5-25. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
145
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
Table 5-31. Timing Requirements for RMII[x]_REFCLK - RMII Mode
(see Figure 5-26)
NO.
MIN
TYP
MAX
UNIT
ns
1
2
3
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
Cycle time, REF_CLK
19.999
20.001
13
Pulse Duration, REF_CLK high
Pulse Duration, REF_CLK low
7
7
ns
13
ns
1
2
RMII[x]_REFCLK
(Input)
3
Figure 5-26. RMII[x]_REFCLK Timing - RMII Mode
Table 5-32. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
(see Figure 5-27)
NO.
MIN
TYP
MAX
UNIT
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, RXD[1:0] valid before REF_CLK
Setup time, CRS_DV valid before REF_CLK
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK
Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLK
1
4
ns
2
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
1
2
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER (inputs)
Figure 5-27. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
146
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-33. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
(see Figure 5-28)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
td(REF_CLK-TXD)
td(REF_CLK-TXEN)
tr(TXD)
Delay time, REF_CLK high to TXD[1:0] valid
Delay time, REF_CLK to TXEN valid
Rise time, TXD outputs
1
2
14.2
ns
2
3
1
1
5
5
ns
ns
tr(TX_EN)
Rise time, TX_EN output
tf(TXD)
Fall time, TXD outputs
tf(TX_EN)
Fall time, TX_EN output
1
RMII[x]_REFCLK (Input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (Outputs)
3
2
Figure 5-28. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
147
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
Table 5-34. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see Figure 5-29)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
1
2
tc(RXC)
Cycle time, RXC
360
440
36
44
7.2
8.8 ns
Pulse duration, RXC
high
tw(RXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(RXCL)
tt(RXC)
Pulse duration, RXC low
Transition time, RXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_RCLK
Figure 5-29. RGMII[x]_RCLK Timing - RGMII Mode
Table 5-35. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see Figure 5-30)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
UNIT
MAX
MAX
MAX
Setup time, RD[3:0] valid
before RXC high or low
tsu(RD-RXC)
tsu(RX_CTL-RXC)
1
1
1
1
1
1
1
1
1
1
1
1
1
ns
Setup time, RX_CTL valid
before RXC high or low
Hold time, RD[3:0] valid
after RXC high or low
th(RXC-RD)
2
3
ns
ns
Hold time, RX_CTL valid
after RXC high or low
th(RXC-RX_CTL)
tt(RD)
Transition time, RD
0.75
0.75
0.75
0.75
0.75
0.75
tt(RX_CTL)
Transition time, RX_CTL
RGMII[x]_RCLK(A)
1
1st Half-byte
2
2nd Half-byte
RGMII[x]_RD[3:0](B)
RGMII[x]_RCTL(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
3
A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
Figure 5-30. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
148
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-36. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-31)
10 Mbps
TYP
100 Mbps
TYP
1000 Mbps
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
8.8 ns
1
2
tc(TXC)
Cycle time, TXC
360
440
36
44
7.2
Pulse duration, TXC
high
tw(TXCH)
160
160
240
16
16
24
3.6
3.6
4.4 ns
3
4
tw(TXCL)
tt(TXC)
Pulse duration, TXC low
Transition time, TXC
240
24
4.4 ns
0.75
0.75
0.75 ns
1
4
2
4
3
RGMII[x]_TCLK
Figure 5-31. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-37. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-32)
10 Mbps
MIN TYP
100 Mbps
MIN TYP
1000 Mbps
MIN TYP
NO.
PARAMETER
UNIT
ns
MAX
0.5
MAX
0.5
MAX
0.5
tsk(TD-TXC)
TD to TXC output skew
TX_CTL to TXC output skew
Transition time, TD
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
1
tsk(TX_CTL-TXC)
0.5
0.5
0.5
tt(TD)
0.75
0.75
0.75
0.75
0.75
0.75
2
ns
tt(TX_CTL)
Transition time, TX_CTL
RGMII[x]_TCLK(A)
1
1
2
RGMII[x]_TD[3:0](B)
RGMII[x]_TCTL(B)
1st Half-byte
2nd Half-byte
TXERR
TXEN
A. The Ethernet MAC and switch implemented in the device supports internal TX delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-32. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
149
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8 External Memory Interfaces
The device includes the following external memory interfaces:
•
•
General-purpose memory controller (GPMC)
LPDDR2, DDR3, and DDR3L Memory Interface (EMIF)
5.13.8.1 General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem and General-Purpose Memory Controller
section of the AM437x Sitara Processors Technical Reference Manual.
The GPMC is the unified memory controller used to interface external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
5.13.8.1.1 GPMC and NOR Flash—Synchronous Mode
Table 5-39 and Table 5-40 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-33 through Figure 5-37).
Table 5-38. GPMC and NOR Flash Timing Conditions—Synchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
0.3
0.3
1.8
1.8
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-39. GPMC and NOR Flash Timing Requirements—Synchronous Mode
OPP100
OPP50
NO.
UNIT
MIN
MAX
MIN
MAX
F12 tsu(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock
gpmc_clk high
3.5
13.2
ns
F13 th(clkH-dV)
Hold time, input data gpmc_ad[15:0] valid after output clock
gpmc_clk high
Setup time, input wait gpmc_wait[x](1) valid before output clock
gpmc_clk high
Hold time, input wait gpmc_wait[x](1) valid after output clock
gpmc_clk high
2.5
3.5
2.5
2.75
13.2
2.5
ns
ns
ns
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
(1) In gpmc_wait[x], x is equal to 0 or 1.
150
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-40. GPMC and NOR Flash Switching Characteristics—Synchronous Mode
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
100
0.5P(2)
0.5P(2)
500
33.33
2
MIN
MAX
F0
F1
F1
1 / tc(clk)
Frequency(1), output clock gpmc_clk
50 MHz
tw(clkH)
tw(clkL)
tdc(clk)
tJ(clk)
Typical pulse duration, output clock gpmc_clk high
Typical pulse duration, output clock gpmc_clk low
Duty cycle error, output clock gpmc_clk
Jitter standard deviation(3), output clock gpmc_clk
Rise time, output clock gpmc_clk
0.5P(2)
0.5P(2)
–500
0.5P(2)
0.5P(2)
–500
0.5P(2)
0.5P(2)
ns
ns
ps
ps
ns
ns
ns
ns
ns
500
33.33
tR(clk)
2
tF(clk)
Fall time, output clock gpmc_clk
2
2
tR(do)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
2
2
2
tF(do)
2
F2
F3
F4
F5
F6
td(clkH-csnV)
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x](4) transition
F(5) – 2.2 F(5) + 4.5
F(5) – 3.2
F(5) + 9.5
td(clkH-csnIV)
td(aV-clk)
td(clkH-aIV)
td(be[x]nV-clk)
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_csn[x](4) invalid
E(6) – 2.2 E(6) + 4.5 E(6) – 3.2
E(6) + 9.5
ns
ns
ns
ns
Delay time, output address gpmc_a[27:1] valid to
output clock gpmc_clk first edge
B(7) – 4.5 B(7) + 3.1 B(7) – 5.5 B(7) + 13.1
-2.3 4.5 -3.3 15.3
B(7) - 1.9 B(7) + 2.3 B(7) – 2.9 B(7) + 12.3
Delay time, output clock gpmc_clk rising edge to
output address gpmc_a[27:1] invalid
Delay time, output lower byte enable and command
latch enable gpmc_be0n_cle, output upper byte
enable gpmc_be1n valid to output clock gpmc_clk
first edge
F7
td(clkH-be[x]nIV)
Delay time, output clock gpmc_clk rising edge to
output lower byte enable and command latch enable
gpmc_be0n_cle, output upper byte enable
gpmc_be1n invalid(8)
D(9) – 2.3 D(9) + 1.9 D(9) – 3.3
D(9) + 6.9
ns
F7
F7
F8
td(clkL-be[x]nIV)
td(clkL-be[x]nIV)
td(clkH-advn)
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid(10)
D(9) – 2.3 D(9) + 1.9 D(9) – 3.3
D(9) + 6.9
ns
ns
ns
Delay time, gpmc_clk falling edge to
gpmc_nbe0_cle, gpmc_nbe1 invalid(11)
D(9) – 2.3 D(9) + 1.9 D(9) – 3.3 D(9) + 11.9
G(12) – 2.3 G(12) + 4.5 G(12) – 3.3 G(12) + 9.5
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale transition
F9
td(clkH-advnIV)
Delay time, output clock gpmc_clk rising edge to
output address valid and address latch enable
gpmc_advn_ale invalid
D(9) – 2.3 D(9) + 4.5 D(9) – 3.3
D(9) + 9.5
ns
F10
F11
F14
F15
F15
F15
F17
td(clkH-oen)
td(clkH-oenIV)
td(clkH-wen)
td(clkH-do)
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen transition
H(13) – 2.3 H(13) + 3.5 H(13) – 3.3
H(13) – 2.3 H(13) + 3.5 H(13) – 3.3
I(14) – 2.3 I(14) + 4.5 I(14) – 3.3
J(15) – 2.3 J(15) + 2.7 J(15) – 3.3
H(13) + 8.5
H(13) + 8.5
I(14) + 9.5
J(15) + 7.7
J(15) + 7.7
ns
ns
ns
ns
ns
ns
ns
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_oen invalid
Delay time, output clock gpmc_clk rising edge to
output write enable gpmc_wen transition
Delay time, output clock gpmc_clk rising edge to
output data gpmc_ad[15:0] transition(8)
td(clkL-do)
Delay time, gpmc_clk falling edge to gpmc_ad[15:0] J(15) – 2.3 J(15) + 2.7 J(15) – 3.3
data bus transition(10)
td(clkL-do)
Delay time, gpmc_clk falling edge to gpmc_ad[15:0] J(15) – 2.3 J(15) + 2.7 J(15) – 3.3 J(15) + 12.7
data bus transition(11)
td(clkH-be[x]n)
Delay time, output clock gpmc_clk rising edge to
output lower byte enable and command latch enable
gpmc_be0n_cle transition(8)
J(15) – 2.3 J(15) + 1.9 J(15) – 3.3
J(15) + 6.9
F17
F17
td(clkL-be[x]n)
td(clkL-be[x]n)
Delay time, gpmc_clk falling edge to
J(15) – 2.3 J(15) + 1.9 J(15) – 3.3
J(15) + 6.9
ns
ns
gpmc_nbe0_cle, gpmc_nbe1 transition(10)
Delay time, gpmc_clk falling edge to
J(15) – 2.3 J(15) + 1.9 J(15) – 3.3 J(15) + 11.9
gpmc_nbe0_cle, gpmc_nbe1 transition(11)
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
151
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-40. GPMC and NOR Flash Switching Characteristics—Synchronous Mode (continued)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
F18
tw(csnV)
Pulse duration, output chip select
gpmc_csn[x](4) low
Read
Write
Read
Write
A(16)
A(16)
C(17)
C(17)
A(16)
A(16)
C(17)
C(17)
ns
ns
ns
ns
F19
F20
tw(be[x]nV)
Pulse duration, output lower byte enable
and command latch enable
gpmc_be0n_cle, output upper byte enable
gpmc_be1n low
tw(advnV)
Pulse duration, output address valid and
address latch enable gpmc_advn_ale low
Read
Write
K(18)
K(18)
K(18)
K(18)
ns
ns
(1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(2) P = gpmc_clk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
(5) For csn falling edge (CS activated):
–
Case GpmcFCLKDivider = 0:
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(19) if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(19) if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(19) if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(6) For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
(7) B = ClkActivationTime × GPMC_FCLK(19)
(8) First transfer only for CLK DIV 1 mode.
(9) For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
(10) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(11) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
(12) For ADV falling edge (ADV activated):
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
–
Case GpmcFCLKDivider = 0:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
–
Case GpmcFCLKDivider = 0:
152
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19)
–
–
Case GpmcFCLKDivider = 1:
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) otherwise
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(19) if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(19) if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
(13) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19) if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
–
Case GpmcFCLKDivider = 0:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(19) if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(19) if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
(14) For WE falling edge (WE activated):
–
Case GpmcFCLKDivider = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(19)
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(19) if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
–
Case GpmcFCLKDivider = 0:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK (19)
–
Case GpmcFCLKDivider = 1:
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(19) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(19) if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(19) if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(15) J = GPMC_FCLK(19)
(16) For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
With n being the page burst access number.
(17) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
With n being the page burst access number.
(18) For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(19)
(19) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
153
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csn[x](A)
F4
gpmc_a[10:1]
Valid Address
F19
F6
F7
gpmc_be0n_cle
gpmc_be1n
F19
F6
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
gpmc_wait[x](B)
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-33. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
154
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
F1
F0
F1
gpmc_clk
gpmc_csn[x](A)
gpmc_a[10:1]
gpmc_be0n_cle
gpmc_be1n
F2
F3
F4
F6
Valid Address
F7
F7
F6
F8
F8
F9
gpmc_advn_ale
gpmc_oen
F10
F11
F13
F13
F12
D 0
F22
F12
D 3
gpmc_ad[15:0]
gpmc_wait[x](B)
D 1
D 2
F21
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-34. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
155
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
gpmc_csn[x](A)
F4
gpmc_a[10:1]
Valid Address
F17
F17
F6
F17
F17
F17
F17
gpmc_be0n_cle
gpmc_be1n
gpmc_advn_ale
gpmc_wen
F6
F8
F8
F9
F14
F14
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
gpmc_wait[x](B)
D 0
D 3
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-35. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)
156
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
F1
F0
F1
gpmc_clk
F2
F3
gpmc_csn[x](A)
gpmc_be0n_cle
gpmc_be1n
F6
F6
F4
F7
Valid
F7
Valid
gpmc_a[27:17]
Address (MSB)
F5
F12
F13
F4
F12
gpmc_ad[15:0]
gpmc_advn_ale
gpmc_oen
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
F10
F11
gpmc_wait[x](B)
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-36. GPMC and Multiplexed NOR Flash—Synchronous Burst Read
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
157
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csn[x](A)
F4
gpmc_a[27:17]
Address (MSB)
F17
F17
F6
F17
F17
F17
F17
gpmc_be1n
F6
gpmc_be0n_cle
F8
F8
F20
F9
gpmc_advn_ale
F14
F14
gpmc_wen
F15
D 1
F15
D 2
F15
gpmc_ad[15:0]
Address (LSB)
D 0
D 3
F22
F21
gpmc_wait[x](B)
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
B. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-37. GPMC and Multiplexed NOR Flash—Synchronous Burst Write
158
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.1.2 GPMC and NOR Flash—Asynchronous Mode
Table 5-42 and Table 5-43 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-38 through Figure 5-43).
Table 5-41. GPMC and NOR Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
0.3
0.3
1.8
1.8
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-42. GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
FI1 Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
FI2 Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
4
6.5
6.5
6.5
4
6.5
6.5
6.5
ns
ns
ns
ns
FI3 Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
FI4 Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
FI5 Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
FI6 Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle,
output upper-byte enable gpmc_be1n generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
ns
ps
FI7 Delay time, output enable gpmc_oen generation from internal functional clock
GPMC_FCLK(3)
FI8 Delay time, output write enable gpmc_wen generation from internal functional
clock GPMC_FCLK(3)
FI9 Skew, internal functional clock GPMC_FCLK(3)
6.5
6.5
100
100
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
159
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-43. GPMC and NOR Flash Timing Requirements—Asynchronous Mode
NO.
OPP100
MIN
OPP50
MIN
UNIT
MAX
H(4)
P(5)
MAX
H(4)
P(5)
H(4)
FA5(1)
FA20(2) tacc1-pgmode(d)
FA21(3) tacc2-pgmode(d)
tacc(d)
Data access time
ns
ns
ns
Page mode successive data access time
Page mode first data access time
H(4)
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(5) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 5-44. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
2
MAX
2
tR(d)
tF(d)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
ns
ns
2
2
Pulse duration, output lower-byte
enable and command latch enable
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
Read
Write
N(1)
N(1)
FA0
FA1
FA3
tw(be[x]nV)
ns
ns
ns
N(1)
N(1)
Read
Write
Read
A(3)
A(3)
B(4) + 2.0
A(3)
A(3)
B(4) + 2.0
Pulse duration, output chip select
gpmc_csn[x](2) low
tw(csnV)
Delay time, output chip select
gpmc_csn[x](2) valid to output address
valid and address latch enable
gpmc_advn_ale invalid
B(4) – 0.2
B(4) – 0.2
B(4) – 0.2
B(4) – 0.2
td(csnV-advnIV)
Write
B(4) + 2.0
B(4) + 2.0
Delay time, output chip select gpmc_csn[x](2)
valid to output enable gpmc_oen invalid (Single
read)
FA4
FA9
td(csnV-oenIV)
C(5) – 0.2
J(6) – 0.2
C(5) + 2.0
J(6) + 2.0
C(5) – 0.2
J(6) – 0.2
C(5) + 2.0
J(6) + 2.0
ns
ns
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_csn[x](2) valid
td(aV-csnV)
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle, output
upper-byte enable gpmc_be1n valid to output
chip select gpmc_csn[x](2) valid
Delay time, output chip select gpmc_csn[x](2)
valid to output address valid and address latch
enable gpmc_advn_ale valid
FA10 td(be[x]nV-csnV)
J(6) – 0.2
J(6) + 2.0
J(6) – 0.2
K(7) – 0.2
J(6) + 2.0
ns
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
K(7) – 0.2
L(8) – 0.2
G(9)
K(7) + 2.0
L(8) + 2.0
K(7) + 2.0
L(8) + 2.0
ns
ns
ns
Delay time, output chip select gpmc_csn[x](2)
valid to output enable gpmc_oen valid
L
(8) – 0.2
G(9)
Pulse durationm output address gpmc_a[26:1]
invalid between 2 successive read and write
accesses
Delay time, output chip select gpmc_csn[x](2)
valid to output enable gpmc_oen invalid (Burst
read)
FA18 td(csnV-oenIV)
I(10) – 0.2
D(11)
E(12) – 0.2 E(12) + 2.0 E(12) – 0.2 E(12) + 2.0
I(10) + 2.0
I(10) – 0.2
I(10) + 2.0
ns
Pulse duration, output address gpmc_a[27:1]
valid — 2nd, 3rd, and 4th accesses
Delay time, output chip select gpmc_csn[x](2)
valid to output write enable gpmc_wen valid
FA20 tw(aV)
D(11)
ns
ns
FA25 td(csnV-wenV)
160
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-44. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued)
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Delay time, output chip select gpmc_csn[x](2)
valid to output write enable gpmc_wen invalid
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
F(13) – 0.2 F(13) + 2.0 F(13) – 0.2 F(13) + 2.0
ns
ns
ns
ns
Delay time, output write enable gpmc_ wen
valid to output data gpmc_ad[15:0] valid
2.8
J(6) + 2.8
2.8
5
J(6) + 2.8
2.8
Delay time, output data gpmc_ad[15:0] valid to
output chip select gpmc_csn[x](2) valid
J(6) – 0.2
J(6) – 0.2
Delay time, output enable gpmc_oen valid to
output address gpmc_ad[15:0] phase end
(1) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(2) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
(3) For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(4) For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK(14)
(5) C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(6) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(7) K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(8) L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(9) G = Cycle2CycleDelay × GPMC_FCLK(14)
(10) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK(14)
(11) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(12) E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(13) F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
161
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
GPMC_FCLK(A)
gpmc_clk
FA5(B)
FA1
gpmc_csn[x](C)
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_be0n_cle
Valid
FA0
gpmc_be1n
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen
Data IN 0
Data IN 0
gpmc_ad[15:0]
gpmc_wait[x](C)
A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-38. GPMC and NOR Flash—Asynchronous Read—Single Word
162
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
GPMC_FCLK(A)
gpmc_clk
FA5(B)
FA5(B)
FA1
FA1
gpmc_csn[x](C)
gpmc_a[10:1]
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
FA10
FA10
Valid
FA0
gpmc_be0n_cle
gpmc_be1n
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen
Data Upper
gpmc_ad[15:0]
gpmc_wait[x](C)
A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-39. GPMC and NOR Flash—Asynchronous Read—32-Bit
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
163
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
GPMC_FCLK(A)
gpmc_clk
FA20(C)
FA20(C)
FA20(C)
FA21(B)
FA1
gpmc_csn[x](D)
FA9
Add0
Add1
Add2
Add3
Add4
gpmc_a[10:1]
FA0
FA10
FA10
gpmc_be0n_cle
FA0
gpmc_be1n
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen
D3
D0
D1
D2
D3
gpmc_ad[15:0]
gpmc_wait[x](D)
A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
D. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-40. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit
164
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x](A)
gpmc_a[10:1]
FA9
Valid Address
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_wait[x](A)
FA29
Data OUT
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-41. GPMC and NOR Flash—Asynchronous Write—Single Word
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Specifications
165
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
GPMC_FCLK(A)
gpmc_clk
FA1
FA5(B)
gpmc_csn[x](C)
FA9
Address (MSB)
FA0
gpmc_a[27:17]
FA10
gpmc_be0n_cle
Valid
FA0
FA10
gpmc_be1n
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen
FA29
FA37
Data IN
Data IN
Address (LSB)
gpmc_ad[15:0]
gpmc_wait[x](C)
A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-42. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word
166
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
gpmc_fclk
gpmc_clk
FA1
gpmc_csn[x](A)
gpmc_a[27:17]
FA9
Address (MSB)
FA0
FA10
FA10
gpmc_be0n_cle
gpmc_be1n
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_wait[x](A)
FA29
FA28
Valid Address (LSB)
Data OUT
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-43. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
167
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.1.3 GPMC and NAND Flash—Asynchronous Mode
Table 5-46 and Table 5-47 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-44 through Figure 5-47).
Table 5-45. GPMC and NAND Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
0.3
0.3
1.8
1.8
ns
ns
Output Condition
CLOAD
Output load capacitance
3
30
pF
Table 5-46. GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode(1)(2)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
GNFI1 Delay time, output data gpmc_ad[15:0] generation from internal
functional clock GPMC_FCLK(3)
6.5
6.5
ns
GNFI2 Delay time, input data gpmc_ad[15:0] capture from internal functional
clock GPMC_FCLK(3)
4.0
6.5
6.5
4.0
6.5
6.5
ns
ns
ns
GNFI3 Delay time, output chip select gpmc_csn[x] generation from internal
functional clock GPMC_FCLK(3)
GNFI4 Delay time, output address valid and address latch enable
gpmc_advn_ale generation from internal functional clock
GPMC_FCLK(3)
GNFI5 Delay time, output lower-byte enable and command latch enable
gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
ns
GNFI6 Delay time, output enable gpmc_oen generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
6.5
6.5
ns
ns
ps
GNFI7 Delay time, output write enable gpmc_wen generation from internal
functional clock GPMC_FCLK(3)
GNFI8 Skew, functional clock GPMC_FCLK(3)
100
100
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Table 5-47. GPMC and NAND Flash Timing Requirements—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
J(2)
MAX
J(2)
GNF12(1) tacc(d)
Access time, input data gpmc_ad[15:0]
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
168
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-48. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
tR(d)
tF(d)
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
2
2
2
2
ns
ns
ns
GNF0 tw(wenV)
Pulse duration, output write enable gpmc_wen
valid
A(1)
A(1)
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
Delay time, output chip select gpmc_csn[x](2)
valid to output write enable gpmc_wen valid
B(3) - 0.2
B(3) + 2.0
B(3) - 0.2
B(3) + 2.0
ns
ns
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle high to
output write enable gpmc_wen valid
C(4) - 0.2 C(4) + 2.0
D(5) - 0.2 D(5) + 2.8
C(4) - 0.2 C(4) + 2.0
D(5) - 0.2 D(5) + 2.0
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
ns
ns
ns
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E(6) - 0.2
F(7) - 0.2
E(6) + 2.8
F(7) + 2.0
E(6) - 0.2
F(7) - 0.2
E(6) + 2.0
F(7) + 2.0
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable and command
latch enable gpmc_be0n_cle invalid
GNF6 tw(wenIV-csnIV)
GNF7 tw(aleH-wenV)
GNF8 tw(wenIV-aleIV)
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x](2)
invalid
G(8) - 0.2 G(8) + 2.0
C(4) - 0.2 C(4) + 2.0
G(8) - 0.2 G(8) + 2.0
C(4) - 0.2 C(4) + 2.0
ns
ns
ns
Delay time, output address valid and address
latch enable gpmc_advn_ale high to output write
enable gpmc_wen valid
Delay time, output write enable gpmc_wen
invalid to output address valid and address latch
enable gpmc_advn_ale invalid
F(7) - 0.2
F(7) + 2.0
F(7) - 0.2
F(7) + 2.0
GNF9 tc(wen)
Cycle time, write
Delay time, output chip select gpmc_csn[x](2)
valid to output enable gpmc_oen valid
H(9)
I(10) + 2.0
H(9)
ns
ns
GNF10 td(csnV-oenV)
I(10) - 0.2
I(10) - 0.2 I(10) + 2.0
GNF13 tw(oenV)
GNF14 tc(oen)
Pulse duration, output enable gpmc_oen valid
Cycle time, read
K(11)
K(11)
ns
ns
ns
L(12)
L(12)
GNF15 tw(oenIV-csnIV)
Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x](2) invalid
M(13) - 0.2 M(13) + 2.0 M(13) - 0.2 M(13) + 2.0
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(2) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
(3) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)
(5) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(6) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(7) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(8) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(9) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(10) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(12) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(13) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
169
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
GPMC_FCLK
GNF1
GNF6
GNF5
gpmc_csn[x](A)
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF2
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Command
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
Figure 5-44. GPMC and NAND Flash—Command Latch Cycle
GPMC_FCLK
gpmc_csn[x](A)
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF1
GNF7
GNF6
GNF8
GNF9
GNF0
gpmc_wen
GNF3
GNF4
Address
gpmc_ad[15:0]
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
Figure 5-45. GPMC and NAND Flash—Address Latch Cycle
170
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
GPMC_FCLK(A)
GNF12(B)
GNF10
GNF15
gpmc_csn[x](C)
gpmc_be0n_cle
gpmc_advn_ale
GNF14
GNF13
gpmc_oen
gpmc_ad[15:0]
DATA
gpmc_wait[x](C)
A. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
B. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of
GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be
internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
C. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6. In gpmc_wait[x], x is equal to 0 or 1.
Figure 5-46. GPMC and NAND Flash—Data Read Cycle
GPMC_FCLK
GNF1
GNF6
gpmc_csn[x](A)
gpmc_be0n_cle
gpmc_advn_ale
gpmc_oen
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
A. In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, 5, or 6.
Figure 5-47. GPMC and NAND Flash—Data Write Cycle
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
171
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2 Memory Interface
The device has a dedicated interface to LPDDR2, DDR3, and DDR3L SDRAM. It supports JEDEC
standard compliant LPDDR2, DDR3, and DDR3L SDRAM devices with a 16- or 32-bit data path to
external SDRAM memory.
For more details on the LPDDR2, DDR3, and DDR3L memory interface, see the EMIF section of the
AM437x Sitara Processors Technical Reference Manual.
5.13.8.2.1 DDR3 and DDR3L Routing Guidelines
This section provides the timing specification for the DDR3 and DDR3L interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 or DDR3L
memory system without the need for a complex timing closure process. For more information regarding
the guidelines, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This
application report provides generic guidelines and approach. All the specifications provided in the data
manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 or
DDR3L interface operation.
NOTE
All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise
noted.
5.13.8.2.1.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-49 and
Figure 5-48.
Table 5-49. Switching Characteristics for DDR3 Memory Interface
NO.
PARAMETER
MIN
MAX
UNIT
tc(DDR_CK)
tc(DDR_CKn)
1
Cycle time, DDR_CK and DDR_CKn
2.5
3.3(1)
ns
(1) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory
devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.
1
DDR_CK
DDR_CKn
Figure 5-48. DDR3 Memory Interface Clock Timing
172
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.2 DDR3 Device Combinations
Because there are several possible combinations of device counts and single-side or dual-side mounting,
Table 5-50 summarizes the supported device configurations.
Table 5-50. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
2
4
16
8
N
16
16
32
32
Y(1)
Y(1)
Y(1)
16
8
(1) DDR3 devices are mirrored when half of the devices are placed on the top of the board and the other half are placed on the bottom of
the board.
5.13.8.2.1.3 DDR3 Interface
5.13.8.2.1.3.1 DDR3 Interface Schematic
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used.
Figure 5-49 shows the schematic connections for 16-bit interface using one x16 DDR3 device. Figure 5-50
shows the schematic connections for 16-bit interface without using VTT termination for the ADDR_CTRL
net class signals. Figure 5-51 shows the schematic connections for 16-bit interface using two x8 DDR3
devices.
Figure 5-52 shows the schematic connections for 32-bit interface using two x16 DDR3 device and
Figure 5-53 shows the schematic connections for 32-bit interface using four x8 DDR3 devices.
When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off
the DDR_DQS[x] pins to the VDDS_DDR supply via a 1-kΩ resistor and pulling the DDR_DQSn[x] pins to
ground via a 1k-Ω resistor. This must be done for each byte not used. Although these signals have
internal pullup and pulldown, external pullup and pulldown provide additional protection against external
electrical noise causing activity on the signals. Also, include the 49.9-Ω pulldown for DDR_VTP. The
VDDS_DDR and DDR_VREF power supply terminals need to be connected to their respective power
supplies even if the DDR3 interface is not being used. All other DDR3 interface pins can be left
unconnected. The supported modes for use of the DDR3 EMIF are 32 bits wide, 16 bits wide, or not used.
The device can only source one load connected to the DQS[x] and DQ[x] net class signals and up to four
loads connected to the CK and ADDR_CTRL net class signals. For more information related to net
classes, see Section 5.13.8.2.1.3.9.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
173
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
16-Bit DDR3
Interface
16-Bit DDR3
Device
DDR_D15
8
DQU7
DDR_D8
DQU0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSUn
DDR_D7
8
DQL7
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSLn
0.1 µF
Zo
Zo
DDR_CK
CK
VDDS_DDR
DDR_CKn
CKn
DDR_ODT0
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CSn
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
16
A0
DDR_A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CASn
RASn
WEn
DDR_CKE0
DDR_RESETn
CKE
DDR_VREF
RESETn
ZQ
ZQ
VREFDQ
VREFCA
DDR_VREF
DDR_VTP
0.1 µF
0.1 µF
0.1 µF
49.9 Ω
( 1%, 20 mW)
Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
Figure 5-49. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device With VTT Termination
174
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
16-Bit DDR3
Interface
16-Bit DDR3
Device
DDR_D15
DQU7
8
DDR_D8
DQU0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSUn
DDR_D7
DQL7
8
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSLn
DDR_CK
CK
DDR_CKn
CKn
DDR_ODT0
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CSn
BA0
BA1
BA2
DDR_A0
A0
16
DDR_A15
A15
VDDS_DDR(A)
DDR_CASn
DDR_RASn
DDR_WEn
CASn
RASn
WEn
DDR_CKE0
DDR_RESETn
CKE
RESETn
ZQ
1 K Ω 1%
0.1 µF
0.1 µF
ZQ
VREFDQ
VREFCA
DDR_VREF
DDR_VREF
0.1 µF
0.1 µF
1 K Ω 1%
DDR_VTP
49.9 Ω
( 1%, 20 mW)
ZQ
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
A. VDDS_DDR is the power supply for the DDR3 memories and the DDR3 interface.
Figure 5-50. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device Without VTT Termination
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
175
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
16-Bit DDR3
Interface
8-Bit DDR3
Devices
DDR_D15
8
DQ7
DQ0
DDR_D8
DDR_DQM1
DM/TDQS
TDQSn
DQS
NC
DDR_DQS1
DDR_DQSn1
DQSn
DDR_D7
8
DQ7
DQ0
DDR_D0
DDR_DQM0
DM/TDQS
TDQSn
DQS
NC
DDR_DQS0
DDR_DQSn0
DQSn
0.1 µF
Zo
Zo
DDR_CK
CK
CK
VDDS_DDR
DDR_CKn
CKn
CKn
DDR_ODT0
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
ODT
CSn
BA0
BA1
BA2
CSn
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
16
A0
A0
DDR_A15
A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CASn
RASn
WEn
CASn
RASn
WEn
DDR_CKE0
DDR_RESETn
CKE
CKE
DDR_VREF
RESETn
ZQ
RESETn
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
DDR_VREF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DDR_VTP
49.9 Ω
( 1%, 20 mW)
Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
Figure 5-51. 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices With VTT Termination
176
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
32-bit DDR3 EMIF
DDR_CKE1
DDR_ODT1
DDR_CSn1
NC
NC
NC
16-Bit DDR3
Devices
DDR_D31
DQU7
DQU0
8
DDR_D24
DDR_DQM3
DDR_DQS3
DDR_DQSn3
DMU
DQSU
DQSUn
DDR_D23
DQL7
8
DDR_D16
DQL0
DDR_DQM2
DDR_DQS2
DDR_DQSn2
DML
DQSL
DQSLn
DDR_D15
DQU7
DQU0
8
DDR_D8
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DMU
DQSU
DQSUn
DDR_D7
DQL7
8
DDR_D0
DQL0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DML
DQSL
DQSLn
0.1 µF
Zo
Zo
DDR_CLK
CK
CK
VDDS_DDR
DDR_CLKn
CKn
CKn
DDR_ODT0
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
ODT
CSn
BA0
BA1
BA2
CSn
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
A0
A0
16
DDR_A15
A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CASn
RASn
WEn
CASn
RASn
WEn
DDR_CKE0
DDR_RESETn
CKE
CKE
DDR_VREF
RSTn
ZQ
RSTn
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
DDR_VREF
DDR_VTP
0.1 µF
0.1 µF
0.1 µF
49.9 Ω ( 1% 20mW)
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
Copyright © 2016, Texas Instruments Incorporated
Figure 5-52. 32-Bit DDR3 Interface Using Two 16-Bit DDR3 Devices With VTT Termination
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
177
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
32-bit DDR3 EMIF
DDR_CKE1
DDR_ODT1
DDR_CSn1
NC
NC
NC
8-Bit DDR3
Devices
8-Bit DDR3
Devices
DDR_D31
DQ7
DQ0
8
DDR_D24
DDR_DQM3
DM/TQS
TDQSn
DQS
NC
DDR_DQS3
DDR_DQSn3
DQSn
DDR_D23
DQ7
DQ0
8
DDR_D16
DDR_DQM2
DM/TQS
TDQSn
DQS
NC
DDR_DQS2
DDR_DQSn2
DQSn
DDR_D15
DQ7
DQ0
8
DDR_D8
DDR_DQM1
DM/TQS
TDQSn
DQS
NC
DDR_DQS1
DDR_DQSn1
DQSn
DDR_D7
DQ7
DQ0
8
DDR_D0
DDR_DQM0
DM/TQS
TDQSn
DQS
NC
DDR_DQS0
DDR_DQSn0
DQSn
0.1 µF
Zo
Zo
DDR_CLK
CK
CK
CK
CK
VDDS_DDR
DDR_CLKn
CKn
CKn
CKn
CKn
DDR_ODT0
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
ODT
CSn
BA0
BA1
BA2
ODT
ODT
ODT
CSn
BA0
BA1
BA2
CSn
BA0
BA1
BA2
CSn
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR_A0
A0
A0
A0
A0
16
DDR_A15
A15
A15
A15
A15
DDR_CASn
DDR_RASn
DDR_WEn
CASn
RASn
WEn
CASn
RASn
WEn
CASn
RASn
WEn
CASn
RASn
WEn
DDR_CKE0
DDR_RESETn
CKE
CKE
CKE
CKE
RSTn
ZQ
RSTn
RSTn
ZQ
RSTn
DDR_VREF
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
DDR_VREF
DDR_VTP
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
49.9 Ω ( 1% 20mW)
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
Copyright © 2016, Texas Instruments Incorporated
Figure 5-53. 32-Bit DDR3 Interface Using Four 8-Bit DDR3 Devices With VTT Termination
178
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.3.2 Compatible JEDEC DDR3 Devices
Table 5-51 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Table 5-51. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
JEDEC DDR3 device speed grade
CONDITION
tC(DDR_CK) and
tC(DDR_CKn) = 2.5ns
MIN
MAX
UNIT
1
DDR3-1600
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(1)
x8
1
x32
4
Devices
(1) For valid DDR3 device configurations and device counts, see Section 5.13.8.2.1.3.1, Figure 5-49, and Figure 5-51.
5.13.8.2.1.3.3 DDR3 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-52.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-52. Minimum PCB Stackup(1)
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Split Power Plane
Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
Table 5-53. PCB Stackup Specifications(1)
NO.
1
PARAMETER
MIN
4
TYP
MAX
UNIT
PCB routing and plane layers
Signal routing layers
2
2
3
Full ground reference layers under DDR3 routing region(2)
Full VDDS_DDR power reference layers under the DDR3 routing region(2)
Number of reference plane cuts allowed within DDR3 routing region(3)
Number of layers between DDR3 routing layer and reference plane(4)
PCB routing feature size
1
4
1
5
0
0
6
7
4
4
mils
mils
mils
mils
Ω
8
PCB trace width, w
PCB BGA escape via pad size(5)
9
18
10
50
Zo
20
10 PCB BGA escape via hole size
13 Single-ended impedance, Zo(6)
14 Impedance control(7)(8)
75
Zo-5
Zo+5
Ω
(1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
(2) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(6) Zo is the nominal singled-ended impedance selected for the PCB.
(7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(8) Tighter impedance control is required to ensure flight time skew is minimal.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
179
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.1.3.4 DDR3 Placement
Figure 5-54 shows the required placement for the device as well as the DDR3 devices. The dimensions
for this figure are defined in Table 5-54. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space.
X1
X2
X2
X2
DDR3
Controller
Y
Figure 5-54. Placement Specifications
Table 5-54. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1000
600
UNIT
mils
mils
mils
w
X1(2)(3)(4)
X2(2)(3)
Y Offset(2)(3)(4)
2
3
1500
4
Clearance from non-DDR3 signal to DDR3 keepout region(5)(6)
4
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) For dimension definitions, see Figure 5-54.
(3) Measurements from center of device to center of DDR3 device.
(4) Minimizing X1 and Y improves timing margins.
(5) w is defined as the signal trace width.
(6) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
180
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.3.5 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 5-55. This region should encompass all DDR3
circuitry and the region size varies with component placement and DDR3 routing. Additional clearances
required for the keepout region are shown in Table 5-54. Non-DDR3 signals should not be routed on the
same signal layer as DDR3 signals within the DDR3 keepout region. Non-DDR3 signals may be routed in
the region provided they are routed on layers separated from DDR3 signal layers by a ground layer. No
breaks should be allowed in the reference ground or VDDS_DDR power plane in this region. In addition,
the VDDS_DDR power plane should cover the entire keepout region.
DDR3 Controller
DDR3 Keepout Region
Encompasses Entire DDR3 Routing Area
Figure 5-55. DDR3 Keepout Region
5.13.8.2.1.3.6 DDR3 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 5-55 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 interface and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 5-55. Bulk Bypass Capacitors(1)
NO.
1
PARAMETER
VDDS_DDR bulk bypass capacitor count
MIN
2
MAX
UNIT
Devices
μF
2
VDDS_DDR bulk bypass total capacitance
DDR3#1 bulk bypass capacitor count
DDR3#1 bulk bypass total capacitance
DDR3#2 bulk bypass capacitor count(2)
DDR3#2 bulk bypass total capacitance(2)
DDR3#3 bulk bypass capacitor count(3)
DDR3#3 bulk bypass total capacitance(3)
DDR3#4bulk bypass capacitor count(3)
20
2
3
Devices
μF
4
20
2
5
Devices
μF
6
20
2
7
Devices
μF
8
20
2
9
Devices
μF
10 DDR3#4 bulk bypass total capacitance(3)
20
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
(2) Only used when two DDR3 devices are used.
(3) Only used when four DDR3 devices are used.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
181
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.1.3.7 DDR3 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, device DDR3 power,
and device DDR3 ground connections. Table 5-56 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the power terminals being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 5-56.
Table 5-56. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
UNIT
0201
0402 10 mils
2
Distance, HS bypass capacitor to VDDS_DDR and VSS terminal being
bypassed(2)(3)(4)
400
mils
3
4
5
6
7
8
9
VDDS_DDR HS bypass capacitor count
20
1
Devices
μF
VDDS_DDR HS bypass capacitor total capacitance
Trace length from VDDS_DDR and VSS terminal to connection via(2)
Distance, HS bypass capacitor to DDR3 device being bypassed(5)
DDR3 device HS bypass capacitor count(6)
DDR3 device HS bypass capacitor total capacitance(6)
Number of connection vias for each HS bypass capacitor(7)(8)
35
70
mils
150
mils
12
0.85
2
Devices
μF
Vias
mils
10 Trace length from bypass capacitor connect to connection via(2)(8)
35
35
100
60
11 Number of connection vias for each DDR3 device power and ground
terminal(9)
1
Vias
12 Trace length from DDR3 device power and ground terminal to connection
via(2)(7)
mils
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer and shorter is better.
(3) Measured from the nearest VDDS_DDR and ground terminal to the center of the capacitor package.
(4) Three of these capacitors should be underneath the device, between the cluster of VDDS_DDR and ground terminals, between the
DDR3 interfaces on the package.
(5) Measured from the DDR3 device power and ground terminal to the center of the capacitor package.
(6) Per DDR3 device.
(7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(8) An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be used for
the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
(9) Up to two pairs of DDR3 power and ground terminals may share a via.
5.13.8.2.1.3.8 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
182
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.3.9 DDR3 Net Classes
Table 5-57 lists the clock net classes for the DDR3 interface. Table 5-58 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 5-57. Clock Net Class Definitions
CLOCK NET CLASS PIN NAMES
CK
DDR_CK and DDR_CKn
DQS0
DQS1
DQS2
DQS3
DDR_DQS0 and DDR_DQSn0
DDR_DQS1 and DDR_DQSn1
DDR_DQS2 and DDR_DQSn2
DDR_DQS3 and DDR_DQSn3
Table 5-58. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[15:0], DDR_CSn0, DDR_CSn1, DDR_CASn,
DDR_RASn, DDR_WEn, DDR_CKE0, DDR_CKE1, DDR_ODT0,
DDR_ODT1
DQ0
DQ1
DQ2
DQ3
DQS0
DQS1
DQS2
DQS3
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
DDR_D[23:16], DDR_DQM2
DDR_D[31:24], DDR_DQM3
5.13.8.2.1.3.10 DDR3 Signal Termination
Signal terminations are required for the CK and ADDR_CTRL net class signals. On-device terminations
(ODTs) are required on the DQS[x] and DQ[x] net class signals. Detailed termination specifications are
covered in the routing rules in the following sections.
Figure 5-50 provides an example DDR3 schematic with one 16-bit DDR3 memory device that does not
have VTT termination on the address and control signals. A typical DDR3 point-to-point topology may
provide acceptable signal integrity without VTT termination. System performance should be verified by
performing signal integrity analysis using specific PCB design details before implementing this topology.
5.13.8.2.1.3.11 DDR3 DDR_VREF Routing
DDR_VREF is used as a reference by the input buffers of the DDR3 memories as well as the device.
DDR_VREF is intended to be half the DDR3 power supply voltage and is typically generated with a
voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide
trace with 0.1 µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to
accommodate routing congestion.
5.13.8.2.1.3.12 DDR3 VTT
Like DDR_VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike
DDR_VREF, VTT is expected to source and sink current, specifically the termination current for the
ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should
be routed as a power subplane. VTT should be bypassed near the terminator resistors.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
183
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 5-59.
5.13.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
Two DDR3 devices are supported on the DDR3 interface consisting of two x8 DDR3 devices arranged as
one 16-bit bank or two x16 DDR3 devices arranged as one 32-bit bank. These two devices may be
mounted on one side of the PCB, or may be mirrored in a pair to save board space at a cost of increased
routing complexity and parts on the backside of the PCB.
5.13.8.2.1.4.2 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 5-56 shows the topology of the CK net classes and Figure 5-57 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
Device
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-56. CK Topology for Two DDR3 Devices
DDR3 Address and Control Input Buffers
Address and Control
Terminator
Rtt
Device
Address and Control
Output Buffer
A1
A2
A3
AT
Vtt
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-57. ADDR_CTRL Topology for Two DDR3 Devices
184
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.4.3 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 5-58 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 5-59
shows the corresponding ADDR_CTRL routing.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-58. CK Routing for Two Single-Side DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-59. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
185
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 5-60 and Figure 5-61 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-60. CK Routing for Two Mirrored DDR3 Devices
Rtt
A2
A3
AT
Vtt
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-61. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
186
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.4.4 Using Four 8-Bit DDR3 Devices
Two DDR3 devices are supported on the DDR3 interface consisting of four x8 DDR3 devices arranged as
one 32-bit bank. These four devices may be mounted on one side of the PCB, or may be mirrored in pairs
to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
5.13.8.2.1.4.5 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 5-62 shows the topology of the CK net classes and Figure 5-63 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
–
–
+
+
+
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
Cac
Device
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-62. CK Topology for Four DDR3 Devices
DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Device
Address and Control
Output Buffer
A1
A2
A3
A4
A3
AT
Vtt
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-63. ADDR_CTRL Topology for Four DDR3 Devices
5.13.8.2.1.4.6 CK and ADDR_CTRL Routing, Four DDR3 Devices
Figure 5-64 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 5-65
shows the corresponding ADDR_CTRL routing.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
187
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-64. CK Routing for Four Single-Side DDR3 Devices
Rtt
A2
A3
A4
A3
AT
Vtt
=
NOTE: For routing definitions, see Table 5-59, CK and ADDR_CTRL Routing Specification.
Figure 5-65. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
188
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
To save PCB space, the four DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 5-66 and Figure 5-67 show the routing for CK and ADDR_CTRL,
respectively, for four DDR3 devices mirrored in a single-pair configuration.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
Figure 5-66. CK Routing for Four Mirrored DDR3 Devices
Rtt
A2
A3
A4
A3
AT
Vtt
=
Figure 5-67. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
189
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.1.4.7 One 16-Bit DDR3 Device
One DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged as
one 16-bit bank.
5.13.8.2.1.4.8 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 5-68 shows the topology of the CK net classes and Figure 5-69 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR3 Differential CK Input Buffer
–
+
Clock Parallel
Terminator
VDDS_DDR
Rcp
A1
A1
A2
A2
AT
AT
Cac
Device
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
Figure 5-68. CK Topology for One DDR3 Device
DDR3 Address and Control Input Buffers
Address and Control
Terminator
Rtt
Device
Address and Control
Output Buffer
A1
A2
AT
Vtt
Figure 5-69. ADDR_CTRL Topology for One DDR3 Device
190
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.4.9 CK and ADDR_CTRL Routing, One DDR3 Device
Figure 5-70 shows the CK routing for one DDR3 device. Figure 5-71 shows the corresponding
ADDR_CTRL routing.
VDDS_DDR
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
Figure 5-70. CK Routing for One DDR3 Device
Rtt
A2
AT
Vtt
=
Figure 5-71. ADDR_CTRL Routing for One DDR3 Device
5.13.8.2.1.5 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
5.13.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point singled ended. Figure 5-72
and Figure 5-73 show these topologies.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
191
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Device
DQS[x]
DDR3
DQS[x]+
DQS[x]-
DQS[x]
IO Buffer
IO Buffer
Routed Differentially
x = 0, 1, 2, 3
Figure 5-72. DQS[x] Topology
Device
DQ[x]
DDR3
DQ[x]
DQ[x]
IO Buffer
IO Buffer
x = 0, 1, 2, 3
Figure 5-73. DQ[x] Topology
5.13.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
Figure 5-74 and Figure 5-75 show the DQS[x] and DQ[x] routing.
DQS[x]
DQS[x]+
DQS[x]-
Routed Differentially
x = 0, 1, 2, 3
Figure 5-74. DQS[x] Routing With Any Number of Allowed DDR3 Devices
DQ[x]
x = 0, 1, 2, 3
Figure 5-75. DQ[x] Routing With Any Number of Allowed DDR3 Devices
192
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.1.6 Routing Specification
5.13.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the device and the DDR3 memories, the maximum possible
Manhattan distance can be determined given the placement. Figure 5-76 shows this distance for two
loads. It is from this distance that the specifications on the lengths of the transmission lines for the
address bus are determined. CACLM is determined similarly for other address bus configurations; that is,
it is based on the longest net of the CK and ADDR_CTRL net class. For CK and ADDR_CTRL routing,
these specifications are contained in Table 5-59.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
193
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
Vtt
=
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
A8(A)
A8(A)
Rtt
A2
A3
A4
A3
AT
Vtt
=
A. It is very likely that the longest CK and ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the
DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net
class that satisfies this criteria and use as the baseline for CK and ADDR_CTRL skew matching and length control.
The length of shorter CK and ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Nonincluded lengths are grayed out in the figure.
Assuming A8 is the longest, CACLM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 5-76. CACLM for Two or Four Address Loads on One Side of PCB
Table 5-59. CK and ADDR_CTRL Routing Specification(1)(2)(3)
NO.
1
PARAMETER
MIN
TYP
MAX
2500
25
UNIT
mils
mils
mils
mils
mils
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
2
3
660
25
4
5
125
194
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-59. CK and ADDR_CTRL Routing Specification(1)(2)(3) (continued)
NO.
PARAMETER
MIN
TYP
MAX
660
25
UNIT
mils
mils
mils
mils
mils
mils
mils
mils
mils
mils
w
6
7
8
9
A4 length
A4 skew
AS length
AS skew
100
25
10 AS+ and AS- length
11 AS+ and AS- skew
12 AT length(6)
13 AT skew(7)
14 AT skew(8)
15 CK and ADDR_CTRL nominal trace length(9)
16 Center-to-center CK to other DDR3 trace spacing(10)
17 Center-to-center ADDR_CTRL to other DDR3 trace spacing(10)(11)
18 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(10)
19 CK center-to-center spacing(12)
70
5
500
100
5
CACLM-50
CACLM
CACLM+50
4
4
3
w
w
20 CK spacing to other net(10)
21 Rcp(13)
22 Rtt(13)(14)
4
Zo-1
Zo-5
w
Ω
Ω
Zo
Zo
Zo+1
Zo+5
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump
between the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
(4) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(5) Nonmirrored configuration (all DDR3 memories on same side of PCB).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 5.13.8.2.1.6.1
and Figure 5-76.
(10) Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
(11) Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
(12) CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended
impedance defined in Table 5-53.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
5.13.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ
Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs,
DQLM0 and DQLM1.
NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
195
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Given the DQS[x] and DQ[x] pin locations on the device and the DDR3 memories, the maximum possible
Manhattan distance can be determined given the placement. Figure 5-77 shows this distance for a two-
load case. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 5-60.
DQLMX0
DQ[0:7], DM0, DQS0
DQ0
DQ[8:15], DM1, DQS1
DQ1
DQLMX1
DQ[16:23], DM2, DQS2
DQ2
DQLMY0
DQLMX2
DQ[24:31], DM3, DQS3
DQLMY1
DQLMY3 DQLMY2
DQ3
DQLMX3
3
2
1
0
DQ0 - DQ3 represent data bytes 0 - 3.
There are four DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
Figure 5-77. DQLM for Any Number of Allowed DDR3 Devices
Table 5-60. DQS[x] and DQ[x] Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
DQLM0
DQLM1
DQLM2
DQLM3
25
UNIT
mils
mils
mils
mils
mils
mils
mils
w
DQ0 nominal length(3)(4)
DQ1 nominal length(3)(5)
DQ2 nominal length
DQ3 nominal length
DQ[x] skew(6)
2
3
4
5
6
DQS[x] skew
DQS[x]-to-DQ[x] skew(6)(7)
5
7
25
8
Center-to-center DQ[x] to other DDR3 trace spacing(8)(9)
Center-to-center DQ[x] to other DQ[x] trace spacing(8)(10)
4
3
9
w
10 DQS[x] center-to-center spacing(11)
11 DQS[x] center-to-center spacing to other net(8)
4
w
(1) DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte. For definition, see Section 5.13.8.2.1.6.2 and Figure 5-77.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) Length matching is only done within a byte. Length matching across bytes is not required. To maintain tighter delay skew, route the
DQ[x] and DQS[x] signals within a byte to have same number of VIA and layer transitions.
(7) Each DQS clock net class is length matched to its associated DQ signal net class.
(8) Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
(9) Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
(10) This applies to spacing within same DQ[x] signal net class.
(11) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo × 2, where Zo is the single-
ended impedance defined in Table 5-53.
196
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.2 LPDDR2 Routing Guidelines
This section provides the timing specification for the LPDDR2 interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR2 memory
system without the need for a complex timing closure process. For more information regarding guidelines
for using this LPDDR2 specification, see Understanding TI's PCB Routing Rule-Based DDR Timing
Specification. This application report provides generic guidelines and approach. All the specifications
provided in the data manual take precedence over the generic guidelines and must be adhered to for a
reliable LPDDR2 interface operation.
5.13.8.2.2.1 LPDDR2 Board Designs
TI only supports board designs using LPDDR2 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the LPDDR2 memory interface are shown in Table 5-61
and Figure 5-78.
Table 5-61. Switching Characteristics for LPDDR2 Memory Interface
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CK)
Cycle time, DDR_CK and DDR_CKn
7.52
3.76(1)
ns
(1) The JEDEC JESD209-2F standard defines the maximum clock period of 100 ns for all standard-speed bin LPDDR2 memory. The
device has only been tested per the limits published in this table.
1
DDR_CK
DDR_CKn
Figure 5-78. LPDDR2 Memory Interface Clock Timing
5.13.8.2.2.2 LPDDR2 Device Configurations
There are several possible combinations of device counts and single-side or dual-side mounting. Table 5-
62 lists all the supported configurations.
Table 5-62. Supported LPDDR2 Device Combinations
NUMBER OF LPDDR2
LPDDR2 DEVICE WIDTH (BITS)
MIRRORED?(1)
LPDDR2 EMIF WIDTH (BITS)
DEVICES
1
2(2)
32
32
16
16
N
N
N
N
32
32
16
16
1
2(2)
(1) Two LPDDR2 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) Two devices are supported only with twin-die configuration which embeds two devices in the same package.
Details on treating unused pins are listed in Section 5.13.8.2.2.3.1.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
197
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.2.3 LPDDR2 Interface
5.13.8.2.2.3.1 LPDDR2 Interface Schematic
The LPDDR2 interface schematic varies, depending upon the width of the LPDDR2 devices used.
Figure 5-79 shows the schematic connections for 16-bit interface using one x16 LPDDR2 device. Two x16
LPDDR2 devices are supported for twin-die configuration which embeds two devices in the same
package.
16-Bit LPDDR2
Interface
16-Bit LPDDR2
Device
DDR_D15
DQ15
8
DDR_D8
DQ8
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DM1
DQS1_t
DQS1_c
DDR_D7
DQ7
8
DDR_D0
DQ0
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DM0
DQS0_t
DQS0_c
DDR_CK
CK_t
CK_c
DDR_CKn
DDR_CKE0
DDR_CKE1
DDR_CSn0
DDR_CSn1
DDR_RASn
CKE0
CKE1
CS0_n
CS1_n
CA0
DDR_CASn
DDR_WEn
DDR_BA0
DDR_BA1
DDR_BA2
CA1
CA2
CA7
CA8
CA9
DDR_A1
DDR_A2
CA5
CA6
CA4
CA3
VDDS_DDR
1 K
DDR_A10
DDR_A13
0.1 µF
0.1 µF
ZQ0/1
ZQ
Vref(CA)
Vref(DQ)
DDR_VREF
DDR_VTP
DDR_VREF
0.1 µF
0.1 µF
1 K
49.9 Ω
( 1%, 20 mW)
Copyright © 2016, Texas Instruments Incorporated
Figure 5-79. 16-Bit Interface Using One 16-Bit LPDDR2 Device
Figure 5-80 shows the schematic connections for 32-bit interface using one x32 LPDDR2 device.
198
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
32-Bit LPDDR2
Interface
32-Bit LPDDR2
Device
DDR_D31
DQ31
8
DDR_D24
DQ24
DDR_DQM3
DDR_DQS3
DDR_DQSn3
DM31
DQS3_t
DQS3_c
DDR_D23
DQ23
8
DDR_D16
DQ16
DDR_DQM2
DDR_DQS2
DDR_DQSn2
DM2
DQS2_t
DQS2_c
DDR_D15
DQ15
8
DDR_D8
DQ8
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DM1
DQS1_t
DQS1_c
DDR_D7
DQ7
8
DQ0
DDR_D0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DM0
DQS0_t
DQS0_c
DDR_CK
CK_t
CK_c
DDR_CKn
DDR_CKE0
DDR_CKE1
DDR_CSn0
DDR_CSn1
DDR_RASn
CKE0
CKE1
CS0_n
CS1_n
CA0
DDR_CASn
DDR_WEn
DDR_BA0
DDR_BA1
DDR_BA2
CA1
CA2
CA7
CA8
CA9
DDR_A1
DDR_A2
CA5
CA6
CA4
CA3
VDDS_DDR
1 K
DDR_A10
DDR_A13
0.1 µF
0.1 µF
ZQ0/1
ZQ
Vref(CA)
Vref(DQ)
DDR_VREF
DDR_VTP
DDR_VREF
0.1 µF
0.1 µF
1 K
49.9 Ω ( 1% 20mW)
Copyright © 2016, Texas Instruments Incorporated
Figure 5-80. 32-Bit Interface Using One 32-Bit LPDDR2 Device
When not using a part of LPDDR2 interface (using x16 or not using the LPDDR2 interface):
•
•
•
•
•
Connect the VDDS_DDR supply to 1.8 V
Connect the DDR_VREF supply to 0.9 V
Tie off DDR_DQS[x] (x=0,1,2,3) that are unused to VSS via 1 kΩ
Tie off DDR_DQSn[x] (x=0,1,2,3) that are unused to VDDS_DDR via 1 kΩ
All other unused pins can be left as NC.
Note: All the unused DDR ADDR_CTRL lines used for DDR3 operation should be left as NC.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
199
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
Table 5-63 shows the supported LPDDR2 device configurations which are compatible with this interface.
Table 5-63. Compatible JEDEC LPDDR2 Devices (Per Interface)
NO.
1
PARAMETER
JEDEC LPDDR2 device speed grade
JEDEC LPDDR2 device bit width
JEDEC LPDDR2 device count
CONDITION
MIN
MAX
UNIT
tc(DDR_CK) and tc(DDR_CKn)
LPDDR2-533
2
x16
1
x32
Bits
3
2(1) Devices
(1) Two devices are supported only with twin-die configuration which embeds two devices in the same package.
5.13.8.2.2.3.3 LPDDR2 PCB Stackup
Table 5-64 shows the minimum stackup requirements. Additional layers may be added to the PCB
stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference
performance, or to reduce the size of the PCB footprint.
Table 5-64. Minimum PCB Stackup
LAYER
TYPE
Signal
Plane
Plane
Signal
DESCRIPTION
Top signal routing
Ground
1
2
3
4
Power
Bottom signal routing
PCB stackup specifications for LPDDR2 interface are listed in Table 5-65.
Table 5-65. PCB Stackup Specifications(1)
NO.
1
PARAMETER
MIN
4
TYP
MAX
UNIT
PCB routing and plane layers
Signal routing layers
2
2
3
Full ground reference layers under LPDDR2 routing region(1)
1
4
Full VDDS_DDR power reference layers under the LPDDR2 routing
region(1)
1
5
6
7
8
9
Number of reference plane cuts allowed within LPDDR2 routing region(2)
Number of layers between LPDDR2 routing layer and reference plane(3)
PCB routing feature size
0
0
4
4
mils
mils
mils
mils
Ω
PCB trace width, w
PCB BGA escape via pad size(4)
18
10
50
Zo
20
10 PCB BGA escape via hole size
11 Single-ended impedance, Zo(5)
12 Impedance control(6)(7)
75
Zo-5
Zo+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the LPDDR2 routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Zo is the nominal singled-ended impedance selected for the PCB.
(6) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo
defined by the single-ended impedance parameter.
(7) Tighter impedance control is required to ensure flight time skew is minimal.
200
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.2.3.4 LPDDR2 Placement
Figure 5-81 shows the placement rules for the device as well as the LPDDR2 memory device. Placement
restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing
space.
X1
LPDDR2
interface
Y
Figure 5-81. Placement Specifications
Table 5-66. Placement Specifications(1)
NO.
1
PARAMETER
MIN
MAX
1500
1500
UNIT
mils
mils
w
X1 Offset(2)(3)
Y Offset(2)(3)(4)
2
3
Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5)
4
(1) LPDDR2 keepout region to encompass entire LPDDR2 routing area.
(2) Measurements from center of device to center of LPDDR2 device.
(3) Minimizing X1 and Y improves timing margins.
(4) w is defined as the signal trace width.
(5) Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground
plane.
5.13.8.2.2.3.5 LPDDR2 Keepout Region
The region of the PCB used for LPDDR2 circuitry must be isolated from other signals. The LPDDR2
keepout region is defined for this purpose and is shown in Figure 5-82. This region should encompass all
LPDDR2 circuitry and the region size varies with component placement and LPDDR2 routing. Non-
LPDDR2 signals should not be routed on the same signal layer as LPDDR2 signals within the LPDDR2
keepout region. Non-LPDDR2 signals may be routed in the region provided they are routed on layers
separated from LPDDR2 signal layers by a ground layer. No breaks should be allowed in the reference
ground or VDDS_DDR power plane in this region. In addition, the VDDS_DDR power plane should cover
the entire keepout region.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
201
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
LPDDR2
interface
LPDDR2 Keepout Region
Encompasses Entire
LPDDR2 Routing Area
Figure 5-82. LPDDR2 Keepout Region
5.13.8.2.2.3.6 LPDDR2 Net Classes
Table 5-67. Clock Net Class Definitions for the LPDDR2
Interface
CLOCK NET CLASS PIN NAMES
CK
DDR_CK and DDR_CKn
DQS0
DQS1
DQS2
DQS3
DDR_DQS0 and DDR_DQSn0
DDR_DQS1 and DDR_DQSn1
DDR_DQS2 and DDR_DQSn2
DDR_DQS3 and DDR_DQSn3
Table 5-68. Signal Net Class and Associated Clock Net Class for LPDDR2 Interface
ASSOCIATED CLOCK
SIGNAL NET CLASS
PIN NAMES
NET CLASS
ADDR_CTRL
CK
DDR_BA[2:0], DDR_CSn0, DDR_CSn1, DDR_CKE0, DDR_CKE1,
DDR_RASn, DDR_CASn, DDR_WEn, DDR_A1, DDR_A2, DDR_A10,
DDR_A13
DQ0
DQ1
DQ2
DQ3
DQS0
DQS1
DQS2
DQS3
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
DDR_D[23:16], DDR_DQM2
DDR_D[31:24], DDR_DQM3
5.13.8.2.2.3.7 LPDDR2 Signal Termination
On-device termination (ODT) is available for DQ[3:0] signal net classes, but is not specifically required for
normal operation. System designers may evaluate the need for additional series termination if required
based on signal integrity, EMI and overshoot/undershoot reduction.
5.13.8.2.2.3.8 LPDDR2 DDR_VREF Routing
DDR_VREF is the reference voltage for the input buffers on the LPDDR2 memory as well as the device.
DDR_VREF is intended to be half the LPDDR2 power supply voltage and is typically generated with a
voltage divider connected to the VDDS_DDR power supply. It should be routed as a nominal 20-mil wide
trace with 0.1-µF bypass capacitors near each device connection. Narrowing of DDR_VREF is allowed to
accommodate routing congestion.
202
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.8.2.2.4 Routing Specification
5.13.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 5-83 and
Figure 5-84 represent the supported topologies. Figure 5-85 and Figure 5-86 show the DQS[x] and DQ[x]
routing. Figure 5-87 shows the DQLM for the LPDDR2 interface.
Device
DQS[x]
DDR3
DQS[x]+
DQS[x]-
DQS[x]
IO Buffer
IO Buffer
Routed Differentially
x = 0, 1, 2, 3
Figure 5-83. DQS[x] Topology
Device
DQ[x]
DDR3
DQ[x]
DQ[x]
IO Buffer
IO Buffer
x = 0, 1, 2, 3
Figure 5-84. DQ[x] Topology
DQS[x]
DQS[x]+
DQS[x]-
Routed Differentially
x = 0, 1, 2, 3
Figure 5-85. DQS[x] Routing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
203
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
DQ[x]
x = 0, 1, 2, 3
Figure 5-86. DQ[x] Routing
DQLMXi
DQi
LPDDR2
interface
i = 0, 1, 2, 3
DQLMYi
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
DQ0 - DQ3 represent data bytes 0 - 3.
There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16-
bit interface. Each DQLM is the longest Manhattan distance of the byte.
Figure 5-87. DQLM for LPDDR2 Interface
Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 5-69.
Table 5-69. DQS[x] and DQ[x] Routing Specification(1)(2)
NO.
1
PARAMETER
MIN
TYP
MAX
DQLM0
DQLM1
DQLM2
DQLM3
50
UNIT
mils
mils
mils
mils
mils
mils
DQ0 nominal length(3)(4)
DQ1 nominal length(3)(5)
DQ2 nominal length (3)(6)
DQ3 nominal length (3)(7)
DQ[x] skew(8)
2
3
4
5
6
DQS[x] skew
10
7
Via count per each trace in DQ[x], DQS[x]
Via count difference across a given DQ[x], DQS[x]
DQS[x]-to-DQ[x] skew(8)(9)
2
8
0
9
50
mils
w
10 Center-to-center DQ[x] to other LPDDR2 trace spacing(10)(11)
11 Center-to-center DQ[x] to other DQ[x] trace spacing(10)(12)
12 DQS[x] center-to-center spacing(13)
4
3
w
13 DQS[x] center-to-center spacing to other net(10)
4
w
204
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
(1) DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net
classes.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) DQLMn is the longest Manhattan distance of a byte.
(4) DQLM0 is the longest Manhattan length for the DQ0 net class.
(5) DQLM1 is the longest Manhattan length for the DQ1 net class.
(6) DQLM2 is the longest Manhattan length for the DQ2 net class.
(7) DQLM3 is the longest Manhattan length for the DQ3 net class.
(8) Length matching is only done within a byte. Length matching across bytes is not required.
(9) Each DQS clock net class is length matched to its associated DQ signal net class.
(10) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.
(11) Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class.
(12) This applies to spacing within same DQ[x] signal net class.
(13) DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-
ended impedance.
5.13.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
CK signals are routed as point-to-point differential, and ADDR_CTRL signals are routed as point-to-point
single ended. The supported topology for CK and ADDR_CTRL are shown in Figure 5-88 through
Figure 5-91. ADDR_CTRL are routed very similar to DQ and CK is routed very similar to DQS.
CK+
Device CK
LPDDR2
Output Buffer
Input Buffer
CK-
Routed Differentially
Figure 5-88. CK Signals Topology
Device
ADDR_CTRL
Output Buffer
LPDDR2
ADDR_CTRL
ADDR_CTRL
Input Buffer
Figure 5-89. ADDR_CTRL Signals Topology
CK-
CK+
CK-
Routed Differentially
Figure 5-90. CK Signals Routing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
205
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
ADDR_CTRL
Figure 5-91. ADDR_CTRL Signals Routing
CACLMX
LPDDR2
interface
CACLM = CACLMX + CACLMY
CACLMY
CACLM is the longest Manhattan distance of the CK/ADDR_CTRL signal class.
Figure 5-92. CACLM for LPDDR2 Interface
Trace routing specifications for the CK and the ADD_CTRL are specified in Table 5-70.
Table 5-70. CK and ADDR_CTRL Routing Specification
NO.
1
PARAMETER
CK and ADDR_CTRL nominal trace length(1)
ADDR_CTRL skew
MIN
TYP
MAX
UNIT
mils
mils
mils
CACLM
2
50
10
2
3
CK skew
4
Via count per each trace ADDR_CTRL, CK
Via count difference across ADDR_CTRL, CK
ADDR_CTRL-to-CK skew
Center-to-center ADDR_CTRL to other LPDDR2 trace spacing(2)(3)
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(2)
CK center-to-center spacing(4)
5
0
6
50
mils
w
7
4
3
8
w
9
10 CK center-to-center spacing to other net(2)
4
w
(1) CACLM is the longest Manhattan distance of ADDR_CTRL and CK.
(2) Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.
(3) Other LPDDR2 trace spacing means signals that are not part of the same CK, ADDR_CTRL signal net class.
(4) CK pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single ended
impedance.
206
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.9 Display Subsystem (DSS)
NOTE
For more information, see the Display Subsystem chapter of the AM437x Sitara Processors
Technical Reference Manual.
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or
internal (SRAM) memory on an LCD panel or a TV set. The display subsystem integrates the following
elements:
•
•
Display controller (DISPC) module
Remote frame buffer interface (RFBI) module
The DSS can be used in the following configuration: LCD display with parallel interface
5.13.9.1 DSS—Parallel Interface
In parallel interface, the paths of the display subsystem modules are the display controller and the RFBI.
The display controller has two I/O pad modes and could be in the following configuration:
•
•
Bypass mode (RFBI disabled), which implements the MIPI DPI protocol
RFBI mode (RFBI enabled), which implements MIPI DBI 2.0 type B protocol
5.13.9.1.1 DSS—Parallel Interface—Bypass Mode
Two types of LCD panel are supported:
•
•
Thin film transistor (TFT) or active matrix technology
Supertwisted nematic (STN) or passive matrix technology
Both configurations are discussed in the following paragraphs.
5.13.9.1.1.1 DSS—Parallel Interface—Bypass Mode—TFT Mode
Table 5-72 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 5-93).
Table 5-71. DSS Timing Conditions—TFT Mode
VALUE
TIMING CONDITION PARAMETER
UNIT
MIN
MAX
Output Condition
CLOAD
Output load capacitance
10
pF
Table 5-72. DSS Switching Characteristics—TFT Mode
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
DL0
DL1
DL2
DL3
DL4
td(pclkA-hsync)
Delay time, output pixel clock dss_pclk active edge to
output horizontal synchronization dss_hsync transition
-2.4
2.4
-3.5
2.5
ns
ns
td(pclkA-vsync)
td(pclkA-acbiasA)
td(pclkA-dV)
Delay time, output pixel clock dss_pclk active edge to
output vertical synchronization dss_vsync transition
-2.4
-2.4
-2.4
2.4
2.4
2.4
100
-3.5
-3.5
-3.5
2.5
2.5
2.5
75
Delay time, output pixel clock dss_pclk active edge to
output data enable dss_acbias active level
ns
Delay time, output pixel clock dss_pclk active edge to
output data dss_data[23:0] valid
Frequency(1), output pixel clock dss_pclk
ns
1 / tc(pclk)
MHz
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
207
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-72. DSS Switching Characteristics—TFT Mode (continued)
OPP100
MIN MAX
0.45P(2) 0.55P(2)(3) 0.45P(2) 0.55P(2)(3)
200 200
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
DL5
tw(pclk)
tJ(pclk)
Pulse duration, output pixel clock dss_pclk low or high
Peak-peak jitter, output pixel clock dss_pclk
ns
ps
(1) The pixel clock frequency is software programmable via the pixel clock DISPC_DIVISOR register.
(2) P = dss_pclk period in ns
(3) tw(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3
DL5
DL4
dss_pclk
DL1
dss_vsync
DL0
dss_hsync
DL2
dss_acbias
DL3
dss_data[23:0]
A. The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
B. The pixel clock frequency is programmable.
C. All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of
dss_pclk too.
D. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Figure 5-93. DSS—TFT Mode
5.13.9.1.1.2 DSS—Parallel Interface—Bypass Mode—STN Mode
Table 5-74 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 5-94).
Table 5-73. DSS Timing Conditions—STN Mode
VALUE
TIMING CONDITION PARAMETER
UNIT
MIN
MAX
Output Condition
CLOAD
Output load capacitance
40
pF
Table 5-74. DSS Switching Characteristics—STN Mode(1)
OPP100
OPP50
MAX
NO.
PARAMETER
UNIT
MIN
MAX
MIN
-6
DL3
td(pclkA-dV)
Delay time, output pixel clock dss_pclk active edge to
output data dss_data[7:0] valid
-6
6
6
ns
DL4
DL5
1 / tc(pclk)
tw(pclk)
Frequency(2), output pixel clock dss_pclk
Pulse duration, output pixel clock dss_pclk low or high 0.45P(3) 0.55P(3)(4) 0.45P(3) 0.55P(3)(4)
45
45
MHz
ns
(1) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.
(2) The pixel clock frequency is software programmable via the pixel clock divider DISPC_DIVISOR register.
(3) P = dss_pclk period in ns
(4) tW(pclk) = 0.66P when DISPC_DIVISOR[7:0] PCD = 3
208
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-74. DSS Switching Characteristics—STN Mode(1) (continued)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
tJ(pclk)
Peak-peak jitter, output pixel clock dss_pclk
200
200
ps
DL5
DL4
dss_pclk
dss_vsync
dss_hsync
dss_acbias
DL3
dss_data[23:0]
A. The pixel data bus depends on the use of 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
B. All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of
dss_pclk too.
C. dss_vsync width must be programmed to be as small as possible.
D. The pixel clock frequency is programmable.
E. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Figure 5-94. DSS—STN Mode
5.13.9.1.2 DSS—Parallel Interface—RFBI Mode—Applications
5.13.9.1.2.1 DSS—Parallel Interface—RFBI Mode—MIPI DBI 2.0—LCD Panel
The Remote Frame Buffer Interface (RFBI) module provides the necessary control signals and data
(MIPI® DBI 2.0 type B protocol) to interface to the LCD driver of the LCD panel.
Table 5-76 and Table 5-77 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-95, Figure 5-96, and Figure 5-97).
Table 5-75. DSS Timing Conditions—RFBI Mode—MIPI DBI 2.0—LCD Panel(1)
VALUE
TIMING CONDITION PARAMETER
UNIT
MIN
MAX
Input Conditions
tR
Input signal rise time
7
7
ns
ns
tF
Input signal fall time
Output Condition
CLOAD
Output load capacitance
30
pF
(1) For any information regarding the RFBI registers configuration, see the Display Subsystem / Display Subsystem Environment / LCD
Support / Parallel Interface / Parallel Interface in RFBI Mode (MIPI DBI Protocol) / Transaction Timing Diagrams section of the AM437x
Sitara Processors Technical Reference Manual.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
209
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-76. DSS Timing Requirements—RFBI Mode—MIPI DBI 2.0—LCD Panel
OPP100
MIN MAX
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
DR0
tsu(dV-rdH)
Setup time, input data rfbi_da[15:0] valid to output
read enable rfbi_rd high
7
7
ns
ns
ns
DR1
th(rdH-dIV)
Hold time, output read enable rfbi_rd high to input data
rfbi_da[15:0] invalid
5
5
td(Data sampled)
Input data rfbi_da[15:0] sampled at the end of the
access time
N(1)
N(1)
(1) N = (AccessTime) × (TimeParaGranularity + 1) × L4CLK
Table 5-77. DSS Switching Characteristics—RFBI Mode—MIPI DBI 2.0—LCD Panel
OPP100
MIN MAX
OPP50
MIN MAX
PARAMETER
UNIT
tw(wrH)
tw(wrL)
Pulse duration, output write enable rfbi_wr high
Pulse duration, output write enable rfbi_wr low
A(1)
B(2)
C(3)
A(1)
B(2)
C(3)
ns
ns
ns
td(a0-wrL)
Delay time, output command/data control rfbi_a0 transition to
output write enable rfbi_wr low
td(wrH-a0)
td(csx-wrL)
td(wrH-csxH)
Delay time, output write enable rfbi_wr high to output
command/data control rfbi_a0 transition
Delay time, output chip select rfbi_csx(14) low to output write
enable rfbi_wr low
D(4)
E(5)
F(6)
D(4)
E(5)
F(6)
ns
ns
ns
Delay time, output write enable rfbi_wr high to output chip select
rfbi_csx(14) high
td(dV)
Output data rfbi_da[15:0] valid
G(7)
H(8)
G(7)
H(8)
ns
ns
td(a0H-rdL)
Delay time, output command/data control rfbi_a0 high to output
read enable rfbi_rd low
td(rdlH-a0)
Delay time, output read enable rfbi_rd high to output
command/data control rfbi_a0 transition
I(9)
I(9)
ns
tw(rdH)
Pulse duration, output read enable rfbi_rd high
Pulse duration, output read enable rfbi_rd low
J(10)
K(11)
L(12)
J(10)
K(11)
L(12)
ns
ns
ns
tw(rdL)
td(rdL-csxL)
Delay time, output read enable rfbi_rd low to output chip select
rfbi_csx(14) low
td(rdH-csxH)
Delay time, output read enable rfbi_rd high to output chip select
rfbi_csx(14) high
M(13)
M(13)
ns
tR(wr)
tF(wr)
tR(a0)
tF(a0)
tR(csx)
tF(csx)
tR(d)
Rise time, output write enable rfbi_wr
Fall time, output write enable rfbi_wr
Rise time, output command/data control rfbi_a0
Fall time, output command/data control rfbi_a0
Rise time, output chip select rfbi_csx(14)
Fall time, output chip select rfbi_csx(14)
Rise time, output data rfbi_da[15:0]
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tF(d)
Fall time, output data rfbi_da[15:0]
tR(rd)
tF(rd)
Rise time, output read enable rfbi_rd
Fall time, output read enable rfbi_rd
(1) A = (WECycleTime – WEOffTime) × (TimeParaGranularity + 1) × L4CLK
(2) B = (WEOffTime – WEOntime) × (TimeParaGranularity + 1) × L4CLK
(3) C = WEOnTime × (TimeParaGranularity + 1) × L4CLK
(4) D = (WECycleTime + CSPulseWidth – WEOffTime) × (TimeParaGranularity + 1) × L4CLK if mode Write to Read or Read to Write is
enabled
(5) E = (WEOnTime – CSOnTime) × (TimeParaGranularity + 1) × L4CLK
(6) F = (CSOffTime – WEOffTime) × (TimeParaGranularity + 1) × L4CLK
(7) G = WECycleTime × (TimeParaGranularity + 1) × L4CLK
210
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
(8) H = REOnTime × (TimeParaGranularity + 1) × L4CLK
(9) I = (RECycleTime + CSPulseWidth – REOffTime) × (TimeParaGranularity + 1) × L4CLK if mode Write to Read or Read to Write is
enabled
(10) J = (RECycleTime – REOffTime) × (TimeParaGranularity + 1) × L4CLK
(11) K = (REOffTime – REOntime) × (TimeParaGranularity + 1) × L4CLK
(12) L = (REOnTime – CSOnTime) × (TimeParaGranularity + 1) × L4CLK
(13) M = (CSOffTime – REOffTime) × (TimeParaGranularity + 1) × L4CLK
(14) In rfbi_csx, x is equal to 0 or 1.
CsPulseWidth
WeCycleTime
CsOffTime
WeCycleTime
rfbi_a0
CsOffTime
CsOnTime
CsOnTime
rfbi_csx(A)
WeOffTime
WeOnTime
WeOffTime
WeOnTime
rfbi_wr
rfbi_da[n:0](B)
rfbi_rd
DATA0
DATA1
rfbi_te_vsync[1:0]
rfbi_hsync[1:0]
A. In rfbi_csx, x is equal to 0 or 1.
B. rfbi_da[n:0], n up to 15
C. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Figure 5-95. DSS—RFBI Mode—MIPI DBI 2.0—LCD Panel—Command / Data Write
AccessTime
ReCycleTime
AccessTime
ReCycleTime
CsPulseWidth
rfbi_a0
rfbi_csx(A)
rfbi_rd
CsOffTime
CsOnTime
CsOffTime
CsOnTime
ReOffTime
ReOnTime
ReOffTime
ReOnTime
DR0
DATA0
DR1
rfbi_da[n:0](B)
rfbi_wr
DATA1
rfbi_te_vsync[1:0]
rfbi_hsync[1:0]
A. In rfbi_csx, x is equal to 0 or 1.
B. rfbi_da[n:0], n up to 15
C. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Figure 5-96. DSS—RFBI Mode—MIPI DBI 2.0—LCD Panel—Command / Data Read
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
211
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
WECycleTime
ReCycleTime
AccessTime
WECycleTime
rfbi_a0
CsOffTime
CsOnTime
CsOffTime
CsOnTime
CsOffTime
CsOnTime
rfbi_csx(A)
WEOffTime
WEOnTime
rfbi_wr
WEOffTime
WEOnTime
ReOffTime
ReOnTime
rfbi_rd
CsPulseWidth
CsPulseWidth
WRITE
rfbi_da[n:0](B)
WRITE
READ
rfbi_te_vsync[1:0]
rfbi_hsync[1:0]
A. In rfbi_csx, x is equal to 0 or 1.
B. rfbi_da[n:0], n up to 15
C. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Figure 5-97. DSS—RFBI Mode—MIPI DBI 2.0—LCD Panel—Command / Data Write to Read and Read to
Write Modes
5.13.9.1.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP
The Remote Frame Buffer Interface (RFBI) module can provide also the necessary control signals and
data to interface to the Pico DLP driver of the Pico DLP panel. Table 5-78 assumes testing over the
recommended operating conditions and electrical characteristic conditions below (see Figure 5-98).
Table 5-78. DSS Timing Conditions—RFBI Mode—Pico DLP
VALUE
TIMING CONDITION PARAMETER
UNIT
MIN
MAX
Output Condition
CLOAD
Output load capacitance
5
pF
To use Pico DLP application, RFBI register must be configured as shown in Table 5-79:
Table 5-79. DSS Register Configuration—RFBI Mode—Pico DLP
DESCRIPTION
Selection parallel mode
REGISTER AND BIT FIELD(1)
BIT
VALUES
RFBI_CONFIGi and
ParallelMode
[1:0]
0b11: 16-bit parallel output interface
selected
Time Granularity (multiplies signal timing
latencies by 2).
RFBI_CONFIGi
andTimeGranularity
[4]
0b0: x2 latency disable
CS signal assertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
CSOnTime
[3:0]
0b0000
CS signal deassertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
CSOffTime
[9:4]
0b000100: 4 cycles
0b0000
WE signal assertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
WEOnTime
[13:10]
[19:14]
[23:20]
WE signal deassertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
WEOffTime
0b000010: 2 cycles
0b0000
RE signal assertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
REOnTime
212
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-79. DSS Register Configuration—RFBI Mode—Pico DLP (continued)
DESCRIPTION
REGISTER AND BIT FIELD(1)
BIT
VALUES
RE signal deassertion time from Start Access
Time
RFBI_ONOFF_TIMEi and
REOffTime
[29:24]
0b0000
Write cycle time
RFBI_CYCLE_TIMEi and
WECycleTime
[5:0]
[11:6]
[17:12]
[18]
0b000100: 4 cycles
0b000000
0b000000
0b0
Read cycle time
RFBI_CYCLE_TIMEi and
ReCycleTime
CS pulse width
RFBI_CYCLE_TIMEi and
CSPulseWidth
Read to Write CS pulse width enable
Read to Read CS pulse width enable
Write to Write CS pulse width enable
Write to Read CS pulse width enable
RFBI_CYCLE_TIMEi and
RWEnable
RFBI_CYCLE_TIMEi and
RREnable
[19]
0b0
RFBI_CYCLE_TIMEi and
WWEnable
[20]
0b0
RFBI_CYCLE_TIMEi and
WREnable
[21]
0b0
From Start Access Time to CLK rising edge
used for the first data capture
RFBI_CYCLE_TIMEi and
AccessTime
[27:22]
0b000000
(1) i is equal to 0 or 1. For more information, see the DSS chapter in the AM437x Sitara Processors Technical Reference Manual.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
213
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-80. DSS Switching Characteristics—RFBI Mode—Pico DLP(1)(2)(3)
OPP100
MAX
OPP50
PARAMETER
UNIT
MIN
MIN
MAX
tw(wrH)
tw(wrL)
Pulse duration, output write enable rfbi_wr high
Pulse duration, output write enable rfbi_wr low
A(4)
B(5)
C(6)
A(4)
B(5)
C(6)
ns
ns
ns
td(a0-wrL)
Delay time, output command/data control rfbi_a0
transition to output write enable rfbi_wr low
td(wrH-a0)
td(csx-wrL)
td(wrH-csxH)
Delay time, output write enable rfbi_wr high to output
command/data control rfbi_a0 transition
Delay time, output chip select rfbi_csx(8) low to output
write enable rfbi_wr low
D(7)
E(9)
D(7)
E(9)
ns
ns
ns
Delay time, output write enable rfbi_wr high to output
chip select rfbi_csx(8) high
F(10)
F(10)
td(dataV)
td(Skew)
Output data rfbi_da[15:0](11) valid
G(12)
15.5
G(12)
15.5
ns
ns
Skew between output write enable falling rfbi_wr and
output data rfbi_da[15:0](11) high or low
td(a0H-rdL)
td(rdlH-a0)
Delay time, output command/data control rfbi_a0 high to
output read enable rfbi_rd low
H(13)
I(14)
H(13)
I(14)
ns
ns
Delay time, output read enable rfbi_rd high to output
command/data control rfbi_a0 transition
tw(rdH)
Pulse duration, output read enable rfbi_rd high
Pulse duration, output read enable rfbi_rd low
J(15)
K(16)
L(17)
J(15)
K(16)
L(17)
ns
ns
ns
tw(rdL)
td(rdL-csxL)
Delay time, output read enable rfbi_rd low to output chip
select rfbi_csx(8) low
td(rdL-csxH)
Delay time, output read enable rfbi_rd low to output chip
select rfbi_csx(8) high
M(18)
M(18)
ns
tR(wr)
tF(wr)
tR(a0)
tF(a0)
Rise time, output write enable rfbi_wr
Fall time, output write enable rfbi_wr
Rise time, output command/data control rfbi_a0
Fall time, output command/data control rfbi_a0
Rise time, output chip select rfbi_csx(8)
Fall time, output chip select rfbi_csx(8)
Rise time, output data rfbi_da[15:0](11)
Fall time, output data rfbi_da[15:0](11)
Rise time, output read enable rfbi_rd
Fall time, output read enable rfbi_rd
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR(csx)
tF(csx)
tR(d)
tF(d)
tR(rd)
tF(rd)
CsOnTime
CS signal assertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
0(19)
40(19)
0(19)
20(19)
-
CsOffTime
WeOnTime
WeOffTime
ReOnTime
ReOffTime
CS signal deassertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
ns
ns
ns
ns
ns
WE signal assertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
WE signal deassertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
RE signal assertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
RE signal deassertion time from Start Access Time –
RFBI_ONOFF_TIMEi Register
-
WeCycleTime
ReCycleTime
CsPulseWidth
Write cycle time – RFBI_CYCLE_TIMEi Register
Read cycle time – RFBI_CYCLE_TIMEi Register
CS pulse width – RFBI_CYCLE_TIMEi Register
40(19)
-
0(19)
ns
ns
ns
214
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
(1) See DM Operating Condition Addendum for OPP voltages.
(2) At OPP100, L4 clock is 100 MHz and at OPP50, L4 clock is 50 MHz.
(3) rfbi_wr must be at 25 MHz.
(4) A = (WECycleTime – WEOffTime) × (TimeParaGranularity + 1) × L4CLK
(5) B = (WEOffTime – WEOntime) × (TimeParaGranularity + 1) × L4CLK
(6) C = WEOnTime × (TimeParaGranularity + 1) × L4CLK
(7) D = (WECycleTime + CSPulseWidth – WEOffTime) × (TimeParaGranularity + 1) × L4CLK if mode Write to Read or Read to Write is
enabled.
(8) In rfbi_csx, x is equal to 0 or 1.
(9) E = (WEOnTime – CSOnTime) × (TimeParaGranularity + 1) × L4CLK
(10) F = (CSOffTime – WEOffTime) × (TimeParaGranularity + 1) × L4CLK
(11) 16-bit parallel output interface is selected in DSS register.
(12) G = WECycleTime × (TimeParaGranularity + 1) × L4CLK
(13) H = REOnTime × (TimeParaGranularity + 1) × L4CLK
(14) I = (RECycleTime + CSPulseWidth – REOffTime) × (TimeParaGranularity + 1) × L4CLK if mode Write to Read or Read to Write is
enabled.
(15) J = (RECycleTime – REOffTime) × (TimeParaGranularity + 1) × L4CLK
(16) K = (REOffTime – REOntime) × (TimeParaGranularity + 1) × L4CLK
(17) L = (REOnTime – CSOnTime) × (TimeParaGranularity + 1) × L4CLK
(18) M = (CSOffTime – REOffTime) × (TimeParaGranularity + 1) × L4CLK
(19) These values are calculated by the following formula: RFBI Register (Value) × L4 Clock (ns).
CsPulseWidth
WeCycleTime
CsOffTime
WeCycleTime
rfbi_a0
rfbi_csx(A)
rfbi_wr
CsOffTime
CsOnTime
CsOnTime
WeOffTime
WeOnTime
WeOffTime
WeOnTime
rfbi_da[n:0](B)
rfbi_rd
DATA0
DATA1
rfbi_te_vsync[1:0]
rfbi_hsync[1:0]
A. In rfbi_csx, x is equal to 0 or 1.
B. rfbi_da[n:0], n up to 15
Figure 5-98. DSS—RFBI Mode—Pico DLP—Command / Data Write
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
215
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.10 Camera (VPFE)
The camera (VPFE) controller receives input video/image data from external capture devices and stores it
to external memory which is transferred into the external memory via a built-in DMA engine. An internal
buffer block provides a high bandwidth path between the module and the external memory. The Cortex-A9
will process the image data based on application requirements.
5.13.10.1 Camera (VPFE) Timing
The following tables assume testing over recommended operating conditions.
Table 5-81. VPFE Timing Requirements
1.8 V, 3.3 V
NO.
OPP50
MIN MAX
OPP100
MIN MAX
UNIT
VF1 tc(CAMx_CLK)
Cycle time, pixel clock input, CAMx_CLK
20
13.3
ns
ns
tsu(CAMx_D-
CAMx_CLK)
VF2
VF3
VF4
VF5
Setup time, CAMx_D to CAMx_CLK rising edge
7.5
3.5
tsu(CAMx_HD-
CAMx_CLK)
Setup time, CAMx_HD to CAMx_CLK rising edge
Setup time, CAMx_VD to CAMx_CLK rising edge
Setup time, CAMx_WEN to CAMx_CLK rising edge
7.5
7.5
3.5
3.5
ns
ns
tsu(CAMx_VD-
CAMx_CLK)
tsu(CAMx_WEN-
CAMx_CLK)
7.5
7.5
6.5
3.5
3.5
2.5
ns
ns
ns
VF6 tsu(C_FLD-CAMx_CLK) Setup time, CAMx_FIELD to CAMx_CLK rising edge
th(CAMx_CLK-
VF7
Hold time, CAMx_D valid after CAMx_CLK rising edge
Hold time, CAMx_HD to CAMx_CLK rising edge
Hold time, CAMx_VD to CAMx_CLK rising edge
Hold time, CAMx_WEN to CAMx_CLK rising edge
CAMx_D)
th(VDIN-HD-
CAMx_CLK)
th(CAMx_VD-
CAMx_CLK)
th(CAMx_WEN-
CAMx_CLK)
VF8
6.5
6.5
2.5
2.5
ns
ns
VF9
VF10
6.5
6.5
2.5
2.5
ns
ns
VF11 th(C_FLD-CAMx_CLK) Hold time, CAMx_FIELD to CAMx_CLK rising edge
Table 5-82. VPFE Output Switching Characteristics
1.8 V, 3.3 V
OPP100
MIN MAX
NO.
PARAMETER
OPP50
MIN MAX
UNIT
td(CAMx_HD-
CAMx_CLK)
td(CAMx_VD-
CAMx_CLK)
td(CAMx_WEN-
CAMx_CLK)
VF12
VF13
VF14
Output delay time, CAMx_HD to CLK rising edge
Output delay time, CAMx_VD to CLK rising edge
Output delay time, CAMx_WEN to CLK rising edge
9
9
9
15
2
2
2
9
9
9
ns
ns
ns
15
15
216
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
VF1
VF2
CAMx_CLK
(Falling Edge)
CAMx_CLK
(Rising Edge)
VF7
VF7
CAMx_D[xx]
VF8, VF9, VF11
VF10
VF3, VF4, VF6
VF5
CAMx_HD,
CAMx_VD,
CAMx_FIELD
CAMx_WEN
Figure 5-99. Camera Input Timings
CAMx_CLK
(Falling Edge)
CAMx_CLK
(Rising Edge)
VF15, VF16,
VF17
VF15, VF16,
VF17
VF12,
VF13, VF14
VF12, VF13, VF14
CAMx_HD,
CAMx_VD,
CAMx_FIELD
Figure 5-100. Camera Output Timings
VF18
CAMx_HD
(Falling Edge)
CAMx_HD
(Rising Edge)
VF20
VF19
CAMx_D[xx]
Figure 5-101. Camera Input Timings With VDIN0_HD as Pixel Clock
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
217
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.11 Inter-Integrated Circuit (I2C)
For more information, see the Inter-Integrated Circuit (I2C) section of the AM437x ARM Cortex-A9
Microprocessors (MPUs) Technical Reference Manual.
5.13.11.1 I2C Electrical Data and Timing
Table 5-83. I2C Timing Conditions - Slave Mode
STANDARD MODE
MIN MAX
FAST MODE
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
Output Condition
Cb
Capacitive load for each bus line
400
400
pF
Table 5-84. Timing Requirements for I2C Input Timings
(see Figure 5-102)
STANDARD MODE
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
us
us
Setup Time, SCL high before SDA low (for a repeated
START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
3
th(SDAL-SCLL)
us
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(1)
0(2)
us
us
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(2)
3.45(3)
0.9(3) us
Pulse duration, SDA high between STOP and START
conditions
8
9
tw(SDAH)
tr(SDA)
4.7
1.3
us
Rise time, SDA
1000
1000
300
300 ns
300 ns
300 ns
300 ns
us
10 tr(SCL)
Rise time, SCL
11 tf(SDA)
Fall time, SDA
12 tf(SCL)
Fall time, SCL
300
13 tsu(SCLH-SDAH)
14 tw(SP)
Setup time, high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
4
0
0.6
0
50
50 ns
(1) A fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the
standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
218
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
9
11
I2C[x]_SDA
6
8
14
4
13
5
10
I2C[x]_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 5-102. I2C Receive Timing
Table 5-85. Switching Characteristics for I2C Output Timings
(see Figure 5-120)
STANDARD MODE
PARAMETER
FAST MODE
NO.
UNIT
MIN
MAX
MIN
MAX
15 tc(SCL)
Cycle time, SCL
10
2.5
us
us
Setup Time, SCL high before SDA low (for a repeated
START condition)
16 tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
17 th(SDAL-SCLL)
us
18 tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
us
us
ns
19 tw(SCLH)
Pulse duration, SCL high
20 tsu(SDAV-SCLH)
21 th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0
3.45
0.9 us
Pulse duration, SDA high between STOP and START
conditions
22 tw(SDAH)
4.7
1.3
us
23 tr(SDA)
Rise time, SDA
1000 20 + 0.1Cb(1)
1000 20 + 0.1Cb(1)
300 20 + 0.1Cb(1)
300 20 + 0.1Cb(1)
0.6
300 ns
300 ns
300 ns
300 ns
us
24 tr(SCL)
Rise time, SCL
25 tf(SDA)
Fall time, SDA
26 tf(SCL)
Fall time, SCL
27 tsu(SCLH-SDAH)
(1) Cb is line load in pF.
Setup time, high before SDA high (for STOP condition)
4
26
24
I2C[x]_SDA
I2C[x]_SCL
21
23
19
28
20
25
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
Figure 5-103. I2C Transmit Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
219
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.12 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
5.13.12.1 McASP Device-Specific Information
The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and
McASP1). The McASP module consists of a transmit and receive section. These sections can operate
completely independently with different data formats, separate master clocks, bit clocks, and frame syncs
or, alternatively, the transmit and receive sections may be synchronized. The McASP module also
includes shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a DIT format where the bit stream is encoded for SPDIF, AES-3, IEC-
60958, CP-430 transmission. The receive section of the McASP peripheral supports the TDM
synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format; however, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode, which is useful for nonaudio data (for example,
passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling,
as well as error management.
The device McASP0 and McASP1 modules have up to four serial data pins each. The McASP FIFO size
is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used transparently to
better manage DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel
Audio Serial Port (McASP) section of the AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical
Reference Manual.
220
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.12.2 McASP Electrical Data and Timing
Table 5-86. McASP Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input signal rise time
Input signal fall time
1(1)
1(1)
4(1)
4(1)
ns
ns
Output Condition
CLOAD Output load capacitance
15
30
pF
(1) Except when specified otherwise.
Table 5-87. Timing Requirements for McASP(1)
(see Figure 5-104)
OPP100
OPP50
MIN
NO.
UNIT
MIN
MAX
MAX
Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
1
2
3
4
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
20
38.46
ns
ns
ns
ns
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
0.5P - 2.5(2)
0.5P - 2.5(2)
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
20
38.46
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
0.5R - 2.5(3)
0.5R - 2.5(3)
ACLKR and
ACLKX int
12.3
4
15.5
6
Setup time, McASP[x]_AFSR and
McASP[x]_AFSX input valid before
McASP[x]_ACLKR and
tsu(AFSRX-
ACLKRX)
ACLKR and
ACLKX ext in
5
6
7
8
ns
ns
ns
ns
McASP[x]_ACLKX
ACLKR and
ACLKX ext out
4
6
ACLKR and
ACLKX int
-1
-1
Hold time, McASP[x]_AFSR and
McASP[x]_AFSX input valid after
McASP[x]_ACLKR and
th(ACLKRX-
AFSRX)
ACLKR and
ACLKX ext in
1.6
1.6
12.3
4
2.3
2.3
15.5
6
McASP[x]_ACLKX
ACLKR and
ACLKX ext out
ACLKR and
ACLKX int
Setup time, McASP[x]_AXR input
tsu(AXR-ACLKRX) valid before McASP[x]_ACLKR and
McASP[x]_ACLKX
ACLKR and
ACLKX ext in
ACLKR and
ACLKX ext out
4
6
ACLKR and
ACLKX int
-1
-1
Hold time, McASP[x]_AXR input
th(ACLKRX-AXR) valid after McASP[x]_ACLKR and
McASP[x]_ACLKX
ACLKR and
ACLKX ext in
1.6
1.6
2.3
2.3
ACLKR and
ACLKX ext out
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in nano seconds (ns).
(3) R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
221
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
2
1
2
McASP[x]_ACLKR/X (Falling Edge Polarity)
McASP[x]_AHCLKR/X (Rising Edge Polarity)
4
4
3
McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
6
5
McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
8
7
McASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-104. McASP Input Timing
222
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-88. Switching Characteristics for McASP(1)
(see Figure 5-105)
OPP100
MIN
OPP50
MIN
NO.
UNIT
MAX
MAX
Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
9
tc(AHCLKRX)
20(2)
38.46
0.5P - 2.5(3)
38.46
ns
ns
ns
ns
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
10 tw(AHCLKRX)
11 tc(ACLKRX)
12 tw(ACLKRX)
0.5P - 2.5(3)
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
20
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
0.5P - 2.5(3)
0.5P - 2.5(3)
0
ACLKR and
ACLKX int
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
0
2
7.25
14
8.5
18
ACLKR and
ACLKX ext in
2.7
McASP[x]_AFSX output valid
13 td(ACLKRX-AFSRX)
ns
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to ACLKR and
McASP[x]_AFSR and
McASP[x]_AFSX output valid with
Pad Loopback
ACLKX ext
out
2
14
2.7
18
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid
ACLKX int
0
2
7.25
14
0
8.5
18
ACLKX ext in
2.7
14 td(ACLKX-AXR)
ns
ns
Delay time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output valid with Pad Loopback
ACLKX ext
out
2
14
2.7
18
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance
ACLKX int
0
2
7.25
14
0
8.5
18
ACLKX ext in
2.7
15 tdis(ACLKX-AXR)
Disable time, McASP[x]_ACLKX
transmit edge to McASP[x]_AXR
output high impedance with Pad
Loopback
ACLKX ext
out
2
14
2.7
18
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) 50 MHz
(3) P = AHCLKR and AHCLKX period.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
223
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
10
10
9
McASP[x]_ACLKR/X (Falling Edge Polarity)
McASP[x]_AHCLKR/X (Rising Edge Polarity)
12
11
12
McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
13
13
13
McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
McASP[x]_AXR[x] (Data Out/Transmit)
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-105. McASP Output Timing
224
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.13 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM437x ARM
Cortex-A9 Microprocessors (MPUs) Technical Reference Manual.
5.13.13.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for
any McSPI and any channel (n).
5.13.13.1.1 McSPI—Slave Mode
Table 5-89. McSPI Timing Conditions—Slave Mode
TIMING CONDITION PARAMETER
MIN
MAX UNIT
Input Conditions
tr
Input signal rise time
5
5
ns
ns
tf
Input signal fall time
Output Condition
Cload
Output load capacitance
20
pF
Table 5-90. Timing Requirements for McSPI Input Timings—Slave Mode
(see Figure 5-106)
OPP100
MIN
OPP50
NO.
UNIT
MAX
MIN
MAX
1
2
3
tc(SPICLK)
Cycle time, SPI_CLK
62.5
0.45P(1)
0.45P(1)
83.2
ns
ns
ns
tw(SPICLKL)
tw(SPICLKH)
Typical Pulse duration, SPI_CLK low
Typical Pulse duration, SPI_CLK high
0.45P(1)
0.45P(1)
0.45P(1)
0.45P(1)
0.45P(1)
0.45P(1)
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK
active edge(2)(3)
4
5
tsu(SIMO-SPICLK)
th(SPICLK-SIMO)
tsu(CS-SPICLK)
th(SPICLK-CS)
12
13
13
ns
ns
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
active edge(2)(3)
12
Setup time, SPI_CS valid before SPI_CLK first
edge(2)
Hold time, SPI_CS valid after SPI_CLK last edge(2)
8
9
12
12
13
13
ns
ns
(1) P = SPI_CLK period.
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-91. Switching Characteristics for McSPI Output Timings—Slave Mode
(see Figure 5-107)
OPP100
MIN
OPP50
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Delay time, SPI_CLK active edge to
SPI_D[x] (SOMI) transition(1)(2)
6
7
td(SPICLK-SOMI)
td(CS-SOMI)
17
0
19
ns
ns
Delay time, SPI_CS active edge to SPI_D[x]
(SOMI) transition(2)
26
29
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
225
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[x] (In)
1
1
3
3
8
2
2
9
POL=0
SPI_SCLK (In)
POL=1
SPI_SCLK (In)
4
5
4
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
SPI_SCLK (In)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (In)
4
4
5
5
SPI_D[x] (SIMO, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-106. SPI Slave Mode Receive Timing
226
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
PHA=0
EPOL=1
SPI_CS[x] (In)
1
1
3
8
2
2
9
POL=0
POL=1
SPI_SCLK (In)
3
SPI_SCLK (In)
6
7
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (In)
SPI_SCLK (In)
1
1
3
2
8
2
3
9
POL=0
POL=1
SPI_SCLK (In)
6
6
6
6
SPI_D[x] (SOMI, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-107. SPI Slave Mode Transmit Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
227
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.13.1.2 McSPI—Master Mode
Table 5-92. McSPI Timing Conditions—Master Mode
LOW LOAD
MIN
HIGH LOAD
MIN
TIMING CONDITION PARAMETER
UNIT
MAX
MAX
Input Conditions
tr
Input signal rise time
Input signal fall time
4
4
8
8
ns
ns
tf
Output Condition
Cload
Output load capacitance
5
25
pF
Table 5-93. Timing Requirements for McSPI Input Timings—Master Mode
(see Figure 5-108)
OPP100
LOW LOAD HIGH LOAD
OPP50
NO.
LOW LOAD
HIGH LOAD
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, SPI_D[x]
(SOMI) valid before
SPI_CLK active edge(2)
(1)
4
5
tsu(SOMI-SPICLK)
3
4.5
4.5
4.5
ns
ns
Hold time, SPI_D[x]
(SOMI) valid after
(1)
th(SPICLK-SOMI)
6
6
6
6
SPI_CLK active edge(2)
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-94. Switching Characteristics for McSPI Output Timings—Master Mode
(see Figure 5-109)
OPP100
OPP50
NO.
PARAMETER
LOW LOAD
MIN
HIGH LOAD
MIN
LOW LOAD
MIN
HIGH LOAD
MIN MAX
UNIT
MAX
MAX
MAX
1
2
tc(SPICLK)
Cycle time, SPI_CLK
20.8
41.6
41.6
41.6
ns
ns
Typical Pulse duration,
SPI_CLK low
tw(SPICLKL)
0.45P(1) 0.45P(1)
0.45P(1) 0.45P(1)
0.45P(1) 0.55P(1)
0.45P(1) 0.55P(1)
0.45P(1) 0.45P(1)
0.45P(1) 0.45P(1)
0.45P(1) 0.45P(1)
0.45P(1) 0.45P(1)
Typical Pulse duration,
SPI_CLK high
tw(SPICLKH)
ns
3
tr(SPICLK)
tf(SPICLK)
Rising time, SPI_CLK
Falling time, SPI_CLK
3.5
3.5
3.5
3.5
3.5
3.5
3.82
3.44
ns
ns
Delay time, SPI_CLK active
edge to SPI_D[x] (SIMO)
transition(2)
td(SPICLK-
6
7
-1
4.5
4.5
-1
6.5
6.5
0
6.5
6.5
0
6.5
6.5
ns
ns
SIMO)
Delay time, SPI_CS active
edge to SPI_D[x] (SIMO)
transition(2)
td(CS-SIMO)
Mode 1
A - 4.2(4)
B - 4.2(5)
B - 4.2(5)
A - 4.2(4)
A - 4.2(4)
B - 4.2(5)
B - 4.2(5)
A - 4.2(4)
A - 5.2(4)
B - 5.2(5)
B - 5.2(5)
A - 5.2(4)
A - 5.2(4)
B - 5.2(5)
B - 5.2(5)
A - 5.2(4)
ns
ns
ns
ns
and 3(3)
Delay time, SPI_CS
td(CS-SPICLK) active to SPI_CLK
first edge
8
9
Mode 0
and 2(3)
Mode 1
and 3(3)
Delay time,
td(SPICLK-CS) SPI_CLK last edge
to SPI_CS inactive
Mode 0
and 2(3)
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
–
–
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
228
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
(4) Case P = 20.8 ns, A = (TCS+1)*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS+0.5)*Fratio*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
(5) B = (TCS+0.5)*TSPICLKREF*Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even≥2).
PHA=0
EPOL=1
SPI_CS[x] (Out)
1
3
8
2
3
9
POL=0
POL=1
SPI_SCLK (Out)
1
2
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
SPI_SCLK (Out)
1
2
1
3
3
2
8
9
POL=0
POL=1
SPI_SCLK (Out)
4
4
5
5
SPI_D[x] (SOMI, In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-108. SPI Master Mode Receive Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
229
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
PHA=0
EPOL=1
SPI_CS[x] (Out)
1
1
3
2
8
2
3
9
POL=0
SPI_SCLK (Out)
POL=1
SPI_SCLK (Out)
6
7
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (Out)
SPI_SCLK (Out)
1
3
2
8
2
3
9
POL=0
POL=1
1
SPI_SCLK (Out)
6
6
6
6
SPI_D[x] (SIMO, Out)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 5-109. SPI Master Mode Transmit Timing
230
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.14 Quad Serial Port Interface (QSPI)
The Quad SPI (QSPI) module allows single, dual or quad read access to external SPI devices. This
module provides a memory mapped register interface, which provides a direct interface to access data
from external SPI devices and to simplify software requirements. It functions as a master only. There is
one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash
memories.
General SPI features:
•
•
•
•
•
•
Programmable clock divider
Six pin interface (QSPI_CLK, QSPI_D0, QSPI_D1,QSPI_D2,QSPI_D3, QSPI_CS0)
One external chip select signal
Support for 3-, 4- or 6-pin SPI interface
Programmable CS0 to DATA_OUT delay from 0 to 3 QSPI_CLKs
Only supports SPI MODE 3
NOTE
For more information, see the Quad Serial Port Interface section of the AM437x ARM
Cortex-A9 Microprocessors (MPUs) Technical Reference Manual.
Table 5-95 displays the switching characteristics for the Quad SPI module.
Table 5-95. QSPI Switching Characteristics
(see Figure 5-110 and Figure 5-111)
OPP100
OPP50
MIN
20.8(1)
9.77(1)
NO.
PARAMETER
MIN
20.8(1)
9.77(1)
MAX
MAX
UNIT
ns
1
2
3
4
tc(QSPI_CLK)
Cycle time, QSPI_CLK
tw(QSPI_CLKL)
Pulse duration, QSPI_CLK low
ns
tw(QSPI_CLKH) Pulse duration, QSPI_CLK high
9.77(1)
9.77(1)
ns
td(CS-QSPI_CLK) Delay time, QSPI_CSn active edge to
QSPI_CLK transition
M*P+5(2)(3)
M*P+5(2)(3)
ns
5
6
7
8
td(QSPI_CLK-
QSPI_CSn)
Delay time, QSPI_CLK transition to
QSPI_CSn inactive edge
M*P+5(2)(3)
M*P+5(2)(3)
ns
ns
ns
ns
td(QSPI_CLK-D1) Delay time, QSPI_CLK active edge to
QSPI_D[0] transition
0
8.5
0
5.5
0
8.5
0
5.5
tsu(D-QSPI_CLK) Setup time, QSPI_D[3:0] valid before active
QSPI_CLK edge
th(QSPI_CLK-D) Hold time, QSPI_D[3:0] valid after active
QSPI_CLK edge
(1) Maximum supported frequency is 48 MHz.
(2) P = QSPI_CLK period.
(3) M = Programmable via Data Delay Zero (DD0) register.
QSPI_CSn
5
1
4
3
2
QSPI_CLK
6
6
7
7
min
max
8
Read Data
8
Read Data
Command
n-1
Command
n-2
QSPI_D[3:0]
1
0
Figure 5-110. QSPI Read Active High Polarity
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
231
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
QSPI_CS
5
1
4
3
2
QSPI_CLK
6
6
6
6
min
max
min
max
Command
n-1
Command
n-2
Write Data
Write Data
0
QSPI_D[0]
1
QSPI_D[3:1]
Figure 5-111. QSPI Write Active High Polarity
232
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.15 HDQ/1-Wire Interface (HDQ/1-Wire)
NOTE
For more information, see HDQ/1-Wire Interface chapter of the AM437x ARM Cortex-A9
Microprocessors (MPUs) Technical Reference Manual.
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use one wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
5.13.15.1 HDQ Protocol
Table 5-96 and Table 5-97 assume testing over the recommended operating conditions (see Figure 5-112,
Figure 5-113, Figure 5-114, and Figure 5-115).
Table 5-96. HDQ Timing Requirements
PARAMETER
MIN
190
32
MAX
UNIT
μs
tCYCD
Bit window
tHW1
Reads 1
66
μs
tHW0
Reads 0
Command to host respond time(1)
70
145
320
μs
tRSPS
190
μs
(1) Defined by software
Table 5-97. HDQ Switching Characteristics
PARAMETER
DESCRIPTION
MIN
190
40
MAX
UNIT
μs
tB
Break timing
Break recovery
Bit window
tBR
μs
tCYCH
tDW1
tDW0
190
0.5
86
250
50
μs
Sends 1 (write)
Sends 0 (write)
μs
145
μs
tB
tBR
HDQ
HDQ
HDQ
Figure 5-112. HDQ Break (Reset) Timing
tCYCH
tHW0
tHW1
Figure 5-113. HDQ Read Bit Timing (Data)
tCYCD
tDW0
tDW1
Figure 5-114. HDQ Write Bit Timing (Command/Address or Data)
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
233
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Command_byte_written
0_(LSB)
Data_byte_received
1
tRSPS
Break
7_(MSB)
0_(LSB)
1
6
6
HDQ
Figure 5-115. HDQ Communication Timing
5.13.15.2 1-Wire Protocol
Table 5-98 and Table 5-99 assume testing over the recommended operating conditions (see Figure 5-116,
Figure 5-117, and Figure 5-118).
Table 5-98. HDQ/1-Wire Timing Requirements—1-Wire Mode
PARAMETER
tPDH
MIN
15
MAX
60
UNIT
μs
Presence pulse delay high
Presence pulse delay low
Read bit-zero time
tPDL
60
240
60
μs
tRDV + tREL
μs
Table 5-99. HDQ/1-Wire Switching Characteristics—1-Wire Mode
PARAMETER
tRSTL
DESCRIPTION
MIN
480
480
60
1
MAX
UNIT
μs
Reset time low
Reset time high
Bit cycle time
960
tRSTH
μs
tSLOT
120
15
μs
tLOW1
Write bit-one time
Write bit-zero time
Recovery time
μs
tLOW0
60
1
120
μs
tREC
μs
tLOWR
Read bit strobe time
1
15
μs
tRSTH
tPDL
tRTSL
tPDH
1-WIRE
Figure 5-116. 1-Wire Break (Reset) Timing
tSLOT_and_tREC
tRDV_and_tREL
tLOWR
1-WIRE
Figure 5-117. 1-Wire Read Bit Timing (Data)
tSLOT_and_tREC
tLOW0
1-WIRE
tLOW1
Figure 5-118. 1-Wire Write Bit Timing (Command/Address or Data)
234
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.16 Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem (PRU-ICSS)
For more information, see the Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem Interface (PRU-ICSS) section of the AM437x Sitara Processors Technical Reference Manual.
5.13.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
Table 5-100. PRU-ICSS PRU Timing Conditions
TIMING CONDITION PARAMETER
MIN
MAX
UNIT
Output Condition
Cload
Capacitive load for each bus line
3
30
pF
5.13.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
Table 5-101. PRU-ICSS PRU Timing Requirements - Direct Input Mode
(see Figure 5-119)
NO.
MIN
2*P(1)
1.00
MAX
UNIT
1
tw(GPI)
tr(GPI)
tf(GPI)
Pulse width, GPI
ns
Rise time, GPI
3.00
3.00
5.00
2
3
ns
ns
Fall time, GPI
Internal skew between GPI[n:0] signals(2)
1.00
tsk(GPI)
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
(2) n = 16, 11 for PRU-ICSS1 and 19 for PRU-ICSS0
2
1
GPI[m:0]
3
Figure 5-119. PRU-ICSS PRU Direct Input Timing
Table 5-102. PRU-ICSS PRU Switching Requirements - Direct Output Mode
(see Figure 5-120)
NO.
MIN
MAX
UNIT
1
2
3
tw(GPO)
tr(GPO)
tf(GPO)
tsk(GPO)
Pulse width, GPO
2*P(1)
ns
Rise time, GPO
1.00
3.00
3.00
5.00
ns
ns
Fall time, GPO
Internal skew between GPO[n:0] signals(2)
1.00
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
(2) n = 11 for PRU-ICSS1 and 19 for PRU-ICSS0
2
1
GPO[n:0]
3
Figure 5-120. PRU-ICSS PRU Direct Output Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
235
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
Table 5-103. PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
(see Figure 5-121 and Figure 5-122)
NO.
1
MIN
20.00
10.00
10.00
1.00
1.00
4.00
0
MAX
UNIT
ns
tc(CLOCKIN)
Cycle time, CLOCKIN
2
tw(CLOCKIN_L)
tw(CLOCKIN_H)
tr(CLOCKIN)
Pulse duration, CLOCKIN low
Pulse duration, CLOCKIN high
Rising time, CLOCKIN
ns
3
ns
4
3.00
3.00
ns
5
tf(CLOCKIN)
Falling time, CLOCKIN
ns
6
tsu(DATAIN-CLOCKIN)
th(CLOCKIN-DATAIN)
tr(DATAIN)
Setup time, DATAIN valid before CLOCKIN
Hold time, DATAIN valid after CLOCKIN
Rising time, DATAIN
ns
7
ns
1.00
1.00
3.00
3.00
8
ns
tf(DATAIN)
Falling time, DATAIN
1
3
5
4
2
CLOCKIN
DATAIN
7
6
8
Figure 5-121. PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode
1
3
4
5
2
CLOCKIN
DATAIN
7
6
8
Figure 5-122. PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode
5.13.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
Table 5-104. PRU-ICSS PRU Timing Requirements - Shift In Mode
(see Figure 5-123)
NO.
MIN
10.00
0.45*P(1)
MAX
UNIT
ns
1
2
3
4
tc(DATAIN)
tw(DATAIN)
tr(DATAIN)
tf(DATAIN)
Cycle time, DATAIN
Pulse width, DATAIN
Rising time, DATAIN
Falling time, DATAIN
0.55*P(1)
3.00
ns
1.00
ns
1.00
3.00
ns
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
236
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1
2
3
4
DATAIN
Figure 5-123. PRU-ICSS PRU Shift In Timing
Table 5-105. PRU-ICSS PRU Switching Requirements - Shift Out Mode
(see Figure 5-124)
NO.
MIN
MAX
UNIT
ns
1
2
3
4
5
tc(CLOCKOUT)
tw(CLOCKOUT)
tr(CLOCKOUT)
tf(CLOCKOUT)
Cycle time, CLOCKOUT
10.00
0.45*P(1)
1.00
Pulse width, CLOCKOUT
0.55*P(1)
3.00
ns
Rising time, CLOCKOUT
ns
Falling time, CLOCKOUT
1.00
3.00
ns
td(CLOCKOUT-
DATAOUT)
Delay time, CLOCKOUT to DATAOUT Valid
-1.50
3.00
ns
tr(DATAOUT)
Rising time, DATAOUT
Falling time, DATAOUT
1.00
1.00
3.00
3.00
6
ns
tf(DATAOUT)
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
1
2
4
3
CLOCKOUT
DATAOUT
5
6
Figure 5-124. PRU-ICSS PRU Shift Out Timing
5.13.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
Table 5-106. PRU-ICSS Timing Requirements - Sigma Delta Mode
(see Figure 5-125 and Figure 5-126)
NO.
1
MIN
20.00
1.00
MAX
UNIT
ns
tw(SDx_CLK)
tr(SDx_CLK)
Pulse width, SDx_CLK
2
Rising time, SDx_CLK
3.00
3.00
ns
3
tf(SDx_CLK)
Falling time, SDx_CLK
1.00
ns
4
tsu(SDx_D-SDx_CLK)
th(SDx_CLK-SDx_D)
tr(SDx_D)
Setup time, SDx_D valid before SDx_CLK active edge
Hold time, SDx_D valid before SDx_CLK active edge
Rising time, SDx_D
10.00
5.00
ns
5
ns
1.00
3.00
3.00
6
ns
tf(SDx_D)
Falling time, SDx_D
1.00
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
237
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
1
2
3
SDx_CLK
SDx_D
4
5
6
Figure 5-125. PRU-ICSS Sigma Delta Timing - SD_CLK Rising Active Edge
1
3
2
SDx_CLK
SDx_D
4
5
6
Figure 5-126. PRU-ICSS Sigma Delta Timing - SD_CLK Falling Active Edge
5.13.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
Table 5-107. PRU-ICSS Timing Requirements - ENDAT Mode
(see Figure 5-127)
NO.
MIN
MAX
UNIT
ns
1
2
3
tw(ENDATx_IN)
tr(ENDATx_IN)
tf(ENDATx_IN)
Pulse width, ENDATx_IN
Rising time, ENDATx_IN
Falling time, ENDATx_IN
40.00
1.00
1.00
10.00
10.00
ns
ns
Table 5-108. PRU-ICSS Switching Requirements - ENDAT Mode
(see Figure 5-127)
NO.
MIN
MAX
UNIT
ns
4
5
6
7
tw(ENDATx_CLK)
tr(ENDATx_CLK)
tf(ENDATx_CLK)
Pulse width, ENDATx_CLK
20.00
1.00
Rising time, ENDATx_CLK
3.00
3.00
ns
Falling time, ENDATx_CLK
1.00
ns
td(ENDATx_OUT-
ENDATx_CLK)
Delay time, ENDATx_CLK fall to ENDATx_OUT
-10.00
10.00
ns
tr(ENDATx_OUT)
Rising time, ENDATx_OUT
1.00
1.00
3.00
3.00
8
9
ns
ns
tf(ENDATx_OUT)
Falling time, ENDATx_OUT
td(ENDATx_OUT_EN-
Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN
-10.00
10.00
ENDATx_CLK)
238
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
3
2
ENDATx_IN
1
4
5
6
ENDATx_CLK
ENDATx_OUT
8
ENDATx_OUT_EN
9
Figure 5-127. PRU-ICSS ENDAT Timing
5.13.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
Table 5-109. PRU-ICSS ECAT Timing Conditions
TIMING CONDITION PARAMETER
MIN
MAX
UNIT
Output Condition
Cload
Capacitive load for each bus line
30
pF
5.13.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
Table 5-110. PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
(see Figure 5-128)
NO.
1
MIN
100.00
1.00
MAX
UNIT
ns
tw(EDIO_LATCH_IN)
tr(EDIO_LATCH_IN)
tf(EDIO_LATCH_IN)
Pulse width, EDIO_LATCH_IN
Rising time, EDIO_LATCH_IN
Falling time, EDIO_LATCH_IN
2
3.00
3.00
ns
3
1.00
ns
4
tsu(EDIO_DATA_IN-
EDIO_LATCH_IN)
th(EDIO_LATCH_IN-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before
EDIO_LATCH_IN active edge
20.00
ns
5
6
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN
active edge
20.00
ns
ns
tr(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
tf(EDIO_DATA_IN)
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
239
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
2
3
EDIO_LATCH_IN
1
4
5
EDIO_DATA_IN[7:0]
6
Figure 5-128. PRU-ICSS ECAT Input Validated With LATCH_IN Timing
Table 5-111. PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
(see Figure 5-129)
NO.
1
MIN
100.00
1.00
MAX
UNIT
ns
tw(EDC_SYNCx_OUT)
tr(EDC_SYNCx_OUT)
tf(EDC_SYNCx_OUT)
Pulse width, EDC_SYNCx_OUT
Rising time, EDC_SYNCx_OUT
Falling time, EDC_SYNCx_OUT
2
3.00
3.00
ns
3
1.00
ns
4
tsu(EDIO_DATA_IN-
EDC_SYNCx_OUT)
th(EDC_SYNCx_OUT-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before
EDC_SYNCx_OUT active edge
24.50
ns
5
6
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT
active edge
22.00
ns
ns
tr(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
tf(EDIO_DATA_IN)
2
3
EDC_SYNCx_OUT
1
4
5
EDIO_DATA_IN[7:0]
6
Figure 5-129. PRU-ICSS ECAT Input Validated With SYNCx Timing
240
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-112. PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
(see Figure 5-130)
NO.
1
MIN
4*P(1)
1.00
MAX
5*P(1)
3.00
UNIT
ns
tw(EDIO_SOF)
tr(EDIO_SOF)
tf(EDIO_SOF)
Pulse duration, EDIO_SOF
Rising time, EDIO_SOF
Falling time, EDIO_SOF
2
ns
3
1.00
3.00
ns
4
tsu(EDIO_DATA_IN-
EDIO_SOF)
Setup time, EDIO_DATA_IN valid before EDIO_SOF
active edge
20.00
ns
5
6
th(EDIO_SOF-EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDIO_SOF active
edge
20.00
ns
ns
tr(EDIO_DATA_IN)
tf(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN
Falling time, EDIO_DATA_IN
1.00
1.00
3.00
3.00
(1) P = PRU-ICSS IEP clock source period.
2
3
EDIO_SOF
1
4
5
EDIO_DATA_IN[7:0]
6
Figure 5-130. PRU-ICSS ECAT Input Validated With SOF
Table 5-113. PRU-ICSS ECAT Timing Requirements - LATCHx_IN
(see Figure 5-131)
NO.
MIN
3*P(1)
MAX
UNIT
ns
1
2
3
tw(EDC_LATCHx_IN)
tr(EDC_LATCHx_IN)
tf(EDC_LATCHx_IN)
Pulse duration, EDC_LATCHx_IN
Rising time, EDC_LATCHx_IN
Falling time, EDC_LATCHx_IN
1.00
3.00
3.00
ns
1.00
ns
(1) P = PRU-ICSS IEP clock source period.
2
3
EDC_LATCHx_IN
1
Figure 5-131. PRU-ICSS ECAT LATCHx_IN Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
241
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-114. PRU-ICSS ECAT Switching Requirements - Digital IOs
NO.
1
MIN
14*P(1)
1.00
MAX
32*P(1)
UNIT
ns
tw(EDIO_OUTVALID)
tr(EDIO_OUTVALID)
tf(EDIO_OUTVALID)
Pulse duration, EDIO_OUTVALID
Rising time, EDIO_OUTVALID
2
3.00
ns
3
Falling time, EDIO_OUTVALID
1.00
3.00
ns
4
td(EDIO_OUTVALID-
EDIO_DATA_OUT)
tr(EDIO_DATA_OUT)
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
0.00
18*P(1)
ns
5
6
7
Rising time, EDIO_DATA_OUT
Falling time, EDIO_DATA_OUT
EDIO_DATA_OUT skew
1.00
1.00
3.00
3.00
8.00
ns
ns
ns
tf(EDIO_DATA_OUT)
tsk(EDIO_DATA_OUT)
(1) P = PRU-ICSS IEP clock source period.
5.13.16.3 PRU-ICSS MII_RT and Switch
Table 5-115. PRU-ICSS MII_RT Switch Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX
UNIT
Input Conditions
tr
tf
Input signal rise time
Input signal fall time
1(1)
1(1)
5(1)
5(1)
ns
ns
Output Condition
CLOAD
Output load capacitance
20
pF
(1) Except when specified otherwise.
5.13.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
Table 5-116. PRU-ICSS MDIO Timing Requirements - MDIO_DATA
(see Figure 5-132)
NO.
MIN
90
0
TYP
MAX
UNIT
ns
1
2
tsu(MDIO-MDC) Setup time, MDIO valid before MDC high
th(MDIO-MDC) Hold time, MDIO valid from MDC high
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
Figure 5-132. PRU-ICSS MDIO_DATA Timing - Input Mode
Table 5-117. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
(see Figure 5-133)
NO.
MIN
400
160
160
TYP
MAX
UNIT
ns
1
2
3
4
tc(MDC)
tw(MDCH)
tw(MDCL)
tt(MDC)
Cycle time, MDC
Pulse duration, MDC high
Pulse duration, MDC low
Transition time, MDC
ns
ns
5
ns
242
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1
4
2
3
MDIO_CLK
4
Figure 5-133. PRU-ICSS MDIO_CLK Timing
Table 5-118. PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
(see Figure 5-134)
NO.
MIN
TYP
MAX
UNIT
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
10
390
ns
1
MDIO_CLK (Output)
MDIO_DATA (Output)
Figure 5-134. PRU-ICSS MDIO_DATA Timing - Output Mode
5.13.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
Table 5-119. PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
(see Figure 5-135)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
40.004
26
1
2
3
4
tc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Cycle time, RX_CLK
ns
ns
ns
ns
Pulse Duration, RX_CLK high
Pulse Duration, RX_CLK low
Transition time, RX_CLK
140
260
14
26
3
3
1
4
2
3
MII_RXCLK
4
Figure 5-135. PRU-ICSS MII_RXCLK Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
243
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-120. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
(see Figure 5-136)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
399.96
140
MAX
400.04
260
MIN
39.996
14
MAX
1
2
3
4
tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Cycle time, TX_CLK
40.004
ns
ns
ns
ns
Pulse Duration, TX_CLK high
Pulse Duration, TX_CLK low
Transition time, TX_CLK
26
26
3
140
260
14
3
1
4
2
3
MII_TXCLK
4
Figure 5-136. PRU-ICSS MII_TXCLK Timing
Table 5-121. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
(see Figure 5-137)
NO.
10 Mbps
TYP
100 Mbps
TYP
UNIT
MIN
MAX
MIN
MAX
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
1
2
tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK
tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK
8
8
ns
ns
th(RX_CLK-RXD)
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
1
2
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
Figure 5-137. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
244
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-122. PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
(see Figure 5-138)
10 Mbps
TYP
100 Mbps
TYP
NO.
UNIT
MIN
MAX
MIN
MAX
td(TX_CLK-TXD)
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
1
5
25
5
25 ns
td(TX_CLK-TX_EN)
1
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
Figure 5-138. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing
5.13.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
Table 5-123. Timing Requirements for PRU-ICSS UART Receive
(see Figure 5-139)
NO.
MIN
0.96U(1)
MAX
1.05U(1)
UNIT
3
tw(RX)
Pulse width, receive start, stop, data bit
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-124. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART
Transmit
(see Figure 5-139)
NO.
1
MIN
0
U - 2(1)
MAX
12
U + 2(1)
UNIT
MHz
ns
fbaud(baud)
tw(TX)
Maximum programmable baud rate
2
Pulse width, transmit start, stop, data bit
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UART_TXD
Data Bits
5
4
Start
Bit
UART_RXD
Data Bits
Figure 5-139. PRU-ICSS UART Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
245
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.17 Multimedia Card (MMC) Interface
For more information, see the Multimedia Card (MMC) section of the AM437x ARM Cortex-A9
Microprocessors (MPUs) Technical Reference Manual.
5.13.17.1 MMC Electrical Data and Timing
Table 5-125. MMC Timing Conditions
TIMING CONDITION PARAMETER
MIN
TYP
MAX UNIT
Input Conditions
tr
tf
Input signal rise time
Input signal fall time
1
1
5
5
ns
ns
Output Condition
Cload
Output load capacitance
3
30
pF
Table 5-126. Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
(see Figure 5-140)
OPP50/OPP100
NO.
1.8 V
TYP
3.3 V
TYP
UNIT
MIN
MAX
MIN
MAX
Setup time, MMC_CMD valid before
MMC_CLK rising clock edge
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
4.1
4.1
ns
ns
ns
ns
Hold time, MMC_CMD valid after
MMC_CLK rising clock edge
1.5
4.1
1.5
1.5
4.1
1.5
Setup time, MMC_DATx valid before
MMC_CLK rising clock edge
Hold time, MMC_DATx valid after
MMC_CLK rising clock edge
Table 5-127. Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
(see Figure 5-140)
OPP50/OPP100
NO.
1.8 V
TYP
3.3 V
TYP
UNIT
MIN
MAX
MIN
MAX
Setup time, MMC_CMD valid before
MMC_CLK rising clock edge
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
4.1
4.1
3.76
4.1
ns
ns
ns
ns
Hold time, MMC_CMD valid after
MMC_CLK rising clock edge
2.55
4.1
Setup time, MMC_DATx valid before
MMC_CLK rising clock edge
Hold time, MMC_DATx valid after
MMC_CLK rising clock edge
2.55
3.76
246
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
1
2
MMC[x]_CLK (Output)
MMC[x]_CMD (Input)
MMC[x]_DAT[7:0] (Inputs)
3
4
Figure 5-140. MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
247
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-128. Switching Characteristics for MMC[x]_CLK
(see Figure 5-141)
STANDARD MODE
MIN TYP MAX
HIGH-SPEED MODE
MIN TYP MAX
NO.
PARAMETER
UNIT
fop(CLK)
Operating frequency, MMC_CLK
Operating period: MMC_CLK
24
48 MHz
ns
tcop(CLK)
41.7
20.8
5
fid(CLK)
Identification mode frequency, MMC_CLK
Identification mode period: MMC_CLK
Pulse duration, MMC_CLK low
400
400 kHz
ns
tcid(CLK)
2500
2500
(1)
(1)
6
7
8
9
tw(CLKL)
tw(CLKH)
tr(CLK)
(0.5*P) - tf(CLK)
(0.5*P) - tf(CLK)
ns
(1)
(1)
Pulse duration, MMC_CLK high
Rise time, All Signals (10% to 90%)
Fall time, All Signals (10% to 90%)
(0.5*P) - tr(CLK)
(0.5*P) - tr(CLK)
ns
2.2
2.2
2.2 ns
2.2 ns
tf(CLK)
(1) P = MMC_CLK period.
5
6
7
8
9
MMC[x]_CLK (Output)
Figure 5-141. MMC[x]_CLK Timing
Table 5-129. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
(see Figure 5-142)
OPP50/OPP100
NO.
PARAMETER
1.8 V
TYP
3.3 V
TYP
UNIT
MIN
MAX
MIN
MAX
Delay time, MMC_CLK falling clock
edge to MMC_CMD transition
10 td(CLKL-CMD)
11 td(CLKL-DAT)
-4
14
-4
-4
17.5
ns
ns
Delay time, MMC_CLK falling clock
edge to MMC_DATx transition
-4
14
17.5
10
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
11
Figure 5-142. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—HSPE=0
248
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Table 5-130. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
(see Figure 5-143)
OPP50/OPP100
1.8 V
TYP
3.3 V
TYP
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Delay time, MMC_CLK rising clock
edge to MMC_CMD transition
12 td(CLKL-CMD)
13 td(CLKL-DAT)
0.8
7.4
0.8
0.8
7.4
ns
ns
Delay time, MMC_CLK rising clock
edge to MMC_DATx transition
0.8
7.4
7.4
12
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
13
Figure 5-143. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—HSPE=1
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
249
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
5.13.18 Universal Asynchronous Receiver/Transmitter (UART)
For more information, see the Universal Asynchronous Receiver/Transmitter (UART) section of the
AM437x ARM Cortex-A9 Microprocessors (MPUs) Technical Reference Manual.
5.13.18.1 UART Electrical Data and Timing
Table 5-131. Timing Requirements for UARTx Receive
(see Figure 5-144)
NO.
MIN
MAX
UNIT
3
tw(RX)
Pulse width, receive start, stop, data bit
0.96U(1)
1.05U(1)
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-132. Switching Characteristics for UARTx Transmit
(see Figure 5-144)
NO.
PARAMETER
Maximum programmable baud rate
Pulse width, transmit start, stop, data bit
MIN
MAX
3.6864
U + 2(1)
UNIT
MHz
ns
1
2
fbaud(baud)
tw(TX)
U - 2(1)
(1) U = UART baud time = 1/programmed baud rate.
2
2
2
Start
Bit
UARTx_TXD
Stop Bit
Data Bits
3
3
3
Start
Bit
UARTx_RXD
Stop Bit
Data Bits
Figure 5-144. UART Timings
250
Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.13.18.2 UART IrDA Interface
The IrDA module operates in three different modes:
•
•
•
Slow infrared (SIR) (≤ 115.2 kbps)
Medium infrared (MIR) (0.576 Mbps and 1.152 Mbps)
Fast infrared (FIR) (4 Mbps).
Figure 5-145 shows the UART IrDA pulse parameters. Table 5-133 and Table 5-134 list the signaling
rates and pulse durations for UART IrDA receive and transmit modes.
Pulse Duration
Pulse Duration
50%
50%
50%
Figure 5-145. UART IrDA Pulse Parameters
Table 5-133. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MIN
MAX
SIR
2.4 kbps
1.41
1.41
1.41
1.41
1.41
1.41
88.55
22.13
11.07
5.96
µs
µs
µs
µs
µs
µs
9.6 kbps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
MIR
4.34
2.23
0.576 Mbps
1.152 Mbps
FIR
297.2
149.6
518.8
258.4
ns
ns
4 Mbps (Single pulse)
4 Mbps (Double pulse)
67
164
289
ns
ns
190
Copyright © 2014–2016, Texas Instruments Incorporated
Specifications
251
Submit Documentation Feedback
Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Table 5-134. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
ELECTRICAL PULSE DURATION
MIN
SIGNALING RATE
UNIT
MAX
SIR
2.4 kbps
78.1
19.5
9.75
4.87
3.25
1.62
78.1
19.5
9.75
4.87
3.25
1.62
µs
µs
µs
µs
µs
µs
9.6 kbps
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
MIR
0.576 Mbps
1.152 Mbps
FIR
414
206
419
211
ns
ns
4 Mbps (Single pulse)
4 Mbps (Double pulse)
123
248
128
253
ns
ns
252
Specifications
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
5.14 Emulation and Debug
5.14.1 IEEE 1149.1 JTAG
5.14.1.1 JTAG Electrical Data and Timing
Table 5-135. Timing Requirements for JTAG
(see Figure 5-146)
OPP100
OPP50
MIN
NO.
UNIT
MIN
60
24
24
3
MAX
MAX
1
tc(TCK)
1a tw(TCKH)
1b tw(TCKL)
Cycle time, TCK
60
24
24
3
ns
ns
ns
ns
ns
ns
ns
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
tsu(TDI-TCKH)
3
4
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
3
8
8
8
8
Table 5-136. Switching Characteristics for JTAG
(see Figure 5-146)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
0
23
0
23
ns
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
Figure 5-146. JTAG Timing
版权 © 2014–2016, Texas Instruments Incorporated
Specifications
253
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
6 Device and Documentation Support
6.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example,
XAM4379xZDN). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZDN), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range, in megahertz (for example, 80 is 800 MHz). 图 6-1
provides a legend for reading the complete device name for any device.
For orderable part numbers of AM437x devices in the ZDN package type, see the Package Option
Addendum of this document, the TI website, or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AM437x Sitara
Processors Silicon Errata.
254
Device and Documentation Support
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
(
)
X
(
)
AM4379
A
ZDN
S
PREFIX
SUFFIX
Blank = Only Public Boot Supported
S = High-Security (AM437xHS) device, Secure Boot Supported
X = Experimental device
Blank = Qualified device
DEVICE(A)
ARM Cortex-A9 MPU:
AM4372
AM4376
AM4377
DEVICE SPEED RANGE
30 = 300-MHZ Cortex-A9
60 = 600-MHz Cortex-A9
80 = 800-MHz Cortex-A9
100 = 1000-MHz Cortex-A9
AM4378
AM4379
TEMPERATURE RANGE
Blank = 0°C to 90°C (commercial junction temperature)
A = –40°C to 105°C (extended junction temperature)
D = –40°C to 90°C (industrial junction temperature)
DEVICE REVISION CODE
A = silicon revision 1.1
B = silicon revision 1.2
PACKAGE TYPE(B)
ZDN = 491-pin plastic BGA, with Pb-free solder balls
A. The device shown in this device nomenclature example is one of several valid part numbers for this family of devices.
For orderable device part numbers, see the Package Option Addendum of this document.
B. BGA = Ball Grid Array.
图 6-1. Device Nomenclature
6.2 Tools and Software
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed below.
Models
AM437x BSDL Model ZDN package BSDL model.
AM437x IBIS Model ZDN package IBIS model.
Design Kits and Evaluation Modules
AM437x Evaluation Module Enables developers to immediately start evaluating the AM437x processor
family (AM4372, AM4376, AM4377, AM4378 and AM4379) and begin building applications
such as portable navigation, patient monitoring, home/building automation, barcode
scanners, portable data terminals and others.
AM437x Industrial Development Kit (IDK) An application development platform for evaluating the
industrial communication and control capabilities of Sitara AM4379 and AM4377 processors
for industrial applications.
AM437x Starter Kit Provides a stable and affordable platform to quickly start evaluation of Sitara ARM
Cortex-A9 AM437x Processors (AM4372, AM4376, AM4378) and accelerate development
for HMI, industrial and networking applications. It is a low-cost development platform based
on the ARM Cortex-A9 processor that is integrated with options such as Dual Gigabit
Ethernet, DDR3L, Camera and Capacitive Touch Screen LCD.
TI Designs
ARM MPU with Integrated BiSS C Master Interface Reference Design Impelementation of BiSS C
Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides
full documentation and source code for Programmable Realtime Unit (PRU).
Sercos III Slave For AM437x Communication Development Platform Reference Design
Combines
the AM437x Sitara processor family from Texas Instruments (TI) and the Sercos III media
access control (MAC) layer into a single system-on-chip (SoC) solution. Targeted for Sercos
III slave communications, the TIDEP0039 allows designers to implement the real-time
Sercos III communication standard for a broad range of industrial automation equipment.
EnDat 2.2 System Reference Design Implements the EnDat 2.2 Master protocol stack and hardware
interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary
encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex
communications using RS485 transceivers and the line termination implemented on the
Sitara AM437x Industrial Development Kit.
版权 © 2014–2016, Texas Instruments Incorporated
Device and Documentation Support
255
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
Acontis EtherCAT Master Stack Reference Design A highly portable software stack that can be used
on various embedded platforms. The EC-Master supports the high performane TI Sitara
MPUs, it provides a sophisticated EtherCAT Master solution which customers can use to
implement EtherCAT communication interface boards, EtherCAT based PLC or motion
control applications.
SPI Master with Signal Path Delay Compensation Reference Design Describes the implementation of
the SPI master protocol with signal path delay compensation on PRU-ICSS. It supports the
32-bit communication protocol of ADS8688 with a SPI clock frequency of up to 16.7MHz.
Isolated Current Shunt and Voltage Measurement Reference Design for Motor Drives Using
AM437x
Uses the AMC130x reinforced isolated delta-sigma modulators along with AM437x Sitara
ARM Cortex-A9 Processor, which implements Sinc filters on PRU-ICSS. The design
provides an ability to evaluate the performance of these measurements: three motor
currents, three inverter voltages, and the DC Link voltage.
Single Chip Drive for Industrial Communications and Motor Control Implements a hardware interface
solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The
platform also allows designers to implement real-time EtherCAT communications standards
in a broad range of industrial automation equipment.
AM437x Low Power Suspend Mode with LPDDR2 Realizes processor power consumption less than 0.1
mW while keeping LPDDR2 memory in self refresh consuming ~ 1.6 mW. The system
solution is comprised of AM437x Sitara processor, LPDDR2 memory and TPS65218 power
management IC and optimized for new low power mode along with support for legacy low
power modes.
AM437x Discrete Power Reference Design Provides flexibility to power designers. This reference
design implementation is a BOM-optimized discrete power solution for the AM437x
processor with a minimal number of discrete ICs and basic feature set. T
Embedded USB 2.0 Reference Design The USB 2.0 reference design guidelines are extremely
important for designers considering USB2.0 electrical compliance testing. The guidelines are
applicable to AM335x and AM437x but also generic to other processors. The approach taken
for these guidelines is highly practical, without complex formulas or theory.
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design Implementation of
HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS).
The two wire interface allows for integration of position feedback wires into motor cable.
Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver
reference design.
Software
Processor SDK for AM437X Sitara Processors - Linux and TI-RTOS Support
A
unified software
platform for TI embedded processors providing easy setup and fast out-of-the-box access to
benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad
portfolio, allowing developers to seamlessly reuse and migrate software across devices.
Programmable Real-time Unit (PRU) Software Support Package An add-on package that provides a
framework and examples for developing software for the Programmable Real-time Unit sub-
system and Industrial Communication Sub-System (PRU-ICSS) in the supported TI
processors.
SYS/BIOS Industrial Software Development Kit (SDK) for Sitara Processors Gives customers the
ability to easily add real-time industrial communications to their design so they can focus on
differentiating their application code.
TI Dual-Mode Bluetooth® Stack Comprised of Single-Mode and Dual-Mode offerings implementing the
Bluetooth 4.0 specification. The Bluetooth stack is fully Bluetooth Special Interest Group
(SIG) qualified, certified and royalty-free, provides simple command line sample applications
to speed development, and upon request has MFI capability.
256
Device and Documentation Support
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
Development Tools
Clock Tree Tool for Sitara ARM Processors Interactive clock tree configuration software that provides
information about the clocks and modules in Sitara devices.
Pin Mux Tool Provides a Graphical User Interface for configuring pin multiplexing settings, resolving
conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C
header/code files that can be imported into software development kits (SDK) or used to
configure customer's custom software. Version 3 of the Pin Mux utility adds the capability of
automatically selecting a mux configuration that satisfies the entered requirements.
Power Estimation Tool (PET) Provides users the ability to gain insight in to the power consumption of
select TI processors. The tool includes the ability for the user to choose multiple application
scenarios and understand the power consumption as well as how advanced power saving
techniques can be applied to further reduce overall power consumption.
XDS200 USB Debug Probe Connects to the target board via a TI 20-pin connector (with multiple
adapters for TI 14-pin, ARM 10-pin and ARM 20-pin) and to the host PC via USB2.0 High
Speed (480Mbps). It also requires a license of Code Composer Studio IDE running on the
host PC.
XDS560v2 System Trace USB and Ethernet Debug Probe Adds system pin trace in its large external
memory buffer. Available for selected TI devices, this external memory buffer captures
device-level information that allows obtaining accurate bus performance activity and
throughput, as well as power management of core and peripherals. Also, all XDS debug
probes support Core and System Trace in all ARM and DSP processors that feature an
Embedded Trace Buffer (ETB).
XDS560v2 System Trace USB Debug Probe Adds system pin trace in its large external memory buffer.
Available for selected TI devices, this external memory buffer captures device-level
information that allows obtaining accurate bus performance activity and throughput, as well
as power management of core and peripherals. Also, all XDS debug probes support Core
and System Trace in all ARM and DSP processors that feature an Embedded Trace Buffer
(ETB).
6.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
AM437x Sitara Processors Silicon Errata
Describes the known exceptions to the functional
specifications for this microprocessor.
Application Reports
High-Speed Interface Layout Guidelines As modern bus interface frequencies scale higher, care must
be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust
solution.
User's Guides
AM437x Sitara Processors Technical Reference Manual Collection of documents providing detailed
information on the device including power, reset, and clock control, interrupts, memory map,
and switch fabric interconnect. Detailed information on the microprocessor unit (MPU)
subsystem as well as a functional description of the peripherals supported is also included.
Discrete Power Solution for AM437x Details the implementation of a BOM-optimized discrete power
solution for the AM437x processor with a minimal number of discrete ICs and basic feature
set. The solution represents a baseline for a discrete power solution that can be extended for
additional features of the AM437x processor.
Powering the AM335x/AM437x with TPS65218 A reference for connectivity between the TPS65218
power management IC and the AM335x or AM437x processor.
版权 © 2014–2016, Texas Instruments Incorporated
Device and Documentation Support
257
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
AM437x GP EVM Hardware User's Guide Describes the hardware architecture of the AM437x
Evaluation Module (EVM) (part number TMDXEVM437X), which is based on the Texas
Instruments (TI) AM437x processor. This EVM is also commonly known as the AM437x
General Purpose (GP) EVM.
White Papers
Highly Integrated industrial Drive to Connect, Control and Communicate Discusses the overall drive
architecture with emphasis on the highly integrated industrial drive solution by Texas
Instruments.
Ensuring Real-Time Predictability High-performance processors like ARM Cortex-A cores have an
entirely different set of resources and pro- cessing capabilities than those of real-time
processing cores, like the Programmable Real-Time Unit (PRU) coprocessor in TI’s Sitara
processors.
Mainline Linux Ensures Stability and Innovation Enabling and empowering the rapid development of
new functionality starts at the foundational level of the system’s software environment – that
is, at the level of the Linux kernel – and builds upward from there.
Scalable Solutions for HMI A well designed HMI system decreases that gap between the production
process and operator through an intuitive visualization system, layers of detail to allow for a
bird’s eye view down to the minute details, as well as training material and documentation at
the operators’ fingertips.
Linaro Speeds Development in TI Linux SDKs Linaro’s software is not a Linux distribution; in fact, it is
distribution neutral. The focus of the organization’s 120 engineers is on optimizing base-level
open-source software in areas that interact directly with the silicon such as multimedia,
graphics, power management, the Linux kernel and booting processes.
Getting Started on TI ARM Embedded Processor Development Beginning with an overview of ARM
technology and available processor platforms, this paper will then explore the fundamentals
of embedded design that influence a system’s architecture and, consequently, impact
processor selection.
The Yocto Project: Changing the Way Embedded Linux Software Solutions are Developed Enabling
complex silicon devices such as SoC with operating firmware and application software can
be a challenge for equipment manufacturers who often are more comfortable with hardware
than software issues.
Other Documents
Sitara AM437x Processor With ARM Cortex-A9 Core TI continues to optimize and expand its portfolio
of Sitara processor solutions for the embedded market. With the Sitara AM437x processors
support for the ARM Cortex-A9 core, extending performance by up to 40 percent over the
current Sitara AM335x processor line.
Sitara Processors Using the ARM Cortex-A series of cores, are optimized system solutions that go
beyond the core, delivering products that support rich graphics capabilities, LCD displays
and multiple industrial protocols.
AM437x Evaluation Module Quick Start Guide Designed to help you through the initial setup of the
EVM. This EVM allows you to experience Linux and other operating systems (OSs) that
showcase the AM437x Cortex-A9 processor, 3D graphics and more.
The following documents are related to the processor. Copies of these documents can be obtained
directly from the internet or from your Texas Instruments representative. To determine the revision of the
Cortex-A9 core used on your device, see the device-specific errata.
Cortex-A9 Technical Reference Manual Technical reference manual for the Cortex-A9 processor.
ARM Core Cortex-A9 (AT400/AT401) Errata Notice Provides a list of advisories for the different
revisions of the Cortex-A9 processor. For a copy of this document, contact your TI
representative.
258
Device and Documentation Support
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
www.ti.com.cn
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
6.4 Related Links
表 6-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表 6-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
AM4372
AM4376
AM4377
AM4378
AM4379
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
6.5 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com
中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
6.6 商标
Sitara, E2E are trademarks of Texas Instruments.
NEON is a trademark of ARM Ltd or its subsidiaries.
ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries.
Bluetooth is a registered trademark of Bluetooth SIG.
EtherCAT is a registered trademark of EtherCAT Technology Group.
PowerVR SGX is a trademark of Imagination Technologies Limited.
基于 Linux 的 is a registered trademark of Linus Torvalds.
单线 is a registered trademark of Maxim Integrated Products, Inc.
EtherNet/IP is a trademark of ODVA, Inc.
PROFIBUS, PROFINET are registered trademarks of PROFIBUS & PROFINET International (PI).
All other trademarks are the property of their respective owners.
6.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
6.8 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
版权 © 2014–2016, Texas Instruments Incorporated
Device and Documentation Support
259
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
AM4372, AM4376, AM4377, AM4378, AM4379
ZHCSDC3D –JUNE 2014–REVISED SEPTEMBER 2016
www.ti.com.cn
7 Mechanical, Packaging, and Orderable Information
7.1 Via Channel
The ZDN package has been specially engineered with Via Channel technology. This technology allows
larger than normal PCB via and trace sizes and reduced PCB signal layers to be used in a PCB design
with the 0.65-mm pitch package, and substantially reduces PCB costs. It allows PCB routing in only two
signal layers (four layers total) due to the increased layer efficiency of the Via Channel BGA technology.
注
Via Channel technology implemented on the this package makes it possible to build a
product with a 4-layer PCB, but a 4-layer PCB may not meet system performance goals.
Therefore, system performance using a 4-layer PCB design must be evaluated during
product design.
7.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device. This data is subject to change without notice and without revision of this document.
The following figure is a preliminary package drawing for the ZDN package option.
Note: The ZDN package is shown with a 17-mm × 17-mm array of 491 solder balls with 0.65-mm pitch,
with via channel array (VCA) technology.
260
Mechanical, Packaging, and Orderable Information
版权 © 2014–2016, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM4372 AM4376 AM4377 AM4378 AM4379
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM4372BZDN60
AM4372BZDN80
AM4372BZDNA60
AM4372BZDNA80
AM4376BZDN100
AM4376BZDN80
AM4376BZDNA100
AM4376BZDNA80
AM4376BZDND100
AM4376BZDND30
AM4376BZDND80
AM4377BZDNA100
AM4377BZDNA80
AM4377BZDND100
AM4377BZDND80
AM4378BZDN100
AM4378BZDN80
AM4378BZDNA100
AM4378BZDNA80
AM4378BZDND100
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 90
0 to 90
AM4372BZDN60
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
AM4372BZDN80
AM4372BZDNA60
AM4372BZDNA80
AM4376BZDN100
AM4376BZDN80
AM4376BZDNA100
AM4376BZDNA80
AM4376BZDND100
AM4376BZDND30
AM4376BZDND80
AM4377BZDNA100
AM4377BZDNA80
AM4377BZDND100
AM4377BZDND80
AM4378BZDN100
AM4378BZDN80
AM4378BZDNA100
AM4378BZDNA80
AM4378BZDND100
-40 to 105
-40 to 105
0 to 90
0 to 90
-40 to 105
-40 to 105
-40 to 90
-40 to 90
-40 to 90
-40 to 105
-40 to 105
-40 to 90
-40 to 90
0 to 90
0 to 90
-40 to 105
-40 to 105
-40 to 90
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM4378BZDND80
AM4379BZDNA100
AM4379BZDNA80
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
ZDN
ZDN
ZDN
491
491
491
90
90
90
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 90
-40 to 105
-40 to 105
AM4378BZDND80
AM4379BZDNA100
AM4379BZDNA80
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AM4372BZDN60
AM4372BZDN80
AM4372BZDNA60
AM4372BZDNA80
AM4376BZDN100
AM4376BZDN80
AM4376BZDNA100
AM4376BZDNA80
AM4376BZDND100
AM4376BZDND30
AM4376BZDND80
AM4377BZDNA100
AM4377BZDNA80
AM4377BZDND100
AM4377BZDND80
AM4378BZDN100
AM4378BZDN80
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
491
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
19.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
Device
Package Package Pins SPQ Unit array
Max
L (mm)
W
K0
P1
CL
CW
Name
Type
matrix temperature
(°C)
(mm) (µm) (mm) (mm) (mm)
AM4378BZDNA100
AM4378BZDNA80
AM4378BZDND100
AM4378BZDND80
AM4379BZDNA100
AM4379BZDNA80
ZDN
ZDN
ZDN
ZDN
ZDN
ZDN
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
NFBGA
491
491
491
491
491
491
90
90
90
90
90
90
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
6 X 15
150
150
150
150
150
150
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
315 135.9 7620 19.5
21
21
21
21
21
21
19.2
19.2
19.2
19.2
19.2
19.2
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明