AM5708BCBDJ [TI]
Sitara 处理器：成本经优化的 Arm Cortex-A15 和 DSP、多媒体和安全引导 | CBD | 538 | 0 to 90;
| 型号： | AM5708BCBDJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Sitara 处理器：成本经优化的 Arm Cortex-A15 和 DSP、多媒体和安全引导 | CBD | 538 | 0 to 90 时钟 外围集成电路 |
| 文件： | 总396页 (文件大小：4643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
AM570x Sitara™ 处理器
1 器件概述
1.1 特性
1
• Arm® Cortex®-A15 微处理器子系统
– DMA 支持
• 调试安全
• C66x 浮点超长指令字 (VLIW) 数字信号处理器
(DSP)
– 安全软件控制的调试访问
– 安全感知调试
• 可信执行环境 (TEE) 支持
– 基于 Arm TrustZone™的 TEE
– 可实现隔离的广泛防火墙支持
– 安全 DMA 路径和互联
– 目标代码与 C67x 和 C64x+ 完全兼容
– 每周期最多 32 次 16 x 16 位定点乘法
• 片上 L3 RAM 高达 512KB
• 3 级 (L3) 和 4 级 (L4) 互连
• DDR3/DDR3L 存储器接口 (EMIF) 模块
– 最高支持 DDR-1333 (667MHz)
– 高达 2GB 的单芯片选择
• 2 个双核 Arm® Cortex®-M4 协处理器（IPU1 和
IPU2）
– 安全监视器/计时器/IPC
• 一个视频输入端口 (VIP) 模块
– 支持多达四个复用输入端口
• 通用存储器控制器 (GPMC)
• 增强型直接存储器存取 (EDMA) 控制器
• 以太网子系统
• 十六个 32 位通用计时器
• 32 位 MPU 看门狗计时器
• 五个高速内部集成电路 (I2C) 端口
• HDQ™/ 单线®接口
• 10 个可配置 UART/IrDA/CIR 模块
• 四个多通道串行外设接口 (McSPI)
• 四路 SPI 接口 (QSPI)
• 8 个多通道音频串行端口 (McASP) 模块
• 超高速 USB 3.0 双重角色器件
• 高速 USB 2.0 双重角色器件
• IVA-HD 子系统
– 针对 H.264 编解码器的 4K @ 15fps 编码和解码
支持
– 其他编解码器高达 1080p60
• 显示子系统
– 全高清视频（1920 × 1080p，60fps）
– 多个视频输入和视频输出
– 2D 和 3D 图形
– 具有 DMA 引擎和多达 3 条管线的显示控制器
– HDMI™编码器：兼容 HDMI 1.4a 和 DVI 1.0
• 2 个双核可编程实时单元和工业通信子系统 (PRU-
ICSS)
• 加速器 (BB2D) 子系统
– Vivante®GC320 内核
• 视频处理引擎 (VPE)
• 可用单核 PowerVR™SGX544 3D GPU
• 安全引导支持
– 硬件强制可信根
– 客户可编程的秘钥
– 支持接管保护、IP 保护和防回滚保护
• 加密加速支持
• 四个多媒体卡/安全数字/安全数字输入输出接口
( MMC™/ SD®/SDIO)
• 具有 5Gbps 通道的 PCI Express® 3.0 子系统
– 一个与第 2 代兼容的双通道端口
– 或两个与第 2 代兼容的单通道端口
• 双控制器局域网 (DCAN) 模块
– CAN 2.0B 协议
• MIPI™CSI-2 摄像头串行接口
• 多达 186 个通用 I/O (GPIO) 引脚
• 电源、复位和时钟管理
– 支持加密内核
– AES – 128/192/256 位秘钥大小
– 3DES – 56/112/168 位秘钥大小
– MD5、SHA1
– SHA2 – 224/256/384/512
– 真随机数生成器
• 支持 CTool 技术的片上调试
• 28nm CMOS 技术
• 17mm × 17mm、0.65mm 间距、538 引脚 BGA
(CBD)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRS961
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
1.2 应用
•
•
•
工业通信
•
•
高性能 应用
人机界面 (HMI)
自动化与控制
其他一般用途
1.3 说明
AM570x Sitara™处理器是 Arm 应用 处理器，旨在满足现代嵌入式产品的密集处理需求。
AM570x 器件通过其极具灵活性的全集成混合处理器解决方案，可实现较高的处理性能。此外，这些器件还
将可编程的视频处理功能与高度集成的外设集完美融合。
可编程性通过具有 Arm Neon™扩展和 TI C66x VLIW 浮点 DSP 内核实现。借助 Arm 处理器，开发人员能
够将控制函数与在 DSP 和协处理器上编程的视觉算法分离开来，从而降低系统软件的复杂性。
此外，TI 提供了一整套针对 Arm 和 C66x DSP 的开发工具，其中包括 C 语言编译器、用于简化编程和调度
的 DSP 汇编优化器、可查看源代码执行情况的调试界面等。
每个器件都具有加密加速特性。HS（高安全性）器件上还提供支持的所有其他安全 特性，包括安全引导支
持、调试安全性和可信执行环境支持。有关 HS 器件的更多信息，请联系您的 TI 代表。
器件信息(1)
封装
器件型号
封装尺寸
AM5706CBD
AM5708CBD
FCBGA (538)
FCBGA (538)
17.0mm × 17.0mm
17.0mm × 17.0mm
(1) 有关更多信息，请参阅节 9：机械、封装和可订购信息。
2
器件概述
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
1.4 功能方框图
图 1-1 是器件的功能方框图。
AM570x
Display Subsystem
MPU
IVA HD
(1x Arm
Cortex–A15)
1080p Video
Co-Processor
1x GFX Pipeline
LCD2
LCD3
3x Video Pipeline
Blend / Scale
GPU
BB2D
(1x SGX544 3D)
(GC320 2D)
HDMI 1.4a
IPU1
(2x Cortex–M4)
DSP
(1x C66x
Co-Processor)
Secure Boot
IPU2
(2x Cortex–M4)
CAL
CSI2 x1
Debug
Security
TEE
(HS devices)
EDMA
sDMA
MMU x2
VIP x1
VPE
High-Speed Interconnect
System
Connectivity
Spinlock
Mailbox x13
GPIO x8
Timers x16
WDT
USB 3.0
Dual Mode FS/HS/SS
w/ PHY
PCIeSS x2
PWM SS x3
HDQ
GMAC_SW
KBD
USB 2.0
Dual Mode FS/HS
PHY
PRU-ICSS x2
Program/Data Storage
Serial Interfaces
QSPI
McASP x8
I2C x5
UART x10
McSPI x4
DCAN x2
MMC / SD x4
DMM
EMIF
1x 32-bit
DDR3(L)
512-KB
OCMC_RAM
w/ ECC
GPMC / ELM
(NAND/NOR/
Async)
intro-001
图 1-1. AM570x 方框图
版权 © 2016–2019, Texas Instruments Incorporated
器件概述
3
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图 ........................................... 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 8
Terminal Configuration and Functions.............. 9
4.1 Pin Diagram .......................................... 9
4.2 Pin Attributes ......................................... 9
4.3 Signal Descriptions.................................. 66
4.4 Pin Multiplexing .................................... 102
4.5 Connections for Unused Pins...................... 116
Specifications ......................................... 117
5.1 Absolute Maximum Ratings........................ 118
5.2 ESD Ratings ....................................... 119
5.3 Power on Hours (POH) Limits ..................... 119
5.4 Recommended Operating Conditions ............. 119
5.5 Operating Performance Points..................... 122
5.6 Power Consumption Summary .................... 142
5.7 Electrical Characteristics........................... 142
6.3 MPU................................................ 321
6.4 DSP Subsystem ................................... 324
6.5 PRU-ICSS.......................................... 328
6.6 Memory Subsystem................................ 329
6.7 Interprocessor Communication .................... 332
6.8 Interrupt Controller................................. 333
6.9 EDMA .............................................. 334
6.10 Peripherals ......................................... 335
6.11 On-chip Debug..................................... 352
Applications, Implementation, and Layout ...... 355
7.1 Power Supply Mapping ............................ 355
2
3
4
7
7.2
7.3
7.4
DDR3 Board Design and Layout Guidelines....... 356
High Speed Differential Signal Routing Guidance. 379
Power Distribution Network Implementation
Guidance........................................... 379
5
7.5 Thermal Solution Guidance........................ 379
7.6 Single-Ended Interfaces ........................... 379
7.7 LJCB_REFN/P Connections....................... 381
7.8 Clock Routing Guidelines .......................... 382
Device and Documentation Support.............. 383
8.1 Device Nomenclature .............................. 383
8.2 Tools and Software ................................ 385
8.3 Documentation Support............................ 386
8.4 Related Links ...................................... 386
8.5 Support Resources ................................ 386
8.6 商标 ................................................ 386
8.7 静电放电警告....................................... 387
8.8 Glossary............................................ 387
8
5.8
VPP Specifications for One-Time Programmable
(OTP) eFuses ...................................... 150
Thermal Resistance Characteristics for CBD
5.9
Package............................................ 151
5.10 Timing Requirements and Switching
Characteristics ..................................... 152
6
Detailed Description.................................. 319
6.1 Description ......................................... 319
6.2 Functional Block Diagram ......................... 319
9
Mechanical, Packaging, and Orderable
Information............................................. 388
9.1 Packaging Information ............................. 388
4
内容
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
2 修订历史记录
Changes from May 16, 2019 to November 15, 2019 (from E Revision (May 2019) to F Revision)
Page
•
Added reminders to disable unused pulls and RX pads in 节 4.2, Pin Attributes .......................................... 10
版权 © 2016–2019, Texas Instruments Incorporated
修订历史记录
5
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
3 Device Comparison
表 3-1 shows a comparison between devices, highlighting the differences.
表 3-1. Device Comparison
DEVICE
FEATURES
AM5708
AM5706
Features
AM5708: 142 (0x8E) AM5706: 140 (0x8C)
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value(2)
AM5708-E: 143
(0x8F)
AM5706-E: 141
(0x8D)
Processors/Accelerators
Speed Grades
J
D, J
Arm Single Cortex-A15 Microprocessor (MPU) Subsystem
C66x VLIW DSP
MPU core 0
Yes
Yes
DSP1
BB2D
VOUT1
VOUT2
VOUT3
HDMI
IPU1
BitBLT 2D Hardware Acceleration Engine (BB2D)
Yes
Not Supported(1)
Not Supported(1)
Not Supported(1)
Yes
Yes
Yes
Display Subsystem
Not Supported(1)
Not Supported(1)
Yes
Yes
Arm Dual Cortex-M4 Image Processing Unit (IPU)
IPU2
Image Video Accelarator (IVA)
IVA
Yes
Yes
Not Supported(1)
Not Supported(1)
SGX544 Single-Core 3D Graphics Processing Unit (GPU)
GPU
vin1a
vin1b
vin2a
vin2b
VPE
Yes
Yes
Yes
Yes
Yes
Video Input Port (VIP)
VIP1
Video Processing Engine (VPE)
Program/Data Storage
On-Chip Shared Memory (RAM)
General-Purpose Memory Controller (GPMC)
DDR3/DDR3L Memory Controller
Dynamic Memory Manager (DMM)
Radio Support
OCMC_RAM1
GPMC
512KB
Yes
EMIF1
up to 2GB
Yes
DMM
Audio Tracking Logic (ATL)
ATL
Not Supported(1)
Not Supported(1)
Not Supported(1)
VCP1
VCP2
Viterbi Coprocessor (VCP)
Peripherals
DCAN1
Yes
Yes
Yes
Yes
Controller Area Network (DCAN) Interface
DCAN2
Enhanced DMA (EDMA)
EDMA
System DMA (DMA_SYSTEM)
DMA_SYSTEM
GMAC_SW[0]
GMAC_SW[1]
GPIO
MII, RMII, or RGMII
Ethernet Subsystem (Ethernet SS)
MII, RMII, or RGMII
General-Purpose I/O (GPIO)
Up to 186
Inter-Integrated Circuit Interface (I2C)
I2C
5
System Mailbox Module
MAILBOX
MLB
13
(1)
Media Local Bus Subsystem (MLBSS)
Not Supported
6
Device Comparison
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 3-1. Device Comparison (continued)
DEVICE
FEATURES
AM5708
AM5706
CSI2_0
CSI2_1
McASP1
McASP2
McASP3
McASP4
McASP5
McASP6
McASP7
McASP8
MMC1
1 CLK + 2 Data
Not Supported(1)
16 serializers
16 serializers
4 serializers
4 serializers
4 serializers
4 serializers
4 serializers
2 serializers
1x UHSI 4b
Camera Adaptation Layer (CAL) Camera Serial Interface 2 (CSI2)
Multichannel Audio Serial Port (McASP)
MMC2
1x eMMC 8b
1x SDIO 8b
1x SDIO 4b
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface
(MMC/SD/SDIO)
MMC3
MMC4
Up to two lanes (second lane shared with
PCIe_SS2 and USB1)
PCIe_SS1
PCIe_SS2
PCI Express 3.0 Port with Integrated PHY
Single lane (shared with PCIe_SS1 and
USB1)
PRU-ICSS1
PRU-ICSS2
SATA
Yes
2x Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem (PRU-ICSS)
Yes
Serial Advanced Technology Attachment (SATA)
Real-Time Clock Subsystem (RTCSS)
Multichannel Serial Peripheral Interface (McSPI)
HDQ1W
Not Supported(1)
Not Supported(1)
RTCSS
McSPI
4
HDQ1W
QSPI
Yes
Yes
Yes
Yes
16
Quad SPI (QSPI)
Spinlock Module
SPINLOCK
KBD
Keyboard Controller (KBD)
Timers, General-Purpose
Timer, Watchdog
TIMERS GP
WD TIMER
PWMSS1
PWMSS2
PWMSS3
UART
Yes
Yes
Yes
Yes
10
Pulse-Width Modulation Subsystem (PWMSS)
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus (USB3.0)
USB1 (Super-
Speed, Dual-Role-
Device [DRD])
Yes
USB2 (High-Speed,
Dual-Role-Device
[DRD], with
Yes
embedded HS PHY)
Universal Serial Bus (USB2.0)
USB3 (High-Speed,
OTG2.0, with ULPI)
Not Supported(1)
Not Supported(1)
USB4 (High-Speed,
OTG2.0, with ULPI)
(1) Features noted as “not supported,” must not be used. Their functionality is not supported by TI for this family of devices. These features
are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained
in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.
(2) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the device TRM.
3.1 Related Products
版权 © 2016–2019, Texas Instruments Incorporated
Device Comparison
7
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
Sitara Processors Scalable processors based on Arm® Cortex®-A cores with flexible peripherals,
connectivity & unified software support – perfect for sensors to servers.
TI's Arm Cortex-A15 Advantage The Arm Cortex-A15 processor is proven in a range of different
markets and is an increasingly popular choice in networking infrastructure, delivering high-
performance processing capability combined with low power consumption. The Cortex-A15
processor delivers roughly twice the performance of the Cortex-A9 processor and can
achieve 3.5 DMIPS/MHz.
Sitara Applications Sitara™ processors provide scalable solutions for a wide range of applications from
HMIs and gateways to more complex equipment such as drives and substation automation
equipment. Sitara Arm® processors offer scalability and reliability as well as multi-protocol
support for industrial communication protocols such as EtherCAT, Ethernet/IP and Profinet.
Reference Designs TI provides many reference designs containing ‘building block’ solutions to enable
customers to rapidly development of their unique products and solutions.
Companion Products for AM570x Review products that are frequently purchased or used in conjunction
with this product.
8
Device Comparison
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
4 Terminal Configuration and Functions
4.1 Pin Diagram
图 4-1 shows the ball locations for the 538 plastic ball grid array (PBGA) package and isused in
conjunction with 表 4-1 through 表 4-30 to locate signal names and ball grid numbers.
图 4-1. CBD S-PBGA-N538 Package (Bottom View)
注
The following bottom balls are not pinned out: AE4 / AE7 / AE10 / AE13 / AD5 / AD8 / AD11
/ AD14 / AC7 / AC9 / AC12 / AC14 / AC17 / AB3 / AB4 / AB5 / AB13 / AB14 / AB17 / AB20 /
AB21 / AB22 / AA14 / AA17 / AA22 / Y22 / W3 / W4 / W5 / W6 / V6 / V21 / V22 / V23 / R3 /
R4 / R5 / R6 / R21 / R22 / R23 / P6 / M3 / M4 / M5 / M6 / M21 / M22 / M23 / J3 / J4 / J5 / J6
/ J21 / J22 / J23 / F4 / F5 / F9 / F12 / F15 / F18 / F21 / F22 / E3 / E4 / E5 / E6 / E9 / E12 /
E15 / E18 / E21 / E22 / E23 / D4 / D5 / D9 / D12 / D15 / D18 / D21 / D22 / C9 / C12 / C15 /
C18.
These balls do not exist on the package.
4.2 Pin Attributes
表 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER:This column lists ball numbers on the bottom side associated with each signal on the
bottom.
2. BALL NAME: This column lists mechanical name from package device (name is taken from muxmode
0).
3. SIGNAL NAME:This column lists names of signals multiplexed on each ball (also notice that the name
of the ball is the signal name in muxmode 0).
注
表 4-1 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in 节 4.3, Signal Descriptions.
注
In driver off mode, the buffer is configured in high-impedance.
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
9
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
注
In some cases 表 4-1 may present more than one signal name per muxmode for the same
ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_*
register.
All other signals are virtual functions that present alternate multiplexing options. This virtual
functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
4. PN: This column shows if the functionality is applicable for AM5706 device. Note that the Pin Attributes
table presents a functionality of super set. If the cell is empty it means that the signal is available in all
devices.
–
–
Yes - Functionality is presented in AM5706
No - Functionality is not presented in AM5706
An empty box means Yes.
5. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
注
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
c. An empty box means Not Applicable.
6. TYPE: Signal type and direction:
–
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or Output
D = Open drain
DS = Differential Signaling
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
注
The RX buffer within the pad logic should be disabled on all pins that are not being used as
an input. For more information, see the Control Module / Control Module Functional
Description / PAD Functional Multiplexing and Configuration section in the device TRM.
7. BALL RESET STATE: The state of the terminal at power-on reset:
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
10
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
注
Designs that contain pullup or pulldown resistors, either on the board or in attached devices
that oppose internal pullup or pulldown resistors, that are active while the device is held in
reset, must not remain in reset for long periods of time.
8. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal)
–
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
注
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power, Reset, and Clock Management / PRCM Reset Management Functional
Description section of the Device TRM.
9. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
An empty box means Not Applicable.
10. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
11. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
12. HYS: Indicates if the input buffer is with hysteresis:
–
–
–
Yes: With hysteresis
No: Without hysteresis
An empty box: Not Applicable
注
For more information, see the hysteresis values in 节 5.7, Electrical Characteristics.
13. BUFFER TYPE: Drive strength of the associated output buffer.
An empty box means Not Applicable.
注
For programmable buffer strength:
–
–
The default value is given in 表 4-1.
A note describes all possible values according to the selected muxmode.
14. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
–
–
–
–
–
–
PU: Internal pullup
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
PUx/PDy: Programmable internal pullup and pulldown
PDy: Programmable internal pulldown
An empty box means No pull
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
11
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
注
Internal pullup or pulldown resistors must be disabled when opposed by an external pullup or
pulldown resistor on the board or within an attached device.
15. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
–
–
–
0: Logic 0 driven on the peripheral's input signal port.
1: Logic 1 driven on the peripheral's input signal port.
blank: Pin state driven on the peripheral's input signal port.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
注
Some of the EMIF1 signals have an additional state change at the release of porz. The state
that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_ck, ddr1_odt[0], ddr1_rst.
drive 1 (OFF) for: ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_nck, ddr1_ba[2:0], ddr1_a[15:0],
ddr1_csn[0], ddr1_cke, ddr1_dqm[3:0]
12
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
F8
cap_vbbldo_dsp
cap_vbbldo_dsp
CAP
T7
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
I
G14
F17
U20
K7
G19
L7
V7
G12
G18
AC1
0
0
0
0
0
0
1.8
Yes
LVCMOS PU/PD
CSI2
AD1
AE2
AB2
AC2
AD2
H23
csi2_0_dx1
csi2_0_dx2
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
dcan1_rx
csi2_0_dx1
csi2_0_dx2
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
I
I
I
I
I
1.8
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS PU/PD
CSI2
1.8
LVCMOS PU/PD
CSI2
1.8
LVCMOS PU/PD
CSI2
1.8
LVCMOS PU/PD
CSI2
1.8
LVCMOS PU/PD
CSI2
dcan1_rx
uart8_txd
mmc2_sdwp
hdmi1_cec
gpio1_15
Driver off
0
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Dual
PU/PD
1
0
Voltage
LVCMOS
2
3
No
6
IO
IO
I
14
15
0
H22
dcan1_tx
dcan1_tx
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
1
uart8_rxd
mmc2_sdcd
hdmi1_hpd
gpio1_14
Driver off
2
3
I
No
6
IO
IO
I
14
15
0
AD16
AD21
ddr1_casn
ddr1_ck
ddr1_casn
O
PU
PD
drive 1
(OFF)
1.35/1.5
1.35/1.5
vdds_ddr1 No
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
ddr1_ck
0
O
drive 0
(OFF)
LVCMOS PUx/PDy
DDR
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
13
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
AB18
AE21
AD17
AE17
AE18
AC18
AE19
AD19
AB19
AD20
AE20
AA18
AA20
Y21
ddr1_cke
ddr1_cke
ddr1_nck
ddr1_rasn
ddr1_rst
ddr1_wen
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
PU
PU
PU
PD
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
drive 1
(OFF)
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
ddr1_nck
ddr1_rasn
ddr1_rst
ddr1_wen
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 0
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
AC20
AA21
AC21
AC22
AC15
AB15
AC16
AE16
AA16
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
14
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
AB16
AC19
AA23
AC24
AB24
AD24
AB23
AC23
AD23
AE24
AA24
W25
ddr1_ba2
ddr1_ba2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
drive 1
(OFF)
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_csn0
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
O
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
Y23
LVCMOS PUx/PDy
DDR
AD25
AC25
AB25
AA25
W24
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
LVCMOS PUx/PDy
DDR
W23
LVCMOS PUx/PDy
DDR
U25
LVCMOS PUx/PDy
DDR
U24
LVCMOS PUx/PDy
DDR
W21
LVCMOS PUx/PDy
DDR
T22
LVCMOS PUx/PDy
DDR
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
15
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
U22
U23
T21
T23
T25
T24
P21
N21
P22
P23
P24
AE23
W22
U21
P25
AD22
Y24
V24
R24
AE22
Y25
V25
R25
ddr1_d21
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
PU
PU
PD
PD
PD
PD
PU
PU
PU
PU
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1 No
vdds_ddr1
LVCMOS PUx/PDy
DDR
ddr1_d22
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
LVCMOS PUx/PDy
DDR
ddr1_d23
LVCMOS PUx/PDy
DDR
ddr1_d24
LVCMOS PUx/PDy
DDR
ddr1_d25
LVCMOS PUx/PDy
DDR
ddr1_d26
LVCMOS PUx/PDy
DDR
ddr1_d27
LVCMOS PUx/PDy
DDR
ddr1_d28
LVCMOS PUx/PDy
DDR
ddr1_d29
LVCMOS PUx/PDy
DDR
ddr1_d30
LVCMOS PUx/PDy
DDR
ddr1_d31
LVCMOS PUx/PDy
DDR
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
O
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
O
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
O
drive 1
(OFF)
LVCMOS PUx/PDy
DDR
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PU
PU
PU
PU
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
vdds_ddr1
LVCMOS PUx/PDy
DDR
16
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
AD18
Y20
ddr1_odt0
ddr1_odt0
0
0
O
PD
drive 0
(OFF)
1.35/1.5
1.35/1.5
1.8/3.3
vdds_ddr1 No
vdds_ddr1 No
LVCMOS PUx/PDy
DDR
ddr1_vref0
emu0
ddr1_vref0
PWR
OFF
PU
drive 1
(OFF)
LVCMOS
DDR
C21
emu0
0
IO
IO
PU
PU
PD
PD
PD
PU
0
vddshv3
vddshv3
vddshv3
vddshv3
vddshv3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
gpio8_30
14
C22
E14
F14
F13
Y5
emu1
emu1
0
IO
IO
PU
PD
PD
PD
PU
0
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
Yes
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
gpio8_31
14
emu2
emu2
emu3
emu4
2
2
2
O
O
O
15
15
15
15
Dual
Voltage
LVCMOS
emu3
Dual
Voltage
LVCMOS
emu4
Dual
Voltage
LVCMOS
gpio6_10
gpio6_10
0
IO
O
IO
I
Dual
Voltage
LVCMOS
mdio_mclk
i2c3_sda
1
1
1
2
vin2b_hsync1
vin1a_clk0
ehrpwm2A
pr2_mii_mt1_clk
pr2_pru0_gpi0
pr2_pru0_gpo0
gpio6_10
4
9
I
0
0
10
11
12
13
14
15
0
O
I
I
O
IO
I
Driver off
Y6
gpio6_11
gpio6_11
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual
PU/PD
Voltage
LVCMOS
mdio_d
1
1
1
i2c3_scl
2
vin2b_vsync1
vin1a_de0
ehrpwm2B
pr2_mii1_txen
pr2_pru0_gpi1
pr2_pru0_gpo1
gpio6_11
4
9
I
0
10
11
12
13
14
15
O
O
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
17
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
H21
gpio6_14
gpio6_14
mcasp1_axr8
dcan2_tx
uart10_rxd
i2c3_sda
timer1
0
IO
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
IO
IO
I
0
1
1
1
2
3
9
IO
IO
IO
I
10
14
15
0
gpio6_14
Driver off
gpio6_15
mcasp1_axr9
dcan2_rx
uart10_txd
i2c3_scl
K22
gpio6_15
IO
IO
IO
O
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
1
2
3
9
1
timer2
10
14
15
0
gpio6_15
Driver off
gpio6_16
mcasp1_axr10
clkout1
K23
gpio6_16
IO
IO
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
9
timer3
10
14
15
0
gpio6_16
Driver off
gpmc_a0
vin1a_d16
vout3_d16
vin1b_d0
i2c4_scl
M1
gpmc_a0
O
I
PD
PD
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
2
No
3
O
I
6
0
1
1
7
IO
I
uart5_rxd
8
gpio7_3
14
IO
gpmc_a26
gpmc_a16
Driver off
15
I
18
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
M2
L2
L1
gpmc_a1
gpmc_a1
0
O
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
vin1a_d17
vout3_d17
vin1b_d1
i2c4_sda
uart5_txd
gpio7_4
2
I
No
3
O
I
6
0
1
7
IO
O
IO
I
8
14
15
0
Driver off
gpmc_a2
vin1a_d18
vout3_d18
vin1b_d2
uart7_rxd
uart5_ctsn
gpio7_5
gpmc_a2
O
I
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
0
2
No
3
O
I
6
0
1
1
7
I
8
I
14
15
0
IO
I
Driver off
gpmc_a3
qspi1_cs2
vin1a_d19
vout3_d19
vin1b_d3
uart7_txd
uart5_rtsn
gpio7_6
gpmc_a3
O
O
I
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
1
1
0
2
No
3
O
I
6
0
7
O
O
IO
I
8
14
15
0
Driver off
gpmc_a4
qspi1_cs3
vin1a_d20
vout3_d20
vin1b_d4
i2c5_scl
K3
gpmc_a4
O
O
I
PD
PD
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
0
2
No
3
O
I
6
0
1
1
7
IO
I
uart6_rxd
gpio1_26
Driver off
8
14
15
IO
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
19
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
K2
gpmc_a5
gpmc_a5
vin1a_d21
vout3_d21
vin1b_d5
i2c5_sda
uart6_txd
gpio1_27
Driver off
gpmc_a6
vin1a_d22
vout3_d22
vin1b_d6
uart8_rxd
uart6_ctsn
gpio1_28
Driver off
gpmc_a7
vin1a_d23
vout3_d23
vin1b_d7
uart8_txd
uart6_rtsn
gpio1_29
Driver off
gpmc_a8
vin1a_hsync0
vout3_hsync
vin1b_hsync1
timer12
0
O
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
2
I
No
No
No
No
3
O
I
6
0
1
7
IO
O
IO
I
8
14
15
0
J1
gpmc_a6
gpmc_a7
gpmc_a8
O
I
1.8/3.3
1.8/3.3
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
0
2
3
O
I
6
0
1
1
7
I
8
I
14
15
0
IO
I
K1
O
I
Dual
Voltage
LVCMOS
PU/PD
0
2
3
O
I
6
0
7
O
O
IO
I
8
14
15
0
K4
O
I
Dual
Voltage
LVCMOS
PU/PD
0
2
3
O
I
6
0
0
7
IO
IO
IO
I
spi4_sclk
gpio1_30
Driver off
8
14
15
20
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
H1
gpmc_a9
gpmc_a9
0
O
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
vin1a_vsync0
vout3_vsync
vin1b_vsync1
timer11
2
I
No
No
No
3
O
I
6
0
0
7
IO
IO
IO
I
spi4_d1
8
gpio1_31
Driver off
gpmc_a10
vin1a_de0
vout3_de
vin1b_clk1
timer10
14
15
0
J2
gpmc_a10
gpmc_a11
gpmc_a12
O
I
1.8/3.3
1.8/3.3
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
0
2
3
O
I
6
0
0
7
IO
IO
IO
I
spi4_d0
8
gpio2_0
14
15
0
Driver off
gpmc_a11
vin1a_fld0
vout3_fld
vin1b_de1
timer9
L3
O
I
Dual
Voltage
LVCMOS
PU/PD
0
2
3
O
I
6
0
1
7
IO
IO
IO
I
spi4_cs0
gpio2_1
8
14
15
0
Driver off
gpmc_a12
gpmc_a0
vin1b_fld1
timer8
G1
O
O
I
Dual
Voltage
LVCMOS
PU/PD
5
6
0
7
IO
IO
I
spi4_cs1
dma_evt1
gpio2_2
8
1
0
9
14
15
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
21
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
H3
gpmc_a13
gpmc_a13
qspi1_rtclk
timer7
0
O
PD
PD
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
I
7
IO
IO
I
spi4_cs2
dma_evt2
gpio2_3
8
1
0
9
14
15
0
IO
I
Driver off
gpmc_a14
qspi1_d3
timer6
H4
gpmc_a14
O
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
7
spi4_cs3
gpio2_4
8
1
14
15
0
Driver off
gpmc_a15
qspi1_d2
timer5
K6
gpmc_a15
O
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
7
gpio2_5
14
15
0
Driver off
gpmc_a16
qspi1_d0
gpio2_6
K5
G2
F2
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
O
IO
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv11 Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
14
15
0
Driver off
gpmc_a17
qspi1_d1
gpio2_7
O
IO
IO
I
Dual
Voltage
LVCMOS
PU/PD
0
1
14
15
0
Driver off
gpmc_a18
qspi1_sclk
gpio2_8
O
IO
IO
I
Dual
Voltage
LVCMOS
PU/PD
1
14
15
0
Driver off
gpmc_a19
mmc2_dat4
gpmc_a13
vin2b_d0
gpio2_9
A4(10)
O
IO
O
I
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
IO
I
Driver off
22
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
E7(10)
gpmc_a20
gpmc_a20
0
O
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
15
15
1.8/3.3
vddshv11 Yes
vddshv11 Yes
vddshv11 Yes
vddshv11 Yes
vddshv11 Yes
vddshv11 Yes
Dual
Voltage
LVCMOS
PU/PD
1
mmc2_dat5
gpmc_a14
vin2b_d1
gpio2_10
Driver off
gpmc_a21
mmc2_dat6
gpmc_a15
vin2b_d2
gpio2_11
Driver off
gpmc_a22
mmc2_dat7
gpmc_a16
vin2b_d3
gpio2_12
Driver off
gpmc_a23
mmc2_clk
gpmc_a17
vin2b_d4
gpio2_13
Driver off
gpmc_a24
mmc2_dat0
gpmc_a18
vin2b_d5
gpio2_14
Driver off
gpmc_a25
mmc2_dat1
gpmc_a19
vin2b_d6
gpio2_15
Driver off
1
IO
O
I
2
6
0
14
15
0
IO
I
D6(10)
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
O
IO
O
I
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
0
IO
I
C5(10)
O
IO
O
I
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
0
IO
I
B5
O
IO
O
I
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
0
IO
I
D7(10)
O
IO
O
I
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
0
IO
I
C6(10)
O
IO
O
I
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
0
14
15
IO
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
23
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
A5(10)
gpmc_a26
gpmc_a26
mmc2_dat2
gpmc_a20
vin2b_d7
gpio2_16
Driver off
gpmc_a27
mmc2_dat3
gpmc_a21
vin2b_hsync1
gpio2_17
Driver off
gpmc_ad0
vin1a_d0
vout3_d0
gpio1_6
0
O
PD
PD
15
1.8/3.3
vddshv11 Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
IO
O
I
2
6
0
14
15
0
IO
I
B6(10)
gpmc_a27
O
IO
O
I
PD
PD
15
1.8/3.3
vddshv11 Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
2
6
14
15
0
IO
I
F1
E2
E1
C1
D1
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
2
No
No
No
No
No
3
O
IO
I
14
15
0
sysboot0
gpmc_ad1
vin1a_d1
vout3_d1
gpio1_7
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot1
gpmc_ad2
vin1a_d2
vout3_d2
gpio1_8
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot2
gpmc_ad3
vin1a_d3
vout3_d3
gpio1_9
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot3
gpmc_ad4
vin1a_d4
vout3_d4
gpio1_10
sysboot4
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
24
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
D2
B1
B2
C2
D3
A2
B3
gpmc_ad5
gpmc_ad5
0
IO
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
vin1a_d5
vout3_d5
gpio1_11
sysboot5
gpmc_ad6
vin1a_d6
vout3_d6
gpio1_12
sysboot6
gpmc_ad7
vin1a_d7
vout3_d7
gpio1_13
sysboot7
gpmc_ad8
vin1a_d8
vout3_d8
gpio7_18
sysboot8
gpmc_ad9
vin1a_d9
vout3_d9
gpio7_19
sysboot9
gpmc_ad10
vin1a_d10
vout3_d10
gpio7_28
sysboot10
gpmc_ad11
vin1a_d11
vout3_d11
gpio7_29
sysboot11
2
I
No
No
No
No
No
No
No
3
O
IO
I
14
15
0
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
IO
I
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
25
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
C3
C4
A3
B4
H5
gpmc_ad12
gpmc_ad12
vin1a_d12
vout3_d12
gpio1_18
0
IO
OFF
OFF
OFF
OFF
PU
OFF
OFF
OFF
OFF
PU
15
15
15
15
15
1.8/3.3
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
0
2
I
No
No
No
No
3
O
IO
I
14
15
0
sysboot12
gpmc_ad13
vin1a_d13
vout3_d13
gpio1_19
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_advn_ale
IO
I
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot13
gpmc_ad14
vin1a_d14
vout3_d14
gpio1_20
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot14
gpmc_ad15
vin1a_d15
vout3_d15
gpio1_21
IO
I
Dual
Voltage
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot15
gpmc_advn_ale
gpmc_cs6
clkout2
O
O
O
I
Dual
Voltage
LVCMOS
1
2
gpmc_wait1
gpmc_a2
3
1
5
O
O
IO
IO
I
gpmc_a23
timer3
6
7
i2c3_sda
8
1
0
dma_evt2
9
gpio2_23
14
IO
gpmc_a19
Driver off
15
I
26
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
H2
gpmc_ben0
gpmc_ben0
0
O
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
PU/PD
Voltage
LVCMOS
gpmc_cs4
vin2b_de1
timer2
1
O
I
6
7
IO
I
dma_evt3
9
0
gpio2_26
14
IO
gpmc_a21
Driver off
gpmc_ben1
gpmc_cs5
vin2b_clk1
gpmc_a3
vin2b_fld1
timer1
15
0
I
H6
gpmc_ben1
O
O
I
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
1
4
5
O
I
6
7
IO
I
dma_evt4
9
0
gpio2_27
14
IO
gpmc_a22
Driver off
gpmc_clk
gpmc_cs7
clkout1
15
0
I
L4
gpmc_clk
IO
O
O
I
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
1
2
gpmc_wait1
vin2b_clk1
timer4
3
6
I
7
IO
IO
I
i2c3_scl
8
1
0
dma_evt1
9
gpio2_22
14
IO
gpmc_a20
Driver off
15
0
I
F3
A6
gpmc_cs0
gpmc_cs1
gpmc_cs0
gpio2_19
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10 Yes
vddshv11 Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
14
15
0
Driver off
gpmc_cs1
mmc2_cmd
gpmc_a22
vin2b_vsync1
gpio2_18
O
IO
O
I
Dual
Voltage
LVCMOS
1
1
2
6
14
15
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
27
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
G4
gpmc_cs2
gpmc_cs2
qspi1_cs0
0
O
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
IO
IO
gpio2_20
gpmc_a23
gpmc_a13
14
Driver off
gpmc_cs3
qspi1_cs1
vin1a_clk0
vout3_clk
gpmc_a1
15
0
I
G3
gpmc_cs3
O
O
I
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
0
2
No
3
O
O
IO
5
gpio2_21
gpmc_a24
gpmc_a14
14
Driver off
15
0
I
G5
F6
gpmc_oen_ren
gpmc_wait0
gpmc_oen_ren
gpio2_24
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10 Yes
vddshv10 Yes
Dual
Voltage
LVCMOS
PU/PD
14
15
0
Driver off
gpmc_wait0
I
Dual
Voltage
LVCMOS
PU/PD
PU/PD
1
gpio2_28
gpmc_a25
gpmc_a15
14
IO
Driver off
15
0
I
G6
gpmc_wen
gpmc_wen
O
IO
I
PU
PU
15
1.8/3.3
vddshv10 Yes
Dual
Voltage
LVCMOS
gpio2_25
14
15
0
Driver off
AE9
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
No
No
No
No
No
No
No
No
O
O
O
O
O
O
O
O
IO
I
1.8
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
HDMIPHY Pdy
AD10
AE11
AD12
AE12
AD13
AE14
AD15
G22
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8/3.3
vddshv3
Yes
Yes
Dual
PU/PD
Voltage
LVCMOS
I2C
Driver off
15
G23
i2c1_sda
i2c1_sda
Driver off
0
IO
I
1.8/3.3
vddshv3
Dual
PU/PD
Voltage
LVCMOS
I2C
15
28
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
G21
F23
i2c2_scl
i2c2_scl
0
IO
15
1.8/3.3
vddshv3
Yes
Dual
PU/PD
PU/PD
1
Voltage
LVCMOS
I2C
hdmi1_ddc_sda
Driver off
No
No
1
IO
I
15
0
i2c2_sda
i2c2_sda
IO
IO
I
15
1.8/3.3
vddshv3
Yes
Yes
Yes
Dual
1
Voltage
LVCMOS
I2C
hdmi1_ddc_scl
Driver off
1
15
0
AB9
AC8
D16
ljcb_clkn
ljcb_clkn
IO
IO
IO
IO
IO
IO
I
1.8
vdda_pcie
vdda_pcie
vddshv3
LJCB
LJCB
ljcb_clkp
ljcb_clkp
0
1.8
mcasp1_aclkr
mcasp1_aclkr
mcasp7_axr2
i2c4_sda
0
PD
PD
PD
PD
15
15
1.8/3.3
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
0
1
1
10
14
15
0
gpio5_0
Driver off
C16
mcasp1_aclkx
mcasp1_aclkx
vin1a_fld0
i2c3_sda
IO
I
1.8/3.3
vddshv3
Dual
Voltage
LVCMOS
0
0
1
7
10
11
12
13
14
15
0
IO
O
I
pr2_mdio_mdclk
pr2_pru1_gpi7
pr2_pru1_gpo7
gpio7_31
O
IO
I
Driver off
D17
C17
mcasp1_fsr
mcasp1_fsx
mcasp1_fsr
mcasp7_axr3
i2c4_scl
IO
IO
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
0
1
1
10
14
15
0
gpio5_1
Driver off
mcasp1_fsx
vin1a_de0
i2c3_scl
IO
I
Dual
Voltage
LVCMOS
0
0
1
1
7
10
11
14
15
IO
IO
IO
I
pr2_mdio_data
gpio7_30
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
29
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
E19
D19
A22
mcasp2_aclkx
mcasp2_aclkx
vin1a_d7
0
IO
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
7
I
pr2_mii0_rxd2
pr2_pru0_gpi18
pr2_pru0_gpo18
Driver off
11
12
13
15
0
I
I
O
I
mcasp2_fsx
mcasp2_fsx
vin1a_d6
IO
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
0
0
7
pr2_mii0_rxd1
pr2_pru0_gpi19
pr2_pru0_gpo19
Driver off
11
12
13
15
0
I
I
O
I
mcasp3_aclkx
mcasp3_aclkx
mcasp3_aclkr
mcasp2_axr12
uart7_rxd
IO
IO
IO
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
1
2
0
1
0
0
3
vin1a_d3
7
I
pr2_mii0_crs
pr2_pru0_gpi12
pr2_pru0_gpo12
gpio5_13
11
12
13
14
15
0
I
I
O
IO
I
Driver off
A23
mcasp3_fsx
mcasp3_fsx
mcasp3_fsr
mcasp2_axr13
uart7_txd
IO
IO
IO
O
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
2
3
vin1a_d2
7
0
0
pr2_mii0_col
pr2_pru0_gpi13
pr2_pru0_gpo13
gpio5_14
11
12
13
14
15
I
I
O
IO
I
Driver off
30
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
C23
B25
AC3
mcasp4_aclkx
mcasp4_aclkx
0
IO
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
mcasp4_aclkr
spi3_sclk
1
IO
IO
I
2
0
1
1
uart8_rxd
3
i2c4_sda
4
IO
I
Driver off
15
0
mcasp4_fsx
mcasp4_fsx
mcasp4_fsr
spi3_d1
IO
IO
IO
O
IO
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
0
1
0
1
2
uart8_txd
3
i2c4_scl
4
Driver off
15
0
mcasp5_aclkx
mcasp5_aclkx
mcasp5_aclkr
spi4_sclk
IO
IO
IO
I
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
2
0
1
1
uart9_rxd
3
i2c5_sda
4
IO
I
pr2_pru1_gpi1
pr2_pru1_gpo1
Driver off
12
13
15
0
O
I
U6
mcasp5_fsx
mcasp5_fsx
mcasp5_fsr
spi4_d1
IO
IO
IO
O
IO
I
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
1
2
uart9_txd
3
i2c5_scl
4
pr2_pru1_gpi2
pr2_pru1_gpo2
Driver off
12
13
15
0
O
I
D14
mcasp1_axr0
mcasp1_axr0
uart6_rxd
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
0
1
0
3
vin1a_vsync0
i2c5_sda
7
I
10
11
12
13
14
15
IO
I
pr2_mii0_rxer
pr2_pru1_gpi8
pr2_pru1_gpo8
gpio5_2
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
31
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
B14
mcasp1_axr1
mcasp1_axr1
uart6_txd
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
3
O
I
vin1a_hsync0
i2c5_scl
7
0
1
0
10
11
12
13
14
15
0
IO
I
pr2_mii_mt0_clk
pr2_pru1_gpi9
pr2_pru1_gpo9
gpio5_3
I
O
IO
I
Driver off
C14
B15
mcasp1_axr2
mcasp1_axr3
mcasp1_axr2
mcasp6_axr2
uart6_ctsn
gpio5_4
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
0
1
1
3
14
15
0
IO
I
Driver off
mcasp1_axr3
mcasp6_axr3
uart6_rtsn
gpio5_5
IO
IO
O
IO
I
Dual
Voltage
LVCMOS
0
0
1
3
14
15
0
Driver off
A15
A14
A17
A16
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr4
mcasp4_axr2
gpio5_6
IO
IO
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
0
1
14
15
0
Driver off
mcasp1_axr5
mcasp4_axr3
gpio5_7
IO
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
14
15
0
Driver off
mcasp1_axr6
mcasp5_axr2
gpio5_8
IO
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
14
15
0
Driver off
mcasp1_axr7
mcasp5_axr3
timer4
IO
IO
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
10
14
15
gpio5_9
Driver off
32
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
A18
B17
B16
mcasp1_axr8
mcasp1_axr8
0
IO
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
0
mcasp6_axr0
spi3_sclk
1
IO
IO
I
3
vin1a_d15
7
timer5
10
11
12
13
14
15
0
IO
O
I
pr2_mii0_txen
pr2_pru1_gpi10
pr2_pru1_gpo10
gpio5_10
O
IO
I
Driver off
mcasp1_axr9
mcasp1_axr9
mcasp6_axr1
spi3_d1
IO
IO
IO
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
0
0
0
1
3
vin1a_d14
7
timer6
10
11
12
13
14
15
0
IO
O
I
pr2_mii0_txd3
pr2_pru1_gpi11
pr2_pru1_gpo11
gpio5_11
O
IO
I
Driver off
mcasp1_axr10
mcasp1_axr10
mcasp6_aclkx
mcasp6_aclkr
spi3_d0
IO
IO
IO
IO
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
0
0
1
2
3
0
0
vin1a_d13
7
timer7
10
11
12
13
14
15
IO
O
I
pr2_mii0_txd2
pr2_pru1_gpi12
pr2_pru1_gpo12
gpio5_12
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
33
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
B18
mcasp1_axr11
mcasp1_axr11
mcasp6_fsx
mcasp6_fsr
spi3_cs0
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
IO
IO
IO
I
2
3
1
0
vin1a_d12
7
timer8
10
11
12
13
14
15
0
IO
O
I
pr2_mii0_txd1
pr2_pru1_gpi13
pr2_pru1_gpo13
gpio4_17
O
IO
I
Driver off
A19
mcasp1_axr12
mcasp1_axr12
mcasp7_axr0
spi3_cs1
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
0
1
3
vin1a_d11
7
timer9
10
11
12
13
14
15
0
IO
O
I
pr2_mii0_txd0
pr2_pru1_gpi14
pr2_pru1_gpo14
gpio4_18
O
IO
I
Driver off
E17
mcasp1_axr13
mcasp1_axr13
mcasp7_axr1
vin1a_d10
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
1
7
timer10
10
11
12
13
14
15
IO
I
pr2_mii_mr0_clk
pr2_pru1_gpi15
pr2_pru1_gpo15
gpio6_4
0
I
O
IO
I
Driver off
34
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
E16
mcasp1_axr14
mcasp1_axr14
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
mcasp7_aclkx
mcasp7_aclkr
vin1a_d9
1
IO
IO
I
2
7
0
0
timer11
10
11
12
13
14
15
0
IO
I
pr2_mii0_rxdv
pr2_pru1_gpi16
pr2_pru1_gpo16
gpio6_5
I
O
IO
I
Driver off
F16
mcasp1_axr15
mcasp1_axr15
mcasp7_fsx
mcasp7_fsr
vin1a_d8
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
2
7
0
0
timer12
10
11
12
13
14
15
0
IO
I
pr2_mii0_rxd3
pr2_pru0_gpi20
pr2_pru0_gpo20
gpio6_6
I
O
IO
I
Driver off
A20
B19
A21
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr0
Driver off
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
15
mcasp2_axr1
Driver off
0
IO
I
Dual
Voltage
LVCMOS
15
mcasp2_axr2
mcasp3_axr2
vin1a_d5
0
IO
IO
I
Dual
Voltage
LVCMOS
0
0
0
0
1
7
pr2_mii0_rxd0
pr2_pru0_gpi16
pr2_pru0_gpo16
gpio6_8
11
12
13
14
15
I
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
35
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
B21
mcasp2_axr3
mcasp2_axr3
mcasp3_axr3
vin1a_d4
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
0
0
1
IO
I
7
pr2_mii0_rxlink
pr2_pru0_gpi17
pr2_pru0_gpo17
gpio6_9
11
12
13
14
15
0
I
I
O
IO
I
Driver off
B20
C19
D20
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr4
mcasp8_axr0
gpio1_4
IO
IO
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
1
14
15
0
Driver off
mcasp2_axr5
mcasp8_axr1
gpio6_7
IO
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
14
15
0
Driver off
mcasp2_axr6
mcasp8_aclkx
mcasp8_aclkr
gpio2_29
IO
IO
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
2
14
15
0
Driver off
C20
B22
mcasp2_axr7
mcasp3_axr0
mcasp2_axr7
mcasp8_fsx
mcasp8_fsr
gpio1_5
IO
IO
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
0
1
2
14
15
0
Driver off
mcasp3_axr0
mcasp2_axr14
uart7_ctsn
IO
IO
I
Dual
Voltage
LVCMOS
0
0
1
1
0
0
2
3
uart5_rxd
4
I
vin1a_d1
7
I
pr2_mii1_rxer
pr2_pru0_gpi14
pr2_pru0_gpo14
Driver off
11
12
13
15
I
I
O
I
36
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
B23
mcasp3_axr1
mcasp3_axr1
0
IO
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
mcasp2_axr15
uart7_rtsn
2
IO
O
O
I
3
uart5_txd
4
vin1a_d0
7
0
0
pr2_mii1_rxlink
pr2_pru0_gpi15
pr2_pru0_gpo15
Driver off
11
12
13
15
0
I
I
O
I
A24
D23
mcasp4_axr0
mcasp4_axr1
mcasp4_axr0
spi3_d0
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
0
1
1
2
uart8_ctsn
3
uart4_rxd
4
I
Driver off
15
0
I
mcasp4_axr1
spi3_cs0
IO
IO
O
O
I
Dual
Voltage
LVCMOS
0
1
2
uart8_rtsn
3
uart4_txd
4
pr2_pru1_gpi0
pr2_pru1_gpo0
Driver off
12
13
15
0
O
I
AA5
mcasp5_axr0
mcasp5_axr0
spi4_d0
IO
IO
I
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
1
2
uart9_ctsn
3
uart3_rxd
4
I
pr2_mdio_mdclk
pr2_pru1_gpi3
pr2_pru1_gpo3
Driver off
11
12
13
15
0
O
I
O
I
AC4
mcasp5_axr1
mcasp5_axr1
spi4_cs0
IO
IO
O
O
IO
I
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
2
uart9_rtsn
3
uart3_txd
4
pr2_mdio_data
pr2_pru1_gpi4
pr2_pru1_gpo4
Driver off
11
12
13
15
1
O
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
37
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
L6
mdio_d
mdio_d
0
IO
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
0
0
0
0
uart3_ctsn
mii0_txer
1
I
3
O
I
vin2a_d0
4
vin1b_d0
5
I
pr1_mii0_rxlink
pr2_pru1_gpi1
pr2_pru1_gpo1
gpio5_16
11
12
13
14
15
0
I
I
O
IO
I
Driver off
L5
mdio_mclk
mdio_mclk
uart3_rtsn
mii0_col
O
O
I
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
1
3
vin2a_clk0
vin1b_clk1
pr1_mii0_col
pr2_pru1_gpi0
pr2_pru1_gpo0
gpio5_15
4
I
5
I
0
0
11
12
13
14
15
0
I
I
O
IO
I
Driver off
U1
U2
T1
T2
U4
T3
U3
mlbp_clk_n
mlbp_clk_p
mlbp_dat_n
mlbp_dat_p
mlbp_sig_n
mlbp_sig_p
mmc1_clk
mlbp_clk_n
mlbp_clk_p
mlbp_dat_n
mlbp_dat_p
mlbp_sig_n
mlbp_sig_p
mmc1_clk
gpio6_21
I
vdds_mlbp No
vdds_mlbp No
vdds_mlbp No
vdds_mlbp No
vdds_mlbp No
vdds_mlbp No
BMLB18
BMLB18
BMLB18
BMLB18
BMLB18
BMLB18
0
I
0
IO
IO
IO
IO
IO
IO
I
OFF
OFF
OFF
OFF
PU
OFF
OFF
OFF
OFF
PU
0
0
0
0
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv8
vddshv8
vddshv8
Yes
SDIO2KV1 Pux/PDy
833
1
1
14
15
0
Driver off
V4
U5
mmc1_cmd
mmc1_sdcd
mmc1_cmd
gpio6_22
IO
IO
I
PU
PU
PU
PU
Yes
Yes
SDIO2KV1 Pux/PDy
833
14
15
0
Driver off
mmc1_sdcd
uart6_rxd
I
Dual
Voltage
LVCMOS
PU/PD
1
1
1
3
I
i2c4_sda
4
IO
IO
I
gpio6_27
14
15
Driver off
38
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
V5
mmc1_sdwp
mmc1_sdwp
0
I
PD
PD
15
1.8/3.3
vddshv8
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
uart6_txd
3
O
IO
IO
I
i2c4_scl
4
gpio6_28
14
15
0
Driver off
Y2
mmc3_clk
mmc3_clk
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
0
0
vin2b_d7
4
vin1a_d7
9
I
ehrpwm2_tripzone_input
pr2_mii1_txd3
pr2_pru0_gpi2
pr2_pru0_gpo2
gpio6_29
10
11
12
13
14
15
0
IO
O
I
O
IO
I
Driver off
Y1
mmc3_cmd
mmc3_cmd
spi3_sclk
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
0
0
0
1
vin2b_d6
4
vin1a_d6
9
I
eCAP2_in_PWM2_out
pr2_mii1_txd2
pr2_pru0_gpi3
pr2_pru0_gpo3
gpio6_30
10
11
12
13
14
15
0
IO
O
I
O
IO
I
Driver off
V3
V2
W1
V1
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat0
gpio6_23
IO
IO
I
PU
PU
PU
PU
PU
PU
PU
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv8
vddshv8
vddshv8
vddshv8
Yes
Yes
Yes
Yes
SDIO2KV1 Pux/PDy
833
1
1
1
1
14
15
0
Driver off
mmc1_dat1
gpio6_24
IO
IO
I
SDIO2KV1 Pux/PDy
833
14
15
0
Driver off
mmc1_dat2
gpio6_25
IO
IO
I
SDIO2KV1 Pux/PDy
833
14
15
0
Driver off
mmc1_dat3
gpio6_26
IO
IO
I
SDIO2KV1 Pux/PDy
833
14
15
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
39
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
Y4
mmc3_dat0
mmc3_dat0
spi3_d1
0
IO
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
1
0
1
0
0
0
1
IO
I
uart5_rxd
2
vin2b_d5
4
I
vin1a_d5
9
I
eQEP3A_in
pr2_mii1_txd1
pr2_pru0_gpi4
pr2_pru0_gpo4
gpio6_31
10
11
12
13
14
15
0
I
O
I
O
IO
I
Driver off
AA2
mmc3_dat1
mmc3_dat1
spi3_d0
IO
IO
O
I
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
0
1
uart5_txd
2
vin2b_d4
4
0
0
0
vin1a_d4
9
I
eQEP3B_in
pr2_mii1_txd0
pr2_pru0_gpi5
pr2_pru0_gpo5
gpio7_0
10
11
12
13
14
15
0
I
O
I
O
IO
I
Driver off
AA3
mmc3_dat2
mmc3_dat2
spi3_cs0
IO
IO
I
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
1
1
0
0
0
0
1
uart5_ctsn
vin2b_d3
2
4
I
vin1a_d3
9
I
eQEP3_index
pr2_mii_mr1_clk
pr2_pru0_gpi6
pr2_pru0_gpo6
gpio7_1
10
11
12
13
14
15
IO
I
I
O
IO
I
Driver off
40
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
W2
mmc3_dat3
mmc3_dat3
0
IO
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
1
1
spi3_cs1
1
IO
O
I
uart5_rtsn
2
vin2b_d2
4
0
0
0
0
vin1a_d2
9
I
eQEP3_strobe
pr2_mii1_rxdv
pr2_pru0_gpi7
pr2_pru0_gpo7
gpio7_2
10
11
12
13
14
15
0
IO
I
I
O
IO
I
Driver off
Y3
mmc3_dat4
mmc3_dat4
spi4_sclk
IO
IO
I
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
0
1
0
0
1
uart10_rxd
vin2b_d1
2
4
I
vin1a_d1
9
I
ehrpwm3A
pr2_mii1_rxd3
pr2_pru0_gpi8
pr2_pru0_gpo8
gpio1_22
10
11
12
13
14
15
0
O
I
0
I
O
IO
I
Driver off
AA1
mmc3_dat5
mmc3_dat5
spi4_d1
IO
IO
O
I
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
0
1
uart10_txd
vin2b_d0
2
4
0
0
vin1a_d0
9
I
ehrpwm3B
pr2_mii1_rxd2
pr2_pru0_gpi9
pr2_pru0_gpo9
gpio1_23
10
11
12
13
14
15
O
I
0
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
41
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
AA4
AB1
L24
mmc3_dat6
mmc3_dat6
0
IO
PU
PU
PD
PU
PU
PD
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
1
0
1
spi4_d0
1
IO
I
uart10_ctsn
2
vin2b_de1
4
I
vin1a_hsync0
ehrpwm3_tripzone_input
pr2_mii1_rxd1
pr2_pru0_gpi10
pr2_pru0_gpo10
gpio1_24
9
I
0
0
0
10
11
12
13
14
15
0
IO
I
I
O
IO
I
Driver off
mmc3_dat7
mmc3_dat7
IO
IO
O
I
15
1.8/3.3
vddshv7
Yes
Dual
Voltage
LVCMOS
1
1
spi4_cs0
1
uart10_rtsn
2
vin2b_clk1
4
vin1a_vsync0
eCAP3_in_PWM3_out
pr2_mii1_rxd0
pr2_pru0_gpi11
pr2_pru0_gpo11
gpio1_25
9
I
0
0
0
10
11
12
13
14
15
0
IO
I
I
O
IO
I
Driver off
nmin_dsp
nmin_dsp
I
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
AE6
AD7
AE8
AD9
F19
K24
pcie_rxn0
pcie_rxp0
pcie_txn0
pcie_txp0
porz
pcie_rxn0
pcie_rxp0
pcie_txn0
pcie_txp0
porz
0
0
0
0
0
0
I
OFF
OFF
OFF
OFF
1.8
vdda_pcie
vdda_pcie
vdda_pcie
vdda_pcie
vddshv3
SERDES
SERDES
SERDES
SERDES
I
1.8
O
O
I
1.8
1.8
1.8/3.3
1.8/3.3
Yes
Yes
IHHV1833 PU/PD
resetn
resetn
I
PU
PU
vddshv3
Dual
PU/PD
Voltage
LVCMOS
42
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
N2
P2
T4
rgmii0_rxc
rgmii0_rxc
0
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
rmii1_txen
mii0_txclk
2
O
I
3
0
0
0
0
vin2a_d5
4
I
vin1b_d5
5
I
pr1_mii_mt0_clk
pr2_pru1_gpi11
pr2_pru1_gpo11
gpio5_26
11
12
13
14
15
0
I
I
O
IO
I
Driver off
rgmii0_rxctl
rgmii0_rxctl
rmii1_txd1
mii0_txd3
I
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
0
2
O
O
I
3
vin2a_d6
4
0
0
vin1b_d6
5
I
pr1_mii0_txd3
pr2_pru1_gpi12
pr2_pru1_gpo12
gpio5_27
11
12
13
14
15
0
O
I
O
IO
I
Driver off
rgmii0_txc
rgmii0_txc
uart3_ctsn
rmii1_rxd1
mii0_rxd3
O
I
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
1
1
0
0
0
0
0
1
0
2
I
3
I
vin2a_d3
4
I
vin1b_d3
5
I
spi3_d0
7
IO
IO
I
spi4_cs2
8
pr1_mii0_rxd3
pr2_pru1_gpi5
pr2_pru1_gpo5
gpio5_20
11
12
13
14
15
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
43
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
T5
rgmii0_txctl
rgmii0_txctl
uart3_rtsn
0
O
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
O
I
rmii1_rxd0
mii0_rxd2
2
0
0
0
0
1
1
0
3
I
vin2a_d4
4
I
vin1b_d4
5
I
spi3_cs0
7
IO
IO
I
spi4_cs3
8
pr1_mii0_rxd2
pr2_pru1_gpi6
pr2_pru1_gpo6
gpio5_21
11
12
13
14
15
0
I
O
IO
I
Driver off
N4
rgmii0_rxd0
rgmii0_rxd0
rmii0_txd0
mii0_txd0
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
O
O
I
3
vin2a_fld0
4
vin1b_fld1
5
I
pr1_mii0_txd0
pr2_pru1_gpi16
pr2_pru1_gpo16
gpio5_31
11
12
13
14
15
0
O
I
O
IO
I
Driver off
N3
rgmii0_rxd1
rgmii0_rxd1
rmii0_txd1
mii0_txd1
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
1
O
O
I
3
vin2a_d9
4
pr1_mii0_txd1
pr2_pru1_gpi15
pr2_pru1_gpo15
gpio5_30
11
12
13
14
15
O
I
O
IO
I
Driver off
44
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
P1
rgmii0_rxd2
rgmii0_rxd2
0
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
PU/PD
0
Voltage
LVCMOS
rmii0_txen
1
O
O
I
mii0_txen
3
vin2a_d8
4
0
pr1_mii0_txen
pr2_pru1_gpi14
pr2_pru1_gpo14
gpio5_29
11
12
13
14
15
0
O
I
O
IO
I
Driver off
N1
rgmii0_rxd3
rgmii0_rxd3
rmii1_txd0
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
PU/PD
0
Voltage
LVCMOS
2
O
O
I
mii0_txd2
3
vin2a_d7
4
0
0
vin1b_d7
5
I
pr1_mii0_txd2
pr2_pru1_gpi13
pr2_pru1_gpo13
gpio5_28
11
12
13
14
15
0
O
I
O
IO
I
Driver off
R1
rgmii0_txd0
rgmii0_txd0
rmii0_rxd0
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
PU/PD
Voltage
LVCMOS
1
0
0
0
1
mii0_rxd0
3
I
vin2a_d10
4
I
spi4_cs0
7
IO
O
I
uart4_rtsn
8
pr1_mii0_rxd0
pr2_pru1_gpi10
pr2_pru1_gpo10
gpio5_25
11
12
13
14
15
0
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
45
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
R2
P3
P4
rgmii0_txd1
rgmii0_txd1
rmii0_rxd1
mii0_rxd1
0
O
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
I
0
0
3
I
vin2a_vsync0
vin1b_vsync1
spi4_d0
4
I
5
I
0
0
1
0
7
IO
IO
I
uart4_ctsn
pr1_mii0_rxd1
pr2_pru1_gpi9
pr2_pru1_gpo9
gpio5_24
8
11
12
13
14
15
0
I
O
IO
I
Driver off
rgmii0_txd2
rgmii0_txd2
rmii0_rxer
O
I
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
0
mii0_rxer
3
I
vin2a_hsync0
vin1b_hsync1
spi4_d1
4
I
5
I
0
0
7
IO
O
I
uart4_txd
8
pr1_mii0_rxer
pr2_pru1_gpi8
pr2_pru1_gpo8
gpio5_23
11
12
13
14
15
0
0
I
O
IO
I
Driver off
rgmii0_txd3
rgmii0_txd3
rmii0_crs
O
I
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
1
0
0
mii0_crs
3
I
vin2a_de0
vin1b_de1
spi4_sclk
4
I
5
I
0
0
1
0
7
IO
I
uart4_rxd
8
pr1_mii0_crs
pr2_pru1_gpi7
pr2_pru1_gpo7
gpio5_22
11
12
13
14
15
I
I
O
IO
I
Driver off
46
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
P5
RMII_MHZ_50_CLK
RMII_MHZ_50_CLK
0
IO
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
vin2a_d11
pr2_pru1_gpi2
pr2_pru1_gpo2
gpio5_17
4
I
12
13
14
15
0
I
O
IO
I
Driver off
E20
K25
C24
rstoutn
rtck
rstoutn
O
PD
PU
PD
PD
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
rtck
0
O
OFF
PD
0
Dual
Voltage
LVCMOS
gpio8_29
14
IO
spi1_sclk
spi1_sclk
gpio7_7
0
IO
IO
I
15
Dual
Voltage
LVCMOS
0
14
15
0
Driver off
spi2_sclk
uart3_rxd
gpio7_14
Driver off
spi1_cs0
gpio7_10
Driver off
spi1_cs1
spi2_cs1
gpio7_11
Driver off
spi1_cs2
uart4_rxd
mmc3_sdcd
spi2_cs2
dcan2_tx
mdio_mclk
hdmi1_hpd
gpio7_12
Driver off
G25
spi2_sclk
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
0
1
1
14
15
0
IO
I
B24
C25
spi1_cs0
spi1_cs1
IO
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
1
14
15
0
IO
IO
IO
I
Dual
Voltage
LVCMOS
1
1
3
14
15
0
E24
spi1_cs2
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
1
1
1
1
1
2
I
3
IO
IO
O
IO
IO
I
4
5
No
6
14
15
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
47
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
E25
spi1_cs3
spi1_cs3
uart4_txd
mmc3_sdwp
spi2_cs3
dcan2_rx
mdio_d
0
IO
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
1
1
O
I
2
0
1
1
1
3
IO
IO
IO
IO
IO
I
4
5
hdmi1_cec
gpio7_13
Driver off
spi1_d0
No
6
14
15
0
D25
D24
F24
spi1_d0
spi1_d1
spi2_cs0
IO
IO
I
PD
PD
PU
PD
PD
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
1
gpio7_9
Driver off
spi1_d1
14
15
0
IO
IO
I
Dual
Voltage
LVCMOS
gpio7_8
Driver off
spi2_cs0
uart3_rtsn
uart5_txd
gpio7_17
Driver off
spi2_d0
14
15
0
IO
O
O
IO
I
Dual
Voltage
LVCMOS
1
2
14
15
0
G24
F25
spi2_d0
spi2_d1
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
0
1
1
uart3_ctsn
uart5_rxd
gpio7_16
Driver off
spi2_d1
1
2
I
14
15
0
IO
I
IO
O
IO
I
Dual
Voltage
LVCMOS
0
uart3_txd
gpio7_15
Driver off
tclk
1
14
15
0
K21
L23
tclk
tdi
I
PU
PU
PU
PU
0
0
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
IQ1833
PU/PD
PU/PD
tdi
0
I
Dual
Voltage
LVCMOS
gpio8_27
14
I
J20
L21
tdo
tdo
0
O
PU
PU
PU
PU
0
0
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
gpio8_28
14
IO
tms
tms
0
I
Dual
Voltage
LVCMOS
48
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
L22
L20
trstn
trstn
0
I
PD
PU
PD
PU
1.8/3.3
vddshv3
Yes
Dual
Voltage
LVCMOS
PU/PD
uart1_ctsn
uart1_rtsn
uart1_ctsn
uart9_rxd
mmc4_clk
gpio7_24
Driver off
uart1_rtsn
uart9_txd
mmc4_cmd
gpio7_25
Driver off
uart1_rxd
mmc4_sdcd
gpio7_22
Driver off
uart1_txd
mmc4_sdwp
gpio7_23
Driver off
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
uart2_rtsn
uart3_txd
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
0
I
I
15
15
1.8/3.3
1.8/3.3
vddshv4
vddshv4
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
1
1
1
2
3
IO
IO
I
14
15
0
M24
O
O
IO
IO
I
PU
PU
Dual
Voltage
LVCMOS
2
3
1
14
15
0
L25
M25
N22
uart1_rxd
uart1_txd
uart2_ctsn
I
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv4
Yes
Yes
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
1
1
3
I
14
15
0
IO
I
O
I
Dual
Voltage
LVCMOS
3
0
14
15
0
IO
I
I
Dual
Voltage
LVCMOS
1
1
1
1
2
I
3
IO
I
4
5
O
IO
I
14
15
0
N24
uart2_rtsn
O
O
O
IO
O
I
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual
Voltage
LVCMOS
PU/PD
1
2
3
1
1
4
5
gpio1_17
Driver off
14
15
IO
I
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
49
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
N23
N25
N5
uart2_rxd
uart2_rxd
uart3_ctsn
uart3_rctx
mmc4_dat0
uart2_rxd
uart1_dcdn
gpio7_26
0
I
I
PU
PU
PD
PU
PU
PD
15
15
15
1.8/3.3
vddshv4
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
1
1
1
2
O
IO
I
3
1
1
1
4
5
I
14
15
0
IO
I
Driver off
uart2_txd
uart2_txd
uart3_rtsn
uart3_sd
O
O
O
IO
O
I
1.8/3.3
vddshv4
Yes
Dual
Voltage
LVCMOS
1
2
mmc4_dat1
uart2_txd
uart1_dsrn
gpio7_27
3
1
0
4
5
14
15
0
IO
I
Driver off
uart3_rxd
uart3_rxd
rmii1_crs
I
1.8/3.3
vddshv9
Yes
Dual
Voltage
LVCMOS
1
0
0
0
0
0
0
2
I
mii0_rxdv
vin2a_d1
3
I
4
I
vin1b_d1
5
I
spi3_sclk
7
IO
I
pr1_mii0_rxdv
pr2_pru1_gpi3
pr2_pru1_gpo3
gpio5_18
11
12
13
14
15
I
O
IO
I
Driver off
50
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
N6
uart3_txd
uart3_txd
0
O
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual
PU/PD
Voltage
LVCMOS
rmii1_rxer
mii0_rxclk
vin2a_d2
2
I
0
0
0
0
0
1
0
3
I
4
I
vin1b_d2
5
I
spi3_d1
7
IO
IO
I
spi4_cs1
8
pr1_mii_mr0_clk
pr2_pru1_gpi4
pr2_pru1_gpo4
gpio5_19
11
12
13
14
15
0
I
O
IO
I
Driver off
AB7
AC6
AD3
usb1_dm
usb1_dm
IO
OFF
OFF
PD
OFF
OFF
PD
3.3
vdda33v_u
sb1
USBPHY
USBPHY
usb1_dp
usb1_dp
0
IO
3.3
vdda33v_u
sb1
usb1_drvvbus
usb1_drvvbus
timer16
0
O
IO
IO
I
15
1.8/3.3
vdda33v_u Yes
sb2
Dual
Voltage
LVCMOS
PU/PD
7
gpio6_12
Driver off
usb2_dm
14
15
0
AC5
AB6
AA6
usb2_dm
IO
3.3
vdda33v_u No
sb2
USBPHY
USBPHY
usb2_dp
usb2_dp
0
IO
3.3
vdda33v_u No
sb2
usb2_drvvbus
usb2_drvvbus
timer15
0
O
IO
IO
I
PD
PD
15
1.8/3.3
vdda33v_u Yes
sb2
Dual
Voltage
LVCMOS
PU/PD
7
gpio6_13
Driver off
usb_rxn0
pcie_rxn1
usb_rxp0
pcie_rxp1
usb_txn0
pcie_txn1
usb_txp0
pcie_txp1
14
15
0
AE5
AD6
AE3
AD4
usb_rxn0
usb_rxp0
usb_txn0
usb_txp0
I
OFF
OFF
OFF
OFF
1.8
1.8
1.8
1.8
vdda_usb1
vdda_usb1
vdda_usb1
vdda_usb1
SERDES
SERDES
SERDES
SERDES
1
I
0
I
1
I
0
O
O
O
O
1
0
1
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
51
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
J15, J16, J18, K12, vdd
K18, L12, L17,
vdd
PWR
M11, M13, M15,
M17, N11, N13,
N15, N18, P10,
P12, P14, P16,
P18, R10, R12,
R14, R16, R17,
T11, T13, T15,
T17, T9, U11, U13,
U15, U18, U9,
V10, V12, V14,
V16, V18, W10,
W12, W14, W16
vpp(11)
F20
vpp
PWR
AA10
Y10
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
L9
T6
R20
vdda_ddr
vdda_ddr
N10
vdda_debug
vdda_dsp_iva
vdda_gpu
vdda_debug
vdda_dsp_iva
vdda_gpu
K10, L10
N9
W15, Y15
K16, L16
W13, Y13
W11, Y11
M10
vdda_hdmi
vdda_mpu_abe
vdda_osc
vdda_hdmi
vdda_mpu_abe
vdda_osc
vdda_pcie
vdda_pcie
vdda_per
vdda_per
W8
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdds18v
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdds18v
Y8
Y9
K14, L14
G11, H20, W7,
Y18
AA19, P20, Y19
G10, G9
vdds18v_ddr1
vddshv1
vdds18v_ddr1
vddshv1
PWR
PWR
PWR
G15, G17, H15,
H17, J19, K19
vddshv3
vddshv3
M19, N19
U7, U8
vddshv4
vddshv7
vddshv8
vddshv9
vddshv10
vddshv4
vddshv7
vddshv8
vddshv9
vddshv10
PWR
PWR
PWR
PWR
PWR
N8, P8
M7, N7
J7, J8, K8
52
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
F7, G7, H7
vddshv11
vddshv11
PWR
PWR
T19, T20, V20,
vdds_ddr1
vdds_ddr1
W17, W18, W20
P7, R7
vdds_mlbp
vdds_mlbp
vdd_dsp
PWR
PWR
H11, H13, H9, J11, vdd_dsp
J13, J9
D8
vin2a_clk0
vin2a_clk0
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
Voltage
LVCMOS
vout2_fld
No
4
O
O
I
emu5
5
kbd_row0
9
0
0
0
eQEP1A_in
pr1_edio_data_in0
pr1_edio_data_out0
10
12
13
14
I
I
O
IO
gpio3_28
gpmc_a27
gpmc_a17
Driver off
15
0
I
C8
vin2a_d0
vin2a_d0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d23
emu10
No
4
O
O
I
5
uart9_ctsn
spi4_d0
7
1
0
0
8
IO
I
kbd_row4
9
ehrpwm1B
pr1_uart0_rxd
pr1_edio_data_in5
pr1_edio_data_out5
gpio4_1
10
11
12
13
14
15
O
I
1
0
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
53
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
B9
vin2a_d1
vin2a_d1
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d22
No
4
O
O
O
IO
I
emu11
5
uart9_rtsn
7
spi4_cs0
8
1
0
0
kbd_row5
9
ehrpwm1_tripzone_input
pr1_uart0_txd
pr1_edio_data_in6
pr1_edio_data_out6
gpio4_2
10
11
12
13
14
15
0
IO
O
I
0
O
IO
I
Driver off
A7
vin2a_d2
vin2a_d2
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d21
No
4
O
O
I
emu12
5
uart10_rxd
8
1
0
0
0
0
kbd_row6
9
I
eCAP1_in_PWM1_out
pr1_ecap0_ecap_capin_apwm_o
pr1_edio_data_in7
pr1_edio_data_out7
gpio4_3
10
11
12
13
14
15
0
IO
IO
I
O
IO
I
Driver off
A9
vin2a_d3
vin2a_d3
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d20
No
4
O
O
O
O
I
emu13
5
uart10_txd
8
kbd_col0
9
ehrpwm1_synci
pr1_edc_latch0_in
pr1_pru1_gpi0
pr1_pru1_gpo0
gpio4_4
10
11
12
13
14
15
0
0
I
I
O
IO
I
Driver off
54
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
A8
vin2a_d4
vin2a_d4
0
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
vout2_d19
emu14
No
No
No
4
O
O
I
5
uart10_ctsn
kbd_col1
8
1
9
O
O
O
I
ehrpwm1_synco
pr1_edc_sync0_out
pr1_pru1_gpi1
pr1_pru1_gpo1
gpio4_5
10
11
12
13
14
15
0
O
IO
I
Driver off
A11
vin2a_d5
vin2a_d5
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
vout2_d18
emu15
4
O
O
O
O
I
5
uart10_rtsn
kbd_col2
8
9
eQEP2A_in
pr1_edio_sof
pr1_pru1_gpi2
pr1_pru1_gpo2
gpio4_6
10
11
12
13
14
15
0
O
I
O
IO
I
Driver off
F10
vin2a_d6
vin2a_d6
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
vout2_d17
emu16
4
O
O
I
5
mii1_rxd1
8
kbd_col3
9
O
I
eQEP2B_in
pr1_mii_mt1_clk
pr1_pru1_gpi3
pr1_pru1_gpo3
gpio4_7
10
11
12
13
14
15
0
0
I
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
55
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
A10
vin2a_d7
vin2a_d7
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d16
emu17
No
4
O
O
I
5
mii1_rxd2
8
0
0
kbd_col4
9
O
IO
O
I
eQEP2_index
pr1_mii1_txen
pr1_pru1_gpi4
pr1_pru1_gpo4
gpio4_8
10
11
12
13
14
15
0
O
IO
I
Driver off
B10
vin2a_d8
vin2a_d8
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
vout2_d15
emu18
No
4
O
O
I
5
mii1_rxd3
8
0
0
kbd_col5
9
O
IO
O
I
eQEP2_strobe
pr1_mii1_txd3
pr1_pru1_gpi5
pr1_pru1_gpo5
10
11
12
13
14
O
IO
gpio4_9
gpmc_a26
Driver off
15
0
I
E10
vin2a_d9
vin2a_d9
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
0
0
vout2_d14
emu19
No
4
O
O
I
5
mii1_rxd0
8
kbd_col6
9
O
O
O
I
ehrpwm2A
pr1_mii1_txd2
pr1_pru1_gpi6
pr1_pru1_gpo6
10
11
12
13
14
O
IO
gpio4_10
gpmc_a25
Driver off
15
I
56
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
D10
C10
B11
vin2a_d10
vin2a_d10
0
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
1
mdio_mclk
3
O
O
O
O
O
I
vout2_d13
No
No
No
4
kbd_col7
9
ehrpwm2B
10
11
12
13
14
pr1_mdio_mdclk
pr1_pru1_gpi7
pr1_pru1_gpo7
O
IO
gpio4_11
gpmc_a24
Driver off
15
0
I
vin2a_d11
vin2a_d11
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
1
mdio_d
3
IO
O
I
vout2_d12
4
kbd_row7
9
0
0
1
ehrpwm2_tripzone_input
pr1_mdio_data
pr1_pru1_gpi8
pr1_pru1_gpo8
10
11
12
13
14
IO
IO
I
O
IO
gpio4_12
gpmc_a23
Driver off
15
0
I
vin2a_d12
vin2a_d12
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
rgmii1_txc
3
O
O
I
vout2_d11
4
mii1_rxclk
8
0
0
kbd_col8
9
O
IO
O
I
eCAP2_in_PWM2_out
pr1_mii1_txd1
pr1_pru1_gpi9
pr1_pru1_gpo9
gpio4_13
10
11
12
13
14
15
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
57
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
D11
vin2a_d13
vin2a_d13
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
rgmii1_txctl
vout2_d10
3
O
O
I
No
4
mii1_rxdv
8
0
0
0
kbd_row8
9
I
eQEP3A_in
pr1_mii1_txd0
pr1_pru1_gpi10
pr1_pru1_gpo10
gpio4_14
10
11
12
13
14
15
0
I
O
I
O
IO
I
Driver off
C11
vin2a_d14
vin2a_d14
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
rgmii1_txd3
vout2_d9
3
O
O
I
No
4
mii1_txclk
8
0
0
0
eQEP3B_in
pr1_mii_mr1_clk
pr1_pru1_gpi11
pr1_pru1_gpo11
gpio4_15
10
11
12
13
14
15
0
I
I
I
O
IO
I
Driver off
B12
vin2a_d15
vin2a_d15
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
0
Voltage
LVCMOS
rgmii1_txd2
vout2_d8
3
O
O
O
IO
I
No
4
mii1_txd0
8
eQEP3_index
pr1_mii1_rxdv
pr1_pru1_gpi12
pr1_pru1_gpo12
gpio4_16
10
11
12
13
14
15
0
0
I
O
IO
I
Driver off
58
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
A12
A13
E11
vin2a_d16
vin2a_d16
0
I
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
vin2b_d7
2
rgmii1_txd1
vout2_d7
3
O
O
O
IO
I
No
No
No
4
mii1_txd1
8
eQEP3_strobe
pr1_mii1_rxd3
pr1_pru1_gpi13
pr1_pru1_gpo13
gpio4_24
10
11
12
13
14
15
0
0
0
I
O
IO
I
Driver off
vin2a_d17
vin2a_d17
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
vin2b_d6
2
I
rgmii1_txd0
vout2_d6
3
O
O
O
O
I
4
mii1_txd2
8
ehrpwm3A
pr1_mii1_rxd2
pr1_pru1_gpi14
pr1_pru1_gpo14
gpio4_25
10
11
12
13
14
15
0
0
I
O
IO
I
Driver off
vin2a_d18
vin2a_d18
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
0
vin2b_d5
2
I
rgmii1_rxc
3
I
vout2_d5
4
O
O
O
I
mii1_txd3
8
ehrpwm3B
pr1_mii1_rxd1
pr1_pru1_gpi15
pr1_pru1_gpo15
gpio4_26
10
11
12
13
14
15
0
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
59
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
F11
B13
E13
vin2a_d19
vin2a_d19
0
I
I
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
vin2b_d4
2
rgmii1_rxctl
vout2_d4
3
No
No
No
4
O
O
IO
I
mii1_txer
8
0
0
0
ehrpwm3_tripzone_input
pr1_mii1_rxd0
pr1_pru1_gpi16
pr1_pru1_gpo16
gpio4_27
10
11
12
13
14
15
0
I
O
IO
I
Driver off
vin2a_d20
vin2a_d20
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
0
vin2b_d3
2
I
rgmii1_rxd3
vout2_d3
3
I
4
O
I
mii1_rxer
8
0
0
0
eCAP3_in_PWM3_out
pr1_mii1_rxer
pr1_pru1_gpi17
pr1_pru1_gpo17
gpio4_28
10
11
12
13
14
15
0
IO
I
I
O
IO
I
Driver off
vin2a_d21
vin2a_d21
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
0
vin2b_d2
2
I
rgmii1_rxd2
vout2_d2
3
I
4
O
I
mii1_col
8
0
0
pr1_mii1_rxlink
pr1_pru1_gpi18
pr1_pru1_gpo18
gpio4_29
11
12
13
14
15
I
I
O
IO
I
Driver off
60
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
C13
D13
B7
vin2a_d22
vin2a_d22
0
I
I
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
PU/PD
PU/PD
0
0
0
vin2b_d1
2
rgmii1_rxd1
vout2_d1
3
No
4
O
I
mii1_crs
8
0
0
pr1_mii1_col
pr1_pru1_gpi19
pr1_pru1_gpo19
gpio4_30
11
12
13
14
15
0
I
I
O
IO
I
Driver off
vin2a_d23
vin2a_d23
vin2b_d0
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
0
0
0
2
I
rgmii1_rxd0
vout2_d0
3
I
No
4
O
O
I
mii1_txen
8
pr1_mii1_crs
pr1_pru1_gpi20
pr1_pru1_gpo20
gpio4_31
11
12
13
14
15
0
0
I
O
IO
I
Driver off
vin2a_de0
vin2a_de0
vin2a_fld0
I
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
1
I
vin2b_fld1
2
I
vin2b_de1
vout2_de
3
I
No
4
O
O
I
emu6
5
kbd_row1
9
0
0
0
eQEP1B_in
pr1_edio_data_in1
pr1_edio_data_out1
gpio3_29
10
12
13
14
15
I
I
O
IO
I
Driver off
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
61
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
C7
vin2a_fld0
vin2a_fld0
0
I
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
Voltage
LVCMOS
PU/PD
vin2b_clk1
2
vout2_clk
No
4
O
O
IO
I
emu7
5
eQEP1_index
pr1_edio_data_in2
pr1_edio_data_out2
10
12
13
14
0
0
O
IO
gpio3_30
gpmc_a27
gpmc_a18
Driver off
15
0
I
E8
vin2a_hsync0
vin2a_hsync0
vin2b_hsync1
vout2_hsync
emu8
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
Voltage
LVCMOS
3
I
No
4
O
O
I
5
uart9_rxd
7
1
0
0
0
1
0
spi4_sclk
8
IO
I
kbd_row2
9
eQEP1_strobe
pr1_uart0_cts_n
pr1_edio_data_in3
pr1_edio_data_out3
10
11
12
13
14
IO
I
I
O
IO
gpio3_31
gpmc_a27
Driver off
15
0
I
B8
vin2a_vsync0
vin2a_vsync0
vin2b_vsync1
vout2_vsync
emu9
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual
PU/PD
Voltage
LVCMOS
3
I
No
4
O
O
O
IO
I
5
uart9_txd
7
spi4_d1
8
0
0
kbd_row3
9
ehrpwm1A
pr1_uart0_rts_n
pr1_edio_data_in4
pr1_edio_data_out4
gpio4_0
10
11
12
13
14
15
O
O
I
0
O
IO
I
Driver off
62
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
A1, A25, AA13,
AA15, AA7, AA8,
AA9, AB8, AC13,
AE1, AE15, AE25,
G13, G16, G8,
vss
vss
GND
H10, H12, H14,
H16, H18, H19,
H8, J10, J12, J14,
J17, K11, K13,
K15, K17, K9, L11,
L13, L15, L18, L8,
M12, M14, M16,
M18, M20, M8, M9,
N12, N14, N16,
N17, N20, P11,
P13, P15, P17,
P19, P9, R11, R13,
R15, R18, R19,
R8, R9, T10, T12,
T14, T16, T18, T8,
U10, U12, U14,
U16, U17, U19,
V11, V13, V15,
V17, V19, V8, V9,
W19, W9, Y14,
Y16, Y17, Y7
AA12
AB11
AC10
vssa_osc0
vssa_osc1
Wakeup0
vssa_osc0
vssa_osc1
dcan1_rx
GND
GND
1
I
I
15
15
1.8/3.3
vdda33v_u Yes
sb1
IHHV1833 PU/PD
IHHV1833 PU/PD
1
gpio1_0
sys_nirq2
14
Driver off
sys_nirq1
15
1
I
I
I
AB10
Wakeup3
1.8/3.3
vdda33v_u Yes
sb1
gpio1_3
14
dcan2_rx
Driver off
xi_osc0
15
0
I
I
Y12
xi_osc0
xi_osc1
xo_osc0
xo_osc1
1.8
1.8
1.8
1.8
vdda_osc No
vdda_osc No
vdda_osc No
vdda_osc No
LVCMOS
Analog
AC11
AB12
AA11
xi_osc1
xo_osc0
xo_osc1
0
0
0
I
LVCMOS
Analog
O
A
LVCMOS
Analog
LVCMOS
Analog
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
63
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
MUXMODE
[5]
VOLTAGE POWER
VALUE
[10]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
[1]
[11]
STATE [8]
J25
xref_clk0
xref_clk0
0
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
PU/PD
Voltage
LVCMOS
mcasp2_axr8
mcasp1_axr4
mcasp1_ahclkx
mcasp5_ahclkx
vin1a_d0
1
IO
IO
O
O
I
0
0
2
3
4
7
0
1
hdq0
8
IO
O
IO
I
clkout2
9
timer13
10
11
12
13
14
15
0
pr2_mii1_col
pr2_pru1_gpi5
pr2_pru1_gpo5
gpio6_17
0
I
O
IO
I
Driver off
J24
xref_clk1
xref_clk1
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
PU/PD
Voltage
LVCMOS
mcasp2_axr9
mcasp1_axr5
mcasp2_ahclkx
mcasp6_ahclkx
vin1a_clk0
timer14
1
IO
IO
O
O
I
0
0
2
3
4
7
0
0
10
11
12
13
14
15
0
IO
I
pr2_mii1_crs
pr2_pru1_gpi6
pr2_pru1_gpo6
gpio6_18
I
O
IO
I
Driver off
H24
xref_clk2
xref_clk2
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
PU/PD
Voltage
LVCMOS
mcasp2_axr10
mcasp1_axr6
mcasp3_ahclkx
mcasp7_ahclkx
timer15
1
IO
IO
O
O
IO
IO
I
0
0
2
3
4
10
14
15
gpio6_19
Driver off
64
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-1. Pin Attributes(1) (continued)
BALL
RESET
REL.
MUXMODE
[9]
BALL
RESET
REL.
I/O
VOLTAGE POWER
BALL
RESET
STATE [7]
PULL
UP/DOWN DSIS [15]
TYPE [14]
BALL NUMBER
[1]
MUXMODE
[5]
BUFFER
TYPE [13]
BALL NAME [2]
SIGNAL NAME [3]
PN [4]
TYPE [6]
HYS [12]
VALUE
[10]
[11]
STATE [8]
H25
xref_clk3
xref_clk3
0
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual
PU/PD
Voltage
LVCMOS
mcasp2_axr11
mcasp1_axr7
mcasp4_ahclkx
mcasp8_ahclkx
hdq0
1
IO
IO
O
0
0
2
3
4
O
7
IO
O
1
clkout3
9
timer16
10
14
15
IO
IO
I
gpio6_20
Driver off
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Section 5.4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
(9) The IHHV1833 buffer exists in the dual-voltage IO logic that can be powered by either 1.8V or 3.3V provided by vddshv3. However, the vddshv3 supply is only used for input protection
circuitry, not for logic functionality. The logic in this buffer operates entirely on the vdds18v supply. Therefore, these input buffers are fully functional whenever vdds18v is valid.
(10) The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device
TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external
pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
(11) This signal is valid only for High-Security devices. For more details, see 节 5.8, VPP Specification for One-Time Programmable (OTP) eFUSEs. For General Purpose devices do not
connect any signal, test point, or board trace to this signal.
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4.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The name of the signal passing through the pin.
注
The subsystem multiplexing signals are not described in 表 4-1 and 表 4-31.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or output
D = Open Drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
4. BALL: Associated ball(s) bottom
注
For more information, see the Control Module / Control Module Register Manual section of
the Device TRM.
4.3.1 VIP
注
For more information, see the Video Input Port (VIP) section of the Device TRM.
表 4-2. VIP Signal Descriptions
SIGNAL NAME
Video Input 1
vin1a_clk0
DESCRIPTION
TYPE
BALL
Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video
capture. Input data is sampled on the CLK0 edge.
I
G3, J24, Y5
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AA1, B23, F1, J25
B22, E2, Y3
A23, E1, W2
A22, AA3, C1
AA2, B21, D1
A21, D2, Y4
B1, D19, Y1
B2, E19, Y2
C2, F16
D3, E16
A2, E17
A19, B3
B18, C3
B16, C4
A3, B17
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表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
vin1a_d15
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_de0
vin1a_fld0
vin1a_hsync0
vin1a_vsync0
vin1b_clk1
vin1b_d0
DESCRIPTION
TYPE
BALL
A18, B4
M1
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Field ID input
Video Input 1 Port A Field ID input
Video Input 1 Port A Horizontal Sync input
Video Input 1 Port A Vertical Sync input
Video Input 1 Port B Clock input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Field ID input
Video Input 1 Port B Field ID input
Video Input 1 Port B Horizontal Sync input
Video Input 1 Port B Vertical Sync input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
M2
L2
L1
K3
K2
J1
K1
C17, J2, Y6
C16, L3
AA4, B14, K4
AB1, D14, H1
J2, L5
L6, M1
M2, N5
L2, N6
L1, T4
K3, T5
K2, N2
J1, P2
K1, N1
L3, P4
G1, N4
K4, P3
H1, R2
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
vin1b_de1
vin1b_fld1
vin1b_hsync1
vin1b_vsync1
Video Input 2
vin2a_clk0
vin2a_d0
Video Input 2 Port A Clock input.
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D8, L5
C8, L6
B9, N5
A7, N6
A9, T4
A8, T5
A11, N2
F10, P2
A10, N1
B10, P1
E10, N3
D10, R1
C10, P5
B11
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
D11
C11
B12
A12
A13
E11
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表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2b_clk1
vin2b_d0
DESCRIPTION
TYPE
BALL
F11
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Field ID input
Video Input 2 Port A Field ID input
Video Input 2 Port A Horizontal Sync input
Video Input 2 Port A Vertical Sync input
Video Input 2 Port B Clock input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Field ID input
Video Input 2 Port B Field ID input
Video Input 2 Port B Horizontal Sync input
Video Input 2 Port B Vertical Sync input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
B13
E13
C13
D13
B7, P4
B7, C7, N4
E8, P3
B8, R2
AB1, C7, L4, H6
AA1, D13, A4
C13, Y3, E7
E13, W2, D6
AA3, B13, C5
AA2, F11, B5
E11, Y4, D7
A13, Y1, C6
A12, Y2, A5
AA4, B7, H2
B7, H6
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
vin2b_d7
vin2b_de1
vin2b_fld1
vin2b_hsync1
vin2b_vsync1
E8, Y5, B6
B8, Y6, A6
4.3.2 DSS
表 4-3. DSS Signal Descriptions
SIGNAL NAME
DPI Video Output 2
vout2_clk
DESCRIPTION
TYPE
BALL
Video Output 2 Clock output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
C7
vout2_d0
D13
C13
E13
B13
F11
E11
A13
A12
B12
C11
D11
B11
C10
D10
E10
B10
A10
F10
vout2_d1
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vout2_d8
vout2_d9
vout2_d10
vout2_d11
vout2_d12
vout2_d13
vout2_d14
vout2_d15
vout2_d16
vout2_d17
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表 4-3. DSS Signal Descriptions (continued)
SIGNAL NAME
vout2_d18
vout2_d19
vout2_d20
vout2_d21
vout2_d22
vout2_d23
vout2_de
DESCRIPTION
TYPE
O
BALL
A11
A8
Video Output 2 Data output
Video Output 2 Data output
O
Video Output 2 Data output
O
A9
Video Output 2 Data output
O
A7
Video Output 2 Data output
O
B9
Video Output 2 Data output
O
C8
Video Output 2 Data Enable output
Video Output 2 Field ID output. This signal is not used for embedded sync modes.
O
B7
vout2_fld
O
D8
vout2_hsync
Video Output 2 Horizontal Sync output. This signal is not used for embedded sync
modes.
O
E8
vout2_vsync
DPI Video Output 3
vout3_clk
Video Output 2 Vertical Sync output. This signal is not used for embedded sync modes.
O
B8
Video Output 3 Clock output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data Enable output
Video Output 3 Field ID output. This signal is not used for embedded sync modes.
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
G3
F1
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
C3
C4
A3
B4
M1
M2
L2
vout3_d0
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_d10
vout3_d11
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d16
vout3_d17
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vout3_de
L1
K3
K2
J1
K1
J2
vout3_fld
L3
vout3_hsync
Video Output 3 Horizontal Sync output. This signal is not used for embedded sync
modes.
K4
vout3_vsync
Video Output 3 Vertical Sync output. This signal is not used for embedded sync modes.
O
H1
4.3.3 HDMI
注
For more information, see the Display Subsystem / Display Subsystem Overview of the
Device TRM.
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表 4-4. HDMI Signal Descriptions
SIGNAL NAME
hdmi1_cec
DESCRIPTION
TYPE
IOD
BALL
E25, H23
E24, H22
F23
HDMI consumer electronic control
hdmi1_hpd
HDMI display hot plug detect
IO
hdmi1_ddc_scl
hdmi1_ddc_sda
hdmi1_clockx
hdmi1_clocky
hdmi1_data2x
hdmi1_data2y
hdmi1_data1x
hdmi1_data1y
hdmi1_data0x
hdmi1_data0y
HDMI display data channel clock
IOD
HDMI display data channel data
IOD
G21
HDMI clock differential positive or negative
HDMI clock differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 0 differential positive or negative
HDMI data 0 differential positive or negative
ODS
ODS
ODS
ODS
ODS
ODS
ODS
ODS
AE9
AD10
AE14
AD15
AE12
AD13
AE11
AD12
4.3.4 CSI2
注
For more information, see the CAL Subsystem / CAL Subsystem Overview of the Device
TRM.
表 4-5. CSI 2 Signal Descriptions
SIGNAL NAME
csi2_0_dx0
csi2_0_dy0
csi2_0_dx1
csi2_0_dy1
csi2_0_dx2
csi2_0_dy2
DESCRIPTION
TYPE
BALL
AC1
AB2
AD1
AC2
AE2
AD2
Serial data/clock input - lane 0 (position 1)
Serial data/clock input - lane 0 (position 1)
Serial data/clock input - lane 1 (position 2)
Serial data/clock input - lane 1 (position 2)
Serial data/clock input - lane 2 (position 3)
Serial data/clock input - lane 2 (position 3)
I
I
I
I
I
I
4.3.5 EMIF
注
For more information, see the Memory Subsystem / EMIF Controller section of the Device
TRM.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-6, EMIF
Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM
memories.
表 4-6. EMIF Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
AC19
AB18
AD21
AE21
AD18
ddr1_csn0
ddr1_cke
ddr1_ck
EMIF1 Chip Select 0
EMIF1 Clock Enable
O
EMIF1 Clock
O
ddr1_nck
ddr1_odt0
EMIF1 Negative Clock
O
EMIF1 On-Die Termination for Chip Select 0
O
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表 4-6. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
AD16
AD17
AE18
AE17
AE16
AA16
AB16
AC18
AE19
AD19
AB19
AD20
AE20
AA18
AA20
Y21
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_rst
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
EMIF1 Column Address Strobe
EMIF1 Row Address Strobe
O
EMIF1 Write Enable
EMIF1 Reset output (DDR3-SDRAM only)
EMIF1 Bank Address
EMIF1 Bank Address
EMIF1 Bank Address
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Data Bus
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AC20
AA21
AC21
AC22
AC15
AB15
AC16
AA23
AC24
AB24
AD24
AB23
AC23
AD23
AE24
AA24
W25
O
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
Y23
EMIF1 Data Bus
AD25
AC25
AB25
AA25
W24
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
W23
EMIF1 Data Bus
U25
EMIF1 Data Bus
U24
EMIF1 Data Bus
W21
EMIF1 Data Bus
T22
EMIF1 Data Bus
U22
EMIF1 Data Bus
U23
EMIF1 Data Bus
T21
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表 4-6. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
O
BALL
T23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
T25
T24
P21
N21
P22
P23
P24
AE23
W22
U21
P25
O
O
O
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AD22
ddr1_dqsn0
ddr1_dqs1
Data strobe 0 invert
IO
IO
AE22
Y24
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn1
ddr1_dqs2
Data strobe 1 invert
IO
IO
Y25
V24
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn2
ddr1_dqs3
Data strobe 2 invert
IO
IO
V25
R24
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn3
ddr1_vref0
Data strobe 3 invert
IO
A
R25
Y20
Reference Power Supply EMIF1
4.3.6 GPMC
注
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the Device TRM.
表 4-7. GPMC Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO
F1
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
IO
IO
IO
IO
IO
IO
E2
E1
C1
D1
D2
B1
B2
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
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表 4-7. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
IO
C2
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D3
A2
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
B3
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
C3
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
C4
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
A3
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
B4
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
G1, M1
G3, M2
H5, L2
H6, L1
K3
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
gpmc_a3
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
K2
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
J1
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
K1
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
K4
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
H1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
J2
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
L3
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
G1
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
A4, H3, G4
E7, H4, G3
D6, K6, F6
C5, K5, M1
B5, G2, D8
D7, F2, C7
A4(3), C6, H5
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
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表 4-7. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A5, E7(3), L4
gpmc_a20
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
O
O
O
O
O
O
B6, D6(3), H2
A6, C5(3), H6
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
B5, H5, C10, G4
D7(3), D10, G3
C6(3), F6, E10
A5(3), M1, B10
B6(3), D8, C7, E8
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
gpmc_cs0
gpmc_cs1
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC Chip Select 4 (active low)
GPMC Chip Select 5 (active low)
GPMC Chip Select 6 (active low)
GPMC Chip Select 7 (active low)
GPMC Clock output
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
I
F3
A6
gpmc_cs2
G4
G3
H2
gpmc_cs3
gpmc_cs4
gpmc_cs5
H6
gpmc_cs6
H5
gpmc_cs7
L4
gpmc_clk(1)(2)
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_wait1
L4
GPMC address valid active low or address latch enable
GPMC output enable active low or read enable
GPMC write enable active low
H5
G5
G6
H2
GPMC lower-byte enable active low
GPMC upper-byte enable active low
GPMC external indication of wait 0
GPMC external indication of wait 1
H6
F6
I
H5, L4
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See 表 5-49, GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and 表 5-51
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
(3) The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in
the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should
be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to
keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
4.3.7 Timers
注
For more information, see the Timers section of the Device TRM.
表 4-8. Timers Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
timer1
PWM output/event trigger input
IO
H21, H6
74
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表 4-8. Timers Signal Descriptions (continued)
SIGNAL NAME
timer2
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
H2, K22
H5, K23
A16, L4
A18, K6
B17, H4
B16, H3
B18, G1
A19, L3
E17, J2
E16, H1
F16, K4
J25
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
timer3
timer4
timer5
timer6
timer7
timer8
timer9
timer10
timer11
timer12
timer13
timer14
timer15
timer16
J24
AA6, H24
AD3, H25
4.3.8 I2C
注
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C
Controller / HS I2C Environment / HS I2C in I2C Mode section of the Device TRM.
注
I2C1 and I2C2 do NOT support HS-mode.
表 4-9. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 1 (I2C1)
i2c1_scl
I2C1 Clock
I2C1 Data
IOD
IOD
G22
G23
i2c1_sda
Inter-Integrated Circuit Interface 2 (I2C2)
i2c2_scl
I2C2 Clock
I2C2 Data
IOD
IOD
G21
F23
i2c2_sda
Inter-Integrated Circuit Interface 3 (I2C3)
i2c3_scl
I2C3 Clock
I2C3 Data
IOD
IOD
C17, K22, L4, Y6
C16, H21, H5, Y5
i2c3_sda
Inter-Integrated Circuit Interface 4 (I2C4)
i2c4_scl
I2C4 Clock
I2C4 Data
IOD
IOD
B25, D17, M1, V5
C23, D16, M2, U5
i2c4_sda
Inter-Integrated Circuit Interface 5 (I2C5)
i2c5_scl
I2C5 Clock
I2C5 Data
IOD
IOD
B14, K3, U6
i2c5_sda
AC3, D14, K2
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4.3.9 HDQ1W
注
For more information, see the Serial Communication Interface / HDQ/1-Wire section of the
Device TRM.
表 4-10. HDQ / 1-Wire Signal Descriptions
SIGNAL NAME
DESCRIPTION
HDQ or 1-wire protocol single interface pin
TYPE
BALL
hdq0
IOD
H25, J25
4.3.10 UART
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Perypheral Booting / Initialization Phase for UART Boot section of the Device
TRM.
表 4-11. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Asynchronous Receiver/Transmitter 1 (UART1)
uart1_dcdn
uart1_dsrn
uart1_dtrn
uart1_rin
UART1 Data Carrier Detect active low
UART1 Data Set Ready Active Low
UART1 Data Terminal Ready Active Low
UART1 Ring Indicator
I
I
N23
N25
N22
N24
L25
M25
L20
M24
O
I
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
UART1 Receive Data
I
UART1 Transmit Data
O
I
UART1 clear to send active low
UART1 request to send active low
O
Universal Asynchronous Receiver/Transmitter 2 (UART2)
uart2_rxd
uart2_txd
uart2_ctsn
uart2_rtsn
UART2 Receive Data
I
N23
N25
N22
N24
UART2 Transmit Data
O
I
UART2 clear to send active low
UART2 request to send active low
O
Universal Asynchronous Receiver/Transmitter 3 (UART3)/IrDA
uart3_rxd
uart3_txd
uart3_ctsn
uart3_rtsn
uart3_rctx
uart3_sd
UART3 Receive Data
I
AA5, G25, N22, N5
AC4, F25, N24, N6
G24, L6, N23, T4
F24, L5, N25, T5
N23
UART3 Transmit Data
O
I
UART3 clear to send active low
UART3 request to send active low
Remote control data
O
O
O
O
Infrared transceiver configure/shutdown
Infrared data output
N25
uart3_irtx
N24
Universal Asynchronous Receiver/Transmitter 4 (UART4)
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
UART4 Receive Data
I
A24, E24, P4
D23, E25, P3
R2
UART4 Transmit Data
O
I
UART4 clear to send active low
UART4 request to send active low
O
R1
Universal Asynchronous Receiver/Transmitter 5 (UART5)
uart5_rxd UART5 Receive Data
I
B22, G24, M1, Y4
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-11. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
AA2, B23, F24, M2
AA3, L2
uart5_txd
uart5_ctsn
uart5_rtsn
UART5 Transmit Data
O
I
UART5 clear to send active low
UART5 request to send active low
O
L1, W2
Universal Asynchronous Receiver/Transmitter 6 (UART6)
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
UART6 Receive Data
I
D14, K3, U5
B14, K2, V5
C14, J1
UART6 Transmit Data
O
I
UART6 clear to send active low
UART6 request to send active low
O
B15, K1
Universal Asynchronous Receiver/Transmitter 7 (UART7)
uart7_rxd
uart7_txd
uart7_ctsn
uart7_rtsn
UART7 Receive Data
I
A22, L2
A23, L1
B22
UART7 Transmit Data
O
I
UART7 clear to send active low
UART7 request to send active low
O
B23
Universal Asynchronous Receiver/Transmitter 8 (UART8)
uart8_rxd
uart8_txd
uart8_ctsn
uart8_rtsn
UART8 Receive Data
I
C23, H22, J1
B25, H23, K1
A24
UART8 Transmit Data
O
I
UART8 clear to send active low
UART8 request to send active low
O
D23
Universal Asynchronous Receiver/Transmitter 9 (UART9)
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
UART9 Receive Data
I
AC3, E8, L20
B8, M24, U6
AA5, C8
UART9 Transmit Data
O
I
UART9 clear to send active low
UART9 request to send active low
O
AC4, B9
Universal Asynchronous Receiver/Transmitter 10 (UART10)
uart10_rxd
uart10_txd
uart10_ctsn
uart10_rtsn
UART10 Receive Data
I
A7, H21, N22, Y3
A9, AA1, K22, N24
A8, AA4
UART10 Transmit Data
O
I
UART10 clear to send active low
UART10 request to send active low
O
A11, AB1
4.3.11 McSPI
注
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (McSPI) section of the Device TRM.
表 4-12. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Serial Peripheral Interface 1
spi1_sclk(1)
SPI1 Clock
IO
IO
IO
IO
IO
IO
IO
C24
D24
D25
B24
C25
E24
E25
spi1_d1
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Chip Select
spi1_d0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
SPI1 Chip Select
SPI1 Chip Select
SPI1 Chip Select
Serial Peripheral Interface 2
spi2_sclk(1)
SPI2 Clock
IO
G25
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表 4-12. SPI Signal Descriptions (continued)
SIGNAL NAME
spi2_d1
DESCRIPTION
TYPE
IO
BALL
F25
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Chip Select
spi2_d0
IO
G24
F24
spi2_cs0
spi2_cs1
spi2_cs2
spi2_cs3
IO
SPI2 Chip Select
IO
C25
E24
E25
SPI2 Chip Select
IO
SPI2 Chip Select
IO
Serial Peripheral Interface 3
spi3_sclk(1)
SPI3 Clock
IO
IO
IO
IO
IO
A18, C23, N5, Y1
B17, B25, N6, Y4
A24, AA2, B16, T4
AA3, B18, D23, T5
A19, W2
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Chip Select
spi3_d0
spi3_cs0
spi3_cs1
SPI3 Chip Select
Serial Peripheral Interface 4
spi4_sclk(1)
SPI4 Clock
IO
IO
IO
AC3, E8, K4, P4, Y3
AA1, B8, H1, P3, U6
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Data. Can be configured as either MISO or MOSI.
spi4_d0
AA4, AA5, C8, J2,
R2
spi4_cs0
SPI4 Chip Select
IO
AB1, AC4, B9, L3,
R1
spi4_cs1
spi4_cs2
spi4_cs3
SPI4 Chip Select
SPI4 Chip Select
SPI4 Chip Select
IO
IO
IO
G1, N6
H3, T4
H4, T5
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.12 QSPI
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the Device TRM.
表 4-13. QSPI Signal Descriptions
SIGNAL NAME
qspi1_sclk
DESCRIPTION
TYPE
BALL
F2
QSPI1 Serial Clock
IO
I
qspi1_rtclk
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
H3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
K5
qspi1_d1
qspi1_d2
QSPI1 Data[1]. Input read data in all modes.
IO
IO
G2
K6
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
IO
H4
qspi1_cs0
qspi1_cs1
qspi1_cs2
qspi1_cs3
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
QSPI1 Chip Select[1]
IO
O
O
O
G4
G3
L1
QSPI1 Chip Select[2]
QSPI1 Chip Select[3]
K3
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4.3.13 McASP
注
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the Device TRM.
表 4-14. MCASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Multichannel Audio Serial Port 1
McASP1 Transmit/Receive Data
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_fsx
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
D14
B14
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit Frame Sync
McASP1 Receive Bit Clock
C14
B15
A15, J25
A14, J24
A17, H24
A16, H25
A18, H21
B17, K22
B16, K23
B18
A19
E17
E16
F16
C17
mcasp1_aclkr(1)
D16
mcasp1_fsr
McASP1 Receive Frame Sync
McASP1 Transmit High-Frequency Master Clock
McASP1 Transmit Bit Clock
D17
mcasp1_ahclkx
mcasp1_aclkx(1)
J25
IO
C16
Multichannel Audio Serial Port 2
McASP2 Transmit/Receive Data
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_axr8
mcasp2_axr9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr12
mcasp2_axr13
mcasp2_axr14
mcasp2_axr15
mcasp2_fsx
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
A20
B19
A21
B21
B20
C19
D20
C20
J25
J24
H24
H25
A22
A23
B22
B23
D19
J24
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit Frame Sync
McASP2 Transmit High-Frequency Master Clock
mcasp2_ahclkx
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表 4-14. MCASP Signal Descriptions (continued)
SIGNAL NAME
mcasp2_aclkx(1)
DESCRIPTION
McASP2 Transmit Bit Clock
TYPE
BALL
IO
E19
Multichannel Audio Serial Port 3
mcasp3_axr0
mcasp3_axr1
mcasp3_axr2
mcasp3_axr3
mcasp3_fsx
McASP3 Transmit/Receive Data
IO
IO
IO
IO
IO
O
B22
B23
A21
B21
A23
H24
A22
A22
A23
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit Frame Sync
McASP3 Transmit High-Frequency Master Clock
McASP3 Transmit Bit Clock
mcasp3_ahclkx
mcasp3_aclkx(1)
mcasp3_aclkr(1)
mcasp3_fsr
IO
IO
IO
McASP3 Receive Bit Clock
McASP3 Receive Frame Sync
Multichannel Audio Serial Port 4
mcasp4_axr0
mcasp4_axr1
mcasp4_axr2
mcasp4_axr3
mcasp4_fsx
McASP4 Transmit/Receive Data
IO
IO
IO
IO
IO
O
A24
D23
A15
A14
B25
H25
C23
C23
B25
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit Frame Sync
McASP4 Transmit High-Frequency Master Clock
McASP4 Transmit Bit Clock
mcasp4_ahclkx
mcasp4_aclkx(1)
mcasp4_aclkr(1)
mcasp4_fsr
IO
IO
IO
McASP4 Receive Bit Clock
McASP4 Receive Frame Sync
Multichannel Audio Serial Port 5
mcasp5_axr0
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_fsx
McASP5 Transmit/Receive Data
IO
IO
IO
IO
IO
O
AA5
AC4
A17
A16
U6
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit Frame Sync
McASP5 Transmit High-Frequency Master Clock
McASP5 Transmit Bit Clock
mcasp5_ahclkx
mcasp5_aclkx(1)
mcasp5_aclkr(1)
mcasp5_fsr
J25
AC3
AC3
U6
IO
IO
IO
McASP5 Receive Bit Clock
McASP5 Receive Frame Sync
Multichannel Audio Serial Port 6
mcasp6_axr0
mcasp6_axr1
mcasp6_axr2
mcasp6_axr3
mcasp6_ahclkx
mcasp6_aclkx(1)
mcasp6_fsx
McASP6 Transmit/Receive Data
IO
IO
IO
IO
O
A18
B17
C14
B15
J24
B16
B18
B16
B18
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit High-Frequency Master Clock
McASP6 Transmit Bit Clock
IO
IO
IO
IO
McASP6 Transmit Frame Sync
McASP6 Receive Bit Clock
mcasp6_aclkr(1)
mcasp6_fsr
McASP6 Receive Frame Sync
Multichannel Audio Serial Port 7
mcasp7_aclkr(1)
mcasp7_aclkx(1)
mcasp7_ahclkx
mcasp7_axr0
McASP7 Receive Bit Clock
IO
IO
O
E16
E16
H24
A19
E17
McASP7 Transmit Bit Clock
McASP7 Transmit High-Frequency Master Clock
McASP7 Transmit/Receive Data
McASP7 Transmit/Receive Data
IO
IO
mcasp7_axr1
80
Terminal Configuration and Functions
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AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-14. MCASP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
IO
BALL
D16
D17
F16
mcasp7_axr2
mcasp7_axr3
mcasp7_fsr
mcasp7_fsx
McASP7 Transmit/Receive Data
McASP7 Transmit/Receive Data
McASP7 Receive Frame Sync
McASP7 Transmit Frame Sync
IO
IO
IO
F16
Multichannel Audio Serial Port 8
mcasp8_aclkr(1)
mcasp8_aclkx(1)
mcasp8_ahclkx
mcasp8_axr0
mcasp8_axr1
mcasp8_fsr
McASP8 Receive Bit Clock
IO
IO
O
D20
D20
H25
B20
C19
C20
C20
McASP8 Transmit Bit Clock
McASP8 Transmit High-Frequency Master Clock
McASP8 Transmit/Receive Data
McASP8 Transmit/Receive Data
McASP8 Receive Frame Sync
IO
IO
IO
IO
mcasp8_fsx
McASP8 Transmit Frame Sync
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.14 USB
注
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the Device TRM.
表 4-15. Universal Serial Bus Signal Descriptions
SIGNAL NAME
Universal Serial Bus 1
usb1_dm
DESCRIPTION
TYPE
BALL
USB1 USB2.0 differential signal pair (negative)
USB1 USB2.0 differential signal pair (positive)
USB1 Drive VBUS signal
IODS
IODS
O
AB7
AC6
AD3
AE5
AD6
AE3
AD4
usb1_dp
usb1_drvvbus
usb_rxn0(1)
usb_rxp0(1)
usb_txn0(1)
usb_txp0(1)
USB1 USB3.0 receiver negative lane
USB1 USB3.0 receiver positive lane
USB1 USB3.0 transmitter negative lane
USB1 USB3.0 transmitter positive lane
IDS
IDS
ODS
ODS
Universal Serial Bus 2
usb2_dm
USB2 USB2.0 differential signal pair (negative)
USB2 USB2.0 differential signal pair (positive)
USB2 Drive VBUS signal
IO
IO
O
AC5
AB6
AA6
usb2_dp
usb2_drvvbus
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.3.15 PCIe
注
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Subsystem sections of the Device
TRM.
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81
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表 4-16. PCIe Signal Descriptions
SIGNAL NAME
pcie_rxn0
pcie_rxp0
pcie_txn0
DESCRIPTION
TYPE
IDS
BALL
AE6
AD7
AE8
AD9
AE5
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.
IDS
ODS
ODS
IDS
pcie_txp0
pcie_rxn1
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
pcie_rxp1
pcie_txn1
pcie_txp1
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IDS
ODS
ODS
AD6
AE3
AD4
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
ljcb_clkn
ljcb_clkp
PCIe1_PHY shared Reference Clock Input / Output Differential Pair (negative)
PCIe1_PHY shared Reference Clock Input / Output Differential Pair (positive)
IODS
IODS
AB9
AC8
4.3.16 DCAN
注
For more information, see the Serial Communication Interface / DCAN section of the Device
TRM.
表 4-17. DCAN Signal Descriptions
SIGNAL NAME
DCAN 1
DESCRIPTION
TYPE
BALL
dcan1_rx
DCAN1 receive data pin
DCAN1 transmit data pin
IO
IO
H23, AC10
H22
dcan1_tx
DCAN 2
dcan2_rx
DCAN2 receive data pin
DCAN2 transmit data pin
IO
IO
E25, K22, AB10
E24, H21
dcan2_tx
4.3.17 GMAC_SW
注
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the Device TRM.
表 4-18. GMAC Signal Descriptions
SIGNAL NAME
rgmii0_rxc
DESCRIPTION
TYPE
BALL
N2
P2
RGMII0 Receive Clock
RGMII0 Receive Control
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Transmit Clock
RGMII0 Transmit Enable
RGMII0 Transmit Data
I
I
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
I
N4
N3
P1
I
I
I
N1
T4
O
O
O
rgmii0_txctl
rgmii0_txd0
T5
R1
82
Terminal Configuration and Functions
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AM5706, AM5708
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-18. GMAC Signal Descriptions (continued)
SIGNAL NAME
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd0
rgmii1_rxd1
rgmii1_rxd2
rgmii1_rxd3
rgmii1_txc
rgmii1_txctl
rgmii1_txd0
rgmii1_txd1
rgmii1_txd2
rgmii1_txd3
mii1_col
DESCRIPTION
TYPE
BALL
R2
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII1 Receive Clock
RGMII1 Receive Control
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Transmit Clock
RGMII1 Transmit Enable
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
MII1 Collision Detect (Sense)
MII1 Carrier Sense
O
O
O
I
P3
P4
E11
F11
D13
C13
E13
B13
B11
D11
A13
A12
B12
C11
E13
C13
B11
E10
F10
A10
B10
D11
B13
C11
B12
A12
A13
E11
D13
F11
L5
I
I
I
I
I
O
O
O
O
O
O
I
mii1_crs
I
mii1_rxclk
mii1_rxd0
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxdv
mii1_rxer
MII1 Receive Clock
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data Valid
MII1 Receive Data Error
MII1 Transmit Clock
MII1 Transmit Data
I
I
mii1_txclk
mii1_txd0
mii1_txd1
mii1_txd2
mii1_txd3
mii1_txen
mii1_txer
I
O
O
O
O
O
O
I
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data Enable
MII1 Transmit Error
mii0_col
MII0 Collision Detect (Sense)
MII0 Carrier Sense
mii0_crs
I
P4
mii0_rxclk
mii0_rxd0
mii0_rxd1
mii0_rxd2
mii0_rxd3
mii0_rxdv
mii0_rxer
MII0 Receive Clock
I
N6
MII0 Receive Data
I
R1
MII0 Receive Data
I
R2
MII0 Receive Data
I
T5
MII0 Receive Data
I
T4
MII0 Receive Data Valid
MII0 Receive Data Error
MII0 Transmit Clock
MII0 Transmit Data
I
N5
I
P3
mii0_txclk
mii0_txd0
mii0_txd1
mii0_txd2
mii0_txd3
mii0_txen
mii0_txer
I
N2
O
O
O
O
O
O
N4
MII0 Transmit Data
N3
MII0 Transmit Data
N1
MII0 Transmit Data
P2
MII0 Transmit Data Enable
MII0 Transmit Error
P1
L6
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表 4-18. GMAC Signal Descriptions (continued)
SIGNAL NAME
rmii1_crs
DESCRIPTION
TYPE
BALL
RMII1 Carrier Sense
I
I
N5
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
rmii0_crs
RMII1 Receive Data
T5
RMII1 Receive Data
I
T4
RMII1 Receive Data Error
RMII1 Transmit Data
RMII1 Transmit Data
RMII1 Transmit Data Enable
RMII0 Carrier Sense
I
N6
O
O
O
I
N1
P2
N2
P4
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_txd0
rmii0_txd1
rmii0_txen
mdio_mclk
mdio_d
RMII0 Receive Data
I
R1
RMII0 Receive Data
I
R2
RMII0 Receive Data Error
RMII0 Transmit Data
RMII0 Transmit Data
RMII0 Transmit Data Enable
Management Data Serial Clock
Management Data
I
P3
O
O
O
O
IO
N4
N3
P1
D10, E24, L5, Y5
C10, E25, L6, Y6
4.3.18 MLB
注
Media Local Bus (MLB) is not available on this device, and must be left unconnected.
表 4-19. MLB Signal Descriptions
SIGNAL NAME
mlbp_clk_n
mlbp_clk_p
mlbp_dat_n
mlbp_dat_p
mlbp_sig_n
mlbp_sig_p
DESCRIPTION
TYPE
IDS
BALL
U1
Media Local Bus (MLB) Subsystem clock differential pair (negative)
Media Local Bus (MLB) Subsystem clock differential pair (positive)
Media Local Bus (MLB) Subsystem data differential pair (negative)
Media Local Bus (MLB) Subsystem data differential pair (positive)
Media Local Bus (MLB) Subsystem signal differential pair (negative)
Media Local Bus (MLB) Subsystem signal differential pair (positive)
IDS
U2
IODS
IODS
IODS
IODS
T1
T2
U4
T3
4.3.19 eMMC/SD/SDIO
注
For more information, see the HS MMC/SDIO section of the Device TRM.
表 4-20. eMMC/SD/SDIO Signal Descriptions
SIGNAL NAME
Multi Media Card 1
mmc1_clk(1)
DESCRIPTION
TYPE
BALL
MMC1 clock
IO
IO
IO
IO
IO
IO
I
U3
V4
V3
V2
W1
V1
U5
mmc1_cmd
MMC1 command
MMC1 data bit 0
MMC1 data bit 1
MMC1 data bit 2
MMC1 data bit 3
MMC1 Card Detect
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
84
Terminal Configuration and Functions
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AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-20. eMMC/SD/SDIO Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
mmc1_sdwp
Multi Media Card 2
mmc2_clk(1)
mmc2_cmd
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_sdcd
mmc2_sdwp
Multi Media Card 3
mmc3_clk(1)
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
mmc3_sdcd
mmc3_sdwp
Multi Media Card 4
mmc4_clk(1)
mmc4_cmd
mmc4_sdcd
mmc4_sdwp
mmc4_dat0
mmc4_dat1
mmc4_dat2
mmc4_dat3
MMC1 Write Protect
I
V5
MMC2 clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
B5
A6
MMC2 command
MMC2 data bit 0
MMC2 data bit 1
MMC2 data bit 2
MMC2 data bit 3
MMC2 data bit 4
MMC2 data bit 5
MMC2 data bit 6
MMC2 data bit 7
MMC2 Card Detect
MMC2 Write Protect
D7
C6
A5
B6
A4
E7
D6
C5
H22
H23
I
MMC3 clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
Y2
Y1
MMC3 command
MMC3 data bit 0
MMC3 data bit 1
MMC3 data bit 2
MMC3 data bit 3
MMC3 data bit 4
MMC3 data bit 5
MMC3 data bit 6
MMC3 data bit 7
MMC3 Card Detect
MMC3 Write Protect
Y4
AA2
AA3
W2
Y3
AA1
AA4
AB1
E24
E25
I
MMC4 clock
IO
IO
I
L20
M24
L25
MMC4 command
MMC4 Card Detect
MMC4 Write Protect
MMC4 data bit 0
MMC4 data bit 1
MMC4 data bit 2
MMC4 data bit 3
I
M25
N23
N25
N22
N24
IO
IO
IO
IO
(1) By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer
to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal
loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as
close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad
loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.20 GPIO
注
For more information, see the General-Purpose Interface section of the Device TRM.
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www.ti.com.cn
表 4-21. GPIOs Signal Descriptions
SIGNAL NAME
GPIO 1
DESCRIPTION
TYPE
BALL
gpio1_0
gpio1_3
General-Purpose Input
General-Purpose Input
I
AC10
AB10
B20
C20
F1
I
gpio1_4
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
gpio1_5
gpio1_6
gpio1_7
E2
gpio1_8
E1
gpio1_9
C1
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
gpio1_20
gpio1_21
gpio1_22
gpio1_23
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
D1
D2
B1
B2
H22
H23
N22
N24
C3
C4
A3
B4
Y3
AA1
AA4
AB1
K3
K2
J1
K1
K4
H1
GPIO2
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J2
L3
G1
H3
H4
K6
K5
G2
F2
A4
E7
D6
C5
B5
D7
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-21. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
gpio2_29
GPIO 3
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
C6
A5
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
B6
A6
F3
G4
G3
L4
H5
G5
G6
H2
H6
F6
D20
gpio3_28
gpio3_29
gpio3_30
gpio3_31
GPIO 4
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
D8
B7
C7
E8
gpio4_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B8
C8
gpio4_1
gpio4_2
B9
gpio4_3
A7
gpio4_4
A9
gpio4_5
A8
gpio4_6
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
B18
A19
A12
A13
E11
F11
B13
E13
C13
gpio4_7
gpio4_8
gpio4_9
gpio4_10
gpio4_11
gpio4_12
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_24
gpio4_25
gpio4_26
gpio4_27
gpio4_28
gpio4_29
gpio4_30
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表 4-21. GPIOs Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpio4_31
General-Purpose Input/Output
IO
D13
GPIO 5
gpio5_0
gpio5_1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D16
D17
D14
B14
C14
B15
A15
A14
A17
A16
A18
B17
B16
A22
A23
L5
gpio5_2
gpio5_3
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
gpio5_10
gpio5_11
gpio5_12
gpio5_13
gpio5_14
gpio5_15
gpio5_16
gpio5_17
gpio5_18
gpio5_19
gpio5_20
gpio5_21
gpio5_22
gpio5_23
gpio5_24
gpio5_25
gpio5_26
gpio5_27
gpio5_28
gpio5_29
gpio5_30
gpio5_31
L6
P5
N5
N6
T4
T5
P4
P3
R2
R1
N2
P2
N1
P1
N3
N4
GPIO 6
gpio6_4
gpio6_5
gpio6_6
gpio6_7
gpio6_8
gpio6_9
gpio6_10
gpio6_11
gpio6_12
gpio6_13
gpio6_14
gpio6_15
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E17
E16
F16
C19
A21
B21
Y5
Y6
AD3
AA6
H21
K22
88
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-21. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio6_16
gpio6_17
gpio6_18
gpio6_19
gpio6_20
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
gpio6_26
gpio6_27
gpio6_28
gpio6_29
gpio6_30
gpio6_31
GPIO 7
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
K23
J25
J24
H24
H25
U3
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
V4
V3
V2
W1
V1
U5
V5
Y2
Y1
Y4
gpio7_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AA2
AA3
W2
gpio7_1
gpio7_2
gpio7_3
M1
gpio7_4
M2
gpio7_5
L2
gpio7_6
L1
gpio7_7
C24
D24
D25
B24
C25
E24
E25
G25
F25
G24
F24
C2
gpio7_8
gpio7_9
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
gpio7_15
gpio7_16
gpio7_17
gpio7_18
gpio7_19
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
gpio7_28
gpio7_29
gpio7_30
gpio7_31
D3
L25
M25
L20
M24
N23
N25
A2
B3
C17
C16
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BALL
表 4-21. GPIOs Signal Descriptions (continued)
SIGNAL NAME
GPIO 8
DESCRIPTION
TYPE
gpio8_27
gpio8_28
General-Purpose Input
I
L23
J20
K25
C21
C22
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
gpio8_29
gpio8_30(1)
gpio8_31(1)
(1) gpio8_30 is multiplexed with EMU0 and gpio8_31 is multiplexed with EMU1. These pins will be sampled at reset release by the test and
emulation logic. Therefore, if they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can
be controlled by logic driven from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
4.3.21 KBD
注
For more information, see Keyboard Controller section of the Device TRM.
表 4-22. Keyboard Signal Descriptions
SIGNAL NAME
kbd_row0
kbd_row1
kbd_row2
kbd_row3
kbd_row4
kbd_row5
kbd_row6
kbd_row7
kbd_row8
kbd_col0
kbd_col1
kbd_col2
kbd_col3
kbd_col4
kbd_col5
kbd_col6
kbd_col7
kbd_col8
DESCRIPTION
Keypad row 0
TYPE
BALL
D8
I
I
Keypad row 1
B7
Keypad row 2
I
E8
Keypad row 3
I
B8
Keypad row 4
I
C8
Keypad row 5
I
B9
Keypad row 6
I
A7
Keypad row 7
I
C10
D11
A9
Keypad row 8
I
Keypad column 0
Keypad column 1
Keypad column 2
Keypad column 3
Keypad column 4
Keypad column 5
Keypad column 6
Keypad column 7
Keypad column 8
O
O
O
O
O
O
O
O
O
A8
A11
F10
A10
B10
E10
D10
B11
4.3.22 PWM
注
For more information, see the Pulse-Width Modulation (PWM) SS section of the Device
TRM.
表 4-23. PWM Signal Descriptions
SIGNAL NAME
PWMSS1
DESCRIPTION
TYPE
BALL
eCAP1_in_PWM1_out ECAP1 Capture Input / PWM Output
IO
A7
90
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-23. PWM Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A9
ehrpwm1_synci
ehrpwm1_synco
EHRPWM1 Sync Input
EHRPWM1 Sync Output
I
O
IO
A8
ehrpwm1_tripzone_in EHRPWM1 Trip Zone Input
put
B9
ehrpwm1A
ehrpwm1B
EHRPWM1 Output A
EHRPWM1 Output B
EQEP1 Index Input
O
O
IO
IO
I
B8
C8
C7
E8
D8
B7
eQEP1_index
eQEP1_strobe
eQEP1A_in
eQEP1B_in
EQEP1 Strobe Input
EQEP1 Quadrature Input A
EQEP1 Quadrature Input B
I
PWMSS2
eCAP2_in_PWM2_out ECAP2 Capture Input / PWM Output
IO
IO
B11, Y1
C10, Y2
ehrpwm2_tripzone_in EHRPWM2 Trip Zone Input
put
ehrpwm2A
ehrpwm2B
EHRPWM2 Output A
EHRPWM2 Output B
EQEP2 Index Input
O
O
IO
IO
I
E10, Y5
D10, Y6
A10
eQEP2_index
eQEP2_strobe
eQEP2A_in
eQEP2B_in
EQEP2 Strobe Input
B10
EQEP2 Quadrature Input A
EQEP2 Quadrature Input B
A11
I
F10
PWMSS3
eCAP3_in_PWM3_out ECAP3 Capture Input / PWM Output
IO
IO
AB1, B13
AA4, F11
ehrpwm3_tripzone_in EHRPWM3 Trip Zone Input
put
ehrpwm3A
ehrpwm3B
EHRPWM3 Output A
EHRPWM3 Output B
EQEP3 Index Input
O
O
IO
IO
I
A13, Y3
AA1, E11
AA3, B12
A12, W2
D11, Y4
eQEP3_index
eQEP3_strobe
eQEP3A_in
eQEP3B_in
EQEP3 Strobe Input
EQEP3 Quadrature Input A
EQEP3 Quadrature Input B
I
AA2, C11
4.3.23 PRU-ICSS
注
For more information, see the Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem section of the Device TRM.
表 4-24. PRU-ICSS Signal Descriptions
SIGNAL NAME
PRU-ICSS1
DESCRIPTION
TYPE
BALL
pr1_ecap0_ecap_capin Capture Input / PWM output
_apwm_o
IO
A7
pr1_edc_sync0_out
pr1_edio_data_in0
pr1_edio_data_in1
pr1_edio_data_in2
pr1_edio_data_in3
pr1_edio_data_in4
SYNC 0 Output
O
I
A8
D8
B7
C7
E8
B8
Ethernet Digital Input
Ethernet Digital Input
Ethernet Digital Input
Ethernet Digital Input
Ethernet Digital Input
I
I
I
I
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表 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
pr1_edio_data_in5
pr1_edio_data_in6
pr1_edio_data_in7
pr1_edio_data_out0
pr1_edio_data_out1
pr1_edio_data_out2
pr1_edio_data_out3
pr1_edio_data_out4
pr1_edio_data_out5
pr1_edio_data_out6
pr1_edio_data_out7
pr1_edio_sof
DESCRIPTION
TYPE
BALL
C8
Ethernet Digital Input
Ethernet Digital Input
Ethernet Digital Input
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Ethernet Digital Output
Start Of Frame
I
I
B9
I
A7
O
O
O
O
O
O
O
O
O
IO
O
I
D8
B7
C7
E8
B8
C8
B9
A7
A11
C10
D10
A9
pr1_mdio_data
pr1_mdio_mdclk
pr1_edc_latch0_in
pr1_mii0_col
MDIO Data
MDIO Clock
Latch Input 0
MII0 Collision Detect
MII0 Carrier Sense
MII0 Receive Data
MII0 Receive Data
MII0 Receive Data
MII0 Receive Data
MII0 Data Valid
I
L5
pr1_mii0_crs
I
P4
pr1_mii0_rxd0
I
R1
pr1_mii0_rxd1
I
R2
pr1_mii0_rxd2
I
T5
pr1_mii0_rxd3
I
T4
pr1_mii0_rxdv
I
N5
pr1_mii0_rxer
MII0 Receive Error
MII0 Receive Link
I
P3
pr1_mii0_rxlink
pr1_mii0_txd0
I
L6
MII0 Transmit Data
MII0 Transmit Data
MII0 Transmit Data
MII0 Transmit Data
MII0 Transmit Enable
MII1 Collision Detect
MII1 Carrier Sense
MII1 Receive Data
MII1 Receive Data
MII1 Receive Data
MII1 Receive Data
MII1 Data Valid
O
O
O
O
O
I
N4
pr1_mii0_txd1
N3
pr1_mii0_txd2
N1
pr1_mii0_txd3
P2
pr1_mii0_txen
P1
pr1_mii1_col
C13
D13
F11
E11
A13
A12
B12
B13
E13
D11
B11
E10
B10
A10
N6
pr1_mii1_crs
I
pr1_mii1_rxd0
I
pr1_mii1_rxd1
I
pr1_mii1_rxd2
I
pr1_mii1_rxd3
I
pr1_mii1_rxdv
I
pr1_mii1_rxer
MII1 Receive Error
MII1 Receive Link
I
pr1_mii1_rxlink
pr1_mii1_txd0
I
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Enable
MII0 Master Receive Clock
MII1 Master Receive Clock
MII0 Master Transmit Clock
MII1 Master Transmit Clock
O
O
O
O
O
I
pr1_mii1_txd1
pr1_mii1_txd2
pr1_mii1_txd3
pr1_mii1_txen
pr1_mii_mr0_clk
pr1_mii_mr1_clk
pr1_mii_mt0_clk
pr1_mii_mt1_clk
I
C11
N2
I
I
F10
92
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A9
pr1_pru1_gpi0
pr1_pru1_gpi1
pr1_pru1_gpi2
pr1_pru1_gpi3
pr1_pru1_gpi4
pr1_pru1_gpi5
pr1_pru1_gpi6
pr1_pru1_gpi7
pr1_pru1_gpi8
pr1_pru1_gpi9
pr1_pru1_gpi10
pr1_pru1_gpi11
pr1_pru1_gpi12
pr1_pru1_gpi13
pr1_pru1_gpi14
pr1_pru1_gpi15
pr1_pru1_gpi16
pr1_pru1_gpi17
pr1_pru1_gpi18
pr1_pru1_gpi19
pr1_pru1_gpi20
pr1_pru1_gpo0
pr1_pru1_gpo1
pr1_pru1_gpo2
pr1_pru1_gpo3
pr1_pru1_gpo4
pr1_pru1_gpo5
pr1_pru1_gpo6
pr1_pru1_gpo7
pr1_pru1_gpo8
pr1_pru1_gpo9
pr1_pru1_gpo10
pr1_pru1_gpo11
pr1_pru1_gpo12
pr1_pru1_gpo13
pr1_pru1_gpo14
pr1_pru1_gpo15
pr1_pru1_gpo16
pr1_pru1_gpo17
pr1_pru1_gpo18
pr1_pru1_gpo19
pr1_pru1_gpo20
pr1_uart0_cts_n
pr1_uart0_rts_n
pr1_uart0_rxd
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
UART Clear-To-Send
I
I
A8
I
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
A9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
A8
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
E8
UART Ready-To-Send
O
I
B8
UART Receive Data
C8
pr1_uart0_txd
UART Transmit Data
O
B9
PRU-ICSS 2
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表 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
pr2_mdio_data
DESCRIPTION
TYPE
BALL
AC4, C17
AA5, C16
A23
A22
A21
D19
E19
F16
E16
D14
B21
A19
B18
B16
B17
A18
J25
MDIO Data
IO
O
I
pr2_mdio_mdclk
pr2_mii0_col
MDIO Clock
MII0 Collision Detect
MII0 Carrier Sense
pr2_mii0_crs
I
pr2_mii0_rxd0
pr2_mii0_rxd1
pr2_mii0_rxd2
pr2_mii0_rxd3
pr2_mii0_rxdv
pr2_mii0_rxer
pr2_mii0_rxlink
pr2_mii0_txd0
pr2_mii0_txd1
pr2_mii0_txd2
pr2_mii0_txd3
pr2_mii0_txen
pr2_mii1_col
MII0 Receive Data
I
MII0 Receive Data
I
MII0 Receive Data
I
MII0 Receive Data
I
MII0 Data Valid
I
MII0 Receive Error
I
MII0 Receive Link
I
MII0 Transmit Data
O
O
O
O
O
I
MII0 Transmit Data
MII0 Transmit Data
MII0 Transmit Data
MII0 Transmit Enable
MII1 Collision Detect
MII1 Carrier Sense
pr2_mii1_crs
I
J24
pr2_mii1_rxd0
pr2_mii1_rxd1
pr2_mii1_rxd2
pr2_mii1_rxd3
pr2_mii1_rxdv
pr2_mii1_rxer
pr2_mii1_rxlink
pr2_mii1_txd0
pr2_mii1_txd1
pr2_mii1_txd2
pr2_mii1_txd3
pr2_mii1_txen
pr2_mii_mr0_clk
pr2_mii_mr1_clk
pr2_mii_mt0_clk
pr2_mii_mt1_clk
pr2_pru0_gpi0
pr2_pru0_gpi1
pr2_pru0_gpi2
pr2_pru0_gpi3
pr2_pru0_gpi4
pr2_pru0_gpi5
pr2_pru0_gpi6
pr2_pru0_gpi7
pr2_pru0_gpi8
pr2_pru0_gpi9
pr2_pru0_gpi10
pr2_pru0_gpi11
pr2_pru0_gpi12
MII1 Receive Data
I
AB1
AA4
AA1
Y3
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Data Valid
I
W2
MII1 Receive Error
I
B22
B23
AA2
Y4
MII1 Receive Link
I
MII1 Transmit Data
O
O
O
O
O
I
MII1 Transmit Data
MII1 Transmit Data
Y1
MII1 Transmit Data
Y2
MII1 Transmit Enable
MII0 Master Receive Clock
MII1 Master Receive Clock
MII0 Master Transmit Clock
MII1 Master Transmit Clock
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
Y6
E17
AA3
B14
Y5
I
I
I
I
Y5
I
Y6
I
Y2
I
Y1
I
Y4
I
AA2
AA3
W2
I
I
I
Y3
I
AA1
AA4
AB1
A22
I
I
I
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表 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A23
pr2_pru0_gpi13
pr2_pru0_gpi14
pr2_pru0_gpi15
pr2_pru0_gpi16
pr2_pru0_gpi17
pr2_pru0_gpi18
pr2_pru0_gpi19
pr2_pru0_gpi20
pr2_pru0_gpo0
pr2_pru0_gpo1
pr2_pru0_gpo2
pr2_pru0_gpo3
pr2_pru0_gpo4
pr2_pru0_gpo5
pr2_pru0_gpo6
pr2_pru0_gpo7
pr2_pru0_gpo8
pr2_pru0_gpo9
pr2_pru0_gpo10
pr2_pru0_gpo11
pr2_pru0_gpo12
pr2_pru0_gpo13
pr2_pru0_gpo14
pr2_pru0_gpo15
pr2_pru0_gpo16
pr2_pru0_gpo17
pr2_pru0_gpo18
pr2_pru0_gpo19
pr2_pru0_gpo20
pr2_pru1_gpi0
pr2_pru1_gpi1
pr2_pru1_gpi2
pr2_pru1_gpi3
pr2_pru1_gpi4
pr2_pru1_gpi5
pr2_pru1_gpi6
pr2_pru1_gpi7
pr2_pru1_gpi8
pr2_pru1_gpi9
pr2_pru1_gpi10
pr2_pru1_gpi11
pr2_pru1_gpi12
pr2_pru1_gpi13
pr2_pru1_gpi14
pr2_pru1_gpi15
pr2_pru1_gpi16
pr2_pru1_gpo0
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Input
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU0 General-Purpose Output
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Input
PRU1 General-Purpose Output
I
I
B22
I
B23
I
A21
I
B21
I
E19
I
D19
I
F16
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Y5
Y6
Y2
Y1
Y4
AA2
AA3
W2
Y3
AA1
AA4
AB1
A22
A23
B22
B23
A21
B21
E19
D19
F16
D23, L5
AC3, L6
U6, P5
AA5, N5
AC4, N6
J25, T4
J24, T5
C16, P4
D14, P3
B14, R2
A18, R1
B17, N2
B16, P2
B18, N1
A19, P1
E17, N3
E16, N4
D23, L5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
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表 4-24. PRU-ICSS Signal Descriptions (continued)
SIGNAL NAME
pr2_pru1_gpo1
DESCRIPTION
TYPE
O
BALL
AC3, L6
U6, P5
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
PRU1 General-Purpose Output
pr2_pru1_gpo2
pr2_pru1_gpo3
pr2_pru1_gpo4
pr2_pru1_gpo5
pr2_pru1_gpo6
pr2_pru1_gpo7
pr2_pru1_gpo8
pr2_pru1_gpo9
pr2_pru1_gpo10
pr2_pru1_gpo11
pr2_pru1_gpo12
pr2_pru1_gpo13
pr2_pru1_gpo14
pr2_pru1_gpo15
pr2_pru1_gpo16
O
O
AA5, N5
AC4, N6
J25, T4
J24, T5
C16, P4
D14, P3
B14, R2
A18, R1
B17, N2
B16, P2
B18, N1
A19, P1
E17, N3
E16, N4
O
O
O
O
O
O
O
O
O
O
O
O
O
注
PRU-ICSS has an internal wrapper multiplexing that allows MII_RT, EnDAT, and Sigma
Delta functionality to be muxed with the PRU GPI/O signals. See PRU-ICSS I/O Interface in
device TRM. Additionally, the EGPIO module can also be configured to export additional
functions to EGPIO pins in place of simple GPIO. See Enhanced General-Purpose
Module/Serial Capture Unit in Device TRM.
4.3.24 Emulation and Debug Subsystem
注
For more information, see the On-Chip Debug Support / Debug Ports section of the Device
TRM.
表 4-25. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
IO
L21
tdi
tdo
JTAG test data
JTAG test port data
JTAG test clock
JTAG test reset
JTAG return clock
Emulator pin 0
Emulator pin 1
Emulator pin 2
Emulator pin 3
Emulator pin 4
Emulator pin 5
Emulator pin 6
Emulator pin 7
Emulator pin 8
I
L23
J20
K21
L22
K25
C21
C22
E14
F14
F13
D8
O
I
tclk
trstn
I
rtck
O
IO
IO
IO
IO
IO
O
O
O
O
emu0(1)
emu1(1)
emu2
emu3
emu4
emu5
emu6
emu7
emu8
B7
C7
E8
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表 4-25. Debug Signal Descriptions (continued)
SIGNAL NAME
emu9
DESCRIPTION
Emulator pin 9
Emulator pin 10
Emulator pin 11
Emulator pin 12
Emulator pin 13
Emulator pin 14
Emulator pin 15
Emulator pin 16
Emulator pin 17
Emulator pin 18
Emulator pin 19
TYPE
O
BALL
B8
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
O
C8
O
B9
O
A7
O
A9
O
A8
O
A11
F10
A10
B10
E10
O
O
O
O
(1) EMU0 and EMU1 are multiplexed with GPIO. These pins will be sampled at reset release by the test and emulation logic. Therefore, if
they are used as GPIO pins, they must return to the high state whenever the device enters reset. This can be controlled by logic driven
from rstoutn. After the device exits reset (indicated by rstoutn rising), these can return to GPIO mode.
4.3.25 System and Miscellaneous
4.3.25.1 Sysboot
注
For more information, see the Initialization (ROM Code) section of the Device TRM.
表 4-26. Sysboot Signal Descriptions
SIGNAL NAME DESCRIPTION
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
TYPE
BALL
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
sysboot10
sysboot11
sysboot12
sysboot13
I
F1
will determine the boot mode configuration of the device.
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
I
I
I
I
I
I
I
I
I
I
I
I
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
C3
C4
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
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表 4-26. Sysboot Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
sysboot14
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
I
A3
will determine the boot mode configuration of the device.
sysboot15
Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
B4
4.3.25.2 Power, Reset, and Clock Management (PRCM)
注
For more information, see PRCM section of the Device TRM.
表 4-27. PRCM Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
clkout1
Device Clock output 1. Can be used externally for devices with non-
critical timing requirements, or for debug, or as a reference clock on
GPMC as described in 表 5-49, GPMC/NOR Flash Interface
Switching Characteristics - Synchronous Mode - Default and 表 5-51,
GPMC/NOR Flash Interface Switching Characteristics - Synchronous
Mode - Alternate.
O
K23, L4
clkout2
clkout3
porz
Device Clock output 2. Can be used externally for devices with non-
critical timing requirements, or for debug.
O
O
I
H5, J25
H25
Device Clock output 3. Can be used xternally for devices with non-
critical timing requirements, or for debug.
Power on Reset (active low). This pin must be asserted low until all
device supplies are valid (see reset sequence/requirements)
F19
resetn
rstoutn
Device Reset Input
I
K24
E20
Reset out (active low). This pin asserts low in response to any global
reset condition on the device.(2)
O
xi_osc0
System Oscillator OSC0 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
I
I
Y12
xi_osc1
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used
AC11
xo_osc0
xo_osc1
System Oscillator OSC0 Crystal output
O
O
I
AB12
AA11
J25
Auxiliary Oscillator OSC1 Crystal output
xref_clk0
External Reference Clock 0. For Audio and other Peripherals.
External Reference Clock 1. For Audio and other Peripherals.
External Reference Clock 2. For Audio and other Peripherals.
External Reference Clock 3. For Audio and other Peripherals.
xref_clk1
I
J24
xref_clk2
I
H24
H25
P5
xref_clk3
RMII_MHZ_50_CLK(1)
I
RMII Reference Clock (50MHz). This pin is an input when external
reference is used or output when internal reference is used.
IO
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SoC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.3.25.3 System Direct Memory Access (SDMA)
注
For more information, see the DMA Controllers / System DMA section of the Device TRM.
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表 4-28. SDMA Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
G1, L4
H3, H5
H2
dma_evt1
dma_evt2
dma_evt3
dma_evt4
System DMA Event Input 1
I
I
I
I
System DMA Event Input 2
System DMA Event Input 3
System DMA Event Input 4
H6
4.3.25.4 Interrupt Controllers (INTC)
注
For more information, see the Interrupt Controllers section of the Device TRM.
表 4-29. INTC Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
nmin_dsp
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the Arm cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or Arm
processors.
I
L24
sys_nirq2
sys_nirq1
External interrupt event to any device INTC
External interrupt event to any device INTC
I
I
AC10
AB10
4.3.26 Power Supplies
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the Device TRM.
表 4-30. Power Supply Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
PWR
J15, J16, J18, K12,
K18, L12, L17, M11,
M13, M15, M17, N11,
N13, N15, N18, P10,
P12, P14, P16, P18,
R10, R12, R14, R16,
R17, T11, T13, T15,
T17, T9, U11, U13,
U15, U18, U9, V10,
V12, V14, V16, V18,
W10, W12, W14, W16
vdd
Core voltage domain supply
eFuse power supply
vpp(2)
PWR
F20
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BALL
表 4-30. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
GND
A1, A25, AA13, AA15,
AA7, AA8, AA9, AB8,
AC13, AE1, AE15,
AE25, G13, G16, G8,
H10, H12, H14, H16,
H18, H19, H8, J10,
J12, J14, J17, K11,
K13, K15, K17, K9,
L11, L13, L15, L18,
L8, M12, M14, M16,
M18, M20, M8, M9,
N12, N14, N16, N17,
N20, P11, P13, P15,
P17, P19, P9, R11,
R13, R15, R18, R19,
R8, R9, T10, T12,
T14, T16, T18, T8,
U10, U12, U14, U16,
U17, U19, V11, V13,
V15, V17, V19, V8,
V9, W19, W9, Y14,
Y16, Y17, Y7
vss
Ground
cap_vbbldo_gpu (1)
cap_vbbldo_iva (1)
cap_vbbldo_mpu (1)
MM (SGX) Back bias supply
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
T7
G14
F17
IVA Back bias supply
MPU back bias supply
(1)
cap_vbbldo_dsp
External capacitor connection for the DSP vbb ldo output
SRAM array supply for core memories
SRAM array supply for core memories
SRAM array supply for core memories
SRAM array supply for SGX (MM) memories
SRAM array supply for IVA memories
External capacitor connection for the DSP
External capacitor connection for the MPU SRAM array ldo output
HS USB1 3p3 supply
F8
cap_vddram_core1(1)
cap_vddram_core3 (1)
cap_vddram_core4 (1)
U20
K7
G19
V7
(1)
cap_vddram_gpu
(1)
cap_vddram_iva
G12
L7
cap_vddram_dsp (1)
cap_vddram_mpu (1)
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
G18
AA10
Y10
HS USB1 3p3 supply
DPLL_CORE and CORE HSDIVIDER analog power supply
CSI Interface 1.8v Supply
L9
T6
vdda_dsp_iva
vdda_mpu_abe
vdda_per
DSP PLL and IVA PLL analog power supply
MPU_ABE PLL analog power supply
DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply
HS USB2 1.8V analog power supply
MLBP IO power supply
K10, L10
K16, L16
M10
Y8
vdda_usb2
vdds_mlbp
P7, R7
vdd_dsp
DSP voltage domain supply
H11, H13, H9, J11,
J13, J9
vdda_ddr
vdda_debug
vdda_gpu
vdda_hdmi
vdda_osc
vdda_pcie
vdda_usb1
vdda_usb3
vdda_video
vdds18v
DDR PLL and DDR HSDIVIDER analog power supply
Debug PLL inside IOSC PLL supply
GPU (SGX) PLL analog power supply
HDMI PLL and HDMI analog power supply
HFOSC - 1.8v vdds supply
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
R20
N10
N9
W15, Y15
W13, Y13
W11, Y11
W8
PCIe PLL analog power supply
USB2 PLL analog power supply
USB3 PLL analog power supply
Y9
VIDEO1 and VIDEO2 PLL analog power supply
1.8V bump added for atestv esd supply
K14, L14
G11, H20, W7, Y18
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表 4-30. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
PWR
PWR
BALL
AA19, P20, Y19
G10, G9
vdds18v_ddr1
vddshv1
DDR2 - 1.8v bias supply
VIN2 domain - 1.8/3.3 mode voltage Power cell - secondary power
supply
vddshv3
vddshv4
vddshv7
vddshv8
GENERAL Domain - 1.8/3.3 mode voltage Power cell - secondary
power supply
PWR
PWR
PWR
PWR
G15, G17, H15, H17,
J19, K19
MMC4 Domain (UART4) - 1.8/3.3 mode voltage Power cell - secondary
power supply
M19, N19
WIFI Power Group (MMC3/MCASP5) - 1.8/3.3 mode voltage Power cell
- secondary power supply
U7, U8
Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group
pins
N8, P8
vddshv9
vddshv10
vddshv11
vdds_ddr1
RGMII - 1.8/3.3 mode voltage Power cell - secondary power supply
GPMC - 1.8/3.3 mode voltage Power cell - secondary power supply
MMC2 - 1.8/3.3 mode voltage Power cell - secondary power supply
DDR2 - vdds2 can be 1.8 (ddr2)/1.5(ddr3) - secondary power supply
PWR
PWR
PWR
PWR
M7, N7
J7, J8, K8
F7, G7, H7
T19, T20, V20, W17,
W18, W20
vssa_osc0
vssa_osc1
OSC0 Analog ground
OSC1 Analog ground
GND
GND
AA12
AB11
(1) This pin must always be connected via a 1-µF capacitor to vss.
(2) This signal is valid only for High-Security devices. For more details, see 节 5.8, VPP Specification for One-Time Programmable (OTP)
eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.
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4.4 Pin Multiplexing
表 4-31 describes the device pin multiplexing (no characteristics are provided in this table).
注
表 4-31, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in 节
4.3, Signal Descriptions.
注
For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration
section of the Device TRM.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (Hi-Z mode is not an input signal).
注
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
注
In some cases 表 4-31 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function
as selected via CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
CAUTION
The I/O timings provided in Section 5.10, Timing Requirements and Switching Characteristics are valid only if signals
within a single IOSET are used. The IOSETs are defined in the corresponding tables.
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
6* 8*
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
7
9
10
11
12
13
14*
15
P25
ddr1_dqm3
ddr1_d10
ddr1_d27
mlbp_sig_p
ddr1_d17
ddr1_a7
Y23
P21
T3
U25
AA20
V25
AB16
T25
ddr1_dqsn2
ddr1_ba2
ddr1_d25
ddr1_d28
ddr1_d13
N21
AB25
AE9
hdmi1_cloc
kx
W23
AC24
AD16
AA23
AD18
AE19
AC20
U21
ddr1_d16
ddr1_d1
ddr1_casn
ddr1_d0
ddr1_odt0
ddr1_a1
ddr1_a9
ddr1_dqm2
ddr1_d8
AA24
U4
mlbp_sig_n
xi_osc1
AC11
AD1
csi2_0_dx1
usb_txn0
usb1_dp
usb_rxp0
ddr1_ba1
xi_osc0
AE3
pcie_txn1
pcie_rxp1
AC6
AD6
AA16
Y12
AB15
AC18
AE11
ddr1_a14
ddr1_a0
hdmi1_data
0x
R25
Y24
ddr1_dqsn3
ddr1_dqs1
ddr1_a8
Y21
W21
AD20
ddr1_d19
ddr1_a4
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
103
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6* 8*
7
9
10
11
12
13
14*
15
AA25
AD13
ddr1_d14
hdmi1_data
1y
AB9
ljcb_clkn
AC25
U22
ddr1_d12
ddr1_d21
ddr1_d4
AB23
AB24
AE16
T22
ddr1_d2
ddr1_ba0
ddr1_d20
ddr1_d23
ddr1_a3
T21
AB19
AE24
AC15
AC21
AD17
AB12
AD23
AD9
ddr1_d7
ddr1_a13
ddr1_a11
ddr1_rasn
xo_osc0
ddr1_d6
pcie_txp0
ddr1_dqs2
mlbp_clk_n
ddr1_d22
mlbp_dat_n
ddr1_a12
ddr1_d3
V24
U1
U23
T1
AC22
AD24
AC8
ljcb_clkp
AE21
Y20
ddr1_nck
ddr1_vref0
pcie_rxp0
mlbp_dat_p
ddr1_dqm0
ddr1_ck
AD7
T2
AE23
AD21
Y25
ddr1_dqsn1
xo_osc1
AA11
AE17
W22
AE12
ddr1_rst
ddr1_dqm1
hdmi1_data
1x
AE14
hdmi1_data
2x
104
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6* 8*
7
9
10
11
12
13
14*
15
AB2
csi2_0_dy0
ddr1_cke
usb2_dp
csi2_0_dx0
pcie_txn0
ddr1_csn0
ddr1_a10
pcie_rxn0
usb1_dm
porz
AB18
AB6
AC1
AE8
AC19
AA21
AE6
AB7
F19
W25
P24
ddr1_d9
ddr1_d31
ddr1_dqs0
ddr1_d29
ddr1_d18
csi2_0_dy2
ddr1_wen
ddr1_a5
AD22
P22
U24
AD2
AE18
AE20
W24
T24
ddr1_d15
ddr1_d26
ddr1_dqs3
R24
AD15
hdmi1_data
2y
AE22
AA18
U2
ddr1_dqsn0
ddr1_a6
mlbp_clk_p
csi2_0_dy1
AC2
AD12
hdmi1_data
0y
T23
ddr1_d24
AD10
hdmi1_cloc
ky
AE5
usb_rxn0
csi2_0_dx2
ddr1_d30
usb2_dm
ddr1_d5
pcie_rxn1
AE2
P23
AC5
AC23
AD19
AC16
AD25
ddr1_a2
ddr1_a15
ddr1_d11
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
105
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
AD4
CTRL_CORE_PAD F1
usb_txp0
gpmc_ad0
pcie_txp1
0x1400
0x1404
0x1408
0x140C
0x1410
0x1414
0x1418
0x141C
0x1420
0x1424
0x1428
0x142C
0x1430
0x1434
0x1438
0x143C
0x1440
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vout3_d0
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
gpio1_6
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
sysboot10
sysboot11
sysboot12
sysboot13
sysboot14
sysboot15
Driver off
_GPMC_AD0
CTRL_CORE_PAD E2
_GPMC_AD1
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
gpio1_7
CTRL_CORE_PAD E1
_GPMC_AD2
gpio1_8
CTRL_CORE_PAD C1
_GPMC_AD3
gpio1_9
CTRL_CORE_PAD D1
_GPMC_AD4
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio7_18
gpio7_19
gpio7_28
gpio7_29
gpio1_18
gpio1_19
gpio1_20
gpio1_21
CTRL_CORE_PAD D2
_GPMC_AD5
CTRL_CORE_PAD B1
_GPMC_AD6
CTRL_CORE_PAD B2
_GPMC_AD7
CTRL_CORE_PAD C2
_GPMC_AD8
CTRL_CORE_PAD D3
_GPMC_AD9
CTRL_CORE_PAD A2
_GPMC_AD10
vin1a_d10 vout3_d10
vin1a_d11 vout3_d11
vin1a_d12 vout3_d12
vin1a_d13 vout3_d13
vin1a_d14 vout3_d14
vin1a_d15 vout3_d15
vin1a_d16 vout3_d16
CTRL_CORE_PAD B3
_GPMC_AD11
CTRL_CORE_PAD C3
_GPMC_AD12
CTRL_CORE_PAD C4
_GPMC_AD13
CTRL_CORE_PAD A3
_GPMC_AD14
CTRL_CORE_PAD B4
_GPMC_AD15
CTRL_CORE_PAD M1
_GPMC_A0
vin1b_d0
i2c4_scl
uart5_rxd
gpio7_3
gpmc_a26
gpmc_a16
0x1444
0x1448
0x144C
0x1450
0x1454
0x1458
CTRL_CORE_PAD M2
_GPMC_A1
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
vin1a_d17 vout3_d17
vin1a_d18 vout3_d18
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
i2c4_sda
uart7_rxd
uart7_txd
i2c5_scl
uart5_txd
uart5_ctsn
uart5_rtsn
uart6_rxd
uart6_txd
uart6_ctsn
gpio7_4
gpio7_5
gpio7_6
gpio1_26
gpio1_27
gpio1_28
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD L2
_GPMC_A2
CTRL_CORE_PAD L1
_GPMC_A3
qspi1_cs2 vin1a_d19 vout3_d19
qspi1_cs3 vin1a_d20 vout3_d20
vin1a_d21 vout3_d21
CTRL_CORE_PAD K3
_GPMC_A4
CTRL_CORE_PAD K2
_GPMC_A5
i2c5_sda
uart8_rxd
CTRL_CORE_PAD J1
_GPMC_A6
vin1a_d22 vout3_d22
106
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x145C
0x1460
0x1464
0x1468
0x146C
0x1470
0x1474
0x1478
0x147C
0x1480
0x1484
0x1488
0x148C
0x1490
0x1494
0x1498
0x149C
0x14A0
0x14A4
0x14A8
0x14AC
0x14B0
0x14B4
CTRL_CORE_PAD K1
_GPMC_A7
gpmc_a7
vin1a_d23 vout3_d23
vin1b_d7
uart8_txd
uart6_rtsn
gpio1_29
Driver off
CTRL_CORE_PAD K4
_GPMC_A8
gpmc_a8
gpmc_a9
gpmc_a10
gpmc_a11
gpmc_a12
vin1a_hsyn vout3_hsyn
vin1b_hsyn timer12
c1
spi4_sclk
spi4_d1
spi4_d0
spi4_cs0
spi4_cs1
spi4_cs2
spi4_cs3
gpio1_30
gpio1_31
gpio2_0
gpio2_1
gpio2_2
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
c0
c
CTRL_CORE_PAD H1
_GPMC_A9
vin1a_vsyn vout3_vsyn
vin1b_vsyn timer11
c1
c0
c
CTRL_CORE_PAD J2
_GPMC_A10
vin1a_de0 vout3_de
vin1b_clk1 timer10
vin1b_de1 timer9
vin1b_fld1 timer8
timer7
CTRL_CORE_PAD L3
_GPMC_A11
vin1a_fld0 vout3_fld
CTRL_CORE_PAD G1
_GPMC_A12
gpmc_a0
dma_evt1
dma_evt2
CTRL_CORE_PAD H3
_GPMC_A13
gpmc_a13 qspi1_rtclk
gpmc_a14 qspi1_d3
gpmc_a15 qspi1_d2
gpmc_a16 qspi1_d0
gpmc_a17 qspi1_d1
gpmc_a18 qspi1_sclk
CTRL_CORE_PAD H4
_GPMC_A14
timer6
CTRL_CORE_PAD K6
_GPMC_A15
timer5
CTRL_CORE_PAD K5
_GPMC_A16
CTRL_CORE_PAD G2
_GPMC_A17
CTRL_CORE_PAD F2
_GPMC_A18
CTRL_CORE_PAD A4
_GPMC_A19
gpmc_a19 mmc2_dat4 gpmc_a13
gpmc_a20 mmc2_dat5 gpmc_a14
gpmc_a21 mmc2_dat6 gpmc_a15
gpmc_a22 mmc2_dat7 gpmc_a16
gpmc_a23 mmc2_clk gpmc_a17
gpmc_a24 mmc2_dat0 gpmc_a18
gpmc_a25 mmc2_dat1 gpmc_a19
gpmc_a26 mmc2_dat2 gpmc_a20
gpmc_a27 mmc2_dat3 gpmc_a21
gpmc_cs1 mmc2_cmd gpmc_a22
gpmc_cs0
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
vin2b_d7
CTRL_CORE_PAD E7
_GPMC_A20
CTRL_CORE_PAD D6
_GPMC_A21
CTRL_CORE_PAD C5
_GPMC_A22
CTRL_CORE_PAD B5
_GPMC_A23
CTRL_CORE_PAD D7
_GPMC_A24
CTRL_CORE_PAD C6
_GPMC_A25
CTRL_CORE_PAD A5
_GPMC_A26
CTRL_CORE_PAD B6
_GPMC_A27
vin2b_hsyn
c1
CTRL_CORE_PAD A6
_GPMC_CS1
vin2b_vsyn
c1
CTRL_CORE_PAD F3
_GPMC_CS0
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
107
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x14B8
CTRL_CORE_PAD G4
_GPMC_CS2
gpmc_cs2 qspi1_cs0
gpio2_20
gpmc_a23
gpmc_a13
Driver off
0x14BC
CTRL_CORE_PAD G3
_GPMC_CS3
gpmc_cs3 qspi1_cs1 vin1a_clk0 vout3_clk
gpmc_a1
gpio2_21
gpmc_a24
gpmc_a14
Driver off
0x14C0
0x14C4
CTRL_CORE_PAD L4
_GPMC_CLK
gpmc_clk
gpmc_cs7 clkout1
gpmc_wait1
gpmc_wait1
vin2b_clk1 timer4
gpmc_a23 timer3
i2c3_scl
dma_evt1
dma_evt2
gpio2_22
gpmc_a20
Driver off
Driver off
CTRL_CORE_PAD H5
_GPMC_ADVN_AL
E
gpmc_advn gpmc_cs6 clkout2
_ale
gpmc_a2
i2c3_sda
gpio2_23
gpmc_a19
0x14C8
CTRL_CORE_PAD G5
_GPMC_OEN_RE
N
gpmc_oen_
ren
gpio2_24
gpio2_25
Driver off
0x14CC
0x14D0
0x14D4
0x14D8
CTRL_CORE_PAD G6
_GPMC_WEN
gpmc_wen
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD H2
_GPMC_BEN0
gpmc_ben0 gpmc_cs4
gpmc_ben1 gpmc_cs5
gpmc_wait0
vin2b_de1 timer2
vin2b_fld1 timer1
dma_evt3
dma_evt4
gpio2_26
gpmc_a21
CTRL_CORE_PAD H6
_GPMC_BEN1
vin2b_clk1 gpmc_a3
gpio2_27
gpmc_a22
CTRL_CORE_PAD F6
_GPMC_WAIT0
gpio2_28
gpmc_a25
gpmc_a15
0x1554
CTRL_CORE_PAD D8
_VIN2A_CLK0
vin2a_clk0
vout2_fld
emu5
kbd_row0 eQEP1A_in
kbd_row1 eQEP1B_in
pr1_edio_d pr1_edio_d gpio3_28
Driver off
ata_in0
ata_out0
gpmc_a27
gpmc_a17
0x1558
0x155C
CTRL_CORE_PAD B7
_VIN2A_DE0
vin2a_de0 vin2a_fld0 vin2b_fld1 vin2b_de1 vout2_de
emu6
emu7
pr1_edio_d pr1_edio_d gpio3_29
ata_in1 ata_out1
Driver off
Driver off
CTRL_CORE_PAD C7
_VIN2A_FLD0
vin2a_fld0
vin2b_clk1
vout2_clk
eQEP1_ind
ex
pr1_edio_d pr1_edio_d gpio3_30
ata_in2
ata_out2
gpmc_a27
gpmc_a18
0x1560
0x1564
0x1568
0x156C
CTRL_CORE_PAD E8
_VIN2A_HSYNC0
vin2a_hsyn
c0
vin2b_hsyn vout2_hsyn emu8
c1
uart9_rxd
uart9_txd
spi4_sclk
spi4_d1
kbd_row2 eQEP1_str pr1_uart0_c pr1_edio_d pr1_edio_d gpio3_31
obe ts_n ata_in3 ata_out3 gpmc_a27
Driver off
Driver off
Driver off
Driver off
c
CTRL_CORE_PAD B8
_VIN2A_VSYNC0
vin2a_vsyn
c0
vin2b_vsyn vout2_vsyn emu9
kbd_row3 ehrpwm1A pr1_uart0_r pr1_edio_d pr1_edio_d gpio4_0
ts_n ata_in4 ata_out4
c1
c
CTRL_CORE_PAD C8
_VIN2A_D0
vin2a_d0
vout2_d23 emu10
uart9_ctsn spi4_d0
uart9_rtsn spi4_cs0
kbd_row4 ehrpwm1B pr1_uart0_r pr1_edio_d pr1_edio_d gpio4_1
xd ata_in5 ata_out5
CTRL_CORE_PAD B9
_VIN2A_D1
vin2a_d1
vout2_d22 emu11
vout2_d21 emu12
kbd_row5 ehrpwm1_tr pr1_uart0_t pr1_edio_d pr1_edio_d gpio4_2
ipzone_inpu xd
t
ata_in6
ata_out6
0x1570
CTRL_CORE_PAD A7
_VIN2A_D2
vin2a_d2
uart10_rxd kbd_row6 eCAP1_in_ pr1_ecap0_ pr1_edio_d pr1_edio_d gpio4_3
Driver off
PWM1_out ecap_capin ata_in7
_apwm_o
ata_out7
0x1574
0x1578
0x157C
CTRL_CORE_PAD A9
_VIN2A_D3
vin2a_d3
vin2a_d4
vin2a_d5
vout2_d20 emu13
vout2_d19 emu14
vout2_d18 emu15
uart10_txd kbd_col0
uart10_ctsn kbd_col1
uart10_rtsn kbd_col2
ehrpwm1_s pr1_edc_lat pr1_pru1_g pr1_pru1_g gpio4_4
ynci ch0_in pi0 po0
Driver off
Driver off
Driver off
CTRL_CORE_PAD A8
_VIN2A_D4
ehrpwm1_s pr1_edc_sy pr1_pru1_g pr1_pru1_g gpio4_5
ynco nc0_out pi1 po1
CTRL_CORE_PAD A11
_VIN2A_D5
eQEP2A_in pr1_edio_s pr1_pru1_g pr1_pru1_g gpio4_6
of pi2 po2
108
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6* 8*
7
9
10
11
12
13
14*
15
0x1580
0x1584
0x1588
0x158C
0x1590
0x1594
CTRL_CORE_PAD F10
_VIN2A_D6
vin2a_d6
vout2_d17 emu16
vout2_d16 emu17
vout2_d15 emu18
vout2_d14 emu19
mii1_rxd1 kbd_col3
mii1_rxd2 kbd_col4
mii1_rxd3 kbd_col5
mii1_rxd0 kbd_col6
kbd_col7
eQEP2B_in pr1_mii_mt pr1_pru1_g pr1_pru1_g gpio4_7
Driver off
1_clk pi3 po3
CTRL_CORE_PAD A10
_VIN2A_D7
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
eQEP2_ind pr1_mii1_tx pr1_pru1_g pr1_pru1_g gpio4_8
ex en pi4 po4
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD B10
_VIN2A_D8
eQEP2_str pr1_mii1_tx pr1_pru1_g pr1_pru1_g gpio4_9
obe d3 pi5 po5 gpmc_a26
CTRL_CORE_PAD E10
_VIN2A_D9
ehrpwm2A pr1_mii1_tx pr1_pru1_g pr1_pru1_g gpio4_10
d2 pi6 po6 gpmc_a25
CTRL_CORE_PAD D10
_VIN2A_D10
mdio_mclk vout2_d13
mdio_d vout2_d12
ehrpwm2B pr1_mdio_ pr1_pru1_g pr1_pru1_g gpio4_11
mdclk pi7 po7 gpmc_a24
CTRL_CORE_PAD C10
_VIN2A_D11
kbd_row7 ehrpwm2_tr pr1_mdio_d pr1_pru1_g pr1_pru1_g gpio4_12
ipzone_inpu ata
t
pi8
po8
gpmc_a23
0x1598
0x159C
0x15A0
0x15A4
0x15A8
0x15AC
0x15B0
0x15B4
CTRL_CORE_PAD B11
_VIN2A_D12
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
rgmii1_txc vout2_d11
rgmii1_txctl vout2_d10
rgmii1_txd3 vout2_d9
rgmii1_txd2 vout2_d8
rgmii1_txd1 vout2_d7
rgmii1_txd0 vout2_d6
rgmii1_rxc vout2_d5
rgmii1_rxctl vout2_d4
mii1_rxclk kbd_col8
eCAP2_in_ pr1_mii1_tx pr1_pru1_g pr1_pru1_g gpio4_13
PWM2_out d1 pi9 po9
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD D11
_VIN2A_D13
mii1_rxdv
mii1_txclk
mii1_txd0
mii1_txd1
mii1_txd2
mii1_txd3
mii1_txer
kbd_row8 eQEP3A_in pr1_mii1_tx pr1_pru1_g pr1_pru1_g gpio4_14
d0 pi10 po10
CTRL_CORE_PAD C11
_VIN2A_D14
eQEP3B_in pr1_mii_mr pr1_pru1_g pr1_pru1_g gpio4_15
1_clk pi11 po11
CTRL_CORE_PAD B12
_VIN2A_D15
eQEP3_ind pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_16
ex dv pi12 po12
CTRL_CORE_PAD A12
_VIN2A_D16
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
eQEP3_str pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_24
obe d3 pi13 po13
CTRL_CORE_PAD A13
_VIN2A_D17
ehrpwm3A pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_25
d2 pi14 po14
CTRL_CORE_PAD E11
_VIN2A_D18
ehrpwm3B pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_26
d1 pi15 po15
CTRL_CORE_PAD F11
_VIN2A_D19
ehrpwm3_tr pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_27
ipzone_inpu d0
t
pi16
po16
0x15B8
0x15BC
0x15C0
0x15C4
0x15E4
0x1604
0x1624
0x163C
0x1640
CTRL_CORE_PAD B13
_VIN2A_D20
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
emu2
rgmii1_rxd3 vout2_d3
rgmii1_rxd2 vout2_d2
rgmii1_rxd1 vout2_d1
rgmii1_rxd0 vout2_d0
mii1_rxer
mii1_col
mii1_crs
mii1_txen
eCAP3_in_ pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_28
PWM3_out er pi17 po17
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD E13
_VIN2A_D21
pr1_mii1_rx pr1_pru1_g pr1_pru1_g gpio4_29
link pi18 po18
CTRL_CORE_PAD C13
_VIN2A_D22
pr1_mii1_c pr1_pru1_g pr1_pru1_g gpio4_30
ol pi19 po19
CTRL_CORE_PAD D13
_VIN2A_D23
pr1_mii1_cr pr1_pru1_g pr1_pru1_g gpio4_31
pi20 po20
s
CTRL_CORE_PAD E14
_VOUT1_D2
CTRL_CORE_PAD F14
_VOUT1_D10
emu3
CTRL_CORE_PAD F13
_VOUT1_D18
emu4
CTRL_CORE_PAD L5
_MDIO_MCLK
mdio_mclk uart3_rtsn
mdio_d uart3_ctsn
mii0_col
vin2a_clk0 vin1b_clk1
vin2a_d0 vin1b_d0
pr1_mii0_c pr2_pru1_g pr2_pru1_g gpio5_15
ol pi0 po0
Driver off
Driver off
CTRL_CORE_PAD L6
_MDIO_D
mii0_txer
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_16
link pi1 po1
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
109
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x1644
CTRL_CORE_PAD P5
_RMII_MHZ_50_CL
K
RMII_MHZ_
50_CLK
vin2a_d11
pr2_pru1_g pr2_pru1_g gpio5_17
pi2 po2
Driver off
0x1648
0x164C
0x1650
0x1654
0x1658
0x165C
0x1660
0x1664
0x1668
0x166C
0x1670
0x1674
0x1678
0x167C
0x1680
0x1684
0x1688
0x168C
0x1690
0x1694
0x1698
0x169C
CTRL_CORE_PAD N5
_UART3_RXD
uart3_rxd
uart3_txd
rmii1_crs
mii0_rxdv
vin2a_d1
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
spi3_sclk
spi3_d1
spi3_d0
spi3_cs0
spi4_sclk
spi4_d1
spi4_d0
spi4_cs0
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_18
dv pi3 po3
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD N6
_UART3_TXD
rmii1_rxer mii0_rxclk vin2a_d2
spi4_cs1
spi4_cs2
spi4_cs3
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
pr1_mii_mr pr2_pru1_g pr2_pru1_g gpio5_19
0_clk pi4 po4
CTRL_CORE_PAD T4
_RGMII0_TXC
rgmii0_txc uart3_ctsn rmii1_rxd1 mii0_rxd3 vin2a_d3
rgmii0_txctl uart3_rtsn rmii1_rxd0 mii0_rxd2 vin2a_d4
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_20
d3 pi5 po5
CTRL_CORE_PAD T5
_RGMII0_TXCTL
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_21
d2 pi6 po6
CTRL_CORE_PAD P4
_RGMII0_TXD3
rgmii0_txd3 rmii0_crs
rgmii0_txd2 rmii0_rxer
rgmii0_txd1 rmii0_rxd1
rgmii0_txd0 rmii0_rxd0
rgmii0_rxc
mii0_crs
vin2a_de0 vin1b_de1
vin2a_hsyn vin1b_hsyn
pr1_mii0_cr pr2_pru1_g pr2_pru1_g gpio5_22
pi7 po7
s
CTRL_CORE_PAD P3
_RGMII0_TXD2
mii0_rxer
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_23
er pi8 po8
c0
c1
CTRL_CORE_PAD R2
_RGMII0_TXD1
mii0_rxd1 vin2a_vsyn vin1b_vsyn
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_24
d1 pi9 po9
c0
c1
CTRL_CORE_PAD R1
_RGMII0_TXD0
mii0_rxd0 vin2a_d10
pr1_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_25
d0 pi10 po10
CTRL_CORE_PAD N2
_RGMII0_RXC
rmii1_txen mii0_txclk vin2a_d5
vin1b_d5
vin1b_d6
vin1b_d7
pr1_mii_mt pr2_pru1_g pr2_pru1_g gpio5_26
0_clk pi11 po11
CTRL_CORE_PAD P2
_RGMII0_RXCTL
rgmii0_rxctl
rmii1_txd1 mii0_txd3
rmii1_txd0 mii0_txd2
mii0_txen
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
pr1_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_27
d3 pi12 po12
CTRL_CORE_PAD N1
_RGMII0_RXD3
rgmii0_rxd3
pr1_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_28
d2 pi13 po13
CTRL_CORE_PAD P1
_RGMII0_RXD2
rgmii0_rxd2 rmii0_txen
rgmii0_rxd1 rmii0_txd1
rgmii0_rxd0 rmii0_txd0
pr1_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_29
en pi14 po14
CTRL_CORE_PAD N3
_RGMII0_RXD1
mii0_txd1
pr1_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_30
d1 pi15 po15
CTRL_CORE_PAD N4
_RGMII0_RXD0
mii0_txd0
vin2a_fld0 vin1b_fld1
pr1_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_31
d0 pi16 po16
CTRL_CORE_PAD AD3
_USB1_DRVVBUS
usb1_drvvb
us
timer16
timer15
gpio6_12
gpio6_13
gpio6_14
gpio6_15
gpio6_16
CTRL_CORE_PAD AA6
_USB2_DRVVBUS
usb2_drvvb
us
CTRL_CORE_PAD H21
_GPIO6_14
gpio6_14
gpio6_15
gpio6_16
xref_clk0
xref_clk1
xref_clk2
mcasp1_ax dcan2_tx
r8
uart10_rxd
i2c3_sda
i2c3_scl
clkout1
timer1
CTRL_CORE_PAD K22
_GPIO6_15
mcasp1_ax dcan2_rx
r9
uart10_txd
timer2
CTRL_CORE_PAD K23
_GPIO6_16
mcasp1_ax
r10
timer3
CTRL_CORE_PAD J25
_XREF_CLK0
mcasp2_ax mcasp1_ax mcasp1_ah mcasp5_ah
r8 r4 clkx clkx
vin1a_d0
hdq0
clkout2
timer13
timer14
timer15
pr2_mii1_c pr2_pru1_g pr2_pru1_g gpio6_17
ol pi5 po5
CTRL_CORE_PAD J24
_XREF_CLK1
mcasp2_ax mcasp1_ax mcasp2_ah mcasp6_ah
r9 r5 clkx clkx
vin1a_clk0
pr2_mii1_cr pr2_pru1_g pr2_pru1_g gpio6_18
pi6 po6
s
CTRL_CORE_PAD H24
_XREF_CLK2
mcasp2_ax mcasp1_ax mcasp3_ah mcasp7_ah
r10 r6 clkx clkx
gpio6_19
110
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x16A0
0x16A4
0x16A8
0x16AC
0x16B0
0x16B4
0x16B8
0x16BC
0x16C0
0x16C4
0x16C8
0x16CC
0x16D0
0x16D4
0x16D8
0x16DC
0x16E0
0x16E4
0x16E8
0x16EC
0x16F0
0x16F4
0x16F8
0x1704
CTRL_CORE_PAD H25
_XREF_CLK3
xref_clk3
mcasp2_ax mcasp1_ax mcasp4_ah mcasp8_ah
hdq0
clkout3
timer16
gpio6_20
Driver off
r11
r7
clkx
clkx
CTRL_CORE_PAD C16
_MCASP1_ACLKX
mcasp1_acl
kx
vin1a_fld0
vin1a_de0
i2c3_sda
i2c3_scl
i2c4_sda
i2c4_scl
i2c5_sda
i2c5_scl
pr2_mdio_ pr2_pru1_g pr2_pru1_g gpio7_31
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
mdclk
pi7
po7
CTRL_CORE_PAD C17
_MCASP1_FSX
mcasp1_fsx
pr2_mdio_d
ata
gpio7_30
gpio5_0
gpio5_1
CTRL_CORE_PAD D16
_MCASP1_ACLKR
mcasp1_acl mcasp7_ax
kr r2
CTRL_CORE_PAD D17
_MCASP1_FSR
mcasp1_fsr mcasp7_ax
r3
CTRL_CORE_PAD D14
_MCASP1_AXR0
mcasp1_ax
r0
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
vin1a_vsyn
c0
pr2_mii0_rx pr2_pru1_g pr2_pru1_g gpio5_2
er pi8 po8
CTRL_CORE_PAD B14
_MCASP1_AXR1
mcasp1_ax
r1
vin1a_hsyn
c0
pr2_mii_mt pr2_pru1_g pr2_pru1_g gpio5_3
0_clk pi9 po9
CTRL_CORE_PAD C14
_MCASP1_AXR2
mcasp1_ax mcasp6_ax
r2
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
r2
CTRL_CORE_PAD B15
_MCASP1_AXR3
mcasp1_ax mcasp6_ax
r3 r3
CTRL_CORE_PAD A15
_MCASP1_AXR4
mcasp1_ax mcasp4_ax
r4 r2
CTRL_CORE_PAD A14
_MCASP1_AXR5
mcasp1_ax mcasp4_ax
r5 r3
CTRL_CORE_PAD A17
_MCASP1_AXR6
mcasp1_ax mcasp5_ax
r6 r2
CTRL_CORE_PAD A16
_MCASP1_AXR7
mcasp1_ax mcasp5_ax
r7 r3
timer4
timer5
timer6
timer7
timer8
timer9
timer10
timer11
timer12
CTRL_CORE_PAD A18
_MCASP1_AXR8
mcasp1_ax mcasp6_ax
r8 r0
spi3_sclk
spi3_d1
vin1a_d15
vin1a_d14
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d7
vin1a_d6
pr2_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_10
en pi10 po10
CTRL_CORE_PAD B17
_MCASP1_AXR9
mcasp1_ax mcasp6_ax
r9 r1
pr2_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_11
d3 pi11 po11
CTRL_CORE_PAD B16
_MCASP1_AXR10
mcasp1_ax mcasp6_acl mcasp6_acl spi3_d0
r10 kx kr
pr2_mii0_tx pr2_pru1_g pr2_pru1_g gpio5_12
d2 pi12 po12
CTRL_CORE_PAD B18
_MCASP1_AXR11
mcasp1_ax mcasp6_fsx mcasp6_fsr spi3_cs0
r11
pr2_mii0_tx pr2_pru1_g pr2_pru1_g gpio4_17
d1 pi13 po13
CTRL_CORE_PAD A19
_MCASP1_AXR12
mcasp1_ax mcasp7_ax
r12 r0
spi3_cs1
pr2_mii0_tx pr2_pru1_g pr2_pru1_g gpio4_18
d0 pi14 po14
CTRL_CORE_PAD E17
_MCASP1_AXR13
mcasp1_ax mcasp7_ax
r13 r1
pr2_mii_mr pr2_pru1_g pr2_pru1_g gpio6_4
0_clk pi15 po15
CTRL_CORE_PAD E16
_MCASP1_AXR14
mcasp1_ax mcasp7_acl mcasp7_acl
r14 kx kr
pr2_mii0_rx pr2_pru1_g pr2_pru1_g gpio6_5
dv pi16 po16
CTRL_CORE_PAD F16
_MCASP1_AXR15
mcasp1_ax mcasp7_fsx mcasp7_fsr
r15
pr2_mii0_rx pr2_pru0_g pr2_pru0_g gpio6_6
d3 pi20 po20
CTRL_CORE_PAD E19
_MCASP2_ACLKX
mcasp2_acl
kx
pr2_mii0_rx pr2_pru0_g pr2_pru0_g
d2 pi18 po18
CTRL_CORE_PAD D19
_MCASP2_FSX
mcasp2_fsx
pr2_mii0_rx pr2_pru0_g pr2_pru0_g
d1 pi19 po19
CTRL_CORE_PAD A20
_MCASP2_AXR0
mcasp2_ax
r0
版权 © 2016–2019, Texas Instruments Incorporated
Terminal Configuration and Functions
111
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x1708
0x170C
0x1710
0x1714
0x1718
0x171C
0x1720
0x1724
0x1728
0x172C
0x1730
0x1734
0x1738
0x173C
0x1740
0x1744
0x1748
0x174C
0x1750
0x1754
0x1758
0x175C
0x1760
0x1764
CTRL_CORE_PAD B19
_MCASP2_AXR1
mcasp2_ax
r1
Driver off
CTRL_CORE_PAD A21
_MCASP2_AXR2
mcasp2_ax mcasp3_ax
r2 r2
vin1a_d5
vin1a_d4
pr2_mii0_rx pr2_pru0_g pr2_pru0_g gpio6_8
d0 pi16 po16
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD B21
_MCASP2_AXR3
mcasp2_ax mcasp3_ax
r3 r3
pr2_mii0_rx pr2_pru0_g pr2_pru0_g gpio6_9
link pi17 po17
CTRL_CORE_PAD B20
_MCASP2_AXR4
mcasp2_ax mcasp8_ax
r4 r0
gpio1_4
gpio6_7
gpio2_29
gpio1_5
CTRL_CORE_PAD C19
_MCASP2_AXR5
mcasp2_ax mcasp8_ax
r5 r1
CTRL_CORE_PAD D20
_MCASP2_AXR6
mcasp2_ax mcasp8_acl mcasp8_acl
r6 kx kr
CTRL_CORE_PAD C20
_MCASP2_AXR7
mcasp2_ax mcasp8_fsx mcasp8_fsr
r7
CTRL_CORE_PAD A22
_MCASP3_ACLKX
mcasp3_acl mcasp3_acl mcasp2_ax uart7_rxd
kx kr r12
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
pr2_mii0_cr pr2_pru0_g pr2_pru0_g gpio5_13
pi12 po12
s
CTRL_CORE_PAD A23
_MCASP3_FSX
mcasp3_fsx mcasp3_fsr mcasp2_ax uart7_txd
r13
pr2_mii0_c pr2_pru0_g pr2_pru0_g gpio5_14
ol pi13 po13
CTRL_CORE_PAD B22
_MCASP3_AXR0
mcasp3_ax
r0
mcasp2_ax uart7_ctsn uart5_rxd
r14
pr2_mii1_rx pr2_pru0_g pr2_pru0_g
er pi14 po14
CTRL_CORE_PAD B23
_MCASP3_AXR1
mcasp3_ax
r1
mcasp2_ax uart7_rtsn uart5_txd
r15
pr2_mii1_rx pr2_pru0_g pr2_pru0_g
link pi15 po15
CTRL_CORE_PAD C23
_MCASP4_ACLKX
mcasp4_acl mcasp4_acl spi3_sclk
kx kr
uart8_rxd
i2c4_sda
CTRL_CORE_PAD B25
_MCASP4_FSX
mcasp4_fsx mcasp4_fsr spi3_d1
uart8_txd
i2c4_scl
CTRL_CORE_PAD A24
_MCASP4_AXR0
mcasp4_ax
r0
spi3_d0
uart8_ctsn uart4_rxd
uart8_rtsn uart4_txd
CTRL_CORE_PAD D23
_MCASP4_AXR1
mcasp4_ax
r1
spi3_cs0
pr2_pru1_g pr2_pru1_g
pi0 po0
CTRL_CORE_PAD AC3
_MCASP5_ACLKX
mcasp5_acl mcasp5_acl spi4_sclk
kx kr
uart9_rxd
uart9_txd
i2c5_sda
i2c5_scl
pr2_pru1_g pr2_pru1_g
pi1 po1
CTRL_CORE_PAD U6
_MCASP5_FSX
mcasp5_fsx mcasp5_fsr spi4_d1
pr2_pru1_g pr2_pru1_g
pi2 po2
CTRL_CORE_PAD AA5
_MCASP5_AXR0
mcasp5_ax
r0
spi4_d0
uart9_ctsn uart3_rxd
uart9_rtsn uart3_txd
pr2_mdio_ pr2_pru1_g pr2_pru1_g
mdclk pi3 po3
CTRL_CORE_PAD AC4
_MCASP5_AXR1
mcasp5_ax
r1
spi4_cs0
pr2_mdio_d pr2_pru1_g pr2_pru1_g
ata pi4 po4
CTRL_CORE_PAD U3
_MMC1_CLK
mmc1_clk
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
CTRL_CORE_PAD V4
_MMC1_CMD
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
CTRL_CORE_PAD V3
_MMC1_DAT0
CTRL_CORE_PAD V2
_MMC1_DAT1
CTRL_CORE_PAD W1
_MMC1_DAT2
112
Terminal Configuration and Functions
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6* 8*
7
9
10
11
12
13
14*
15
0x1768
0x176C
0x1770
0x1774
0x1778
0x177C
CTRL_CORE_PAD V1
_MMC1_DAT3
mmc1_dat3
gpio6_26
Driver off
CTRL_CORE_PAD U5
_MMC1_SDCD
mmc1_sdcd
uart6_rxd
uart6_txd
i2c4_sda
i2c4_scl
gpio6_27
gpio6_28
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD V5
_MMC1_SDWP
mmc1_sdw
p
CTRL_CORE_PAD Y5
_GPIO6_10
gpio6_10
gpio6_11
mmc3_clk
mdio_mclk i2c3_sda
vin2b_hsyn
c1
vin1a_clk0 ehrpwm2A pr2_mii_mt pr2_pru0_g pr2_pru0_g gpio6_10
1_clk pi0 po0
CTRL_CORE_PAD Y6
_GPIO6_11
mdio_d
i2c3_scl
vin2b_vsyn
c1
vin1a_de0 ehrpwm2B pr2_mii1_tx pr2_pru0_g pr2_pru0_g gpio6_11
en pi1 po1
CTRL_CORE_PAD Y2
_MMC3_CLK
vin2b_d7
vin1a_d7
ehrpwm2_tr pr2_mii1_tx pr2_pru0_g pr2_pru0_g gpio6_29
ipzone_inpu d3
t
pi2
po2
0x1780
0x1784
0x1788
0x178C
0x1790
0x1794
0x1798
0x179C
CTRL_CORE_PAD Y1
_MMC3_CMD
mmc3_cmd spi3_sclk
mmc3_dat0 spi3_d1
mmc3_dat1 spi3_d0
mmc3_dat2 spi3_cs0
mmc3_dat3 spi3_cs1
mmc3_dat4 spi4_sclk
mmc3_dat5 spi4_d1
mmc3_dat6 spi4_d0
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
vin2b_de1
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
eCAP2_in_ pr2_mii1_tx pr2_pru0_g pr2_pru0_g gpio6_30
PWM2_out d2 pi3 po3
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD Y4
_MMC3_DAT0
uart5_rxd
uart5_txd
eQEP3A_in pr2_mii1_tx pr2_pru0_g pr2_pru0_g gpio6_31
d1 pi4 po4
CTRL_CORE_PAD AA2
_MMC3_DAT1
eQEP3B_in pr2_mii1_tx pr2_pru0_g pr2_pru0_g gpio7_0
d0 pi5 po5
CTRL_CORE_PAD AA3
_MMC3_DAT2
uart5_ctsn
uart5_rtsn
uart10_rxd
uart10_txd
uart10_ctsn
eQEP3_ind pr2_mii_mr pr2_pru0_g pr2_pru0_g gpio7_1
ex 1_clk pi6 po6
CTRL_CORE_PAD W2
_MMC3_DAT3
eQEP3_str pr2_mii1_rx pr2_pru0_g pr2_pru0_g gpio7_2
obe dv pi7 po7
CTRL_CORE_PAD Y3
_MMC3_DAT4
ehrpwm3A pr2_mii1_rx pr2_pru0_g pr2_pru0_g gpio1_22
d3 pi8 po8
CTRL_CORE_PAD AA1
_MMC3_DAT5
ehrpwm3B pr2_mii1_rx pr2_pru0_g pr2_pru0_g gpio1_23
d2 pi9 po9
CTRL_CORE_PAD AA4
_MMC3_DAT6
vin1a_hsyn ehrpwm3_tr pr2_mii1_rx pr2_pru0_g pr2_pru0_g gpio1_24
c0
ipzone_inpu d1
t
pi10
po10
0x17A0
0x17A4
0x17A8
0x17AC
0x17B0
0x17B4
0x17B8
0x17BC
0x17C0
CTRL_CORE_PAD AB1
_MMC3_DAT7
mmc3_dat7 spi4_cs0
spi1_sclk
uart10_rtsn
vin2b_clk1
vin1a_vsyn eCAP3_in_ pr2_mii1_rx pr2_pru0_g pr2_pru0_g gpio1_25
c0 PWM3_out d0 pi11 po11
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD C24
_SPI1_SCLK
gpio7_7
gpio7_8
gpio7_9
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
CTRL_CORE_PAD D24
_SPI1_D1
spi1_d1
CTRL_CORE_PAD D25
_SPI1_D0
spi1_d0
CTRL_CORE_PAD B24
_SPI1_CS0
spi1_cs0
CTRL_CORE_PAD C25
_SPI1_CS1
spi1_cs1
spi2_cs1
CTRL_CORE_PAD E24
_SPI1_CS2
spi1_cs2
spi1_cs3
spi2_sclk
uart4_rxd
uart4_txd
uart3_rxd
mmc3_sdcd spi2_cs2
dcan2_tx
dcan2_rx
mdio_mclk hdmi1_hpd
mdio_d hdmi1_cec
CTRL_CORE_PAD E25
_SPI1_CS3
mmc3_sdw spi2_cs3
p
CTRL_CORE_PAD G25
_SPI2_SCLK
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表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
ADDRESS REGISTER NAME
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
9
10
11
12
13
14*
15
0x17C4
0x17C8
0x17CC
0x17D0
0x17D4
0x17E0
0x17E4
0x17E8
0x17EC
0x17F0
0x17F4
0x17F8
0x17FC
0x1800
0x1804
0x1808
0x180C
0x1818
0x1824
0x1830
0x1834
0x1838
0x183C
0x1840
CTRL_CORE_PAD F25
_SPI2_D1
spi2_d1
uart3_txd
gpio7_15
gpio7_16
gpio7_17
gpio1_14
gpio1_15
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
gpio1_16
gpio1_17
Driver off
CTRL_CORE_PAD G24
_SPI2_D0
spi2_d0
uart3_ctsn uart5_rxd
uart3_rtsn uart5_txd
uart8_rxd
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD F24
_SPI2_CS0
spi2_cs0
dcan1_tx
dcan1_rx
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
uart2_rxd
uart2_txd
uart2_ctsn
CTRL_CORE_PAD H22
_DCAN1_TX
mmc2_sdcd
hdmi1_hpd
hdmi1_cec
CTRL_CORE_PAD H23
_DCAN1_RX
uart8_txd
mmc2_sdw
p
CTRL_CORE_PAD L25
_UART1_RXD
mmc4_sdcd
CTRL_CORE_PAD M25
_UART1_TXD
mmc4_sdw
p
CTRL_CORE_PAD L20
_UART1_CTSN
uart9_rxd
uart9_txd
mmc4_clk
CTRL_CORE_PAD M24
_UART1_RTSN
mmc4_cmd
CTRL_CORE_PAD N23
_UART2_RXD
uart3_ctsn uart3_rctx mmc4_dat0 uart2_rxd
uart1_dcdn
uart1_dsrn
CTRL_CORE_PAD N25
_UART2_TXD
uart3_rtsn uart3_sd
uart3_rxd
mmc4_dat1 uart2_txd
CTRL_CORE_PAD N22
_UART2_CTSN
mmc4_dat2 uart10_rxd uart1_dtrn
mmc4_dat3 uart10_txd uart1_rin
CTRL_CORE_PAD N24
_UART2_RTSN
uart2_rtsn uart3_txd
i2c1_sda
uart3_irtx
CTRL_CORE_PAD G23
_I2C1_SDA
CTRL_CORE_PAD G22
_I2C1_SCL
i2c1_scl
CTRL_CORE_PAD F23
_I2C2_SDA
i2c2_sda
i2c2_scl
hdmi1_ddc
_scl
CTRL_CORE_PAD G21
_I2C2_SCL
hdmi1_ddc
_sda
CTRL_CORE_PAD AC10
_WAKEUP0
dcan1_rx
gpio1_0
sys_nirq2
CTRL_CORE_PAD AB10
_WAKEUP3
sys_nirq1
gpio1_3
dcan2_rx
CTRL_CORE_PAD L21
_TMS
tms
tdi
CTRL_CORE_PAD L23
_TDI
gpio8_27
gpio8_28
CTRL_CORE_PAD J20
_TDO
tdo
tclk
trstn
CTRL_CORE_PAD K21
_TCLK
CTRL_CORE_PAD L22
_TRSTN
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 4-31. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS REGISTER NAME
0
1
2
3*
4*
5*
6* 8*
7
9
10
11
12
13
14*
15
0x1844
0x1848
0x184C
0x185C
0x1860
0x1864
CTRL_CORE_PAD K25
_RTCK
rtck
gpio8_29
CTRL_CORE_PAD C21
_EMU0
emu0
gpio8_30
gpio8_31
CTRL_CORE_PAD C22
_EMU1
emu1
CTRL_CORE_PAD K24
_RESETN
resetn
nmin_dsp
rstoutn
CTRL_CORE_PAD L24
_NMIN_DSP
CTRL_CORE_PAD E20
_RSTOUTN
1. NA in table stands for Not Applicable.
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4.5 Connections for Unused Pins
This section describes the connection requirements of the unused and reserved balls.
注
The following balls are reserved: K20, L19, G20
These balls must be left unconnected.
注
All unused power supply balls must be supplied with the voltages specified in the
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are
included in 节 4.3, Signal Descriptions.
表 4-32. Unused Balls Specific Connection Requirements
BALLS
CONNECTION REQUIREMENTS
These balls must be connected to GND through an external pull
resistor if unused.
Y12 / AC11 / L22 / AC10 / AB10 / AD22 / Y24 / V24 / R24
K21 / L24 / K24 / G22 / G23 / L21 / G21 / F23 / AE22 / Y25 / V25 / These balls must be connect to the corresponding power supply
R25
through an external pull resistor if unused.
F20 (vpp)
This ball must be left unconnected if unused.
注
All other unused signal balls with a Pad Configuration register can be left unconnected with
their internal pullup or pulldown resistor enabled.
注
All other unused signal balls without a Pad Configuration register can be left unconnected.
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5 Specifications
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-6, EMIF
Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM
memories.
注
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
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5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER(1)
MIN
-0.3
-0.3
MAX
UNIT
V
VSUPPLY (Steady-State)
Supply Voltage Ranges (Steady-
State)
Core (vdd, vdd_dsp)
1.5
2.0
Analog (vdda_usb1, vdda_usb2,
vdda_per, vdda_ddr, vdda_debug,
vdda_mpu_abe, vdda_usb3,
vdda_csi, vdda_core_gmac,
vdda_gpu, dda_hdmi, vdda_pcie,
vdda_video, vdda_osc)
V
Analog 3.3V (vdda33v_usb1,
vdda33v_usb2)
-0.3
-0.3
-0.3
-0.3
3.8
2.1
2.1
3.8
V
V
V
V
vdds18v, vdds18v_ddr1,
vdds_mlbp, vdds_ddr1
vddshv1, vddshv3, vddshv4,
vddshv7-11 (1.8V mode)
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9-11 (3.3V mode)
vddshv8 (3.3V mode)
Core I/Os
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3.6
1.5
2.0
3.5
1.65
1.8
2.1
3.8
V
V
V
V
V
V
V
V
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
Analog I/Os (except HDMI)
HDMI I/Os
I/O 1.35V
I/O 1.5V
1.8V I/Os
3.3V I/Os (except those powered by
vddshv8)
3.3V I/Os (powered by vddshv8)
-0.3
3.6
105
V
V/s
V
SR
Maximum slew rate, all supplies
VIO (Transient Overshoot / Input and Output Voltage Ranges (Transient Overshoot/Undershoot)
0.2 ×
Undershoot)
Note: valid for up to 20% of the signal period. See 图 5-1, IO transient
voltage ranges.
VDD (4)
TSTG
Storage temperature range after soldered onto PC Board
I-test(5), All I/Os (if different levels then one line per level)
Over-voltage Test(6), All supplies (if different levels then one line per level)
-55
-100
N/A
+150
100
°C
mA
V
Latch-up I-Test
Latch-up OV-Test
1.5 ×
Vsupply
max
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Section 5.4, Recommended Operating
Conditions, is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) See I/Os supplied by this power pin in 表 4-1 Pin Attributes
(4) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(5) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(6) Per JEDEC JESD78 at 125°C.
(7) The maximum valid input voltage on an IO pin cannot exceed 0.3 volts when the supply powering the IO is turned off. This requirement
applies to all the IO pins which are not fail-safe and for all values of IO supply voltage. Special attention should be applied anytime
peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached
peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences.
118
Specifications
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Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Nominal IO
supply voltage
Tperiod
Tundershoot
VSS
Undershoot = 20% of nominal
IO supply voltage
osus_sprs851
(1) Tovershoot + Tundershoot < 20% of Tperiod
图 5-1. IO transient voltage ranges
5.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±1000
VESD Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Power on Hours (POH) Limits
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
注
POH is a function of voltage, temperature and time. Usage at higher voltages and
temperatures will result in a reduction in POH.
表 5-1. Power on Hour (POH) Limits(1)
OPERATING CONDITION
COMMERCIAL JUNCTION
TEMP RANGE 0°C ~ 90°C
EXTENDED JUNCTION TEMP RANGE -40°C ~ 105°C
OPP
HDMI
JUNCTION
TEMP (Tj)
LIFETIME
(POH)
JUNCTION
TEMP (Tj)
LIFETIME
(POH)
JUNCTION
TEMP (Tj)
LIFETIME
(POH)
ALL
Not Used
Used(2)
90°C
90°C
100k
100k
100°C
100°C
100k
63k
105°C
105°C
100k (3)
45k
(1) Unless specified in 表 5-1, all voltage domains and operating conditions are supported in the device at the noted temperatures.
(2) Power-on hours (POH) assume HDMI is used at the maximum supported bit rate continuously and/or operating the device continuously
at the VD_MPU operating point (OPP) noted.
(3) 90k POH only if SuperSpeed USB 3.0 Dual-Role-Device (at 5 Gbps) or PCIe in Gen-II mode (at 5 Gbps) are used.
5.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
DSP voltage domain supply
See 节 5.5
See 节 5.5
V
V
vdd_dsp
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
vdda_usb1
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
DPLL_USB and HS USB1 1.8V
analog power supply
1.71
1.80
1.836
1.89
V
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_usb2
HS USB2 1.8V analog power supply
Maximum noise (peak-peak)
1.71
3.135
3.135
1.71
1.836
3.366
3.366
1.836
1.89
3.465
3.465
1.89
V
mVPPmax
vdda33v_usb1(5)
vdda33v_usb2(5)
vdda_per
HS USB1 3.3V analog power supply
Maximum noise (peak-peak)
3.3
50
V
mVPPmax
V
HS USB2 3.3V analog power supply
Maximum noise (peak-peak)
3.3
50
mVPPmax
V
PER PLL and PER HSDIVIDER
analog power supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
V
vdda_ddr
DPLL_DDR and DDR HSDIVIDER
analog power supply
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
DPLL_DEBUG analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_debug
1.71
1.71
1.836
1.836
1.89
1.89
V
mVPPmax
V
vdda_core_gmac
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.80
Maximum noise (peak-peak)
DPLL_GPU analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_gpu
1.71
1.71
1.836
1.836
1.89
1.89
V
mVPPmax
V
vdda_hdmi
PLL_HDMI and HDMI analog power
supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
V
vdda_pcie
vdda_usb3
DPLL_PCIe_REF and PCIe analog
power supply
1.71
1.71
1.80
1.836
1.836
1.836
1.89
1.89
Maximum noise (peak-peak)
50
mVPPmax
V
DPLL_USB_OTG_SS and USB3.0
RX/TX analog power supply
1.80
Maximum noise (peak-peak)
DPLL_VIDEO1 analog power supply
Maximum noise (peak-peak)
MLBP IO power supply
50
1.80
50
mVPPmax
vdda_video
vdds_mlbp
vdda_mpu_abe
vdda_osc
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.89
1.89
1.89
1.89
1.89
1.89
1.89
V
mVPPmax
V
1.80
50
Maximum noise (peak-peak)
DPLL_MPU analog power supply
Maximum noise (peak-peak)
HFOSC analog power supply
Maximum noise (peak-peak)
CSI Interface 1.8v Supply
Maximum noise (peak-peak)
1.8V power supply
mVPPmax
V
1.80
50
1.836
mVPPmax
V
1.80
50
mVPPmax
V
vdda_csi
1.80
50
1.836
1.836
1.836
mVPPmax
V
vdds18v
1.80
50
Maximum noise (peak-peak)
EMIF1 bias power supply
mVPPmax
V
vdds18v_ddr1
1.80
50
Maximum noise (peak-peak)
mVPPmax
120
Specifications
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
vdds_ddr1
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
EMIF1 power supply
(1.5V for DDR3 mode /
1.35V DDR3L mode)
1.35-V
Mode
1.28
1.35
1.377
1.42
V
1.5-V Mode
1.43
1.50
50
1.53
1.57
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
3.3-V Mode
vddshv1
vddshv10
vddshv11
vddshv3
vddshv4
vddshv7
vddshv8
vddshv9
Dual Voltage (1.8V or
3.3V) power supply for
the VIN2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the GPMC Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the GENERAL Power
Group pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC4 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the WIFI Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC1 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
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Specifications
121
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
Ground supply
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
V
vss
0
0
0
vssa_osc0
vssa_osc1
OSC0 analog ground
OSC1 analog ground
V
V
(1)
TJ
Operating junction
temperature range
Commercial
Extended
0
90
°C
-40
105
ddr1_vref0
Reference Power Supply EMIF1
0.5 × vdds_ddr1
V
(1) Refer to Power on Hours table for limitations.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
(5) USB Analog supply also powers digital IO buffers. This supply cannot be tied to VSS if USB is unused since digital IO buffers must be
powered during device operation.
5.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
表 5-2 describes the maximum supported frequency per speed grade for AM570x devices.
表 5-2. Speed Grade Maximum Frequency(1)(2)
MAXIMUM FREQUENCY (MHz)
DEVICE SPEED
MPU
1000
1000
500
DSP
750
750
500
IPU
IVA
532
N/A
N/A
GPU
425
N/A
N/A
L3
DDR3 / DDR3L
667 (DDR3-1333)
667 (DDR3-1333)
533 (DDR3-1066)
AM5708xxJ
AM5706xxJ
AM5706xxD
212.8
212.8
212.8
266
266
266
(1) N/A stands for Not Applicable.
(2) If the corresponding core is not available in the respective subdevice, the value shall be read as N/A. For more information, see 表 3-1,
Device Comparison.
5.5.1 AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in 表 5-3.
表 5-3. AVS and ABB Requirements per vdd_* Supply
SUPPLY
VOLTAGE DOMAIN
VD_CORE
VD_SGX
AVS REQUIRED?
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
ABB REQUIRED?
No
vdd
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
Yes, for all OPPs
VD_MPU
vdd_dsp
VD_DSP
VD_IVA
5.5.2 Voltage And Core Clock Specifications
表 5-4 shows the recommended OPP per voltage domain.
122
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-4. Voltage Domains Operating Performance Points (1)
DOMAIN
CONDITION
OPP_NOM
NOM (2)
1.15
OPP_HIGH
NOM (2) MAX DC (4)
MIN (3)
MAX (3)
MIN (3)
MAX (3)
(8)
VD_CORE (V)
BOOT (Before AVS is
1.11
1.2
Not Applicable
(5)
enabled)
After AVS is enabled (5)
AVS
AVS
1.2
Not Applicable
Voltage
Voltage
(6)
(6) – 3.5%
(9)
VD_DSP (V)
BOOT (Before AVS is
enabled)
After AVS is enabled (5)
1.02
AVS
1.06
1.16
1.2
Not Applicable
(5)
AVS
AVS
AVS
AVS
AVS
Voltage(6) Voltage
Voltage(6) Voltage (6) Voltage (6) Voltage(6)
(6)
– 3.5%
– 3.5%
+2%
+ 5%
(1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with
the ability to modify the voltage to comply with future recommendations.
(2) In a typical implementation, the power supply should target the NOM voltage.
(3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(4) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(6) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
–
–
–
OPP_NOM for DSP: 0.85 V – 1.15 V
OPP_NOM for CORE: 0.85 V - 1.15 V
OPP_HIGH: 1.01 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(7) The power supply must be programmed with the AVS voltages for the CORE voltage domain, either just after the ROM boot or at the
earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
(8) The package routes VD_CORE (vdd) to the VD_MPU, VD_SGX, VD_CORE and VD_RTC domains on the die.
(9) The package routes VD_DSP (vdd_dsp) to the VD_DSPEVE and VD_IVA domains on the die.
表 5-5 describes the standard processor clocks speed characteristics vs OPP of the device.
表 5-5. Supported OPP vs Max Frequency (2)
DESCRIPTION
OPP_NOM
OPP_HIGH
MAXIMUM FREQUENCY (MHz)
MAXIMUM FREQUENCY (MHz)
VD_CORE
MPU_CLK
GPU_CLK
1000
425.6
N/A
N/A
N/A
N/A
N/A
CORE_IPUx_CLK
L3_CLK
212.8
266
DDR3 / DDR3L
667 (DDR3-1333)
VD_DSP
IVA_GCLK
DSP_CLK
388.3
600
532
750
(1) N/A stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see 表 5-2).
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. 表 5-6 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
123
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
AES1
AES2
BB2D
AES1_L3_CLK
AES2_L3_CLK
BB2D_FCLK
BB2D_ICLK
Int
Int
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
BB2D_GFCLK
CORE_X2_CLK
CORE_X2_CLK
BB2D_GFCLK
CORE_X2_CLK
SYS_CLK1/610
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
Func
Int
354.6
266
DSS_L3_GICLK
FUNC_32K_CLK
COUNTER_32K
COUNTER_32K_FC
LK
Func
0.032
COUNTER_32K_ICL
K
Int
Int
38.4
4.8
WKUPAON_GICLK
L3INSTR_TS_GCLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_B L3INSTR_TS_GCLK
ANDGAP
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_C L4CFG_L4_GICLK
ORE
Int
Int
133
L4CFG_L4_GICLK
WKUPAON_GICLK
CORE_X2_CLK
DPLL_CORE
CTRL_MODULE_
WKUP
WKUPAON_GICLK
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN1
DCAN2
DCAN1_FCLK
DCAN1_ICLK
Func
Int
38.4
266
DCAN1_SYS_CLK
WKUPAON_GICLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
OSC0
OSC1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN2_FCLK
DCAN2_ICLK
Func
Int
38.4
266
266
DCAN2_SYS_CLK
L4PER2_L3_GICLK
L4SEC_L3_GICLK
EMIF_DLL_GCLK
SYS_CLK1
OSC0
CORE_X2_CLK
CORE_X2_CLK
EMIF_DLL_GCLK
DPLL_CORE
DPLL_CORE
DPLL_DDR
DES3DES
DLL
DES_CLK_L3
Int
EMIF_DLL_FCLK
Func
EMIF_DLL_FC
LK
DLL_AGING
FCLK
Int
38.4
L3INSTR_DLL_AGING
_GCLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DMM
DPLL_DEBUG
DSP1
DMM_CLK
SYSCLK
Int
Int
266
38.4
EMIF_L3_GICLK
EMU_SYS_CLK
DSP1_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
DSP1_FICLK
Int &
Func
DSP_CLK
DSP_GFCLK
DPLL_DSP
124
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
DSS
DSS_HDMI_CEC_C
LK
Func
Func
0.032
HDMI_CEC_GFCLK
SYS_CLK1/610
OSC0
DSS_HDMI_PHY_C
LK
48
HDMI_PHY_GFCLK
FUNC_192M_CLK
DPLL_PER
DSS_CLK
Func
Func
192
DSS_GFCLK
DSS_CLK
SYS_CLK1
SYS_CLK2
CORE_X2_CLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
SYS_CLK2
HDMI_CLK
DPLL_PER
OSC0
HDMI_CLKINP
38.4
HDMI_DPLL_CLK
OSC1
DSS_L3_ICLK
Int
266
DSS_L3_GICLK
DPLL_CORE
OSC0
VIDEO1_CLKINP
Func
38.4
VIDEO1_DPLL_CLK
OSC1
VIDEO2_CLKINP
Func
Func
38.4
VIDEO2_DPLL_CLK
N/A
OSC0
OSC1
DPLL_DSI1_A_CLK
1
209.3
DPLL_HDMI
DPLL_VIDEO1
VIDEO1_CLKOUT
1
DPLL_DSI1_B_CLK
1
Func
Func
209.3
209.3
N/A
N/A
VIDEO1_CLKOUT
3
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
DPLL_ABE
DPLL_ABE_X2_CL
K
DPLL_DSI1_C_CLK
1
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT
3
DPLL_VIDEO1
DPLL_HDMI_CLK1
LCD1_CLK
Func
Func
185.6
209.3
N/A
N/A
HDMI_CLK
DPLL_HDMI
DSS DISPC
DPLL_DSI1_A_CL
K1
See DSS data in
the rows above
DSS_CLK
LCD2_CLK
LCD3_CLK
F_CLK
Func
Func
Func
209.3
209.3
209.3
N/A
N/A
N/A
DPLL_DSI1_B_CL
K1
DSS_CLK
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
CORE_X2_CLK
EFUSE_CTRL_CU
ST
ocp_clk
sys_clk
Int
133
CUSTEFUSE_L4_GICL
K
DPLL_CORE
OSC0
Func
38.4
CUSTEFUSE_SYS_GF
CLK
SYS_CLK1
ELM
EMIF_OCP_FW
EMIF_PHY1
EMIF1
ELM_ICLK
L3_CLK
Int
Int
266
266
L4PER_L3_GICLK
EMIF_L3_GICLK
EMIF_PHY_GCLK
EMIF_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
EMIF_PHY_GCLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_DDR
EMIF_PHY1_FCLK
EMIF1_ICLK
Func
Int
DDR
266
DPLL_CORE
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
125
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
GMAC_SW
CPTS_RFT_CLK
Func
266
GMAC_RFT_CLK
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_GMAC
DPLL_GMAC
CORE_X2_CLK
GMAC_250M_CLK
MAIN_CLK
Int
125
250
GMAC_MAIN_CLK
GMII_250MHZ_CLK
MHZ_250_CLK
Func
GMII_250MHZ_CL
K
MHZ_5_CLK
MHZ_50_CLK
Func
Func
Func
Func
Int
5
50
RGMII_5MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
WKUPAON_GICLK
GMAC_RMII_HS_
CLK
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
GMAC_RMII_HS_
CLK
RMII1_MHZ_50_CL
K
50
GMAC_RMII_HS_
CLK
RMII2_MHZ_50_CL
K
50
GMAC_RMII_HS_
CLK
GPIO1
GPIO1_ICLK
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
GPIO1_DBCLK
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_
OSC0
LK
GFCLK
GPIO2
GPIO3
GPIO4
GPIO2_ICLK
GPIO2_DBCLK
GPIO3_ICLK
GPIO3_DBCLK
GPIO4_ICLK
GPIO4_DBCLK
PIDBCLK
Int
Func
Int
266
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
L4PER_L3_GICLK
GPIO_GFCLK
DPLL_CORE
OSC0
Func
Int
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO5
GPIO6
GPIO7
GPIO8
GPMC
GPIO5_ICLK
GPIO5_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO6_ICLK
GPIO6_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO7_ICLK
GPIO7_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO8_ICLK
GPIO8_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPMC_FCLK
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
126
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
GPU
GPU_FCLK1
GPU_FCLK2
GPU_ICLK
Func
GPU_CLK
GPU_CORE_GCLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
Func
GPU_CLK
GPU_HYD_GCLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
Int
266
GPU_L3_GICLK
CORE_X2_CLK
FUNC_192M_CLK
HDMI PHY
HDQ1W
DSS_HDMI_PHY_C
LK
Func
38.4
HDMI_PHY_GFCLK
HDQ1W_ICLK
Int &
Func
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDQ1W_FCLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
PI_L3CLK
Func
Int
12
266
96
PER_12M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
IPU_L3_GICLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
I2C1
I2C2
I2C3
I2C4
I2C5
Func
Int
266
96
Func
Int
266
96
Func
Int
266
96
Func
Int
266
96
Func
IPU_96M_GFCLK
L3INIT_L3_GICLK
IEEE1500_2_OCP
IPU1
Int &
Func
266
IPU1_GFCLK
Int &
Func
425.6
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
DPLL_CORE
CORE_IPU_ISS_B
OOST_CLK
IPU2
IPU2_GFCLK
Int &
Func
425.6
IPU2_GFCLK
IVA_GCLK
CORE_IPU_ISS_B
OOST_CLK
IVA
IVA_GCLK
KBD_FCLK
Int
IVA_GCLK
0.032
IVA_GFCLK
DPLL_IVA
OSC0
KBD
Func
WKUPAON_SYS_GFC WKUPAON_32K_
LK
GFCLK
PICLKKBD
Func
0.032
WKUPAON_SYS_GFC
LK
KBD_ICLK
PICLKOCP
Int
Int
38.4
38.4
WKUPAON_GICLK
WKUPAON_GICLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
L3_INSTR
L3_MAIN
L3_CLK
Int
Int
Int
Int
Int
Int
Int
Int
L3_CLK
L3_CLK
L3_CLK
133
L3INSTR_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
L3_CLK1
L3_CLK2
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
133
133
133
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
127
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
MAILBOX1
MAILBOX2
MAILBOX3
MAILBOX4
MAILBOX5
MAILBOX6
MAILBOX7
MAILBOX8
MAILBOX9
MAILBOX10
MAILBOX11
MAILBOX12
MAILBOX13
MAILBOX1_FLCK
MAILBOX2_FLCK
MAILBOX3_FLCK
MAILBOX4_FLCK
MAILBOX5_FLCK
MAILBOX6_FLCK
MAILBOX7_FLCK
MAILBOX8_FLCK
MAILBOX9_FLCK
MAILBOX10_FLCK
MAILBOX11_FLCK
MAILBOX12_FLCK
MAILBOX13_FLCK
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
266
266
266
266
266
266
266
266
266
266
266
266
266
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
128
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McASP1
MCASP1_AHCLKR
Func
100
MCASP1_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP1_AHCLKX
Func
100
MCASP1_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP1_FCLK
MCASP1_ICLK
Func
Int
192
266
MCASP1_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
IPU_L3_GICLK
CORE_X2_CLK
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
129
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McASP2
MCASP2_AHCLKR
Func
100
MCASP2_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP2_AHCLKX
Func
100
MCASP2_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP2_FCLK
MCASP2_ICLK
Func
Int
192
266
MCASP2_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
130
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McASP3
MCASP3_AHCLKX
Func
100
MCASP3_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP3_FCLK
Func
192
MCASP3_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP3_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP4_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
McASP4
MCASP4_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP4_FCLK
MCASP4_ICLK
Func
Int
192
266
MCASP4_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
131
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McASP5
MCASP5_AHCLKX
Func
100
MCASP5_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP5_FCLK
Func
192
MCASP5_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
DPLL_PER
MCASP5_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP6_AHCLKX
CORE_X2_CLK
McASP6
MCASP6_AHCLKX
Func
ABE_24M_GFCLK
FUNC_24M_GFCL
K
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
Module MLB
Module MLB
OSC0
ATL_CLK2
ATL_CLK3
MLB_CLK
MLBP_CLK
ABE_SYS_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
MCASP6_FCLK
MCASP6_ICLK
Func
Int
192
266
MCASP6_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
132
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McASP7
MCASP7_AHCLKX
Func
100
MCASP7_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP7_FCLK
Func
192
MCASP7_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP7_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP8_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
McASP8
MCASP8_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP8_FCLK
Func
192
MCASP8_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
MCASP8_ICLK
SPI1_ICLK
SPI1_FCLK
SPI2_ICLK
SPI2_FCLK
SPI3_ICLK
SPI3_FCLK
Int
Int
266
266
48
L4PER2_L3_GICLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
McSPI1
McSPI2
McSPI3
Func
Int
266
48
Func
Int
266
48
Func
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
133
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
McSPI4
SPI4_ICLK
SPI4_FCLK
MLB_L3_ICLK
MLB_L4_ICLK
MLB_FCLK
CTRLCLK
Int
Func
Int
266
48
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
MLB_SS
CSI2_0
266
133
266
96
MLB_SHB_L3_GICLK
MLB_SPB_L4_GICLK
MLB_SYS_L3_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
Int
Func
Int &
Func
LVDSRX_96M_GFCLK FUNC_192M_CLK
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
OSC0
MMC1
MMC2
MMC1_CLK_32K
MMC1_FCLK
Func
Func
0.032
192
L3INIT_32K_GFCLK
MMC1_GFCLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
OSC0
128
MMC1_ICLK1
MMC1_ICLK2
MMC2_CLK_32K
MMC2_FCLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L3INIT_32K_GFCLK
MMC2_GFCLK
133
Func
Func
0.032
192
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
128
MMC2_ICLK1
MMC2_ICLK2
MMC3_ICLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC3_GFCLK
133
MMC3
MMC4
Int
266
MMC3_CLK_32K
MMC3_FCLK
Func
Func
0.032
48
DPLL_PER
192
MMC4_ICLK
MMC4_CLK_32K
MMC4_FCLK
Int
266
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC4_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_CORE
OSC0
Func
Func
0.032
48
DPLL_PER
192
MMU_EDMA
MMU_PCIESS
MPU
MMU1_CLK
MMU2_CLK
MPU_CLK
Int
Int
266
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
MPU_GCLK
CORE_X2_CLK
CORE_X2_CLK
MPU_GCLK
DPLL_CORE
DPLL_CORE
DPLL_MPU
266
Int &
Func
MPU_CLK
MPU_EMU_DBG
FCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
MPU_GCLK
OSC0
DPLL_MPU
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OCMC_RAM1
OCMC_ROM
OCP_WP_NOC
OCP2SCP1
OCMC1_L3_CLK
OCMC_L3_CLK
PICLKOCPL3
Int
Int
Int
Int
266
266
266
133
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L3INIT_L4_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
L4CFG1_ADAPTER
_CLKIN
OCP2SCP2
OCP2SCP3
L4CFG2_ADAPTER
_CLKIN
Int
Int
133
133
L4CFG_L4_GICLK
L3INIT_L4_GICLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
L4CFG3_ADAPTER
_CLKIN
134
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
PCIe_SS1
PCIE1_PHY_WKUP
_CLK
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
DPLL_CORE
PCIe_SS1_FICLK
PCIEPHY_CLK
Int
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
Func
Func
PCIE_PHY_GCLK
APLL_PCIE
APLL_PCIE
PCIEPHY_CLK_DIV
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE1_REF_CLKIN
PCIE1_PWR_CLK
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
Func
Func
38.4
PCIE_SYS_GFCLK
PCIE_32K_GFCLK
SYS_CLK1
OSC0
PCIe_SS2
PCIE2_PHY_WKUP
_CLK
0.032
FUNC_32K_CLK
DPLL_CORE
PCIe_SS2_FICLK
PCIEPHY_CLK
Int
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
Func
Func
PCIE_PHY_GCLK
APLL_PCIE
APLL_PCIE
PCIEPHY_CLK_DIV
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE2_REF_CLKIN
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE2_PWR_CLK
32K_CLK
Func
Func
Func
38.4
0.032
38.4
PCIE_SYS_GFCLK
FUNC_32K_CLK
WKUPAON_ICLK
SYS_CLK1
SYS_CLK1/610
SYS_CLK1
OSC0
OSC0
PRCM_MPU
SYS_CLK
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PWMSS1
PWMSS2
PWMSS3
QSPI
PWMSS1_GICLK
PWMSS2_GICLK
PWMSS3_GICLK
Int &
Func
266
266
266
L4PER2_L3_GICLK
L4PER2_L3_GICLK
L4PER2_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
Int &
Func
Int &
Func
QSPI_ICLK
QSPI_FCLK
Int
266
128
L4PER2_L3_GICLK
QSPI_GFCLK
CORE_X2_CLK
FUNC_256M_CLK
PER_QSPI_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
Func
RNG
RNG_ICLK
Int
Int
266
266
L4SEC_L3_GICLK
L4CFG_L3_GICLK
SAR_ROM
PRCM_ROM_CLOC
K
SDMA
SDMA_FCLK
Int &
Func
266
DMA_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SHA2MD51
SHA2MD52
SL2
SHAM_1_CLK
SHAM_2_CLK
IVA_GCLK
MCLK
Int
Int
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
IVA_GCLK
CORE_X2_CLK
CORE_X2_CLK
IVA_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_IVA
DPLL_CORE
OSC0
Int
IVA_GCLK
133
SMARTREFLEX_C
ORE
Int
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_D
SP
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
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Specifications
135
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
SMARTREFLEX_G
PU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_I
VAHD
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_M
PU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
Int
Int
266
L4CFG_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER1_FCLK
Func
100
TIMER1_GFCLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER2
TIMER2_ICLK
TIMER2_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER2_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
136
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
TIMER3
TIMER3_ICLK
TIMER3_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER3_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER4
TIMER4_ICLK
TIMER4_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER4_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER5
TIMER5_ICLK
TIMER5_FCLK
Int
266
100
IPU_L3_GICLK
TIMER5_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
137
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
TIMER6
TIMER6_ICLK
TIMER6_FCLK
Int
266
100
IPU_L3_GICLK
TIMER6_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER7
TIMER7_ICLK
TIMER7_FCLK
Int
266
100
IPU_L3_GICLK
TIMER7_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER8
TIMER8_ICLK
TIMER8_FCLK
Int
266
100
IPU_L3_GICLK
TIMER8_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
138
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
TIMER9
TIMER9_ICLK
TIMER9_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER9_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER10
TIMER11
TIMER12
TIMER10_ICLK
TIMER10_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER10_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER11_ICLK
TIMER11_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER11_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
SYS_CLK1
DPLL_VIDEO1
DPLL_HDMI
OSC0
TIMER12_ICLK
TIMER12_FCLK
Int
38.4
WKUPAON_GICLK
OSC_32K_CLK
DPLL_ABE_X2_CL
K
DPLL_ABE
Func
0.032
RC_CLK
RC oscillator
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
139
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
TIMER13
TIMER13_ICLK
TIMER13_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER13_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER14
TIMER14_ICLK
TIMER14_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER14_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER15
TIMER15_ICLK
TIMER15_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER15_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
140
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
TIMER16
TIMER16_ICLK
TIMER16_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER16_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
OSC0
TPCC
TPTC1
TPTC2
UART1
TPCC_GCLK
TPTC0_GCLK
TPTC1_GCLK
UART1_FCLK
UART1_ICLK
UART2_FCLK
UART2_ICLK
UART3_FCLK
UART3_ICLK
UART4_FCLK
UART4_ICLK
UART5_FCLK
UART5_ICLK
UART6_FCLK
UART6_ICLK
UART7_FCLK
UART7_ICLK
UART8_FCLK
UART8_ICLK
UART9_FCLK
UART9_ICLK
UART10_FCLK
UART10_ICLK
Int
Int
266
266
266
48
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
UART1_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
SYS_CLK1
Int
Func
Int
266
48
L4PER_L3_GICLK
UART2_GFCLK
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART9
UART10
Func
Int
266
48
L4PER_L3_GICLK
UART3_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART4_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART5_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART6_GFCLK
Func
Int
266
48
IPU_L3_GICLK
Func
Int
UART7_GFCLK
266
48
L4PER2_L3_GICLK
UART8_GFCLK
Func
Int
266
48
L4PER2_L3_GICLK
UART9_GFCLK
Func
Int
266
48
L4PER2_L3_GICLK
UART10_GFCLK
WKUPAON_GICLK
Func
Int
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
USB1
USB1_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
USB3PHY_REF_CL
K
Func
34.3
USB_LFPS_TX_GFCL CORE_USB_OTG_
K
SS_LFPS_TX_CLK
USB2PHY1_TREF_
CLK
Func
Func
38.4
960
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC0
USB2PHY1_REF_C
LK
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
141
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-6. Maximum Supported Frequency (continued)
MODULE
CLOCK SOURCES
MAX. CLOCK
ALLOWED
(MHz)
PLL / OSC /
PRCM CLOCK NAME SOURCE CLOCK
NAME
INPUT CLOCK
NAME
CLOCK
TYPE
PLL / OSC /
SOURCE NAME
INSTANCE NAME
USB2
USB2_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
USB2PHY2_TREF_
CLK
Func
38.4
USB_OTG_SS_REF_C
LK
USB2PHY2_REF_C
LK
Func
Func
Func
960
0.032
0.032
266
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
OSC0
USB_PHY1_CORE USB2PHY1_WKUP_
CLK
COREAON_32K_GFCL
K
SYS_CLK1/610
SYS_CLK1/610
CORE_X2_CLK
USB_PHY2_CORE USB2PHY2_WKUP_
CLK
COREAON_32K_GFCL
K
OSC0
VIP1
L3_CLK_PROC_CL
K
Int &
Func
VIP1_GCLK
DPLL_CORE
DPLL_CORE
CORE_ISS_MAIN_
CLK
VPE
L3_CLK_PROC_CL
K
Int &
Func
300
VPE_GCLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT
4
DPLL_VIDEO1
WD_TIMER1
WD_TIMER2
PIOCPCLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PITIMERCLK
Func
Int
0.032
38.4
OSC_32K_CLK
RC_CLK
RC oscillator
OSC0
WD_TIMER2_ICLK
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
DPLL_ABE
WD_TIMER2_FCLK
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_
LK GFCLK
5.6 Power Consumption Summary
注
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
注
The data specified in 节 5.7 through 节 5.7.3 are subject to change.
注
The interfaces or signals described in 节 5.7 through 节 5.7.3 correspond to the interfaces or
signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
142
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
注
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control
Module of the Device TRM.
表 5-7. LVCMOS DDR DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn0, ddr1_cke,
ddr1_odt0, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst
Balls: AA23 / AC24 / AB24 / AD24 / AB23 / AC23 / AD23 / AE24 / AA24 / W25 / Y23 / AD25 / AC25 / AB25 / AA25 / W24 / W23 / U25 /
U24 / W21 / T22 / U22 / U23 / T21 / T23 / T25 / T24 / P21 / N21 / P22 / P23 / P24 / AC18 / AE19 / AD19 / AB19 / AD20 / AE20 / AA18 /
AA20 / Y21 / AC20 / AA21 / AC21 / AC22 / AC15 / AB15 / AC16 / AE23 / W22 / U21 / P25 / AE16 / AA16 / AB16 / AC19 / AB18 / AD18 /
AD16 / AD17 / AE18 / AE17
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9 × VDDS
V
V
0.1 × VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
VREF+
-10%vdds
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
Signal Names in MUXMODE 0 (Differential Signals): ddr1_ck, ddr1_nck, ddr1_dqs[3:0], ddr1_dqsn[3:0]
Bottom Balls: AD21 / AE21 / AD22 / AE22 / Y24 / Y25 / V24 / V25 / R24 / R25
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9 × VDDS
V
V
0.1 × VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
Low-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
143
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-7. LVCMOS DDR DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
VCM
Input common-mode voltage
VREF
VREF+
V
-10%vdds
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
Differential Receiver Mode
VSWING Input voltage swing
VCM Input common-mode voltage
DDR3/DDR3L
0.2
vdds+0.4
V
V
VREF
VREF+
-10%vdds
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS stands for corresponding power supply (that is, vdds_ddr1). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [11] column.
(2) VREF in this table stands for corresponding Reference Power Supply (that is, ddr1_vref0). For more information on the power supply
name and the corresponding ball, see 表 4-1, POWER [11] column.
表 5-8. Dual Voltage LVCMOS I2C DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: i2c1_scl; i2c1_sda; i2c2_scl; i2c2_sda
Balls: G22 / G23 / G21 / F23
MIN
NOM
MAX
UNIT
I2C Standard Mode – 1.8 V
VIH
VIL
Input high-level threshold
Input low-level threshold
Hysteresis
0.7 × VDDS
0.1 × VDDS
V
V
0.3 × VDDS
Vhys
IIN
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS
IOLmin
tOF
Low-level output current @VOL=0.2 × VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
I2C Fast Mode – 1.8 V
VIH
VIL
Input high-level threshold
0.7 × VDDS
0.1 × VDDS
V
V
Input low-level threshold
Hysteresis
0.3 × VDDS
Vhys
IIN
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS
IOLmin
tOF
Low-level output current @VOL=0.2 × VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 400 pF
20+0.1 × Cb
250
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表 5-8. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
I2C Standard Mode – 3.3 V
VIH
VIL
Input high-level threshold
Input low-level threshold
Hysteresis
0.7 × VDDS
V
V
0.3 × VDDS
Vhys
IIN
0.05 × VDDS
31
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
80
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
ns
I2C Fast Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7 × VDDS
V
V
Input low-level threshold
Hysteresis
0.3 × VDDS
Vhys
IIN
0.05 × VDDS
31
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDSS
80
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1 × Cb
250
290
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
40
(1) VDDS stands for corresponding power supply (that is, vddshv3). For more information on the power supply name and the corresponding
ball, see 表 4-1, POWER [11] column.
(2) For more information on the I/O cell configurations, see the Control Module section of the Device TRM.
表 5-9. IQ1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk
Balls: K21
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表 5-9. IQ1833 Buffers DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
1.8-V Mode
MIN
NOM
MAX
UNIT
VIH
Input high-level threshold (Does not meet JEDEC VIH
)
0.75 ×
VDDS
V
V
VIL
Input low-level threshold (Does not meet JEDEC VIL)
0.25 ×
VDDS
VHYS
IIN
Input hysteresis voltage
100
2
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
3.3-V Mode
VIH
Pad capacitance (including package capacitance)
Input high-level threshold (Does not meet JEDEC VIH
Input low-level threshold (Does not meet JEDEC VIL)
Input hysteresis voltage
)
2.0
V
V
VIL
0.6
VHYS
IIN
400
5
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
Pad capacitance (including package capacitance)
(1) VDDS stands for corresponding power supply (that is, vddshv3). For more information on the power supply name and the corresponding
ball, see 表 4-1, POWER [11] column.
表 5-10. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: porz / wakeup3 / wakeup0
Balls: AB10/ AC10/ F19
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
1.2(1)
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
0.02
1
1
CPAD
3.3-V Mode
VIH
Input high-level threshold
1.2(1)
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
5
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
8
1
CPAD
(1) The IHHV1833 buffer exists in the dual-voltage IO logic that can be powered by either 1.8V or 3.3V provided by vddshv3. However, the
vddshv3 supply is only used for input protection circuitry, not for logic functionality. The logic in this buffer operates entirely on the
vdds18v supply. Therefore, these input buffers are fully functional whenever vdds18v is valid.
表 5-11. LVCMOS CSI2 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signals MUXMODE 0: csi2_0_dx[2:0] / csi2_0_dy[2:0]
Bottom Balls: AC1 / AB2 / AD1 / AC2 / AE2 / AD2
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
VIH
VIL
Input high-level voltage
Input low-level voltage
Input high-level threshold(1)
880
1350
550
mV
mV
mV
VITH
880
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表 5-11. LVCMOS CSI2 DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
550
25
NOM
MAX
UNIT
mV
VITL
Input low-level threshold(2)
Input hysteresis(3)
VHYS
mV
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
VIL
VITL
VHYS
Input low-level voltage
Input low-level threshold(4)
Input hysteresis(3)
300
mV
mV
mV
300
25
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
VIDTH
VIDTL
Differential input high-level threshold
Differential input low-level threshold
Maximum differential input voltage(7)
Single-ended input high voltage(5)
Single-ended input low voltage(5)
Differential input common-mode voltage(5)(6)
Differential input impedance
70
mV
mV
mV
mV
mV
mV
Ω
–70
270
460
VIDMAX
VIHHS
VILHS
–40
70
VCMRXDC
ZID
330
125
80
100
(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference
between the VITH threshold and the VITL threshold.
(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VODMAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see 表 4-5, CSI 2 Signal Descriptions.
表 5-12. BMLB18 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: mlbp_dat_n / mlbp_dat_p / mlbp_sig_n / mlbp_sig_p / mlbp_clk_n / mlbp_clk_p
Balls: T1 / T2 / U4 / T3 / U1 / U2
1.8-V Mode
VIH/VIL
Input high-level threshold
Input hysteresis voltage
VCM ±
50mV
V
VHYS
VOD
NONE
mV
mV
Differential output voltage (measured with 50Ω resistor
between PAD and PADN)
300
1
500
VCM
Common mode output voltage
1.5
4
V
CPAD
Pad capacitance (including package capacitance)
pF
表 5-13. Dual Voltage SDIO1833 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: U3 / V4 / V3 / V2 / W1 / V1
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表 5-13. Dual Voltage SDIO1833 DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
1.8-V Mode
MIN
NOM
MAX
UNIT
VIH
VIL
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
1.27
V
V
0.58
(2)
VHYS
IIN
50
mV
µA
µA
30
30
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
50
60
120
120
210
200
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
5
pF
V
1.4
0.45
V
3.3-V Mode
VIH
Input high-level threshold
0.625 ×
VDDS
V
VIL
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
0.25 × VDDS
V
(2)
VHYS
IIN
40
mV
µA
µA
110
110
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
40
10
100
100
290
290
5
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
pF
V
0.75 × VDDS
0.125 ×
VDDS
V
(1) VDDS stands for corresponding power supply (that is, vddshv8). For more information on the power supply name and the corresponding
ball, see 表 4-1, POWER [11] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
表 5-14. Dual Voltage LVCMOS DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
0.35 × VDDS
0.45
UNIT
1.8-V Mode
VIH
Input high-level threshold
0.65 × VDDS
V
V
VIL
Input low-level threshold
VHYS
VOH
Input hysteresis voltage
100
mV
V
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
VDDS-0.45
VOL
V
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表 5-14. Dual Voltage LVCMOS DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
IIN
Input current at each I/O pin
16
16
µA
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
50
60
120
120
210
200
4
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
3.3-V Mode
VIH
Input high-level threshold
2
V
V
VIL
Input low-level threshold
0.8
0.2
VHYS
VOH
Input hysteresis voltage
200
mV
V
Output high-level threshold (IOH = 100 µA)
Output low-level threshold (IOL = 100 µA)
VDDS-0.2
VOL
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
IIN
Input current at each I/O pin
65
65
µA
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
40
10
100
100
200
290
4
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表 4-1,
POWER [11] column.
5.7.1 USBPHY DC Electrical Characteristics
注
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
注
USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0
dated April 27, 2000 including ECNs and Errata as applicable.
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5.7.2 HDMIPHY DC Electrical Characteristics
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not
reproduced here.
5.7.3 PCIEPHY DC Electrical Characteristics
注
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 3.0.
5.8 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is
applicable only for High-Security Devices.
表 5-15. Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
vdd
vpp
Supply voltage range for the core domain
during OTP operation
1.11
1.15
1.2
V
Supply voltage range for the eFuse ROM
domain during normal operation
NC
V
V
Supply voltage range for the eFuse ROM
domain during OTP programming(1)(2)
1.8
25
I(vpp)
Tj
100
85
mA
ºC
Temperature (junction)
0
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family
meet the supply voltage range needed for vpp.
(2) During normal operation, no voltage should be applied to vpp. This can be typically achieved by disabling the regulator attached to the
vpp terminal. For more details, see TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices.
5.8.1 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The vpp power supply must be disabled when not programming OTP registers.
The vpp power supply must be ramped up after the proper device power-up sequence (for more
details, see Section 5.10.3).
5.8.2 Programming Sequence
Programming sequence for OTP eFuses:
1. Power on the board per the power-up sequencing. No voltage should be applied on the vpp terminal
during power up and normal operation.
2. Load the OTP write software required to program the eFuse (contact your local TI representative for
the OTP software package).
3. Apply the voltage on the vpp terminal according to the specification in 表 5-15.
4. Run the software that programs the OTP registers.
5. After validating the content of the OTP registers, remove the voltage from the vpp terminal.
150
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5.8.3 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge
that the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a
sequence step. Further the TI Device may fail to secure boot if the error code correction check fails for the
Production Keys or if the image is not signed and optionally encrypted with the current active Production
Keys. These types of situations will render the TI Device inoperable and TI will be unable to confirm
whether the TI Devices conformed to their specifications prior to the attempted e-Fuse.
CONSEQUENTLY, TI WILL HAVE NO LIABILITY (WARRANTY OR OTHERWISE) FOR ANY TI
DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
5.9 Thermal Resistance Characteristics for CBD Package
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Section 5.4, Recommended Operating Conditions.
It is recommended to perform thermal simulations at the system level with the worst case device power
consumption.
5.9.1 Package Thermal Characteristics
表 5-16 provides the thermal resistance characteristics for the package used on this device.
注
Power dissipation of 3.0 W and an ambient temperature of 85ºC is assumed for CBD
package.
表 5-16. Thermal Resistance Characteristics
NO.
T1
PARAMETER
RΘJC
DESCRIPTION
°C/W(1)
0.23
3.65
12.8
10.4
9.6
AIR FLOW (m/s)(2)
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N/A
0
T2
RΘJB
T3
T4
0.5
1
T5
RΘJA
Junction-to-moving air
T6
8.8
2
T7
8.3
3
T8
0.1
0
T9
0.1
0.5
1
T10
T11
T12
T13
T14
T15
T16
T17
ΨJT
Junction-to-package top
0.1
0.1
2
0.1
3
3.7
0
3.7
0.5
1
ΨJB
Junction-to-board
3.6
3.6
2
3.5
3
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement,
which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more
information, see these EIA/JEDEC standards:
–
–
–
–
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
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5.10 Timing Requirements and Switching Characteristics
5.10.1 Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
Table 5-17. Timing Parameters
SUBSCRIPTS
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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5.10.1.1 Parameter Information
Tester Pin Electronics
Transmission Line
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
Figure 5-2. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
Figure 5-3. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
Figure 5-4. Rise and Fall Transition Time Voltage Reference Levels
5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to ensure timings,
unless specific instructions otherwise are given in the individual timing subsections of the datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
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5.10.1.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report. If needed, external logic hardware such as buffers may be used to compensate any
timing differences.
5.10.2 Interface Clock Specifications
5.10.2.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
5.10.2.2 Interface Clock Frequency
The two interface clock characteristics are:
•
•
The maximum clock frequency
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
5.10.3 Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation. The power supply names described in this section comprise a superset of a family of
compatible devices. Some members of this family will not include a subset of these power supplies and
their associated device modules. Refer to the 节 4.2, Pin Attributes of the 节 4, Terminal Configuration and
Functions to determine which power supplies are applicable.
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Figure 5-5 and Figure 5-6, describe the device Power Sequencing.
Note 3
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_video, vdda_osc,
vdda_mpu_abe
(12)
vdds_ddr1, ddr1_vref0
VD_CORE BOOT voltage
vdd
VD_DSP BOOT voltage
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_csi, vdda_pcie, vdda_usb3
Note 13
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9,
vddshv10, vddshv11
Note 4
vdda33v_usb1, vdda33v_usb2
Note 5
vddshv8
xi_osc0
Note 7
resetn/porz
Note 8
Note 9
sysboot[15:0]
Valid Config
Note 10
rstoutn
SPRS960_ELCH_04
Figure 5-5. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) vdd must ramp before or at the same time as vdd_dsp.
(4) If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can
be combined with vdds18v.
(5) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(6) vdds and vdda rails must not be combined together.
(7) porz must remain asserted low until all of the following conditions are met:
–
–
–
All device supply rails reach stable operational levels.
xi_osc0 is stable and at a valid frequency.
Minimum of 12P after both of the above conditions are met, where P = 1 / (SYS_CLK1/610), units in ns.
resetn must be high prior to, or rise simultaneous with, porz but not before its power supply, vddshv3, rising.
(8) Setup time: sysboot[15:0] pins must be valid 2P(11) before porz is de-asserted high.
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(9) Hold time: sysboot[15:0] pins must be valid 15P(11) after porz is de-asserted high.
(10) rstoutn will be asserted low when porz is low, and de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3
reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches
during power up.
(11) P = 1/(SYS_CLK1/610) frequency in ns.
(12) ddr1_vref0 may rise coincident with vdds_ddr1 or at a later time. However, it must be valid before porz rising.
(13) vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_usb3 can be energized concurrently or after vdda33v_usb1, vdda33v_usb2.
Note 4
porz
Note 6
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 5
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9,
vddshv10, vddshv11
Note 7
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_csi, vdda_pcie, vdda_usb3
vdd_dsp
vdd
(10)
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_video, vdda_osc,
vdda_mpu_abe
vdds18v, vdds_mlbp, vdds18v_ddr1
xi_osc0
SPRS960_ELCH_05
Figure 5-6. Power-Down Sequencing (8)(9)
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) vdd must ramp after or at the same time as vdd_dsp.
(5) If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can
be combined with vdds18v.
–
vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] is allowed to ramp down at either of the two points shown in the timing diagram
in either 1.8V mode or in 3.3V mode.
–
If vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] ramps down at the later time in the diagram then the board design must
ensure that the vddshv[1, 3-4, 7, 9-11] rail is never higher than 2.0 V above the vdds18v rail.
(6) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
(7) The 1.8V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies
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coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.
(8) The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available
but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC
that is recommended for use with this SoC. The accelerated sequence has porz go low first followed immediately by 3.3V vddshvx
supplies and vddshv8 simultaneously second, 1.8V PHY, 3.3V USB and core supplies simultaneously third, DDR supplies, DDR
references and 1.8V PLL supplies simultaneously fourth and all other 1.8V supplies simultaneously last.
(9) Ramped Down is defined as reaching a voltage level of no more than 0.6V.
(10) ddr1_vref0 may fall coincident with vdds_ddr1, or at a prior time but after porz is asserted low.
Figure 5-7 describes vddshv[1, 3-4, 7, 9-11] Supplies Falling Before vdds18v Supplies Delta.
vddshv1, vddshv3,
vddshv4, vddshv7,
vddshv9, vddshv10,
vddshv11, vddshv8 (Note 2)
vdds18v
Vdelta
(Note1)
SPRS85v_ELCH_06
Figure 5-7. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1, 3-4, 7, 9-11] rails.
5.10.4 Clock Specifications
NOTE
For more information, see Power Reset and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
•
The system clocks, SYS_CLK1 (Mandatory) and SYS_CLK2 (Optional) are the main clock sources of
the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the
wake-up (WKUP) domain is supplied.
Figure 5-8 shows the external input clock sources and the output clocks to peripherals.
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DEVICE
rstoutn
Warm reset output.
Device reset input.
Power ON Reset.
resetn
porz
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xi_osc0
xo_osc0
To quartz (from oscillator output).
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xi_osc1
xo_osc1
clkout1
clkout2
clkout3
To quartz (from oscillator output).
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
xref_clk0
xref_clk1
xref_clk2
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk3
Boot Mode Configuration
sysboot[15:0]
Figure 5-8. Clock Interface
5.10.4.1 Input Clocks / Oscillators
•
The source of the internal system clock (SYS_CLK1) could be either:
–
A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc0 and xo_osc0.
•
The source of the internal system clock (SYS_CLK2) could be either:
–
A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc1 and xo_osc1.
SYS_CLK1 is received directly from oscillator OSC0. For more information about SYS_CLK1 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.10.4.1.1 OSC0 External Crystal
An external crystal is connected to the device pins. Figure 5-9 describes the crystal implementation.
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Device
xo_osc0
vssa_osc0
xi_osc0
Rd
(Optional)
Crystal
Rd
Cf2
Cf1
(Optional)
Figure 5-9. OSC0 Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-9, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-10. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-18 summarizes
the required electrical constraints.
Table 5-18. OSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX UNIT
19.2, 20, 27
MHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
pF
pF
Cf2
ESR(Cf1,Cf2)
Crystal ESR
100
7
Ω
(1)
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz, 20 MHz, 27 MHz
pF
19.2 MHz, 20 MHz
27 MHz
7
5
7
pF
pF
pF
-
ESR = 50 Ω
19.2 MHz, 20 MHz
27 MHz
ESR = 60 Ω
ESR = 80 Ω
ESR = 100 Ω
CO
Crystal shunt capacitance
Not Supported
Not Supported
19.2 MHz, 20 MHz
27 MHz
5
3
pF
-
19.2 MHz, 20 MHz
27 MHz
pF
-
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
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Table 5-18. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX UNIT
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc0)
Frequency accuracy(1), xi_osc0
ppm
Ethernet MII using derived
clock
±100
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-19 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-19. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time
19.2, 20, 27 MHz
tsX
4
5.10.4.1.2 OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK1 clock input to the system. The external connections to support this are shown in Figure 5-11.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Device
xo_osc0
vssa_osc0
xi_osc0
NC
SPRS906_CLK_04
Figure 5-11. 1.8-V LVCMOS-Compatible Clock Input
Table 5-20 summarizes the OSC0 input clock electrical characteristics.
Table 5-20. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
19.2, 20, 27
2.384
MAX
UNIT
MHz
pF
f
Frequency
CIN
IIN
Input capacitance
2.184
4
2.584
10
Input current (3.3V mode)
6
µA
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Table 5-21 details the OSC0 input clock timing requirements.
Table 5-21. OSC0 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
1 /
tc(xiosc0)
CK0
Frequency, xi_osc0
19.2, 20, 27
MHz
0.55 ×
tc(xiosc0)
0.45
tc(xiosc0)
×
CK1
tw(xiosc0) Pulse duration, xi_osc0 low or high
tj(xiosc0) Period jitter(1), xi_osc0
ns
ns
0.01 ×
tc(xiosc0)
tR(xiosc0) Rise time, xi_osc0
tF(xiosc0) Fall time, xi_osc0
5
5
ns
ns
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc0) Frequency accuracy(2), xi_osc0
ppm
Ethernet MII using derived
clock
±100
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
SPRS906_CLK_05
Figure 5-12. xi_osc0 Input Clock
5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.10.4.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. Figure 5-13 describes the crystal implementation.
Device
xo_osc1
xi_osc1
vssa_osc1
Rd
(Optional)
Crystal
Rd
(Optional)
Cf2
Cf1
Figure 5-13. Crystal Implementation
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NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-13, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-14. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-22 summarizes
the required electrical constraints.
Table 5-22. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX
UNIT
MHz
pF
pF
Ω
Range from 19.2 to 32
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
100
7
Cf2
ESR(Cf1,Cf2) Crystal ESR
ESR = 30 Ω 19.2 MHz ≤ fp ≤ 32 MHz
ESR = 40 Ω 19.2 MHz ≤ fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 25 MHz
pF
pF
pF
pF
-
5
7
ESR = 50 Ω 25 MHz < fp ≤ 27 MHz
27 MHz < fp ≤ 32 MHz
5
Not Supported
Not Supported
Not Supported
19.2 MHz ≤ fp ≤ 23 MHz
7
5
pF
pF
-
CO
Crystal shunt capacitance
ESR = 60 Ω 23 MHz < fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 23 MHz
5
3
pF
pF
-
ESR = 80 Ω 23 MHz ≤ fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 20 MHz
ESR = 100 Ω
3
pF
-
20 MHz < fp ≤ 32 MHz
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
mH
fF
CM
Crystal motional capacitance
3.42
Ethernet and MLB not used
±200
±50
Ethernet RGMII and RMII
using derived clock
tj(xiosc1)
Frequency accuracy(1), xi_osc1
ppm
Ethernet MII using derived
clock
±100
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 5-23 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-23. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time
Range from 19.2 to 32
tsX
4
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5.10.4.1.3.2 OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK2 clock input to the system. The external connections to support this are shown in, Figure 5-15.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (vss).
Device
xo_osc1
vssa_osc1
xi_osc1
NC
SPRS906_CLK_07
Figure 5-15. 1.8-V LVCMOS-Compatible Clock Input
Table 5-24 summarizes the OSC1 input clock electrical characteristics.
Table 5-24. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
Frequency
Range from 12 to 38.4
CIN
IIN
Input capacitance
2.819
3.019
6
See(2)
3.219
10
Input current (3.3V mode)
Start-up time(1)
4
µA
tsX
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 5-23, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 5-25 details the OSC1 input clock timing requirements.
Table 5-25. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
1 /
tc(xiosc1)
CK0
Frequency, xi_osc1
Range from 12 to 38.4
MHz
0.45 ×
tc(xiosc1)
0.55 ×
tc(xiosc1)
CK1
tw(xiosc1) Pulse duration, xi_osc1 low or high
tj(xiosc1) Period jitter(1), xi_osc1
ns
ns
0.01 ×
tc(xiosc1)
(3)
tR(xiosc1) Rise time, xi_osc1
tF(xiosc1) Fall time, xi_osc1
5
5
ns
ns
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc1) Frequency accuracy(2), xi_osc1
ppm
Ethernet MII using derived
clock
±100
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(1) Period jitter is meant here as follows:
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period
The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02 × tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
CK0
CK1
CK1
xi_osc1
SPRS906_CLK_08
Figure 5-16. xi_osc1 Input Clock
5.10.4.1.4 RC On-die Oscillator Clock
NOTE
The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is
not accurate 32kHz clock.
The frequency may significantly vary with temperature and silicon characteristics.
For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock
Management.
5.10.4.2 Output Clocks
The device provides three output clocks. Summary of these output clocks are as follows:
•
•
•
clkout1 - Device Clock output 1. Can be used as a system clock for other devices. The source of the
clkout1 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
clkout2 - Device Clock output 2. Can be used as a system clock for other devices. The source of the
clkout2 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
clkout3 - Device Clock output 3. Can be used as a system clock for other devices. The source of the
clkout3 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
For more information about Output Clocks see Device TRM, Chapter: Power, Reset, and Clock
Management.
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5.10.4.3 DPLLs, DLLs
NOTE
For more information, see:
•
Power, Reset, and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
•
Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
•
They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
•
•
•
•
DPLL_MPU: It supplies the MPU subsystem clocking internally.
DPLL_IVA: It feeds the IVA subsystem clocking.
DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
•
•
•
•
•
•
DPLL_ABE: It provides clocks to various modules within the device.
DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
DPLL_DSP: It feeds the DSP Subsystem clocking.
DPLL_GPU: It supplies clock for the GPU Subsystem.
DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
•
•
DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
•
DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
•
•
•
•
DPLL_VIDEO1; (It is controlled from DSS)
DPLL_HDMI; (It is controlled from DSS)
DPLL_DEBUG; (It is controlled from DEBUGSS)
DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
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5.10.4.3.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 5-26 summarizes DPLL type described in Section 5.10.4.3, DPLLs, DLLs Specifications
introduction.
Table 5-26. DPLL Control Type
DPLL NAME
DPLL_ABE
TYPE
CONTROLLED BY PRCM
(1)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-28 (Type B)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-28 (Type B)
Table 5-28 (Type B)
Table 5-28 (Type B)
Table 5-27 (Type A)
Table 5-27 (Type A)
Table 5-27 (Type A)
Yes
(1)
DPLL_CORE
Yes
(2)
DPLL_DEBUGSS
DPLL_DSP
No
(1)
Yes
(1)
DPLL_GMAC
Yes
(2)
DPLL_HDMI
No
(1)
DPLL_IVA
Yes
(1)
DPLL_MPU
Yes
(1)
DPLL_PER
Yes
(1)
APLL_PCIE
Yes
(1)
DPLL_PCIE_REF
DPLL_USB
Yes
(1)
Yes
(2)
DPLL_USB_OTG_SS
DPLL_VIDEO1
No
(2)
No
(1)
DPLL_DDR
Yes
(1)
DPLL_GPU
Yes
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
Table 5-27 and Table 5-28 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
Table 5-27. DPLL Type A Characteristics
NAME
finput
DESCRIPTION
MIN
0.032
0.15
10
TYP
MAX
52
UNIT
MHz
MHz
MHz
COMMENTS
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
FINP
finternal
52
REFCLK
FINPHIF
fCLKINPHIF
1400
Bypass mode: fCLKOUT
=
fCLKINPULOW
CLKINPULOW input frequency
CLKOUT output frequency
0.001
600
MHz
MHz
fCLKINPULOW / (M1 + 1) if
ulowclken = 1
(6)
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)
(2)
fCLKOUT
20
1800
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Table 5-27. DPLL Type A Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
COMMENTS
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
(1)
(2)
fCLKOUTx2
CLKOUTx2 output frequency
40
2200
(3)
(4)
20
1400
2200
FINPHIF / M3 if clkinphifsel = 1
fCLKOUTHIF
CLKOUTHIF output frequency
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
(3)
(4)
40
DCOCLKLDO output
frequency
2 × [M / (N + 1)] × FINP (in
locked condition)
fCLKDCOLDO
tlock
40
2800
MHz
µs
6 + 350 ×
REFCLK
Frequency lock time
Phase lock time
6 + 500 ×
REFCLK
plock
µs
Relock time—Frequency
lock(5) (LP relock time from
bypass)
Relock time—Phase lock(5)
(LP relock time from bypass)
6 + 70 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
trelock-L
prelock-L
trelock-F
prelock-F
µs
µs
µs
µs
6 + 120 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
Relock time—Frequency
lock(5) (fast relock time from
bypass)
Relock time—Phase lock(5)
(fast relock time from bypass)
3.55 + 70 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
3.55 + 120 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
Table 5-28. DPLL Type B Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
finput
CLKINP input clock frequency
0.62
60
MHz
FINP
REFCLK internal reference
clock frequency
finternal
0.62
2.5
MHz
[1 / (N + 1)] × FINP
Bypass mode: fCLKOUT
=
CLKINPULOW bypass input
clock frequency
fCLKINPULOW
0.001
600
MHz
fCLKINPULOW / (M1 + 1) If
(4)
ulowclken = 1
CLKOUTLDO output clock
frequency
M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
fCLKLDOOUT
fCLKOUT
fCLKDCOLDO
20
2500
MHz
MHz
CLKOUT output clock
frequency
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
20
1450
(5)
(5)
750
1500
MHz
MHz
Internal oscillator (DCO) output
clock frequency
[M / (N + 1)] × FINP (in locked
condition)
(5)
(5)
1250
2500
CLKOUTLDO period jitter
CLKOUT period jitter
The period jitter at the output
clocks is ± 2.5% peak to peak
tJ
–2.5%
2.5%
CLKDCOLDO period jitter
350 ×
REFCLKs
tlock
plock
Frequency lock time
µs
µs
µs
500 ×
REFCLKs
Phase lock time
Relock time—Frequency lock(3)
(LP relock time from bypass)
9 + 30 ×
REFCLKs
trelock-L
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Table 5-28. DPLL Type B Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
Relock time—Phase lock(3) (LP
relock time from bypass)
9 + 125 ×
REFCLKs
prelock-L
µs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
5.10.4.3.2 DLL Characteristics
Table 5-29 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
Table 5-29. DLL Characteristics
NAME
finput
DESCRIPTION
Input clock frequency (EMIF_DLL_FCLK)
MIN
TYP
MAX
333
50k
UNIT
MHz
tlock
Lock time
cycles
cycles
trelock
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
5.10.5 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
5.10.6 Peripherals
5.10.6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
5.10.6.2 Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. 表 5-30 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
表 5-30. Modes Summary
Virtual or Manual IO Mode Name
DPI Video Output
Data Manual Timing Mode
No Virtual or Manual IO Timing Mode Required
DSS_VIRTUAL1
DPI3 Video Output Default Timings - Rising-edge Clock Reference
DPI3 Video Output Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
VOUT2_IOSET1_MANUAL4
VOUT2_IOSET1_MANUAL5
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET1 MANUAL4 Timings
DPI2 Video Output IOSET1 MANUAL5 Timings
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表 5-30. Modes Summary (continued)
Virtual or Manual IO Mode Name
VOUT3_MANUAL1
Data Manual Timing Mode
DPI3 Video Output Alternate Timings
DPI3 Video Output MANUAL4 Timings
DPI3 Video Output MANUAL5 Timings
VOUT3_MANUAL4
VOUT3_MANUAL5
GPMC
No Virtual or Manual IO Timing Mode Required
GPMC_VIRTUAL1
GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP2_VIRTUAL1_SYNC_RX_80M
MCASP2_VIRTUAL2_ASYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL4_ASYNC_RX_80M
No Virtual or Manual IO Timing Mode Required
MCASP3_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP4_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP5_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP6_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP7_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP8_VIRTUAL1_SYNC_RX
eMMC/SD/SDIO
McASP1 Asynchronous and Synchronous Transmit Timings
See 表 5-78
See 表 5-78
McASP2 Asynchronous and Synchronous Transmit Timings
See 表 5-79
See 表 5-79
See 表 5-79
See 表 5-79
McASP3 Synchronous Transmit Timings
See 表 5-80
McASP4 Synchronous Transmit Timings
See 表 5-81
McASP5 Synchronous Transmit Timings
See 表 5-82
McASP6 Synchronous Transmit Timings
See 表 5-83
McASP7 Synchronous Transmit Timings
See 表 5-84
McASP8 Synchronous Transmit Timings
See 表 5-85
No Virtual or Manual IO Timing Mode Required
MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12
(Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and
Pad Loopback) Timings
MMC1_VIRTUAL1
MMC1 SDR50 (Pad Loopback) Timings
MMC1 DS (Internal Loopback) Timings
MMC1 SDR50 (Internal Loopback) Timings
MMC1 DDR50 (Internal Loopback) Timings
MMC1 DDR50 (Pad Loopback) Timings
MMC1 SDR104 Timings
MMC1_VIRTUAL4
MMC1_VIRTUAL5
MMC1_VIRTUAL6
MMC1_MANUAL1
MMC1_MANUAL2
No Virtual or Manual IO Timing Mode Required
MMC2_VIRTUAL2
MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL1
MMC2_MANUAL2
MMC2 DDR (Internal Loopback Manual) Timings
MMC2 HS200 Timings
MMC2_MANUAL3
No Virtual or Manual IO Timing Mode Required
MMC3_MANUAL1
MMC3 DS, SDR12, HS, SDR25 Timings
MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required
QSPI
MMC4 DS, SDR12, HS, SDR25 Timings
No Virtual or Manual IO Timing Mode Required
QSPI1_MANUAL1
QSPI Mode 3 Timings
QSPI Mode 0 Timings
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表 5-30. Modes Summary (continued)
Virtual or Manual IO Mode Name
GMAC
Data Manual Timing Mode
No Virtual or Manual IO Timing Mode Required
GMAC_RGMII0_MANUAL1
GMAC_RGMII1_MANUAL1
GMAC_RMII0_MANUAL1
GMAC_RMII1_MANUAL1
VIP
GMAC MII0/1 Timings
GMAC RGMII0 with Transmit Clock Internal Delay Enabled
GMAC RGMII1 with Transmit Clock Internal Delay Enabled
GMAC RMII0 Timings
GMAC RMII1 Timings
VIP_MANUAL3
VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL4
VIP_MANUAL5
VIP_MANUAL6
VIP_MANUAL7
VIN1A (IOSET2) and VIN2B (IOSET1/10) Rise-Edge Capture Mode Timings
VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIP_MANUAL9
VIP_MANUAL10
VIN2B (IOSET2/11) Rise-Edge Capture Mode Timings
VIN2B (IOSET2/11) Fall-Edge Capture Mode Timings
VIP_MANUAL11
VIP_MANUAL12
VIN1A (IOSET2) and VIN2B (IOSET1/10) Fall-Edge Capture Mode Timings
VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL14
VIP_MANUAL15
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
VIP_MANUAL16
PRU-ICSS
No Virtual or Manual IO Timing Mode Required
PR1_PRU1_DIR_IN_MANUAL
PR1_PRU1_DIR_OUT_MANUAL
PR1_PRU1_PAR_CAP_MANUAL
PR2_PRU0_DIR_IN_MANUAL2
PR2_PRU0_DIR_OUT_MANUAL2
PR2_PRU1_DIR_IN_MANUAL1
PR2_PRU1_DIR_IN_MANUAL2
PR2_PRU1_DIR_OUT_MANUAL1
PR2_PRU1_DIR_OUT_MANUAL2
PR2_PRU0_PAR_CAP_MANUAL2
PR2_PRU1_PAR_CAP_MANUAL1
PR2_PRU1_PAR_CAP_MANUAL2
All PRU_ICSS Modes not covered below
PRU-ICSS1 PRU1 Direct Input Mode Timings
PRU-ICSS1 PRU1 Direct Output Mode Timings
PRU-ICSS1 PRU1 Parallel Capture Mode Timings
PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings
PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings
PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings
PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings
PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings
PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings
PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode Timings
PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode Timings
PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, PCIe, DCAN, GPIO, KBD, PWM, JTAG, TPIU, SDMA, INTC
No Virtual or Manual IO Timing Mode Required
All Modes
5.10.6.3 VIP
The Device includes 1 Video Input Port (VIP).
表 5-31, 图 5-17 and 图 5-18 present timings and switching characteristics of the VIP.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in 表 5-32.
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表 5-31. Timing Requirements for VIP (3)(4)(5)
NO.
V1
PARAMETER
DESCRIPTION
Cycle time, vinx_clki (3) (5)
MIN
6.06 (2)
MAX
UNIT
ns
tc(CLK)
V2
tw(CLKH)
Pulse duration, vinx_clki high (3) (5)
0.45 × P
ns
(2)
V3
V4
V6
tw(CLKL)
Pulse duration, vinx_clki low (3) (5)
0.45 × P
ns
ns
ns
(2)
tsu(CTL/DATA-CLK)
th(CLK-CTL/DATA)
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
3.11 (2)
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5)
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5)
-0.05 (2)
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
V3
V2
V1
vinx_clki
SPRS906_TIMING_VIP_01
图 5-17. Video Input Ports clock signal
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
图 5-18. Video Input Ports timings
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In 表 5-32 and 表 5-33 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.
表 5-32. VIN1 IOSETs
SIGNALS
IOSET2
IOSET6 (1)
BALL MUX
IOSET7 (1)
BALL MUX
IOSET8
IOSET9
IOSET10
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin1a
vin1a_clk0
vin1a_hsync0
vin1a_vsync0
vin1a_fld0
vin1a_de0
vin1a_d0
G3
K4
H1
L3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Y5
9
9
9
J24
B14
D14
C16
C17
J25
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
J24
B14
D14
C16
C17
B23
B22
A23
A22
B21
A21
D19
E19
F16
E16
E17
A19
B18
B16
B17
A18
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
AA4
AB1
J2
Y6
AA1
Y3
9
9
9
9
9
9
9
9
9
F1
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
C3
C4
A3
B4
M1
M2
L2
vin1a_d1
B22
A23
A22
B21
A21
D19
E19
F16
E16
E17
A19
B18
B16
B17
A18
vin1a_d2
W2
AA3
AA2
Y4
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
Y1
vin1a_d7
Y2
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
L1
K3
K2
J1
K1
172
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表 5-32. VIN1 IOSETs (continued)
SIGNALS
IOSET2
BALL
IOSET6 (1)
IOSET7 (1)
IOSET8
IOSET9
BALL MUX
IOSET10
BALL MUX
MUX
BALL
MUX
BALL
MUX
vin1b
BALL
MUX
vin1b_clk1
vin1b_hsync1
vin1b_vsync1
vin1b_fld1
vin1b_de1
vin1b_d0
L5
P3
R2
N4
P4
L6
5
5
5
5
5
5
5
5
5
5
5
5
5
J2
K4
H1
G1
L3
M1
M2
L2
L1
K3
K2
J1
6
6
6
6
6
6
6
6
6
6
6
6
6
vin1b_d1
N5
N6
T4
T5
N2
P2
N1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
K1
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad
Configuration Registers.
表 5-33. VIN2 IOSETs
SIGNALS
IOSET1
BALL MUX
IOSET2
BALL MUX
IOSET4
IOSET5
BALL MUX
vin2a
IOSET6
IOSET7 (1)
BALL MUX
IOSET8 (1)
BALL MUX
IOSET9 (1)
BALL MUX
BALL
MUX
BALL
MUX
vin2a_clk0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_de0
vin2a_d0
D8
E8
B8
C7
B7
C8
B9
A7
A9
A8
0
0
0
0
0
0
0
0
0
0
D8
E8
B8
B7
0
0
0
1
L5
P3
R2
N4
P4
L6
N5
N6
T4
T5
4
4
4
4
4
4
4
4
4
4
C8
B9
A7
A9
A8
0
0
0
0
0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
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IOSET9 (1)
表 5-33. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
IOSET5
IOSET6
IOSET7 (1)
IOSET8 (1)
BALL
MUX
BALL
MUX
BALL
MUX
0
BALL
MUX
0
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin2a_d5
vin2a_d6
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
N2
P2
N1
P1
N3
R1
P5
4
4
4
4
4
4
4
0
0
vin2a_d7
0
0
vin2a_d8
0
0
vin2a_d9
0
0
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vin2b
vin2b_clk1
vin2b_hsync1
vin2b_vsync1
vin2b_fld1
vin2b_de1
vin2b_d0
L4
B6
A6
H6
H2
A4
E7
D6
C5
B5
D7
C6
6
6
6
6
6
6
6
6
6
6
6
6
H6
B6
A6
4
6
6
C7
E8
B8
2
3
3
C7
E8
B8
B7
2
3
3
2
AB1
Y5
4
4
4
Y6
H2
A4
E7
D6
C5
B5
D7
C6
6
6
6
6
6
6
6
6
B7
3
2
2
2
2
2
2
2
AA4
AA1
Y3
4
4
4
4
4
4
4
4
D13
C13
E13
B13
F11
E11
A13
D13
C13
E13
B13
F11
E11
A13
2
2
2
2
2
2
2
vin2b_d1
vin2b_d2
W2
AA3
AA2
Y4
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
Y1
174
Specifications
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表 5-33. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
BALL MUX
IOSET5
BALL MUX
IOSET6
BALL MUX
IOSET7 (1)
IOSET8 (1)
IOSET9 (1)
BALL
A5
MUX
BALL
A5
MUX
BALL
A12
MUX
BALL
A12
MUX
BALL
Y2
MUX
vin2b_d7
6
6
2
2
4
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad
Configuration Registers.
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the
Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module
Chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-34, Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.
表 5-34 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-34. Manual Functions Mapping for VIN2A (IOSET4/5/6)
BALL
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
0
1
4
P5
RMII_MHZ_50_CL
K
2616
1379
2798
1294
CFG_RMII_MHZ_50_CLK_IN
-
-
vin2a_d11
L6
L5
mdio_d
2558
998
1105
463
2790
1029
2896
2844
2856
2804
2801
2807
2835
2831
2764
2843
2816
954
431
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d0
vin2a_clk0
vin2a_d5
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
2658
2658
2638
2641
2641
2644
2638
2672
2604
2683
2563
862
651
1628
1123
1737
1676
1828
1454
1663
1442
1598
1483
1518
888
vin2a_d6
vin2a_fld0
vin2a_d9
1702
1652
1790
1396
1640
1417
1600
1344
vin2a_d8
vin2a_d7
vin2a_d3
vin2a_d4
vin2a_d10
vin2a_vsync0
vin2a_hsync0
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表 5-34. Manual Functions Mapping for VIN2A (IOSET4/5/6) (continued)
BALL
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
0
1
4
P4
N5
rgmii0_txd3
uart3_rxd
uart3_txd
vin2a_clk0
vin2a_d0
2717
2445
2650
0
1461
1145
1197
0
2913
2743
2842
0
1310
923
1080
0
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
CFG_VIN2A_CLK0_IN
CFG_VIN2A_D0_IN
CFG_VIN2A_D1_IN
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D2_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_D3_IN
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
CFG_VIN2A_VSYNC0_IN
-
-
vin2a_de0
-
-
vin2a_d1
N6
-
-
vin2a_d2
D8
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
1812
1701
1720
1622
1350
1613
1149
1530
1512
1293
2140
2041
1675
1972
1957
2011
1962
1457
1535
1676
1513
1616
1286
1544
1732
1461
1877
1566
102
439
215
0
1936
2229
2031
1702
1819
1476
1701
2021
2044
1839
2494
1699
1736
2412
2391
2446
2395
1943
1601
2052
1571
1855
1224
1373
1949
1983
1943
1612
0
-
B9
vin2a_d1
10
0
-
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
A7
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
-
0
-
412
147
516
450
449
488
371
275
35
0
-
260
0
-
-
0
-
11
5
-
-
0
-
611
0
-
-
B13
E13
C13
D13
A9
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
441
556
433
523
361
0
88
161
102
145
0
-
-
-
-
-
A8
vin2a_d4
0
-
A11
F10
A10
B10
E10
B7
vin2a_d5
271
0
0
-
vin2a_d6
0
-
vin2a_d7
141
437
265
208
562
0
0
-
vin2a_d8
618
509
0
-
vin2a_d9
-
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
C7
151
0
-
-
-
E8
B8
0
0
176
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Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-35, Manual Functions Mapping for VIN2B (IOSET7/8/9) for a definition of the Manual modes.
表 5-35 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-35. Manual Functions Mapping for VIN2B (IOSET7/8/9)
BALL
BALL NAME
VIP_MANUAL4
VIP_MANUAL6
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
2
3
4
Y5
Y6
gpio6_10
gpio6_11
2829
2648
2794
2789
2689
2605
2616
2760
2757
2688
2638
995
884
1033
1074
1162
1180
1219
703
1235
880
1177
1165
182
0
3009
2890
2997
2959
2897
2891
2947
2931
2979
2894
2894
1202
1739
1568
2217
2029
2202
2313
2334
2288
2048
0
892
1096
1089
1210
1269
1219
590
1342
891
1262
1187
107
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
-
-
vin2b_hsync1
-
-
vin2b_vsync1
Y2
mmc3_clk
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
CFG_VIN2A_VSYNC0_IN
-
-
vin2b_d7
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
-
-
vin2b_d6
Y4
-
-
vin2b_d5
AA2
AA3
W2
Y3
-
-
vin2b_d4
-
-
vin2b_d3
-
-
vin2b_d2
-
-
vin2b_d1
AA1
AA4
AB1
A12
A13
E11
F11
B13
E13
C13
D13
B7
-
-
vin2b_d0
-
-
vin2b_de1
-
-
vin2b_clk1
1423
1253
2080
1849
1881
1917
1955
1899
1568
0
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
vin2b_fld1
vin2b_clk1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
-
0
0
-
0
0
-
50
0
-
167
79
0
-
0
-
145
261
0
0
-
0
vin2b_de1
-
C7
0
E8
1793
1382
0
2011
1632
0
vin2b_hsync1
vin2b_vsync1
B8
0
0
-
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Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-36, Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10) for a definition of the
Manual modes.
表 5-36 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-36. Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10)
BALL
BALL NAME
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
6
M1
M2
J2
gpmc_a0
gpmc_a1
3080
2958
3073
3014
1385
3041
859
1792
1890
1653
1784
0
3376
3249
3388
3290
1246
3322
720
1632
1749
1433
1693
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A19_IN
CFG_GPMC_A2_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
CFG_GPMC_A8_IN
CFG_GPMC_A9_IN
CFG_GPMC_AD0_IN
CFG_GPMC_AD1_IN
CFG_GPMC_AD10_IN
CFG_GPMC_AD11_IN
CFG_GPMC_AD12_IN
CFG_GPMC_AD13_IN
vin1a_d16
vin1a_d17
vin1a_de0
vin1a_fld0
-
-
-
gpmc_a10
gpmc_a11
gpmc_a19
gpmc_a2
-
L3
A4
L2
E7
D6
C5
B5
D7
C6
A5
B6
L1
K3
K2
J1
-
vin2b_d0
1960
0
1850
0
vin1a_d18
-
-
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a3
vin2b_d1
1465
1210
1111
1137
1402
1298
934
0
1334
1064
954
0
-
vin2b_d2
0
0
-
vin2b_d3
0
0
-
vin2b_d4
0
1051
1283
1153
870
0
-
vin2b_d5
0
0
-
vin2b_d6
0
0
-
vin2b_d7
0
0
-
vin2b_hsync1
3019
3063
3021
3062
3260
3033
2991
2907
2858
2920
2719
2845
2765
2145
1981
1954
1716
1889
1702
1905
1342
1321
1384
1310
1135
1225
3296
3357
3304
3348
3583
3328
3281
3181
3132
3223
3019
3160
3045
2050
1829
1840
1592
1631
1547
1766
1255
1234
1204
1198
917
1119
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_hsync0
vin1a_vsync0
vin1a_d0
vin1a_d1
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
-
-
-
-
-
-
-
-
-
-
-
-
-
gpmc_a4
gpmc_a5
gpmc_a6
K1
K4
H1
F1
E2
A2
B3
C3
C4
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
178
Specifications
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表 5-36. Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10) (continued)
BALL
BALL NAME
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
6
A3
B4
E1
C1
D1
D2
B1
B2
C2
D3
H2
H6
L4
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ben0
gpmc_ben1
gpmc_clk
2845
2766
2951
2825
2927
2923
2958
2900
2845
2779
1555
1501
0
1150
1453
1296
1154
1245
1251
1342
1244
1585
1343
0
3153
3044
3226
3121
3246
3217
3238
3174
3125
3086
1425
1397
0
952
1355
1209
997
1014
1098
1239
1157
1482
1223
0
CFG_GPMC_AD14_IN
CFG_GPMC_AD15_IN
CFG_GPMC_AD2_IN
CFG_GPMC_AD3_IN
CFG_GPMC_AD4_IN
CFG_GPMC_AD5_IN
CFG_GPMC_AD6_IN
CFG_GPMC_AD7_IN
CFG_GPMC_AD8_IN
CFG_GPMC_AD9_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CLK_IN
CFG_GPMC_CS1_IN
CFG_GPMC_CS3_IN
vin1a_d14
vin1a_d15
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
-
-
-
-
-
-
-
-
-
-
-
vin2b_de1
vin2b_fld1
vin2b_clk1
vin2b_vsync1
-
0
0
-
0
0
-
A6
G3
gpmc_cs1
gpmc_cs3
1192
1324
0
1102
1466
0
-
374
353
vin1a_clk0
Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-37, Manual Functions Mapping for VIN1B (IOSET6/7) for a definition of the Manual modes.
表 5-37 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-37. Manual Functions Mapping for VIN1B (IOSET6/7)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
-
-
-
-
-
-
-
-
-
6
M1
M2
J2
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
1873
1629
0
702
772
0
2202
2057
0
441
413
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A12_IN
CFG_GPMC_A2_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
vin1b_d0
vin1b_d1
vin1b_clk1
vin1b_de1
vin1b_fld1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
L3
G1
L2
L1
K3
K2
1851
2009
1734
1757
1794
1726
1011
601
898
1076
893
853
2126
2289
2131
2106
2164
2120
856
327
573
812
559
523
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表 5-37. Manual Functions Mapping for VIN1B (IOSET6/7) (continued)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
612
A_DELAY (ps)
G_DELAY (ps)
338
5
-
6
J1
K1
K4
H1
L6
L5
N2
P2
N4
N1
T4
T5
R2
P3
P4
N5
N6
gpmc_a6
gpmc_a7
1792
2117
1758
1705
1945
255
2153
2389
2140
2067
2265
337
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
vin1b_d6
610
304
-
vin1b_d7
gpmc_a8
653
308
CFG_GPMC_A8_IN
-
vin1b_hsync1
gpmc_a9
899
646
CFG_GPMC_A9_IN
-
vin1b_vsync1
mdio_d
671
414
CFG_MDIO_D_IN
vin1b_d0
vin1b_clk1
vin1b_d5
vin1b_d6
vin1b_fld1
vin1b_d7
vin1b_d3
vin1b_d4
vin1b_vsync1
vin1b_hsync1
vin1b_de1
vin1b_d1
vin1b_d2
-
-
-
-
-
-
-
-
-
-
-
-
-
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
uart3_txd
119
0
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
2057
2121
2070
2092
2088
2143
2078
1928
2255
1829
2030
909
2341
2323
2336
2306
2328
2312
2324
2306
2401
2220
2324
646
1139
655
988
340
1357
1205
1383
1189
1125
971
1216
1079
1311
1065
763
846
747
400
837
568
Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-38, Manual Functions Mapping for VIN2B (IOSET2/11) for a definition of the Manual modes.
表 5-38 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-38. Manual Functions Mapping for VIN2B (IOSET2/11)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
4
-
-
-
-
-
-
-
6
A4
E7
D6
C5
B5
D7
C6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
1600
1440
1602
1395
1571
1463
1426
943
621
2023
1875
2021
1822
2045
1893
1842
477
136
604
519
200
396
732
CFG_GPMC_A19_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
1066
983
716
832
1166
180
Specifications
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表 5-38. Manual Functions Mapping for VIN2B (IOSET2/11) (continued)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
4
6
A5
B6
H2
H6
A6
gpmc_a26
gpmc_a27
gpmc_ben0
gpmc_ben1
gpmc_cs1
1362
1283
1978
0
1094
809
780
0
1797
1760
2327
0
584
338
389
0
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CS1_IN
-
vin2b_d7
vin2b_hsync1
vin2b_de1
-
-
-
vin2b_clk1
-
1411
982
1857
536
vin2b_vsync1
Manual IO Timings Modes must be used to ensure some IO timings for VIP1. See 表 5-30, Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-39, Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.
表 5-39 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-39. Manual Functions Mapping for VIN1A (IOSET8/9/10)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
7
9
Y5
gpio6_10
2131
3720
2447
3061
3113
2803
3292
2854
2813
2471
2815
2965
3082
2898
2413
2478
2806
2861
1583
2198
2170
4106
3042
3380
3396
3362
3357
3145
3229
3053
3225
3427
3253
3368
2972
3062
3175
2936
1878
2180
2448
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
-
vin1a_clk0
Y6
gpio6_11
2732
0
-
vin1a_de0
C16
D14
B14
B16
B18
A19
E17
E16
F16
A18
B17
C17
E19
A21
B21
D19
A22
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_axr8
mcasp1_axr9
mcasp1_fsx
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR15_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP1_FSX_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
CFG_MCASP3_ACLKX_IN
vin1a_fld0
vin1a_vsync0
vin1a_hsync0
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d15
vin1a_d14
vin1a_de0
vin1a_d7
vin1a_d5
vin1a_d4
vin1a_d6
vin1a_d3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
292
304
0
0
0
0
546
320
196
0
0
0
0
0
201
83
0
0
440
139
0
0
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
0
0
0
0
242
599
0
78
0
mcasp3_aclkx
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表 5-39. Manual Functions Mapping for VIN1A (IOSET8/9/10) (continued)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
0
A_DELAY (ps)
G_DELAY (ps)
375
7
9
-
B22
B23
A23
Y2
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
2873
1625
2792
3907
3892
3786
3673
3818
3902
3905
3807
3724
3775
1971
0
3109
2072
3146
4260
4242
4156
4053
4209
4259
4259
4167
4123
4159
2472
0
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_XREF_CLK0_IN
CFG_XREF_CLK1_IN
vin1a_d1
1400
0
1023
257
vin1a_d0
-
vin1a_d2
-
2744
2768
2765
2961
2447
2903
2622
2824
2818
2481
0
2450
2470
2522
2667
2096
2672
2342
2595
2491
2161
0
-
vin1a_d7
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
vin1a_hsync0
vin1a_vsync0
-
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
xref_clk0
-
Y4
-
AA2
AA3
W2
Y3
-
-
-
-
AA1
AA4
AB1
J25
J24
-
-
-
vin1a_d0
vin1a_clk0
xref_clk1
192
603
-
182
Specifications
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5.10.6.4 DSS
Two Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 2 and DPI
Video Output 3.
注
The DPI Video Output i (i = 2, 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
注
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-44.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
表 5-40, 表 5-41 and 图 5-19 assume testing over the recommended operating conditions and electrical
characteristic conditions.
表 5-40. DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2)
NO.
D1
PARAMETER
tc(clk)
tw(clkL)
DESCRIPTION
MODE
MIN
11.76
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
P × 0.5-
(1)
1
D3
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P × 0.5-
ns
(1)
1
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表 5-40. DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
2.5
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
2.5
ns
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
-2.5
-2.5
2.5
2.5
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx
Processors for Use With Video Display SerDes for additional guidance.
表 5-41. DPI Video Output i (i = 2, 3) Alternate Switching Characteristics(2)
NO.
D1
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.06
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
tw(clkL)
P × 0.5-
(1)
1
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P × 0.5-
ns
(1)
1
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync, vouti_de,
and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync, vouti_de,
and vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx
Processors for Use With Video Display SerDes for additional guidance.
表 5-42. DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2)
NO.
D1
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.06 (3)
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
tw(clkL)
P*0.5-1
(1)
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
(1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI1
DPI1
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
2.85
5.56
ns
184
Specifications
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表 5-42. DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
2.85
5.56
ns
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx
Processors for Use With Video Display SerDes for additional guidance.
表 5-43. DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics (2)
NO.
D1
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.06 (3)
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
tw(clkL)
P*0.5-1
(1)
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
(1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI1
DPI1
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note Optimizing DRA7xx and TDA2xx
Processors for Use With Video Display SerDes for additional guidance.
D2
D3
D1
D6
D4
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_clk
vouti_clk
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
even
vouti_fld
odd
SWPS049-018
图 5-19. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the Device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the Device TRM.
In 表 5-44 are presented the specific groupings of signals (IOSET) for use with VOUT2.
表 5-44. VOUT2 IOSETs
SIGNALS
IOSET1
BALL
C8
MUX
4
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
B9
4
A7
4
A9
4
A8
4
A11
F10
A10
B10
E10
D10
C10
B11
4
4
4
4
4
4
4
4
186
Specifications
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表 5-44. VOUT2 IOSETs (continued)
SIGNALS
IOSET1
BALL
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
B8
MUX
4
vout2_d10
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_vsync
vout2_hsync
vout2_clk
vout2_fld
vout2_de
4
4
4
4
4
4
4
4
4
4
4
E8
4
C7
4
D8
4
B7
4
In are presented the specific groupings of signals (IOSET) for use with VOUT3.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to ensure some IO timings for VOUT3. See 表 5-30, Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-45, Virtual
Functions Mapping for VOUT3 for a definition of the Virtual modes.
表 5-45 presents the values for DELAYMODE bitfield.
表 5-45. Virtual Functions Mapping for DSS VOUT3
BALL
BALL NAME
Delay Mode Value
MUXMODE
3
DSS_VIRTUAL1
B4
K4
D1
F1
C4
L2
gpmc_ad15
gpmc_a8
14
15
14
14
14
15
14
15
15
14
15
15
15
vout3_d15
vout3_hsync
vout3_d4
vout3_d0
vout3_d13
vout3_d18
vout3_d1
vout3_d20
vout3_d22
vout3_d14
vout3_d17
vout3_clk
vout3_vsync
gpmc_ad4
gpmc_ad0
gpmc_ad13
gpmc_a2
E2
K3
J1
gpmc_ad1
gpmc_a4
gpmc_a6
A3
M2
G3
H1
gpmc_ad14
gpmc_a1
gpmc_cs3
gpmc_a9
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Specifications
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表 5-45. Virtual Functions Mapping for DSS VOUT3 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
DSS_VIRTUAL1
3
B3
B1
E1
C1
K1
L1
gpmc_ad11
gpmc_ad6
gpmc_ad2
gpmc_ad3
gpmc_a7
14
14
14
14
15
15
14
14
15
15
14
14
15
14
15
14
vout3_d11
vout3_d6
vout3_d2
vout3_d3
vout3_d23
vout3_d19
vout3_d10
vout3_d7
vout3_de
vout3_d21
vout3_d8
vout3_d5
vout3_d16
vout3_d12
vout3_fld
vout3_d9
gpmc_a3
A2
B2
J2
gpmc_ad10
gpmc_ad7
gpmc_a10
gpmc_a5
K2
C2
D2
M1
C3
L3
gpmc_ad8
gpmc_ad5
gpmc_a0
gpmc_ad12
gpmc_a11
gpmc_ad9
D3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for VOUT2. See 表 5-30, Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-46, Manual
Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.
表 5-46 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
188
Specifications
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-46. Manual Functions Mapping for DSS VOUT2 IOSET1
BALL
BALL
NAME
VOUT2_IOSET1
_MANUAL1
VOUT2_IOSET1
_MANUAL2
VOUT2_IOSET1
_MANUAL3
VOUT2_IOSET1
_MANUAL4
VOUT2_IOSET1
_MANUAL5
CFG REGISTER
MUXMODE
4
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2571
2124
2103
2091
2142
2920
2776
2904
2670
2814
3002
1893
1698
2193
1736
1636
1628
1538
1997
2528
2038
1746
2213
2268
2170
2102
0
(ps)
(ps)
1059
589
568
557
608
1816
1872
1769
1665
1908
1897
358
163
658
202
101
93
(ps)
(ps)
1025
577
557
545
596
1783
1838
1757
1632
1878
1865
347
151
646
190
89
(ps)
(ps)
4110
3613
3442
3430
3481
3943
3799
3869
3792
3837
4024
3432
3237
3531
3075
3074
3266
2968
3335
3867
3577
3285
3552
3607
3509
3841
0
(ps)
(ps)
4980
4483
4312
4200
4251
4713
4669
4739
4662
4707
4894
4302
4007
4401
3945
3944
4036
3838
4205
4537
4347
4055
4272
4277
4379
4611
0
(ps)
D8
C8
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_fld0
0
0
0
0
0
CFG_VIN2A_CLK0_OUT
CFG_VIN2A_D0_OUT
CFG_VIN2A_D1_OUT
CFG_VIN2A_D10_OUT
CFG_VIN2A_D11_OUT
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
CFG_VIN2A_D18_OUT
CFG_VIN2A_D19_OUT
CFG_VIN2A_D2_OUT
CFG_VIN2A_D20_OUT
CFG_VIN2A_D21_OUT
CFG_VIN2A_D22_OUT
CFG_VIN2A_D23_OUT
CFG_VIN2A_D3_OUT
CFG_VIN2A_D4_OUT
CFG_VIN2A_D5_OUT
CFG_VIN2A_D6_OUT
CFG_VIN2A_D7_OUT
CFG_VIN2A_D8_OUT
CFG_VIN2A_D9_OUT
CFG_VIN2A_DE0_OUT
CFG_VIN2A_FLD0_OUT
vout2_fld
vout2_d23
vout2_d22
vout2_d13
vout2_d12
vout2_d11
vout2_d10
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d21
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_de
vout2_clk
0
0
0
0
0
B9
0
0
0
0
0
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
A7
0
0
0
0
0
0
0
0
0
0
385
322
0
255
192
0
276
213
0
601
538
174
473
371
415
0
601
538
174
473
371
415
0
257
155
199
0
127
31
69
0
148
43
89
0
0
0
0
0
0
0
0
0
0
0
B13
E13
C13
D13
A9
0
0
0
0
0
0
0
0
0
0
0
0
81
0
0
0
0
0
0
0
0
0
0
0
462
993
503
211
678
733
635
568
1398
974
0
450
982
492
200
666
721
623
556
1385
936
0
0
0
A8
0
0
0
0
0
A11
F10
A10
B10
E10
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C7
983
0
1185
0
1202
0
994
0
994
0
E8
vin2a_hsy
nc0
2482
4021
4891
CFG_VIN2A_HSYNC0_ vout2_hsync
OUT
B8
vin2a_vsy
nc0
2296
0
784
0
750
0
3935
0
4805
0
CFG_VIN2A_VSYNC0_O vout2_vsync
UT
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190
Specifications
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
Manual IO Timings Modes must be used to ensure some IO timings for VOUT3. See 表 5-30, Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-47, Manual
Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
表 5-47 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-47. Manual Functions Mapping for DSS VOUT3
BALL
BALL
NAME
VOUT3_MANUAL1
VOUT3_MANUAL4
VOUT3_MANUAL5
CFG REGISTER
MUXMODE
3
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2395
2412
2473
2906
2360
2391
2626
2338
2374
2432
3155
2309
2360
2420
2235
2253
1949
2318
2123
2195
2617
2350
2324
2371
2231
2440
2479
2355
0
(ps)
0
(ps)
3909
3957
3980
4253
3873
4112
4336
3840
3913
3947
4309
3842
3652
3762
3456
3584
3589
3547
3302
3532
3859
3590
3534
3609
3416
3661
3714
3593
0
(ps)
0
(ps)
4779
4827
4850
5123
4743
4982
5206
4710
4783
4817
5179
4712
4522
4632
4326
4454
4459
4417
4172
4402
4729
4460
4404
4479
4286
4531
4584
4463
0
(ps)
0
M1
M2
J2
gpmc_a0
gpmc_a1
CFG_GPMC_A0_OUT
CFG_GPMC_A1_OUT
CFG_GPMC_A10_OUT
CFG_GPMC_A11_OUT
CFG_GPMC_A2_OUT
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A5_OUT
CFG_GPMC_A6_OUT
CFG_GPMC_A7_OUT
CFG_GPMC_A8_OUT
CFG_GPMC_A9_OUT
CFG_GPMC_AD0_OUT
CFG_GPMC_AD1_OUT
CFG_GPMC_AD10_OUT
CFG_GPMC_AD11_OUT
CFG_GPMC_AD12_OUT
CFG_GPMC_AD13_OUT
CFG_GPMC_AD14_OUT
CFG_GPMC_AD15_OUT
CFG_GPMC_AD2_OUT
CFG_GPMC_AD3_OUT
CFG_GPMC_AD4_OUT
CFG_GPMC_AD5_OUT
CFG_GPMC_AD6_OUT
CFG_GPMC_AD7_OUT
CFG_GPMC_AD8_OUT
CFG_GPMC_AD9_OUT
CFG_GPMC_CS3_OUT
vout3_d16
vout3_d17
vout3_de
vout3_fld
0
0
0
gpmc_a10
gpmc_a11
gpmc_a2
0
0
0
L3
0
0
0
L2
0
0
0
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vout3_hsync
vout3_vsync
vout3_d0
vout3_d1
vout3_d10
vout3_d11
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_clk
L1
gpmc_a3
0
0
0
K3
K2
J1
gpmc_a4
0
0
0
gpmc_a5
0
0
0
gpmc_a6
0
0
0
K1
K4
H1
F1
E2
A2
B3
C3
C4
A3
B4
E1
C1
D1
D2
B1
B2
C2
D3
G3
gpmc_a7
0
0
0
gpmc_a8
0
105
0
105
0
gpmc_a9
0
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_cs3
0
0
0
0
0
0
0
0
0
0
0
0
427
0
0
0
0
0
0
0
0
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
641
905
905
5.10.6.5 HDMI
The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals
from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other
video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p
@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is
supported (differential).
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注
For more information, see the High-Definition Multimedia Interface chapter of the Device
TRM.
5.10.6.6 CSI2
注
For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the Device
TRM.
The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external
image sensor, data from memory. The CAL is a key component for the following multimedia applications:
camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces
(primary and secondary):
•
The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with data lanes.
5.10.6.6.1 CSI-2 MIPI D-PHY
The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 2 data differential lanes plus 1 clock differential lane in synchronous mode,
double data rate:
•
1.5 Gbps (750 MHz) @OPP_NOM for each lane.
5.10.6.7 EMIF
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
•
•
•
16-bit or 32-bit data path to external SDRAM memory
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
One interface with associated DDR3/DDR3L PHYs
注
For more information, see the EMIF Controller section of the Device TRM.
5.10.6.8 GPMC
The GPMC is the unified memory controller that interfaces external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
注
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
192
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5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-48 and 表 5-49 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-20, 图 5-21, 图 5-22, 图 5-23, 图 5-24 and 图 5-25).
表 5-48. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default
NO.
PARAMETER
DESCRIPTION
MIN
3
MAX UNIT
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
ns
ns
ns
ns
1.1
2.5
1.3
注
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
表 5-49. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default
NO.
F0
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period
MIN
MAX UNIT
11.3
ns
(7)
(7)
F2
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
td(clkH-ADDIV)
td(nBEV-clk)
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
td(clkH-nOE)
td(clkH-nOEIV)
td(clkH-nWE)
td(clkH-Data)
td(clkH-nBE)
tw(nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
F-1.7
F+4.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
F3
E-1.7 (6) E+4.2 (6)
B-1.8 (3) B+4.3 (3)
-1.8
F4
F5
F6
B-4.3(3)
B+1.5(3)
F7
D-1.5(5) D+4.3(5)
G-1.3 (8) G+4.2 (8)
D-1.3 (5) G+4.2 (5)
H-1.0 (9) H+3.2 (9)
E-1.0 (6) E+3.2 (6)
I-0.9 (10) I+4.2 (10)
F8
F9
F10
F11
F14
F15
F17
F18
F19
F20
F23
(11)
(11)
J-2.1
J-1.5
J+4.6
J+4.3
(11)
(11)
A (2)
(4)
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K (12)
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16 transition
0.5
7.5
表 5-50. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate(1)
NO.
PARAMETER
DESCRIPTION
MIN
2.5
MAX UNIT
F12 tsu(dV-clkH)
F13 th(clkH-dV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
ns
ns
1.9
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表 5-50. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate(1) (continued)
NO.
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
PARAMETER
DESCRIPTION
MIN
2.5
MAX UNIT
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
ns
ns
1.9
(1) Total GPMC load on any signal at 3.3V must not exceed 10pF.
表 5-51. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate(1)
NO.
F0
F2
F3
F4
F5
F6
F7
F8
F9
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period (13)
MIN
MAX UNIT
15.04
ns
(7)
(7)
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
F+0.6
F+7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
E+0.6 (6) E+7.0 (6)
B-0.7 (3) B+7.0 (3)
-0.7
td(clkH-ADDIV)
td(nBEV-clk)
B-7.0
D-0.4
B+0.4
D+7.0
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
G+0.7 (8) G+6.1 (8)
D+0.7 (5) D+6.1 (5)
H+0.7 (9) H+5.1 (9)
E+0.7 (6) E+5.1 (6)
I+0.7 (10) I+6.1 (10)
F10 td(clkH-nOE)
F11 td(clkH-nOEIV)
F14 td(clkH-nWE)
F15 td(clkH-Data)
F17 td(clkH-nBE)
F18 tw(nCSV)
(11)
(11)
J-0.4
J-0.4
J+4.9
J+4.9
(11)
(11)
A (2)
(4)
F19 tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
F20 tw(nADVV)
F23 td(CLK-GPIO)
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14)
K (12)
0.5
7.5
(1) Total GPMC load on any signal at 3.3V must not exceed 10pF.
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
with n the page burst access number.
(3) B = ClkActivationTime × GPMC_FCLK
(4) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For Burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK with n the page burst
access number.
(5) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(6) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(7) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 × CSExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1:
F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
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F = (3 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
(8) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV desactivated) in Reading mode:
Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 3) is a multiple of 4)
For ADV rising edge (ADV desactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 3) is a multiple of 4)
(9) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay)) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE desactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
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- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE desactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(11) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(12) For read:
K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(13) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(14) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(15) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F19
F7
F7
gpmc_ben1
gpmc_ben0
F6
F19
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F4
F5
F12
D 0
gpmc_ad[15:0]
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_01
图 5-20. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F6
F7
F7
F19
gpmc_ben1
F6
F19
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_02
图 5-21. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
198
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F7
F19
gpmc_ben1
gpmc_ben0
Valid
F6
F19
Valid
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F5
F11
F12
F4
F13
D1
F12
gpmc_ad[15:0]
D0
D2
D3
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_03
图 5-22. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F7
F6
F19
gpmc_ben1
Valid
F7
F6
F19
gpmc_ben0
Valid
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F12
F13
D1
F12
gpmc_ad[15:0]
D0
D3
D2
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_04
图 5-23. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
200
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F17
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
Address (LSB)
D 0
D 3
F22
F21
F23
F23
gpio6_16.clkout1
GPMC_05
图 5-24. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 0 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
gpmc_ben1
gpmc_ben0
Address
F17
F17
F6
F6
F17
F17
F17
F17
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
D 0
D 3
F21
F22
F23
F23
gpio6_16.clkout1
GPMC_06
图 5-25. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-52 and 表 5-53 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-26, 图 5-27, 图 5-28, 图 5-29, 图 5-30 and 图 5-31).
表 5-52. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
PARAMETER
tacc(DAT)
DESCRIPTION
MIN
MAX
UNIT
cycles
cycles
(1)
FA5
Data Maximum Access Time (GPMC_FCLK cycles)
H
FA20 tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
P (2)
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表 5-52. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
cycles
ns
(1)
FA21 tacc2-pgmode(DAT)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
H
-
-
tsu(DV-OEH)
th(OEH-DV)
1.9
1
ns
(1) H = Access Time × (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime × (TimeParaGranularity + 1)
表 5-53. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX UNIT
-
-
4.067
4.463
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fallling time, gpmc_ad[15:0] output data
(1)
FA0 tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
N
(2)
FA1 tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(3)
(3)
FA3 td(nCSV-nADVIV)
FA4 td(nCSV-nOEIV)
FA9 td(AV-nCSV)
FA10 td(nBEV-nCSV)
FA12 td(nCSV-nADVV)
FA13 td(nCSV-nOEV)
FA16 tw(AIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
Delay time, address bus valid to gpmc_cs[7:0] valid
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, address invalid between 2 successive R/W accesses
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
Delay time, gpmc_ wen valid to data bus valid
B - 2
B + 4
(4)
(5)
(4)
(5)
(5)
(6)
(7)
C - 2
J - 2
J - 2
K - 2
L - 2
G
C + 4
J + 4
J + 4
K + 4
L + 4
(5)
(6)
(7)
(8)
(9)
(9)
FA18 td(nCSV-nOEIV)
FA20 tw(AV)
I - 2
D
I + 4
(10)
(11)
(12)
(11)
(12)
FA25 td(nCSV-nWEV)
FA27 td(nCSV-nWEIV)
FA28 td(nWEV-DV)
FA29 td(DV-nCSV)
FA37 td(nOEV-AIV)
E - 2
F - 2
E + 4
F + 4
2
(5)
(5)
Delay time, data bus valid to gpmc_cs[7:0] valid
J - 2
J + 4
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus
phase end
2
(1) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(3) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
(4) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(5) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK
(6) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
(7) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(8) G = Cycle2CycleDelay × GPMC_FCLK × (TimeParaGranularity +1)
(9) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) ×
GPMC_FCLK
(10) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK
(11) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(12) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
Valid
FA0
gpmc_ben1
Valid
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
OUT
IN
OUT
DIR
GPMC_07
图 5-26. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
204
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GPMC_FCLK
gpmc_clk
gpmc_csi
FA5
FA5
FA1
FA1
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA12
FA3
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
OUT
FA14
OUT
DIR
IN
IN
GPMC_08
图 5-27. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA21
FA20
Add1
FA20 FA20
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Add0
Add2
Add3
Add4
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D2
D3
D0
D1
gpmc_waitj
FA15
FA14
OUT
OUT
DIR
IN
SPRS91v_GPMC_09
图 5-28. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime
register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
206
Specifications
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
FA29
Data OUT
OUT
GPMC_10
图 5-29. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
Valid
FA0
FA10
gpmc_ben1
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
FA29
FA37
Data IN
Data IN
Address (LSB)
FA15
FA14
OUT
DIR
OUT
IN
gpmc_waitj
GPMC_11
图 5-30. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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gpmc_fclk
gpmc_clk
gpmc_csi
FA1
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
FA10
gpmc_ben0
FA0
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
FA29
FA28
Valid Address (LSB)
Data OUT
OUT
GPMC_12
图 5-31. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-54 and 表 5-55 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-32, 图 5-33, 图 5-34 and 图 5-35).
表 5-54. GPMC/NAND Flash Interface Timing Requirements
NO.
GNF12
-
PARAMETER
tacc(DAT)
tsu(DV-OEH)
DESCRIPTION
MIN
MAX
J (1)
UNIT
cycles
ns
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
1.9
1
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
ns
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(1) J = AccessTime × (TimeParaGranularity + 1)
表 5-55. GPMC/NAND Flash Interface Switching Characteristics
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX UNIT
-
-
4.067
4.463
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fallling time, gpmc_ad[15:0] output data
GNF0 tw(nWEV)
Pulse duration, gpmc_wen valid time
A (1)
(2)
(2)
GNF1 td(nCSV-nWEV)
GNF2 td(CLEH-nWEV)
GNF3 td(nWEV-DV)
GNF4 td(nWEIV-DIV)
GNF5 td(nWEIV-CLEIV)
GNF6 td(nWEIV-nCSIV)
GNF7 td(ALEH-nWEV)
GNF8 td(nWEIV-ALEIV)
GNF9 tc(nWE)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
Delay time, gpmc_advn_ale high to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
Cycle time, write cycle time
B - 2
B + 4
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(8)
(9)
C - 2
D - 2
E - 2
F - 2
G - 2
C - 2
F - 2
C + 4
D + 4
E + 4
F + 4
G + 4
C + 4
F + 4
H
(9)
GNF10 td(nCSV-nOEV)
GNF13 tw(nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, gpmc_oen_ren valid time
I - 2
I + 4
K (10)
(11)
GNF14 tc(nOE)
Cycle time, read cycle time
L
(12)
(12)
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
M - 2
M + 4
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay ) × GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay ) × GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay ) × GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay ) × GPMC_FCLK
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay ) × GPMC_FCLK
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GPMC_FCLK
GNF1
GNF2
GNF6
GNF5
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
GNF0
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
图 5-32. GPMC / NAND Flash - Command Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF7
GNF6
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Address
GPMC_14
图 5-33. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
图 5-34. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
图 5-35. GPMC / NAND Flash - Data Write Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
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Virtual IO Timings Modes must be used to ensure some IO timings for GPMC. See 表 5-30 Modes Summary for a list of IO timings requiring the
use of Virtual IO Timings Modes. See 表 5-56 Virtual Functions Mapping for GPMC for a definition of the Virtual modes.
表 5-56 presents the values for DELAYMODE bitfield.
表 5-56. Virtual Functions Mapping for GPMC
BALL
BALL NAME
Delay Mode Value
GPMC_VIRTUAL1
15
MUXMODE
0
1
2
3
5
6
14(1)
14(1)
H5
gpmc_advn_al
e
gpmc_advn_al
e
gpmc_cs6
gpmc_wait1
gpmc_a2
gpmc_a23
B4
B1
E1
E10
G6
A3
H3
K4
H4
D1
A5
F1
gpmc_ad15
gpmc_ad6
gpmc_ad2
vin2a_d9
13
13
13
9
gpmc_ad15
gpmc_ad6
gpmc_ad2
gpmc_a25
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
15
13
15
14
15
13
15
13
15
9
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
vin2a_d11
gpmc_ad1
gpmc_ad13
gpmc_a2
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
gpmc_a20
F6
C10
E2
C4
L2
gpmc_a23
13
13
14
13
9
gpmc_ad1
gpmc_ad13
gpmc_a2
D2
B10
F3
gpmc_ad5
vin2a_d8
gpmc_ad5
gpmc_a26
gpmc_a27
gpmc_cs0
vin2a_hsync0
gpmc_a4
15
9
gpmc_cs0
E8
K3
H2
J1
14
15
14
15
13
gpmc_a4
gpmc_ben0
gpmc_a6
gpmc_ben0
gpmc_a6
gpmc_cs4
K6
B3
gpmc_a15
gpmc_ad11
gpmc_a15
gpmc_ad11
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表 5-56. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
K5
M2
D7
B5
C2
A2
C3
E7
D10
G3
G5
H1
A6
C1
B2
K1
L1
gpmc_a16
gpmc_a1
15
14
15
15
13
13
13
15
9
gpmc_a16
gpmc_a1
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
vin2a_d10
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
gpmc_a18
gpmc_a17
gpmc_a14
gpmc_a22
gpmc_a24
14
15
14
15
13
13
14
14
15
15
15
15
11
14
15
15
14
15
15
13
15
15
14
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a1
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
gpmc_a3
gpmc_a3
H6
L4
gpmc_ben1
gpmc_clk
gpmc_ben1
gpmc_clk
gpmc_cs5
gpmc_cs7
gpmc_a3
gpmc_a0
gpmc_wait1
C5
G4
C7
J2
gpmc_a22
gpmc_cs2
vin2a_fld0
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
gpmc_a22
gpmc_cs2
gpmc_a16
gpmc_a27
gpmc_a18
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
G1
G2
K2
D6
B6
D3
A4
C6
M1
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a15
gpmc_a21
gpmc_a13
gpmc_a19
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表 5-56. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
D8
F2
L3
vin2a_clk0
gpmc_a18
gpmc_a11
11
15
14
gpmc_a27
gpmc_a17
gpmc_a18
gpmc_a11
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(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
5.10.6.9 Timers
The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz
synchronized timer (COUNTER_32K) that have the following features:
•
Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Supported modes:
–
–
–
Compare and capture modes
Auto-reload mode
Start-stop mode
•
On-the-fly read/write register (while counting)
The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following
features:
•
•
•
Free-running 32-bit upward counter
On-the-fly read/write register (while counting)
Reset upon occurrence of a timer overflow condition
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU
watchdog timer.
The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
In are presented the specific groupings of signals (IOSET) for use with TIMERS.
注
For additional information on the Timer Module, see the Device TRM.
5.10.6.10 I2C
The device includes 5 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
注
Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is
not supported.
注
Inter-integrated circuit i (i=1 to 5) module is also referred to as I2Ci.
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注
For more information, see the Multimaster High-Speed I2C Controller section of the Device
TRM.
表 5-57, 表 5-58 and 图 5-36 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-57. Timing Requirements for I2C Input Timings(1)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
3
th(SDAL-SCLL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
0(3)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
3.45(4)
0.9(4) µs
Pulse duration, SDA high between STOP and
START conditions
8
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
20 + 0.1Cb
9
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300(3) ns
300(3) ns
300(3) ns
300(3) ns
µs
(5)
20 + 0.1Cb
10
11
12
13
(5)
20 + 0.1Cb
(5)
20 + 0.1Cb
300
(5)
Setup time, SCL high before SDA high (for
STOP condition)
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
14
15
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50 ns
(5)
Cb
400
400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
表 5-58. Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)(1)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
Cb = 400 pF (2)
UNIT
MIN
0.294
160
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
0.588
µs
ns
tsu(SCLH-SDAL)
Set-up time, SCL high before
SDA low (for a repeated START
condition)
160
3
th(SDAL-SCLL)
Hold time, SCL low after SDA
low (for a repeated START
condition)
160
160
ns
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表 5-58. Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)(1) (continued)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
Cb = 400 pF (2)
UNIT
MIN
160
60
MAX
MIN
320
120
10
MAX
ns
4
5
6
tw(SCLL)
LOW period of the SCLH clock
HIGH period of the SCLH clock
tw(SCLH)
ns
tsu(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10
ns
(3)
(3)
7
th(SCLL-SDAV)
tsu(SCLH-SDAH)
tw(SP)
Hold time, SDA valid after SCL
low
0
70
0
150
ns
ns
ns
pF
pF
13
14
15
16
Setup time, SCL high before
SDA high (for a STOP condition)
160
0
160
0
Pulse duration, spike (must be
suppressed)
10
100
400
10
400
400
(2)
Cb
Capacitive load for SDAH and
SCLH lines
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
(1) I2C HS-Mode is only supported on I2C3/4/5. I2C HS-Mode is not supported on I2C1/2.
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
9
11
I2Ci_SDA
I2Ci_SCL
6
8
14
4
13
5
10
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_01
图 5-36. I2C Receive Timing
表 5-59 and 图 5-37 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-59. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
18
th(SDAL-SCLL)
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100
218
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表 5-59. Switching Characteristics Over Recommended Operating Conditions for I2C Output
Timings(2) (continued)
STANDARD MODE
FAST MODE
MIN
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MAX
0.9 µs
µs
Hold time, SDA valid after SCL low (for I2C
bus devices)
22
23
24
25
26
27
th(SCLL-SDAV)
tw(SDAH)
tr(SDA)
0
3.45
0
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
20 + 0.1Cb
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300(3) ns
300(3) ns
300(3) ns
300(3) ns
(1) (3)
20 + 0.1Cb
tr(SCL)
(1) (3)
20 + 0.1Cb
tf(SDA)
(1) (3)
20 + 0.1Cb
tf(SCL)
300
(1) (3)
Setup time, SCL high before SDA high (for
STOP condition)
28
29
tsu(SCLH-SDAH)
Cp
4
0.6
µs
Capacitance for each I2C pin
10
10 pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, and I2C5 use standard LVCMOS buffers to emulate open-drain buffers and their
rise/fall times should be referenced in the device IBIS model.
注
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
26
24
I2Ci_SDA
I2Ci_SCL
21
23
19
28
20
25
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_02
图 5-37. I2C Transmit Timing
5.10.6.11 HDQ1W
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
注
For more information, see the HDQ / 1-Wire section of the Device TRM.
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5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
表 5-60 and 表 5-61 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-38, 图 5-39, 图 5-40 and 图 5-41).
表 5-60. HDQ/1-Wire Timing Requirements—HDQ Mode
NO.
1
PARAMETER
tCYCH
DESCRIPTION
MIN
190
MAX
250
UNIT
µs
Read bit window timing
2
tHW1
tHW0
tRSPS
Read one data valid after HDQ low
Read zero data hold after HDQ low
Response time from HDQ slave device(1)
32(2)
70(2)
190
66(2)
145(2)
320
µs
3
µs
4
µs
(1) Defined by software.
(2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see
"HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM.
表 5-61. HDQ / 1-Wire Switching Characteristics - HDQ Mode
NO.
5
PARAMETER
DESCRIPTION
MIN
190
40
MAX
UNIT
µs
tB
Break timing
6
tBR
Break recovery time
Write bit windows timing
µs
7
tCYCD
tDW1
tDW0
190
0.5
86
µs
8
Write one data valid after HDQ low
Write zero data hold after HDQ low
50
µs
9
145
µs
tB
tBR
HDQ
HDQ
HDQ
SPRS906_TIMING_HDQ1W_01
图 5-38. HDQ Break and Break Recovery Timing — HDQ Interface Writing to Slave
tCYCH
tHW0
tHW1
SPRS906_TIMING_HDQ1W_02
图 5-39. Device HDQ Interface Bit Read Timing (Data)
tCYCD
tDW0
tDW1
SPRS906_TIMING_HDQ1W_03
图 5-40. Device HDQ Interface Bit Write Timing (Command / Address or Data)
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Command_byte_written
0_(LSB)
Data_byte_received
1
tRSPS
Break
1
6
7_(MSB)
0_(LSB)
6
HDQ
SPRS906_TIMING_HDQ1W_04
图 5-41. HDQ Communication Timing
5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
表 5-62 and 表 5-63 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-42, 图 5-43 and 图 5-44).
表 5-62. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
10
PARAMETER
tPDH
DESCRIPTION
MIN
15
MAX
60
UNIT
µs
Presence pulse delay high
Presence pulse delay low
Read data valid time
11
tPDL
tRDV
tREL
60
240
15
µs
12
tLOWR
0
µs
13
Read data release time
45
µs
表 5-63. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
14
15
16
17
18
19
20
PARAMETER
DESCRIPTION
Reset time low
MIN
480
480
60
1
MAX
UNIT
µs
tRSTL
tRSTH
tSLOT
tLOW1
tLOW0
tREC
960
Reset time high
µs
Bit cycle time
120
15
µs
Write bit-one time
Write bit-zero time(2)
µs
60
1
120
µs
Recovery time
Read bit strobe time(1)
µs
tLOWR
1
15
µs
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) tLOWR must be less than tSLOT
.
tRSTH
tPDL
tPDH
tRTSL
1-WIRE
SPRS906_TIMING_HDQ1W_05
图 5-42. 1-Wire—Break (Reset)
tSLOT_and_tREC
tRDV_and_tREL
tLOWR
1-WIRE
SPRS906_TIMING_HDQ1W_06
图 5-43. 1-Wire—Read Bit (Data)
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tSLOT_and_tREC
tLOW0
tLOW1
1-WIRE
SPRS906_TIMING_HDQ1W_07
图 5-44. 1-Wire—Write Bit-One Timing (Command / Address or Data)
5.10.6.12 UART
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one
UART supports IrDA features. Each UART can be used for configuration and data exchange with a
number of external peripheral devices or interprocessor communication between devices
The UARTi (where i = 1 to 10) include the following features:
•
•
•
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
Only UART3 supports IrDA
注
For more information, see the UART section of the Device TRM.
表 5-64, 表 5-65 and 图 5-45 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-64. Timing Requirements for UART
NO.
4
PARAMETER
DESCRIPTION
MIN
0.96U(1)
0.96U(1)
P(2)
MAX UNIT
tw(RX)
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
1.05U(1)
1.05U(1)
ns
ns
ns
ns
5
tw(CTS)
td(RTS-TX)
td(CTS-TX)
P(2)
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
表 5-65. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
MAX UNIT
15 pF
30 pF
100 pF
12
f(baud)
Maximum programmable baud rate
0.23
MHz
ns
0.115
U + 2(1)
2
tw(TX)
Pulse width, transmit data bit, 15/30/100 pF high or low
U - 2(1)
222
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表 5-65. Switching Characteristics Over Recommended Operating Conditions for UART (continued)
NO.
PARAMETER
tw(RTS)
DESCRIPTION
MIN
U - 2(1)
MAX UNIT
U + 2(1)
ns
3
Pulse width, transmit start bit, 15/30/100 pF high or low
(1) U = UART baud time = 1/programmed baud rate
2
1
Start
Bit
UART_TXD
Data Bits
3
4
Start
Bit
UART_RXD
Data Bits
SPRS961_TIMING_UART_01
图 5-45. UART Timing
In are presented the specific groupings of signals (IOSET) for use with UART.
5.10.6.13 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
SPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
注
For more information, see the Serial Communication Interface section of the Device TRM.
注
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
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CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in 表
5-68.
表 5-66, 图 5-46 and 图 5-47 present Timing Requirements for McSPI - Master Mode.
表 5-66. Timing Requirements for SPI - Master Mode (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SM1
tc(SPICLK)
Cycle time, spi_sclk (1) (2)
SPI1/2/3/
4
20.8 (3)
ns
SM2
SM3
tw(SPICLKL)
tw(SPICLKH)
Typical Pulse duration, spi_sclk low (1)
Typical Pulse duration, spi_sclk high (1)
0.5 × P-1
ns
ns
(4)
0.5 × P-1
(4)
SM4
SM5
SM6
tsu(MISO-SPICLK)
th(SPICLK-MISO)
td(SPICLK-SIMO)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
Hold time, spi_d[x] valid after spi_sclk active edge (1)
Delay time, spi_sclk active edge to spi_d[x] transition (1)
3.5
3.7
ns
ns
ns
ns
ns
ns
ns
ns
SPI1
SPI2
SPI3
SPI4
-3.57
-3.9
-4.9
-4.3
4.1
3.6
4.7
4.5
5
SM7
SM8
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
Delay time, spi_cs[x] active to spi_sclk first edge (1)
td(CS-SPICLK)
MASTER B-4.2 (6)
_PHA0
(5)
MASTER A-4.2 (7)
ns
ns
ns
_PHA1
(5)
SM9
td(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)
MASTER A-4.2 (7)
_PHA0
(5)
MASTER B-4.2 (6)
_PHA1
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
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spim_cs(OUT)
spim_sclk(OUT)
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PHA=0
EPOL=1
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SM1
SM3
SM2
spim_sclk(OUT)
spim_d(OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
spim_d(OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRS906_TIMING_McSPI_01
图 5-46. McSPI - Master Mode Transmit
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
SM2
POL=1
spim_sclk(OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
POL=1
spim_sclk(OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_02
图 5-47. McSPI - Master Mode Receive
表 5-67, 图 5-48 and 图 5-49 present Timing Requirements for McSPI - Slave Mode.
表 5-67. Timing Requirements for SPI - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS1 (1) tc(SPICLK)
SS2 (1) tw(SPICLKL)
SS3 (1) tw(SPICLKH)
Cycle time, spi_sclk
62.5 (2)
ns
(3)
Typical Pulse duration, spi_sclk low
Typical Pulse duration, spi_sclk high
0.45 × P
ns
ns
(4)
0.45 × P
(4)
SS4 (1) tsu(SIMO-SPICLK)
SS5 (1) th(SPICLK-SIMO)
SS6 (1) td(SPICLK-SOMI)
Setup time, spi_d[x] valid before spi_sclk active edge
Hold time, spi_d[x] valid after spi_sclk active edge
Delay time, spi_sclk active edge to mcspi_somi transition
5
5
2
2
ns
ns
ns
ns
SPI1/2/3
SPI4
26.6
20.1
226
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表 5-67. Timing Requirements for SPI - Slave Mode (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
SS7 (5) td(CS-SOMI)
SS8 (1) tsu(CS-SPICLK)
SS9 (1) th(SPICLK-CS)
Delay time, spi_cs[x] active edge to mcspi_somi transition
Setup time, spi_cs[x] valid before spi_sclk first edge
Hold time, spi_cs[x] valid after spi_sclk last edge
20.95
5
5
ns
SPI1/2
SPI3
ns
7.5
6
ns
SPI4
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
SS1
SS2
spim_sclk(IN)
spim_d(OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
spim_sclk(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
spim_sclk(IN)
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRS906_TIMING_McSPI_03
图 5-48. McSPI - Slave Mode Transmit
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PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
spim_sclk(IN)
SS1
SS2
POL=1
spim_sclk(IN)
SS5
SS4
SS4
SS5
Bit n-2
Bit n-1
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
spim_sclk(IN)
SS1
SS3
POL=1
spim_sclk(IN)
SS4
SS5
SS4
Bit n-1
SS5
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_04
图 5-49. McSPI - Slave Mode Receive
In 表 5-68 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
表 5-68. McSPI3/4 IOSETs
SIGNALS
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
BALL
MUX
MUX
MUX
MUX
MUX
McSPI3
B18
spi3_cs0
spi3_cs1
spi3_d0
spi3_d1
spi3_sclk
T5
W2
T4
7
1
7
7
7
3
3
3
3
3
D23
2
AA3
W2
AA2
Y4
1
1
1
1
1
A19
B16
A24
B25
C23
2
2
2
N6
N5
B17
A18
Y1
McSPI4
R1
spi4_cs0
spi4_cs1
spi4_cs2
L3
G1
H3
8
8
8
B9
G1
H3
8
8
8
7
8
8
AC4
N6
2
8
8
AB1
N6
1
8
8
N6
T4
T4
T4
228
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SIGNALS
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-68. McSPI3/4 IOSETs (continued)
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
BALL
MUX
MUX
MUX
MUX
MUX
spi4_cs3
spi4_d0
spi4_d1
spi4_sclk
H4
J2
8
8
8
8
H4
C8
B8
E8
8
8
8
8
T5
R2
P3
P4
8
7
7
7
T5
AA5
U6
8
2
2
2
T5
AA4
AA1
Y3
8
1
1
1
H1
K4
AC3
5.10.6.14 QSPI
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
•
•
•
•
•
•
•
•
Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer
注
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-69 and 表 5-70 Present Timing and Switching Characteristics for Quad SPI Interface.
表 5-69. Switching Characteristics for QSPI
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q1
tc(SCLK)
Cycle time, sclk
Default Timing Mode,
Clock Mode 0
11.71
ns
Default Timing Mode,
Clock Mode 3
20.8
ns
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表 5-69. Switching Characteristics for QSPI (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q2
tw(SCLKL)
Pulse duration, sclk low
Y × P-1
ns
(1)
Q3
Q4
tw(SCLKH)
Pulse duration, sclk high
Y × P-1
ns
(1)
td(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0
Default Timing Mode
Default Timing Mode
Default Timing Mode
-M × P-
-M ×
ns
ns
1.6 (2)
P+2.6
(3)
(2) (3)
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
N × P-
N ×
1.6 (2)
P+2.6
(3)
(2) (3)
Q6
Q7
Q8
Q9
td(SCLK-D0)
tena(CS-D0LZ)
tdis(CS-D0Z)
td(SCLK-D0)
Delay time, sclk falling edge to d[0] transition
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
Delay time, sclk first falling edge to first d[0] transition
-1.6
2.6
ns
ns
ns
ns
-P-3.5 -P+2.5
-P-2.5 -P+2.0
PHA=0 Only, Default
Timing Mode
-1.6- 2.6-P(2)
P(2)
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
cs
Q5
Q1
PHA=1
POL=1
Q4
Q3
Q2
sclk
Q15
Q14
Q12
Q6
Q13
Read Data
Bit 1
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 0
d[0]
Q15
Q14
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_01
图 5-50. QSPI Read (Clock Mode 3)
230
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cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
rtclk
POL=0
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_02
图 5-51. QSPI Read (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-70. Timing Requirements for QSPI(3)(2)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q12
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Default Timing Mode,
Clock Mode 0
4.6
ns
tsu(D-SCLK)
th(RTCLK-D)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling rtclk edge
Hold time, d[3:0] valid after falling sclk edge
Default Timing Mode,
Clock Mode 3
12.3
-0.1
0.1
ns
ns
ns
ns
ns
Q13
Default Timing Mode,
Clock Mode 0
Default Timing Mode,
Clock Mode 3
Q14
Q15
Setup time, final d[3:0] bit valid before final falling sclk
edge
Default Timing Mode,
Clock Mode 3
12.3-P
(1)
Hold time, final d[3:0] bit valid after final falling sclk
edge
Default Timing Mode,
Clock Mode 3
0.1+P
(1)
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
cs
Q5
Q1
PHA=1
Q4
Q3
Q2
POL=1
sclk
Q8
Q6
Q6
Q6
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_03
图 5-52. QSPI Write (Clock Mode 3)
cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_04
图 5-53. QSPI Write (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
232
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注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for QSPI. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-71 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
表 5-71 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-71. Manual Functions Mapping for QSPI
BALL
BALL NAME
QSPI1_MANUAL1
CFG REGISTER
MUXMODE
1
A_DELAY (ps)
G_DELAY (ps)
L1
K3
H3
H4
K6
K5
K5
G2
F2
G4
G3
gpmc_a3
gpmc_a4
0
0
0
0
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A13_IN
CFG_GPMC_A14_IN
CFG_GPMC_A15_IN
CFG_GPMC_A16_IN
CFG_GPMC_A16_OUT
CFG_GPMC_A17_IN
CFG_GPMC_A18_OUT
CFG_GPMC_CS2_OUT
CFG_GPMC_CS3_OUT
qspi1_cs2
qspi1_cs3
qspi1_rtclk
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d0
qspi1_d1
qspi1_sclk
qspi1_cs0
qspi1_cs1
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_cs2
gpmc_cs3
0
0
2247
2176
2229
0
1186
1197
1268
0
2251
0
1217
0
0
0
0
0
5.10.6.15 McASP
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
•
•
•
McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
McASP3 through McASP7 modules supporting 4 channels with independent TX/RX clock/sync domain
McASP8 module supporting 2 channels with independent TX/RX clock/sync domain
注
For more information, see the Serial Communication Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-72, 表 5-73, 表 5-74 and 图 5-54 present Timing Requirements for McASP1 to McASP8
.
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表 5-72. Timing Requirements for McASP1(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
20
MAX
UNIT
ns
Cycle time, AHCLKX
2
tw(AHCLKX)
tc(ACLKRX)
Pulse duration, AHCLKX high or low
Cycle time, ACLKR/X
0.35P (2)
ns
3
20
ns
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5R - 3
ns
(3)
5
6
7
8
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
20.5
4
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.7
in
ACLKR/X ext
out
ACLKR/X int
21.6
11.5
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.8
in
ACLKR/X ext
out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 5-73. Timing Requirements for McASP2(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
(2)
3
4
tc(ACLKX)
Cycle time, ACLKX
Any Other Conditions
20
ns
ns
ACLKX/AFSX (In Sync Mode)
and AXR are all inputs "80M"
Virtual IO Timing Modes
12.5
tw(ACLKX)
Pulse duration, ACLKX high or low
Any Other Conditions
0.5R - 3
ns
ns
(3)
ACLKX/AFSX (In Sync Mode)
and AXR are all inputs "80M"
Virtual IO Timing Modes
0.38R
(3)
5
tsu(AFSX-ACLK)
Setup time, AFSX input valid before ACLKX
ACLKX int
20.3
4.5
ns
ns
ACLKX ext in
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
234
Specifications
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表 5-73. Timing Requirements for McASP2(1) (continued)
NO.
PARAMETER
DESCRIPTION
Hold time, AFSX input valid after ACLKX
MODE
ACLKX int
MIN
-1
MAX UNIT
6
th(ACLK-AFSX)
tsu(AXR-ACLK)
th(ACLK-AXR)
ns
ns
ACLKX ext in
ACLKX ext out
1.8
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
7
8
Setup time, AXR input valid before ACLKX
Hold time, AXR input valid after ACLKX
ACLKX int
21.1
4.5
ns
ns
ACLKX ext in
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
ACLKX int
-1
ns
ns
ACLKX ext in
1.8
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKX period in ns.
表 5-74. Timing Requirements for McASP3/4/5/6/7/8(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
(2)
3
4
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5R - 3
(3)
5
6
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
ACLKR/X int
19.7
5.6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
-1.1
2.5
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKX int
(ASYNC=0)
20.3
5.1
ns
ns
ns
ns
ACLKR/X ext in
ACLKR/X ext out
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKX
ACLKX int
(ASYNC=0)
-0.8
2.5
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
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2
1
2
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
图 5-54. McASP Input Timing
表 5-75, 表 5-76, 表 5-77 and 图 5-55 present Switching Characteristics Over Recommended Operating
Conditions for McASP1 to McASP8.
表 5-75. Switching Characteristics Over Recommended Operating Conditions for McASP1(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
236
Specifications
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表 5-75. Switching Characteristics Over Recommended Operating Conditions for McASP1(1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
-0.9
2
MAX UNIT
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X int
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.1
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-1.4
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 5-76. Switching Characteristics Over Recommended Operating Conditions for McASP2 (1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKX)
tw(ACLKX)
Cycle time, ACLKX
20
ns
ns
Pulse duration, ACLKX high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSX)
Delay time, ACLKX transmit edge to AFSX output valid
Delay time, ACLKX transmit edge to AXR output valid
ACLKX int
-1
2
6
ns
ns
ACLKX ext in
ACLKX ext out
23.2
td(ACLK-AXR)
ACLKX int
-1.3
2
6
ns
ns
ACLKX ext in
23.7
ACLKX ext out
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKX period in ns.
表 5-77. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-0.5
1.9
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.5
td(ACLK-AXR)
ACLKR/X int
-1.4
1.1
7.1
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.2
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(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
10
10
9
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
12
11
12
(A)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/T ransmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
图 5-55. McASP Output Timing
表 5-78 through 表 5-85 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see 图 5-56
through 图 5-63).
238
Specifications
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表 5-78. Virtual Mode Case Details for McASP1
No.
CASE
CASE Description
Virtual Mode Settings
Notes
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX: Output
CLKR / FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
CLKX / FSR: Output
CLKR / FSX: Input
MCASP1_VIRTUAL2_ASYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
CLKR / FSR: Output
CLKX / FSX: Input
CLKR / FSX: Output
CLKX / FSR: Input
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output CLKX:
Input
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX: Input
CO-FI-
CLKX: Output FSX:
Input
Default (No Virtual Mode)
表 5-79. Virtual Mode Case Details for McASP2
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
FSX: Output
CLKX: Input
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL1_SYNC_RX_80M(2)
Default (No Virtual Mode)
CLKX / FSX:
Input
8
CO-FI-
CLKX: Output
FSX: Input
See 图 5-63
Default (No Virtual Mode)
(1) Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are
bidirectional).
(2) Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.
表 5-80. Virtual Mode Case Details for McASP3
No.
CASE
CASE
Description
Virtual Mode Settings
Virtual Mode Value
Notes
Signals
IP Mode : ASYNC
1
COIFOI
CLKX /
FSX: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
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Specifications
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表 5-80. Virtual Mode Case Details for McASP3 (continued)
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
Default (No Virtual Mode)
2
COIFIO
CLKX /
FSR: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
See 图 5-57
See 图 5-58
See 图 5-59
MCASP3_VIRTUAL2_SYNC_RX
FSX: Input
3
4
CIOFIO
CIOFOI
CLKR /
FSR: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
FSX: Input
CLKR /
FSX: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX /
FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX /
FSX: Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 5-81. Virtual Mode Case Details for McASP4
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX: Output
FSX: Input
Default (No Virtual Mode)
240
Specifications
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表 5-82. Virtual Mode Case Details for McASP5
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX: Output
FSX: Input
Default (No Virtual Mode)
表 5-83. Virtual Mode Case Details for McASP6
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
MCASP6_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
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表 5-84. Virtual Mode Case Details for McASP7
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
MCASP7_VIRTUAL2_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 5-85. Virtual Mode Case Details for McASP8
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-60
See 图 5-61
See 图 5-62
See 图 5-63
FSX: Output
CLKX: Input
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
242
Specifications
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_01
图 5-56. McASP1-8 COIFOI – ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_02
图 5-57. McASP1-8 COIFIO – ASYNC Mode
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Specifications
243
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_03
图 5-58. McASP1-8 CIOFIO – ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_04
图 5-59. McASP1-8 CIOFOI – ASYNC Mode
244
Specifications
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ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_05
图 5-60. McASP1-8 CO-FO- – SYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_06
图 5-61. McASP1-8 CI-FO- – SYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_07
图 5-62. McASP1-8 CI-FI- – SYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_08
图 5-63. McASP1-8 CO-FI- – SYNC Mode
246
Specifications
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注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
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Virtual IO Timings Modes must be used to ensure some IO timings for McASP1. See 表 5-30 Modes Summary for a list of IO timings requiring the
use of Virtual IO Timings Modes. See 表 5-86 Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.
表 5-86 presents the values for DELAYMODE bitfield.
表 5-86. Virtual Functions Mapping for McASP1
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
0
2
C16
H21
E17
A15
H24
B17
A16
A19
K23
K22
H25
A17
B16
D17
A18
B18
C14
C17
E16
F16
B14
D16
A14
J24
mcasp1_aclkx
gpio6_14
15
14
15
14
14
15
14
15
14
14
14
14
15
N/A
15
15
14
15
15
15
15
N/A
14
15
15
14
15
14
13
14
13
13
14
13
14
13
13
13
13
14
14
14
14
13
14
14
14
14
14
13
14
14
13
14
mcasp1_aclkx
mcasp1_axr8
mcasp1_axr13
mcasp1_axr4
xref_clk2
mcasp1_axr13
mcasp1_axr4
mcasp1_axr6
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
gpio6_16
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
mcasp1_axr10
mcasp1_axr9
gpio6_15
xref_clk3
mcasp1_axr7
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
xref_clk1
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
mcasp1_axr5
mcasp1_axr4
D14
B15
J25
mcasp1_axr0
mcasp1_axr3
xref_clk0
mcasp1_axr0
mcasp1_axr3
248
Specifications
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Virtual IO Timings Modes must be used to ensure some IO timings for McASP2. See 表 5-30 Modes Summary for a list of IO timings requiring the
use of Virtual IO Timings Modes. See 表 5-87 Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.
表 5-87 presents the values for DELAYMODE bitfield.
表 5-87. Virtual Functions Mapping for McASP2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP2_VIRTUAL1
_SYNC_RX_80M
MCASP2_VIRTUAL2
MCASP2_VIRTUAL3
_SYNC_RX
MCASP2_VIRTUAL4
_ASYNC_RX_80M
0
2
_ASYNC_RX
B22
D20
C19
D19
H24
B21
A22
E19
C20
H25
B23
A23
A21
B20
J24
mcasp3_axr0
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
xref_clk2
15
14
14
15
12
15
15
15
14
12
15
15
15
14
10
14
14
10
14
13
13
14
11
14
14
14
13
11
14
14
14
13
9
10
12
12
10
10
10
10
10
12
10
10
10
10
12
8
9
11
11
9
mcasp2_axr14
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr3
mcasp3_aclkx
mcasp2_aclkx
mcasp2_axr7
xref_clk3
9
mcasp2_axr3
9
mcasp2_axr12
9
mcasp2_aclkx
mcasp2_axr7
11
9
mcasp3_axr1
mcasp3_fsx
mcasp2_axr2
mcasp2_axr4
xref_clk1
8
mcasp2_axr15
mcasp2_axr13
9
9
mcasp2_axr2
mcasp2_axr4
11
6
mcasp2_axr9
mcasp2_axr8
B19
A20
J25
mcasp2_axr1
mcasp2_axr0
xref_clk0
13
13
9
12
12
8
11
11
6
mcasp2_axr1
mcasp2_axr0
Virtual IO Timings Modes must be used to ensure some IO timings for McASP3/4/5/6/7/8. See 表 5-30 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See 表 5-88 Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.
表 5-88 presents the values for DELAYMODE bitfield.
表 5-88. Virtual Functions Mapping for McASP3/4/5/6/7/8
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
0
2
MCASP3_VIRTUAL2_SYNC_RX
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表 5-88. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
B21
A22
B22
B23
A23
A21
mcasp2_axr3
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
8
8
8
6
8
8
mcasp3_axr3
mcasp3_aclkr
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mcasp3_fsr
mcasp2_axr2
mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
B25
C23
A24
D23
A14
A15
mcasp4_fsx
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp1_axr5
mcasp1_axr4
14
14
14
14
12
12
mcasp4_fsx
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsr
mcasp4_aclkr
mcasp4_axr3
mcasp4_axr2
MCASP5_VIRTUAL1_SYNC_RX
AC3
U6
mcasp5_aclkx
mcasp5_fsx
14
14
14
12
14
12
mcasp5_aclkx
mcasp5_aclkr
mcasp5_fsr
mcasp5_fsx
AC4
A17
AA5
A16
mcasp5_axr1
mcasp1_axr6
mcasp5_axr0
mcasp1_axr7
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_axr0
MCASP6_VIRTUAL1_SYNC_RX
C14
B15
B16
B17
A18
B18
mcasp1_axr2
mcasp1_axr3
mcasp1_axr10
mcasp1_axr9
mcasp1_axr8
mcasp1_axr11
12
mcasp6_axr2
mcasp6_axr3
mcasp6_aclkx
mcasp6_axr1
mcasp6_axr0
mcasp6_fsx
12
10
mcasp6_aclkr
mcasp6_fsr
10
10
10
MCASP7_VIRTUAL2_SYNC_RX
A19
F16
E16
E17
mcasp1_axr12
mcasp1_axr15
mcasp1_axr14
mcasp1_axr13
10
10
10
10
mcasp7_axr0
mcasp7_fsx
mcasp7_fsr
mcasp7_aclkx
mcasp7_axr1
mcasp7_aclkr
250
Specifications
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表 5-88. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
0
2
D16
D17
mcasp1_aclkr
mcasp1_fsr
13
13
mcasp7_axr2
mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
B20
C20
D20
C19
mcasp2_axr4
mcasp2_axr7
mcasp2_axr6
mcasp2_axr5
10
10
10
10
mcasp8_axr0
mcasp8_fsx
mcasp8_fsr
mcasp8_aclkx
mcasp8_axr1
mcasp8_aclkr
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5.10.6.16 USB
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
•
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
•
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
注
For more information, see the SuperSpeed USB DRD section of the Device TRM.
5.10.6.16.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
•
USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
5.10.6.16.2 USB2 PHY
The USB2 interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
5.10.6.17 PCIe
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
Supports 2 ports × 1-lane or 1 port × 2-lanes configuration
Single virtual channel (VC0), single traffic class (TC0)
Single function in end-point mode
Automatic width and speed negotiation
Max payload: 128 byte outbound, 256 byte inbound
Automatic credit management
ECRC generation and checking
Configurable BAR filtering
Legacy interrupt reception (RC) and generation (EP)
MSI generation and reception
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0.
252
Specifications
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注
For more information, see the PCIe Controller section of the Device TRM.
5.10.6.18 DCAN
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Direct access to Message RAM during test mode
CAN Rx/Tx pins are configurable as general-purpose IO pins
Two interrupt lines (plus additional parity-error interrupts line)
RAM initialization
DMA support
注
For more information, see the DCAN section of the Device TRM.
注
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
注
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter
tolerance calculations must be performed to validate the implementation.
表 5-89 and 表 5-90 present timing and switching characteristics for DCANx Interface.
表 5-89. Timing Requirements for DCANx Receive
NO.
PARAMETER
f(baud)
td(DCANRX)
DESCRIPTION
Maximum programmable baud rate
MIN
NOM
MAX UNIT
-
-
1
Mbps
ns
Delay time, DCANx_RX pin to receive shift register
15
表 5-90. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
PARAMETER
f(baud)
td(DCANTX)
DESCRIPTION
Maximum programmable baud rate
Delay time, Transmit shift register to DCANx_TX pin(1)
MIN
MAX UNIT
-
-
1
Mbps
ns
23
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(1) These values do not include rise/fall times of the output buffer.
5.10.6.19 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
注
For more information, see the Ethernet Subsystem section of the Device TRM.
注
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-95, 表 5-98, 表 5-103 and 表
5-110.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-91 and 图 5-64 present timing requirements for MIIn in receive operation.
5.10.6.19.1 GMAC MII Timings
表 5-91. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(RX_CLK)
Cycle time, miin_rxclk
ns
2
3
4
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
Transition time, miin_rxclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
254
Specifications
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1
4
2
3
miin_rxclk
4
SPRS906_TIMING_GMAC_MIIRXCLK_01
图 5-64. Clock Timing (GMAC Receive) - MIIn operation
表 5-92 and 图 5-65 present timing requirements for MIIn in transmit operation.
表 5-92. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(TX_CLK)
Cycle time, miin_txclk
ns
2
3
4
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, miin_txclk high
Pulse duration, miin_txclk low
Transition time, miin_txclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
1
4
2
3
miin_txclk
4
SPRS906_TIMING_GMAC_MIITXCLK_02
图 5-65. Clock Timing (GMAC Transmit) - MIIn operation
表 5-93 and 图 5-66 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
表 5-93. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
PARAMETER
tsu(RXD-RX_CLK)
DESCRIPTION
MIN
MAX
UNIT
1
2
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
Setup time, receive selected signals valid before miin_rxclk
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
Hold time, receive selected signals valid after miin_rxclk
8
ns
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1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
SPRS906_TIMING_GMAC_MIIRCV_03
图 5-66. GMAC Receive Interface Timing MIIn operation
表 5-94 and 图 5-67 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
表 5-94. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
td(TX_CLK-TX_ER)
DESCRIPTION
MIN
MAX
UNIT
1
Delay time, miin_txclk to transmit selected signals valid
0
25
ns
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen, miin_txer (outputs)
SPRS906_TIMING_GMAC_MIITX_04
图 5-67. GMAC Transmit Interface Timing MIIn operation
In 表 5-95 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
表 5-95. GMAC MII IOSETs
SIGNALS
IOSET5
IOSET6
BALL
MUX
GMAC MII1
BALL
MUX
mii1_txd3
mii1_txd2
mii1_txd1
mii1_txd0
mii1_rxd3
mii1_rxd2
mii1_rxd1
mii1_rxd0
mii1_col
E11
A13
A12
B12
B10
A10
F10
E10
E13
B13
F11
D13
C13
B11
C11
D11
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
mii1_rxer
mii1_txer
mii1_txen
mii1_crs
mii1_rxclk
mii1_txclk
mii1_rxdv
256
Specifications
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表 5-95. GMAC MII IOSETs (continued)
SIGNALS
IOSET5
IOSET6
BALL
MUX
GMAC MII0
BALL
MUX
mii0_txd3
mii0_txd2
mii0_txd1
mii0_txd0
mii0_rxd3
mii0_rxd2
mii0_rxd1
mii0_rxd0
mii0_txclk
mii0_txer
mii0_rxer
mii0_rxdv
mii0_crs
P2
N1
N3
N4
T4
T5
R2
R1
N2
L6
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
P3
N5
P4
L5
mii0_col
mii0_rxclk
mii0_txen
N6
P1
5.10.6.19.2 GMAC MDIO Interface Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-96, 表 5-96 and 图 5-68 present timing requirements for MDIO.
表 5-96. Timing Requirements for MDIO Input
No
PARAMETER
tc(MDC)
DESCRIPTION
MIN
400
160
160
90
MAX
UNIT
ns
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
Cycle time, MDC
tw(MDCH)
Pulse Duration, MDC High
ns
tw(MDCL)
Pulse Duration, MDC Low
ns
tsu(MDIO-MDC)
th(MDIO_MDC)
Setup time, MDIO valid before MDC High
Hold time, MDIO valid from MDC High
ns
0
ns
表 5-97. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
tt(MDC)
DESCRIPTION
MIN
MAX
5
UNIT
ns
MDIO6
MDIO7
Transition time, MDC
Delay time, MDC low to MDIO valid
td(MDC-MDIO)
-150
150
ns
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1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
图 5-68. GMAC MDIO diagrams
In 表 5-98 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
表 5-98. GMAC MDIO IOSETs
SIGNALS
IOSET7
IOSET8
IOSET9
IOSET10
BALL
C10
MUX
BALL
L6
MUX
BALL
Y6
MUX
BALL
E25
MUX
mdio_d
3
3
0
0
1
1
5
5
mdio_mclk
D10
L5
Y5
E24
5.10.6.19.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the Device TRM for full details about RMII reference clock.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-99, 表 5-100 and 图 5-69 present timing requirements for GMAC RMIIn Receive.
表 5-99. Timing Requirements for GMAC REF_CLK - RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
RMII4 ttt(REF_CLK)
Cycle time, REF_CLK
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
7
ns
ns
258
Specifications
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表 5-100. Timing Requirements for GMAC RMIIn Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII5
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, receive selected signals valid before REF_CLK
4
ns
RMII6
Hold time, receive selected signals valid after REF_CLK
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII2
RMII4
RMII6
RMII5
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS906_TIMING_GMAC_RGMIITX_09
图 5-69. GMAC Receive Interface Timing RMIIn operation
表 5-101, 表 5-101 and 图 5-70 present switching characteristics for GMAC RMIIn Transmit 10/100Mbit/s.
表 5-101. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII
Operation
NO.
PARAMETER
tc(REF_CLK)
DESCRIPTION
MIN
20
7
MAX UNIT
RMII7
RMII8
RMII9
Cycle time, REF_CLK
ns
tw(REF_CLKH)
tw(REF_CLKL)
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
ns
ns
7
RMII10 tt(REF_CLK)
表 5-102. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
DESCRIPTION
RMIIn
MIN
MAX UNIT
RMII0
2
13.5
13.8
ns
ns
Delay time, REF_CLK high to selected transmit signals
valid
RMII11
RMII1
2
RMII7
RMII8
RMII9
RMII10
RMII11
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS906_TIMING_GMAC_RMIITX_07
图 5-70. GMAC Transmit Interface Timing RMIIn Operation
In 表 5-103 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
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表 5-103. GMAC RMII IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
GMAC RMII1
BALL
MUX
RMII_MHZ_50_CLK
rmii1_txd1
P5
0
2
2
2
2
2
2
2
P2
N1
T4
T5
N6
N2
N5
rmii1_txd0
rmii1_rxd1
rmii1_rxd0
rmii1_rxer
rmii1_txen
rmii1_crs
GMAC RMII0
RMII_MHZ_50_CLK
rmii0_txd1
P5
N3
N4
R2
R1
P1
P3
P4
0
1
1
1
1
1
1
1
rmii0_txd0
rmii0_rxd1
rmii0_rxd0
rmii0_txen
rmii0_rxer
rmii0_crs
Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-104 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
表 5-104 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-104. Manual Functions Mapping for GMAC RMII0
BALL
BALL NAME
GMAC_RMII0_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
1
P5
R1
R2
P3
P4
RMII_MHZ_50_CLK
rgmii0_txd0
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
RMII_MHZ_50_CLK
2444
2453
2356
2415
804
981
847
993
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_crs
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-105 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
表 5-105 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-105. Manual Functions Mapping for GMAC RMII1
BALL
BALL NAME
GMAC_RMII1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
2
P5
T5
RMII_MHZ_50_CLK
rgmii0_txctl
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXCTL_IN
RMII_MHZ_50_CLK
2450
909
rmii1_rxd0
260
Specifications
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表 5-105. Manual Functions Mapping for GMAC RMII1 (continued)
BALL NAME
GMAC_RMII1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
2
T4
N6
N5
rgmii0_txc
uart3_txd
uart3_rxd
2327
2553
1943
926
443
CFG_RGMII0_TXC_IN
CFG_UART3_TXD_IN
CFG_UART3_RXD_IN
rmii1_rxd1
rmii1_rxer
rmii1_crs
1110
5.10.6.19.4 GMAC RGMII Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-106, 表 5-107 and 图 5-71 present timing requirements for receive RGMIIn operation.
表 5-106. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX UNIT
1
tc(RXC)
Cycle time, rgmiin_rxc
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(RXCH)
tw(RXCL)
tt(RXC)
Pulse duration, rgmiin_rxc high
Pulse duration, rgmiin_rxc low
Transition time, rgmiin_rxc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-107. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before
rgmiin_rxc high/low
RGMII0/1
1
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after
rgmiin_rxc high/low
RGMII0/1
1
ns
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(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
1
4
2
4
3
rgmiin_rxc(A)
5
1st Half-byte
2nd Half-byte
6
rgmiin_rxd[3:0](B)
rgmiin_rxctl(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
SPRS906_TIMING_GMAC_RGMIIRX_08
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
图 5-71. GMAC Receive Interface Timing, RGMIIn operation
表 5-108, 表 5-109 and 图 5-72 present switching characteristics for transmit - RGMIIn for
10/100/1000Mbit/s.
表 5-108. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX UNIT
1
tc(TXC)
Cycle time, rgmiin_txc
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-109. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
5
tosu(TXD-TXC)
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
262
Specifications
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表 5-109. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
(1) (continued)
NO. PARAMETER
toh(TXC-TXD)
DESCRIPTION
MODE
MIN
MAX UNIT
6
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
1
4
2
4
3
rgmiin_txc(A)
[internal delay enabled]
5
rgmiin_txd[3:0](B)
rgmiin_txctl(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
6
SPRS906_TIMING_GMAC_RGMIITX_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
图 5-72. GMAC Transmit Interface Timing RGMIIn operation
In 表 5-110 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
表 5-110. GMAC RGMII IOSETs
SIGNALS
IOSET3
IOSET4
BALL
MUX
GMAC RGMII1
BALL
MUX
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
rgmii1_rxctl
rgmii1_txc
C11
B12
A12
A13
B13
E13
C13
D13
F11
B11
D11
3
3
3
3
3
3
3
3
3
3
3
rgmii1_txctl
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表 5-110. GMAC RGMII IOSETs (continued)
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
rgmii1_rxc
E11
3
GMAC RGMII0
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii0_txc
P4
P3
R2
R1
N1
P1
N3
N4
T4
P2
N2
T5
0
0
0
0
0
0
0
0
0
0
0
0
rgmii0_rxctl
rgmii0_rxc
rgmii0_txctl
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
264
Specifications
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Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See 表 5-30 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-111 Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.
表 5-111 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-111. Manual Functions Mapping for GMAC RGMII0
BALL
BALL NAME
GMAC_RGMII0_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
N2
P2
N4
N3
P1
N1
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
413
27
3
0
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
2296
1721
1786
1966
2057
134
40
0
T4
T5
R1
R2
P3
P4
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
0
0
0
0
0
0
60
60
60
0
CFG_RGMII0_TXC_OUT
CFG_RGMII0_TXCTL_OUT
CFG_RGMII0_TXD0_OUT
CFG_RGMII0_TXD1_OUT
CFG_RGMII0_TXD2_OUT
CFG_RGMII0_TXD3_OUT
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
60
120
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Manual IO Timings Modes must be used to ensure some IO timings for GMAC. See 表 5-30 Modes Summary for a list of IO timings requiring the
use of Manual IO Timings Modes. See 表 5-112 Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.
表 5-112 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-112. Manual Functions Mapping for GMAC RGMII1
BALL
BALL NAME
GMAC_RGMII1_MANUAL1
CFG REGISTER
MUXMODE
3
A_DELAY (ps)
G_DELAY (ps)
E11
F11
B13
E13
C13
D13
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
530
71
0
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
1099
1337
1517
1331
1328
142
114
171
0
B11
D11
C11
B12
A12
A13
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
0
170
150
0
0
0
0
0
0
0
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
60
60
266
Specifications
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5.10.6.20 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO)
注
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
5.10.6.20.1 MMC1—SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
•
•
•
•
•
•
•
Default speed, 4-bit data, SDR, half-cycle
High speed, 4-bit data, SDR, half-cycle
SDR12, 4-bit data, half-cycle
SDR25, 4-bit data, half-cycle
UHS-I SDR50, 4-bit data, half-cycle
UHS-I SDR104, 4-bit data, half-cycle
UHS-I DDR50, 4-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
5.10.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
表 5-113 and 表 5-114 present Timing requirements and Switching characteristics for MMC1 - Default
Speed in receiver and transmitter mode (see 图 5-73 and 图 5-74).
表 5-113. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
DSSD5 tsu(cmdV-clkH)
DSSD6 th(clkH-cmdV)
DSSD7 tsu(dV-clkH)
DSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
20.46
5.11
ns
ns
20.46
ns
表 5-114. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DSSD0 fop(clk)
DSSD1 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5 × P-
(1)
0.185
DSSD2 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
DSSD3 td(clkL-cmdV)
DSSD4 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
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(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
mmc1_cmd
DSSD6
DSSD5
DSSD8
DSSD7
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_01
图 5-73. MMC/SD/SDIO in - Default Speed - Receiver Mode
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD3
DSSD4
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_02
图 5-74. MMC/SD/SDIO in - Default Speed - Transmitter Mode
5.10.6.20.1.2 High speed, 4-bit data, SDR, half-cycle
表 5-115 and 表 5-116 present Timing requirements and Switching characteristics for MMC1 - High Speed
in receiver and transmitter mode (see 图 5-75 and 图 5-76).
表 5-115. Timing Requirements for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
HSSD3 tsu(cmdV-clkH)
HSSD4 th(clkH-cmdV)
HSSD7 tsu(dV-clkH)
HSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
ns
ns
ns
表 5-116. Switching Characteristics for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HSSD1 fop(clk)
HSSD2H tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5 × P-
(1)
0.185
HSSD2L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
HSSD5 td(clkL-cmdV)
HSSD6 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-7.6
-7.6
3.6
3.6
ns
ns
268
Specifications
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(1) P = output mmc1_clk period in ns
HSSD1
HSSD2H
HSSD4
HSSD2L
mmc1_clk
mmc1_cmd
HSSD3
HSSD7
HSSD8
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_03
图 5-75. MMC/SD/SDIO in - High Speed - Receiver Mode
HSSD1
HSSD2H
HSSD2L
HSSD5
mmc1_clk
mmc1_cmd
HSSD5
HSSD6
HSSD6
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_04
图 5-76. MMC/SD/SDIO in - High Speed - Transmitter Mode
5.10.6.20.1.3 SDR12, 4-bit data, half-cycle
表 5-117 and 表 5-118 present Timing requirements and Switching characteristics for MMC1 - SDR12 in
receiver and transmitter mode (see 图 5-77 and 图 5-78).
表 5-117. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR12 tsu(cmdV-clkH)
5
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
25.99
ns
SDR12 th(clkH-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
ns
Internal Loopback Clock
SDR12 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
25.99
SDR12 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 5-118. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5 × P-
(1)
0.185
SDR122 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185(1)
ns
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
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(1) P = output mmc1_clk period in ns
SDR122
SDR121
SDR120
mmc1_clk
mmc1_cmd
SDR126
SDR125
SDR128
SDR127
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_05
图 5-77. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
SDR122
SDR121
SDR120
SDR123
SDR124
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_06
图 5-78. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
5.10.6.20.1.4 SDR25, 4-bit data, half-cycle
表 5-119 and 表 5-120 present Timing requirements and Switching characteristics for MMC1 - SDR25 in
receiver and transmitter mode (see 图 5-79 and 图 5-80).
表 5-119. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR25 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
5.3
ns
SDR25 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
5.3
ns
ns
SDR25 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
SDR25 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 5-120. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR252L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
ns
(1)
SDR255 td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
270
Specifications
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表 5-120. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR256 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmc1_clk
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
图 5-79. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
HSSDR255
SDR256
mmc1_clk
mmc1_cmd
SDR255
SDR256
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_08
图 5-80. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
5.10.6.20.1.5 UHS-I SDR50, 4-bit data, half-cycle
表 5-121 and 表 5-122 present Timing requirements and Switching characteristics for MMC1 - SDR50 in
receiver and transmitter mode (see 图 5-81 and 图 5-82).
表 5-121. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR50 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
1.48
ns
SDR50 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.7
ns
ns
SDR50 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
1.48
SDR50 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.7
1.6
ns
ns
Internal Loopback Clock
表 5-122. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
96
SDR502 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR502L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
ns
-3.66
1.46
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(1) P = output mmc1_clk period in ns
SDR501
SDR502L
SDR502H
mmc1_clk
mmc1_cmd
SDR504
SDR508
SDR503
SDR507
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_09
图 5-81. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmc1_clk
mmc1_cmd
SDR505
SDR506
SDR506
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_10
图 5-82. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
5.10.6.20.1.6 UHS-I SDR104, 4-bit data, half-cycle
表 5-123 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and
transmitter mode (see 图 5-83 and 图 5-84).
表 5-123. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR1041 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
192
SDR1042 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR1042 tw(clkL)
L
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
SDR1045 td(clkL-cmdV)
SDR1046 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-1.09
-1.09
0.49
0.49
ns
ns
(1) P = output mmc1_clk period in ns
SDR1041
SDR1042L
SDR1042H
SDR1044
mmc1_clk
mmc1_cmd
SDR1043
SDR1047
SDR1048
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_11
图 5-83. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
272
Specifications
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SDR1041
SDR1042H
SDR1042L
SDR1045
mmc1_clk
SDR1045
mmc1_cmd
SDR1046
SDR1046
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_12
图 5-84. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
5.10.6.20.1.7 UHS-I DDR50, 4-bit data
表 5-124 and 表 5-125 present Timing requirements and Switching characteristics for MMC1 - DDR50 in
receiver and transmitter mode (see 图 5-85 and 图 5-86).
表 5-124. Timing Requirements for MMC1 - SD Card DDR50 Mode
PARAME
NO.
DESCRIPTION
MODE
MIN
MAX UNIT
TER
DDR50 tsu(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk
transition
1.79
ns
5
DDR50 th(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition
6
2
ns
DDR50 tsu(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
Pad Loopback
1.79
1.79
2
ns
ns
ns
ns
Internal Loopback
Pad Loopback
DDR50 th(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
Internal Loopback
1.6
表 5-125. Switching Characteristics for MMC1 - SD Card DDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DDR500 fop(clk)
DDR501 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5 × P-
(1)
0.185
DDR502 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
DDR503 td(clk-cmdV)
DDR504 td(clk-dV)
Delay time, mmc1_clk transition to mmc1_cmd transition
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
1.225
1.225
6.6
6.6
ns
ns
(1) P = output mmc1_clk period in ns
DDR500
DDR501
DDR502
mmc1_clk
DDR505
DDR506
mmc1_cmd
DDR507
DDR508
DDR507
DDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_13
图 5-85. SDMMC - High Speed SD - DDR - Data/Command Receive
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DDR500
DDR501
DDR502
mmc1_clk
DDR503(max)
DDR503(min)
mmc1_cmd
DDR504(max)
DDR504(min)
DDR504(max)
DDR504(min)
mmc1_dat[3:0]
MMC1_14
图 5-86. SDMMC - High Speed SD - DDR - Data/Command Transmit
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to ensure some IO timings for MMC1. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-126 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
表 5-126 presents the values for DELAYMODE bitfield.
表 5-126. Virtual Functions Mapping for MMC1
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
MMC1_
MMC1_
MMC1_
MMC1_
VIRTUAL1
VIRTUAL4
VIRTUAL5
VIRTUAL6
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
15
15
15
15
15
15
12
12
12
12
12
12
11
11
11
11
11
11
10
10
10
10
10
10
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for MMC1. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-127 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
表 5-127 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
274
Specifications
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表 5-127. Manual Functions Mapping for MMC1
BALL
BALL NAME
MMC1_MANUAL1
MMC1_MANUAL2
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
588
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
CFG_MMC1_CLK_IN
CFG_MMC1_CMD_IN
CFG_MMC1_DAT0_IN
CFG_MMC1_DAT1_IN
CFG_MMC1_DAT2_IN
CFG_MMC1_DAT3_IN
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1000
1375
1000
1000
1000
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1230
0
0
0
0
0
0
0
520
0
320
0
CFG_MMC1_CLK_OUT
CFG_MMC1_CMD_OUT
CFG_MMC1_DAT0_OUT
CFG_MMC1_DAT1_OUT
CFG_MMC1_DAT2_OUT
CFG_MMC1_DAT3_OUT
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
56
76
91
99
40
83
98
106
0
0
0
0
V4
V3
V2
W1
V1
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
0
0
0
0
0
0
0
0
0
0
51
0
0
0
0
0
0
CFG_MMC1_CMD_OEN
CFG_MMC1_DAT0_OEN
CFG_MMC1_DAT1_OEN
CFG_MMC1_DAT2_OEN
CFG_MMC1_DAT3_OEN
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
363
199
273
5.10.6.20.2 MMC2 — eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
•
•
•
•
Standard JC64 SDR, 8-bit data, half cycle
High-speed JC64 SDR, 8-bit data, half cycle
High-speed HS200 JEDS84, 8-bit data, half cycle
High-speed JC64 DDR, 8-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
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5.10.6.20.2.1 Standard JC64 SDR, 8-bit data, half cycle
表 5-128 and 表 5-129 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter mode (see
图 5-87 and 图 5-88).
表 5-128. Timing Requirements for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
13.19
8.4
MAX
UNIT
ns
SSDR5
SSDR6
SSDR7
SSDR8
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
13.19
8.4
ns
th(clkH-dV)
ns
276
Specifications
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表 5-129. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SSDR1 fop(clk)
SSDR2H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
24
0.5 × P-
(1)
0.172
SSDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
SSDR3 td(clkL-cmdV)
SSDR4 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-16.96
-16.96
16.96
16.96
ns
ns
(1) P = output mmc2_clk period in ns
SSDR2
SSDR1
SSDR2
mmc2_clk
SSDR6
SSDR8
SSDR5
mmc2_cmd
SSDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_01
图 5-87. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
SSDR2
SSDR1
SSDR3
SSDR4
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_02
图 5-88. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
5.10.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
表 5-130 and 表 5-131 present Timing requirements and Switching characteristics for MMC2 - High speed
SDR in receiver and transmitter mode (see 图 5-89 and 图 5-90).
表 5-130. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.6
2.6
5.6
2.6
MAX
UNIT
ns
JC643 tsu(cmdV-clkH)
JC644 th(clkH-cmdV)
JC647 tsu(dV-clkH)
JC648 th(clkH-dV)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
ns
ns
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表 5-131. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
JC641 fop(clk)
JC642H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
48
0.5 × P-
(1)
0.172
JC642L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
JC645 td(clkL-cmdV)
JC646 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-6.64
-6.64
6.64
6.64
ns
ns
(1) P = output mmc2_clk period in ns
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC643
JC644
JC647
JC648
SPRS906_TIMING_MMC2_03
图 5-89. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC645
JC645
JC646
JC646
MMC2_04
图 5-90. MMC/SD/SDIO in - High Speed JC64 - transmitter Mode
5.10.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
表 5-132 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see 图 5-91).
278
Specifications
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表 5-132. Switching Characteristics for MMC2 - JEDS84 HS200 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HS2001 fop(clk)
HS2002H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
192
0.5 × P-
(1)
0.172
HS2002L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
HS2005 td(clkL-cmdV)
HS2006 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-1.136
-1.136
0.536
0.536
ns
ns
(1) P = output mmc2_clk period in ns
HS2001
HS2002H
HS2002L
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
HS2005
HS2006
HS2005
HS2006
MMC2_05
图 5-91. eMMC in - HS200 SDR - Transmitter Mode
5.10.6.20.2.4 High-speed JC64 DDR, 8-bit data
表 5-133 and 表 5-134 present Timing requirements and Switching characteristics for MMC2 - High speed
DDR in receiver and transmitter mode (see 图 5-92 and 图 5-93).
表 5-133. Timing Requirements for MMC2 - JC64 High Speed DDR Mode
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
DDR3 tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk
transition
1.8
ns
DDR4 th(clk-cmdV)
DDR7 tsu(dV-clk)
DDR8 th(clk-dV)
Hold time, mmc2_cmd valid after mmc2_clk
transition
1.6
1.8
ns
ns
ns
ns
ns
ns
ns
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
Hold time, mmc2_dat[7:0] valid after mmc2_clk
transition
Pad Loopback (1.8V and 3.3V),
Boot
1.6
Internal Loopback (1.8V with
MMC2_VIRTUAL2)
1.86
1.95
Internal Loopback (3.3V with
MMC2_VIRTUAL2)
Internal Loopback (1.8V with
MMC2_MANUAL2)
Internal Loopback (3.3V with
MMC2_MANUAL2)
1.6
表 5-134. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DDR1
fop(clk)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
48
DDR2H tw(clkH)
0.5 × P-
(1)
0.172
DDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
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表 5-134. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
NO.
PARAMETER
td(clk-cmdV)
td(clk-dV)
DESCRIPTION
MIN
2.9
MAX
7.14
7.14
UNIT
ns
DDR5
DDR6
Delay time, mmc2_clk transition to mmc2_cmd transition
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
2.9
ns
(1) P = output mmc2_clk period in ns
DDR1
DDR2H
DDR2L
DDR3
mmc2_clk
DDR4
mmc2_cmd
DDR8
DDR8
DDR8
DDR7
DDR7
DDR7
DDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_07
图 5-92. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
DDR1
DDR2
DDR2
DDR5
mmc2_clk
DDR5
DDR5
DDR5
mmc2_cmd
DDR6
DDR6
DDR6
DDR6
DDR6
DDR6
mmc2_dat[7:0]
MMC2_08
图 5-93. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to ensure some IO timings for MMC2. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-135 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
表 5-135 presents the values for DELAYMODE bitfield.
表 5-135. Virtual Functions Mapping for MMC2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MMC2_VIRTUAL2
A6
A4
gpmc_cs1
gpmc_a19
13
13
mmc2_cmd
mmc2_dat4
280
Specifications
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表 5-135. Virtual Functions Mapping for MMC2 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MMC2_VIRTUAL2
E7
D6
C5
B5
D7
C6
A5
B6
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
13
13
13
13
13
13
13
13
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_clk
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for MMC2. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-136 Manual
Functions Mapping for MMC2 for a definition of the Manual modes.
表 5-136 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-136. Manual Functions Mapping for MMC2
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
(ps)
(ps)
A4
E7
D6
C5
B5
D7
C6
A5
B6
A6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CFG_GPMC_A19_IN mmc2_dat4
CFG_GPMC_A20_IN mmc2_dat5
CFG_GPMC_A21_IN mmc2_dat6
CFG_GPMC_A22_IN mmc2_dat7
119
0
0
127
22
72
410
82
0
0
0
0
18
894
30
0
0
0
0
4000
CFG_GPMC_A23_IN
mmc2_clk
0
0
0
0
0
0
CFG_GPMC_A24_IN mmc2_dat0
CFG_GPMC_A25_IN mmc2_dat1
CFG_GPMC_A26_IN mmc2_dat2
CFG_GPMC_A27_IN mmc2_dat3
CFG_GPMC_CS1_IN mmc2_cmd
0
23
0
0
77
0
0
0
0
0
A4
E7
D6
C5
B5
D7
C6
A5
B6
A6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
152
206
78
2
0
0
0
0
0
0
0
0
0
0
152
206
78
2
0
0
0
0
0
0
0
0
0
0
285
189
0
0
0
CFG_GPMC_A19_OUT mmc2_dat4
CFG_GPMC_A20_OUT mmc2_dat5
CFG_GPMC_A21_OUT mmc2_dat6
CFG_GPMC_A22_OUT mmc2_dat7
CFG_GPMC_A23_OUT mmc2_clk
CFG_GPMC_A24_OUT mmc2_dat0
CFG_GPMC_A25_OUT mmc2_dat1
CFG_GPMC_A26_OUT mmc2_dat2
CFG_GPMC_A27_OUT mmc2_dat3
CFG_GPMC_CS1_OUT mmc2_cmd
120
70
360
0
0
266
0
266
0
730
0
0
0
0
0
43
0
43
0
70
0
0
0
0
0
0
120
A4
gpmc_a19
0
0
0
0
0
0
CFG_GPMC_A19_OEN mmc2_dat4
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表 5-136. Manual Functions Mapping for MMC2 (continued)
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
0
(ps)
231
39
(ps)
0
E7
D6
C5
D7
C6
A5
B6
A6
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
CFG_GPMC_A20_OEN mmc2_dat5
CFG_GPMC_A21_OEN mmc2_dat6
CFG_GPMC_A22_OEN mmc2_dat7
CFG_GPMC_A24_OEN mmc2_dat0
CFG_GPMC_A25_OEN mmc2_dat1
CFG_GPMC_A26_OEN mmc2_dat2
CFG_GPMC_A27_OEN mmc2_dat3
0
0
0
0
0
0
0
0
0
91
0
0
0
0
0
176
0
0
0
0
0
0
0
0
0
0
0
101
0
0
0
0
0
0
0
0
0
0
0
360
0
CFG_GPMC_CS1_OE mmc2_cmd
N
5.10.6.20.3 MMC3 and MMC4—SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
•
•
•
MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
•
•
MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
MMC3 8-bit data, UHS-I SDR50
注
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
注
For more information, see the MMC/SDIO chapter of the Device TRM.
5.10.6.20.3.1 MMC3 and MMC4, SD Default Speed
图 5-94 , 图 5-95, and 表 5-137 through 表 5-140 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
(1)
表 5-137. Timing Requirements for MMC3 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 7
(2)
表 5-138. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5 × P-
(1)
0.270
282
Specifications
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(2)
表 5-138. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DS2
tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-139. Timing Requirements for MMC4 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 3
(2)
表 5-140. Switching Characteristics for MMC4 - Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5 × P-
(1)
0.270
DS2
tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmcj_clk
mmcj_cmd
DS6
DS5
DS8
DS7
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_07
图 5-94. MMC/SD/SDIOj in - Default Speed - Receiver Mode
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DS2
DS1
DS0
mmcj_clk
DS3
mmcj_cmd
DS4
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_08
图 5-95. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
5.10.6.20.3.2 MMC3 and MMC4, SD High Speed
图 5-96, 图 5-97, and 表 5-141 through 表 5-144 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter mode.
(1)
表 5-141. Timing Requirements for MMC3 - SD/SDIO High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 7
(2)
表 5-142. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
HS2H
0.5 × P-
(1)
0.270
HS2L
tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-7.6
-7.6
3.6
3.6
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-143. Timing Requirements for MMC4 - High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 3
(2)
表 5-144. Switching Characteristics for MMC4 - High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
48
HS2H
Pulse duration, mmc4_clk high
0.5 × P-
(1)
0.270
284
Specifications
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(2)
表 5-144. Switching Characteristics for MMC4 - High Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HS2L
tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS4
HS3
HS7
HS8
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_09
图 5-96. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS5
HS5
HS6
HS6
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_10
图 5-97. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmitter Mode
5.10.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
图 5-98, 图 5-99, and 表 5-145, through 表 5-148 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
(1)
表 5-145. Timing Requirements for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 5-146. Switching Characteristics for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5 × P-
(1)
0.270
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(2)
表 5-146. Switching Characteristics for MMC3 - SDR12 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR122 tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-147. Timing Requirements for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) j in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 5-148. Switching Characteristics for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5 × P-
(1)
0.270
SDR122 tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
SDR125 td(clkL-cmdV)
SDR126 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
SDR122
SDR121
SDR120
mmcj_clk
mmcj_cmd
SDR126
SDR125
SDR128
SDR127
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_11
图 5-98. MMC/SD/SDIOj in - SDR12 - Receiver Mode
286
Specifications
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SDR122
SDR121
SDR120
mmcj_clk
SDR123
SDR124
mmcj_cmd
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_12
图 5-99. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
5.10.6.20.3.4 MMC3 and MMC4, SD SDR25 Mode
图 5-100, 图 5-101, and 表 5-149, through 表 5-152 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
(1)
表 5-149. Timing Requirements for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR253 tsu(cmdV-clkH)
SDR254 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
ns
ns
(2)
表 5-150. Switching Characteristics for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.270
SDR252L tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-151. Timing Requirements for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR255 tsu(cmdV-clkH)
SDR256 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
ns
(2)
表 5-152. Switching Characteristics for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.270
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(2)
表 5-152. Switching Characteristics for MMC4 - SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR252L tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmcj_clk
mmcj_cmd
SDR257
SDR258
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_13
图 5-100. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
SDR255
mmcj_clk
mmcj_cmd
SDR255
SDR256
SDR256
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_14
图 5-101. MMC/SD/SDIOj in - SDR25 - Transmitter Mode
5.10.6.20.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
图 5-102, 图 5-103, 表 5-153, and 表 5-154 present Timing requirements and Switching characteristics for
MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
(1)
表 5-153. Timing Requirements for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
1.48
1.6
MAX
UNIT
ns
SDR503 tsu(cmdV-clkH)
SDR504 th(clkH-cmdV)
SDR507 tsu(dV-clkH)
SDR508 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
1.48
1.6
ns
ns
(2)
表 5-154. Switching Characteristics for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
64
SDR502 tw(clkH)
H
0.5 × P-
(1)
0.270
SDR502L tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
288
Specifications
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(2)
表 5-154. Switching Characteristics for MMC3 - SDR50 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
-3.66
-3.66
MAX
1.46
1.46
UNIT
ns
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
SDR501
SDR502L
SDR502H
SDR504
mmcj_clk
mmcj_cmd
SDR503
SDR507
SDR508
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_05
图 5-102. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmcj_clk
mmcj_cmd
SDR505
SDR506
SDR506
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_06
图 5-103. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for MMC3. See 表 5-30 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-155 Manual
Functions Mapping for MMC3 for a definition of the Manual modes.
表 5-155 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-155. Manual Functions Mapping for MMC3
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
Y2
Y2
Y1
Y1
Y1
Y4
mmc3_clk
mmc3_clk
1085
1269
0
21
0
CFG_MMC3_CLK_IN
CFG_MMC3_CLK_OUT
CFG_MMC3_CMD_IN
CFG_MMC3_CMD_OEN
CFG_MMC3_CMD_OUT
CFG_MMC3_DAT0_IN
mmc3_clk
mmc3_clk
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
0
128
98
0
0
0
0
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表 5-155. Manual Functions Mapping for MMC3 (continued)
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
Y4
Y4
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
362
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_MMC3_DAT0_OEN
CFG_MMC3_DAT0_OUT
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT1_OEN
CFG_MMC3_DAT1_OUT
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT2_OEN
CFG_MMC3_DAT2_OUT
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT3_OEN
CFG_MMC3_DAT3_OUT
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT4_OEN
CFG_MMC3_DAT4_OUT
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT5_OEN
CFG_MMC3_DAT5_OUT
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT6_OEN
CFG_MMC3_DAT6_OUT
CFG_MMC3_DAT7_IN
CFG_MMC3_DAT7_OEN
CFG_MMC3_DAT7_OUT
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
AA2
AA2
AA2
AA3
AA3
AA3
W2
7
333
0
0
402
0
203
549
1
W2
W2
Y3
121
440
206
336
283
174
320
443
0
Y3
Y3
AA1
AA1
AA1
AA4
AA4
AA4
AB1
AB1
AB1
2
344
0
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
5.10.6.21 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
•
Wake-up request generation in idle mode upon the detection of external events
注
For more information, see the General-Purpose Interface chapter of the Device TRM.
290
Specifications
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注
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
5.10.6.22 PRU-ICSS
The device Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-
ICSS) consists of dual 32-bit Load / Store RISC CPU cores - Programmable Real-Time Units (PRU0 and
PRU1), shared, data, and instruction memories, internal peripheral modules, and an interrupt controller
(PRU-ICSS_INTC). The programmable nature of the PRUs, along with their access to pins, events and all
SoC resources, provides flexibility in implementing fast real-time responses, specialized data handling
operations, customer peripheral interfaces, and in off-loading tasks from the other processor cores of the
system-on-chip (SoC).
The each PRU-ICSS includes the following main features:
•
21x Enhanced GPIs (EGPIs) and 21x Enhanced GPOs (EGPOs) with asynchronous capture and serial
support per each PRU CPU core
•
One Ethernet MII_RT module (PRU-ICSS_MII_RT) with two MII ports and configurable connections to
PRUs
•
•
•
•
•
•
•
•
•
1 MDIO Port (PRU-ICSS_MII_MDIO)
One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
1 x 16550-compatible UART with a dedicated 192 MHz clock to support 12Mbps Profibus
1 Industrial Ethernet timer with 7/9 capture and 8 compare events
1 Enhanced Capture Module (ECAP)
1 Interrupt Controller (PRU-ICSS_INTC)
A flexible power management support
Integrated switched central resource with programmable priority
Parity control supported by all memories
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in the 表 5-178 and 表 5-179.
注
For more information about PRU-ICSS subsystems interfaces, please see the Device TRM.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-31 and described in Device TRM, Control
Module Chapter.
5.10.6.22.1 Programmable Real-Time Unit (PRU-ICSS PRU)
5.10.6.22.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
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表 5-156. PRU-ICSS PRU Timing Requirements - Direct Input Mode
NO.
1
PARAMETER
tw(GPI)
DESCRIPTION
MIN
2 × P (1)
MAX
UNIT
ns
Pulse width, GPI
2
tsk(GPI)
Skew between GPI[20:0] signals
4.5
ns
(1) ICSS_CLK clock period
1
GPI[m:0]
2
SPRS91x_TIMING_PRU_01
图 5-104. PRU-ICSS PRU Direct Input Timing
(1) m in GPI[m:0] = 20
表 5-157. PRU-ICSS PRU Switching Requirements – Direct Output Mode
NO.
1
PARAMETER
tw(GPO)
DESCRIPTION
MIN
2 × P (1)
MAX
UNIT
ns
Pulse width, GPO
2
tsk(GPO)
Skew between GPO[20:0] signals
4.5
ns
(1) ICSS_CLK clock period
1
GPO[n:0]
2
SPRS91x_TIMING_PRU_02
图 5-105. PRU-ICSS PRU Direct Output Timing
(1) n in GPO[n:0] = 20
5.10.6.22.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
表 5-158. PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
NO.
1
PARAMETER
tw(CLOCKIN)
DESCRIPTION
MIN
20
9
MAX
UNIT
ns
Cyle time, CLOCKIN
2
tw(CLOCKIN_L)
Pulse duration, CLOCKIN low
Pulse duration, CLOCKIN high
Setup time, DATAIN valid before CLOCKIN
Hold time, DATAIN valid after CLOCKIN
11
11
ns
3
tw(CLOCKIN_H)
9
ns
4
tsu(DATAIN-CLOCKIN)
th(CLOCKIN-DATAIN)
4.5
0
ns
5
ns
1
3
2
CLOCKIN
DATAIN
5
4
SPRS91x_TIMING_PRU_03
图 5-106. PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode
292
Specifications
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1
3
2
CLOCKIN
DATAIN
5
4
SPRS91x_TIMING_PRU_04
图 5-107. PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode
5.10.6.22.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
表 5-159. PRU-ICSS PRU Timing Requirements – Shift In Mode
NO.
1
PARAMETER
tc(DATAIN)
DESCRIPTION
MIN
MAX
UNIT
ns
Cycle time, DATAIN
Pulse width, DATAIN
10.00
2
tw(DATAIN)
0.45 × P
ns
(1)
(1) P = 10.00ns
1
2
DATAIN
SPRS91x_TIMING_PRU_05
图 5-108. PRU-ICSS PRU Shift In Timing
表 5-160. PRU-ICSS PRU Switching Requirements - Shift Out Mode
NO.
1
PARAMETER
tc(CLOCKOUT)
tw(CLOCKOUT)
DESCRIPTION
MIN
MAX
UNIT
ns
Cycle time, CLOCKOUT
Pulse width, CLOCKOUT
10.00
2
0.45 × P
ns
(1)
3
td(CLOCKOUT-DATAOUT)
Delay time, CLOCKOUT to DATAOUT Valid
-3.00
3.60
ns
(1) P = 10.00ns
1
2
CLOCKOUT
DATAOUT
3
SPRS91x_TIMING_PRU_06
图 5-109. PRU-ICSS PRU Shift Out Timing
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5.10.6.22.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
表 5-161. PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
NO.
1
PARAMETER
DESCRIPTION
Pulse width, SDx_CLK
MIN
MAX
UNIT
ns
tw(SDx_CLK)
20
10
5
2
tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge
th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge
ns
3
ns
1
SDx_CLK
SDx_D
2
3
SPRS91x_TIMING_PRU_07
图 5-110. PRU-ICSS PRU SD_CLK Falling Active Edge
1
SDx_CLK
SDx_D
2
3
SPRS91x_TIMING_PRU_08
图 5-111. PRU-ICSS PRU SD_CLK Rising Active Edge
表 5-162. PRU-ICSS PRU Timing Requirements - EnDAT Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
MAX
UNIT
1
tw(ENDATx_IN)
Pulse width, ENDATx_IN
40
ns
表 5-163. PRU-ICSS PRU Switching Requirements - EnDAT Mode
NO.
2
PARAMETER
DESCRIPTION
MIN
UNIT
ns
tw(ENDATx_CLK)
Pulse width, ENDATx_CLK
20
3
td(ENDATx_OUT-
ENDATx_CLK)
Delay time, ENDATx_CLK fall to ENDATx_OUT
-10
10
10
ns
4
td(ENDATx_OUT_EN- Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN
ENDATx_CLK)
-10
ns
294
Specifications
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ENDATx_IN
1
2
ENDATx_CLK
ENDATx_OUT
3
4
ENDATx_OUT_EN
SPRS91x_TIMING_PRU_09
图 5-112. PRU-ICSS PRU EnDAT Timing
5.10.6.22.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
5.10.6.22.2.1 PRU-ICSS ECAT Electrical Data and Timing
表 5-164. PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
NO.
1
PARAMETER
DESCRIPTION
MIN
100.00
20.00
MAX
UNIT
ns
tw(EDIO_LATCH_IN)
Pulse width, EDIO_LATCH_IN
2
tsu(EDIO_DATA_IN-
EDIO_LATCH_IN)
th(EDIO_LATCH_IN-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN active
edge
ns
3
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active edge
20.00
ns
EDIO_LATCH_IN
1
2
3
EDIO_DATA_IN[7:0]
SPRS91x_TIMING_PRU_ECAT_01
图 5-113. PRU-ICSS ECAT Input Validated with LATCH_IN Timing
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表 5-165. PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
NO.
1
PARAMETER
DESCRIPTION
MIN
100.00
20.00
MAX
UNIT
ns
tw(EDC_SYNCx_OUT)
Pulse width, EDC_SYNCx_OUT
2
tsu(EDIO_DATA_IN-
EDC_SYNCx_OUT)
th(EDC_SYNCx_OUT-
EDIO_DATA_IN)
Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active
edge
ns
3
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge
20.00
ns
EDC_SYNCx_OUT
1
2
3
EDIO_DATA_IN[7:0]
SPRS91x_TIMING_PRU_ECAT_02
图 5-114. PRU-ICSS ECAT Input Validated With SYNCx Timing
表 5-166. PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
NO.
1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
tw(EDIO_SOF)
Pulse duration, EDIO_SOF
4 × P (1) 5 × P (1)
2
tsu(EDIO_DATA_IN-
EDIO_SOF)
Setup time, EDIO_DATA_IN valid before EDIO_SOF active edge
20.00
ns
3
th(EDIO_SOF-
EDIO_DATA_IN)
Hold time, EDIO_DATA_IN valid after EDIO_SOF active edge
20.00
ns
(1) ICSS_IEP_CLK clock period
EDIO_SOF
1
2
3
EDIO_DATA_IN[7:0]
SPRS91x_TIMING_PRU_ECAT_03
图 5-115. PRU-ICSS ECAT Input Validated With SOF
表 5-167. PRU-ICSS ECAT Timing Requirements - LATCHx_IN
NO.
PARAMETER
DESCRIPTION
MIN
3 × P (1)
MAX
UNIT
1
tw(EDC_LATCHx_IN)
Pulse duration, EDC_LATCHx_IN
ns
296
Specifications
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(1) ICSS_IEP_CLK clock period
EDC_LATCHx_IN
1
SPRS91x_TIMING_PRU_ECAT_04
图 5-116. PRU-ICSS ECAT LATCHx_IN Timing
表 5-168. PRU-ICSS ECAT Switching Requirements - Digital IOs
NO.
1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
tw(EDIO_OUTVALID)
Pulse duration, EDIO_OUTVALID
14 × P (1) 32 × P (1)
0.00 18 × P (1)
2
td(EDIO_OUTVALID-
EDIO_DATA_OUT)
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
ns
1
tsk(EDIO_DATA_OUT)
EDIO_DATA_OUT skew
8
ns
(1) ICSS_IEP_CLK clock period
5.10.6.22.3 PRU-ICSS MII_RT and Switch
5.10.6.22.3.1 PRU-ICSS MDIO Electrical Data and Timing
表 5-169. PRU-ICSS MDIO Timing Requirements – MDIO_DATA
NO.
1
PARAMETER
tsu(MDIO-MDC)
th(MDIO-MDC)
DESCRIPTION
MIN
90
0
MAX
UNIT
ns
Setup time, MDIO valid before MDC high
Hold time, MDIO valid from MDC high
2
ns
1
2
MDIO_CLK (Output)
MDIO_DATA (Input)
SPRS91x_TIMING_PRU_MII_RT_01
图 5-117. PRU-ICSS MDIO_DATA Timing - Input Mode
表 5-170. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
NO.
1
PARAMETER
tc(MDC)
DESCRIPTION
MIN
MAX
UNIT
Cycle time, MDC
400
160
160
ns
ns
ns
ns
2
tw(MDCH)
tw(MDCL)
tt(MDC)
Pulse duration, MDC high
Pulse duration, MDC low
Transition time, MDC
3
4
5
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1
4
2
3
MDIO_CLK
4
SPRS91x_TIMING_PRU_MII_RT_02
图 5-118. PRU-ICSS MDIO_CLK Timing
表 5-171. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
td(MDC-MDIO)
Delay time, MDC high to MDIO valid
0
390
ns
1
MDIO_CLK (Output)
MDIO_DATA (Output)
SPRS91x_TIMING_PRU_MII_RT_03
图 5-119. PRU-ICSS MDIO_DATA Timing – Output Mode
5.10.6.22.3.2 PRU-ICSS MII_RT Electrical Data and Timing
注
In order to ensure the MII_RT IO timing values published in the device data manual, the
ICSS_CLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY
bitfield in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6h (non-default value).
表 5-172. PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX UNIT
1
tc(RX_CLK)
Cycle time, RX_CLK
399.96 400.04
39.996 40.004
ns
ns
ns
ns
ns
ns
2
3
tw(RX_CLKH)
Pulse duration, RX_CLK high
Pulse duration, RX_CLK low
140
14
260
26
tw(RX_CLKL)
140
14
260
26
1
4
2
3
MII_RXCLK
4
SPRS91x_TIMING_PRU_MII_RT_04
图 5-120. PRU-ICSS MII[x]_RXCLK Timing
298
Specifications
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表 5-173. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX UNIT
1
tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Cycle time, TX_CLK
399.96 400.04
39.996 40.004
ns
ns
ns
ns
ns
ns
ns
ns
2
3
4
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
140
14
260
26
260
26
3
140
14
3
1
4
2
3
MII_TXCLK
4
SPRS91x_TIMING_PRU_MII_RT_05
图 5-121. PRU-ICSS MII[x]_TXCLK Timing
表 5-174. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
NO.
PARAMETER
tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
DESCRIPTION
SPEED
MIN
MAX UNIT
1
Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK
10 Mbps
8
ns
100 Mbps
10 Mbps
100 Mbps
8
8
8
ns
ns
ns
2
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
th(RX_CLK-RXD)
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
1
2
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
SPRS91x_TIMING_PRU_MII_RT_06
图 5-122. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
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MAX UNIT
表 5-175. PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
NO.
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
DESCRIPTION
SPEED
MIN
1
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid
10 Mbps
5
25
ns
100 Mbps
5
25
ns
1
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
SPRS91x_TIMING_PRU_MII_RT_07
图 5-123. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing
5.10.6.22.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
表 5-176. Timing Requirements for PRU-ICSS UART Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
1.05U(1)
UNIT
ns
(1)
3
tw(RX)
Pulse duration, receive start, stop, data bit
0.96U
(1) U = UART baud time = 1/programmed baud rate.
表 5-177. Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART
Transmit
NO.
1
PARAMETER
ƒbaud(baud)
tw(TX)
DESCRIPTION
MIN
MAX
12
U + 2(1)
UNIT
MHz
ns
Maximum programmable baud rate
Pulse duration, transmit start, stop, data bit
0
(1)
2
U - 2
(1) U = UART baud time = 1/programmed baud rate.
2
1
Start
Bit
UART_TXD
Data Bits
3
4
Start
Bit
UART_RXD
Data Bits
SPRS961_TIMING_UART_01
图 5-124. PRU-ICSS UART Timing
5.10.6.22.5 PRU-ICSS IOSETs
In 表 5-178 are presented the specific groupings of signals (IOSET) for use with PRU-ICSS1.
300
Specifications
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表 5-178. PRU-ICSS1 IOSETs
SIGNALS
IOSET1
MUX
PRU-ICSS 1
12
IOSET2
BALL
BALL
MUX
pr1_pru1_gpi20
pr1_pru1_gpi19
pr1_pru1_gpi18
pr1_pru1_gpi17
pr1_pru1_gpi16
pr1_pru1_gpi15
pr1_pru1_gpi14
pr1_pru1_gpi13
pr1_pru1_gpi12
pr1_pru1_gpi11
pr1_pru1_gpi10
pr1_pru1_gpo20
pr1_pru1_gpo19
pr1_pru1_gpo18
pr1_pru1_gpo17
pr1_pru1_gpo16
pr1_pru1_gpo15
pr1_pru1_gpo14
pr1_pru1_gpo13
pr1_pru1_gpo12
pr1_pru1_gpo11
pr1_pru1_gpo10
pr1_pru1_gpi9
pr1_pru1_gpi8
pr1_pru1_gpi7
pr1_pru1_gpi6
pr1_pru1_gpi5
pr1_pru1_gpi4
pr1_pru1_gpi3
pr1_pru1_gpi2
pr1_pru1_gpi1
pr1_pru1_gpi0
pr1_pru1_gpo9
pr1_pru1_gpo8
pr1_pru1_gpo7
pr1_pru1_gpo6
pr1_pru1_gpo5
pr1_pru1_gpo4
pr1_pru1_gpo3
pr1_pru1_gpo2
pr1_pru1_gpo1
pr1_pru1_gpo0
pr1_mii1_crs
D13
C13
E13
B13
F11
E11
A13
A12
B12
C11
D11
D13
C13
E13
B13
F11
E11
A13
A12
B12
C11
D11
B11
C10
D10
E10
B10
A10
F10
A11
A8
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
12
12
12
12
12
12
12
12
12
A9
12
B11
C10
D10
E10
B10
A10
F10
A11
A8
13
13
13
13
13
13
13
13
13
A9
13
D13
E13
C13
11
pr1_mii1_rxlink
pr1_mii1_col
11
11
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表 5-178. PRU-ICSS1 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
L5
MUX
11
BALL
MUX
pr1_mii0_col
pr1_mii0_rxlink
L6
11
pr1_mii0_crs
P4
11
pr1_edio_data_out7
pr1_edio_data_out6
pr1_edio_data_out5
pr1_edio_data_out4
pr1_edio_data_out3
pr1_edio_data_out2
pr1_edio_data_out1
pr1_edio_data_out0
pr1_edio_data_in7
pr1_edio_data_in6
pr1_edio_data_in5
pr1_edio_data_in4
pr1_edio_data_in3
pr1_edio_data_in2
pr1_edio_data_in1
pr1_edio_data_in0
pr1_edio_sof
A7
B9
C8
B8
E8
C7
B7
D8
A7
B9
C8
B8
E8
C7
B7
D8
A11
A9
A8
13
13
13
13
13
13
13
13
12
12
12
12
12
12
12
12
11
11
11
pr1_edc_latch0_in
pr1_edc_sync0_out
pr1_uart0_cts_n
pr1_uart0_rts_n
E8
B8
B9
C8
A7
11
11
11
11
11
pr1_uart0_txd
pr1_uart0_rxd
pr1_ecap0_ecap_capin_apwm
_o
PRU-ICSS 1 MII
pr1_mii1_txd3
pr1_mii1_txd2
pr1_mii1_txd1
pr1_mii1_txd0
pr1_mii1_rxd3
pr1_mii1_rxd2
pr1_mii1_rxd1
pr1_mii1_rxd0
pr1_mii1_rxdv
pr1_mii1_txen
pr1_mii1_rxer
pr1_mii_mr1_clk
pr1_mii_mt1_clk
pr1_mii0_txd3
pr1_mii0_txd2
pr1_mii0_txd1
pr1_mii0_txd0
pr1_mii0_rxd3
B10
E10
B11
D11
A12
A13
E11
F11
B12
A10
B13
C11
F10
P2
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
N1
N3
N4
T4
302
Specifications
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表 5-178. PRU-ICSS1 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
T5
MUX
11
11
11
11
11
11
11
11
11
11
BALL
MUX
pr1_mii0_rxd2
pr1_mii0_rxd1
pr1_mii0_rxd0
pr1_mii0_rxdv
pr1_mii0_txen
pr1_mii0_rxer
pr1_mii_mt0_clk
pr1_mii_mr0_clk
pr1_mdio_mdclk
pr1_mdio_data
R2
R1
N5
P1
P3
N2
N6
D10
C10
In 表 5-179, 表 5-180 and 表 5-181 are presented the specific groupings of signals (IOSET) for use with
PRU-ICSS2.
表 5-179. PRU-ICSS2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
PRU-ICSS 2
pr2_pru1_gpi16
pr2_pru1_gpi15
pr2_pru1_gpi14
pr2_pru1_gpi13
pr2_pru1_gpi12
pr2_pru1_gpi11
pr2_pru1_gpi10
pr2_pru1_gpi9
pr2_pru1_gpi8
pr2_pru1_gpi7
pr2_pru1_gpi6
pr2_pru1_gpi5
pr2_pru1_gpi4
pr2_pru1_gpi3
pr2_pru1_gpi2
pr2_pru1_gpi1
pr2_pru1_gpi0
pr2_pru1_gpo16
pr2_pru1_gpo15
pr2_pru1_gpo14
pr2_pru1_gpo13
pr2_pru1_gpo12
pr2_pru1_gpo11
pr2_pru1_gpo10
pr2_pru1_gpo9
pr2_pru1_gpo8
pr2_pru1_gpo7
pr2_pru1_gpo6
N4
N3
P1
N1
P2
N2
R1
R2
P3
P4
T5
T4
N6
N5
P5
L6
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
E16
E17
A19
B18
B16
B17
A18
B14
D14
C16
J24
J25
AC4
AA5
U6
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
AC3
D23
E16
E17
A19
B18
B16
B17
A18
B14
D14
C16
J24
L5
N4
N3
P1
N1
P2
N2
R1
R2
P3
P4
T5
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表 5-179. PRU-ICSS2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
T4
MUX
13
BALL
J25
AC4
AA5
U6
MUX
13
13
13
13
13
13
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
pr2_pru1_gpo5
pr2_pru1_gpo4
pr2_pru1_gpo3
pr2_pru1_gpo2
pr2_pru1_gpo1
pr2_pru1_gpo0
pr2_pru0_gpi20
pr2_pru0_gpi19
pr2_pru0_gpi18
pr2_pru0_gpi17
pr2_pru0_gpi16
pr2_pru0_gpi15
pr2_pru0_gpi14
pr2_pru0_gpi13
pr2_pru0_gpi12
pr2_pru0_gpi11
pr2_pru0_gpi10
pr2_pru0_gpi9
pr2_pru0_gpi8
pr2_pru0_gpi7
pr2_pru0_gpi6
pr2_pru0_gpi5
pr2_pru0_gpi4
pr2_pru0_gpi3
pr2_pru0_gpi2
pr2_pru0_gpi1
pr2_pru0_gpi0
pr2_pru0_gpo20
pr2_pru0_gpo19
pr2_pru0_gpo18
pr2_pru0_gpo17
pr2_pru0_gpo16
pr2_pru0_gpo15
pr2_pru0_gpo14
pr2_pru0_gpo13
pr2_pru0_gpo12
pr2_pru0_gpo11
pr2_pru0_gpo10
pr2_pru0_gpo9
pr2_pru0_gpo8
pr2_pru0_gpo7
pr2_pru0_gpo6
pr2_pru0_gpo5
pr2_pru0_gpo4
pr2_pru0_gpo3
pr2_pru0_gpo2
N6
N5
P5
13
13
13
L6
13
AC3
D23
F16
D19
E19
B21
A21
B23
B22
A23
A22
AB1
AA4
AA1
Y3
L5
13
W2
AA3
AA2
Y4
Y1
Y2
Y6
Y5
F16
D19
E19
B21
A21
B23
B22
A23
A22
AB1
AA4
AA1
Y3
W2
AA3
AA2
Y4
Y1
Y2
304
Specifications
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表 5-179. PRU-ICSS2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
Y6
MUX
13
pr2_pru0_gpo1
pr2_pru0_gpo0
pr2_mii1_crs
pr2_mii1_rxlink
pr2_mii0_crs
pr2_mii0_rxlink
pr2_mii0_col
pr2_mii1_col
Y5
13
J24
B23
A22
B21
A23
J25
11
11
11
11
11
11
PRU-ICSS 2 MII
pr2_mii1_txd3
pr2_mii1_txd2
pr2_mii1_txd1
pr2_mii1_txd0
pr2_mii1_rxd3
pr2_mii1_rxd2
pr2_mii1_rxd1
pr2_mii1_rxd0
pr2_mii_mr1_clk
pr2_mii1_rxer
pr2_mii_mt1_clk
pr2_mii1_rxdv
pr2_mii1_txen
pr2_mii0_txd3
pr2_mii0_txd2
pr2_mii0_txd1
pr2_mii0_txd0
pr2_mii0_rxd3
pr2_mii0_rxd2
pr2_mii0_rxd1
pr2_mii0_rxd0
pr2_mii_mr0_clk
pr2_mii0_rxer
pr2_mii_mt0_clk
pr2_mii0_rxdv
pr2_mii0_txen
pr2_mdio_mdclk
pr2_mdio_data
Y2
Y1
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
Y4
AA2
Y3
AA1
AA4
AB1
AA3
B22
Y5
W2
Y6
B17
B16
B18
A19
F16
E19
D19
A21
E17
D14
B14
E16
A18
C16
C17
AA5
AC4
11
11
表 5-180. PRU-ICSS2 IOSETs (EnDAT)(1)
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
PRU-ICSS 2 EnDAT
pr2_pru1_endat0_clk
pr2_pru1_endat0_out
pr2_pru1_endat0_out_en
pr2_pru1_endat1_clk
L5
L6
P5
N5
13
13
13
13
D23
AC3
U6
13
13
13
13
AA5
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Specifications
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表 5-180. PRU-ICSS2 IOSETs (EnDAT)(1) (continued)
SIGNALS
IOSET3
IOSET4
BALL
N6
T4
MUX
13
BALL
AC4
J25
MUX
13
pr2_pru1_endat1_out
pr2_pru1_endat1_out_en
pr2_pru1_endat2_clk
pr2_pru1_endat2_out
pr2_pru1_endat2_out_en
pr2_pru1_endat0_in
pr2_pru1_endat1_in
pr2_pru1_endat2_in
13
13
T5
13
J24
13
P4
13
C16
D14
B14
A18
B17
13
P3
13
13
R2
R1
N2
12
12
12
12
12
12
(1) These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the
PRU-ICSS internal wrapper multiplexing.
表 5-181. PRU-ICSS2 IOSETs (Sigma Delta)(1)
SIGNALS
IOSET4
BALL
MUX
PRU-ICSS 2 SD
pr2_pru0_sd0_clk
pr2_pru0_sd0_d
pr2_pru0_sd1_clk
pr2_pru0_sd1_d
pr2_pru0_sd2_clk
pr2_pru0_sd2_d
pr2_pru0_sd3_clk
pr2_pru0_sd3_d
pr2_pru0_sd4_clk
pr2_pru0_sd4_d
pr2_pru0_sd5_clk
pr2_pru0_sd5_d
pr2_pru0_sd6_clk
pr2_pru0_sd6_d
pr2_pru0_sd7_clk
pr2_pru0_sd7_d
pr2_pru0_sd8_clk
pr2_pru0_sd8_d
Y5
Y6
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Y2
Y1
Y4
AA2
AA3
W2
Y3
AA1
AA4
AB1
A22
A23
B22
B23
A21
B21
(1) These signals are internally muxed with the PRU GPI/GPO signals. Refer to the PRU chapter in the TRM for more details about the
PRU-ICSS internal wrapper multiplexing.
5.10.6.22.6 PRU-ICSS Manual Functional Mapping
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Input
mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes.
See 表 5-182 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the
Manual modes.
306
Specifications
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表 5-182 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-182. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode
BALL
BALL NAME
PR1_PRU1_DIR_IN_MANUAL
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
G_DELAY (ps)
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
A9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
800
0
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_D3_IN
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
pr1_pru1_gpi7
pr1_pru1_gpi8
pr1_pru1_gpi9
pr1_pru1_gpi10
pr1_pru1_gpi11
pr1_pru1_gpi12
pr1_pru1_gpi13
pr1_pru1_gpi14
pr1_pru1_gpi15
pr1_pru1_gpi16
pr1_pru1_gpi17
pr1_pru1_gpi18
pr1_pru1_gpi19
pr1_pru1_gpi20
pr1_pru1_gpi0
pr1_pru1_gpi1
pr1_pru1_gpi2
pr1_pru1_gpi3
pr1_pru1_gpi4
pr1_pru1_gpi5
pr1_pru1_gpi6
200
0
0
400
300
400
900
1500
100
500
500
600
900
100
600
200
400
500
600
A8
A11
F10
A10
B10
E10
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Output
mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes.
See 表 5-183 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the
Manual modes.
表 5-183 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-183. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode
BALL
BALL NAME
PR1_PRU1_DIR_OUT_MANUAL
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
G_DELAY (ps)
1000
1300
2300
2200
1800
1800
1600
2000
700
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
0
0
0
0
0
0
0
0
0
0
0
0
CFG_VIN2A_D10_OUT
CFG_VIN2A_D11_OUT
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
CFG_VIN2A_D18_OUT
CFG_VIN2A_D19_OUT
CFG_VIN2A_D20_OUT
CFG_VIN2A_D21_OUT
pr1_pru1_gpo7
pr1_pru1_gpo8
pr1_pru1_gpo9
pr1_pru1_gpo10
pr1_pru1_gpo11
pr1_pru1_gpo12
pr1_pru1_gpo13
pr1_pru1_gpo14
pr1_pru1_gpo15
pr1_pru1_gpo16
pr1_pru1_gpo17
pr1_pru1_gpo18
700
500
400
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表 5-183. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode (continued)
BALL
BALL NAME
PR1_PRU1_DIR_OUT_MANUAL
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
G_DELAY (ps)
0
C13
D13
A9
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
0
0
CFG_VIN2A_D22_OUT
CFG_VIN2A_D23_OUT
CFG_VIN2A_D3_OUT
CFG_VIN2A_D4_OUT
CFG_VIN2A_D5_OUT
CFG_VIN2A_D6_OUT
CFG_VIN2A_D7_OUT
CFG_VIN2A_D8_OUT
CFG_VIN2A_D9_OUT
pr1_pru1_gpo19
pr1_pru1_gpo20
pr1_pru1_gpo0
pr1_pru1_gpo1
pr1_pru1_gpo2
pr1_pru1_gpo3
pr1_pru1_gpo4
pr1_pru1_gpo5
pr1_pru1_gpo6
400
0
2200
2800
400
A8
540
0
A11
F10
A10
B10
E10
0
1500
2200
2600
2300
0
0
0
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Parallel
Capture Mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See 表 5-184 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode
for a definition of the Manual modes.
表 5-184 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-184. Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode
BALL
BALL NAME
PR1_PRU1_PAR_CAP_MANUAL
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
1535
1151
1173
970
G_DELAY (ps)
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
A9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
0
0
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D3_IN
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
pr1_pru1_gpi7
pr1_pru1_gpi8
pr1_pru1_gpi9
pr1_pru1_gpi10
pr1_pru1_gpi11
pr1_pru1_gpi12
pr1_pru1_gpi13
pr1_pru1_gpi14
pr1_pru1_gpi15
pr1_pru1_gpi16
pr1_pru1_gpi0
pr1_pru1_gpi1
pr1_pru1_gpi2
pr1_pru1_gpi3
pr1_pru1_gpi4
pr1_pru1_gpi5
pr1_pru1_gpi6
0
0
1196
1286
1354
1331
2097
0
0
0
0
0
0
453
0
1566
1012
1337
1130
1202
1395
1338
A8
0
A11
F10
A10
B10
E10
0
0
0
0
0
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct
Input mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-185 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a
definition of the Manual modes.
表 5-185 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
308
Specifications
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表 5-185. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode
BALL
BALL NAME
PR2_PRU0_DIR_IN_MANUAL2
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
G_DELAY (ps)
3300
3400
1300
800
Y5
Y6
gpio6_10
gpio6_11
1000
1000
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
pr2_pru0_gpi0
pr2_pru0_gpi1
pr2_pru0_gpi20
pr2_pru0_gpi18
pr2_pru0_gpi16
pr2_pru0_gpi17
pr2_pru0_gpi19
pr2_pru0_gpi14
pr2_pru0_gpi15
pr2_pru0_gpi13
pr2_pru0_gpi2
pr2_pru0_gpi3
pr2_pru0_gpi4
pr2_pru0_gpi5
pr2_pru0_gpi6
pr2_pru0_gpi7
pr2_pru0_gpi8
pr2_pru0_gpi9
pr2_pru0_gpi10
pr2_pru0_gpi11
pr2_pru0_gpi12
F16
E19
A21
B21
D19
B22
B23
A23
Y2
mcasp1_axr15
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
CFG_MCASP1_AXR15_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
0
0
1900
1400
1400
1400
1000
1300
3700
3500
3500
4000
3300
3900
3500
3600
3500
3100
0
0
0
0
0
0
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
0
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
mcasp3_aclkx
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_MCASP3_ACLKX_IN
Y4
AA2
AA3
W2
Y3
AA1
AA4
AB1
A22
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct
Output mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-186 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a
definition of the Manual modes.
表 5-186 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-186. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode
BALL
BALL NAME
PR2_PRU0_DIR_OUT_MANUAL2
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
G_DELAY (ps)
Y5
Y6
gpio6_10
gpio6_11
1800
1900
2100
400
400
500
500
0
CFG_GPIO6_10_OUT
CFG_GPIO6_11_OUT
pr2_pru0_gpo0
pr2_pru0_gpo1
pr2_pru0_gpo20
pr2_pru0_gpo18
pr2_pru0_gpo16
pr2_pru0_gpo17
pr2_pru0_gpo19
pr2_pru0_gpo12
pr2_pru0_gpo14
pr2_pru0_gpo15
pr2_pru0_gpo13
pr2_pru0_gpo2
pr2_pru0_gpo3
pr2_pru0_gpo4
2500
F16
E19
A21
B21
D19
A22
B22
B23
A23
Y2
mcasp1_axr15
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
0
CFG_MCASP1_AXR15_OUT
CFG_MCASP2_ACLKX_OUT
CFG_MCASP2_AXR2_OUT
CFG_MCASP2_AXR3_OUT
CFG_MCASP2_FSX_OUT
CFG_MCASP3_ACLKX_OUT
CFG_MCASP3_AXR0_OUT
CFG_MCASP3_AXR1_OUT
CFG_MCASP3_FSX_OUT
CFG_MMC3_CLK_OUT
0
0
0
0
0
500
0
0
0
200
300
2200
2300
1600
0
2100
2300
2000
Y1
mmc3_cmd
mmc3_dat0
CFG_MMC3_CMD_OUT
CFG_MMC3_DAT0_OUT
Y4
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Specifications
309
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www.ti.com.cn
表 5-186. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode (continued)
BALL
BALL NAME
PR2_PRU0_DIR_OUT_MANUAL2
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
2000
G_DELAY (ps)
1700
AA2
AA3
W2
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
CFG_MMC3_DAT1_OUT
CFG_MMC3_DAT2_OUT
CFG_MMC3_DAT3_OUT
CFG_MMC3_DAT4_OUT
CFG_MMC3_DAT5_OUT
CFG_MMC3_DAT6_OUT
CFG_MMC3_DAT7_OUT
pr2_pru0_gpo5
pr2_pru0_gpo6
pr2_pru0_gpo7
pr2_pru0_gpo8
pr2_pru0_gpo9
pr2_pru0_gpo10
pr2_pru0_gpo11
2050
2200
2000
2000
Y3
2150
2600
AA1
AA4
AB1
2400
2600
2200
2300
1800
2400
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct
Input mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-187 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a
definition of the Manual modes.
表 5-187 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-187. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode
BALL
BALL NAME
PR2_PRU1_DIR_IN_MANUAL1
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
G_DELAY (ps)
P5
RMII_MHZ_50_CL
K
1400
1200
CFG_RMII_MHZ_50_CLK_IN
pr2_pru1_gpi2
L6
L5
mdio_d
1300
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1300
1300
1300
1300
1300
1600
800
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
pr2_pru1_gpi1
pr2_pru1_gpi0
pr2_pru1_gpi11
pr2_pru1_gpi12
pr2_pru1_gpi16
pr2_pru1_gpi15
pr2_pru1_gpi14
pr2_pru1_gpi13
pr2_pru1_gpi5
pr2_pru1_gpi6
pr2_pru1_gpi10
pr2_pru1_gpi9
pr2_pru1_gpi8
pr2_pru1_gpi7
pr2_pru1_gpi3
pr2_pru1_gpi4
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
P4
N5
N6
500
1800
1300
1650
1400
1650
900
1300
900
1400
1100
1300
1000
800
uart3_txd
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct
Input mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-188 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a
definition of the Manual modes.
表 5-188 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
310
Specifications
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提交文档反馈意见
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AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-188. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode
BALL
BALL NAME
PR2_PRU1_DIR_IN_MANUAL2
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
400
G_DELAY (ps)
C16
D14
B14
B16
B18
A19
E17
E16
A18
B17
D23
AC3
AA5
AC4
U6
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr8
mcasp1_axr9
mcasp4_axr1
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
0
200
300
500
500
0
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
CFG_XREF_CLK0_IN
pr2_pru1_gpi7
pr2_pru1_gpi8
pr2_pru1_gpi9
pr2_pru1_gpi12
pr2_pru1_gpi13
pr2_pru1_gpi14
pr2_pru1_gpi15
pr2_pru1_gpi16
pr2_pru1_gpi10
pr2_pru1_gpi11
pr2_pru1_gpi0
pr2_pru1_gpi1
pr2_pru1_gpi3
pr2_pru1_gpi4
pr2_pru1_gpi2
pr2_pru1_gpi5
pr2_pru1_gpi6
700
600
600
700
500
600
200
0
600
800
0
600
300
0
500
2100
2300
2300
2100
0
1959
2000
1800
1780
0
J25
J24
xref_clk0
xref_clk1
0
0
CFG_XREF_CLK1_IN
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct
Output mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-189 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a
definition of the Manual modes.
表 5-189 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-189. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode
BALL
BALL NAME
PR2_PRU1_DIR_OUT_MANUAL1
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
2306
G_DELAY (ps)
100
P5
L6
RMII_MHZ_50_CLK
mdio_d
CFG_RMII_MHZ_50_CLK_OUT
CFG_MDIO_D_OUT
pr2_pru1_gpo2
pr2_pru1_gpo1
pr2_pru1_gpo0
pr2_pru1_gpo11
pr2_pru1_gpo12
pr2_pru1_gpo16
pr2_pru1_gpo15
pr2_pru1_gpo14
pr2_pru1_gpo13
pr2_pru1_gpo5
pr2_pru1_gpo6
pr2_pru1_gpo10
pr2_pru1_gpo9
pr2_pru1_gpo8
pr2_pru1_gpo7
pr2_pru1_gpo3
pr2_pru1_gpo4
1900
2000
L5
mdio_mclk
rgmii0_rxc
2000
1100
CFG_MDIO_MCLK_OUT
CFG_RGMII0_RXC_OUT
CFG_RGMII0_RXCTL_OUT
CFG_RGMII0_RXD0_OUT
CFG_RGMII0_RXD1_OUT
CFG_RGMII0_RXD2_OUT
CFG_RGMII0_RXD3_OUT
CFG_RGMII0_TXC_OUT
CFG_RGMII0_TXCTL_OUT
CFG_RGMII0_TXD0_OUT
CFG_RGMII0_TXD1_OUT
CFG_RGMII0_TXD2_OUT
CFG_RGMII0_TXD3_OUT
CFG_UART3_RXD_OUT
CFG_UART3_TXD_OUT
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
P4
N5
N6
2000
1200
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
2000
1700
2000
1000
2200
1000
2200
1300
2250
1100
2350
1000
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
2000
1200
2000
1500
1850
1000
2100
1100
2200
1000
2000
1600
uart3_txd
2000
1000
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
311
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AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct
Output mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See 表 5-190 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a
definition of the Manual modes.
表 5-190 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-190. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode
BALL
BALL NAME
PR2_PRU1_DIR_OUT_MANUAL2
CFG REGISTER
MUXMODE
13
A_DELAY (ps)
G_DELAY (ps)
800
C16
D14
B14
B16
B18
A19
E17
E16
A18
B17
D23
AC3
AA5
AC4
U6
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr8
mcasp1_axr9
mcasp4_axr1
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
200
200
0
CFG_MCASP1_ACLKX_OUT
CFG_MCASP1_AXR0_OUT
CFG_MCASP1_AXR1_OUT
CFG_MCASP1_AXR10_OUT
CFG_MCASP1_AXR11_OUT
CFG_MCASP1_AXR12_OUT
CFG_MCASP1_AXR13_OUT
CFG_MCASP1_AXR14_OUT
CFG_MCASP1_AXR8_OUT
CFG_MCASP1_AXR9_OUT
CFG_MCASP4_AXR1_OUT
CFG_MCASP5_ACLKX_OUT
CFG_MCASP5_AXR0_OUT
CFG_MCASP5_AXR1_OUT
CFG_MCASP5_FSX_OUT
CFG_XREF_CLK0_OUT
pr2_pru1_gpo7
pr2_pru1_gpo8
pr2_pru1_gpo9
pr2_pru1_gpo12
pr2_pru1_gpo13
pr2_pru1_gpo14
pr2_pru1_gpo15
pr2_pru1_gpo16
pr2_pru1_gpo10
pr2_pru1_gpo11
pr2_pru1_gpo0
pr2_pru1_gpo1
pr2_pru1_gpo3
pr2_pru1_gpo4
pr2_pru1_gpo2
pr2_pru1_gpo5
pr2_pru1_gpo6
1000
1110
2500
1900
2300
1200
1100
1600
1900
700
0
0
0
200
200
200
0
0
1400
1500
1500
1300
0
4000
3000
1900
2700
160
J25
J24
xref_clk0
xref_clk1
0
0
CFG_XREF_CLK1_OUT
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2
Parallel Capture Mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See 表 5-191 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel
Capture Mode for a definition of the Manual modes.
表 5-191 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-191. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode
BALL
BALL NAME
PR2_PRU0_PAR_CAP_MANUAL2
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
4125
3935
0
G_DELAY (ps)
Y5
Y6
gpio6_10
gpio6_11
481
997
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
pr2_pru0_gpi0
pr2_pru0_gpi1
pr2_pru0_gpi16
pr2_pru0_gpi12
pr2_pru0_gpi14
pr2_pru0_gpi15
pr2_pru0_gpi13
pr2_pru0_gpi2
pr2_pru0_gpi3
pr2_pru0_gpi4
pr2_pru0_gpi5
A21
A22
B22
B23
A23
Y2
mcasp2_axr2
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
CFG_MCASP2_AXR2_IN
CFG_MCASP3_ACLKX_IN
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
571
0
1570
1405
1946
4093
4043
4010
3817
0
0
0
1066
921
864
1643
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
Y4
AA2
312
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM5706 AM5708
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
表 5-191. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode (continued)
BALL
BALL NAME
PR2_PRU0_PAR_CAP_MANUAL2
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
4040
G_DELAY (ps)
AA3
W2
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
673
1478
729
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
pr2_pru0_gpi6
pr2_pru0_gpi7
pr2_pru0_gpi8
pr2_pru0_gpi9
pr2_pru0_gpi10
pr2_pru0_gpi11
3923
Y3
4096
AA1
AA4
AB1
3926
1271
929
4004
3963
666
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1
Parallel Capture Mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See 表 5-192 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel
Capture Mode for a definition of the Manual modes.
表 5-192 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-192. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode
BALL
BALL NAME
PR2_PRU1_PAR_CAP_MANUAL1
CFG REGISTER
MUXMODE
12
A_DELAY (ps)
G_DELAY (ps)
P5
RMII_MHZ_5
0_CLK
1717
0
CFG_RMII_MHZ_50_CLK_IN
pr2_pru1_gpi2
L5
L6
mdio_d
2088
1321
1287
2456
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
pr2_pru1_gpi1
pr2_pru1_gpi0
pr2_pru1_gpi11
pr2_pru1_gpi12
pr2_pru1_gpi16
pr2_pru1_gpi15
pr2_pru1_gpi14
pr2_pru1_gpi13
pr2_pru1_gpi5
pr2_pru1_gpi6
pr2_pru1_gpi10
pr2_pru1_gpi9
pr2_pru1_gpi8
pr2_pru1_gpi7
pr2_pru1_gpi3
pr2_pru1_gpi4
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
P4
N5
N6
2157
2008
2271
1851
1875
1685
2131
1734
1764
1654
1242
uart3_txd
Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2
Parallel Capture Mode. See 表 5-30 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See 表 5-193 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel
Capture Mode for a definition of the Manual modes.
表 5-193 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
版权 © 2016–2019, Texas Instruments Incorporated
Specifications
313
提交文档反馈意见
产品主页链接: AM5706 AM5708
AM5706, AM5708
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
表 5-193. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode
BALL
BALL NAME
PR2_PRU1_PAR_CAP_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
1928
2413
2523
2607
2669
2225
2315
0
G_DELAY (ps)
12
C16
D14
B14
B16
B18
A19
E17
E16
A18
B17
D23
AC3
AA5
AC4
U6
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr8
mcasp1_axr9
mcasp4_axr1
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
0
0
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
CFG_XREF_CLK0_IN
pr2_pru1_gpi7
pr2_pru1_gpi8
pr2_pru1_gpi9
pr2_pru1_gpi12
pr2_pru1_gpi13
pr2_pru1_gpi14
pr2_pru1_gpi15
pr2_pru1_gpi16
pr2_pru1_gpi10
pr2_pru1_gpi11
pr2_pru1_gpi0
pr2_pru1_gpi1
pr2_pru1_gpi3
pr2_pru1_gpi4
pr2_pru1_gpi2
pr2_pru1_gpi5
pr2_pru1_gpi6
25
0
92
0
0
0
2201
2293
1759
3732
3776
3886
3800
1375
1320
0
278
0
1810
2255
1923
1449
21
0
J25
J24
xref_clk0
xref_clk1
CFG_XREF_CLK1_IN
314
Specifications
版权 © 2016–2019, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: AM5706 AM5708
AM5706, AM5708
www.ti.com.cn
ZHCSH00F –AUGUST 2016–REVISED NOVEMBER 2019
5.10.6.23 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
•
•
•
Sysboot Interface
System DMA Interface
Interrupt Controllers (INTC) Interface
5.10.7 Emulation and Debug Subsystem
The Device includes the following Test interfaces:
•
•
IEEE 1149.1 Standard-Test-Access Port (JTAG)
Trace Port Interface Unit (TPIU)
5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
•
•
•
•
•
32KB embedded trace buffer (ETB)
5-pin system trace interface for debug
Supports Advanced Event Triggering (AET)
All processors can be emulated via JTAG ports
All functions on EMU pins of the device:
–
–
EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
EMU[4:2] - STM trace only (single direction)
5.10.7.1.1 JTAG Electrical Data/Timing
表 5-194, 表 5-195 and 图 5-125 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
表 5-194. Timing Requirements for IEEE 1149.1 JTAG
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
6.23
ns
31.15
31.15
ns
ns
表 5-195. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
td(TCKL-TDOV)
DESCRIPTION
MIN
MAX
UNIT
2
Delay time, TCK low to TDO valid
0
30.5
ns
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1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
SPRS906_TIMING_JTAG_01
图 5-125. JTAG Timing
表 5-196, 表 5-197 and 图 5-126 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
表 5-196. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
6.23
ns
31.15
31.15
ns
ns
表 5-197. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
td(TCK-RTCK)
DESCRIPTION
MIN
MAX
UNIT
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the Arm is in the scan chain, the delay
time is a function of the Arm functional clock).
5
0
27
ns
6
7
8
tc(RTCK)
Cycle time, RTCK
62.29
24.92
24.92
ns
ns
ns
tw(RTCKH)
tw(RTCKL)
Pulse duration, RTCK high (40% of tc)
Pulse duration, RTCK low (40% of tc)
5
TCK
6
7
8
RTCK
SPRS906_TIMING_JTAG_02
图 5-126. JTAG With RTCK Timing
316
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5.10.7.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-199.
5.10.7.2.1 TPIU PLL DDR Mode
表 5-198 and 图 5-127 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-198. Switching Characteristics for TPIU
NO.
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, TRACECLK period
MIN
5.56
MAX
UNIT
ns
TPIU1
TPIU4
TPIU5
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL transition
Skew time, TRACECLK transition to TRACEDATA[17:0]
-1.61
-1.61
1.98
1.98
ns
td(clk-dataV)
ns
TPIU1
TPIU2
TPIU3
TRACECLK
TPIU4
TPIU4
TRACECTL
TPIU5
TPIU5
TRACEDATA[X:0]
SPRS906_TIMING_TIMER_01
图 5-127. TPIU—PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
In 表 5-199 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
表 5-199. TPIU IOSETs
SIGNALS
IOSET1
IOSET2
BALL
E10
B10
A10
F10
A11
A8
MUX
5
BALL
MUX
emu19
emu18
emu17
emu16
emu15
emu14
emu13
emu12
emu11
emu10
emu9
5
5
5
5
5
A9
5
A7
5
B9
5
C8
5
B8
5
emu8
E8
5
emu7
C7
5
emu6
B7
5
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表 5-199. TPIU IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
D8
MUX
BALL
MUX
emu5
emu1
emu0
5
0
0
C22
C21
C22
C21
0
0
318
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6 Detailed Description
6.1 Description
AM570x Sitara™ processors are Arm applications processors built to meet the intense processing needs
of modern embedded products.
AM570x devices bring high processing performance through the maximum flexibility of a fully integrated
mixed processor solution. The devices also combine programmable video processing with a highly
integrated peripheral set.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and TI
C66x VLIW floating-point DSP cores. The Arm processor lets developers keep control functions separate
from vision algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the
system software.
Additionally, TI provides a complete set of development tools for the Arm and C66x DSP, including C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface
for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including
support for secure boot, debug security and support for trusted execution environment are available on
High-Security (HS) devices. For more information about HS devices, contact your TI representative.
6.2 Functional Block Diagram
图 6-1 is functional block diagram for the device.
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AM570x
Display Subsystem
MPU
IVA HD
(1x Arm
Cortex–A15)
1080p Video
Co-Processor
1x GFX Pipeline
LCD2
LCD3
3x Video Pipeline
Blend / Scale
GPU
BB2D
(1x SGX544 3D)
(GC320 2D)
HDMI 1.4a
IPU1
(2x Cortex–M4)
DSP
(1x C66x
Co-Processor)
Secure Boot
IPU2
(2x Cortex–M4)
CAL
CSI2 x1
Debug
Security
TEE
(HS devices)
EDMA
sDMA
MMU x2
VIP x1
VPE
High-Speed Interconnect
System
Connectivity
Spinlock
Mailbox x13
GPIO x8
Timers x16
WDT
USB 3.0
Dual Mode FS/HS/SS
w/ PHY
PCIeSS x2
PWM SS x3
HDQ
GMAC_SW
KBD
USB 2.0
Dual Mode FS/HS
PHY
PRU-ICSS x2
Program/Data Storage
Serial Interfaces
QSPI
McASP x8
I2C x5
UART x10
McSPI x4
DCAN x2
MMC / SD x4
DMM
EMIF
1x 32-bit
DDR3(L)
512-KB
OCMC_RAM
w/ ECC
GPMC / ELM
(NAND/NOR/
Async)
intro-001
图 6-1. AM570x Block Diagram
320
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6.3 MPU
The Cortex®-A15 microprocessor unit (MPU) subsystem serves the applications processing role by
running the high-level operating system (HLOS) and application code.
The MPU subsystem incorporates one Cortex-A15 MPU core (MPU_C0), individual level 1 (L1) caches,
level 2 (L2) cache (MPU_L2CACHE) shared between them, and various other shared peripherals. To aid
software development, the processor core can be kept cache-coherent with the L2 cache.
The MPU subsystem provides a high-performance computing platform with high peak-computing
performance and low memory latency.
The Arm subsystem supports the following key features:
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•
Arm Cortex-A15 MP Core™ (MPU_CLUSTER)
–
One Cortex-A15 MPU core (revision r2p2) which has the following features:
•
Superscalar, dynamic multi-issue technology
–
–
Out-of-order (OoO) instruction dispatch and completion
Dynamic branch prediction with branch target buffer (BTB), global history buffer (GHB), and
48-entry return stack
–
–
–
–
Continuous fetch and decoding of three instructions per clock cycle
Dispatch of up to four instructions and completion of eight instructions per clock cycle
Provides optimal performance from binaries compiled for previous Arm processors
Five execution units handle simple instructions, branch instructions, Neon and floating point
instructions, multiply instructions, and load and store instructions.
–
Simple instructions take two cycles from dispatch, while complex instructions take up to 11
cycles.
–
–
Can issue two simple instructions in a cycle
Can issue a load and a store instruction in the same cycle
•
•
Integrated Neon processing engine to include the Arm Neon Advanced SIMD (single instruction,
multiple data) support for accelerated media and signal processing computation
Includes VFPv4-compatible hardware to support single- and double-precision add, subtract,
divide, multiply and accumulate, and square root operations
•
•
Extensive support to accelerate virtualization using a hypervisor
32-KiB L1 instruction (L1I) and 32-KiB L1 data (L1D) cache:
–
–
64-byte line size
2-way set associative
•
Memory management unit (MMU):
–
Two-level translation lookaside buffer (TLB) organization
–
First level is an 32-entry, fully associative micro-TLB implemented for each of instruction
fetch, load, and store.
–
Second level is a unified, 4-way associative, 512-entry main TLB
–
Supports hardware TLB table-walk for backward-compatible and new 64-bit entry page table
formats
–
–
New page table format can produce 40-bit physical addresses
Two-stage translation where first stage is HLOS-controlled and the second level may be
controlled by a hypervisor. Second stage always uses the new page table format
–
Integrated L2 cache (MPU_L2CACHE) and snoop control unit (SCU):
•
1-MiB of unified (instructions and data) cache organized as 16 ways of 1024 sets of 64-byte
lines
•
Redundant L1 data (cache) tags to perform snoop filtering (L1 instruction cache tags are not
duplicated)
•
•
Operates at Cortex-A15 MPU core clock rate
Integrated L2 cache controller (MPU_L2CACHE_CTRL):
–
–
–
Sixteen 64-byte line buffers that handle evictions, line fills and snoop transfers
One 128-bit AMBA4 Coherent Bus (AXI4-ACE) port
Auto-prefetch buffer for up to 16 streams and detecting forward and backward strides
–
Generalized interrupt controller (GIC, also referred to as MPU_INTC): An interrupt controller
supplied by Arm. The single GIC in the MPU_CLUSTER routes interrupts to the MPU core. The
GIC supports:
•
•
•
Number of shared peripheral interrupts (SPI): 160
Number of software generated interrupts (SGI): 16
Number of CPU interfaces: 1
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•
Virtual CPU interface for virtualization support. This allows the majority of guest operating
system (OS) interactions with the GIC to be handled in hardware, but with physical interrupts
still requiring hypervisor intervention to assign them to the appropriate virtual machine.
–
–
Integrated timer counter and one timer block
Arm CoreSight™ debug and trace modules. For more information, see chapter On-Chip Debug
Support of the Device TRM.
•
MPU_AXI2OCP bridge (local interconnect):
–
Connected to Memory Adapter (MPU_MA), which routes the non-EMIF address space transactions
to MPU_AXI2OCP
–
–
Single request multiple data (SRMD) protocol on L3_MAIN port
Multiple targets:
•
•
•
64-bit port to the L3_MAIN interconnect. Interface frequency is 1/4 or 1/8 of core frequency
MPU_ROM
Internal MPU subsystem peripheral targets, including Memory Adapter LISA Section Manager
(MA_LSM), wake-up generator (MPU_WUGEN), watchdog timer (MPU_WD_TIMER), and local
PRCM module (MPU_PRCM) configuration
•
Internal AXI target, CoreSight System Trace Module (CS_STM)
•
Memory adapter (MPU_MA): Helps decrease the latency of accesses between the MPU_L2CACHE
and the external memory interface (EMIF1) by providing a direct path between the MPU subsystem
and EMIF1:
–
–
–
Connected to 128-bit AMBA4 interface of MPU_CLUSTER
Direct 128-bit interface to EMIF1
Interface speed between MPU_CLUSTER and MPU_MA is at half-speed of the MPU core
frequency
–
–
Quarter-speed interface to EMIF
Uses firewall logic to check access rights of incoming addresses
•
•
Local PRCM (MPU_PRCM):
–
–
Handles MPU_C0 power domain
Supports SR3-APG (SmartReflex3 Automatic Power Gating) power management technology inside
the MPU_CLUSTER
–
MPU subsystem has five power domains
Wake-up generator (MPU_WUGEN)
Responsible for waking up the MPU core
–
•
•
Standby controller: Handles the power transitions inside the MPU subsystem
Realtime (master) counter (COUNTER_REALTIME): Produces the count used by the private timer
peripheral in the MPU_CLUSTER
•
•
Watchdog timer (MPU_WD_TIMER): Used to generate a chip-level watchdog reset request to global
PRCM
On-chip boot ROM (MPU_ROM): The MPU_ROM size is 48-KiB, and the address range is from
0x4003 8000 to 0x4004 3FFF. For more information about booting from this memory, see chapter
Initialization of the Device TRM.
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•
Interfaces:
–
–
–
128-bit interface to EMIF1
64-bit master port to the L3_MAIN interconnect
32-bit slave port from the L4_CFG_EMU interconnect (debug subsystem) for configuration of the
MPU subsystem debug modules
–
32-bit slave port from the L4_CFG interconnect for memory adapter firewall (MPU_MA_NTTP_FW)
configuration
–
–
32-bit ATB output for transmitting debug and trace data
160 peripheral interrupt inputs
For more information, see section Arm Cortex-A15 Subsystem in chapter Processors and Accelerators of
the Device TRM.
6.4 DSP Subsystem
The device includes a single instance (DSP1) of a digital signal processor (DSP) subsystem, based on the
TI's standard TMS320C66x DSP CorePac core.
The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating
point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible
with the C64x+/C674x DSPs.
For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set
Reference Guide, (SPRUGH7).
The DSP subsystem integrated in the device includes the following components:
•
A TMS320C66x CorePac DSP core that encompasses:
–
–
–
–
–
–
–
L1 program-dedicated (L1P) cacheable memory
L1 data-dedicated (L1D) cacheable memory
L2 (program and data) cacheable memory
Extended Memory Controller (XMC)
External Memory Controller (EMC)
DSP CorePac located interrupt controller (INTC)
DSP CorePac located power-down controller (PDC)
•
Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and
peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The
external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from
the DSP1 dedicated outputs of the device DMA Events Crossbar for the subsystem.
•
•
•
A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the
subsystem or the remainder of the device via the device L3_MAIN interconnect.
Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the
device L3_MAIN interconnect address space
Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation,
and connection to the device power, reset, and clock management (PRCM) module
The TMS320C66x Instruction Set Architecture (ISA) is the latest for the C6000 family. As with its
predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional
units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total
of 64 general-purpose 32-bit registers.
Some features of the DSP C6000 family devices are:
•
Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:
–
–
Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
Allows designers to develop highly effective RISC-like code for fast development time
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•
•
•
Instruction packing
–
–
Gives code size equivalence for eight instructions executed serially or in parallel
Reduces code size, program fetches, and power consumption
Conditional execution of most instructions
–
–
Reduces costly branching
Increases parallelism for higher sustained performance
Efficient code execution on independent functional units
–
–
Industry's most efficient C compiler on DSP benchmark suite
Industry's first assembly optimizer for fast development and improved parallelization
•
•
8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications
40-bit arithmetic options which add extra precision for vocoders and other computationally intensive
applications
•
•
Saturation and normalization to provide support for key arithmetic operations
Field manipulation and instruction extract, set, clear, and bit counting support common operation found
in control and data manipulation applications.
The C66x CPU has the following additional features:
•
•
•
•
Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.
Quad 8-bit and dual 16-bit instruction set extensions with data flow support
Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses
Special communication-specific instructions have been added to address common operations in error-
correcting codes.
•
•
Bit count and rotate hardware extends support for bit-level algorithms.
Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce
code size.
•
Protected mode operation: A two-level system of privileged program execution to support higher-
capability operating systems and system features such as memory protection.
•
•
Exceptions support for error detection and program redirection to provide robust code execution
Hardware support for modulo loop operation to reduce code size and allow interrupts during fully-
pipelined code
•
•
Each multiplier can perform 32 × 32 bit multiplies
Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts
per clock cycle
The TMS320C66x has the following key improvements to the ISA:
•
•
•
•
4x Multiply Accumulate improvement for both fixed and floating point
Improvement of the floating point arithmetic
Enhancement of the vector processing capability for fixed and floating point
Addition of domain-specific instructions for complex arithmetic and matrix operations
On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD
instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD
operations for 8-bit data. C66x enhances this capabilities with the addition of SIMD instructions for 32-bit
data allowing operation on 128-bit vectors. For example the QMPY32 instruction is able to perform the
element to element multiplication between two vectors of four 32-bit data each.
C66x ISA includes a set of specific instructions to handle complex arithmetic and matrix operations.
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•
TMS320C66x DSP CorePac memory components:
–
A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:
•
When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache
line
•
The DSP CorePac L1P memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
•
The L1P is capable of cache block and global coherence operations
The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM
The L1P memory can be fully configured as a cache or SRAM
Page size for L1P memory is 2KB
–
A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
•
When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache
line
•
The DSP CorePac L1D memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
The L1D memory can be fully configured as a cache or SRAM
No support for error correction or detection
Page size for L1D memory is 2KB
–
A 288-KiB (program and data) L2 memory, only part of which is cacheable:
•
When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte
cache line
•
•
•
Only 256 KiB of L2 memory can be configured as cache or SRAM
32 KiB of the L2 memory is always mapped as SRAM
The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including
necessary SRAM
•
•
The L2 memory controller supports hardware prefetching and also provides bandwidth
management, memory protection, and power-down functions.
Page size for L2 memory is 16KB
•
The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP
subsystem and device. It has :
–
a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA,
DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.
–
a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP
subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the
DSP subsystem is the slave in a transaction.
•
•
The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which
are a result of CPU instruction fetches, load/store commands, cache operations) to device resources
via the C66x DSP CorePac 128-bit master DMA (MDMA) port:
–
Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on
the MDMA port
–
Prefetch, multi-in-flight requests
A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to
the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt
controller supports up to 128 system events of which 64 interrupts are external to DSP subsystem,
collected from the DSP1 dedicated outputs of the device Interrupt Crossbar.
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•
Local Enhanced Direct Memory Access (EDMA) controller features:
–
–
Channel controller (CC) : 64-channel, 128 PaRAM, 2 Queues
2 x Third-party Transfer Controllers (TPTC0 and TPTC1):
•
•
Each TC has a 128-bit read port and a 128-bit write port
2KiB FIFOs on each TPTC
–
–
1-dimensional/2-dimensional (1D/2D) addressing
Chaining capability
•
DSP subsystem integrated MMUs:
Two MMUs are integrated:
–
•
The MMU0 is located between DSP MDMA master port and the device L3_MAIN interconnect
and can be optionally bypassed
•
The MMU1 is located between the EDMA master port and the device L3_MAIN interconnect
•
•
A DSP local Power-Down Controller (PDC) is responsible to power-down various parts of the DSP
C66x CorePac, or the entire DSP C66x CorePac.
The DSP subsystem System Control logic provides:
–
–
–
–
Slave idle and master standby protocols with device PRCM for powerdown
OCP Disconnect handshake for init and target busses
Asynchronous reset
Power-down modes:
•
"Clockstop" mode featuring wake-up on interrupt event. The DMA event wake-up is managed in
software.
•
•
The device DSP subsystem is supplied by a PRCM DPLL, but DSP1 has integrated its own PLL
module outside the C66x CorePac for clock gating and division.
The device DSP subsystem has following port instances to connect to remaining part of the
device. See also :
–
–
–
–
A 128-bit initiator (DSP MDMA master) port for MDMA/Cache requests
A 128-bit initiator (DSP EDMA master) port for EDMA requests
A 32-bit initiator (DSP CFG master) port for configuration requests
A 128-bit target (DSP slave) port for requests to DSP memories and various peripherals
•
C66x DSP subsystem (DSPSS) safety aspects:
–
–
–
Above mentioned memory ECC/ED mechanisms
MMUs enable mapping of only the necessary application space to the processor
Memory Protection Units internal to the DSPSS (in L1P, L1D and L2 memory controllers) and
external to DSPSS (firewalls) to help define legal accesses and raise exceptions on illegal
accesses
–
Exceptions: Memory errors, various DSP errors, MMU errors and some system errors are detected
and cause exceptions. The exceptions could be handled by the DSP or by a designated safety
processor at the chip level. Note that it may not be possible for the safety processor to completely
handle some exceptions
Unsupported features on the C66x DSP core for the device are:
•
The Extended Memory Controller MPAX (memory protection and address extension) 36-bit addressing
is NOT supported
Known DSP subsystem powermode restrictions for the device are:
•
"Full logic / RAM retention" mode featuring wake-up on both interrupt or DMA event (logic in “always
on” domain). Only OFF mode is supported by DSP subsystem, requiring full boot.
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Fore more information about:
•
C66x debug/trace support, see chapter On-Chip Debug of the Device TRM.
6.5 PRU-ICSS
The device Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) consists
of dual 32-bit Load / Store RISC CPU cores - Programmable Real-Time Units (PRU0 and PRU1), shared,
data, and instruction memories, internal peripheral modules, and an interrupt controller (PRU-ICSS_INTC).
The programmable nature of the PRUs, along with their access to pins, events and all SoC resources,
provides flexibility in implementing fast real-time responses, specialized data handling operations,
customer peripheral interfaces, and in off-loading tasks from the other processor cores of the system-on-
chip (SoC).
The each PRU-ICSS includes the following main features:
•
21x Enhanced GPIs (EGPIs) and 21x Enhanced GPOs (EGPOs) with asynchronous capture and serial
support per each PRU CPU core
•
One Ethernet MII_RT module (PRU-ICSS_MII_RT) with two MII ports and configurable connections to
PRUs
•
•
•
•
•
•
•
•
•
1 MDIO Port (PRU-ICSS_MII_MDIO)
One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
1 x 16550-compatible UART with a dedicated 192 MHz clock to support 12Mbps Profibus
1 Industrial Ethernet timer with 7/9 capture and 8 compare events
1 Enhanced Capture Module (ECAP)
1 Interrupt Controller (PRU-ICSS_INTC)
A flexible power management support
Integrated switched central resource with programmable priority
Parity control supported by all memories
For more information, see chapter Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem (PRU-ICSS) of the Device TRM.
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6.6 Memory Subsystem
6.6.1 EMIF
The EMIF module provides connectivity between DDR memory types and manages data bus read/write
accesses between external memory and device subsystems which have master access to the L3_MAIN
interconnect and DMA capability.
The EMIF module has the following capabilities:
•
•
Supports JEDEC standard-compliant DDR3/DDR3L-SDRAM memory types
2-GiB SDRAM address range over one chip-select. This range is configurable through the dynamic
memory manager (DMM) module
•
•
•
Supports SDRAM devices with one, two, four or eight internal banks
Supports SDRAM devices with single or dual die packages
Data bus widths:
–
–
–
–
128-bit L3_MAIN (system) interconnect data bus width
128-bit port for direct connection with MPU subsystem
32-bit SDRAM data bus width
16-bit SDRAM data bus width used in narrow mode
•
Supported CAS latencies:
DDR3: 5, 6, 7, 8, 9, 10 and 11
–
•
•
•
•
•
•
•
•
•
•
•
•
Supports 256-, 512-, 1024-, and 2048-word page sizes
Supported burst length: 8
Supports sequential burst type
SDRAM auto initialization from reset or configuration change
Supports self refresh and power-down modes for low power
Partial array self-refresh mode for low power.
Output impedance (ZQ) calibration for DDR3
Supports on-die termination (ODT) DDR3
Supports prioritized refresh
Programmable SDRAM refresh rate and backlog counter
Programmable SDRAM timing parameters
Write and read leveling/calibration and data eye training for DDR3.
The EMIF module does not support:
•
•
•
•
•
Burst chop for DDR3
Interleave burst type
Auto precharge because of better Bank Interleaving performance
DLL disabling from EMIF side
SDRAM devices with more than one die, or topologies which require more than one chip select on a
single EMIF channel
For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem
of the Device TRM.
6.6.2 GPMC
The General Purpose Memory Controller (GPMC) is an external memory controller of the device. Its data
access engine provides a flexible programming model for communication with all standard memories.
The GPMC supports the following various access types:
•
Asynchronous read/write access
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•
•
•
•
•
•
•
Asynchronous read page access (4, 8, and 16 Word16)
Synchronous read/write access
Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16)
Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16)
Address-data-multiplexed (AD) access
Address-address-data (AAD) multiplexed access
Little- and big-endian access
The GPMC can communicate with a wide range of external devices:
•
•
•
•
•
•
External asynchronous or synchronous 8-bit wide memory or device (non burst device)
External asynchronous or synchronous 16-bit wide memory or device
External 16-bit non-multiplexed NOR flash device
External 16-bit address and data multiplexed NOR Flash device
External 8-bit and 16-bit NAND flash device
External 16-bit pseudo-SRAM (pSRAM) device
The main features of the GPMC are:
•
•
8- or 16-bit-wide data path to external memory device
Supports up to eight CS regions of programmable size and programmable base addresses in a total
address space of 1 GiB
•
•
Supports transactions controlled by a firewall
On-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or
Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with
512-byte page size or greater)
•
•
•
•
Fully pipelined operation for optimal memory bandwidth use
The clock to the external memory is provided from GPMC functional clock divided by 1, 2, 3, or 4
Supports programmable autoclock gating when no access is detected
Independent and programmable control signal timing parameters for setup and hold time on a per-chip
basis. Parameters are set according to the memory device timing parameters, with a timing granularity
of one GPMC functional clock cycle.
•
Flexible internal access time control (WAIT state) and flexible handshake mode using external WAIT
pin monitoring
•
•
•
Support bus keeping
Support bus turnaround
Prefetch and write posting engine associated with to achieve full performance from the NAND device
with minimum effect on NOR/SRAM concurrent access
For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory
Subsystem of the Device TRM.
6.6.3 ELM
In the case of NAND modules with no internal correction capability, sometimes referred to as bare NAND,
the correction process can be delegated to the error location module (ELM) used in conjunction with the
GPMC.
The ELM supports the following features:
•
•
•
4, 8, and 16 bits per 512-byte block error location based on BCH algorithm
Eight simultaneous processing contexts
Page-based and continuous modes
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•
Interrupt generation when error location process completes:
–
–
When the full page has been processed in page mode
For each syndrome polynomial (checksum-like information) in continuous mode
For more information, see section Error Location Module (ELM) in chapter Memory Subsystem of the
Device TRM.
6.6.4 OCMC
There is one on-chip memory controller (OCMC) in the device.
The OCM Controller supports the following features:
•
•
L3_MAIN data interface:
–
–
–
Used for maximum throughput performance
128-bit data bus width
Burst supported
L4 interface (OCMC_RAM only):
–
–
–
–
Used for access to configuration registers
32-bit data bus width
Only single accesses supported
The L4 associated OCMC clock is two times lower than the L3 associated OCMC clock
•
Error correction and detection:
–
–
Single error correction and dual error detection
9-bit Hamming error correction code (ECC) calculated on 128-bit data word which is concatenated
with memory address bits
–
–
–
–
–
–
Hamming distance of 4
Enable/Disable mode control through a dedicated register
Single bit error correction on a read transaction
Exclusion of repeated addresses from correctable error address trace history
ECC valid for all write transactions to an enabled region
Sub-128-bit writes supported via read modify write
•
•
ECC Error Status Reporting:
–
–
Trace history buffer (FIFO) with depth of 4 for corrected error address
Trace history buffer with depth of 4 for non correctable error address and also including double
error detection
–
Interrupt generation for correctable and uncorrectable detected errors
ECC Diagnostics Configuration:
–
Counters for single error correction (SEC), double error detection (DED) and address error events
(AEE)
–
–
–
Programmable threshold registers for exeptions associated with SEC, DED and AEE counters
Register control for enabling and disabling of diagnostics
Configuration registers and ECC status accessible through L4 interconnect
•
Circular buffer for sliced based VIP frame transfers:
–
–
Up to 12 programmable circular buffers mapped with unique virtual frame addresses
On the fly (with no additional latency) address translation from virtual to OCMC circular buffer
memory space
–
–
–
–
Virtual frame size up to 8 MiB and circular buffer size up to 1 MiB
Error handling and reporting of illegal CBUF addressing
Underflow and Overflow status reporting and error handling
Last access read/write address history
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•
Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events
The OCM controller does not have a memory protection logic and does not support endianism conversion.
For more information, see section On-Chip Memory (OCM) in chapter Memory Subsystem of the Device
TRM.
6.7 Interprocessor Communication
6.7.1 MailBox
Communication between the on-chip processors of the device uses a queued mailbox-interrupt
mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel
between two processors through a set of registers and associated interrupt signals by sending and
receiving messages (mailboxes).
The device implements the following mailbox types:
•
System mailbox:
–
–
–
Number of instances: 13
Used for communication between: MPU, DSP1, IPU1, and IPU2 subsystems
Reference name: MAILBOX(1..13)
•
IVA mailbox:
–
–
Number of instances: 1
Used for communication between: IVA local user (ICONT1, or ICONT2) and three external users
(selected among MPU, DSP1, IPU1, and IPU2 subsystems)
–
Reference name: IVA_MBOX
Each mailbox module supports the following features:
•
Parameters configurable at design time
–
–
–
Number of users
Number of mailbox message queues
Number of messages (FIFO depth) for each message queue
•
•
•
•
32-bit message width
Message reception and queue-not-full notification using interrupts
Support of 16-/32-bit addressing scheme
Power management support
For more information, see chapter MailBox of the Device TRM.
6.7.2 Spinlock
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
•
•
•
Cortex®-A15 microprocessor unit (MPU) subsystem
Digital signal processor (DSP) subsystem – DSP1
Dual Cortex-M4 image processing unit (IPU) subsystems – IPU1 and IPU2
The Spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient
way to perform a lock operation of a device resource using a single read-access, avoiding the need of
a readmodify- write bus transfer that the programmable cores are not capable of.
For more information, see chapter Spinlock Module of the Device TRM.
6.8 Interrupt Controller
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The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The MPU, DSP, and IPU (x2) subsystems are capable of servicing these interrupts via their integrated
interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller
Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor
interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device
TRM.
Cortex®-A15 MPU Subsystem Interrupt Controller (MPU_INTC)
The MPU_INTC module (also called Generalized Interrupt Controller [GIC]) is a single functional unit that
is integrated in the Arm® Cortex-A15 multiprocessor core (MPCore) alongside Cortex-A15 processor. It
provides:
•
•
•
•
•
•
160 hardware interrupt inputs
Generation of interrupts by software
Prioritization of interrupts
Masking of any interrupts
Distribution of the interrupts to the target Cortex-A15 processor(s)
Tracking the status of interrupts
The Cortex-A15 processor supports three main groups of interrupt sources, with each interrupt source
having a unique ID:
•
Software Generated Interrupts (SGIs): SGIs are generated by writing to the Cortex-A15 Software
Generated Interrupt Register (GICD_SGIR). A maximum of 16 SGIs (ID0–ID15) can be generated for
the CPU interface. An SGI has edge-triggered properties. The software triggering of the interrupt is
equivalent to the edge transition of the interrupt signal on a peripheral input.
•
•
Private Peripheral Interrupts (PPIs): A PPI is an interrupt generated by a peripheral that is specific to
the processor. Although interrupts ID16–ID31 are dedicated to PPIs in general, only seven PPIs are
actually used for the CPU interface (ID25–ID31). Interrupts ID16–ID24 are reserved (not used).
Shared Peripheral Interrupts (SPIs): SPIs are triggered by events generated on associated interrupt
input lines. In this device, the GIC is configured to support 160 SPIs corresponding to its external
IRQS[159:0] signals.
For detailed information about this module and description of SGIs and PPIs, see the Arm Cortex-A15
MPCore Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).
C66x DSP Subsystem Interrupt Controller (DSP1_INTC)
The DSP1 subsystem integrates an interrupt controller - DSP1_INTC, which interfaces the system events
to the C66x core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized
interrupts presented to the C66x CPU.
For detailed information about this module, see chapter DSP Subsystem of the Device TRM.
Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPUx_Cx_INTC, where x = 1, 2)
There are two Image Processing Unit (IPU) subsystems in the device - IPU1, and IPU2. Each IPU
subsystem integrates two Arm Cortex-M4 cores.
A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping
is the same (per IPU) for the two cores to facilitate parallel processing. The NVIC supports:
•
64 external interrupts (in addition to 16 Cortex-M4 internal interrupts), which are dynamically prioritized
with 16 levels of priority defined for each core
•
•
•
•
Low-latency exception and interrupt handling
Prioritization and handling of exceptions
Control of the local power management
Debug accesses to the processor core
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For detailed information about this module, refer to Arm Cortex-M4 Technical Reference Manual (available
at infocenter.arm.com/help/index.jsp).
6.9 EDMA
The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service user-
programmed data transfers between two memory-mapped slave endpoints on the device.
Typical usage of the EDMA controller includes:
•
Servicing software-driven paging transfers (for example, data movement between external memory
[such as SDRAM] and internal memory [such as DSP L2 SRAM])
•
•
•
Servicing event-driven peripherals, such as a serial port
Performing sorting or sub-frame extraction of various data structures
Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the Arm
CorePac
The EDMA controller consists of two major principle blocks:
•
•
EDMA Channel Controller
EDMA Transfer Controller(s)
The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The
EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers.
The EDMACC serves to prioritize incoming software requests or events from peripherals and submits
transfer requests (TR) to the EDMA transfer controller.
The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets
(TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller
issues read/write commands to the source and destination addresses programmed for a given transfer.
There are two EDMA controllers present on this device:
•
EDMA_0, integrating:
–
–
1 Channel Controller, referenced as: EDMACC_0
2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1
(or EDMATC_1)
•
EDMA_1, integrating:
–
–
1 Channel Controller, referenced as: EDMACC_1
2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1
(or EDMATC_3)
The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For
simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to
EDMA Channel Controllers functionality and features.
The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and
EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be
regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and
features.
Each EDMACC has the following features:
•
Fully orthogonal transfer description
–
3 transfer dimensions:
•
•
•
Array (multiple bytes)
Frame (multiple arrays)
Block (multiple frames)
–
–
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
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•
•
Flexible transfer definition
–
–
–
Increment or constant addressing modes
Linking mechanism allows automatic PaRAM set update
Chaining allows multiple transfers to execute with one event
64 DMA channels
–
Channels triggered by either:
•
•
•
Event synchronization
Manual synchronization (CPU write to event set register)
Chain synchronization (completion of one transfer triggers another transfer)
–
Support for programmable DMA Channel to PaRAM mapping
•
8 Quick DMA (QDMA) channels
–
–
QDMA channels are triggered automatically upon writing to PaRAM set entry
Support for programmable QDMA channel to PaRAM mapping
•
•
•
512 PaRAM sets
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
2 transfer controllers/event queues
16 event entries per event queue
Interrupt generation based on:
–
–
–
–
Transfer completion
Error conditions
•
•
Debug visibility
–
–
Queue water marking/threshold
Error and status recording to facilitate debug
Memory protection support
–
–
Proxied memory protection for TR submission
Active memory protection for accesses to PaRAM and registers
Each EDMATC has the following features:
•
Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC
manages the 3rd dimension)
•
•
•
•
•
•
Up to 4 in-flight transfer requests (TR)
Programmable priority levels
Support for increment or constant addressing mode transfers
Interrupt and error support
Supports only little-endian operation in this device
Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR
For more information chapter EDMA Controller of the Device TRM.
6.10 Peripherals
6.10.1 VIP
The VIP module provides video capture functions for the device. VIP incorporates a multi-channel raw
video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)
engine to store incoming video in various formats. The device uses a single instantiation of the VIP
module giving the ability of capturing up to two video streams.
A VIP module includes the following main features:
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•
•
Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which
has two video input ports, Port A and Port B, where Port A can be configured as a 24/16/8-bit port, and
Port B is a fixed 8-bit port.
Each video Port A can be operated as a port with clock independent input channels (with interleaved or
separated Y/C data input). Embedded sync and external sync modes are supported for all input
configurations.
•
•
Support for a single external asynchronous pixel clock, up to 165MHz per port.
Pixel Clock Input Domain Port A supports up to one 24-bit input data bus, including BT.1120 style
embedded sync for 16-bit and 24-bit data.
•
•
•
Embedded Sync data interface mode supports single or multiplexed sources
Discrete Sync data interface mode supports only single source input
24-bit data input plus discrete syncs can be configured to include:
–
–
–
–
–
–
–
8-bit YUV422 (Y and U/V time interleaved)
16-bit YUV422 (CbY and CrY time interleaved)
24-bit YUV444
16-bit RGB565
24-bit RGB888
12/16-bit RAW Capture
24-bit RAW capture
•
•
•
Discrete sync modes include:
–
–
–
–
VSYNC + HSYNC (FID determined by FID signal pin or HSYNC/VSYNC skew)
VSYNC + ACTVID + FID
VBLANK + ACTVID (ACTVID toggles in VBLANK) + FID
VBLANK + ACTVID (no ACTVID toggles in VBLANK) + FID
Multichannel parser (embedded syncs only)
–
–
–
–
Embedded syncs only
Pixel (2x or 4x) or Line multiplexed modes supported
Performs demultiplexing and basic error checking
Supports maximum of 9 channels in Line Mux (8 normal + 1 split line)
Ancillary data capture support
–
–
For 16-bit or 24-bit input, ancillary data may be extracted from any single channel
For 8-bit time interleaved input, ancillary data can be chosen from the Luma channel, the Chroma
channel, or both channels
–
–
Horizontal blanking interval data capture only supported when using discrete syncs (VSYNC +
HSYNC or VSYNC + HBLANK)
Ancillary data extraction supported on multichannel capture as well as single source streams
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•
Format conversion and scaling
–
–
–
–
–
Programmable color space conversion
YUV422 to YUV444 conversion
YUV444 to YUV422 conversion
YUV422 to YUV420 conversion
YUV444 Source: YUV444 to YUV444, YUV444 to RGB888, YUV444 to YUV422, YUV444 to
YUV420
–
–
RGB888 Source: RGB888 to RGB888, RGB888 to YUV444, RGB888 to YUV422, RGB888 to
YUV420
YUV422 Source: YUV422 to YUV422, YUV422 to YUV420, YUV422 to YUV444, YUV422 to
RGB888
–
–
Supports RAW to RAW (no processing)
Scaling and format conversions do not work for multiplexed input
•
•
Supports up to 2047 pixels wide input - when scaling is engaged
Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without
scaling
•
•
Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling
The maximum supported input resolution is further limited by:
–
–
Pixel clock and feature-dependent constraints
For RGB24-bit format (RAW data), the maximum frame width is limited to 2730 pixels
For more information, see chapter Video Input Port of the Device TRM
6.10.2 DSS
Display Port Interfaces (DPI) is available in DSS named DPI Video Output (VOUT).
VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
For more information, see section Display Subsystem (DSS) of the Device TRM.
6.10.3 Timers
The device includes several types of timers used by the system software, including 16 general-purpose
(GP) timers, one watchdog timer, and a 32-kHz synchronized timer (COUNTER_32K).
6.10.3.1 General-Purpose Timers
The device has 16 GP timers: TIMER1 through TIMER16.
•
TIMER1(1ms tick): has its event capture pin tied to 32KHz clock and can be used to gauge the system
clock input and detects its frequency among 19.2, 20, or 27 MHz. It includes a specific functions to
generate accurate tick interrupts to the operating system and it belongs to the PD_WKUPAON domain
•
TIMER2 and TIMER10: (1ms tick timers): they include a specific functions to generate accurate tick
interrupts to the operating system, TIMER2 and TIMER10 belong to the PD_L4PER domain
•
•
•
TIMER3/4/9/11/13/14/15/16: they belongs to the PD_L4PER domain
TIMER12 belongs to the PD_WKUPAON power domain
TIMER5 trough TIMER8: belong to the PD_IPU module
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Each timer (except TIMER12) can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz
clock. The selection of clock source is made at the power, reset, and clock management (PRCM) module
level. TIMER12 can be clocked only from the internal oscillator (on-die oscillator)
The following are the main features of the GP timer controllers:
•
Level 4 (L4) slave interface support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
10-bit address bus width
Burst mode not supported
Write nonposted transaction mode supported
•
•
•
•
•
•
•
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Compare and capture modes
Autoreload mode
Start/stop mode
Programmable divider clock source (2n, where n = [0:8])
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
Dedicated GP output signal for using the TIMERi_GPO_CFG signal
On-the-fly read/write register (while counting)
1-ms tick with 32.768-Hz functional clock generated (only TIMER1, TIMER2, and TIMER10)
For more information, see section Timers of the Device TRM.
6.10.3.2 32-kHz Synchronized Timer (COUNTER_32K)
The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-
kHz system clock.
The main features of the 32-kHz synchronized timer controller are:
•
L4 slave interface (OCP) support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
16-bit address bus width
Burst mode not supported
Write nonposted transaction mode not supported
•
Only read operations are supported on the module registers; no write operation is supported (no
error/no action on write).
•
•
•
•
Free-running 32-bit upward counter
Start and keep counting after power-on reset
Automatic roll over to 0; highest value reached: 0xFFFF FFFF
On-the-fly read (while counting)
For more information, see section Timers of the Device TRM.
6.10.3.3 Watchdog Timer
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2.
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The watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt
to the device system modules following an overflow condition. The WD_TIMER2 timer serves resets to the
PRCM module (its interrupt outputs are unused).
WD_TIMER2 is located in the PD_WKUPAON power domain, and can run when the device is in lowest
power state (all power domains are off except always-on (AON) and WKUP).
The watchdog timer can be accessed, loaded, and cleared by registers through the L4_WKUP interface.
The watchdog timer has the 32-kHz clock for its timer clock input. WD_TIMER2 directly generates a warm
reset condition on overflow.
WD_TIMER2 connects to a single target agent port on the L4_WKUP interconnect.
The main features of the watchdog timer controllers are:
•
L4 slave interface support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
11-bit address bus width
Burst mode not supported
Write nonposted mode supported
•
•
•
•
•
•
•
Free-running 32-bit upward counter
Programmable divider clock source (2n where n = [0:7])
On-the-fly read/write register (while counting)
Subset programming model of the GP timer
The watchdog timer is reset either on power on or after a warm reset before it starts counting.
Reset or interrupt actions when a timer overflow condition occurs
The watchdog timer generates a reset or an interrupt in its hardware integration.
For more information, see section Timers of the Device TRM.
6.10.4 I2C
The device contains five multimaster high-speed (HS) inter-integrated circuit (I2C) controllers (I2Ci
modules, where i = 1, 2, 3, 4, 5) each of which provides an interface between a local host (LH), such as a
digital signal processor (DSP), and any I2C-bus-compatible device that connects through the I2C serial
bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to
and from the LH device through the 2-wire I2C interface.
Each multimaster HS I2C controller can be configured to act like a slave or master I2C-compatible device.
I2C1 and I2C2 controllers have dedicated I2C compliant open drain buffers, and support Fast mode (up to
400Kbps).
I2C3, I2C4 and I2C5 controllers are multiplexed with standard LVCMOS IO and connected to emulate open
drain. I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high
when transmitting logic 1. These controllers support HS mode (up to 3.4Mbps).
For more information, see section Multimaster High-Speed I2C Controller (I2C) in chapter Serial
Communication Interfaces of the Device TRM.
6.10.5 UART
The UART is a simple L4 slave peripheral that utilizes the DMA_SYSTEM or EDMA for data transfer or
IRQ polling via CPU. There are 10 UART modules in the device. Only one UART supports IrDA features.
Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
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6.10.5.1 UART Features
The UARTi (where i = 1 to 10) include the following features:
•
•
•
•
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Programmable interrupt trigger levels for FIFOs
Baud generation based on programmable divisors N (where N = 1…16,384) operating from a fixed
functional clock of 48 MHz or 192 MHz
Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two
options:
•
•
•
Baud rate = (functional clock / 16) / N
Baud rate = (functional clock / 13) / N
This software programming mode enables higher baud rates with the same error amount without
changing the clock source
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
The 48 MHz functional clock option allows baud rates up to 3.6Mbps
The 192 MHz functional clock option allows baud rates up to 12Mbps
UART1 module has extended modem control signals (DCD, RI, DTR, DSR)
UART3 supports IrDA
6.10.5.2 IrDA Features
UART3 supports the following IrDA key features:
•
Support of IrDA 1.4 slow infrared (SIR), medium infrared (MIR), and fast infrared (FIR)
communications:
–
Frame formatting: Addition of variable beginning-of-frame (xBOF) characters and end-of-frame
(EOF) characters
–
–
–
–
Uplink/downlink cyclic redundancy check (CRC) generation/detection
Asynchronous transparency (automatic insertion of break character)
Eight-entry status FIFO (with selectable trigger levels) to monitor frame length and frame errors
Framing error, CRC error, illegal symbol (FIR), and abort pattern (SIR, MIR) detection
6.10.5.3 CIR Features
The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a
programmable t period) to encompass the various formats of infrared encoding for remote-control
applications. The CIR logic transmits data packets based on a user-definable frame structure and packet
content.
The CIR (UART3 only) includes the following features to provide CIR support for remote-control
applications:
•
•
•
•
•
Transmit mode only (receive mode is not supported)
Free data format (supports any remote-control private standards)
Selectable bit rate
Configurable carrier frequency
1/2, 5/12, 1/3, or 1/4 carrier duty cycle
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For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Serial
Communication Interfaces of the Device TRM.
6.10.6 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (McSPI1,
McSPI2, McSPI3, and McSPI4) in the device. All these four modules support up to four external devices
(four chip selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of McSPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
McSPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
•
•
•
Single interrupt line for multiple interrupt source events
Power management through wake-up capabilities
Enable the addition of a programmable start-bit for McSPI transfer per channel (start-bit mode)
Supports start-bit write command
Supports start-bit pause and break sequence
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel
For more information, see section Serial Peripheral Interface (McSPI) in chapter Serial Communication
Interfaces of the Device TRM.
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6.10.7 QSPI
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only.
The QSPI supports the following features:
•
General SPI features:
–
–
–
–
–
–
–
–
–
–
–
–
Programmable clock divider
Six pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
4 external chip-select signals
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Programmable signal polarities
Programmable active clock edge
Software-controllable interface allowing for any type of SPI transfer
Control through L3_MAIN configuration port
•
Serial flash interface (SFI) features:
–
–
–
–
Serial flash read/write interface
Additional registers for defining read and write commands to the external serial flash device
1 to 4 address bytes
Fast read support, where fast read requires dummy bytes after address bytes; 0 to 3 dummy bytes
can be configured.
–
–
–
–
Dual read support
Quad read support
Little-endian support only
Linear increment addressing mode only
The QSPI supports only dual and quad reads. Dual or quad writes are not supported. In addition, there is
no "pass through" mode supported where the data present on the QSPI input is sent to its output.
For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Serial
Communication Interfaces of the Device TRM.
6.10.8 McASP
The MCASP functions as a general-purpose audio serial port optimized to the requirements of various
audio applications. The McASP module can operate in both transmit and receive modes. The McASP is
useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and
transmission as well as for an intercomponent digital audio interface transmission (DIT). The McASP has
the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer
component.
Although intercomponent digital audio interface reception (DIR) mode (i.e. S/PDIF stream receiving) is not
natively supported by the McASP module, a specific TDM mode implementation for the McASP receivers
allows an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
•
•
McASP1 and McASP2 supporting 16 channels with independent TX/RX clock/sync domain
McASP3 through McASP7 modules supporting 4 channels with independent TX/RX clock/sync domain
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•
McASP8 supporting 2 channels with independent TX/RX clock/sync domain
For more information, see section Multichannel Audio Serial Port (McASP) in chapter Serial
Communication Interfaces of the Device TRM.
6.10.9 USB
SuperSpeed USB DRD Subsystem has three instances in the device providing the following functions:
•
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY
•
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY
SuperSpeed USB DRD Subsystem has the following features:
• Dual-role-device (DRD) capability:
–
Supports USB Peripheral (or Device) mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps),
and FS (12 Mbps)
–
Supports USB Host mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps), FS (12 Mbps), and
LS (1.5 Mbps)
–
–
–
–
–
USB static peripheral operation
USB static host operation
Flexible stream allocation
Stream priority
External Buffer Control
•
Each instance contains single xHCI controller with the following features:
–
–
–
–
–
–
–
Internal DMA controller
Descriptor caching and data prefetching
Interrupt moderation and blocking
Power management USB3.0 states for U0, U1, U2, and U3
Dynamic FIFO memory allocation for all endpoints
Supports all modes of transfers (control, bulk, interrupt, and isochronous)
Supports high bandwidth ISO mode
•
•
Connects to an external charge pump for VBUS 5 V generation
USB-HS PHY (USB2PHY1 and USB2PHY2 for USB1 and USB2, respectively): contain the USB
functions, drivers, receivers, and pads for correct D+/D– signalling
For more information, see section SuperSpeed USB DRD (USB) in chapter Serial Communication
Interfaces of the Device TRM.
6.10.10 PCIe
The Peripheral Component Interconnect Express (PCIe) module is a multi-lane I/O interconnect that
provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane,
per direction, for serial links on backplanes and printed wiring boards. It is a 3-rd Generation I/O
Interconnect technology succeeding PCI and ISA bus that is designed to be used as a general-purpose
serial I/O interconnect. It is also used as a bridge to other interconnects like USB2/3.0, GbE MAC, and so
forth.
The PCI Express standard predecessor - PCI, is a parallel bus architecture that is increasingly difficult to
scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe
architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the
necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It
is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its
practical performance limits while simplifying the interface design.
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The device instantiates two PCIe subsystems (PCIe_SS1 and PCIe_SS2). The PCIe controller is capable
to operate either in Root Complex (RC) or in End Point (EP) PCIe mode. The device PCIe_SS1 controller
supports up to two 16-bit data lanes on its PIPE port. The device PCIe_SS2 controller supports only one
16-bit data lane on its PIPE port.
When the PCIe_SS1 controller PIPE port is configured to operate in a single-lane mode, it operates on a
single pair of PCIe PHY serializer and deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX. When PCIe_SS1
PIPE is configured to operate in dual-lane mode, it operates on two pairs of PCIe PHY serializer and
deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX and PCIe2_PHY_TX/PCIe2_PHY_RX, respectively. The
single-lane PCIe_SS2 controller PIPE port (if enabled) can operate only on the
PCIe2_PHY_TX/PCIe2_PHY_RX pair. Hereby, if PCIe_SS2 controller is used, the PCIe_SS1 can operate
only in a single-lane mode on the PCIe1_PHY_TX/PCIe1_PHY_RX. In addition, PCIe PHY subsystem
encompasses a PCIe PCS (physical coding sublayer), a PCIe power management logic, APLL, a DPLL
reference clock generator and an APLL clock low-jitter buffer.
•
•
The PCIe Controller implements the transport and link layers of the PCIe interface protocol.
PCIe PCS (a physical coding sublayer component) converts a 8-bit portion of parallel data over a PCIe
lane to a 10-bit parallel data to adapt the process of serialization and deserialization in the TX/RX
PHYs to various requirements. At the same time it transforms the transmission rate to maintain the
PCIe Gen2 bandwidth (5 Gbps) on both sides (PCIe controller and PHY).
•
•
A multiplexer logic which adds flexibility to connect a PCIe controller hardware mapped PCS logic
output to a single (for the single-lane PCIe_SS2 controller) or to a couple (for the 2-lane PCIe_SS1
controller) of PHY ports at a time
Physical layer (PHY) serializer/deserializer components with associated power control logic, building
the so called PMA (physical media attachment) part of the PCIe_PHY transceiver, as follows:
–
PCIe physical port 0 associated serializer (TX) - PCIe1_PHY_TX and deserializer (RX) -
PCIe1_PHY_RX
–
PCIe physical port 1 associated serializer (TX) - PCIe2_PHY_TX and deserializer (RX) -
PCIe2_PHY_RX
•
•
•
DPLL_PCIe_REF is a DPLL clock source, controlled from the device PRCM, that provides a 100-MHz
clock to the PCIe PHY serializer/deserializer components reference clock inputs.
Both the PCIe_SS1 and PCIe_SS2 share the same APLL (APLLPCIe) which by default multiplies the
DPLL_PCIe_REF (typically 100 MHz or 20 MHz) clock to 2.5 GHz.
The APLLPCIe low-jitter buffer (ACSPCIE) and additional logic takes care to provide the PCIe APLL
reference input clock.
PCIe module supports the following features:
•
•
PCI Local Bus Specification revision 3.0
PCI Express Base 3.0 Specification, revision 1.0.
At system level the device supports PCI express interface in the following configurations:
•
•
•
•
Each PCIe subsystem controller has support for PCIe Gen2 mode (5.0 Gbps per lane) and Gen1 mode
(2.5 Gbps per lane).
One PCIe (PCIe_SS1) operates as Gen2 2-lanes supporting in either root-complex (RC) or end-point
EP.
Two PCIe (PCIe_SS1 and PCIe_SS2) operates Gen2 1-lane supporting either RC or EP with the
possibility of one operating in Gen1 and one in Gen2.
PCIe_SS1 can be configured to operate in either 2-Lane (dual lane) or 1-Lane (single lane) mode, as
follows:
–
–
Single Lane - lane 0 mapped to the PCIe port 0 of the device
Flexible dual lane configuration - lanes 0 and 1 can be swapped on the two PCIe ports
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•
PCIe_SS2 can only operate in 1-Lane mode, as follows:
Single Lane - lane 0 mapped to the device PCIe port 1
–
When PCIe_SS1 is configured to operate in dual-lane mode, PCIe_SS2 is in-operable as both
PCIe1_PHY_RX/TX and PCIe2_PHY_RX/TX are assigned to PCIe_SS1, and thereby NOT available to
PCIe_SS2.
The main features of a device PCIe controller are:
•
•
•
16-bit operation at 250 MHz on PIPE interface (per 16-bit lane)
One master port on the L3_MAIN supporting 32-bit address and 64-bit data bus.
PCIe_SS1 master port dedicated MMU (device MMU2) on L3_MAIN path, to which PCIe traffic can be
optionally mapped.
•
•
One slave port on the L3_MAIN supporting 29-bit address and 64-bit data bus.
Maximum outbound payload size of 64 Bytes (the L3 Interconnect PCIe1/2 target ports split bursts of
size >64 Bytes to the into multiple 64 Byte bursts)
•
•
•
•
•
Maximum inbound payload size of 256 Bytes (internally converted to 128 Byte - bursts)
No remote read request size limit: implicit support for 4 KiB-size and greater
Support of EP legacy mode
Support of inbound I/O accesses in EP legacy mode
PIPE interface features fixed-width (16-bit data per lane) and dynamic frequency to switch between
PCIe Gen1 and Gen2.
•
•
Ultra-low transmit and receive latency
Automatic Lane reversal as specified in the PCI Express Base 3.0 Specification, revision 1.0 (transmit
and receive)
•
•
•
•
•
•
•
•
•
•
•
•
•
Polarity inversion on receive
Single Virtual Channel (VC0) and Single Traffic Class (TC0)
Single Function in End point mode
Automatic credit management
ECRC generation and checking
All PCI Device Power Management D-states with the exception of D3cold/L2 state
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
PCI Express Link Power Management states except for L2 state
PCI Express Advanced Error Reporting (AER)
PCI Express messages for both transmit and receive
Filtering for Posted, Non-Posted, and Completion traffic
Configurable BAR filtering, I/O filtering, configuration filtering and completion lookup/timeout
Access to configuration space registers and external application memory mapped registers through
ECAM mechanism.
•
•
Legacy PCI Interrupts reception (RC) and generation (EP)
2 x hardware interrupts per PCIe_SS1 and PCIe_SS2 controller mapped via the device Interrupt
Crossbar (IRQ_CROSSBAR) to multiple device host (MPU, DSP, and so forth) interrupt controllers in
the device
•
•
MSIs generation and reception
PCIe_PHY Loopback in RC mode
For more information, see section PCIe Controller in chapter Serial Communication Interfaces of the
Device TRM.
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6.10.11 DCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time applications. CAN has high immunity to electrical interference and the ability to self-
diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Direct access to Message RAM during test mode
CAN Rx/Tx pins are configurable as general-purpose IO pins
Two interrupt lines (plus additional parity-error interrupts line)
RAM initialization
DMA support
For more information, see section Controller Area Network Interface (DCAN) in chapter Serial
Communication Interfaces of the Device TRM.
6.10.12 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the gigabit media independent interface (G/MII) in
MII mode, reduced gigabit media independent interface (RGMII), reduced media independent interface
(RMII), and the management data input output (MDIO) for physical layer device (PHY) management.
The GMAC_SW subsystem provides the following features:
•
Two Ethernet ports (port 1 and port 2) with selectable RGMII, RMII, and G/MII (in MII mode only)
interfaces plus internal Communications Port Programming Interface (CPPI 3.1) on port 0
•
•
•
•
•
•
•
•
Synchronous 10/100/1000 Mbit operation
Wire rate switching (802.1d)
Non-blocking switch fabric
Flexible logical FIFO-based packet buffer structure
Four priority level Quality Of Service (QOS) support (802.1p)
CPPI 3.1 compliant DMA controllers
Support for Audio/Video Bridging (P802.1Qav/D6.0)
Support for IEEE 1588 Clock Synchronization (2008 Annex D and Annex F)
–
Timing FIFO and time stamping logic embedded in the subsystem
•
•
•
Device Level Ring (DLR) Support
Energy Efficient Ethernet (EEE) support (802.3az)
Flow Control Support (802.3x)
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•
Address Lookup Engine (ALE)
–
–
–
–
–
–
–
–
–
–
–
1024 total address entries plus VLANs
Wire rate lookup
Host controlled time-based aging
Multiple spanning tree support (spanning tree per VLAN)
L2 address lock and L2 filtering support
MAC authentication (802.1x)
Receive-based or destination-based multicast and broadcast rate limits
MAC address blocking
Source port locking
OUI (Vendor ID) host accept/deny feature
Remapping of priority level of VLAN or ports
•
•
VLAN support
802.1Q compliant
–
•
•
Auto add port VLAN for untagged frames on ingress
Auto VLAN removal on egress and auto pad to minimum frame size
Ethernet Statistics:
–
–
EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (shared)
Programmable statistics interrupt mask when a statistic is above one half its 32-bit value
•
•
•
•
•
•
•
•
•
Flow Control Support (802.3x)
Digital loopback and FIFO loopback modes supported
Maximum frame size 2016 bytes (2020 with VLAN)
8k (2048 × 32) internal CPPI buffer descriptor memory
Management Data Input/Output (MDIO) module for PHY Management
Programmable interrupt control with selected interrupt pacing
Emulation support
Programmable Transmit Inter Packet Gap (IPG)
Reset isolation (switch function remains active even in case of all device resets except for POR pin
reset and ICEPICK cold reset)
•
•
Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps.
IEEE 802.3 gigabit Ethernet conformant
For more information, see section Gigabit Ethernet Switch (GMAC_SW) in chapter Serial Communication
Interfaces of the Device TRM.
6.10.13 eMMC/SD/SDIO
The eMMC/SD/SDIO host controller provides an interface between a local host (LH) such as a
microprocessor unit (MPU) or digital signal processor (DSP) and either eMMC, SD® memory cards, or
SDIO cards and handles eMMC/SD/SDIO transactions with minimal LH intervention.
Optionally, the controller is connected to the L3_MAIN interconnect to have a direct access to system
memory. It also supports two direct memory access (DMA) slave channels or a DMA master access (in
this case, slave DMA channels are deactivated) depending on its integration.
The eMMC/SD/SDIO host controller deals with eMMC/SD/SDIO protocol at transmission level, data
packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.
The application interface can send every eMMC/SD/SDIO command and poll for the status of the adapter
or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.
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The application interface can read card responses or flag registers. It can also mask individual interrupt
sources. All these operations can be performed by reading and writing control registers. The
eMMC/SD/SDIO host controller also supports two DMA channels.
There are four eMMC/SD/SDIO host controllers inside the device. gives an overview of the
eMMC/SD/SDIOi (i = 1 to 4) controllers.
Each controller has the following data width:
•
•
•
•
eMMC/SD/SDIO1 - 4-bit wide data bus
eMMC/SD/SDIO2 - 8-bit wide data bus
eMMC/SD/SDIO3 - 8-bit wide data bus
eMMC/SD/SDIO4 - 4-bit wide data bus
The eMMC/SD/SDIOi controller is also referred to as MMCi.
Compliance with standards:
•
•
•
•
Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC
standard specification, v4.5.
Full compliance with SD command/response sets as defined in the SD Physical Layer specification
v3.01
Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume
operations as defined in the SD part E1 specification v3.00
Full compliance with SD Host Controller Standard Specification sets as defined in the SD card
specification Part A2 v3.00
Main features of the eMMC/SD/SDIO host controllers:
•
•
•
•
•
•
•
•
Flexible architecture allowing support for new command structure
32-bit wide access bus to maximize bus throughput
Designed for low power
Programmable clock generation
Dedicated DLL to support SDR104 mode (MMC1 only)
Dedicated DLL to support HS200 mode (MMC2 only)
Card insertion/removal detection and write protect detection
L4 slave interface supports:
–
–
–
–
–
32-bit data bus width
8/16/32 bit access supported
9-bit address bus width
Streaming burst supported only with burst length up to 7
WNP supported
•
L3 initiator interface Supports:
–
–
–
–
32-bit data bus width
8/16/32 bit access supported
32-bit address bus width
Burst supported
•
•
•
•
•
Built-in 1024-byte buffer for read or write
Two DMA channels, one interrupt line
Support JC 64 v4.4.1 boot mode operations
Support SDA 3.00 Part A2 programming model
Support SDA 3.00 Part A2 DMA feature (ADMA2)
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•
Supported data transfer rates:
–
MMCi supports the following SD v3.0 data transfer rates:
•
•
•
•
•
•
•
DS mode (3.3V IOs): up to 12 MBps (24 MHz clock)
HS mode (3.3V IOs): up to 24 MBps (48 MHz clock)
SDR12 (1.8V IOs): up to 12 MBps (24 MHz clock)
SDR25 (1.8V IOs): up to 24 MBps (48 MHz clock)
SDR50 (1.8V IOs): up to 48 MBps (96 MHz clock) - MMC1 and MMC3 only
DDR50 (1.8V IOs): up to 48 MBps (48 MHz clock) - MMC1 only
SDR104 (1.8V IOs) cards can be supported up to 192 MHz clock (96 MBps max) - MMC1 only
–
–
MMCi supports the Default SD mode 1-bit data transfer up to 24Mbps (3MBps)
Only MMC2 supports also the following JC64 v4.5 data transfer rates:
•
•
Up to 192 MBps in eMMC mode, 8-bit SDR mode (192 MHz clock frequency)
Up to 96 MBps in eMMC mode, 8-bit DDR mode (48 MHz clock frequency)
•
All eMMC/SD/SDIO controllers are connected to 1.8V/3.3V compatible I/Os to support 1.8V/3.3V
signaling
注
eMMC functionality is supported fully by MMC2 only. The other MMC modules are capable of
eMMC functionality, but are not timing-optimized for eMMC.
The differences between the eMMC/SD/SDIO host controllers and a standard SD host controller defined
by the SD Card Specification, Part A2, SD Host Controller Standard Specification, v3.0 are:
•
The clock divider in the eMMC/SD/SDIO host controller supports a wider range of frequency than
specified in the SD Memory Card Specifications, v3.0. The eMMC/SD/SDIO host controller supports
odd and even clock ratio.
•
•
•
The eMMC/SD/SDIO host controller supports configurable busy time-out.
ADMA2 64-bit mode is not supported.
There is no external LED control.
注
Only even ratios are supported in DDR mode.
For more information, see chapter eMMC/SD/SDIO of the Device TRM.
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6.10.14 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks.
Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus,
the general-purpose interface supports up to 256 (8 × 32) pins. Since some of the pins are reserved in this
Device, general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations.
•
Wake-up request generation in idle mode upon the detection of external events
For more information, see section General-Purpose Interface (GPIO) of the Device TRM.
6.10.15 ePWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
Each ePWM module supports the following features:
•
•
Dedicated 16-bit time-base counter with period and frequency control
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
–
–
–
Two independent PWM outputs with single-edge operation
Two independent PWM outputs with dual-edge symmetric operation
One independent PWM output with dual-edge asymmetric operation
•
•
•
•
•
Asynchronous override control of PWM signals through software.
Programmable phase-control support for lag or lead operation relative to other ePWM modules.
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
Dead-band generation with independent rising and falling edge delay control.
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault
conditions.
•
A trip condition can force either high, low, or high-impedance state logic levels at PWM
outputs.
•
•
Programmable event prescaling minimizes CPU overhead on interrupts.
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
For more information, see section Enhanced PWM (ePWM) Module in chapter Pulse-Width Modulation
Subsystem of the Device TRM.
6.10.16 eCAP
Uses for eCAP include:
•
•
•
Sample rate measurements of audio inputs
Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor pulses
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•
•
•
4 stage sequencer (Mod4 counter) which is synchronized to external events (ECAPx pin edges)
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
•
32-bit time base counter
4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event time-stamps
Continuous mode capture of time-stamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All above resources dedicated to a single input pin
When not used in capture mode, the ECAP module can be configured as a single channel PWM output
For more information, see section Enhanced Capture (eCAP) Module in chapter Pulse-Width Modulation
Subsystem of the Device TRM.
6.10.17 eQEP
A single track of slots patterns the periphery of an incremental encoder disk, as shown in 图 6-2. These
slots create an alternating pattern of dark and light lines. The disk count is defined as the number of
dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to
generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an
absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position, and zero reference.
QEPA
QEPB
QEPI
eqep-001
图 6-2. Optical Encoder Disk
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of
phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The
clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB
channel.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
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For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Pulse-
Width Modulation Subsystem of the Device TRM.
6.11 On-chip Debug
Debugging a system that contains an embedded processor involves an environment that connects high-
level debugging software running on a host computer to a low-level debug interface supported by the
target device. Between these levels, a debug and trace controller (DTC) facilitates communication
between the host debugger and the debug support logic on the target chip.
The DTC is a combination of hardware and software that connects the host debugger to the target system.
The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the
debugger user to JTAG® commands and scans that execute the core hardware.
The debug software and hardware components let the user control multiple central processing unit (CPU)
cores embedded in the device in a global or local manner. This environment provides:
•
•
•
Synchronized global starting and stopping of multiple processors
Starting and stopping of an individual processor
Each processor can generate triggers that can be used to alter the execution flow of other processors
System topics include but are not limited to:
•
•
•
System clocking and power-down issues
Interconnection of multiple devices
Trigger channels
For more information, see chapter On-chip Debug of the Device TRM.
The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It
provides the following features:
•
External debug interfaces:
–
Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)
•
•
Used for debugger connection
Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7
adapter module
•
Controls ICEPick (generic test access port [TAP] for dynamic TAP insertion) to allow the
debugger to access several debug resources through its secondary (output) JTAG ports (for
more information, see ICEPick Secondary TAPs section of the Device TRM).
–
Debug (trace) port
•
•
•
Can be used to export processor or system trace off-chip (to an external trace receiver)
Can be used for cross-triggering with an external device
Configured through debug resources manager (DRM) module instantiated in the debug
subsystem
•
For more information about debug (trace) port, see Debug (Trace) Port and Concurrent Debug
Modes sections of the Device TRM.
•
•
JTAG based processor debug on:
–
–
–
–
Cortex-A15 in MPU
C66x in DSP1
Cortex-M4 (x2) in IPU1, IPU2
Arm968 (x2) in IVA
Dynamic TAP insertion
–
–
Controlled by ICEPick
For more information, see , Dynamic TAP Insertion.
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•
Power and clock management
–
–
–
–
Debugger can get the status of the power domain associated to each TAP.
Debugger may prevent the application software switching off the power domain.
Application power management behavior can be preserved during debug across power transitions.
For more information, see Power and Clock Management section of the Device TRM.
•
•
Reset management
–
–
Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
For more information, see Reset Management section of the Device TRM.
Cross-triggering
–
Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to
another:
•
Subsystem A can be programmed to generate a debug event, which can then be exported as a
global trigger across the device.
•
Subsystem B can be programmed to be sensitive to the trigger line input and to generate an
action on trigger detection.
–
–
Two global trigger lines are implemented
Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the
debug subsystem
–
Various Arm® CoreSight™ cross-trigger modules implemented to provide support for CoreSight
triggers distribution
•
•
CoreSight Cross-Trigger Interface (CS_CTI) modules
CoreSight Cross-Trigger Matrix (CS_CTM) modules
–
For more information about cross-triggering, see Cross-Triggering section of the Device TRM.
•
•
Suspend
–
Provides a way to stop a closely coupled hardware process running on a peripheral module when
the host processor enters debug state
–
For more information about suspend, see Suspend section of the Device TRM.
MPU watchpoint
–
–
–
Embedded in MPU subsystem
Provides visibility on MPU to EMIF direct paths
For more information, see MPU Memory Adaptor (MPU_MA) Watchpoint section of the Device
TRM.
•
Processor trace
–
–
–
–
Cortex-A15 (MPU) and C66x (DSP) processor trace is supported
Program trace only for MPU (no data trace)
MPU trace supported by a CoreSight Program Trace Macrocell (CS_PTM) module
Three exclusive trace sinks:
•
•
•
CoreSight Trace Port Interface Unit (CS_TPIU) – trace export to an external trace receiver
CTools Trace Buffer Router (CT_TBR) in system bridge mode – trace export through USB
CT_TBR in buffer mode – trace history store into on-chip trace buffer
–
For more information, see Processor Trace section of the Device TRM.
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•
System instrumentation (trace)
–
Supported by a CTools System Trace Module (CT_STM), implementing MIPI System Trace
Protocol (STP) (rev 2.0)
–
Real-time software trace
•
•
MPU software instrumentation through CoreSight STM (CS_STM) (STP2.0)
System-on-chip (SoC) software instrumentation through CT_STM (STP2.0)
–
–
OCP watchpoint (OCP_WP_NOC)
•
OCP target traffic monitoring: OCP_WP_NOC can be configured to generate a trigger upon
watchpoint match (that is, when target transaction attributes match the user-defined attributes).
•
•
SoC events trace
DMA transfer profiling
Statistics collector (performance probes)
•
Computes traffic statistics within a user-defined window and periodically reports to the user
through the CT_STM interface
•
•
Embedded in the L3_MAIN interconnect
10 instances:
–
–
1 instance dedicated to target (SDRAM) load monitoring
9 instances dedicated to master latency monitoring
–
–
–
IVA instrumentation (hardware accelerator [HWA] profiling)
•
Supported through a software message and system trace event (SMSET) module embedded in
the IVA subsystem
Power-management events profiling (PM instrumentation [PMI])
•
Monitoring major power-management events. The PM state changes are handled as generic
events and encapsulated in STP messages.
Clock-management events profiling (CM instrumentation [CMI])
•
Monitoring major clock management events. The CM state changes are handled as generic
events and encapsulated in STP messages.
•
Two instances, one per CM
–
–
CM1 Instrumentation (CMI1) module mapped in the PD_CORE_AON power domain
CM2 Instrumentation (CMI2) module mapped in the PD_CORE power domain
–
For more information, see System Instrumentation section of the Device TRM.
•
Performance monitoring
–
–
Supported by subsystem counter timer module (SCTM) for IPU
Supported by performance monitoring unit (PMU) for MPU subsystem
For more information, see chapter On-Chip Debug Support of the Device TRM.
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7 Applications, Implementation, and Layout
注
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Power Supply Mapping
TPS659163 or LP8733 are the Power Management IC (PMIC) that should be used for Device designs. TI
requires use of this PMIC for the following reasons:
•
•
TI has validated their use with the Device
Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
•
•
Support for power sequencing requirements (refer to Section 5.10.3, Power Supply Sequences)
Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSs, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail. It is possible that
some voltage domains on the device are unused in some systems. In such cases, to ensure device
reliability, it is still required that the supply pins for the specific voltage domains are connected to some
core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. For example, if DSP domain is not used, they can be combined with the CORE domain, thereby
having a single power supply driving the combined CORE and DSP domains.
For the combined rail, the following relaxations do apply:
•
•
The AVS voltage of active rail in the combined rail needs to be used to set the power supply
The decoupling capacitance should be set according to the active rail in the combined rail
表 7-1 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659163 PMIC.
表 7-1. TPS659163 Power Supply Connections(1)
SMPS
SMPS1
SMPS2
SMPS3
SMPS4
Valid Combination
VD_CORE
TPS659163 Current Limitation (2) (3)
3.5A
3.5A
3A
Free (DDR Memory)
VD_DSP
VDDS18V
1.5A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Refer to the PMIC data manual for the latest TPS659163 specifications.
(3) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
表 7-2 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the LP8733 PMIC.
表 7-2. LP8733 Power Supply Connections
SMPS
Valid Combination
VD_CORE
LP8733 Current Limitation(1) (2) (3)
SMPS1
SMPS2
3A
3A
VD_DSP
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(1) Refer to the LP8733 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(3) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
7.2 DDR3 Board Design and Layout Guidelines
7.2.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
•
•
•
•
•
•
•
•
•
•
•
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
7.2.2 DDR3 Board Design and Layout Guidelines
7.2.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in 表 7-3 and 图
7-1.
表 7-3. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CLK)
Cycle time, DDR_CLK
1.5
2.5(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
图 7-1. DDR3 Memory Controller Clock Timing
7.2.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF.
7.2.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting, 表
7-4 summarizes the supported device configurations.
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表 7-4. Supported DDR3 Device Combinations
DDR3 DATA DEVICE WIDTH
(BITS)
NUMBER OF DDR3 DEVICES
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
2
2
3
4
4
5
16
8
N
Y(1)
N
Y(1)
N(3)(4)
N
16
16
32
32
32
32
32
32
16
16
16
8
8
Y(2)
(3)(4)
8
N
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) This is two mirrored pairs of DDR3 devices.
(3) Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the
AM57xx family of devices.
(4) The DDR memory connected to the DDR ECC bus does NOT need to be the same part number as the DDR memories connected to the
DDR data bus. However, some constraints do apply. When selecting a memory for the DDR ECC bus, the following restrictions must be
adhered to as compared to the DDR memories on the data bus:
–
–
–
–
Match the same DDR3 speed grade
Have an equal number of internal banks
Have an equal number of columns
Have a greater or equal number of rows
7.2.2.4 DDR3 Interface Schematic
7.2.2.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. 图 7-2 and 图 7-3 show the schematic connections for 32-bit interfaces
using x16 devices.
7.2.2.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see 图 7-2 and
图 7-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
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32-bit DDR3 EMIF
16-Bit DDR3
Devices
ddr1_d31
8
DQ15
DQ8
ddr1_d24
ddr1_dqm3
ddr1_dqs3
ddr1_dqsn3
UDM
UDQS
UDQS
ddr1_d23
8
DQ7
ddr1_d16
ddr1_dqm2
ddr1_dqs2
ddr1_dqsn2
D08
LDM
LDQS
LDQS
ddr1_d15
8
DQ15
DQ8
ddr1_d8
ddr1_dqm1
ddr1_dqs1
ddr1_dqsn1
UDM
UDQS
UDQS
DQ7
ddr1_d7
8
ddr1_d0
ddr1_dqm0
ddr1_dqs0
ddr1_dqsn0
ddr1_ck
DQ0
LDM
LDQS
LDQS
CK
0.1 µF
Zo
Zo
CK
CK
DDR_1V5
ddr1_nck
CK
ddr1_odt0
ddr1_csn0
ddr1_odt1
ddr1_csn1
ODT
CS
ODT
CS
ddr1_ba0
ddr1_ba1
ddr1_ba2
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
ddr1_a0
16
Zo
Zo
ddr1_a15
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_cke
ddr1_rst
A15
A15
CAS
RAS
WE
CAS
RAS
WE
CKE
CKE
RST
DDR_VREF
RST
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
ddr1_vref0
0.1 µF
0.1 µF
0.1 µF
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
SPRS906_PCB_DDR3_02
图 7-2. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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32-bit DDR3 EMIF
8-Bit DDR3
Devices
8-Bit DDR3
Devices
ddrx_d31
DQ7
8
ddrx_d24
DQ0
ddrx_dqm3
DM/TQS
TDQS
DQS
NC
ddrx_dqs3
ddrx_dqsn3
DQS
ddrx_d23
DQ7
DQ0
8
ddrx_d16
ddrx_dqm2
DM/TQS
TDQS
NC
ddrx_dqs2
DQS
DQS
ddrx_dqsn2
ddrx_d15
DQ7
8
ddrx_d8
DQ0
ddrx_dqm1
DM/TQS
TDQS
DQS
NC
ddrx_dqs1
ddrx_dqsn1
DQS
ddrx_d7
ddrx_d0
DQ7
DQ0
8
NC
TDQS
DM/TQS
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_ck
DQS
DQS
CK
0.1 µF
CK
CK
CK
Zo
Zo
ddrx_nck
ddrx_odt0
ddrx_csn0
ddrx_odt1
ddrx_csn1
ddrx_ba0
ddrx_ba1
ddrx_ba2
ddrx_a0
CK
CK
CK
CK
DDR_1V5
ODT
CS
ODT
CS
ODT
CS
ODT
CS
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
Zo
Zo
16
ddrx_a15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
A15
A15
CAS
RAS
WE
A15
A15
CAS
RAS
WE
CAS
CAS
RAS
RAS
WE
WE
CKE
CKE
RST
CKE
CKE
RST
RST
RST
DDR_VREF
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
ddrx_vref0
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_03
图 7-3. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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7.2.2.5 Compatible JEDEC DDR3 Devices
表 7-5 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.
表 7-5. Compatible JEDEC DDR3 Devices (Per Interface)
NO.
PARAMETER
JEDEC DDR3 device speed grade(1)
CONDITION
MIN
DDR3-800
DDR3-1066
DDR3-1333
x8
MAX
DDR3-1600
DDR3-1600
DDR3-1600
x16
UNIT
1
DDR clock rate = 400MHz
400MHz < DDR clock rate ≤ 533MHz
533MHz < DDR clock rate ≤ 667MHz
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(2)
Bits
2
4
Devices
(1) Refer to 表 7-3 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see 节 7.2.2.4, 图 7-2, and 图 7-3.
7.2.2.6 PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in 表 7-6. Additional
layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI performance,
or to reduce the size of the PCB footprint. Complete stackup specifications are provided in 表 7-7.
表 7-6. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
1
2
3
4
5
6
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
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表 7-7. PCB Stackup Specifications
NO.
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PARAMETER
MIN
TYP
MAX
UNIT
PCB routing/plane layers
Signal routing layers
6
3
1
1
Full ground reference layers under DDR3 routing region(1)
Full 1.5-V power reference layers under the DDR3 routing region(1)
Number of reference plane cuts allowed within DDR routing region(2)
Number of layers between DDR3 routing layer and reference plane(3)
PCB routing feature size
0
0
4
4
Mils
Mils
Ω
PCB trace width, w
Single-ended impedance, Zo
50
75
Impedance control(5)
Z-5
Z
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
7.2.2.7 Placement
图 7-4 shows the required placement for the processor as well as the DDR3 devices. The dimensions for
this figure are defined in 表 7-8. The placement does not restrict the side of the PCB on which the devices
are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for
proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are omitted from
the placement.
图 7-4. Placement Specifications
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表 7-8. Placement Specifications DDR3
NO.
PARAMETER
MIN
MAX
500
UNIT
Mils
Mils
Mils
Mils
Mils
KOD31
KOD32
KOD33
KOD34
KOD35
KOD36
KOD37
X1
X2
600
X3
600
Y1
1800
600
Y2
DDR3 keepout region (1)
Clearance from non-DDR3 signal to DDR3 keepout region (2) (3)
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
7.2.2.8 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in 图 7-5. The size of this region varies with the placement
and DDR routing. Additional clearances required for the keepout region are shown in 表 7-8. Non-DDR3
signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-DDR3
signals may be routed in the region, provided they are routed on layers separated from the DDR signal
layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In
addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two
signals from the DDR3 controller should be separated from each other by the specification in 表 7-8, (see
KOD37).
图 7-5. DDR3 Keepout Region
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7.2.2.9 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. 表 7-9
contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass
capacitance may be needed for other circuitry.
表 7-9. Bulk Bypass Capacitors
NO.
1
PARAMETER
vdds_ddrx bulk bypass capacitor count(1)
vdds_ddrx bulk bypass total capacitance
MIN
1
MAX
UNIT
Devices
μF
2
22
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
7.2.2.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. 表 7-10 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in 表 7-10.
表 7-10. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
0402
400
UNIT
10 Mils
Mils
0201
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
Processor HS bypass capacitor count per vdds_ddrx rail
Processor HS bypass capacitor total capacitance per vdds_ddrx rail
Number of connection vias for each device power/ground ball(5)
Trace length from device power/ground ball to connection via(2)
Distance, HS bypass capacitor to DDR device being bypassed(6)
DDR3 device HS bypass capacitor count(7)
3
See 节 7.4 and (11)
See 节 7.4 and (11)
Devices
μF
4
5
Vias
6
35
70
Mils
7
150
Mils
8
12
0.85
2
Devices
μF
9
DDR3 device HS bypass capacitor total capacitance(7)
10 Number of connection vias for each HS capacitor(8)(9)
11 Trace length from bypass capacitor connect to connection via(2)(9)
12 Number of connection vias for each DDR3 device power/ground ball(10)
13 Trace length from DDR3 device power/ground ball to connection via(2)(8)
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
Vias
35
35
100
60
Mils
1
Vias
Mils
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
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(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
7.2.2.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
7.2.2.11 Net Classes
表 7-11 lists the clock net classes for the DDR3 interface. 表 7-12 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
表 7-11. Clock Net Class Definitions
CLOCK NET CLASS Processor PIN NAMES
CK
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR3 memory systems.
表 7-12. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
Processor PIN NAMES
NET CLASS
ADDR_CTRL
CK
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
DQ0
DQ1
DQ2(1)
DQ3(1)
DQS0
DQS1
DQS2
DQS3
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
(1) Only used on 32-bit wide DDR3 memory systems.
7.2.2.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
7.2.2.13 VREF_DDR Routing
ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
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7.2.2.14 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed in a fly-by topology. They are routed in a similar manner
and are length matched to minimize skew between them. CK is a bit more complicated because it runs at
a higher transition rate and is differential. The following subsections show the topology and routing for
various DDR3 configurations for CK and ADDR_CTRL. The figures in the following subsections define the
terms for the routing specification detailed in 表 7-13. Balanced-T routing is not recommended.
7.2.2.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
图 7-6 shows the topology of the CK net classes and 图 7-7 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
–
–
+
+
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_06
图 7-6. CK Topology for Four x8 DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
A3
AT
VTT
SPRS906_PCB_DDR3_07
图 7-7. ADDR_CTRL Topology for Four x8 DDR3 Devices
7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
图 7-8 shows the CK routing for four DDR3 devices placed on the same side of the PCB. 图 7-9 shows the
corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_08
图 7-8. CK Routing for Four Single-Side DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_09
图 7-9. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. 图 7-10 and 图 7-11 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_10
图 7-10. CK Routing for Four Mirrored DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_11
图 7-11. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
7.2.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
图 7-12 shows the topology of the CK net classes and 图 7-13 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_12
图 7-12. CK Topology for Two DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
AT
VTT
SPRS906_PCB_DDR3_13
图 7-13. ADDR_CTRL Topology for Two DDR3 Devices
7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
图 7-14 shows the CK routing for two DDR3 devices placed on the same side of the PCB. 图 7-15 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_14
图 7-14. CK Routing for Two Single-Side DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_15
图 7-15. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. 图 7-16 and 图 7-17 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_16
图 7-16. CK Routing for Two Mirrored DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_17
图 7-17. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
7.2.2.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
图 7-18 shows the topology of the CK net classes and 图 7-19 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffer
–
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_18
图 7-18. CK Topology for One DDR3 Device
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
AT
VTT
SPRS906_PCB_DDR3_19
图 7-19. ADDR_CTRL Topology for One DDR3 Device
7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
图 7-20 shows the CK routing for one DDR3 device placed on the same side of the PCB. 图 7-21 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_20
图 7-20. CK Routing for One DDR3 Device
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Rtt
A2
AT
VTT
=
SPRS906_PCB_DDR3_21
图 7-21. ADDR_CTRL Routing for One DDR3 Device
7.2.2.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. 图 7-22 and 图
7-23 show these topologies.
Processor
DQS
DDR
DQSn+
DQSn-
DQS
IO Buffer
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_22
图 7-22. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
Dn
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_23
图 7-23. DQ/DM Topology
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7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
图 7-24 and 图 7-25 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
图 7-24. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
图 7-25. DQ/DM Routing With Any Number of Allowed DDR3 Devices
7.2.2.17 Routing Specification
7.2.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-26 and 图 7-27 show this
distance for four loads and two loads, respectively. It is from this distance that the specifications on the
lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for
other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class.
For CK and ADDR_CTRL routing, these specifications are contained in 表 7-13.
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
A8(A)
A8(A)
Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_26
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-26. CACLM for Four Address Loads on One Side of PCB
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A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_27
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-27. CACLM for Two Address Loads on One Side of PCB
表 7-13. CK and ADDR_CTRL Routing Specification(2)(3)
NO.
PARAMETER
MIN
TYP
MAX
500(1)
29
UNIT
ps
CARS31
CARS32
CARS33
CARS34
CARS35
CARS36
CARS37
CARS38
CARS39
CARS310
CARS311
CARS312
CARS313
CARS314
CARS315
CARS316
CARS317
CARS318
CARS319
CARS320
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
A4 length
ps
125
6
ps
ps
6
ps
125
6
17(1)
14(1)
12
ps
A4 skew
ps
AS length
5
1.3
5
ps
AS skew
ps
AS+/AS- length
AS+/AS- skew
AT length(6)
AT skew(7)
AT skew(8)
ps
1
ps
75
14
ps
ps
1
ps
CK/ADDR_CTRL trace length
1020
3(1)
1(15)
ps
Vias per trace
vias
vias
Via count difference
Center-to-center CK to other DDR3 trace spacing(9)
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
4w
3w
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
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表 7-13. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CK center-to-center spacing(11) (12)
CK spacing to other net(9)
Rcp(13)
MIN
TYP
MAX
UNIT
CARS321
CARS322
CARS323
CARS324
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
Ω
Ω
Rtt(13)(14)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
7.2.2.17.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
注
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-28 shows this distance for four
loads. It is from this distance that the specifications on the lengths of the transmission lines for the data
bus are determined. For DQS and DQ/DM routing, these specifications are contained in 表 7-14.
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DQLMX0
DB0
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DB1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMX2
DQ[23:31]/DM3/DQS3
DQLMY0
DQLMY1
DQLMY3 DQLMY2
DB3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
SPRS906_PCB_DDR3_28
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
图 7-28. DQLM for Any Number of Allowed DDR3 Devices
表 7-14. Data Routing Specification(2)
NO.
PARAMETER
MIN
TYP
MAX
340
340
340
340
5
UNIT
ps
DRS31
DRS32
DRS33
DRS34
DRS35
DRS36
DRS37
DRS38
DRS39
DRS310
DRS311
DRS312
DRS313
DB0 length
DB1 length
ps
DB2 length
ps
DB3 length
DBn skew(3)
ps
ps
DQSn+ to DQSn- skew
DQSn to DBn skew(3)(4)
Vias per trace
Via count difference
1
ps
5(10)
2(1)
0(10)
ps
vias
vias
w(5)
w(5)
Center-to-center DBn to other DDR3 trace spacing(6)
Center-to-center DBn to other DBn trace spacing(7)
DQSn center-to-center spacing(8) (9)
4
3
DQSn center-to-center spacing to other net
4
w(5)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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7.3 High Speed Differential Signal Routing Guidance
The High-Speed Interface Layout Guidelines Application Report provides guidance for successful routing
of the high speed differential signals. This includes PCB stackup and materials guidance as well as routing
skew, length and spacing limits. TI supports only designs that follow the board design guidelines
contained in the application report.
7.4 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well
as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only
designs that follow the board design guidelines contained in the application report.
7.5 Thermal Solution Guidance
The Thermal Design Guide for DSP and Arm Application Processors Application Report and the AM572x
Thermal Considerations Application Report provide guidance for successful implementation of a thermal
solution for system designs that contain an AM57xx application processor. They provide background
information on common terms and methods related to thermal solutions. Test data and thermal
calculations are also provided for a sample design. TI supports only designs that follow the system design
guidelines contained in the application reports. Devices must be operated within their rated temperature
ranges at all times to maintain proper function and rated Power On Hours.
7.6 Single-Ended Interfaces
7.6.1 General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
•
Line spacing:
For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
–
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see 图 7-29).
W
D+
S = 2 W = 200 µm
SPRS906_PCB_SE_GND_01
图 7-29. Ground Guard Illustration
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•
Length matching (unless otherwise specified):
–
For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
–
For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
•
•
Characteristic impedance
–
Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
–
For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
7.6.2 QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
•
•
The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
•
•
The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in 图 7-30.
Propagation delays and matching:
–
–
–
–
A to C = C to D = E to F.
Matching skew: < 60pS
A to B < 450pS
B to C = as small as possible (<60pS)
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Locate both R2 resistors
close together near the QSPI device
A
D
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
qspi1_rtclk
E
F
QSPI device
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS906_PCB_QSPI_01
图 7-30. QSPI Interface High Level Schematic
注
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
7.7 LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
•
External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
•
Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
•
•
External AC coupling capacitors described in should be populated at the ljcb_clkn / ljcb_clkp inputs.
All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-
side termination to ground described in is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode.
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表 7-15. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
100
MAX
UNIT
nF
ljcb_clkn / ljcb_clkp AC coupling capacitor value
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
0402
0603
EIA
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
表 7-16. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
Ohms
7.8 Clock Routing Guidelines
7.8.1 Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground.
图 7-31 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
vssa_oscj
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_PCB_CLK_OSC_03
(1) j in *_osc = 0 or 1
图 7-31. Grounding Scheme for High-Frequency Clock
382
Applications, Implementation, and Layout
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8 Device and Documentation Support
TI offers an extensive line of development tools, including methods to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules as listed below.
8.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, AM570x). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of AM570x devices in the CBD package type, see the Package Option
Addendum of this document, the TI website (ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AM571x (SR 2.0, 1.0)
and AM570x (SR 2.1, 2.0) Sitara™ Processors.
8.1.1 Standard Package Symbolization
注
Some devices may have a cosmetic circular marking visible on the top of the device package
which results from the production test process. In addition, some devices may also show a
color variation in the package substrate which results from the substrate manufacturer.
These differences are cosmetic only with no reliability impact.
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TM
SITARA
aBBBBBBrPPPzYyTSs
XXXXXXX
PIN ONE INDICATOR
G1
YYY
ZZZ
O
SPRS906_PACK_01
图 8-1. Printed Device Reference
8.1.2 Device Naming Convention
表 8-1. Nomenclature Description
FIELD PARAMETER
FIELD DESCRIPTION
VALUE
DESCRIPTION
a
Device evolution
stage(1)
X
P
Prototype
Preproduction (production test flow, no reliability data)
Production
BLANK
BBBBBB
r
Base production part
number
AM5708 HighTier (See 表 3-1, Device Comparison)
AM5706 Low Tier (See 表 3-1, Device Comparison)
Device revision
BLANK
SR 1.0
A
SR 2.0
B
SR 2.1
PPP
z
Package designator
Device Speed
CBD
CBD FCBGA-N538 (17mm × 17mm) Package
J
Indicates the speed grade for each of the cores in the device. For more
information see 表 5-2, Speed Grade Maximum Frequency
D
OTHER
E
Yy
Device Type
All industrial protocols enabled (basic protocols plus EtherCAT slave and
POWERLINK slave)
BLANK
A
Basic industrial protocols enabled
(2)
T
Temperature
Extended (see Section 5.4, Recommended Operating Conditions)
Commercial (see Section 5.4, Recommended Operating Conditions)
High-Security device, Secure Boot Supported
BLANK
S
Ss
Security Level
Ss
Dummy key High-Security device, Secure Boot Supported
General Purpose Device/Customer specific HS device
BLANK
XXXXXXX
YYY
Lot Trace Code
Production Code, For TI use only
Production Code, For TI use only
Pin one designator
ZZZ
O
384
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表 8-1. Nomenclature Description (continued)
FIELD PARAMETER
FIELD DESCRIPTION
VALUE
DESCRIPTION
G1
ECAT—Green package designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still under development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
注
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
8.2 Tools and Software
The following products support development for AM570x platforms:
Development tools
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
The Clock Tree Tool (CTT) for Sitara™ Arm®, Automotive, and Digital Signal Processors is
an interactive clock tree configuration software that provides information about the clocks
and modules in these TI devices. It allows the user to: Visualize the device clock tree.
Interact with clock tree elements and view the effect on PRCM registers. Interact with the
PRCM registers and view the effect on the device clock tree. View a trace of all the device
registers affected by the user interaction with clock tree.
Code Composer Studio (CCS) Integrated Development Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse software framework with advanced embedded debug capabilities from TI resulting in
a compelling feature-rich development environment for embedded developers.
Pin mux tool
The Pin MUX Utility is a software tool which provides a Graphical User Interface for
configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics
for TI MPUs. Results are output as C header/code files that can be imported into software
development kits (SDKs) or used to configure customer's custom software. Version 4 of the
Pin Mux utility adds the capability of automatically selecting a mux configuration that satisfies
the entered requirements.
Power Estimation Tool (PET)
Power Estimation Tool (PET) provides users the ability to gain insight in to the power
consumption of select TI processors. The tool includes the ability for the user to choose
multiple application scenarios and understand the power consumption as well as how
advanced power saving techniques can be applied to further reduce overall power
consumption.
XDS110 JTAG Debug Probe
The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded
processors. The XDS110 replaces the XDS100 family while supporting a wider variety of
standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes
support Core and System Trace in all Arm and DSP processors that feature an Embedded
Trace Buffer (ETB).
The Texas Instruments XDS110 connects to the target board via a TI 20-pin connector (with
multiple adapters for TI 14-pin and, Arm 10-pin and Arm 20-pin) and to the host PC via
USB2.0 High Speed (480Mbps). It also features two additional connections: the Auxiliary 14-
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pin port connector that enables EnergyTrace™, a full duplex UART port and four General-
Purpose I/Os, and the Expansion 30-pin connector to connect the XDS110 EnergyTrace
HDR add-on.
Models
AM570x BSDL Model BSDL Model
AM570x IBIS Model IBIS Model
AM570x Thermal Model Thermal Model
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or
authorized distributor.
8.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The following documents describe the AM570x devices.
Technical Reference Manual
AM571x (SR2.0, SR1.0) AM570x (SR2.1, SR2.0) Sitara™ Processors
Details the integration, the environment, the functional description, and the programming
models for each peripheral and subsystem in the TDA3 family of devices.
Errata
AM571x (SR 2.0, 1.0) and AM570x (SR 2.1, 2.0) Sitara™ Processors
Describes the known exceptions to the functional specifications for the device.
8.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表 8-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
AM5706
AM5708
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
8.6 商标
Sitara, E2E are trademarks of Texas Instruments.
Vivante is a registered trademark of Vivante Corporation.
TrustZone, Neon, CoreSight are trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
Arm, Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
HDQ is a trademark of Benchmarq.
HDMI is a trademark of HDMI Licensing, LLC.
386
Device and Documentation Support
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PowerVR is a trademark of Imagination Technologies Limited.
JTAG is a registered trademark of JTAG Technologies, Inc.
单线 is a registered trademark of Maxim Integrated.
MIPI is a trademark of Mobile Industry Processor Interface (MIPI) Alliance.
MMC is a trademark of MultiMediaCard Association.
SD is a registered trademark of Toshiba Corporation.
All other trademarks are the property of their respective owners.
8.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
The device package has been specially engineered with a new technology called Via Channel. The Via
Channel Array technology allows larger than normal PCB via sizes and reduces PCB signal layers to be
used in a PCB design with this 0.65-mm pitch package, and will substantially reduce PCB costs. Via
Channel also allows PCB routing in only two signal layers (four layers total) due to the increased layer
efficiency of the Via Channel BGA technology.
388
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM5706BCBDD
ACTIVE
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
CBD
538
538
538
538
538
538
538
538
538
84
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
0 to 90
AM5706BCBDD
SITARA(TM)
784
Samples
784 CBD G1
AM5706BCBDDA
AM5706BCBDDEA
AM5706BCBDJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CBD
CBD
CBD
CBD
CBD
CBD
CBD
CBD
84
84
84
84
84
84
84
750
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
0 to 90
AM5706BCBDDA
SITARA(TM)
784
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
784 CBD G1
AM5706BCBDDEA
SITARA(TM)
784
784 CBD G1
AM5706BCBDJ
SITARA(TM)
784
784 CBD G1
AM5706BCBDJA
AM5706BCBDJEA
AM5708BCBDJ
-40 to 105
-40 to 105
0 to 90
AM5706BCBDJA
SITARA(TM)
784
784 CBD G1
AM5706BCBDJEA
SITARA(TM)
784
784 CBD G1
AM5708BCBDJ
SITARA(TM)
784
784 CBD G1
AM5708BCBDJA
AM5708BCBDJAR
-40 to 105
-40 to 105
AM5708BCBDJA
SITARA(TM)
784
784 CBD G1
AM5708BCBDJA
SITARA(TM)
784
784 CBD G1
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM5708BCBDJEA
AM5708BCBDJEAR
AM5708BCBDJR
ACTIVE
FCCSP
FCCSP
FCCSP
CBD
538
538
538
84
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
AM5708BCBDJEA
SITARA(TM)
784
Samples
784 CBD G1
ACTIVE
ACTIVE
CBD
CBD
750
750
Call TI
Call TI
-40 to 105
0 to 90
AM5708BCBDJEA
SITARA(TM)
784
Samples
Samples
784 CBD G1
AM5708BCBDJ
SITARA(TM)
784
784 CBD G1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AM5706BCBDD
AM5706BCBDDA
AM5706BCBDDEA
AM5706BCBDJ
CBD
CBD
CBD
CBD
CBD
CBD
CBD
CBD
CBD
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
538
538
538
538
538
538
538
538
538
84
84
84
84
84
84
84
84
84
6 X 14
6 X 14
6 X 14
6 X 14
6 X 14
6 X 14
6 X 14
6 X 14
6 X 14
150
150
150
150
150
150
150
150
150
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
22
22
22
22
22
22
22
22
22
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
14.5 14.45
AM5706BCBDJA
AM5706BCBDJEA
AM5708BCBDJ
AM5708BCBDJA
AM5708BCBDJEA
Pack Materials-Page 1
PACKAGE OUTLINE
CBD0538A
FCBGA - 1.298 mm max height
SCALE 0.800
BALL GRID ARRAY
17.1
16.9
B
A
BALL A1 CORNER
17.1
16.9
(
14)
4X (R1)
(0.378)
C
SEATING PLANE
BALL TYP
NOTE 4
0.1 C
1.298 MAX
0.36
TYP
0.26
15.6 TYP
SYMM
(0.7) TYP
(0.7) TYP
0.65 TYP
AE
AC
AA
W
U
AD
AB
Y
V
T
R
SYMM
15.6
TYP
P
N
M
K
L
J
H
F
G
E
D
B
0.47
0.37
C
538X
0.15
0.08
A
C A B
1
3
5
7
9
11 13 15 17
19 21
23 25
24
14
16 18
20 22
2
4
6
8
10 12
0.65 TYP
C
NOTE 3
4222967/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
CBD0538A
FCBGA - 1.298 mm max height
BALL GRID ARRAY
(0.65) TYP
1
2
3
4
5
6
7
9
10 11
8
12
13
14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
(0.65) TYP
538X ( 0.35)
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
(
0.35)
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
METAL
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222967/A 04/2016
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
CBD0538A
FCBGA - 1.298 mm max height
BALL GRID ARRAY
538X ( 0.35)
(0.65) TYP
1
2
3
4
5
6
7
9
10 11
8
12
13
14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
(0.65)
TYP
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4222967/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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重要声明和免责声明
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