AM6234ASGGHAALW [TI]
具有基于 Arm® Cortex®-A53 的对象和手势识别功能的物联网 (IoT) 和网关 SoC | ALW | 425 | -40 to 105;
| 型号： | AM6234ASGGHAALW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基于 Arm® Cortex®-A53 的对象和手势识别功能的物联网 (IoT) 和网关 SoC | ALW | 425 | -40 to 105 |
| 文件： | 总266页 (文件大小：5806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
AM62x Sitara™ 处理器
存储器子系统：
1 特性
• 高达816KB 的片上RAM
处理器内核：
– 具有SECDED ECC 的64KB 片上RAM
(OCSRAM)，可以分为更小的存储器组，以
32KB 为增量递增，最多可支持2 个独立的存储
器组
– SMS 子系统中具有SECDED ECC 的256KB 片
上RAM
– SMS 子系统中具有SECDED ECC 的176KB 片
上RAM，用于TI 安全固件
– Cortex-M4F MCU 子系统中具有SECDED ECC
• 多达四核64 位Arm® Cortex®-A53 微处理器子系
统，性能高达1.4GHz
– 四核Cortex-A53 集群（具有512KB L2 共享缓
存，包括SECDED ECC）
– 每个A53 内核包含具有SECDED ECC 功能的
32KB L1 DCache 和具有奇偶校验保护的32KB
L1 ICache
• 频率高达400MHz 的单核Arm® Cortex®-M4F
MCU
的256KB 片上RAM
– 具有SECDED ECC 的256KB SRAM
• 专用器件/电源管理器
– 器件/电源管理器子系统中具有SECDED ECC
的64KB 片上RAM
• DDR 子系统(DDRSS)
多媒体：
– 支持LPDDR4、DDR4 存储器类型
– 具有内联ECC 的16 位数据总线
– 支持高达1600MT/s 的速度
– 最大可寻址范围
• 显示子系统
– 双显示支持
– 每个显示屏1920x1080 @ 60fps
– 1 个2048x1080 + 1 个1280x720
– 高达165MHz 的像素时钟支持，每个显示屏具
有独立PLL
– OLDI（4 通道LVDS - 2x）和DPI（24 位RGB
LVCMOS）
• 8GB（对于DDR4）
• 4GB（对于LPDDR4）
功能安全：
• 以符合功能安全标准为目标[工业]
– 支持定帧检测和MISR 数据检查等安全功能
– 专为功能安全应用开发
– 将提供相关文档来协助进行符合IEC 61508 标
准的功能安全系统设计
– 致力于让系统能力达到SIL-3 级
– 致力于让硬件完整性高达SIL-2 级
– 安全相关认证
• 3D 图形处理单元
– 每个时钟1 个像素或更高
– 填充率大于500 百万像素/秒
– >500 百万像素/秒，>8 个GFLOP
– 支持至少2 个合成层
– 支持高达2048x1080 @60fps 的分辨率
– 支持ARGB32、RGB565 和YUV 格式
– 支持2D 图形
• 计划通过TUV SUD 的IEC 61508 认证
• 以符合功能安全标准为目标[汽车]
– 专为功能安全应用开发
– 将提供相关文档来协助进行符合ISO 26262 标
准的功能安全系统设计
– OpenGL ES 3.1、Vulkan 1.2
• 一个4 通道摄像头串行接口(CSI-Rx) 以及DPHY
– 符合MIPI® CSI-2 v1.3 标准+ MIPI D-PHY 1.2
– 支持高达2.5Gbps 的1、1、3 或4 数据通道模
式
– 系统可满足ASIL D 等级要求
– 以硬件完整性高达ASIL B 级为目标
– 安全相关认证
– ECC 验证/校正和RAM 上的CRC 校验+ ECC
– 虚拟通道支持（多达16 个）
• 计划通过TUV SUD 的ISO 26262 认证
• 符合AEC-Q100 标准
– 能够通过DMA 将流数据直接写入DDR
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
信息安全：
高速接口：
• 支持安全启动
• 支持集成以太网交换机（总共2 个外部端口）
– 硬件强制可信根(ROT)
– 支持通过备用密钥转换RoT
– 支持接管保护、IP 保护和防回滚保护
• 支持可信执行环境(TEE)
– RMII (10/100) 或RGMII (10/100/1000)
– IEEE1588（附件D、E 和F，及802.1AS
PTP）
– 第45 条MDIO PHY 管理规范
– 基于ALE 引擎的数据包分类器，具有512 个分
类器
– 基于Arm TrustZone® 的TEE
– 可实现隔离的广泛防火墙支持
– 安全监视器/计时器/IPC
– 基于优先级的流量控制
– 时间敏感型网络(TSN) 支持
– 四个CPU 硬件中断节奏
– 硬件中的IP/UDP/TCP 校验和卸载
• 两个USB2.0 端口
– 安全存储支持
– 支持回放保护存储器块(RPMB)
• 具有用户可编程HSM 内核的专用安全控制器以及
用于隔离式处理的专用安全DMA 和IPC 子系统
• 支持加密加速
– 可配置为USB 主机、USB 外设或USB 双角色
器件（DRD 模式）的端口
– 集成了USB VBUS 检测
– 会话感知型加密引擎可基于输入数据流自动切换
密钥材料
• 支持加密内核
– 支持通过USB 进行跟踪
– AES –128/192/256 位密钥大小
– SHA2 –224/256/384/512 位密钥大小
– 具有真随机数生成器的DRBG
– 可在RSA/ECC 处理中提供帮助的PKA（公钥
加速器），支持安全启动
通用连接：
• 9 个通用异步接收器/发送器(UART)
• 5 个串行外设接口(SPI) 控制器
• 6 个内部集成电路(I2C) 端口
• 调试安全性
• 3 个多通道音频串行端口(McASP)
– 受安全软件控制的调试访问
– 安全感知调试
– 高达50MHz 的发送和接收时钟
– 3 个McASP 上具有多达16/10/6 个串行数据引
脚并具有独立的TX 和RX 时钟
– 支持时分多路复用(TDM)、内部IC 声音(I2S)
和类似格式
– 支持数字音频接口传输（SPDIF、IEC60958-1
和AES-3 格式）
– 用于发送和接收的FIFO 缓冲器（256 字节）
– 支持音频基准输出时钟
PRU 子系统：
• 运行频率高达333MHz 的双核可编程实时单元子系
统(PRUSS)
• 用于驱动GPIO 以实现周期精确的协议，例如：
– 通用输入/输出(GPIO)
– UART
– I2C
• 3 个增强型PWM 模块(ePWM)
• 3 个增强型正交编码器脉冲模块(eQEP)
• 3 个增强型捕捉模块(eCAP)
• 通用I/O (GPIO)，所有LVCMOS I/O 均可配置为
GPIO
– 外部ADC
• 每个PRU 16KB 程序存储器，具有SECDED ECC
• 每个PRU 8KB 数据存储器，具有SECDED ECC
• 具有SECDED ECC 的32KB 通用存储器
• CRC32/16 硬件加速器
• 3 个支持CAN-FD 的控制器局域网(CAN) 模块
• 具有3 组30 x 32 位寄存器的暂存存储器
• 1 个工业64 位计时器，具有9 个捕捉事件和16 个
比较事件以及慢速和快速补偿
– 符合CAN 协议2.0A、B 和ISO 11898-1 标准
– 完全支持CAN FD（最多64 个数据字节）
– 消息RAM 的奇偶校验/ECC 检查
– 速度高达8Mbps
• 1 个中断控制器(INTC)，至少支持64 个输入事件
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
媒体和数据存储：
优化的电源管理解决方案：
• 3 个多媒体卡/安全数字® (MMC/SD®) 接口
• 推荐的TPS65219 电源管理IC (PMIC)
– 1 个8 位eMMC 接口，速度高达HS200
– 2 个高达UHS-I 的4 位SD/SDIO 接口
– 与eMMC 5.1、SD 3.0 和SDIO 3.0 版兼容
• 1 个高达133MHz 的通用存储器控制器(GPMC)
– 灵活的8 位和16 位异步存储器接口，具有多达
四个芯片（22 位地址）选择（NAND、NOR、
Muxed-NOR 和SRAM）
– 专为满足器件电源要求而设计的配套PMIC
– 灵活的映射和出厂编程配置，支持多种不同的用
例
引导选项：
• UART
• I2C EEPROM
• OSPI/QSPI 闪存
• GPMC NOR/NAND 闪存
• NAND 串行闪存
– 使用BCH 代码，支持4 位、8 位或16 位ECC
– 使用海明码来支持1 位ECC
– 错误定位器模块(ELM)
• SD 卡
• eMMC
• 与GPMC 配合使用，以找到来自伴随多项式
的数据错误（在使用BCH 算法时生成）的地
址
• 根据BCH 算法，支持4 位、8 位和16 位每
512 字节块错误定位
• 从大容量存储设备进行USB（主机）引导
• 从外部主机进行USB（设备）引导（DFU 模式）
• 以太网
• 具有DDR/SDR 支持的OSPI/QSPI
技术/封装：
– 支持串行NAND 和串行NOR 闪存器件
– 支持4GB 存储器地址
– 具有可选实时加密的XIP 模式
• 16nm 技术
• 13mm x 13mm、0.5mm 间距、425 引脚FCCSP
BGA (ALW)
• 17.2mm x 17.2mm、0.8mm 间距、441 引脚
FCBGA (AMC)
电源管理：
• 器件/电源管理器支持多种低功耗模式
– 部分IO 支持CAN/GPIO/UART 唤醒
– DeepSleep
– 仅MCU
– 待机
– Cortex-A53 的动态频率缩放
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
2 应用
• 人机界面(HMI)
• 零售自动化
• 驾驶员监控系统(DMS/OMS)/车内监控(ICM)
• 远程信息处理控制单元(TCU)
• 3D 点云
• 车辆对基础设施(V2V)/车辆对车辆(V2X)
• 3D 可重构汽车仪表组
• 电器用户界面和连接
• 医疗设备
3 说明
低成本 AM62x Sitara™ MPU 系列应用处理器专为 Linux® 应用开发而构建。凭借可扩展的 Arm® Cortex®-A53
性能和嵌入式功能，例如双显示支持和 3D 图形加速，以及一组广泛的外设，AM62x 器件非常适合广泛的工业和
汽车应用，同时还提供智能功能和优化的电源架构。
其中的一些应用包括：
• 工业HMI
• 电动汽车充电站
• 非接触式楼宇门禁
• 驾驶员监控系统
AM62x Sitara™ 处理器的13mm x 13mm 封装(ALW) 型号是工业级处理器，而17.2mm x 17.2mm 封装(AMC) 型
号则满足 AEC-Q100 汽车标准。可以使用集成的 Cortex-M4F 内核和专用外设来满足工业和汽车功能安全要求，
这些内核和外设均可与AM62x 处理器的其余部分隔离。
3 端口千兆以太网交换机具有一个内部端口和两个外部端口，支持时间敏感网络 (TSN)。该器件上的附加 PRU 模
块可为客户自己的用例提供实时 I/O 功能。此外，AM62x 中包含大量外设，可实现系统级连接，例如：USB、
MMC/SD、摄像头接口、OSPI、CAN-FD 和GPMC，用于将主机接口并行连接到外部 ASIC/FPGA。AM62x 器件
还通过内置硬件安全模块 (HSM) 支持安全启动来实现 IP 保护，并为便携式和功耗敏感型应用提供高级电源管理
支持
AM62x 处理器系列中的产品：
• AM625 –具有基于Arm® Cortex®-A53 的边缘AI 和全高清双显示的人机交互SoC
• AM625-Q1 –适用于数字仪表组且具有嵌入式安全功能的汽车显示SoC
• AM623 –具有基于Arm® Cortex®-A53 的对象和手势识别功能的物联网(IoT) 和网关SoC
• AM620-Q1 –具有嵌入式安全功能的汽车计算SoC，适用于驾驶员监控、网络和V2X 系统
封装信息
封装(1)
封装尺寸(2)
器件型号
AM625
ALW（FCCSP BGA，425）
AMC（FCBGA，441）
ALW（FCCSP BGA，425）
AMC（FCBGA，441）
13 mm × 13 mm
17.2mm × 17.2mm
13 mm × 13 mm
17.2 mm x 17.2 mm
AM625-Q1
AM623
AM620-Q1
(1) 如需了解更多信息，请参阅机械、封装和可订购信息。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
3.1 功能方框图
图3-1 展示了器件的功能方框图。
备注
要了解 TI 软件开发套件 (SDK) 目前支持的器件功能，请搜索位于“Downloads”选项卡选项中的
AM62x 软件构建表，在Processor-SDK-AM62x 上提供。
AM62x
Application Cores
MCUSS With FFI
PRUSS
®
Arm®
Arm®
Arm
®
Cortex -A53
Cortex®-A53
Cortex®-M4F
System Memory
®
Arm®
256KB TCM
Arm
®
Cortex -A53
Cortex®-A53
64KB OCRAM
GPMC
with ECC
512KB L2 with ECC
DDR4/LPDDR4
with inline ECC
(16b)
General Connectivity (Main Domain)
3x MMCSD
General Connectivity
(MCUSS)
2-port Gb Ethernet w/ 1588
GPIO
GPIO
3x SPI
Multimedia
2x SPI
UART
3x ePWM
3x eCAP
3x eQEP
2x USB 2.0
2x Display
with DPI
and OLDI / LVDS
8x UART
CAN-FD
3D Graphics
Processing Unit
2x CAN-FD
I2C
5x I2C
OSPI
3x McASP
CSI2 w/ DPHY
Security Management Subsystem (SMS)
Secure Boot
426KB SRAM
SHA
MD5
PKA
AES
DRBG
TRNG
HSM
System Services
DMA
Firewall
DCC
ESM
ECC
System
Monitor
Secure
Boot
Device/Power
Manager
Debug
Timers
IPC
图3-1. 功能方框图
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
7.10 Thermal Resistance Characteristics..................... 102
7.11 Timing and Switching Characteristics................... 103
8 Detailed Description....................................................230
8.1 Overview.................................................................230
8.2 Processor Subsystems........................................... 231
8.3 Accelerators and Coprocessors..............................233
8.4 Other Subsystems.................................................. 234
8.5 Peripherals..............................................................236
9 Applications, Implementation, and Layout............... 240
9.1 Device Connection and Layout Fundamentals....... 240
9.2 Peripheral- and Interface-Specific Design
Information................................................................ 241
10 Device and Documentation Support........................248
10.1 Device Nomenclature............................................248
10.2 Tools and Software............................................... 251
10.3 Documentation Support........................................ 251
10.4 支持资源................................................................251
10.5 Trademarks...........................................................251
10.6 静电放电警告........................................................ 252
10.7 术语表................................................................... 252
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 4
3 说明................................................................................... 4
3.1 功能方框图..................................................................5
4 Revision History.............................................................. 7
5 Device Comparison.........................................................9
5.1 Related Products...................................................... 10
6 Terminal Configuration and Functions........................11
6.1 Pin Diagrams.............................................................11
6.2 Pin Attributes.............................................................13
6.3 Signal Descriptions................................................... 56
6.4 Pin Connectivity Requirements.................................86
7 Specifications................................................................ 90
7.1 Absolute Maximum Ratings...................................... 90
7.2 ESD Ratings for Devices which are not AEC -
Q100 Qualified............................................................ 92
7.3 ESD Ratings for AEC - Q100 Qualified Devices
in the AMC Package....................................................92
7.4 Power-On Hours (POH)............................................92
7.5 Recommended Operating Conditions.......................93
7.6 Operating Performance Points..................................95
7.7 Power Consumption Summary................................. 95
7.8 Electrical Characteristics...........................................96
7.9 VPP Specifications for One-Time Programmable
Information.................................................................. 253
11.1 Packaging Information.......................................... 253
(OTP) eFuses............................................................101
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
4 Revision History
Changes from November 12, 2022 to June 15, 2023 (from Revision A (NOVEMBER 2022) to
Revision B (JUNE 2023))
Page
• 通篇：将文档产品状态从“混合量产状态”更改为“量产数据”，其中ALW 和AMC 封装器件均完全符合量产
数据要求............................................................................................................................................................. 1
• 通篇：为支持17.2mm × 17.2mm AMC 封装的AM625-Q1 和AM620-Q1 器件添加了汽车AEC - Q100 器件特
定信息.................................................................................................................................................................1
•
•
•
•
•
•
（特性）：将CSI 数据速率从2.5Gbps 更改为1.5Gbps，以便与CSI-2 时序部分中定义的速率一致..............1
（特性）：更新了安全功能以阐明支持的内容....................................................................................................1
（特性）：在描述MMC/SD 特性的第一个要点中添加了多媒体卡(MMC).........................................................1
（说明）：添加了AM625-Q1 和AM620-Q1 并更新了每个器件的说明.............................................................4
（封装信息）：更新了表以便与新的内容标准一致，并添加了汽车“-Q1”器件...............................................4
（功能方框图）：添加了软件构建表注释...........................................................................................................5
• (Device Comparison): Added AM625-Q1 to the AM625 columns and added new columns for the AM620-Q1
devices................................................................................................................................................................9
• (Device Comparison): Corrected the name of the JTAG User ID register.......................................................... 9
• (Pin Connectivity Requirements): Updated the second note to include the meaning of "no connect"..............86
• (Pin Connectivity Requirements): Updated the second paragraph of the note following the Connectivity
Requirements table. The update clarifies the operation of configurable device IOs and includes precautions
that must be taken to prevent floating signals from damaging device input buffers......................................... 86
• (ESD Ratings for Devices which are not AEC - Q100 Qualified): Changed the title to clarify the ESD ratings
defined in this table apply to devices which are not AEC - Q100 qualified.......................................................92
• (ESD Ratings for AEC - Q100 Qualified Devices in the AMC Package): Changed the title to clarify the ESD
ratings defined in this table only apply to AEC - Q100 qualified devices in the AMC package........................ 92
• (Recommended Operating Conditions): Created separate table notes for VDD_CANUART and
VDDSHV_CANUART........................................................................................................................................93
• (Operating Performance Points): Changed the Maximum Operating Frequency of the Device/Power Manager
(Cortex-R5F) for speed grades "S" and "T" from 800 to 400............................................................................95
• (DDR Electrical Characteristics): Added references to the respective JEDEC standards..............................100
• (Power-Up Sequencing): Added Power-Up Sequencing –Supply / Signal Assignments table with waveform
references and notes. Added a new waveform for VDD_CANUART to show its sequence requirements
relative to VDD_CORE when powered from a separate always on power source.........................................106
• (Power-Down Sequencing): Added Power-Down Sequencing –Supply / Signal Assignments table with
waveform references and notes. Added a new waveform for VDD_CANUART to show its sequence
requirements relative to VDD_CORE when powered from a separate always on power source...................109
• (MCU_RESETSTATz, and RESETSTATz Switching Characteristics): Changed the minimum value of
parameter RST13 from "0" to "960"................................................................................................................ 112
• (LFXOSC Modes of Operation): Changed the value of PD_C for BYPASS mode from "X" to "0"................. 125
• (DSS Switching Characteristics): Added external pixel clock mode "EXTPCLKIN" to parameters D2, D3, D4,
and D5. Also changed the "Internal PLL" mode min value for parameters D2 and D3 from "0.0475P" to
"0.0475P - 0.3"............................................................................................................................................... 139
• (MCASP): Updated each AHCLKR/X table note to include a TRM reference for clock source options. Also
corrected a typographical error on the signal name associated with the first waveform in each timing diagram
by changing "MCASP[x]_ACLKR/X" to "MCASP[x]_AHCLKR/X"...................................................................173
• (MMC0 DLL Delay Mapping): Changed the OTAPDLYENA and OTAPDLYSEL values for Legacy SDR and
High Speed SDR modes................................................................................................................................ 184
• (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Changed the "UHS-I DR50" mode name to "UHS-I
DDR50" to correct a typographical error.........................................................................................................198
• (OSPI Switching Characteristics –PHY Data Training): Added maximum values to the OSPI0_CLK Cycle
Time parameter (O1) to define a minimum operating frequency of 133MHz. Also updated Note 1 and Note 4,
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to
"reference clock" in Note 4 so it matches the clock name used in the TRM.................................................. 210
• (OSPI0 Switching Characteristics –PHY SDR Mode): Updated Note 1 and Note 4, where "in ns" was added
to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 212
• (OSPI0 Switching Characteristics –PHY DDR Mode): Updated Note 1 and Note 4, where "in ns" was added
to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 214
• (OSPI0 Timing Requirements –Tap SDR Mode): Updated the constant values associated with the minimum
setup and minimum hold formulas in parameters O19 and O20. Note 2 was also updated to change "refclk" to
"reference clock" so it matches the clock name used in the TRM..................................................................216
• (OSPI0 Switching Characteristics –Tap SDR Mode): Updated Note 1 and Note 4, where "in ns" was added
to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it
matches the clock name used in the TRM..................................................................................................... 216
• (OSPI0 Timing Requirements –Tap DDR Mode): Updated the constant values associated with the minimum
setup and minimum hold formulas in parameters O13 and O14. Note 2 was also updated to change "refclk" to
"reference clock" so it matches the clock name used in the TRM..................................................................218
• (OSPI0 Switching Characteristics –Tap DDR Mode): Updated the minimum data output delay and maximum
data output delay formulas in parameter O6. Also updated Note 1 and Note 5, where "in ns" was added to the
OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 5 so it
matches the clock name used in the TRM..................................................................................................... 218
• (PRUSS PRU Switching Characteristics –Direct Output Mode): Changed the maximum skew value for the
GPO to GPO parameter (PRDO1) from 3ns to 2ns........................................................................................220
• (PRUSS UART Switching Characteristics): Added a maximum value and units to the start bit low pulse width
parameter (4)..................................................................................................................................................225
• (Device Nomenclature): Updated the orderable part number example in the first paragraph by removing the
"X" prefix.........................................................................................................................................................248
• (Device Nomenclature): Changed "ALV package type" in the last paragraph to "ALW or AMC package
types"..............................................................................................................................................................248
• (Device Naming Convention): Added AM620x devices..................................................................................250
• (Device Naming Convention): Changed "ppp" to "PPP" to match the upper case letters used in the Standard
Package Symbolization figure........................................................................................................................ 250
Copyright © 2023 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
5 Device Comparison
表5-1 shows a comparison between devices, highlighting the differences.
备注
Availability of features listed in this table are a function of shared IO pins, where IO signals associated
with many of the features are multiplexed to a limited number of pins. The SysConfig tool should be
used to assign signal functions to pins. This will provide a better understanding of limitations
associated with pin multiplexing.
备注
To understand what device features are currently supported by TI Software Development Kits (SDKs),
search for the AM62x Software Build Sheet located in the Downloads tab option provided at
Processor-SDK-AM62x.
表5-1. Device Comparison
AM625, AM625-Q1
AM623
AM620-Q1
REFERENCE
NAME
FEATURES
AM6254 AM6252 AM6251
AM6234
AM6232
AM6231
AM6204 AM6202 AM6201
WKUP_MMR0_JTAG_USER_ID[31:13](1)
Register bit values by device "Features" code (See Device Naming Convention for more information on device features)
C: 0x1D123
G: 0x1D127
0x1D0A3
0x1D0A7
0x1D103
0x1D107
0x1D083
0x1D087
–
–
–
–
–
0x1D067
0x1D047 0x1D307 0x1D287 0x1D247
PROCESSORS AND ACCELERATORS
Speed Grades (See Device Speed Grades)
T, S, K, G
Arm Cortex-A53
Arm A53
Quad
Core
Dual
Core
Single
Core
Quad
Core
Dual
Core
Single
Core
Quad
Core
Dual
Core
Single
Core
Microprocessor Subsystem
Arm Cortex-M4F
Arm M4F
Single Core
Functional Safety Optional(5)
in MCU domain
3D Graphics Engine
(OpenGL ES 3.1, Vulkan 1.2)
3D Graphics
engine
Yes
Yes
Yes
No
No
No
No
No
No
Device Management
Subsystem
WKUP_R5F
Security
Single core
Yes
Crypto Accelerators
PROGRAM AND DATA STORAGE
On-Chip Shared Memory
(RAM) in MAIN Domain
OCSRAM
MCU_MSRAM
64KB (with SECDED ECC)
256KB
On-Chip Shared Memory
(RAM) in M4F Domain
DDR4/LPDDR4 DDR
Subsystem
DDRSS
GPMC
16-bit data with inline ECC; up to 8GB using DDR4 or 4GB using LPDDR4
Up to 1GB with ECC
General-Purpose Memory
Controller
PERIPHERALS
1x DPI
No
No
Display Subsystem
DSS
1x LVDS
Modular Controller Area
Network Interface with Full
CAN-FD Support
MCAN
3
General-Purpose I/O
GPIO
I2C
Up to 170
Inter-Integrated Circuit
Interface
6
3
5
Multichannel Audio Serial Port MCASP
Multichannel Serial Peripheral
Interface
MCSPI
1x eMMC (8-bits)
Multi-Media Card/ Secure
MM/CSD
Digital Interface
2x SD/SDIO (4-bits)
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表5-1. Device Comparison (continued)
AM625, AM625-Q1
AM623
AM6232
Yes(2)
AM620-Q1
AM6204 AM6202 AM6201
REFERENCE
FEATURES
NAME
AM6254 AM6252 AM6251
AM6234
AM6231
Flash Subsystem (FSS)(2)
OSPI0/QSPI0
PRUSS
Programmable Real-Time Unit
Subsystem(3)
2x PRU Cores (Optional)
No
Industrial Communication
Subsystem Support(4)
PRUSS
Gigabit Ethernet Interface
General-Purpose Timers
CPSW3G
TIMER
Yes
12 (4 in MCU Channel)
Enhanced Pulse-Width
Modulator Module
EPWM
ECAP
EQEP
3
3
3
Enhanced Capture Module
Enhanced Quadrature Encoder
Pulse Module
Universal Asynchronous
Receiver and Transmitter
UART
9
CSI2-RX Controller with DPHY CSI-RX
USB2.0 Controller with PHY USB 2.0
1
2
(1) For more details about the WKUP_MMR0_JTAG_USER_ID register and DEVICE_ID bit field, see the device TRM.
(2) One flash interface, configured as OSPI0 or QSPI0.
(3) PRU Subsystem (PRUSS) is available when selecting an orderable part number that includes a Features code of C. Refer to Device
Naming Convention for definition of feature codes.
(4) Industrial Communication Subsystem support is not available for this family of devices.
(5) Functional Safety is available when selecting an orderable part number that includes a Functional Safety code of F. Refer to Device
Naming Convention for definition of feature codes.
5.1 Related Products
Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores with flexible
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara
processors have the reliability needed for use in industrial applications.
AM625 Sitara™ processors Human-machine-interaction SoC with Arm® Cortex®-A53-based edge AI and full-
HD dual display. The low-cost AM625x Sitara™ MPU family of application processors are built for Linux®
application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as: dual-
display support and 3D graphics acceleration, along with an extensive set of peripherals that make the AM62x
device well-suited for a broad range of industrial and automotive applications while offering intelligent features
and optimized power architecture as well.
AM623 Sitara™ processors Internet of Things (IoT) and gateway SoC with Arm® Cortex®-A53-based object
and gesture recognition. The low-cost AM623x Sitara™ MPU family of application processors are built for
Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such
as: dual-display support, along with an extensive set of peripherals that make the AM62x device well-suited for a
broad range of industrial and automotive applications while offering intelligent features and optimized power
architecture as well.
Sitara™ AM62x Developer Portal TI provides a wide range of design resource to ease customers’ evaluation
and development on AM62x platform. You can find the most important design resource in this page, such as
evaluation boards/reference designs, demos, software development kit for Linux/Android/Realtime-Linux/
FreeRTOS, SDK developer guide, configuration tools, Linux academy.
Sitara™ AM62x processors - Design Galley TI provides many reference designs containing ‘building block’
solutions to enable customers to rapidly develop their own unique products and solutions. here are 10+
reference designs with demos for analytic, HMI, and connectivity.
Copyright © 2023 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
6 Terminal Configuration and Functions
6.1 Pin Diagrams
备注
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
图 6-1 shows the ball locations for the 425-ball flip chip ball grid array (FCCSP BGA) package to quickly locate
signal names and ball grid numbering. This figure is used in conjunction with 节 6.2.1 through 表 6-74 (Pin
Attributes table and all Signal Descriptions tables, including the Connectivity Requirements table).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OLDI0
_CLK0P
OLDI0
_CLK1N
USB0
_RCALIB
CSI0
_RXCLKP
RGMII1_RX
_CTL
RGMII1
_TD2
RGMII1
_TXC
RGMII1
_TD0
RGMII2
_TXC
RGMII2
_RD3
RGMII2
_RD0
AE
AD
AC
AB
AA
Y
VSS
RSVD3
OLDI0_A5N
OLDI0_A6N
OLDI0_A7P
VSS
USB1_DP
USB0_DM
VSS
CSI0_RXP2
CSI0_RXP1
VSS
VSS
VSS
OLDI0
_CLK0N
OLDI0
_CLK1P
CSI0
_RXCLKN
RGMII1
_RXC
RGMII1
_TD3
RGMII1_TX
_CTL
RGMII1
_TD1
RGMII2
_TD2
RGMII2_RX
_CTL
RGMII2
_RXC
VSS
MMC0_DAT6 OLDI0_A1N
OLDI0_A5P
OLDI0_A4N
OLDI0_A3N
OLDI0_A6P
OLDI0_A7N
VSS
USB1_DM
USB0_DP
VSS
CSI0_RXN2
CSI0_RXP3
CSI0_RXN1
VSS
MDIO0_MDC
VSS
USB1
_RCALIB
RGMII1
_RD1
RGMII2
_TD3
RGMII2
_RD2
VOUT0
_PCLK
VOUT0
_VSYNC
MMC0_DAT5 MMC0_DAT7
OLDI0_A4P
OLDI0_A0N
DDR0_DM1
USB0_VBUS
CSI0_RXP0
RGMII1
_RD2
RGMII1
_RD0
RGMII2
_RD1
MDIO0
_MDIO
VOUT0
_HSYNC
VOUT0
_DATA12
MMC0_CLK MMC0_DAT4
OLDI0_A1P
VSS
USB1_VBUS
CSI0_RXN3
RSVD6
CSI0_RXN0
CSI0
_RXRCALIB
RGMII1
_RD3
RGMII2
_TD1
RGMII2_TX
_CTL
VOUT0
_DATA15
VOUT0
_DATA11
VOUT0
_DATA13
VOUT0
_DATA7
MMC0_DAT1 MMC0_DAT0 MMC0_DAT2
OLDI0_A3P
OLDI0_A2P
OLDI0_A2N
VSS
VDDA_1P8
_USB
VDDA_3P3
_USB
RGMII2
_TD0
VOUT0
_DATA14
VOUT0
_DATA6
VOUT0
_DATA5
VOUT0
_DATA4
DDR0_DQ14
VSS
MMC0_CMD MMC0_DAT3
OLDI0_A0P
RSVD7
VOUT0_DE
VDDA_1P8
_OLDI0
VDDA_1P8
_OLDI0
VDDA_CORE VDDA_CORE VDDA_1P8
_USB
VOUT0
_DATA9
VOUT0
_DATA3
VOUT0
_DATA2
W
V
DDR0_DQ15 DDR0_DQ12
VSS
VDDSHV2
CAP_VDDS2
VDD_CORE
VDDSHV2
_CSIRX0
_CSIRX0
DDR0_DQS1
VOUT0
_DATA10
VOUT0
_DATA8
VOUT0
_DATA1
GPMC0
_WAIT1
DDR0_DQS1
_n
DDR0_DQ11 DDR0_DQ13
VDD_CORE
VSS
VSS
VDDR_CORE
VSS
VSS
VSS
VDD_CORE
VSS
VSS
VDDSHV3
VSS
VOUT0
_DATA0
GPMC0
_WAIT0
GPMC0
_AD15
GPMC0
_AD14
U
DDR0_DQ8 DDR0_DQ10 DDR0_DQ9
RSVD5
CAP_VDDS4
VDDSHV4
VSS
VDDA_PLL0 VDD_CORE
VDDR_CORE VDDA_PLL1
VSS
VDDA
_TEMP0
GPMC0
_AD12
GPMC0
_AD13
GPMC0
_AD10
T
DDR0_PAR
DDR0_A13
DDR0_A8
DDR0_BA1
DDR0_BA0
DDR0_CK0
DDR0_A5
DDR0_A0
RSVD4
DDR0_A6
DDR0_A7
DDR0_BG0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDSHV3
DDR0
_ALERT_n
GPMC0
_AD11
R
DDR0_A10
DDR0_A11
DDR0_A12
VDDS_DDR
VDD_CORE VDDR_CORE
VDD_CORE
VSS
VSS
VSS
GPMC0_AD7 GPMC0_AD8 GPMC0_AD9
GPMC0_AD4 GPMC0_CLK
P
DDR0_A9
VSS
VDDS_DDR
VDDR_CORE VDD_CORE
VDDSHV3
VDDSHV3
VSS
CAP_VDDS3
GPMC0_AD6 GPMC0_AD5
DDR0_ACT
_n
GPMC0
_BE1n
N
DDR0_BG1 DDR0_WE_n
VDD_CORE
VDD_CORE VDDR_CORE VDD_CORE VDDR_CORE
VSS
GPMC0_AD1 GPMC0_AD2 GPMC0_AD3
DDR0_CAS
_n
DDR0_RAS
_n
VDDS_DDR
_C
GPMC0
GPMC0
M
L
DDR0_CAL0
VSS
VSS
VSS
VSS
VSS
VDD_CORE
VSS
VDDSHV1
GPMC0_DIR
_CSn0
GPMC0_AD0
_BE0n_CLE
DDR0_CK0
_n
DDR0_CS0
_n
GPMC0
_CSn1
GPMC0
_ADVn_ALE
GPMC0_OEn
_REn
DDR0_A3
VDDS_DDR
VDDA_MCU
VDD_CORE
VDDA_PLL2 VDD_CORE
VDDSHV1
VSS
GPMC0_WEn
GPMC0_WPn
OSPI0_D5
DDR0_CS1
DDR0_A2
_n
VMON_3P3
_SOC
GPMC0
_CSn2
GPMC0
_CSn3
K
DDR0_A4
VSS
VSS
VDDS_DDR
VSS
VSS
VSS
VSS
VSS
VSS
VDDR_CORE VDD_CORE CAP_VDDS1
VSS
J
DDR0_A1
DDR0_ODT1 DDR0_CKE1
VPP
VDD_CORE VDDR_CORE
VDD_CORE
VDDSHV6
CAP_VDDS6
OSPI0_D7
OSPI0_D4
OSPI0_DQS
OSPI0_CLK
OSPI0_D1
OSPI0_D3
VDDSHV
_CANUART
CAP_VDDS
_MCU
OSPI0
_CSn2
H
DDR0_ODT0 DDR0_CKE0
DDR0_DM0
DDR0_DQ1
DDR0_DQ3
VDD_CORE
VMON_VSYS
CAP_VDDS0
VSS
CAP_VDDS5
VDDSHV5
VSS
VSS
OSPI0_D6
DDR0
CAP_VDDS
_CANUART
VMON_1P8
_SOC
VDDSHV
_MCU
VDDA
_TEMP1
OSPI0
_CSn1
OSPI0
_LBCLKO
G
F
DDR0_DQ5
_RESET0_n
VDDS_OSC0
VDDSHV0
VSS
VDD
_CANUART
VDDSHV
_MCU
USB1
_DRVVBUS
RESET
_REQz
RESETSTA
z
OSPI0
_CSn0
DDR0_DQ7
DDR0_DQ6
DDR0_DQ2
DDR0_DQ4
DDR0_DQ0
RSVD2
VDDSHV0
OSPI0_D2
OSPI0_D0
DDR0_DQS0
_n
MCU_MCAN1
_TX
MCU_SPI0
_CS0
MCU
EMU0
MCASP0
_AXR0
MCASP0
_AFSR
OSPI0
_CSn3
E
DDR0_DQS0
RSVD8
UART0_TXD MCAN0_RX
PORz_OUT
MMC1_DAT3
MMC1_DAT2
MMC2_DAT2
_RESETz
MCU
_ERRORn
MCU_MCAN1
_RX
MCU_MCAN0
_TX
MCU_SPI0
_D0
MCU_I2C0
_SDA
MCASP0
_AFSX
D
MCU_PORz
TDO
UART0_RXD
EXTINTn
MMC1_SDCD
MMC1_SDWP
I2C1_SCL
MMC2_DAT3 MMC2_CLK
MMC2_CMD MMC2_DAT1
WKUP
_LFOSC0
_XO
WKUP
_LFOSC0
_XI
WKUP
_UART0
_TXD
WKUP
_UART0
_CTSn
MCU_SPI0
_D1
USB0
_DRVVBUS
C
EMU1
SPI0_CS1
SPI0_D0
MCAN0_TX
WKUP
_UART0
_RXD
MCU_OSC0 MCU_MCAN0
MCU_UART0 MCU_UART0
_RXD _RTSn
PMIC_LPM
_EN0
MCU_SPI0
_CS1
WKUP_I2C0
_SCL
MCU_RESETS
UART0
SPI0_D1
MCASP0
_AXR1
MCASP0
_AXR3
MCASP0
_ACLKX
B
RSVD0
VSS
TRSTn
TCK
TMS
TATz
I2C0_SCL
I2C0_SDA
MMC1_DAT1 MMC1_CLK MMC2_SDWP MMC2_DAT0
VSS
_XI
_RX
_RTSn
WKUP
_UART0
_RTSn
MCU_OSC0
_XO
MCU_UART0 MCU_UART0
_TXD _CTSn
MCU_SPI0
_CLK
MCU_I2C0
_SCL
WKUP_I2C0
_SDA
WKUP
TDI
UART0
SPI0_CLK
EXT
_REFCLK1
MCASP0
_AXR2
MCASP0
_ACLKR
A
RSVD1
SPI0_CS0
I2C1_SDA
MMC1_CMD MMC1_DAT0 MMC2_SDCD
VSS
VSS
_CLKOUT0
_CTSn
Not to scale
图6-1. ALW FCCSP Package (Bottom View)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
图 6-2 shows the ball locations for the 441-ball flip chip ball grid array (FCBGA BGA) package to quickly locate
signal names and ball grid numbering. This figure is used in conjunction with 节 6.2.1 through 表 6-74 (Pin
Attributes table and all Signal Descriptions tables, including the Connectivity Requirements table).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
OLDI0
_CLK1P
CSI0
_RXCLKP
CSI0
_RXCLKN
RGMII1
_RXC
RGMII1
_RD2
RGMII1
_TD3
RGMII1
_TD1
RGMII2
_TD0
AA
Y
W
V
U
T
VSS
OLDI0_A0N
OLDI0_A0P
OLDI0_A4N
OLDI0_A5P
OLDI0_A5N
OLDI0_A7N
VSS
OLDI0_A6N
USB0_DM
VSS
VSS
VSS
OLDI0
_CLK1N
RGMII1
_RD3
RGMII1
_RD1
RGMII1
_TD2
RGMII2
_TXC
RGMII2
_RD2
RGMII2
_RD1
RGMII2_TX
_CTL
MMC0_CLK MMC0_DAT4
VSS
VSS
OLDI0_A4P
VSS
OLDI0_A3N
OLDI0_A1P
OLDI0_A2P
VSS
OLDI0_A7P
USB1_DM
OLDI0_A6P
USB1_DP
USB0_DP
VSS
CSI0_RXP0
CSI0_RXN3
CSI0_RXP1
CSI0_RXN2
VSS
CSI0_RXN0
VSS
RGMII1_RX
_CTL
RGMII1
_RD0
RGMII1
_TXC
RGMII2
_TD2
RGMII2
_RD0
RGMII2_RX
_CTL
RGMII2
_RD3
VOUT0
_HSYNC
MMC0_DAT3 MMC0_DAT2 MMC0_DAT5 MMC0_DAT6 OLDI0_A3P
MMC0_DAT1 MMC0_DAT0 MMC0_CMD MMC0_DAT7 OLDI0_A1N
VSS
VSS
CSI0_RXP3
VSS
OLDI0
_CLK0N
OLDI0
_CLK0P
USB1
_RCALIB
RGMII1_TX
_CTL
RGMII2
_TD3
RGMII2
_RXC
VOUT0
_DATA15
VOUT0
_DATA13
USB0_VBUS
VSS
CSI0_RXN1
VSS
MDIO0_MDC
VSS
RGMII1
_TD0
RGMII2
_TD1
MDIO0
_MDIO
VOUT0
_PCLK
VOUT0
_DATA14
VOUT0
_DATA12
VOUT0
_DATA11
VOUT0
_DATA8
VDDS_DDR DDR0_DQ11 DDR0_DQ12 DDR0_DQ13
VSS
OLDI0_A2N
VSS
USB1_VBUS
VSS
CSI0_RXP2
VSS
USB0
_RCALIB
CSI0
_RXRCALIB
VOUT0
_VSYNC
VOUT0
_DATA10
VOUT0
_DATA7
VOUT0
_DATA5
VOUT0
_DATA6
DDR0_DQS1 DDR0_DQ10
VSS
DDR0_DQ14 DDR0_DQ15
VSS
VSS
VSS
RSVD5
RSVD6
VDDSHV2
VDDA_PLL1
VSS
VSS
VOUT0_DE
DDR0_DQS1
DDR0_DQ9
_n
VDDA_1P8
_OLDI0
VDDA_3P3
_USB
VDDA_1P8
_USB
VDDA_1P8
_CSIRX0
VOUT0
_DATA9
VOUT0
_DATA2
VOUT0
_DATA3
VOUT0
_DATA4
VOUT0
_DATA0
R
P
N
M
L
DDR0_DQ8
DDR0_DM1
DDR0_A6
DDR0_A9
RSVD7
VSS
RSVD4
VSS
VSS
VSS
CAP_VDDS2
VDDSHV2
VSS
VSS
VDDA_1P8
_OLDI0
VDDA_CORE VDDA_CORE
_USB
GPMC0
_WAIT1
VOUT0
_DATA1
GPMC0
_AD14
GPMC0
_AD15
GPMC0
_WAIT0
VSS
DDR0_A8
DDR0_A7
VSS
DDR0_A12
DDR0_A13
RSVD8
VDDSHV4
VDDSHV4
VDD_CORE
VSS
VSS
VSS
_CSIRX0
DDR0
_ALERT_n
GPMC0
_AD12
GPMC0
_AD11
GPMC0
_AD13
DDR0_A10
DDR0_A11
DDR0_BA1
VSS
VSS
CAP_VDDS4 VDD_CORE VDDA_PLL0 VDD_CORE
VSS
VDD_CORE
VDDSHV3
VDDSHV3
GPMC0_AD8 GPMC0_AD9
DDR0_ACT
_n
VDDA
_TEMP0
GPMC0
_AD10
DDR0_PAR
DDR0_BG1
DDR0_ODT1
VSS
VDD_CORE
VDDS_DDR
VSS
VSS
VDDR_CORE
VSS
VDD_CORE VDDR_CORE VDD_CORE CAP_VDDS3
VSS
VSS
GPMC0_CLK GPMC0_AD7 GPMC0_AD4
VDDS_DDR
_C
VDDA_DDR
_PLL0
VSS
DDR0_BG0
DDR0_CAL0
DDR0_ODT0
DDR0_A3
DDR0_A2
VSS
DDR0_BA0
VSS
VSS
VDD_CORE
VSS
VDDA_PLL2
VSS
VDD_CORE
VSS
CAP_VDDS1
VDDSHV1
CAP_VDDS6
VDDSHV6
CAP_VDDS5
VSS
VSS
GPMC0_AD5 GPMC0_AD6 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3
DDR0_CK0
_n
DDR0_RAS
_n
VMON_3P3
_SOC
GPMC0
_BE0n_CLE
GPMC0
_BE1n
GPMC0
_ADVn_ALE
GPMC0_OEn
_REn
K
J
VSS
VDDS_DDR
VDDS_DDR
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VDDSHV1
GPMC0_AD0
DDR0_CAS
_n
GPMC0
_CSn0
DDR0_CK0 DDR0_WE_n
DDR0_A4
DDR0_A5
DDR0_A1
DDR0_A0
DDR0_DQ3
VSS
VDDS_OSC0 VDDS_DDR
VSS
VDD_CORE
VDD_CORE
VSS
VSS
GPMC0_WEn
GPMC0_DIR GPMC0_WPn
OSPI0_D7
OSPI0_D5
OSPI0_D4
OSPI0_D2
DDR0_CS0
_n
VDDSHV
_CANUART
VDD
_CANUART
VMON_1P8
_SOC
GPMC0
_CSn1
GPMC0
_CSn2
GPMC0
H
G
F
VSS
DDR0_CKE1
VSS
VDDA_MCU VDDR_CORE VDD_CORE
VSS
VDD_CORE
VDDSHV5
VDDSHV5
VDDSHV6
OSPI0_DQS
_CSn3
DDR0_CS1
_n
DDR0
_RESET0_n
VDDSHV
_CANUART
CAP_VDDS
_CANUART
VDDSHV
_MCU
CAP_VDDS
_MCU
OSPI0
_LBCLKO
DDR0_CKE0
DDR0_DQ5
DDR0_DM0
DDR0_DQ2
RSVD1
VSS
VSS
VSS
CAP_VDDS0
VDDSHV0
I2C0_SCL
SPI0_CLK
SPI0_D0
VDDSHV0
VSS
OSPI0_D1
OSPI0_CLK
OSPI0_D6
OSPI0_D3
VDDSHV
_MCU
VDDA
_TEMP1
OSPI0
_CSn1
OSPI0
_CSn0
DDR0_DQ6
DDR0_DQ7
VMON_VSYS
RSVD2
VPP
RSVD3
VSS
UART0_TXD
VSS
VSS
OSPI0_D0
DDR0_DQS0
_n
MCU_SPI0
_CS0
MCU_SPI0
_D0
WKUP_I2C0
_SCL
RESETSTA
z
RESET
_REQz
USB1
_DRVVBUS
OSPI0
_CSn2
OSPI0
_CSn3
E
D
C
B
A
VSS
DDR0_DQ1
TDO
TDI
PORz_OUT
SPI0_CS1
MMC2_DAT2 MMC2_DAT3 MMC2_CLK
MCU_MCAN1 MCU_MCAN1 MCU_UART0
MCU_SPI0
_D1
MCASP0
_AFSR
MCASP0
_ACLKR
USB0
_DRVVBUS
MCASP0
_AXR0
DDR0_DQS0 DDR0_DQ4
VSS
EMU0
I2C0_SDA
VSS
MMC2_SDCD MMC2_DAT1
_TX
_RX
_RTSn
WKUP
_UART0
_TXD
MCU_MCAN0 MCU_MCAN0
_RX
PMIC_LPM
_EN0
MCU_SPI0
_CS1
MCU
_RESETz
UART0
_RTSn
EXT
_REFCLK1
MCASP0
_AFSX
MCASP0
_ACLKX
VDDS_DDR
DDR0_DQ0
MCU_PORz
TCK
SPI0_CS0
MMC1_SDCD
MMC1_SDWP
MCAN0_RX
MMC1_CMD MMC1_DAT3 MMC2_SDWP MMC2_CMD
_TX
WKUP
_UART0
_RTSn
WKUP
_UART0
_RXD
MCU
_ERRORn
MCU_UART0
_TXD
MCU_SPI0
_CLK
MCU_UART0
_CTSn
MCU_I2C0
_SCL
WKUP
_CLKOUT0
UART0
_CTSn
MCASP0
_AXR2
MCASP0
RSVD0
EMU1
TMS
MCAN0_TX
EXTINTn
MMC1_DAT1 MMC1_DAT2 MMC2_DAT0
_AXR3
WKUP
_LFOSC0
_XI
WKUP
_LFOSC0
_XO
WKUP
_UART0
_CTSn
MCU_OSC0
_XI
MCU_OSC0
_XO
MCU_UART0 WKUP_I2C0
_RXD _SDA
MCU_I2C0
_SDA
MCU_RESETS
TATz
MCASP0
_AXR1
VSS
VSS
TRSTn
UART0_RXD
SPI0_D1
I2C1_SDA
I2C1_SCL
MMC1_DAT0 MMC1_CLK
VSS
Not to scale
图6-2. AMC FCBGA Package (Bottom View)
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
6.2 Pin Attributes
The following list describes the contents of each column in 表6-1, Pin Attributes (ALW, AMC Packages):
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically
taken from the primary MUXMODE 0 signal function).
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.
备注
Many device pins support multiple signal functions. Some signal functions are selected via a
single layer of multiplexers associated with pins. Other signal functions are selected via two or
more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
表6-1, Pin Attributes (ALW, AMC Packages) only defines signal multiplexing at the pins. For more
information, related to signal multiplexing at the pins, see the Pad Configuration Registers section
in the Device Configuration chapter of the device TRM. For information associated with peripheral
signal multiplexing, see the respective peripheral chapter in the device TRM.
4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal
function is not necessarily the default pin multiplexed signal function.
备注
The value found in the MUX MODE AFTER RESET column defines the default pin
multiplexed signal function selected when MCU_PORz is deasserted.
b. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all
MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin
multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE should be
used.
c. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the
rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not
programmable via MUXMODE.
d. An empty box means Not Applicable.
备注
The following configurations of MUXMODE must be avoided for proper device operation.
• Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not
supported as it can yield unexpected results.
• Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be
undefined.
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English Data Sheet: SPRSP58
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
5. TYPE: Signal type and direction:
• I = Input
• O = Output
• OD = Output, with open-drain output function
• IO = Input, Output, or simultaneously Input and Output
• IOD = Input, Output, or simultaneously Input and Output, with open-drain output function
• IOZ = Input, Output, or simultaneously Input and Output, with three-state output function
• OZ = Output with three-state output function
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor.
6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic
"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.
• 0: Logic 0 driven to the subsystem input.
• 1: Logic 1 driven to the subsystem input.
• pad: Logic state of the pad is driven to the subsystem input.
• An empty box means Not Applicable.
7. BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RX
defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of
internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– Low: The output buffer is enabled and drives VOL
.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
8. BALL STATE AFTER RESET RX/TX/PULL: State of the terminal after MCU_PORz is deasserted, where
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state
of internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– SS: The subsystem selected with MUXMODE determines the output buffer state.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal
function after MCU_PORz is deasserted.
An empty box means Not Applicable.
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
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10. I/O OPERATING VOLTAGE: This column describes I/O operating voltage options of the respective power
supply, when applicable.
An empty box means Not Applicable.
For more information, see valid operating voltage range(s) defined for each power supply in 节7.5,
Recommended Operating Conditions.
11. POWER: The power supply of the associated I/O, when applicable.
An empty box means Not Applicable.
12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis
• An empty box means Not Applicable.
For more information, see the hysteresis values in 节7.8, Electrical Characteristics.
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be
used to determine which Electrical Characteristics table is applicable.
An empty box means Not Applicable.
For electrical characteristics, refer to the appropriate buffer type table in 节7.8, Electrical Characteristics.
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
• PU: Internal pull-up
• PD: Internal pull-down
• PU/PD: Internal pull-up and pull-down
• An empty box means No internal pull.
15. PADCONFIG Register:Name of the IO pad configuration register associated with Ball.
16. PADCONFIG Address:Physical address of the IO pad configuration register associated with Ball.
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
H15
K18
G12
L15
CAP_VDDS0
CAP_VDDS1
CAP_VDDS2
CAP_VDDS3
CAP_VDDS4
CAP_VDDS5
CAP_VDDS6
CAP_VDDS_CANUART
CAP_VDDS_MCU
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXRCALIB
CSI0_RXN0
CAP_VDDS0
CAP
CAP_VDDS1
CAP_VDDS2
CAP_VDDS3
CAP_VDDS4
CAP_VDDS5
CAP_VDDS6
CAP_VDDS_CANUART
CAP_VDDS_MCU
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXRCALIB
CSI0_RXN0
CAP
W17
P19
R13
M15
N8
CAP
CAP
U7
CAP
H17
G15
J15
CAP
J19
CAP
G9
G8
CAP
H11
G11
AA14
AA13
T11
CAP
AD15
AE15
AA14
AB14
AD14
AD13
AB12
AC15
AE14
AE13
AC13
I
I
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
VDDA_1P8_CSIRX
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
D-PHY
A
I
Y13
V13
U12
W12
Y12
V12
U11
W11
CSI0_RXN1
CSI0_RXN1
I
CSI0_RXN2
CSI0_RXN2
I
CSI0_RXN3
CSI0_RXN3
I
CSI0_RXP0
CSI0_RXP0
I
CSI0_RXP1
CSI0_RXP1
I
CSI0_RXP2
CSI0_RXP2
I
CSI0_RXP3
CSI0_RXP3
I
VDDS_DDR,
VDDS_DDR_C
N6
R3
M4
T1
M5
N3
J1
M1
N1
J3
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
O
IO
O
O
O
O
O
O
O
O
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
M2
K5
J2
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
F5
G5
G4
H4
VDDS_DDR,
VDDS_DDR_C
J2
DDR0_A1
DDR0_A1
VDDS_DDR,
VDDS_DDR_C
K3
L5
DDR0_A2
DDR0_A2
VDDS_DDR,
VDDS_DDR_C
DDR0_A3
DDR0_A3
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VDDS_DDR,
VDDS_DDR_C
K4
K1
R2
P2
P1
P4
R5
P5
R6
R1
M1
N1
T4
N2
M2
L1
J5
H5
P4
N2
P2
N4
N3
M3
P5
N5
L5
DDR0_A4
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
DDR0_A5
VDDS_DDR,
VDDS_DDR_C
DDR0_A6
VDDS_DDR,
VDDS_DDR_C
DDR0_A7
VDDS_DDR,
VDDS_DDR_C
DDR0_A8
VDDS_DDR,
VDDS_DDR_C
DDR0_A9
VDDS_DDR,
VDDS_DDR_C
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_A10
DDR0_A11
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
L3
VDDS_DDR,
VDDS_DDR_C
L4
VDDS_DDR,
VDDS_DDR_C
L2
VDDS_DDR,
VDDS_DDR_C
K4
J1
VDDS_DDR,
VDDS_DDR_C
O
O
O
O
O
O
IO
VDDS_DDR,
VDDS_DDR_C
L2
K1
G3
H2
H3
G1
E3
VDDS_DDR,
VDDS_DDR_C
H2
J4
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
L6
VDDS_DDR,
VDDS_DDR_C
K2
H5
VDDS_DDR,
VDDS_DDR_C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
18
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VDDS_DDR,
VDDS_DDR_C
W5
F4
G5
F3
H6
E3
G2
F2
F1
U1
U3
U2
V5
W2
V6
Y1
W1
E1
E2
V1
V2
H1
R4
C2
E4
D3
E5
D2
F3
F1
F2
R3
R2
T2
U2
U3
U4
T4
T5
D1
E1
T1
R1
J4
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_DM1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
VDDS_DDR,
VDDS_DDR_C
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VDDS_DDR,
VDDS_DDR_C
J3
K2
G2
DDR0_ODT1
DDR0_ODT1
O
O
1.1 V/1.2 V
1.1 V/1.2 V
DDR
DDR
VDDS_DDR,
VDDS_DDR_C
G1
DDR0_RESET0_n
EMU0
DDR0_RESET0_n
EMU0
PADCONFIG:
MCU_PADCONFIG30
0x04084078
E12
C11
D16
D9
0
0
IO
IO
0
0
On / Off / Up
On / Off / Up
Off / Off / NA
On / Off / Up
On / Off / Up
Off / Off / NA
0
0
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV0
Yes
Yes
Yes
LVCMOS
LVCMOS
I2C OD FS
PU/PD
PU/PD
EMU1
PADCONFIG:
MCU_PADCONFIG31
0x0408407C
B10
B16
EMU1
EXTINTn
EXTINTn
0
7
I
1
pad
0
PADCONFIG:
PADCONFIG125
0x000F41F4
GPIO1_31
IOD
EXT_REFCLK1
SYNC1_OUT
0
1
2
3
4
5
6
7
8
0
2
4
5
6
7
0
2
3
4
5
6
7
I
O
IO
O
IO
O
I
SPI2_CS3
1
0
EXT_REFCLK1
SYSCLKOUT0
TIMER_IO4
PADCONFIG:
PADCONFIG124
0x000F41F0
A18
C14
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
CLKOUT0
CP_GEMAC_CPTS0_RFT_CLK
GPIO1_30
0
pad
0
IO
IO
O
IO
IO
I
ECAP0_IN_APWM_OUT
GPMC0_ADVn_ALE
MCASP1_AXR2
PR0_PRU0_GPO9
PR0_PRU0_GPI9
TRC_DATA7
0
0
0
GPMC0_ADVn_ALE
PADCONFIG:
PADCONFIG33
0x000F4084
L23
K20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
O
IO
O
IO
I
GPIO0_32
pad
0
GPMC0_CLK
MCASP1_AXR3
GPMC0_FCLK_MUX
PR0_PRU0_GPO8
PR0_PRU0_GPI8
TRC_DATA6
GPMC0_CLK
PADCONFIG:
PADCONFIG31
0x000F407C
P25
M19
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
GPIO0_31
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
20
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_DIR
0
1
3
4
5
6
7
8
0
2
4
5
6
7
0
2
4
5
6
7
0
1
2
3
4
5
6
7
O
IO
IO
IO
I
PR0_ECAP0_IN_APWM_OUT
MCASP2_AXR13
PR0_PRU0_GPO16
PR0_PRU0_GPI16
TRC_DATA14
0
0
0
0
GPMC0_DIR
PADCONFIG:
PADCONFIG41
0x000F40A4
M22
J19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
GPIO0_40
IO
IO
O
pad
0
EQEP2_S
GPMC0_OEn_REn
MCASP1_AXR1
PR0_PRU0_GPO10
PR0_PRU0_GPI10
TRC_DATA8
IO
IO
I
0
0
0
GPMC0_OEn_REn
PADCONFIG:
PADCONFIG34
0x000F4088
L24
K21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
GPIO0_33
IO
O
pad
GPMC0_WEn
MCASP1_AXR0
PR0_PRU0_GPO11
PR0_PRU0_GPI11
TRC_DATA9
IO
IO
I
0
0
0
GPMC0_WEn
PADCONFIG:
PADCONFIG35
0x000F408C
L25
J17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
GPIO0_34
IO
O
pad
0
GPMC0_WPn
AUDIO_EXT_REFCLK1
GPMC0_A22
IO
OZ
O
GPMC0_WPn
UART6_TXD
PADCONFIG:
PADCONFIG40
0x000F40A0
K25
J20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
PR0_PRU0_GPO15
PR0_PRU0_GPI15
TRC_DATA13
IO
I
0
0
O
GPIO0_39
IO
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_AD0
0
IO
O
I
0
PR0_PRU1_GPO8
PR0_PRU1_GPI8
MCASP2_AXR4
PR0_PRU0_GPO0
PR0_PRU0_GPI0
TRC_CLK
1
2
0
0
0
0
GPMC0_AD0
3
IO
IO
I
PADCONFIG:
PADCONFIG15
0x000F403C
M25
N23
N24
N25
K19
L19
L20
L21
4
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
5
6
O
IO
I
GPIO0_15
7
pad
0
BOOTMODE00
GPMC0_AD1
Bootstrap
0
IO
O
I
PR0_PRU1_GPO9
PR0_PRU1_GPI9
MCASP2_AXR5
PR0_PRU0_GPO1
PR0_PRU0_GPI1
TRC_CTL
1
2
0
0
0
0
GPMC0_AD1
3
IO
IO
I
PADCONFIG:
PADCONFIG16
0x000F4040
4
VDDSHV3
VDDSHV3
VDDSHV3
LVCMOS
LVCMOS
LVCMOS
5
6
O
IO
I
GPIO0_16
7
pad
0
BOOTMODE01
GPMC0_AD2
Bootstrap
0
IO
O
I
PR0_PRU1_GPO10
PR0_PRU1_GPI10
MCASP2_AXR6
PR0_PRU0_GPO2
PR0_PRU0_GPI2
TRC_DATA0
1
2
0
0
0
0
GPMC0_AD2
3
IO
IO
I
PADCONFIG:
PADCONFIG17
0x000F4044
4
5
6
O
IO
I
GPIO0_17
7
pad
0
BOOTMODE02
GPMC0_AD3
Bootstrap
0
IO
O
I
PR0_PRU1_GPO11
PR0_PRU1_GPI11
MCASP2_AXR7
PR0_PRU0_GPO3
PR0_PRU0_GPI3
TRC_DATA1
1
2
0
0
0
0
GPMC0_AD3
3
IO
IO
I
PADCONFIG:
PADCONFIG18
0x000F4048
4
5
6
7
O
IO
I
GPIO0_18
pad
BOOTMODE03
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
22
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_AD4
0
IO
O
I
0
PR0_PRU1_GPO12
PR0_PRU1_GPI12
MCASP2_AXR8
PR0_PRU0_GPO4
PR0_PRU0_GPI4
TRC_DATA2
1
2
0
0
0
0
GPMC0_AD4
3
IO
IO
I
PADCONFIG:
PADCONFIG19
0x000F404C
P24
P22
P21
R23
M21
L17
L18
M20
4
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
On / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
5
6
O
IO
I
GPIO0_19
7
pad
0
BOOTMODE04
GPMC0_AD5
Bootstrap
0
IO
O
I
PR0_PRU1_GPO13
PR0_PRU1_GPI13
MCASP2_AXR9
PR0_PRU0_GPO5
PR0_PRU0_GPI5
TRC_DATA3
1
2
0
0
0
0
GPMC0_AD5
3
IO
IO
I
PADCONFIG:
PADCONFIG20
0x000F4050
4
VDDSHV3
VDDSHV3
VDDSHV3
5
6
O
IO
I
GPIO0_20
7
pad
0
BOOTMODE05
GPMC0_AD6
Bootstrap
0
IO
O
I
PR0_PRU1_GPO14
PR0_PRU1_GPI14
MCASP2_AXR10
PR0_PRU0_GPO6
PR0_PRU0_GPI6
TRC_DATA4
1
2
0
0
0
0
GPMC0_AD6
3
IO
IO
I
PADCONFIG:
PADCONFIG21
0x000F4054
4
5
6
O
IO
I
GPIO0_21
7
pad
0
BOOTMODE06
GPMC0_AD7
Bootstrap
0
IO
O
I
PR0_PRU1_GPO15
PR0_PRU1_GPI15
MCASP2_AXR11
PR0_PRU0_GPO7
PR0_PRU0_GPI7
TRC_DATA5
1
2
0
0
0
0
GPMC0_AD7
3
IO
IO
I
PADCONFIG:
PADCONFIG22
0x000F4058
4
5
6
7
O
IO
I
GPIO0_22
pad
BOOTMODE07
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_AD8
0
IO
O
I
0
VOUT0_DATA16
UART2_RXD
1
2
1
0
GPMC0_AD8
MCASP2_AXR0
PR0_PRU1_GPO0
PR0_PRU1_GPI0
GPIO0_23
3
IO
O
I
PADCONFIG:
PADCONFIG23
0x000F405C
R24
N20
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
4
5
0
7
IO
I
pad
BOOTMODE08
GPMC0_AD9
Bootstrap
0
IO
O
O
IO
O
I
0
0
VOUT0_DATA17
UART2_TXD
1
2
GPMC0_AD9
MCASP2_AXR1
PR0_PRU1_GPO1
PR0_PRU1_GPI1
GPIO0_24
3
PADCONFIG:
PADCONFIG24
0x000F4060
R25
N21
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
4
5
0
7
IO
I
pad
BOOTMODE09
GPMC0_AD10
VOUT0_DATA18
UART3_RXD
Bootstrap
0
IO
O
I
0
1
2
1
0
GPMC0_AD10
MCASP2_AXR2
PR0_PRU1_GPO2
PR0_PRU1_GPI2
GPIO0_25
3
IO
O
I
PADCONFIG:
PADCONFIG25
0x000F4064
T25
M17
4
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
0
7
IO
O
I
pad
OBSCLK0
8
BOOTMODE10
GPMC0_AD11
VOUT0_DATA19
UART3_TXD
Bootstrap
0
IO
O
O
IO
O
I
0
1
2
GPMC0_AD11
MCASP2_AXR3
PR0_PRU1_GPO3
PR0_PRU1_GPI3
TRC_DATA23
GPIO0_26
3
0
0
PADCONFIG:
PADCONFIG26
0x000F4068
R21
N18
4
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
6
7
O
IO
I
pad
BOOTMODE11
Bootstrap
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
24
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AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_AD12
0
IO
O
I
0
VOUT0_DATA20
UART4_RXD
1
2
1
0
0
0
GPMC0_AD12
MCASP2_AFSX
PR0_PRU0_GPO0
PR0_PRU0_GPI0
TRC_DATA22
3
IO
IO
I
PADCONFIG:
PADCONFIG27
0x000F406C
T22
N17
4
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
6
O
IO
I
GPIO0_27
7
pad
0
BOOTMODE12
GPMC0_AD13
VOUT0_DATA21
UART4_TXD
Bootstrap
0
IO
O
O
IO
IO
I
1
2
GPMC0_AD13
MCASP2_ACLKX
PR0_PRU0_GPO1
PR0_PRU0_GPI1
TRC_DATA21
3
0
0
0
PADCONFIG:
PADCONFIG28
0x000F4070
T24
N19
4
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
6
O
IO
I
GPIO0_28
7
pad
0
BOOTMODE13
GPMC0_AD14
VOUT0_DATA22
UART5_RXD
Bootstrap
0
IO
O
I
1
2
1
0
0
0
MCASP2_AFSR
PR0_PRU0_GPO2
PR0_PRU0_GPI2
TRC_DATA20
3
IO
IO
I
GPMC0_AD14
4
PADCONFIG:
PADCONFIG29
0x000F4074
U25
P19
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
6
O
IO
I
GPIO0_29
7
8
pad
1
UART2_CTSn
BOOTMODE14
Bootstrap
I
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_AD15
0
IO
O
O
IO
IO
I
0
VOUT0_DATA23
UART5_TXD
1
2
MCASP2_ACLKR
PR0_PRU0_GPO3
PR0_PRU0_GPI3
TRC_DATA19
3
0
0
0
GPMC0_AD15
4
PADCONFIG:
PADCONFIG30
0x000F4078
U24
P20
On / Off / Off
On / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
5
6
O
IO
O
I
GPIO0_30
7
pad
UART2_RTSn
8
BOOTMODE15
GPMC0_BE0n_CLE
MCASP1_ACLKX
PR0_PRU0_GPO12
PR0_PRU0_GPI12
TRC_DATA10
Bootstrap
0
2
4
5
6
7
0
3
4
5
6
7
0
3
4
5
6
7
0
1
2
3
4
5
6
7
O
IO
IO
I
0
0
0
GPMC0_BE0n_CLE
PADCONFIG:
PADCONFIG36
0x000F4090
M24
N20
M21
K17
K18
J18
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
O
IO
O
IO
IO
I
GPIO0_35
pad
GPMC0_BE1n
MCASP2_AXR12
PR0_PRU0_GPO13
PR0_PRU0_GPI13
TRC_DATA11
0
0
0
GPMC0_BE1n
PADCONFIG:
PADCONFIG37
0x000F4094
O
IO
O
IO
IO
I
GPIO0_36
pad
GPMC0_CSn0
MCASP2_AXR14
PR0_PRU0_GPO17
PR0_PRU0_GPI17
TRC_DATA15
0
0
0
GPMC0_CSn0
PADCONFIG:
PADCONFIG42
0x000F40A8
O
IO
O
O
I
GPIO0_41
pad
GPMC0_CSn1
PR0_PRU1_GPO16
PR0_PRU1_GPI16
MCASP2_AXR15
PR0_PRU0_GPO18
PR0_PRU0_GPI18
TRC_DATA16
0
0
0
0
GPMC0_CSn1
IO
IO
I
PADCONFIG:
PADCONFIG43
0x000F40AC
L21
H17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
GPIO0_42
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
26
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
GPMC0_CSn2
0
1
2
3
4
5
6
7
8
0
1
2
3
4
6
7
8
0
2
4
5
6
7
0
1
2
3
7
8
O
IOD
IO
I
I2C2_SCL
1
0
1
0
0
MCASP1_AXR4
UART4_RXD
GPMC0_CSn2
PADCONFIG:
PADCONFIG44
0x000F40B0
K22
H18
PR0_PRU0_GPO19
PR0_PRU0_GPI19
TRC_DATA17
GPIO0_43
IO
I
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
IO
O
pad
0
MCASP1_AFSR
GPMC0_CSn3
I2C2_SDA
IOD
OZ
O
1
0
GPMC0_A20
GPMC0_CSn3
UART4_TXD
PADCONFIG:
PADCONFIG45
0x000F40B4
K24
H19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
MCASP1_AXR5
TRC_DATA18
GPIO0_44
IO
O
IO
IO
I
pad
0
MCASP1_ACLKR
GPMC0_WAIT0
MCASP1_AFSX
PR0_PRU0_GPO14
PR0_PRU0_GPI14
TRC_DATA12
GPIO0_37
1
IO
IO
I
0
GPMC0_WAIT0
0
PADCONFIG:
PADCONFIG38
0x000F4098
U23
P21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
0
O
IO
I
pad
1
GPMC0_WAIT1
VOUT0_EXTPCLKIN
GPMC0_A21
I
0
GPMC0_WAIT1
OZ
I
PADCONFIG:
PADCONFIG39
0x000F409C
V25
P17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
UART6_RXD
1
pad
0
GPIO0_38
IO
IO
EQEP2_I
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
I2C0_SCL
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
0
1
2
3
4
7
8
9
0
1
2
3
4
7
8
9
IOD
IO
O
1
0
PR0_IEP0_EDIO_DATA_IN_OUT30
SYNC0_OUT
OBSCLK0
O
I2C0_SCL
UART1_DCDn
EQEP2_A
I
1
0
PADCONFIG:
PADCONFIG120
0x000F41E0
B16
E12
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
I
EHRPWM_SOCA
GPIO1_26
O
IO
IO
IO
IOD
IO
IO
IO
I
pad
0
ECAP1_IN_APWM_OUT
SPI2_CS0
1
I2C0_SDA
1
PR0_IEP0_EDIO_DATA_IN_OUT31
SPI2_CS2
0
1
I2C0_SDA
TIMER_IO5
0
PADCONFIG:
PADCONFIG121
0x000F41E4
A16
D14
UART1_DSRn
EQEP2_B
1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
I
0
EHRPWM_SOCB
GPIO1_27
O
IO
IO
IOD
I
pad
0
ECAP2_IN_APWM_OUT
I2C1_SCL
1
UART1_RXD
1
TIMER_IO0
IO
IO
I
0
I2C1_SCL
SPI2_CS1
1
PADCONFIG:
PADCONFIG122
0x000F41E8
B17
A17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EHRPWM0_SYNCI
GPIO1_28
0
IO
IO
I
pad
0
EHRPWM2_A
MMC2_SDCD
I2C1_SDA
1
IOD
O
1
UART1_TXD
TIMER_IO1
IO
IO
O
0
0
I2C1_SDA
SPI2_CLK
PADCONFIG:
PADCONFIG123
0x000F41EC
A17
A16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EHRPWM0_SYNCO
GPIO1_29
IO
IO
I
pad
0
EHRPWM2_B
MMC2_SDWP
1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
28
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MCAN0_RX
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
6
7
8
0
1
2
7
8
I
1
0
UART5_TXD
TIMER_IO3
O
IO
O
I
SYNC3_OUT
UART1_RIn
MCAN0_RX
1
0
PADCONFIG:
PADCONFIG119
0x000F41DC
E15
A15
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
EQEP2_S
IO
O
IO
IO
I
PR0_UART0_TXD
GPIO1_25
pad
0
MCASP2_AXR1
EHRPWM_TZn_IN4
MCAN0_TX
0
O
I
UART5_RXD
TIMER_IO2
1
0
IO
O
O
IO
I
SYNC2_OUT
UART1_DTRn
EQEP2_I
MCAN0_TX
PADCONFIG:
PADCONFIG118
0x000F41D8
C15
B13
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
1
PR0_UART0_RXD
GPIO1_24
IO
IO
I
pad
0
MCASP2_AXR0
EHRPWM_TZn_IN3
MCASP0_ACLKR
SPI2_CLK
0
IO
IO
O
IO
IO
IO
IO
IO
IO
IO
I
0
0
MCASP0_ACLKR
UART1_TXD
EHRPWM0_B
GPIO1_14
PADCONFIG:
PADCONFIG108
0x000F41B0
A20
D16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
PU/PD
0
pad
0
EQEP1_I
MCASP0_ACLKX
SPI2_CS1
0
MCASP0_ACLKX
1
PADCONFIG:
PADCONFIG105
0x000F41A4
B20
C17
ECAP2_IN_APWM_OUT
GPIO1_11
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
pad
0
EQEP1_A
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MCASP0_AFSR
0
1
2
6
7
8
0
1
2
7
8
0
1
2
5
6
7
8
0
1
2
5
6
7
8
0
1
2
3
4
5
6
7
8
IO
IO
I
0
1
SPI2_CS0
MCASP0_AFSR
UART1_RXD
1
PADCONFIG:
PADCONFIG107
0x000F41AC
E19
D15
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
PU/PD
EHRPWM0_A
GPIO1_13
IO
IO
IO
IO
IO
IO
IO
I
0
pad
0
EQEP1_S
MCASP0_AFSX
SPI2_CS3
0
MCASP0_AFSX
1
PADCONFIG:
PADCONFIG106
0x000F41A8
D20
C16
AUDIO_EXT_REFCLK1
GPIO1_12
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
LVCMOS
PU/PD
pad
0
EQEP1_B
MCASP0_AXR0
PR0_ECAP0_IN_APWM_OUT
AUDIO_EXT_REFCLK0
PR0_UART0_TXD
EHRPWM1_B
GPIO1_10
IO
IO
IO
O
0
0
MCASP0_AXR0
0
PADCONFIG:
PADCONFIG104
0x000F41A0
E18
D18
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
IO
IO
IO
IO
I
0
pad
0
EQEP0_I
MCASP0_AXR1
SPI2_CS2
0
1
MCASP0_AXR1
ECAP1_IN_APWM_OUT
PR0_UART0_RXD
EHRPWM1_A
GPIO1_9
0
PADCONFIG:
PADCONFIG103
0x000F419C
B18
A18
1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
IO
IO
IO
O
0
pad
0
EQEP0_S
MCASP0_AXR2
SPI2_D1
0
0
UART1_RTSn
UART6_TXD
MCASP0_AXR2
O
PADCONFIG:
PADCONFIG102
0x000F4198
A19
B17
PR0_IEP0_EDIO_DATA_IN_OUT29
ECAP2_IN_APWM_OUT
PR0_UART0_TXD
GPIO1_8
IO
IO
O
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
I
pad
0
EQEP0_B
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
30
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MCASP0_AXR3
0
1
2
3
4
5
6
7
8
IO
IO
I
0
0
SPI2_D0
UART1_CTSn
1
MCASP0_AXR3
UART6_RXD
I
1
PADCONFIG:
PADCONFIG101
0x000F4194
B19
B18
PR0_IEP0_EDIO_DATA_IN_OUT28
ECAP1_IN_APWM_OUT
PR0_UART0_RXD
GPIO1_7
IO
IO
I
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
0
1
IO
I
pad
0
EQEP0_A
MCU_ERRORn
PADCONFIG:
MCU_PADCONFIG24
0x04084060
D1
A8
B1
B9
MCU_ERRORn
0
IO
Off / Off / Down On / SS / Down
0
7
7
1.8 V
VDDS_OSC0
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
LVCMOS
I2C OD FS
I2C OD FS
PU/PD
MCU_I2C0_SCL
MCU_I2C0_SCL
MCU_GPIO0_17
MCU_I2C0_SDA
MCU_GPIO0_18
0
7
0
7
IOD
IOD
IOD
IOD
1
PADCONFIG:
MCU_PADCONFIG17
0x04084044
Off / Off / NA
Off / Off / NA
On / SS / NA
On / SS / NA
1.8 V/3.3 V
1.8 V/3.3 V
pad
1
MCU_I2C0_SDA
PADCONFIG:
MCU_PADCONFIG18
0x04084048
D10
A10
pad
MCU_MCAN0_RX
MCU_TIMER_IO0
MCU_SPI1_CS3
MCU_GPIO0_14
MCU_MCAN0_TX
WKUP_TIMER_IO0
MCU_SPI0_CS3
MCU_GPIO0_13
MCU_MCAN1_RX
MCU_TIMER_IO3
MCU_SPI0_CS2
MCU_SPI1_CS2
MCU_SPI1_CLK
MCU_GPIO0_16
0
1
2
7
0
1
2
7
0
1
2
3
4
7
I
1
0
MCU_MCAN0_RX
IO
IO
IO
O
PADCONFIG:
MCU_PADCONFIG14
0x04084038
B3
D6
C4
C5
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
pad
MCU_MCAN0_TX
IO
IO
IO
I
0
1
PADCONFIG:
MCU_PADCONFIG13
0x04084034
pad
1
IO
IO
IO
IO
IO
0
MCU_MCAN1_RX
1
PADCONFIG:
MCU_PADCONFIG16
0x04084040
D4
D6
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_CANUART
Yes
LVCMOS
PU/PD
1
0
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MCU_MCAN1_TX
0
1
3
4
7
O
IO
IO
I
MCU_MCAN1_TX
MCU_TIMER_IO2
MCU_SPI1_CS1
MCU_EXT_REFCLK0
MCU_GPIO0_15
MCU_OSC0_XI
0
1
PADCONFIG:
MCU_PADCONFIG15
0x0408403C
E5
D5
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_CANUART
Yes
LVCMOS
PU/PD
0
IO
I
pad
B2
A3
A5
A6
MCU_OSC0_XI
MCU_OSC0_XO
MCU_PORz
1.8 V
1.8 V
VDDS_OSC0
VDDS_OSC0
HFOSC
HFOSC
MCU_OSC0_XO
O
PADCONFIG:
MCU_PADCONFIG22
0x04084058
D2
B12
E11
A7
B2
A12
C9
B7
MCU_PORz
0
I
0
0
0
7
7
1.8 V
VDDS_OSC0
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
Yes
Yes
FS RESET
LVCMOS
LVCMOS
LVCMOS
LVCMOS
MCU_RESETSTATz
MCU_RESETSTATz
MCU_GPIO0_21
0
7
O
PADCONFIG:
MCU_PADCONFIG23
0x0408405C
Off / Low / Off
On / Off / Up
Off / Off / Off
Off / Off / Off
Off / SS / Off
On / Off / Up
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
PU/PD
PU/PD
PU/PD
PU/PD
IO
pad
MCU_RESETz
PADCONFIG:
MCU_PADCONFIG21
0x04084054
MCU_RESETz
0
I
MCU_SPI0_CLK
MCU_SPI0_CLK
MCU_GPIO0_2
0
7
IO
IO
0
PADCONFIG:
MCU_PADCONFIG2
0x04084008
pad
MCU_SPI0_CS0
MCU_SPI0_CS0
0
4
IO
IO
1
0
PADCONFIG:
MCU_PADCONFIG0
0x04084000
WKUP_TIMER_IO1
E8
E7
MCU_GPIO0_0
7
IO
pad
1
MCU_SPI0_CS1
MCU_OBSCLK0
MCU_SYSCLKOUT0
MCU_EXT_REFCLK0
MCU_TIMER_IO1
MCU_GPIO0_1
0
1
2
3
4
7
0
IO
O
MCU_SPI0_CS1
O
PADCONFIG:
MCU_PADCONFIG1
0x04084004
B8
C8
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV_MCU
Yes
LVCMOS
PU/PD
I
0
0
IO
IO
IO
pad
0
MCU_SPI0_D0
MCU_SPI0_D0
PADCONFIG:
MCU_PADCONFIG3
0x0408400C
D9
C9
E8
D8
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_GPIO0_3
MCU_SPI0_D1
MCU_GPIO0_4
7
0
7
IO
IO
IO
pad
0
MCU_SPI0_D1
PADCONFIG:
MCU_PADCONFIG4
0x04084010
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
32
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MCU_UART0_CTSn
0
1
3
7
0
1
3
7
0
I
1
0
MCU_UART0_CTSn
MCU_TIMER_IO0
MCU_SPI1_D0
IO
IO
IO
O
PADCONFIG:
MCU_PADCONFIG7
0x0408401C
A6
B6
B8
D7
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
0
MCU_GPIO0_7
pad
MCU_UART0_RTSn
MCU_TIMER_IO1
MCU_SPI1_D1
MCU_UART0_RTSn
IO
IO
IO
I
0
0
PADCONFIG:
MCU_PADCONFIG8
0x04084020
MCU_GPIO0_8
pad
1
MCU_UART0_RXD
MCU_UART0_RXD
PADCONFIG:
MCU_PADCONFIG5
0x04084014
B5
A5
A8
B6
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
VDDSHV2
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
MCU_GPIO0_5
MCU_UART0_TXD
MCU_GPIO0_6
MDIO0_MDC
GPIO0_86
7
0
7
0
7
0
7
IO
O
pad
MCU_UART0_TXD
PADCONFIG:
MCU_PADCONFIG6
0x04084018
IO
O
pad
MDIO0_MDC
PADCONFIG:
PADCONFIG88
0x000F4160
AD24
AB22
V17
U16
IO
IO
IO
pad
0
MDIO0_MDIO
MDIO0_MDIO
GPIO0_85
PADCONFIG:
PADCONFIG87
0x000F415C
VDDSHV2
pad
MMC0_CLK
I2C3_SCL
0
1
2
3
4
5
6
7
IO
IOD
IO
O
0
1
0
EHRPWM2_A
PR0_PRU1_GPO4
PR0_PRU1_GPI4
SPI1_CS1
MMC0_CLK
PADCONFIG:
PADCONFIG134
0x000F4218
AB1
Y1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
I
0
1
IO
IO
IO
TIMER_IO4
0
GPIO1_40
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MMC0_CMD
0
1
2
3
4
5
6
7
0
2
3
7
0
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
IO
IOD
IO
IO
I
1
1
I2C3_SDA
EHRPWM2_B
PR0_PRU0_GPO4
PR0_PRU0_GPI4
SPI1_CS2
0
MMC0_CMD
0
PADCONFIG:
PADCONFIG136
0x000F4220
Y3
V3
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
IO
IO
IO
IO
IO
I
1
TIMER_IO5
0
GPIO1_41
pad
0
MMC1_CLK
TIMER_IO4
MMC1_CLK
0
PADCONFIG:
PADCONFIG141
0x000F4234
B22
A21
A20
C18
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV5
VDDSHV5
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
UART3_RXD
GPIO1_46
1
IO
IO
IO
O
pad
1
MMC1_CMD
TIMER_IO5
MMC1_CMD
0
PADCONFIG:
PADCONFIG143
0x000F423C
UART3_TXD
GPIO1_47
IO
I
pad
1
MMC1_SDCD
UART6_RXD
TIMER_IO6
MMC1_SDCD
I
1
PADCONFIG:
PADCONFIG144
0x000F4240
D17
C17
D25
C24
C15
B15
E21
C21
IO
O
0
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
VDDSHV6
VDDSHV6
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
SDIO
PU/PD
PU/PD
PU/PD
PU/PD
UART3_RTSn
GPIO1_48
IO
I
pad
1
MMC1_SDWP
UART6_TXD
TIMER_IO7
MMC1_SDWP
O
PADCONFIG:
PADCONFIG145
0x000F4244
IO
I
0
1
UART3_CTSn
GPIO1_49
IO
IO
IO
IO
I
pad
0
MMC2_CLK
MCASP1_ACLKR
MCASP1_AXR5
UART6_RXD
GPIO0_69
MMC2_CLK
0
PADCONFIG:
PADCONFIG70
0x000F4118
0
1
IO
IO
IO
IO
O
pad
1
MMC2_CMD
MCASP1_AFSR
MCASP1_AXR4
UART6_TXD
GPIO0_70
MMC2_CMD
0
PADCONFIG:
PADCONFIG72
0x000F4120
0
SDIO
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
34
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
VDDSHV6
VDDSHV6
[5]
[6]
MMC2_SDCD
0
1
3
7
0
1
3
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
1
0
MMC2_SDCD
MCASP1_ACLKX
UART4_RXD
GPIO0_71
IO
I
PADCONFIG:
PADCONFIG73
0x000F4124
A23
B23
D20
C20
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
IO
I
pad
1
MMC2_SDWP
MCASP1_AFSX
UART4_TXD
GPIO0_72
MMC2_SDWP
IO
O
IO
IO
I
0
PADCONFIG:
PADCONFIG74
0x000F4128
pad
1
MMC0_DAT0
UART3_CTSn
EHRPWM_TZn_IN1
PR0_PRU0_GPO3
PR0_PRU0_GPI3
SPI2_CLK
1
MMC0_DAT0
I
0
PADCONFIG:
PADCONFIG133
0x000F4214
AA2
V2
IO
I
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
IO
IO
IO
O
IO
IO
I
0
GPIO1_39
pad
1
MMC0_DAT1
UART3_RTSn
EHRPWM1_B
PR0_PRU0_GPO2
PR0_PRU0_GPI2
SPI1_CS3
0
0
MMC0_DAT1
PADCONFIG:
PADCONFIG132
0x000F4210
AA1
V1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
IO
IO
IO
IO
O
IO
IO
I
1
SPI2_CS0
1
GPIO1_38
pad
1
MMC0_DAT2
UART3_TXD
EHRPWM1_A
PR0_PRU0_GPO1
PR0_PRU0_GPI1
SPI1_CLK
0
0
MMC0_DAT2
PADCONFIG:
PADCONFIG131
0x000F420C
AA3
W2
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
IO
IO
IO
0
TIMER_IO0
0
GPIO1_37
pad
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MMC0_DAT3
0
1
2
3
4
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
IO
I
1
1
UART3_RXD
EHRPWM0_B
PR0_PRU0_GPO0
PR0_PRU0_GPI0
SPI1_CS0
IO
IO
I
0
MMC0_DAT3
0
PADCONFIG:
PADCONFIG130
0x000F4208
Y4
W1
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
IO
IO
IO
IO
I
1
SPI2_CS2
1
GPIO1_36
pad
1
MMC0_DAT4
UART2_CTSn
EHRPWM0_A
PR0_PRU1_GPO3
PR0_PRU1_GPI3
SPI2_D1
1
MMC0_DAT4
IO
O
I
0
PADCONFIG:
PADCONFIG129
0x000F4204
AB2
Y2
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
0
IO
IO
IO
O
I
GPIO1_35
pad
1
MMC0_DAT5
UART2_RTSn
EHRPWM_TZn_IN2
PR0_PRU1_GPO2
PR0_PRU1_GPI2
SPI2_D0
MMC0_DAT5
0
PADCONFIG:
PADCONFIG128
0x000F4200
AC1
W3
O
I
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
0
IO
IO
IO
O
O
O
I
GPIO1_34
pad
1
MMC0_DAT6
UART2_TXD
EHRPWM0_SYNCO
PR0_PRU1_GPO1
PR0_PRU1_GPI1
SPI1_D1
MMC0_DAT6
PADCONFIG:
PADCONFIG127
0x000F41FC
AD2
W4
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
0
IO
IO
IO
SPI2_CS3
1
GPIO1_33
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
36
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
MMC0_DAT7
0
1
2
3
4
5
6
7
0
1
2
3
4
7
0
1
2
3
4
7
0
1
2
3
7
0
1
2
3
7
0
1
IO
I
1
1
0
UART2_RXD
EHRPWM0_SYNCI
PR0_PRU1_GPO0
PR0_PRU1_GPI0
SPI1_D0
I
MMC0_DAT7
O
I
PADCONFIG:
PADCONFIG126
0x000F41F8
AC2
V4
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV4
Yes
SDIO
PU/PD
0
0
IO
IO
IO
IO
I
SPI2_CS1
1
GPIO1_32
pad
1
MMC1_DAT0
CP_GEMAC_CPTS0_HW2TSPUSH
TIMER_IO3
0
MMC1_DAT0
IO
I
0
PADCONFIG:
PADCONFIG140
0x000F4230
A22
A19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
SDIO
PU/PD
UART2_CTSn
1
ECAP2_IN_APWM_OUT
GPIO1_45
IO
IO
IO
I
0
pad
1
MMC1_DAT1
CP_GEMAC_CPTS0_HW1TSPUSH
TIMER_IO2
0
MMC1_DAT1
IO
O
IO
IO
IO
O
IO
O
IO
IO
O
IO
I
0
PADCONFIG:
PADCONFIG139
0x000F422C
B21
B19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
Yes
Yes
SDIO
PU/PD
UART2_RTSn
ECAP1_IN_APWM_OUT
GPIO1_44
0
pad
1
MMC1_DAT2
MMC1_DAT2
CP_GEMAC_CPTS0_TS_SYNC
TIMER_IO1
PADCONFIG:
PADCONFIG138
0x000F4228
C21
B20
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV5
SDIO
PU/PD
UART2_TXD
GPIO1_43
pad
1
MMC1_DAT3
MMC1_DAT3
CP_GEMAC_CPTS0_TS_COMP
TIMER_IO0
PADCONFIG:
PADCONFIG137
0x000F4224
D22
B24
C19
B21
0
1
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV5
VDDSHV6
Yes
Yes
SDIO
SDIO
PU/PD
PU/PD
UART2_RXD
GPIO1_42
IO
IO
IO
pad
1
MMC2_DAT0
MMC2_DAT0
PADCONFIG:
PADCONFIG69
0x000F4114
MCASP1_AXR0
0
GPIO0_68
7
IO
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
VDDSHV6
VDDSHV6
[5]
[6]
MMC2_DAT1
MMC2_DAT1
0
1
IO
IO
1
0
PADCONFIG:
PADCONFIG68
0x000F4110
MCASP1_AXR1
GPIO0_67
C25
E23
D21
E19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
Yes
Yes
SDIO
PU/PD
PU/PD
7
IO
pad
MMC2_DAT2
MCASP1_AXR2
UART5_TXD
GPIO0_66
0
1
3
7
0
1
3
7
IO
IO
O
1
0
MMC2_DAT2
PADCONFIG:
PADCONFIG67
0x000F410C
SDIO
SDIO
IO
IO
IO
I
pad
1
MMC2_DAT3
MCASP1_AXR3
UART5_RXD
GPIO0_65
MMC2_DAT3
0
PADCONFIG:
PADCONFIG66
0x000F4108
D24
E20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV6
Yes
PU/PD
1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
pad
AA5
Y6
AA2
AA3
V5
OLDI0_A0N
OLDI0_A0P
OLDI0_A1N
OLDI0_A1P
OLDI0_A2N
OLDI0_A2P
OLDI0_A3N
OLDI0_A3P
OLDI0_A4N
OLDI0_A4P
OLDI0_A5N
OLDI0_A5P
OLDI0_A6N
OLDI0_A6P
OLDI0_A7N
OLDI0_A7P
OLDI0_CLK0N
OLDI0_CLK0P
OLDI0_CLK1N
OLDI0_CLK1P
OSPI0_CLK
OLDI0_A0N
OLDI0_A0P
OLDI0_A1N
OLDI0_A1P
OLDI0_A2N
OLDI0_A2P
OLDI0_A3N
OLDI0_A3P
OLDI0_A4N
OLDI0_A4P
OLDI0_A5N
OLDI0_A5P
OLDI0_A6N
OLDI0_A6P
OLDI0_A7N
OLDI0_A7P
OLDI0_CLK0N
OLDI0_CLK0P
OLDI0_CLK1N
OLDI0_CLK1P
OSPI0_CLK
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
VDDA_1P8_OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
OLDI
AD3
AB4
Y8
V6
U7
AA8
AB6
AA7
AC6
AC5
AE5
AD6
AE6
AD7
AD8
AE7
AD4
AE3
AE4
AD5
U6
W6
W5
AA4
Y5
AA6
AA5
AA10
Y9
AA8
Y8
V7
V8
Y7
AA7
0
7
PADCONFIG:
PADCONFIG0
0x000F4000
H24
G19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
GPIO0_0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
38
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
OSPI0_DQS
OSPI0_DQS
0
5
I
I
0
1
PADCONFIG:
PADCONFIG2
0x000F4008
UART5_CTSn
GPIO0_2
J24
G25
F23
G21
H20
G18
F19
F17
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
VDDSHV1
VDDSHV1
VDDSHV1
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
7
IO
pad
0
OSPI0_LBCLKO
OSPI0_LBCLKO
UART5_RTSn
0
5
IO
O
PADCONFIG:
PADCONFIG1
0x000F4004
GPIO0_1
7
0
IO
O
pad
pad
OSPI0_CSn0
OSPI0_CSn0
PADCONFIG:
PADCONFIG11
0x000F402C
GPIO0_11
7
0
7
IO
O
OSPI0_CSn1
OSPI0_CSn1
GPIO0_12
PADCONFIG:
PADCONFIG12
0x000F4030
IO
pad
1
OSPI0_CSn2
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
O
IO
O
SPI1_CS1
OSPI0_CSn2
OSPI0_RESET_OUT1
MCASP1_AFSR
MCASP1_AXR2
UART5_RXD
PADCONFIG:
PADCONFIG13
0x000F4034
H21
E17
IO
IO
I
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
1
GPIO0_13
IO
O
pad
OSPI0_CSn3
OSPI0_RESET_OUT0
OSPI0_ECC_FAIL
MCASP1_ACLKR
MCASP1_AXR3
UART5_TXD
O
OSPI0_CSn3
I
1
0
0
PADCONFIG:
PADCONFIG14
0x000F4038
E24
E18
IO
IO
O
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV1
Yes
LVCMOS
PU/PD
GPIO0_14
IO
IO
pad
0
OSPI0_D0
OSPI0_D0
PADCONFIG:
PADCONFIG3
0x000F400C
E25
G24
F25
F18
G17
F21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
VDDSHV1
VDDSHV1
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
GPIO0_3
OSPI0_D1
GPIO0_4
OSPI0_D2
GPIO0_5
7
0
7
0
7
IO
IO
IO
IO
IO
pad
0
OSPI0_D1
PADCONFIG:
PADCONFIG4
0x000F4010
pad
0
OSPI0_D2
PADCONFIG:
PADCONFIG5
0x000F4014
pad
Copyright © 2023 Texas Instruments Incorporated
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39
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
OSPI0_D3
OSPI0_D3
0
7
IO
IO
0
PADCONFIG:
PADCONFIG6
0x000F4018
F24
J23
F20
G21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV1
Yes
Yes
LVCMOS
PU/PD
PU/PD
GPIO0_6
pad
OSPI0_D4
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
IO
IO
IO
I
0
1
OSPI0_D4
SPI1_CS0
PADCONFIG:
PADCONFIG7
0x000F401C
MCASP1_AXR1
UART6_RXD
GPIO0_7
0
VDDSHV1
VDDSHV1
VDDSHV1
VDDSHV1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
1
IO
IO
IO
IO
O
pad
0
OSPI0_D5
OSPI0_D5
SPI1_CLK
0
PADCONFIG:
PADCONFIG8
0x000F4020
J25
H25
J22
H21
G20
J21
MCASP1_AXR0
UART6_TXD
GPIO0_8
0
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
Yes
Yes
Yes
PU/PD
PU/PD
PU/PD
IO
IO
IO
IO
O
pad
0
OSPI0_D6
OSPI0_D6
SPI1_D0
0
PADCONFIG:
PADCONFIG9
0x000F4024
MCASP1_ACLKX
UART6_RTSn
GPIO0_9
0
IO
IO
IO
IO
I
pad
0
OSPI0_D7
OSPI0_D7
SPI1_D1
0
PADCONFIG:
PADCONFIG10
0x000F4028
MCASP1_AFSX
UART6_CTSn
GPIO0_10
0
1
IO
O
pad
PMIC_LPM_EN0
PMIC_LPM_EN0
PADCONFIG:
MCU_PADCONFIG32
0x04084080
B7
C7
Off / Off / Off
Off / Low / Off
Off / Low / Off
On / Off / Up
Off / SS / Off
Off / SS / Off
Off / SS / Off
On / Off / Up
0
0
0
0
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV0
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
MCU_GPIO0_22
PORz_OUT
7
IO
pad
PORz_OUT
PADCONFIG:
PADCONFIG148
0x000F4250
E21
F22
F20
E13
E14
E15
0
O
RESETSTATz
PADCONFIG:
PADCONFIG147
0x000F424C
RESETSTATz
RESET_REQz
0
0
O
I
VDDSHV0
RESET_REQz
PADCONFIG:
PADCONFIG146
0x000F4248
VDDSHV0
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
40
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
RGMII1_RXC
0
1
2
7
0
1
I
I
0
0
RGMII1_RXC
RMII1_REF_CLK
PR0_UART0_CTSn
GPIO0_80
PADCONFIG:
PADCONFIG82
0x000F4148
AD17
AA16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
I
1
IO
I
pad
0
RGMII1_RX_CTL
RGMII1_RX_CTL
RMII1_RX_ER
PADCONFIG:
PADCONFIG81
0x000F4144
I
0
AE17
AE19
AD19
W14
W16
V15
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
GPIO0_79
7
IO
pad
RGMII1_TXC
RGMII1_TXC
0
1
IO
I
0
0
PADCONFIG:
PADCONFIG76
0x000F4130
RMII1_CRS_DV
GPIO0_74
7
IO
pad
RGMII1_TX_CTL
RGMII1_TX_CTL
RMII1_TX_EN
0
1
O
O
PADCONFIG:
PADCONFIG75
0x000F412C
GPIO0_73
7
IO
pad
RGMII2_RXC
0
1
2
3
4
5
7
0
1
2
3
4
7
0
1
2
3
4
7
I
I
0
0
RMII2_REF_CLK
MCASP2_AXR1
PR0_PRU0_GPO1
PR0_PRU0_GPI1
PR0_ECAP0_SYNC_IN
GPIO1_2
RGMII2_RXC
IO
IO
I
0
PADCONFIG:
PADCONFIG96
0x000F4180
AD23
V18
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
I
0
IO
I
pad
0
RGMII2_RX_CTL
RMII2_RX_ER
MCASP2_AXR3
PR0_PRU0_GPO0
PR0_PRU0_GPI0
GPIO1_1
I
0
RGMII2_RX_CTL
IO
IO
I
0
PADCONFIG:
PADCONFIG95
0x000F417C
AD22
W19
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
0
IO
IO
I
pad
0
RGMII2_TXC
RMII2_CRS_DV
MCASP2_AXR5
PR0_PRU1_GPO1
PR0_PRU1_GPI1
GPIO0_88
0
RGMII2_TXC
IO
O
I
0
PADCONFIG:
PADCONFIG90
0x000F4168
AE21
Y18
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
RGMII2_TX_CTL
0
1
2
3
4
7
0
1
O
O
IO
O
I
RMII2_TX_EN
MCASP2_AXR4
PR0_PRU1_GPO0
PR0_PRU1_GPI0
GPIO0_87
RGMII2_TX_CTL
0
PADCONFIG:
PADCONFIG89
0x000F4164
AA19
Y21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
pad
0
IO
I
RGMII1_RD0
RGMII1_RD0
PADCONFIG:
PADCONFIG83
0x000F414C
RMII1_RXD0
I
0
AB17
AC17
AB16
AA15
AE20
AD20
AE18
AD18
W15
Y16
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
VDDSHV2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
GPIO0_81
7
IO
pad
RGMII1_RD1
RGMII1_RD1
RMII1_RXD1
0
1
I
I
0
0
PADCONFIG:
PADCONFIG84
0x000F4150
GPIO0_82
7
IO
pad
0
RGMII1_RD2
RGMII1_RD2
0
2
I
PADCONFIG:
PADCONFIG85
0x000F4154
PR0_UART0_RTSn
O
AA17
Y15
GPIO0_83
7
0
IO
I
pad
0
RGMII1_RD3
RGMII1_RD3
PADCONFIG:
PADCONFIG86
0x000F4158
GPIO0_84
7
IO
pad
RGMII1_TD0
RGMII1_TD0
RMII1_TXD0
0
1
O
O
PADCONFIG:
PADCONFIG77
0x000F4134
U14
GPIO0_75
7
IO
pad
pad
RGMII1_TD1
RGMII1_TD1
RMII1_TXD1
0
1
O
O
PADCONFIG:
PADCONFIG78
0x000F4138
AA19
Y17
GPIO0_76
7
IO
RGMII1_TD2
RGMII1_TD2
0
2
O
I
PADCONFIG:
PADCONFIG79
0x000F413C
PR0_UART0_RXD
1
GPIO0_77
7
IO
pad
RGMII1_TD3
RGMII1_TD3
0
2
O
O
PADCONFIG:
PADCONFIG80
0x000F4140
PR0_UART0_TXD
AA18
GPIO0_78
7
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
42
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
RGMII2_RD0
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
2
3
4
5
7
8
0
2
3
4
5
7
8
0
1
2
3
4
7
I
I
0
0
0
0
0
RMII2_RXD0
RGMII2_RD0
MCASP2_AXR2
PR0_PRU0_GPO2
PR0_PRU0_GPI2
PR0_UART0_RTSn
GPIO1_3
IO
IO
I
PADCONFIG:
PADCONFIG97
0x000F4184
AE23
AB20
AC21
W18
Y20
Y19
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV2
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
O
IO
I
pad
0
RGMII2_RD1
RMII2_RXD1
I
0
RGMII2_RD1
MCASP2_AFSR
PR0_PRU0_GPO3
PR0_PRU0_GPI3
MCASP2_AXR7
GPIO1_4
IO
IO
I
0
PADCONFIG:
PADCONFIG98
0x000F4188
0
VDDSHV2
0
IO
IO
I
0
pad
0
RGMII2_RD2
MCASP2_AXR0
PR0_PRU0_GPO4
PR0_PRU0_GPI4
PR0_UART0_RXD
GPIO1_5
IO
IO
I
0
RGMII2_RD2
0
PADCONFIG:
PADCONFIG99
0x000F418C
0
VDDSHV2
I
1
IO
I
pad
0
EQEP2_A
RGMII2_RD3
I
0
AUDIO_EXT_REFCLK0
PR0_PRU0_GPO16
PR0_PRU0_GPI16
PR0_UART0_TXD
GPIO1_6
IO
IO
I
0
RGMII2_RD3
0
PADCONFIG:
PADCONFIG100
0x000F4190
AE22
W20
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
O
IO
I
pad
0
EQEP2_B
RGMII2_TD0
O
O
IO
O
I
RMII2_TXD0
RGMII2_TD0
MCASP2_AXR6
PR0_PRU1_GPO2
PR0_PRU1_GPI2
GPIO0_89
0
PADCONFIG:
PADCONFIG91
0x000F416C
Y18
AA20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
0
IO
pad
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
RGMII2_TD1
0
1
2
3
4
5
7
0
2
3
4
5
7
8
0
2
3
4
5
6
7
8
O
O
RMII2_TXD1
MCASP2_ACLKR
PR0_PRU1_GPO3
PR0_PRU1_GPI3
MCASP2_AXR8
GPIO0_90
RGMII2_TD1
IO
O
0
PADCONFIG:
PADCONFIG92
0x000F4170
AA18
U15
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
I
0
0
IO
IO
O
pad
RGMII2_TD2
MCASP2_AFSX
PR0_PRU1_GPO4
PR0_PRU1_GPI4
PR0_ECAP0_IN_APWM_OUT
GPIO0_91
IO
O
0
RGMII2_TD2
PADCONFIG:
PADCONFIG93
0x000F4174
AD21
W17
I
0
0
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
IO
IO
IO
O
pad
0
EQEP2_I
RGMII2_TD3
MCASP2_ACLKX
PR0_PRU1_GPO16
PR0_PRU1_GPI16
PR0_ECAP0_SYNC_OUT
PR0_UART0_CTSn
GPIO1_0
IO
O
0
0
RGMII2_TD3
I
PADCONFIG:
PADCONFIG94
0x000F4178
AC20
V16
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV2
Yes
LVCMOS
PU/PD
O
I
1
pad
0
IO
IO
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IO
O
EQEP2_S
B1
A2
B3
C3
E6
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD0
RSVD1
F6
RSVD2
AE2
T2
F8
RSVD3
R6
T13
T14
M4
M5
RSVD4
U4
RSVD5
AA12
Y15
E7
RSVD6
RSVD7
RSVD8
SPI0_CLK
0
1
2
7
0
SPI0_CLK
CP_GEMAC_CPTS0_TS_SYNC
EHRPWM1_A
GPIO1_17
PADCONFIG:
PADCONFIG111
0x000F41BC
A14
D12
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
IO
IO
0
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
44
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
SPI0_CS0
0
2
6
7
0
1
2
3
7
9
0
1
2
7
0
1
2
7
IO
IO
I
1
0
SPI0_CS0
EHRPWM0_A
PADCONFIG:
PADCONFIG109
0x000F41B4
A13
C13
C11
D13
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
PR0_ECAP0_SYNC_IN
GPIO1_15
0
IO
IO
O
IO
IO
IO
I
pad
1
SPI0_CS1
CP_GEMAC_CPTS0_TS_COMP
EHRPWM0_B
SPI0_CS1
0
0
PADCONFIG:
PADCONFIG110
0x000F41B8
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
VDDSHV0
ECAP0_IN_APWM_OUT
GPIO1_16
pad
0
EHRPWM_TZn_IN5
SPI0_D0
IO
I
0
SPI0_D0
CP_GEMAC_CPTS0_HW1TSPUSH
EHRPWM1_B
0
PADCONFIG:
PADCONFIG112
0x000F41C0
B13
B14
C12
A14
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
IO
IO
I
0
GPIO1_18
pad
0
SPI0_D1
SPI0_D1
CP_GEMAC_CPTS0_HW2TSPUSH
EHRPWM_TZn_IN0
GPIO1_19
0
PADCONFIG:
PADCONFIG113
0x000F41C4
I
0
IO
pad
TCK
PADCONFIG:
MCU_PADCONFIG25
0x04084064
A10
A11
D12
B11
B10
C10
D10
E10
B11
A11
TCK
TDI
0
0
0
0
0
I
On / Off / Up
On / Off / Up
Off / Off / Up
On / Off / Up
On / Off / Up
On / Off / Up
Off / SS / Up
On / Off / Up
0
0
0
0
0
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
TDI
PADCONFIG:
MCU_PADCONFIG27
0x0408406C
I
TDO
PADCONFIG:
MCU_PADCONFIG28
0x04084070
TDO
TMS
TRSTn
OZ
TMS
PADCONFIG:
MCU_PADCONFIG29
0x04084074
I
I
TRSTn
PADCONFIG:
MCU_PADCONFIG26
0x04084068
On / Off / Down On / Off / Down
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
UART0_CTSn
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
7
0
1
2
3
7
I
IO
IOD
I
1
1
1
1
0
0
SPI0_CS2
I2C3_SCL
UART2_RXD
UART0_CTSn
TIMER_IO6
IO
IO
O
PADCONFIG:
PADCONFIG116
0x000F41D0
A15
B14
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
AUDIO_EXT_REFCLK0
PR0_ECAP0_SYNC_OUT
GPIO1_22
IO
IO
I
pad
0
MCASP2_AFSX
MMC2_SDCD
UART0_RTSn
SPI0_CS3
1
O
IO
IOD
O
1
1
I2C3_SDA
UART2_TXD
UART0_RTSn
TIMER_IO7
IO
IO
IO
IO
IO
I
0
0
PADCONFIG:
PADCONFIG117
0x000F41D4
B15
C13
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
AUDIO_EXT_REFCLK1
PR0_ECAP0_IN_APWM_OUT
GPIO1_23
0
pad
0
MCASP2_ACLKX
MMC2_SDWP
UART0_RXD
1
I
1
UART0_RXD
ECAP1_IN_APWM_OUT
SPI2_D0
IO
IO
IO
IO
O
0
PADCONFIG:
PADCONFIG114
0x000F41C8
D14
E14
A13
E11
0
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
VDDSHV0
VDDSHV0
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
EHRPWM2_A
GPIO1_20
0
pad
UART0_TXD
UART0_TXD
ECAP2_IN_APWM_OUT
SPI2_D1
IO
IO
IO
IO
0
0
PADCONFIG:
PADCONFIG115
0x000F41CC
Off / Off / Off
Off / Off / Off
1.8 V/3.3 V
EHRPWM2_B
GPIO1_21
0
pad
VDDA_1P8_USB,
VDDA_3P3_USB
AE11
AD11
AA11
Y10
USB0_DM
USB0_DP
USB0_DM
USB0_DP
IO
IO
1.8 V/3.3 V
1.8 V/3.3 V
USB2PHY
USB2PHY
VDDA_1P8_USB,
VDDA_3P3_USB
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
46
Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
USB0_DRVVBUS
USB0_DRVVBUS
0
7
O
PADCONFIG:
PADCONFIG149
0x000F4254
C20
D17
Off / Off / Down Off / Off / Down
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
GPIO1_50
IO
pad
VDDA_1P8_USB,
VDDA_3P3_USB
AE10
AC11
AD10
AE9
T8
V10
W8
W9
USB0_RCALIB
USB0_VBUS
USB1_DM
USB0_RCALIB
USB0_VBUS
USB1_DM
A
A
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
USB2PHY
USB2PHY
USB2PHY
USB2PHY
VDDA_1P8_USB,
VDDA_3P3_USB
VDDA_1P8_USB,
VDDA_3P3_USB
IO
VDDA_1P8_USB,
VDDA_3P3_USB
USB1_DP
USB1_DP
IO
O
USB1_DRVVBUS
USB1_DRVVBUS
0
7
PADCONFIG:
PADCONFIG150
0x000F4258
F18
E16
Off / Off / Down Off / Off / Down
7
1.8 V/3.3 V
VDDSHV0
Yes
LVCMOS
PU/PD
GPIO1_51
IO
pad
VDDA_1P8_USB,
VDDA_3P3_USB
AC9
V9
U9
USB1_RCALIB
USB1_VBUS
USB1_RCALIB
USB1_VBUS
A
A
1.8 V/3.3 V
1.8 V/3.3 V
USB2PHY
USB2PHY
VDDA_1P8_USB,
VDDA_3P3_USB
AB10
Y11
W14
R11
R12
P9, R9
R10
P12
P11
L9
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_1P8_OLDI0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_1P8_OLDI0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
W10, W9
Y13
W13
W12
L11
U11
H10
N10
P14
K12
M7
VDDA_PLL0
VDDA_PLL0
U15
VDDA_PLL1
VDDA_PLL1
L14
VDDA_PLL2
VDDA_PLL2
T9
VDDA_TEMP0
VDDA_TEMP0
G16
F16
VDDA_TEMP1
VDDA_TEMP1
J12, K16,
N12, N14, H11, M10,
VDDR_CORE
VDDR_CORE
PWR
P16, R12,
T10, U14
M13
F15, G14
L18, M19
W16, W19
F12, G13 VDDSHV0
K15, K16 VDDSHV1
R14, R15 VDDSHV2
VDDSHV0
VDDSHV1
VDDSHV2
PWR
PWR
PWR
Copyright © 2023 Texas Instruments Incorporated
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47
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
N18, P18,
T19, U18
N15, N16 VDDSHV3
N7, P7 VDDSHV4
VDDSHV3
PWR
T7
G17
VDDSHV4
PWR
PWR
PWR
PWR
PWR
F14, G14 VDDSHV5
H15, H16 VDDSHV6
VDDSHV5
J18
VDDSHV6
H9
G7, H7
VDDSHV_CANUART
VDDSHV_CANUART
VDDSHV_MCU
F11, G12
F10, G10 VDDSHV_MCU
K9, L8, P9, C1, J8, K7,
VDDS_DDR
VDDS_DDR
PWR
R8
M9
G7
F8
K9, L8, U1
L7
J7
VDDS_DDR_C
VDDS_OSC0
VDDS_DDR_C
VDDS_OSC0
PWR
PWR
PWR
H8
VDD_CANUART
VDD_CANUART
H8, J11,
J14, K17,
L12, L15,
M16, N11,
N13, N8,
P17, R11,
R14, U12,
V15, V17,
V8
H12, H14,
J11, J13,
J9, K10,
K14, L11,
L13, M12,
M14, M8,
N11, N13,
N9, P8
VDD_CORE
VDD_CORE
PWR
G10
K10
H10
H9
K11
F6
VMON_1P8_SOC
VMON_3P3_SOC
VMON_VSYS
VMON_1P8_SOC
VMON_3P3_SOC
VMON_VSYS
A
A
A
VOUT0_DE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
I
GPMC0_A17
PR0_PRU1_GPO17
PR0_PRU1_GPI17
UART3_CTSn
VOUT0_DE
0
1
PADCONFIG:
PADCONFIG63
0x000F40FC
Y20
T17
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I
PR0_PRU0_GPO7
PR0_PRU0_GPI7
GPIO0_62
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_HSYNC
GPMC0_A16
PR0_PRU1_GPO15
PR0_PRU1_GPI15
UART3_RTSn
VOUT0_HSYNC
0
PADCONFIG:
PADCONFIG62
0x000F40F8
AB24
W21
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
I
PR0_PRU0_GPO6
PR0_PRU0_GPI6
GPIO0_61
0
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
48
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VOUT0_PCLK
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
I
GPMC0_A19
PR0_PRU1_GPO19
PR0_PRU1_GPI19
UART2_CTSn
VOUT0_PCLK
0
1
PADCONFIG:
PADCONFIG65
0x000F4104
AC24
U17
I
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
PR0_PRU0_GPO19
PR0_PRU0_GPI19
GPIO0_64
IO
I
0
0
IO
IO
O
OZ
O
I
pad
0
PR0_ECAP0_IN_APWM_OUT
VOUT0_VSYNC
GPMC0_A18
PR0_PRU1_GPO18
PR0_PRU1_GPI18
UART2_RTSn
VOUT0_VSYNC
0
PADCONFIG:
PADCONFIG64
0x000F4100
AC25
T16
R21
P18
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
VDDSHV3
VDDSHV3
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
O
IO
I
PR0_PRU0_GPO18
PR0_PRU0_GPI18
GPIO0_63
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA0
GPMC0_A0
PR0_PRU1_GPO0
PR0_PRU1_GPI0
UART2_RXD
VOUT0_DATA0
0
1
PADCONFIG:
PADCONFIG46
0x000F40B8
U22
I
PR0_PRU0_GPO8
PR0_PRU0_GPI8
GPIO0_45
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA1
GPMC0_A1
PR0_PRU1_GPO1
PR0_PRU1_GPI1
UART2_TXD
VOUT0_DATA1
0
PADCONFIG:
PADCONFIG47
0x000F40BC
V24
O
IO
I
PR0_PRU0_GPO9
PR0_PRU0_GPI9
GPIO0_46
0
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VOUT0_DATA2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
I
GPMC0_A2
PR0_PRU1_GPO2
PR0_PRU1_GPI2
UART3_RXD
VOUT0_DATA2
0
1
PADCONFIG:
PADCONFIG48
0x000F40C0
W25
W24
Y25
Y24
R18
R19
R20
T20
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
I
PR0_PRU0_GPO10
PR0_PRU0_GPI10
GPIO0_47
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA3
GPMC0_A3
PR0_PRU1_GPO3
PR0_PRU1_GPI3
UART3_TXD
VOUT0_DATA3
0
PADCONFIG:
PADCONFIG49
0x000F40C4
VDDSHV3
VDDSHV3
VDDSHV3
LVCMOS
LVCMOS
LVCMOS
O
IO
I
PR0_PRU0_GPO11
PR0_PRU0_GPI11
GPIO0_48
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA4
GPMC0_A4
PR0_PRU1_GPO4
PR0_PRU1_GPI4
UART4_RXD
VOUT0_DATA4
0
1
PADCONFIG:
PADCONFIG50
0x000F40C8
I
PR0_PRU0_GPO12
PR0_PRU0_GPI12
GPIO0_49
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA5
GPMC0_A5
PR0_PRU1_GPO5
PR0_PRU1_GPI5
UART4_TXD
VOUT0_DATA5
0
PADCONFIG:
PADCONFIG51
0x000F40CC
O
IO
I
PR0_PRU0_GPO13
PR0_PRU0_GPI13
GPIO0_50
0
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
50
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VOUT0_DATA6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
I
GPMC0_A6
PR0_PRU1_GPO6
PR0_PRU1_GPI6
UART5_RXD
VOUT0_DATA6
0
1
PADCONFIG:
PADCONFIG52
0x000F40D0
Y23
AA25
V21
T21
T19
U21
R17
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
I
PR0_PRU0_GPO14
PR0_PRU0_GPI14
GPIO0_51
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA7
GPMC0_A7
PR0_PRU1_GPO7
PR0_PRU1_GPI7
UART5_TXD
VOUT0_DATA7
0
PADCONFIG:
PADCONFIG53
0x000F40D4
VDDSHV3
VDDSHV3
VDDSHV3
O
IO
I
PR0_PRU0_GPO15
PR0_PRU0_GPI15
GPIO0_52
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA8
GPMC0_A8
PR0_PRU1_GPO16
PR0_PRU1_GPI16
UART6_RXD
VOUT0_DATA8
0
1
PADCONFIG:
PADCONFIG54
0x000F40D8
I
PR0_PRU0_GPO17
PR0_PRU0_GPI17
GPIO0_53
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA9
GPMC0_A9
PR0_PRU1_GPO8
PR0_PRU1_GPI8
UART6_TXD
VOUT0_DATA9
0
PADCONFIG:
PADCONFIG55
0x000F40DC
W21
O
IO
I
PR0_PRU0_GPO16
PR0_PRU0_GPI16
GPIO0_54
0
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VOUT0_DATA10
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
I
GPMC0_A10
PR0_PRU1_GPO9
PR0_PRU1_GPI9
UART6_RTSn
VOUT0_DATA10
0
PADCONFIG:
PADCONFIG56
0x000F40E0
V20
T18
U20
U19
V21
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV3
Yes
Yes
Yes
Yes
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
O
IO
I
PR0_PRU0_GPO0
PR0_PRU0_GPI0
GPIO0_55
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA11
GPMC0_A11
PR0_PRU1_GPO10
PR0_PRU1_GPI10
UART6_CTSn
VOUT0_DATA11
0
1
PADCONFIG:
PADCONFIG57
0x000F40E4
AA23
AB25
AA24
VDDSHV3
VDDSHV3
VDDSHV3
LVCMOS
LVCMOS
LVCMOS
I
PR0_PRU0_GPO1
PR0_PRU0_GPI1
GPIO0_56
IO
I
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA12
GPMC0_A12
PR0_PRU1_GPO11
PR0_PRU1_GPI11
UART5_RTSn
VOUT0_DATA12
0
PADCONFIG:
PADCONFIG58
0x000F40E8
O
IO
I
PR0_PRU0_GPO2
PR0_PRU0_GPI2
GPIO0_57
0
0
IO
O
OZ
O
I
pad
VOUT0_DATA13
GPMC0_A13
PR0_PRU1_GPO12
PR0_PRU1_GPI12
UART5_CTSn
VOUT0_DATA13
0
1
PADCONFIG:
PADCONFIG59
0x000F40EC
I
PR0_PRU0_GPO3
PR0_PRU0_GPI3
GPIO0_58
IO
I
0
0
IO
pad
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
52
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
VOUT0_DATA14
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
O
OZ
O
GPMC0_A14
PR0_PRU1_GPO13
PR0_PRU1_GPI13
UART4_RTSn
PR0_PRU0_GPO4
PR0_PRU0_GPI4
GPIO0_59
VOUT0_DATA14
I
0
PADCONFIG:
PADCONFIG60
0x000F40F0
Y22
U18
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
O
IO
I
0
0
IO
O
pad
VOUT0_DATA15
GPMC0_A15
OZ
O
PR0_PRU1_GPO14
PR0_PRU1_GPI14
UART4_CTSn
PR0_PRU0_GPO5
PR0_PRU0_GPI5
GPIO0_60
VOUT0_DATA15
I
0
1
PADCONFIG:
PADCONFIG61
0x000F40F4
AA21
V20
Off / Off / Off
Off / Off / Off
7
1.8 V/3.3 V
VDDSHV3
Yes
LVCMOS
PU/PD
I
IO
I
0
0
IO
PWR
pad
J8
F7
VPP
VPP
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL
NUMBER
[1]
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
A1, A21,
A4, AA1,
AA12,
A1, A24,
AA15,
A25, AA11, AA21, AA9,
AB9, AD1, D11, D19,
AD12,
AD16,
AD25, AD9,
D4, E2,
F11, F13,
F15, F4,
AE1, AE12, F9, G16,
AE16,
AE24,
AE25, AE8,
B25, F13,
G13, G19,
H13, H16,
G6, G9,
H1, H13,
H6, J10,
J12, J14,
J16, J6,
K13, K3,
H18, H20, K6, K8, L1,
J13, J7,
K13, K15,
K19, K7,
L10, L12,
L14, L16,
L6, M11, VSS
VSS
PWR
L20, M10, M16, M18,
M12, M13, M6, M9,
M17, M18, N12, N14,
M7, M8,
N15, P10,
P13, P7,
R13, R15,
R18, R20,
T13, T14,
T16, T17,
T18, T8,
N6, P1,
P10, P13,
P15, P16,
P3, P6,
R16, R5,
R7, R8,
T10, T12,
T15, T3,
U19, U8,
V10, V11,
V13, V16,
V18, V9,
W7, Y2
T6, T7, T9,
U10, U13,
U5, U8,
V11, V14,
V19, W10,
W13, W7,
Y11, Y14,
Y3, Y4, Y6
WKUP_CLKOUT0
WKUP_CLKOUT0
MCU_GPIO0_23
WKUP_I2C0_SCL
MCU_GPIO0_19
WKUP_I2C0_SDA
MCU_GPIO0_20
0
7
0
7
0
7
O
PADCONFIG:
MCU_PADCONFIG33
0x04084084
A12
B9
B12
E9
Off / Off / Off
Off / Off / NA
Off / Off / NA
Off / SS / Off
On / SS / NA
On / SS / NA
0
7
7
1.8 V/3.3 V
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_MCU
VDDSHV_MCU
VDDSHV_MCU
Yes
Yes
Yes
LVCMOS
I2C OD FS
I2C OD FS
PU/PD
IO
pad
1
WKUP_I2C0_SCL
IOD
IOD
IOD
IOD
PADCONFIG:
MCU_PADCONFIG19
0x0408404C
pad
1
WKUP_I2C0_SDA
PADCONFIG:
MCU_PADCONFIG20
0x04084050
A9
A9
pad
C2
C1
A2
A3
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
I
1.8 V
1.8 V
VDDS_OSC0
VDDS_OSC0
LFXOSC
LFXOSC
O
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SPRSP58
54
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表6-1. Pin Attributes (ALW, AMC Packages) (continued)
BALL
STATE
DURING
RESET
(RX/TX/PULL)
[7]
BALL
STATE
AFTER
RESET
(RX/TX/PULL)
[8]
MUX
MODE
AFTER OPERATING
RESET VOLTAGE [10]
[9]
ALW
BALL
NUMBER
[1]
AMC
BALL NAME [2]
PADCONFIG Register [15]
PADCONFIG Address [16]
I/O
PULL
UP/DOWN
TYPE [14]
BALL
NUMBER
[1]
MUX
MODE [4]
TYPE DSIS
HYS
[12]
BUFFER
TYPE [13]
SIGNAL NAME [3]
POWER [11]
[5]
[6]
WKUP_UART0_CTSn
0
1
3
7
0
1
3
7
0
2
I
1
0
WKUP_UART0_CTSn
WKUP_TIMER_IO0
MCU_SPI1_CS0
IO
IO
IO
O
PADCONFIG:
MCU_PADCONFIG11
0x0408402C
C6
A4
A7
B4
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
MCU_GPIO0_11
pad
WKUP_UART0_RTSn
WKUP_TIMER_IO1
MCU_SPI1_CLK
WKUP_UART0_RTSn
IO
IO
IO
I
0
0
PADCONFIG:
MCU_PADCONFIG12
0x04084030
MCU_GPIO0_12
WKUP_UART0_RXD
MCU_SPI0_CS2
pad
1
WKUP_UART0_RXD
PADCONFIG:
IO
1
B4
C5
B5
C6
Off / Off / Off
Off / Off / Off
Off / Off / Off
Off / Off / Off
7
7
1.8 V/3.3 V
1.8 V/3.3 V
VDDSHV_CANUART
VDDSHV_CANUART
Yes
Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
MCU_PADCONFIG9
0x04084024
MCU_GPIO0_9
7
IO
pad
WKUP_UART0_TXD
WKUP_UART0_TXD
MCU_SPI1_CS2
0
2
O
PADCONFIG:
MCU_PADCONFIG10
0x04084028
IO
1
MCU_GPIO0_10
7
IO
pad
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English Data Sheet: SPRSP58
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6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
备注
Signal names and descriptions provided in each Signal Descriptions table, represent the pin
multiplexed signal function which is implemented at the pin and selected via PADCONFIG
registers. Device subsystems may provide secondary multiplexing of signal functions, which are
not described in these tables. For more information on secondary multiplexed signal functions,
see the respective peripheral chapter of the device TRM.
2. PIN TYPE: Signal direction and type:
• I = Input
• O = Output
• OD = Output, with open-drain output function
• IO = Input, Output, or simultaneously Input and Output
• IOD = Input, Output, or simultaneously Input and Output with open-drain output function
• IOZ = Input, Output, or simultaneously Input and Output with three-state output function
• OZ = Output with three-state output function
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor
3. DESCRIPTION: Description of the signal
4. BALL: Ball number(s) associated with signal
For more information on the IO cell configurations, see the Pad Configuration Registers section in Device
Configuration chapter of the device TRM.
6.3.1 CPSW3G
6.3.1.1 MAIN Domain
表6-2. CPSW3G0 RGMII1 Signal Descriptions
SIGNAL NAME [1]
RGMII1_RXC
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AD17
AE17
AMC PIN [4]
AA16
W14
I
I
RGMII Receive Clock
RGMII1_RX_CTL
RGMII1_TXC
RGMII1_TX_CTL
RGMII1_RD0
RGMII1_RD1
RGMII1_RD2
RGMII1_RD3
RGMII1_TD0
RGMII1_TD1
RGMII1_TD2
RGMII1_TD3
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
IO
O
I
AE19
W16
AD19
AB17
V15
W15
I
AC17
AB16
Y16
I
AA17
Y15
I
AA15
O
O
O
O
AE20
U14
AD20
AE18
AA19
Y17
AD18
AA18
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表6-3. CPSW3G0 RGMII2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AD23
AD22
AE21
AA19
AE23
AB20
AC21
AE22
Y18
AMC PIN [4]
V18
RGMII2_RXC
RGMII2_RX_CTL
RGMII2_TXC
RGMII2_TX_CTL
RGMII2_RD0
RGMII2_RD1
RGMII2_RD2
RGMII2_RD3
RGMII2_TD0
RGMII2_TD1
RGMII2_TD2
RGMII2_TD3
I
I
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
W19
Y18
IO
O
I
Y21
W18
Y20
I
I
Y19
I
W20
AA20
U15
O
O
O
O
AA18
AD21
AC20
W17
V16
表6-4. CPSW3G0 RMII1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
ALW PIN [4]
AE19
AMC PIN [4]
W16
RMII1_CRS_DV
RMII1_REF_CLK
RMII1_RX_ER
RMII1_TX_EN
RMII1_RXD0
RMII1_RXD1
RMII1_TXD0
I
I
AD17
AA16
W14
I
AE17
O
I
AD19
V15
RMII Receive Data 0
AB17
W15
I
RMII Receive Data 1
AC17
Y16
O
O
RMII Transmit Data 0
AE20
U14
RMII1_TXD1
RMII Transmit Data 1
AD20
AA19
表6-5. CPSW3G0 RMII2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
RMII Carrier Sense / Data Valid
RMII Reference Clock
RMII Receive Data Error
RMII Transmit Enable
ALW PIN [4]
AE21
AMC PIN [4]
Y18
RMII2_CRS_DV
RMII2_REF_CLK
RMII2_RX_ER
RMII2_TX_EN
RMII2_RXD0
RMII2_RXD1
RMII2_TXD0
I
I
AD23
AD22
AA19
V18
I
W19
O
I
Y21
RMII Receive Data 0
AE23
W18
I
RMII Receive Data 1
AB20
Y20
O
O
RMII Transmit Data 0
Y18
AA20
U15
RMII2_TXD1
RMII Transmit Data 1
AA18
6.3.2 CPTS
备注
Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals
are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input
signals are sent to the peripherals while output signals are sourced from the peripherals. For more
information, see the Time Sync and Compare Events section in the Time Sync chapter in the device
TRM.
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6.3.2.1 MAIN Domain
表6-6. CPTS Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
CP_GEMAC_CPTS0_RFT_CLK
I
CPTS Reference Clock Input
A18
C14
CPTS Time Stamp Counter Compare Output
from CPSW3G0 CPTS
CP_GEMAC_CPTS0_TS_COMP
CP_GEMAC_CPTS0_TS_SYNC
CP_GEMAC_CPTS0_HW1TSPUSH
CP_GEMAC_CPTS0_HW2TSPUSH
SYNC0_OUT
O
C13, D22
A14, C21
B13, B21
A22, B14
B16
C19, D13
B20, D12
B19, C12
A14, A19
E12
CPTS Time Stamp Counter Bit Output from
CPSW3G0 CPTS
O
I
CPTS Hardware Time Stamp Push Input to
Time Sync Router
CPTS Hardware Time Stamp Push Input to
Time Sync Router
I
CPTS Time Stamp Generator Bit 0 Output from
Time Sync Router
O
O
O
O
CPTS Time Stamp Generator Bit 1 Output from
Time Sync Router
SYNC1_OUT
A18
C14
CPTS Time Stamp Generator Bit 2 Output from
Time Sync Router
SYNC2_OUT
C15
B13
CPTS Time Stamp Generator Bit 3 Output from
Time Sync Router
SYNC3_OUT
E15
A15
6.3.3 CSI-2
6.3.3.1 MAIN Domain
表6-7. CSIRX0 Signal Descriptions
SIGNAL NAME [1]
CSI0_RXCLKN
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AD15
AMC PIN [4]
AA14
CSI-2 Differential Receive Clock Input
(negative)
I
I
CSI0_RXCLKP
CSI-2 Differential Receive Clock Input (positive)
AE15
AA13
CSI-2 D-PHY connection to external calibration
resistor
CSI0_RXRCALIB (1)
A
AA14
T11
CSI0_RXN0
CSI0_RXN1
CSI0_RXN2
CSI0_RXN3
CSI0_RXP0
CSI0_RXP1
CSI0_RXP2
CSI0_RXP3
I
I
I
I
I
I
I
I
CSI-2 Differential Receive Input (negative)
CSI-2 Differential Receive Input (negative)
CSI-2 Differential Receive Input (negative)
CSI-2 Differential Receive Input (negative)
CSI-2 Differential Receive Input (positive)
CSI-2 Differential Receive Input (positive)
CSI-2 Differential Receive Input (positive)
CSI-2 Differential Receive Input (positive)
AB14
AD14
AD13
AB12
AC15
AE14
AE13
AC13
Y13
V13
U12
W12
Y12
V12
U11
W11
(1) An external 499 Ω±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
6.3.4 DDRSS
6.3.4.1 MAIN Domain
表6-8. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
DDR0_ACT_n
PIN TYPE [2]
DESCRIPTION [3]
DDRSS Activation Command
DDRSS Alert
ALW PIN [4]
AMC PIN [4]
O
IO
O
N6
R3
M4
T1
M1
N1
J3
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDRSS Column Address Strobe
DDRSS Command and Address Parity
DDRSS Row Address Strobe
O
M2
K5
DDR0_RAS_n
O
M5
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www.ti.com.cn
表6-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
N3
J1
AMC PIN [4]
J2
DDR0_WE_n
DDR0_A0
O
O
DDRSS Write Enable
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Bank Address
DDRSS Bank Address
DDRSS Bank Group
DDRSS Bank Group
IO Pad Calibration Resistor
DDRSS Clock
F5
DDR0_A1
O
J2
G5
G4
H4
J5
DDR0_A2
O
K3
L5
DDR0_A3
O
DDR0_A4
O
K4
K1
R2
P2
P1
P4
R5
P5
R6
R1
M1
N1
T4
DDR0_A5
O
H5
P4
N2
P2
N4
N3
M3
P5
N5
L5
DDR0_A6
O
DDR0_A7
O
DDR0_A8
O
DDR0_A9
O
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0 (1)
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
O
O
O
O
O
O
L3
O
L4
O
N2
M2
L1
L2
A
K4
J1
O
O
DDRSS Negative Clock
DDRSS Clock Enable
DDRSS Clock Enable
DDRSS Chip Select
DDRSS Chip Select
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data
L2
K1
G3
H2
H3
G1
E3
R4
C2
E4
D3
E5
D2
F3
O
H2
J4
O
O
L6
O
K2
H5
W5
F4
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DDRSS Data
G5
F3
DDRSS Data
DDRSS Data
H6
E3
G2
F2
DDRSS Data
DDRSS Data
DDRSS Data
F1
DDRSS Data
F1
F2
DDRSS Data
U1
U3
U2
V5
W2
V6
Y1
W1
E1
R3
R2
T2
DDRSS Data
DDRSS Data
DDRSS Data
U2
U3
U4
T4
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
T5
DDRSS Data Strobe
D1
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
DDR0_DQS0_n
PIN TYPE [2]
DESCRIPTION [3]
DDRSS Complimentary Data Strobe
DDRSS Data Strobe
ALW PIN [4]
AMC PIN [4]
IO
IO
IO
O
E2
V1
V2
H1
J3
E1
T1
R1
J4
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDRSS Complimentary Data Strobe
DDRSS On-Die Termination for Chip Select 0
DDRSS On-Die Termination for Chip Select 1
DDRSS Reset
DDR0_ODT1
O
K2
G2
DDR0_RESET0_n
O
G1
(1) An external 240 Ω±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is
5.2mW. No external voltage should be applied to this pin.
6.3.5 DSS
6.3.5.1 MAIN Domain
表6-9. DSS0 Signal Descriptions
SIGNAL NAME [1]
VOUT0_DE
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
Y20
AMC PIN [4]
T17
O
I
Video Output Data Enable
VOUT0_EXTPCLKIN
VOUT0_HSYNC
VOUT0_PCLK
Video Output External Pixel Clock Input
Video Output Horizontal Sync
Video Output Pixel Clock Output
Video Output Vertical Sync
Video Output Data 0
V25
P17
W21
U17
T16
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AB24
AC24
AC25
U22
VOUT0_VSYNC
VOUT0_DATA0
VOUT0_DATA1
VOUT0_DATA2
VOUT0_DATA3
VOUT0_DATA4
VOUT0_DATA5
VOUT0_DATA6
VOUT0_DATA7
VOUT0_DATA8
VOUT0_DATA9
VOUT0_DATA10
VOUT0_DATA11
VOUT0_DATA12
VOUT0_DATA13
VOUT0_DATA14
VOUT0_DATA15
VOUT0_DATA16
VOUT0_DATA17
VOUT0_DATA18
VOUT0_DATA19
VOUT0_DATA20
VOUT0_DATA21
VOUT0_DATA22
VOUT0_DATA23
R21
P18
R18
R19
R20
T20
Video Output Data 1
V24
Video Output Data 2
W25
W24
Y25
Video Output Data 3
Video Output Data 4
Video Output Data 5
Y24
Video Output Data 6
Y23
T21
Video Output Data 7
AA25
V21
T19
Video Output Data 8
U21
R17
T18
Video Output Data 9
W21
V20
Video Output Data 10
Video Output Data 11
Video Output Data 12
Video Output Data 13
Video Output Data 14
Video Output Data 15
Video Output Data 16
Video Output Data 17
Video Output Data 18
Video Output Data 19
Video Output Data 20
Video Output Data 21
Video Output Data 22
Video Output Data 23
AA23
AB25
AA24
Y22
U20
U19
V21
U18
V20
N20
N21
M17
N18
N17
N19
P19
P20
AA21
R24
R25
T25
R21
T22
T24
U25
U24
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www.ti.com.cn
6.3.6 ECAP
6.3.6.1 MAIN Domain
表6-10. ECAP0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary
PWM (APWM) Ouput
ECAP0_IN_APWM_OUT
IO
A18, C13
C14, D13
表6-11. ECAP1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary
PWM (APWM) Ouput
B16, B18, B19, A13, A18, B18,
ECAP1_IN_APWM_OUT
IO
B21, D14
B19, E12
表6-12. ECAP2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Enhanced Capture (ECAP) Input or Auxiliary
PWM (APWM) Ouput
A16, A19, A22, A19, B17, C17,
ECAP2_IN_APWM_OUT
IO
B20, E14
D14, E11
6.3.7 Emulation and Debug
6.3.7.1 MAIN Domain
表6-13. Trace Signal Descriptions
SIGNAL NAME [1]
TRC_CLK
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
M25
N23
N24
N25
P24
P22
P21
R23
P25
L23
AMC PIN [4]
K19
L19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Clock
TRC_CTL
Trace Control
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
Trace Data 4
Trace Data 5
Trace Data 6
Trace Data 7
Trace Data 8
Trace Data 9
Trace Data 10
Trace Data 11
Trace Data 12
Trace Data 13
Trace Data 14
Trace Data 15
Trace Data 16
Trace Data 17
Trace Data 18
Trace Data 19
Trace Data 20
Trace Data 21
Trace Data 22
TRC_DATA0
TRC_DATA1
TRC_DATA2
TRC_DATA3
TRC_DATA4
TRC_DATA5
TRC_DATA6
TRC_DATA7
TRC_DATA8
TRC_DATA9
TRC_DATA10
TRC_DATA11
TRC_DATA12
TRC_DATA13
TRC_DATA14
TRC_DATA15
TRC_DATA16
TRC_DATA17
TRC_DATA18
TRC_DATA19
TRC_DATA20
TRC_DATA21
TRC_DATA22
L20
L21
M21
L17
L18
M20
M19
K20
K21
J17
L24
L25
M24
N20
U23
K25
M22
M21
L21
K17
K18
P21
J20
J19
J18
H17
H18
H19
P20
P19
N19
N17
K22
K24
U24
U25
T24
T22
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-13. Trace Signal Descriptions (continued)
SIGNAL NAME [1]
TRC_DATA23
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
O
Trace Data 23
R21
N18
6.3.7.2 MCU Domain
表6-14. JTAG Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
E12
AMC PIN [4]
D9
EMU0
EMU1
TCK
IO
Emulation Control 0
IO
Emulation Control 1
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Reset
C11
B10
I
A10
C10
TDI
I
A11
D10
TDO
OZ
D12
E10
TMS
I
I
B11
B11
TRSTn
B10
A11
6.3.8 EPWM
6.3.8.1 MAIN Domain
表6-15. EPWM Signal Descriptions
SIGNAL NAME [1]
EHRPWM_SOCA
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B16
AMC PIN [4]
E12
O
O
I
EHRPWM Start of Conversion A
EHRPWM_SOCB
EHRPWM Start of Conversion B
A16
D14
EHRPWM_TZn_IN0
EHRPWM_TZn_IN1
EHRPWM_TZn_IN2
EHRPWM_TZn_IN3
EHRPWM_TZn_IN4
EHRPWM_TZn_IN5
EHRPWM Trip Zone Input 0 (active low)
EHRPWM Trip Zone Input 1 (active low)
EHRPWM Trip Zone Input 2 (active low)
EHRPWM Trip Zone Input 3 (active low)
EHRPWM Trip Zone Input 4 (active low)
EHRPWM Trip Zone Input 5 (active low)
B14
A14
I
AA2
V2
I
AC1
W3
I
C15
B13
I
E15
A15
I
C13
D13
表6-16. EPWM0 Signal Descriptions
SIGNAL NAME [1]
EHRPWM0_A
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
IO
EHRPWM Output A
A13, AB2, E19 C11, D15, Y2
A20, C13, Y4 D13, D16, W1
EHRPWM0_B
EHRPWM Output B
Sync Input to EHRPWM module from an
external pin
EHRPWM0_SYNCI
EHRPWM0_SYNCO
I
AC2, B17
A17, AD2
A17, V4
A16, W4
Sync Input to EHRPWM module from an
external pin
O
表6-17. EPWM1 Signal Descriptions
SIGNAL NAME [1]
EHRPWM1_A
PIN TYPE [2]
DESCRIPTION [3]
EHRPWM Output A
EHRPWM Output B
ALW PIN [4]
AMC PIN [4]
IO
IO
A14, AA3, B18 A18, D12, W2
AA1, B13, E18 C12, D18, V1
EHRPWM1_B
表6-18. EPWM2 Signal Descriptions
SIGNAL NAME [1]
EHRPWM2_A
PIN TYPE [2]
DESCRIPTION [3]
EHRPWM Output A
EHRPWM Output B
ALW PIN [4]
AMC PIN [4]
IO
IO
AB1, B17, D14 A13, A17, Y1
A17, E14, Y3 A16, E11, V3
EHRPWM2_B
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6.3.9 EQEP
6.3.9.1 MAIN Domain
表6-19. EQEP0 Signal Descriptions
SIGNAL NAME [1]
EQEP0_A (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B19
AMC PIN [4]
B18
I
EQEP Quadrature Input A
EQEP0_B (1)
I
EQEP Quadrature Input B
EQEP Index
A19
B17
EQEP0_I (1)
IO
IO
E18
D18
EQEP0_S (1)
EQEP Strobe
B18
A18
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
表6-20. EQEP1 Signal Descriptions
SIGNAL NAME [1]
EQEP1_A (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B20
AMC PIN [4]
C17
I
EQEP Quadrature Input A
EQEP1_B (1)
EQEP1_I (1)
EQEP1_S (1)
I
EQEP Quadrature Input B
EQEP Index
D20
C16
IO
IO
A20
D16
EQEP Strobe
E19
D15
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
表6-21. EQEP2 Signal Descriptions
SIGNAL NAME [1]
EQEP2_A (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AC21, B16
A16, AE22
AMC PIN [4]
E12, Y19
I
I
EQEP Quadrature Input A
EQEP2_B (1)
EQEP Quadrature Input B
EQEP Index
D14, W20
AD21, C15,
V25
EQEP2_I (1)
IO
IO
B13, P17, W17
A15, J19, V16
AC20, E15,
M22
EQEP2_S (1)
EQEP Strobe
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10 GPIO
6.3.10.1 MAIN Domain
表6-22. GPIO0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
H24
AMC PIN [4]
G19
G18
H20
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
GPIO0_8
GPIO0_9
GPIO0_10
GPIO0_11
GPIO0_12
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
G25
J24
E25
F18
G24
F25
G17
F21
F24
F20
J23
G21
H21
J25
H25
G20
J21
J22
F23
F19
G21
F17
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表6-22. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
GPIO0_13 (1)
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
H21
E24
M25
N23
N24
N25
P24
P22
P21
R23
R24
R25
T25
AMC PIN [4]
E17
E18
K19
L19
IO
GPIO0_14 (1)
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO0_32
GPIO0_33
GPIO0_34
GPIO0_35
GPIO0_36
GPIO0_37
GPIO0_38
GPIO0_39
GPIO0_40
GPIO0_41
GPIO0_42
GPIO0_43 (1)
GPIO0_44 (1)
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
GPIO0_51
GPIO0_52
GPIO0_53
GPIO0_54
GPIO0_55
GPIO0_56
GPIO0_57
IO
IO
IO
IO
L20
IO
L21
IO
M21
L17
IO
IO
L18
IO
M20
N20
N21
M17
N18
N17
N19
P19
P20
M19
K20
K21
J17
IO
IO
IO
IO
R21
T22
IO
IO
T24
IO
U25
U24
P25
L23
IO
IO
IO
IO
L24
IO
L25
IO
M24
N20
U23
V25
K25
M22
M21
L21
K17
K18
P21
P17
J20
IO
IO
IO
IO
IO
J19
IO
J18
IO
H17
H18
H19
R21
P18
R18
R19
R20
T20
T21
T19
U21
R17
T18
U20
U19
IO
K22
K24
U22
V24
W25
W24
Y25
Y24
Y23
AA25
V21
W21
V20
AA23
AB25
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
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表6-22. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
AA24
Y22
AMC PIN [4]
V21
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPIO0_63
GPIO0_64
GPIO0_65 (1)
GPIO0_66 (1)
GPIO0_67 (1)
GPIO0_68 (1)
GPIO0_69 (1)
GPIO0_70 (1)
GPIO0_71 (1)
GPIO0_72 (1)
GPIO0_73
GPIO0_74
GPIO0_75
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
GPIO0_80
GPIO0_81
GPIO0_82
GPIO0_83
GPIO0_84
GPIO0_85
GPIO0_86
GPIO0_87
GPIO0_88
GPIO0_89
GPIO0_90
GPIO0_91
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
U18
AA21
AB24
Y20
V20
W21
T17
AC25
AC24
D24
T16
U17
E20
E23
E19
C25
D21
B24
B21
D25
E21
C24
C21
A23
D20
B23
C20
AD19
AE19
AE20
AD20
AE18
AD18
AE17
AD17
AB17
AC17
AB16
AA15
AB22
AD24
AA19
AE21
Y18
V15
W16
U14
AA19
Y17
AA18
W14
AA16
W15
Y16
AA17
Y15
U16
V17
Y21
Y18
AA20
U15
AA18
AD21
W17
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
表6-23. GPIO1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
AC20
AMC PIN [4]
V16
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
IO
IO
IO
IO
IO
IO
IO
AD22
W19
AD23
V18
AE23
W18
AB20
Y20
AC21
Y19
AE22
W20
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www.ti.com.cn
表6-23. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
B19
A19
B18
E18
B20
D20
E19
A20
A13
C13
A14
B13
B14
D14
E14
A15
B15
C15
E15
B16
A16
B17
A17
A18
D16
AC2
AD2
AC1
AB2
Y4
AMC PIN [4]
B18
B17
A18
D18
C17
C16
D15
D16
C11
D13
D12
C12
A14
A13
E11
B14
C13
B13
A15
E12
D14
A17
A16
C14
B16
V4
GPIO1_7
GPIO1_8
GPIO1_9
GPIO1_10
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
IO
IO
IO
IO
IO
IO
IO
IO
IO
GPIO1_16 (1)
IO
GPIO1_17
IO
GPIO1_18
IO
GPIO1_19
IO
GPIO1_20
IO
GPIO1_21
IO
GPIO1_22
IO
GPIO1_23
IO
GPIO1_24
IO
GPIO1_25
IO
GPIO1_26
IO
GPIO1_27
IO
GPIO1_28
IO
GPIO1_29
IO
GPIO1_30
IO
GPIO1_31 (1)
GPIO1_32 (1)
GPIO1_33 (1)
GPIO1_34 (1)
GPIO1_35 (1)
GPIO1_36 (1)
GPIO1_37 (1)
GPIO1_38 (1)
GPIO1_39 (1)
GPIO1_40 (1)
GPIO1_41 (1)
GPIO1_42 (1)
GPIO1_43 (1)
GPIO1_44 (1)
GPIO1_45 (1)
GPIO1_46 (1)
GPIO1_47 (1)
GPIO1_48 (1)
GPIO1_49 (2)
GPIO1_50
IOD
IO
IO
W4
IO
W3
IO
Y2
IO
W1
IO
AA3
AA1
AA2
AB1
Y3
W2
IO
V1
IO
V2
IO
Y1
IO
V3
IO
D22
C21
B21
A22
B22
A21
D17
C17
C20
C19
B20
B19
A19
A20
C18
C15
B15
D17
IO
IO
IO
IO
IO
IO
IO
IO
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www.ti.com.cn
表6-23. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
GPIO1_51
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
General Purpose Input/Output
F18
E16
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
(2) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.10.2 MCU Domain
表6-24. MCU_GPIO0 Signal Descriptions
SIGNAL NAME [1]
MCU_GPIO0_0 (1)
PIN TYPE [2]
DESCRIPTION [3]
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
ALW PIN [4]
E8
AMC PIN [4]
E7
IO
IO
MCU_GPIO0_1 (1)
MCU_GPIO0_2
MCU_GPIO0_3
MCU_GPIO0_4
MCU_GPIO0_5
MCU_GPIO0_6
MCU_GPIO0_7 (1)
MCU_GPIO0_8 (1)
MCU_GPIO0_9
MCU_GPIO0_10
MCU_GPIO0_11 (1)
MCU_GPIO0_12 (1)
MCU_GPIO0_13
MCU_GPIO0_14
MCU_GPIO0_15 (1)
MCU_GPIO0_16 (1)
MCU_GPIO0_17
MCU_GPIO0_18
MCU_GPIO0_19
MCU_GPIO0_20
MCU_GPIO0_21
MCU_GPIO0_22
MCU_GPIO0_23
B8
C8
IO
A7
B7
IO
D9
E8
IO
C9
D8
IO
B5
A8
IO
A5
B6
IO
A6
B8
IO
B6
D7
IO
B4
B5
IO
C5
C6
IO
C6
A7
IO
A4
B4
IO
D6
C5
IO
B3
C4
IO
E5
D5
IO
D4
D6
IOD
IOD
IOD
IOD
IO
A8
B9
D10
B9
A10
E9
A9
A9
B12
B7
A12
C7
IO
IO
A12
B12
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
6.3.11 GPMC
6.3.11.1 MAIN Domain
表6-25. GPMC0 Signal Descriptions
SIGNAL NAME [1]
GPMC0_ADVn_ALE
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
GPMC Address Valid (active low) or Address
Latch Enable
O
L23
K20
GPMC0_CLK
O
O
O
GPMC clock
P25
M22
P25
M19
J19
GPMC0_DIR
GPMC Data Bus Signal Direction Control
GPMC functional clock output
GPMC0_FCLK_MUX
M19
GPMC Output Enable (active low) or Read
Enable (active low)
GPMC0_OEn_REn
O
L24
K21
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表6-25. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
GPMC0_WEn
PIN TYPE [2]
DESCRIPTION [3]
GPMC Write Enable (active low)
GPMC Flash Write Protect (active low)
ALW PIN [4]
L25
AMC PIN [4]
J17
O
O
GPMC0_WPn
K25
J20
GPMC Address 0 Output. Only used to
effectively address 8-bit data non-multiplexed
memories
GPMC0_A0
OZ
U22
R21
GPMC address 1 Output in A/D non-multiplexed
mode and Address 17 in A/D multiplexed mode
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
V24
W25
W24
Y25
P18
R18
R19
R20
T20
T21
T19
U21
R17
GPMC address 2 Output in A/D non-multiplexed
mode and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed
mode and Address 19 in A/D multiplexed mode
GPMC address 4 Output in A/D non-multiplexed
mode and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed
mode and Address 21 in A/D multiplexed mode
Y24
GPMC address 6 Output in A/D non-multiplexed
mode and Address 22 in A/D multiplexed mode
Y23
GPMC address 7 Output in A/D non-multiplexed
mode and Address 23 in A/D multiplexed mode
AA25
V21
GPMC address 8 Output in A/D non-multiplexed
mode and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed
mode and Address 25 in A/D multiplexed mode
W21
GPMC address 10 Output in A/D non-
multiplexed mode and Address 26 in A/D
multiplexed mode
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
GPMC0_A17
GPMC0_A18
GPMC0_A19
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
V20
AA23
AB25
AA24
Y22
T18
U20
U19
V21
U18
V20
W21
T17
T16
U17
GPMC address 11 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 12 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 13 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 14 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 15 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
AA21
AB24
Y20
GPMC address 16 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 17 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC address 18 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
AC25
AC24
GPMC address 19 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
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表6-25. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
GPMC address 20 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC0_A20
GPMC0_A21
GPMC0_A22
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
OZ
K24
H19
GPMC address 21 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
OZ
OZ
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
V25
K25
M25
N23
N24
N25
P24
P22
P21
R23
R24
R25
T25
R21
T22
T24
U25
U24
P17
J20
GPMC address 22 Output in A/D non-
multiplexed mode and unused in A/D
multiplexed mode
GPMC Data 0 Input/Output in A/D non-
multiplexed mode and additionally Address 1
Output in A/D multiplexed mode
K19
L19
L20
L21
M21
L17
L18
M20
N20
N21
M17
N18
N17
N19
P19
P20
GPMC Data 1 Input/Output in A/D non-
multiplexed mode and additionally Address 2
Output in A/D multiplexed mode
GPMC Data 2 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 3 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 4 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 5 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 6 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 7 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 8 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 9 Input/Output in A/D non-
multiplexed mode and additionally Address 3
Output in A/D multiplexed mode
GPMC Data 10 Input/Output in A/D non-
multiplexed mode and additionally Address 11
Output in A/D multiplexed mode
GPMC Data 11 Input/Output in A/D non-
multiplexed mode and additionally Address 12
Output in A/D multiplexed mode
GPMC Data 12 Input/Output in A/D non-
multiplexed mode and additionally Address 13
Output in A/D multiplexed mode
GPMC Data 13 Input/Output in A/D non-
multiplexed mode and additionally Address 14
Output in A/D multiplexed mode
GPMC Data 14 Input/Output in A/D non-
multiplexed mode and additionally Address 15
Output in A/D multiplexed mode
GPMC Data 15 Input/Output in A/D non-
multiplexed mode and additionally Address 16
Output in A/D multiplexed mode
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表6-25. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
GPMC0_BE0n_CLE
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
GPMC Lower-Byte Enable (active low) or
Command Latch Enable
O
M24
K17
GPMC0_BE1n
GPMC0_CSn0
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
GPMC0_WAIT1
O
O
O
O
O
I
GPMC Upper-Byte Enable (active low)
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC External Indication of Wait
GPMC External Indication of Wait
N20
M21
L21
K22
K24
U23
V25
K18
J18
H17
H18
H19
P21
P17
I
6.3.12 I2C
6.3.12.1 MAIN Domain
表6-26. I2C0 Signal Descriptions
SIGNAL NAME [1]
I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B16
AMC PIN [4]
E12
IOD
IOD
I2C Clock
I2C Data
I2C0_SDA
A16
D14
表6-27. I2C1 Signal Descriptions
SIGNAL NAME [1]
I2C1_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B17
AMC PIN [4]
A17
IOD
IOD
I2C Clock
I2C Data
I2C1_SDA
A17
A16
表6-28. I2C2 Signal Descriptions
SIGNAL NAME [1]
I2C2_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
K22
AMC PIN [4]
H18
IOD
IOD
I2C Clock
I2C Data
I2C2_SDA
K24
H19
表6-29. I2C3 Signal Descriptions
SIGNAL NAME [1]
I2C3_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
A15, AB1
B15, Y3
AMC PIN [4]
B14, Y1
IOD
IOD
I2C Clock
I2C Data
I2C3_SDA
C13, V3
6.3.12.2 MCU Domain
表6-30. MCU_I2C0 Signal Descriptions
SIGNAL NAME [1]
MCU_I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IOD
I2C Clock
I2C Data
A8
B9
MCU_I2C0_SDA
IOD
D10
A10
6.3.12.3 WKUP Domain
表6-31. WKUP_I2C0 Signal Descriptions
SIGNAL NAME [1]
WKUP_I2C0_SCL
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IOD
I2C Clock
I2C Data
B9
A9
E9
A9
WKUP_I2C0_SDA
IOD
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6.3.13 MCAN
6.3.13.1 MAIN Domain
表6-32. MCAN0 Signal Descriptions
SIGNAL NAME [1]
MCAN0_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
ALW PIN [4]
E15
AMC PIN [4]
A15
I
MCAN0_TX
O
C15
B13
6.3.13.2 MCU Domain
表6-33. MCU_MCAN0 Signal Descriptions
SIGNAL NAME [1]
MCU_MCAN0_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
ALW PIN [4]
AMC PIN [4]
I
B3
D6
C4
C5
MCU_MCAN0_TX
O
表6-34. MCU_MCAN1 Signal Descriptions
SIGNAL NAME [1]
MCU_MCAN1_RX
PIN TYPE [2]
DESCRIPTION [3]
MCAN Receive Data
MCAN Transmit Data
ALW PIN [4]
AMC PIN [4]
I
D4
E5
D6
D5
MCU_MCAN1_TX
O
6.3.14 MCASP
6.3.14.1 MAIN Domain
表6-35. MCASP0 Signal Descriptions
SIGNAL NAME [1]
MCASP0_ACLKR
MCASP0_ACLKX
MCASP0_AFSR
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
A20
AMC PIN [4]
D16
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Receive Bit Clock
MCASP Transmit Bit Clock
B20
C17
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
E19
D15
MCASP0_AFSX
D20
C16
MCASP0_AXR0
E18
D18
MCASP0_AXR1
B18
A18
MCASP0_AXR2
A19
B17
MCASP0_AXR3
B19
B18
表6-36. MCASP1 Signal Descriptions
SIGNAL NAME [1]
MCASP1_ACLKR
MCASP1_ACLKX
MCASP1_AFSR
MCASP1_AFSX
MCASP1_AXR0
MCASP1_AXR1
MCASP1_AXR2
MCASP1_AXR3
MCASP1_AXR4
MCASP1_AXR5
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Receive Bit Clock
D25, E24, K24 E18, E21, H19
A23, H25, M24 D20, G20, K17
C24, H21, K22 C21, E17, H18
B23, J22, U23 C20, J21, P21
B24, J25, L25 B21, H21, J17
C25, J23, L24 D21, G21, K21
E23, H21, L23 E17, E19, K20
D24, E24, P25 E18, E20, M19
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
C24, K22
D25, K24
C21, H18
E21, H19
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表6-37. MCASP2 Signal Descriptions
SIGNAL NAME [1]
MCASP2_ACLKR
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
IO
IO
IO
MCASP Receive Bit Clock
AA18, U24
P20, U15
AC20, B15,
T24
MCASP2_ACLKX
MCASP2_AFSR
MCASP2_AFSX
MCASP Transmit Bit Clock
MCASP Receive Frame Sync
MCASP Transmit Frame Sync
C13, N19, V16
P19, Y20
AB20, U25
A15, AD21,
T22
B14, N17, W17
AC21, C15,
R24
MCASP2_AXR0
MCASP2_AXR1
IO
IO
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
B13, N20, Y19
A15, N21, V18
AD23, E15,
R25
MCASP2_AXR2
MCASP2_AXR3
MCASP2_AXR4
MCASP2_AXR5
MCASP2_AXR6
MCASP2_AXR7
MCASP2_AXR8
MCASP2_AXR9
MCASP2_AXR10
MCASP2_AXR11
MCASP2_AXR12
MCASP2_AXR13
MCASP2_AXR14
MCASP2_AXR15
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
MCASP Serial Data (Input/Output)
AE23, T25
AD22, R21
AA19, M25
AE21, N23
N24, Y18
AB20, N25
AA18, P24
P22
M17, W18
N18, W19
K19, Y21
L19, Y18
AA20, L20
L21, Y20
M21, U15
L17
P21
L18
R23
M20
N20
K18
M22
J19
M21
J18
L21
H17
6.3.15 MCSPI
6.3.15.1 MAIN Domain
表6-38. MCSPI0 Signal Descriptions
SIGNAL NAME [1]
SPI0_CLK
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
A14
AMC PIN [4]
D12
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI0_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
A13
C11
SPI0_CS1
C13
D13
SPI0_CS2
A15
B14
SPI0_CS3
B15
C13
SPI0_D0
B13
C12
SPI0_D1
SPI Data 1
B14
A14
表6-39. MCSPI1 Signal Descriptions
SIGNAL NAME [1]
SPI1_CLK
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AA3, J25
J23, Y4
AB1, H21
Y3
AMC PIN [4]
H21, W2
G21, W1
E17, Y1
V3
IO
IO
IO
IO
IO
IO
SPI Clock
SPI1_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI1_CS1
SPI1_CS2
SPI1_CS3
AA1
V1
SPI1_D0
AC2, H25
G20, V4
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www.ti.com.cn
表6-39. MCSPI1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
SPI1_D1
IO
SPI Data 1
AD2, J22
J21, W4
表6-40. MCSPI2 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
SPI2_CLK
SPI2_CS0
SPI2_CS1
SPI2_CS2
SPI2_CS3
SPI2_D0
IO
IO
IO
IO
IO
IO
IO
SPI Clock
A17, A20, AA2 A16, D16, V2
AA1, B16, E19 D15, E12, V1
AC2, B17, B20 A17, C17, V4
A16, B18, Y4 A18, D14, W1
A18, AD2, D20 C14, C16, W4
AC1, B19, D14 A13, B18, W3
A19, AB2, E14 B17, E11, Y2
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI2_D1
SPI Data 1
6.3.15.2 MCU Domain
表6-41. MCU_MCSPI0 Signal Descriptions
SIGNAL NAME [1]
MCU_SPI0_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CS3
MCU_SPI0_D0
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
IO
IO
IO
IO
IO
IO
SPI Clock
A7
E8
B7
E7
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
B8
C8
B4, D4
D6
B5, D6
C5
D9
E8
MCU_SPI0_D1
SPI Data 1
C9
D8
表6-42. MCU_MCSPI1 Signal Descriptions
SIGNAL NAME [1]
MCU_SPI1_CLK
MCU_SPI1_CS0
MCU_SPI1_CS1
MCU_SPI1_CS2
MCU_SPI1_CS3
MCU_SPI1_D0
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
IO
IO
IO
IO
IO
IO
SPI Clock
A4, D4
C6
B4, D6
A7
SPI Chip Select 0
SPI Chip Select 2
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
E5
D5
C5, D4
B3
C6, D6
C4
A6
B8
MCU_SPI1_D1
SPI Data 1
B6
D7
6.3.16 MDIO
6.3.16.1 MAIN Domain
表6-43. MDIO0 Signal Descriptions
SIGNAL NAME [1]
MDIO0_MDC
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AD24
AMC PIN [4]
V17
O
MDIO Clock
MDIO Data
MDIO0_MDIO
IO
AB22
U16
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6.3.17 MMC
6.3.17.1 MAIN Domain
表6-44. MMC0 Signal Descriptions
SIGNAL NAME [1]
MMC0_CLK (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AB1
AMC PIN [4]
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MMC/SD/SDIO Clock
MMC/SD/SDIO Command
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
Y1
V3
MMC0_CMD
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
Y3
AA2
V2
AA1
V1
AA3
W2
W1
Y2
Y4
AB2
AC1
AD2
AC2
W3
W4
V4
(1) For MMC0_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG135 register must remain in its default state
of 0x1 because of retiming purposes.
表6-45. MMC1 Signal Descriptions
SIGNAL NAME [1]
MMC1_CLK (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
B22
AMC PIN [4]
A20
IO
IO
I
MMC/SD/SDIO Clock
MMC1_CMD
MMC1_SDCD
MMC1_SDWP
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC/SD/SDIO Command
SD Card Detect
A21
C18
D17
C15
I
SD Write Protect
C17
B15
IO
IO
IO
IO
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
A22
A19
B21
B19
C21
B20
D22
C19
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG142 register must remain in its default state
of 0x1 because of retiming purposes.
表6-46. MMC2 Signal Descriptions
SIGNAL NAME [1]
MMC2_CLK (1)
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
D25
AMC PIN [4]
E21
IO
IO
I
MMC/SD/SDIO Clock
MMC2_CMD
MMC2_SDCD
MMC2_SDWP
MMC2_DAT0
MMC2_DAT1
MMC2_DAT2
MMC2_DAT3
MMC/SD/SDIO Command
SD Card Detect
C24
C21
A15, A23, B17 A17, B14, D20
A17, B15, B23 A16, C13, C20
I
SD Write Protect
IO
IO
IO
IO
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
B24
C25
E23
D24
B21
D21
E19
E20
(1) For MMC2_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG71 register must remain in its default state
of 0x1 because of retiming purposes.
6.3.18 OLDI
6.3.18.1 MAIN Domain
表6-47. OLDI0 Signal Descriptions
SIGNAL NAME [1]
OLDI0_A0N
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
IO
OLDI Differential Data (negative)
AA5
AA2
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www.ti.com.cn
表6-47. OLDI0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Data (negative)
OLDI Differential Data (positive)
OLDI Differential Clock (negative)
OLDI Differential Clock (positive)
OLDI Differential Clock (negative)
OLDI Differential Clock (positive)
ALW PIN [4]
Y6
AMC PIN [4]
AA3
V5
OLDI0_A0P
OLDI0_A1N
OLDI0_A1P
OLDI0_A2N
OLDI0_A2P
OLDI0_A3N
OLDI0_A3P
OLDI0_A4N
OLDI0_A4P
OLDI0_A5N
OLDI0_A5P
OLDI0_A6N
OLDI0_A6P
OLDI0_A7N
OLDI0_A7P
OLDI0_CLK0N
OLDI0_CLK0P
OLDI0_CLK1N
OLDI0_CLK1P
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AD3
AB4
Y8
V6
U7
AA8
AB6
AA7
AC6
AC5
AE5
AD6
AE6
AD7
AD8
AE7
AD4
AE3
AE4
AD5
U6
W6
W5
AA4
Y5
AA6
AA5
AA10
Y9
AA8
Y8
V7
V8
Y7
AA7
6.3.19 OSPI
6.3.19.1 MAIN Domain
表6-48. OSPI0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
OSPI0_CLK
O
I
OSPI Clock
H24
G19
OSPI Data Strobe (DQS) or Loopback Clock
Input
OSPI0_DQS
J24
H20
OSPI0_ECC_FAIL
OSPI0_LBCLKO
OSPI0_CSn0
OSPI0_CSn1
OSPI0_CSn2
OSPI0_CSn3
OSPI0_D0
I
OSPI ECC Status
OSPI Loopback Clock Output
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Chip Select 2 (active low)
OSPI Chip Select 3 (active low)
OSPI Data 0
E24
G25
F23
G21
H21
E24
E25
G24
F25
F24
J23
J25
H25
J22
E24
H21
E18
G18
F19
F17
E17
E18
F18
G17
F21
F20
G21
H21
G20
J21
IO
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
O
OSPI0_D1
OSPI Data 1
OSPI0_D2
OSPI Data 2
OSPI0_D3
OSPI Data 3
OSPI0_D4
OSPI Data 4
OSPI0_D5
OSPI Data 5
OSPI0_D6
OSPI Data 6
OSPI0_D7
OSPI Data 7
OSPI0_RESET_OUT0
OSPI0_RESET_OUT1
OSPI Reset
E18
E17
O
OSPI Reset
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
6.3.20 Power Supply
表6-49. Power Supply Signal Descriptions
SIGNAL NAME [1]
CAP_VDDS0 (1)
PIN TYPE [2]
DESCRIPTION [3]
External capacitor connection for IO group 0
External capacitor connection for IO group 1
External capacitor connection for IO group 2
External capacitor connection for IO group 3
External capacitor connection for IO group 4
External capacitor connection for IO group 5
External capacitor connection for IO group 6
External capacitor connection for IO CANUART
External capacitor connection for IO MCU
USB 1.8 V analog supply
ALW PIN [4]
H15
AMC PIN [4]
G12
L15
CAP
CAP_VDDS1 (1)
CAP
K18
CAP_VDDS2 (1)
CAP
W17
P19
R13
M15
N8
CAP_VDDS3 (1)
CAP
CAP_VDDS4 (1)
CAP
U7
CAP_VDDS5 (1)
CAP
H17
G15
J15
CAP_VDDS6 (1)
CAP
J19
CAP_VDDS_CANUART (1)
CAP_VDDS_MCU (1)
VDDA_1P8_USB
VDDA_1P8_CSIRX0
VDDA_1P8_OLDI0
VDDA_3P3_USB
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0
VDDA_MCU
CAP
G9
G8
CAP
H11
G11
R11
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
Y11
CSIRX analog supply high
W14
W10, W9
Y13
R12
P9, R9
R10
P12
OLDI analog supply
USB 3.3 V analog supply
CSIRX analog supply low
W13
W12
USB Core Supply
P11
DDR Deskew PLL analog supply
POR and MCU PLL analog supply
L9
L11
H10
MAIN PLL, DDR PLL, DSS PLL0, and DSS
PLL1 analog supply
VDDA_PLL0
PWR
U11
N10
VDDA_PLL1
VDDA_PLL2
VDDA_TEMP0
VDDA_TEMP1
PWR
PWR
PWR
PWR
PER0 PLL and PER1 PLL analog supply
ARM0 PLL and SMS PLL analog supply
TEMP0 analog supply
U15
L14
T9
P14
K12
M7
TEMP1 analog supply
G16
F16
J12, K16, N12,
N14, P16,
VDDR_CORE
PWR
Core Supply
H11, M10, M13
R12, T10, U14
VDDSHV0
VDDSHV1
VDDSHV2
PWR
PWR
PWR
IO supply for IO group 0
IO supply for IO group 1
IO supply for IO group 2
F15, G14
L18, M19
W16, W19
F12, G13
K15, K16
R14, R15
N18, P18, T19,
U18
VDDSHV3
PWR
IO supply for IO group 3
N15, N16
VDDSHV4
PWR
PWR
PWR
PWR
PWR
IO supply for IO group 4
IO supply for IO group 5
IO supply for IO group 6
IO supply for IO CANUART
IO supply for IO MCU
T7
G17
N7, P7
F14, G14
H15, H16
G7, H7
VDDSHV5
VDDSHV6
J18
VDDSHV_CANUART
VDDSHV_MCU
H9
F11, G12
F10, G10
C1, J8, K7, K9,
L8, U1
VDDS_DDR
PWR
DDR PHY IO supply
K9, L8, P9, R8
VDDS_DDR_C
VDDS_OSC0
PWR
PWR
PWR
DDR clock IO supply
MCU_OSC0 supply
CANUART Core Supply
M9
G7
F8
L7
J7
VDD_CANUART
H8
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-49. Power Supply Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
H8, J11, J14,
K17, L12, L15,
M16, N11,
N13, N8, P17,
R11, R14,
H12, H14, J11,
J13, J9, K10,
K14, L11, L13,
M12, M14, M8,
N11, N13, N9,
P8
VDD_CORE
VPP
PWR
Core supply
U12, V15, V17,
V8
PWR
eFuse ROM programming supply
J8
F7
A1, A21, A4,
AA1, AA12,
A1, A24, A25, AA15, AA21,
AA11, AB9,
AD1, AD12,
AA9, D11,
D19, D4, E2,
AD16, AD25, F11, F13, F15,
AD9, AE1,
AE12, AE16,
F4, F9, G16,
G6, G9, H1,
AE24, AE25, H13, H6, J10,
AE8, B25, F13, J12, J14, J16,
G13, G19,
H13, H16,
J6, K13, K3,
K6, K8, L1,
H18, H20, J13, L10, L12, L14,
J7, K13, K15, L16, L6, M11,
K19, K7, L20, M16, M18, M6,
VSS
PWR
Ground
M10, M12,
M13, M17,
M9, N12, N14,
N6, P1, P10,
M18, M7, M8, P13, P15, P16,
N15, P10, P13, P3, P6, R16,
P7, R13, R15,
R5, R7, R8,
R18, R20, T13, T10, T12, T15,
T14, T16, T17, T3, T6, T7, T9,
T18, T8, U19, U10, U13, U5,
U8, V10, V11, U8, V11, V14,
V13, V16, V18,
V19, W10,
V9, W7, Y2 W13, W7, Y11,
Y14, Y3, Y4,
Y6
(1) This pin must always be connected via a 1-μF capacitor to VSS.
6.3.21 PRUSS
备注
The PRUSS contains a second layer of peripheral signal multiplexing to enable additional functionality
on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRUSS
chapter in the device TRM
6.3.21.1 MAIN Domain
表6-50. PRUSS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
PRUSS Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
AC24, AD21, C13, D18, J19,
PR0_ECAP0_IN_APWM_OUT
IO
B15, E18, M22
A13, AD23
U17, W17
C11, V18
B14, V16
PR0_ECAP0_SYNC_IN
I
PRUSS ECAP Sync Input
PRUSS ECAP Sync Output
PR0_ECAP0_SYNC_OUT
O
A15, AC20
PRUSS Industrial Ethernet Digital I/O Data
Input/Output
PR0_IEP0_EDIO_DATA_IN_OUT28
PR0_IEP0_EDIO_DATA_IN_OUT29
IO
IO
B19
A19
B18
B17
PRUSS Industrial Ethernet Digital I/O Data
Input/Output
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-50. PRUSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
PRUSS Industrial Ethernet Digital I/O Data
Input/Output
PR0_IEP0_EDIO_DATA_IN_OUT30
IO
B16
E12
PRUSS Industrial Ethernet Digital I/O Data
Input/Output
PR0_IEP0_EDIO_DATA_IN_OUT31
PR0_PRU0_GPI0
IO
I
A16
D14
AD22, M25, K19, N17, T18,
T22, V20, Y4
PRUSS PRU Data Input
PRUSS PRU Data Input
W1, W19
AA23, AA3,
AD23, N23,
T24
L19, N19, U20,
V18, W2
PR0_PRU0_GPI1
PR0_PRU0_GPI2
I
I
AA1, AB25,
AE23, N24,
U25
L20, P19, U19,
V1, W18
PRUSS PRU Data Input
AA2, AA24,
AB20, N25,
U24
L21, P20, V2,
V21, Y20
PR0_PRU0_GPI3
PR0_PRU0_GPI4
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
AC21, P24,
Y22, Y3
M21, U18, V3,
Y19
PR0_PRU0_GPI5
PR0_PRU0_GPI6
PR0_PRU0_GPI7
PR0_PRU0_GPI8
PR0_PRU0_GPI9
PR0_PRU0_GPI10
PR0_PRU0_GPI11
PR0_PRU0_GPI12
PR0_PRU0_GPI13
PR0_PRU0_GPI14
PR0_PRU0_GPI15
I
I
I
I
I
I
I
I
I
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
AA21, P22
AB24, P21
R23, Y20
P25, U22
L23, V24
L24, W25
L25, W24
M24, Y25
N20, Y24
U23, Y23
AA25, K25
L17, V20
L18, W21
M20, T17
M19, R21
K20, P18
K21, R18
J17, R19
K17, R20
K18, T20
P21, T21
J20, T19
AE22, M22,
W21
PR0_PRU0_GPI16
I
PRUSS PRU Data Input
J19, R17, W20
PR0_PRU0_GPI17
PR0_PRU0_GPI18
PR0_PRU0_GPI19
I
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
M21, V21
AC25, L21
AC24, K22
J18, U21
H17, T16
H18, U17
AD22, M25, K19, N17, T18,
PR0_PRU0_GPO0
PR0_PRU0_GPO1
IO
IO
PRUSS PRU Data Output
PRUSS PRU Data Output
T22, V20, Y4
W1, W19
AA23, AA3,
AD23, N23,
T24
L19, N19, U20,
V18, W2
AA1, AB25,
AE23, N24,
U25
L20, P19, U19,
V1, W18
PR0_PRU0_GPO2
IO
PRUSS PRU Data Output
AA2, AA24,
AB20, N25,
U24
L21, P20, V2,
V21, Y20
PR0_PRU0_GPO3
PR0_PRU0_GPO4
IO
IO
PRUSS PRU Data Output
PRUSS PRU Data Output
AC21, P24,
Y22, Y3
M21, U18, V3,
Y19
PR0_PRU0_GPO5
PR0_PRU0_GPO6
PR0_PRU0_GPO7
PR0_PRU0_GPO8
PR0_PRU0_GPO9
IO
IO
IO
IO
IO
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
AA21, P22
AB24, P21
R23, Y20
P25, U22
L23, V24
L17, V20
L18, W21
M20, T17
M19, R21
K20, P18
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-50. PRUSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
L24, W25
L25, W24
M24, Y25
N20, Y24
U23, Y23
AA25, K25
AMC PIN [4]
K21, R18
J17, R19
K17, R20
K18, T20
P21, T21
J20, T19
PR0_PRU0_GPO10
PR0_PRU0_GPO11
PR0_PRU0_GPO12
PR0_PRU0_GPO13
PR0_PRU0_GPO14
PR0_PRU0_GPO15
IO
IO
IO
IO
IO
IO
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
AE22, M22,
W21
PR0_PRU0_GPO16
IO
PRUSS PRU Data Output
J19, R17, W20
PR0_PRU0_GPO17
PR0_PRU0_GPO18
PR0_PRU0_GPO19
PR0_UART0_CTSn
PR0_UART0_RTSn
IO
IO
IO
I
PRUSS PRU Data Output
M21, V21
AC25, L21
AC24, K22
AC20, AD17
AB16, AE23
J18, U21
H17, T16
PRUSS PRU Data Output
PRUSS PRU Data Output
H18, U17
AA16, V16
AA17, W18
PRUSS UART Clear to Send (active low)
PRUSS UART Request to Send (active low)
O
AC21, AE18, A18, B13, B18,
PR0_UART0_RXD
PR0_UART0_TXD
I
PRUSS UART Receive Data
PRUSS UART Transmit Data
B18, B19, C15
Y17, Y19
A19, AD18,
AE22, E15,
E18
A15, AA18,
B17, D18, W20
O
表6-51. PRUSS1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
AA19, AC2,
R24, U22
N20, R21, V4,
Y21
PR0_PRU1_GPI0
PR0_PRU1_GPI1
PR0_PRU1_GPI2
PR0_PRU1_GPI3
PR0_PRU1_GPI4
I
PRUSS PRU Data Input
AD2, AE21, N21, P18, W4,
R25, V24
I
I
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
Y18
AC1, T25,
W25, Y18
AA20, M17,
R18, W3
AA18, AB2,
R21, W24
N18, R19,
U15, Y2
AB1, AD21,
Y25
R20, W17, Y1
PR0_PRU1_GPI5
PR0_PRU1_GPI6
PR0_PRU1_GPI7
PR0_PRU1_GPI8
PR0_PRU1_GPI9
PR0_PRU1_GPI10
PR0_PRU1_GPI11
PR0_PRU1_GPI12
PR0_PRU1_GPI13
PR0_PRU1_GPI14
PR0_PRU1_GPI15
I
I
I
I
I
I
I
I
I
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
Y24
T20
Y23
T21
AA25
T19
M25, W21
N23, V20
AA23, N24
AB25, N25
AA24, P24
P22, Y22
AA21, P21
AB24, R23
K19, R17
L19, T18
L20, U20
L21, U19
M21, V21
L17, U18
L18, V20
M20, W21
AC20, L21,
V21
PR0_PRU1_GPI16
I
PRUSS PRU Data Input
H17, U21, V16
PR0_PRU1_GPI17
PR0_PRU1_GPI18
PR0_PRU1_GPI19
I
I
I
PRUSS PRU Data Input
PRUSS PRU Data Input
PRUSS PRU Data Input
Y20
T17
T16
U17
AC25
AC24
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AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-51. PRUSS1 Signal Descriptions (continued)
SIGNAL NAME [1]
PR0_PRU1_GPO0
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
AA19, AC2,
R24, U22
N20, R21, V4,
Y21
O
PRUSS PRU Data Output
AD2, AE21, N21, P18, W4,
PR0_PRU1_GPO1
PR0_PRU1_GPO2
PR0_PRU1_GPO3
PR0_PRU1_GPO4
O
O
O
O
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
R25, V24
Y18
AC1, T25,
W25, Y18
AA20, M17,
R18, W3
AA18, AB2,
R21, W24
N18, R19,
U15, Y2
AB1, AD21,
Y25
R20, W17, Y1
PR0_PRU1_GPO5
PR0_PRU1_GPO6
PR0_PRU1_GPO7
PR0_PRU1_GPO8
PR0_PRU1_GPO9
PR0_PRU1_GPO10
PR0_PRU1_GPO11
PR0_PRU1_GPO12
PR0_PRU1_GPO13
PR0_PRU1_GPO14
PR0_PRU1_GPO15
O
O
O
O
O
O
O
O
O
O
O
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
Y24
T20
Y23
T21
AA25
T19
M25, W21
N23, V20
AA23, N24
AB25, N25
AA24, P24
P22, Y22
AA21, P21
AB24, R23
K19, R17
L19, T18
L20, U20
L21, U19
M21, V21
L17, U18
L18, V20
M20, W21
AC20, L21,
V21
PR0_PRU1_GPO16
O
PRUSS PRU Data Output
H17, U21, V16
PR0_PRU1_GPO17
PR0_PRU1_GPO18
PR0_PRU1_GPO19
O
O
O
PRUSS PRU Data Output
PRUSS PRU Data Output
PRUSS PRU Data Output
Y20
T17
T16
U17
AC25
AC24
6.3.22 Reserved
表6-52. Reserved Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
Reserved, must be left unconnected
ALW PIN [4]
AMC PIN [4]
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
N/A
B1
A2
B3
C3
E6
N/A
N/A
F6
N/A
AE2
T2
F8
N/A
R6
T13
T14
M4
M5
N/A
U4
N/A
AA12
Y15
E7
N/A
N/A
6.3.23 System and Miscellaneous
6.3.23.1 Boot Mode Configuration
6.3.23.1.1 MAIN Domain
表6-53. Sysboot Signal Descriptions
SIGNAL NAME [1]
BOOTMODE00
BOOTMODE01
PIN TYPE [2]
DESCRIPTION [3]
Bootmode pin 0
Bootmode pin 1
ALW PIN [4]
M25
AMC PIN [4]
K19
I
I
N23
L19
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English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-53. Sysboot Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
N24
AMC PIN [4]
L20
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
BOOTMODE08
BOOTMODE09
BOOTMODE10
BOOTMODE11
BOOTMODE12
BOOTMODE13
BOOTMODE14
BOOTMODE15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode pin 2
Bootmode pin 3
Bootmode pin 4
Bootmode pin 5
Bootmode pin 6
Bootmode pin 7
Bootmode pin 8
Bootmode pin 9
Bootmode pin 10
Bootmode pin 11
Bootmode pin 12
Bootmode pin 13
Bootmode pin 14
Bootmode pin 15
N25
L21
P24
M21
L17
P22
P21
L18
R23
M20
N20
R24
R25
N21
T25
M17
N18
R21
T22
N17
T24
N19
U25
P19
U24
P20
6.3.23.2 Clock
6.3.23.2.1 MCU Domain
表6-54. MCU Clock Signal Descriptions
SIGNAL NAME [1]
MCU_OSC0_XI
PIN TYPE [2]
DESCRIPTION [3]
High frequency oscillator input
High frequency oscillator output
ALW PIN [4]
AMC PIN [4]
I
B2
A3
A5
A6
MCU_OSC0_XO
O
6.3.23.2.2 WKUP Domain
表6-55. WKUP Clock Signal Descriptions
SIGNAL NAME [1]
WKUP_LFOSC0_XI
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
I
Low frequency (32.768 KHz) oscillator input
Low frequency (32.768 KHz) oscillator output
C2
C1
A2
A3
WKUP_LFOSC0_XO
O
6.3.23.3 System
6.3.23.3.1 MAIN Domain
表6-56. System Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
External clock input to McASP or output from
McASP
A15, AE22,
E18
AUDIO_EXT_REFCLK0
IO
IO
B14, D18, W20
External clock input to McASP or output from
McASP
AUDIO_EXT_REFCLK1
CLKOUT0
B15, D20, K25 C13, C16, J20
RMII Clock Output (50 MHz). This pin is used
for clock source to the external RMII PHY and
must also be routed back to the respective
RMII[x]_REF_CLK pin for proper device
operation.
O
A18
C14
EXTINTn
I
I
External Interrupt
D16
A18
B16
C14
EXT_REFCLK1
External clock input to Main Domain
Main Domain Observation clock output for test
and debug purposes only
OBSCLK0
O
B16, T25
E12, M17
PORz_OUT
O
O
Main Domain POR status output
E21
F22
E13
E14
RESETSTATz
Main Domain warm reset status output
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表6-56. System Signal Descriptions (continued)
SIGNAL NAME [1]
RESET_REQz
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
I
Main Domain external warm reset request input
F20
E15
Main Domain system clock output (divided by 4)
for test and debug purposes only
SYSCLKOUT0
O
A18
C14
6.3.23.3.2 MCU Domain
表6-57. MCU System Signal Descriptions
SIGNAL NAME [1]
MCU_ERRORn
PIN TYPE [2]
DESCRIPTION [3]
Error signal output from MCU Domain ESM
External input to MCU Domain
ALW PIN [4]
D1
AMC PIN [4]
B1
IO
I
MCU_EXT_REFCLK0
B8, E5
C8, D5
MCU Domain Observation clock output for test
and debug purposes only
MCU_OBSCLK0
O
B8
C8
MCU_PORz
I
O
I
MCU Domain cold reset
D2
B12
E11
B2
A12
C9
MCU_RESETSTATz
MCU_RESETz
MCU Domain warm reset status output
MCU Domain warm reset
MCU Domain system clock output (divided by 4)
for test and debug purposes only
MCU_SYSCLKOUT0
O
B8
C8
6.3.23.3.3 WKUP Domain
表6-58. WKUP System Signal Descriptions
SIGNAL NAME [1]
PMIC_LPM_EN0
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Dual-function PMIC control output, Low Power
Mode (active low) or PMIC Enable (active high)
O
O
B7
C7
WKUP_CLKOUT0
WKUP Domain CLKOUT0 output
A12
B12
6.3.23.4 VMON
表6-59. VMON Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Voltage monitor input for 1.8 V SoC power
supply
VMON_1P8_SOC
A
A
G10
H9
Voltage monitor input for 3.3 V SoC power
supply
VMON_3P3_SOC
VMON_VSYS
K10
H10
K11
F6
Voltage monitor input, fixed 0.45 V (+/-3%)
threshold. Use with external precision voltage
divider to monitor a higher voltage rail such as
the PMIC input supply.
A
6.3.24 TIMER
6.3.24.1 MAIN Domain
表6-60. TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Timer Inputs and Outputs (not tied to single
timer instance)
TIMER_IO0
IO
IO
IO
IO
AA3, B17, D22 A17, C19, W2
Timer Inputs and Outputs (not tied to single
timer instance)
TIMER_IO1
TIMER_IO2
TIMER_IO3
A17, C21
B21, C15
A22, E15
A16, B20
B13, B19
A15, A19
Timer Inputs and Outputs (not tied to single
timer instance)
Timer Inputs and Outputs (not tied to single
timer instance)
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表6-60. TIMER Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Timer Inputs and Outputs (not tied to single
timer instance)
TIMER_IO4
TIMER_IO5
TIMER_IO6
TIMER_IO7
IO
A18, AB1, B22 A20, C14, Y1
A16, A21, Y3 C18, D14, V3
Timer Inputs and Outputs (not tied to single
timer instance)
IO
IO
IO
Timer Inputs and Outputs (not tied to single
timer instance)
A15, D17
B15, C17
B14, C15
B15, C13
Timer Inputs and Outputs (not tied to single
timer instance)
6.3.24.2 MCU Domain
表6-61. MCU_TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Timer Inputs and Outputs (not tied to single
timer instance)
MCU_TIMER_IO0
IO
A6, B3
B8, C4
Timer Inputs and Outputs (not tied to single
timer instance)
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
IO
IO
IO
B6, B8
E5
C8, D7
D5
Timer Inputs and Outputs (not tied to single
timer instance)
Timer Inputs and Outputs (not tied to single
timer instance)
D4
D6
6.3.24.3 WKUP Domain
表6-62. WKUP_TIMER Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
Timer Inputs and Outputs (not tied to single
timer instance)
WKUP_TIMER_IO0
IO
C6, D6
A7, C5
Timer Inputs and Outputs (not tied to single
timer instance)
WKUP_TIMER_IO1
IO
A4, E8
B4, E7
6.3.25 UART
6.3.25.1 MAIN Domain
表6-63. UART0 Signal Descriptions
SIGNAL NAME [1]
UART0_CTSn
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALW PIN [4]
A15
AMC PIN [4]
B14
I
UART0_RTSn
O
I
B15
C13
UART0_RXD
D14
A13
UART0_TXD
O
UART Transmit Data
E14
E11
表6-64. UART1 Signal Descriptions
SIGNAL NAME [1]
UART1_CTSn
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Clear to Send (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
ALW PIN [4]
B19
AMC PIN [4]
B18
I
I
UART1_DCDn
UART1_DSRn
UART1_DTRn
B16
E12
I
A16
D14
O
I
C15
B13
UART1_RIn
E15
A15
UART1_RTSn
O
I
UART Request to Send (active low)
UART Receive Data
A19
B17
UART1_RXD
B17, E19
A17, D15
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表6-64. UART1 Signal Descriptions (continued)
SIGNAL NAME [1]
UART1_TXD
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
O
UART Transmit Data
A17, A20
A16, D16
表6-65. UART2 Signal Descriptions
SIGNAL NAME [1]
UART2_CTSn
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
A22, AB2,
AC24, U25
A19, P19, U17,
Y2
I
UART Clear to Send (active low)
AC1, AC25, B19, P20, T16,
UART2_RTSn
UART2_RXD
UART2_TXD
O
I
UART Request to Send (active low)
UART Receive Data
B21, U24
W3
A15, AC2,
B14, C19,
D22, R24, U22 N20, R21, V4
AD2, B15, B20, C13,
C21, R25, V24 N21, P18, W4
O
UART Transmit Data
表6-66. UART3 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
UART3_CTSn
UART3_RTSn
I
UART Clear to Send (active low)
AA2, C17, Y20 B15, T17, V2
AA1, AB24,
C15, V1, W21
D17
O
UART Request to Send (active low)
UART Receive Data
B22, T25,
W25, Y4
A20, M17,
R18, W1
UART3_RXD
UART3_TXD
I
A21, AA3,
R21, W24
C18, N18,
R19, W2
O
UART Transmit Data
表6-67. UART4 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
ALW PIN [4]
AA21
AMC PIN [4]
V20
UART4_CTSn
UART4_RTSn
I
O
Y22
U18
A23, K22, T22,
Y25
D20, H18,
N17, R20
UART4_RXD
UART4_TXD
I
UART Receive Data
UART Transmit Data
B23, K24, T24,
Y24
C20, H19,
N19, T20
O
表6-68. UART5 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
ALW PIN [4]
AA24, J24
AB25, G25
AMC PIN [4]
H20, V21
UART5_CTSn
UART5_RTSn
I
O
G18, U19
C15, D24,
H21, U25, Y23
B13, E17, E20,
P19, T21
UART5_RXD
UART5_TXD
I
UART Receive Data
UART Transmit Data
AA25, E15, A15, E18, E19,
E23, E24, U24
O
P20, T19
表6-69. UART6 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
ALW PIN [4]
AA23, J22
H25, V20
AMC PIN [4]
J21, U20
UART6_CTSn
UART6_RTSn
I
O
G20, T18
B19, D17,
D25, J23, V21,
V25
B18, C15, E21,
G21, P17, U21
UART6_RXD
I
UART Receive Data
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表6-69. UART6 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALW PIN [4]
AMC PIN [4]
A19, C17,
C24, J25, K25,
W21
B15, B17, C21,
H21, J20, R17
UART6_TXD
O
UART Transmit Data
6.3.25.2 MCU Domain
表6-70. MCU_UART0 Signal Descriptions
SIGNAL NAME [1]
MCU_UART0_CTSn
MCU_UART0_RTSn
MCU_UART0_RXD
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALW PIN [4]
AMC PIN [4]
I
A6
B6
B5
A5
B8
D7
A8
B6
O
I
MCU_UART0_TXD
O
UART Transmit Data
6.3.25.3 WKUP Domain
表6-71. WKUP_UART0 Signal Descriptions
SIGNAL NAME [1]
WKUP_UART0_CTSn
WKUP_UART0_RTSn
WKUP_UART0_RXD
WKUP_UART0_TXD
PIN TYPE [2]
DESCRIPTION [3]
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALW PIN [4]
AMC PIN [4]
I
C6
A4
B4
C5
A7
B4
B5
C6
O
I
O
UART Transmit Data
6.3.26 USB
6.3.26.1 MAIN Domain
表6-72. USB0 Signal Descriptions
SIGNAL NAME [1]
USB0_DM
PIN TYPE [2]
DESCRIPTION [3]
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
ALW PIN [4]
AE11
AMC PIN [4]
AA11
Y10
IO
IO
O
A
USB0_DP
AD11
USB0_DRVVBUS
USB0_RCALIB (1)
USB0_VBUS (2)
C20
D17
AE10
T8
A
AC11
V10
(1) An external 499 Ω±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.2.3, USB VBUS
Design Guidelines.
表6-73. USB1 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
ALW PIN [4]
AD10
AE9
AMC PIN [4]
USB1_DM
USB1_DP
IO
IO
O
A
W8
W9
E16
V9
USB1_DRVVBUS
USB1_RCALIB (1)
USB1_VBUS (2)
F18
AC9
A
AB10
U9
(1) An external 499 Ω±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.2.3, USB VBUS
Design Guidelines.
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6.4 Pin Connectivity Requirements
This section describes connectivity requirements for package balls that have specific connectivity requirements
and unused package balls.
备注
All power balls must be supplied with the voltages specified in 节 7.5, Recommended Operating
Conditions, unless otherwise specified .
备注
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be
connected to these device ball numbers.
表6-74. Connectivity Requirements
ALW
BALL
AMC
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
NUMBER
Each of these balls must be connected to VSS through separate
external pull resistors to ensure the inputs associated with these
balls are held to a valid logic low level if a PCB signal trace is
connected and not actively driven by an attached device. The
internal pull-down can be used to hold a valid logic low level if no
PCB signal trace is connected to the ball.
D1
B10
B1
A11
MCU_ERRORn
TRSTn
E12
C11
E11
F20
A10
A11
B11
D9
B10
C9
E15
C10
D10
B11
EMU0
EMU1
MCU_RESETz
RESET_REQz
TCK
Each of these balls must be connected to the corresponding power
supply(1) through separate external pull resistors to ensure the inputs
associated with these balls are held to a valid logic high level if a
PCB signal trace is connected and not actively driven by an attached
device. The internal pull-up can be used to hold a valid logic high
level if no PCB signal trace is connected to the ball.
TDI
TMS
A8
D10
B9
B9
A10
E9
MCU_I2C0_SCL
MCU_I2C0_SDA
WKUP_I2C0_SCL
WKUP_I2C0_SDA
Each of these balls must be connected to the corresponding power
supply(1) through separate external pull resistors to ensure the inputs
associated with these balls are held to a valid logic high level.
A9
A9
M25
N23
N24
N25
P24
P22
P21
R23
R24
R25
T25
R21
T22
T24
U25
U24
K19
L19
L20
L21
M21
L17
L18
M20
N20
N21
M17
N18
N17
N19
P19
P20
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
Each of these balls must be connected to the corresponding power
supply(1) or VSS through separate external pull resistors to ensure
the inputs associated with these balls are held to a valid logic high or
low level as appropriate to select the desired device boot mode.
K9
L8
P9
R8
-
K9
L8
J8
K7
C1
U1
L7
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR_C
If DDRSS is not used, each of these balls must be connected directly
to VSS.
-
M9
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表6-74. Connectivity Requirements (continued)
ALW
BALL
AMC
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
NUMBER
N6
R3
M4
T1
M5
N3
J1
J2
K3
L5
K4
K1
R2
P2
P1
P4
R5
P5
R6
R1
M1
N1
T4
N2
M2
L1
M1
N1
J3
M2
K5
J2
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
F5
G5
G4
H4
J5
H5
P4
N2
P2
N4
N3
M3
P5
N5
L5
L3
L4
L2
K4
J1
If DDRSS is not used, leave unconnected.
L2
H2
J4
K1
G3
H2
H3
G1
E3
R4
C2
E4
D3
E5
D2
F3
F1
F2
R3
R2
T2
U2
U3
U4
T4
T5
D1
E1
T1
R1
J4
Note: The DDR0 pins in this list can only be left unconnected when
VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0
pins must be connected as defined in the DDR Board Design and
Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are
connected to a power source.
L6
K2
H5
W5
F4
G5
F3
H6
E3
G2
F2
F1
U1
U3
U2
V5
W2
V6
Y1
W1
E1
E2
V1
V2
H1
J3
K2
G2
G1
USB0 and USB1 share these power rails, so each of these balls
must be connected to valid power sources when either USB0 or
USB1 is used.
W12
Y11
Y13
P11
R11
R10
VDDA_CORE_USB
VDDA_1P8_USB
VDDA_3P3_USB
If USB0 and USB1 are not used, each of these balls must be
connected directly to VSS.
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ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
表6-74. Connectivity Requirements (continued)
ALW
BALL
AMC
BALL
BALL NAME
CONNECTION REQUIREMENTS
NUMBER
NUMBER
If USB0 or USB1 is not used, leave the respective DM, DP, and
VBUS balls unconnected.
AE11
AA11
Y10
T8
V10
W8
W9
V9
USB0_DM
USB0_DP
USB0_RCALIB
USB0_VBUS
USB1_DM
USB1_DP
USB1_RCALIB
USB1_VBUS
AD11
AE10
AC11
AD10
AE9
Note: The USB0_RCALIB and USB1_RCALIB pins can only be left
unconnected when VDDA_CORE_USB, VDDA_1P8_USB, and
VDDA_3P3_USB are connected to VSS. The USB0_RCALIB and
USB1_RCALIB pins must be connected to VSS through separate
appropriate external resistors when VDDA_CORE_USB,
VDDA_1P8_USB, and VDDA_3P3_USB are connected to power
sources.
AC9
AB10
U9
If CSIRX0 is not used and the device boundary scan function is
required, each of these balls must be connected to valid power
sources.
W13
W14
P12
R12
VDDA_CORE_CSIRX0
VDDA_1P8_CSIRX0
If CSIRX0 is not used and the device boundary scan function is not
required, each of these balls can alternatively be connected directly
to VSS.
AD15
AE15
AB14
AC15
AD14
AE14
AD13
AE13
AB12
AC13
AA14
AA14
AA13
Y13
Y12
V13
V12
U12
U11
W12
W11
T11
CSI0_RXCLKN
CSI0_RXCLKP
CSI0_RXN0
CSI0_RXP0
CSI0_RXN1
CSI0_RXP1
CSI0_RXN2
CSI0_RXP2
CSI0_RXN3
CSI0_RXP3
CSI0_RXRCALIB
If CSIRX0 is not used, leave unconnected.
AA5
Y6
AD3
AB4
Y8
AA2
AA3
V5
V6
U7
OLDI0_A0N
OLDI0_A0P
OLDI0_A1N
OLDI0_A1P
OLDI0_A2N
OLDI0_A2P
OLDI0_A3N
OLDI0_A3P
OLDI0_A4N
OLDI0_A4P
OLDI0_A5N
OLDI0_A5P
OLDI0_A6N
OLDI0_A6P
OLDI0_A7N
OLDI0_A7P
OLDI0_CLK0N
OLDI0_CLK0P
OLDI0_CLK1N
OLDI0_CLK1P
AA8
AB6
AA7
AC6
AC5
AE5
AD6
AE6
AD7
AD8
AE7
AD4
AE3
AE4
AD5
U6
W6
W5
AA4
Y5
AA6
AA5
AA10
Y9
AA8
Y8
V7
V8
Y7
If OLDI0 is not used, leave unconnected.
AA7
If VMON_VSYS is not used, this ball must be connected directly to
VSS.
H10
F6
VMON_VSYS
If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor
the SOC power rails, these balls must still be connected to their
respective 1.8V and 3.3V power rails.
G10
K10
H9
K11
VMON_1P8_SOC
VMON_3P3_SOC
(1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table.
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备注
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This can be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which are
only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are
recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold
inputs of any attached device in a valid logic state until software initializes the respective IOs. The
state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and
BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input
buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input
buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The
input buffer can enter a high-current state which could damage the IO cell if allowed to float between
these levels.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX UNIT
VDD_CORE
Core supply
1.05
1.05
1.05
1.05
1.05
1.05
1.57
1.57
1.98
1.98
V
V
V
V
V
V
V
V
V
V
VDDR_CORE
RAM supply
VDD_CANUART
VDDA_CORE_CSIRX0
VDDA_CORE_USB
VDDA_DDR_PLL0(3)
VDDS_DDR
CANUART core supply
CSIRX0 core supply
USB0 and USB1 core supply
DDR Deskew PLL supply
DDR PHY IO supply
VDDS_DDR_C
VDDS_OSC0
DDR clock IO supply
MCU_OSC0 supply
VDDA_MCU
RCOSC, POR, POK, and MCU PLL analog supply
MAIN PLL, DDR PLL, DSS PLL0, and DSS PLL1 analog
supply
VDDA_PLL0
-0.3
1.98
V
VDDA_PLL1
VDDA_PLL2
VDDA_1P8_CSIRX0
VDDA_1P8_OLDI0
VDDA_1P8_USB
VDDA_TEMP0
VDDA_TEMP1
VPP
PER0 PLL and PER1 PLL analog supply
ARM0 PLL and SMS PLL analog supply
CSIRX0 1.8 V analog supply
OLDI0 1.8 V analog supply
USB0 and USB1 1.8 V analog supply
TEMP0 analog supply
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
1.98
1.98
1.98
1.98
1.98
1.98
1.98
1.98
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
3.63
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
TEMP1 analog supply
eFuse ROM programming supply
IO supply for IO MCU
VDDSHV_MCU
VDDSHV_CANUART
VDDSHV0
IO supply for IO CANUART
IO supply for IO group 0
VDDSHV1
IO supply for IO group 1
VDDSHV2
IO supply for IO group 2
VDDSHV3
IO supply for IO group 3
VDDSHV4
IO supply for IO group 4
VDDSHV5
IO supply for IO group 5
VDDSHV6
IO supply for IO group 6
VDDA_3P3_USB
USB0 and USB1 3.3 V analog supply
MCU_PORz
MCU_I2C0_SCL, MCU_I2C0_SDA,
WKUP_I2C0_SCL, WKUP_I2C0_SDA,
and EXTINTn
-0.3
-0.3
1.98(4)
3.63(4)
V
When operating at 1.8V
MCU_I2C0_SCL, MCU_I2C0_SDA,
WKUP_I2C0_SCL, WKUP_I2C0_SDA,
and EXTINTn
Steady-state max voltage at all fail-safe IO pins
When operating at 3.3V
VMON_1P8_SOC
VMON_3P3_SOC
VMON_VSYS(5)
-0.3
-0.3
-0.3
1.98
3.63
1.98
V
V
V
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over operating junction temperature range (unless otherwise noted)(1) (2)
PARAMETER
MIN
MAX UNIT
USB0_VBUS, USB1_VBUS(7)
-0.3
3.6
V
V
Steady-state max voltage at all other IO pins(6)
IO supply
voltage + 0.3
All other IO pins
-0.3
20% of IO supply voltage for up to 20%
of the signal period (see 图7-1, IO
Transient overshoot and undershoot at IO pin
0.2 × VDD(8)
V
Transient Voltage Ranges)
I-Test
Latch-up performance(9)
-100
-55
100
1.5 x VDD(8)
+150
mA
V
Over-Voltage (OV) Test
TSTG
Storage temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under 节7.5, Recommended Operating
Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be
fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) The VDDA_DDR_PLL0 power rail is only available on the AMC package. This power rail is internally connected to VDD_CORE in the
ALW package.
(4) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also
defined by the maximum VIH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where
the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.
(5) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see 节9.2.4, System Power Supply
Monitor Design Guidelines.
(6) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage
range, including power supply ramp-up and ramp-down sequences.
(7) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.2.3, USB Design
Guidelines.
(8) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(9) For current pulse injection (I-Test):
•
Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For over-voltage performance (Over-Voltage (OV) Test):
Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.
•
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,
EXTINTn, VMON_1P8_SOC, VMON_3P3_SOC, VMON_VSYS, and MCU_PORz are the only fail-safe IO
terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value
defined by the "Steady-state max voltage at all other IO pins" parameter in 节7.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A. Tovershoot + Tundershoot < 20% of Tperiod
图7-1. IO Transient Voltage Ranges
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7.2 ESD Ratings for Devices which are not AEC - Q100 Qualified
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic discharge
V(ESD)
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
(ESD)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings for AEC - Q100 Qualified Devices in the AMC Package
VALUE
±1000
UNIT
Human-body model (HBM), per AEC - Q100-002(1)
Charged-device model (CDM), per AEC - Q100-011
Corner pins
(A1, A21, AA1, and
AA21)
V(ESD)
Electrostatic discharge
±750
±250
V
All other pins
(1) AEC - Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Power-On Hours (POH)
POWER ON HOURS (POH)(1) (2) (3)
JUNCTION TEMPERATURE RANGE (TJ)
LIFETIME (POH)
100000
Commercial
0°C to 95°C
Extended Industrial
Automotive
100000
–40°C to 105°C
–40°C to 125°C
20000(4)
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
and 10%@125°C.
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7.5 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
NOM MAX(1) UNIT
VDD_CORE(2)
Core supply
CSIRX0 core supply
USB0 and USB1 core supply
DDR Deskew PLL supply
0.75-V operation
0.85-V operation
0.715
0.75
0.79
V
VDDA_CORE_CSIRX0(2)
VDDA_CORE_USB(2)
VDDA_DDR_PLL0(2) (3)
0.81
0.85
0.895
V
0.75-V operation
0.85-V operation
0.715
0.81
0.81
1.06
1.14
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
see(6)
1.71
3.135
3.135
0
0.75
0.85
0.85
1.1
0.79
0.895
0.895
1.17
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CANUART(4)
CANUART core supply
RAM supply
VDDR_CORE
VDDS_DDR(5)
DDR PHY IO supply
DDR clock IO supply
1.1-V operation
1.2-V operation
VDDS_DDR_C(5)
1.2
1.26
VDDS_OSC0
VDDA_MCU
MCU_OSC0 supply
1.8
1.89
RCOSC, POR, POK, and MCU PLL analog supply
MAIN PLL, DDR PLL, DSS PLL0, and DSS PLL1 analog supply
PER0 PLL and PER1 PLL analog supply
ARM0 PLL and SMS PLL analog supply
CSIRX0 1.8 V analog supply
1.8
1.89
VDDA_PLL0
1.8
1.89
VDDA_PLL1
1.8
1.89
VDDA_PLL2
1.8
1.89
VDDA_1P8_CSIRX0
VDDA_1P8_OLDI0
VDDA_1P8_USB
VDDA_TEMP0
VDDA_TEMP1
VPP
1.8
1.89
OLDI0 1.8 V analog supply
1.8
1.89
USB0 and USB1 1.8 V analog supply
TEMP0 analog supply
1.8
1.89
1.8
1.89
TEMP1 analog supply
1.8
1.89
eFuse ROM programming supply
Voltage monitor for 1.8 V SoC power supply
USB0 and USB1 3.3 V analog supply
Voltage monitor for 3.3 V SoC power supply
Voltage monitor pin
see(6)
see(6)
VMON_1P8_SOC
VDDA_3P3_USB
VMON_3P3_SOC
VMON_VSYS
USB0_VBUS
1.8
1.89
3.3
3.465
3.465
1
3.3
see(7)
see(8)
see(8)
1.8
USB0 Level-shifted VBUS Input
0
3.465
3.465
1.89
USB1_VBUS
USB1 Level-shifted VBUS Input
0
1.8-V operation
Dual-voltage IO supply
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
VDDSHV_CANUART(9)
VDDSHV_MCU
VDDSHV0
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV1
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV2
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV3
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV4
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV5
3.3-V operation
3.3
3.465
1.89
1.8-V operation
Dual-voltage IO supply
1.8
VDDSHV6
3.3-V operation
3.3
3.465
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over operating junction temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN(1)
NOM MAX(1) UNIT
Automotive
-40
125
105
95
°C
°C
°C
Extended
Industrial
TJ
Operating junction temperature range
-40
0
Commercial
(1) The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during
normal device operation.
(2) VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from the same power source.
Care should be taken to ensure that voltage differential between VDD_CORE and VDDA_CORE_USB is within +/- 1%.
(3) The VDDA_DDR_PLL0 power rail is only available on the AMC package. This power rail is internally connected to VDD_CORE in the
ALW package.
(4) VDD_CANUART shall be connected to an always on power source when using Partial IO low power mode. VDD_CANUART shall be
connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_USB, and VDDA_DDR_PLL0 when not
using Partial IO low power mode.
(5) VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.
(6) Refer to the Recommended Operating Conditions for OTP eFuse Programming table for VPP supply voltages based on eFuse usage.
(7) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see 节9.2.4, System Power Supply
Monitor Design Guidelines.
(8) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.2.3, USB Design
Guidelines.
(9) VDDSHV_CANUART shall be connected to an always on power sources when using Partial IO low power mode. VDDSHV_CANUART
shall be connected to any valid IO power source when not using Partial IO low power mode.
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7.6 Operating Performance Points
This section describes maximum operating conditions of the device in 表 7-1 and describes each Operating
Performance Point (OPP) for processor clocks and device core clocks in 表7-2.
表7-1. Device Speed Grades
MAXIMUM
MAXIMUM OPERATING FREQUENCY (MHz)
TRANSITION
RATE (MT/s)(2)
Speed
Grade
VDD_CORE
(V)(1)
Device/
Power
(Cortex- Manager
SMS
Subsystem
(Dual
Cortex-
M4F)
A53SS
(Cortex- GPU PRU
A53x)
Main
Infra
(CBA)
MCUSS
OCSRAM
DDR4
LPDDR4
M4F)
(Cortex-
R5F)
G
K
S
0.75/0.85
0.75/0.85
0.75/0.85
0.75/0.85
0.85
300
800
500
500
500
250
250
333
250
250
250
400
400
400
400
400
400
400
400
400
400
400
400
1600
1600
1600
1600
1600
1600
1000
1250
1400
T
500
333
250
400
400
400
400
1600
1600
(1) Nominal operating voltage, see Recommended Operating Conditions.
(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
表7-2. Device Operating Performance Points
FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)
MT/s(3)
DEVICE/
POWER
MANAGER
OPP
High
Low
A53SS(1)
MAIN
INFRA (CBA)
SMS /
SMS CBA
GPU
PRU
MCUSS
OCSRAM
DDR4
LPDDR4
From
ARM0
PLL
Bypass
to
Speed
Grade
Maximum
1600
(Max)
500
250
125
400
133
400
400
From
DDR
333,
250,
or
400
or
200
PLL
Bypass(4)
to
1600
250
(DRAM DLL
Bypass)
200
N/A
133
133
(1) Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.
(2) Fixed operating frequency, set by software at boot.
(3) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
(4) The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL
Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.
7.7 Power Consumption Summary
For information on the device power consumption, see the AM62x Power Estimation Tool application note.
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7.8 Electrical Characteristics
备注
The interfaces or signals described in 节 7.8 correspond to the interfaces or signals available in
multiplexing mode 0 (Primary Signal Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.8.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8 V MODE
VIL
Input Low Voltage
0.3 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
Input Low Voltage Steady State
Input High Voltage
VIH
0.7 × VDD(1)
0.7 × VDD(1)
0.1 × VDD(1)
1.98(2)
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
VOL
Output Low Voltage
0.2 × VDD(1)
V
(3)
IOL
Low Level Output Current
VOL(MAX)
10
mA
18f(4)
or
(5)
SRI
Input Slew Rate
V/s
1.8E+6
3.3 V MODE (6)
VIL
Input Low Voltage
0.3 × VDD(1)
0.25 × VDD(1)
3.63(2)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.7 × VDD(1)
0.7 × VDD(1)
0.05 × VDD(1)
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 3.3 V
or
VI = 0 V
IIN
Input Leakage Current.
±10
0.4
µA
VOL
Output Low Voltage
V
(3)
IOL
Low Level Output Current
VOL(MAX)
10
mA
33f(4)
or
(5)
SRI
Input Slew Rate
8E+7
V/s
3.3E+6
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) This value also defines the Absolute Maximum Ratings value the IO.
(3) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value. The
value defined by this parameter should be considered the maximum current available to a system implementation which needs to
maintain the specified VOL value for attached components.
(4) f = toggle frequency of the input signal in Hz.
(5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
(6) I2C Hs-mode is not supported when operating the IO in 3.3 V mode.
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7.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.3 ×
VDDS_OSC0
VIL
Input Low Voltage
V
0.3 ×
VDDS_OSC0
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
V
V
0.7 ×
VDDS_OSC0
0.7 ×
VDDS_OSC0
Input High Voltage Steady State
Input Hysteresis Voltage
V
200
mV
VI = 1.8 V
or
VI = 0 V
IIN
Input Leakage Current.
Input Slew Rate
±10
µA
18f(1)
or
(2)
SRI
V/s
1.8E+6
(1) f = toggle frequency of the input signal in Hz.
(2) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
7.8.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.35 ×
VDDS_OSC0
VIL
Input Low Voltage
V
0.65 ×
VDDS_OSC0
VIH
Input High Voltage
V
VHYS
Input Hysteresis Voltage
49
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
7.8.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.30 ×
VDDS_OSC0
VIL
VIH
Input Low Voltage
V
0.70 ×
VDDS_OSC0
Input High Voltage
V
Active Mode
85
mV
mV
VHYS
Input Hysteresis Voltage
Bypass Mode
324
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
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MAX UNIT
7.8.5 SDIO Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.8 V MODE
VIL
Input Low Voltage
0.58
0.58
V
V
VILSS
Input Low Voltage Steady State
Input High Voltage
VIH
1.27
1.7
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
RPU
RPD
VOL
Pull-up Resistor
40
40
50
50
60
60
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
0.45
VDDSHV5 -
0.45
VOH
Output High Voltage
V
(1)
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
4
4
mA
mA
(1)
IOH
18f(2)
or
(3)
SRI
Input Slew Rate
V/s
1.8E+6
3.3 V MODE
0.25 ×
VDDSHV5
VIL
Input Low Voltage
V
V
V
0.15 ×
VDDSHV5
VILSS
VIH
VIHSS
VHYS
Input Low Voltage Steady State
Input High Voltage
0.625 ×
VDDSHV5
0.625 ×
VDDSHV5
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 3.3 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0 V
RPU
RPD
Pull-up Resistor
40
40
50
50
60
60
kΩ
kΩ
Pull-down Resistor
0.125 ×
VDDSHV5
VOL
VOH
Output Low Voltage
Output High Voltage
V
V
0.75 ×
VDDSHV5
(1)
IOL
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
6
mA
mA
(1)
IOH
10
33f(2)
or
(3)
SRI
Input Slew Rate
V/s
3.3E+6
(1) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able
to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(2) f = toggle frequency of the input signal in Hz.
(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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7.8.6 LVCMOS Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8-V MODE
VIL
Input Low Voltage
0.35 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.65 × VDD(1)
0.85 × VDD(1)
150
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
mV
VI = 1.8 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
RPU
RPD
VOL
VOH
Pull-up Resistor
15
15
22
22
30
30
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
Output High Voltage
Low Level Output Current
High Level Output Current
0.45
VDD(1) - 0.45
V
(2)
IOL
VOL(MAX)
VOH(MIN)
3
3
mA
mA
(2)
IOH
18f(3)
or
(4)
SRI
Input Slew Rate
V/s
1.8E+6
3.3-V MODE
VIL
Input Low Voltage
0.8
0.6
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
2.0
2.0
V
VIHSS
VHYS
Input High Voltage Steady State
Input Hysteresis Voltage
V
150
mV
VI = 3.3 V
or
IIN
Input Leakage Current.
±10
µA
VI = 0.0 V
RPU
RPD
VOL
VOH
Pull-up Resistor
15
15
22
22
30
30
kΩ
kΩ
V
Pull-down Resistor
Output Low Voltage
Output High Voltage
Low Level Output Current
High Level Output Current
0.4
2.4
5
V
(2)
IOL
VOL(MAX)
VOH(MIN)
mA
mA
(2)
IOH
9
33f(3)
or
(4)
SRI
Input Slew Rate
V/s
3.3E+6
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able
to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
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7.8.7 OLDI LVDS (OLDI) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VOH
VOL
Voltage, Output High
1.5
Voltage, Output Low
0.925
1.125
V
VOCM
Voltage, Output Common Mode
1.375
30
V
Delta Voltage, Output Common Mode
(Difference between high and low steady-states)
mV
Differential Load = 100Ω
ΔVOCM
VOD
Voltage, Output Differential
250
-10
400
50
mV
mV
Delta Voltage, Output Differential
(Difference between high and low steady-states)
ΔVOD
V = VSS
Differential Load = 100Ω
-5
mA
µA
IOS
Current, Output Short-Circuit
Current, Output High-Z
V = VDD(1)
or
4
40
IOZ
V = VSS
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
7.8.8 CSI-2 (D-PHY) Electrical Characteristics
备注
CSIRX0 is compliant with MIPI DPHY v1.2 dated August 1, 2014 including ECNs and Errata as
applicable
7.8.9 USB2PHY Electrical Characteristics
备注
The USB0 and USB1 interfaces are compliant with Universal Serial Bus Revision 2.0 Specification
dated April 27, 2000 including ECNs and Errata as applicable.
7.8.10 DDR Electrical Characteristics
备注
The DDR interface is compatible with DDR4 devices that are JESD79-4B standard-compliant, and
LPDDR4 devices that are JESD209-4B standard-compliant
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7.9 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses.
7.9.1 Recommended Operating Conditions for OTP eFuse Programming
over operating junction temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain during OTP
operation; OPP NOM (BOOT)
V
See 节7.5
VPP
Supply voltage range for the eFuse ROM domain during
normal operation without hardware support to program
eFuse ROM
NC(1)
V
V
V
Supply voltage range for the eFuse ROM domain during
normal operation with hardware support to program eFuse
ROM
0
Supply voltage range for the eFuse ROM domain during
OTP programming(2)
1.71
1.8
1.89
I(VPP)
SR(VPP)
Tj
VPP current
400
6E + 4
85
mA
V/s
°C
VPP Slew Rate
Operating junction temperature range while programming
eFuse ROM.
0
25
(1) NC indicates No Connect.
(2) Supply voltage range includes DC errors and peak-to-peak noise.
7.9.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP power supply must be disabled when not programming OTP registers.
• The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see
节7.11.2.2, Power Supply Sequencing).
7.9.3 Programming Sequence
Programming sequence for OTP eFuses:
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during
power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
• Apply the voltage on the VPP terminal according to the specification in 节7.9.1.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP terminal.
7.9.4 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that the
e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step.
Further the TI Device may fail to secure boot if the error code correction check fails for the Production Keys or if
the image is not signed and optionally encrypted with the current active Production Keys. These types of
situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices conformed
to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
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7.10 Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in 节7.5, Recommended Operating Conditions.
7.10.1 Thermal Resistance Characteristics for ALW and AMC Packages
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
ALW
AMC
AIR
NO.
PARAMETER
DESCRIPTION
PACKAGE
PACKAGE
FLOW
°C/W(1) (2)
°C/W(1) (2)
(m/s)(3)
T1
T2
Junction-to-case
Junction-to-board
Junction-to-free air
3.7
8.3
1.2
3.9
N/A
N/A
0
RΘJC
RΘJB
RΘJA
T3
22.3
15.7
14.5
13.9
0.2
13.3
9.7
T4
1
T5
Junction-to-moving air
8.7
2
T6
8.1
3
T7
0.73
0.75
0.76
0.77
3.7
0
T8
0.3
1
Junction-to-package top
Junction-to-board
ΨJT
T9
0.3
2
T10
T11
T12
T13
T14
0.3
3
8.2
0
7.7
3.4
1
ΨJB
7.6
3.3
2
7.5
3.3
3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(3) m/s = meters per second.
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7.11 Timing and Switching Characteristics
备注
The Timing Requirements and Switching Characteristics values may change following the silicon
characterization result.
备注
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.
7.11.1 Timing Parameters and Information
The timing parameter symbols used in 节 7.11, Timing and Switching Characteristics are created in accordance
with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been
abbreviated in 表7-3:
表7-3. Timing Parameters Subscripts
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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7.11.2 Power Supply Requirements
This section describes the power supply requirements to ensure proper device operation.
备注
All power balls must be supplied with the voltages specified in the Recommended Operating
Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity
Requirements.
7.11.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in 图 7-2, TI recommends
having the supply ramp slew for a 1.8-V supply of more than 100 µs.
图7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
slew rate < 18 mV/μs
slew > (supply value) / (18 mV/μs)
or
supply value × 55.6 μs/V
SPRT740_ELCH_06
图7-2. Power Supply Slew and Slew Rate
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7.11.2.2 Power Supply Sequencing
This section describes power sequence requirements using power sequence diagrams and associated notes.
Each power sequence diagram demonstrates the sequential order expected for each device power rail. This is
done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be associated
with more than one waveform and the associated note will describe which waveform is applicable. Each
waveform defines a transition region for the associated power rails and shows its sequential relationship to the
transition regions of other power rails. The notes associated with the power sequence diagram provides further
detail of these requirements. See the Power-up Sequence section for details on power-up requirements, and the
Power-down Sequence section for details on power-down requirements.
Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The
legends shown in 图 7-3 and 图 7-4 along with their descriptions are provided to clarify what each transition
regions represents.
图7-3 defines a transition region with multiple power rails which may be sourced from multiple power supplies or
a single power supply. Transitions shown within the transition region represent a use case where multiple power
supplies are used to source power rails associated with this waveform, and these power supplies are allowed to
ramp at different times within the region since they do not have any specific sequence requirement relative to
each other.
图7-3. Multiple Power Supply Transition Legend
图 7-4 defines a transition region with one or more power rails which must be sourced from a single common
power supply. No transitions are shown within the region to represent a single ramp within the transition region.
图7-4. Single Common Power Supply Transition Legend
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7.11.2.2.1 Power-Up Sequencing
表7-4 and 图7-5 describes the device power-up sequencing.
备注
The power supply sequencing requirements defined in this section does not include entry or exit from
low power modes. See 节 7.11.2.2.3, Partial IO Power Sequencing for more information on power
supply sequence requirements when entering or exiting low power modes.
表7-4. Power-Up Sequencing –Supply / Signal Assignments
See: 图7-5
WAVEFORM
SUPPLY / SIGNAL NAME
A
B
VSYS(1), VMON_VSYS(2)
VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB,
VMON_3P3_SOC(4)
VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDA_MCU,
VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_USB, VDDA_TEMP0,
VDDA_TEMP1, VMON_1P8_SOC(6)
C
D
E
F
VDDSHV4(7), VDDSHV5(7), VDDSHV6(7)
VDDS_DDR(8), VDDS_DDR_C(8)
VDD_CANUART(9)
G
VDD_CANUART(10), VDD_CORE(10) (12), VDDA_CORE_CSIRX0(10), VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10)
VDD_CANUART(11), VDD_CORE(11) (12), VDDA_CORE_CSIRX0(11), VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11)
VDDR_CORE(12)
,
H
I
VPP(13)
J
K
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XI
(1) VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply
that sources power management devices which source all other supplies.
(2) VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see the System Power
Supply Monitor Design Guidelines.
(3) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements.
VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any
valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power
source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.
When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V
supplies during the 3.3V ramp period defined by this waveform.
(4) The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V supply source.
(5) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements.
VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any
valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power
source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.
When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V
supplies during the 1.8V ramp period defined by this waveform.
(6) The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V supply source.
(7) VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any
dependency on other power rails. This capability is required to support UHS-I SD Cards.
(8) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.
(9) VDD_CANUART shall be connected to an always-on power source when using Partial IO low power mode.
When VDD_CANUART is connected to an always-on power source, the potential applied to VDD_CORE must never be greater than
the potential applied to VDD_CANUART + 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before
and ramp down after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for VDD_CORE.
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(10) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and
VDDA_DDR_PLL0 when not using Partial IO low power mode.
VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or
0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior to VDDR_CORE as defined by this waveform.
(11) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDD_CORE, VDDA_CORE_CSIRX0,
VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.
VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB, and VDDA_DDR_PLL0 can be operated at 0.75V or
0.85V. When these supplies are operating at 0.85V, they shall be powered from the same source as VDDR_CORE and ramped during
the 0.85V ramp period defined by this waveform.
(12) The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or
power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at
0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE.
VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is
operating at 0.85V.
(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and
during normal device operation. This supply shall only be sourced while programming eFuse.
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VSYS
Waveform A
Waveform B
VMON_VSYS
Waveform C
Waveform D
Waveform E
Waveform F
Waveform G
Waveform H
Waveform I
Hi-Z
Waveform J
Waveform K
AM62Ax_ELCH_01
图7-5. Power-Up Sequencing
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7.11.2.2.2 Power-Down Sequencing
表7-5 and 图7-6 describes the device power-down sequencing.
备注
The power supply sequencing requirements defined in this section does not include entry or exit from
low power modes. See 节 7.11.2.2.3, Partial IO Power Sequencing for more information on power
supply sequence requirements when entering or exiting low power modes.
表7-5. Power-Down Sequencing –Supply / Signal Assignments
See: 图7-6
WAVEFORM
SUPPLY / SIGNAL NAME
A
B
VSYS, VMON_VSYS
VDDSHV_CANUART(1), VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDA_3P3_USB,
VMON_3P3_SOC
VDDSHV_CANUART(2), VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDA_MCU,
VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSIRX0, VDDA_1P8_USB, VDDA_TEMP0,
VDDA_TEMP1, VMON_1P8_SOC
C
D
E
F
VDDSHV4(3), VDDSHV5(3), VDDSHV6(3)
VDDS_DDR, VDDS_DDR_C
VDD_CANUART(4)
G
VDD_CANUART(5), VDD_CORE(5), VDDA_CORE_CSIRX0(5), VDDA_CORE_USB0(5), VDDA_DDR_PLL0(5)
VDD_CANUART(6), VDD_CORE(6), VDDA_CORE_CSIRX0(6), VDDA_CORE_USB0(6), VDDA_DDR_PLL0(6)
VDDR_CORE
,
H
I
VPP
J
K
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XI
(1) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 3.3V.
(2) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 1.8V.
(3) VDDSHV4, VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any
dependency on other power rails. This capability is required to support UHS-I SD Cards.
(4) VDDSHV_CANUART when connected to an always-on power source for Partial IO low power mode.
(5) VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB0, and VDDA_DDR_PLL0 when operating at 0.75V
(6) VDD_CANUART, VDD_CORE, VDDA_CORE_CSIRX0, VDDA_CORE_USB0, and VDDA_DDR_PLL0 when operating at 0.85V
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VSYS
VMON_VSYS
Waveform A
Waveform B
Waveform C
Waveform D
Waveform E
Waveform F
Waveform G
Waveform H
Waveform I
Hi-Z
Waveform J
Waveform K
AM62Ax_ELCH_02
图7-6. Power-Down Sequencing
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7.11.2.2.3 Partial IO Power Sequencing
This section describes power supply sequence requirements when entering or exiting low power modes.
For more information on low power modes supported by this device and the names assigned to each low power
mode, see the Power Modes section in the Device Configuration chapter of the Technical Reference Manual.
Partial IO is the only low power mode that requires power supply changes to the device power rails. All power
supply rails except VDD_CANUART and VDDSHV_CANUART are turned off when operating in Partial IO mode.
The power sequence required to enter Partial IO is the same sequence defined in 节 7.11.2.2.2, Power-Down
Sequencing with the exception of VDD_CANUART and VDDSHV_CANUART, which remain powered. The
power sequence required to exit Partial IO is the same sequence defined in 节7.11.2.2.1, Power-Up Sequencing
with the exception of VDD_CANUART and VDDSHV_CANUART, which are already powered.
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7.11.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.11.3.1 Reset Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for reset related signals.
表7-6. Reset Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V
VDD(1) = 3.3V
0.0033
0.0018
V/ns
V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
表7-7. MCU_PORz Timing Requirements
see 图7-7
NO.
PARAMETER
MIN
MAX UNIT
Hold time, MCU_PORz active (low) at Power-up
after supplies valid (using external crystal circuit)
RST1
9500000
ns
th(SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-up
after supplies valid and external clock stable (using
external LVCMOS clock source)
RST2
1200
1200
ns
ns
Pulse Width, MCU_PORz low after Power-up
(without removal of Power or system reference
clock MCU_OSC0_XI/XO)
RST3 tw(MCU_PORzL)
图7-7. MCU_PORz Timing Requirements
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表7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see 图7-8
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
RST4 td(MCU_PORzL-MCU_RESETSTATzL)
RST5 td(MCU_PORzH-MCU_RESETSTATzH)
RST6 td(MCU_PORzL-RESETSTATzL)
RST7 td(MCU_PORzH-RESETSTATzH)
RST8 tw(MCU_RESETSTATzL)
0
ns
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
6120*S(1)
0
ns
ns
ns
ns
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RESETSTATz inactive (high)
9195*S(1)
966*S(1)
Pulse Width, MCU_RESETSTATz low
(SW_MCU_WARMRST)
Pulse Width, RESETSTATz low
(SW_MCU_WARMRST, SW_MAIN_PORz, or
SW_MAIN_WARMRST)
RST9 tw(RESETSTATzL)
4040*S
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
图7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
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表7-9. MCU_RESETz Timing Requirements
see 图7-9
NO.
PARAMETER
MIN
MAX UNIT
(1)
RST10 tw(MCU_RESETzL)
Pulse Width, MCU_RESETz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
表7-10. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see 图7-9
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)
0
ns
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)
RST13 td(MCU_RESETzL-RESETSTATzL)
966*S(1)
960
ns
ns
ns
Delay time, MCU_RESETz active (low) to
RESETSTATz active (low)
RST14 td(MCU_RESETzH-RESETSTATzH)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
4040*S(1)
(1) S = MCU_OSC0_XI/XO clock period in ns.
图7-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching
Characteristics
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表7-11. RESET_REQz Timing Requirements
see 图7-10
NO.
PARAMETER
MIN
MAX UNIT
(1)
RST15 tw(RESET_REQzL)
Pulse Width, RESET_REQz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
表7-12. RESETSTATz Switching Characteristics
see 图7-10
NO.
PARAMETER
MIN
MAX UNIT
Delay time, RESET_REQz active (low) to
RESETSTATz active (low)
RST16 td(RESET_REQzL-RESETSTATzL)
900*T(1)
ns
Delay time, RESET_REQz inactive (high) to
RESETSTATz inactive (high)
RST17 td(RESET_REQzH-RESETSTATzH)
4040*S(2)
ns
(1) T = Reset Isolation Time (Software Dependent)
(2) S = MCU_OSC0_XI/XO clock period in ns.
图7-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics
表7-13. EMUx Timing Requirements
see 图7-11
NO.
PARAMETER
MIN
MAX UNIT
Setup time, EMU[1:0] before MCU_PORz inactive
(high)
RST18 tsu(EMUx-MCU_PORz)
3*S(1)
ns
Hold time, EMU[1:0] after MCU_PORz inactive
(high)
RST19 th(MCU_PORz - EMUx)
10
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
图7-11. EMUx Timing Requirements
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表7-14. BOOTMODE Timing Requirements
see 图7-12
NO.
PARAMETER
MIN
MAX UNIT
Setup time, BOOTMODE[15:00] before
PORz_OUT high (External MCU PORz event or
Software SW_MAIN_PORz)
RST23 tsu(BOOTMODE-PORz_OUT)
3*S(1)
ns
Hold time, BOOTMODE[15:00] after PORz_OUT
high (External MCU PORz event, or Software
SW_MAIN_PORz)
RST24 th(PORz_OUT - BOOTMODE)
0
ns
(1) S = MCU_OSC0_XI/XO clock period in ns.
表7-15. PORz_OUT Switching Characteristics
see 图7-12
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
PORz_OUT active (low)
RST25 td(MCU_PORzL-PORz_OUT)
RST26 td(MCU_PORzH-PORz_OUT)
RST27 tw(PORz_OUTL)
0
ns
Delay time, MCU_PORz inactive (high) to
PORz_OUT inactive (high)
1840
1200
ns
ns
Pulse Width, PORz_OUT low (MCU_PORz or
SW_MAIN_PORz)
图7-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics
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7.11.3.2 Error Signal Timing
Tables and figures provided in this section define timing conditions and switching characteristics for
MCU_ERRORn.
表7-16. Error Signal Timing Conditions
PARAMETER
MIN
MAX UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
表7-17. MCU_ERRORn Switching Characteristics
see 图7-13
NO.
PARAMETER
MIN
MAX UNIT
Cycle time minimum, MCU_ERRORn (PWM
mode enabled)
ERR1 tc(MCU_ERRORn)
ERR2 tw(MCU_ERRORn)
td (ERROR_CONDITION-
(P*H)+(P*L)(1) (3) (4)
P*R(1) (2)
ns
Pulse width minimum, MCU_ERRORn active
(PWM mode disabled)(5)
ns
ns
Delay time, ERROR CONDITION to
MCU_ERRORn active(5)
ERR3
50*P(1)
MCU_ERRORnL)
(1) P = ESM functional clock period in ns.
(2) R = Error Pin Counter Pre-Load Register count value.
(3) H = Error Pin PWM High Pre-Load Register count value.
(4) L = Error Pin PWM Low Pre-Load Register count value.
(5) When PWM mode is enabled, MCU_ERRORn stops toggling after ERR3 and will maintain its value (either high or low) until the error is
cleared. When PWM mode is disabled, MCU_ERRORn is active low.
Internal Error Condition
(Active High)
ERR1
MCU_ERRORn
(PWM Mode Enabled)
ERR2
ERR3
MCU_ERRORn
(PWM Mode Disabled)
图7-13. MCU_ERRORn Timing Requirements and Switching Characteristics
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7.11.3.3 Clock Timing
Tables and figures provided in this section define timing conditions, timing requirements and switching
characteristics for clock signals.
表7-18. Clock Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
V/ns
OUTPUT CONDITIONS
pF
pF
pF
5
10
30
5 ns ≤tc < 8 ns
8 ns ≤tc < 20 ns
20 ns ≤tc
CL
Output load capacitance
表7-19. Clock Timing Requirements
see 图7-14
NO.
MIN
MAX UNIT
CLK1 tc(EXT_REFCLK1)
Cycle time minimum, EXT_REFCLK1
10
E*0.45(1)
E*0.45(1)
10
ns
CLK2 tw(EXT_REFCLK1H)
Pulse Duration, EXT_REFCLK1 high
E*0.55(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK3 tw(EXT_REFCLK1L)
Pulse Duration, EXT_REFCLK1 low
E*0.55(1)
CLK1 tc(MCU_EXT_REFCLK0)
CLK2 tw(MCU_EXT_REFCLK0H)
CLK3 tw(MCU_EXT_REFCLK0L)
CLK1 tc(AUDIO_EXT_REFCLK0)
CLK2 tw(AUDIO_EXT_REFCLK0H)
CLK3 tw(AUDIO_EXT_REFCLK0L)
CLK1 tc(AUDIO_EXT_REFCLK1)
CLK2 tw(AUDIO_EXT_REFCLK1H)
CLK3 tw(AUDIO_EXT_REFCLK1L)
Cycle time minimum, MCU_EXT_REFCLK0
Pulse Duration, MCU_EXT_REFCLK0 high
Pulse Duration, MCU_EXT_REFCLK0 low
Cycle time minimum, AUDIO_EXT_REFCLK0
Pulse Duration, AUDIO_EXT_REFCLK0 high
Pulse Duration, AUDIO_EXT_REFCLK0 low
Cycle time minimum, AUDIO_EXT_REFCLK1
Pulse Duration, AUDIO_EXT_REFCLK1 high
Pulse Duration, AUDIO_EXT_REFCLK1 low
F*0.45(2)
F*0.45(2)
20
F*0.55(2)
F*0.55(2)
G*0.45(3)
G*0.45(3)
20
G*0.55(3)
G*0.55(3)
H*0.45(4)
H*0.45(4)
H*0.55(4)
H*0.55(4)
(1) E = EXT_REFCLK1 cycle time in ns.
(2) F = MCU_EXT_REFCLK0 cycle time in ns.
(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK1
CLK2
CLK3
Input Clock
图7-14. Clock Timing Requirements
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表7-20. Clock Switching Characteristics
see 图7-15
NO.
PARAMETER
MIN
8
MAX UNIT
CLK4 tc(SYSCLKOUT0)
CLK5 tw(SYSCLKOUT0H)
CLK6 tw(SYSCLKOUT0L)
CLK4 tc(OBSCLK0)
Cycle time minimum,SYSCLKOUT0
Pulse Duration, SYSCLKOUT0 high
Pulse Duration, SYSCLKOUT0 low
Cycle time minimum, OBSCLK0
ns
A*0.4(1)
A*0.4(1)
5
A*0.6(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A*0.6(1)
CLK5 tw(OBSCLK0H)
Pulse Duration, OBSCLK0 high
B*0.45(2)
B*0.45(2)
20
B*0.55(2)
B*0.55(2)
CLK6 tw(OBSCLK0L)
Pulse Duration, OBSCLK0 low
CLK4 tc(CLKOUT0)
Cycle time minimum, CLKOUT0
CLK5 tw(CLKOUT0H)
Pulse Duration, CLKOUT0 high
C*0.4(3)
C*0.4(3)
10
C*0.6(3)
C*0.6(3)
CLK6 tw(CLKOUT0L)
Pulse Duration, CLKOUT0 low
CLK4 tc(MCU_SYSCLKOUT0)
CLK5 tw(MCU_SYSCLKOUT0H)
CLK6 tw(MCU_SYSCLKOUT0L)
CLK4 tc(MCU_OBSCLK0)
CLK5 tw(MCU_OBSCLK0H)
CLK6 tw(MCU_OBSCLK0L)
CLK4 tc(WKUP_CLKOUT0)
CLK5 tw(WKUP_CLKOUT0H)
CLK6 tw(WKUP_CLKOUT0L)
Cycle time minimum, MCU_SYSCLKOUT0
Pulse Duration, MCU_SYSCLKOUT0 high
Pulse Duration, MCU_SYSCLKOUT0 low
Cycle time minimum, MCU_OBSCLK0
Pulse Duration, MCU_OBSCLK0 high
Pulse Duration, MCU_OBSCLK0 low
Cycle time minimum, WKUP_CLKOUT0
Pulse Duration, WKUP_CLKOUT0 high
Pulse Duration, WKUP_CLKOUT0 low
E*0.4(4)
E*0.4(4)
5
E*0.6(4)
E*0.6(4)
D*0.45(5)
D*0.45(5)
5
D*0.55(5)
D*0.55(5)
W*0.4(6)
W*0.4(6)
W*0.6(6)
W*0.6(6)
Cycle time minimum, AUDIO_EXT_REFCLK0
(McASP Clock Source)
20
ns
ns
CLK4 tc(AUDIO_EXT_REFCLK0 )
Cycle time minimum, AUDIO_EXT_REFCLK0
(PLL Clock Source)
10
CLK5 tw(AUDIO_EXT_REFCLK0 H)
CLK6 tw(AUDIO_EXT_REFCLK0 L)
Pulse Duration, AUDIO_EXT_REFCLK0 high
Pulse Duration, AUDIO_EXT_REFCLK0 low
G*0.4(7)
G*0.4(7)
G*0.6(7)
G*0.6(7)
ns
ns
Cycle time minimum, AUDIO_EXT_REFCLK1
(McASP Clock Source)
20
ns
ns
CLK4 tc(AUDIO_EXT_REFCLK1 )
Cycle time minimum, AUDIO_EXT_REFCLK1
(PLL Clock Source)
10
CLK5 tw(AUDIO_EXT_REFCLK1 H)
CLK6 tw(AUDIO_EXT_REFCLK1 L)
Pulse Duration, AUDIO_EXT_REFCLK1 high
Pulse Duration, AUDIO_EXT_REFCLK1 low
J*0.4(8)
J*0.4(8)
J*0.6(8)
J*0.6(8)
ns
ns
(1) A = SYSCLKOUT0 cycle time in ns.
(2) B = OBSCLK0 cycle time in ns.
(3) C = CLKOUT0 cycle time in ns.
(4) E = MCU_SYSCLKOUT0 cycle time in ns.
(5) D = MCU_OBSCLK0 cycle time in ns.
(6) W = WKUP_CLKOUT0 cycle time in ns.
(7) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(8) J = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK4
CLK5
CLK6
Output Clock
图7-15. Clock Switching Characteristics
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7.11.4 Clock Specifications
7.11.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
• MCU_OSC0_XO/MCU_OSC0_XI —external main crystal interface pins connected to the internal high-
frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock
HFOSC0_CLKOUT.
• WKUP_LFOSC0_XO/WKUP_LFOSC0_XI —external crystal interface pins connected to internal low-
frequency oscillator (WKUP_LFOSC0), which sources optional 32768 Hz reference clock.
• General purpose clock inputs
– MCU_EXT_REFCLK0 —optional external system clock.
– EXT_REFCLK1 —optional external system clock.
• External CPTS reference clock input
– CP_GEMAC_CPTS0_RFT_CLK —optional reference clock input for CPTS_RFT_CLK.
• External audio reference clock inputs/outputs
– AUDIO_EXT_REFCLK[1:0] —optional McASP high-frequency input clocks when configured to operate as
an input.
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
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7.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
图 7-16 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit
must be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.
Device
MCU_OSC0_XO
MCU_OSC0_XI
Crystal
CL2
CL1
PCB Ground
AM65x_MCU_OSC_INT_01
图7-16. MCU_OSC0 Crystal Implementation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-21 summarizes the
required electrical constraints.
表7-21. MCU_OSC0 Crystal Circuit Requirements
PARAMETER
MIN
TYP
MAX
UNIT
MHz
ppm
Fxtal
Fxtal
Crystal Parallel Resonance Frequency
25
Crystal Frequency Stability and Tolerance
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
7
pF
pF
pF
pF
pF
pF
Cshunt
Crystal Circuit Shunt Capacitance
25 MHz
25 MHz
25 MHz
ESRxtal = 30 Ω
ESRxtal = 40 Ω
ESRxtal = 50 Ω
5
5
(1)
ESRxtal
Crystal Effective Series Resistance
Ω
(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
表7-22 details the switching characteristics of the oscillator.
表7-22. MCU_OSC0 Switching Characteristics - Crystal Mode
PARAMETER
PACKAGE
MIN
TYP
MAX
0.812
1.635
UNIT
pF
CXI
XI Capacitance
ALW
AMC
pF
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表7-22. MCU_OSC0 Switching Characteristics - Crystal Mode (continued)
PARAMETER
PACKAGE
MIN
TYP
MAX
UNIT
pF
CXO
CXIXO
ts
XO Capacitance
ALW
0.83
AMC
1.72
0.0114
0.267
pF
XI to XO Mutual Capacitance
Start-up Time
ALW
pF
AMC
pF
4
ms
VDD_CORE (min.)
VDD_CORE
VSS
VDDS_OSC0 (min.)
VDDS_OSC0
MCU_OSC0_XO
tsX
VSS
Time
AM65x_MCU_OSC_STARTUP_02
图7-17. MCU_OSC0 Start-up Time
7.11.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB
designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits and
device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in 表7-22.
Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
MCU_OSC0_XO
AM65x_MCU_OSC_CC_05
图7-18. Load Capacitance
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Load capacitors, CL1 and CL2 in 图 7-16, should be chosen such that the below equation is satisfied. CL in the
equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.11.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in 表 7-21. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in 表7-22.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CPCBXIXO
CXIXO
CO
MCU_OSC0_XO
AM65x_MCU_OSC_SC_06
图7-19. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
C
shunt ≥CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
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7.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
图 7-20 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V LVCMOS
square-wave digital clock source.
备注
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an
unknown state when DC is applied to the input. Therefore, application software must power down
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.
Device
MCU_OSC0_XO
MCU_OSC0_XI
PCB Ground
AM65x_MCU_OSC_EXT_CLK_03
图7-20. 1.8-V LVCMOS-Compatible Clock Input
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7.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
图 7-21 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd
is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator
performance with production crystal circuit components installed on preproduction PCBs.
Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
Rd
Crystal
(Optional)
(Optional)
Rbias
Cf2
Cf1
PCB Ground
J7ES_LF_OSC_INT_12
图7-21. WKUP_LFOSC0 Crystal Implementation
表7-23 presents LFXOSC modes of operation.
表7-23. LFXOSC Modes of Operation
CLK_O
UT
MODE
BP_C PD_C
XI
XO
DESCRIPTION
ACTIVE
0
0
XTAL
XTAL CLK_OU
T
Active oscillator mode providing 32kHz
PWRDN
BYPASS
0
1
1
0
X
PD
PD
LOW Output will be pulled down to LOW. PAD to be tri-stated. Active mode disabled
CLK
CLK
XI is driven by external clock source. XO is pulled down to LOW. Due to ESD
diode to supply, XI should not be driven unless oscillator supply is present.
备注
User should set CTRLMMR_WKUP_LFXOSC_TRIM[18:16] i_mult = 3b’001 for CL in the range 6pf
to 9.5pf. CTRLMMR_WKUP_LFXOSC_TRIM [18:16] i_mult = 3b’010 for CL in the range 8.5pf to
12pf. Default setting is 3b’010.
备注
The load capacitors, Cf1 and Cf2 in 图 7-22, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.
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Cf1Cf2
= (Cf1+Cf2)
C
L
J7ES_CL_MATH_03
图7-22. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-24 summarizes the
required electrical constraints.
表7-24. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
TYP
MAX UNIT
Parallel resonance crystal frequency
32768
Hz
Cf1
Cf2
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
4
pF
pF
pF
pF
pF
pF
ESRxtal –40 kΩ
ESRxtal –60 kΩ
ESRxtal –80 kΩ
ESRxtal –100 kΩ
3
Cshunt Shunt capacitance
2
1
(1)
ESR
Crystal effective series resistance
Ω
(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
表7-25 details the switching characteristics of the oscillator and the requirements of the input clock.
表7-25. WKUP_LFOSC0 Switching Characteristics –Crystal Mode
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Hz
fxtal
tsX
Oscillation frequency
Start-up time
32768
96.5
ms
VDD_CORE (min.)
VSS
VDD_CORE
VDDS_OSC0
VDDS_OSC0 (min.)
WKUP_LFOSC0_XO
tsX
VSS
Time
LFXOSC_STARTUP_02
图7-23. WKUP_LFOSC0 Start-up Time
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7.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
图 7-24 shows the recommended oscillator connections when WKUP_LFOSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Device
WKUP_LFOSC0_XI
WKUP_LFOSC0_XO
PCB Ground
AM62x_MCU_OSC_EXT_CLK_03
图7-24. 1.8-V LVCMOS-Compatible Clock Input
7.11.4.1.5 WKUP_LFOSC0 Not Used
图7-25 shows the recommended oscillator connections when WKUP_LFOSC0 is not used.
Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
NC
PCB Ground
图7-25. WKUP_LFOSC0 Not Used
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7.11.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
• MCU_SYSCLKOUT0
– MCU_PLL0_HSDIV0_CLKOUT (MCU_SYSCLKOUT0) divided by 4 and sent out of the device as
MCU_SYSCLKOUT0. This clock output is provided for test and debug purposes only.
• MCU_OBSCLK0
– Observation clock output for test and debug purposes only.
• WKUP_CLKOUT0
– WKUP domain CLKOUT0 output.
• SYSCLKOUT0
– MAIN_PLL0_HSDIV0_CLKOUT (SYSCLKOUT0) divided by 4 and then sent out of the device as
SYSCLKOUT0. This clock output is provided for test and debug purposes only.
• CLKOUT0
– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-
by-10. This clock output was provided as an optional source to the external PHY. When configured to
operate as the RMII Clock source (50 MHz) the signal must also be routed back to the respective
RMII[x]_REF_CLK pin for proper device operation.
• OBSCLK0
– Observation clock output for test and debug purposes only.
• AUDIO_EXT_REFCLK[1:0]
– Option of sourcing one of six McASP high-frequency audio reference clocks,
MAIN_PLL1_HSDIV6_CLKOUT, or MAIN_PLL2_HSDIV8_CLKOUT when configured to operate as an
output.
7.11.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from
off-chip power-sources.
There is one PLL in the MCU domain:
• MCU PLL
There are eight PLLs in the MAIN domain:
• MAIN PLL
• PER0 PLL
• PER1 PLL
• ARM0 PLL
• DDR PLL
• SMS_PLL
• DSS0 PLL
• DSS1 PLL
The system designer should consider the reference clock source start-up time and the PLL lock requirements
before configuring and using any of the PLL outputs as clock sources. The device reference clock input
requirements are defined in 节 7.11.4.1, Input Clocks / Oscillators. PLL configuration details are described in the
device TRM.
For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration
section in the device TRM.
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7.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
All clock and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create non-
monotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and
control signals since they are more likely to generate glitches inside the device.
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7.11.5 Peripherals
7.11.5.1 CPSW3G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.11.5.1.1 CPSW3G MDIO Timing
表 7-26, 表 7-27, 表 7-28, and 图 7-26 present timing conditions, requirements, and switching characteristics for
CPSW3G MDIO.
表7-26. CPSW3G MDIO Timing Conditions
PARAMETER
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
470
表7-27. CPSW3G MDIO Timing Requirements
see 图7-26
NO.
PARAMETER
MIN
90
0
MAX
UNIT
ns
MDIO1 tsu(MDIO_MDC)
MDIO2 th(MDC_MDIO)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
ns
表7-28. CPSW3G MDIO Switching Characteristics
see 图7-26
NO.
PARAMETER
MIN
400
160
160
-150
MAX
UNIT
ns
MDIO3 tc(MDC)
Cycle time, MDIO[x]_MDC
MDIO4 tw(MDCH)
MDIO5 tw(MDCL)
MDIO7 td(MDC_MDIO)
Pulse Duration, MDIO[x]_MDC high
ns
Pulse Duration, MDIO[x]_MDC low
ns
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
图7-26. CPSW3G MDIO Timing Requirements and Switching Characteristics
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7.11.5.1.2 CPSW3G RMII Timing
表 7-29, 表 7-30, 图 7-27, 表 7-31, 图 7-28, 表 7-32, and 图 7-29 present timing conditions, requirements, and
switching characteristics for CPSW3G RMII.
表7-29. CPSW3G RMII Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V
VDD(1) = 3.3V
0.18
0.4
0.54 V/ns
1.2 V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
3
25
pF
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
表7-30. RMII[x]_REF_CLK Timing Requirements –RMII Mode
see 图7-27
NO.
PARAMETER
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
DESCRIPTION
MIN
MAX
20.001
13
UNIT
ns
RMII1
RMII2
RMII3
Cycle time, RMII[x]_REF_CLK
19.999
Pulse Duration, RMII[x]_REF_CLK High
Pulse Duration, RMII[x]_REF_CLK Low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
图7-27. CPSW3G RMII[x]_REF_CLK Timing Requirements –RMII Mode
表7-31. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements –RMII Mode
see 图7-28
NO.
PARAMETER
DESCRIPTION
MIN
4
MAX
UNIT
ns
RMII4
tsu(RXD-REF_CLK)
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
4
ns
4
ns
RMII5
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
2
ns
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
图7-28. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements –RMII Mode
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表7-32. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode
see 图7-29
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII6 td(REF_CLK-TXD)
Delay time, RMII[x]_REF_CLK High to RMII[x]_
TXD[1:0] valid
2
10
ns
td(REF_CLK-TX_EN)
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN
valid
2
10
ns
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
图7-29. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode
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7.11.5.1.3 CPSW3G RGMII Timing
表 7-33, 表 7-34, 表 7-35, 图 7-30, 表 7-36, 表 7-37, and 图 7-31 present timing conditions, requirements, and
switching characteristics for CPSW3G RGMII.
表7-33. CPSW3G RGMII Timing Conditions
PARAMETER
MIN
2.64
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
5
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
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MAX UNIT
表7-34. RGMII[x]_RXC Timing Requirements –RGMII Mode
see 图7-30
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_RXC
MODE
10Mbps
MIN
360
36
RGMII1 tc(RXC)
RGMII2 tw(RXCH)
RGMII3 tw(RXCL)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
3.6
4.4
表7-35. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements –RGMII Mode
see 图7-30
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
MAX UNIT
RGMII4 tsu(RD-RXC)
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
RGMII5 th(RXC-RD)
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
图7-30. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII
Mode
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表7-36. RGMII[x]_TXC Switching Characteristics –RGMII Mode
see 图7-31
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_TXC
MODE
10Mbps
MIN
360
36
MAX UNIT
RGMII6 tc(TXC)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
RGMII7 tw(TXCH)
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
RGMII8 tw(TXCL)
100Mbps
1000Mbps
3.6
4.4
表7-37. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics –RGMII Mode
see 图7-31
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX UNIT
RGMII9 tosu(TD-TXC)
Output setup time(1), RGMII[x]_TD[3:0] valid to
RGMII[x]_TXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
tosu(TX_CTL-TXC)
Output setup time(1), RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
RGMII10 toh(TXC-TD)
Output hold time(1), RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
10Mbps
toh(TXC-TX_CTL)
Output hold time(1), RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
(1) Output setup/hold times are defining a delay relationship of the transmit data and control outputs relative to the transmit clock output,
but this output relationship is being presented as the minimum setup/hold times provided to the attached receiver. This approach
matches how the output timing relationships are defined in the RGMII specification.
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
图7-31. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics -
RGMII Mode
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7.11.5.2 CPTS
表 7-38, 表 7-39, 图 7-32, 表 7-40, and 图 7-33 present timing conditions, requirements, and switching
characteristics for CPTS.
表7-38. CPTS Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
表7-39. CPTS Timing Requirements
see 图7-32
NO.
T1
T2
T3
T4
T5
PARAMETER
DESCRIPTION
Pulse duration, HWnTSPUSH high
MIN
12P(1) + 2
12P(1) + 2
5
MAX
UNIT
ns
tw(HWTSPUSHH)
tw(HWTSPUSHL)
tc(RFT_CLK)
Pulse duration, HWnTSPUSH low
Cycle time, RFT_CLK
ns
8
ns
tw(RFT_CLKH)
tw(RFT_CLKL)
Pulse duration, RFT_CLK high
Pulse duration, RFT_CLK low
0.45T(2)
0.45T(2)
ns
ns
(1) P = functional clock period in ns.
(2) T = RFT_CLK cycle time in ns.
T1
T2
HWn_TSPUSH
RFT_CLK
T3
T4
T5
图7-32. CPTS Timing Requirements
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表7-40. CPTS Switching Characteristics
see 图7-33
NO.
PARAMETER
DESCRIPTION
Pulse duration, TS_COMP high
SOURCE
MIN
36P(1) - 2
36P(1) - 2
36P(1) - 2
36P(1) - 2
36P(1) - 2
5P(1) - 2
MAX UNIT
T6
tw(TS_COMPH)
tw(TS_COMPL)
tw(TS_SYNCH)
tw(TS_SYNCL)
tw(SYNC_OUTH)
ns
ns
ns
ns
ns
ns
ns
ns
T7
Pulse duration, TS_COMP low
Pulse duration, TS_SYNC high
Pulse duration, TS_SYNC low
Pulse duration, SYNCn_OUT high
T8
T9
T10
TS_SYNC
GENF
T11
tw(SYNC_OUTL)
Pulse duration, SYNCn_OUT low
TS_SYNC
GENF
36P(1) - 2
5P(1) - 2
(1) P = functional clock period in ns.
T6
T7
TS_COMP
T8
T9
TS_SYNC
T10
T11
SYNCn_OUT
图7-33. CPTS Switching Characteristics
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
7.11.5.3 CSI-2
备注
For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) section in the
device TRM.
The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor. It is a key
component for the following multimedia applications: camera viewfinder, video record, and still image capture.
The CSI_RX_IF has a primary serial interface CSI-2 port (CSIRX0) compliant with the MIPI D-PHY RX
specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock
lane in synchronous mode, double data rate. Refer to the MIPI specifications for timing details.
• Support for 1,2,3 or 4 data lane mode up to 1.5Gbps
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7.11.5.4 DDRSS
For more details about features and additional description information on the device (LP)DDR4 Memory
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
表7-41 and 图7-34 present switching characteristics for DDRSS.
表7-41. DDRSS Switching Characteristics
see 图7-34
NO.
PARAMETER
DDR TYPE
LPDDR4
DDR4
MIN
1.25(1)
1.25(1)
MAX UNIT
20
ns
ns
tc(DDR_CKP/
1
Cycle time, DDR_CKP and DDR_CKN
DDR_CKN)
1.6
(1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB
implementation. Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR
frequency.
1
DDR0_CKP
DDR0_CKN
图7-34. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
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7.11.5.5 DSS
表 7-42, 表 7-43, 图 7-35, 表 7-44 and 图 7-36 present timing conditions, requirements, and switching
characteristics for DSS.
表7-42. DSS Timing Conditions
PARAMETER
MIN
1.44
1.5
MAX
26.4
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
100
ps
表7-43. DSS External Pixel Clock Timing Requirements
see 图7-35
NO.
MIN
6.06
MAX
UNIT
D6
D7
D8
tc(extpclkin)
Cycle time, VOUT(x)_EXTPCLKIN(2)
ns
ns
ns
tw(extpclkinL)
tw(extpclkinH)
Pulse duration, VOUT(x)_EXTPCLKIN(2) low
Pulse duration, VOUT(x)_EXTPCLKIN(2) high
0.475P(1)
0.475P(1)
(1) P = VOUT(x)_EXTPCLKIN cycle time in ns
(2) x in VOUT(x) = 0
D7
D8
D6
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_EXTPCLKIN
VOUT(x)_EXTPCLKIN
DPI_TIMING_02
图7-35. DSS External Pixel Clock Timing Requirements
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表7-44. DSS Switching Characteristics
see 图7-36
NO.
PARAMETER
MODE
MIN
MAX UNIT
D1
tc(pclk)
Cycle time, VOUT(x)_PCLK(2)
6.06
ns
ns
ns
ns
ns
Internal PLL 0.475P(1) - 0.3
EXTPCLKIN
Y(3) - 0.45
Internal PLL 0.475P(1) -0.3
D2
D3
D4
tw(pclkL)
Pulse duration, VOUT(x)_PCLK(2) low
tw(pclkH)
Pulse duration, VOUT(x)_PCLK(2) high
EXTPCLKIN
Internal PLL
EXTPCLKIN
Internal PLL
Z(4) - 0.45
Delay time, VOUT(x)_PCLK(2) transition to
VOUT(x)_DATA[23:0](2) transition
-0.68
1.78
1.78
1.78
ns
ns
ns
td(pclkV-dataV)
-0.68
Delay time, VOUT(x)_PCLK(2) transition to control signals
VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2)
falling edge
-0.68
D5
td(pclkV-ctrlL)
EXTPCLKIN
-0.68
1.78
ns
(1) P = VOUT(x)_PCLK cycle time in ns
(2) x in VOUT(x) = 0
(3) Y = tw(extpclkinL), parameter D7 from 表7-43, DSS External Pixel Clock Timing Requirements
(4) Z = tw(extpclkinH), parameter D8 from 表7-43, DSS External Pixel Clock Timing Requirements
D2
D3
D1
Falling-edge Clock Reference
Rising-edge Clock Reference
VOUT(x)_PCLK
VOUT(x)_PCLK
D5
VOUT(x)_VSYNC
D5
VOUT(x)_HSYNC
VOUT(x)_DATA[23:0]
VOUT(x)_DE
D4
data_1 data_2
D5
data_n
DPI_TIMING_01
A. The assertion of data can be programmed to occur on the falling or rising edge of the pixel clock. Refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
B. The polarity and pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section
in Peripherals chapter in the device TRM.
C. The VOUT(x)_PCLK frequency is configurable, refer to Display Subsystem section in Peripherals chapter in the device TRM.
图7-36. DSS Switching Characteristics
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the
device TRM.
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7.11.5.6 ECAP
表 7-45, 表 7-46, 图 7-37, 表 7-47, and 图 7-38 present timing conditions, requirements, and switching
characteristics for ECAP.
表7-45. ECAP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
表7-46. ECAP Timing Requirements
see 图7-37
NO.
PARAMETER
DESCRIPTION
Pulse duration, CAP (asynchronous)
MIN
MAX
UNIT
CAP1 tw(CAP)
2P(1) + 2
ns
(1) P = sysclk period in ns.
CAP1
CAP
EPERIPHERALS_TIMNG_01
图7-37. ECAP Timings Requirements
表7-47. ECAP Switching Characteristics
see 图7-38
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP2 tw(APWM)
Pulse duration, APWMx high/low
2P(1) - 2
ns
(1) P = sysclk period in ns.
CAP2
APWM
EPERIPHERALS_TIMNG_02
图7-38. ECAP Switching Characteristics
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
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7.11.5.7 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
7.11.5.7.1 Trace
表7-48. Trace Timing Conditions
PARAMETER
MIN
MAX UNIT
OUTPUT CONDITIONS
CL Output load capacitance
PCB CONNECTIVITY REQUIREMENTS
2
5
pF
ps
td(Trace Mismatch)
Propagation delay mismatch across all traces
200
表7-49. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
6.83
2.66
2.66
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
0.85
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.85
0.85
0.85
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
3.3V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
8.78
3.64
3.64
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
1.10
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.10
1.10
1.10
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
图7-39. Trace Switching Characteristics
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7.11.5.7.2 JTAG
表7-50. JTAG Timing Conditions
PARAMETER
MIN
0.5
5
MAX
2.0
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
15
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
Propagation delay mismatch across all traces
83.5
1000(1)
100
ps
ps
td(Trace Mismatch Delay)
(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
表7-51. JTAG Timing Requirements
see 图7-40
NO.
MIN
MAX
UNIT
ns
J1
tc(TCK)
Cycle time minimum, TCK
40(1)
J2
tw(TCKH)
Pulse width minimum, TCK high
0.4P(2)
ns
J3
tw(TCKL)
Pulse width minimum, TCK low
0.4P(2)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
Input setup time minimum, TDI valid to TCK high
Input setup time minimum, TMS valid to TCK high
Input hold time minimum, TDI valid from TCK high
Input hold time minimum, TMS valid from TCK high
2
2
3
3
ns
J4
J5
ns
ns
ns
(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristis for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
•
•
Minimum TDO setup time of 2 ns relative to the rising edge of TCK
TDI and TMS output delay in the range of -12.9 ns to 13.9 ns relative to the falling edge of TCK
(2) P = TCK cycle time in ns
表7-52. JTAG Switching Characteristics
see 图7-40
NO.
PARAMETER
MIN
MAX
UNIT
ns
J6
J7
td(TCKL-TDOI)
td(TCKL-TDOV)
Delay time minimum, TCK low to TDO invalid
Delay time maximum, TCK low to TDO valid
0
12
ns
J1
J2
J3
TCK
TDI / TMS
TDO
J4
J5
J4
J5
J7
J6
图7-40. JTAG Timing Requirements and Switching Characteristics
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7.11.5.8 EPWM
表 7-53, 表 7-54, 图 7-41, 表 7-55, 图 7-42, 图 7-43, and 图 7-44 present timing conditions, requirements, and
switching characteristics for EPWM.
表7-53. EPWM Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
表7-54. EPWM Timing Requirements
see 图7-41
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_SYNCI
MIN
2P(1) + 2
3P(1) + 2
MAX
UNIT
ns
PWM6 tw(SYNCIN)
PWM7 tw(TZ)
Pulse duration, EHRPWM_TZn_IN low
ns
(1) P = sysclk period in ns.
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
图7-41. EPWM Timing Requirements
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AM625, AM625-Q1, AM623, AM620-Q1
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表7-55. EPWM Switching Characteristics
see 图7-42, 图7-43, and 图7-44
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_A/B high/low
Pulse duration, EHRPWM_SYNCO
MIN
P(1) - 3
P(1) - 3
MAX
UNIT
ns
PWM1 tw(PWM)
PWM2 tw(SYNCOUT)
PWM3 td(TZ-PWM)
ns
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced
high/low
11
11
ns
PWM4 td(TZ-PWMZ)
PWM5 tw(SOC)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z
Pulse duration, EHRPWM_SOCA/B output
ns
ns
P(1) - 3
(1) P = sysclk period in ns.
PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
EHRPWM_SOCA/B
PWM5
EPERIPHERALS_TIMNG_04
图7-42. EHRPWM Switching Characteristics
PWM3
EHRPWM_A/B
EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05
图7-43. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics
PWM4
EHRPWM_A/B
EHRPWM_TZn_IN
图7-44. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
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7.11.5.9 EQEP
表 7-56, 表 7-57, 图 7-45, and 表 7-58 present timing conditions, requirements, and switching characteristics for
EQEP.
表7-56. EQEP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
表7-57. EQEP Timing Requirements
see 图7-45
NO.
PARAMETER
DESCRIPTION
MIN
2P(1) + 2
2P(1) + 2
2P(1) + 2
2P(1) + 2
2P(1) + 2
MAX
UNIT
ns
QEP1
QEP2
QEP3
QEP4
QEP5
tw(QEP)
Pulse duration, QEP_A/B
Pulse duration, QEP_I high
Pulse duration, QEP_I low
tw(QEPIH)
tw(QEPIL)
tw(QEPSH)
tw(QEPSL)
ns
ns
Pulse duration, QEP_S high
Pulse duration, QEP_S low
ns
ns
(1) P = sysclk period in ns
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
图7-45. EQEP Timing Requirements
表7-58. EQEP Switching Characteristics
DESCRIPTION
NO.
PARAMETER
td(QEP-CNTR)
MIN
MAX
UNIT
QEP6
Delay time, external clock to counter increment
24
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
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7.11.5.10 GPIO
表7-59, 表7-60, and 表7-61 present timing conditions, requirements, and switching characteristics for GPIO.
The device has three instances of the GPIO module.
• MCU_GPIO0
• GPIO0
• GPIO1
备注
GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO
module and x represents one of the input/output signals associated with the module.
For additional description information on the device GPIO, see the corresponding subsections within
Signal Descriptions and Detailed Description sections.
表7-59. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX UNIT
INPUT CONDITIONS
LVCMOS
0.2
0.2
6.6 V/ns
0.8 V/ns
SRI
Input slew rate
I2C OD FS
OUTPUT CONDITIONS
LVCMOS
3
3
10
pF
pF
CL
Output load capacitance
I2C OD FS
100
表7-60. GPIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
MODE
1.8 V
3.3 V
MIN
MAX UNIT
2P + 2.6(1)
2P + 3.5(1)
ns
ns
GPIO1 tw(GPIO_IN)
Pulse width, GPIOn_x
(1) P = functional clock period in ns.
表7-61. GPIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
BUFFER TYPE
MIN
MAX UNIT
0.975P(1)
-
LVCMOS
ns
ns
3.6
GPIO2 tw(GPIO_OUT)
Pulse width, GPIOn_x
I2C OD FS
160
(1) P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
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7.11.5.11 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
表7-62 presents timing conditions for GPMC.
表7-62. GPMC Timing Conditions
PARAMETER
MIN
1.65
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
4
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
133 MHz Synchronous Mode
All other modes
140
140
360
720
ps
ps
td(Trace Delay)
Propagation delay of each trace
td(Trace Mismatch
Propagation delay mismatch across all traces
200
ps
Delay)
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.11.5.11.1 GPMC and NOR Flash —Synchronous Mode
表 7-63 and 表 7-64 present timing requirements and switching characteristics for GPMC and NOR Flash -
Synchronous Mode.
表7-63. GPMC and NOR Flash Timing Requirements —Synchronous Mode
see 图7-46, 图7-47, and 图7-50
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
GPMC_FCLK = GPMC_FCLK =
100 MHz(1)
133 MHz(1)
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
Setup time, input data
GPMC_AD[15:0] valid before output
clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.61
0.92
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.86
2.09
2.09
1.61
0.86
3.41
2.09
2.09
0.92
3.41
ns
ns
ns
ns
ns
Hold time, input data
GPMC_AD[15:0] valid after output
clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Setup time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GPMC_WAIT[j](2) (3) valid before
output clock GPMC_CLK high
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
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表7-63. GPMC and NOR Flash Timing Requirements —Synchronous Mode (continued)
see 图7-46, 图7-47, and 图7-50
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
GPMC_FCLK = GPMC_FCLK =
100 MHz(1)
133 MHz(1)
F22 th(clkH-waitV)
Hold time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.09
2.09
ns
GPMC_WAIT[j](2) (3) valid after
output clock GPMC_CLK high
not_div_by_1_mode;
GPMC_FCLK_MUX;
2.09
2.09
ns
TIMEPARAGRANULARITY_X1
(1) GPMC_FCLK select
•
•
gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
(2) In GPMC_WAIT[j], j is equal to 0 or 1.
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-
Purpose Memory Controller (GPMC) section in the device TRM.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For not_div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
表7-64. GPMC and NOR Flash Switching Characteristics –Synchronous Mode
see 图7-46, 图7-47, 图7-48, 图7-49, and 图7-50
MIN
100 MHz
10.00
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(16)
UNIT
(2)
133 MHz
F0 1 / tc(clk)
F1 tw(clkH)
Period, output clock GPMC_CLK(15)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
7.52
ns
Typical pulse duration, output clock
GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0.475P
- 0.3(14)
0.475P
ns
ns
- 0.3(14)
F1 tw(clkL)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode;
GPMC_FCLK_MUX;
0.475P
- 0.3(14)
0.475P
- 0.3(14)
TIMEPARAGRANULARITY_X1
F2 td(clkH-csnV)
Delay time, output clock GPMC_CLK
rising edge to output chip select
GPMC_CSn[i] transition(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
F - 2.2
F + F - 2.2
3.75
F + ns
3.75
(5)
(5)
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK
rising edge to output chip select
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
E - 2.2
E + E - 2.2 E + 4.5 ns
3.18
(4)
(4)
GPMC_CSn[i] invalid(13)
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表7-64. GPMC and NOR Flash Switching Characteristics –Synchronous Mode (continued)
see 图7-46, 图7-47, 图7-48, 图7-49, and 图7-50
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(16)
UNIT
(2)
100 MHz
133 MHz
F4 td(aV-clk)
Delay time, output address
GPMC_A[27:1] valid to output clock
GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2.3 B + 4.5 B - 2.3 B + 4.5 ns
(2)
(2)
F5 td(clkH-aIV)
Delay time, output clock GPMC_CLK
rising edge to output address
GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3
4.5
-2.3
4.5 ns
F6 td(be[x]nV-clk)
Delay time, output lower byte enable
and command latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
B - 2.3 B + 1.9 B - 2.3 B + 1.9 ns
(2)
(2)
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1
enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK
rising edge to output lower byte
div_by_1_mode;
GPMC_FCLK_MUX;
D - D + 1.9 D - 2.3 D + 1.9 ns
2.3(3)
(3)
enable and command latch enable
TIMEPARAGRANULARITY_X1
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid(10)
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
(3)
(3)
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
(3)
(3)
F8 td(clkH-advn)
F9 td(clkH-advnIV)
F10 td(clkH-oen)
F11 td(clkH-oenIV)
F14 td(clkH-wen)
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
G - G + 4.5 G - 2.3 G + 4.5 ns
2.3(6)
(6)
GPMC_ADVn_ALE transition
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
D - 2.3 D + 4.5 D - 2.3 D + 4.5 ns
(3)
(3)
GPMC_ADVn_ALE invalid
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output write enable
GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
I - 2.3 I + 4.5 I - 2.3 I + 4.5 ns
(8)
(8)
F15 td(clkH-do)
F15 td(clkL-do)
F15 td(clkL-do).
F17 td(clkH-be[x]n)
Delay time, output clock GPMC_CLK
rising edge to output data
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
GPMC_AD[15:0] transition(10)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
(9)
(9)
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
GPMC_BE0n_CLE transition(10)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
(9)
(9)
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表7-64. GPMC and NOR Flash Switching Characteristics –Synchronous Mode (continued)
see 图7-46, 图7-47, 图7-48, 图7-49, and 图7-50
MIN
100 MHz
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(16)
UNIT
(2)
133 MHz
F17 td(clkL-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(9)
(9)
F17 td(clkL-be[x]n).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
(9)
(9)
F18 tw(csnV)
Pulse duration, output chip select
GPMC_CSn[i](13) low
Read
Write
Read
Write
A
A
C
C
A
A
C
C
ns
ns
ns
ns
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
F20 tw(advnV)
Pulse duration, output address valid
and address latch enable
GPMC_ADVn_ALE low
Read
Write
K
K
K
K
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(14)
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) For csn falling edge (CS activated):
•
Case GPMCFCLKDIVIDER = 0:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
Case GPMCFCLKDIVIDER = 0:
•
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– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
•
•
Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
•
Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
•
Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
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– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
•
Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2:
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) J = GPMC_FCLK(14)
(10) First transfer only for CLK DIV 1 mode.
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(16) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
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F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
GPMC_A[MSB:1]
Valid Address
F19
F6
F7
GPMC_BE0n_CLE
F19
GPMC_BE1n
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F12
D 0
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-46. GPMC and NOR Flash —Synchronous Single Read (GPMCFCLKDIVIDER = 0)
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F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F4
F6
GPMCA[MSB:1]
Valid Address
F7
F7
F9
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F13
F12
D 0
F22
F12
D 3
GPMC_AD[15:0]
GPMC_WAIT[j]
D 1
D 2
F21
GPMC_02
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-47. GPMC and NOR Flash —Synchronous Burst Read —4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1
F0
GPMC_CLK
GPMC_CSn[i]
F2
F3
F4
F6
Valid Address
GPMC_A[MSB:1]
F17
F17
F17
F17
F17
F17
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
D 0
D 3
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-48. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F6
F4
F7
GMPC_BE0n_CLE
Valid
F7
Valid
GPMC_BE1n
GPMC_A[27:17]
Address (MSB)
F5
F12
F13
F4
F12
GPMC_AD[15:0]
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-49. GPMC and Multiplexed NOR Flash —Synchronous Burst Read
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F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
F6
GPMC_A[27:17]
Address (MSB)
F17
F17
F17
F17
GPMC_BE1n
F17
F17
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
Address (LSB)
D 0
D 3
F22
F21
GPMC_WAIT[j]
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-50. GPMC and Multiplexed NOR Flash —Synchronous Burst Write
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7.11.5.11.2 GPMC and NOR Flash —Asynchronous Mode
表 7-65 and 表 7-66 present timing requirements and switching characteristics for GPMC and NOR Flash —
Asynchronous Mode.
表7-65. GPMC and NOR Flash Timing Requirements –Asynchronous Mode
see 图7-51, 图7-52, 图7-53, and 图7-55
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
FA5(1) tacc(d)
Data access time
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
FA2 tacc1-pgmode(d)
0(2)
Page mode successive data access time
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
P(3) ns
FA2 tacc2-pgmode(d)
1(1)
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
表7-66. GPMC and NOR Flash Switching Characteristics –Asynchronous Mode
see 图7-51, 图7-52, 图7-53, 图7-54, 图7-55, and 图7-56
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
N (12) ns
N (12)
133 MHz
FA0 tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
Write
FA1 tw(csnV)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
Write
Read
Write
A (1) ns
A (1)
FA3 td(csnV-advnIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
B - 2 (2) B + 2(2) ns
B - 2(2) B + 2(2)
FA4 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
C - 2(3) C + 2(3) ns
FA9 td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
J - 2(9)
J + 2(9) ns
TIMEPARAGRANULARITY_X1
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2(9)
J + 2(9) ns
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
K - 2(10) K + 2(10) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
L - 2(11) L + 2(11) ns
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
G (7)
ns
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表7-66. GPMC and NOR Flash Switching Characteristics –Asynchronous Mode (continued)
see 图7-51, 图7-52, 图7-53, 图7-54, 图7-55, and 图7-56
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
133 MHz
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
I - 2(8)
I + 2(8) ns
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX;
D (4)
ns
TIMEPARAGRANULARITY_X1
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
FA37 td(oenV-aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
E - 2(5) E + 2(5) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F - 2(6) F + 2(6) ns
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2
ns
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
J - 2(9)
J + 2(9) ns
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX;
2
ns
TIMEPARAGRANULARITY_X1
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
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OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data IN 0
Data IN 0
GPMC_WAIT[j]
GPMC_06
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-51. GPMC and NOR Flash —Asynchronous Read —Single Word
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GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
FA5
FA5
FA1
FA1
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
GPMC_A[MSB:1]
FA10
FA10
Valid
FA0
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-52. GPMC and NOR Flash —Asynchronous Read —32–Bit
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GPMC_FCLK
GPMC_CLK
FA20
Add3
FA20
Add1
FA21
FA20
Add2
FA1
GPMC_CSn[i]
FA9
Add0
Add4
GPMC_A[MSB:1]
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D0
D1
D2
D3
GPMC_WAIT[j]
GPMC_08
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-53. GPMC and NOR Flash —Asynchronous Read —Page Mode 4x16–Bit
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
GPMC_BE0n_CLE
GPMC_BE1n
Valid Address
FA0
FA10
FA10
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
GPMC_AD[15:0]
GPMC_WAIT[j]
FA29
Data OUT
GPMC_09
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-54. GPMC and NOR Flash —Asynchronous Write —Single Word
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GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
Address (MSB)
FA0
GPMC_A[27:17]
FA10
GPMC_BE0n_CLE
Valid
FA0
FA10
GPMC_BE1n
Valid
FA3
FA12
GPMC_ADVn_ALE
GPMC_OEn_REn
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_10
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
图7-55. GPMC and Multiplexed NOR Flash —Asynchronous Read —Single Word
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GPMC_FCLK
GPMC_CLK
GPMC_CSn[i]
FA1
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
FA28
GPMC_AD[15:0]
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-56. GPMC and Multiplexed NOR Flash —Asynchronous Write —Single Word
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7.11.5.11.3 GPMC and NAND Flash —Asynchronous Mode
表 7-67 and 表 7-68 present timing requirements and switching characteristics for GPMC and NAND Flash —
Asynchronous Mode.
表7-67. GPMC and NAND Flash Timing Requirements –Asynchronous Mode
see 图7-59
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
133 MHz
GNF12(1) tacc(d)
Access time, input data GPMC_AD[15:0](3)
div_by_1_mode;
GPMC_FCLK_MUX;
J(2) ns
TIMEPARAGRANULARITY_X1
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
表7-68. GPMC and NAND Flash Switching Characteristics –Asynchronous Mode
see 图7-57, 图7-58, 图7-59 and 图7-60
NO.
PARAMETER
MODE(4)
MIN
MAX UNIT
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
A
ns
TIMEPARAGRANULARITY_X1
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
B - 2
C - 2
D - 2
E - 2
F - 2
G - 2
C - 2
B + 2 ns
C + 2 ns
D + 2 ns
E + 2 ns
F + 2 ns
G + 2 ns
C + 2 ns
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
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表7-68. GPMC and NAND Flash Switching Characteristics –Asynchronous Mode (continued)
see 图7-57, 图7-58, 图7-59 and 图7-60
NO.
PARAMETER
MODE(4)
MIN
MAX UNIT
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F - 2
F + 2 ns
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX;
H
ns
TIMEPARAGRANULARITY_X1
GNF10 td(csnV-oenV)
GNF13 tw(oenV)
GNF14 tc(oen)
Delay time, output chip select GPMC_CSn[i](2)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
I - 2
I + 2 ns
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
K
ns
ns
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX;
L
TIMEPARAGRANULARITY_X1
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
M - 2
M + 2 ns
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
•
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF2
GNF6
GNF5
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF0
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-57. GPMC and NAND Flash —Command Latch Cycle
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GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF7
GNF6
GNF8
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF9
GNF0
GNF3
GNF4
Address
GPMC_AD[15:0]
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-58. GPMC and NAND Flash —Address Latch Cycle
GPMC_FCLK
GPMC_CSn[i]
GNF12
GNF10
GNF15
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
DATA
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
图7-59. GPMC and NAND Flash —Data Read Cycle
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GPMC_FCLK
GNF1
GNF6
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
DATA
GPMC_15
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
图7-60. GPMC and NAND Flash —Data Write Cycle
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7.11.5.12 I2C
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not fully
compliant to the I2C electrical specification. The speeds supported and exceptions are described per port below:
• I2C0, I2C1, I2C2, and I2C3
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
– Exceptions:
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C
specification because they are implemented with higher performance LVCMOS push-pull IOs that were
designed to support other signal functions that could not be implemented with I2C compatible IOs. The
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z
state.
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
• MCU_I2C0 and WKUP_I2C0
– Speeds:
• Standard-mode (up to 100 Kbits/s)
– 1.8 V
– 3.3 V
• Fast-mode (up to 400 Kbits/s)
– 1.8 V
– 3.3 V
• Hs-mode (up to 3.4 Mbits/s)
– 1.8 V
– Exceptions:
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So
Hs-mode is limited to 1.8-V operation.
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C
specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
备注
I2C3 has one or more signals which can be multiplexed to more than one pin. Timing is only valid for
specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are
defined in the SysConfig-PinMux Tool.
Refer to the Philips I2C-bus specification version 2.1 for timing details.
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For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
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7.11.5.13 MCAN
表7-69 and 表7-70 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
备注
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
表7-69. MCAN Timing Conditions
PARAMETER
MIN
2
MAX
15
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
5
20
表7-70. MCAN Switching Characteristics
NO.
PARAMETER
DESCRIPTION
Delay time, transmit shift register to MCANn_TX
Delay time, MCANn_RX to receive shift register
MIN
MAX
10
UNIT
ns
MCAN1 td(MCAN_TX)
MCAN2 td(MCAN_RX)
10
ns
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
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7.11.5.14 MCASP
备注
McASP has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.
表 7-71, 表 7-72, 图 7-61, 表 7-73, and 图 7-62 present timing conditions, requirements, and switching
characteristics for MCASP.
表7-71. MCASP Timing Conditions
PARAMETER
MIN
0.7
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay)
Propagation delay of each trace
100
1100
100
ps
ps
td(Trace Mismatch Delay)
Propagation delay mismatch across all traces
表7-72. MCASP Timing Requirements
see 图7-61
NO.
MODE(1)
MIN
20
MAX UNIT
ASP1 tc(AHCLKRX)
ASP2 tw(AHCLKRX)
ASP3 tc(ACLKRX)
ASP4 tw(ACLKRX)
Cycle time, MCASP[x]_AHCLKR/X(4)
ns
ns
0.5P(2)
-
Pulse duration, MCASP[x]_AHCLKR/X(4) high or low
Cycle time, MCASP[x]_ACLKR/X(4)
1.53
20
ns
ns
0.5R(3)
-
Pulse duration, MCASP[x]_ACLKR/X(4) high or low
1.53
Setup time, MCASP[x]_AFSR/X(4) input valid before
MCASP[x]_ACLKR/X(4)
ACLKR/X int
9.29
4
ns
ns
ns
ns
ASP5 tsu(AFSRX-ACLKRX)
ASP6 th(ACLKRX-AFSRX)
ASP7 tsu(AXR-ACLKRX)
ASP8 th(ACLKRX-AXR)
ACLKR/X ext in/out
ACLKR/X int
Hold time, MCASP[x]_AFSR/X(4) input valid after
MCASP[x]_ACLKR/X(4)
-1
ACLKR/X ext in/out
ACLKR/X int
1.6
9.29
4
Setup time, MCASP[x]_AXR(4) input valid before
MCASP[x]_ACLKR/X(4)
ACLKR/X ext in/out
ACLKR/X int
Hold time, MCASP[x]_AXR(4) input valid after
MCASP[x]_ACLKR/X(4)
-1
ACLKR/X ext in/out
1.6
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns. For details on AHCLKR/X clock source options, see the McASP Clocks table in the Multichannel Audio
Serial Port (MCASP) section of the Module Integration chapter found in the Technical Reference Manual.
(3) R = ACLKR/X period in ns.
(4) x in MCASP[x]_* is 0, 1 or 2
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ASP2
ASP2
ASP1
MCASP[x]_AHCLKR/X (Falling Edge Priority)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP4
ASP4
ASP3
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
图7-61. MCASP Timing Requirements
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表7-73. MCASP Switching Characteristics
see 图7-62
NO.
PARAMETER
DESCRIPTION
MODE(1)
MIN
20
MAX UNIT
ASP9 tc(AHCLKRX)
ASP10 tw(AHCLKRX)
ASP11 tc(ACLKRX)
ASP12 tw(ACLKRX)
Cycle time, MCASP[x]_AHCLKR/X(4)
ns
ns
ns
ns
Pulse duration, MCASP[x]_AHCLKR/X(4) high or low
Cycle time, MCASP[x]_ACLKR/X(4)
0.5P(2) - 2
20
Pulse duration, MCASP[x]_ACLKR/X(4) high or low
0.5R(3) - 2
-1
Delay time, MCASP[x]_ACLKR/X(4) transmit edge to
MCASP[x]_AFSR/X(4) output valid
ACLKR/X int
7.25
ns
12.84
ASP13 td(ACLKRX-AFSRX)
ASP14 td(ACLKX-AXR)
ASP15 tdis(ACLKX-AXR)
ACLKR/X ext in/out
ACLKR/X int
-15.29
-1
Delay time, MCASP[x]_ACLKX(4) transmit edge to
MCASP[x]_AXR(4) output valid
7.25
ns
12.84
ACLKR/X ext in/out
ACLKR/X int
-15.29
-1
Disable time, MCASP[x]_ACLKX(4) transmit edge to
MCASP[x]_AXR(4) output high impedance
7.25
ns
14
ACLKR/X ext in/out
-14.9
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns. For details on AHCLKR/X clock source options, see the McASP Clocks table in the Multichannel Audio
Serial Port (MCASP) section of the Module Integration chapter found in the Technical Reference Manual.
(3) R = ACLKR/X period in ns.
(4) x in MCASP[x]_* is 0, 1 or 2
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ASP10
ASP10
ASP9
MCASP[x]_AHCLKR/X (Falling Edge Priority)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP12
ASP12
ASP11
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)
ASP13
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCASP[x]_AXR[x] (Data Out/Transmit)
ASP13
ASP13
ASP13
ASP14
ASP15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
图7-62. MCASP Switching Characteristics
For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.
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7.11.5.15 MCSPI
备注
McSPI has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
表7-74 presents timing conditions for MCSPI.
表7-74. MCSPI Timing Conditions
PARAMETER
MIN
2
MAX
8.5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
6
12
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
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7.11.5.15.1 MCSPI —Controller Mode
表 7-75, 图 7-63, 表 7-76, and 图 7-64 present timing requirements and switching characteristics for SPI –
Controller Mode.
表7-75. MCSPI Timing Requirements –Controller Mode
see 图7-63
NO.
SM4
SM5
PARAMETER
DESCRIPTION
MIN
2.8
3
MAX
UNIT
ns
tsu(POCI-SPICLK)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
th(SPICLK-POCI)
ns
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SM1
SM3
SM2
SPI_SCLK (OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SM5
SM4
SM5
Bit n-2
SM4
Bit n-1
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_02
图7-63. SPI Controller Mode Receive Timing
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表7-76. MCSPI Switching Characteristics - Controller Mode
see 图7-64
NO.
PARAMETER
MIN
20
0.5P - 1(1)
0.5P - 1(1)
-3
MAX UNIT
SM1
SM2
SM3
SM6
SM7
SM8
tc(SPICLK)
Cycle time, SPIn_CLK
ns
ns
ns
tw(SPICLKL)
Pulse duration, SPIn_CLK low
tw(SPICLKH)
td(SPICLK-PICO)
td(CS-PICO)
Pulse duration, SPIn_CLK high
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
Delay time, SPIn_CSi active to SPIn_CLK first edge
2.5
ns
ns
ns
ns
ns
ns
5
td(CS-SPICLK)
PHA = 0
PHA = 1
PHA = 0
PHA = 1
B - 4 (3)
A - 4 (2)
A - 4(2)
B - 4(3)
SM9
td(SPICLK-CS)
Delay time, SPIn_CLK last edge to SPIn_CSi inactive
(1) P = SPI_CLK period in ns.
(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =
(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
图7-64. SPI Controller Mode Transmit Timing
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7.11.5.15.2 MCSPI —Peripheral Mode
表 7-77, 图 7-65, 表 7-78, and 图 7-66 present timing requirements and switching characteristics for SPI –
Peripheral Mode.
表7-77. MCSPI Timing Requirements –Peripheral Mode
see 图7-65
NO.
SS1
SS2
SS3
SS4
SS5
SS8
SS9
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
tc(SPICLK)
Cycle time, SPIn_CLK
20
0.45P(1)
0.45P(1)
tw(SPICLKL)
Pulse duration, SPIn_CLK low
ns
tw(SPICLKH)
Pulse duration, SPIn_CLK high
ns
tsu(PICO-SPICLK)
th(SPICLK-PICO)
tsu(CS-SPICLK)
th(SPICLK-CS)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
Setup time, SPIn_CSi valid before SPIn_CLK first edge
Hold time, SPIn_CSi valid after SPIn_CLK last edge
5
5
5
5
ns
ns
ns
ns
(1) P = SPIn_CLK period in ns.
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PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SPI_SCLK (IN)
SPI_SCLK (IN)
SS1
SS2
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
SPI_CS[i] (IN)
PHA=1
EPOL=1
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SPI_SCLK (IN)
SPI_SCLK (IN)
SS1
SS3
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_04
图7-65. SPI Peripheral Mode Receive Timing
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表7-78. MCSPI Switching Characteristics –Peripheral Mode
see 图7-66
NO.
PARAMETER
td(SPICLK-POCI)
tsk(CS-POCI)
DESCRIPTION
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
MIN
2
MAX
17.12
UNIT
ns
SS6
SS7
20.95
ns
PHA=0
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SS1
SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
图7-66. SPI Peripheral Mode Transmit Timing
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7.11.5.16 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 subsections within
Signal Descriptions and Detailed Description sections.
备注
Some operating modes require software configuration of the MMC DLL delay settings, as shown in 表
7-79 and 表7-97.
The modes which show a value of "Tuning" in the ITAPDLYSEL column of 表7-79 and 表7-97 require
a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming Guide in
the device TRM for more information on the tuning algorithm and configuration of input delays
required to optimize input timing.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
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7.11.5.16.1 MMC0 - eMMC/SD/SDIO Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
• Legacy SDR
• High Speed SDR
• HS200
MMC0 interface is also compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default Speed
• High Speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I DDR50
• UHS–I SDR104
表7-79 presents the required DLL software configuration settings for MMC0 timing modes.
表7-79. MMC0 DLL Delay Mapping for all Timing Modes
REGISTER NAME
BIT FIELD
MMCSD0_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD0_SS_PHY_CTRL_5_REG
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
8-bit PHY operating
1.8 V, 25 MHz
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x6
0x0
0x0
0xF
0xF
0xC
0x9
0x6
0x0
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
NA(1)
NA(1)
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
0x7
Legacy
SDR
8-bit PHY operating
3.3 V, 25 MHz
8-bit PHY operating
1.8 V, 50 MHz
NA(1)
High
Speed
SDR
8-bit PHY operating
3.3 V, 50 MHz
NA(1)
8-bit PHY operating
1.8 V, 200 MHz
HS200
Tuning(2)
0x0
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
0x0
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
Tuning(2)
Tuning(2)
Tuning(2)
UHS-I
DDR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
(1) NA means Not Applicable
(2) Tuning means this mode requires a tuning algorithm to be used for optimal input timing
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表7-80 presents timing conditions for MMC0.
表7-80. MMC0 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Legacy SDR @ 3.3 V
High Speed SDR@ 3.3V
Default Speed
0.69
0.14
2.06 V/ns
High Speed
Legacy SDR @ 1.8 V
UHS-I SDR12
SRI
Input slew rate
1.44 V/ns
1.34 V/ns
High Speed SDR @ 1.8 V
UHS-I SDR25
0.3
1
UHS-I DDR50
2
V/ns
OUTPUT CONDITIONS
HS200
UHS-I SDR104
1
1
10
12
pF
pF
CL
Output load capacitance
All other modes
PCB CONNECTIVITY REQUIREMENTS
Legacy SDR
High Speed SDR
HS200
126
756
ps
ps
Default Speed
High Speed
UHS-I SDR12
UHS-I SDR25
UHS-I SDR50
UHS-I SDR104
td(Trace Delay)
Propagation delay of each trace
126
239
1386
UHS-I DDR50
1134
8
ps
ps
High Speed SDR
HS200
High Speed
UHS-I SDR104
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
UHS-I DDR50
20
ps
ps
All other modes
100
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7.11.5.16.1.1 Legacy SDR Mode
表 7-81, 图 7-67, 表 7-82, and 图 7-68 present timing requirements and switching characteristics for MMC0 –
Legacy SDR Mode.
表7-81. MMC0 Timing Requirements –Legacy SDR Mode
see 图7-67
IO
NO.
Operating
Voltage
MIN
MAX
UNIT
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
4.2
2.15
0.87
1.67
4.2
ns
ns
ns
ns
ns
ns
ns
ns
LSDR1
LSDR2
LSDR3
LSDR4
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
2.15
0.87
1.67
图7-67. MMC0 –Legacy SDR –Receive Mode
表7-82. MMC0 Switching Characteristics –Legacy SDR Mode
see 图7-68
IO
NO.
PARAMETER
Operating
Voltage
MIN
MAX UNIT
fop(clk)
tc(clk)
tw(clkH)
tw(clkL)
Operating frequency, MMC0_CLK
Cycle time, MMC0_CLK
25
MHz
ns
LSDR5
LSDR6
LSDR7
40
18.7
18.7
-2.1
-1.8
-2.1
-1.8
Pulse duration, MMC0_CLK high
Pulse duration, MMC0_CLK low
ns
ns
1.8 V
3.3 V
1.8 V
3.3 V
2.1
2.2
2.1
2.2
ns
LSDR8
LSDR9
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
ns
ns
td(clkL-dV)
ns
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图7-68. MMC0 –Legacy SDR –Transmit Mode
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7.11.5.16.1.2 High Speed SDR Mode
表 7-83, 图 7-69, 表 7-84, and 图 7-70 present timing requirements and switching characteristics for MMC0 –
High Speed SDR Mode.
表7-83. MMC0 Timing Requirements –High Speed SDR Mode
see 图7-69
IO
NO.
Operating
Voltage
MIN
MAX UNIT
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
1.8 V
3.3 V
2.15
2.24
1.27
1.66
2.15
2.24
1.27
1.66
ns
ns
ns
ns
ns
ns
ns
ns
HSSDR1
HSSDR2
HSSDR3
HSSDR4
tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
图7-69. MMC0 –High Speed SDR Mode –Receive Mode
表7-84. MMC0 Switching Characteristics –High Speed SDR Mode
see 图7-70
IO
NO.
PARAMETER
Operating
Voltage
MIN
MAX UNIT
fop(clk)
tc(clk)
tw(clkH)
tw(clkL)
Operating frequency, MMC0_CLK
Cycle time, MMC0_CLK
50
MHz
ns
HSSDR5
HSSDR6
HSSDR7
20
9.2
Pulse duration, MMC0_CLK high
Pulse duration, MMC0_CLK low
ns
9.2
ns
1.8 V
3.3 V
1.8 V
3.3 V
-1.55
-1.8
-1.55
-1.8
3.05
2.2
ns
HSSDR8
HSSDR9
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
ns
3.05
2.2
ns
td(clkL-dV)
ns
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图7-70. MMC0 –High Speed SDR Mode –Transmit Mode
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7.11.5.16.1.3 HS200 Mode
表7-85 and 图7-71 present switching characteristics for MMC0 –HS200 Mode.
表7-85. MMC0 Switching Characteristics –HS200 Mode
see 图7-71
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
HS2005
HS2006
HS2007
HS2008
HS2009
tc(clk)
Cycle time, MMC0_CLK
5
2.12
2.12
1.07
1.07
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
3.21
3.21
ns
ns
图7-71. MMC0 –HS200 Mode –Transmit Mode
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7.11.5.16.1.4 Default Speed Mode
表 7-86, 图 7-72, 表 7-87, and 图 7-73 present timing requirements and switching characteristics for MMC0 –
Default Speed Mode.
表7-86. Timing Requirements for MMC0 –Default Speed Mode
see 图7-72
NO.
DS1
DS2
DS3
DS4
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
DS2
DS4
DS1
DS3
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-72. MMC0 –Default Speed –Receive Mode
表7-87. Switching Characteristics for MMC0 –Default Speed Mode
see 图7-73
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMC0_CLK
40
18.7
18.7
- 1.8
- 1.8
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition
2.2
2.2
ns
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
图7-73. MMC0 –Default Speed –Transmit Mode
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7.11.5.16.1.5 High Speed Mode
表 7-88, 图 7-74, 表 7-89, and 图 7-75 present timing requirements and switching characteristics for MMC0 –
High Speed Mode.
表7-88. Timing Requirements for MMC0 –High Speed Mode
see 图7-74
NO.
HS1
HS2
HS3
HS4
MIN
2.24
1.66
2.24
1.66
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
HS1
HS3
HS2
HS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-74. MMC0 –High Speed –Receive Mode
表7-89. Switching Characteristics for MMC0 –High Speed Mode
see 图7-75
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
Cycle time. MMC0_CLK
20
9.2
tw(clkH)
Pulse duration, MMC0_CLK high
ns
tw(clkL)
Pulse duration, MMC0_CLK low
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition
-1.8
-1.8
2.2
2.2
ns
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-75. MMC0 –High Speed –Transmit Mode
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7.11.5.16.1.6 UHS–I SDR12 Mode
表 7-90, 图 7-76, 表 7-91, and 图 7-77 present timing requirements and switching characteristics for MMC0 –
UHS-I SDR12 Mode.
表7-90. Timing Requirements for MMC0 –UHS-I SDR12 Mode
see 图7-76
NO.
MIN
4.2
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
SDR124 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
0.87
4.2
ns
ns
0.87
ns
MMC[x]_CLK
SDR122
SDR124
SDR121
SDR123
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-76. MMC0 –UHS-I SDR12 –Receive Mode
表7-91. Switching Characteristics for MMC0 –UHS-I SDR12 Mode
see 图7-77
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
25
SDR125 tc(clk)
Cycle time, MMC0_CLK
40
18.7
18.7
1.5
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkL-cmdV)
SDR129 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
8.6
8.6
ns
1.5
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
图7-77. MMC0 –UHS-I SDR12 –Transmit Mode
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7.11.5.16.1.7 UHS–I SDR25 Mode
表 7-92, 图 7-78, 表 7-93, and 图 7-79 present timing requirements and switching characteristics for MMC0 –
UHS-I SDR25 Mode.
表7-92. Timing Requirements for MMC0 –UHS-I SDR25 Mode
see 图7-78
NO.
MIN
2.15
1.27
2.15
1.27
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
ns
ns
ns
MMC[x]_CLK
SDR252
SDR254
SDR251
SDR253
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-78. MMC0 –UHS-I SDR25 –Receive Mode
表7-93. Switching Characteristics for MMC0 –UHS-I SDR25 Mode
see 图7-79
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
SDR255 tc(clk)
Cycle time, MMC0_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkL-cmdV)
SDR259 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
8.1
8.1
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
图7-79. MMC0 –UHS-I SDR25 –Transmit Mode
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7.11.5.16.1.8 UHS–I SDR50 Mode
表7-94 and 图7-80 presents switching characteristics for MMC0 –UHS-I SDR50 Mode.
表7-94. Switching Characteristics for MMC0 –UHS-I SDR50 Mode
see 图7-80
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
100
SDR505 tc(clk)
Cycle time, MMC0_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkL-cmdV)
SDR509 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
SDR505
SDR506
SDR507
MMC[x]_CLK
SDR508
SDR508
MMC[x]_CMD
SDR509
SDR509
MMC[x]_DAT[3:0]
图7-80. MMC0 –UHS-I SDR50 –Transmit Mode
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7.11.5.16.1.9 UHS–I DDR50 Mode
表7-95 and 图7-81 present switching characteristics for MMC0 –UHS-I DDR50 Mode.
表7-95. Switching Characteristics for MMC0 –UHS-I DDR50 Mode
see 图7-81
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMC0_CLK
20
9.2
tw(clkH)
tw(clkL)
td(clk-cmdV)
td(clk-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK transition to MMC0_DAT[3:0] transition
1.12
1.12
6.43
6.43
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
图7-81. MMC0 –UHS-I DDR50 –Transmit Mode
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7.11.5.16.1.10 UHS–I SDR104 Mode
表7-96 and 图7-82 present switching characteristics for MMC0 –UHS-I SDR104 Mode.
表7-96. Switching Characteristics for MMC0 –UHS-I SDR104 Mode
see 图7-82
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMC0_CLK
200
SDR1045 tc(clk)
Cycle time, MMC0_CLK
5
2.12
2.12
1.07
1.07
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkL-cmdV)
SDR1049 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
ns
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
3.21
3.21
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
MMC[x]_CMD
SDR1049
SDR1049
MMC[x]_DAT[3:0]
图7-82. MMC0 –UHS-I SDR104 –Transmit Mode
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7.11.5.16.2 MMC1/MMC2 - SD/SDIO Interface
MMC1/MMC2 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I DDR50
• UHS–I SDR104
表7-97 presents the required DLL software configuration settings for MMC1/2 timing modes.
表7-97. MMC1/MMC2 DLL Delay Mapping for all Timing Modes
MMCSD1_SS_PHY_CTRL_4_REG/
MMCSD2_SS_PHY_CTRL_4_REG
MMCSD1_SS_PHY_CTRL_5_REG/
MMCSD2_SS_PHY_CTRL_5_REG
REGISTER NAME
BIT FIELD
[20]
[15:12]
[8]
[4:0]
[2:0]
BIT FIELD NAME
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0xF
0xF
0xC
0x9
0x6
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x7
0x7
0x7
0x7
0x7
0x7
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
Tuning(1)
Tuning(1)
Tuning(1)
UHS-I
DDR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
(1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing
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表7-98 presents timing conditions for MMC1.
表7-98. MMC1/MMC2 Timing Conditions
PARAMETER
MIN
MAX UNIT
Input Conditions
Default Speed
High Speed
0.69
2.06 V/ns
1.34 V/ns
UHS–I SDR12
UHS–I SDR25
SRI
Input slew rate
0.34
1
2
V/ns
pF
UHS–I DDR50
Output Conditions
CL
Output load capacitance
All modes
1
10
PCB Connectivity Requirements
239
126
1134
1386
ps
ps
UHS–I DDR50
td(Trace Delay)
Propagation delay of each trace
All other modes
High Speed
UHS–I SDR104
8
ps
td(Trace Mismatch
Propagation delay mismatch across all
traces
20
ps
ps
UHS–I DDR50
Delay)
All other modes
100
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7.11.5.16.2.1 Default Speed Mode
表 7-99, 图 7-83, 表 7-100, and 图 7-84 present timing requirements and switching characteristics for MMC1/
MMC2 –Default Speed Mode.
表7-99. Timing Requirements for MMC1/MMC2 –Default Speed Mode
see 图7-83
NO.
DS1
DS2
DS3
DS4
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
DS2
DS4
DS1
DS3
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-83. MMC1/MMC2 –Default Speed –Receive Mode
表7-100. Switching Characteristics for MMC1/MMC2 –Default Speed Mode
see 图7-84
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
25
DS5
DS6
DS7
DS8
DS9
tc(clk)
Cycle time, MMCx_CLK
40
18.7
18.7
- 1.8
- 1.8
tw(clkH)
Pulse duration, MMCx_CLK high
ns
tw(clkL)
Pulse duration, MMCx_CLK low
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMCx_CLK falling edge to MMCx_CMD transition
Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition
2.2
2.2
ns
ns
DS5
DS6
DS7
MMC[x]_CLK
MMC[x]_CMD
DS8
DS9
MMC[x]_DAT[3:0]
图7-84. MMC1/MMC2 –Default Speed –Transmit Mode
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7.11.5.16.2.2 High Speed Mode
表 7-101, 图 7-85, 表 7-102, and 图 7-86 present timing requirements and switching characteristics for MMC1/
MMC2 –High Speed Mode.
表7-101. Timing Requirements for MMC1/MMC2 –High Speed Mode
see 图7-85
NO.
HS1
HS2
HS3
HS4
MIN
2.24
1.66
2.24
1.66
MAX
UNIT
ns
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
HS1
HS3
HS2
HS4
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-85. MMC1/MMC2 –High Speed –Receive Mode
表7-102. Switching Characteristics for MMC1/MMC2 –High Speed Mode
see 图7-86
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
HS5
HS6
HS7
HS8
HS9
tc(clk)
Cycle time. MMCx_CLK
20
9.2
tw(clkH)
Pulse duration, MMCx_CLK high
ns
tw(clkL)
Pulse duration, MMCx_CLK low
9.2
ns
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMCx_CLK falling edge to MMCx_CMD transition
Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition
- 1.8
- 1.8
2.2
2.2
ns
ns
HS5
HS6
HS7
MMC[x]_CLK
HS8
HS9
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-86. MMC1/MMC2 –High Speed –Transmit Mode
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7.11.5.16.2.3 UHS–I SDR12 Mode
表 7-103, 图 7-87, 表 7-104, and 图 7-88 present timing requirements and switching characteristics for MMC1/
MMC2 –UHS-I SDR12 Mode.
表7-103. Timing Requirements for MMC1/MMC2 –UHS-I SDR12 Mode
see 图7-87
NO.
MIN
MAX
UNIT
ns
SDR121 tsu(cmdV-clkH)
SDR122 th(clkH-cmdV)
SDR123 tsu(dV-clkH)
SDR124 th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
4.2
0.87
4.2
ns
ns
0.87
ns
MMC[x]_CLK
SDR122
SDR124
SDR121
SDR123
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-87. MMC1/MMC2 –UHS-I SDR12 –Receive Mode
表7-104. Switching Characteristics for MMC1/MMC2 –UHS-I SDR12 Mode
see 图7-88
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
25
SDR125 tc(clk)
Cycle time, MMCx_CLK
40
18.7
18.7
1.5
SDR126 tw(clkH)
SDR127 tw(clkL)
SDR128 td(clkL-cmdV)
SDR129 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
8.6
8.6
ns
1.5
ns
SDR125
SDR126
SDR127
MMC[x]_CLK
SDR128
SDR128
MMC[x]_CMD
SDR129
SDR129
MMC[x]_DAT[3:0]
图7-88. MMC1/MMC2 –UHS-I SDR12 –Transmit Mode
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7.11.5.16.2.4 UHS–I SDR25 Mode
表 7-105, 图 7-89, 表 7-106, and 图 7-90 present timing requirements and switching characteristics for MMC1/
MMC2 –UHS-I SDR25 Mode.
表7-105. Timing Requirements for MMC1/MMC2 –UHS-I SDR25 Mode
see 图7-89
NO.
MIN
2.15
1.27
2.15
1.27
MAX
UNIT
ns
SDR251 tsu(cmdV-clkH)
SDR252 th(clkH-cmdV)
SDR253 tsu(dV-clkH)
SDR254 th(clkH-dV)
Setup time, MMCx_CMD valid before MMCx_CLK rising edge
Hold time, MMCx_CMD valid after MMCx_CLK rising edge
Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge
Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge
ns
ns
ns
MMC[x]_CLK
SDR252
SDR254
SDR251
SDR253
MMC[x]_CMD
MMC[x]_DAT[3:0]
图7-89. MMC1/MMC2 –UHS-I SDR25 –Receive Mode
表7-106. Switching Characteristics for MMC1/MMC2 –UHS-I SDR25 Mode
see 图7-90
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
SDR255 tc(clk)
Cycle time, MMCx_CLK
20
9.2
9.2
2.4
2.4
SDR256 tw(clkH)
SDR257 tw(clkL)
SDR258 td(clkL-cmdV)
SDR259 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
8.1
8.1
ns
ns
SDR255
SDR256
SDR257
MMC[x]_CLK
SDR258
SDR258
MMC[x]_CMD
SDR259
SDR259
MMC[x]_DAT[3:0]
图7-90. MMC1/MMC2 –UHS-I SDR25 –Transmit Mode
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7.11.5.16.2.5 UHS–I SDR50 Mode
表7-107 and 图7-91 presents switching characteristics for MMC1/MMC2 –UHS-I SDR50 Mode.
表7-107. Switching Characteristics for MMC1/MMC2 –UHS-I SDR50 Mode
see 图7-91
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
100
SDR505 tc(clk)
Cycle time, MMCx_CLK
10
4.45
4.45
1.2
SDR506 tw(clkH)
SDR507 tw(clkL)
SDR508 td(clkL-cmdV)
SDR509 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
SDR505
SDR506
SDR507
MMC[x]_CLK
SDR508
SDR508
MMC[x]_CMD
SDR509
SDR509
MMC[x]_DAT[3:0]
图7-91. MMC1/MMC2 –UHS-I SDR50 –Transmit Mode
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7.11.5.16.2.6 UHS–I DDR50 Mode
表7-108 and 图7-92 present switching characteristics for MMC1/MMC2 –UHS-I DDR50 Mode.
表7-108. Switching Characteristics for MMC1/MMC2 –UHS-I DDR50 Mode
see 图7-92
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
50
DDR505
DDR506
DDR507
DDR508
DDR509
tc(clk)
Cycle time, MMCx_CLK
20
9.2
tw(clkH)
tw(clkL)
td(clk-cmdV)
td(clk-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
9.2
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK transition to MMCx_DAT[3:0] transition
1.12
1.12
6.43
6.43
ns
ns
DDR505
DDR506
DDR507
MMC[x]_CLK
MMC[x]_CMD
DDR508
DDR509
DDR509
MMC[x]_DAT[3:0]
图7-92. MMC1/MMC2 –UHS-I DDR50 –Transmit Mode
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7.11.5.16.2.7 UHS–I SDR104 Mode
表7-109 and 图7-93 present switching characteristics for MMC1/MMC2 –UHS-I SDR104 Mode.
表7-109. Switching Characteristics for MMC1/MMC2 –UHS-I SDR104 Mode
see 图7-93
NO.
PARAMETER
MIN
MAX
UNIT
MHz
ns
fop(clk)
Operating frequency, MMCx_CLK
200
SDR1045 tc(clk)
Cycle time, MMCx_CLK
5
2.12
2.12
1.07
1.07
SDR1046 tw(clkH)
SDR1047 tw(clkL)
SDR1048 td(clkL-cmdV)
SDR1049 td(clkL-dV)
Pulse duration, MMCx_CLK high
ns
Pulse duration, MMCx_CLK low
ns
Delay time, MMCx_CLK rising edge to MMCx_CMD transition
Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition
3.21
3.21
ns
ns
SDR1045
SDR1046
SDR1047
MMC[x]_CLK
SDR1048
SDR1048
MMC[x]_CMD
SDR1049
SDR1049
MMC[x]_DAT[3:0]
图7-93. MMC1/MMC2 –UHS-I SDR104 –Transmit Mode
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7.11.5.17 OLDI
7.11.5.17.1 OLDI0 Switching Characteristics
表7-110 and 图7-94 present switching characteristics for OLDI0.
表7-110. OLDI0 Switching Characteristics
NO.
PARAMETER
MODE
MIN
TYP
MAX UNIT
Rise time, OLDI0_CLK[1:0]P,
OLDI0_CLK[1:0]N, OLDI0_A[7:0]P,
and OLDI0_A[7:0]N
Slow(1)
0.5
0.25
ns
ns
ns
ns
OLDI1 tt(LHTT)
Fast(2)
Slow(1)
Fast(2)
Fall time, OLDI0_CLK[1:0]P,
OLDI0_CLK[1:0]N, OLDI0_A[7:0]P,
and OLDI0_A[7:0]N
0.5
OLDI2 tt(HLTT)
0.25
OLDI3 tc(CLK)
OLDI4 tw(BIT)
Cycle time, OLDI0_CLK[1:0]P and OLDI0_CLK[1:0]N
Bit width, OLDI0_A[7:0]P and OLDI0_A[7:0]N
6.06
110.01
ns
ns
(1/7)OLDI3
Bit 1 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
OLDI5 td(BIT1)
OLDI6 td(BIT0)
OLDI7 td(BIT6)
OLDI8 td(BIT5)
OLDI9 td(BIT4)
OLDI10 td(BIT3)
- (0.1)OLDI3
(0.1)OLDI3
ns
ns
ns
ns
ns
ns
Bit 0 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(1/7)OLDI3
- (0.1)OLDI3
(1/7) OLDI3
+ (0.1)OLDI3
Bit 6 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(2/7)OLDI3
- (0.1)OLDI3
(2/7) OLDI3
+ (0.1)OLDI3
Bit 5 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(3/7)OLDI3
- (0.1)OLDI3
(3/7) OLDI3
+ (0.1)OLDI3
Bit 4 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(4/7)OLDI3
- (0.1)OLDI3
(4/7) OLDI3
+ (0.1)OLDI3
Bit 3 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(5/7)OLDI3
- (0.1)OLDI3
(5/7) OLDI3
+ (0.1)OLDI3
Bit 2 delay time, OLDI0_CLK[1:0]P and
OLDI0_CLK[1:0]N to OLDI0_A[7:0]P and
OLDI0_A[7:0]N
(6/7)OLDI3
- (0.1)OLDI3
(6/7) OLDI3
+ (0.1)OLDI3
OLDI11 td(BIT2)
ns
ps
Skew, OLDI0_A[7:0]P and OLDI0_A[7:0]N relative to
any other OLDI0_A[7:0]P and OLDI0_A[7:0]N
OLDI12 tsk(TCCS)
50
(1) Slow mode: TXDRV[3:0] = 0100b without back termination (RTERM_EN = 0b with 100Ωdifferential termination on far-end only)
(2) Fast mode: TXDRV[3:0] = 1000b with back termination (RTERM_EN = 1b with 100Ωdifferential termination on far-end only, or
RTERM_EN = 0b with 100Ωdifferential termination on near-end and far-end)
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OLDI3
OLDI1, OLDI2
80%
20%
OLDI0_CLK[1:0]P
OLDI0_CLK[1:0]N
80%
20%
OLDI11
OLDI10
OLDI9
OLDI8
OLDI7
OLDI6
OLDI5
OLDI4
OLDI1, OLDI2
OLDI0_A[7:0]P
80%
20%
bit 2
bit 1
bit 0
bit 6
bit 5
bit 4
bit 3
OLDI0_A[7:0]N
图7-94. OLDI0 Switching Characteristics
For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device
TRM.
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7.11.5.18 OSPI
OSPI0 offers two data capture modes, PHY mode and Tap mode.
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each
reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle
of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the
receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data
capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the
OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO
looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS
output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when
using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the
Internal PHY Loopback or Internal Pad Loopback clocking topologies.
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture
delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide
by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the
receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture
clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an
OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
节 7.11.5.18.1 defines timing requirements and switching characteristics associated with PHY mode and 节
7.11.5.18.2 defines timing requirements and switching characteristics associated with Tap mode.
表7-111 presents timing conditions for OSPI0.
表7-111. OSPI0 Timing Conditions
PARAMETER
MODE
MIN
1
MAX UNIT
INPUT CONDITIONS
SRI Input slew rate
OUTPUT CONDITIONS
6
V/ns
pF
CL
Output load capacitance
3
10
PCB CONNECTIVITY REQUIREMENTS
No Loopback
Propagation delay of OSPI0_CLK trace
Internal PHY Loopback
Internal Pad Loopback
450
ps
td(Trace Delay)
Propagation delay of OSPI0_LBCLKO
trace
External Board Loopback
DQS
2L(1) - 30
L(1) - 30
2L(1) + 30
L(1) + 30
ps
ps
Propagation delay of OSPI0_DQS trace
Propagation delay mismatch of
OSPI0_D[7:0] and OSPI0_CSn[3:0]
relative to OSPI0_CLK
td(Trace Mismatch
All modes
60
ps
Delay)
(1) L = Propagation delay of OSPI0_CLK trace
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7.11.5.18.1 OSPI0 PHY Mode
7.11.5.18.1.1 OSPI0 With PHY Data Training
Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating
frequency. A data training method may be implemented to dynamically configure optimal read and write timing.
Implementing data training enables proper operation across temperature with a specific process, voltage, and
frequency operating condition, while achieving a higher operating frequency.
Data transmit and receive timing parameters are not defined for the data training use case since they are
dynamically adjusted based on the operating condition.
表 7-112 defines DLL delays required for OSPI0 with Data Training. 表 7-113, 图 7-95, 表 7-114, and 图 7-96
present timing requirements and switching characteristics for OSPI0 with Data Training.
表7-112. OSPI0 DLL Delay Mapping for PHY Data Training
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
PHY_CONFIG_TX_DLL_DELAY_FLD,
DELAY VALUE
Transmit
All modes
Receive
(1)
(2)
All modes
PHY_CONFIG_RX_DLL_DELAY_FLD
(1) Transmit DLL delay value determined by training software
(2) Receive DLL delay value determined by training software
表7-113. OSPI0 Timing Requirements –PHY Data Training
see 图7-95
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
(1)
O15 tsu(D-LBCLK)
O16 th(LBCLK-D)
DDR with DQS
ns
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
(1)
DDR with DQS
ns
(1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum
data valid window.
OSPI_DQS
O15 O16 O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
图7-95. OSPI0 Timing Requirements –PHY Data Training, DDR with DQS
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表7-114. OSPI Switching Characteristics –PHY Data Training
See 图7-96
NO.
PARAMETER
MODE
1.8V, DDR
3.3V, DDR
DDR
MIN
6.02
MAX UNIT
7.52
7.52
ns
ns
ns
ns
O1
tc(CLK)
Cycle time, OSPI0_CLK
7.52
O2
O3
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
DDR
((0.475P(1)) +
(0.975M(2)R(4)) +
(0.04TD(5)) - 1)
((0.525P(1)) +
(1.025M(2)R(4)) +
(0.11TD(5)) + 1)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
O4
td(CSn-CLK)
DDR
ns
((0.475P(1)) +
(0.975N(3)R(4)) -
(0.04TD(5)) - 1)
((0.525P(1)) +
(1.025N(3)R(4)) -
(0.11TD(5)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
O5
O6
td(CLK-CSn)
DDR
DDR
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
(6)
(6)
td(CLK-D)
(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns
(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD
(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data
valid window.
OSPI_CSn
O4
O3
O5
OSPI_CLK
OSPI_D[i:0]
O2
O6
O6
O1
OSPI_TIMING_01
图7-96. OSPI0 Switching Characteristics –PHY DDR Data Training
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7.11.5.18.1.2 OSPI0 Without Data Training
备注
Timing parameters defined in this section are only applicable when data training is not implemented
and DLL delays are configured as described in 表7-115 and 表7-118.
7.11.5.18.1.2.1 OSPI0 PHY SDR Timing
表 7-115 defines DLL delays required for OSPI0 PHY SDR Mode. 表 7-116, 图 7-97, 图 7-98, 表 7-117, and 图
7-99 present timing requirements and switching characteristics for OSPI0 PHY SDR Mode.
表7-115. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
All modes
Receive
PHY_CONFIG_TX_DLL_DELAY_FLD,
0x0
0x0
All modes
PHY_CONFIG_RX_DLL_DELAY_FLD
表7-116. OSPI0 Timing Requirements –PHY SDR Mode
see 图7-97 and 图7-98
NO.
MODE
MIN
MAX UNIT
1.8V, SDR with Internal PHY Loopback
3.3V, SDR with Internal PHY Loopback
1.8V, SDR with Internal PHY Loopback
3.3V, SDR with Internal PHY Loopback
1.8V, SDR with External Board Loopback
3.3V, SDR with External Board Loopback
1.8V, SDR with External Board Loopback
3.3V, SDR with External Board Loopback
4.8
5.19
-0.5
-0.5
0.6
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
O19 tsu(D-CLK)
O20 th(CLK-D)
O21 tsu(D-LBCLK)
O22 th(LBCLK-D)
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
0.9
1.7
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
2.0
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
图7-97. OSPI0 Timing Requirements –PHY SDR with Internal PHY Loopback
OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
图7-98. OSPI0 Timing Requirements –PHY SDR with External Board Loopback
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表7-117. OSPI0 Switching Characteristics –PHY SDR Mode
see 图7-99
NO.
PARAMETER
MODE
1.8V
MIN
7
MAX UNIT
ns
ns
ns
ns
O7
tc(CLK)
Cycle time, OSPI0_CLK
3.3V
6.03
O8
O9
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
O10 td(CSn-CLK)
O11 td(CLK-CSn)
ns
ns
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
1.8V
3.3V
-1.16
-1.33
1.25
1.51
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O12 td(CLK-D)
(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
图7-99. OSPI0 Switching Characteristics –PHY SDR
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7.11.5.18.1.2.2 OSPI0 PHY DDR Timing
表 7-118 defines DLL delays required for OSPI0 PHY DDR Mode. 表 7-119, 图 7-100, 表 7-120, and 图 7-101
present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.
表7-118. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
DELAY VALUE
Transmit
1.8V
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
0x46
0x43
3.3V
Receive
1.8V, DQS
3.3V, DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
0x15
0x3A
0x0
All other modes
表7-119. OSPI0 Timing Requirements –PHY DDR Mode
see 图7-100
NO.
MODE
MIN
MAX UNIT
1.8V, DDR with External Board Loopback
1.8V, DDR with DQS
0.53
-0.46
1.23
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, OSPI0_D[7:0] valid before
active OSPI0_DQS edge
O15 tsu(D-LBCLK)
3.3V, DDR with External Board Loopback
3.3V, DDR with DQS
-0.66
1.24(1)
3.59
1.8V, DDR with External Board Loopback
1.8V, DDR with DQS
Hold time, OSPI0_D[7:0] valid after active
OSPI0_DQS edge
O16 th(LBCLK-D)
3.3V, DDR with External Board Loopback
3.3V, DDR with DQS
1.44(1)
7.92
(1) This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length
between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.
The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.
OSPI_DQS
O15 O16 O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
图7-100. OSPI0 Timing Requirements –PHY DDR with External Board Loopback or DQS
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表7-120. OSPI0 Switching Characteristics –PHY DDR Mode
see 图7-101
NO.
PARAMETER
MODE
MIN
19
MAX UNIT
O1
O2
O3
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) -
((0.525P(1)) -
O4
O5
td(CSn-CLK)
td(CLK-CSn)
ns
ns
(0.975M(2)R(4))) (1.025M(2)R(4)) + 7)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 7)
(1.025N(3)R(4)))
1.8V
3.3V
-7.71
-7.71
-1.56
-1.56
ns
ns
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O6
td(CLK-D)
(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O6
O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
图7-101. OSPI0 Switching Characteristics –PHY DDR
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7.11.5.18.2 OSPI0 Tap Mode
7.11.5.18.2.1 OSPI0 Tap SDR Timing
表 7-121, 图 7-102, 表 7-122, and 图 7-103 present timing requirements and switching characteristics for OSPI0
Tap SDR Mode.
表7-121. OSPI0 Timing Requirements –Tap SDR Mode
see 图7-102
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
(15.4 -
O19 tsu(D-CLK)
No Loopback
ns
(0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
(- 4.3 +
O20 th(CLK-D)
No Loopback
ns
(0.975T(1)R(2)))
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
图7-102. OSPI0 Timing Requirements –Tap SDR, No Loopback
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表7-122. OSPI0 Switching Characteristics –Tap SDR Mode
see 图7-103
NO.
PARAMETER
MODE
MIN
20
MAX UNIT
O7
O8
O9
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
O10 td(CSn-CLK)
O11 td(CLK-CSn)
O12 td(CLK-D)
ns
ns
ns
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
- 4.25
7.25
(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
图7-103. OSPI0 Switching Characteristics –Tap SDR, No Loopback
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7.11.5.18.2.2 OSPI0 Tap DDR Timing
表 7-123, 图 7-104, 表 7-124, and 图 7-105 present timing requirements and switching characteristics for OSPI0
Tap DDR Mode.
表7-123. OSPI0 Timing Requirements –Tap DDR Mode
see 图7-104
NO.
MODE
MIN
MAX UNIT
Setup time, OSPI0_D[7:0] valid before
active OSPI0_CLK edge
(17.04 -
O13 tsu(D-CLK)
No Loopback
ns
(0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active
OSPI0_CLK edge
(- 3.16 +
O14 th(CLK-D)
No Loopback
ns
(0.975T(1)R(2)))
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns
OSPI_CLK
O13 O14 O13 O14
OSPI_D[i:0]
OSPI_TIMING_03
图7-104. OSPI0 Timing Requirements –Tap DDR, No Loopback
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表7-124. OSPI0 Switching Characteristics –Tap DDR Mode
see 图7-105
NO.
PARAMETER
MODE
MIN
40
MAX UNIT
O1
O2
O3
tc(CLK)
Cycle time, OSPI0_CLK
ns
ns
ns
tw(CLKL)
tw(CLKH)
Pulse duration, OSPI0_CLK low
Pulse duration, OSPI0_CLK high
((0.475P(1)) - 0.3)
((0.475P(1)) - 0.3)
Delay time, OSPI0_CSn[3:0] active edge
to OSPI0_CLK rising edge
((0.475P(1)) +
((0.525P(1)) +
O4
O5
td(CSn-CLK)
td(CLK-CSn)
ns
ns
((0.975M(2)R(5)) - 1) ( 1.025M(2)R(5)) + 1)
Delay time, OSPI0_CLK rising edge to
OSPI0_CSn[3:0] inactive edge
((0.475P(1)) +
((0.525P(1)) +
(0.975N(3)R(5)) - 1) (1.025N(3)R(5)) + 1)
(- 5.04 + (3.64 +
(0.975(T(4) + 1)R(5)
- (0.525P(1)))
Delay time, OSPI0_CLK active edge to
OSPI0_D[7:0] transition
O6
td(CLK-D)
)
(1.025(T(4) + 1)R(5)
)
ns
- (0.475P(1)))
(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]
(5) R = reference clock cycle time in ns
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O6
O6
O1
OSPI_D[i:0]
OSPI_TIMING_01
图7-105. OSPI0 Switching Characteristics –Tap DDR, No Loopback
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7.11.5.19 PRUSS
The device has a single Programmable Real-Time Unit Subsystem (PRUSS), which includes two PRU cores.
The programmable nature of the PRU cores, along with their access to pins, events and all device resources,
provides flexibility in implementing fast real-time responses, specialized data handling operations, custom
peripheral interfaces, and off-loading of tasks from the other processor cores in the device.
For more details about features and additional description information on the device PRUSS, see the
corresponding sections within Signal Descriptions and Detailed Description.
备注
PRUSS contains a second layer of peripheral signal multiplexing to enable additional functionality on
the PRU GPO and GPI signals. This peripheral multiplexing is described in the PRUSS chapter in the
device TRM.
备注
PRUSS has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.
7.11.5.19.1 PRUSS Programmable Real-Time Unit (PRU)
备注
PRUSS signals have different functionality depending on the mode of operation. The signal naming in
this section matches the naming used in the PRU Module Interface section in the device TRM.
表7-125. PRUSS PRU Timing Conditions
PARAMETER
MIN
1
MAX
3
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
2
30
7.11.5.19.1.1 PRUSS PRU Direct Output Mode Timing
表7-126. PRUSS PRU Switching Characteristics –Direct Output Mode
see 图7-106
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRDO1 tsk(GPO-GPO)
Skew, GPO to GPO
2
ns
GPO[n:0]
PRDO1
PRU_TIMING_02
A. n in GPO[n:0] = 19.
图7-106. PRUSS PRU Direct Output Timing
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7.11.5.19.1.2 PRUSS PRU Parallel Capture Mode Timing
表7-127. PRUSS PRU Timing Requirements –Parallel Capture Mode
see 图7-107 and 图7-108
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
PRPC1 tc(CLOCK)
Cycle time, CLOCKIN
20
0.45P(1)
0.45P(1)
4
PRPC2 tw(CLOCKL)
Pulse duration, CLOCKIN low
ns
PRPC3 tw(CLOCKH)
PRPC4 tsu(DATAIN-CLOCK)
PRPC5 th(CLOCK-DATAIN)
Pulse duration, CLOCKIN high
ns
Setup time, DATAIN valid before CLOCKIN active edge
Hold time, DATAIN valid after CLOCKIN active edge
ns
0
ns
(1) P = CLOCKIN cycle time in ns
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_03
图7-107. PRUSS PRU Parallel Capture Timing Requirements –Rising Edge Mode
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_04
图7-108. PRUSS PRU Parallel Capture Timing Requirements –Falling Edge Mode
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7.11.5.19.1.3 PRUSS PRU Shift Mode Timing
表7-128. PRUSS PRU Timing Requirements –Shift In Mode
see 图7-109
NO.
PARAMETER
DESCRIPTION
Pulse duration, DATAIN high
Pulse duration, DATAIN low
MIN
2P(1) + 2
2P(1) + 2
MAX
UNIT
ns
PRSI1 tw(DATAINH)
PRSI2 tw(DATAINL)
ns
(1) P = Internal shift in clock period in ns, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the GPCFGn_REG register,
where PRUn represents the respective PRU0 or PRU1 instance.
PRSI1
PRSI2
DATAIN
PRU_TIMING_05
图7-109. PRUSS PRU Shift In Timing
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表7-129. PRUSS PRU Switching Characteristics –Shift Out Mode
see 图7-110
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
PRSO1
tc(CLOCKOUT)
Cycle time, CLOCKOUT
10
PRSO2L tw(CLOCKOUTL)
Pulse duration, CLOCKOUT low
0.475P(1)Z(2)
-
ns
0.3
PRSO2H tw(CLOCKOUTH)
Pulse duration, CLOCKOUT high
0.475P(1)Y(3)
-
ns
ns
0.3
PRSO3
td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid
0
3
(1) P = Software programmable shift out clock period in ns, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the
GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance.
(2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is
an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5).
c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0).
d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 *
PRUn_GPI_DIV0).
(3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is
an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 - 0.5).
c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).
d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *
PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high
pulse and Y2 is the second high pulse.
PRSO1
PRSO2H
PRSO2L
CLOCKOUT
DATAOUT
PRSO3
PRU_TIMING_06
图7-110. PRUSS PRU Shift Out Timing
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7.11.5.19.2 PRUSS Industrial Ethernet Peripheral (IEP)
表7-130. PRUSS IEP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
3
OUTPUT CONDITIONS
CL
Output load capacitance
3
10
7.11.5.19.2.1 PRUSS IEP Timing
表7-131. PRUSS IEP Switching Characteristics –Digital IOs
see 图7-111
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
IEPIO4 tsk(EDIO_DATA_OUT)
EDIO_DATA_OUT skew
5
ns
EDIO_DATA_OUT
IEPIO4
PRU_EDIO_DATA_OUT_TIMING_00
图7-111. PRUSS IEP Digital IOs Timing Requirements
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7.11.5.19.3 PRUSS Universal Asynchronous Receiver Transmitter (UART)
表7-132. PRUSS UART Timing Conditions
PARAMETER
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30(1)
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
7.11.5.19.3.1 PRUSS UART Timing
表7-133. PRUSS UART Timing Requirements
see 图7-112
NO.
PARAMETER
tw(RXD)
tw(RXDS)
DESCRIPTION
MIN
MAX
UNIT
0.95U(1)
1.05U(1)
1
Pulse width, receive data bit high or low
ns
(2)
(2)
0.95U(1)
2
Pulse width, receive start bit low
ns
(2)
(1) U = UART baud time in ns = 1/programmed baud rate.
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
表7-134. PRUSS UART Switching Characteristics
see 图7-112
NO.
PARAMETER
DESCRIPTION
MIN
MAX
12
UNIT
Mbps
ns
f(baud)
Programmed baud rate
3
4
tw(TXD)
Pulse width, transmit data bit high or low
Pulse width, transmit start bit low
U(1) - 2
U(1) - 2
U(1) + 2
U(1) + 2
tw(TXDS)
ns
(1) U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the
device TRM.
2
1
Start
VIH
Bit
PRGi_UART0_RXD
VIL
Data Bits
4
3
Start
Bit
PRGi_UART0_TXD
Data Bits
PRU_UART_TIMING_01_RCVRVIHVIL
图7-112. PRUSS UART Timing Requirements and Switching Characteristics
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7.11.5.19.4 PRUSS Enhanced Capture Peripheral (ECAP)
表7-135. PRUSS ECAP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
3
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
7.11.5.19.4.1 PRUSS ECAP Timing
表7-136. PRUSS ECAP Timing Requirements
see 图7-113
NO.
PARAMETER
DESCRIPTION
Pulse Duration, CAP (asynchronous)
Pulse Duration, SYNCI (asynchronous)
MIN
2P(1) + 2
2P(1) + 2
MAX
UNIT
ns
PREP1 tw(CAP)
PREP2 tw(SYNCI)
ns
(1) P = CORE_CLK period in ns.
PREP1
PREP2
CAP
SYNCI
图7-113. PRUSS ECAP Timing
表7-137. PRUSS ECAP Switching Characteristics
see 图7-114
NO.
PARAMETER
DESCRIPTION
Pulse Duration, APWM high/low
MIN
2P(1) - 2
P(1) - 2
MAX
UNIT
ns
PREP3 tw(APWM)
PREP4 tw(SYNCO)
Pulse Duration, SYNCO (asynchronous)
ns
(1) P = CORE_CLK period in ns.
PREP3
PREP4
APWM
SYNCO
图7-114. PRUSS ECAP Switching Characteristics
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7.11.5.20 Timers
For more details about features and additional description information on the device Timers, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
表7-138. Timer Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
表7-139. Timer Input Timing Requirements
see 图7-115
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
T1
tw(TINPH)
Pulse duration, high
Pulse duration, low
CAPTURE
4P(1)
+
ns
2.5
T2
tw(TINPL)
CAPTURE
4P(1)
+
ns
2.5
(1) P = functional clock period in ns.
表7-140. Timer Output Switching Characteristics
see 图7-115
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
tw(TOUTH)
Pulse duration, high
Pulse duration, low
PWM
4P(1)
-
ns
2.5
T4
tw(TOUTL)
PWM
4P(1)
-
ns
2.5
(1) P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
图7-115. Timer Timing Requirements and Switching Characteristics
For more information, see Timers section in Peripherals chapter in the device TRM.
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7.11.5.21 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
表7-141. UART Timing Conditions
PARAMETER
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30(1)
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
表7-142. UART Timing Requirements
see 图7-116
NO.
PARAMETER
tw(RXD)
tw(RXDS)
DESCRIPTION
MIN
MAX
UNIT
0.95U(1)
1.05U(1)
1
Pulse width, receive data bit high or low
ns
(2)
(2)
0.95U(1)
2
Pulse width, receive start bit low
ns
(2)
(1) U = UART baud time in ns = 1/programmed baud rate.
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
表7-143. UART Switching Characteristics
see 图7-116
NO.
PARAMETER
DESCRIPTION
Programmable baud rate for Main Domain UARTs
Programmable baud rate for MCU and WKUP Domain UARTs
Pulse width, transmit data bit high or low
MIN
MAX
12
UNIT
Mbps
Mbps
ns
f(baud)
3.7
3
4
tw(TXD)
U(1) - 2
U(1) - 2
U(1) + 2
tw(TXDS)
Pulse width, transmit start bit low
ns
(1) U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the
device TRM.
2
1
Start
VIH
Bit
UARTi_RXD
VIL
Data Bits
4
3
Start
Bit
UARTi_TXD
Data Bits
UART_TIMING_01_RCVRVIHVIL
图7-116. UART Timing Requirements and Switching Characteristics
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For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.11.5.22 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
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8 Detailed Description
8.1 Overview
The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development.
With scalable Arm® Cortex®-A53 performance and embedded features, such as: dual-display support and 3D
graphics acceleration, along with an extensive set of peripherals that make the AM62x device well-suited for a
broad range of industrial and automotive applications while offering intelligent features and optimized power
architecture as well.
Some of these applications include:
• Industrial HMI
• EV charging stations
• Touchless building access
• Driver monitoring systems
AM62x Sitara™ processors are industrial-grade in the 13 x 13 mm package (ALW) and can meet the AEC - Q100
automotive standard in the 17.2 x 17.2 mm package (AMC). Industrial and Automotive functional safety
requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all
be isolated from the rest of the AM62x processor.
The 3-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking
(TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own
use cases. In addition, the extensive set of peripherals included in AM62x enables system-level connectivity,
such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external
ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security
Module (HSM) and employs advanced power management support for portable and power-sensitive applications
备注
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
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8.2 Processor Subsystems
8.2.1 Arm Cortex-A53 Subsystem
The SoC implements one cluster of quad-core Arm® Cortex®-A53 MPCore™, with 32KB L1 instruction, 32KB L1
data, per core and 512KB L2 shared cache.
The Cortex®-A53 cores are general-purpose processors that can be used for running customer applications.
备注
Notes on references used in this document:
• A53SS is also referred to as Arm® CorePac.
• Cortex®-A53 is often shortened to A53.
The A53SS is built around the Cortex®-A53 MPCore™ (Arm®-A53 Cluster), which is provided by Arm and
configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus, it delivers high
performance and optimal power management, debug and emulation capabilities.
The A53 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 Instruction and
Data Caches, compatible with Arm®v8-A architecture. It delivers significantly more performance than its
predecessors at a higher level of power efficiency.
The Arm®v8-A architecture brings a number of new features. These include 64-bit data processing, extended
virtual addressing and 64-bit general purpose registers. The A53 processor is Arm’s first Arm®v8-A processor
aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-issue pipeline, and
improved integer, Arm® Neon™, Floating-Point Unit (FPU) and memory performance.
The A53 CPU supports two execution states: AArch32 and AArch64. The AArch64 state gives the A53 CPU its
ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing Arm®v7-A
applications.
For more information, see Arm Cortex-A53 Subsystem section in Processors and Accelerators chapter in the
device TRM.
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8.2.2 Device/Power Manager
The WKUP_R5FSS is a single-core implementation of the Arm® Cortex®-R5F processor that acts as the Device
Manager responsible for boot, resource management, and power management functions. It also includes
accompanying memories (L1 caches and tightly-coupled memories), standard Arm® CoreSight™™ debug and
trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules for
protocol conversion and address translation for easy integration into the SoC.
备注
The Cortex-R5F processor is a Cortex-R5 processor that includes the optional floating point unit
(FPU) extension. In this TRM, all references to the Cortex-R5 processor apply to the Cortex-R5F
processor by default.
For more information, see Device Manager Cortex R5F Subsystem section in Processors and Accelerators
chapter in the device TRM.
8.2.3 Arm Cortex-M4F
The MCU_M4FSS is an Arm® Cortex®-M4F based subsystem that can run safety processing or be used as a
general purpose MCU. During the boot process, the MCU_M4FSS will be configured by an initial software
running on a different core. Following configuration, software will release the safety processor (M4F) out of reset,
and at this point safety processor code or general purpose code can start execution.
备注
The Cortex-M4F processor is a Cortex-M4 processor that includes the optional floating point unit
(FPU) extension.
For more information, see Cortex-M4F Subsystem section in Processors and Accelerators chapter in the device
TRM.
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8.3 Accelerators and Coprocessors
8.3.1 Graphics Processing Unit (GPU)
The GPU is an area optimized Graphics Core supporting OpenGL ES 3.1 and Vulkan 1.2.
For more information, see Graphics Processing Unit section in Processors and Accelerators chapter in the
device TRM.
8.3.2 Programmable Real-Time Unit Subsystem (PRUSS)
The PRUSS consists of:
• Two 32-bit load/store RISC CPU cores —Programmable Real-Time Units (PRU0 and PRU1)
• Data RAMs per PRU core (DRAM)
• Instruction RAMs per PRU core (IRAM)
• Shared RAM (SRAM)
• Peripheral modules: UART0, ECAP0, IEP0, MDIO
• Interrupt Controller (INTC) per core
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level host
CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s
instruction memory.
The programmable nature of the PRU cores, along with their access to pins, events and all device resources,
provides flexibility in implementing fast real-time responses, specialized data handling operations, custom
peripheral interfaces, and in offloading tasks from the other processor cores of the device.
For more information, see Programmable Real-Time Unit Subsystem section in Processors and Accelerators
chapter in the device TRM.
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8.4 Other Subsystems
8.4.1 Dual Clock Comparator (DCC)
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution
of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The
desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
For more information, see Dual Clock Comparator section in Peripherals chapter in the device TRM.
8.4.2 Data Movement Subsystem (DMSS)
The DMSS module provides data movement (DMA) and bridges between the CBA switched interconnect and
the packet streaming fabric (network on chip) on the device.
The Data Movement Subsystem (DMSS) consists of DMA/Queue Management components and Peripherals:
•Packet DMA
•Block Copy DMA
•Ring Accelerator
•Packet Streaming Interface (PSILSS)
•Infrastructure components such as CBASS, secure proxy, and an interrupt aggregator
8.4.3 Memory Cyclic Redundancy Check (MCRC)
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the
signature for a set of data and then compare the calculated signature value against a pre-determined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
parallel and can be used on any memory system.
For more information, see Memory Cyclic Redundancy Check section in Peripherals chapter in the device TRM.
8.4.4 Peripheral DMA Controller (PDMA)
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of
peripherals, which perform data transfers using memory mapped registers (MMRs) accessed via a standard
non-coherent bus fabric. The PDMA module is located close to one or more peripherals which require an
external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting
only statically configured transfer request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data
stream which is then sent to a remote peer DMSS destination channel which then performs the movement of the
data into memory. Likewise, a remote DMSS source channel fetches data from memory and transfers it to a peer
PDMA destination channel over PSI-L which then performs the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (DMSS + PDMA) to right size the data transfer complexity
at each point in the system to match the requirements of whatever is being transferred to or from. Peripherals
are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO dimensioning
requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically for sample
size and FIFO depth), hardcoded address maps, and simple triggering capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and
employs round-robin scheduling between channels in order to share the underlying DMA hardware.
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8.4.5 Real-Time Clock (RTC)
The basic purpose for the RTC is to keep time of day. The other equally important purpose of RTC is for Digital
Rights management. Some degree of tamper proofing is needed to ensure that simply stopping, resetting, or
corrupting the RTC does not go unnoticed so that if this occurs, the application can re-acquire the time of day
from a trusted source.
For more information, see Real-Time Clock section in Peripherals chapter in the device TRM.
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8.5 Peripherals
8.5.1 Gigabit Ethernet Switch (CPSW3G)
The 3-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device
and can be configured as an Ethernet switch.
For more information, see Gigabit Ethernet Switch section in Peripherals chapter in the device TRM.
8.5.2 Camera Streaming Interface Receiver (CSI_RX_IF)
The integration of the CSI_RX_IF module allows the device to stream video inputs from multiple cameras to
internal memory.
For more information, see Camera Streaming Interface Receiver section in Peripherals chapter in the device
TRM.
8.5.3 DDR Subsystem (DDRSS)
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these
blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to
external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via CBASS0
interconnect.
For more information, see DDR Subsystem section in Peripherals chapter in the device TRM.
8.5.4 Display Subsystem (DSS)
The Display Subsystem (DSS) is a flexible, multi-pipeline subsystem that supports high-resolution display
outputs. DSS includes input pipelines providing multi-layer blending with transparency to enable on-the-fly
composition. Various pixel processing capabilities are supported, such as color space conversion and scaling,
among others. DSS includes a DMA engine, which allows direct access to the frame buffer (device system
memory). Display outputs can connect seamlessly to an Open LVDS Display Interface transmitter (OLDITX), or
can directly drive device pads as a Display Parallel Interface (DPI).
For more information, see Display Subsystem section in Peripherals chapter in the device TRM.
8.5.5 Enhanced Capture (ECAP)
The ECAP module provides accurate timing of events. When not being used for event capture, its resources can
be used to generate a single channel of asymmetrical PWM waveforms.
The Enhanced Capture (ECAP) module can be used for:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
For more information, see Enhanced Capture section in Peripherals chapter in the device TRM.
8.5.6 Error Location Module (ELM)
The ELM extracts error addresses from generated syndrome polynomials.
The ELM is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash page
and stored in GPMC registers are passed to the ELM. A host processor can then correct the data block by
flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
For more information, see Error Location Module section in Peripherals chapter in the device TRM.
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8.5.7 Enhanced Pulse Width Modulation (EPWM)
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
For more information, see Enhanced Pulse Width Modulation section in Peripherals chapter in the device TRM.
8.5.8 Error Signaling Module (ESM)
The Error Signaling Module (ESM) aggregates events and/or errors from throughout the device into one location.
It can signal both low and high priority interrupts to a processor to deal with an event and/or manipulate an I/O
error pin to signal an external hardware that an error has occurred. Therefore an external controller is able to
reset the device or keep the system in a safe, known state.
For more information, see Error Signaling Module section in Peripherals chapter in the device TRM.
8.5.9 Enhanced Quadrature Encoder Pulse (EQEP)
The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined
as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is
added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate
an absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position and zero reference.
For more information, see Enhanced Quadrature Encoder Pulse section in Peripherals chapter in the device
TRM.
8.5.10 General-Purpose Interface (GPIO)
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, user can write to an internal register to
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface section in Peripherals chapter in the device TRM.
8.5.11 General-Purpose Memory Controller (GPMC)
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external
memory devices like:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
• NAND flash
• Pseudo-SRAM devices
For more information, see General-Purpose Memory Controller section in Peripherals chapter in the device
TRM.
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8.5.12 Global Timebase Counter (GTC)
The GTC module provides a continuous running counter that can be used for time synchronization and debug
trace time stamping.
For more information, see Global Timebase Counter section in Peripherals chapter in the device TRM.
8.5.13 Inter-Integrated Circuit (I2C)
The device contains multicontroller Inter-Integrated Circuit (I2C) controllers each of which provides an interface
between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial
bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and
from the LH device through the 2-wire I2C interface.
Each multicontroller I2C module can be configured to act like a target or controller I2C-compatible device.
I2C instances may be implemented with dedicated, I2C compliant, open-drain I/O buffers, or with standard
LVCMOS I/O buffers. The I2C instances associated with open-drain I/O buffers can support Hs-mode (up to 3.4
Mbps when the I/O buffers are operating at 1.8 V but limited to 400 kbps when the I/O buffers are operating at
3.3 V).
The I2C instances associated with standard LVCMOS I/O buffers can support Fast-mode (up to 400 kbps). The
LVCMOS I/O buffers being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z state.
For more information, see Inter-Integrated Circuit section in Peripherals chapter in the device TRM.
8.5.14 Modular Controller Area Network (MCAN)
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control with a high level of security. CAN has high immunity to electrical interference and the ability to
self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
For more information, see Modular Controller Area Network section in Peripherals chapter in the device TRM.
8.5.15 Multichannel Audio Serial Port (MCASP)
This section introduces the Multichannel Audio Serial Port (MCASP) module and describes its main functions
and connections in the device.
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio
applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for
time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for
an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly
connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.
Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not
natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows
an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
For more information, see Multichannel Audio Serial Port section in Peripherals chapter in the device TRM.
8.5.16 Multichannel Serial Peripheral Interface (MCSPI)
The MCSPI module is a multichannel transmit/receive, controller/peripheral synchronous serial bus.
For more information, see Multichannel Serial Peripheral Interface section in Peripherals chapter in the device
TRM.
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8.5.17 Multi-Media Card Secure Digital (MMCSD)
The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded Multi-Media Card), SD 4.10 (Secure
Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO
protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,
and checking for syntactical correctness
For more information, see Multi-Media Card Secure Digital section in Peripherals chapter in the device TRM.
8.5.18 Octal Serial Peripheral Interface (OSPI)
The Octal Serial Peripheral Interface (OSPI) module is a Serial Peripheral Interface (SPI) module which allows
single, dual, quad or octal read and write access to external flash devices. This module has a memory mapped
register interface, which provides a direct memory interface for accessing data from external flash devices,
simplifying software requirements.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up
to silently perform some requested operation, signaling its completion via interrupts or status registers. For
indirect operations, data is transferred between system memory and external flash memory via an internal
SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds.
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using
user programmable configuration registers.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
8.5.19 Timers
All timers include specific functions to generate accurate tick interrupts to the operating system.
For more information, see Timers section in Peripherals chapter in the device TRM.
8.5.20 Universal Asynchronous Receiver/Transmitter (UART)
The UART is a peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. All UART
modules support IrDA and CIR modes when 48 MHz function clock is used. Each UART can be used for
configuration and data exchange with a number of external peripheral devices or interprocessor communication
between devices.
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter section in Peripherals
chapter in the device TRM.
8.5.21 Universal Serial Bus Subsystem (USBSS)
USB (Universal Serial Bus) provides a low-cost connectivity solution for numerous consumer portable devices by
implementing a mechanism for data transfer between USB devices.
The device instantiates two independent instances of a third-party USB subsystem (USB2SS) operating at up to
USB2.0 speeds (480Mb/s), either of which can be independently configured to act as a USB Host or a USB
Device.
For more information, see Universal Serial Bus Subsystem section in Peripherals chapter in the device TRM.
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9 Applications, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Device Connection and Layout Fundamentals
9.1.1 Power Supply
9.1.1.1 Power Supply Designs
The TPS65219 Power Management IC (PMIC) is recommended for an integrated AM62x power solution. This
cost and space optimized solution is designed to power the AM62 processor and its principal peripherals. For the
full application note and operational details, refer to Powering the AM62x with the TPS65219 PMIC
List of benefits when using TPS65219 PMIC to power AM62x:
• Full device performance entitlement as validated on TI Evaluation boards
• Factory programmed configurations support power rail load steps, supply voltage accuracies and maximum
load currents with margins
• Factory programmed configurations support LPDDR4 and DDR4 memory
• Meets all AM62x voltage and sequencing requirements, refer to 节7.5, Recommended Operating Conditions
and 节7.11.2.2, Power Supply Sequencing
9.1.1.2 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that
follow the board design guidelines contained in the application report.
9.1.2 External Oscillator
For more information about External Oscillators, see the Clock Specifications section.
9.1.3 JTAG, EMU, and TRACE
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical
Reference Manual
9.1.4 Reset
9.1.5 Unused Pins
For more information about Unused Pins, see 节6.4, Pin Connectivity Requirements
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9.2 Peripheral- and Interface-Specific Design Information
9.2.1 DDR Board Design and Layout Guidelines
The goal of the AM62x DDR Board Design and Layout Guidelines is to make the DDR system implementation
straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that
allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports
board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.
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9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or
SPI devices.
9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to
B) must be ≤450 ps (~7cm as stripline or ~8cm as microstrip)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-1
• Propagation delays and matching:
– (A to B) ≤450 ps
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_01
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
图9-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad
Loopback
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9.2.2.2 External Board Loopback
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin
• The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be
approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device
CLK pin (A to B)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-2
• Propagation delays and matching:
– (C to D) = 2 x ((A to B) ± 30 ps), see the exception note below.
– (E to F, or F to E) = ((A to B) ± 60 ps)
备注
The External Board Loopback hold time requirement (defined by parameter number O16 in 表 7-119,
OSPI0 Timing Requirements - PHY DDR Mode) may be larger than the hold time provided by a typical
OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the
OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
C
R1
0 Ω*
OSPI[x]_LBCLKO
D
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_02
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if
needed.
图9-2. OSPI Connectivity Schematic for External Board Loopback
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9.2.2.3 DQS (only available in Octal SPI devices)
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin
• The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D
to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached
OSPI/QSPI/SPI device CLK pin (A to B)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-3
• Propagation delays and matching:
– (D to C) = ((A to B) ± 30 ps)
– (E to F, or F to E) = ((A to B) ± 60 ps)
A
B
R1
0 Ω*
OSPI/QSPI/SPI
Device Clock Input
OSPI[x]_CLK
OSPI[x]_LBCLKO
C
D
OSPI Device DQS
OSPI[x]_DQS
E
F
OSPI[x]_D[y],
OSPI[x]_CSn[z]
OSPI/QSPI/SPI
Device IO[y], CS#
OSPI_Board_03
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
图9-3. OSPI Connectivity Schematic for DQS
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9.2.3 USB VBUS Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the
图 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these external
resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5 V should be less than
100 nA.
Device
USBn_VBUS
16.5 kΩ
1%
3.5 kΩ
1%
VBUS signal
10 kΩ
1%
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
图9-4. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in 图 9-4 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
9.2.4 System Power Supply Monitor Design Guidelines
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a
single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via and
external resistor divider circuit. This system supply is monitored by comparing the external voltage divider output
voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied to
VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point is
determined by the system designer when selecting component values used to implement the external resistor
voltage divider circuit.
When designing the resistor divider circuit the designer must understand various factors which contribute to
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the
VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1%
resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This
minimizes variability contributed by resistor value tolerances. Input leakage current associated with
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the
voltage divider output. The VMON_VSYS input leakage current can be in the range of 10 nA to 2.5 µA when
applying 0.45 V.
备注
The resistor voltage divider shall be designed such that the output voltage never exceeds the
maximum value defined in the Recommended Operating Conditions section, during normal operating
conditions.
图9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger threshold
is 5 V - 10%, or 4.5 V.
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For this example, the designer must understand which variables effect the maximum trigger threshold when
selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45 V + 3% needs to be
considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The
effect of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum
trigger point is not obvious. When selecting component values which produce a maximum trigger voltage, the
system designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high
combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When implementing a
resistor divider where R1 = 4.81 KΩand R2 = 40.2 KΩ, the result is a maximum trigger threshold of 4.517 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.013 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.013 V to 4.517 V.
Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this
range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above can be reduced to about
10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor divider bias
current vs loading error is something the system designer needs to consider when selecting component values.
The system designer must also consider implementing a noise filter on the voltage divider output since
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by
installing a capacitor across R1 as shown in 图9-5. However, the system designer must determine the response
time of this filter based on system supply noise and expected response to transient events.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ 1%
C1
Value = Determined by system designer
(System Power Supply)
4.81 kΩ
1%
R1
VSS
SPRSP56_VMON_ER_MON_01
图9-5. System Supply Monitor Voltage Divider Circuit
VMON_1P8_SOC pin provides a way to monitor external 1.8 V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.
VMON_3P3_SOC pin provides a way to monitor external 3.3 V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.
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9.2.5 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application note.
9.2.6 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application note.
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10 Device and Documentation Support
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, AM6254ATCGGAALW). Texas Instruments recommends two of three possible prefix designators for
related support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final
electrical specifications.
null (BLANK) Production version of the silicon die that is fully qualified and meets final electrical specifications.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of AM62x devices in the ALW or AMC package types, see the Package Option
Addendum at the end of this document, the TI website (ti.com), or contact your TI sales representative.
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10.1.1 Standard Package Symbolization
备注
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
SITARA
SITARA
aBBBBBBr
ZfYytPPPQ1
XXXXXXX
aBBBBBBr
ZfYytPPPQ1
XXXXXXX
A1 (PIN ONE INDICATOR)
YYY
G1
A1 (PIN ONE INDICATOR)
G1
ZZZ
YYY
O
O
图10-1. Printed Device Reference
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10.1.2 Device Naming Convention
FIELD PARAMETER FIELD DESCRIPTION
VALUE
DESCRIPTION
X
Prototype
a
Device evolution stage
P
BLANK(1)
AM6254
AM6252
AM6251
AM6234
AM6232
AM6231
AM6204
AM6202
AM6201
A
Preproduction (production test flow, no reliability data)
Production
Base production part
number
BBBBBB
See 表5-1, Device Comparison
r
Device revision
SR1.0
G
K
Z
Device Speed Grade
See 表7-1, Device Speed Grades
S
T
G
Base, no additional Features
Base, plus PRU Subsystem (PRUSS) enabled
Non-Functional Safety
Functional Safety
Features
(see 表5-1)
f
C
G
Y
y
Functional Safety
Security
F
G
Non-Secure
Other
Secure
–40°C to 105°C - Extended Industrial (see 节7.5, Recommended
Operation Conditions)
A
H
I
0°C to 95°C - Commercial (see 节7.5, Recommended Operation
Conditions)
t
Temperature(2)
–40°C to 125°C - Automotive (see 节7.5, Recommended Operation
Conditions)
ALW
AMC
FCCSP BGA (425-pin)
PPP
Q1
Package Designator
FCBGA (441-pin)
Q1
Automotive Qualified (AEC - Q100)
Standard
Automotive Designator
BLANK(1)
xxxxxxx
YYY
ZZZ
O
Lot Trace Code (LTC)
Production Code, For TI use only
Production Code, For TI use only
Pin one designator
G1
ECAT - Green package designator
(1) BLANK in the symbol or part number is collapsed so there are no gaps between characters.
(2) Applies to device max junction temperature.
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10.2 Tools and Software
The following Development Tools support development for TI's Embedded Processing platforms:
Development Tools
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster than
ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for
embedded developers.
SysConfig-PinMux Tool The SysConfig-PinMux Tool is a software tool which provides a Graphical User
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration
to satisfy entered system requirements. The tool generates output C header/code files that can be imported into
software development kits (SDKs) and used to configure customer's software to meet custom hardware
requirements. The Cloud-based SysConfig-PinMux Tool is also available.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The following documents describe the AM62x devices.
Technical Reference Manual
AM62x Sitara Processors Technical Reference Manual: Details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the AM62x family of
devices.
Errata
AM62x Sitara Processors Silicon Errata: Describes the known exceptions to the functional specifications for
the device.
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
Sitara™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
MPCore™, Neon™, and CoreSight™ are trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
Arm®, Cortex®, and TrustZone® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
MIPI® is a registered trademark of MIPI Alliance.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 251
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
安全数字® and SD® are registered trademarks of SD Card Association.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
252 Submit Document Feedback
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
AM625, AM625-Q1, AM623, AM620-Q1
ZHCSQL8B –JUNE 2022 –REVISED JUNE 2023
www.ti.com.cn
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 253
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1
English Data Sheet: SPRSP58
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM6201ASGFHIAMCRQ1
AM6202ATGFHIAMCRQ1
AM6204ASGFHIAMCRQ1
ACTIVE
FCBGA
FCBGA
FCBGA
AMC
441
441
441
500
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
AM6201A
SGFHIAMCQ1
131
Samples
Samples
Samples
ACTIVE
ACTIVE
AMC
AMC
500
500
Call TI
Call TI
-40 to 125
AM6202A
TGFHIAMCQ1
131
-40 to 125
AM6204A
SGFHIAMCQ1
131
AM6231AGGGGHALW
AM6231AKGGHHALW
AM6231ASGGGAALW
PREVIEW
PREVIEW
ACTIVE
FCCSP
FCCSP
FCCSP
ALW
ALW
ALW
425
425
425
119
119
119
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
0 to 95
0 to 95
RoHS & Green
Level-3-250C-168 HR
-40 to 105
AM6231A
SGGGAALW
131
Samples
Samples
AM6231ASGGHAALW
AM6231ATCGHAALW
PREVIEW
ACTIVE
FCCSP
FCCSP
ALW
ALW
425
425
119
119
TBD
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6231A
TCGHAALW
131
AM6231ATGGHAALW
AM6232ASGGHAALW
AM6232ATCGGAALW
PREVIEW
PREVIEW
ACTIVE
FCCSP
FCCSP
FCCSP
ALW
ALW
ALW
425
425
425
119
119
119
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6232A
TCGGAALW
131
Samples
Samples
AM6232ATCGHAALW
ACTIVE
FCCSP
ALW
425
119
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6232A
TCGHAALW
131
AM6232ATGGHAALW
AM6234ASGGHAALW
AM6234ATCGGAALW
PREVIEW
PREVIEW
ACTIVE
FCCSP
FCCSP
FCCSP
ALW
ALW
ALW
425
425
425
119
119
119
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6234A
TCGGAALW
131
Samples
Samples
AM6234ATCGHAALW
ACTIVE
FCCSP
ALW
425
119
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6234A
TCGHAALW
131
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM6234ATGGHAALW
AM6251AKGGHHALW
AM6251ASGGHAALW
AM6251ATCGHAALW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
FCCSP
FCCSP
FCCSP
FCCSP
ALW
ALW
ALW
ALW
425
425
425
425
119
119
119
119
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
0 to 95
TBD
Call TI
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6251A
TCGHAALW
131
Samples
Samples
AM6251ATGGHAALW
PREVIEW
ACTIVE
FCCSP
FCBGA
ALW
AMC
425
441
119
500
TBD
Call TI
Call TI
Call TI
-40 to 105
-40 to 125
AM6252ASGFHIAMCRQ1
RoHS & Green
Level-3-260C-168 HR
AM6252A
SGFHIAMCQ1
131
AM6252ASGGHAALW
AM6252ATCGGAALW
PREVIEW
ACTIVE
FCCSP
FCCSP
ALW
ALW
425
425
119
119
TBD
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6252A
TCGGAALW
131
Samples
Samples
AM6252ATCGHAALW
ACTIVE
FCCSP
ALW
425
119
RoHS & Green
Call TI
Level-3-250C-168 HR
-40 to 105
AM6252A
TCGHAALW
131
AM6252ATGGHAALW
AM6254ASGGHAALW
AM6254ATCGGAALW
PREVIEW
PREVIEW
ACTIVE
FCCSP
FCCSP
FCCSP
ALW
ALW
ALW
425
425
425
119
119
119
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
RoHS & Green
Level-3-250C-168 HR
AM6254A
TCGGAALW
131
Samples
Samples
Samples
AM6254ATCGHAALW
AM6254ATGFHIAMCRQ1
AM6254ATGGHAALW
ACTIVE
ACTIVE
FCCSP
FCBGA
FCCSP
ALW
AMC
ALW
425
441
425
119
500
119
RoHS & Green
RoHS & Green
TBD
Call TI
Call TI
Call TI
Level-3-250C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 105
-40 to 125
-40 to 105
AM6254A
TCGHAALW
131
AM6254A
TGFHIAMCQ1
131
PREVIEW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AM625, AM625-Q1 :
Catalog : AM625
•
Automotive : AM625-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AM6201ASGFHIAMCRQ1 FCBGA
AM6202ATGFHIAMCRQ1 FCBGA
AM6204ASGFHIAMCRQ1 FCBGA
AM6252ASGFHIAMCRQ1 FCBGA
AM6254ATGFHIAMCRQ1 FCBGA
AMC
AMC
AMC
AMC
AMC
441
441
441
441
441
500
500
500
500
500
330.0
330.0
330.0
330.0
330.0
32.4
32.4
32.4
32.4
32.4
17.6
17.6
17.6
17.6
17.6
17.6
17.6
17.6
17.6
17.6
3.74
3.74
3.74
3.74
3.74
24.0
24.0
24.0
24.0
24.0
32.0
32.0
32.0
32.0
32.0
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
AM6201ASGFHIAMCRQ1
AM6202ATGFHIAMCRQ1
AM6204ASGFHIAMCRQ1
AM6252ASGFHIAMCRQ1
AM6254ATGFHIAMCRQ1
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
AMC
AMC
AMC
AMC
AMC
441
441
441
441
441
500
500
500
500
500
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
336.6
41.3
41.3
41.3
41.3
41.3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AM6231ASGGGAALW
AM6231ATCGHAALW
AM6232ATCGGAALW
AM6232ATCGHAALW
AM6234ATCGGAALW
AM6234ATCGHAALW
AM6251ATCGHAALW
AM6252ATCGGAALW
AM6252ATCGHAALW
AM6254ATCGGAALW
AM6254ATCGHAALW
ALW
ALW
ALW
ALW
ALW
ALW
ALW
ALW
ALW
ALW
ALW
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
FCCSP
425
425
425
425
425
425
425
425
425
425
425
119
119
119
119
119
119
119
119
119
119
119
07x17
07x17
07x17
07x17
07x17
07x17
07x17
07x17
07x17
07x17
07x17
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
315 135.9 7620 18.1
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.7
12.9
12.9
12.9
12.9
12.9
12.9
12.9
12.9
12.9
12.9
12.9
Pack Materials-Page 3
PACKAGE OUTLINE
AMC0441A
FCBGA - 2.57 mm max height
SCALE 0.900
BALL GRID ARRAY
17.3
17.1
A
B
BALL A1 CORNER
PIN 1 ID
(OPTIONAL)
17.3
17.1
(
12.8)
0.1 C
(
11)
16.8)
(
(1.45)
2.57
2.29
0.2 C
C
SEATING PLANE
0.15 C
(0.577)
0.5
TYP
0.3
16 TYP
SYMM
(0.6) TYP
(0.6) TYP
0.8 TYP
AA
Y
W
V
U
T
R
P
N
M
L
SYMM
16
K
J
TYP
H
G
F
E
D
C
B
A
0.55
0.45
C A B
441X
0.25
0.1
1
2
3
4
5
6 7 8 9 10 12 14 16 18 20
11 13 15 17 19 21
C
0.8 TYP
4228316/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
AMC0441A
FCBGA - 2.57 mm max height
BALL GRID ARRAY
(0.8) TYP
441X ( 0.4)
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SNOWN
SCALE:6X
0.07 MAX
0.07 MIN
METAL UNDER
SOLDER MASK
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4228316/A 12/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AMC0441A
FCBGA - 2.57 mm max height
BALL GRID ARRAY
(0.8) TYP
441X 0.4
(0.8) TYP
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
A
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 6X
4228316/A 12/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ALW0425A
FCCSP - 0.89 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC BALL GRID ARRAY
13.1
12.9
B
A
BALL A1
CORNER
13.1
12.9
0.1 C
0.89
0.77
0.2 C
C
SEATING PLANE
0.08 C
0.284
0.184
12 TYP
SYMM
(0.5)
(0.5)
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
SYMM
12 TYP
K
J
H
G
F
E
D
C
0.35
425X
0.25
B
A
0.15
C A B
C
0.08
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
0.5 TYP
0.5 TYP
4227026/B 06/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ALW0425A
FCCSP - 0.89 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
425X ( 0.25)
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.25)
(
0.25)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4227026/B 06/2023
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ALW0425A
FCCSP - 0.89 mm max height
PLASTIC BALL GRID ARRAY
(0.5) TYP
425X ( 0.25)
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4227026/B 06/2023
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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