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AM6421BSEFHAALV [TI]

单核 64 位 Arm® Cortex®-A53，双核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性 | ALV | 441 | -40 to 105;
AM6421BSEFHAALV
型号： AM6421BSEFHAALV
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

单核 64 位 Arm® Cortex®-A53，双核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性 | ALV | 441 | -40 to 105

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AM6442, AM6441, AM6422, AM6421, AM6412, AM6411  
ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
AM64x Sitara™ 处理器  
• 兼容16550 且具有专用192MHz 时钟的  
UART，支持12Mbps PROFIBUS  
1 特性  
处理器内核：  
存储器子系统：  
• 1 个双核64 位Arm® Cortex®-A53 微处理器系统，  
性能高达1.0GHz  
• 具有SECDED ECC 的高达2MB 的片上RAM  
(OCSRAM)：  
– 双核Cortex-A53 集群（具有256KB L2 共享缓  
存，包括SECDED ECC）  
– 每个A53 内核包含具有SECDED ECC 功能的  
32KB L1 DCache 和具有奇偶校验保护的32KB  
L1 ICache  
– 可以按256KB 的增量分成更小的存储器组，多  
达8 个独立的存储器组  
– 每个存储器组可分配给一个内核以简化软件任务  
分区  
• DDR 子系统(DDRSS)  
• 最多2 个双核Arm® Cortex®-R5F MCU 子系统，工  
作频率高达800MHz，集成用于实现实时处理  
– 支持LPDDR4、DDR4 存储器类型  
– 具有内联ECC 的16 位数据总线  
– 支持高达1600MT/s 的速度  
– 双核Arm® Cortex®-R5F 支持双核和单核模式  
– 每个R5F 内核32KB ICache、32KB DCache  
和64KB TCM，总共256KB TCM，所有存储器  
上都有SECDED ECC  
• 1 个通用存储器控制器(GPMC)  
– 具有133MHz 时钟的16 位并行总线或  
– 具有100MHz 时钟的32 位并行总线  
– 错误定位模块(ELM) 支持  
• 1 个单核Arm® Cortex®-M4F MCU，高达400MHz  
– 具有SECDED ECC 的256KB SRAM  
片上系统(SoC) 服务：  
工业子系统：  
• 设备管理安全控制器(DMSC-L)  
• 2 个千兆位工业通信子系统(PRU_ICSSG)  
– 支持Profinet IRT、Profinet RT、EtherNet/IP、  
EtherCAT 和时间敏感网络(TSN) 等等  
– 向后兼容10/100Mb PRU_ICSS  
– 集中式SoC 系统控制器  
– 管理系统服务，包括初始引导、信息安全、和时  
钟/复位/电源管理  
– 通过消息管理器与各种处理单元通信  
– 简化的接口可优化未使用的外设  
• 数据移动子系统(DMSS)  
– 每个PRU_ICSSG 包含：  
• 2 个以太网端口  
– MII (10/100)  
– 块复制DMA (BCDMA)  
– 数据包DMA (PKTDMA)  
– 安全代理(SEC_PROXY)  
– 环形加速器(RINGACC)  
– RGMII (10/100/1000)  
• 每个PRU_ICSSG 6 个PRU RISC 内核，而  
每个内核具有：  
– 具有ECC 的指令RAM  
– 宽边RAM  
信息安全：  
– 具有可选累加器的乘法器(MAC)  
– CRC16/32 硬件加速器  
– 用于大/小端字节序转换的字节交换  
– 用于UDP 校验和的SUM32 硬件加速器  
– 支持抢占的任务管理器  
• 支持安全启动  
– 硬件强制可信根(ROT)  
– 支持通过备用密钥转换RoT  
– 支持接管保护、IP 保护和防回滚保护  
• 支持加密加速  
• 三个具有ECC 的数据RAM  
• 8 组30 × 32 位寄存器暂存区存储器  
• 中断控制器和任务管理器  
• 两个用于时间戳和其他时间同步功能的64 位  
工业以太网外设(IEP)  
– 会话感知型加密引擎可基于输入数据流自动切换  
密钥材料  
– 支持加密内核  
• AES –128/192/256 位密钥大小  
• 3DES –56/112/168 位密钥大小  
• MD5、SHA1  
• SHA2 –224/256/384/512  
• 具有真随机数生成器的DRBG  
• 可在RSA/ECC 处理中提供帮助的PKA（公  
钥加速器）  
• 18 个Σ-Δ滤波器  
– 短路逻辑  
– 过流逻辑  
• 6 个多协议位置编码器接口  
• 一个增强型捕捉模块(ECAP)  
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问  
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SPRSP56  
 
 
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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– DMA 支持  
• 调试安全性  
通用连接：  
• 6 个内部集成电路(I2C) 端口  
– 受安全软件控制的调试访问  
– 安全感知调试  
• 支持可信执行环境(TEE)  
– 基于Arm TrustZone® 的TEE  
– 可实现隔离的广泛防火墙支持  
– 安全监视器/计时器/IPC  
• 安全存储支持  
• 9 个可配置的通用异步接收/发送(UART) 模块  
• 1 个可配置为八通道SPI (OSPI) 闪存接口或一个四  
通道SPI (QSPI) 的闪存子系统(FSS)  
• 1 个12 位模数转换器(ADC)  
– 高达4MSPS  
– 8 个多路复用模拟输入  
• 7 个多通道串行外设接口(MCSPI) 控制器  
• 6 个快速串行接口接收器(FSI_RX) 内核  
• 2 个快速串行接口发送器(FSI_TX) 内核  
• 3 个通用I/O (GPIO) 模块  
• 支持XIP 模式下OSPI 接口的实时加密  
• 通过基于数据包的硬件加密引擎为数据（有效载  
荷）加密/认证提供网络安全支持  
• 用于密钥和安全管理的安全协处理器(DMSC-L)，  
具有用于确保安全的专用设备级互连  
控制接口：  
高速接口：  
• 9 个增强型脉冲宽度调制器(EPWM) 模块  
• 3 个增强型捕捉(ECAP) 模块  
• 3 个增强型正交编码器脉冲(EQEP) 模块  
• 2 个模块化控制器区域网(MCAN) 模块，具有或不  
具有完整CAN-FD 支持  
• 1 个集成以太网交换机(CPSW3G) 支持：  
– 多达2 个以太网端口  
• RMII (10/100)  
• RGMII (10/100/1000)  
– IEEE 1588（2008 附件D、E 和F）及  
802.1AS PTP  
– 第45 条MDIO PHY 管理规范  
– 节能以太网(802.3az)  
媒体和数据存储：  
• 2 个多媒体卡/安全数字(MMC/SD/SDIO) 接口  
– 一个4 位，用于SD/SDIO；  
– 一个8 位，用于eMMC  
• 1 个PCI-Express® 第2 代控制器(PCIE)  
– 适用于高速卡在3.3V 至1.8V 电压之间切换的  
– 支持第2 代运行  
– 支持单通道运行  
集成模拟开关  
• 1 个USB 3.1 双角色器件(DRD) 子系统(USBSS)  
电源管理：  
– 可配置为USB 主机、  
USB 器件或  
USB 双角色器件的端口  
– USB 器件：高速(480Mbps) 和  
全速(12Mbps)  
• 的简化电源序列  
• 集成的SDIO LDO 可为SD 接口处理自动电压转换  
• 集成了电压监控器，可对过欠压状态进行安全监控  
• 集成了电源干扰检测器，可检测快速电源瞬变  
– USB 主机：SuperSpeed 第1 代(5Gbps)、  
高速(480Mbps)、  
全速(12Mbps) 和  
低速(1.5Mbps)  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
功能安全：  
SoC 架构：  
• 以功能安全合规型为目标  
• 支持从UART、I2C、OSPI/QSPI 闪存、SPI 闪  
存、并行NOR 闪存、并行NAND 闪存、SD、  
eMMC、USB、PCIe 和以太网接口进行主引导  
• 16nm FinFET 技术  
– 专为功能安全应用开发  
– 将提供相关文档来协助进行符合IEC 61508 标  
准的功能安全系统设计  
– 系统可满足SIL 3 要求  
– 硬件完整性高达SIL 2 目标等级  
– 安全相关认证  
• 17.2mm × 17.2mm、0.8mm 间距、441 引脚BGA  
封装  
• 计划通过IEC 61508 认证  
– 计算临界存储器具有ECC 或奇偶校验  
– 部分内部总线互连具有ECC 和奇偶校验  
– 针对CPU 和片上RAM 的内置自检(BIST)  
– 带有错误引脚的错误信令模块(ESM)  
– 运行时安全诊断，电压、温度和时钟监控，窗口  
式看门狗计时器，用于存储器完整性检查的  
CRC 引擎  
– 专用MCU 域存储器、接口和M4F 内核，能够  
与具有防止干扰(FFI) 功能的更大SoC 隔离  
• 独立互连  
• 防火墙和超时垫圈  
• 专用PLL  
• 专用I/O 电源  
• 单独复位  
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2 应用  
• 可编程逻辑控制器(PLC)  
• 电机驱动器  
• 远程I/O  
• 工业机器人  
• 状态监控网关  
3 说明  
AM64x 是 Sitara™ 新增的工业级异构 Arm® 处理器产品系列，专为要求独特结合实时处理和通信与应用处理的电  
机驱动器和可编程逻辑控制器 (PLC) 等工业应用而构建。AM64x 将两个支持 TSN 技术的 Sitara 器件千兆位  
PRU-ICSSG 实例与最多两个 Arm® Cortex®-A53 内核、最多四个 Cortex-R5F MCU 和一个Cortex-M4F MCU 合  
并到一起。  
AM64x 旨在通过高性能 R5F 内核、紧密耦合的存储器组、可配置的 SRAM 分区和进出外设的专用低延迟路径提  
供出色的实时性能，从而实现数据快速进出 SoC。这种确定性架构允许 AM64x 处理伺服驱动器中的严格控制环  
路，同时 FSI、GPMC、PWM、Δ-Σ 抽取滤波器和绝对编码器接口等外设可帮助启用这些系统中的多种不同架  
构。  
Cortex-A53 提供了 Linux 应用所必需的强大计算元件。Linux 和实时 (RT) Linux 则通过 TI 的 Processor SDK  
Linux 提供，后者会每年更新为最新的长期支持 (LTS) Linux 内核、引导加载程序和 Yocto 文件系统。AM64x 通过  
可配置的内存分区在 Linux 应用和实时数据流之间实现隔离，从而帮助桥接 Linux 世界与现实世界。Cortex-A53  
可分配到采用Linux 的DDR 中严格工作，而内部SRAM 可以拆分成各种大小，供Cortex-R5F 综合或单独使用。  
AM64x 提供灵活的工业通信能力，包括用于 EtherCAT 子器件、PROFINET 器件、EtherNet/IP 适配器和 IO-Link  
主站的全协议栈。PRU-ICSSG 进一步提供了千兆位和基于 TSN 技术的协议所需的能力。此外，PRU-ICSSG 还  
支持SoC 中的其他接口，包括Δ-Σ抽取滤波器和绝对编码器接口。  
可通过集成的Cortex-M4F 及其专用外设启用功能安全特性，这些外设均可与 SoC 的其余部分隔离。AM64x 还支  
持安全启动。  
封装信息  
封装(1)  
器件型号  
AM6442...ALV  
封装尺寸  
17.2mm × 17.2mm  
17.2mm × 17.2mm  
17.2mm × 17.2mm  
FCBGA（441 引脚）  
FCBGA（441 引脚）  
FCBGA（441 引脚）  
FCBGA（441 引脚）  
FCBGA（441 引脚）  
FCBGA（441 引脚）  
AM6441...ALV  
AM6422...ALV  
AM6421...ALV  
AM6412...ALV  
AM6411...ALV  
17.2mm × 17.2mm  
17.2mm × 17.2mm  
17.2mm × 17.2mm  
(1) 如需了解更多信息，请参阅机械、封装和可订购信息。  
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3.1 功能方框图  
图3-1 是器件的功能方框图。  
备注  
要了解TI 软件开发套件(SDK) 目前支持的器件功能，请参阅AM64x 软件构建表。  
AM64x  
Application cores  
Real-time cores  
Isolated core(A)  
®
Arm®  
Arm®  
Arm®  
Arm®  
Arm®  
Arm®  
Arm  
Cortex -A53  
®
Cortex®-A53  
Cortex®-R5F Cortex®-R5F Cortex®-R5F Cortex®-R5F  
Cortex®-M4F  
256KB L2 with ECC  
128KB TCM  
System Memory  
128KB TCM  
256KB SRAM  
DDR4/LPDDR4 with inline ECC  
2 MB SRAM with ECC  
2x MMCSD  
Security  
System Services  
SHA  
MD5  
PKA  
DRBG  
12x GP Timers  
AES  
Sync  
Manager  
Secure  
Boot  
4x WWDT  
3DES  
Isolated Connectivity(A)  
(for use with Cortex-M4F)  
Industrial Connectivity  
General Connectivity  
PCIe(C)  
1x Single lane  
Gen 2  
GPMC / ELM  
8x FSI  
GPIO  
5x MCSPI  
4x I2C  
PRU-ICSS(Gb)  
Encoder  
with 9x ∑∆  
GPIO  
2x MCSPI  
2x I2C  
2x GMAC  
9x EPWM  
3x ECAP  
3x EQEP  
2x CAN-FD  
3-port Gb  
Ethernet(B)  
7x UART  
PRU-ICSS(Gb)  
1x USB 3.1 DRD(C)  
2x UART  
OSPI or QSPI  
1x ADC  
Encoder  
2x GMAC  
with 9x ∑∆  
intro_001  
A. 外设与M4F 内核隔离是一项可选功能。在非隔离配置中，MCU 域资源可跨SoC 共享。  
B. 一个端口仅用于内部连接；不连接到任何引脚。  
C. USB SuperSpeed 和PCIe 共用一个通用串行器/解串器PHY。因此，将串行器/解串器PHY 用于PCIe 时，USB 将被限制为非  
SuperSpeed 模式。  
图3-1. 功能方框图  
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Table of Contents  
7.9 Thermal Resistance Characteristics........................111  
7.10 Timing and Switching Characteristics................... 112  
8 Detailed Description....................................................230  
8.1 Overview.................................................................230  
8.2 Processor Subsystems........................................... 231  
8.3 Accelerators and Coprocessors..............................233  
8.4 Other Subsystems.................................................. 233  
9 Applications, Implementation, and Layout............... 241  
9.1 Device Connection and Layout Fundamentals....... 241  
9.2 Peripheral- and Interface-Specific Design  
Information................................................................ 242  
10 Device and Documentation Support........................249  
10.1 Device Nomenclature............................................249  
10.2 Tools and Software............................................... 252  
10.3 Documentation Support........................................ 252  
10.4 支持资源................................................................252  
10.5 Trademarks...........................................................252  
10.6 Electrostatic Discharge Caution............................253  
10.7 术语表................................................................... 253  
11 Mechanical, Packaging, and Orderable  
1 特性................................................................................... 1  
2 应用................................................................................... 4  
3 说明................................................................................... 4  
3.1 功能方框图..................................................................5  
4 Revision History.............................................................. 7  
5 Device Comparison.......................................................10  
5.1 Related Products...................................................... 12  
6 Terminal Configuration and Functions........................13  
6.1 Pin Diagrams............................................................ 13  
6.2 Pin Attributes.............................................................14  
6.3 Signal Descriptions................................................... 60  
6.4 Pin Connectivity Requirements.................................95  
7 Specifications................................................................ 99  
7.1 Absolute Maximum Ratings...................................... 99  
7.2 ESD Ratings........................................................... 101  
7.3 Power-On Hours (POH)..........................................101  
7.4 Recommended Operating Conditions.....................102  
7.5 Operating Performance Points................................103  
7.6 Power Consumption Summary............................... 103  
7.7 Electrical Characteristics.........................................104  
7.8 VPP Specifications for One-Time Programmable  
Information.................................................................. 254  
11.1 Packaging Information.......................................... 254  
(OTP) eFuses............................................................110  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
4 Revision History  
Changes from July 16, 2022 to September 21, 2022 (from Revision D (JULY 2022) to Revision E  
(SEPTEMBER 2022))  
Page  
• 通篇：将文档产品状态从“预告信息”更改为“量产数据”.............................................................................. 1  
•
（特性）：更新了USB 特性以阐明器件和主机模式支持的速度........................................................................ 1  
（特性）：更新了“硬件完整性高达SIL 2 目标等级”要点以删除“针对MCU 域，”，因为新目标包括MCU  
和主域.................................................................................................................................................................1  
（应用）：添加了带链接的“状态监控网关”要点.............................................................................................4  
（功能方框图）：更新了注释C 以阐明当通用串行器/解串器PHY 用于PCIe 时的USB 速度限制...................5  
•
•
•
• (Device Comparison): Changed "Industrial Communication Subsystem Support" to "PRU_ICSSG Industrial  
Communication Support" and changed content of notes associated with PRU_ICSSG to clarify PRU_ICSSG  
features are still enabled on devices that do not enable Industrial Communication Support........................... 10  
• (Device Comparison): Added a new note to clarify USB speed limitations when shared SerDes PHY is being  
used for PCIe....................................................................................................................................................10  
• (Pin Attributes - BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/  
PULL): Added "NA: Not Applicable" to the description to help clarify the I2C Open-drain Fail-safe (I2C OD  
FS) buffer type does not having internal pulls.................................................................................................. 14  
• (Pin Attributes - Pins C19, A18, B18, E9, and A10): Changed the "PULL" value in the "BALL STATE DURING  
RESET RX/TX/PULL" and "BALL STATE AFTER RESET RX/TX/PULL" columns from "Off" to "NA" to help  
clarify the I2C Open-drain Fail-safe (I2C OD FS) buffer type does not having internal pulls........................... 18  
• (Pin Attributes - Pin G18, J21, G19, K20, J20, J18, J17, H17, H19, H18, G17): Defined values in the "BALL  
STATE DURING RESET RX/TX/PULL" and "BALL STATE AFTER RESET RX/TX/PULL" columns for each  
pin.....................................................................................................................................................................18  
• (Pin Attributes - Pin F18): Removed the "PU/PD" value from the "PULL UP/DOWN TYPE" column since this  
pin does not having internal pulls..................................................................................................................... 18  
• (ADC0 Signal Descriptions): Updated note associated with ADC0_REFP and ADC_REFN to clarify  
connectivity requirements.................................................................................................................................60  
• (DDRSS0 Signal Descriptions): Updated note associated with DDR_CAL0 to include maximum power  
dissipation expected for calibration resistor......................................................................................................60  
• (EQEP0 Signal Descriptions): Added a note and note references to identify each EQEP with a debounce  
function on its input...........................................................................................................................................60  
• (EQEP1 Signal Descriptions): Added a note and note references to identify each EQEP with a debounce  
function on its input...........................................................................................................................................60  
• (EQEP2 Signal Descriptions): Added a note and note references to identify each EQEP with a debounce  
function on its input...........................................................................................................................................60  
• (USB0 Signal Descriptions): Changed the maximum power dissipation expected for the USB0_RCALIB  
calibration resistor from 7.5mW to 7.2mW........................................................................................................60  
• (Pin Connectivity Requirements): Deleted pin J15 from the row associated with VDDS_MMC0.....................95  
• (Absolute Maximum Ratings): Defined values for all previously undefined TBD values.................................. 99  
• (Absolute Maximum Ratings): Changed all 3.8V maximum values to 3.63V....................................................99  
• (Absolute Maximum Ratings): Changed all 2.2V maximum values to 1.98V except MCU_PORz, which was  
changed to 3.63V..............................................................................................................................................99  
• (ESD Ratings): Replaced TBD values with tested values.............................................................................. 101  
• (Speed Grade Maximum Frequency): Defined values for all previously undefined TBD values.................... 103  
• (Power Consumption Summary): Added a link to the AM64x/AM243x Power Estimation Tool application note  
........................................................................................................................................................................103  
• (I2C OD FS Electrical Characteristics): Defined maximum VIH values for 1.8-V mode and 3.3-V mode and  
included a note that describes how these values also define the absolute maximum input voltage. Removed  
the typical Input Leakage Current value and several TBD values which were not applicable........................104  
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• (I2C OD FS Electrical Characteristics): Removed the typical Input Leakage Current value and several TBD  
values which were not applicable................................................................................................................... 104  
• (I2C OD FS Electrical Characteristics): Defined the minimum input slew rate value and added notes to  
describe this parameter.................................................................................................................................. 104  
• Removed non-applicable TBD values. .......................................................................................................... 105  
• Defined the minimum input slew rate value and added notes to describe this parameter..............................105  
• (High-Frequency Oscillator (HFOSC) Electrical Characteristics): Defined maximum Input Leakage Current  
value............................................................................................................................................................... 105  
• (SDIO Electrical Characteristics): Removed non-applicable TBD values from 3.3-V mode Input Slew Rate.106  
• (SDIO Electrical Characteristics): Defined the minimum input slew rate value and added notes to describe  
this parameter.................................................................................................................................................106  
• (LVCMOS Electrical Characteristics): Removed non-applicable TBD values from 1.8-V mode and 3.3-V mode  
Input Slew Rate.............................................................................................................................................. 107  
• (LVCMOS Electrical Characteristics): Defined the minimum input slew rate value and added notes to describe  
this parameter.................................................................................................................................................107  
• (ADC12B Electrical Characteristics): Added Positive Reference Voltage and Negative Reference Voltage  
parameters, with a note that describes connectivity requirements for the ADC0_REFP and ADC0_REFN pins  
........................................................................................................................................................................108  
• (ADC12B Electrical Characteristics): Changed the Differential Non-Linearity values; the minimum value was  
changed from -1 to > -1 to indicate there is no missing codes, the typical value was removed, and the  
maximum value was changed from 2 to +1.................................................................................................... 108  
• (ADC12B Electrical Characteristics): Changed the Integral Non-Linearity values; the minimum value was  
changed to -2, the typical value was removed, and the maximum value was changed from ±3 to +2...........108  
• (ADC12B Electrical Characteristics): Changed the typical Gain Error value from ±2 to ±10..........................108  
• (ADC12B Electrical Characteristics): Changed the typical Offset Error value from ±2 to ±5..........................108  
• (ADC12B Electrical Characteristics): Changed the “Input Sampling Capacitance (CIN)”parameter to  
“Sampling Capacitance (CSMPL)”, with the same typical value.................................................................. 108  
• (ADC12B Electrical Characteristics): Changed the typical Total Harmonic Distortion value from 75 to -75...108  
• (ADC12B Electrical Characteristics): Removed the Spurious Free Dynamic Range and Signal-to-Noise Plus  
Distortion parameters..................................................................................................................................... 108  
• (ADC12B Electrical Characteristics): Changed the “Input Impedance of ADC0_AIN[7:0]  
(RADC0_AIN[7:0])”parameter to “Analog Input Impedance, ADC0_AIN[7:0] (ZADC0_AIN[7:0])”and  
replaced the formula for calculating a typical value with a note that clarifies input impedance of the  
ADC0_AIN[7:0] analog inputs.........................................................................................................................108  
• (ADC12B Electrical Characteristics): Removed the VSS and VDDA_ADC0 test conditions from the Input  
Leakage parameter and defined a single maximum value that represents the entire input voltage range of the  
ADC0_AIN[7:0] analog inputs.........................................................................................................................108  
• (ADC12B Electrical Characteristics): Removed the Channel to Channel Isolation parameter.......................108  
• (ADC12B Electrical Characteristics): Changed the maximum input leakage of General Purpose Input Mode  
from 2μA to 10μA.........................................................................................................................................108  
• (Power-Up Sequencing): Added a separate waveform for VDDSHV5 with a reference to Note 12 that clarifies  
this power rail supports power-up, power-down, or dynamic voltage change without any dependency on other  
power rails.......................................................................................................................................................115  
• (Power-Down Sequencing): Added a separate waveform for VDDSHV5 with a reference to Note 6 that  
clarifies this power rail supports power-up, power-down, or dynamic voltage change without any dependency  
on other power rails.........................................................................................................................................117  
• Included "Recommended Clock, System, and Control Signal Transition Behavior" section and associated  
details............................................................................................................................................................. 132  
• (Clock Specifications): Included an new/updated section titled "Recommended System Precautions for Clock  
and Control Signal Transitions"...................................................................................................................... 132  
• (CPSW3G): Updated the Note to reference the CPSW3G IOSETs section for the several tables contained  
within the section............................................................................................................................................ 133  
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• (GPIO Timing Conditions): Changed the minimum Input Slew rate for the LVCMOS buffer type, and defined  
Input Slew Rate values for the I2C OD FS buffer type................................................................................... 147  
• (GPIO Timing Requirements): Changed the "BUFFER TYPE" column to "MODE", replaced buffer types with  
operating voltage, retained the minimum pulse width value for 1.8-V mode, and changed the minimum pulse  
width value for 3.3-V mode.............................................................................................................................147  
• (GPMC and NOR Flash —Synchronous Mode): Changed the "not_div_by_1_mode"minimum value in the  
"Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (th(clkH-waitV))" parameter from  
2.9 to 2.29 to correct a typographical error.....................................................................................................148  
• (GPMC and NAND Flash —Asynchronous Mode): Removing the TBD maximum value from the "Pulse  
duration, output write enable GPMC_WEn valid (tw(wenV))" parameter since a maximum value is not  
applicable for this parameter.......................................................................................................................... 166  
• (I2C Timing): Removed all timing parameter tables and diagrams, and referenced the Philips I2C-bus™  
specification version 2.1 as the source for this information. Added per port descriptions that define each  
speed mode supported and included additional information that details exceptions to the I2C specification 172  
• (I2C Timing): Added per port descriptions that define each speed mode supported and included additional  
information that details exceptions to the I2C specification............................................................................172  
• (MCSPI - Controller Mode): Inclusive Nomenclature Updates....................................................................... 175  
• (MCSPI - Peripheral Mode): Inclusive Nomenclature Updates.......................................................................177  
• (OSPI Switching Characteristics –PHY Data Training): Defined values for all previously undefined TBD  
values............................................................................................................................................................. 197  
• (OSPI0 Timing Requirements –PHY SDR Mode): Updated all setup and hold values................................199  
• (PRU_ICSSM UART Timing Conditions): Changed the minimum and maximum values for Input Slew Rate,  
and added a note to the maximum output load capacitance value in the Timing Conditions table................ 216  
• (PRU_ICSSG UART Timing Requirements): Changed the description for each pulse width parameter, added  
a note that clarifies the data valid time requirements for each parameter in the Timing Requirements table 216  
• (PRU_ICSSG UART Timing Requirements and Switching Characteristics): Updated the timing diagram to  
show RXD timing relative to VIL and VIH ........................................................................................................216  
• (UART Timing Conditions): Added a note to the maximum output load capacitance value in the Timing  
Conditions table..............................................................................................................................................226  
• (UART Timing Requirements): Changed the start pulse width parameter description and added a note that  
clarifies the data valid time requirements for each parameter in the Timing Requirements table.................. 226  
• (UART Switching Characteristics): Added a new row for Programmable baud rate with different limits for Main  
Domain and MCU Domain UARTs..................................................................................................................226  
• (UART Switching Characteristics): Changed the start pulse width parameter description, removed the CTS  
delay parameter, and removed the load capacitance references from the Programmable baud rate parameter  
........................................................................................................................................................................226  
• (UART Timing Requirements and Switching Characteristics): Updated the timing diagram to remove CTS and  
show RXD timing relative to VIL and VIH ........................................................................................................226  
• (UART): Updated maximum baud rate from 3.6864 Mbps to 12 Mbps on all UARTs except MCU_UART0 and  
MCU_UART1..................................................................................................................................................239  
• (Universal Serial Bus Subsystem): Removed references to OTG support and USB SuperSpeed support when  
operating as USB device................................................................................................................................ 240  
• (Power Supply Designs): Changed section title from "Power Supply Decoupling and Bulk Capacitors" to  
"Power Supply"...............................................................................................................................................241  
• (Power Supply Designs): Changed section title from "Power Supply Mapping" to "Power Supply Designs" and  
included PMIC recommendations and associated content links.....................................................................241  
• Updating the xref href attribute value to correct ti.com link. (ZF)no................................................................241  
• (Device Naming Convention): Changed descriptions associated with Feature codes to clarify PRU_ICSSG  
features are still enabled on devices that do not enable Industrial Communication Support, and changed the  
Security feature code from "Other" to "H".......................................................................................................251  
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5 Device Comparison  
表5-1 shows a comparison between devices, highlighting the differences.  
备注  
Availability of features listed in this table are a function of shared IO pins, where IO signals associated  
with many of the features are multiplexed to a limited number of pins. The SysConfig tool should be  
used to assign signal functions to pins. This will provide a better understanding of limitations  
associated with pin multiplexing.  
备注  
To understand what device features are currently supported by TI Software Development Kits (SDKs),  
see the AM64x Software Build Sheet.  
表5-1. Device Comparison  
REFERENCE  
FEATURES  
AM6442  
AM6441  
AM6422  
AM6421  
AM6412  
AM6411  
NAME  
C: 0x19403  
C: 0x19203  
CTRLMMR_WKUP_JTAG_DEVICE_ID[31:13] DEVICE_ID register D: 0x19464  
D: 0x19264  
E: 0x19265  
F: 0x19266  
D: 0x19424  
D: 0x19224  
E: 0x19225  
F: 0x19226  
bit field value(1)  
E: 0x19465  
F: 0x19466  
PROCESSORS AND ACCELERATORS  
Speed Grades (See 表7-1)  
S
S
S
S
S, K  
S, K  
Arm Cortex-A53 Microprocessor Subsystem  
Arm A53  
Arm R5F  
Dual Core  
Single Core  
Dual Core  
Single Core  
Dual Core  
Single Core  
2 ×  
Dual Core  
2 ×  
Dual Core  
1 ×  
Dual Core  
1 ×  
Dual Core  
Arm Cortex-R5F  
Single Core  
Single Core  
Single Core  
Functional  
Safety  
Single Core  
Functional Safety Optional(4)  
Arm Cortex-M4F  
Arm M4F  
Single Core  
Single Core  
Optional(4)  
Device Management Security Controller  
Crypto Accelerators  
DMSC-L  
Security  
Yes  
Yes  
PROGRAM AND DATA STORAGE  
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM  
R5F Tightly Coupled Memory (TCM) TCM  
On-Chip Shared Memory (RAM) in M4F Domain MCU_MSRAM  
2MB  
256KB  
256KB  
256KB  
256KB  
128KB  
128KB  
256KB  
DDR4/LPDDR4 DDR Subsystem  
General-Purpose Memory Controller  
PERIPHERALS  
DDRSS  
GPMC  
Up to 2GB (16-bit data) with inline ECC  
Up to 1GB with ECC  
Modular Controller Area Network Interface  
Full CAN-FD Support(2)  
MCAN  
2
MCAN  
Optional  
Optional  
No  
Optional  
Up to 198  
No  
No  
No  
No  
General-Purpose I/O  
GPIO  
Inter-Integrated Circuit Interface  
Analog-to-Digital Converter  
I2C  
6
ADC  
1
Multichannel Serial Peripheral Interface  
MCSPI  
7
MMCSD0  
MMCSD1  
FSI_TX  
FSI_RX  
OSPI0/QSPI0  
PCIE0  
eMMC (8-bits)  
Multi-Media Card/ Secure Digital Interface  
Fast Serial Interface  
SD/SDIO (4-bits)  
2
6
Flash Subsystem (FSS)(3)  
Yes  
PCI Express Port with Integrated SerDes PHY  
Programmable Real-Time Unit Subsystem(5)  
Single Lane(7)  
2
PRU_ICSSG  
PRU_ICSSG Industrial Communication  
Support(6)  
PRU_ICSSG  
CPSW3G  
Optional  
No  
No  
Gigabit Ethernet Interface  
Yes  
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表5-1. Device Comparison (continued)  
REFERENCE  
NAME  
FEATURES  
AM6442  
AM6441  
AM6422  
AM6421  
AM6412  
AM6411  
General-Purpose Timers  
TIMER  
EPWM  
ECAP  
EQEP  
16 (4 in MCU Channel)  
Enhanced Pulse-Width Modulator Module  
Enhanced Capture Module  
9
3
3
Enhanced Quadrature Encoder Pulse Module  
Universal Asynchronous Receiver and  
Transmitter  
UART  
USB0  
9
Universal Serial Bus (USB3.1 Gen1) SuperSpeed  
Dual-Role-Device (DRD) Ports with SS SerDes  
PHY and USB 2.0 PHY  
Yes(7)  
(1) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device TRM.  
(2) Full CAN-FD Support is available when selecting an orderable part number that includes a feature code of E or F. Refer to  
Nomenclature Description table for the definition of feature codes.  
(3) One flash interface, configured as OSPI0 or QSPI0.  
(4) Functional Safety is available when selecting an orderable part number that includes a feature code of F. Refer to Nomenclature  
Description table for the definition of feature codes.  
(5) Orderable part numbers with a feature code of C support using PRU_ICSSG for use cases other than industrial communication. Refer  
to Nomenclature Description table for the definition of feature codes.  
(6) PRU_ICSSG industrial communication includes Ethernet networking (MII/RGMII, MDIO), Sigma-Delta (SD) decimation, and three  
channel peripheral interface (EnDat 2.2 and BiSS). PRU_ICSSG industrial communication support is available when selecting an  
orderable part number that includes a feature code of D, E, or F. Refer to Nomenclature Description table for the definition of feature  
codes.  
(7) USB SuperSpeed and PCIe share a common SerDes PHY. Therefore, USB will be limited to non-SuperSpeed modes when using the  
SerDes PHY for PCIe.  
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5.1 Related Products  
Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores with flexible  
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara  
processors have the reliability needed for use in industrial applications.  
AM64x Sitara™ processors AM6x processors enable gigabit industrial Ethernet networks, robust operation  
with extensive ECC on memories, and enhanced security features. Additional features such as an integrated  
lockstep MCU subsystem and diagnostic libraries help enable functional safety systems.  
Sitara™ processors - Applications Sitara™ processors provide scalable solutions for a wide range of  
applications from HMIs and gateways to more complex equipment such as drives and substation automation  
equipment. Sitara processors also offer multi-protocol support for industrial communication protocols such as  
EtherCAT®, Ethernet/IP, and Profinet.  
Sitara™ processors - Reference designs TI provides many reference designs containing ‘building block’  
solutions to enable customers to rapidly develop their own unique products and solutions.  
Companion Products for AM64x Review products that are frequently purchased or used in conjunction with  
this product to complete your design.  
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6 Terminal Configuration and Functions  
6.1 Pin Diagrams  
备注  
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt  
is made to use "ball" only when referring to the physical package.  
图 6-1 shows the ball locations for the 441-ball flip chip ball grid array (FCBGA) package to quickly locate signal  
names and ball grid numbering. This figure is used in conjunction with 表 6-1 through 表 6-80 (Pin Attributes  
table and all Signal Descriptions tables, including the Connectivity Requirements table).  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
PRG1  
_MDIO0  
_MDIO  
PRG0_PRU0 PRG0_PRU0 PRG0_PRU1 PRG0_PRU0  
_GPO4 _GPO12 _GPO16 _GPO10  
PRG1_PRU0 PRG1_PRU0 PRG1_PRU0 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1  
SERDES0  
_TX0_N  
SERDES0  
_TX0_P  
AA  
Y
W
V
U
T
VSS  
VSS  
VSS  
USB0_DP  
USB0_DM  
VSS  
_GPO6  
_GPO11  
_GPO14  
_GPO11  
_GPO14  
_GPO2  
_GPO5  
_GPO17  
VSS  
PRG1  
_MDIO0  
_MDC  
PRG0_PRU0 PRG0_PRU1 PRG0_PRU0 PRG0_PRU1 PRG0_PRU1  
_GPO0 _GPO0 _GPO11 _GPO12 _GPO9  
PRG1_PRU0 PRG1_PRU0 PRG1_PRU0 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1  
_GPO0  
SERDES0  
_RX0_N  
SERDES0  
_RX0_P  
GPMC0  
_WAIT1  
GPMC0  
_AD15  
GPMC0  
_AD14  
VSS  
VSS  
_GPO4  
_GPO15  
_GPO16  
_GPO15  
_GPO3  
_GPO18  
PRG0_PRU0 PRG0_PRU1 PRG0_PRU1 PRG0_PRU1 PRG0_PRU1 PRG0_PRU0 PRG1_PRU0 PRG1_PRU0 PRG1_PRU0  
_GPO19 _GPO1 _GPO4 _GPO11 _GPO7 _GPO9 _GPO19 _GPO2 _GPO13  
PRG1_PRU1 PRG1_PRU1 PRG1_PRU0 PRG1_PRU1  
_GPO0 _GPO4 _GPO8 _GPO10  
SERDES0  
_REFCLK0N _REFCLK0P  
SERDES0  
GPMC0  
_WAIT0  
GPMC0  
_AD11  
GPMC0  
_AD12  
VSS  
RSVD4  
VSS  
PRG0_PRU0 PRG0_PRU0 PRG0_PRU1 PRG0_PRU0 PRG0_PRU1 PRG0_PRU1 PRG1_PRU0 PRG1_PRU0 PRG1_PRU0 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1 PRG1_PRU0 PRG1_PRU1 PRG1_PRU1  
GPMC0  
_AD13  
RSVD5  
USB0_ID  
VSS  
VSS  
GPMC0_AD8 GPMC0_AD6 GPMC0_AD7  
_GPO18  
_GPO3  
_GPO2  
_GPO14  
_GPO17  
_GPO10  
_GPO18  
_GPO3  
_GPO16  
_GPO12  
_GPO1  
_GPO19  
_GPO5  
_GPO9  
_GPO7  
PRG0_PRU0 PRG0_PRU0  
_GPO17 _GPO2  
PRG0_PRU0 PRG0_PRU1 PRG0_PRU1 PRG1_PRU0 PRG1_PRU0 PRG1_PRU0 PRG1_PRU1 PRG1_PRU1 PRG1_PRU1 PRG1_PRU0 PRG1_PRU0 PRG1_PRU0  
USB0  
_RCALIB  
VSS  
GPMC0_AD4 GPMC0_AD5 GPMC0_AD3 GPMC0_AD1  
_GPO16  
_GPO15  
_GPO14  
_GPO17  
_GPO1  
_GPO12  
_GPO13  
_GPO6  
_GPO8  
_GPO7  
_GPO10  
_GPO9  
PRG0_PRU0 PRG0_PRU0 PRG0_PRU0 PRG0_PRU1 PRG0_PRU0 PRG0_PRU1  
_GPO7 _GPO8 _GPO6 _GPO3 _GPO15 _GPO13  
VDDA_0P85  
_USB0  
SERDES0  
_REXT  
GPMC0  
_BE1n  
CAP_VDDS1  
VSS  
VDDSHV2  
VSS  
VSS  
USB0_VBUS  
VSS  
GPMC0_AD9 GPMC0_AD2  
GPMC0_AD0 GPMC0_WEn  
PRG0_PRU1 PRG0_PRU1 PRG0_PRU0 PRG0_PRU0 PRG0_PRU1 PRG0_PRU0  
VDDA_3P3  
_USB0  
VDDA_1P8  
_SERDES0  
VDDA_1P8  
_USB0  
GPMC0  
_AD10  
GPMC0_OEn  
GPMC0_CLK  
GPMC0  
_CSn0  
GPMC0  
_CSn1  
GPMC0  
_CSn3  
R
P
N
M
L
VSS  
VDDSHV1  
VSS  
VDDSHV2  
VSS  
VDD_CORE  
VSS  
VDDSHV2  
CAP_VDDS2  
VSS  
_GPO8  
_GPO19  
_GPO5  
_GPO1  
_GPO6  
_GPO13  
_REn  
PRG0  
_MDIO0  
_MDIO  
PRG0  
_MDIO0  
_MDC  
VDDA_0P85  
_SERDES0  
_C  
PRG0_PRU1 PRG0_PRU1  
_GPO5 _GPO18  
VDDA_0P85 VDDA_0P85  
GPMC0  
_ADVn_ALE  
GPMC0  
VSS  
GPMC0  
_CSn2  
VSS  
VSS  
VSS  
VSS  
VDDSHV3  
CAP_VDDS3  
VDDSHV4  
VDDSHV5  
VDDSHV3  
OSPI0_D5  
OSPI0_CLK  
OSPI0_D2  
OSPI0_D4  
_SERDES0  
_SERDES0  
_BE0n_CLE  
OSPI0  
_LBCLKO  
DDR0_DQS1 DDR0_DQ15 DDR0_DQ13 DDR0_DQ12 DDR0_DQ8  
VDDSHV1  
VDD_CORE  
VDD_CORE  
VSS  
VDDA_PLL0  
VSS  
VSS  
GPMC0_WPn GPMC0_DIR  
OSPI0_D6  
OSPI0_D1  
OSPI0_DQS  
OSPI0_D0  
DDR0_DQS1  
_n  
DDR0_DM1 DDR0_DQ11 DDR0_DQ14  
DDR0_A12  
DDR0_A7  
VSS  
VDDSHV1  
VSS  
VDD_CORE  
VSS  
VDD_CORE  
VSS  
VDDR_CORE  
VDDSHV4  
VDDSHV5  
CAP_VDDS4  
OSPI0_D7  
OSPI0_D3  
VDDA  
_TEMP1  
OSPI0  
_CSn3  
OSPI0  
_CSn1  
OSPI0  
_CSn0  
VSS  
DDR0_DQ10  
RSVD6  
VSS  
DDR0_DQ9  
DDR0_A13  
DDR0_A9  
VDDS_DDR  
VSS  
VDD_CORE  
VSS  
VDDR_CORE  
VDD_CORE CAP_VDDS5  
VSS  
MMC1_CLK MMC1_DAT1  
CAP  
_VDDSHV  
_MMC1  
VMON_1P8  
_MCU  
OSPI0  
_CSn2  
K
J
RSVD7  
DDR0_A10  
DDR0_A8  
DDR0_PAR  
VSS  
VDDS_DDR  
VSS  
VDD_CORE VMON_VSYS VDD_CORE  
VDDA_MCU VDD_MMC0 VDDS_MMC0  
MMC1_DAT3 MMC1_DAT2 MMC0_DAT0 MMC1_DAT0  
DDR0_CAS  
_n  
VDDS_DDR  
_C  
DDR0_A11  
DDR0_A6  
VDDS_DDR  
VSS  
VSS  
VDDA_PLL1  
VSS  
VDD_CORE VDDA_PLL2 VDD_CORE  
VDDA_ADC  
VSS  
ADC0_REFP ADC0_REFN MMC0_DAT3 MMC0_DAT2 MMC1_CMD MMC0_DAT1 MMC0_CMD  
DDR0  
_ALERT_n  
DDR0_ACT  
_n  
CAP_VDDS  
_MCU  
VDD_DLL  
_MMC0  
VDDA_3P3  
_SDIO  
H
G
F
DDR0_BG1 DDR0_WE_n DDR0_CAL0  
VSS  
VDDS_DDR  
VSS  
VSS  
CAP_VDDS0 VDDS_OSC  
RSVD0  
VSS  
MMC0_DAT4 MMC0_DAT6 MMC0_DAT5  
VSS  
VSS  
VDDSHV  
_MCU  
VDDSHV  
_MCU  
VDDA  
_TEMP0  
VSS  
DDR0_BG0  
DDR0_A5  
DDR0_A2  
DDR0_A0  
VSS  
DDR0_BA0  
DDR0_BA1  
VDDS_DDR  
VSS  
VDDSHV0  
RSVD8  
RSVD2  
VDDSHV0  
VPP  
MMC0_DAT7 MMC0_CLK  
MMC0_DS  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN7  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN2  
RSVD1  
DDR0_RAS  
_n  
VDDSHV  
_MCU  
VMON_3P3  
_MCU  
VMON_3P3  
_SOC  
RESETSTA  
Tz  
MMC0  
RSVD3  
DDR0_CK0  
DDR0_CKE1 DDR0_CKE0 DDR0_ODT1  
VDDS_DDR  
VSS  
VSS  
EMU1  
EMU0  
VSS  
VDDSHV0  
VSS  
ADC0_AIN6  
_CALPAD  
DDR0_CK0  
_n  
DDR0_CS0  
_n  
DDR0_CS1  
_n  
MCU_SPI0  
_CLK  
MCU_SPI0  
_D0  
MCU_UART0  
_RTSn  
MCU_I2C0  
_SCL  
VMON_1P8  
_SOC  
UART1  
_RTSn  
RESET  
PORz_OUT  
USB0  
_DRVVBUS  
E
D
C
B
A
DDR0_ODT0  
VSS  
VSS  
UART1_TXD UART1_RXD  
_REQz  
DDR0  
_RESET0_n  
MCU_SPI0  
_CS0  
MCU_SPI1  
_CLK  
MCU_UART0 MCU_UART1  
_CTSn  
UART1  
_CTSn  
ECAP0_IN  
MCAN1_RX  
VSS  
DDR0_A4  
DDR0_A3  
DDR0_DQ5  
DDR0_DQ7  
DDR0_DQ3  
TRSTn  
TDI  
SPI0_CS0  
SPI0_CLK  
SPI0_CS1  
SPI1_CS1  
SPI1_CLK  
SPI1_CS0  
SPI0_D1  
UART0_RXD  
MMC1_SDCD ADC0_AIN3  
_APWM_OUT  
_TXD  
MCU_SPI0  
_CS1  
MCU_SPI1  
_D0  
MCU_SPI1  
_D1  
MCU_UART1  
_RXD  
MCU_OSC0  
_XI  
DDR0_DQS0 DDR0_DQ6  
VSS  
DDR0_A1  
DDR0_DQ2  
VSS  
TMS  
VSS  
UART0_TXD  
MCAN1_TX  
MCAN0_RX  
MCAN0_TX  
I2C1_SCL  
I2C0_SDA  
I2C0_SCL  
EXTINTn  
MMC1_SDWP  
DDR0_DQS0  
DDR0_DM0  
_n  
MCU_SPI0  
_D1  
MCU_SPI1  
_CS1  
MCU_UART1 MCU_UART1  
_CTSn _RTSn  
MCU_I2C1  
_SDA  
MCU  
_RESETz  
MCU_RESETS  
TATz  
UART0  
_CTSn  
MCU_OSC0  
_XO  
DDR0_DQ4  
DDR0_DQ0  
TCK  
SPI1_D0  
SPI1_D1  
I2C1_SDA  
MCU_PORz  
MCU  
_SAFETY  
_ERRORn  
MCU_SPI1  
_CS0  
MCU_UART0 MCU_UART0  
_TXD _RXD  
MCU_I2C0  
_SDA  
MCU_I2C1  
_SCL  
UART0  
_RTSn  
EXT  
_REFCLK1  
VSS  
DDR0_DQ1  
VSS  
TDO  
SPI0_D0  
VSS  
Not to scale  
图6-1. ALV FCBGA-N441 Pin Diagram (Bottom View)  
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6.2 Pin Attributes  
The following list describes the contents of each column in 表6-1, Pin Attributes:  
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.  
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically  
taken from the primary MUXMODE 0 signal function).  
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.  
备注  
Many device pins support multiple signal functions. Some signal functions are selected via a  
single layer of multiplexers associated with pins. Other signal functions are selected via two or  
more layers of multiplexers, where one layer is associated with the pins and other layers are  
associated with peripheral logic functions.  
表6-1, Pin Attributes only defines signal multiplexing at the pins. For more information, related to  
signal multiplexing at the pins, see the Pad Configuration Registers section in the Device  
Configuration chapter of the device TRM. For information associated with peripheral signal  
multiplexing, see the respective peripheral chapter in the device TRM.  
4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:  
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal  
function is not necessarily the default pin multiplexed signal function.  
备注  
The value found in the MUX MODE AFTER RESET column defines the default pin  
multiplexed signal function selected when MCU_PORz is deasserted.  
b. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all  
MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin  
multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE should be  
used.  
c. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the  
rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not  
programmable via MUXMODE.  
d. An empty box means Not Applicable.  
备注  
The following configurations of MUXMODE must be avoided for proper device operation.  
• Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not  
supported as it can yield unexpected results.  
• Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be  
undefined.  
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5. TYPE: Signal type and direction:  
• I = Input  
• O = Output  
• OD = Output, with open-drain output function  
• IO = Input, Output, or simultaneously Input and Output  
• IOD = Input, Output, or simultaneously Input and Output, with open-drain output function  
• IOZ = Input, Output, or simultaneously Input and Output, with three-state output function  
• OZ = Output with three-state output function  
• A = Analog  
• PWR = Power  
• GND = Ground  
• CAP = LDO Capacitor.  
6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic  
"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.  
• 0: Logic 0 driven to the subsystem input.  
• 1: Logic 1 driven to the subsystem input.  
• pad: Logic state of the pad is driven to the subsystem input.  
• An empty box means Not Applicable.  
7. BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RX  
defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of  
internal pull resistors:  
• RX (Input buffer)  
– Off: The input buffer is disabled.  
– On: The input buffer is enabled.  
• TX (Output buffer)  
– Off: The output buffer is disabled.  
– Low: The output buffer is enabled and drives VOL  
.
• PULL (Internal pull resistors)  
– Off: Internal pull resistors are turned off.  
– Up: Internal pull-up resistor is turned on.  
– Down: Internal pull-down resistor is turned on.  
– NA: Not Applicable.  
• An empty box means Not Applicable.  
8. BALL STATE AFTER RESET RX/TX/PULL: State of the terminal after MCU_PORz is deasserted, where  
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state  
of internal pull resistors:  
• RX (Input buffer)  
– Off: The input buffer is disabled.  
– On: The input buffer is enabled.  
• TX (Output buffer)  
– Off: The output buffer is disabled.  
– SS: The subsystem selected with MUXMODE determines the output buffer state.  
• PULL (Internal pull resistors)  
– Off: Internal pull resistors are turned off.  
– Up: Internal pull-up resistor is turned on.  
– Down: Internal pull-down resistor is turned on.  
– NA: Not Applicable.  
• An empty box means Not Applicable.  
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9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal  
function after MCU_PORz is deasserted.  
An empty box means Not Applicable.  
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10. I/O OPERATING VOLTAGE: This column describes I/O operating voltage options of the respective power  
supply, when applicable.  
An empty box means Not Applicable.  
For more information, see valid operating voltage range(s) defined for each power supply in 节7.4,  
Recommended Operating Conditions.  
11. POWER: The power supply of the associated I/O, when applicable.  
An empty box means Not Applicable.  
12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:  
• Yes: With hysteresis  
• No: Without hysteresis  
• An empty box means Not Applicable.  
For more information, see the hysteresis values in 节7.7, Electrical Characteristics.  
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be  
used to determine which Electrical Characteristics table is applicable.  
An empty box means Not Applicable.  
For electrical characteristics, refer to the appropriate buffer type table in 节7.7, Electrical Characteristics.  
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and  
pulldown resistors can be enabled or disabled via software.  
• PU: Internal pull-up  
• PD: Internal pull-down  
• PU/PD: Internal pull-up and pull-down  
• An empty box means No internal pull.  
15. PADCONFIG Register:Name of the IO pad configuration register associated with Ball.  
16. PADCONFIG Address:Physical address of the IO pad configuration register associated with Ball.  
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表6-1. Pin Attributes (ALV Package)  
BALL  
BALL  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
STATE  
AFTER  
RESET  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
J16  
J15  
G20  
F20  
E21  
D20  
G21  
F21  
F19  
E20  
H12  
T7  
ADC0_REFN  
ADC0_REFP  
ADC0_AIN0  
ADC0_REFN  
A
A
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
VDDA_ADC0  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC12B  
ADC0_REFP  
ADC0_AIN0  
A
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
ADC0_AIN1  
ADC0_AIN1  
A
ADC0_AIN2  
ADC0_AIN2  
A
ADC0_AIN3  
ADC0_AIN3  
A
ADC0_AIN4  
ADC0_AIN4  
A
ADC0_AIN5  
ADC0_AIN5  
A
ADC0_AIN6  
ADC0_AIN6  
A
ADC0_AIN7  
ADC0_AIN7  
A
CAP_VDDS0  
CAP_VDDS1  
CAP_VDDS2  
CAP_VDDS3  
CAP_VDDS4  
CAP_VDDS5  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
CAP_VDDS0  
CAP_VDDS1  
CAP_VDDS2  
CAP_VDDS3  
CAP_VDDS4  
CAP_VDDS5  
CAP_VDDSHV_MMC1  
CAP_VDDS_MCU  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
R11  
N14  
M16  
L13  
K15  
H10  
VDDS_DDR,  
VDDS_DDR_C  
H2  
H1  
J5  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
O
IO  
O
O
O
O
O
O
O
O
O
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
K5  
F6  
H4  
D2  
C5  
E2  
D4  
D3  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A1  
DDR0_A1  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A2  
DDR0_A2  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A3  
DDR0_A3  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A4  
DDR0_A4  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
VDDS_DDR,  
VDDS_DDR_C  
F2  
J2  
DDR0_A5  
DDR0_A5  
DDR0_A6  
DDR0_A7  
DDR0_A8  
DDR0_A9  
O
O
O
O
O
O
O
O
O
O
O
O
O
A
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A6  
VDDS_DDR,  
VDDS_DDR_C  
L5  
J3  
DDR0_A7  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_A8  
VDDS_DDR,  
VDDS_DDR_C  
J4  
DDR0_A9  
VDDS_DDR,  
VDDS_DDR_C  
K3  
J1  
DDR0_A10  
DDR0_A11  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_A10  
DDR0_A11  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
M5  
K4  
G4  
G5  
G2  
H3  
H5  
F1  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
O
O
O
O
O
O
IO  
IO  
IO  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
VDDS_DDR,  
VDDS_DDR_C  
A2  
B5  
A4  
B3  
C4  
C2  
B4  
N5  
L4  
DDR0_DQ1  
DDR0_DQ1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
1.1 V/1.2 V  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ2  
DDR0_DQ2  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ3  
DDR0_DQ3  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ4  
DDR0_DQ4  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ5  
DDR0_DQ5  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ6  
DDR0_DQ6  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ7  
DDR0_DQ7  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ8  
DDR0_DQ8  
VDDS_DDR,  
VDDS_DDR_C  
DDR0_DQ9  
DDR0_DQ9  
VDDS_DDR,  
VDDS_DDR_C  
L2  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
DDR0_RESET0_n  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
DDR0_RESET0_n  
VDDS_DDR,  
VDDS_DDR_C  
M3  
N4  
N3  
M4  
N2  
C1  
B1  
N1  
M1  
E5  
F5  
D5  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
VDDS_DDR,  
VDDS_DDR_C  
O
VDDS_DDR,  
VDDS_DDR_C  
O
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
ECAP0_IN_APWM_OUT  
SYNC0_OUT  
0
1
2
5
6
7
IO  
O
I
0
ECAP0_IN_APWM_OUT  
CPTS0_RFT_CLK  
CP_GEMAC_CPTS0_RFT_CLK  
SPI4_CS3  
0
0
PADCONFIG:  
PADCONFIG156  
0x000F4270  
D18  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
I
IO  
IO  
1
GPIO1_68  
pad  
EMU0  
PADCONFIG:  
MCU_PADCONFIG31  
0x0408407C  
D10  
E10  
C19  
EMU0  
0
IO  
1
1
On / Off / Up  
On / Off / Up  
Off / Off / NA  
On / Off / Up  
On / Off / Up  
Off / Off / NA  
0
0
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV0  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
I2C OD FS  
PU/PD  
PU/PD  
EMU1  
EMU1  
0
15  
0
IO  
O
PADCONFIG:  
MCU_PADCONFIG32  
0x04084080  
MCU_OBSCLK0  
EXTINTn  
EXTINTn  
I
1
pad  
0
PADCONFIG:  
PADCONFIG158  
0x000F4278  
GPIO1_70  
7
IOD  
EXT_REFCLK1  
SYNC1_OUT  
0
1
2
5
7
0
1
2
3
6
7
9
0
1
2
3
4
6
7
9
I
O
IO  
O
IO  
O
I
EXT_REFCLK1  
PADCONFIG:  
PADCONFIG157  
0x000F4274  
A19  
SPI2_CS3  
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
CLKOUT0  
GPIO1_69  
pad  
GPMC0_ADVn_ALE  
FSI_RX5_CLK  
UART5_RXD  
0
1
0
GPMC0_ADVn_ALE  
I
PADCONFIG:  
PADCONFIG33  
0x000F4084  
P16  
EHRPWM_TZn_IN3  
TRC_DATA15  
I
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
O
IO  
I
GPIO0_32  
pad  
0
PRG0_PWM3_TZ_IN  
GPMC0_CLK  
O
I
0
FSI_RX4_CLK  
UART4_RTSn  
EHRPWM3_SYNCO  
GPMC0_FCLK_MUX  
TRC_DATA14  
0
O
O
O
O
IO  
O
GPMC0_CLK  
PADCONFIG:  
PADCONFIG31  
0x000F407C  
R17  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
GPIO0_31  
pad  
PRG0_PWM3_TZ_OUT  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
GPMC0_DIR  
0
O
I
GPMC0_DIR  
EQEP0_B  
3
0
pad  
0
PADCONFIG:  
PADCONFIG41  
0x000F40A4  
N17  
GPIO0_40  
7
IO  
IO  
IO  
O
I
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
EHRPWM6_B  
PRG1_PWM2_B0  
GPMC0_OEn_REn  
FSI_RX5_D0  
UART5_TXD  
EHRPWM4_A  
TRC_DATA16  
GPIO0_33  
8
9
1
0
1
0
0
GPMC0_OEn_REn  
2
O
IO  
O
IO  
IO  
O
I
PADCONFIG:  
PADCONFIG34  
0x000F4088  
R18  
3
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
6
7
pad  
0
PRG0_PWM3_A1  
GPMC0_WEn  
FSI_RX5_D1  
UART5_RTSn  
EHRPWM4_B  
TRC_DATA17  
GPIO0_34  
9
0
1
0
0
GPMC0_WEn  
2
O
IO  
O
IO  
IO  
O
O
I
PADCONFIG:  
PADCONFIG35  
0x000F408C  
T21  
3
Off / Off / Off  
Off / Off / Off  
On / Off / Off  
Off / Off / Off  
Off / Off / Off  
On / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV3  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
6
7
pad  
1
PRG0_PWM3_B1  
GPMC0_WPn  
FSI_TX1_CLK  
EQEP0_A  
9
0
1
3
0
GPMC0_WPn  
GPMC0_A22  
TRC_DATA22  
GPIO0_39  
4
OZ  
O
IO  
IO  
IO  
IO  
I
PADCONFIG:  
PADCONFIG40  
0x000F40A0  
N16  
VDDSHV3  
LVCMOS  
6
7
pad  
0
EHRPWM6_A  
PRG1_PWM2_A0  
GPMC0_AD0  
FSI_RX2_CLK  
UART2_RXD  
EHRPWM0_SYNCI  
TRC_CLK  
8
9
0
0
0
1
0
GPMC0_AD0  
2
I
1
PADCONFIG:  
PADCONFIG15  
0x000F403C  
T20  
3
I
0
VDDSHV3  
LVCMOS  
6
7
O
IO  
I
GPIO0_15  
pad  
BOOTMODE00  
Bootstrap  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
GPMC0_AD1  
0
IO  
I
0
0
FSI_RX2_D0  
1
UART2_TXD  
2
O
O
O
IO  
O
I
GPMC0_AD1  
EHRPWM0_SYNCO  
TRC_CTL  
3
PADCONFIG:  
PADCONFIG16  
0x000F4040  
U21  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV3  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
6
GPIO0_16  
7
pad  
PRG0_PWM2_TZ_OUT  
BOOTMODE01  
GPMC0_AD2  
FSI_RX2_D1  
9
Bootstrap  
0
IO  
I
0
0
1
UART2_RTSn  
EHRPWM_TZn_IN0  
TRC_DATA0  
2
O
I
GPMC0_AD2  
3
0
PADCONFIG:  
PADCONFIG17  
0x000F4044  
T18  
U20  
U18  
VDDSHV3  
VDDSHV3  
VDDSHV3  
6
O
IO  
I
GPIO0_17  
7
pad  
0
PRG0_PWM2_TZ_IN  
BOOTMODE02  
GPMC0_AD3  
FSI_RX3_CLK  
UART3_RXD  
EHRPWM0_A  
TRC_DATA1  
9
Bootstrap  
I
0
IO  
I
0
0
1
0
1
2
I
GPMC0_AD3  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG18  
0x000F4048  
6
GPIO0_18  
7
pad  
0
PRG0_PWM2_A0  
BOOTMODE03  
GPMC0_AD4  
FSI_RX3_D0  
9
Bootstrap  
0
IO  
I
0
0
1
UART3_TXD  
2
O
IO  
O
IO  
IO  
I
GPMC0_AD4  
EHRPWM0_B  
TRC_DATA2  
3
0
PADCONFIG:  
PADCONFIG19  
0x000F404C  
6
GPIO0_82  
7
9
pad  
1
PRG0_PWM2_B0  
BOOTMODE04  
Bootstrap  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
GPMC0_AD5  
0
IO  
I
0
0
FSI_RX3_D1  
UART3_RTSn  
EHRPWM1_A  
TRC_DATA3  
1
2
O
IO  
O
IO  
IO  
I
GPMC0_AD5  
3
0
PADCONFIG:  
PADCONFIG20  
0x000F4050  
U19  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
6
GPIO0_83  
7
pad  
0
PRG0_PWM2_A1  
BOOTMODE05  
GPMC0_AD6  
FSI_RX4_D0  
UART4_RXD  
EHRPWM1_B  
TRC_DATA4  
9
Bootstrap  
0
IO  
I
0
0
1
0
1
2
I
GPMC0_AD6  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG21  
0x000F4054  
V20  
V21  
V19  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
VDDSHV3  
VDDSHV3  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
6
GPIO0_21  
7
pad  
1
PRG0_PWM2_B1  
BOOTMODE06  
GPMC0_AD7  
FSI_RX4_D1  
UART4_TXD  
EHRPWM_TZn_IN1  
EHRPWM8_A  
TRC_DATA5  
9
Bootstrap  
0
IO  
I
0
0
1
2
O
I
GPMC0_AD7  
3
0
0
PADCONFIG:  
PADCONFIG22  
0x000F4058  
4
IO  
O
IO  
IO  
I
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
Yes  
PU/PD  
6
GPIO0_22  
7
pad  
0
PRG1_PWM2_A2  
BOOTMODE07  
GPMC0_AD8  
FSI_RX0_CLK  
UART2_CTSn  
EHRPWM2_A  
TRC_DATA6  
9
Bootstrap  
0
IO  
I
0
0
1
0
1
2
I
GPMC0_AD8  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG23  
0x000F405C  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
Yes  
PU/PD  
6
GPIO0_23  
7
9
pad  
0
PRG0_PWM2_A2  
BOOTMODE08  
Bootstrap  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
GPMC0_AD9  
0
IO  
I
0
0
1
0
FSI_RX0_D0  
UART3_CTSn  
EHRPWM2_B  
TRC_DATA7  
GPIO0_24  
1
2
I
GPMC0_AD9  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG24  
0x000F4060  
T17  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
6
7
pad  
1
PRG0_PWM2_B2  
BOOTMODE09  
GPMC0_AD10  
FSI_RX0_D1  
UART4_CTSn  
EHRPWM_TZn_IN2  
EHRPWM8_B  
TRC_DATA8  
GPIO0_25  
9
Bootstrap  
0
IO  
I
0
0
1
0
0
1
2
I
GPMC0_AD10  
3
I
PADCONFIG:  
PADCONFIG25  
0x000F4064  
R16  
4
IO  
O
IO  
IO  
I
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
6
7
pad  
1
PRG1_PWM2_B2  
BOOTMODE10  
GPMC0_AD11  
FSI_RX1_CLK  
UART5_CTSn  
EQEP1_A  
9
Bootstrap  
0
IO  
I
0
0
1
0
1
2
I
GPMC0_AD11  
3
I
PADCONFIG:  
PADCONFIG26  
0x000F4068  
W20  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
TRC_DATA9  
GPIO0_26  
6
O
IO  
IO  
I
7
pad  
0
EHRPWM7_A  
BOOTMODE11  
GPMC0_AD12  
FSI_RX1_D0  
UART6_CTSn  
EQEP1_B  
8
Bootstrap  
0
IO  
I
0
0
1
0
1
2
I
GPMC0_AD12  
3
I
PADCONFIG:  
PADCONFIG27  
0x000F406C  
W21  
On / Off / Off  
On / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
TRC_DATA10  
GPIO0_27  
6
O
IO  
IO  
I
7
8
pad  
0
EHRPWM7_B  
BOOTMODE12  
Bootstrap  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
GPMC0_AD13  
0
IO  
I
0
0
0
FSI_RX1_D1  
1
GPMC0_AD13  
EHRPWM3_A  
TRC_DATA11  
GPIO0_28  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG28  
0x000F4070  
V18  
6
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
On / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV3  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
7
pad  
0
PRG0_PWM3_A0  
BOOTMODE13  
GPMC0_AD14  
FSI_TX0_D0  
9
Bootstrap  
0
IO  
O
I
0
1
UART6_RXD  
EHRPWM3_B  
TRC_DATA12  
GPIO0_29  
2
1
0
GPMC0_AD14  
3
IO  
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG29  
0x000F4074  
Y21  
VDDSHV3  
LVCMOS  
6
7
pad  
1
PRG0_PWM3_B0  
BOOTMODE14  
GPMC0_AD15  
FSI_TX0_D1  
9
Bootstrap  
0
IO  
O
O
I
0
1
GPMC0_AD15  
UART6_TXD  
2
PADCONFIG:  
PADCONFIG30  
0x000F4078  
Y20  
EHRPWM3_SYNCI  
TRC_DATA13  
GPIO0_30  
3
0
VDDSHV3  
LVCMOS  
6
O
IO  
I
7
pad  
BOOTMODE15  
GPMC0_BE0n_CLE  
FSI_TX1_D0  
Bootstrap  
0
1
2
3
5
6
7
9
0
1
3
6
7
9
O
O
O
I
UART6_RTSn  
EHRPWM_TZn_IN4  
EHRPWM7_A  
TRC_DATA18  
GPIO0_35  
GPMC0_BE0n_CLE  
0
0
PADCONFIG:  
PADCONFIG36  
0x000F4090  
P17  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
IO  
O
IO  
IO  
O
O
IO  
O
IO  
IO  
pad  
0
PRG1_PWM2_A1  
GPMC0_BE1n  
FSI_TX0_CLK  
EHRPWM5_A  
TRC_DATA19  
GPIO0_36  
GPMC0_BE1n  
0
PADCONFIG:  
PADCONFIG37  
0x000F4094  
T19  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
pad  
0
PRG0_PWM3_A2  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
GPMC0_CSn0  
0
3
6
7
8
0
3
5
7
8
9
0
1
2
3
5
7
9
0
1
2
3
4
5
7
0
3
6
7
9
O
IO  
O
GPMC0_CSn0  
EQEP0_S  
0
PADCONFIG:  
PADCONFIG42  
0x000F40A8  
R19  
TRC_DATA23  
GPIO0_41  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
Yes  
LVCMOS  
PU/PD  
IO  
I
pad  
0
EHRPWM6_SYNCI  
GPMC0_CSn1  
EQEP0_I  
O
IO  
I
0
0
GPMC0_CSn1  
EHRPWM_TZn_IN2  
GPIO0_42  
PADCONFIG:  
PADCONFIG43  
0x000F40AC  
R20  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
LVCMOS  
PU/PD  
IO  
O
pad  
EHRPWM6_SYNCO  
PRG1_PWM2_TZ_OUT  
GPMC0_CSn2  
I2C2_SCL  
O
O
IOD  
IO  
IO  
I
1
0
GPMC0_CSn2  
TIMER_IO8  
PADCONFIG:  
PADCONFIG44  
0x000F40B0  
P19  
EQEP1_S  
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
EHRPWM_TZn_IN4  
GPIO0_43  
0
IO  
I
pad  
0
PRG1_PWM2_TZ_IN  
GPMC0_CSn3  
I2C2_SDA  
O
IOD  
IO  
IO  
OZ  
I
1
0
0
GPMC0_CSn3  
TIMER_IO9  
PADCONFIG:  
PADCONFIG45  
0x000F40B4  
R21  
EQEP1_I  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
GPMC0_A20  
EHRPWM_TZn_IN5  
GPIO0_44  
0
pad  
1
IO  
I
GPMC0_WAIT0  
EHRPWM5_B  
TRC_DATA20  
GPIO0_37  
GPMC0_WAIT0  
IO  
O
0
PADCONFIG:  
PADCONFIG38  
0x000F4098  
W19  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
pad  
1
PRG0_PWM3_B2  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
GPMC0_WAIT1  
0
1
3
4
5
6
7
9
0
I
O
1
0
0
FSI_TX1_D1  
EHRPWM_TZn_IN5  
GPMC0_A21  
EHRPWM7_B  
TRC_DATA21  
GPIO0_38  
I
GPMC0_WAIT1  
OZ  
IO  
O
PADCONFIG:  
PADCONFIG39  
0x000F409C  
Y18  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV3  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IOD  
pad  
1
PRG1_PWM2_B1  
I2C0_SCL  
I2C0_SCL  
1
PADCONFIG:  
PADCONFIG152  
0x000F4260  
A18  
B18  
Off / Off / NA  
Off / Off / NA  
On / SS / NA  
On / SS / NA  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
I2C OD FS  
I2C OD FS  
GPIO1_64  
I2C0_SDA  
GPIO1_65  
7
0
7
IOD  
IOD  
IOD  
pad  
1
I2C0_SDA  
PADCONFIG:  
PADCONFIG153  
0x000F4264  
pad  
I2C1_SCL  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
6
7
8
9
IOD  
I
1
0
I2C1_SCL  
CPTS0_HW1TSPUSH  
TIMER_IO0  
SPI2_CS1  
PADCONFIG:  
PADCONFIG154  
0x000F4268  
C18  
B19  
IO  
IO  
IO  
IOD  
I
0
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1
GPIO1_66  
pad  
1
I2C1_SDA  
I2C1_SDA  
CPTS0_HW2TSPUSH  
TIMER_IO1  
SPI2_CS2  
0
PADCONFIG:  
PADCONFIG155  
0x000F426C  
IO  
IO  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1
GPIO1_67  
pad  
1
MCAN0_RX  
UART4_TXD  
TIMER_IO3  
SYNC3_OUT  
SPI4_CS2  
O
IO  
O
0
MCAN0_RX  
PADCONFIG:  
PADCONFIG149  
0x000F4254  
B17  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
I
1
pad  
0
GPIO1_61  
EQEP2_S  
UART0_RIn  
1
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
MCAN0_TX  
0
1
2
3
6
7
8
9
0
1
2
3
4
5
6
7
8
9
15  
0
1
2
3
4
5
6
7
8
9
0
O
I
UART4_RXD  
TIMER_IO2  
1
0
IO  
O
MCAN0_TX  
SYNC2_OUT  
SPI4_CS1  
PADCONFIG:  
PADCONFIG148  
0x000F4250  
A17  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
O
1
pad  
0
GPIO1_60  
EQEP2_I  
UART0_DTRn  
MCAN1_RX  
I2C3_SDA  
I
1
1
0
IOD  
IO  
O
ECAP2_IN_APWM_OUT  
OBSCLK0  
MCAN1_RX  
TIMER_IO5  
IO  
O
0
PADCONFIG:  
PADCONFIG151  
0x000F425C  
D17  
UART5_TXD  
EHRPWM_SOCB  
GPIO1_63  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
O
IO  
I
pad  
0
EQEP2_B  
UART0_DSRn  
OBSCLK0  
I
1
O
MCAN1_TX  
O
I2C3_SCL  
IOD  
IO  
O
1
0
ECAP1_IN_APWM_OUT  
SYSCLKOUT0  
TIMER_IO4  
MCAN1_TX  
IO  
I
0
1
PADCONFIG:  
PADCONFIG150  
0x000F4258  
C17  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
UART5_RXD  
EHRPWM_SOCA  
GPIO1_62  
O
IO  
I
pad  
0
EQEP2_A  
UART0_DCDn  
MCU_I2C0_SCL  
I
1
MCU_I2C0_SCL  
IOD  
1
PADCONFIG:  
MCU_PADCONFIG18  
0x04084048  
E9  
Off / Off / NA  
Off / Off / NA  
On / SS / NA  
On / SS / NA  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
I2C OD FS  
I2C OD FS  
MCU_GPIO0_18  
MCU_I2C0_SDA  
MCU_GPIO0_19  
7
0
7
IOD  
IOD  
IOD  
pad  
1
MCU_I2C0_SDA  
PADCONFIG:  
MCU_PADCONFIG19  
0x0408404C  
A10  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
MCU_I2C1_SCL  
MCU_I2C1_SCL  
0
7
0
7
IOD  
IO  
1
PADCONFIG:  
MCU_PADCONFIG20  
0x04084050  
A11  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
MCU_GPIO0_20  
MCU_I2C1_SDA  
MCU_GPIO0_21  
pad  
1
MCU_I2C1_SDA  
IOD  
IO  
PADCONFIG:  
MCU_PADCONFIG21  
0x04084054  
B10  
LVCMOS  
pad  
C21  
B20  
MCU_OSC0_XI  
MCU_OSC0_XO  
MCU_PORz  
MCU_OSC0_XI  
MCU_OSC0_XO  
I
1.8 V  
1.8 V  
VDDS_OSC  
VDDS_OSC  
Yes  
Yes  
HFOSC  
HFOSC  
O
PADCONFIG:  
MCU_PADCONFIG23  
0x0408405C  
B21  
B13  
B12  
A20  
E6  
MCU_PORz  
0
I
0
0
0
0
7
7
7
1.8 V  
VDDS_OSC  
VDDSHV_MCU  
VDDSHV_MCU  
VDDS_OSC  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
FS RESET  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
MCU_RESETSTATz  
MCU_RESETSTATz  
MCU_GPIO0_22  
0
7
O
PADCONFIG:  
MCU_PADCONFIG24  
0x04084060  
Off / Low / Off  
On / Off / Up  
Off / Off / Down  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / SS / Off  
On / Off / Up  
On / SS / Down  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
IO  
pad  
MCU_RESETz  
PADCONFIG:  
MCU_PADCONFIG22  
0x04084058  
MCU_RESETz  
0
0
I
MCU_SAFETY_ERRORn  
PADCONFIG:  
MCU_PADCONFIG25  
0x04084064  
MCU_SAFETY_ERRORn  
IO  
MCU_SPI0_CLK  
MCU_SPI0_CLK  
MCU_GPIO0_11  
MCU_SPI1_CLK  
MCU_GPIO0_7  
MCU_SPI0_CS0  
MCU_GPIO0_13  
0
7
0
7
0
7
IO  
IO  
IO  
IO  
IO  
IO  
0
pad  
0
PADCONFIG:  
MCU_PADCONFIG2  
0x04084008  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
MCU_SPI1_CLK  
PADCONFIG:  
MCU_PADCONFIG7  
0x0408401C  
D7  
pad  
1
MCU_SPI0_CS0  
PADCONFIG:  
MCU_PADCONFIG0  
0x04084000  
D6  
pad  
1
MCU_SPI0_CS1  
MCU_OBSCLK0  
MCU_SYSCLKOUT0  
MCU_GPIO0_12  
0
1
2
7
IO  
O
MCU_SPI0_CS1  
PADCONFIG:  
MCU_PADCONFIG1  
0x04084004  
C6  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
O
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
MCU_SPI0_D0  
MCU_SPI0_D0  
0
7
0
7
0
7
IO  
IO  
IO  
IO  
IO  
IO  
0
pad  
0
PADCONFIG:  
MCU_PADCONFIG3  
0x0408400C  
E7  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
MCU_GPIO0_10  
MCU_SPI0_D1  
MCU_GPIO0_4  
MCU_SPI1_CS0  
MCU_GPIO0_5  
MCU_SPI0_D1  
PADCONFIG:  
MCU_PADCONFIG4  
0x04084010  
B6  
A7  
B7  
C7  
C8  
pad  
1
MCU_SPI1_CS0  
PADCONFIG:  
MCU_PADCONFIG5  
0x04084014  
pad  
MCU_SPI1_CS1  
MCU_SPI1_CS1  
0
1
IO  
I
1
0
PADCONFIG:  
MCU_PADCONFIG6  
0x04084018  
MCU_EXT_REFCLK0  
MCU_GPIO0_6  
MCU_SPI1_D0  
7
0
IO  
IO  
pad  
0
MCU_SPI1_D0  
PADCONFIG:  
MCU_PADCONFIG8  
0x04084020  
MCU_GPIO0_8  
MCU_SPI1_D1  
MCU_GPIO0_9  
7
0
7
IO  
IO  
IO  
pad  
0
MCU_SPI1_D1  
PADCONFIG:  
MCU_PADCONFIG9  
0x04084024  
pad  
MCU_UART0_CTSn  
MCU_TIMER_IO0  
MCU_SPI0_CS2  
MCU_GPIO0_1  
0
1
2
7
0
1
2
7
0
I
1
0
MCU_UART0_CTSn  
IO  
IO  
IO  
O
PADCONFIG:  
MCU_PADCONFIG12  
0x04084030  
D8  
E8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1
pad  
MCU_UART0_RTSn  
MCU_TIMER_IO1  
MCU_SPI1_CS2  
MCU_GPIO0_0  
MCU_UART0_RTSn  
IO  
IO  
IO  
I
0
1
PADCONFIG:  
MCU_PADCONFIG13  
0x04084034  
pad  
1
MCU_UART0_RXD  
MCU_UART0_RXD  
PADCONFIG:  
MCU_PADCONFIG10  
0x04084028  
A9  
A8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
MCU_GPIO0_3  
MCU_UART0_TXD  
MCU_GPIO0_2  
7
0
7
IO  
O
pad  
MCU_UART0_TXD  
PADCONFIG:  
MCU_PADCONFIG11  
0x0408402C  
IO  
pad  
MCU_UART1_CTSn  
MCU_TIMER_IO2  
MCU_SPI0_CS3  
MCU_GPIO0_16  
0
1
2
7
I
1
0
MCU_UART1_CTSn  
IO  
IO  
IO  
PADCONFIG:  
MCU_PADCONFIG16  
0x04084040  
B8  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
1
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
MCU_UART1_RTSn  
0
1
2
7
0
O
IO  
IO  
IO  
I
MCU_UART1_RTSn  
MCU_TIMER_IO3  
MCU_SPI1_CS3  
MCU_GPIO0_17  
MCU_UART1_RXD  
0
1
PADCONFIG:  
MCU_PADCONFIG17  
0x04084044  
B9  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV_MCU  
Yes  
LVCMOS  
PU/PD  
pad  
1
MCU_UART1_RXD  
PADCONFIG:  
MCU_PADCONFIG14  
0x04084038  
C9  
D9  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
MCU_GPIO0_14  
MCU_UART1_TXD  
MCU_GPIO0_15  
7
0
7
IO  
O
pad  
MCU_UART1_TXD  
PADCONFIG:  
MCU_PADCONFIG15  
0x0408403C  
IO  
pad  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
F18  
G18  
J21  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
A
1.8 V  
1.8 V  
1.8 V  
1.8 V  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
IO  
IO  
IO  
On / Low / Off  
On / Off / Up  
On / SS / Off  
On / SS / Up  
PU/PD  
PU/PD  
PU/PD  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
G19  
On / Off / Down  
On / Off / Down  
VDD_DLL_MMC0  
MMC1_CLK  
UART2_CTSn  
TIMER_IO4  
UART4_RXD  
GPIO1_75  
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
IO  
I
MMC1_CLK  
1
0
PADCONFIG:  
PADCONFIG163  
0x000F428C  
L20  
J19  
D19  
IO  
I
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV5  
VDDSHV5  
VDDSHV0  
Yes  
Yes  
Yes  
SDIO  
SDIO  
PU/PD  
PU/PD  
PU/PD  
1
IO  
IO  
O
IO  
O
IO  
I
pad  
1
MMC1_CMD  
UART2_RTSn  
TIMER_IO5  
UART4_TXD  
GPIO1_76  
MMC1_CMD  
PADCONFIG:  
PADCONFIG165  
0x000F4294  
0
pad  
0
MMC1_SDCD  
UART3_CTSn  
TIMER_IO6  
UART5_RXD  
GPIO1_77  
MMC1_SDCD  
I
1
PADCONFIG:  
PADCONFIG166  
0x000F4298  
IO  
I
0
LVCMOS  
1
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
MMC1_SDWP  
0
1
2
3
7
I
0
0
MMC1_SDWP  
UART3_RTSn  
TIMER_IO7  
UART5_TXD  
GPIO1_78  
O
PADCONFIG:  
PADCONFIG167  
0x000F429C  
C20  
IO  
O
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
pad  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
K20  
J20  
J18  
J17  
H17  
H19  
H18  
G17  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / Off / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
On / SS / Up  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
eMMCPHY  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
VDDS_MMC0,  
VDD_MMC0,  
VDD_DLL_MMC0  
MMC1_DAT0  
0
1
2
3
7
0
1
2
3
7
IO  
I
1
0
0
MMC1_DAT0  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO3  
PADCONFIG:  
PADCONFIG162  
0x000F4288  
K21  
L21  
IO  
O
IO  
IO  
I
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
VDDSHV5  
VDDSHV5  
Yes  
Yes  
SDIO  
SDIO  
PU/PD  
PU/PD  
UART3_TXD  
GPIO1_74  
pad  
1
MMC1_DAT1  
MMC1_DAT1  
CP_GEMAC_CPTS0_HW1TSPUSH  
TIMER_IO2  
0
PADCONFIG:  
PADCONFIG161  
0x000F4284  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
UART3_RXD  
1
GPIO1_73  
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
MMC1_DAT2  
0
1
2
3
7
0
1
2
3
7
0
IO  
O
1
0
MMC1_DAT2  
CP_GEMAC_CPTS0_TS_SYNC  
TIMER_IO1  
PADCONFIG:  
PADCONFIG160  
0x000F4280  
K19  
IO  
O
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
VDDSHV5  
Yes  
Yes  
SDIO  
PU/PD  
PU/PD  
UART2_TXD  
GPIO1_72  
IO  
IO  
O
pad  
1
MMC1_DAT3  
MMC1_DAT3  
CP_GEMAC_CPTS0_TS_COMP  
TIMER_IO0  
PADCONFIG:  
PADCONFIG159  
0x000F427C  
K18  
IO  
I
0
1
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
VDDSHV5  
SDIO  
UART2_RXD  
GPIO1_71  
IO  
O
pad  
OSPI0_CLK  
OSPI0_CLK  
PADCONFIG:  
PADCONFIG0  
0x000F4000  
N20  
N19  
N21  
L19  
L18  
K17  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
GPIO0_0  
7
0
7
0
7
0
7
0
7
IO  
I
pad  
0
OSPI0_DQS  
OSPI0_DQS  
GPIO0_2  
PADCONFIG:  
PADCONFIG2  
0x000F4008  
IO  
IO  
IO  
O
pad  
0
OSPI0_LBCLKO  
OSPI0_LBCLKO  
GPIO0_1  
PADCONFIG:  
PADCONFIG1  
0x000F4004  
pad  
OSPI0_CSn0  
OSPI0_CSn0  
GPIO0_11  
PADCONFIG:  
PADCONFIG11  
0x000F402C  
IO  
O
pad  
pad  
OSPI0_CSn1  
OSPI0_CSn1  
GPIO0_12  
PADCONFIG:  
PADCONFIG12  
0x000F4030  
IO  
OSPI0_CSn2  
OSPI0_CSn2  
0
2
O
O
PADCONFIG:  
PADCONFIG13  
0x000F4034  
OSPI0_RESET_OUT1  
GPIO0_13  
7
IO  
pad  
OSPI0_CSn3  
0
1
2
7
0
O
O
I
OSPI0_CSn3  
OSPI0_RESET_OUT0  
OSPI0_ECC_FAIL  
GPIO0_14  
PADCONFIG:  
PADCONFIG14  
0x000F4038  
L17  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1
pad  
0
IO  
IO  
OSPI0_D0  
OSPI0_D0  
PADCONFIG:  
PADCONFIG3  
0x000F400C  
M19  
GPIO0_3  
7
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
OSPI0_D1  
OSPI0_D1  
GPIO0_4  
OSPI0_D2  
GPIO0_5  
OSPI0_D3  
GPIO0_6  
OSPI0_D4  
GPIO0_7  
OSPI0_D5  
GPIO0_8  
OSPI0_D6  
GPIO0_9  
OSPI0_D7  
GPIO0_10  
0
7
0
7
0
7
0
7
0
7
0
7
0
7
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
0
pad  
0
PADCONFIG:  
PADCONFIG4  
0x000F4010  
M18  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Low / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / SS / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
7
0
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV4  
VDDSHV0  
VDDSHV1  
VDDSHV1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
OSPI0_D2  
PADCONFIG:  
PADCONFIG5  
0x000F4014  
M20  
M21  
P21  
P20  
N18  
M17  
E17  
P3  
pad  
0
OSPI0_D3  
PADCONFIG:  
PADCONFIG6  
0x000F4018  
pad  
0
OSPI0_D4  
PADCONFIG:  
PADCONFIG7  
0x000F401C  
pad  
0
OSPI0_D5  
PADCONFIG:  
PADCONFIG8  
0x000F4020  
pad  
0
OSPI0_D6  
PADCONFIG:  
PADCONFIG9  
0x000F4024  
pad  
0
OSPI0_D7  
PADCONFIG:  
PADCONFIG10  
0x000F4028  
pad  
PORz_OUT  
PADCONFIG:  
PADCONFIG171  
0x000F42AC  
PORz_OUT  
0
O
PRG0_MDIO0_MDC  
PRG0_MDIO0_MDC  
GPIO1_41  
0
7
O
PADCONFIG:  
PADCONFIG129  
0x000F4204  
IO  
pad  
GPMC0_A13  
9
OZ  
PRG0_MDIO0_MDIO  
PRG0_MDIO0_MDIO  
GPIO1_40  
0
7
IO  
IO  
0
PADCONFIG:  
PADCONFIG128  
0x000F4200  
pad  
P2  
GPMC0_A12  
9
OZ  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG0_PRU0_GPO0  
0
1
IO  
I
0
0
PRG0_PRU0_GPI0  
PRG0_RGMII1_RD0  
PRG0_PWM3_A0  
GPIO1_0  
PRG0_PRU0_GPO0  
2
I
0
PADCONFIG:  
PADCONFIG88  
0x000F4160  
Y1  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
3
IO  
IO  
I
0
7
pad  
1
UART2_CTSn  
10  
0
PRG0_PRU0_GPO1  
PRG0_PRU0_GPI1  
PRG0_RGMII1_RD1  
PRG0_PWM3_B0  
GPIO1_1  
IO  
I
0
1
0
PRG0_PRU0_GPO1  
2
I
0
PADCONFIG:  
PADCONFIG89  
0x000F4164  
R4  
U2  
V2  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
VDDSHV1  
VDDSHV1  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
3
IO  
IO  
O
IO  
I
1
7
pad  
UART2_TXD  
10  
0
PRG0_PRU0_GPO2  
PRG0_PRU0_GPI2  
PRG0_RGMII1_RD2  
PRG0_PWM2_A0  
GPIO1_2  
0
0
1
PRG0_PRU0_GPO2  
2
I
0
PADCONFIG:  
PADCONFIG90  
0x000F4168  
3
IO  
IO  
OZ  
O
IO  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
Yes  
PU/PD  
7
pad  
GPMC0_A0  
9
UART2_RTSn  
10  
0
PRG0_PRU0_GPO3  
PRG0_PRU0_GPI3  
PRG0_RGMII1_RD3  
PRG0_PWM3_A2  
GPIO1_3  
0
0
1
PRG0_PRU0_GPO3  
2
I
0
PADCONFIG:  
PADCONFIG91  
0x000F416C  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
Yes  
PU/PD  
3
IO  
IO  
I
0
7
pad  
1
UART3_CTSn  
10  
0
PRG0_PRU0_GPO4  
PRG0_PRU0_GPI4  
PRG0_RGMII1_RX_CTL  
PRG0_PWM2_B0  
GPIO1_4  
IO  
I
0
1
0
PRG0_PRU0_GPO4  
2
I
0
PADCONFIG:  
PADCONFIG92  
0x000F4170  
AA2  
3
IO  
IO  
OZ  
O
IO  
I
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
GPMC0_A1  
9
UART3_TXD  
10  
0
PRG0_PRU0_GPO5  
PRG0_PRU0_GPI5  
PRG0_PWM3_B2  
GPIO1_5  
0
0
PRG0_PRU0_GPO5  
1
PADCONFIG:  
PADCONFIG93  
0x000F4174  
R3  
3
IO  
IO  
O
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
UART3_RTSn  
10  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG0_PRU0_GPO6  
0
1
IO  
I
0
0
PRG0_PRU0_GPI6  
PRG0_RGMII1_RXC  
PRG0_PWM3_A1  
GPIO1_6  
PRG0_PRU0_GPO6  
2
I
0
PADCONFIG:  
PADCONFIG94  
0x000F4178  
T3  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
3
IO  
IO  
I
0
7
pad  
1
UART4_CTSn  
10  
0
PRG0_PRU0_GPO7  
PRG0_PRU0_GPI7  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_PWM3_B1  
CPTS0_HW2TSPUSH  
CP_GEMAC_CPTS0_HW2TSPUSH  
TIMER_IO6  
IO  
I
0
1
0
2
I
0
PRG0_PRU0_GPO7  
3
IO  
I
1
PADCONFIG:  
PADCONFIG95  
0x000F417C  
T1  
4
0
VDDSHV1  
VDDSHV1  
VDDSHV1  
5
I
0
6
IO  
IO  
O
IO  
I
0
GPIO1_7  
7
pad  
UART4_TXD  
10  
0
PRG0_PRU0_GPO8  
PRG0_PRU0_GPI8  
PRG0_PWM2_A1  
GPIO1_8  
0
0
1
PRG0_PRU0_GPO8  
3
IO  
IO  
OZ  
O
IO  
I
0
PADCONFIG:  
PADCONFIG96  
0x000F4180  
T2  
7
pad  
GPMC0_A2  
9
UART4_RTSn  
10  
0
PRG0_PRU0_GPO9  
PRG0_PRU0_GPI9  
PRG0_UART0_CTSn  
PRG0_PWM3_TZ_IN  
RGMII1_RX_CTL  
RMII1_RX_ER  
0
0
1
2
I
1
PRG0_PRU0_GPO9  
3
I
0
PADCONFIG:  
PADCONFIG97  
0x000F4184  
W6  
4
I
0
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT28  
GPIO1_9  
6
IO  
IO  
I
0
7
pad  
1
UART2_RXD  
10  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG0_PRU0_GPO10  
0
1
2
3
4
5
6
7
10  
0
1
2
3
7
10  
0
1
2
3
7
9
0
1
2
3
6
7
9
0
1
2
3
6
7
9
IO  
I
0
0
PRG0_PRU0_GPI10  
PRG0_UART0_RTSn  
PRG0_PWM2_B1  
RGMII1_RXC  
O
IO  
I
PRG0_PRU0_GPO10  
1
0
PADCONFIG:  
PADCONFIG98  
0x000F4188  
AA5  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
RMII_REF_CLK  
PRG0_IEP0_EDIO_DATA_IN_OUT29  
GPIO1_10  
I
0
IO  
IO  
I
0
pad  
1
UART3_RXD  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPI11  
PRG0_RGMII1_TD0  
PRG0_PWM3_TZ_OUT  
GPIO1_11  
IO  
I
0
0
PRG0_PRU0_GPO11  
O
O
IO  
I
PADCONFIG:  
PADCONFIG99  
0x000F418C  
Y3  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
pad  
1
UART4_RXD  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPI12  
PRG0_RGMII1_TD1  
PRG0_PWM0_A0  
GPIO1_12  
IO  
I
0
0
PRG0_PRU0_GPO12  
O
IO  
IO  
OZ  
IO  
I
PADCONFIG:  
PADCONFIG100  
0x000F4190  
AA3  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0
pad  
GPMC0_A14  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPI13  
PRG0_RGMII1_TD2  
PRG0_PWM0_B0  
SPI3_D0  
0
0
PRG0_PRU0_GPO13  
O
IO  
IO  
IO  
OZ  
IO  
I
PADCONFIG:  
PADCONFIG101  
0x000F4194  
R6  
1
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
GPIO1_13  
pad  
GPMC0_A15  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPI14  
PRG0_RGMII1_TD3  
PRG0_PWM0_A1  
SPI3_D1  
0
0
PRG0_PRU0_GPO14  
O
IO  
IO  
IO  
OZ  
PADCONFIG:  
PADCONFIG102  
0x000F4198  
V4  
0
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
GPIO1_14  
pad  
GPMC0_A3  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG0_PRU0_GPO15  
0
1
2
3
6
7
9
0
1
2
3
6
7
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10  
IO  
I
0
0
PRG0_PRU0_GPI15  
PRG0_RGMII1_TX_CTL  
PRG0_PWM0_B1  
SPI3_CS1  
PRG0_PRU0_GPO15  
O
IO  
IO  
IO  
OZ  
IO  
I
PADCONFIG:  
PADCONFIG103  
0x000F419C  
T5  
1
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
GPIO1_15  
pad  
GPMC0_A16  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPI16  
PRG0_RGMII1_TXC  
PRG0_PWM0_A2  
SPI3_CLK  
0
0
PRG0_PRU0_GPO16  
IO  
IO  
IO  
IO  
OZ  
IO  
I
0
PADCONFIG:  
PADCONFIG104  
0x000F41A0  
U4  
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0
GPIO1_16  
pad  
GPMC0_A4  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPI17  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_PWM0_B2  
CPTS0_TS_SYNC  
CP_GEMAC_CPTS0_TS_SYNC  
SPI3_CS0  
0
0
O
IO  
O
O
IO  
IO  
IO  
OZ  
IO  
I
1
PRG0_PRU0_GPO17  
PADCONFIG:  
PADCONFIG105  
0x000F41A4  
U1  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
pad  
0
GPIO1_17  
TIMER_IO11  
GPMC0_A17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPI18  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
CP_GEMAC_CPTS0_HW1TSPUSH  
EHRPWM8_A  
0
0
I
0
I
0
PRG0_PRU0_GPO18  
I
0
PADCONFIG:  
PADCONFIG106  
0x000F41A8  
V1  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
I
0
GPIO1_18  
pad  
1
UART4_CTSn  
GPMC0_A5  
OZ  
I
UART2_RXD  
1
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG0_PRU0_GPO19  
0
1
IO  
I
0
0
PRG0_PRU0_GPI19  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_PWM0_TZ_OUT  
CPTS0_TS_COMP  
CP_GEMAC_CPTS0_TS_COMP  
EHRPWM8_B  
2
O
O
O
O
IO  
IO  
O
OZ  
I
3
PRG0_PRU0_GPO19  
4
PADCONFIG:  
PADCONFIG107  
0x000F41AC  
W1  
5
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
6
0
GPIO1_19  
7
pad  
UART4_RTSn  
8
GPMC0_A6  
9
UART3_RXD  
10  
0
1
0
PRG0_PRU1_GPO0  
PRG0_PRU1_GPI0  
PRG0_RGMII2_RD0  
GPIO1_20  
IO  
I
1
0
PRG0_PRU1_GPO0  
2
I
0
PADCONFIG:  
PADCONFIG108  
0x000F41B0  
Y2  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
IO  
I
pad  
0
EQEP0_A  
8
UART5_CTSn  
10  
0
I
1
PRG0_PRU1_GPO1  
PRG0_PRU1_GPI1  
PRG0_RGMII2_RD1  
GPIO1_21  
IO  
I
0
1
0
PRG0_PRU1_GPO1  
2
I
0
PADCONFIG:  
PADCONFIG109  
0x000F41B4  
W2  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
IO  
I
pad  
0
EQEP0_B  
8
UART5_TXD  
10  
0
O
IO  
I
PRG0_PRU1_GPO2  
PRG0_PRU1_GPI2  
PRG0_RGMII2_RD2  
PRG0_PWM2_A2  
GPIO1_22  
0
0
1
PRG0_PRU1_GPO2  
2
I
0
PADCONFIG:  
PADCONFIG110  
0x000F41B8  
V3  
3
IO  
IO  
IO  
O
IO  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
0
EQEP0_S  
8
UART5_RTSn  
10  
0
PRG0_PRU1_GPO3  
PRG0_PRU1_GPI3  
PRG0_RGMII2_RD3  
GPIO1_23  
0
0
1
PRG0_PRU1_GPO3  
2
I
0
PADCONFIG:  
PADCONFIG111  
0x000F41BC  
T4  
7
IO  
I
pad  
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
EQEP1_A  
8
GPMC0_A18  
9
OZ  
I
UART6_CTSn  
10  
1
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG0_PRU1_GPO4  
0
1
IO  
I
0
0
PRG0_PRU1_GPI4  
PRG0_RGMII2_RX_CTL  
PRG0_PWM2_B2  
GPIO1_24  
PRG0_PRU1_GPO4  
2
I
0
PADCONFIG:  
PADCONFIG112  
0x000F41C0  
W3  
3
IO  
IO  
I
1
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
7
pad  
0
EQEP1_B  
8
UART6_TXD  
10  
0
O
IO  
I
PRG0_PRU1_GPO5  
PRG0_PRU1_GPI5  
GPIO1_25  
0
0
PRG0_PRU1_GPO5  
1
PADCONFIG:  
PADCONFIG113  
0x000F41C4  
P4  
7
IO  
IO  
O
IO  
I
pad  
0
VDDSHV1  
EQEP1_S  
8
UART6_RTSn  
10  
0
PRG0_PRU1_GPO6  
PRG0_PRU1_GPI6  
PRG0_RGMII2_RXC  
GPIO1_26  
0
0
1
PRG0_PRU1_GPO6  
2
I
0
PADCONFIG:  
PADCONFIG114  
0x000F41C8  
R5  
7
IO  
I
pad  
0
VDDSHV1  
EQEP2_A  
8
GPMC0_A19  
9
OZ  
I
UART4_CTSn  
10  
0
1
0
PRG0_PRU1_GPO7  
PRG0_PRU1_GPI7  
PRG0_IEP1_EDC_LATCH_IN1  
RGMII1_RD0  
IO  
I
1
0
2
I
0
PRG0_PRU1_GPO7  
4
I
0
PADCONFIG:  
PADCONFIG115  
0x000F41CC  
W5  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
RMII1_RXD0  
5
I
0
GPIO1_27  
7
IO  
I
pad  
0
EQEP2_B  
8
UART4_TXD  
10  
0
O
IO  
I
PRG0_PRU1_GPO8  
PRG0_PRU1_GPI8  
PRG0_PWM2_TZ_OUT  
GPIO1_28  
0
0
1
PRG0_PRU1_GPO8  
3
O
IO  
IO  
O
PADCONFIG:  
PADCONFIG116  
0x000F41D0  
R1  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
0
EQEP2_S  
8
UART4_RTSn  
10  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG0_PRU1_GPO9  
0
1
IO  
I
0
0
PRG0_PRU1_GPI9  
PRG0_UART0_RXD  
RGMII1_RD1  
2
I
1
PRG0_PRU1_GPO9  
4
I
0
PADCONFIG:  
PADCONFIG117  
0x000F41D4  
Y5  
RMII1_RXD1  
5
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
PRG0_IEP0_EDIO_DATA_IN_OUT30  
GPIO1_29  
6
IO  
IO  
IO  
I
0
7
pad  
0
EQEP0_I  
8
UART5_RXD  
10  
0
1
PRG0_PRU1_GPO10  
PRG0_PRU1_GPI10  
PRG0_UART0_TXD  
PRG0_PWM2_TZ_IN  
RGMII1_RD2  
IO  
I
0
1
0
2
O
I
3
0
0
PRG0_PRU1_GPO10  
4
I
PADCONFIG:  
PADCONFIG118  
0x000F41D8  
V6  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
RMII1_TXD0  
5
O
IO  
IO  
IO  
I
PRG0_IEP0_EDIO_DATA_IN_OUT31  
GPIO1_30  
6
0
pad  
0
7
EQEP1_I  
8
UART6_RXD  
10  
0
1
PRG0_PRU1_GPO11  
PRG0_PRU1_GPI11  
PRG0_RGMII2_TD0  
GPIO1_31  
IO  
I
0
1
0
PRG0_PRU1_GPO11  
2
O
IO  
IO  
I
PADCONFIG:  
PADCONFIG119  
0x000F41DC  
W4  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
0
EQEP2_I  
8
UART4_RXD  
10  
0
1
PRG0_PRU1_GPO12  
PRG0_PRU1_GPI12  
PRG0_RGMII2_TD1  
PRG0_PWM1_A0  
GPIO1_32  
IO  
I
0
1
0
2
O
IO  
IO  
I
PRG0_PRU1_GPO12  
3
0
pad  
0
PADCONFIG:  
PADCONFIG120  
0x000F41E0  
Y4  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
EQEP2_B  
8
GPMC0_A7  
9
OZ  
O
UART4_TXD  
10  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG0_PRU1_GPO13  
0
1
IO  
I
0
0
PRG0_PRU1_GPI13  
PRG0_RGMII2_TD2  
PRG0_PWM1_B0  
GPIO1_33  
2
O
PRG0_PRU1_GPO13  
3
IO  
IO  
IO  
OZ  
I
1
pad  
0
PADCONFIG:  
PADCONFIG121  
0x000F41E4  
T6  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
EQEP0_I  
8
GPMC0_A8  
9
UART5_RXD  
10  
0
1
0
0
PRG0_PRU1_GPO14  
PRG0_PRU1_GPI14  
PRG0_RGMII2_TD3  
PRG0_PWM1_A1  
GPIO1_34  
IO  
I
1
2
O
PRG0_PRU1_GPO14  
3
IO  
IO  
IO  
OZ  
I
0
pad  
0
PADCONFIG:  
PADCONFIG122  
0x000F41E8  
U6  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
EQEP1_I  
8
GPMC0_A9  
9
UART6_RXD  
10  
0
1
0
0
PRG0_PRU1_GPO15  
PRG0_PRU1_GPI15  
PRG0_RGMII2_TX_CTL  
PRG0_PWM1_B1  
GPIO1_35  
IO  
I
1
PRG0_PRU1_GPO15  
2
O
PADCONFIG:  
PADCONFIG123  
0x000F41EC  
U5  
3
IO  
IO  
OZ  
IO  
IO  
I
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
GPMC0_A10  
9
PRG0_ECAP0_IN_APWM_OUT  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPI16  
PRG0_RGMII2_TXC  
PRG0_PWM1_A2  
GPIO1_36  
10  
0
0
0
1
0
PRG0_PRU1_GPO16  
2
IO  
IO  
IO  
OZ  
O
0
PADCONFIG:  
PADCONFIG124  
0x000F41F0  
AA4  
3
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV1  
Yes  
LVCMOS  
PU/PD  
7
pad  
GPMC0_A11  
9
PRG0_ECAP0_SYNC_OUT  
10  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG0_PRU1_GPO17  
0
1
2
3
4
5
7
8
10  
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
4
IO  
I
0
0
PRG0_PRU1_GPI17  
PRG0_IEP1_EDC_SYNC_OUT1  
PRG0_PWM1_B2  
O
IO  
I
PRG0_PRU1_GPO17  
1
0
PADCONFIG:  
PADCONFIG125  
0x000F41F4  
V5  
RGMII1_RD3  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV1  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
RMII1_TXD1  
O
IO  
O
I
GPIO1_37  
pad  
PRG0_ECAP0_SYNC_OUT  
PRG0_ECAP0_SYNC_IN  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPI18  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_PWM1_TZ_IN  
MDIO0_MDIO  
0
0
0
0
0
0
IO  
I
I
PRG0_PRU1_GPO18  
I
PADCONFIG:  
PADCONFIG126  
0x000F41F8  
P5  
IO  
O
IO  
IO  
I
VDDSHV1  
LVCMOS  
RMII1_TX_EN  
EHRPWM7_A  
0
pad  
0
GPIO1_38  
PRG0_ECAP0_SYNC_IN  
PRG0_PRU1_GPO19  
PRG0_PRU1_GPI19  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_PWM1_TZ_OUT  
MDIO0_MDC  
IO  
I
0
0
O
O
O
I
PRG0_PRU1_GPO19  
PADCONFIG:  
PADCONFIG127  
0x000F41FC  
R2  
VDDSHV1  
LVCMOS  
RMII1_CRS_DV  
0
0
EHRPWM7_B  
IO  
IO  
IO  
O
O
GPIO1_39  
pad  
0
PRG0_ECAP0_IN_APWM_OUT  
PRG1_MDIO0_MDC  
MDIO0_MDC  
PRG1_MDIO0_MDC  
PADCONFIG:  
PADCONFIG87  
0x000F415C  
Y6  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO0_86  
7
IO  
pad  
PRG1_MDIO0_MDIO  
PRG1_MDIO0_MDIO  
MDIO0_MDIO  
0
4
IO  
IO  
0
0
PADCONFIG:  
PADCONFIG86  
0x000F4158  
AA6  
GPIO0_85  
7
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG1_PRU0_GPO0  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
3
4
7
8
IO  
I
0
0
PRG1_PRU0_GPI0  
PRG1_RGMII1_RD0  
PRG1_PWM3_A0  
GPIO0_45  
PRG1_PRU0_GPO0  
I
0
PADCONFIG:  
PADCONFIG46  
0x000F40B8  
Y7  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD16  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPI1  
PRG1_RGMII1_RD1  
PRG1_PWM3_B0  
GPIO0_46  
0
0
PRG1_PRU0_GPO1  
I
0
PADCONFIG:  
PADCONFIG47  
0x000F40BC  
U8  
W8  
V8  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD17  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPI2  
PRG1_RGMII1_RD2  
PRG1_PWM2_A0  
GPIO0_47  
0
0
PRG1_PRU0_GPO2  
I
0
PADCONFIG:  
PADCONFIG48  
0x000F40C0  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD18  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPI3  
PRG1_RGMII1_RD3  
PRG1_PWM3_A2  
GPIO0_48  
0
0
PRG1_PRU0_GPO3  
I
0
PADCONFIG:  
PADCONFIG49  
0x000F40C4  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD19  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPI4  
PRG1_RGMII1_RX_CTL  
PRG1_PWM2_B0  
GPIO0_49  
0
0
PRG1_PRU0_GPO4  
I
0
PADCONFIG:  
PADCONFIG50  
0x000F40C8  
Y8  
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD20  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPI5  
PRG1_PWM3_B2  
RGMII1_RX_CTL  
GPIO0_50  
0
0
PRG1_PRU0_GPO5  
IO  
I
1
PADCONFIG:  
PADCONFIG51  
0x000F40CC  
V13  
0
IO  
IO  
pad  
0
GPMC0_AD21  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG1_PRU0_GPO6  
0
1
2
3
7
8
0
1
2
3
4
5
6
7
8
0
1
3
4
7
8
0
1
2
3
4
5
6
7
8
IO  
I
0
0
PRG1_PRU0_GPI6  
PRG1_RGMII1_RXC  
PRG1_PWM3_A1  
GPIO0_51  
PRG1_PRU0_GPO6  
I
0
PADCONFIG:  
PADCONFIG52  
0x000F40D0  
AA7  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD22  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPI7  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_PWM3_B1  
CPTS0_HW2TSPUSH  
CLKOUT0  
0
0
I
0
PRG1_PRU0_GPO7  
IO  
I
1
PADCONFIG:  
PADCONFIG53  
0x000F40D4  
U13  
W13  
U15  
0
VDDSHV2  
VDDSHV2  
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
O
IO  
IO  
IO  
IO  
I
TIMER_IO10  
0
pad  
0
GPIO0_52  
GPMC0_AD23  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPI8  
PRG1_PWM2_A1  
RGMII1_RXC  
0
0
PRG1_PRU0_GPO8  
IO  
I
0
PADCONFIG:  
PADCONFIG54  
0x000F40D8  
0
GPIO0_53  
IO  
IO  
IO  
I
pad  
0
GPMC0_AD24  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPI9  
PRG1_UART0_CTSn  
PRG1_PWM3_TZ_IN  
RGMII1_TX_CTL  
RMII1_RX_ER  
0
0
I
1
PRG1_PRU0_GPO9  
I
0
PADCONFIG:  
PADCONFIG55  
0x000F40DC  
O
I
0
0
PRG1_IEP0_EDIO_DATA_IN_OUT28  
GPIO0_54  
IO  
IO  
IO  
pad  
0
GPMC0_AD25  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG1_PRU0_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO  
I
0
0
PRG1_PRU0_GPI10  
PRG1_UART0_RTSn  
PRG1_PWM2_B1  
RGMII1_TXC  
O
PRG1_PRU0_GPO10  
IO  
IO  
I
1
0
PADCONFIG:  
PADCONFIG56  
0x000F40E0  
U14  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII_REF_CLK  
0
PRG1_IEP0_EDIO_DATA_IN_OUT29  
GPIO0_55  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD26  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPI11  
PRG1_RGMII1_TD0  
PRG1_PWM3_TZ_OUT  
GPIO0_56  
0
0
PRG1_PRU0_GPO11  
O
PADCONFIG:  
PADCONFIG57  
0x000F40E4  
AA8  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
O
IO  
IO  
IO  
I
pad  
0
GPMC0_AD27  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPI12  
PRG1_RGMII1_TD1  
PRG1_PWM0_A0  
GPIO0_57  
0
0
PRG1_PRU0_GPO12  
O
PADCONFIG:  
PADCONFIG58  
0x000F40E8  
U9  
IO  
IO  
IO  
IO  
I
0
pad  
0
GPMC0_AD28  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPI13  
PRG1_RGMII1_TD2  
PRG1_PWM0_B0  
GPIO0_58  
0
0
PRG1_PRU0_GPO13  
O
PADCONFIG:  
PADCONFIG59  
0x000F40EC  
W9  
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD29  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPI14  
PRG1_RGMII1_TD3  
PRG1_PWM0_A1  
GPIO0_59  
0
0
PRG1_PRU0_GPO14  
O
PADCONFIG:  
PADCONFIG60  
0x000F40F0  
AA9  
IO  
IO  
IO  
0
pad  
0
GPMC0_AD30  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG1_PRU0_GPO15  
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
IO  
I
0
0
PRG1_PRU0_GPI15  
PRG1_RGMII1_TX_CTL  
PRG1_PWM0_B1  
GPIO0_60  
PRG1_PRU0_GPO15  
O
PADCONFIG:  
PADCONFIG61  
0x000F40F4  
Y9  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
IO  
I
1
pad  
0
GPMC0_AD31  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPI16  
PRG1_RGMII1_TXC  
PRG1_PWM0_A2  
GPIO0_61  
0
0
PRG1_PRU0_GPO16  
IO  
IO  
IO  
O
0
PADCONFIG:  
PADCONFIG62  
0x000F40F8  
V9  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
pad  
GPMC0_BE2n  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPI17  
PRG1_IEP0_EDC_SYNC_OUT1  
PRG1_PWM0_B2  
CPTS0_TS_SYNC  
TIMER_IO7  
IO  
I
0
0
O
PRG1_PRU0_GPO17  
IO  
O
1
PADCONFIG:  
PADCONFIG63  
0x000F40FC  
U7  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
IO  
IO  
OZ  
IO  
I
0
GPIO0_62  
pad  
GPMC0_A0  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPI18  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_PWM0_TZ_IN  
CPTS0_HW1TSPUSH  
TIMER_IO8  
0
0
I
0
PRG1_PRU0_GPO18  
I
0
PADCONFIG:  
PADCONFIG64  
0x000F4100  
V7  
VDDSHV2  
LVCMOS  
I
0
IO  
IO  
OZ  
IO  
I
0
GPIO0_63  
pad  
GPMC0_A1  
PRG1_PRU0_GPO19  
PRG1_PRU0_GPI19  
PRG1_IEP0_EDC_SYNC_OUT0  
PRG1_PWM0_TZ_OUT  
CPTS0_TS_COMP  
TIMER_IO9  
0
0
O
PRG1_PRU0_GPO19  
O
PADCONFIG:  
PADCONFIG65  
0x000F4104  
W7  
VDDSHV2  
LVCMOS  
O
IO  
IO  
OZ  
0
GPIO0_64  
pad  
GPMC0_A2  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG1_PRU1_GPO0  
0
1
2
4
5
7
8
0
1
2
4
5
7
8
0
1
2
3
4
7
8
0
1
2
4
7
8
0
1
2
3
4
5
7
8
IO  
I
0
0
PRG1_PRU1_GPI0  
PRG1_RGMII2_RD0  
RGMII2_RD0  
PRG1_PRU1_GPO0  
I
0
PADCONFIG:  
PADCONFIG66  
0x000F4108  
W11  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII2_RXD0  
I
0
GPIO0_65  
IO  
OZ  
IO  
I
pad  
GPMC0_A3  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPI1  
PRG1_RGMII2_RD1  
RGMII2_RD1  
0
0
PRG1_PRU1_GPO1  
I
0
PADCONFIG:  
PADCONFIG67  
0x000F410C  
V11  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII2_RXD1  
I
0
GPIO0_66  
IO  
OZ  
IO  
I
pad  
GPMC0_A4  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPI2  
PRG1_RGMII2_RD2  
PRG1_PWM2_A2  
RGMII2_RD2  
0
0
PRG1_PRU1_GPO2  
I
0
PADCONFIG:  
PADCONFIG68  
0x000F4110  
AA12  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
GPIO0_67  
IO  
OZ  
IO  
I
pad  
GPMC0_A5  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPI3  
PRG1_RGMII2_RD3  
RGMII2_RD3  
0
0
PRG1_PRU1_GPO3  
I
0
PADCONFIG:  
PADCONFIG69  
0x000F4114  
Y12  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
I
0
GPIO0_68  
IO  
OZ  
IO  
I
pad  
GPMC0_A6  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPI4  
PRG1_RGMII2_RX_CTL  
PRG1_PWM2_B2  
RGMII2_RX_CTL  
RMII2_RX_ER  
0
0
I
0
PRG1_PRU1_GPO4  
IO  
I
1
PADCONFIG:  
PADCONFIG70  
0x000F4118  
W12  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
I
0
GPIO0_69  
IO  
OZ  
pad  
GPMC0_A7  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG1_PRU1_GPO5  
0
1
4
7
8
0
1
2
4
7
8
0
1
2
4
5
6
7
8
0
1
3
4
7
8
0
1
2
4
5
6
7
8
IO  
I
0
0
PRG1_PRU1_GPO5  
PRG1_PRU1_GPI5  
RGMII1_RD0  
PADCONFIG:  
PADCONFIG71  
0x000F411C  
AA13  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
Yes  
LVCMOS  
PU/PD  
GPIO0_70  
IO  
OZ  
IO  
I
pad  
GPMC0_A8  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPI6  
PRG1_RGMII2_RXC  
RGMII2_RXC  
0
0
PRG1_PRU1_GPO6  
I
0
PADCONFIG:  
PADCONFIG72  
0x000F4120  
U11  
V15  
U12  
V14  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
VDDSHV2  
VDDSHV2  
VDDSHV2  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
I
0
GPIO0_71  
IO  
OZ  
IO  
I
pad  
GPMC0_A9  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPI7  
PRG1_IEP1_EDC_LATCH_IN1  
RGMII1_TD0  
0
0
0
I
PRG1_PRU1_GPO7  
O
I
PADCONFIG:  
PADCONFIG73  
0x000F4124  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
Yes  
Yes  
Yes  
PU/PD  
PU/PD  
PU/PD  
RMII1_RXD0  
0
1
SPI3_CS3  
IO  
IO  
OZ  
IO  
I
GPIO0_72  
pad  
GPMC0_A10  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPI8  
PRG1_PWM2_TZ_OUT  
RGMII1_RD1  
0
0
PRG1_PRU1_GPO8  
O
I
PADCONFIG:  
PADCONFIG74  
0x000F4128  
0
GPIO0_73  
IO  
OZ  
IO  
I
pad  
GPMC0_A11  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPI9  
PRG1_UART0_RXD  
RGMII1_TD1  
0
0
1
I
PRG1_PRU1_GPO9  
O
I
PADCONFIG:  
PADCONFIG75  
0x000F412C  
RMII1_RXD1  
0
0
PRG1_IEP0_EDIO_DATA_IN_OUT30  
GPIO0_74  
IO  
IO  
OZ  
pad  
GPMC0_A12  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG1_PRU1_GPO10  
0
1
2
3
4
5
6
7
8
0
1
2
4
5
7
8
0
1
2
3
4
5
7
8
0
1
2
3
4
5
7
8
IO  
I
0
0
PRG1_PRU1_GPI10  
PRG1_UART0_TXD  
PRG1_PWM2_TZ_IN  
RGMII1_TD2  
O
PRG1_PRU1_GPO10  
I
0
PADCONFIG:  
PADCONFIG76  
0x000F4130  
W14  
O
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII1_TXD0  
O
PRG1_IEP0_EDIO_DATA_IN_OUT31  
GPIO0_75  
IO  
IO  
OZ  
IO  
I
0
pad  
GPMC0_A13  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPI11  
PRG1_RGMII2_TD0  
RGMII2_TD0  
0
0
PRG1_PRU1_GPO11  
O
PADCONFIG:  
PADCONFIG77  
0x000F4134  
AA10  
O
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII2_TXD0  
O
GPIO0_76  
IO  
OZ  
IO  
I
pad  
GPMC0_A14  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPI12  
PRG1_RGMII2_TD1  
PRG1_PWM1_A0  
RGMII2_TD1  
0
0
O
PRG1_PRU1_GPO12  
IO  
O
0
PADCONFIG:  
PADCONFIG78  
0x000F4138  
V10  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII2_TXD1  
O
GPIO0_77  
IO  
OZ  
IO  
I
pad  
GPMC0_A15  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPI13  
PRG1_RGMII2_TD2  
PRG1_PWM1_B0  
RGMII2_TD2  
0
0
O
PRG1_PRU1_GPO13  
IO  
O
1
PADCONFIG:  
PADCONFIG79  
0x000F413C  
U10  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII2_CRS_DV  
GPIO0_78  
I
0
IO  
OZ  
pad  
GPMC0_A16  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
PRG1_PRU1_GPO14  
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
9
IO  
I
0
0
PRG1_PRU1_GPI14  
PRG1_RGMII2_TD3  
PRG1_PWM1_A1  
RGMII2_TD3  
PRG1_PRU1_GPO14  
O
PADCONFIG:  
PADCONFIG80  
0x000F4140  
AA11  
IO  
O
0
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV2  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
GPIO0_79  
IO  
OZ  
IO  
I
pad  
GPMC0_A17  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPI15  
PRG1_RGMII2_TX_CTL  
PRG1_PWM1_B1  
RGMII2_TX_CTL  
RMII2_TX_EN  
0
0
O
PRG1_PRU1_GPO15  
IO  
O
1
PADCONFIG:  
PADCONFIG81  
0x000F4144  
Y11  
VDDSHV2  
LVCMOS  
O
GPIO0_80  
IO  
OZ  
IO  
I
pad  
GPMC0_A18  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPI16  
PRG1_RGMII2_TXC  
PRG1_PWM1_A2  
RGMII2_TXC  
0
0
PRG1_PRU1_GPO16  
IO  
IO  
IO  
IO  
OZ  
IO  
I
0
PADCONFIG:  
PADCONFIG82  
0x000F4148  
Y10  
0
VDDSHV2  
LVCMOS  
0
GPIO0_81  
pad  
GPMC0_A19  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPI17  
PRG1_IEP1_EDC_SYNC_OUT1  
PRG1_PWM1_B2  
RGMII1_TD3  
0
0
O
PRG1_PRU1_GPO17  
IO  
O
1
PADCONFIG:  
PADCONFIG83  
0x000F414C  
AA14  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII1_TXD1  
O
GPIO0_19  
IO  
O
pad  
GPMC0_BE3n  
PRG1_ECAP0_SYNC_OUT  
O
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
PRG1_PRU1_GPO18  
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
6
7
8
9
IO  
I
0
0
0
0
0
PRG1_PRU1_GPI18  
PRG1_IEP1_EDC_LATCH_IN0  
PRG1_PWM1_TZ_IN  
RGMII1_RD2  
I
PRG1_PRU1_GPO18  
I
PADCONFIG:  
PADCONFIG84  
0x000F4150  
Y13  
I
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII1_TX_EN  
O
IO  
I
GPIO0_20  
pad  
1
UART5_CTSn  
PRG1_ECAP0_SYNC_IN  
PRG1_PRU1_GPO19  
PRG1_PRU1_GPI19  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_PWM1_TZ_OUT  
RGMII1_RD3  
I
0
IO  
I
0
0
O
O
I
PRG1_PRU1_GPO19  
0
0
PADCONFIG:  
PADCONFIG85  
0x000F4154  
V12  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV2  
Yes  
LVCMOS  
PU/PD  
RMII1_CRS_DV  
I
SPI3_CS2  
IO  
IO  
O
IO  
1
GPIO0_84  
pad  
UART5_RTSn  
PRG1_ECAP0_IN_APWM_OUT  
0
RESETSTATz  
PADCONFIG:  
PADCONFIG169  
0x000F42A4  
F16  
E18  
RESETSTATz  
RESET_REQz  
0
0
O
I
Off / Low / Off  
On / Off / Up  
Off / SS / Off  
On / Off / Up  
0
0
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
RESET_REQz  
PADCONFIG:  
PADCONFIG168  
0x000F42A0  
H16  
D21  
G13  
F17  
W15  
V16  
K2  
RSVD0  
RSVD1  
RSVD2  
RSVD3  
RSVD4  
RSVD5  
RSVD6  
RSVD7  
RSVD8  
RSVD0  
RSVD1  
RSVD2  
RSVD3  
RSVD4  
RSVD5  
RSVD6  
RSVD7  
RSVD8  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
K1  
F12  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
T13  
SERDES0_REXT  
SERDES0_REXT  
A
IO  
IO  
I
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
SERDES  
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
W16  
W17  
Y15  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_TX0_N  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_TX0_N  
SERDES0_TX0_P  
SERDES  
SERDES  
SERDES  
SERDES  
SERDES  
SERDES  
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
Y16  
I
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
AA16  
AA17  
O
O
0,  
VDDA_0P85_SERDES  
0_C  
VDDA_1P8_SERDES0  
,
VDDA_0P85_SERDES  
SERDES0_TX0_P  
SPI0_CLK  
0,  
VDDA_0P85_SERDES  
0_C  
SPI0_CLK  
GPIO1_44  
0
7
IO  
IO  
0
PADCONFIG:  
PADCONFIG132  
0x000F4210  
D13  
C14  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
pad  
SPI1_CLK  
SPI1_CLK  
0
3
IO  
I
0
0
PADCONFIG:  
PADCONFIG137  
0x000F4224  
EHRPWM6_SYNCI  
GPIO1_49  
7
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
SPI0_CS0  
SPI0_CS0  
GPIO1_42  
SPI0_CS1  
0
7
IO  
IO  
1
pad  
1
PADCONFIG:  
PADCONFIG130  
0x000F4208  
D12  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
0
1
2
3
4
5
6
7
0
IO  
O
CPTS0_TS_COMP  
I2C2_SCL  
IOD  
IO  
O
1
0
SPI0_CS1  
TIMER_IO10  
PADCONFIG:  
PADCONFIG131  
0x000F420C  
C13  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
PRG0_IEP0_EDIO_OUTVALID  
UART6_RXD  
I
1
0
ADC_EXT_TRIGGER0  
GPIO1_43  
I
IO  
IO  
pad  
0
SPI0_D0  
SPI0_D0  
PADCONFIG:  
PADCONFIG133  
0x000F4214  
A13  
A14  
B14  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
GPIO1_45  
SPI0_D1  
7
0
7
IO  
IO  
IO  
pad  
0
SPI0_D1  
PADCONFIG:  
PADCONFIG134  
0x000F4218  
GPIO1_46  
pad  
SPI1_CS0  
SPI1_CS0  
0
3
IO  
IO  
1
0
PADCONFIG:  
PADCONFIG135  
0x000F421C  
EHRPWM6_A  
GPIO1_47  
7
IO  
pad  
1
SPI1_CS1  
0
1
2
4
5
6
7
8
0
3
IO  
O
CPTS0_TS_SYNC  
I2C2_SDA  
IOD  
O
1
SPI1_CS1  
PRG1_IEP0_EDIO_OUTVALID  
UART6_TXD  
PADCONFIG:  
PADCONFIG136  
0x000F4220  
D14  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
O
ADC_EXT_TRIGGER1  
GPIO1_48  
I
0
pad  
0
IO  
IO  
IO  
O
TIMER_IO11  
SPI1_D0  
SPI1_D0  
0
PADCONFIG:  
PADCONFIG138  
0x000F4228  
EHRPWM6_SYNCO  
B15  
A15  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
GPIO1_50  
7
IO  
pad  
SPI1_D1  
SPI1_D1  
0
3
IO  
IO  
0
0
PADCONFIG:  
PADCONFIG139  
0x000F422C  
EHRPWM6_B  
GPIO1_51  
7
IO  
pad  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
TCK  
PADCONFIG:  
MCU_PADCONFIG26  
0x04084068  
B11  
TCK  
TDI  
0
0
0
0
0
I
On / Off / Up  
On / Off / Up  
Off / Off / Up  
On / Off / Up  
On / Off / Down  
On / Off / Up  
On / Off / Up  
Off / SS / Up  
On / Off / Up  
On / Off / Down  
0
0
0
0
0
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
VDDSHV_MCU  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
TDI  
PADCONFIG:  
MCU_PADCONFIG28  
0x04084070  
C11  
A12  
C12  
D11  
I
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
TDO  
PADCONFIG:  
MCU_PADCONFIG29  
0x04084074  
TDO  
TMS  
TRSTn  
OZ  
TMS  
PADCONFIG:  
MCU_PADCONFIG30  
0x04084078  
I
I
TRSTn  
PADCONFIG:  
MCU_PADCONFIG27  
0x0408406C  
UART0_CTSn  
SPI0_CS2  
0
1
2
3
4
6
7
8
9
0
1
3
4
6
7
8
0
2
7
8
I
1
1
IO  
I
ADC_EXT_TRIGGER0  
UART2_RXD  
TIMER_IO6  
SPI4_CLK  
0
UART0_CTSn  
I
1
PADCONFIG:  
PADCONFIG142  
0x000F4238  
B16  
IO  
IO  
IO  
IO  
O
O
IO  
O
IO  
IO  
IO  
IO  
I
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
0
GPIO1_54  
pad  
0
EQEP0_S  
CP_GEMAC_CPTS0_TS_SYNC  
UART0_RTSn  
SPI0_CS3  
1
UART0_RTSn  
UART2_TXD  
TIMER_IO7  
SPI4_D0  
PADCONFIG:  
PADCONFIG143  
0x000F423C  
A16  
0
0
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
Yes  
LVCMOS  
PU/PD  
GPIO1_55  
pad  
0
EQEP0_I  
UART0_RXD  
SPI2_D0  
1
UART0_RXD  
IO  
IO  
I
0
PADCONFIG:  
PADCONFIG140  
0x000F4230  
D15  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
LVCMOS  
PU/PD  
GPIO1_52  
pad  
0
EQEP0_A  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
UART0_TXD  
0
2
7
8
0
1
2
3
4
5
6
7
8
0
1
4
5
6
7
8
0
2
5
7
8
0
2
5
7
8
O
IO  
IO  
I
UART0_TXD  
SPI2_D1  
0
pad  
0
PADCONFIG:  
PADCONFIG141  
0x000F4234  
C16  
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
GPIO1_53  
EQEP0_B  
UART1_CTSn  
SPI1_CS2  
I
1
IO  
I
1
ADC_EXT_TRIGGER1  
PCIE0_CLKREQn  
UART3_RXD  
0
UART1_CTSn  
IO  
I
0
PADCONFIG:  
PADCONFIG146  
0x000F4248  
D16  
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
CP_GEMAC_CPTS0_TS_SYNC  
SPI4_D1  
O
IO  
IO  
IO  
O
IO  
O
I
0
pad  
0
GPIO1_58  
EQEP1_S  
UART1_RTSn  
SPI1_CS3  
1
UART1_RTSn  
UART3_TXD  
PADCONFIG:  
PADCONFIG147  
0x000F424C  
E16  
CP_GEMAC_CPTS0_HW2TSPUSH  
SPI4_CS0  
0
1
Off / Off / Off  
Off / Off / Off  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
IO  
IO  
IO  
I
GPIO1_59  
pad  
0
EQEP1_I  
UART1_RXD  
1
UART1_RXD  
SPI2_CS0  
IO  
O
IO  
I
1
PADCONFIG:  
PADCONFIG144  
0x000F4240  
E15  
E14  
CP_GEMAC_CPTS0_TS_COMP  
GPIO1_56  
Off / Off / Off  
Off / Off / Off  
7
7
1.8 V/3.3 V  
VDDSHV0  
VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
pad  
0
EQEP1_A  
UART1_TXD  
O
IO  
I
UART1_TXD  
SPI2_CLK  
0
0
PADCONFIG:  
PADCONFIG145  
0x000F4244  
CP_GEMAC_CPTS0_HW1TSPUSH  
GPIO1_57  
Off / Off / Off  
Off / Off / Off  
1.8 V/3.3 V  
IO  
I
pad  
0
EQEP1_B  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
AA20  
AA19  
USB0_DM  
USB0_DP  
USB0_DM  
USB0_DP  
IO  
IO  
1.8 V/3.3 V  
1.8 V/3.3 V  
USB2PHY  
USB2PHY  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
STATE  
DURING  
RESET  
BALL  
STATE  
AFTER  
RESET  
MUX  
MODE  
AFTER  
RESET  
[9]  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [7]  
RX/TX/PULL [8]  
USB0_DRVVBUS  
USB0_DRVVBUS  
0
7
O
PADCONFIG:  
PADCONFIG170  
0x000F42A8  
E19  
Off / Off / Down  
Off / Off / Down  
7
1.8 V/3.3 V  
VDDSHV0  
Yes  
LVCMOS  
PU/PD  
GPIO1_79  
IO  
pad  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
U16  
U17  
T14  
USB0_ID  
USB0_ID  
A
A
A
1.8 V/3.3 V  
1.8 V/3.3 V  
1.8 V/3.3 V  
USB2PHY  
USB2PHY  
USB2PHY  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
USB0_RCALIB  
USB0_VBUS  
USB0_RCALIB  
USB0_VBUS  
VDDA_3P3_USB0,  
VDDA_1P8_USB0,  
VDDA_0P85_USB0  
P12, P13  
P11  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_ADC  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_ADC  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
T12  
R14  
R15  
H15  
R13  
J13  
K12  
VDDA_MCU  
VDDA_MCU  
N12  
VDDA_PLL0  
VDDA_PLL0  
H9  
VDDA_PLL1  
VDDA_PLL1  
J11  
VDDA_PLL2  
VDDA_PLL2  
G11  
VDDA_TEMP0  
VDDA_TEMP0  
L11  
VDDA_TEMP1  
VDDA_TEMP1  
L10, M13  
VDDR_CORE  
VDDR_CORE  
F11, G12,  
G14  
VDDSHV0  
VDDSHV0  
PWR  
M7, N6, P7 VDDSHV1  
R10, R8, T9 VDDSHV2  
VDDSHV1  
VDDSHV2  
VDDSHV3  
VDDSHV4  
VDDSHV5  
VDDSHV_MCU  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
P14, P15  
M14, M15  
L14, L15  
VDDSHV3  
VDDSHV4  
VDDSHV5  
F9, G10, G8 VDDSHV_MCU  
F7, G6, H7,  
VDDS_DDR  
J6, K7, L6  
VDDS_DDR  
PWR  
J8  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
PWR  
PWR  
PWR  
K14  
H13  
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表6-1. Pin Attributes (ALV Package) (continued)  
BALL  
BALL  
MUX  
BALL NAME [2]  
PADCONFIG Register [15]  
PADCONFIG Address [16]  
MUX  
MODE  
[4]  
STATE  
DURING  
RESET  
RX/TX/PULL [7]  
STATE  
AFTER  
RESET  
MODE  
AFTER  
RESET  
[9]  
I/O  
PULL  
UP/DOWN  
TYPE [14]  
BALL  
NUMBER [1]  
TYPE  
[5]  
DSIS  
[6]  
HYS  
[12]  
BUFFER  
TYPE [13]  
SIGNAL NAME [3]  
OPERATING  
VOLTAGE [10]  
POWER [11]  
RX/TX/PULL [8]  
J10, J12,  
K11, K9, L12,  
L8, M11, M9,  
N10, N8, P9  
VDD_CORE  
VDD_CORE  
PWR  
H14  
K13  
K16  
E12  
F13  
F14  
K10  
G15  
VDD_DLL_MMC0  
VDD_MMC0  
VDD_DLL_MMC0  
VDD_MMC0  
PWR  
PWR  
A
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
VPP  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
VPP  
A
A
A
A
PWR  
A1, A21, A5,  
A6, AA1,  
AA15, AA18,  
AA21, C10,  
C15, C3, D1,  
E11, E13,  
F10, F15, F8,  
G1, G16, G3,  
G7, G9, H11,  
H20, H21,  
H6, H8, J14,  
J7, J9, K6,  
K8, L1, L16,  
L3, L7, L9,  
M10, M12,  
M6, M8, N11,  
N13, N15,  
VSS  
VSS  
GND  
N7, N9, P1,  
P10, P18, P6,  
P8, R12, R7,  
R9, T10, T11,  
T15, T16, T8,  
U3, V17,  
W10, W18,  
Y14, Y17,  
Y19  
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6.3 Signal Descriptions  
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing  
options.  
The following list describes the column headers:  
1. SIGNAL NAME: The name of the signal passing through the pin.  
备注  
Signal names and descriptions provided in each Signal Descriptions table, represent the pin  
multiplexed signal function which is implemented at the pin and selected via PADCONFIG  
registers. Device subsystems may provide secondary multiplexing of signal functions, which are  
not described in these tables. For more information on secondary multiplexed signal functions,  
see the respective peripheral chapter of the device TRM.  
2. PIN TYPE: Signal direction and type:  
• I = Input  
• O = Output  
• OD = Output, with open-drain output function  
• IO = Input, Output, or simultaneously Input and Output  
• IOD = Input, Output, or simultaneously Input and Output with open-drain output function  
• IOZ = Input, Output, or simultaneously Input and Output with three-state output function  
• OZ = Output with three-state output function  
• A = Analog  
• PWR = Power  
• GND = Ground  
• CAP = LDO Capacitor  
3. DESCRIPTION: Description of the signal  
4. BALL: Ball number(s) associated with signal  
For more information on the IO cell configurations, see the Pad Configuration Registers section in Device  
Configuration chapter of the device TRM.  
6.3.1 ADC  
备注  
The ADC can be configured to operate as eight general-purpose digital inputs. For more information,  
see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.  
6.3.1.1 MAIN Domain  
表6-2. ADC0 Signal Descriptions  
SIGNAL NAME [1]  
ADC0_REFN (4)  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
J16  
A
A
A
A
A
A
A
A
ADC0 Negative Reference  
ADC0_REFP (4)  
ADC0 Positive Reference  
J15  
ADC0_AIN0 (1) (2) (3)  
ADC0_AIN1 (1) (2) (3)  
ADC0_AIN2 (1) (2) (3)  
ADC0_AIN3 (1) (2) (3)  
ADC0_AIN4 (1) (2) (3)  
ADC0_AIN5 (1) (2) (3)  
ADC Analog Input 0 / GPIO1_80 (Input Only)  
ADC Analog Input 1 / GPIO1_81 (Input Only)  
ADC Analog Input 2 / GPIO1_82 (Input Only)  
ADC Analog Input 3 / GPIO1_83 (Input Only)  
ADC Analog Input 4 / GPIO1_84 (Input Only)  
ADC Analog Input 5 / GPIO1_85 (Input Only)  
G20  
F20  
E21  
D20  
G21  
F21  
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表6-2. ADC0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ADC Analog Input 6 / GPIO1_86 (Input Only)  
ADC Analog Input 7 / GPIO1_87 (Input Only)  
ADC Trigger Input  
ALV PIN [4]  
F19  
ADC0_AIN6 (1) (2) (3)  
ADC0_AIN7 (1) (2) (3)  
ADC_EXT_TRIGGER0  
ADC_EXT_TRIGGER1  
A
A
I
E20  
B16, C13  
D14, D16  
I
ADC Trigger Input  
(1) The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate  
in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC)  
section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.  
(2) The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode.  
(3) Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected  
to a power source.  
(4) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails,  
where ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is  
connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected to the same power source  
as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency  
decoupling capacitor must be connected directly between ADC0_REFP and ADC0_REFN. The high frequency decoupling capacitor  
should be placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN pins with  
vias. ADC0_REFP may be connected to VSS if ADC0 is not used and VDDA_ADC0 has been connected to VSS. The high frequency  
decoupling capacitor described above will not be required if ADC0 is not used and ADC0_REFP is connected to VSS. See the Pin  
Connectivity Requirements section for more information on ADC0 connectivity.  
6.3.2 CPSW3G  
6.3.2.1 MAIN Domain  
表6-3. CPSW3G0 RGMII1 Signal Descriptions  
SIGNAL NAME [1]  
RGMII1_RXC  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
AA5, W13  
V13, W6  
U14  
I
I
RGMII Receive Clock  
RGMII1_RX_CTL  
RGMII1_TXC  
RGMII1_TX_CTL  
RGMII1_RD0  
RGMII1_RD1  
RGMII1_RD2  
RGMII1_RD3  
RGMII1_TD0  
RGMII1_TD1  
RGMII1_TD2  
RGMII1_TD3  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
IO  
O
I
U15  
AA13, W5  
U12, Y5  
V6, Y13  
V12, V5  
V15  
I
I
I
O
O
O
O
V14  
W14  
AA14  
表6-4. CPSW3G0 RGMII2 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U11  
RGMII2_RXC  
RGMII2_RX_CTL  
RGMII2_TXC  
RGMII2_TX_CTL  
RGMII2_RD0  
RGMII2_RD1  
RGMII2_RD2  
RGMII2_RD3  
RGMII2_TD0  
RGMII2_TD1  
RGMII2_TD2  
I
I
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
W12  
Y10  
IO  
O
I
Y11  
W11  
I
V11  
I
AA12  
Y12  
I
O
O
O
AA10  
V10  
U10  
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表6-4. CPSW3G0 RGMII2 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
RGMII2_TD3  
O
RGMII Transmit Data 3  
AA11  
表6-5. CPSW3G0 RMII1 and RMII2 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R2, V12  
U15, W6  
P5, Y13  
U10  
RMII1_CRS_DV  
RMII1_RX_ER  
RMII1_TX_EN  
RMII2_CRS_DV  
RMII2_RX_ER  
RMII2_TX_EN  
RMII1_RXD0  
RMII1_RXD1  
RMII1_TXD0  
I
I
RMII Carrier Sense / Data Valid  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Carrier Sense / Data Valid  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Receive Data 0  
RMII Receive Data 1  
RMII Transmit Data 0  
RMII Transmit Data 1  
RMII Receive Data 0  
RMII Receive Data 1  
RMII Transmit Data 0  
RMII Transmit Data 1  
RMII Reference Clock  
O
I
I
W12  
O
I
Y11  
V15, W5  
V14, Y5  
V6, W14  
AA14, V5  
W11  
I
O
O
I
RMII1_TXD1  
RMII2_RXD0  
RMII2_RXD1  
RMII2_TXD0  
I
V11  
O
O
I
AA10  
RMII2_TXD1  
V10  
RMII_REF_CLK (1)  
AA5, U14  
(1) RMII_REF_CLK is common to both RMII1 and RMII2.  
6.3.3 CPTS  
6.3.3.1 MAIN Domain  
表6-6. CP GEMAC CPTS0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
CP_GEMAC_CPTS0_RFT_CLK  
I
CPTS Reference Clock Input to CPSW3G0 CPTS  
D18  
CPTS Time Stamp Counter Compare Output from  
CPSW3G0 CPTS  
CP_GEMAC_CPTS0_TS_COMP  
CP_GEMAC_CPTS0_TS_SYNC  
CP_GEMAC_CPTS0_HW1TSPUSH  
CP_GEMAC_CPTS0_HW2TSPUSH  
O
O
I
E15, K18, W1  
CPTS Time Stamp Counter Bit Output from CPSW3G0 B16, D16, K19,  
CPTS  
U1  
CPTS Hardware Time Stamp Push Input to CPSW3G0  
CPTS  
E14, L21, V1  
E16, K21, T1  
CPTS Hardware Time Stamp Push Input to CPSW3G0  
CPTS  
I
表6-7. CPTS0 Signal Descriptions  
SIGNAL NAME [1]  
CPTS0_RFT_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D18  
I
CPTS Reference Clock Input  
CPTS0_TS_COMP  
O
O
CPTS Time Stamp Counter Compare Output  
CPTS Time Stamp Counter Bit Output  
C13, W1, W7  
D14, U1, U7  
CPTS0_TS_SYNC  
CPTS Hardware Time Stamp Push Input to Time Sync  
Router  
CPTS0_HW1TSPUSH  
CPTS0_HW2TSPUSH  
SYNC0_OUT  
I
C18, V1, V7  
B19, T1, U13  
D18  
CPTS Hardware Time Stamp Push Input to Time Sync  
Router  
I
CPTS Time Stamp Generator Bit 0 Output from Time  
Sync Router  
O
O
CPTS Time Stamp Generator Bit 1 Output from Time  
Sync Router  
SYNC1_OUT  
A19  
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表6-7. CPTS0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
A17  
CPTS Time Stamp Generator Bit 2 Output from Time  
Sync Router  
SYNC2_OUT  
SYNC3_OUT  
O
O
CPTS Time Stamp Generator Bit 3 Output from Time  
Sync Router  
B17  
6.3.4 DDRSS  
6.3.4.1 MAIN Domain  
表6-8. DDRSS0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
H2  
H1  
J5  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
O
IO  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
DDRSS Activation Command  
DDRSS Alert  
DDRSS Column Address Strobe  
DDRSS Command and Address Parity  
DDRSS Row Address Strobe  
DDRSS Write Enable  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Address Bus  
DDRSS Bank Address  
DDRSS Bank Address  
DDRSS Bank Group  
DDRSS Bank Group  
IO Pad Calibration Resistor  
DDRSS Clock  
K5  
F6  
H4  
D2  
C5  
E2  
D4  
D3  
F2  
DDR0_A1  
DDR0_A2  
DDR0_A3  
DDR0_A4  
DDR0_A5  
DDR0_A6  
J2  
DDR0_A7  
L5  
DDR0_A8  
J3  
DDR0_A9  
J4  
DDR0_A10  
DDR0_A11  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0 (1)  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
K3  
J1  
M5  
K4  
G4  
G5  
G2  
H3  
H5  
F1  
O
O
O
O
O
O
IO  
IO  
IO  
IO  
IO  
IO  
DDRSS Negative Clock  
DDRSS Clock Enable  
DDRSS Clock Enable  
DDRSS Chip Select 0  
DDRSS Chip Select 1  
DDRSS Data Mask  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
A2  
B5  
A4  
DDRSS Data Mask  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
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表6-8. DDRSS0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
B3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
C4  
C2  
B4  
N5  
L4  
L2  
M3  
N4  
N3  
M4  
N2  
DDRSS Data Strobe 0  
C1  
DDR0_DQS0_n  
DDR0_DQS1  
DDRSS Complimentary Data Strobe 0  
DDRSS Data Strobe 1  
B1  
N1  
DDR0_DQS1_n  
DDR0_ODT0  
DDRSS Complimentary Data Strobe 1  
DDRSS On-Die Termination for Chip Select 0  
DDRSS On-Die Termination for Chip Select 1  
DDRSS Reset  
M1  
E5  
DDR0_ODT1  
O
F5  
DDR0_RESET0_n  
O
D5  
(1) An external 240 Ω±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is  
5.2mW. No external voltage should be applied to this pin.  
6.3.5 ECAP  
6.3.5.1 MAIN Domain  
表6-9. ECAP0 Signal Descriptions  
SIGNAL NAME [1]  
ECAP0_IN_APWM_OUT  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Output  
IO  
D18  
表6-10. ECAP1 Signal Descriptions  
SIGNAL NAME [1]  
ECAP1_IN_APWM_OUT  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Output  
IO  
C17  
表6-11. ECAP2 Signal Descriptions  
SIGNAL NAME [1]  
ECAP2_IN_APWM_OUT  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Output  
IO  
D17  
6.3.6 Emulation and Debug  
6.3.6.1 MAIN Domain  
表6-12. Trace Signal Descriptions  
SIGNAL NAME [1]  
TRC_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T20  
O
O
O
Trace Clock  
Trace Control  
Trace Data 0  
TRC_CTL  
U21  
TRC_DATA0  
T18  
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表6-12. Trace Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U20  
U18  
U19  
V20  
TRC_DATA1  
TRC_DATA2  
TRC_DATA3  
TRC_DATA4  
TRC_DATA5  
TRC_DATA6  
TRC_DATA7  
TRC_DATA8  
TRC_DATA9  
TRC_DATA10  
TRC_DATA11  
TRC_DATA12  
TRC_DATA13  
TRC_DATA14  
TRC_DATA15  
TRC_DATA16  
TRC_DATA17  
TRC_DATA18  
TRC_DATA19  
TRC_DATA20  
TRC_DATA21  
TRC_DATA22  
TRC_DATA23  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Data 1  
Trace Data 2  
Trace Data 3  
Trace Data 4  
Trace Data 5  
Trace Data 6  
Trace Data 7  
Trace Data 8  
Trace Data 9  
Trace Data 10  
Trace Data 11  
Trace Data 12  
Trace Data 13  
Trace Data 14  
Trace Data 15  
Trace Data 16  
Trace Data 17  
Trace Data 18  
Trace Data 19  
Trace Data 20  
Trace Data 21  
Trace Data 22  
Trace Data 23  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
Y21  
Y20  
R17  
P16  
R18  
T21  
P17  
T19  
W19  
Y18  
N16  
R19  
6.3.6.2 MCU Domain  
表6-13. JTAG Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D10  
EMU0  
EMU1  
TCK  
IO  
Emulation Control 0  
Emulation Control 1  
JTAG Test Clock Input  
JTAG Test Data Input  
JTAG Test Data Output  
JTAG Test Mode Select Input  
JTAG Reset  
IO  
E10  
I
B11  
TDI  
I
C11  
TDO  
OZ  
A12  
TMS  
I
I
C12  
TRSTn  
D11  
6.3.7 EPWM  
6.3.7.1 MAIN Domain  
表6-14. EPWM Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C17  
EHRPWM_SOCA  
EHRPWM_SOCB  
EHRPWM_TZn_IN0  
EHRPWM_TZn_IN1  
EHRPWM_TZn_IN2  
EHRPWM_TZn_IN3  
O
O
I
EHRPWM Start of Conversion A  
EHRPWM Start of Conversion B  
D17  
EHRPWM Trip Zone Input 0 (active low)  
EHRPWM Trip Zone Input 1 (active low)  
EHRPWM Trip Zone Input 2 (active low)  
EHRPWM Trip Zone Input 3 (active low)  
T18  
I
V21  
I
R16, R20  
P16  
I
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表6-14. EPWM Signal Descriptions (continued)  
SIGNAL NAME [1]  
EHRPWM_TZn_IN4  
EHRPWM_TZn_IN5  
PIN TYPE [2]  
DESCRIPTION [3]  
EHRPWM Trip Zone Input 4 (active low)  
EHRPWM Trip Zone Input 5 (active low)  
ALV PIN [4]  
P17, P19  
I
I
R21, Y18  
表6-15. EPWM0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U20  
EHRPWM0_A  
IO  
IO  
I
EHRPWM Output A  
EHRPWM0_B  
EHRPWM Output B  
U18  
EHRPWM0_SYNCI  
EHRPWM0_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
T20  
O
U21  
表6-16. EPWM1 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U19  
EHRPWM1_A  
EHRPWM1_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
V20  
表6-17. EPWM2 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V19  
EHRPWM2_A  
EHRPWM2_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
T17  
表6-18. EPWM3 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V18  
EHRPWM3_A  
IO  
IO  
I
EHRPWM Output A  
EHRPWM3_B  
EHRPWM Output B  
Y21  
EHRPWM3_SYNCI  
EHRPWM3_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
Y20  
O
R17  
表6-19. EPWM4 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R18  
EHRPWM4_A  
EHRPWM4_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
T21  
表6-20. EPWM5 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T19  
EHRPWM5_A  
EHRPWM5_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
W19  
表6-21. EPWM6 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
B14, N16  
A15, N17  
C14, R19  
B15, R20  
EHRPWM6_A  
IO  
IO  
I
EHRPWM Output A  
EHRPWM6_B  
EHRPWM Output B  
EHRPWM6_SYNCI  
EHRPWM6_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
O
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表6-22. EPWM7 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
EHRPWM Output A  
EHRPWM Output B  
ALV PIN [4]  
P17, P5, W20  
R2, W21, Y18  
EHRPWM7_A  
EHRPWM7_B  
IO  
IO  
表6-23. EPWM8 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V1, V21  
EHRPWM8_A  
EHRPWM8_B  
IO  
IO  
EHRPWM Output A  
EHRPWM Output B  
R16, W1  
6.3.8 EQEP  
6.3.8.1 MAIN Domain  
表6-24. EQEP0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D15, N16, Y2  
C16, N17, W2  
A16, R20, T6, Y5  
B16, R19, V3  
EQEP0_A (1)  
EQEP0_B (1)  
EQEP0_I (1)  
EQEP0_S (1)  
I
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
I
IO  
IO  
EQEP Strobe  
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
表6-25. EQEP1 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
E15, T4, W20  
E14, W21, W3  
EQEP1_A (1)  
EQEP1_B (1)  
I
I
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
E16, R21, U6,  
V6  
EQEP1_I (1)  
EQEP1_S (1)  
IO  
IO  
EQEP Strobe  
D16, P19, P4  
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
表6-26. EQEP2 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C17, R5  
EQEP2_A (1)  
EQEP2_B (1)  
EQEP2_I (1)  
EQEP2_S (1)  
I
EQEP Quadrature Input A  
I
EQEP Quadrature Input B  
EQEP Index  
D17, W5, Y4  
A17, W4  
IO  
IO  
EQEP Strobe  
B17, R1  
(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
6.3.9 FSI  
6.3.9.1 MAIN Domain  
表6-27. FSI0 RX Signal Descriptions  
SIGNAL NAME [1]  
FSI_RX0_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V19  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
FSI_RX0_D0  
FSI_RX0_D1  
T17  
R16  
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表6-28. FSI0 TX Signal Descriptions  
SIGNAL NAME [1]  
FSI_TX0_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T19  
O
FSI Clock  
FSI Data  
FSI Data  
FSI_TX0_D0  
FSI_TX0_D1  
O
O
Y21  
Y20  
表6-29. FSI1 RX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
W20  
FSI_RX1_CLK  
FSI_RX1_D0  
FSI_RX1_D1  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
W21  
V18  
表6-30. FSI1 TX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
N16  
FSI_TX1_CLK  
FSI_TX1_D0  
FSI_TX1_D1  
O
O
O
FSI Clock  
FSI Data  
FSI Data  
P17  
Y18  
表6-31. FSI2 RX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T20  
FSI_RX2_CLK  
FSI_RX2_D0  
FSI_RX2_D1  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
U21  
T18  
表6-32. FSI3 RX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U20  
FSI_RX3_CLK  
FSI_RX3_D0  
FSI_RX3_D1  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
U18  
U19  
表6-33. FSI4 RX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R17  
FSI_RX4_CLK  
FSI_RX4_D0  
FSI_RX4_D1  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
V20  
V21  
表6-34. FSI5 RX Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
P16  
FSI_RX5_CLK  
FSI_RX5_D0  
FSI_RX5_D1  
I
I
I
FSI Clock  
FSI Data  
FSI Data  
R18  
T21  
6.3.10 GPIO  
6.3.10.1 MAIN Domain  
表6-35. GPIO0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
GPIO0_0  
IO  
General Purpose Input/Output  
N20  
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表6-35. GPIO0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
N21  
N19  
M19  
M18  
M20  
M21  
P21  
P20  
N18  
M17  
L19  
GPIO0_1  
IO  
General Purpose Input/Output  
GPIO0_2  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
GPIO0_3  
IO  
GPIO0_4  
IO  
GPIO0_5  
IO  
GPIO0_6  
IO  
GPIO0_7  
IO  
GPIO0_8  
IO  
GPIO0_9  
IO  
GPIO0_10  
GPIO0_11  
GPIO0_12  
GPIO0_13  
GPIO0_14  
GPIO0_15  
GPIO0_16  
GPIO0_17  
GPIO0_18  
GPIO0_19  
GPIO0_20  
GPIO0_21  
GPIO0_22  
GPIO0_23  
GPIO0_24  
GPIO0_25  
GPIO0_26  
GPIO0_27  
GPIO0_28  
GPIO0_29  
GPIO0_30  
GPIO0_31  
GPIO0_32  
GPIO0_33  
GPIO0_34  
GPIO0_35  
GPIO0_36  
GPIO0_37  
GPIO0_38  
GPIO0_39  
GPIO0_40  
GPIO0_41  
GPIO0_42  
GPIO0_43 (1)  
GPIO0_44 (1)  
GPIO0_45  
IO  
IO  
IO  
L18  
IO  
K17  
L17  
IO  
IO  
T20  
IO  
U21  
T18  
IO  
IO  
U20  
AA14  
Y13  
V20  
V21  
V19  
T17  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
R16  
W20  
W21  
V18  
Y21  
Y20  
R17  
P16  
R18  
T21  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
P17  
T19  
IO  
IO  
W19  
Y18  
N16  
N17  
R19  
R20  
P19  
R21  
Y7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
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表6-35. GPIO0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U8  
GPIO0_46  
GPIO0_47  
GPIO0_48  
GPIO0_49  
GPIO0_50  
GPIO0_51  
GPIO0_52  
GPIO0_53  
GPIO0_54  
GPIO0_55  
GPIO0_56  
GPIO0_57  
GPIO0_58  
GPIO0_59  
GPIO0_60  
GPIO0_61  
GPIO0_62  
GPIO0_63  
GPIO0_64  
GPIO0_65  
GPIO0_66  
GPIO0_67  
GPIO0_68  
GPIO0_69  
GPIO0_70  
GPIO0_71  
GPIO0_72  
GPIO0_73  
GPIO0_74  
GPIO0_75  
GPIO0_76  
GPIO0_77  
GPIO0_78  
GPIO0_79  
GPIO0_80  
GPIO0_81  
GPIO0_82  
GPIO0_83  
GPIO0_84  
GPIO0_85  
GPIO0_86  
IO  
General Purpose Input/Output  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
W8  
IO  
V8  
IO  
Y8  
IO  
V13  
AA7  
U13  
W13  
U15  
U14  
AA8  
U9  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
W9  
IO  
AA9  
Y9  
IO  
IO  
V9  
IO  
U7  
IO  
V7  
IO  
W7  
IO  
W11  
V11  
AA12  
Y12  
W12  
AA13  
U11  
V15  
U12  
V14  
W14  
AA10  
V10  
U10  
AA11  
Y11  
Y10  
U18  
U19  
V12  
AA6  
Y6  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
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表6-36. GPIO1 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Y1  
GPIO1_0  
IO  
General Purpose Input/Output  
GPIO1_1  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
R4  
GPIO1_2  
IO  
U2  
GPIO1_3  
IO  
V2  
GPIO1_4  
IO  
AA2  
R3  
GPIO1_5  
IO  
GPIO1_6  
IO  
T3  
GPIO1_7  
IO  
T1  
GPIO1_8  
IO  
T2  
GPIO1_9  
IO  
W6  
AA5  
Y3  
GPIO1_10  
GPIO1_11  
GPIO1_12  
GPIO1_13  
GPIO1_14  
GPIO1_15  
GPIO1_16  
GPIO1_17  
GPIO1_18  
GPIO1_19  
GPIO1_20  
GPIO1_21  
GPIO1_22  
GPIO1_23  
GPIO1_24  
GPIO1_25  
GPIO1_26  
GPIO1_27  
GPIO1_28  
GPIO1_29  
GPIO1_30  
GPIO1_31  
GPIO1_32  
GPIO1_33  
GPIO1_34  
GPIO1_35  
GPIO1_36  
GPIO1_37  
GPIO1_38  
GPIO1_39  
GPIO1_40  
GPIO1_41  
GPIO1_42  
GPIO1_43  
GPIO1_44  
IO  
IO  
IO  
AA3  
R6  
IO  
IO  
V4  
IO  
T5  
IO  
U4  
IO  
U1  
IO  
V1  
IO  
W1  
Y2  
IO  
IO  
W2  
V3  
IO  
IO  
T4  
IO  
W3  
P4  
IO  
IO  
R5  
IO  
W5  
R1  
IO  
IO  
Y5  
IO  
V6  
IO  
W4  
Y4  
IO  
IO  
T6  
IO  
U6  
IO  
U5  
IO  
AA4  
V5  
IO  
IO  
P5  
IO  
R2  
IO  
P2  
IO  
P3  
IO  
D12  
C13  
D13  
IO  
IO  
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表6-36. GPIO1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
A13  
A14  
B14  
D14  
C14  
B15  
A15  
D15  
C16  
B16  
A16  
E15  
E14  
D16  
E16  
A17  
B17  
C17  
D17  
A18  
B18  
C18  
B19  
D18  
A19  
C19  
K18  
K19  
L21  
GPIO1_45  
GPIO1_46  
GPIO1_47  
GPIO1_48  
GPIO1_49  
GPIO1_50  
GPIO1_51  
GPIO1_52  
GPIO1_53  
GPIO1_54  
GPIO1_55  
GPIO1_56  
GPIO1_57  
GPIO1_58  
GPIO1_59  
GPIO1_60  
GPIO1_61  
GPIO1_62  
GPIO1_63  
GPIO1_64  
GPIO1_65  
GPIO1_66  
GPIO1_67  
GPIO1_68 (1)  
GPIO1_69  
GPIO1_70 (1)  
GPIO1_71 (1)  
GPIO1_72 (1)  
GPIO1_73 (1)  
GPIO1_74 (1)  
GPIO1_75 (1)  
GPIO1_76 (1)  
GPIO1_77 (1)  
GPIO1_78 (1)  
GPIO1_79  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IOD  
IOD  
IO  
IO  
IO  
IO  
IOD  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
K21  
L20  
J19  
D19  
C20  
E19  
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
6.3.10.2 MCU Domain  
表6-37. MCU_GPIO0 Signal Descriptions  
SIGNAL NAME [1]  
MCU_GPIO0_0 (1)  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
IO  
IO  
IO  
IO  
IO  
General Purpose Input/Output  
E8  
D8  
A8  
A9  
B6  
MCU_GPIO0_1 (1)  
MCU_GPIO0_2  
MCU_GPIO0_3  
MCU_GPIO0_4  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
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表6-37. MCU_GPIO0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
A7  
MCU_GPIO0_5 (1)  
MCU_GPIO0_6 (1)  
MCU_GPIO0_7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IOD  
IOD  
IO  
IO  
IO  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
B7  
D7  
MCU_GPIO0_8  
C7  
MCU_GPIO0_9  
C8  
MCU_GPIO0_10  
MCU_GPIO0_11  
MCU_GPIO0_12 (1)  
MCU_GPIO0_13 (1)  
MCU_GPIO0_14  
MCU_GPIO0_15  
MCU_GPIO0_16 (1)  
MCU_GPIO0_17 (1)  
MCU_GPIO0_18  
MCU_GPIO0_19  
MCU_GPIO0_20 (1)  
MCU_GPIO0_21 (1)  
MCU_GPIO0_22  
E7  
E6  
C6  
D6  
C9  
D9  
B8  
B9  
E9  
A10  
A11  
B10  
B13  
(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device  
Configuration chapter.  
6.3.11 GPMC  
6.3.11.1 MAIN Domain  
表6-38. GPMC0 Signal Descriptions  
SIGNAL NAME [1]  
GPMC0_ADVn_ALE  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
GPMC Address Valid (active low) or Address Latch  
Enable  
O
O
O
P16  
R17  
N17  
GPMC0_CLK (1)  
GPMC0_DIR  
GPMC clock  
GPMC Data Bus Signal Direction Control  
GPMC Output Enable (active low) or Read Enable  
(active low)  
GPMC0_OEn_REn  
O
O
O
R18  
T21  
N16  
GPMC0_WEn  
GPMC0_WPn  
GPMC Write Enable (active low)  
GPMC Flash Write Protect (active low)  
GPMC Address 0 Output. Only used to effectively  
address 8-bit data non-multiplexed memories  
GPMC0_A0  
GPMC0_A1  
GPMC0_A2  
GPMC0_A3  
GPMC0_A4  
GPMC0_A5  
GPMC0_A6  
GPMC0_A7  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
U2, U7  
AA2, V7  
T2, W7  
GPMC address 1 Output in A/D non-multiplexed mode  
and Address 17 in A/D multiplexed mode  
GPMC address 2 Output in A/D non-multiplexed mode  
and Address 18 in A/D multiplexed mode  
GPMC address 3 Output in A/D non-multiplexed mode  
and Address 19 in A/D multiplexed mode  
V4, W11  
U4, V11  
AA12, V1  
W1, Y12  
W12, Y4  
GPMC address 4 Output in A/D non-multiplexed mode  
and Address 20 in A/D multiplexed mode  
GPMC address 5 Output in A/D non-multiplexed mode  
and Address 21 in A/D multiplexed mode  
GPMC address 6 Output in A/D non-multiplexed mode  
and Address 22 in A/D multiplexed mode  
GPMC address 7 Output in A/D non-multiplexed mode  
and Address 23 in A/D multiplexed mode  
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表6-38. GPMC0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
AA13, T6  
U11, U6  
U5, V15  
AA4, U12  
P2, V14  
P3, W14  
AA10, AA3  
R6, V10  
T5, U10  
AA11, U1  
T4, Y11  
R5, Y10  
R21  
GPMC address 8 Output in A/D non-multiplexed mode  
and Address 24 in A/D multiplexed mode  
GPMC0_A8  
GPMC0_A9  
GPMC0_A10  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
GPMC0_A20  
GPMC0_A21  
GPMC0_A22  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
GPMC address 9 Output in A/D non-multiplexed mode  
and Address 25 in A/D multiplexed mode  
GPMC address 10 Output in A/D non-multiplexed  
mode and Address 26 in A/D multiplexed mode  
GPMC address 11 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 12 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 13 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 14 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 15 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 16 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 17 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 18 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 19 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 20 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
GPMC address 21 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
Y18  
GPMC address 22 Output in A/D non-multiplexed  
mode and unused in A/D multiplexed mode  
N16  
GPMC Data 0 Input/Output in A/D non-multiplexed  
mode and additionally Address 1 Output in A/D  
multiplexed mode  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
GPMC Data 1 Input/Output in A/D non-multiplexed  
mode and additionally Address 2 Output in A/D  
multiplexed mode  
GPMC Data 2 Input/Output in A/D non-multiplexed  
mode and additionally Address 3 Output in A/D  
multiplexed mode  
GPMC Data 3 Input/Output in A/D non-multiplexed  
mode and additionally Address 4 Output in A/D  
multiplexed mode  
GPMC Data 4 Input/Output in A/D non-multiplexed  
mode and additionally Address 5 Output in A/D  
multiplexed mode  
GPMC Data 5 Input/Output in A/D non-multiplexed  
mode and additionally Address 6 Output in A/D  
multiplexed mode  
GPMC Data 6 Input/Output in A/D non-multiplexed  
mode and additionally Address 7 Output in A/D  
multiplexed mode  
GPMC Data 7 Input/Output in A/D non-multiplexed  
mode and additionally Address 8 Output in A/D  
multiplexed mode  
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表6-38. GPMC0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V19  
T17  
R16  
W20  
W21  
V18  
Y21  
Y20  
Y7  
GPMC Data 8 Input/Output in A/D non-multiplexed  
mode and additionally Address 9 Output in A/D  
multiplexed mode  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_AD16  
GPMC0_AD17  
GPMC0_AD18  
GPMC0_AD19  
GPMC0_AD20  
GPMC0_AD21  
GPMC0_AD22  
GPMC0_AD23  
GPMC0_AD24  
GPMC0_AD25  
GPMC0_AD26  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
GPMC Data 9 Input/Output in A/D non-multiplexed  
mode and additionally Address 10 Output in A/D  
multiplexed mode  
GPMC Data 10 Input/Output in A/D non-multiplexed  
mode and additionally Address 11 Output in A/D  
multiplexed mode  
GPMC Data 11 Input/Output in A/D non-multiplexed  
mode and additionally Address 12 Output in A/D  
multiplexed mode  
GPMC Data 12 Input/Output in A/D non-multiplexed  
mode and additionally Address 13 Output in A/D  
multiplexed mode  
GPMC Data 13 Input/Output in A/D non-multiplexed  
mode and additionally Address 14 Output in A/D  
multiplexed mode  
GPMC Data 14 Input/Output in A/D non-multiplexed  
mode and additionally Address 15 Output in A/D  
multiplexed mode  
GPMC Data 15 Input/Output in A/D non-multiplexed  
mode and additionally Address 16 Output in A/D  
multiplexed mode  
GPMC Data 16 Input/Output in A/D non-multiplexed  
mode and additionally Address 17 Output in A/D  
multiplexed mode  
GPMC Data 17 Input/Output in A/D non-multiplexed  
mode and additionally Address 18 Output in A/D  
multiplexed mode  
U8  
GPMC Data 18 Input/Output in A/D non-multiplexed  
mode and additionally Address 19 Output in A/D  
multiplexed mode  
W8  
GPMC Data 19 Input/Output in A/D non-multiplexed  
mode and additionally Address 20 Output in A/D  
multiplexed mode  
V8  
GPMC Data 20 Input/Output in A/D non-multiplexed  
mode and additionally Address 21 Output in A/D  
multiplexed mode  
Y8  
GPMC Data 21 Input/Output in A/D non-multiplexed  
mode and additionally Address 22 Output in A/D  
multiplexed mode  
V13  
AA7  
U13  
W13  
U15  
U14  
GPMC Data 22 Input/Output in A/D non-multiplexed  
mode and additionally Address 23 Output in A/D  
multiplexed mode  
GPMC Data 23 Input/Output in A/D non-multiplexed  
mode and additionally Address 24 Output in A/D  
multiplexed mode  
GPMC Data 24 Input/Output in A/D non-multiplexed  
mode and additionally Address 25 Output in A/D  
multiplexed mode  
GPMC Data 25 Input/Output in A/D non-multiplexed  
mode and additionally Address 26 Output in A/D  
multiplexed mode  
GPMC Data 26 Input/Output in A/D non-multiplexed  
mode and additionally Address 27 Output in A/D  
multiplexed mode  
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表6-38. GPMC0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
GPMC0_AD27  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
GPMC Data 27 Input/Output in A/D non-multiplexed  
mode and additionally Address 28 Output in A/D  
multiplexed mode  
IO  
IO  
IO  
IO  
IO  
AA8  
U9  
GPMC Data 28 Input/Output in A/D non-multiplexed  
mode and additionally Address 29 Output in A/D  
multiplexed mode  
GPMC0_AD28  
GPMC0_AD29  
GPMC0_AD30  
GPMC Data 29 Input/Output in A/D non-multiplexed  
mode and additionally Address 30 Output in A/D  
multiplexed mode  
W9  
AA9  
Y9  
GPMC Data 30 Input/Output in A/D non-multiplexed  
mode and additionally Address 31 Output in A/D  
multiplexed mode  
GPMC Data 31 Input/Output in A/D non-multiplexed  
mode and additionally Address 0 Output in A/D  
multiplexed mode  
GPMC0_AD31  
GPMC Lower-Byte Enable (active low) or Command  
Latch Enable  
GPMC0_BE0n_CLE  
O
O
O
O
O
O
O
O
I
P17  
T19  
V9  
GPMC0_BE1n  
GPMC0_BE2n  
GPMC0_BE3n  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC Upper-Byte Enable (active low)  
GPMC Upper-Byte Enable (active low)  
GPMC Upper-Byte Enable (active low)  
GPMC Chip Select 0 (active low)  
GPMC Chip Select 1 (active low)  
GPMC Chip Select 2 (active low)  
GPMC Chip Select 3 (active low)  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
AA14  
R19  
R20  
P19  
R21  
W19  
Y18  
I
(1) The RXACTIVE bit of the CTRLMMR_PADCONFIG32 register must be set to 0x1 and the TX_DIS bit of the  
CTRLMMR_PADCONFIG32 register must be reset to 0x0 when GPMC0 is operating in synchronous mode.  
6.3.12 I2C  
6.3.12.1 MAIN Domain  
表6-39. I2C0 Signal Descriptions  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
A18  
I2C0_SCL  
I2C0_SDA  
IOD  
I2C Clock  
I2C Data  
IOD  
B18  
表6-40. I2C1 Signal Descriptions  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C18  
I2C1_SCL  
I2C1_SDA  
IOD  
I2C Clock  
I2C Data  
IOD  
B19  
表6-41. I2C2 Signal Descriptions  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C13, P19  
I2C2_SCL  
I2C2_SDA  
IOD  
I2C Clock  
I2C Data  
IOD  
D14, R21  
表6-42. I2C3 Signal Descriptions  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
I2C3_SCL  
IOD  
I2C Clock  
C17  
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表6-42. I2C3 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
I2C3_SDA  
IOD  
I2C Data  
D17  
6.3.12.2 MCU Domain  
表6-43. MCU_I2C0 Signal Descriptions  
SIGNAL NAME [1]  
MCU_I2C0_SCL  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
IOD  
I2C Clock  
I2C Data  
E9  
MCU_I2C0_SDA  
IOD  
A10  
表6-44. MCU_I2C1 Signal Descriptions  
SIGNAL NAME [1]  
MCU_I2C1_SCL  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
A11  
IOD  
I2C Clock  
I2C Data  
MCU_I2C1_SDA  
IOD  
B10  
6.3.13 MCAN  
6.3.13.1 MAIN Domain  
表6-45. MCAN0 Signal Descriptions  
SIGNAL NAME [1]  
MCAN0_RX  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
B17  
I
MCAN Receive Data  
MCAN Transmit Data  
MCAN0_TX  
O
A17  
表6-46. MCAN1 Signal Descriptions  
SIGNAL NAME [1]  
MCAN1_RX  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D17  
I
MCAN Receive Data  
MCAN Transmit Data  
MCAN1_TX  
O
C17  
6.3.14 MCSPI  
6.3.14.1 MAIN Domain  
表6-47. MCSPI0 Signal Descriptions  
SIGNAL NAME [1]  
SPI0_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D13  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI0_CS0  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
D12  
SPI0_CS1  
C13  
SPI0_CS2  
B16  
SPI0_CS3  
A16  
SPI0_D0  
A13  
SPI0_D1  
SPI Data 1  
A14  
表6-48. MCSPI1 Signal Descriptions  
SIGNAL NAME [1]  
SPI1_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C14  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI1_CS0  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
B14  
SPI1_CS1  
D14  
SPI1_CS2  
D16  
SPI1_CS3  
E16  
SPI1_D0  
B15  
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表6-48. MCSPI1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
SPI1_D1  
IO  
SPI Data 1  
A15  
表6-49. MCSPI2 Signal Descriptions  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
E14  
SPI2_CLK  
SPI2_CS0  
SPI2_CS1  
SPI2_CS2  
SPI2_CS3  
SPI2_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
E15  
C18  
B19  
A19  
D15  
SPI2_D1  
SPI Data 1  
C16  
表6-50. MCSPI3 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
SPI3_CLK  
SPI3_CS0  
SPI3_CS1  
SPI3_CS2  
SPI3_CS3  
SPI3_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
U4  
U1  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
T5  
V12  
V15  
R6  
SPI3_D1  
SPI Data 1  
V4  
表6-51. MCSPI4 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
B16  
SPI4_CLK  
SPI4_CS0  
SPI4_CS1  
SPI4_CS2  
SPI4_CS3  
SPI4_D0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 0  
SPI Chip Select 2  
SPI Data 0  
E16  
A17  
B17  
D18  
A16  
SPI4_D1  
SPI Data 1  
D16  
6.3.14.2 MCU Domain  
表6-52. MCU_MCSPI0 Signal Descriptions  
SIGNAL NAME [1]  
MCU_SPI0_CLK  
MCU_SPI0_CS0  
MCU_SPI0_CS1  
MCU_SPI0_CS2  
MCU_SPI0_CS3  
MCU_SPI0_D0  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
E6  
D6  
C6  
D8  
B8  
E7  
B6  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
MCU_SPI0_D1  
SPI Data 1  
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表6-53. MCU_MCSPI1 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
MCU_SPI1_CLK  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
MCU_SPI1_CS2  
MCU_SPI1_CS3  
MCU_SPI1_D0  
MCU_SPI1_D1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
SPI Clock  
D7  
A7  
B7  
E8  
B9  
C7  
C8  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
SPI Data 1  
6.3.15 MDIO  
6.3.15.1 MAIN Domain  
表6-54. MDIO0 Signal Descriptions  
SIGNAL NAME [1]  
MDIO0_MDC  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R2, Y6  
O
MDIO Clock  
MDIO Data  
MDIO0_MDIO  
IO  
AA6, P5  
6.3.16 MMC  
6.3.16.1 MAIN Domain  
表6-55. MMC0 Signal Descriptions  
SIGNAL NAME [1]  
MMC0_CALPAD (1)  
MMC0_CLK  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
F18  
A
MMC/SD/SDIO Calibration Resistor  
MMC/SD/SDIO Clock  
MMC/SD/SDIO Command  
MMC Data Strobe  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
G18  
J21  
MMC0_CMD  
MMC0_DS  
G19  
K20  
MMC0_DAT0  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC0_DAT1  
J20  
MMC0_DAT2  
J18  
MMC0_DAT3  
J17  
MMC0_DAT4  
H17  
MMC0_DAT5  
H19  
MMC0_DAT6  
H18  
MMC0_DAT7  
G17  
(1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
表6-56. MMC1 Signal Descriptions  
SIGNAL NAME [1]  
MMC1_CLK (1)  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
L20  
IO  
IO  
I
MMC/SD/SDIO Clock  
MMC1_CMD  
MMC1_SDCD  
MMC1_SDWP  
MMC1_DAT0  
MMC1_DAT1  
MMC1_DAT2  
MMC1_DAT3  
MMC/SD/SDIO Command  
SD Card Detect  
J19  
D19  
I
SD Write Protect  
C20  
IO  
IO  
IO  
IO  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
MMC/SD/SDIO Data  
K21  
L21  
K19  
K18  
(1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG164 register must remain in its default state  
of 0x1 because of retiming purposes.  
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6.3.17 OSPI  
6.3.17.1 MAIN Domain  
表6-57. OSPI0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
N20  
N19  
L17  
OSPI0_CLK  
OSPI0_DQS  
O
OSPI Clock  
I
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI ECC Status  
OSPI0_ECC_FAIL  
OSPI0_LBCLKO  
OSPI0_CSn0  
OSPI0_CSn1  
OSPI0_CSn2  
OSPI0_CSn3  
OSPI0_D0  
I
IO  
O
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Chip Select 2 (active low)  
OSPI Chip Select 3 (active low)  
OSPI Data 0  
N21  
L19  
O
L18  
O
K17  
O
L17  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
M19  
M18  
M20  
M21  
P21  
OSPI0_D1  
OSPI Data 1  
OSPI0_D2  
OSPI Data 2  
OSPI0_D3  
OSPI Data 3  
OSPI0_D4  
OSPI Data 4  
OSPI0_D5  
OSPI Data 5  
P20  
OSPI0_D6  
OSPI Data 6  
N18  
M17  
L17  
OSPI0_D7  
OSPI Data 7  
OSPI0_RESET_OUT0  
OSPI0_RESET_OUT1  
OSPI Reset  
O
OSPI Reset  
K17  
6.3.18 Power Supply  
表6-58. Power Supply Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
External capacitor connection for IO group 0  
External capacitor connection for IO group 1  
External capacitor connection for IO group 2  
External capacitor connection for IO group 3  
External capacitor connection for IO group 4  
External capacitor connection for IO group 5  
External capacitor connection for MMC1  
External capacitor connection for IO MCU  
SERDES0 0.85 V analog supply  
SERDES0 clock 0.85 V analog supply  
USB0 0.85 V analog supply  
ALV PIN [4]  
H12  
T7  
CAP_VDDS0 (1)  
CAP  
CAP_VDDS1 (1)  
CAP  
CAP_VDDS2 (1)  
CAP  
R11  
CAP_VDDS3 (1)  
CAP  
N14  
M16  
L13  
CAP_VDDS4 (1)  
CAP  
CAP_VDDS5 (1)  
CAP  
CAP_VDDSHV_MMC1 (2)  
CAP_VDDS_MCU (1)  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_3P3_SDIO  
VDDA_3P3_USB0  
VDDA_ADC  
CAP  
K15  
CAP  
H10  
P12, P13  
P11  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
T12  
SERDES0 1.8 V analog supply  
R14  
R15  
H15  
R13  
J13  
USB0 1.8 V analog supply  
SDIO 3.3 V analog supply  
USB0 3.3 V analog supply  
ADC0 analog supply  
VDDA_MCU  
POR and MCU PLL analog supply  
Main, PER1, and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
K12  
VDDA_PLL0  
N12  
H9  
VDDA_PLL1  
VDDA_PLL2  
J11  
VDDA_TEMP0  
TEMP0 analog supply  
G11  
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表6-58. Power Supply Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
L11  
VDDA_TEMP1  
VDDR_CORE  
VDDSHV0  
PWR  
TEMP1 analog supply  
PWR  
RAM supply  
L10, M13  
PWR  
IO supply for IO group 0  
IO supply for IO group 1  
IO supply for IO group 2  
IO supply for IO group 3  
IO supply for IO group 4  
IO supply for IO group 5  
IO supply for IO MCU  
F11, G12, G14  
M7, N6, P7  
R10, R8, T9  
P14, P15  
VDDSHV1  
PWR  
VDDSHV2  
PWR  
VDDSHV3  
PWR  
VDDSHV4  
PWR  
M14, M15  
L14, L15  
VDDSHV5  
PWR  
VDDSHV_MCU  
PWR  
F9, G10, G8  
F7, G6, H7, J6,  
K7, L6  
VDDS_DDR  
DDR PHY IO supply  
PWR  
PWR  
PWR  
PWR  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
DDR clock IO supply  
MMC0 PHY IO supply  
MCU_OSC0 supply  
J8  
K14  
H13  
J10, J12, K11,  
K9, L12, L8,  
M11, M9, N10,  
N8, P9  
VDD_CORE  
Core supply  
PWR  
PWR  
PWR  
PWR  
VDD_DLL_MMC0  
VDD_MMC0  
VPP  
MMC0 PLL analog supply  
MMC0 PHY core supply  
H14  
K13  
G15  
eFuse ROM programming supply  
A1, A21, A5, A6,  
AA1, AA15,  
AA18, AA21,  
C10, C15, C3,  
D1, E11, E13,  
F10, F15, F8,  
G1, G16, G3,  
G7, G9, H11,  
H20, H21, H6,  
H8, J14, J7, J9,  
K6, K8, L1, L16,  
L3, L7, L9, M10,  
M12, M6, M8,  
N11, N13, N15,  
N7, N9, P1, P10,  
P18, P6, P8,  
VSS  
Ground  
R12, R7, R9,  
T10, T11, T15,  
T16, T8, U3,  
V17, W10, W18,  
Y14, Y17, Y19  
GND  
(1) This pin must always be connected via a 1-μF capacitor to VSS.  
(2) This pin must always be connected via a 3.3-μF ±20% capacitor to VSS.  
6.3.19 PRU_ICSSG  
备注  
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU  
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in  
the device TRM.  
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6.3.19.1 MAIN Domain  
表6-59. PRU_ICSSG0 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
PRU-ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Output  
PRG0_ECAP0_IN_APWM_OUT  
IO  
I
R2, U5  
P5, V5  
AA4, V5  
C13  
PRG0_ECAP0_SYNC_IN  
PRU-ICSSG ECAP Sync Input  
PRG0_ECAP0_SYNC_OUT  
PRG0_IEP0_EDIO_OUTVALID  
O
O
PRU-ICSSG ECAP Sync Output  
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_IEP0_EDIO_DATA_IN_OUT28  
PRG0_IEP0_EDIO_DATA_IN_OUT29  
PRG0_IEP0_EDIO_DATA_IN_OUT30  
PRG0_IEP0_EDIO_DATA_IN_OUT31  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_IEP1_EDC_LATCH_IN1  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_IEP1_EDC_SYNC_OUT1  
I
I
V1  
T1  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
IO  
IO  
IO  
IO  
I
W1  
U1  
W6  
AA5  
Y5  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
V6  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
P5  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
I
W5  
R2  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
O
IO  
I
V5  
P3  
PRG0_MDIO0_MDC  
PRG0_MDIO0_MDIO  
PRG0_PRU0_GPI0  
PRG0_PRU0_GPI1  
PRG0_PRU0_GPI2  
PRG0_PRU0_GPI3  
PRG0_PRU0_GPI4  
PRG0_PRU0_GPI5  
PRG0_PRU0_GPI6  
PRG0_PRU0_GPI7  
PRG0_PRU0_GPI8  
PRG0_PRU0_GPI9  
PRG0_PRU0_GPI10  
PRG0_PRU0_GPI11  
PRG0_PRU0_GPI12  
PRG0_PRU0_GPI13  
PRG0_PRU0_GPI14  
PRG0_PRU0_GPI15  
PRG0_PRU0_GPI16  
PRU-ICSSG MDIO Clock  
PRU-ICSSG MDIO Data  
P2  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
Y1  
I
R4  
U2  
V2  
I
I
I
AA2  
R3  
T3  
I
I
I
T1  
I
T2  
I
W6  
AA5  
Y3  
I
I
I
AA3  
R6  
V4  
I
I
I
T5  
I
U4  
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表6-59. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U1  
PRG0_PRU0_GPI17  
PRG0_PRU0_GPI18  
PRG0_PRU0_GPI19  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPI0  
PRG0_PRU1_GPI1  
PRG0_PRU1_GPI2  
PRG0_PRU1_GPI3  
PRG0_PRU1_GPI4  
PRG0_PRU1_GPI5  
PRG0_PRU1_GPI6  
PRG0_PRU1_GPI7  
PRG0_PRU1_GPI8  
PRG0_PRU1_GPI9  
PRG0_PRU1_GPI10  
PRG0_PRU1_GPI11  
PRG0_PRU1_GPI12  
PRG0_PRU1_GPI13  
PRG0_PRU1_GPI14  
PRG0_PRU1_GPI15  
PRG0_PRU1_GPI16  
PRG0_PRU1_GPI17  
PRG0_PRU1_GPI18  
PRG0_PRU1_GPI19  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO1  
I
I
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
V1  
I
W1  
Y1  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
R4  
U2  
V2  
AA2  
R3  
T3  
T1  
T2  
W6  
AA5  
Y3  
AA3  
R6  
V4  
T5  
U4  
U1  
V1  
W1  
Y2  
I
W2  
V3  
I
I
T4  
I
W3  
P4  
I
I
R5  
I
W5  
R1  
I
I
Y5  
I
V6  
I
W4  
Y4  
I
I
T6  
I
U6  
I
U5  
I
AA4  
V5  
I
I
P5  
I
R2  
IO  
IO  
Y2  
W2  
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表6-59. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PRG0_PRU1_GPO2  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
V3  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRU-ICSSG PRU Data Output  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
PRG0_PWM0_TZ_IN  
PRG0_PWM0_TZ_OUT  
PRG0_PWM1_TZ_IN  
PRG0_PWM1_TZ_OUT  
PRG0_PWM2_TZ_IN  
PRG0_PWM2_TZ_OUT  
PRG0_PWM3_TZ_IN  
PRG0_PWM3_TZ_OUT  
PRG0_PWM0_A0  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
T4  
W3  
P4  
R5  
W5  
R1  
Y5  
V6  
W4  
Y4  
T6  
U6  
U5  
AA4  
V5  
P5  
R2  
V1  
O
W1  
I
P5  
O
R2  
I
T18, V6  
R1, U21  
P16, W6  
R17, Y3  
AA3  
V4  
O
I
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
PRG0_PWM0_A1  
PRG0_PWM0_A2  
U4  
PRG0_PWM0_B0  
R6  
PRG0_PWM0_B1  
T5  
PRG0_PWM0_B2  
U1  
PRG0_PWM1_A0  
Y4  
PRG0_PWM1_A1  
U6  
PRG0_PWM1_A2  
AA4  
T6  
PRG0_PWM1_B0  
PRG0_PWM1_B1  
U5  
PRG0_PWM1_B2  
V5  
PRG0_PWM2_A0  
U2, U20  
T2, U19  
V19, V3  
AA2, U18  
AA5, V20  
T17, W3  
V18, Y1  
PRG0_PWM2_A1  
PRG0_PWM2_A2  
PRG0_PWM2_B0  
PRG0_PWM2_B1  
PRG0_PWM2_B2  
PRG0_PWM3_A0  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-59. PRU_ICSSG0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R18, T3  
T19, V2  
R4, Y21  
T1, T21  
R3, W19  
T3  
PRG0_PWM3_A1  
IO  
IO  
IO  
IO  
IO  
I
PRU_ICSSG PWM Output A  
PRG0_PWM3_A2  
PRU_ICSSG PWM Output A  
PRG0_PWM3_B0  
PRU_ICSSG PWM Output B  
PRG0_PWM3_B1  
PRU_ICSSG PWM Output B  
PRG0_PWM3_B2  
PRU_ICSSG PWM Output B  
PRG0_RGMII1_RXC  
PRG0_RGMII1_RX_CTL  
PRG0_RGMII1_TXC  
PRG0_RGMII1_TX_CTL  
PRG0_RGMII2_RXC  
PRG0_RGMII2_RX_CTL  
PRG0_RGMII2_TXC  
PRG0_RGMII2_TX_CTL  
PRG0_RGMII1_RD0  
PRG0_RGMII1_RD1  
PRG0_RGMII1_RD2  
PRG0_RGMII1_RD3  
PRG0_RGMII1_TD0  
PRG0_RGMII1_TD1  
PRG0_RGMII1_TD2  
PRG0_RGMII1_TD3  
PRG0_RGMII2_RD0  
PRG0_RGMII2_RD1  
PRG0_RGMII2_RD2  
PRG0_RGMII2_RD3  
PRG0_RGMII2_TD0  
PRG0_RGMII2_TD1  
PRG0_RGMII2_TD2  
PRG0_RGMII2_TD3  
PRG0_UART0_CTSn  
PRG0_UART0_RTSn  
PRG0_UART0_RXD  
PRG0_UART0_TXD  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU-ICSSG UART Clear to Send (active low)  
PRU-ICSSG UART Request to Send (active low)  
PRU-ICSSG UART Receive Data  
PRU-ICSSG UART Transmit Data  
I
AA2  
U4  
IO  
O
I
T5  
R5  
I
W3  
IO  
O
I
AA4  
U5  
Y1  
I
R4  
I
U2  
I
V2  
O
O
O
O
I
Y3  
AA3  
R6  
V4  
Y2  
I
W2  
I
V3  
I
T4  
O
O
O
O
I
W4  
Y4  
T6  
U6  
W6  
O
I
AA5  
Y5  
O
V6  
表6-60. PRU_ICSSG1 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
PRU-ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Output  
PRG1_ECAP0_IN_APWM_OUT  
IO  
I
V12  
Y13  
PRG1_ECAP0_SYNC_IN  
PRU-ICSSG ECAP Sync Input  
PRG1_ECAP0_SYNC_OUT  
PRG1_IEP0_EDIO_OUTVALID  
O
O
PRU-ICSSG ECAP Sync Output  
AA14  
D14  
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_IEP0_EDC_SYNC_OUT0  
I
I
V7  
U13  
W7  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
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表6-60. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U7  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRG1_IEP0_EDC_SYNC_OUT1  
O
IO  
IO  
IO  
IO  
I
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRG1_IEP0_EDIO_DATA_IN_OUT28  
PRG1_IEP0_EDIO_DATA_IN_OUT29  
PRG1_IEP0_EDIO_DATA_IN_OUT30  
PRG1_IEP0_EDIO_DATA_IN_OUT31  
PRG1_IEP1_EDC_LATCH_IN0  
U15  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
U14  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
V14  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
W14  
Y13  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Latch Input  
PRG1_IEP1_EDC_LATCH_IN1  
I
V15  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_IEP1_EDC_SYNC_OUT1  
O
V12  
PRU_ICSSG Industrial Ethernet Distributed Clock  
Sync Output  
O
AA14  
Y6  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
PRG1_PRU0_GPI0  
PRG1_PRU0_GPI1  
PRG1_PRU0_GPI2  
PRG1_PRU0_GPI3  
PRG1_PRU0_GPI4  
PRG1_PRU0_GPI5  
PRG1_PRU0_GPI6  
PRG1_PRU0_GPI7  
PRG1_PRU0_GPI8  
PRG1_PRU0_GPI9  
PRG1_PRU0_GPI10  
PRG1_PRU0_GPI11  
PRG1_PRU0_GPI12  
PRG1_PRU0_GPI13  
PRG1_PRU0_GPI14  
PRG1_PRU0_GPI15  
PRG1_PRU0_GPI16  
PRG1_PRU0_GPI17  
PRG1_PRU0_GPI18  
PRG1_PRU0_GPI19  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO7  
O
PRU-ICSSG MDIO Clock  
IO  
PRU-ICSSG MDIO Data  
AA6  
Y7  
I
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
I
U8  
I
W8  
V8  
I
I
Y8  
I
I
V13  
AA7  
U13  
W13  
U15  
U14  
AA8  
U9  
I
I
I
I
I
I
I
W9  
AA9  
Y9  
I
I
I
V9  
I
U7  
I
V7  
I
W7  
Y7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
U8  
W8  
V8  
Y8  
V13  
AA7  
U13  
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ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
表6-60. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
W13  
U15  
U14  
AA8  
U9  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU1_GPI0  
PRG1_PRU1_GPI1  
PRG1_PRU1_GPI2  
PRG1_PRU1_GPI3  
PRG1_PRU1_GPI4  
PRG1_PRU1_GPI5  
PRG1_PRU1_GPI6  
PRG1_PRU1_GPI7  
PRG1_PRU1_GPI8  
PRG1_PRU1_GPI9  
PRG1_PRU1_GPI10  
PRG1_PRU1_GPI11  
PRG1_PRU1_GPI12  
PRG1_PRU1_GPI13  
PRG1_PRU1_GPI14  
PRG1_PRU1_GPI15  
PRG1_PRU1_GPI16  
PRG1_PRU1_GPI17  
PRG1_PRU1_GPI18  
PRG1_PRU1_GPI19  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Input  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
W9  
AA9  
Y9  
V9  
U7  
V7  
W7  
W11  
V11  
I
I
AA12  
Y12  
W12  
AA13  
U11  
I
I
I
I
I
V15  
U12  
V14  
W14  
AA10  
V10  
U10  
AA11  
Y11  
I
I
I
I
I
I
I
I
I
Y10  
AA14  
Y13  
V12  
W11  
V11  
I
I
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AA12  
Y12  
W12  
AA13  
U11  
V15  
U12  
V14  
W14  
AA10  
V10  
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表6-60. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PRG1_PRU1_GPO13  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
U10  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRU-ICSSG PRU Data Output  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO19  
PRG1_PWM0_TZ_IN  
PRG1_PWM0_TZ_OUT  
PRG1_PWM1_TZ_IN  
PRG1_PWM1_TZ_OUT  
PRG1_PWM2_TZ_IN  
PRG1_PWM2_TZ_OUT  
PRG1_PWM3_TZ_IN  
PRG1_PWM3_TZ_OUT  
PRG1_PWM0_A0  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU-ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
AA11  
Y11  
Y10  
AA14  
Y13  
V12  
V7  
O
W7  
I
Y13  
O
V12  
I
P19, W14  
R20, U12  
U15  
O
I
O
AA8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
U9  
PRG1_PWM0_A1  
AA9  
PRG1_PWM0_A2  
V9  
PRG1_PWM0_B0  
W9  
PRG1_PWM0_B1  
Y9  
PRG1_PWM0_B2  
U7  
PRG1_PWM1_A0  
V10  
PRG1_PWM1_A1  
AA11  
Y10  
PRG1_PWM1_A2  
PRG1_PWM1_B0  
U10  
PRG1_PWM1_B1  
Y11  
PRG1_PWM1_B2  
AA14  
N16, W8  
P17, W13  
AA12, V21  
N17, Y8  
U14, Y18  
R16, W12  
Y7  
PRG1_PWM2_A0  
PRG1_PWM2_A1  
PRG1_PWM2_A2  
PRG1_PWM2_B0  
PRG1_PWM2_B1  
PRG1_PWM2_B2  
PRG1_PWM3_A0  
PRG1_PWM3_A1  
AA7  
PRG1_PWM3_A2  
V8  
PRG1_PWM3_B0  
U8  
PRG1_PWM3_B1  
U13  
PRG1_PWM3_B2  
V13  
PRG1_RGMII1_RXC  
PRG1_RGMII1_RX_CTL  
PRG1_RGMII1_TXC  
PRG1_RGMII1_TX_CTL  
PRG1_RGMII2_RXC  
PRG1_RGMII2_RX_CTL  
AA7  
I
Y8  
IO  
O
V9  
Y9  
I
U11  
I
W12  
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表6-60. PRU_ICSSG1 Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU-ICSSG UART Clear to Send (active low)  
PRU-ICSSG UART Request to Send (active low)  
PRU-ICSSG UART Receive Data  
PRU-ICSSG UART Transmit Data  
ALV PIN [4]  
Y10  
Y11  
PRG1_RGMII2_TXC  
PRG1_RGMII2_TX_CTL  
PRG1_RGMII1_RD0  
PRG1_RGMII1_RD1  
PRG1_RGMII1_RD2  
PRG1_RGMII1_RD3  
PRG1_RGMII1_TD0  
PRG1_RGMII1_TD1  
PRG1_RGMII1_TD2  
PRG1_RGMII1_TD3  
PRG1_RGMII2_RD0  
PRG1_RGMII2_RD1  
PRG1_RGMII2_RD2  
PRG1_RGMII2_RD3  
PRG1_RGMII2_TD0  
PRG1_RGMII2_TD1  
PRG1_RGMII2_TD2  
PRG1_RGMII2_TD3  
PRG1_UART0_CTSn  
PRG1_UART0_RTSn  
PRG1_UART0_RXD  
PRG1_UART0_TXD  
IO  
O
I
Y7  
I
U8  
I
W8  
I
V8  
O
O
O
O
I
AA8  
U9  
W9  
AA9  
W11  
V11  
I
I
AA12  
Y12  
AA10  
V10  
U10  
AA11  
U15  
U14  
V14  
W14  
I
O
O
O
O
I
O
I
O
6.3.20 Reserved  
表6-61. Reserved Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
H16  
RSVD0  
RSVD1  
RSVD2  
RSVD3  
RSVD4  
RSVD5  
RSVD6  
RSVD7  
RSVD8  
N/A  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
Reserved, must be left unconnected  
N/A  
D21  
N/A  
G13  
F17  
N/A  
N/A  
W15  
V16  
N/A  
N/A  
K2  
N/A  
K1  
N/A  
F12  
6.3.21 SERDES  
6.3.21.1 MAIN Domain  
表6-62. SERDES0 Signal Descriptions  
SIGNAL NAME [1] ((2)  
PCIE0_CLKREQn  
)
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D16  
IO  
A
PCIE Clock Request Signal  
SERDES0_REXT (1)  
External SerDes PHY Calibration Resistor  
SerDes PHY Reference Clock Input/Output (negative)  
SerDes PHY Reference Clock Input/Output (positive)  
SerDes PHY Differential Receive Data (negative)  
T13  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
IO  
IO  
I
W16  
W17  
Y15  
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表6-62. SERDES0 Signal Descriptions (continued)  
SIGNAL NAME [1] ((2)  
SERDES0_RX0_P  
)
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Y16  
I
SerDes PHY Differential Receive Data (positive)  
SerDes PHY Differential Transmit Data (negative)  
SerDes PHY Differential Transmit Data (positive)  
SERDES0_TX0_N  
SERDES0_TX0_P  
O
O
AA16  
AA17  
(1) An external 3.01 kΩ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
(2) The functionality of these pins is controlled by SERDES0_LN0_CTRL_LANE_FUNC_SEL.  
6.3.22 System and Miscellaneous  
6.3.22.1 Boot Mode Configuration  
6.3.22.1.1 MAIN Domain  
表6-63. Sysboot Signal Descriptions  
SIGNAL NAME [1]  
BOOTMODE00  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T20  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode pin 0  
Bootmode pin 1  
Bootmode pin 2  
Bootmode pin 3  
Bootmode pin 4  
Bootmode pin 5  
Bootmode pin 6  
Bootmode pin 7  
Bootmode pin 8  
Bootmode pin 9  
Bootmode pin 10  
Bootmode pin 11  
Bootmode pin 12  
Bootmode pin 13  
Bootmode pin 14  
Bootmode pin 15  
BOOTMODE01  
BOOTMODE02  
BOOTMODE03  
BOOTMODE04  
BOOTMODE05  
BOOTMODE06  
BOOTMODE07  
BOOTMODE08  
BOOTMODE09  
BOOTMODE10  
BOOTMODE11  
BOOTMODE12  
BOOTMODE13  
BOOTMODE14  
BOOTMODE15  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
Y21  
Y20  
6.3.22.2 Clock  
6.3.22.2.1 MCU Domain  
表6-64. MCU Clock Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C21  
MCU_OSC0_XI  
MCU_OSC0_XO  
I
High frequency oscillator input  
High frequency oscillator output  
O
B20  
6.3.22.3 System  
6.3.22.3.1 MAIN Domain  
表6-65. System Signal Descriptions  
SIGNAL NAME [1]  
CLKOUT0  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
RMII Clock Output (50 MHz). This pin is used for clock  
source to the external PHY and must be routed back to  
the RMII_REF_CLK pin for proper device operation.  
O
I
A19, U13  
C19  
EXTINTn  
External Interrupt  
External clock input to Main Domain, routed to Timer  
clock muxes as one of the selectable input clock  
sources for Timer/WDT modules, or as reference clock  
to MAIN_PLL2 (PER1 PLL)  
EXT_REFCLK1  
I
A19  
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表6-65. System Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
GPMC functional clock output selected through a mux  
logic  
GPMC0_FCLK_MUX  
OBSCLK0  
O
R17  
Observation clock output for test and debug purposes  
only  
O
O
O
I
D17  
E17  
F16  
E18  
PORz_OUT  
Main Domain POR status output  
RESETSTATz  
RESET_REQz  
Main Domain warm reset status output  
Main Domain external warm reset request input  
SYSCLK0 output from Main PLL controller (divided by  
6) for test and debug purposes only  
SYSCLKOUT0  
O
C17  
6.3.22.3.2 MCU Domain  
表6-66. MCU System Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
MCU_EXT_REFCLK0  
MCU_OBSCLK0  
I
External system clock input  
B7  
Observation clock output for test and debug purposes  
only  
O
I
C6, E10  
B21  
MCU_PORz  
MCU Domain cold reset  
MCU_RESETSTATz  
MCU_RESETz  
O
I
MCU Domain warm reset status output  
MCU Domain warm reset  
B13  
B12  
MCU_SAFETY_ERRORn  
IO  
Error signal output from MCU Domain ESM  
A20  
MCU Domain system clock output for test and debug  
purposes only  
MCU_SYSCLKOUT0  
O
C6  
6.3.22.4 VMON  
表6-67. VMON Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
K16  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
A
A
A
A
Voltage monitor input for 1.8 V MCU power supply  
Voltage monitor input for 1.8 V SoC power supply  
Voltage monitor input for 3.3 V MCU power supply  
Voltage monitor input for 3.3 V SoC power supply  
E12  
F13  
F14  
Voltage monitor input, fixed 0.45 V (+/-3%) threshold.  
Use with external precision voltage divider to monitor a  
higher voltage rail such as the PMIC input supply.  
VMON_VSYS  
A
K10  
6.3.23 TIMER  
6.3.23.1 MAIN Domain  
表6-68. TIMER Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
C18, K18  
B19, K19  
A17, L21  
B17, K21  
C17, L20  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO0  
IO  
IO  
IO  
IO  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO1  
TIMER_IO2  
TIMER_IO3  
TIMER_IO4  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
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表6-68. TIMER Signal Descriptions (continued)  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D17, J19  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO5  
TIMER_IO6  
TIMER_IO7  
TIMER_IO8  
TIMER_IO9  
TIMER_IO10  
TIMER_IO11  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
B16, D19, T1  
A16, C20, U7  
P19, V7  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
R21, W7  
Timer Inputs and Outputs (not tied to single timer  
instance)  
C13, U13  
D14, U1  
Timer Inputs and Outputs (not tied to single timer  
instance)  
6.3.23.2 MCU Domain  
表6-69. MCU_TIMER Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
Timer Inputs and Outputs (not tied to single timer  
instance)  
MCU_TIMER_IO0  
IO  
IO  
IO  
IO  
D8  
E8  
B8  
B9  
Timer Inputs and Outputs (not tied to single timer  
instance)  
MCU_TIMER_IO1  
MCU_TIMER_IO2  
MCU_TIMER_IO3  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
6.3.24 UART  
6.3.24.1 MAIN Domain  
表6-70. UART0 Signal Descriptions  
SIGNAL NAME [1]  
UART0_CTSn  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
B16  
I
I
UART Clear to Send (active low)  
UART Data Carrier Detect (active low)  
UART Data Set Ready (active low)  
UART Data Terminal Ready (active low)  
UART Ring Indicator  
UART0_DCDn  
UART0_DSRn  
UART0_DTRn  
C17  
I
D17  
O
I
A17  
UART0_RIn  
B17  
UART0_RTSn  
O
I
UART Request to Send (active low)  
UART Receive Data  
A16  
UART0_RXD  
D15  
UART0_TXD  
O
UART Transmit Data  
C16  
表6-71. UART1 Signal Descriptions  
SIGNAL NAME [1]  
UART1_CTSn  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D16  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
UART1_RTSn  
O
I
E16  
UART1_RXD  
E15  
UART1_TXD  
O
UART Transmit Data  
E14  
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表6-72. UART2 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
UART Clear to Send (active low)  
UART Request to Send (active low)  
ALV PIN [4]  
L20, V19, Y1  
J19, T18, U2  
UART2_CTSn  
UART2_RTSn  
I
O
B16, K18, T20,  
V1, W6  
UART2_RXD  
UART2_TXD  
UART Receive Data  
UART Transmit Data  
I
A16, K19, R4,  
U21  
O
表6-73. UART3 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
D19, T17, V2  
C20, R3, U19  
UART3_CTSn  
UART3_RTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
O
AA5, D16, L21,  
U20, W1  
UART3_RXD  
UART3_TXD  
UART Receive Data  
UART Transmit Data  
I
AA2, E16, K21,  
U18  
O
表6-74. UART4 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
R16, R5, T3, V1  
R1, R17, T2, W1  
UART4_CTSn  
UART4_RTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
O
A17, L20, V20,  
W4, Y3  
UART4_RXD  
UART4_TXD  
UART Receive Data  
UART Transmit Data  
I
B17, J19, T1,  
V21, W5, Y4  
O
表6-75. UART5 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
W20, Y13, Y2  
T21, V12, V3  
UART5_CTSn  
UART5_RTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
O
C17, D19, P16,  
T6, Y5  
UART5_RXD  
UART5_TXD  
UART Receive Data  
UART Transmit Data  
I
C20, D17, R18,  
W2  
O
表6-76. UART6 Signal Descriptions  
SIGNAL NAME [1]  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
T4, W21  
UART6_CTSn  
UART6_RTSn  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
O
P17, P4  
C13, U6, V6,  
Y21  
UART6_RXD  
UART6_TXD  
UART Receive Data  
UART Transmit Data  
I
O
D14, W3, Y20  
6.3.24.2 MCU Domain  
表6-77. MCU_UART0 Signal Descriptions  
SIGNAL NAME [1]  
MCU_UART0_CTSn  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
I
O
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
D8  
E8  
A9  
MCU_UART0_RTSn  
MCU_UART0_RXD  
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表6-77. MCU_UART0 Signal Descriptions (continued)  
SIGNAL NAME [1]  
MCU_UART0_TXD  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
O
UART Transmit Data  
A8  
表6-78. MCU_UART1 Signal Descriptions  
SIGNAL NAME [1]  
MCU_UART1_CTSn  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
I
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
B8  
B9  
C9  
D9  
MCU_UART1_RTSn  
MCU_UART1_RXD  
MCU_UART1_TXD  
O
I
O
UART Transmit Data  
6.3.25 USB  
6.3.25.1 MAIN Domain  
表6-79. USB0 Signal Descriptions  
SIGNAL NAME [1]  
USB0_DM  
PIN TYPE [2]  
DESCRIPTION [3]  
ALV PIN [4]  
AA20  
AA19  
E19  
IO  
IO  
O
A
USB 2.0 Differential Data (negative)  
USB 2.0 Differential Data (positive)  
USB VBUS control output (active high)  
USB 2.0 Dual-Role Device Role Select  
Pin to connect to calibration resistor  
USB Level-shifted VBUS Input  
USB0_DP  
USB0_DRVVBUS  
USB0_ID  
U16  
USB0_RCALIB (1)  
USB0_VBUS (2)  
A
U17  
A
T14  
(1) An external 499 Ω±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is  
7.2mW. No external voltage should be applied to this pin.  
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.2.3, USB VBUS  
Design Guidelines.  
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6.4 Pin Connectivity Requirements  
This section describes connectivity requirements for package balls that have specific connectivity requirements  
and unused package balls.  
备注  
All power balls must be supplied with the voltages specified in the Recommended Operating  
Conditions section, unless otherwise specified in Signal Descriptions.  
备注  
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be  
connected to these device ball numbers.  
表6-80. Connectivity Requirements  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
Each of these balls must be connected to VSS through separate  
external pull resistors to ensure these balls are held to a valid logic  
low level if a PCB signal trace is connected and not actively driven  
by an attached device. The internal pull-down can be used to hold a  
valid logic low level if no PCB signal trace is connected to the ball.  
A20  
D11  
MCU_SAFETY_ERRORn  
TRSTn  
D10  
E10  
B12  
E18  
B11  
C11  
C12  
EMU0  
EMU1  
MCU_RESETz  
RESET_REQz  
TCK  
Each of these balls must be connected to the corresponding power  
supply(1) through separate external pull resistors to ensure these  
balls are held to a valid logic high level if a PCB signal trace is  
connected and not actively driven by an attached device. The  
internal pull-up can be used to hold a valid logic high level if no PCB  
signal trace is connected to the ball.  
TDI  
TMS  
A18  
B18  
E9  
I2C0_SCL  
I2C0_SDA  
MCU_I2C0_SCL  
MCU_I2C0_SDA  
Each of these balls must be connected to the corresponding power  
supply(1) through separate external pull resistors to ensure these  
balls are held to a valid logic high level.  
A10  
T20  
U21  
T18  
U20  
U18  
U19  
V20  
V21  
V19  
T17  
R16  
W20  
W21  
V18  
Y21  
Y20  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
Each of these balls must be connected to the corresponding power  
supply(1) or VSS through separate external pull resistors to ensure  
these balls are held to a valid logic high or low level as appropriate to  
select the desired device boot mode.  
J13  
G20  
F20  
E21,  
D20  
G21  
F21  
F19  
E20  
J15  
J16  
VDDA_ADC  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
ADC0_REFP  
ADC0_REFN  
If the entire ADC0 is not used, each of these balls must be  
connected directly to VSS.  
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表6-80. Connectivity Requirements (continued)  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
G20  
F20  
E21,  
D20  
G21  
F21  
F19  
E20  
ADC0_AIN0  
ADC0_AIN1  
ADC0_AIN2  
ADC0_AIN3  
ADC0_AIN4  
ADC0_AIN5  
ADC0_AIN6  
ADC0_AIN7  
Any unused ADC0_AIN[7:0] ball must be pulled to VSS through a  
resistor or connected directly to VSS when VDDA_ADC is connected  
to a power source.  
F7  
G6  
H7  
J6,  
K7  
L6  
J8  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR_C  
If DDRSS0 is not used, each of these balls must be connected  
directly to VSS.  
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表6-80. Connectivity Requirements (continued)  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
H2  
H1  
J5  
DDR0_ACT_n  
DDR0_ALERT_n  
DDR0_CAS_n  
DDR0_PAR  
DDR0_RAS_n  
DDR0_WE_n  
DDR0_A0  
DDR0_A1  
DDR0_A2  
DDR0_A3  
DDR0_A4  
K5  
F6  
H4  
D2  
C5  
E2  
D4  
D3  
F2  
J2  
DDR0_A5  
DDR0_A6  
L5  
DDR0_A7  
J3  
DDR0_A8  
J4  
DDR0_A9  
K3  
J1  
DDR0_A10  
DDR0_A11  
M5  
K4  
G4  
G5  
G2  
H3  
H5  
F1  
E1  
F4  
F3  
E3  
E4  
B2  
M2  
A3  
A2  
B5  
A4  
B3  
C4  
C2  
B4  
N5  
L4  
DDR0_A12  
DDR0_A13  
DDR0_BA0  
DDR0_BA1  
DDR0_BG0  
DDR0_BG1  
DDR0_CAL0  
DDR0_CK0  
DDR0_CK0_n  
DDR0_CKE0  
DDR0_CKE1  
DDR0_CS0_n  
DDR0_CS1_n  
DDR0_DM0  
DDR0_DM1  
DDR0_DQ0  
DDR0_DQ1  
DDR0_DQ2  
DDR0_DQ3  
DDR0_DQ4  
DDR0_DQ5  
DDR0_DQ6  
DDR0_DQ7  
DDR0_DQ8  
DDR0_DQ9  
DDR0_DQ10  
DDR0_DQ11  
DDR0_DQ12  
DDR0_DQ13  
DDR0_DQ14  
DDR0_DQ15  
DDR0_DQS0  
DDR0_DQS0_n  
DDR0_DQS1  
DDR0_DQS1_n  
DDR0_ODT0  
DDR0_ODT1  
DDR0_RESET0_n  
If DDRSS0 is not used, leave unconnected.  
Note: The DDR0 pins in this list can only be left unconnected when  
VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0  
pins must be connected as defined in the AM64x\AM243x DDR  
Board Design and Layout Guidelines, when VDDS_DDR and  
VDDS_DDR_C are connected to a power source.  
L2  
M3  
N4  
N3  
M4  
N2  
C1  
B1  
N1  
M1  
E5  
F5  
D5  
K13  
H14  
VDD_MMC0  
VDD_DLL_MMC0  
If MMC0 is not used, each of these balls must be connected to the  
same power source as VDD_CORE.  
If MMC0 is not used, each of these balls must be connected to any  
1.8-V power source that does not violate device power supply  
sequencing requirements.  
K14  
VDDS_MMC0  
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表6-80. Connectivity Requirements (continued)  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
F18  
G18  
J21  
G19  
K20  
J20  
J18  
J17  
H17  
H19  
H18  
G17  
MMC0_CALPAD  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
If MMC0 is not used, each of these balls must be left unconnected.  
H15  
K15  
VDDA_3P3_SDIO  
CAP_VDDSHV_MMC1  
If SDIO_LDO is not used to power VDDSHV5, each of these balls  
must be connected directly to VSS.  
If SERDES0 is not used and the device boundary scan function is  
required, each of these balls must be connected to valid power  
sources.  
P12  
P13  
P11  
R14  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_1P8_SERDES0  
If SERDES0 is not used and the device boundary scan function is  
not required, each of these balls can alternatively be connected  
directly to VSS.  
If SERDES0 is not used, leave unconnected.  
T13  
SERDES0_REXT  
Note: The SERDES0_REXT pin can only be left unconnected when  
VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and  
VDDA_1P8_SERDES0 are connected to VSS. The  
SERDES0_REXT pin must be connected to VSS through the  
appropriate external resistor when VDDA_0P85_SERDES0,  
VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are  
connected to power sources.  
W16  
W17  
Y15  
Y16  
AA16  
AA17  
SERDES0_REFCLK0N  
SERDES0_REFCLK0P  
SERDES0_RX0_N  
SERDES0_RX0_P  
SERDES0_TX0_N  
SERDES0_TX0_P  
T12  
R15  
R13  
VDDA_0P85_USB0  
VDDA_1P8_USB0  
VDDA_3P3_USB0  
If USB0 is not used, each of these balls must be connected directly  
to VSS.  
If USB0 is not used, leave unconnected.  
AA20  
AA19  
U16  
U17  
T14  
USB0_DM  
USB0_DP  
USB0_ID  
USB0_RCALIB  
USB0_VBUS  
Note: The USB0_RCALIB pin can only be left unconnected when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are  
connected to VSS. The USB0_RCALIB pin must be connected to  
VSS through the appropriate external resistor when  
VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are  
connected to power sources.  
If VMON_VSYS is not used, this ball must be connected directly to  
VSS.  
K10  
VMON_VSYS  
K16  
E12  
F13  
F14  
VMON_1P8_MCU  
VMON_1P8_SOC  
VMON_3P3_MCU  
VMON_3P3_SOC  
If VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, and  
VMON_3P3_SOC are not used to monitor the MCU and SOC power  
rails, these balls must still be connected to their respective 1.8-V and  
3.3-V power rails.  
(1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table.  
备注  
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for  
some operating conditions. This can be the case when connected to components with leakage to the  
opposite logic level, or when external noise sources couple to signal traces attached to balls which are  
only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are  
recommended to hold a valid logic level on balls with external connections.  
If balls are allowed to float between valid logic levels, the input buffer can enter a high-current state  
which can damage the IO cell.  
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7 Specifications  
备注  
All specifications listed are preliminary and may change during device characterization.  
7.1 Absolute Maximum Ratings  
over operating junction temperature range (unless otherwise noted)(1)(2)  
PARAMETER  
MIN  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
MAX UNIT  
VDD_CORE  
Core supply  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.05  
1.57  
1.57  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
1.98  
3.63  
3.63  
3.63  
3.63  
3.63  
3.63  
3.63  
3.63  
3.63  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDR_CORE  
VDD_MMC0  
RAM supply  
MMC0 PHY core supply  
MMC0 PLL analog supply  
SERDES0 0.85-V analog supply  
SERDES0 clock 0.85-V analog supply  
USB0 0.85-V analog supply  
DDR PHY IO supply  
VDD_DLL_MMC0  
VDDA_0P85_SERDES0  
VDDA_0P85_SERDES0_C  
VDDA_0P85_USB0  
VDDS_DDR  
VDDS_DDR_C  
VDDS_MMC0  
VDDS_OSC  
DDR clock IO supply  
MMC0 PHY IO supply  
MCU_OSC0 supply  
VDDA_MCU  
POR and MCU PLL analog supply  
ADC0 analog supply  
VDDA_ADC0  
VDDA_PLL0  
Main, PER1, and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
SERDES0 1.8-V analog supply  
USB0 1.8-V analog supply  
TEMP0 analog supply  
VDDA_PLL1  
VDDA_PLL2  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_TEMP0  
VDDA_TEMP1  
VPP  
TEMP1 analog supply  
eFuse ROM programming supply  
IO supply for IO MCU  
VDDSHV_MCU  
VDDSHV0  
IO supply for IO group 0  
IO supply for IO group 1  
IO supply for IO group 2  
IO supply for IO group 3  
IO supply for IO group 4  
IO supply for IO group 5  
USB0 3.3-V analog supply  
SDIO 3.3-V analog supply  
VDDSHV1  
VDDSHV2  
VDDSHV3  
VDDSHV4  
VDDSHV5  
VDDA_3P3_USB0  
VDDA_3P3_SDIO  
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MAX UNIT  
over operating junction temperature range (unless otherwise noted)(1)(2)  
PARAMETER  
MIN  
MCU_PORz  
-0.3  
3.63  
V
MCU_I2C0_SCL, MCU_I2C0_SDA,  
I2C0_SCL, I2C0_SDA, and EXTINTn  
When operating at 1.8V  
-0.3  
-0.3  
1.98(3)  
V
MCU_I2C0_SCL, MCU_I2C0_SDA,  
I2C0_SCL, I2C0_SDA, and EXTINTn  
When operating at 3.3V  
3.63(3)  
Steady-state max voltage at all fail-safe IO pins  
VMON_1P8_MCU, and  
VMON_1P8_SOC  
-0.3  
-0.3  
1.98  
3.63  
V
V
VMON_3P3_MCU, and  
VMON_3P3_SOC  
VMON_VSYS(4)  
USB0_VBUS(6)  
USB0_ID(7)  
-0.3  
-0.3  
-0.3  
1.98  
3.6  
V
V
3.6  
Steady-state max voltage at all other IO pins(5)  
IO supply  
voltage + 0.3  
All other IO pins  
-0.3  
V
V
20% of IO supply voltage for up to 20%  
of the signal period (see 图7-1, IO  
Transient Voltage Ranges)  
Transient overshoot and undershoot at IO pin  
Latch-up performance(9)  
0.2 × VDD(8)  
I-Test  
-100  
-55  
+100  
1.5 x VDD(8)  
+150  
mA  
V
Over-Voltage (OV) Test  
TSTG  
Storage temperature  
°C  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If  
used outside the 节7.4, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully  
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.  
(2) All voltage values are with respect to VSS, unless otherwise noted.  
(3) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also  
defined by the maximum VIH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where  
the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.  
(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see 节9.2.4, System Power Supply  
Monitor Design Guidelines.  
(5) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For  
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be  
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources  
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage  
range, including power supply ramp-up and ramp-down sequences.  
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.2.3, USB Design  
Guidelines.  
(7) The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring  
voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB  
host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source.  
(8) VDD is the voltage on the corresponding power-supply pin(s) for the IO.  
(9) For current pulse injection (I-Test):  
•
Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times  
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.  
For over-voltage performance (Over-Voltage (OV) Test):  
Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.  
•
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply  
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO  
power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA,  
I2C0_SCL, I2C0_SDA,  
EXTINTn, VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, VMON_3P3_SOC, VMON_VSYS, and  
MCU_PORz are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to  
them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in 节7.1.  
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Overshoot = 20% of nominal  
IO supply voltage  
Tovershoot  
Tperiod  
Tundershoot  
Undershoot = 20% of nominal  
IO supply voltage  
A. Tovershoot + Tundershoot < 20% of Tperiod  
图7-1. IO Transient Voltage Ranges  
7.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)  
Electrostatic discharge  
V(ESD)  
(ESD)  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Power-On Hours (POH)  
EXTENDED JUNCTION TEMPERATURE RANGE(1) (2) (3)  
JUNCTION TEMP (TJ)  
LIFETIME (POH)  
-40°C to 105°C  
100000  
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard  
terms and conditions for TI semiconductor products.  
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted  
temperatures.  
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.  
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7.4 Recommended Operating Conditions  
over operating junction temperature range (unless otherwise noted)  
SUPPLY NAME  
DESCRIPTION  
MIN(1)  
0.715  
0.81  
0.81  
0.81  
0.81  
0.81  
0.81  
0.81  
1.06  
1.14  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
3.135  
3.135  
3.135  
3.135  
0
NOM MAX(1) UNIT  
0.75-V operation  
0.85-V operation  
0.75  
0.85  
0.85  
0.85  
0.85  
0.85  
0.85  
0.85  
1.1  
0.79  
0.895  
0.895  
0.895  
0.895  
0.895  
0.895  
0.895  
1.17  
1.26  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
3.465  
3.465  
3.465  
3.465  
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE  
Core supply  
VDDR_CORE  
RAM supply  
VDD_MMC0(2)  
MMC0 PHY core supply  
MMC0 PLL analog supply  
VDD_DLL_MMC0(2)  
VDDA_0P85_SERDES0  
SERDES0 0.85 V analog supply  
VDDA_0P85_SERDES0_C SERDES0 clock 0.85 V analog supply  
VDDA_0P85_USB0  
USB0 0.85 V analog supply  
VDDS_DDR(3)  
DDR PHY IO supply  
DDR clock IO supply  
1.1-V operation  
1.2-V operation  
VDDS_DDR_C(3)  
1.2  
VDDS_MMC0  
VDDS_OSC  
MMC0 PHY IO supply  
1.8  
MCU_OSC0 supply  
1.8  
VDDA_MCU  
POR and MCU PLL analog supply  
ADC0 analog supply  
1.8  
VDDA_ADC0  
1.8  
VDDA_PLL0  
Main, PER and R5F PLL analog supply  
ARM and DDR PLL analog supply  
PER0 PLL analog supply  
1.8  
VDDA_PLL1  
1.8  
VDDA_PLL2  
1.8  
VDDA_1P8_SERDES0  
VDDA_1P8_USB0  
VDDA_TEMP0  
VDDA_TEMP1  
VPP  
SERDES0 1.8 V analog supply  
USB0 1.8 V analog supply  
1.8  
1.8  
TEMP0 analog supply  
1.8  
TEMP1 analog supply  
1.8  
eFuse ROM programming supply  
Voltage monitor for 1.8 V MCU power supply  
Voltage monitor for 1.8 V SoC power supply  
USB0 3.3 V analog supply  
1.8  
VMON_1P8_MCU  
VMON_1P8_SOC  
VDDA_3P3_USB0  
VDDA_3P3_SDIO  
VMON_3P3_MCU  
VMON_3P3_SOC  
VMON_VSYS  
USB0_VBUS  
1.8  
1.8  
3.3  
SDIO 3.3 V analog supply  
3.3  
Voltage monitor for 3.3 V MCU power supply  
Voltage monitor for 3.3 V SoC power supply  
Voltage monitor pin  
3.3  
3.3  
see(4)  
see(5)  
see(6)  
1.8  
USB Level-shifted VBUS Input  
USB0 analog I/O for RID detection  
0
3.465  
USB0_ID  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
1.8-V operation  
3.3-V operation  
1.71  
3.135  
1.71  
1.89  
3.465  
1.89  
VDDSHV_MCU  
VDDSHV0  
VDDSHV1  
VDDSHV2  
VDDSHV3  
VDDSHV4  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
Dual-voltage IO supply  
3.3  
1.8  
3.135  
1.71  
3.3  
3.465  
1.89  
1.8  
3.135  
1.71  
3.3  
3.465  
1.89  
1.8  
3.135  
1.71  
3.3  
3.465  
1.89  
1.8  
3.135  
1.71  
3.3  
3.465  
1.89  
1.8  
3.135  
3.3  
3.465  
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SUPPLY NAME  
VDDSHV5  
TJ  
DESCRIPTION  
MIN(1)  
1.71  
NOM MAX(1) UNIT  
1.8-V operation  
3.3-V operation  
Extended  
1.8  
3.3  
1.89  
3.465  
105  
V
V
Dual-voltage IO supply  
Operating junction temperature range  
3.135  
-40  
°C  
(1) The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during  
normal device operation.  
(2) VDD_MMC0 and VDD_DLL_MMC0 must be connected to the same power source as VDD_CORE when MMC0 is not used. In this  
case, VDD_MMC0 and VDD_DLL_MMC0 may be operated at a nominal voltage of 0.75 or 0.85.  
(3) VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.  
(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see 节9.2.4, System Power Supply  
Monitor Design Guidelines.  
(5) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.2.3, USB Design  
Guidelines.  
(6) The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring  
voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB  
host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source.  
7.5 Operating Performance Points  
This section describes the operating conditions of the device. This section also contains the description of each  
Operating Performance Point (OPP) for processor clocks and device core clocks.  
表7-1 describes the maximum supported frequency per speed grade for the device.  
表7-1. Speed Grade Maximum Frequency  
MAXIMUM FREQUENCY (MHz)  
DEVICE  
SPEED  
GRADE  
A53SS  
R5FSS  
M4FSS CBASS0 ICSSG DMSC-L  
DDR4(1)  
LPDDR4(1)  
AM64x  
AM64x  
S
K
1000  
800  
800  
400  
400  
400  
250  
250  
333  
250  
250  
250  
800 (DDR-1600)  
800 (DDR-1600)  
800 (LPDDR-1600)  
800 (LPDDR-1600)  
(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.  
Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR  
frequency.  
7.6 Power Consumption Summary  
For information on the device power consumption, see the AM64x/AM243x Power Estimation Tool application  
note .  
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7.7 Electrical Characteristics  
备注  
The interfaces or signals described in 节 7.7.1 through 节 7.7.10 correspond to the interfaces or  
signals available in multiplexing mode 0 (Primary Function).  
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical  
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC  
electrical characteristics are specified for the different multiplexing modes (Functions).  
7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
1.8 V MODE  
VIL  
Input Low Voltage  
0.3 × VDD(1)  
0.3 × VDD(1)  
V
V
VILSS  
Input Low Voltage Steady State  
Input High Voltage  
VIH  
0.7 × VDD(1)  
0.7 × VDD(1)  
0.1 × VDD(1)  
1.98(2)  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
VOL  
Output Low Voltage  
0.2 × VDD(1)  
V
(3)  
IOL  
Low Level Output Current  
VOL(MAX)  
20  
mA  
18f(4)  
or  
(5)  
SRI  
Input Slew Rate  
V/s  
1.8E+6  
3.3 V MODE (6)  
VIL  
Input Low Voltage  
0.3 × VDD(1)  
0.25 × VDD(1)  
3.63(2)  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.7 × VDD(1)  
0.7 × VDD(1)  
0.05 × VDD(1)  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
mV  
VI = 3.3 V  
or  
VI = 0 V  
IIN  
Input Leakage Current.  
±10  
0.4  
µA  
VOL  
Output Low Voltage  
V
(3)  
IOL  
Low Level Output Current  
VOL(MAX)  
20  
mA  
33f(4)  
or  
(5)  
SRI  
Input Slew Rate  
8E+7  
V/s  
3.3E+6  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see  
POWER column of the Pin Attributes table.  
(2) This value also defines the Absolute Maximum Ratings value the IO.  
(3) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value. The  
value defined by this parameter should be considered the maximum current available to a system implementation which needs to  
maintain the specified VOL value for attached components.  
(4) f = toggle frequency of the input signal in Hz.  
(5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching  
Characteristics sections. Select the MIN parameter which results in the largest value.  
(6) I2C Hs-mode is not supported when operating the IO in 3.3 V mode.  
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7.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
0.3 ×  
V
VIL  
Input Low Voltage  
VDDS_OSC  
0.3 ×  
VDDS_OSC  
VILSS  
VIH  
VIHSS  
VHYS  
Input Low Voltage Steady State  
Input High Voltage  
V
V
0.7 ×  
VDDS_OSC  
0.7 ×  
VDDS_OSC  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
200  
mV  
VI = 1.8 V  
or  
VI = 0 V  
IIN  
Input Leakage Current.  
Input Slew Rate  
±10  
µA  
18f(1)  
or  
(2)  
SRI  
V/s  
1.8E+6  
(1) f = toggle frequency of the input signal in Hz.  
(2) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching  
Characteristics sections. Select the MIN parameter which results in the largest value.  
7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
0.35 ×  
V
VIL  
Input Low Voltage  
VDDS_OSC  
0.65 ×  
VDDS_OSC  
VIH  
Input High Voltage  
V
VHYS  
Input Hysteresis Voltage  
49  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0.0 V  
7.7.4 eMMCPHY Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
0.35 ×  
V
VIL  
Input Low Voltage  
VDDS_MMC0  
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.20  
V
V
0.65 ×  
VDDS_MMC0  
VIHSS  
IIN  
Input High Voltage Steady State  
Input Leakage Current.  
Pull-up Resistor  
1.4  
V
VI = 1.8 V or 0 V  
±10  
25  
µA  
kΩ  
kΩ  
V
RPU  
RPD  
VOL  
15  
15  
20  
20  
Pull-down Resistor  
25  
Output Low Voltage  
IOL = 2 mA  
IOH = -2 mA  
0.30  
VDDS_MMC0  
- 0.30  
VOH  
SRI  
Output High Voltage  
Input Slew Rate  
V
5E+8  
V/s  
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MAX UNIT  
7.7.5 SDIO Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
1.8 V MODE  
VIL  
Input Low Voltage  
0.58  
0.58  
V
V
VILSS  
Input Low Voltage Steady State  
Input High Voltage  
VIH  
1.27  
1.7  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
RPU  
RPD  
VOL  
Pull-up Resistor  
40  
40  
50  
50  
60  
60  
kΩ  
kΩ  
V
Pull-down Resistor  
Output Low Voltage  
0.45  
VDDSHV5 -  
0.45  
VOH  
Output High Voltage  
V
(1)  
IOL  
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MIN)  
4
4
mA  
mA  
(1)  
IOH  
18f(2)  
or  
(3)  
SRI  
Input Slew Rate  
V/s  
1.8E+6  
3.3 V MODE  
0.25 ×  
VDDSHV5  
VIL  
Input Low Voltage  
V
V
V
0.15 ×  
VDDSHV5  
VILSS  
VIH  
VIHSS  
VHYS  
Input Low Voltage Steady State  
Input High Voltage  
0.625 ×  
VDDSHV5  
0.625 ×  
VDDSHV5  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
VI = 3.3 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0 V  
RPU  
RPD  
Pull-up Resistor  
40  
40  
50  
50  
60  
60  
kΩ  
kΩ  
Pull-down Resistor  
0.125 ×  
VDDSHV5  
VOL  
VOH  
Output Low Voltage  
Output High Voltage  
V
V
0.75 ×  
VDDSHV5  
(1)  
IOL  
Low Level Output Current  
High Level Output Current  
VOL(MAX)  
VOH(MIN)  
6
mA  
mA  
(1)  
IOH  
10  
33f(2)  
or  
(3)  
SRI  
Input Slew Rate  
V/s  
3.3E+6  
(1) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able  
to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current  
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.  
(2) f = toggle frequency of the input signal in Hz.  
(3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching  
Characteristics sections. Select the MIN parameter which results in the largest value.  
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7.7.6 LVCMOS Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
1.8-V MODE  
VIL  
Input Low Voltage  
0.35 × VDD(1)  
0.3 × VDD(1)  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
0.65 × VDD(1)  
0.85 × VDD(1)  
150  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
mV  
VI = 1.8 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0.0 V  
RPU  
RPD  
VOL  
VOH  
Pull-up Resistor  
15  
15  
22  
22  
30  
30  
kΩ  
kΩ  
V
Pull-down Resistor  
Output Low Voltage  
Output High Voltage  
Low Level Output Current  
High Level Output Current  
0.45  
VDD(1) - 0.45  
V
(2)  
IOL  
VOL(MAX)  
VOH(MIN)  
3
3
mA  
mA  
(2)  
IOH  
18f(3)  
or  
(4)  
SRI  
Input Slew Rate  
V/s  
1.8E+6  
3.3-V MODE  
VIL  
Input Low Voltage  
0.8  
0.6  
V
V
VILSS  
VIH  
Input Low Voltage Steady State  
Input High Voltage  
2.0  
2.0  
V
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
150  
mV  
VI = 3.3 V  
or  
IIN  
Input Leakage Current.  
±10  
µA  
VI = 0.0 V  
RPD  
RPD  
VOL  
VOH  
Pull-down Resistor  
15  
15  
22  
22  
30  
30  
kΩ  
kΩ  
V
Pull-down Resistor  
Output Low Voltage  
Output High Voltage  
Low Level Output Current  
High Level Output Current  
0.4  
2.4  
5
V
(2)  
IOL  
VOL(MAX)  
VOH(MIN)  
mA  
mA  
(2)  
IOH  
9
33f(3)  
or  
(4)  
SRI  
Input Slew Rate  
V/s  
3.3E+6  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see  
POWER column of the Pin Attributes table.  
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able  
to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current  
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.  
(3) f = toggle frequency of the input signal in Hz.  
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching  
Characteristics sections. Select the MIN parameter which results in the largest value.  
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7.7.7 ADC12B Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Positive Reference Voltage,  
ADC0_VREFP  
(1)  
(1)  
VADC0_VREFP  
VADC0_VREFN  
1.71  
1.89  
V
Negative Reference Voltage,  
ADC0_VREFN  
VSS  
V
V
Analog Input Voltage,  
ADC_AIN[7:0], Full-scale  
VADC_AIN[7:0]  
VSS  
VDDA_ADC0  
DNL  
INL  
Differential Non-Linearity  
Integral Non-Linearity  
Gain Error  
> -1  
-2  
+1  
+2  
LSB  
LSB  
LSB  
LSB  
LSBGAIN-ERROR  
±10  
±5  
LSBOFFSET-ERROR Offset Error  
Input Signal:  
SNR  
Signal-to-Noise Ratio  
200 kHz sine wave at  
-0.5 dB Full Scale  
70  
dB  
Input Signal:  
THD  
Total Harmonic Distortion  
200 kHz sine wave at  
-0.5 dB Full Scale  
-75  
dB  
Analog Input Impedance,  
ADC0_AIN[7:0]  
(2)  
ZADC_AIN[0:7]  
Ω
IIN  
CSMPL  
Input Leakage  
±10  
5.5  
μA  
Sampling Capacitance  
pF  
Sampling Dynamics  
FSMPL_CLK  
ADC0 SMPL_CLK Frequency  
Conversion Time  
60  
13  
MHz  
ADC0  
SMPL_CLK  
Cycles  
tC  
ADC0  
tACQ  
Acquisition Time  
Sampling Rate  
2
257 SMPL_CLK  
Cycles  
ADC0 SMPL_CLK  
= 60 MHz  
TR  
4
MSPS  
General Purpose Input Mode (3)  
0.35 ×  
VDDA_ADC0  
VIL  
VILSS  
VIH  
Input Low Voltage  
V
V
V
0.35 ×  
VDDA_ADC0  
Input Low Voltage Steady State  
Input High Voltage  
0.65 ×  
VDDA_ADC0  
0.65 ×  
VDDA_ADC0  
VIHSS  
VHYS  
Input High Voltage Steady State  
Input Hysteresis Voltage  
V
200  
mV  
ADC0_AIN[7:0] =  
VDDA_ADC0  
or  
II  
Input Leakage Current  
10  
μA  
ADC0_AIN[7:0] = VSS  
(1) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails.  
ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is  
connected to a power source capable of providing at least 4 mA of current. ADC0_REFP can be connected to the same power source  
as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency  
decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array  
on the back side of the PCB.  
(2) The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency.  
The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and  
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acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the  
internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than  
14 bits of accuracy.  
(3) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate  
as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1).  
7.7.8 USB2PHY Electrical Characteristics  
备注  
USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000  
including ECNs and Errata as applicable.  
7.7.9 SerDes PHY Electrical Characteristics  
备注  
The PCIe interface is compliant with the electrical parameters specified in PCI Express® Base  
Specification Revision 4.0, February 19, 2014.  
备注  
USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative  
Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26,  
2013.  
7.7.10 DDR Electrical Characteristics  
备注  
The DDR interface is compatible with DDR4 and LPDDR4 devices  
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7.8 VPP Specifications for One-Time Programmable (OTP) eFuses  
This section specifies the operating conditions required for programming the OTP eFuses..  
7.8.1 Recommended Operating Conditions for OTP eFuse Programming  
over operating junction temperature range (unless otherwise noted)  
PARAMETER  
DESCRIPTION  
MIN  
NOM  
MAX  
UNIT  
VDD_CORE  
Supply voltage range for the core domain during OTP  
operation; OPP NOM (BOOT)  
See Recommended Operating  
V
Conditions  
VPP  
Supply voltage range for the eFuse ROM domain during  
normal operation without hardware support to program eFuse  
ROM  
NC(1)  
V
V
V
Supply voltage range for the eFuse ROM domain during  
normal operation with hardware support to program eFuse  
ROM  
0
Supply voltage range for the eFuse ROM domain during OTP  
programming(2)  
1.71  
1.8  
25  
1.89  
I(VPP)  
SR(VPP)  
TJ  
VPP current  
400  
6E+4  
85  
mA  
V/s  
°C  
VPP Slew Rate  
Operating junction temperature range while programming  
eFuse ROM.  
0
(1) NC stands for No Connect.  
(2) Supply voltage range includes DC errors and peak-to-peak noise.  
7.8.2 Hardware Requirements  
The following hardware requirements must be met when programming keys in the OTP eFuses:  
• The VPP power supply must be disabled when not programming OTP registers.  
• The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see  
节7.10.2, Power Supply Sequencing).  
7.8.3 Programming Sequence  
Programming sequence for OTP eFuses:  
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during  
power up and normal operation.  
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP  
software package).  
• Apply the voltage on the VPP terminal according to the specification in 节7.8.1.  
• Run the software that programs the OTP registers.  
• After validating the content of the OTP registers, remove the voltage from the VPP terminal.  
7.8.4 Impact to Your Hardware Warranty  
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that the  
e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step.  
Further the TI Device may fail to secure boot if the error code correction check fails for the Production Keys or if  
the image is not signed and optionally encrypted with the current active Production Keys. These types of  
situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices conformed  
to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY  
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.  
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7.9 Thermal Resistance Characteristics  
For operation and reliability concerns, the maximum junction temperature of the device must be equal to or less  
than the TJ value identified in Recommended Operating Conditions.  
7.9.1 Thermal Resistance Characteristics  
表7-2. Thermal Resistance Characteristics  
TI recommends performing system level thermal simulations with worst case device power consumption.  
AIR FLOW  
NO.  
PARAMETER(1)  
DESCRIPTION  
ALV Package  
°C/W(2)  
(m/s)(3)  
T1  
T2  
0.98  
3.87  
12.8  
9.2  
N/A  
N/A  
0
Junction-to-case  
Junction-to-board  
Junction-to-free air  
RΘJC  
RΘJB  
RΘJA  
T3  
T4  
1
T5  
Junction-to-moving air  
8.2  
2
RΘJA  
T6  
7.6  
3
T7  
0.53  
0.55  
0.57  
0.58  
3.74  
3.5  
0
T8  
1
Junction-to-package top  
ΨJT  
T9  
2
T10  
T11  
T12  
T13  
T14  
3
0
1
Junction-to-board  
ΨJB  
3.4  
2
3.3  
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a  
JEDEC defined 1S0P system) and is subject to change based on environment as well as application. For more information, see the  
EIA/JEDEC standards.  
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Packages  
(2) °C/W = degrees Celsius per watt.  
(3) m/s = meters per second.  
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7.10 Timing and Switching Characteristics  
备注  
The Timing Requirements and Switching Characteristics values may change following the silicon  
characterization result.  
备注  
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,  
unless specific instructions are given otherwise.  
7.10.1 Timing Parameters and Information  
The timing parameter symbols used in Timing and Switching Characteristics sections are created in accordance  
with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been  
abbreviated in 表7-3:  
表7-3. Timing Parameters Subscripts  
SYMBOL  
PARAMETER  
Cycle time (period)  
Delay time  
c
d
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
Unknown, changing, or don't care level  
Fall time  
X
F
H
High  
L
Low  
R
Rise time  
V
Valid  
IV  
AE  
FE  
LE  
Z
Invalid  
Active Edge  
First Edge  
Last Edge  
High impedance  
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7.10.2 Power Supply Requirements  
This section describes the power supply requirements to ensure proper device operation.  
备注  
All power balls must be supplied with the voltages specified in the Recommended Operating  
Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity  
Requirements.  
7.10.2.1 Power Supply Slew Rate Requirement  
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the  
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in 图 7-2, TI recommends  
having the supply ramp slew for a 1.8-V supply of more than 100 µs.  
图7-2 describes the Power Supply Slew Rate Requirement in the device.  
Supply value  
t
slew rate < 18 mV/μs  
slew > (supply value) / (18 mV/μs)  
or  
supply value × 55.6 μs/V  
SPRT740_ELCH_06  
图7-2. Power Supply Slew and Slew Rate  
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7.10.2.2 Power Supply Sequencing  
This section describes power sequence requirements using power sequence diagrams and associated notes.  
Each power sequence diagram demonstrates the sequential order expected for each device power rail. This is  
done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be associated  
with more than one waveform and the associated note will describe which waveform is applicable. Each  
waveform defines a transition region for the associated power rails and shows its sequential relationship to the  
transition regions of other power rails. The notes associated with the power sequence diagram provides further  
detail of these requirements. See the Power-up Sequence section for details on power-up requirements, and the  
Power-down Sequence section for details on power-down requirements.  
Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The  
legends shown in 图 7-3 and 图 7-4 along with their descriptions are provided to clarify what each transition  
regions represents.  
图7-3 defines a transition region with multiple power rails which may be sourced from multiple power supplies or  
a single power supply. Transitions shown within the transition region represent a use case where multiple power  
supplies are used to source power rails associated with this waveform, and these power supplies are allowed to  
ramp at different times within the region since they do not have any specific sequence requirement relative to  
each other.  
图7-3. Multiple Power Supply Transition Legend  
图 7-4 defines a transition region with one or more power rails which must be sourced from a single common  
power supply. No transitions are shown within the region to represent a single ramp within the transition region.  
图7-4. Single Common Power Supply Transition Legend  
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7.10.2.2.1 Power-Up Sequencing  
图7-5 describes the device power-up sequencing.  
VSYS  
Note 1  
Note 2  
VSYS, VMON_VSYS  
VMON_VSYS  
(3)  
(3)  
(3)  
(3)  
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3  
(3)  
,
(3)  
VDDSHV4 , VDDA_3P3_SDIO, VDDA_3P3_USB0,  
(4)  
VMON_3P3_SOC , VMON_3P3_MCU  
(4)  
(5)  
(5)  
(5)  
(5)  
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3  
(5)  
,
(5)  
VDDSHV4 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,  
(6)  
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU  
(6)  
VMON_1P8_SOC , VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0  
,
(12)  
VDDSHV5  
(7)  
VDDS_DDR , VDDS_DDR_C  
(7)  
(8)(10)  
VDD_CORE  
(9)(10)  
(10)  
, VDDR_CORE , VDDA_0P85_SERDES0_C,  
VDD_CORE  
VDDA_0P85_SERDES0, VDDA_0P85_USB0,  
VDD_DLL_MMC0, VDD_MMC0  
Hi-Z  
(11)  
VPP  
MCU_PORz  
MCU_OSC0_XI, MCU_OSC0_XO  
AM64x_ELCH_01  
图7-5. Power-Up Sequencing  
1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to  
be a pre-regulated supply that sources power management devices which source all other supplies.  
2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information,  
see 节9.2.4, System Power Supply Monitor Design Guidelines.  
3. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or 3.3V  
depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO  
supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period  
defined by this waveform.  
4. The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be  
connected to the respective 3.3V supply source.  
5. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or 3.3V  
depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO  
supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period  
defined by this waveform.  
6. The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be  
connected to the respective 1.8V supply source.  
7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp  
together.  
8. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.75V, it shall be ramped  
up prior to all 0.85V supplies as shown in this waveform.  
9. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.85V, it shall be ramped  
up with other 0.85V supplies during the 0.85V ramp period defined by this waveform.  
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10. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +  
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after  
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements  
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by  
the same source so they ramp together when VDD_CORE is operating at 0.85V.  
11. VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/  
down sequences and during normal device operation. This supply shall only be sourced while programming  
eFuse.  
12. VDDSHV5 was designed to support power-up, power-down, or dynamic voltage change without any  
dependency on other power rails. This capability is required to support UHS-I SD Cards.  
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7.10.2.2.2 Power-Down Sequencing  
图7-6 describes the device power-down sequencing.  
VSYS  
VSYS, VMON_VSYS  
VMON_VSYS  
(1)  
(1)  
(1)  
(1)  
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3  
(1)  
,
(1)  
VDDSHV4 , VDDA_3P3_SDIO, VDDA_3P3_USB0,  
VMON_3P3_SOC, VMON_3P3_MCU  
(2)  
(2)  
(2)  
(2)  
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3  
(2)  
,
(2)  
VDDSHV4 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,  
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU,  
VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0  
(6)  
VDDSHV5  
VDDS_DDR, VDDS_DDR_C  
(3)(5)  
VDD_CORE  
(4)(5)  
(5)  
, VDDR_CORE , VDDA_0P85_SERDES0_C,  
VDD_CORE  
VDDA_0P85_SERDES0, VDDA_0P85_USB0,  
VDD_DLL_MMC0, VDD_MMC0  
VPP  
Hi-Z  
MCU_PORz  
MCU_OSC0_XI, MCU_OSC0_XO  
AM64x_ELCH_02  
图7-6. Power-Down Sequencing  
1. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.  
2. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.  
3. VDD_CORE when operating at 0.75V.  
4. VDD_CORE when operating at 0.85V.  
5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +  
0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after  
VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements  
beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by  
the same source so they ramp together when VDD_CORE is operating at 0.85V.  
6. VDDSHV5 was designed to support power-up, power-down, or dynamic voltage change without any  
dependency on other power rails. This capability is required to support UHS-I SD Cards.  
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7.10.3 System Timing  
For more details about features and additional description information on the subsystem multiplexing signals,  
see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
表7-4. System Timing Conditions  
PARAMETER  
MIN  
0.5  
3
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
CL  
Input slew rate  
OUTPUT CONDITIONS  
Output load capacitance  
30  
7.10.3.1 Reset Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for reset  
related signals.  
表7-5. MCU_PORz Timing Requirements  
see 图7-7  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Hold time, MCU_PORz active (low) at Power-up  
after supplies valid (using external crystal)  
RST1  
9500000  
ns  
th(SUPPLIES_VALID - MCU_PORz)  
Hold time, MCU_PORz active (low) at Power-up  
after supplies valid and external clock stable (using  
external LVCMOS oscillator)  
RST2  
1200  
1200  
ns  
ns  
Pulse Width minimum, MCU_PORz low after  
Power-up (without removal of Power or system  
reference clock MCU_OSC0_XI/XO)  
RST3 tw(MCU_PORzL)  
图7-7. MCU_PORz Timing Requirements  
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表7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
see 图7-8  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_PORz active (low) to  
MCU_RESETSTATz active (low)  
RST4 td(MCU_PORzL-MCU_RESETSTATzL)  
RST5 td(MCU_PORzH-MCU_RESETSTATzH)  
RST6 td(MCU_PORzL-RESETSTATzL)  
RST7 td(MCU_PORzH-RESETSTATzH)  
RST8 tw(MCU_RESETSTATzL)  
0
ns  
Delay time, MCU_PORz inactive (high) to  
MCU_RESETSTATz inactive (high)  
6120*S(1)  
0
ns  
ns  
ns  
ns  
Delay time, MCU_PORz active (low) to  
RESETSTATz active (low)  
Delay time, MCU_PORz inactive (high) to  
RESETSTATz inactive (high)  
9195*S(1)  
4040*S(1)  
Pulse Width Minimum MCU_RESETSTATz low  
(SW_MCU_WARMRST)  
Pulse Width Minimum RESETSTATz low  
(SW_MCU_WARMRST, SW_MAIN_PORz, or  
SW_MAIN_WARMRST)  
RST9 tw(RESETSTATzL)  
301200  
ns  
(1) S = MCU_OSC0_XI/XO clock period  
图7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
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表7-7. MCU_RESETz Timing Requirements  
see 图7-9  
NO.  
PARAMETER  
MIN  
MAX UNIT  
(1)  
RST10 tw(MCU_RESETzL)  
Pulse Width minimum, MCU_RESETz active (low)  
1200  
ns  
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
表7-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics  
see 图7-9  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_RESETz active (low) to  
MCU_RESETSTATz active (low)  
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)  
0
ns  
Delay time, MCU_RESETz inactive (high) to  
MCU_RESETSTATz inactive (high)  
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)  
RST13 td(MCU_RESETzL-RESETSTATzL)  
966*S(1)  
0
ns  
ns  
ns  
Delay time, MCU_RESETz active (low) to  
RESETSTATz active (low)  
RST14 td(MCU_RESETzH-RESETSTATzH)  
Delay time, MCU_RESETz inactive (high) to  
RESETSTATz inactive (high)  
4040*S(1)  
(1) S = MCU_OSC0_XI/XO clock period  
图7-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching  
Characteristics  
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表7-9. RESET_REQz Timing Requirements  
see 图7-10  
NO.  
PARAMETER  
MIN  
MAX UNIT  
(1)  
RST15 tw(RESET_REQzL)  
Pulse Width minimum, RESET_REQz active (low)  
1200  
ns  
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.  
表7-10. RESETSTATz Switching Characteristics  
see 图7-10  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, RESET_REQz active (low) to  
RESETSTATz active (low)  
RST16 td(RESET_REQzL-RESETSTATzL)  
T(1)  
ns  
Delay time, RESET_REQz inactive (high) to  
RESETSTATz inactive (high)  
RST17 td(RESET_REQzH-RESETSTATzH)  
W(2)  
ns  
(1) T = Reset Isolation Time (Software Dependent)  
(2) W = Max [300 μs (Typical) from RESETz_REQz inactive (high), Reset Isolation Time + 300 μs (TYP) from RESET_REQz active  
(low)]  
图7-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics  
表7-11. EMUx Timing Requirements  
see 图7-11  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Setup time, EMU[1:0] before MCU_PORz inactive  
(high)  
RST18 tsu(EMUx-MCU_PORz)  
3*S(1)  
ns  
Hold time, EMU[1:0] after MCU_PORz inactive  
(high)  
RST19 th(MCU_PORz - EMUx)  
10  
ns  
(1) S = MCU_OSC0_XI/XO clock period  
图7-11. EMUx Timing Requirements  
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表7-12. BOOTMODE Timing Requirements  
see 图7-12  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Setup time, BOOTMODE[15:00] before  
PORz_OUT high (External MCU PORz event or  
Software SW_MAIN_PORz)  
RST23 tsu(BOOTMODE-PORz_OUT)  
3*S(1)  
ns  
Hold time, BOOTMODE[15:00] after PORz_OUT  
high (External MCU PORz event, Software  
SW_MAIN_PORz)  
RST24 th(PORz_OUT - BOOTMODE)  
0
ns  
(1) S = MCU_OSC0_XI/XO clock period  
表7-13. PORz_OUT Switching Characteristics  
see 图7-12  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Delay time, MCU_PORz active (low) to  
PORz_OUT active (low)  
RST25 td(MCU_PORzL-PORz_OUT)  
RST26 td(MCU_PORzH-PORz_OUT)  
RST27 tw(PORz_OUTL)  
0
ns  
Delay time, MCU_PORz inactive (high) to  
PORz_OUT inactive (high)  
0
ns  
ns  
Pulse Width Minimum PORz_OUT low  
(MCU_PORz, SW_MAIN_PORz)  
1200  
图7-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics  
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7.10.3.2 Safety Signal Timing  
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn.  
表7-14. MCU_SAFETY_ERRORn Switching Characteristics  
see 图7-13  
NO.  
PARAMETER  
MIN  
MAX UNIT  
Cycle time minimum, MCU_SAFETY_ERRORn  
(PWM mode enabled)  
SFTY1 tc(MCU_SAFETY_ERRORn)  
(P*H)+(P*L)(1) (3) (4)  
ns  
Pulse width minimum, MCU_SAFETY_ERRORn  
active (PWM mode disabled)(5)  
SFTY2 tw(MCU_SAFETY_ERRORn)  
P*R(1) (2)  
50*P(1)  
ns  
ns  
td (ERROR_CONDITION-  
Delay time, ERROR CONDITION to  
MCU_SAFETY_ERRORn active(5)  
SFTY3  
MCU_SAFETY_ERRORnL)  
(1) P = ESM functional clock  
(2) R = Error Pin Counter Pre-Load Register count value  
(3) H = Error Pin PWM High Pre-Load Register count value  
(4) L = Error Pin PWM Low Pre-Load Register count value  
(5) When PWM mode is enabled, MCU_SAFETY_ERRORn stops toggling after RST22 and will maintain its value (either high or low) until  
the error is cleared. When PWM mode is disabled, MCU_SAFETY_ERRORn is active low.  
图7-13. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics  
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7.10.3.3 Clock Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for clock  
signals.  
表7-15. Clock Timing Requirements  
see 图7-14  
NO.  
MIN  
10  
MAX UNIT  
CLK1 tc(EXT_REFCLK1)  
CLK2 tw(EXT_REFCLK1H)  
CLK3 tw(EXT_REFCLK1L)  
CLK19 tc(MCU_EXT_REFCLK0)  
CLK20 tw(MCU_EXT_REFCLK0H)  
CLK21 tw(MCU_EXT_REFCLK0L)  
Cycle time minimum, EXT_REFCLK1  
ns  
Pulse Duration minimum, EXT_REFCLK1 high  
Pulse Duration minimum, EXT_REFCLK1 low  
Cycle time minimum, MCU_EXT_REFCLK0  
Pulse Duration minimum, MCU_EXT_REFCLK0 high  
Pulse Duration minimum, MCU_EXT_REFCLK0 low  
E*0.45(1)  
E*0.45(1)  
10  
E*0.55(1)  
ns  
ns  
ns  
ns  
ns  
E*0.55(1)  
F*0.45(2)  
F*0.45(2)  
F*0.55(2)  
F*0.55(2)  
(1) E = EXT_REFCLK1 cycle time  
(2) F = MCU_EXT_REFCLK0 cycle time  
CLK1  
CLK2  
CLK3  
EXT_REFCLK1  
CLK19  
CLK20  
CLK21  
MCU_EXT_REFCLK0  
图7-14. Clock Timing Requirements  
表7-16. Clock Switching Characteristics  
see 图7-15  
NO.  
PARAMETER  
MIN  
8
MAX UNIT  
CLK4 tc(SYSCLKOUT0)  
CLK5 tw(SYSCLKOUT0H)  
CLK6 tw(SYSCLKOUT0L)  
CLK7 tc(OBSCLK0)  
Cycle time minimum,SYSCLKOUT0  
ns  
Pulse Duration minimum, SYSCLKOUT0 high  
Pulse Duration minimum, SYSCLKOUT0 low  
Cycle time minimum, OBSCLK0  
A*0.4(1)  
A*0.4(1)  
5
A*0.6(1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A*0.6(1)  
CLK8 tw(OBSCLK0H)  
Pulse Duration minimum, OBSCLK0 high  
Pulse Duration minimum,OBSCLK0 low  
Cycle time minimum, CLKOUT0  
B*0.45(2)  
B*0.45(2)  
20  
B*0.55(2)  
B*0.55(2)  
CLK9 tw(OBSCLK0L)  
CLK10 tc(CLKOUT0)  
CLK11 tw(CLKOUT0H)  
Pulse Duration minimum, CLKOUT0 high  
Pulse Duration minimum,CLKOUT0 low  
Cycle time minimum, MCU_SYSCLKOUT0  
Pulse Duration minimum, MCU_SYSCLKOUT0 high  
Pulse Duration minimum,MCU_SYSCLKOUT0 low  
Cycle time minimum, MCU_OBSCLK0  
Pulse Duration minimum, MCU_OBSCLK0 high  
Pulse Duration minimum,MCU_OBSCLK0 low  
C*0.4(3)  
C*0.4(3)  
10  
C*0.6(3)  
C*0.6(3)  
CLK12 tw(CLKOUT0L)  
CLK13 tc(MCU_SYSCLKOUT0)  
CLK14 tw(MCU_SYSCLKOUT0H)  
CLK15 tw(MCU_SYSCLKOUT0L)  
CLK16 tc(MCU_OBSCLK0)  
CLK17 tw(MCU_OBSCLK0H)  
CLK18 tw(MCU_OBSCLK0L)  
G*0.4(4)  
G*0.4(4)  
5
G*0.6(4)  
G*0.6(4)  
H*0.45(5)  
H*0.45(5)  
H*0.55(5)  
H*0.55(5)  
(1) A = SYSCLKOUT0 cycle time  
(2) B = OBSCLK0 cycle time  
(3) C = CLKOUT0 cycle time  
(4) G = MCU_SYSCLKOUT0 cycle time  
(5) H = MCU_OBSCLK0 cycle time  
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CLK4  
CLK7  
CLK5  
CLK8  
CLK6  
SYSCLKOUT0  
CLK9  
OBSCLK0  
CLKOUT0  
CLK10  
CLK11  
CLK12  
CLK13  
CLK16  
CLK14  
CLK17  
CLK15  
CLK18  
MCU_SYSCLKOUT0  
MCU_OBSCLK0  
图7-15. Clock Switching Characteristics  
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7.10.4 Clock Specifications  
7.10.4.1 Input Clocks / Oscillators  
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as  
follows:  
• MCU_OSC0_XI/MCU_OSC0_XO —Еxternal main crystal interface pins connected to the internal high-  
frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock  
MCU_HFOSC0_CLKOUT.  
• General purpose clock inputs  
– MCU_EXT_REFCLK0 —Optional external system clock input for MCU domain.  
– EXT_REFCLK1 —Optional external system clock input for MAIN domain.  
– SERDES0_REFCLK0P/N —Optional SERDES0 reference clock input for PCIe.  
• External CPTS reference clock inputs  
– CP_GEMAC_CPTS0_RFT_CLK —CPTS reference clock input.  
– CPTS_RFT_CLK —CPTS reference clock input.  
图7-16 shows the external input clock sources and the output clocks to peripherals.  
DEVICE  
Reference Clock Output  
CLKOUT  
SYSCLKOUT0  
Main Domain System Clock (MAIN_SYSCLK0) divided-by-4  
MCU Domain System Clock (MCU_SYSCLK0) divided-by-4  
MCU_SYSCLKOUT0  
MCU_OSC0_XI  
MCU_OSC0_XO  
External main crystal interface pins connected to internal oscillator  
which provides reference clock to PLLs within MCU domain  
and MAIN domain.  
JTAG Clock Input  
TCK  
MCU Warm Reset Input / Device Warm Reset Input  
MCU_RESETz  
MCU_PORz  
MCU Power ON Reset / Device Power ON Reset  
Boot Mode Configuration / Devices Select  
DDR Differential Clock Outputs  
BOOTMODE[15:00]  
DDR0_CK0/DDR0_CK0_n  
SERDES0_REFCLK0P/N  
Optional SERDES0 Reference Clock Input for PCIe  
Observation Clock Outputs for MCU Domain Clock / MAIN Domain Clocks  
Optional External System Clock Inputs - (MCU Domain) / (MAIN Domain)  
MCU_OBSCLK0 / OBSCLK0  
MCU_EXT_REFCLK0 / EXT_REFCLK1  
CPTS Reference Clock Inputs  
CP_GEMAC_CPTS0_RFT_CLK / CPTS0_RFT_CLK  
CP_GEMAC_CPTS0_RFT_CLK /  
CPTS0_RFT_CLK  
J7ES_CLOCK_01  
图7-16. Input Clocks Interface  
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the  
device TRM.  
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7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source  
图 7-17 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit  
must be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.  
Device  
MCU_OSC0_XI  
MCU_OSC0_XO  
Rd  
Crystal  
(Optional)  
C
C
f2  
f1  
图7-17. MCU_OSC0 Crystal Implementation  
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-17 summarizes the  
required electrical constraints.  
表7-17. MCU_OSC0 Crystal Circuit Requirements  
PARAMETER  
MIN  
TYP  
MAX UNIT  
Fxtal  
Crystal Parallel Resonance Frequency  
25  
MHz  
Ethernet RGMII and RMII  
not used  
±100  
ppm  
±50  
Fxtal  
Crystal Frequency Stability and Tolerance  
Ethernet RGMII and RMII  
using derived clock  
CL1+PCBXI  
CL2+PCBXO  
CL  
Capacitance of CL1 + CPCBXI  
Capacitance of CL2 + CPCBXO  
Crystal Load Capacitance  
12  
12  
6
24  
24  
12  
7
pF  
pF  
pF  
pF  
pF  
pF  
25 MHz  
25 MHz  
25 MHz  
ESRxtal = 30 Ω  
Cshunt  
Crystal Circuit Shunt Capacitance  
Crystal Effective Series Resistance  
5
ESRxtal = 40 Ω  
ESRxtal = 50 Ω  
5
(1)  
ESRxtal  
Ω
(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.  
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal  
based on worst case environment and expected life expectancy of the system.  
表7-18 details the switching characteristics of the oscillator.  
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表7-18. MCU_OSC0 Switching Characteristics - Crystal Mode  
PARAMETER  
MIN  
TYP  
MAX  
1.44  
1.52  
0.01  
UNIT  
pF  
CXI  
XI Capacitance  
XO Capacitance  
CXO  
CXIXO  
ts  
pF  
XI to XO Mutual Capacitance  
Start-up Time  
pF  
4
ms  
VDD_CORE (min.)  
VDD_CORE  
VDDS_OSC  
VSS  
VDDS_OSC (min.)  
MCU_OSC0_XO  
tsX  
VSS  
Time  
AM65x_MCU_OSC_STARTUP_02  
图7-18. MCU_OSC0 Start-up Time  
7.10.4.1.1.1 Load Capacitance  
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined  
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,  
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to  
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB  
designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits and  
device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic  
capacitance values are defined in 表7-18.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
MCU_OSC0_XI  
CL1  
CPCBXI  
CXI  
CL2  
CPCBXO  
CXO  
MCU_OSC0_XO  
AM65x_MCU_OSC_CC_05  
图7-19. Load Capacitance  
Load capacitors, CL1 and CL2 in 图 7-17, should be chosen such that the below equation is satisfied. CL in the  
equation is the load specified by the crystal manufacturer.  
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CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]  
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the  
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to  
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5  
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -  
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF  
7.10.4.1.1.2 Shunt Capacitance  
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for  
MCU_OSC0 operating conditions defined in 表 7-17. Shunt capacitance, Cshunt, of the crystal circuit is a  
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal  
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB  
designer should be able to extract mutual parasitic capacitance between these signal traces. The device  
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined  
in 表7-18.  
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is  
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can  
also be minimized by placing a ground trace between these signals when the layout requires them to be routed  
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as  
possible when selecting a crystal.  
Device  
Crystal Circuit  
Components  
PCB  
Signal Traces  
MCU_OSC0_XI  
CPCBXIXO  
CXIXO  
CO  
MCU_OSC0_XO  
AM65x_MCU_OSC_SC_06  
图7-20. Shunt Capacitance  
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt  
capacitance specified by the crystal manufacturer.  
C
shunt ≥CO + CPCBXIXO + CXIXO  
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,  
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.  
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7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source  
图 7-21 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V LVCMOS  
square-wave digital clock source.  
备注  
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This  
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an  
unknown state when DC is applied to the input. Therefore, application software must power down  
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.  
Device  
MCU_OSC0_XO  
MCU_OSC0_XI  
PCB Ground  
AM65x_MCU_OSC_EXT_CLK_03  
图7-21. 1.8-V LVCMOS-Compatible Clock Input  
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7.10.4.2 Output Clocks  
The device provides several system clock outputs. Summary of these output clocks are as follows:  
• MCU_SYSCLKOUT0  
– MCU_SYSCLKOUT0 is the MCU domain system clock (MCU_SYSCK0) divided-by-4. This clock output is  
provided for test and debug purposes only.  
• MCU_OBSCLK0  
– Observation clock output for test and debug purposes only.  
• SYSCLKOUT0  
– SYSCLKOUT0 is the MAIN domain system clock (MAIN_SYSCLK0) divided-by-4. This clock output is  
provided for test and debug purposes only.  
• CLKOUT0  
– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL0_HSDIV4_CLKOUT) divided-by-5 or divided-  
by-10. This clock output was provided to source to the external PHY. When configured to operate as the  
RMII Clock source (50 MHz) the signal must also be routed back to the RMII_REF_CLK pin for proper  
device operation.  
• OBSCLK0  
– Observation clock output for test and debug purposes only.  
• GPMC_FCLK_MUX  
– GPMC_FCLK_MUX is the GPMC0 functional clock (GPMC_FCLK). This clock is provided as an  
alternative GPMC interface clock when attached devices require a continuous running clock.  
For more information, see Clock Outputs section in Clocking chapter and GPMC Clock Configuration section in  
Peripherals chapter in the device TRM.  
7.10.4.3 PLLs  
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from  
off-chip power-sources.  
There is one PLL in the MCU domain:  
• MCU0_PLL  
There are six PLLs in the MAIN domain:  
• ARM0_PLL  
• MAIN_PLL  
• PER0_PLL  
• PER1_PLL  
• DDR PLL  
• R5F PLL  
备注  
For more information, see:  
• Device Configuration / Clocking / PLLs section in the device TRM.  
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit  
(PRU_ICSSG) section in the device TRM.  
备注  
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is  
ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.  
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7.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions  
All clock and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic  
manner.  
Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create non-  
monotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and  
control signals since they are more likely to generate glitches inside the device.  
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7.10.5 Peripherals  
7.10.5.1 CPSW3G  
For more details about features and additional description information on the device Gigabit Ethernet MAC, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
备注  
CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more  
signals which can be multiplexed to more than one pin. Timing requirements and switching  
characteristics defined in this section are only valid for specific pin combinations known as IOSETs.  
Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G  
IOSETs section.  
7.10.5.1.1 CPSW3G MDIO Timing  
表 7-19, 表 7-20, 表 7-21, and 图 7-22 present timing conditions, requirements, and switching characteristics for  
CPSW3G MDIO.  
表7-19. CPSW3G MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
表7-20. CPSW3G MDIO Timing Requirements  
see 图7-22  
NO.  
PARAMETER  
MIN  
90  
0
MAX  
UNIT  
ns  
MDIO1 tsu(MDIO_MDC)  
MDIO2 th(MDC_MDIO)  
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high  
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high  
ns  
表7-21. CPWS3G MDIO Switching Characteristics  
see 图7-22  
NO.  
PARAMETER  
MIN  
400  
160  
160  
-150  
MAX  
UNIT  
ns  
MDIO3 tc(MDC)  
Cycle time, MDIO[x]_MDC  
MDIO4 tw(MDCH)  
MDIO5 tw(MDCL)  
MDIO7 td(MDC_MDIO)  
Pulse Duration, MDIO[x]_MDC high  
ns  
Pulse Duration, MDIO[x]_MDC low  
ns  
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid  
150  
ns  
MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
图7-22. CPSW3G MDIO Timing Requirements and Switching Characteristics  
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7.10.5.1.2 CPSW3G RMII Timing  
表 7-22, 表 7-23, 图 7-23, 表 7-24, 图 7-24 表 7-25, and 图 7-25 present timing conditions, requirements, and  
switching characteristics for CPSW3G RMII.  
表7-22. CPSW3G RMII Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
VDD(1) = 1.8V  
VDD(1) = 3.3V  
0.18  
0.4  
0.54 V/ns  
1.2 V/ns  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
3
25  
pF  
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see  
POWER column of the Pin Attributes table.  
表7-23. RMII[x]_REF_CLK Timing Requirements –RMII Mode  
see 图7-23  
NO.  
PARAMETER  
tc(REF_CLK)  
tw(REF_CLKH)  
tw(REF_CLKL)  
DESCRIPTION  
MIN  
MAX  
20.001  
13  
UNIT  
ns  
RMII1  
RMII2  
RMII3  
Cycle time, RMII[x]_REF_CLK  
19.999  
Pulse Duration, RMII[x]_REF_CLK High  
Pulse Duration, RMII[x]_REF_CLK Low  
7
7
ns  
13  
ns  
RMII1  
RMII2  
RMII[x]_REF_CLK  
RMII3  
图7-23. CPSW3G RMII[x]_REF_CLK Timing Requirements –RMII Mode  
表7-24. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements –RMII Mode  
see 图7-24  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
4
MAX  
UNIT  
ns  
RMII4  
tsu(RXD-REF_CLK)  
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK  
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK  
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK  
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK  
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK  
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK  
tsu(CRS_DV-REF_CLK)  
tsu(RX_ER-REF_CLK)  
th(REF_CLK-RXD)  
4
ns  
4
ns  
RMII5  
2
ns  
th(REF_CLK-CRS_DV)  
th(REF_CLK-RX_ER)  
2
ns  
2
ns  
RMII4  
RMII5  
RMII[x]_REF_CLK  
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,  
RMII[x]_RX_ER  
图7-24. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements –RMII Mode  
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表7-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode  
see 图7-25  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
RMII6 td(REF_CLK-TXD)  
Delay time, RMII[x]_REF_CLK High to RMII[x]_  
TXD[1:0] valid  
2
10  
ns  
td(REF_CLK-TX_EN)  
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN  
valid  
2
10  
ns  
RMII6  
RMII[x]_REF_CLK  
RMII[x]_TXD[1:0], RMII[x]_TX_EN  
图7-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode  
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7.10.5.1.3 CPSW3G RGMII Timing  
表 7-26, 表 7-27, 表 7-28, 图 7-26, 表 7-29, 表 7-30, and 图 7-27 present timing conditions, requirements, and  
switching characteristics for CPSW3G RGMII.  
表7-26. CPSW3G RGMII Timing Conditions  
PARAMETER  
MIN  
2.64  
2
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
5
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
PCB CONNECTIVITY REQUIREMENTS  
RGMII[x]_RXC,  
RGMII[x]_RD[3:0],  
RGMII[x]_RX_CTL  
50  
50  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
Delay)  
RGMII[x]_TXC,  
RGMII[x]_TD[3:0],  
RGMII[x]_TX_CTL  
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表7-27. RGMII[x]_RXC Timing Requirements –RGMII Mode  
see 图7-26  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_RXC  
MODE  
10Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII1 tc(RXC)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
RGMII2 tw(RXCH)  
Pulse duration, RGMII[x]_RXC high  
Pulse duration, RGMII[x]_RXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
RGMII3 tw(RXCL)  
100Mbps  
1000Mbps  
3.6  
4.4  
表7-28. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements –RGMII Mode  
see 图7-26  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
1
MAX UNIT  
RGMII4 tsu(RD-RXC)  
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
1
1
tsu(RX_CTL-RXC)  
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
10Mbps  
1
1
RGMII5 th(RXC-RD)  
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
10Mbps  
1
1
th(RXC-RX_CTL)  
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC  
high/low  
1
100Mbps  
1000Mbps  
1
1
RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
RGMII[x]_RX_CTL(B)  
1st Half-byte  
RXDV  
2nd Half-byte  
RXERR  
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of  
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.  
图7-26. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII  
Mode  
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MAX UNIT  
表7-29. RGMII[x]_TXC Switching Characteristics –RGMII Mode  
see 图7-27  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_TXC  
MODE  
10Mbps  
MIN  
360  
36  
RGMII6 tc(TXC)  
RGMII7 tw(TXCH)  
RGMII8 tw(TXCL)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_TXC high  
Pulse duration, RGMII[x]_TXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
100Mbps  
1000Mbps  
3.6  
4.4  
表7-30. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics –RGMII Mode  
see 图7-27  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
MAX UNIT  
RGMII9 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC  
high/low  
100Mbps  
1000Mbps  
10Mbps  
RGMII10 toh(TXC-TD)  
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC  
high/low  
100Mbps  
1000Mbps  
10Mbps  
toh(TXC-TX_CTL)  
Output hold time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
100Mbps  
1000Mbps  
RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of  
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.  
图7-27. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics -  
RGMII Mode  
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7.10.5.1.4 CPSW3G IOSETs  
表7-31 defines valid pin combinations of each CPSW3G MDIO0 IOSET.  
表7-31. CPSW3G MDIO0 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
BALL NAME  
MUXMODE  
BALL NAME  
MUXMODE  
MDIO0_MDIO  
MDIO0_MDC  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
4
4
PRG1_MDIO0_MDIO  
PRG1_MDIO0_MDC  
4
4
表7-32 defines valid pin combinations of each CPSW3G RMII1 and RMII2 IOSET.  
表7-32. CPSW3G RMII1 and RMII2 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
BALL NAME  
MUXMODE  
BALL NAME  
MUXMODE  
RMII_REF_CLK(1)  
RMII1_CRS_DV  
RMII1_RX_ER  
RMII1_RXD0  
RMII1_RXD1  
RMII1_TXD0  
RMII1_TXD1  
RMII1_TX_EN  
RMII2_CRS_DV  
RMII2_RX_ER  
RMII2_RXD0  
RMII2_RXD1  
RMII2_TXD0  
RMII2_TXD1  
RMII2_TX_EN  
PRG1_PRU0_GPO10  
PRG1_PRU1_GPO19  
PRG1_PRU0_GPO9  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO15  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
PRG0_PRU0_GPO10  
PRG0_PRU1_GPO19  
PRG0_PRU0_GPO9  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO15  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
(1) RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed  
signal assignments must use the same IOSET.  
表7-33 defines valid pin combinations of each CPSW3G RGMII1 IOSET.  
表7-33. CPSW3G RGMII1 IOSETs  
SIGNALS  
IOSET1  
IOSET2  
BALL NAME  
MUXMODE  
BALL NAME  
MUXMODE  
RGMII1_TX_CTL  
RGMII1_TXC  
RGMII1_TD0  
RGMII1_TD1  
RGMII1_TD2  
RGMII1_TD3  
RGMII1_RX_CTL  
RGMII1_RXC  
RGMII1_RD0  
RGMII1_RD1  
RGMII1_RD2  
RGMII1_RD3  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO17  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO17  
4
4
4
4
4
4
4
4
4
4
4
4
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO17  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO8  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO19  
4
4
4
4
4
4
4
4
4
4
4
4
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7.10.5.2 DDRSS  
For more details about features and additional description information on the device (LP)DDR4 Memory  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
表7-34 and 图7-28 present switching characteristics for DDRSS.  
表7-34. DDRSS Switching Characteristics  
see 图7-28  
NO.  
PARAMETER  
DDR TYPE  
LPDDR4  
DDR4  
MIN  
1.25(1)  
1.25(1)  
MAX UNIT  
20  
ns  
ns  
tc(DDR_CKP/  
1
Cycle time, DDR_CKP and DDR_CKN  
DDR_CKN)  
1.6  
(1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB  
implementation. Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve  
maximum DDR frequency.  
1
DDR0_CKP  
DDR0_CKN  
图7-28. DDRSS Switching Characteristics  
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.  
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7.10.5.3 ECAP  
表 7-35, 表 7-36, 图 7-29, 表 7-37, and 图 7-30 present timing conditions, requirements, and switching  
characteristics for ECAP.  
表7-35. ECAP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
表7-36. ECAP Timing Requirements  
see 图7-29  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, CAP (asynchronous)  
MIN  
2 + 2P(1)  
MAX  
UNIT  
CAP1 tw(CAP)  
ns  
(1) P = sysclk period in ns.  
CAP1  
CAP  
EPERIPHERALS_TIMNG_01  
图7-29. ECAP Timings Requirements  
表7-37. ECAP Switching Characteristics  
see 图7-30  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
CAP2 tw(APWM)  
Pulse duration, APWMx high/low  
-2 + 2P(1)  
ns  
(1) P = sysclk period in ns.  
CAP2  
APWM  
EPERIPHERALS_TIMNG_02  
图7-30. ECAP Switching Characteristics  
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.  
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7.10.5.4 EPWM  
表 7-38, 表 7-39, 图 7-31, 表 7-40, 图 7-32, 图 7-33, and 图 7-34 present timing conditions, requirements, and  
switching characteristics for EPWM.  
表7-38. EPWM Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
表7-39. EPWM Timing Requirements  
see 图7-31  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_SYNCI  
MIN  
2 + 2P(1)  
2 + 3P(1)  
MAX  
UNIT  
ns  
PWM6 tw(SYNCIN)  
PWM7 tw(TZ)  
Pulse duration, EHRPWM_TZn_IN low  
ns  
(1) P = sysclk period in ns.  
PWM6  
EHRPWM_SYNCI  
PWM7  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMNG_07  
图7-31. EPWM Timing Requirements  
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表7-40. EPWM Switching Characteristics  
see 图7-32, 图7-33, and 图7-34  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EHRPWM_A/B high/low  
Pulse duration, EHRPWM_SYNCO  
MIN  
P - 3(1)  
P - 3(1)  
MAX  
UNIT  
ns  
PWM1 tw(PWM)  
PWM2 tw(SYNCOUT)  
PWM3 td(TZ-PWM)  
ns  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced  
high/low  
11  
11  
ns  
PWM4 td(TZ-PWMZ)  
PWM5 tw(SOC)  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z  
Pulse duration, EHRPWM_SOCA/B output  
ns  
ns  
P - 3(1)  
(1) P = sysclk period in ns.  
PWM1  
EHRPWM_A/B  
PWM1  
PWM2  
EHRPWM_SYNCO  
EHRPWM_SOCA/B  
PWM5  
EPERIPHERALS_TIMNG_04  
图7-32. EHRPWM Switching Characteristics  
PWM3  
EHRPWM_A/B  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMING_05  
图7-33. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics  
PWM4  
EHRPWM_A/B  
EHRPWM_TZn_IN  
图7-34. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in  
the device TRM.  
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7.10.5.5 EQEP  
表 7-41, 表 7-42, 图 7-35, and 表 7-43 present timing conditions, requirements, and switching characteristics for  
EQEP.  
表7-41. EQEP Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
表7-42. EQEP Timing Requirements  
see 图7-35  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
2 + 2P(1)  
MAX  
UNIT  
ns  
QEP1  
QEP2  
QEP3  
QEP4  
QEP5  
tw(QEP)  
Pulse duration, QEP_A/B  
Pulse duration, QEP_I high  
Pulse duration, QEP_I low  
tw(QEPIH)  
tw(QEPIL)  
tw(QEPSH)  
tw(QEPSL)  
ns  
ns  
Pulse duration, QEP_S high  
Pulse duration, QEP_S low  
ns  
ns  
(1) P = sysclk period in ns  
QEP1  
QEP_A/B  
QEP2  
QEP_I  
QEP3  
QEP4  
QEP_S  
QEP5  
EPERIPHERALS_TIMNG_03  
图7-35. EQEP Timing Requirements  
表7-43. EQEP Switching Characteristics  
DESCRIPTION  
NO.  
PARAMETER  
td(QEP-CNTR)  
MIN  
MAX  
UNIT  
QEP6  
Delay time, external clock to counter increment  
24  
ns  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter  
in the device TRM.  
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7.10.5.6 FSI  
表 7-44, 表 7-45, 图 7-36, 表 7-46, 图 7-37, 表 7-47, and 图 7-38 present timing conditions, requirements, and  
switching characteristics for FSI.  
表7-44. FSI Timing Conditions  
PARAMETER  
MIN  
0.8  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
表7-45. FSI Timing Requirements  
see 图7-36  
NO.  
MIN  
MAX  
UNIT  
ns  
FSIR1 tc(RX_CLK)  
Cycle time, FSI_RXn_CLK  
20  
FSIR2 tw(RX_CLK)  
Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high  
Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK  
Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK  
0.5P - 1(1) 0.5P + 1(1)  
ns  
FSIR3 tsu(RX_D-RX_CLK)  
FSIR4 th(RX_CLK-RX_D)  
3
ns  
2.5  
ns  
(1) P = FSI_RXn_CLK period in ns.  
FSIR1  
FSIR2  
FSIR2  
FSI_RXn_CLK  
FSI_RXn_D0  
FSI_RXn_D1  
FSIR3  
FSIR4  
图7-36. FSI Timing Requirements  
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表7-46. FSI Switching Characteristics - FSI Mode  
see 图7-37  
NO.  
PARAMETER  
MODE  
MIN  
20  
0.5p + 1(1)  
0.25P - 2(1)  
MAX UNIT  
FSIT1 tc(TX_CLK)  
Cycle time, FSI_TXn_CLK  
FSI Mode  
FSI Mode  
FSI Mode  
ns  
FSIT2 tw(TX_CLK)  
FSIT3 td(TX_CLK-TX_D)  
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high  
0.5P - 1(1)  
ns  
ns  
Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK  
high or FSI_TXn_CLK low  
0.25P +  
2.5(1)  
(1) P = FSI_TXn_CLK period in ns.  
FSIT1  
FSIT2  
FSIT2  
FSI_TXn_CLK  
FSI_TXn_D0  
FSI_TXn_D1  
FSIT3  
图7-37. FSI Switching Characteristics - FSI Mode  
表7-47. FSI Switching Characteristics - SPI Mode  
see 图7-38  
NO.  
PARAMETER  
MODE  
MIN  
20  
0.5P + 1(1)  
MAX UNIT  
FSIT4 tc(TX_CLK)  
FSIT5 tw(TX_CLK)  
Cycle time, FSI_TXn_CLK  
SPI Mode  
SPI Mode  
SPI Mode  
SPI Mode  
SPI Mode  
ns  
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high  
0.5P - 1(1)  
ns  
ns  
ns  
ns  
FSIT6 td(TX_CLKH-TX_D0) Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid  
3
FSIT7 td(TX_D1-TX_CLK)  
FSIT8 td(TX_CLK-TX_D1)  
Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high  
Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high  
P - 3(1)  
P - 2(1)  
(1) P = FSI_TXn_CLK period in ns.  
FSIT4  
FSIT5  
FSIT5  
FSI_TXn_CLK  
FSI_TXn_D0  
FSI_TXn_D1  
FSIT6  
FSIT8  
FSIT7  
图7-38. FSI Switching Characteristics - SPI Mode  
For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.  
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7.10.5.7 GPIO  
表7-48, 表7-49, and 表7-50 present timing conditions, requirements, and switching characteristics for GPIO.  
The device has three instances of the GPIO module.  
• MCU_GPIO0  
• GPIO0  
• GPIO1  
备注  
GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO  
module and x represents one of the input/output signals associated with the module.  
For additional description information on the device GPIO, see the corresponding subsections within  
Signal Descriptions and Detailed Description sections.  
表7-48. GPIO Timing Conditions  
PARAMETER  
BUFFER TYPE  
MIN  
MAX UNIT  
INPUT CONDITIONS  
LVCMOS  
0.2  
0.2  
6.6 V/ns  
0.8 V/ns  
SRI  
Input slew rate  
I2C OD FS  
OUTPUT CONDITIONS  
LVCMOS  
3
3
10  
pF  
pF  
CL  
Output load capacitance  
I2C OD FS  
100  
表7-49. GPIO Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
1.8 V  
3.3 V  
MIN  
MAX UNIT  
2P + 2.6(1)  
2P + 3.5(1)  
ns  
ns  
GPIO1 tw(GPIO_IN)  
Pulse width, GPIOn_x  
(1) P = functional clock period in ns.  
表7-50. GPIO Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
BUFFER TYPE  
MIN  
MAX UNIT  
0.975P(1)  
-
LVCMOS  
ns  
ns  
3.6  
GPIO2 tw(GPIO_OUT)  
Pulse width, GPIOn_x  
I2C OD FS  
160  
(1) P = functional clock period in ns.  
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.  
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7.10.5.8 GPMC  
For more details about features and additional description information on the device General-Purpose Memory  
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
备注  
GPMC has one or more signals which can be multiplexed to more than one pin. Timing requirements  
and switching characteristics defined in this section are only valid for specific pin combinations known  
as IOSETs. Valid pin combinations or IOSETs for this interface is shown in 节7.10.5.8.4.  
表7-51 presents timing conditions for GPMC.  
表7-51. GPMC Timing Conditions  
PARAMETER  
MIN  
1.65  
5
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
PCB CONNECTIVITY REQUIREMENTS  
133 MHz Synchronous Mode  
All other modes  
140  
140  
360  
720  
ps  
ps  
td(Trace Delay)  
Propagation delay of each trace  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
200  
ps  
Delay)  
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the  
device TRM.  
7.10.5.8.1 GPMC and NOR Flash —Synchronous Mode  
Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (th(clkH-waitV)  
)
表 7-52 and 表 7-53 present timing requirements and switching characteristics for GPMC and NOR Flash -  
Synchronous Mode.  
表7-52. GPMC and NOR Flash Timing Requirements —Synchronous Mode  
see 图7-39, 图7-40, and 图7-43  
MIN  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(5)  
UNIT  
GPMC_FCLK = GPMC_FCLK =  
100 MHz(2)  
133 MHz(2)  
F12 tsu(dV-clkH)  
F13 th(clkH-dV)  
F21 tsu(waitV-clkH)  
Setup time, input data  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.81  
1.12  
ns  
GPMC_AD[n:0](1) valid before  
output clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
1.06  
2.29  
2.29  
1.81  
1.06  
3.5  
2.29  
2.29  
1.12  
3.5  
ns  
ns  
ns  
ns  
ns  
Hold time, input data  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_AD[n:0](1) valid after output  
clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Setup time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GPMC_WAIT[j](3) (4) valid before  
output clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
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表7-52. GPMC and NOR Flash Timing Requirements —Synchronous Mode (continued)  
see 图7-39, 图7-40, and 图7-43  
MIN  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(5)  
UNIT  
GPMC_FCLK = GPMC_FCLK =  
100 MHz(2)  
133 MHz(2)  
F22 th(clkH-waitV)  
Hold time, input wait  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.29  
2.29  
ns  
GPMC_WAIT[j](3) (4) valid after  
output clock GPMC_CLK high  
not_div_by_1_mode;  
GPMC_FCLK_MUX;  
2.29  
2.29  
ns  
TIMEPARAGRANULARITY_X1  
(1) Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz  
(2) GPMC_FCLK select  
•
•
gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK  
gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK  
(3) In GPMC_WAIT[j], j is equal to 0 or 1.  
(4) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-  
Purpose Memory Controller (GPMC) section in the device TRM.  
(5) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For not_div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:  
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
表7-53. GPMC and NOR Flash Switching Characteristics –Synchronous Mode  
see 图7-39, 图7-40, 图7-41, 图7-42, and 图7-43  
MIN  
100 MHz  
10.00  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(3)  
133 MHz  
F0 1 / tc(clk)  
F1 tw(clkH)  
Period, output clock GPMC_CLK(16)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
7.52  
ns  
Typical pulse duration, output clock  
GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
0.475P  
- 0.3(15)  
0.475P  
ns  
ns  
- 0.3(15)  
F1 tw(clkL)  
Typical pulse duration, output clock  
GPMC_CLK low  
div_by_1_mode;  
GPMC_FCLK_MUX;  
0.475P  
- 0.3(15)  
0.475P  
- 0.3(15)  
TIMEPARAGRANULARITY_X1  
F2 td(clkH-csnV)  
Delay time, output clock GPMC_CLK  
rising edge to output chip select  
GPMC_CSn[i] transition(14)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
F - 2.2  
F + F - 2.2  
3.75  
F + ns  
3.75  
(6)  
(6)  
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK  
rising edge to output chip select  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
E - 2.2  
E + E - 2.2 E + 4.5 ns  
3.18  
(5)  
(5)  
GPMC_CSn[i] invalid(14)  
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表7-53. GPMC and NOR Flash Switching Characteristics –Synchronous Mode (continued)  
see 图7-39, 图7-40, 图7-41, 图7-42, and 图7-43  
MIN  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(3)  
100 MHz  
133 MHz  
F4 td(aV-clk)  
Delay time, output address  
GPMC_A[27:1] valid to output clock  
GPMC_CLK first edge  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
B - 2.3 B + 4.5 B - 2.3 B + 4.5 ns  
(3)  
(3)  
F5 td(clkH-aIV)  
Delay time, output clock GPMC_CLK  
rising edge to output address  
GPMC_A[27:1] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
-2.3  
4.5  
-2.3  
4.5 ns  
F6 td(be[x]nV-clk)  
Delay time, output lower byte enable  
and command latch enable  
div_by_1_mode;  
GPMC_FCLK_MUX;  
B - 2.3 B + 1.9 B - 2.3 B + 1.9 ns  
(3)  
(3)  
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1  
enable GPMC_BE1n valid to output  
clock GPMC_CLK first edge  
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK  
rising edge to output lower byte  
div_by_1_mode;  
GPMC_FCLK_MUX;  
D - D + 1.9 D - 2.3 D + 1.9 ns  
2.3(4)  
(4)  
enable and command latch enable  
TIMEPARAGRANULARITY_X1  
GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n invalid(11)  
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
invalid(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns  
(4)  
(4)  
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
invalid(13)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns  
(4)  
(4)  
F8 td(clkH-advn)  
F9 td(clkH-advnIV)  
F10 td(clkH-oen)  
F11 td(clkH-oenIV)  
F14 td(clkH-wen)  
Delay time, output clock GPMC_CLK  
rising edge to output address valid  
and address latch enable  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
G - G + 4.5 G - 2.3 G + 4.5 ns  
2.3(7)  
(7)  
GPMC_ADVn_ALE transition  
Delay time, output clock GPMC_CLK  
rising edge to output address valid  
and address latch enable  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
D - 2.3 D + 4.5 D - 2.3 D + 4.5 ns  
(4)  
(4)  
GPMC_ADVn_ALE invalid  
Delay time, output clock GPMC_CLK  
rising edge to output enable  
GPMC_OEn_REn transition  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
H - H + 3.5 H - 2.3 H + 3.5 ns  
2.3(8)  
(8)  
Delay time, output clock GPMC_CLK  
rising edge to output enable  
GPMC_OEn_REn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns  
(8)  
(8)  
Delay time, output clock GPMC_CLK  
rising edge to output write enable  
GPMC_WEn transition  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
I - 2.3 I + 4.5 I - 2.3 I + 4.5 ns  
(9)  
(9)  
F15 td(clkH-do)  
F15 td(clkL-do)  
F15 td(clkL-do).  
F17 td(clkH-be[x]n)  
Delay time, output clock GPMC_CLK  
rising edge to output data  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(10)  
(10)  
GPMC_AD[n:0](1) transition(11)  
Delay time, GPMC_CLK falling edge  
to GPMC_AD[n:0](1) data bus  
transition(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(10)  
(10)  
Delay time, GPMC_CLK falling edge  
to GPMC_AD[n:0](1) data bus  
transition(13)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns  
(10)  
(10)  
Delay time, output clock GPMC_CLK  
rising edge to output lower byte  
enable and command latch enable  
GPMC_BE0n_CLE transition(11)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
(10)  
(10)  
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表7-53. GPMC and NOR Flash Switching Characteristics –Synchronous Mode (continued)  
see 图7-39, 图7-40, 图7-41, 图7-42, and 图7-43  
MIN  
100 MHz  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
MAX  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(17)  
UNIT  
(3)  
133 MHz  
F17 td(clkL-be[x]n)  
Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
transition(12)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
(10)  
(10)  
F17 td(clkL-be[x]n).  
Delay time, GPMC_CLK falling edge  
to GPMC_BE0n_CLE, GPMC_BE1n  
transition(13)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns  
(10)  
(10)  
F18 tw(csnV)  
Pulse duration, output chip select  
GPMC_CSn[i](14) low  
Read  
Write  
Read  
Write  
A
A
C
C
A
A
C
C
ns  
ns  
ns  
ns  
F19 tw(be[x]nV)  
Pulse duration, output lower byte  
enable and command latch enable  
GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n low  
F20 tw(advnV)  
Pulse duration, output address valid  
and address latch enable  
GPMC_ADVn_ALE low  
Read  
Write  
K
K
K
K
ns  
ns  
(1) Synchronous Mode supports 16-bit data bus up to 133 MHz and 32-bit data bus up to 100 MHz  
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
With n being the page burst access number.  
(3) B = ClkActivationTime × GPMC_FCLK(15)  
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)  
(6) For csn falling edge (CS activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and  
CSOnTime are even)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime) is a multiple of 3)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)  
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)  
(7) For ADV falling edge (ADV activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and  
ADVOnTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
Case GPMCFCLKDIVIDER = 0:  
•
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– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)  
•
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Writing mode:  
•
Case GPMCFCLKDIVIDER = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)  
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):  
•
Case GPMCFCLKDIVIDER = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and  
OEOnTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and  
OEOffTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(9) For WE falling edge (WE activated):  
•
Case GPMCFCLKDIVIDER = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15)  
•
Case GPMCFCLKDIVIDER = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and  
WEOnTime are even)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
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– I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)  
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
•
Case GPMCFCLKDIVIDER = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK (15)  
•
Case GPMCFCLKDIVIDER = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and  
WEOffTime are even)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise  
Case GPMCFCLKDIVIDER = 2:  
•
– I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(10) J = GPMC_FCLK(15)  
(11) First transfer only for CLK DIV 1 mode.  
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.  
(13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.  
(14) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
(15) P = GPMC_CLK period in ns  
(16) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the  
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.  
(17) For div_by_1_mode:  
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
For no extra_delay:  
•
•
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed  
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed  
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed  
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
GPMC_A[MSB:1]  
Valid Address  
F19  
F6  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F19  
F6  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F12  
D 0  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_01  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-39. GPMC and NOR Flash —Synchronous Single Read (GPMCFCLKDIVIDER = 0)  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F4  
F6  
GPMCA[MSB:1]  
Valid Address  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F7  
F9  
F6  
F8  
F8  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F13  
F12  
D 0  
F22  
F12  
D 3  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
D 1  
D 2  
F21  
GPMC_02  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-40. GPMC and NOR Flash —Synchronous Burst Read —4x16–bit (GPMCFCLKDIVIDER = 0)  
F1  
F1  
F0  
GPMC_CLK  
GPMC_CSn[i]  
F2  
F3  
F4  
F6  
Valid Address  
GPMC_A[MSB:1]  
F17  
F17  
F17  
F17  
F17  
F17  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_WEn  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
D 0  
D 3  
GPMC_03  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
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B. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-41. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)  
F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[i]  
F6  
F6  
F4  
F7  
GMPC_BE0n_CLE  
Valid  
F7  
Valid  
GPMC_BE1n  
GPMC_A[27:17]  
Address (MSB)  
F5  
F12  
F13  
F4  
F12  
GPMC_AD[15:0]  
Address (LSB)  
D0  
D1  
D2  
D3  
F8  
F8  
F9  
GPMC_ADVn_ALE  
F10  
F11  
GPMC_OEn_REn  
GPMC_WAIT[j]  
GPMC_04  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-42. GPMC and Multiplexed NOR Flash —Synchronous Burst Read  
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F1  
F1  
F0  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[i]  
F4  
F6  
F6  
GPMC_A[27:17]  
Address (MSB)  
F17  
F17  
F17  
F17  
GPMC_BE1n  
F17  
F17  
BPMC_BE0n_CLE  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
F14  
F14  
GPMC_WEn  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
Address (LSB)  
D 0  
D 3  
F22  
F21  
GPMC_WAIT[j]  
GPMC_05  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-43. GPMC and Multiplexed NOR Flash —Synchronous Burst Write  
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7.10.5.8.2 GPMC and NOR Flash —Asynchronous Mode  
表 7-54 and 表 7-55 present timing requirements and switching characteristics for GPMC and NOR Flash —  
Asynchronous Mode.  
表7-54. GPMC and NOR Flash Timing Requirements –Asynchronous Mode  
see 图7-44, 图7-45, 图7-46, and 图7-48  
NO. PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
FA5(1) tacc(d)  
Data access time  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H(4) ns  
TIMEPARAGRANULARITY_X1  
FA2 tacc1-pgmode(d)  
0(2)  
Page mode successive data access time  
Page mode first data access time  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
P(3) ns  
FA2 tacc2-pgmode(d)  
1(1)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H(4) ns  
TIMEPARAGRANULARITY_X1  
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active  
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional  
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
表7-55. GPMC and NOR Flash Switching Characteristics –Asynchronous Mode  
see 图7-44, 图7-45, 图7-46, 图7-47, 图7-48, and 图7-49  
MIN  
MAX  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
UNIT  
N (12) ns  
N (12)  
133 MHz  
FA0 tw(be[x]nV)  
Pulse duration, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid time  
Read  
Write  
FA1 tw(csnV)  
Pulse duration, output chip select GPMC_CSn[i](13)  
low  
Read  
Write  
Read  
A (1) ns  
A (1)  
B - 2.1 B + 2.1 ns  
FA3 td(csnV-advnIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
(2)  
(2)  
Write  
B - 2.1 B + 2.1  
(2)  
(2)  
FA4 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Single read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
C - 2.1 C + 2.1 ns  
(3)  
(3)  
FA9 td(aV-csnV)  
Delay time, output address GPMC_A[27:1] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
TIMEPARAGRANULARITY_X1  
FA10 td(be[x]nV-csnV)  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid to output  
chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
FA12 td(csnV-advnV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
K - 2.1 K + 2.1 ns  
(10)  
(10)  
FA13 td(csnV-oenV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
L - 2.1  
L + 2.1 ns  
(11)  
(11)  
TIMEPARAGRANULARITY_X1  
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表7-55. GPMC and NOR Flash Switching Characteristics –Asynchronous Mode (continued)  
see 图7-44, 图7-45, 图7-46, 图7-47, 图7-48, and 图7-49  
MIN  
MAX  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
UNIT  
133 MHz  
G (7)  
FA16 tw(aIV)  
Pulse duration output address GPMC_A[26:1]  
invalid between 2 successive read and write  
accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
ns  
FA18 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output enable GPMC_OEn_REn invalid  
(Burst read)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
I - 2.1 (8) I + 2.1 (8) ns  
FA20 tw(aV)  
Pulse duration, output address GPMC_A[27:1]  
valid - 2nd, 3rd, and 4th accesses  
div_by_1_mode;  
GPMC_FCLK_MUX;  
D (4)  
ns  
TIMEPARAGRANULARITY_X1  
FA25 td(csnV-wenV)  
FA27 td(csnV-wenIV)  
FA28 td(wenV-dV)  
FA29 td(dV-csnV)  
FA37 td(oenV-aIV)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
E - 2.1 E + 2.1 ns  
(5)  
(5)  
Delay time, output chip select GPMC_CSn[i](13)  
valid to output write enable GPMC_WEn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
F - 2.1 (6) F + 2.1 ns  
(6)  
Delay time, output write enable GPMC_WEn valid  
to output data GPMC_AD[15:0] valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
2.1 ns  
Delay time, output data GPMC_AD[15:0] valid to  
output chip select GPMC_CSn[i](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
J - 2.1 (9)  
J + 2.1 ns  
(9)  
Delay time, output enable GPMC_OEn_REn valid  
to output address GPMC_AD[15:0] phase end  
div_by_1_mode;  
GPMC_FCLK_MUX;  
2.1 ns  
TIMEPARAGRANULARITY_X1  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
with n being the page burst access number  
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)  
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))  
× GPMC_FCLK(14)  
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)  
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
•
For TIMEPARAGRANULARITY_X1:  
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•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
GPMC_FCLK  
GPMC_CLK  
FA5  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
FA10  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data IN 0  
Data IN 0  
GPMC_WAIT[j]  
GPMC_06  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-44. GPMC and NOR Flash —Asynchronous Read —Single Word  
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GPMC_FCLK  
GPMC_CLK  
GPMC_CSn[i]  
FA5  
FA5  
FA1  
FA1  
FA16  
FA9  
FA9  
Address 0  
FA0  
Address 1  
FA0  
GPMC_A[MSB:1]  
FA10  
FA10  
Valid  
FA0  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
Valid  
FA10  
FA10  
FA3  
FA3  
FA12  
FA12  
GPMC_ADCn_ALE  
FA4  
FA4  
FA13  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data Upper  
GPMC_WAIT[j]  
GPMC_07  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-45. GPMC and NOR Flash —Asynchronous Read —32–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA20  
Add3  
FA20  
Add1  
FA21  
FA20  
Add2  
FA1  
GPMC_CSn[i]  
FA9  
Add0  
Add4  
GPMC_A[MSB:1]  
GPMC_BE0n_CLE  
FA0  
FA10  
FA10  
FA0  
GPMC_BE1n  
FA12  
GPMC_ADVn_ALE  
FA18  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
D3  
D0  
D1  
D2  
D3  
GPMC_WAIT[j]  
GPMC_08  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by  
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.  
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC  
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock  
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first  
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.  
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-46. GPMC and NOR Flash —Asynchronous Read —Page Mode 4x16–Bit  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[i]  
FA9  
GPMC_A[MSB:1]  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid Address  
FA0  
FA10  
FA10  
FA0  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
FA29  
Data OUT  
GPMC_09  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-47. GPMC and NOR Flash —Asynchronous Write —Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
FA5  
GPMC_CSn[i]  
FA9  
Address (MSB)  
FA0  
GPMC_A[27:17]  
FA10  
GPMC_BE0n_CLE  
Valid  
FA0  
FA10  
GPMC_BE1n  
Valid  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
GPMC_10  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-48. GPMC and Multiplexed NOR Flash —Asynchronous Read —Single Word  
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GPMC_FCLK  
GPMC_CLK  
GPMC_CSn[i]  
FA1  
FA9  
GPMC_A[27:17]  
Address (MSB)  
FA0  
FA10  
FA10  
GPMC_BE0n_CLE  
GPMC_BE1n  
FA0  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
FA28  
GPMC_AD[15:0]  
Valid Address (LSB)  
Data OUT  
GPMC_WAIT[j]  
GPMC_11  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-49. GPMC and Multiplexed NOR Flash —Asynchronous Write —Single Word  
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7.10.5.8.3 GPMC and NAND Flash —Asynchronous Mode  
表 7-56 and 表 7-57 present timing requirements and switching characteristics for GPMC and NAND Flash —  
Asynchronous Mode.  
表7-56. GPMC and NAND Flash Timing Requirements –Asynchronous Mode  
see 图7-52  
MIN  
MAX  
NO.  
PARAMETER  
DESCRIPTION  
MODE(4)  
UNIT  
133 MHz  
GNF12(1) tacc(d)  
Access time, input data GPMC_AD[15:0](3)  
div_by_1_mode;  
GPMC_FCLK_MUX;  
J(2) ns  
TIMEPARAGRANULARITY_X1  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
表7-57. GPMC and NAND Flash Switching Characteristics –Asynchronous Mode  
see 图7-50, 图7-51, 图7-52 and 图7-53  
NO.  
PARAMETER  
MODE(4)  
MIN  
MAX UNIT  
GNF0 tw(wenV)  
Pulse duration, output write enable GPMC_WEn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
A
ns  
TIMEPARAGRANULARITY_X1  
GNF1 td(csnV-wenV)  
GNF2 tw(cleH-wenV)  
GNF3 tw(wenV-dV)  
GNF4 tw(wenIV-dIV)  
GNF5 tw(wenIV-cleIV)  
Delay time, output chip select GPMC_CSn[i](2)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
B - 2  
C - 2  
D - 2  
E - 2  
F - 2  
G - 2  
C - 2  
B + 2 ns  
C + 2 ns  
D + 2 ns  
E + 2 ns  
F + 2 ns  
G + 2 ns  
C + 2 ns  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE high to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output data GPMC_AD[15:0] valid to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output data GPMC_AD[15:0] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output lower-byte enable and command  
latch enable GPMC_BE0n_CLE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn  
invalid to output chip select GPMC_CSn[i](2)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
GNF7 tw(aleH-wenV)  
Delay time, output address valid and address latch  
enable GPMC_ADVn_ALE high to output write  
enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
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表7-57. GPMC and NAND Flash Switching Characteristics –Asynchronous Mode (continued)  
see 图7-50, 图7-51, 图7-52 and 图7-53  
NO.  
PARAMETER  
MODE(4)  
MIN  
MAX UNIT  
GNF8 tw(wenIV-aleIV)  
Delay time, output write enable GPMC_WEn  
invalid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
F - 2  
F + 2 ns  
GNF9 tc(wen)  
Cycle time, write  
div_by_1_mode;  
GPMC_FCLK_MUX;  
H
ns  
TIMEPARAGRANULARITY_X1  
GNF10 td(csnV-oenV)  
GNF13 tw(oenV)  
GNF14 tc(oen)  
Delay time, output chip select GPMC_CSn[i](2)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
I - 2  
I + 2 ns  
Pulse duration, output enable GPMC_OEn_REn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
K
ns  
ns  
Cycle time, read  
div_by_1_mode;  
GPMC_FCLK_MUX;  
L
TIMEPARAGRANULARITY_X1  
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn  
invalid to output chip select GPMC_CSn[i](2)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX;  
TIMEPARAGRANULARITY_X1  
M - 2  
M + 2 ns  
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX:  
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
•
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
GPMC_FCLK  
GPMC_CSn[i]  
GNF1  
GNF2  
GNF6  
GNF5  
GPMC_BE0n_CLE  
GPMC_ADCn_ALE  
GPMC_OEn_REn  
GPMC_WEn  
GNF0  
GNF3  
GNF4  
GPMC_AD[15:0]  
Command  
GPMC_12  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-50. GPMC and NAND Flash —Command Latch Cycle  
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GPMC_FCLK  
GNF1  
GNF6  
GNF8  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GNF7  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
GNF9  
GNF0  
GPMC_WEn  
GNF3  
GNF4  
Address  
GPMC_AD[15:0]  
GPMC_13  
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-51. GPMC and NAND Flash —Address Latch Cycle  
GPMC_FCLK  
GPMC_CSn[i]  
GNF12  
GNF10  
GNF15  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF14  
GNF13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
GPMC_WAIT[j]  
DATA  
GPMC_14  
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional  
clock edge. GNF12 value must be stored inside AccessTime register bits field.  
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.  
图7-52. GPMC and NAND Flash —Data Read Cycle  
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GPMC_FCLK  
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GNF1  
GNF6  
GPMC_CSn[i]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
GNF9  
GNF0  
GPMC_WEn  
GNF3  
GNF4  
GPMC_AD[15:0]  
DATA  
GPMC_15  
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.  
图7-53. GPMC and NAND Flash —Data Write Cycle  
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7.10.5.8.4 GPMC0 IOSETs  
表7-58 defines valid pin combinations of each GPMC0 IOSET.  
表7-58. GPMC0 IOSETs  
IOSET1  
IOSET2  
BALL NAME  
GPMC0_AD0  
SIGNALS  
BALL NAME  
GPMC0_AD0  
MUXMODE  
MUXMODE  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_CLK  
GPMC0_CLKLB  
GPMC0_ADVn_ALE  
GPMC0_OEn_REn  
GPMC0_WEn  
GPMC0_BE0n_CLE  
GPMC0_BE1n  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_WPn  
GPMC0_DIR  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
GPMC0_AD1  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_CLK  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_CLK  
GPMC0_CLKLB  
GPMC0_ADVn_ALE  
GPMC0_OEn_REn  
GPMC0_WEn  
GPMC0_CLKLB  
GPMC0_ADVn_ALE  
GPMC0_OEn_REn  
GPMC0_WEn  
GPMC0_BE0n_CLE  
GPMC0_BE1n  
GPMC0_BE0n_CLE  
GPMC0_BE1n  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_WPn  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_WPn  
GPMC0_DIR  
GPMC0_DIR  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_AD16  
GPMC0_AD17  
GPMC0_AD18  
GPMC0_AD19  
GPMC0_AD20  
GPMC0_AD21  
GPMC0_AD22  
GPMC0_AD23  
GPMC0_AD24  
GPMC0_AD25  
GPMC0_AD26  
GPMC0_CSn0  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_CSn3  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
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表7-58. GPMC0 IOSETs (continued)  
IOSET1  
IOSET2  
SIGNALS  
GPMC0_AD27  
BALL NAME  
MUXMODE  
BALL NAME  
MUXMODE  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO17  
GPMC0_CSn3  
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_MDIO0_MDIO  
PRG0_MDIO0_MDC  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO17  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO6  
PRG1_PRU1_GPO17  
GPMC0_CSn3  
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
8
4
4
4
GPMC0_AD28  
GPMC0_AD29  
GPMC0_AD30  
GPMC0_AD31  
GPMC0_BE2n  
GPMC0_A0  
GPMC0_A1  
GPMC0_A2  
GPMC0_A3  
GPMC0_A4  
GPMC0_A5  
GPMC0_A6  
GPMC0_A7  
GPMC0_A8  
GPMC0_A9  
GPMC0_A10  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
GPMC0_BE3n  
GPMC0_A20  
GPMC0_A21  
GPMC0_A22  
GPMC0_WAIT1  
GPMC0_WAIT1  
GPMC0_WPn  
GPMC0_WPn  
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7.10.5.9 I2C  
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was  
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not fully  
compliant to the I2C electrical specification. The speeds supported and exceptions are described per port below:  
• MCU_I2C1, I2C1, I2C2, and I2C3  
– Speeds:  
• Standard-mode (up to 100 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Fast-mode (up to 400 Kbits/s)  
– 1.8 V  
– 3.3 V  
– Exceptions:  
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C  
specification because they are implemented with higher performance LVCMOS push-pull IOs that were  
designed to support other signal functions that could not be implemented with I2C compatible IOs. The  
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This  
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z  
state.  
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the  
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals  
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.  
• MCU_I2C0 and I2C0  
– Speeds:  
• Standard-mode (up to 100 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Fast-mode (up to 400 Kbits/s)  
– 1.8 V  
– 3.3 V  
• Hs-mode (up to 3.4 Mbit/s)  
– 1.8 V  
– Exceptions:  
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So  
Hs-mode is limited to 1.8-V operation.  
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8  
V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C  
specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow  
the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.  
• The I2C specification defines a maximum input voltage VIH of (VDD + 0.5 V), which exceeds the  
absolute maximum ratings for the device IOs. The system must bemdaex signed to ensure the I2C signals  
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.  
Refer to the Philips I2C-bus specification version 2.1 for timing details.  
For more details about features and additional description information on the device Inter-Integrated Circuit, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
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7.10.5.10 MCAN  
表7-59 and 表7-60 presents timing conditions and switching characteristics for MCAN.  
For more details about features and additional description information on the device Controller Area Network  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
备注  
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,  
where n represents the specific MCAN module.  
表7-59. MCAN Timing Conditions  
PARAMETER  
MIN  
2
MAX  
15  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
5
20  
表7-60. MCAN Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
Delay time, transmit shift register to MCANn_TX  
Delay time, MCANn_RX to receive shift register  
MIN  
MAX  
10  
UNIT  
ns  
MCAN1 td(MCAN_TX)  
MCAN2 td(MCAN_RX)  
10  
ns  
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.  
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7.10.5.11 MCSPI  
For more details about features and additional description information on the device Serial Port Interface, see  
the corresponding subsections within Signal Descriptions and Detailed Description sections.  
表7-61 presents timing conditions for MCSPI.  
表7-61. MCSPI Timing Conditions  
PARAMETER  
MIN  
2
MAX  
8.5  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
6
12  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
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7.10.5.11.1 MCSPI —Controller Mode  
表 7-62, 图 7-54, 表 7-63, and 图 7-55 present timing requirements and switching characteristics for SPI –  
Controller Mode.  
表7-62. MCSPI Timing Requirements –Controller Mode  
see 图7-54  
NO.  
SM4  
SM5  
PARAMETER  
DESCRIPTION  
MIN  
2.8  
3
MAX  
UNIT  
ns  
tsu(POCI-SPICLK)  
Setup time, SPIn_D[x] valid before SPIn_CLK active edge  
Hold time, SPIn_D[x] valid after SPIn_CLK active edge  
th(SPICLK-POCI)  
ns  
PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SM5  
SM5  
SM4  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM2  
SM1  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SM5  
SM4  
SM5  
Bit n-2  
SM4  
Bit n-1  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_02  
图7-54. MCSPI Controller Mode Receive Timing  
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表7-63. MCSPI Switching Characteristics - Controller Mode  
see 图7-55  
NO.  
PARAMETER  
MIN  
20  
0.5P - 1(1)  
0.5P - 1(1)  
-3  
MAX UNIT  
SM1  
SM2  
SM3  
SM6  
SM7  
SM8  
tc(SPICLK)  
Cycle time, SPIn_CLK  
ns  
ns  
ns  
tw(SPICLKL)  
Pulse duration, SPIn_CLK low  
tw(SPICLKH)  
td(SPICLK-PICO)  
td(CS-PICO)  
Pulse duration, SPIn_CLK high  
Delay time, SPIn_CLK active edge to SPIn_D[x]  
Delay time, SPIn_CSi active edge to SPIn_D[x]  
Delay time, SPIn_CSi active to SPIn_CLK first edge  
2.5  
ns  
ns  
ns  
ns  
ns  
ns  
5
td(CS-SPICLK)  
PHA = 0  
PHA = 1  
PHA = 0  
PHA = 1  
B - 4 (3)  
A - 4 (2)  
A - 4(2)  
B - 4(3)  
SM9  
td(SPICLK-CS)  
Delay time, SPIn_CLK last edge to SPIn_CSi inactive  
(1) P = SPI_CLK period in ns.  
(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =  
(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.  
(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.  
PHA=0  
EPOL=1  
SPI_CS[i] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SPI_D[x] (OUT)  
SM7  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
SPI_CS[i] (OUT)  
SPI_SCLK (OUT)  
SM1  
SM2  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SPI_D[x] (OUT)  
SM6  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
SM6  
Bit 1  
Bit0  
SPRSP08_TIMING_McSPI_01  
图7-55. MCSPI Controller Mode Transmit Timing  
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7.10.5.11.2 MCSPI —Peripheral Mode  
表 7-64, 图 7-56, 表 7-65, and 图 7-57 present timing requirements and switching characteristics for SPI –  
Peripheral Mode.  
表7-64. MCSPI Timing Requirements –Peripheral Mode  
see 图7-56  
NO.  
SS1  
SS2  
SS3  
SS4  
SS5  
SS8  
SS9  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
tc(SPICLK)  
Cycle time, SPIn_CLK  
20  
0.45P(1)  
0.45P(1)  
tw(SPICLKL)  
Pulse duration, SPIn_CLK low  
ns  
tw(SPICLKH)  
Pulse duration, SPIn_CLK high  
ns  
tsu(PICO-SPICLK)  
th(SPICLK-PICO)  
tsu(CS-SPICLK)  
th(SPICLK-CS)  
Setup time, SPIn_D[x] valid before SPIn_CLK active edge  
Hold time, SPIn_D[x] valid after SPIn_CLK active edge  
Setup time, SPIn_CSi valid before SPIn_CLK first edge  
Hold time, SPIn_CSi valid after SPIn_CLK last edge  
5
5
5
5
ns  
ns  
ns  
ns  
(1) P = SPIn_CLK period in ns.  
PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS2  
POL=1  
SPI_SCLK (IN)  
SS5  
SS4  
SS5  
Bit n-2  
SS4  
Bit n-1  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[i] (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS3  
POL=1  
SPI_SCLK (IN)  
SS4  
SS5  
SS4  
SS5  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_04  
图7-56. SPI Peripheral Mode Receive Timing  
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表7-65. MCSPI Switching Characteristics –Peripheral Mode  
see 图7-57  
NO.  
PARAMETER  
td(SPICLK-POCI)  
tsk(CS-POCI)  
DESCRIPTION  
Delay time, SPIn_CLK active edge to SPIn_D[x]  
Delay time, SPIn_CSi active edge to SPIn_D[x]  
MIN  
2
MAX  
17.12  
UNIT  
ns  
SS6  
SS7  
20.95  
ns  
PHA=0  
EPOL=1  
SPI_CS[i] (IN)  
SPI_SCLK (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
POL=1  
SS1  
SS2  
SPI_SCLK (IN)  
SPI_D[x] (OUT)  
SS7  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
SPI_CS[i] (IN)  
SPI_SCLK (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
POL=1  
SS1  
SS3  
SPI_SCLK (IN)  
SPI_D[x] (OUT)  
SS6  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
SS6  
Bit 1  
Bit 0  
SPRSP08_TIMING_McSPI_03  
图7-57. SPI Peripheral Mode Transmit Timing  
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7.10.5.12 MMCSD  
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),  
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at  
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking  
for syntactical correctness.  
For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal  
Descriptions and Detailed Description sections.  
备注  
Some operating modes require software configuration of the MMC DLL delay settings, as shown in 表  
7-66 and 表7-75.  
The modes which show a value of "Tuning" in the ITAPDLYSEL column of 表7-66 and 表7-75 require  
a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming Guide in  
the device TRM for more information on the tuning algorithm and configuration of input delays  
required to optimize input timing.  
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in  
the device TRM.  
7.10.5.12.1 MMC0 - eMMC Interface  
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and supports the  
following eMMC applications:  
• Legacy speed  
• High speed SDR  
• High speed DDR  
• HS200  
表7-66 presents the required DLL software configuration settings for MMC0 timing modes.  
表7-66. MMC0 DLL Delay Mapping for all Timing Modes  
REGISTER NAME  
MMCSD0_SS_PHY_CTRL_4_REG  
MMCSD0_SS_PHY_CTRL_5_REG  
BIT FIELD  
[31:24]  
[20]  
[15:12]  
[8]  
[4:0]  
[17:16]  
[10:8]  
[2:0]  
SELDLYTXCLK  
SELDLYRXCLK  
BIT FIELD NAME  
STRBSEL  
OTAPDLYENA  
OTAPDLYSEL  
ITAPDLYENA  
ITAPDLYSEL  
FRQSEL  
CLKBUFSEL  
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL  
DELAY CHAIN  
SELECT  
DELAY  
BUFFER  
DURATION  
STROBE  
DELAY  
DLL REF  
FREQUENCY  
MODE DESCRIPTION  
8-bit PHY  
Legacy  
operating 1.8 V,  
SDR  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x1  
0x1  
NA(1)  
NA(1)  
0x6  
0x1  
0x1  
0x1  
0x1  
0x10  
0xA  
0x1  
0x1  
0x0  
0x0  
0x0  
0x0  
0x4  
0x0  
0x7  
0x7  
0x7  
0x7  
25 MHz  
High  
8-bit PHY  
Speed operating 1.8 V,  
SDR  
High  
50 MHz  
8-bit PHY  
Speed operating 1.8 V,  
0x3  
DDR  
50 MHz  
8-bit PHY  
HS200 operating 1.8 V,  
200 MHz  
0x7  
Tuning(2)  
(1) NA means Not Applicable  
(2) Tuning means this mode requires a tuning algorithm to optimize input timing  
表7-67 presents timing conditions for MMC0.  
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表7-67. MMC0 Timing Conditions  
PARAMETER  
MIN  
INPUT CONDITIONS  
Legacy SDR  
0.14  
0.3  
1.44 V/ns  
0.9 V/ns  
0.9 V/ns  
0.9 V/ns  
High Speed SDR  
SRI  
Input slew rate  
High Speed DDR (CMD)  
High Speed DDR (DAT[7:0])  
0.3  
0.45  
OUTPUT CONDITIONS  
Legacy SDR  
1
1
1
1
12  
12  
12  
6
pF  
pF  
pF  
pF  
High Speed SDR  
CL  
Output load capacitance  
High Speed DDR  
HS200  
PCB CONNECTIVITY REQUIREMENTS  
All modes  
td(Trace Delay)  
Propagation delay of each trace  
126  
756  
100  
8
ps  
ps  
ps  
Legacy SDR, High Speed SDR  
High Speed DDR, HS200  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
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7.10.5.12.1.1 Legacy SDR Mode  
表 7-68, 图 7-58, 表 7-69, and 图 7-59 present timing requirements and switching characteristics for MMC0 –  
Legacy SDR Mode.  
表7-68. MMC0 Timing Requirements –Legacy SDR Mode  
see 图7-58  
NO.  
MIN  
9.69  
MAX  
UNIT  
ns  
LSDR1 tsu(cmdV-clkH)  
LSDR2 th(clkH-cmdV)  
LSDR3 tsu(dV-clkH)  
LSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
27.97  
9.69  
ns  
ns  
27.97  
ns  
图7-58. MMC0 –Legacy SDR –Receive Mode  
表7-69. MMC0 Switching Characteristics –Legacy SDR Mode  
see 图7-59  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
25  
LSDR5  
LSDR6  
LSDR7  
LSDR8  
LSDR9  
tc(clk)  
Cycle time, MMC0_CLK  
40  
18.7  
tw(clkH)  
Pulse duration, MMC0_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC0_CLK low  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
-16.1  
-16.1  
16.1  
16.1  
ns  
ns  
图7-59. MMC0 –Legacy SDR –Transmit Mode  
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7.10.5.12.1.2 High Speed SDR Mode  
表 7-70, 图 7-60, 表 7-71, and 图 7-61 present timing requirements and switching characteristics for MMC0 –  
High Speed SDR Mode.  
表7-70. MMC0 Timing Requirements –High Speed SDR Mode  
see 图7-60  
NO.  
MIN  
2.99  
2.67  
2.99  
2.67  
MAX  
UNIT  
ns  
HSSDR1 tsu(cmdV-clkH)  
HSSDR2 th(clkH-cmdV)  
HSSDR3 tsu(dV-clkH)  
HSSDR4 th(clkH-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge  
ns  
ns  
ns  
图7-60. MMC0 –High Speed SDR Mode –Receive Mode  
表7-71. MMC0 Switching Characteristics –High Speed SDR Mode  
see 图7-61  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
HSSDR5 tc(clk)  
Operating frequency, MMC0_CLK  
50  
Cycle time, MMC0_CLK  
20  
9.2  
HSSDR6 tw(clkH)  
HSSDR7 tw(clkL)  
HSSDR8 td(clkL-cmdV)  
HSSDR9 td(clkL-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
9.2  
ns  
Delay time, MMC0_CLK falling edge to MMC0_CMD transition  
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition  
-6.35  
-6.35  
6.35  
6.35  
ns  
ns  
图7-61. MMC0 –High Speed SDR Mode –Transmit Mode  
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7.10.5.12.1.3 High Speed DDR Mode  
表 7-72, 图 7-62, 表 7-73, and 图 7-63 present timing requirements and switching characteristics for MMC0 –  
High Speed DDR Mode.  
表7-72. MMC0 Timing Requirements –High Speed DDR Mode  
see 图7-62  
NO.  
MIN  
3.88  
2.67  
0.83  
1.76  
MAX  
UNIT  
ns  
HSDDR1 tsu(cmdV-clk)  
HSDDR2 th(clk-cmdV)  
HSDDR3 tsu(dV-clk)  
HSDDR4 th(clk-dV)  
Setup time, MMC0_CMD valid before MMC0_CLK rising edge  
Hold time, MMC0_CMD valid after MMC0_CLK rising edge  
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition  
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition  
ns  
ns  
ns  
图7-62. MMC0 –High Speed DDR Mode –Receive Mode  
表7-73. MMC0 Switching Characteristics –High Speed DDR Mode  
see 图7-63  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
HSDDR5 tc(clk)  
Operating frequency, MMC0_CLK  
50  
Cycle time, MMC0_CLK  
20  
9.2  
HSDDR6 tw(clkH)  
HSDDR7 tw(clkL)  
HSDDR8 td(clk-cmdV)  
HSDDR9 td(clk-dV)  
Pulse duration, MMC0_CLK high  
ns  
Pulse duration, MMC0_CLK low  
9.2  
ns  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition  
3.31  
2.81  
16.19  
6.94  
ns  
ns  
图7-63. MMC0 –High Speed DDR Mode –Transmit Mode  
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7.10.5.12.1.4 HS200 Mode  
表7-74 and 图7-64 present switching characteristics for MMC0 –HS200 Mode.  
表7-74. MMC0 Switching Characteristics –HS200 Mode  
see 图7-64  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC0_CLK  
200  
HS2005  
HS2006  
HS2007  
HS2008  
HS2009  
tc(clk)  
Cycle time, MMC0_CLK  
5
2.08  
2.08  
0.99  
0.99  
tw(clkH)  
Pulse duration, MMC0_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC0_CLK low  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC0_CLK rising edge to MMC0_CMD transition  
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition  
3.28  
3.28  
ns  
ns  
图7-64. MMC0 –HS200 Mode –Transmit Mode  
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7.10.5.12.2 MMC1 - SD/SDIO Interface  
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer  
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:  
• Default speed  
• High speed  
• UHS–I SDR12  
• UHS–I SDR25  
• UHS–I SDR50  
• UHS–I SDR104  
• UHS–I DDR50  
表7-75 presents the required DLL software configuration settings for MMC1 timing modes.  
表7-75. MMC1 DLL Delay Mapping for all Timing Modes  
REGISTER NAME  
BIT FIELD  
MMCSD1_SS_PHY_CTRL_4_REG  
[15:12] [8]  
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL  
MMCSD1_SS_PHY_CTRL_5_REG  
[20]  
[4:0]  
[2:0]  
BIT FIELD NAME  
CLKBUFSEL  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DELAY  
BUFFER  
DURATION  
DELAY  
ENABLE  
DELAY  
VALUE  
MODE  
DESCRIPTION  
Default  
Speed  
4-bit PHY operating  
3.3 V, 25 MHz  
0x0  
0x0  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x0  
0xF  
0xF  
0xC  
0x9  
0x6  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x0  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
High  
Speed  
4-bit PHY operating  
3.3 V, 50 MHz  
UHS-I  
SDR12  
4-bit PHY operating  
1.8 V, 25 MHz  
0x0  
UHS-I  
SDR25  
4-bit PHY operating  
1.8 V, 50 MHz  
0x0  
UHS-I  
SDR50  
4-bit PHY operating  
1.8 V, 100 MHz  
Tuning(1)  
Tuning(1)  
Tuning(1)  
UHS-I  
DR50  
4-bit PHY operating  
1.8 V, 50 MHz  
UHS-I  
SDR104  
4-bit PHY operating  
1.8, V 200 MHz  
(1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing  
表7-76 presents timing conditions for MMC1.  
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表7-76. MMC1 Timing Conditions  
PARAMETER  
MIN  
Input Conditions  
Default Speed, High Speed  
UHS–I SDR12, UHS–I SDR25  
UHS–I DDR50  
0.69  
0.34  
1
2.06 V/ns  
1.34 V/ns  
SRI  
Input slew rate  
2
V/ns  
Output Conditions  
3
1
10  
10  
pF  
pF  
UHS–I DDR50  
CL  
Output load capacitance  
All other modes  
PCB Connectivity Requirements  
240  
126  
1134  
1386  
20  
ps  
ps  
ps  
ps  
UHS–I DDR50  
td(Trace Delay)  
Propagation delay of each trace  
All other modes  
UHS–I DDR50, UHS–I SDR104  
All other modes  
td(Trace Mismatch  
Propagation delay mismatch across all  
traces  
Delay)  
100  
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7.10.5.12.2.1 Default Speed Mode  
表 7-77, 图 7-65, 表 7-78, and 图 7-66 present timing requirements and switching characteristics for MMC1 –  
Default Speed Mode.  
表7-77. Timing Requirements for MMC1 –Default Speed Mode  
see 图7-65  
NO.  
DS1  
DS2  
DS3  
DS4  
MIN  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC1_CMD valid before MMCi_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
2.55  
19.67  
2.55  
ns  
ns  
19.67  
ns  
MMC[x]_CLK  
DS2  
DS4  
DS1  
DS3  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-65. MMC1 –Default Speed –Receive Mode  
表7-78. Switching Characteristics for MMC1 –Default Speed Mode  
see 图7-66  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
25  
DS5  
DS6  
DS7  
DS8  
DS9  
tc(clk)  
Cycle time, MMC1_CLK  
40  
18.7  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
18.7  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
- 14.1  
- 14.1  
14.1  
14.1  
ns  
ns  
DS5  
DS6  
DS7  
MMC[x]_CLK  
MMC[x]_CMD  
DS8  
DS9  
MMC[x]_DAT[3:0]  
图7-66. MMC1 –Default Speed –Transmit Mode  
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7.10.5.12.2.2 High Speed Mode  
表 7-79, 图 7-67, 表 7-80, and 图 7-68 present timing requirements and switching characteristics for MMC1 –  
High Speed Mode.  
表7-79. Timing Requirements for MMC1 –High Speed Mode  
see 图7-67  
NO.  
HS1  
HS2  
HS3  
HS4  
MIN  
2.55  
2.67  
2.55  
2.67  
MAX  
UNIT  
ns  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clkH)  
th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
ns  
ns  
MMC[x]_CLK  
HS1  
HS3  
HS2  
HS4  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-67. MMC1 –High Speed –Receive Mode  
表7-80. Switching Characteristics for MMC1 –High Speed Mode  
see 图7-68  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
50  
HS5  
HS6  
HS7  
HS8  
HS9  
tc(clk)  
Cycle time. MMC1_CLK  
20  
9.2  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
9.2  
ns  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMC1_CLK falling edge to MMC1_CMD transition  
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition  
-7.35  
-7.35  
3.35  
3.35  
ns  
ns  
HS5  
HS6  
HS7  
MMC[x]_CLK  
HS8  
HS9  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-68. MMC1 –High Speed –Transmit Mode  
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7.10.5.12.2.3 UHS–I SDR12 Mode  
表 7-81, 图 7-69, 表 7-82, and 图 7-70 present timing requirements and switching characteristics for MMC1 –  
UHS-I SDR12 Mode.  
表7-81. Timing Requirements for MMC1 –UHS-I SDR12 Mode  
see 图7-69  
NO.  
MIN  
21.65  
1.67  
MAX  
UNIT  
ns  
SDR121 tsu(cmdV-clkH)  
SDR122 th(clkH-cmdV)  
SDR123 tsu(dV-clkH)  
SDR124 th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
21.65  
1.67  
ns  
ns  
MMC[x]_CLK  
SDR122  
SDR124  
SDR121  
SDR123  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-69. MMC1 –UHS-I SDR12 –Receive Mode  
表7-82. Switching Characteristics for MMC1 –UHS-I SDR12 Mode  
see 图7-70  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
25  
SDR125 tc(clk)  
Cycle time, MMC1_CLK  
40  
18.7  
SDR126 tw(clkH)  
SDR127 tw(clkL)  
SDR128 td(clkL-cmdV)  
SDR129 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
18.7  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
-13.6  
-13.6  
13.6  
13.6  
ns  
ns  
SDR125  
SDR126  
SDR127  
MMC[x]_CLK  
SDR128  
SDR128  
MMC[x]_CMD  
SDR129  
SDR129  
MMC[x]_DAT[3:0]  
图7-70. MMC1 –UHS-I SDR12 –Transmit Mode  
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7.10.5.12.2.4 UHS–I SDR25 Mode  
表 7-83, 图 7-71, 表 7-84, and 图 7-72 present timing requirements and switching characteristics for MMC1 –  
UHS-I SDR25 Mode.  
表7-83. Timing Requirements for MMC1 –UHS-I SDR25 Mode  
see 图7-71  
NO.  
MIN  
2.15  
1.67  
2.15  
1.67  
MAX  
UNIT  
ns  
SDR251 tsu(cmdV-clkH)  
SDR252 th(clkH-cmdV)  
SDR253 tsu(dV-clkH)  
SDR254 th(clkH-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge  
ns  
ns  
ns  
MMC[x]_CLK  
SDR252  
SDR254  
SDR251  
SDR253  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-71. MMC1 –UHS-I SDR25 –Receive Mode  
表7-84. Switching Characteristics for MMC1 –UHS-I SDR25 Mode  
see 图7-72  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
50  
SDR255 tc(clk)  
Cycle time, MMC1_CLK  
20  
9.2  
SDR256 tw(clkH)  
SDR257 tw(clkL)  
SDR258 td(clkL-cmdV)  
SDR259 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
9.2  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
-7.1  
-7.1  
3.1  
3.1  
ns  
ns  
SDR255  
SDR256  
SDR257  
MMC[x]_CLK  
SDR258  
SDR258  
MMC[x]_CMD  
SDR259  
SDR259  
MMC[x]_DAT[3:0]  
图7-72. MMC1 –UHS-I SDR25 –Transmit Mode  
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7.10.5.12.2.5 UHS–I SDR50 Mode  
表7-85, and 图7-73 presents switching characteristics for MMC1 –UHS-I SDR50 Mode.  
表7-85. Switching Characteristics for MMC1 –UHS-I SDR50 Mode  
see 图7-73  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
100  
SDR505 tc(clk)  
Cycle time, MMC1_CLK  
10  
4.45  
4.45  
1.2  
SDR506 tw(clkH)  
SDR507 tw(clkL)  
SDR508 td(clkL-cmdV)  
SDR509 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
6.35  
6.35  
ns  
1.2  
ns  
SDR505  
SDR506  
SDR507  
MMC[x]_CLK  
SDR508  
SDR508  
MMC[x]_CMD  
SDR509  
SDR509  
MMC[x]_DAT[3:0]  
图7-73. MMC1 –UHS-I SDR50 –Transmit Mode  
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7.10.5.12.2.6 UHS–I DDR50 Mode  
表 7-86, 图 7-74, 表 7-87, and 图 7-75 present timing requirements and switching characteristics for MMC1 –  
UHS-I DDR50 Mode.  
表7-86. Timing Requirements for MMC1 –UHS-I DDR50 Mode  
see 图7-74  
NO.  
MIN  
2.99  
1.91  
-0.06  
1.91  
MAX  
UNIT  
ns  
DDR501  
DDR502  
DDR503  
DDR504  
tsu(cmdV-clk)  
th(clk-cmdV)  
tsu(dV-clk)  
th(clk-dV)  
Setup time, MMC1_CMD valid before MMC1_CLK rising edge  
Hold time, MMC1_CMD valid after MMC1_CLK rising edge  
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition  
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition  
ns  
ns  
ns  
MMC[x]_CLK  
MMC[x]_CMD  
DDR501  
DDR502  
DDR503  
DDR504  
DDR503  
DDR504  
MMC[x]_DAT[3:0]  
图7-74. MMC1 –UHS-I DDR50 –Receive Mode  
表7-87. Switching Characteristics for MMC1 –UHS-I DDR50 Mode  
see 图7-75  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
tc(clk)  
Operating frequency, MMC1_CLK  
50  
DDR505  
DDR506  
DDR507  
DDR508  
DDR509  
Cycle time, MMC1_CLK  
20  
9.2  
9.2  
1.2  
1.2  
tw(clkH)  
Pulse duration, MMC1_CLK high  
ns  
tw(clkL)  
Pulse duration, MMC1_CLK low  
ns  
td(clk-cmdV)  
td(clk-dV)  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition  
13.1  
6.35  
ns  
ns  
DDR505  
DDR506  
DDR507  
MMC[x]_CLK  
MMC[x]_CMD  
DDR508  
DDR509  
DDR509  
MMC[x]_DAT[3:0]  
图7-75. MMC1 –UHS-I DDR50 –Transmit Mode  
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7.10.5.12.2.7 UHS–I SDR104 Mode  
表7-88, and 图7-76 present switching characteristics for MMC1 –UHS-I SDR104 Mode.  
表7-88. Switching Characteristics for MMC1 –UHS-I SDR104 Mode  
see 图7-76  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
MHz  
ns  
fop(clk)  
Operating frequency, MMC1_CLK  
200  
SDR1045 tc(clk)  
Cycle time, MMC1_CLK  
5
2.08  
2.08  
1.12  
1.12  
SDR1046 tw(clkH)  
SDR1047 tw(clkL)  
SDR1048 td(clkL-cmdV)  
SDR1049 td(clkL-dV)  
Pulse duration, MMC1_CLK high  
ns  
Pulse duration, MMC1_CLK low  
ns  
Delay time, MMC1_CLK rising edge to MMC1_CMD transition  
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition  
3.16  
3.16  
ns  
ns  
SDR1045  
SDR1046  
SDR1047  
MMC[x]_CLK  
SDR1048  
SDR1048  
MMC[x]_CMD  
SDR1049  
SDR1049  
MMC[x]_DAT[3:0]  
图7-76. MMC1 –UHS-I SDR104 –Transmit Mode  
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7.10.5.13 CPTS  
表 7-89, 表 7-90, 图 7-77, 表 7-91, and 图 7-78 present timing conditions, requirements, and switching  
characteristics for CPTS.  
表7-89. CPTS Timing Conditions  
PARAMETER  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
表7-90. CPTS Timing Requirements  
see 图7-77  
NO.  
T1  
T2  
T3  
T4  
T5  
PARAMETER  
DESCRIPTION  
Pulse duration, HWnTSPUSH high  
MIN  
12P(1) + 2  
12P(1) + 2  
5
MAX  
UNIT  
ns  
tw(HWTSPUSHH)  
tw(HWTSPUSHL)  
tc(RFT_CLK)  
Pulse duration, HWnTSPUSH low  
Cycle time, RFT_CLK  
ns  
8
ns  
tw(RFT_CLKH)  
tw(RFT_CLKL)  
Pulse duration, RFT_CLK high  
Pulse duration, RFT_CLK low  
0.45T(2)  
0.45T(2)  
ns  
ns  
(1) P = functional clock period in ns.  
(2) T = RFT_CLK period in ns.  
T1  
T2  
HWn_TSPUSH  
RFT_CLK  
T3  
T4  
T5  
图7-77. CPTS Timing Requirements  
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表7-91. CPTS Switching Characteristics  
see 图7-78  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, TS_COMP high  
SOURCE  
MIN  
36P(1) - 2  
36P(1) - 2  
36P(1) - 2  
36P(1) - 2  
36P(1) - 2  
5P(1) - 2  
MAX UNIT  
T6  
tw(TS_COMPH)  
tw(TS_COMPL)  
tw(TS_SYNCH)  
tw(TS_SYNCL)  
tw(SYNC_OUTH)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T7  
Pulse duration, TS_COMP low  
Pulse duration, TS_SYNC high  
Pulse duration, TS_SYNC low  
Pulse duration, SYNCn_OUT high  
T8  
T9  
T10  
TS_SYNC  
GENF  
T11  
tw(SYNC_OUTL)  
Pulse duration, SYNCn_OUT low  
TS_SYNC  
GENF  
36P(1) - 2  
5P(1) - 2  
(1) P = functional clock period in ns.  
T6  
T7  
TS_COMP  
T8  
T9  
TS_SYNC  
T10  
T11  
SYNCn_OUT  
图7-78. CPTS Switching Characteristics  
For more information, see Data Movement Architecture (DMA) chapter in the device TRM.  
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7.10.5.14 OSPI  
OSPI0 offers two data capture modes, PHY mode and Tap mode.  
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each  
reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle  
of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the  
receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data  
capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the  
OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO  
looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS  
output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when  
using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the  
Internal PHY Loopback or Internal Pad Loopback clocking topologies.  
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture  
delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide  
by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the  
receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture  
clock. This clocking topology supports a maximum internal reference clock rate of 200 MHz, which produces an  
OSPI0_CLK rate up to 50 MHz for SDR mode or 25 MHz for DDR mode.  
For more details about features and additional description information on the device Octal Serial Peripheral  
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
节 7.10.5.14.1 defines timing requirements and switching characteristics associated with PHY mode and 节  
7.10.5.14.2 defines timing requirements and switching characteristics associated with Tap mode.  
表7-92 presents timing conditions for OSPI0.  
表7-92. OSPI0 Timing Conditions  
PARAMETER  
MODE  
MIN  
1
MAX UNIT  
INPUT CONDITIONS  
SRI Input slew rate  
OUTPUT CONDITIONS  
6
V/ns  
pF  
CL  
Output load capacitance  
3
10  
PCB CONNECTIVITY REQUIREMENTS  
No Loopback  
Propagation delay of OSPI0_CLK trace  
Internal PHY Loopback  
Internal Pad Loopback  
450  
ps  
td(Trace Delay)  
Propagation delay of OSPI0_LBCLKO  
trace  
External Board Loopback  
DQS  
2L(1) - 30  
L(1) - 30  
2L(1) + 30  
L(1) + 30  
ps  
ps  
Propagation delay of OSPI0_DQS trace  
Propagation delay mismatch of  
OSPI0_D[7:0] and OSPI0_CSn[3:0]  
relative to OSPI0_CLK  
td(Trace Mismatch  
All modes  
60  
ps  
Delay)  
(1) L = Propagation delay of OSPI0_CLK trace  
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device  
TRM.  
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7.10.5.14.1 OSPI0 PHY Mode  
7.10.5.14.1.1 OSPI0 With PHY Data Training  
Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating  
frequency. A data training method may be implemented to dynamically configure optimal read and write timing.  
Implementing data training enables proper operation across temperature with a specific process, voltage, and  
frequency operating condition, while achieving a higher operating frequency.  
Data transmit and receive timing parameters are not defined for the data training use case since they are  
dynamically adjusted based on the operating condition.  
表7-93 defines DLL delays required for OSPI0 with Data Training. 表7-94, 图7-79 表7-95, and 图7-80 present  
timing requirements and switching characteristics for OSPI0 with Data Training.  
表7-93. OSPI0 DLL Delay Mapping for PHY Data Training  
MODE  
OSPI_PHY_CONFIGURATION_REG BIT FIELD  
PHY_CONFIG_TX_DLL_DELAY_FLD,  
DELAY VALUE  
Transmit  
All modes  
Receive  
(1)  
(2)  
All modes  
PHY_CONFIG_RX_DLL_DELAY_FLD  
(1) Transmit DLL delay value determined by training software  
(2) Receive DLL delay value determined by training software  
表7-94. OSPI0 Timing Requirements –PHY Data Training  
see 图7-79  
NO.  
MODE  
MIN  
MAX UNIT  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_DQS edge  
(1)  
O15 tsu(D-LBCLK)  
O16 th(LBCLK-D)  
DDR with DQS  
ns  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_DQS edge  
(1)  
DDR with DQS  
ns  
(1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum  
data valid window.  
OSPI_DQS  
O15 O16 O15 O16  
OSPI_D[i:0]  
OSPI_TIMING_04  
图7-79. OSPI0 Timing Requirements –PHY Data Training, DDR with DQS  
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表7-95. OSPI Switching Characteristics –PHY Data Training  
See 图7-80  
NO.  
PARAMETER  
MODE  
1.8V, DDR  
3.3V, DDR  
DDR  
MIN  
6.02  
MAX UNIT  
ns  
ns  
ns  
ns  
O1  
tc(CLK)  
Cycle time, OSPI0_CLK  
7.52  
O2  
O3  
tw(CLKL)  
tw(CLKH)  
Pulse duration, OSPI0_CLK low  
Pulse duration, OSPI0_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
DDR  
((0.475P(1)) +  
(0.975M(2)R(4)) +  
(0.04TD(5)) - 1)  
((0.525P(1)) +  
Delay time, OSPI0_CSn[3:0] active edge  
to OSPI0_CLK rising edge  
O4  
td(CSn-CLK)  
DDR  
(1.025M(2)R(4)) +  
(0.11TD(5)) + 1)  
ns  
((0.475P(1)) +  
(0.975N(3)R(4)) -  
(0.04TD(5)) - 1)  
((0.525P(1)) +  
(1.025N(3)R(4)) -  
(0.11TD(5)) + 1)  
Delay time, OSPI0_CLK rising edge to  
OSPI0_CSn[3:0] inactive edge  
O5  
O6  
td(CLK-CSn)  
DDR  
DDR  
ns  
ns  
Delay time, OSPI0_CLK active edge to  
OSPI0_D[7:0] transition  
(6)  
(6)  
td(CLK-D)  
(1) P = OSPI0_CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD  
(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data  
valid window.  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
OSPI_D[i:0]  
O2  
O6  
O6  
O1  
OSPI_TIMING_01  
图7-80. OSPI0 Switching Characteristics –PHY DDR Data Training  
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7.10.5.14.1.2 OSPI0 Without Data Training  
备注  
Timing parameters defined in this section are only applicable when data training is not implemented  
and DLL delays are configured as described in 表7-96 and 表7-99.  
7.10.5.14.1.2.1 OSPI0 PHY SDR Timing  
表 7-96 defines DLL delays required for OSPI0 PHY SDR Mode. 表 7-97, 图 7-81, 图 7-82, 表 7-98, and 图 7-83  
present timing requirements and switching characteristics for OSPI0 PHY SDR Mode.  
表7-96. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes  
MODE  
OSPI_PHY_CONFIGURATION_REG BIT FIELD  
DELAY VALUE  
Transmit  
All modes  
Receive  
PHY_CONFIG_TX_DLL_DELAY_FLD,  
0x0  
0x0  
All modes  
PHY_CONFIG_RX_DLL_DELAY_FLD  
表7-97. OSPI0 Timing Requirements –PHY SDR Mode  
see 图7-81 and 图7-82  
NO.  
MODE  
MIN  
MAX UNIT  
1.8V, SDR with Internal PHY Loopback  
3.3V, SDR with Internal PHY Loopback  
1.8V, SDR with Internal PHY Loopback  
3.3V, SDR with Internal PHY Loopback  
1.8V, SDR with External Board Loopback  
3.3V, SDR with External Board Loopback  
1.8V, SDR with External Board Loopback  
3.3V, SDR with External Board Loopback  
4.8  
5.19  
-0.5  
-0.5  
0.6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_CLK edge  
O19 tsu(D-CLK)  
O20 th(CLK-D)  
O21 tsu(D-LBCLK)  
O22 th(LBCLK-D)  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_CLK edge  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_DQS edge  
0.9  
1.7  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_DQS edge  
2.0  
OSPI_CLK  
O19  
O20  
OSPI_D[i:0]  
OSPI_TIMING_05  
图7-81. OSPI0 Timing Requirements –PHY SDR with Internal PHY Loopback  
OSPI_DQS  
O21  
O22  
OSPI_D[i:0]  
OSPI_TIMING_06  
图7-82. OSPI0 Timing Requirements –PHY SDR with External Board Loopback  
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表7-98. OSPI0 Switching Characteristics –PHY SDR Mode  
see 图7-83  
NO.  
PARAMETER  
MODE  
1.8V  
MIN  
7
MAX UNIT  
ns  
ns  
ns  
ns  
O7  
tc(CLK)  
Cycle time, OSPI0_CLK  
3.3V  
6.03  
O8  
O9  
tw(CLKL)  
tw(CLKH)  
Pulse duration, OSPI0_CLK low  
Pulse duration, OSPI0_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
Delay time, OSPI0_CSn[3:0] active edge  
to OSPI0_CLK rising edge  
((0.475P(1)) +  
((0.525P(1)) +  
O10 td(CSn-CLK)  
O11 td(CLK-CSn)  
ns  
ns  
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)  
Delay time, OSPI0_CLK rising edge to  
OSPI0_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)  
1.8V  
3.3V  
-1.16  
-1.33  
1.25  
1.51  
ns  
ns  
Delay time, OSPI0_CLK active edge to  
OSPI0_D[7:0] transition  
O12 td(CLK-D)  
(1) P = CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
图7-83. OSPI0 Switching Characteristics –PHY SDR  
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7.10.5.14.1.2.2 OSPI0 PHY DDR Timing  
表 7-99 defines DLL delays required for OSPI0 PHY DDR Mode. 表 7-100, 图 7-84, 表 7-101, and 图 7-85  
present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.  
表7-99. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes  
MODE  
OSPI_PHY_CONFIGURATION_REG BIT FIELD  
DELAY VALUE  
Transmit  
1.8V  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
0x3E  
0x3B  
3.3V  
Receive  
1.8V, DQS  
3.3V, DQS  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
0x15  
0x3A  
0x0  
All other modes  
表7-100. OSPI0 Timing Requirements –PHY DDR Mode  
see 图7-84  
NO.  
MODE  
MIN  
MAX UNIT  
1.8V, DDR with External Board Loopback  
1.8V, DDR with DQS  
0.53  
-0.46  
1.23  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_DQS edge  
O15 tsu(D-LBCLK)  
3.3V, DDR with External Board Loopback  
3.3V, DDR with DQS  
-0.66  
1.24(1)  
3.59  
1.8V, DDR with External Board Loopback  
1.8V, DDR with DQS  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_DQS edge  
O16 th(LBCLK-D)  
3.3V, DDR with External Board Loopback  
3.3V, DDR with DQS  
1.44(1)  
7.92  
(1) This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length  
between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.  
The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.  
OSPI_DQS  
O15 O16 O15 O16  
OSPI_D[i:0]  
OSPI_TIMING_04  
图7-84. OSPI0 Timing Requirements –PHY DDR with External Board Loopback or DQS  
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表7-101. OSPI0 Switching Characteristics –PHY DDR Mode  
see 图7-85  
NO.  
PARAMETER  
MODE  
MIN  
19  
MAX UNIT  
O1  
O2  
O3  
tc(CLK)  
tw(CLKL)  
tw(CLKH)  
Cycle time, OSPI0_CLK  
ns  
ns  
ns  
Pulse duration, OSPI0_CLK low  
Pulse duration, OSPI0_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
Delay time, OSPI0_CSn[3:0] active edge  
to OSPI0_CLK rising edge  
((0.475P(1)) -  
((0.525P(1)) -  
O4  
O5  
td(CSn-CLK)  
td(CLK-CSn)  
ns  
ns  
(0.975M(2)R(4))) (1.025M(2)R(4)) + 7)  
Delay time, OSPI0_CLK rising edge to  
OSPI0_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
(0.975N(3)R(4)) - 7)  
(1.025N(3)R(4)))  
1.8V  
3.3V  
-7.71  
-7.71  
-1.56  
-1.56  
ns  
ns  
Delay time, OSPI0_CLK active edge to  
OSPI0_D[7:0] transition  
O6  
td(CLK-D)  
(1) P = OSPI0_CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O6  
O6  
O1  
OSPI_D[i:0]  
OSPI_TIMING_01  
图7-85. OSPI0 Switching Characteristics –PHY DDR  
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7.10.5.14.2 OSPI0 Tap Mode  
7.10.5.14.2.1 OSPI0 Tap SDR Timing  
表 7-102, 图 7-86, 表 7-103, and 图 7-87 present timing requirements and switching characteristics for OSPI0  
Tap SDR Mode.  
表7-102. OSPI0 Timing Requirements –Tap SDR Mode  
see 图7-86  
NO.  
MODE  
MIN  
MAX UNIT  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_CLK edge  
(10.4 -  
O19 tsu(D-CLK)  
No Loopback  
ns  
(0.975T(1)R(2)))  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_CLK edge  
(0.7 +  
O20 th(CLK-D)  
No Loopback  
ns  
(0.975T(1)R(2)))  
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]  
(2) R = refclk cycle time in ns  
OSPI_CLK  
O19  
O20  
OSPI_D[i:0]  
OSPI_TIMING_05  
图7-86. OSPI0 Timing Requirements –Tap SDR, No Loopback  
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表7-103. OSPI0 Switching Characteristics –Tap SDR Mode  
see 图7-87  
NO.  
PARAMETER  
MODE  
MIN  
20  
MAX UNIT  
O7  
O8  
O9  
tc(CLK)  
tw(CLKL)  
tw(CLKH)  
Cycle time, OSPI0_CLK  
ns  
ns  
ns  
Pulse duration, OSPI0_CLK low  
Pulse duration, OSPI0_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
Delay time, OSPI0_CSn[3:0] active edge  
to OSPI0_CLK rising edge  
((0.475P(1)) +  
((0.525P(1)) +  
O10 td(CSn-CLK)  
O11 td(CLK-CSn)  
O12 td(CLK-D)  
ns  
ns  
ns  
(0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)  
Delay time, OSPI0_CLK rising edge to  
OSPI0_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)  
Delay time, OSPI0_CLK active edge to  
OSPI0_D[7:0] transition  
- 4.25  
7.25  
(1) P = CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
图7-87. OSPI0 Switching Characteristics –Tap SDR, No Loopback  
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7.10.5.14.2.2 OSPI0 Tap DDR Timing  
表 7-104, 图 7-88, 表 7-105, and 图 7-89 present timing requirements and switching characteristics for OSPI0  
Tap DDR Mode.  
表7-104. OSPI0 Timing Requirements –Tap DDR Mode  
see 图7-88  
NO.  
MODE  
MIN  
MAX UNIT  
Setup time, OSPI0_D[7:0] valid before  
active OSPI0_CLK edge  
(12.04 -  
O13 tsu(D-CLK)  
No Loopback  
ns  
(0.975T(1)R(2)))  
Hold time, OSPI0_D[7:0] valid after active  
OSPI0_CLK edge  
(1.84 +  
O14 th(CLK-D)  
No Loopback  
ns  
(0.975T(1)R(2)))  
(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]  
(2) R = refclk cycle time in ns  
OSPI_CLK  
O13 O14 O13 O14  
OSPI_D[i:0]  
OSPI_TIMING_03  
图7-88. OSPI0 Timing Requirements –Tap DDR, No Loopback  
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表7-105. OSPI0 Switching Characteristics –Tap DDR Mode  
see 图7-89  
NO.  
PARAMETER  
MODE  
MIN  
40  
MAX UNIT  
O1  
O2  
O3  
tc(CLK)  
tw(CLKL)  
tw(CLKH)  
Cycle time, OSPI0_CLK  
ns  
ns  
ns  
Pulse duration, OSPI0_CLK low  
Pulse duration, OSPI0_CLK high  
((0.475P(1)) - 0.3)  
((0.475P(1)) - 0.3)  
((0.525P(1)) +  
Delay time, OSPI0_CSn[3:0] active edge  
to OSPI0_CLK rising edge  
((0.475P(1)) +  
O4  
td(CSn-CLK)  
( 1.025M(2)R(4)) +  
1)  
ns  
((0.975M(2)R(4)) - 1)  
Delay time, OSPI0_CLK rising edge to  
OSPI0_CSn[3:0] inactive edge  
((0.475P(1)) +  
((0.525P(1)) +  
O5  
O6  
td(CLK-CSn)  
td(CLK-D)  
ns  
ns  
(0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)  
Delay time, OSPI0_CLK active edge to  
OSPI0_D[7:0] transition  
(- 17.94 +  
(- 1.56 +  
(0.975T(5)R(4)))  
(1.025T(5)R(4)))  
(1) P = CLK cycle time = SCLK period in ns  
(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk cycle time in ns  
(5) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]  
OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O6  
O6  
O1  
OSPI_D[i:0]  
OSPI_TIMING_01  
图7-89. OSPI0 Switching Characteristics –Tap DDR, No Loopback  
7.10.5.15 PCIe  
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the  
specification for timing details.  
For more details about features and additional description information on the device Peripheral Component  
Interconnect Express, see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals  
chapter in the device TRM.  
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7.10.5.16 PRU_ICSSG  
The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication  
Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU  
cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast  
real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks  
from the other processor cores in the device.  
For more details about features and additional description information on the device PRU_ICSSG, see the  
corresponding subsections within Signal Descriptions and Detailed Description sections.  
备注  
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU  
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in  
the device TRM.  
7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)  
备注  
The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The  
signal naming in this section matches the naming used in the PRU Module Interface section in the  
device TRM.  
表7-106. PRU_ICSSG PRU Timing Conditions  
PARAMETER  
MIN  
MAX  
3
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
30  
7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing  
表7-107. PRU_ICSSG PRU Switching Characteristics –Direct Output Mode  
see 图7-90  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRDO1 tsk(GPO-GPO)  
Skew, GPO to GPO  
3
ns  
GPO[n:0]  
PRDO1  
PRU_TIMING_02  
A. n in GPO[n:0] = 19.  
图7-90. PRU_ICSSG PRU Direct Output Timing  
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7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing  
表7-108. PRU_ICSSG PRU Timing Requirements –Parallel Capture Mode  
see 图7-91 and 图7-92  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
PRPC1 tc(CLOCK)  
Cycle time, CLOCKIN  
20  
0.45P(1)  
0.45P(1)  
4
PRPC2 tw(CLOCKL)  
Pulse duration, CLOCKIN low  
ns  
PRPC3 tw(CLOCKH)  
PRPC4 tsu(DATAIN-CLOCK)  
PRPC5 th(CLOCK-DATAIN)  
Pulse duration, CLOCKIN high  
ns  
Setup time, DATAIN valid before CLOCKIN active edge  
Hold time, DATAIN valid after CLOCKIN active edge  
ns  
0
ns  
(1) P = CLOCKIN cycle time in ns  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
PRU_TIMING_03  
图7-91. PRU_ICSSG PRU Parallel Capture Timing Requirements –Rising Edge Mode  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
PRU_TIMING_04  
图7-92. PRU_ICSSG PRU Parallel Capture Timing Requirements –Falling Edge Mode  
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7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing  
表7-109. PRU_ICSSG PRU Timing Requirements –Shift In Mode  
see 图7-93  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, DATAIN high  
Pulse duration, DATAIN low  
MIN  
2P(1) + 2  
2P(1) + 2  
MAX  
UNIT  
ns  
PRSI1 tw(DATAINH)  
PRSI2 tw(DATAINL)  
ns  
(1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.  
PRUn represents the respective PRU0 or PRU1 instance.  
PRSI1  
PRSI2  
DATAIN  
PRU_TIMING_05  
图7-93. PRU_ICSSG PRU Shift In Timing  
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表7-110. PRU_ICSSG PRU Switching Characteristics –Shift Out Mode  
see 图7-94  
NO.  
PARAMETER  
tc(CLOCKOUT)  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
PRSO1  
Cycle time, CLOCKOUT  
10  
PRSO2L tw(CLOCKOUTL)  
Pulse duration, CLOCKOUT low  
0.475P(1)Z(2)  
-
ns  
0.3  
PRSO2H tw(CLOCKOUTH)  
Pulse duration, CLOCKOUT high  
0.475P(1)Y(3)  
-
ns  
ns  
0.3  
PRSO3  
td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid  
-1  
4
(1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the  
ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance.  
(2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.  
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is  
an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).  
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 + 0.5).  
c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0).  
d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 *  
PRUn_GPI_DIV0).  
(3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.  
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is  
an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).  
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 - 0.5).  
c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *  
PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).  
d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *  
PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high  
pulse and Y2 is the second high pulse.  
PRSO1  
PRSO2H  
PRSO2L  
CLOCKOUT  
DATAOUT  
PRSO3  
PRU_TIMING_06  
图7-94. PRU_ICSSG PRU Shift Out Timing  
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7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface  
表7-111. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
18  
7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing  
表7-112. PRU_ICSSG PRU Timing Requirements –Sigma Delta Mode  
see 图7-95 and 图7-96  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
40  
20  
20  
10  
5
MAX  
UNIT  
ns  
PRSD1  
tc(SD_CLK)  
Cycle time, SDx_CLK  
PRSD2L tw(SD_CLKL)  
PRSD2H tw(SD_CLKH)  
Pulse duration, SDx_CLK low  
ns  
Pulse duration, SDx_CLK high  
ns  
PRSD3  
PRSD4  
tsu(SD_D-SD_CLK)  
Setup time, SDx_D valid before SDx_CLK active edge  
Hold time, SDx_D valid before SDx_CLK active edge  
ns  
th(SD_CLK-SD_D)  
ns  
PRSD1  
PRSD2H  
SDx_CLK  
SDx_D  
PRSD2L  
PRSD4  
PRSD3  
PRU_TIMING_07  
图7-95. PRU_ICSSG PRU SD_CLK Falling Active Edge  
PRSD2L  
SDx_CLK  
SDx_D  
PRSD4  
PRSD3  
PRU_TIMING_08  
图7-96. PRU_ICSSG PRU SD_CLK Rising Active Edge  
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表7-113. PRU_ICSSG PRU Timing Requirements –Peripheral Interface Mode  
see 图7-97  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, PIF_DATA_IN high  
MIN  
MAX  
UNIT  
PRPIF1 tw(PIF_DATA_INH)  
2 +  
ns  
0.475*(4*P)(1)  
PRPIF2 tw(PIF_DATA_INL)  
Pulse duration, PIF_DATA_IN low  
2 +  
ns  
0.475*(4*P)(1)  
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the  
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.  
PRPIF1  
PRPIF2  
PIF_DATA_IN  
PRUPIF_TIMING_01  
图7-97. PRU_ICSSG PRU Peripheral Interface Timing Requirements  
表7-114. PRU_ICSSG PRU Switching Characteristics –Peripheral Interface Mode  
see 图7-98  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
30  
0.475*P(1)  
0.475*P(1)  
-5  
MAX  
UNIT  
ns  
PRPIF3 tc(PIF_CLK)  
PRPIF4 tw(PIF_CLKH)  
PRPIF5 tw(PIF_CLKL)  
Cycle time, PIF_CLK  
Pulse duration, PIF_CLK high  
ns  
Pulse duration, PIF_CLK low  
ns  
PRPIF6 td(PIF_CLK-  
Delay time, PIF_CLK fall to PIF_DATA_OUT  
5
5
ns  
PIF_DATA_OUT)  
PRPIF7 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN  
-5  
ns  
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the  
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.  
PRPIF3  
PRPIF4  
PRPIF5  
PIF_CLK  
PRPIF6  
PIF_DATA_OUT  
PRPIF7  
PIF_DATA_EN  
图7-98. PRU_ICSSG PRU Peripheral Interface Switching Characteristics  
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7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)  
表7-115. PRU_ICSSG PWM Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.10.5.16.2.1 PRU_ICSSG PWM Timing  
表7-116. PRU_ICSSG PWM Switching Characteristics  
see 图7-99  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRPWM1 tsk(PWM_A-PWM_B)  
Skew, PWM_A to PWM_B  
5
ns  
PWM_A/B  
PRPWM1  
PRU_PWM_TIMING_01  
图7-99. PRU_ICSSG PWM Timing  
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MAX UNIT  
7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)  
表7-117. PRU_ICSSG IEP Timing Conditions  
PARAMETER  
MIN  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
V/ns  
OUTPUT CONDITIONS  
EDC_SYNC_OUTx  
EDIO_OUTVALID  
2
3
7
pF  
pF  
CL  
Output load capacitance  
EDIO_DATA_OUT  
10  
7.10.5.16.3.1 PRU_ICSSG IEP Timing  
表7-118. PRU_ICSSG IEP Timing Requirements –Input Validated with SYNC  
see 图7-100  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDC_SYNC_OUTx low  
Pulse duration, EDC_SYNC_OUTx high  
MIN  
20P(1) - 2  
20P(1) - 2  
20  
MAX  
UNIT  
ns  
PRIEP1 tw(EDC_SYNC_OUTxL)  
PRIEP2 tw(EDC_SYNC_OUTxH)  
ns  
PRIEP3 tsu(EDIO_DATA_IN-  
Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active  
edge  
ns  
EDC_SYNC_OUTx)  
PRIEP4 th(EDC_SYNC_OUTx-  
Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active  
edge  
20  
ns  
EDIO_DATA_IN)  
(1) P = PRU_ICSSG IEP clock source period in ns.  
EDC_SYNC_OUTx  
PRIEP2  
PRIEP1  
PRIEP3  
PRIEP4  
EDIO_DATA_IN[7:0]  
PRU_IEP_TIMING_01  
图7-100. PRU_ICSSG IEP SYNC Timing Requirements  
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表7-119. PRU_ICSSG IEP Switching Characteristics –Digital IOs  
see 图7-101  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDIO_OUTVALID low  
MIN  
14P(1) - 2  
32P(1) - 2  
0
MAX  
UNIT  
ns  
IEPIO1 tw(EDIO_OUTVALIDL)  
IEPIO2 tw(EDIO_OUTVALIDH)  
Pulse duration, EDIO_OUTVALID high  
ns  
IEPIO3 td(EDIO_OUTVALID-  
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT  
18P(1)  
5
ns  
EDIO_DATA_OUT)  
IEPIO4 tsk(EDIO_DATA_OUT)  
EDIO_DATA_OUT skew  
ns  
(1) P = PRU_ICSSG IEP clock source period in ns.  
EDIO_DATA_OUT  
IEPIO4  
PRU_EDIO_DATA_OUT_TIMING_00  
图7-101. PRU_ICSSG IEP Digital IOs Timing Requirements  
表7-120. PRU_ICSSG IEP Timing Requirements –LATCH_INx  
see 图7-102  
NO.  
PARAMETER  
DESCRIPTION  
Pulse duration, EDC_LATCH_INx low  
Pulse duration, EDC_LATCH_INx high  
MIN  
3P(1) + 2  
3P(1) + 2  
MAX  
UNIT  
ns  
PRLA1 tw(EDC_LATCH_INxL)  
PRLA2 tw(EDC_LATCH_INxH)  
ns  
(1) P = PRU_ICSSG IEP clock source period in ns.  
PRLA1  
EDC_LATCH_INx  
PRLA2  
PRU_IEP_TIMING_02  
图7-102. PRU_ICSSG IEP LATCH_INx Timing Requirements  
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7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)  
表7-121. PRU_ICSSG UART Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
0.5  
1
5
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30(1)  
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the  
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall  
times will increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices.  
Therefore, it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then  
use the device IBIS models to verify the actual load capacitance on the UART signals will not increase the rise/fall times beyond the  
point where it violates the minimum data valid time of the attached device.  
7.10.5.16.4.1 PRU_ICSSG UART Timing  
表7-122. PRU_ICSSG UART Timing Requirements  
see 图7-103  
NO.  
PARAMETER  
tw(RXD)  
tw(RXDS)  
DESCRIPTION  
MIN  
MAX  
UNIT  
0.95U(1)  
1.05U(1)  
1
Pulse width, receive data bit high or low  
ns  
(2)  
(2)  
0.95U(1)  
2
Pulse width, receive start bit low  
ns  
(2)  
(1) U = UART baud time in ns = 1/programmed baud rate.  
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.  
表7-123. PRU_ICSSG UART Switching Characteristics  
see 图7-103  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
12  
UNIT  
Mbps  
ns  
f(baud)  
Programmed baud rate  
3
4
tw(TXD)  
Pulse width, transmit data bit high or low  
Pulse width, transmit start bit low  
U(1) - 2  
U(1) - 2  
U(1) + 2  
U(1) + 2  
tw(TXDS)  
ns  
(1) U = UART baud time in ns = 1/programmed baud rate.  
2
1
Start  
Bit  
VIH  
PRGi_UART0_RXD  
VIL  
Data Bits  
4
3
Start  
Bit  
PRGi_UART0_TXD  
Data Bits  
PRU_UART_TIMING_01_RCVRVIHVIL  
图7-103. PRU_ICSSG UART Timing Requirements and Switching Characteristics  
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7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)  
表7-124. PRU_ICSSG ECAP Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.10.5.16.5.1 PRU_ICSSG ECAP Timing  
表7-125. PRU_ICSSG ECAP Timing Requirements  
see 图7-104  
NO.  
PARAMETER  
DESCRIPTION  
Pulse Duration, CAP (asynchronous)  
MIN  
2P(1) + 2  
2P(1) + 2  
MAX  
UNIT  
ns  
PREP1 tw(CAP)  
PREP2 tw(SYNCI)  
Pulse Duration, SYNCI (asynchronous)  
ns  
(1) P = CORE_CLK period in ns.  
PREP1  
CAP  
PREP2  
SYNCI  
图7-104. PRU_ICSSG ECAP Timing  
表7-126. PRU_ICSSG ECAP Switching Characteristics  
see 图7-105  
NO.  
PARAMETER  
DESCRIPTION  
Pulse Duration, APWM high/low  
MIN  
2P(1) - 2  
P(1) - 2  
MAX  
UNIT  
ns  
PREP3 tw(APWM)  
PREP4 tw(SYNCO)  
Pulse Duration, SYNCO (asynchronous)  
ns  
(1) P = CORE_CLK period in ns.  
PREP3  
PREP4  
APWM  
SYNCO  
图7-105. PRU_ICSSG ECAP Switching Characteristics  
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7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch  
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -  
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.  
7.10.5.16.6.1 PRU_ICSSG MDIO Timing  
表 7-127, 表 7-128, 表 7-129, and 图 7-106 present timing conditions, requirements, and switching  
characteristics for PRU_ICSSG MDIO.  
表7-127. PRU_ICSSG MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
表7-128. PRU_ICSSG MDIO Timing Requirements  
see 图7-106  
NO.  
PARAMETER  
MIN  
90  
0
MAX  
UNIT  
ns  
MDIO1 tsu(MDIO_MDC)  
MDIO2 th(MDC_MDIO)  
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high  
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high  
ns  
表7-129. PRU_ICSSG MDIO Switching Characteristics  
see 图7-106  
NO.  
PARAMETER  
MIN  
400  
160  
160  
-150  
MAX  
UNIT  
ns  
MDIO3 tc(MDC)  
Cycle time, MDIO[x]_MDC  
MDIO4 tw(MDCH)  
MDIO5 tw(MDCL)  
MDIO7 td(MDC_MDIO)  
Pulse Duration, MDIO[x]_MDC high  
Pulse Duration, MDIO[x]_MDC low  
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid  
ns  
ns  
150  
ns  
MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
图7-106. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics  
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7.10.5.16.6.2 PRU_ICSSG MII Timing  
备注  
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the  
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz,  
225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1  
register must be set to 0h (default value).  
表 7-130, 表 7-131, 图 7-107, 表 7-132, 图 7-108, 表 7-133, 图 7-109, 表 7-134, and 图 7-110 present timing  
conditions, requirements, and switching characteristics for PRU_ICSSG MII.  
表7-130. PRU_ICSSG MII Timing Conditions  
PARAMETER  
MIN  
0.9  
2
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
表7-131. PRU_ICSSG MII Timing Requirements –MII[x]_RX_CLK  
see 图7-107  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, MII[x]_RX_CLK  
MODE  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
MIN  
MAX UNIT  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
PMIR1 tc(RX_CLK)  
PMIR2 tw(RX_CLKH)  
PMIR3 tw(RX_CLKL)  
140  
14  
260  
26  
Pulse Duration, MII[x]_RX_CLK High  
Pulse Duration, MII[x]_RX_CLK Low  
140  
14  
260  
26  
PMIR1  
PMIR2  
PMIR3  
MII_RX_CLK  
PRU_MII_RT_TIMING_04  
图7-107. PRU_ICSSG MII[x]_RX_CLK Timing  
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表7-132. PRU_ICSSG MII Timing Requirements –MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER  
see 图7-108  
NO.  
PARAMETER  
tsu(RXD-RX_CLK)  
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
tsu(RXD-RX_CLK)  
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
th(RX_CLK-RXD)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK  
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK  
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK  
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK  
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK  
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK  
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK  
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK  
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK  
8
10 Mbps  
8
8
PMIR4  
8
100  
Mbps  
8
8
8
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
th(RX_CLK-RXD)  
10 Mbps  
8
8
PMIR5  
8
100  
Mbps  
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
8
8
PMIR4  
PMIR5  
MII_RX_CLK  
MII_RXD[3:0],  
MII_RX_DV, MII_RX_ER  
图7-108. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing  
表7-133. PRU_ICSSG MII Timing Requirements –MII[x]_TX_CLK  
see 图7-109  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, MII[x]_TX_CLK  
MODE  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
MIN  
MAX UNIT  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
PMIT1 tc(TX_CLK)  
140  
14  
260  
26  
PMIT2 tw(TX_CLKH)  
Pulse Duration, MII[x]_TX_CLK High  
Pulse Duration, MII[x]_TX_CLK Low  
140  
14  
260  
26  
PMIT3 tw(TX_CLKL)  
PMIT1  
PMIT2  
PMIT3  
MII_TX_CLK  
图7-109. PRU_ICSSG MII[x]_TX_CLK Timing  
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表7-134. PRU_ICSSG MII Switching Characteristics –MII[x]_TXD[3:0] and MII[x]_TX_EN  
see 图7-110  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
0
MAX  
25  
UNIT  
ns  
td(TX_CLK-TXD)  
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid  
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid  
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid  
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid  
10 Mbps  
td(TX_CLK-TX_EN)  
td(TX_CLK-TXD)  
0
25  
ns  
PMIT4  
0
25  
ns  
100  
Mbps  
td(TX_CLK-TX_EN)  
0
25  
ns  
PMIT4  
MII_TX_CLK  
MII_TXD[3:0], MII_TX_EN  
图7-110. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing  
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7.10.5.16.6.3 PRU_ICSSG RGMII Timing  
表 7-135, 表 7-136, 表 7-137, 图 7-111, 表 7-138, 表 7-139, and 图 7-112 present timing conditions,  
requirements, and switching characteristics for PRU_ICSSG RGMII.  
表7-135. PRU_ICSSG RGMII Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
INPUT CONDITIONS  
VDD = 1.8V  
VDD = 3.3V  
1.44  
2.65  
5
5
V/ns  
V/ns  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
20  
pF  
PCB CONNECTIVITY REQUIREMENTS  
RGMII[x]_RXC,  
RGMII[x]_RD[3:0],  
RGMII[x]_RX_CTL  
50  
50  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
Delay)  
RGMII[x]_TXC,  
RGMII[x]_TD[3:0],  
RGMII[x]_TX_CTL  
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表7-136. PRU_ICSSG RGMII Timing Requirements –RGMII[x]_RXC  
see 图7-111  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_RXC  
MODE  
10 Mbps  
MIN  
360  
36  
MAX UNIT  
RGMII1 tc(RXC)  
RGMII2 tw(RXCH)  
RGMII3 tw(RXCL)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_RXC high  
Pulse duration, RGMII[x]_RXC low  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
100 Mbps  
1000 Mbps  
3.6  
4.4  
表7-137. PRU_ICSSG RGMII Timing Requirements –RGMII[x]_RD[3:0] and RGMII[x]_RX_CTL  
see 图7-111  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
1
MAX UNIT  
RGMII4 tsu(RD-RXC)  
Setup time, RGMII[x]_RD[3:0] valid before RXC high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
tsu(RX_CTL-RXC)  
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
RGMII5 th(RXC-RD)  
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
10 Mbps  
1
1
th(RXC-RX_CTL)  
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC  
high/low  
1
100 Mbps  
1000 Mbps  
1
1
RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
RGMII[x]_RX_CTL(B)  
1st Half-byte  
RXDV  
2nd Half-byte  
RXERR  
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of  
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.  
图7-111. PRU_ICSSG RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII  
Mode  
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MAX UNIT  
表7-138. PRU_ICSSG RGMII Switching Characteristics –RGMII[x]_TXC  
see 图7-112  
NO.  
PARAMETER  
DESCRIPTION  
Cycle time, RGMII[x]_TXC  
MODE  
10 Mbps  
MIN  
360  
36  
RGMII6 tc(TXC)  
RGMII7 tw(TXCH)  
RGMII8 tw(TXCL)  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RGMII[x]_TXC high  
Pulse duration, RGMII[x]_TXC low  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
100 Mbps  
1000 Mbps  
3.6  
4.4  
表7-139. PRU_ICSSG RGMII Switching Characteristics –RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL  
see 图7-112  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
MAX UNIT  
RGMII9 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC  
high/low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
10 Mbps  
RGMII10 toh(TXC-TD)  
Output setup time, RGMII[x]_TD[3:0] valid after  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
10 Mbps  
toh(TXC-TX_CTL)  
Output setup time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
100 Mbps  
1000 Mbps  
RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of  
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.  
图7-112. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics  
- RGMII Mode  
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7.10.5.17 Timers  
For more details about features and additional description information on the device Timers, see the  
corresponding subsections within Signal Descriptions and Detailed Description sections.  
表7-140. Timer Timing Conditions  
PARAMETER  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
表7-141. Timer Input Timing Requirements  
see 图7-113  
NO.  
PARAMETER  
tw(TINPH)  
tw(TINPL)  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
T1  
Pulse duration, high  
Pulse duration, low  
CAPTURE 2 + 4P(1)  
CAPTURE 2 + 4P(1)  
ns  
ns  
T2  
(1) P = functional clock period in ns.  
表7-142. Timer Output Switching Characteristics  
see 图7-113  
NO.  
PARAMETER  
tw(TOUTH)  
tw(TOUTL)  
DESCRIPTION  
MODE  
MIN  
-2 + 4P(1)  
-2 + 4P(1)  
MAX  
UNIT  
ns  
T3  
Pulse duration, high  
Pulse duration, low  
PWM  
PWM  
T4  
ns  
(1) P = functional clock period in ns.  
T1  
T2  
TIMER_IOx (inputs)  
T3  
T4  
TIMER_IOx (outputs)  
TIMER_01  
图7-113. Timer Timing Requirements and Switching Characteristics  
For more information, see Timers section in Peripherals chapter in the device TRM.  
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7.10.5.18 UART  
For more details about features and additional description information on the device Universal Asynchronous  
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
表7-143. UART Timing Conditions  
PARAMETER  
MIN  
0.5  
1
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30(1)  
(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the  
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall  
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,  
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the  
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point  
where the minimum data valid time of the attached device is violated.  
表7-144. UART Timing Requirements  
see 图7-114  
NO.  
PARAMETER  
tw(RXD)  
tw(RXDS)  
DESCRIPTION  
MIN  
MAX  
UNIT  
0.95U(1)  
1.05U(1)  
1
Pulse width, receive data bit high or low  
ns  
(2)  
(2)  
0.95U(1)  
2
Pulse width, receive start bit low  
ns  
(2)  
(1) U = UART baud time in ns = 1/programmed baud rate.  
(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.  
表7-145. UART Switching Characteristics  
see 图7-114  
NO.  
PARAMETER  
DESCRIPTION  
Programmable baud rate for Main Domain UARTs  
Programmable baud rate for MCU Domain UARTs  
Pulse width, transmit data bit high or low  
Pulse width, transmit start bit low  
MIN  
MAX  
12  
UNIT  
Mbps  
Mbps  
ns  
f(baud)  
3.7  
3
4
tw(TXD)  
U(1) - 2.2 U(1) + 2.2  
U(1) - 2.2  
tw(TXDS)  
ns  
(1) U = UART baud time in ns = 1/programmed baud rate.  
2
1
Start  
VIH  
Bit  
UARTi_RXD  
VIL  
Data Bits  
4
3
Start  
Bit  
UARTi_TXD  
Data Bits  
UART_TIMING_01_RCVRVIHVIL  
图7-114. UART Timing Requirements and Switching Characteristics  
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For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter  
in the device TRM.  
7.10.5.19 USB  
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the  
specification for timing details.  
The USB 3.1 GEN1 subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0.  
Refer to the specification for timing details.  
For more details about features and additional description information on the device Universal Serial Bus  
Subsystem (USB), see the corresponding subsections within Signal Descriptions and Detailed Description  
sections.  
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7.10.6 Emulation and Debug  
For more details about features and additional description information on the device Trace and JTAG interfaces,  
see the corresponding subsections within Signal Descriptions and Detailed Description sections.  
7.10.6.1 Trace  
表7-146. Trace Timing Conditions  
PARAMETER  
MIN  
MAX UNIT  
OUTPUT CONDITIONS  
CL Output load capacitance  
PCB CONNECTIVITY REQUIREMENTS  
2
5
pF  
VDDSHV3 = 1.8V  
VDDSHV3 =3.3V  
200  
100  
ps  
ps  
td(Trace Mismatch)  
Propagation delay mismatch across all traces  
表7-147. Trace Switching Characteristics  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
1.8V Mode  
DBTR1 tc(TRC_CLK)  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Cycle time, TRC_CLK  
6.50  
2.50  
2.50  
ns  
ns  
ns  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
tosu(TRC_DATAV-  
DBTR4  
Output setup time, TRC_DATA valid to TRC_CLK edge  
0.81  
ns  
TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid  
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge  
0.81  
0.81  
0.81  
ns  
ns  
ns  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
3.3V Mode  
DBTR1 tc(TRC_CLK)  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Cycle time, TRC_CLK  
8.67  
3.58  
3.58  
ns  
ns  
ns  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
tosu(TRC_DATAV-  
DBTR4  
Output setup time, TRC_DATA valid to TRC_CLK edge  
1.08  
ns  
TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid  
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge  
1.08  
1.08  
1.08  
ns  
ns  
ns  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
DBTR1  
DBTR2  
DBTR3  
TRC_CLK  
(Worst Case 1)  
(Ideal)  
(Worst Case 2)  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
TRC_DATA  
TRC_CTL  
SPRSP08_Debug_01  
图7-115. Trace Switching Characteristics  
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7.10.6.2 JTAG  
表7-148. JTAG Timing Conditions  
PARAMETER  
MIN  
0.5  
5
MAX  
2.0  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
15  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
Propagation delay mismatch across all traces  
83.5  
1000(1)  
100  
ps  
ps  
td(Trace Mismatch Delay)  
(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It  
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the  
additional trace delay.  
表7-149. JTAG Timing Requirements  
see 图7-116  
NO.  
MIN  
MAX  
UNIT  
ns  
J1  
tc(TCK)  
Cycle time minimum, TCK  
45.5(1)  
J2  
tw(TCKH)  
Pulse width minimum, TCK high  
0.4P(2)  
ns  
J3  
tw(TCKL)  
Pulse width minimum, TCK low  
0.4P(2)  
ns  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
th(TCK-TDI)  
th(TCK-TMS)  
Input setup time minimum, TDI valid to TCK high  
Input setup time minimum, TMS valid to TCK high  
Input hold time minimum, TDI valid from TCK high  
Input hold time minimum, TMS valid from TCK high  
4
4
2
2
ns  
J4  
J5  
ns  
ns  
ns  
(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached  
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these  
assumptions.  
•
•
Minimum TDO setup time of 2.2 ns relative to the rising edge of TCK  
TDI and TMS output delay in the range of -16.1 ns to 14.1 ns relative to the falling edge of TCK  
(2) P = TCK cycle time in ns  
表7-150. JTAG Switching Characteristics  
see 图7-116  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
J6  
J7  
td(TCKL-TDOI)  
td(TCKL-TDOV)  
Delay time minimum, TCK low to TDO invalid  
Delay time maximum, TCK low to TDO valid  
0
14  
ns  
J1  
J2  
J3  
TCK  
TDI / TMS  
TDO  
J4  
J5  
J4  
J5  
J7  
J6  
图7-116. JTAG Timing Requirements and Switching Characteristics  
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8 Detailed Description  
8.1 Overview  
AM64x is an extension of the Sitara™ industrial-grade family of heterogeneous Arm processors. AM64x is built  
for industrial applications, such as motor drives and programmable logic controllers (PLCs), which require a  
unique combination of real-time processing and communications with applications processing. AM64x combines  
two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG, up to two Arm Cortex-A53 cores, up to four  
Cortex-R5F MCUs, and a Cortex-M4F MCU domain.  
AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled  
Memory banks, configurable SRAM partitioning, and low-latency paths to and from peripherals for rapid data  
movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control  
loops found in servo drives, while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and  
absolute encoder interfaces help enable a number of different architectures found in these systems.  
The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-  
time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term  
Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux  
world with the real-time world by enabling isolation between Linux applications and real-time streams through  
configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and  
the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.  
The PRU_ICSSG in AM64x provides the flexible industrial communications capability necessary to run gigabit  
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU_ICSSG also enables  
additional interfaces in the SoC including sigma delta decimation filter modules and absolute encoder interfaces.  
Functional safety features can be enabled through the MCU domain with an integrated Cortex-M4F and  
dedicated peripheral set which can all be shared or isolated from the rest of the SoC. AM64x also supports  
secure boot.  
备注  
For more information on features, subsystems, and architecture of superset device System on Chip  
(SoC), see the device TRM.  
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8.2 Processor Subsystems  
8.2.1 Arm Cortex-A53 Subsystem  
The A53SS module supports the following features:  
• Dual Core A53 Cluster  
– Full ARM v8-A Architecture Compliant  
• AArch32 and AArch64 Execution States  
• All exception levels EL0-3  
• A32 Instruction Set (Previously ARM instruction set)  
• T32 instruction set (previously Thumb instruction set)  
• A64 Instruction Set  
– Advanced SIMD and Floating Point Extensions (NEON)  
– ARMv8 Cryptography Extensions  
– ARMv8 Cryptography Extensions  
– ARM GICv3 architecture  
– In-order pipeline with symmetric dual-issue of most instructions  
– Harvard L1 with system MMU  
• 32 KB Instruction Cache  
• 32 KB Data Cache  
– 256KB Shared L2 Cache  
– Generic Timer(s)  
– Debug  
• 128-Bit VBUSM Initiator Interfaces (for axi_r and axi_r channels)  
• 128-Bit VBUSM Target Interface (for Accelerator Coherency Port)  
• 64-bit Grey-coded system input time  
• 48-bit Grey-coded debug input time  
• 32-bit VBUSP Target Interface for Debug  
• Integrated PBIST Controller with BISOR  
For more information, see Dual-A53 MPU Subsystem section in Processors and Accelerators chapter in the  
device TRM.  
8.2.2 Arm Cortex-R5F Subsystem (R5FSS)  
The R5FSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for dual/single-core  
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®  
CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and  
various wrappers for protocol conversion and address translation for easy integration into the SoC.  
备注  
The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit  
(FPU) extension.  
For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the  
device TRM.  
8.2.3 Arm Cortex-M4F (M4FSS)  
The M4FSS module on the AM64x device provides a safety channel (secondary channel - working in conjunction  
with an external microcontroller)- or- a general purpose MCU.  
The M4FSS module supports the following features:  
• Cortex M4F With MPU  
• ARMv7-M architecture  
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• Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs  
• Ability to executed code from internal or external memories  
• 192 KB of SRAM (I-Code)  
• 64 KB of SRAM (D-Code)  
• External access to internal memories if allowed  
• Debug Support Including:  
– DAP based Debug to the CPU Core  
– Full Debug Features of CPU Core are enabled  
– Standard ITM trace  
– CTM Cross Trigger  
– ETM Trace Support  
• Fault Detection and Correction  
– SECDED ECC protection on I-CODE  
– SECDED ECC protection on D-CODE  
– Fault Error Interrupt Output  
For more information, see Arm Cortex M4F Subsystem (M4FSS) section in Processors and Accelerators chapter  
in the device TRM.  
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8.3 Accelerators and Coprocessors  
8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)  
The PRU_ICSSG module supports the following main features:  
• 3x PRUs  
– General-Purpose PRU (PRU)  
– Real-Time PRU(RTU_PRU)  
– Transmit PRU (TX_PRU)  
• 2x Ethernet MII_G_RT configurable connection to PRUs  
– Up to 2x RGMII ports  
– Up to 2x MII ports  
– RX Classifier  
• 2x Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions  
• 2x Industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast  
compensation.  
• 1x MDIO  
• 1x UART, with a dedicated 192-MHz clock input  
• Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable PWM  
outputs.  
• Supports up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.  
• 1x Enhanced Capture Module (ECAP)  
• 1x Interrupt Controller (INTC)  
– 160 input events supported –96 external, 64 internal  
• Flexible power management support  
• Integrated switched central resource with programmable priority  
• All memories support ECC  
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -  
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.  
8.4 Other Subsystems  
8.4.1 PDMA Controller  
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of  
peripherals, which perform data transfers using memory mapped registers accessed via a standard non-  
coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require  
an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and  
supporting only statically configured Transfer Request (TR) operations.  
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals  
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data  
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of  
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to  
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.  
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer  
complexity at each point in the system to match the requirements of whatever is being transferred to or from.  
Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO  
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically  
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.  
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous  
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and  
employs round-robin scheduling between channels in order to share the underlying DMA hardware.  
There are five PDMA modules in the device.  
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For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.  
8.4.2 Peripherals  
8.4.2.1 ADC  
The analog-to-digital converter (ADC) module is a single-channel general purpose analog-to-digital converter  
with an 8-input analog multiplexer, which supports 12-bit conversion samples from an analog front end (AFE).  
There is one ADC module in the device.  
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.  
8.4.2.2 DCC  
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution  
of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The  
desired accuracy can be programed based on calculation for each application. The DCC measures the  
frequency of a selectable clock source using another input clock as a reference.  
The device has seven instances of DCC modules.  
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.  
8.4.2.3 Dual Date Rate (DDR) External Memory Interface (DDRSS)  
Integrated in MAIN domain: one instance of DDR Subsystem (DDRSS) is used as an interface to external RAM  
devices which can be utilized for storing program or data. DDRSS provides the following main features:  
• Support of DDR4 / LPDDR4 memory types  
• 16-bit memory bus interface with in-line ECC  
• System bus interface: little Endian only with 128-bit data width  
• Configuration bus Interface: little Endian only with 32-bit data width  
• Support of dual rank configuration  
• Support of automatic idle power saving mode when no or low activity is detected  
• Class of Service (CoS) - three latency classes supported  
• Prioritized refresh scheduling  
• Statistical counters for performance management  
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.  
8.4.2.4 ECAP  
This section describes the Enhanced Capture (ECAP) module for the device.  
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.  
8.4.2.5 EPWM  
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU  
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand  
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and  
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;  
instead, the EPWM is built up from smaller single channel modules with separate resources and that can  
operate together as required to form a system. This modular approach results in an orthogonal architecture and  
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.  
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance  
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x  
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so  
forth.  
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Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral  
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules  
can also operate stand-alone.  
The device has six instances of EPWM modules.  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in  
the device TRM.  
8.4.2.6 ELM  
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when  
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then  
correct the data block by flipping the bits to which the ELM error-location outputs point.  
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND  
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is  
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.  
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses this  
to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome  
polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an  
optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-  
Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome  
polynomials.  
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.  
8.4.2.7 ESM  
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device  
into one location. The module can signal both low and high priority interrupts to a processor to deal with a safety  
event and/or manipulate an I/O error pin to signal external hardware that an error has occurred. This allows an  
external controller to reset the device or keep the system in safe, known state.  
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.  
8.4.2.8 GPIO  
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be  
configured as either inputs or outputs. When configured as an output, user can write to an internal register to  
control the state driven on the output pin. When configured as an input, user can obtain the state of the input by  
reading the state of an internal register.  
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different  
interrupt/event generation modes.  
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.  
8.4.2.9 EQEP  
The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary  
incremental encoder to get position, direction and speed information from a rotating machine for use in high  
performance motion and position control system. The disk of an incremental encoder is patterned with a single  
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined  
as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is  
added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate  
an absolute position. Encoder manufacturers identify the index pulse using different terms such as index,  
marker, home position and zero reference.  
To derive direction information, the lines on the disk are read out by two different photo-elements that "look" at  
the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized with a  
reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the disk  
rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other.  
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These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders  
is defined as the QEPA channel going positive before the QEPB channel and vice versa.  
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel can be at a  
geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the  
QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder  
directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so  
by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the  
motor.  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter  
in the device TRM.  
8.4.2.10 GPMC  
The GPMC module supports the following features:  
• Data path to external memory device can be 32, 16 or 8 bits wide  
• Support for the following memory types:  
– Asynchronous or synchronous 8-bit memory or device (non-burst device)  
– Asynchronous or synchronous 16-bit memory or device  
– Asynchronous or synchronous 32-bit memory or device  
– 16-bit non-multiplexed NOR Flash device  
– 16-bit address and 32-bit address and data multiplexed NOR Flash device  
– 8-bit and 16-bit NAND flash device  
– 16-bit and 32bit pSRAM device  
• Supports Error Code detection using BCH code (t=4, 8 or 16) or Hamming code for 8-bit or 16-bit NAND-  
flash, organized with page size of 512 Byte, 1Kbytes, or more. •Supports 1 GByte maximum addressing  
capability, which can be divided into 8 independent chip-select with programmable bank size and base  
address on 16 MByte, 32 MByte, 64 MByte, or 128 MByte boundary.  
• Fully-pipelined operation for optimal memory bandwidth usage  
• Supports external device clock frequency of /1, /2, /3, and /4 divide of interface clock  
• Supports programmable auto-clock gating when there is no access  
• Supports MIdlereq/SIdleAck protocol  
• Supports the following interface protocols when communicating with external memory or external devices:  
– Asynchronous read/write access  
– Asynchronous read page access (4-8-16 Word16), 4-8-16 Word32  
– Synchronous read/write access  
– Synchronous read burst access without wrap capability (4-8-16-32 Word16, 4-8-16 Word32)  
– Synchronous read burst access with wrap capability (4-8-16-32 Word16, 4-8-16 Word32)  
• Address and data multiplexed access  
• Each chip-select has independent and programmable control signal timing parameters for Setup and Hold  
time. Parameters are set according to the memory device timing parameters, with one interface clock cycle  
timing granularity.  
• Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin  
• Supports bus keeping  
• Supports bus turn around  
• Pre-fetch and write posting engine associated with system DMA, to get full performance from NAND device,  
and with minimum impact on NOR/SRAM concurrent access monitoring (up to 4 WAIT pins)  
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the  
device TRM.  
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8.4.2.11 I2C  
The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the multi-  
controller I2C bus, which allows serial transfer of 8-bit data to and from other I2C controller and target devices,  
through a two-wire interface.  
The I2C module supports the following main features:  
• Compliant with Philips I2C specification version 2.1  
• Supported Speeds:  
– Standard mode (up to 100 K bits/s)  
– Fast mode (up to 400 K bits/s)  
– High-speed mode (up to 3.4 M bits/s), I2C0 and MCU_I2C0 only  
• Multi-controller transmitter and target receiver mode  
• Multi-controller receiver and target transmitter mode  
• Combined controller transmit/receive and receive/transmit modes  
• 7-bit and 10-bit device addressing modes  
• Built-in 32-byte FIFO for buffered read or write  
• Programmable multi-target channel (responds to 4 separates addresses)  
• Programmable clock generation  
• Support for asynchronous wake-up  
• One interrupt line  
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device  
TRM.  
8.4.2.12 MCAN  
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed  
real-time control with a high level of security. CAN has high immunity to electrical interference and the ability to  
self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire  
network, which provides for data consistency in every node of the system.  
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN  
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices  
can coexist on the same network without any conflict.  
The device supports 2 MCAN modules  
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device  
TRM.  
8.4.2.13 MCRC Controller  
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the  
integrity of a memory system. A signature representing the contents of the memory is obtained when the  
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the  
signature for a set of data and then compare the calculated signature value against a pre-determined good  
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in  
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC  
controller compresses each data being read through CPU read data bus.  
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device  
TRM.  
8.4.2.14 MCSPI  
The MCSPI module is a multichannel transmit/receive, controller/peripheral synchronous serial bus.  
There are total of seven MCSPI modules in the device.  
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For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the  
device TRM.  
8.4.2.15 MMCSD  
There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1.  
Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and  
MMCSD1 is associated with MMC1.  
The MMCSD Host Controller supports:  
• One controller with 8-bit wide data bus  
• One controller with 4-bit wide data bus  
• Support of eMMC5.1 Host Specification (JESD84-B51)  
• Support of SD Host Controller Standard Specification - SDIO 3.00  
• Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3  
• eMMC Electrical Standard 5.1 (JESD84-B51)  
• Multi-Media card features:  
– Backward compatible with earlier eMMC standards  
– Legacy MMC SDR: 1.8 V, 8/4/1-bit bus width, 0-25 MHz, 25/12.5/3.125 MB/s  
– High Speed SDR: 1.8 V, 8/4/1-bit bus width, 0-50 MHz, 50/25/6.25 MB/s  
– High Speed DDR: 1.8 V, 8/4-bit bus width, 0-50 MHz, 100/50 MB/s  
– HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s  
• SD card support: SDIO, SDR12, SDR25, SDR50, DDR50  
• System bus interface: CBA 4.0 VBUSM initiator port with 64-bit data width and 64-bit address, little Endian  
only  
• Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear  
incrementing addressing mode, little Endian only  
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in  
the device TRM.  
8.4.2.16 OSPI  
The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which  
allows single, dual, quad or octal read and write access to external flash devices. This module has a memory  
mapped register interface, which provides a direct memory interface for accessing data from external flash  
devices, simplifying software requirements.  
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor  
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up  
to silently perform some requested operation, signaling its completion via interrupts or status registers. For  
indirect operations, data is transferred between system memory and external flash memory via an internal  
SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds.  
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using  
user programmable configuration registers.  
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device  
TRM.  
8.4.2.17 Peripheral Component Interconnect Express (PCIe)  
The PCIe subsystem supports the following main features:  
• Dual mode –root port (RP) or end point (EP) modes. Selectable through bootstrap pins.  
• 1-lane configuration with up to 5.0GT/lane.  
• 62.5/125 MHz operation on PIPE interface for Gen1/Gen2 respectively  
• Constant 32-bit PIPE width for Gen1/Gen2 modes  
• Maximum outbound payload size of 128 bytes  
• Maximum inbound payload size of 128 bytes  
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• Maximum remote read request size of 4K bytes  
• Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.  
• Four virtual channels (4VC)  
• Resizable BAR capability  
• SRIS support  
• Power Management  
– L1 Power Management Substate support  
– D1 support  
– L1 Power Shutoff support  
• Legacy, MSI, and MSI-X interrupt support  
• 32 outbound address translation regions  
• Precision time measurement (PTM)  
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals  
chapter in the device TRM.  
8.4.2.18 Serializer/Deserializer (SerDes) PHY  
Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/  
Deserializer (SerDes) Multi-protocol Multi-link PHY with the following main blocks:  
• Single-lane SerDes PHY with common module for peripheral and Tx clocking handling  
• Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/  
decoding and symbol alignment  
• MUX module for device interface multiplexing into a single SerDes lane (Tx and Rx)  
• A wrapper for sending control and reporting status signals from the SerDes and muxes  
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.  
8.4.2.19 Real Time Interrupt (RTI/WWDT)  
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)  
functionality for the device.  
For more information, see Real Time Interrupt (RTI/WWDT) Module section in Peripherals chapter of the device  
TRM.  
8.4.2.20 Dual Mode Timer (DMTIMER)  
The Dual Mode Timer (DMTIMER) module supports the following main features:  
• Interrupts generated on overflow, compare, and capture events  
• Free running 32-bit upward counter  
• Supported operating modes:  
– Compare and capture modes  
– Auto-reload mode  
– Start-stop mode  
• Programmable divider clock source (2n with n=[0:8])  
• Dedicated input trigger for capture mode, and dedicated output trigger/PWM (pulse width modulation) signal  
• On the fly read/write register (while counting)  
• Generate 1-ms tick with 32768-Hz functional clock  
For more information, see Timers section in Peripherals chapter in the device TRM.  
8.4.2.21 UART  
The UART module supports the following main features:  
• 16C750 compatibility  
• Baud rate from 300 bps up to 12 Mbps (MCU_UART0 and MCU_UART1 limited to 3.7 Mbps)  
• Auto-baud between 1200 bps and 115.2 Kbps  
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• Software/hardware flow control  
– Programmable Xon/Xoff characters  
– Programmable Auto-RTS and Auto CTS  
• Programmable serial interface characteristics  
– 5-, 6-, 7-, 8-bit characters  
– Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and  
detection  
– 1-, 1.5-, or 2-stop bit generation  
• Optional multi-drop transmission  
• Configurable time-guard feature  
• False start bit detection  
• Line break generation and detection  
• Modem control functions on UART0 (CTS, RTS, DSR, DTR, RI, and DCD)  
• Fully prioritized interrupt system controls  
• Internal test and loopback capabilities  
• RS-485 External transceiver auto flow control support  
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in  
Peripherals chapter in the device TRM.  
8.4.2.22 Universal Serial Bus Subsystem (USBSS)  
The Universal Serial Bus Subsystem (USBSS) module supports the following main features:  
General USB interface:  
• Compliant with USB 3.1 specification  
• Compliant with xHCI 1.1 specification  
• Port configurable as:  
– USB host:  
• SuperSpeed Gen 1 (5 Gbps)  
• High-speed (480 Mbps)  
• Full-speed (12 Mbps)  
• Low-speed (1.5 Mbps)  
– USB device/peripheral:  
• High-speed (480 Mbps)  
• Full-speed (12Mbps)  
– USB Dual-Role device  
USB Host mode features:  
• 64 slots  
• Up to 96 periodic simultaneous endpoints  
• 256 primary streams  
• MSI  
• Root hub  
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device  
TRM.  
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9 Applications, Implementation, and Layout  
备注  
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定  
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。  
9.1 Device Connection and Layout Fundamentals  
9.1.1 Power Supply  
9.1.1.1 Power Supply Designs  
The LP8733xx Power Management IC (PMIC) is recommended for an integrated AM64x power design. This  
cost and space optimized silicon powers the latest Sitara devices and their principal peripherals. For the full  
application note and related operational details, refer to Using LP8733xx and TPS65218xx PMICs to Power  
AM64x and AM243x Sitara Processors.  
备注  
AM64x supports discrete power supply topologies and customized power designs to meet various  
system requirements.  
9.1.1.2 Power Distribution Network Implementation Guidance  
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for  
successful implementation of the power distribution network. This includes PCB stackup guidance as well as  
guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that  
follow the board design guidelines contained in the application report.  
9.1.2 External Oscillator  
For more information about External Oscillators, see the Clock Specifications section.  
9.1.3 JTAG and EMU  
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various  
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target  
Connection Guide.  
For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical  
Reference Manual  
9.1.4 Unused Pins  
For more information about Unused Pins, see the Pin Connectivity Requirements section.  
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9.2 Peripheral- and Interface-Specific Design Information  
9.2.1 DDR Board Design and Layout Guidelines  
The goal of the AM64x\AM243x DDR Board Design and Layout Guidelines is to make the DDR system  
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and  
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.  
TI only supports board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.  
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9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines  
The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or  
SPI devices.  
9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback  
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device  
• The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to  
B) must be ≤450 ps (~7cm as stripline or ~8cm as microstrip)  
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached  
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal  
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-1  
• Propagation delays and matching:  
– (A to B) ≤450 ps  
– (E to F, or F to E) = ((A to B) ± 60 ps)  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
Device Clock Input  
OSPI[x]_CLK  
OSPI[x]_LBCLKO  
OSPI Device DQS  
OSPI[x]_DQS  
E
F
OSPI[x]_D[y],  
OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
Device IO[y], CS#  
OSPI_Board_01  
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.  
图9-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad  
Loopback  
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9.2.2.2 External Board Loopback  
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device  
• The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin  
• The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be  
approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device  
CLK pin (A to B)  
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached  
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal  
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-2  
• Propagation delays and matching:  
– (C to D) = 2 x ((A to B) ± 30 ps), see the exception note below.  
– (E to F, or F to E) = ((A to B) ± 60 ps)  
备注  
The External Board Loopback hold time requirement (defined by parameter number O16 in 表 7-100,  
OSPI0 Timing Requirements - PHY DDR Mode) may be larger than the hold time provided by a typical  
OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the  
OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
Device Clock Input  
OSPI[x]_CLK  
C
R1  
0 Ω*  
OSPI[x]_LBCLKO  
D
OSPI Device DQS  
OSPI[x]_DQS  
E
F
OSPI[x]_D[y],  
OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
Device IO[y], CS#  
OSPI_Board_02  
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if  
needed.  
图9-2. OSPI Connectivity Schematic for External Board Loopback  
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9.2.2.3 DQS (only available in Octal SPI devices)  
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device  
• The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin  
• The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D  
to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached  
OSPI/QSPI/SPI device CLK pin (A to B)  
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached  
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal  
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-3  
• Propagation delays and matching:  
– (D to C) = ((A to B) ± 30 ps)  
– (E to F, or F to E) = ((A to B) ± 60 ps)  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
Device Clock Input  
OSPI[x]_CLK  
OSPI[x]_LBCLKO  
C
D
OSPI Device DQS  
OSPI[x]_DQS  
E
F
OSPI[x]_D[y],  
OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
Device IO[y], CS#  
OSPI_Board_03  
* 0 Ωresistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.  
图9-3. OSPI Connectivity Schematic for DQS  
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9.2.3 USB VBUS Design Guidelines  
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as  
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to  
be 30 V.  
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the  
图 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these external  
resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5 V should be less than  
100 nA.  
Device  
USBn_VBUS  
16.5 kΩ  
1%  
3.5 kΩ  
1%  
VBUS signal  
10 kΩ  
1%  
6.8V  
(BZX84C6V8 or equivalent)  
VSS  
VSS  
J7ES_USB_VBUS_01  
图9-4. USB VBUS Detect Voltage Divider / Clamp Circuit  
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in 图 9-4 limits the input  
current to the actual device pin in a case where VBUS is applied while the device is powered off.  
9.2.4 System Power Supply Monitor Design Guidelines  
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a  
single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via and  
external resistor divider circuit. This system supply is monitored by comparing the external voltage divider output  
voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied to  
VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point is  
determined by the system designer when selecting component values used to implement the external resistor  
voltage divider circuit.  
When building the resistor divider circuit the designer must understand various factors which contribute to  
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the  
VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1%  
resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This  
minimizes variability contributed by resistor value tolerances. Input leakage current associated with  
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the  
voltage divider output. The VMON_VSYS input leakage current can be in the range of 10 nA to 2.5 µA when  
applying 0.45 V.  
备注  
The resistor voltage divider shall be designed such that the output voltage never exceeds the  
maximum value defined in the Recommended Operating Conditions section, during normal operating  
conditions.  
图9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger threshold  
is 5 V - 10%, or 4.5 V.  
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For this example, the designer must understand which variables effect the maximum trigger threshold when  
selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45 V + 3% needs to be  
considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The  
effect of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum  
trigger point is not obvious. When selecting component values which produce a maximum trigger voltage, the  
system designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high  
combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When implementing a  
resistor divider where R1 = 4.81 KΩand R2 = 40.2 KΩ, the result is a maximum trigger threshold of 4.517 V.  
Once component values have been selected to satisfy the maximum trigger voltage as described above, the  
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an  
output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input  
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result  
is a minimum trigger threshold of 4.013 V.  
This example demonstrates a system power supply voltage trip point that ranges from 4.013 V to 4.517 V.  
Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,  
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this  
range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.  
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor  
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above can be reduced to about  
10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor divider bias  
current vs loading error is something the system designer needs to consider when selecting component values.  
The system designer must also consider implementing a noise filter on the voltage divider output since  
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by  
installing a capacitor across R1 as shown in 图9-5. However, the system designer must determine the response  
time of this filter based on system supply noise and expected response to transient events.  
Device  
VMON_VSYS  
R2  
VSYS  
40.2 kΩ 1%  
C1  
Value = Determined by system designer  
(System Power Supply)  
4.81 kΩ  
1%  
R1  
VSS  
SPRSP56_VMON_ER_MON_01  
图9-5. System Supply Monitor Voltage Divider Circuit  
VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8 V power supplies. These  
pins must be connected directly to their respective power source. An internal resistor divider with software  
control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider  
to create appropriate under voltage and over voltage interrupts.  
VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3 V power supplies. These  
pins must be connected directly to their respective power source. An internal resistor divider with software  
control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider  
to create appropriate under voltage and over voltage interrupts.  
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9.2.5 High Speed Differential Signal Routing Guidance  
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed  
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and  
spacing limits. TI supports only designs that follow the board design guidelines contained in the application  
report.  
9.2.6 Thermal Solution Guidance  
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful  
implementation of a thermal solution for system designs containing this device. This document provides  
background information on common terms and methods related to thermal solutions. TI only supports designs  
that follow system design guidelines contained in the application report.  
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10 Device and Documentation Support  
10.1 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
embedded processor devices and support tools. Each device has one of three prefixes: X, P, or null (no prefix)  
(for example, XAM6442ASFGGAALV). Texas Instruments recommends two of three possible prefix designators  
for related support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product  
development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).  
Device development evolutionary flow:  
X
P
Experimental device that is not necessarily representative of the device's final electrical  
specifications and may not use production assembly flow.  
Prototype device that is not necessarily the final silicon die and may not necessarily meet final  
electrical specifications.  
null (BLANK) Production version of the silicon die that is fully qualified and meets final electrical specifications.  
Support tool development evolutionary flow:  
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.  
TMDS Fully-qualified development-support product.  
X and P devices and TMDX development-support tools are shipped against the following disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
Production devices and TMDS development-support tools have been characterized fully, and the quality and  
reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system because their  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
For orderable part numbers of AM64x devices in the ALV package type, see the Package Option Addendum at  
the end of this document, the TI website (ti.com), or contact your TI sales representative.  
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10.1.1 Standard Package Symbolization  
备注  
Some devices may have a cosmetic circular marking visible on the top of the device package which  
results from the production test process. In addition, some devices may also show a color variation in  
the package substrate which results from the substrate manufacturer. These differences are cosmetic  
only with no reliability impact.  
SITARA  
aBBBBBBr  
ZfYytPPPQ1  
XXXXXXX  
A1 (PIN ONE INDICATOR)  
G1  
YYY  
O
图10-1. Printed Device Reference  
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10.1.2 Device Naming Convention  
表10-1. Nomenclature Description  
FIELD PARAMETER FIELD DESCRIPTION  
VALUE  
DESCRIPTION  
X
P
Prototype  
a
Device evolution stage  
Preproduction (production test flow, no reliability data)  
Production  
BLANK  
AM6442  
AM6441  
AM6422  
AM6421  
AM6412  
AM6411  
A
Base production part  
number  
BBBBBB  
See 表5-1, Device Comparison  
Silicon Revision (SR) 1.0  
SR 2.0  
r
Device revision  
B
S
Z
Device Speed Grades  
See 表7-1, Speed Grade Maximum Frequency  
K
C
All PRU_ICSSG features are enabled except for industrial  
communication support. PRU_ICSSG industrial communication  
interfaces include Ethernet networking (MII/RGMII, MDIO), Sigma-Delta  
(SD) decimation, and three channel peripheral interface (EnDat 2.2 and  
BiSS)  
Features  
(see 表5-1)  
f
D
E
Features supported by C, plus PRU_ICSSG industrial communication is  
enabled  
Features supported by D, plus EtherCAT HW Accelerator and CAN-FD  
are enabled  
F
G
F
Features supported by E, plus Pre-integrated Stacks are enabled  
Non-Functional Safety  
Functional Safety  
Non-Secure  
Y
y
Functional Safety  
Security  
G
H
A
Secure  
-40°C to 105°C - Extended Industrial (see 节7.4, Recommended  
Operating Conditions)  
t
Temperature (1)  
PPP  
Package Designator  
ALV  
Q1  
ALV FCBGA-N441 (17.2 mm × 17.2 mm) Package  
Auto Qualified (Q100)  
Q1  
Automotive Designator  
BLANK  
Standard  
XXXXXXX  
Lot Trace Code (LTC)  
YYY  
O
Production Code; For TI use only  
Pin one designator  
G1  
ECAT—Green package designator  
(1) Applies to device max junction temperature.  
备注  
BLANK in the symbol or part number is collapsed so there are no gaps between characters.  
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10.2 Tools and Software  
The following Development Tools support development for TI's Embedded Processing platforms:  
Development Tools  
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated  
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded  
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded  
applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment,  
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through  
each step of the application development flow. Familiar tools and interfaces allow users to get started faster than  
ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced  
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for  
embedded developers.  
SysConfig-PinMux Tool The SysConfig-PinMux Tool is a software tool which provides a Graphical User  
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI  
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration  
to satisfy entered system requirements. The tool generates output C header/code files that can be imported into  
software development kits (SDKs) and used to configure customer's software to meet custom hardware  
requirements. The Cloud-based SysConfig-PinMux Tool is also available.  
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments  
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized  
distributor.  
10.3 Documentation Support  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
The following documents describe the AM64x devices.  
Technical Reference Manual  
AM64x/AM243x Processors Silicon Revision 1.0 Technical Reference Manual Details the integration, the  
environment, the functional description, and the programming models for each peripheral and subsystem in the  
AM64x family of devices.  
Errata  
AM64x/AM243x Processors Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the  
functional specifications for the device.  
10.4 支持资源  
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅  
TI 的《使用条款》。  
10.5 Trademarks  
Sitara™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.  
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
Arm®, Cortex®, and TrustZone® are registered trademarks of Arm Limited.  
PCI-Express® is a registered trademark of PCI-SIG.  
EtherCAT® is a registered trademark of Beckhoff Automation GmbH.  
所有商标均为其各自所有者的财产。  
Copyright © 2022 Texas Instruments Incorporated  
252 Submit Document Feedback  
Product Folder Links: AM6442 AM6441 AM6422 AM6421 AM6412 AM6411  
 
 
 
 
AM6442, AM6441, AM6422, AM6421, AM6412, AM6411  
www.ti.com.cn  
ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
10.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
10.7 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback 253  
Product Folder Links: AM6442 AM6441 AM6422 AM6421 AM6412 AM6411  
 
 
AM6442, AM6441, AM6422, AM6421, AM6412, AM6411  
ZHCSN84E –JANUARY 2021 –REVISED SEPTEMBER 2022  
www.ti.com.cn  
11 Mechanical, Packaging, and Orderable Information  
11.1 Packaging Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
Copyright © 2022 Texas Instruments Incorporated  
254 Submit Document Feedback  
Product Folder Links: AM6442 AM6441 AM6422 AM6421 AM6412 AM6411  
 
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-May-2023  
PACKAGING INFORMATION  
Orderable Device  
AM6411BKCGHAALV  
AM6411BSCGHAALV  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
-40 to 105  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
ACTIVE  
FCBGA  
FCBGA  
ALV  
441  
441  
84  
RoHS & Green  
RoHS & Green  
Call TI  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
AM6411B  
KCGHAALV  
709  
Samples  
Samples  
ACTIVE  
ALV  
84  
Call TI  
-40 to 105  
AM6411B  
SCGHAALV  
709  
AM6412BKCGHAALV  
AM6412BSCGHAALV  
PREVIEW  
ACTIVE  
FCBGA  
FCBGA  
ALV  
ALV  
441  
441  
84  
84  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 105  
-40 to 105  
RoHS & Green  
Level-3-250C-168 HR  
AM6412B  
SCGHAALV  
709  
Samples  
AM6421BSDGHAALV  
AM6421BSEFHAALV  
AM6421BSFFHAALV  
PREVIEW  
PREVIEW  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
ALV  
ALV  
ALV  
441  
441  
441  
84  
84  
84  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 105  
-40 to 105  
-40 to 105  
RoHS & Green  
Level-3-250C-168 HR  
AM6421B  
SFFHAALV  
709  
Samples  
Samples  
Samples  
Samples  
AM6421BSFGHAALV  
AM6422BSDGHAALV  
AM6441BSEFHAALV  
ACTIVE  
ACTIVE  
ACTIVE  
FCBGA  
FCBGA  
FCBGA  
ALV  
ALV  
ALV  
441  
441  
441  
84  
84  
84  
RoHS & Green  
RoHS & Green  
RoHS & Green  
Call TI  
Call TI  
Call TI  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 105  
-40 to 105  
-40 to 105  
AM6421B  
SFGHAALV  
709  
AM6422B  
SDGHAALV  
709  
AM6441B  
SEFHAALV  
709  
AM6441BSEGHAALV  
AM6441BSFFHAALV  
PREVIEW  
ACTIVE  
FCBGA  
FCBGA  
ALV  
ALV  
441  
441  
84  
84  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 105  
-40 to 105  
RoHS & Green  
Level-3-250C-168 HR  
AM6441B  
SFFHAALV  
709  
Samples  
Samples  
Samples  
AM6442BSDGHAALV  
AM6442BSEFHAALV  
ACTIVE  
ACTIVE  
FCBGA  
FCBGA  
ALV  
ALV  
441  
441  
84  
84  
RoHS & Green  
RoHS & Green  
Call TI  
Call TI  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
-40 to 105  
-40 to 105  
AM6442B  
SDGHAALV  
709  
AM6442B  
SEFHAALV  
709  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-May-2023  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
AM6442BSEGHAALV  
AM6442BSFFHAALV  
PREVIEW  
ACTIVE  
FCBGA  
FCBGA  
ALV  
ALV  
441  
441  
84  
84  
TBD  
Call TI  
Call TI  
Call TI  
-40 to 105  
-40 to 105  
RoHS & Green  
Level-3-250C-168 HR  
AM6442B  
SFFHAALV  
709  
Samples  
Samples  
AM6442BSFGHAALV  
ACTIVE  
FCBGA  
ALV  
441  
84  
RoHS & Green  
Call TI  
Level-3-250C-168 HR  
-40 to 105  
AM6442B  
SFGHAALV  
709  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
23-May-2023  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
25-Mar-2023  
TRAY  
L - Outer tray length without tabs  
KO -  
Outer  
tray  
height  
W -  
Outer  
tray  
width  
Text  
P1 - Tray unit pocket pitch  
CW - Measurement for tray edge (Y direction) to corner pocket center  
CL - Measurement for tray edge (X direction) to corner pocket center  
Chamfer on Tray corner indicates Pin 1 orientation of packed units.  
*All dimensions are nominal  
Device  
Package Package Pins SPQ Unit array  
Max  
matrix temperature  
(°C)  
L (mm)  
W
K0  
P1  
CL  
CW  
Name  
Type  
(mm) (µm) (mm) (mm) (mm)  
AM6411BKCGHAALV  
AM6411BSCGHAALV  
AM6412BSCGHAALV  
AM6421BSFFHAALV  
AM6421BSFGHAALV  
AM6422BSDGHAALV  
AM6441BSEFHAALV  
AM6441BSFFHAALV  
AM6442BSDGHAALV  
AM6442BSEFHAALV  
AM6442BSFFHAALV  
AM6442BSFGHAALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
ALV  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
FCBGA  
441  
441  
441  
441  
441  
441  
441  
441  
441  
441  
441  
441  
84  
84  
84  
84  
84  
84  
84  
84  
84  
84  
84  
84  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
6 x 14  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
150  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
315 135.9 7620  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
22  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
14.5 14.55  
Pack Materials-Page 1  
PACKAGE OUTLINE  
ALV0441A  
FCBGA - 2.657 mm max height  
SCALE 0.900  
BALL GRID ARRAY  
17.3  
17.1  
A
B
BALL A1 CORNER  
PIN 1 ID  
(OPTIONAL)  
17.3  
17.1  
(
12.8)  
0.1 C  
(
(
10.8)  
16.8)  
(1.45)  
2.652  
2.332  
0.2 C  
C
SEATING PLANE  
0.15 C  
(0.662)  
0.5  
TYP  
0.3  
16 TYP  
SYMM  
(0.6) TYP  
(0.6) TYP  
0.8 TYP  
AA  
Y
W
V
U
T
R
P
N
M
L
SYMM  
16  
K
J
TYP  
H
G
F
E
D
C
B
A
0.55  
0.45  
C A B  
441X  
0.25  
0.1  
1
2
3
4
5
6 7 8 9 10 12 14 16 18 20  
11 13 15 17 19 21  
C
0.8 TYP  
4225999/A 06/2020  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
ALV0441A  
FCBGA - 2.657 mm max height  
BALL GRID ARRAY  
441X ( 0.4)  
(0.8) TYP  
1
2 3  
4
5
6
7
8
9
10 11 12 13 14 15 16  
20 21  
17 18 19  
A
(0.8) TYP  
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
LAND PATTERN EXAMPLE  
EXPOSED METAL SNOWN  
SCALE:6X  
0.07 MAX  
0.07 MIN  
METAL UNDER  
SOLDER MASK  
(
0.4)  
METAL  
EXPOSED METAL  
(
0.4)  
SOLDER MASK  
OPENING  
EXPOSED METAL  
SOLDER MASK  
OPENING  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4225999/A 06/2020  
NOTES: (continued)  
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
ALV0441A  
FCBGA - 2.657 mm max height  
BALL GRID ARRAY  
441X 0.4  
(0.8) TYP  
1
2 3  
4
5
6
7
8
9
10 11 12 13 14 15 16  
20 21  
17 18 19  
A
(0.8) TYP  
B
C
D
E
F
G
H
J
K
L
SYMM  
M
N
P
R
T
U
V
W
Y
AA  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.15 mm THICK STENCIL  
SCALE: 6X  
4225999/A 06/2020  
NOTES: (continued)  
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
本、损失和债务，TI 对此概不负责。  
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE  
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023，德州仪器 (TI) 公司  

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