AM6442BSFGHAALV [TI]
双核 64 位 Arm® Cortex®-A53，四核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性 | ALV | 441 | -40 to 105;
| 型号： | AM6442BSFGHAALV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双核 64 位 Arm® Cortex®-A53，四核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性 | ALV | 441 | -40 to 105 PC |
| 文件： | 总237页 (文件大小：5006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AM6442, AM6441, AM6421
AM6412, AM6411
SPRSP56 – JANUARY 2021
AM64x Sitara™ Processors
•
Two 64-bit Industrial Ethernet Peripherals
(IEPs) for time stamping and other time
synchronization functions
1 Features
Processor cores:
•
18× Sigma-Delta filters
– Short circuit logic
•
1× Dual 64-bit Arm® Cortex®-A53 microprocessor
subsystem at up to 1.0 GHz
– Over-current logic
– Dual-core Cortex-A53 cluster with 256KB L2
shared cache with SECDED ECC
– Each A53 Core has 32KB L1 DCache with
SECDED ECC and 32KB L1 ICache with Parity
protection
2× Dual-core Arm® Cortex®-R5F MCU subsystems
at at up to 800 MHz, integrated for real-time
processing
•
•
•
6× Multi-protocol position encoder interfaces
One Enhanced Capture Module (ECAP)
16550-compatible UART with a dedicated
192-MHz clock to support 12-Mbps
PROFIBUS
•
Memory subsystem:
– Dual-core Arm® Cortex®-R5F supports dual-
•
Up to 2MB of On-chip RAM (OCSRAM) with
SECDED ECC:
core and single-core modes
– Can be divided into smaller banks in
increments of 256KB for as many as 8 separate
memory banks
– Each memory bank can be allocated to a single
core to facilitate software task partitioning
DDR Subsystem (DDRSS)
– 32KB ICache, 32KB DCache and 64KB TCM
per each R5F core for a total of 256KB TCM
with SECDED ECC on all memories
1× Single-core Arm® Cortex®-M4F MCU at up to
400 MHz
•
•
•
– 256KB SRAM with SECDED ECC
– Supports LPDDR4, DDR4 memory types
– 16-Bit data bus with inline ECC
Industrial subsystem:
•
2× gigabit Industrial Communication Subsystems
(PRU_ICSSG)
– Supports Profinet IRT, Profinet RT, EtherNet/IP,
EtherCAT, Time-Sensitive Networking (TSN),
and more
– Supports speeds up to 1600 MT/s
1× General-Purpose Memory Controller (GPMC)
– 16-Bit parallel bus with 133 MHz clock or
– 32-Bit parallel bus with 100 MHz clock
– Error Location Module (ELM) support
– Backward compatibility with 10/100Mb
PRU_ICSS
System on Chip (SoC) Services:
– Each PRU_ICSSG contains:
•
Device Management Security Controller (DMSC-L)
– Centralized SoC system controller
– Manages system services including initial boot,
security, and clock/reset/power management
– Communication with various processing units
over message manager
•
•
2× 10/100/1000 Ethernet ports
6 PRU RISC cores per PRU_ICSSG each
core having:
– Instruction RAM with ECC
– Broadside RAM
– Multiplier with optional accumulator
(MAC)
– Simplified interface for optimizing unused
peripherals
– CRC16/32 hardware accelerator
– Byte swap for Big/Little Endian
conversion
– SUM32 hardware accelerator for UDP
checksum
– Task Manager for preemption support
Three Data RAMs with ECC
8 banks of 30 × 32-bit register scratchpad
memory
•
Data Movement Subsystem (DMSS)
– Block Copy DMA (BCDMA)
– Packet DMA (PKTDMA)
– Secure Proxy (SEC_PROXY)
– Ring Accelerator (RINGACC)
•
•
Security:
•
Secure boot supported
– Hardware-enforced Root-of-Trust (RoT)
– Support to switch RoT via backup key
•
Interrupt controller and task manager
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
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AM6412, AM6411
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– Support for takeover protection, IP protection,
and anti-roll back protection
Cryptographic acceleration supported
– Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming
data stream
•
•
9× configurable Universal Asynchronous Recieve/
Transmit (UART) modules
1× Flash Subsystem (FSS) that can be configured
as Octal SPI (OSPI) flash interfaces or one Quad
SPI (QSPI)
1× 12-Bit Analog-to-Digital Converters (ADC)
– Up to 4 MSPS
•
•
– Supports cryptographic cores
•
•
•
•
•
•
AES – 128/192/256 Bits key sizes
3DES – 56/112/168 Bits key sizes
MD5, SHA1
– 8× multiplexed analog inputs
7× Multichannel Serial Peripheral Interfaces
(MCSPI) controllers
6× Fast Serial Interface Receiver (FSI_RX) cores
2× Fast Serial Interface Transmitter (FSI_TX)
cores
•
•
•
SHA2 – 224/256/384/512
DRBG with true random number generator
PKA (Public Key Accelerator) to Assist in
RSA/ECC processing
•
3× General-Purpose I/O (GPIO) modules
– DMA support
Debugging security
– Secure software controlled debug access
– Security aware debugging
Trusted Execution Environment (TEE) supported
– Arm TrustZone® based TEE
– Extensive firewall support for isolation
– Secure watchdog/timer/IPC
Secure storage support
On-the-Fly encryption and authentication support
for OSPI interface in XIP mode
Networking security support for data (Payload)
encryption/authentication via packet based
hardware cryptographic engine
Control interfaces:
•
•
•
9x Enhanced Pulse-Width Modulator (EPWM)
modules
•
•
3× Enhanced Capture (ECAP) modules
3× Enhanced Quadrature Encoder Pulse (EQEP)
modules
•
2× Modular Controller Area Network (MCAN)
modules with or without full CAN-FD support
•
•
Media and data storage:
•
2× Multi-Media Card/Secure Digital (MMC/SD/
SDIO) interfaces
•
•
– One 4-bit for SD/SDIO;
– One 8-bit for eMMC
Security co-processor (DMSC-L) for key and
security management, with dedicated device level
interconnect for security
– Integrated analog switch for voltage switching
between 3.3V to 1.8V for high-speed cards
Power management:
High-speed interfaces:
•
•
Simplified power sequence
Integrated SDIO LDO for handling automatic
voltage transition for SD interface
•
1× Integrated Ethernet switch supporting
– Up to 2 RGMII (10/100/1000)
– IEEE 1588 (2008 Annex D, Annex E, Annex F)
with 802.1AS PTP
– Clause 45 MDIO PHY management
– Energy efficient Ethernet (802.3az)
1× PCI-Express® Gen2 controller (PCIE)
– Supports Gen2 operation
•
•
Integrated voltage supervisor for safety monitoring
of over-under voltage conditions
Integrated power supply glitch detector for
detecting fast supply transients
•
•
– Supports Single Lane operation
1× USB 3.1-Gen1 Dual-Role Device (DRD)
Subsystem (USBSS)
– One enhanced SuperSpeed Gen1 port
– Port configurable as USB host, USB peripheral,
or USB Dual-Role Device
– Integrated USB VBUS detection
General connectivity:
•
6× Inter-Integrated Circuit (I2C) ports
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Functional Safety:
SoC architecture:
•
Functional Safety-Compliant targeted
– Developed for functional safety applications
– Documentation will be available to aid IEC
61508 functional safety system design
– Systematic capability up to SIL 3
– Hardware integrity up to SIL 2 targeted for MCU
domain
•
Supports primary boot from UART, I2C, OSPI/
QSPI Flash, SPI Flash, parallel NOR Flash,
parallel NAND Flash, SD, eMMC, USB 2.0, PCIe,
and Ethernet interfaces
16-nm FinFET technology
17.2 mm × 17.2 mm, 0.8-mm pitch, 441-pin BGA
package
•
•
– Quality-Managed Main Domain
– Safety-related certification
•
IEC 61508 certification planned
– ECC or parity on calculation-critical memories
– ECC and parity on select internal bus
interconnect
– Built-In Self-Test (BIST) for CPU and on-chip
RAM
– Error Signaling Module (ESM) with error pin
– Runtime safety diagnostics, voltage,
temperature, and clock monitoring, windowed
watchdog timers, CRC engine for memory
integrity checks
– Dedicated MCU domain memory, interfaces,
and M4F core capable of being isolated from
the larger SoC with Freedom From Interference
(FFI) features
•
•
•
•
•
Separate interconnect
Firewalls and timeout gaskets
Dedicated PLL
Dedicated I/O supply
Separate reset
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2 Applications
•
•
•
•
Programmable Logic Controller (PLC)
Motor Drives
Remote I/O
Industrial Robots
3 Description
AM64x is an extension of Sitara’s industrial-grade family of heterogeneous Arm processors. AM64x is built for
industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a
unique combination of real-time processing and communications with applications processing. AM64x combines
two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Arm Cortex-A53 cores, up to four
Cortex-R5F MCUs, and a Cortex-M4F MCU.
AM64x is architected to provide best-in-class real-time performance through the high-performance R5Fs, Tightly-
Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from
peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to
handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta
decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these
systems.
The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-
time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term
Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux
world with the real-time world by enabling isolation between Linux applications and real-time streams through
configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and
the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.
The PRU-ICSSG in AM64x provides the flexible industrial communications capability necessary to run gigabit
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU-ICSSG also enables
additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.
Functional safety features can be enabled through the integrated Cortex-M4F along with its dedicated
peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
Device Information
PART NUMBER
AM6442...ALV
PACKAGE(1)
BODY SIZE
(441-Pin) FCBGA
(441-Pin) FCBGA
(441-Pin) FCBGA
(441-Pin) FCBGA
(441-Pin) FCBGA
17.2 mm × 17.2 mm
17.2 mm × 17.2 mm
17.2 mm × 17.2 mm
17.2 mm × 17.2 mm
17.2 mm × 17.2 mm
AM6441...ALV
AM6421...ALV
AM6412...ALV
AM6411...ALV
(1) For more information, see Section 11, Mechanical, Packaging, and Orderable Information.
3.1 Functional Block Diagram
Figure 3-1 is functional block diagram for the device.
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A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across SoC when in non-isolated
configuration.
Note
One port is internally connected only; not connected to any pins.
Note
USB3.1 and PCIe share a common SerDes lanes.
Figure 3-1. Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................4
3 Description.......................................................................4
3.1 Functional Block Diagram...........................................4
4 Revision History.............................................................. 6
5 Device Comparison.........................................................7
5.1 Related Products........................................................ 9
6 Terminal Configuration and Functions........................10
6.1 Pin Diagram.............................................................. 10
6.2 Pin Attributes.............................................................11
6.3 Signal Descriptions................................................... 56
6.4 Pin Multiplexing.........................................................92
6.5 Connections for Unused Pins................................. 103
7 Specifications.............................................................. 106
7.1 Absolute Maximum Ratings.................................... 106
7.2 ESD Ratings........................................................... 107
7.3 Power-On Hours (POH)..........................................107
7.4 Recommended Operating Conditions.....................109
7.5 Operating Performance Points................................110
7.6 Power Consumption Summary............................... 110
7.7 Electrical Characteristics.........................................110
7.8 VPP Specifications for One-Time Programmable
7.9 Thermal Resistance Characteristics....................... 119
7.10 Timing and Switching Characteristics................... 120
8 Detailed Description....................................................208
8.1 Overview.................................................................208
8.2 Processor Subsystems........................................... 209
8.3 Accelerators and Coprocessors..............................211
8.4 Other Subsystems...................................................211
9 Applications, Implementation, and Layout............... 220
9.1 Power Supply Mapping...........................................220
9.2 Device Connection and Layout Fundamentals....... 220
9.3 Peripheral- and Interface-Specific Design
Information................................................................ 221
10 Device and Documentation Support........................227
10.1 Device Nomenclature............................................227
10.2 Tools and Software............................................... 229
10.3 Documentation Support........................................ 230
10.4 Support Resources............................................... 230
10.5 Trademarks...........................................................230
10.6 Electrostatic Discharge Caution............................230
10.7 Glossary................................................................230
11 Mechanical, Packaging, and Orderable
Information.................................................................. 231
11.1 Packaging Information.......................................... 231
(OTP) eFuses............................................................117
4 Revision History
DATE
REVISION
NOTES
January 2021
*
Initial external release.
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5 Device Comparison
Table 5-1 shows a comparison between devices, highlighting the differences.
Table 5-1. Device Comparison
REFERENCE
NAME
FEATURES(1)
Features
AM6442
AM6441
AM6421
AM6412
AM6411
CTRLMMR_WKUP_JTAG_DEVICE_ID[31:13
] DEVICE_ID register bit field value(3)
C: 0x19403
C: 0x19203
D: 0x19464
E: 0x19465
F: 0x19466
D: 0x19264
E: 0x19265
F: 0x19266
D: 0x19224
E: 0x19225
F: 0x19226
PROCESSORS AND ACCELERATORS
Speed Grades
See Table 7-1
Dual Core
See Table 7-1
Single Core
See Table 7-1
Single Core
See Table 7-1
Dual Core
See Table 7-1
Single Core
Arm Cortex-A53
Arm A53
Microprocessor Subsystem
Arm Cortex-R5F
Arm Cortex-M4F
Arm R5F
Arm M4F
2 × Dual Core
Single Core
Yes
2 × Dual Core
Single Core
Yes
1 × Dual Core
Single Core
Yes
Single Core
Single Core
Yes
Single Core
Single Core
Yes
Device Management Security DMSC-L
Controller
Cryto Accelerators
Security
Safety
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MCU domain with Arm
Cortex-M4F
PROGRAM AND DATA STORAGE
On-Chip Shared Memory
(RAM) in MAIN Domain
OCSRAM
2MB
2MB
2MB
2MB
2MB
R5F Tightly Coupled Memory TCM
(TCM)
256KB
256KB
256KB
256KB
256KB
256KB
128KB
256KB
128KB
256KB
On-Chip Shared Memory
(RAM) in M4F Domain
MCU_MSRA
M
DDR4/LPDDR4 DDR
Subsystem
DDRSS
Up to 2GB (16-
bit data) with
inline ECC
Up to 2GB (16-
bit data) with
inline ECC
Up to 2GB (16-
bit data) with
inline ECC
Up to 2GB (16-
bit data) with
inline ECC
Up to 2GB (16-
bit data) with
inline ECC
General-Purpose Memory
Controller
GPMC
MCAN
Up to 1GB with
ECC
Up to 1GB with
ECC
Up to 1GB with
ECC
Up to 1GB with
ECC
Up to 1GB with
ECC
PERIPHERALS
Modular Controller Area
Network Interface
2
2
2
2
2
Full CAN-FD Support
General-Purpose I/O
MCAN
GPIO
I2C
Optional
Up to 198
4
Optional
Up to 198
4
Optional
Up to 198
4
No
Up to 198
4
No
Up to 198
4
Inter-Integrated Circuit
Interface
Analog-to-Digital Converter
ADC
1
7
1
7
1
7
1
7
1
7
Multichannel Serial Peripheral MCSPI
Interface
Multi-Media Card/ Secure
Digital Interface
MMCSD0
eMMC (8-bits)
eMMC (8-bits)
eMMC (8-bits)
eMMC (8-bits)
eMMC (8-bits)
MMCSD1
FSI_TX
SD/SDIO (4-bits) SD/SDIO (4-bits) SD/SDIO (4-bits) SD/SDIO (4-bits) SD/SDIO (4-bits)
Fast Serial Interface
2
2
2
2
6
2
6
FSI_RX
6
6
6
Flash Subsystem (FSS)
OSPI0/QSPI0
PCIE0
Yes(2)
Yes(2)
Yes(2)
Yes(2)
Yes(2)
PCI Express Port with
Integrated PHY
Single Lane
Single Lane
Single Lane
Single Lane
Single Lane
Programmable Real-Time Unit PRU_ICSSG
Subsystem
2
2
2
2
2
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Table 5-1. Device Comparison (continued)
REFERENCE
NAME
FEATURES(1)
AM6442
AM6441
AM6421
AM6412
AM6411
Industrial Communication
Subsystem Support
PRU_ICSSG
Optional
Optional
Optional
No
No
Gigabit Ethernet Interface
General-Purpose Timers
CPSW3G
TIMER
Yes
Yes
Yes
Yes
Yes
16 (4 in MCU
Channel)
16 (4 in MCU
Channel)
16 (4 in MCU
Channel)
16 (4 in MCU
Channel)
16 (4 in MCU
Channel)
Enhanced Pulse-Width
Modulator Module
EPWM
9
9
9
9
9
Enhanced Capture Module
ECAP
EQEP
3
3
3
3
3
3
3
3
3
3
Enhanced Quadrature
Encoder Pulse Module
Universal Asynchronous
Receiver and Transmitter
UART
9
9
9
9
9
Universal Serial Bus (USB3.1 USB0
Gen1) SuperSpeed Dual-
Role-Device (DRD) Ports with
SS PHY
Yes
Yes
Yes
Yes
Yes
(1) Features noted as “not supported”, must not be used. Their functionality is not supported by TI for this family of devices. These
features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been
retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.
(2) One simultaneous flash interfaces configured as OSPI0 or QSPI0.
(3) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device TRM.
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5.1 Related Products
Sitara™ processors Broad family of scalable processors based on Arm® Cortex®-A cores with flexible
accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara
processors have the reliability needed for use in industrial applications.
AM64x Sitara™ processors AM6x processors enable gigabit industrial Ethernet networks, robust operation
with extensive ECC on memories, and enhanced security features. Additional features such as an integrated
lockstep MCU subsystem and diagnostic libraries help enable functional safety systems.
Sitara™ processors - Applications Sitara™ processors provide scalable solutions for a wide range of
applications from HMIs and gateways to more complex equipment such as drives and substation automation
equipment. Sitara processors also offer multi-protocol support for industrial communication protocols such as
EtherCAT®, Ethernet/IP, and Profinet.
Sitara™ processors - Reference designs TI provides many reference designs containing ‘building block’
solutions to enable customers to rapidly develop their own unique products and solutions.
Companion Products for AM64x Review products that are frequently purchased or used in conjunction with
this product to complete your design.
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6 Terminal Configuration and Functions
6.1 Pin Diagram
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.
Figure 6-1 shows the ball locations for the 441-ball flip chip ball grid array (FCBGA) package that are used in
conjunction with Table 6-1 through Table 6-79 (Pin Attributes table through Reserved Balls table) to locate signal
names and ball grid numbers.
Figure 6-1. ALV FCBGA-N441 Pin Diagram (Bottom View)
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6.2 Pin Attributes
Table 6-1. Pin Attributes (ALV Package)
BALL
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
RESET
REL.
STATE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
MUXMODE
G20
F20
E21
D20
G21
F21
F19
E20
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
ADC0_AIN0
0
0
0
0
0
0
0
0
A
A
A
A
A
A
A
A
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_AD Yes
C0
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC12B
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
VDDA_AD Yes
C0
VDDA_AD Yes
C0
VDDA_AD Yes
C0
VDDA_AD Yes
C0
VDDA_AD Yes
C0
VDDA_AD Yes
C0
VDDA_AD Yes
C0
H12
T7
CAP_VDDS0
CAP_VDDS0
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
O
CAP_VDDS1
CAP_VDDS1
R11
N14
M16
L13
K15
H10
H2
CAP_VDDS2
CAP_VDDS2
CAP_VDDS3
CAP_VDDS3
CAP_VDDS4
CAP_VDDS4
CAP_VDDS5
CAP_VDDS5
CAP_VDDSHV_MMC1
CAP_VDDS_MCU
DDR0_ACT_n
CAP_VDDSHV_MMC1
CAP_VDDS_MCU
DDR0_ACT_n
1.1 V/1.2 V VDDS_DD
DDR
DDR
DDR
DDR
DDR
R,
VDDS_DD
R_C
H1
J5
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
IO
O
O
O
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
K5
F6
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
DDR0_RAS_n
DDR0_RAS_n
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
H4
DDR0_WE_n
DDR0_WE_n
O
O
O
O
O
O
O
O
O
O
O
O
O
1.1 V/1.2 V VDDS_DD
DDR
R,
VDDS_DD
R_C
D2
C5
E2
D4
D3
F2
J2
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
DDR0_A5
DDR0_A6
DDR0_A7
DDR0_A8
DDR0_A9
DDR0_A10
DDR0_A11
1.1 V/1.2 V VDDS_DD
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
L5
J3
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
J4
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
K3
J1
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
M5
DDR0_A12
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
O
O
O
O
O
O
A
1.1 V/1.2 V VDDS_DD
DDR
R,
VDDS_DD
R_C
K4
G4
G5
G2
H3
H5
F1
E1
F4
F3
E3
E4
DDR0_A13
1.1 V/1.2 V VDDS_DD
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
R,
VDDS_DD
R_C
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
DDR0_CAL0
DDR0_CK0
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
O
O
O
O
O
O
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
B2
DDR0_DM0
DDR0_DM0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1.1 V/1.2 V VDDS_DD
DDR
R,
VDDS_DD
R_C
M2
A3
A2
B5
A4
B3
C4
C2
B4
N5
L4
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
1.1 V/1.2 V VDDS_DD
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
L2
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
M3
DDR0_DQ11
DDR0_DQ11
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
1.1 V/1.2 V VDDS_DD
DDR
R,
VDDS_DD
R_C
N4
N3
M4
N2
C1
B1
N1
M1
E5
F5
D5
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
1.1 V/1.2 V VDDS_DD
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
O
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
O
1.1 V/1.2 V VDDS_DD
R,
VDDS_DD
R_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
D18
ECAP0_IN_APWM_OUT
ECAP0_IN_APWM_OUT
SYNC0_OUT
0
1
2
5
6
7
0
IO
O
I
0
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
1/1
CPTS0_RFT_CLK
CP_GEMAC_CPTS0_RFT_CLK
SPI4_CS3
0
0
1
I
IO
IO
IO
GPIO1_68
pad
D10
E10
EMU0
EMU1
EMU0
OFF
OFF
0
0
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
EMU1
0
15
0
7
0
1
2
5
7
0
1
2
3
6
7
9
0
1
2
3
4
6
7
9
0
3
7
8
9
IO
O
I
1.8 V/3.3 V VDDSHV_ Yes
MCU
1/1
1/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
MCU_OBSCLK0
EXTINTn
C19
A19
EXTINTn
1
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
I2C OD FS
LVCMOS
GPIO1_70
IO
I
pad
0
EXT_REFCLK1
EXT_REFCLK1
SYNC1_OUT
SPI2_CS3
PU/PD
PU/PD
O
IO
O
IO
O
I
1
CLKOUT0
GPIO1_69
pad
P16
GPMC0_ADVn_ALE
GPMC0_ADVn_ALE
FSI_RX5_CLK
UART5_RXD
EHRPWM_TZn_IN3
TRC_DATA15
GPIO0_32
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
0
1
0
I
I
O
IO
I
pad
0
PRG0_PWM3_TZ_IN
GPMC0_CLK
FSI_RX4_CLK
UART4_RTSn
EHRPWM3_SYNCO
GPMC0_FCLK_MUX
TRC_DATA14
GPIO0_31
R17
GPMC0_CLK
O
I
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
0
O
O
O
O
IO
O
O
I
pad
PRG0_PWM3_TZ_OUT
GPMC0_DIR
N17
GPMC0_DIR
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
EQEP0_B
0
GPIO0_40
IO
IO
IO
pad
0
EHRPWM6_B
PRG1_PWM2_B0
1
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
R18
GPMC0_OEn_REn
GPMC0_OEn_REn
0
1
2
3
6
7
9
0
1
2
3
6
7
9
0
1
3
4
6
7
8
9
0
1
2
3
6
7
O
I
OFF
7
7
7
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
FSI_RX5_D0
UART5_TXD
EHRPWM4_A
TRC_DATA16
GPIO0_33
0
0
O
IO
O
IO
IO
O
I
pad
0
PRG0_PWM3_A1
GPMC0_WEn
FSI_RX5_D1
UART5_RTSn
EHRPWM4_B
TRC_DATA17
GPIO0_34
T21
GPMC0_WEn
OFF
PU/PD
0
0
O
IO
O
IO
IO
O
O
I
pad
1
PRG0_PWM3_B1
GPMC0_WPn
FSI_TX1_CLK
EQEP0_A
N16
GPMC0_WPn
OFF
PU/PD
0
GPMC0_A22
TRC_DATA22
GPIO0_39
OZ
O
IO
IO
IO
IO
I
pad
0
EHRPWM6_A
PRG1_PWM2_A0
GPMC0_AD0
FSI_RX2_CLK
UART2_RXD
EHRPWM0_SYNCI
TRC_CLK
0
T20
GPMC0_AD0
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
0
I
1
I
0
O
IO
I
GPIO0_15
pad
BOOTMODE00
GPMC0_AD1
FSI_RX2_D0
UART2_TXD
EHRPWM0_SYNCO
TRC_CTL
Bootstrap
U21
GPMC0_AD1
0
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1
2
O
O
O
IO
O
I
3
6
GPIO0_16
7
pad
PRG0_PWM2_TZ_OUT
BOOTMODE01
9
Bootstrap
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
T18
GPMC0_AD2
GPMC0_AD2
0
1
2
3
6
7
9
IO
I
0
0
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
FSI_RX2_D1
UART2_RTSn
EHRPWM_TZn_IN0
TRC_DATA0
O
I
0
O
IO
I
GPIO0_17
pad
0
PRG0_PWM2_TZ_IN
BOOTMODE02
GPMC0_AD3
FSI_RX3_CLK
UART3_RXD
EHRPWM0_A
TRC_DATA1
Bootstrap
I
U20
U18
U19
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
0
IO
I
0
0
1
0
OFF
OFF
OFF
PU/PD
PU/PD
PU/PD
1
2
I
3
IO
O
IO
IO
I
6
GPIO0_18
7
pad
0
PRG0_PWM2_A0
BOOTMODE03
GPMC0_AD4
FSI_RX3_D0
UART3_TXD
EHRPWM0_B
TRC_DATA2
9
Bootstrap
0
IO
I
0
0
1
2
O
IO
O
IO
IO
I
3
0
6
GPIO0_82
7
pad
1
PRG0_PWM2_B0
BOOTMODE04
GPMC0_AD5
FSI_RX3_D1
UART3_RTSn
EHRPWM1_A
TRC_DATA3
9
Bootstrap
0
IO
I
0
0
1
2
O
IO
O
IO
IO
I
3
0
6
GPIO0_83
7
pad
0
PRG0_PWM2_A1
BOOTMODE05
9
Bootstrap
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
V20
GPMC0_AD6
GPMC0_AD6
0
1
2
3
6
7
9
IO
I
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
FSI_RX4_D0
UART4_RXD
EHRPWM1_B
TRC_DATA4
I
IO
O
IO
IO
I
GPIO0_21
pad
1
PRG0_PWM2_B1
BOOTMODE06
GPMC0_AD7
FSI_RX4_D1
UART4_TXD
EHRPWM_TZn_IN1
EHRPWM8_A
TRC_DATA5
Bootstrap
V21
GPMC0_AD7
0
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1
2
O
I
3
0
0
4
IO
O
IO
IO
I
6
GPIO0_22
7
pad
0
PRG1_PWM2_A2
BOOTMODE07
GPMC0_AD8
FSI_RX0_CLK
UART2_CTSn
EHRPWM2_A
TRC_DATA6
9
Bootstrap
V19
GPMC0_AD8
0
IO
I
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1
2
I
3
IO
O
IO
IO
I
6
GPIO0_23
7
pad
0
PRG0_PWM2_A2
BOOTMODE08
GPMC0_AD9
FSI_RX0_D0
UART3_CTSn
EHRPWM2_B
TRC_DATA7
9
Bootstrap
T17
GPMC0_AD9
0
IO
I
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1
2
I
3
IO
O
IO
IO
I
6
GPIO0_24
7
pad
1
PRG0_PWM2_B2
BOOTMODE09
9
Bootstrap
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
R16
GPMC0_AD10
GPMC0_AD10
0
1
2
3
4
6
7
9
IO
I
0
0
1
0
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
FSI_RX0_D1
UART4_CTSn
EHRPWM_TZn_IN2
EHRPWM8_B
TRC_DATA8
GPIO0_25
I
I
IO
O
IO
IO
I
pad
1
PRG1_PWM2_B2
BOOTMODE10
GPMC0_AD11
FSI_RX1_CLK
UART5_CTSn
EQEP1_A
Bootstrap
W20
W21
V18
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
0
IO
I
0
0
1
0
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
1
2
I
3
I
TRC_DATA9
GPIO0_26
6
O
IO
IO
I
7
pad
0
EHRPWM7_A
BOOTMODE11
GPMC0_AD12
FSI_RX1_D0
UART6_CTSn
EQEP1_B
8
Bootstrap
0
IO
I
0
0
1
0
1
2
I
3
I
TRC_DATA10
GPIO0_27
6
O
IO
IO
I
7
pad
0
EHRPWM7_B
BOOTMODE12
GPMC0_AD13
FSI_RX1_D1
EHRPWM3_A
TRC_DATA11
GPIO0_28
8
Bootstrap
0
IO
I
0
0
0
1
3
IO
O
IO
IO
I
6
7
pad
0
PRG0_PWM3_A0
BOOTMODE13
9
Bootstrap
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y21
GPMC0_AD14
GPMC0_AD14
0
1
2
3
6
7
9
IO
O
I
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
FSI_TX0_D0
UART6_RXD
EHRPWM3_B
TRC_DATA12
GPIO0_29
1
0
IO
O
IO
IO
I
pad
1
PRG0_PWM3_B0
BOOTMODE14
GPMC0_AD15
FSI_TX0_D1
Bootstrap
Y20
GPMC0_AD15
0
IO
O
O
I
0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
1
UART6_TXD
2
EHRPWM3_SYNCI
TRC_DATA13
GPIO0_30
3
0
6
O
IO
I
7
pad
BOOTMODE15
GPMC0_BE0n_CLE
FSI_TX1_D0
Bootstrap
P17
GPMC0_BE0n_CLE
0
1
2
3
5
6
7
9
0
1
3
6
7
9
0
3
6
7
8
O
O
O
I
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
UART6_RTSn
EHRPWM_TZn_IN4
EHRPWM7_A
TRC_DATA18
GPIO0_35
0
0
IO
O
IO
IO
O
O
IO
O
IO
IO
O
IO
O
IO
I
pad
0
PRG1_PWM2_A1
GPMC0_BE1n
FSI_TX0_CLK
EHRPWM5_A
TRC_DATA19
GPIO0_36
T19
GPMC0_BE1n
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
0
pad
0
PRG0_PWM3_A2
GPMC0_CSn0
EQEP0_S
R19
GPMC0_CSn0
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
0
TRC_DATA23
GPIO0_41
pad
0
EHRPWM6_SYNCI
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
R20
GPMC0_CSn1
GPMC0_CSn1
0
3
5
7
8
9
0
1
2
3
5
7
9
0
1
2
3
4
5
7
0
3
6
7
9
0
1
3
4
5
6
7
9
0
4
7
O
IO
I
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1/0
1/0
1/0
EQEP0_I
0
0
EHRPWM_TZn_IN2
GPIO0_42
IO
O
O
O
pad
EHRPWM6_SYNCO
PRG1_PWM2_TZ_OUT
GPMC0_CSn2
I2C2_SCL
P19
GPMC0_CSn2
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
IOD
IO
IO
I
1
TIMER_IO8
0
EQEP1_S
0
EHRPWM_TZn_IN4
GPIO0_43
0
IO
I
pad
0
PRG1_PWM2_TZ_IN
GPMC0_CSn3
I2C2_SDA
R21
GPMC0_CSn3
O
OFF
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
PU/PD
IOD
IO
IO
OZ
I
1
0
0
TIMER_IO9
EQEP1_I
GPMC0_A20
EHRPWM_TZn_IN5
GPIO0_44
0
IO
I
pad
1
W19
GPMC0_WAIT0
GPMC0_WAIT1
GPMC0_WAIT0
EHRPWM5_B
TRC_DATA20
GPIO0_37
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV3 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
O
0
IO
IO
I
pad
1
PRG0_PWM3_B2
GPMC0_WAIT1
FSI_TX1_D1
Y18
1
1.8 V/3.3 V VDDSHV3 Yes
O
EHRPWM_TZn_IN5
GPMC0_A21
EHRPWM7_B
TRC_DATA21
GPIO0_38
I
0
0
OZ
IO
O
IO
IO
IOD
I
pad
1
PRG1_PWM2_B1
I2C0_SCL
A18
I2C0_SCL
1
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
I2C OD FS
UART6_CTSn
GPIO1_64
1
IO
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
B18
I2C0_SDA
I2C0_SDA
0
4
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
6
7
8
9
0
1
2
3
6
7
8
9
IOD
1
OFF
7
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
I2C OD FS
1/0
1/0
1/0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
UART6_RTSn
GPIO1_65
O
IO
IOD
I
pad
1
C18
B19
B17
I2C1_SCL
I2C1_SDA
MCAN0_RX
I2C1_SCL
OFF
OFF
OFF
LVCMOS
PU/PD
CPTS0_HW1TSPUSH
TIMER_IO0
SPI2_CS1
0
IO
IO
IO
IOD
I
0
1
GPIO1_66
pad
1
I2C1_SDA
7
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
CPTS0_HW2TSPUSH
TIMER_IO1
SPI2_CS2
0
IO
IO
IO
I
0
1
GPIO1_67
pad
1
MCAN0_RX
UART4_TXD
TIMER_IO3
SYNC3_OUT
SPI4_CS2
1.8 V/3.3 V VDDSHV0 Yes
O
IO
O
0
IO
IO
IO
I
1
GPIO1_61
pad
0
EQEP2_S
UART0_RIn
MCAN0_TX
UART4_RXD
TIMER_IO2
SYNC2_OUT
SPI4_CS1
1
A17
MCAN0_TX
O
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
I
1
0
IO
O
IO
IO
IO
O
1
GPIO1_60
pad
0
EQEP2_I
UART0_DTRn
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
D17
MCAN1_RX
MCAN1_RX
0
1
2
3
4
5
6
7
8
9
15
0
1
2
3
4
5
6
7
8
9
0
7
0
7
0
7
0
7
I
1
1
0
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1/0
1/0
1/0
1/0
0/1
0/1
0/1
0/1
I2C3_SDA
IOD
IO
O
ECAP2_IN_APWM_OUT
OBSCLK0
TIMER_IO5
IO
O
0
UART5_TXD
EHRPWM_SOCB
GPIO1_63
O
IO
I
pad
0
EQEP2_B
UART0_DSRn
OBSCLK0
I
1
O
C17
MCAN1_TX
MCAN1_TX
O
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
I2C3_SCL
IOD
IO
O
1
0
ECAP1_IN_APWM_OUT
SYSCLKOUT0
TIMER_IO4
IO
I
0
1
UART5_RXD
EHRPWM_SOCA
GPIO1_62
O
IO
I
pad
0
EQEP2_A
UART0_DCDn
MCU_I2C0_SCL
MCU_GPIO0_18
MCU_I2C0_SDA
MCU_GPIO0_19
MCU_I2C1_SCL
MCU_GPIO0_20
MCU_I2C1_SDA
MCU_GPIO0_21
MCU_OSC0_XI
I
1
E9
MCU_I2C0_SCL
MCU_I2C0_SDA
MCU_I2C1_SCL
MCU_I2C1_SDA
IOD
IO
IOD
IO
IOD
IO
IOD
IO
I
1
OFF
OFF
OFF
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
I2C OD FS
I2C OD FS
LVCMOS
LVCMOS
pad
1
A10
A11
B10
1.8 V/3.3 V VDDSHV_ Yes
MCU
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
PU/PD
PU/PD
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
pad
C21
B20
B21
B13
MCU_OSC0_XI
MCU_OSC0_XO
MCU_PORz
1.8 V
1.8 V
1.8 V
VDDS_OS Yes
C
HFOSC
MCU_OSC0_XO
MCU_PORz
O
I
VDDS_OS Yes
C
HFOSC
0
0
0
VDDS_OS Yes
C
FS RESET
LVCMOS
MCU_RESETSTATz
MCU_RESETSTATz
MCU_GPIO0_22
MCU_RESETz
0
7
0
O
IO
I
PD
1.8 V/3.3 V VDDSHV_ Yes
MCU
PU/PD
PU/PD
0/0
0/0
1/1
pad
B12
MCU_RESETz
OFF
0
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
A20
E6
MCU_SAFETY_ERRORn
MCU_SPI0_CLK
MCU_SAFETY_ERRORn
0
IO
OFF
0
1.8 V
VDDS_OS Yes
C
LVCMOS
LVCMOS
PU/PD
1/0
MCU_SPI0_CLK
MCU_GPIO0_11
MCU_SPI1_CLK
MCU_GPIO0_7
MCU_SPI0_CS0
MCU_GPIO0_13
MCU_SPI0_CS1
MCU_OBSCLK0
MCU_SYSCLKOUT0
MCU_GPIO0_12
MCU_SPI0_D0
0
7
0
7
0
7
0
1
2
7
0
7
0
7
0
7
0
1
7
0
7
0
7
0
1
2
7
0
1
2
7
0
7
0
7
IO
IO
IO
IO
IO
IO
IO
O
0
OFF
OFF
OFF
OFF
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
PU/PD
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
pad
0
D7
D6
C6
MCU_SPI1_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
7
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
LVCMOS
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
O
IO
IO
IO
IO
IO
IO
IO
IO
I
pad
0
E7
B6
A7
B7
MCU_SPI0_D0
MCU_SPI0_D1
MCU_SPI1_CS0
MCU_SPI1_CS1
OFF
OFF
OFF
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
MCU_GPIO0_10
MCU_SPI0_D1
pad
0
1.8 V/3.3 V VDDSHV_ Yes
MCU
MCU_GPIO0_4
MCU_SPI1_CS0
MCU_GPIO0_5
MCU_SPI1_CS1
MCU_EXT_REFCLK0
MCU_GPIO0_6
MCU_SPI1_D0
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
pad
1
1.8 V/3.3 V VDDSHV_ Yes
MCU
0
IO
IO
IO
IO
IO
I
pad
0
C7
C8
D8
MCU_SPI1_D0
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
MCU_GPIO0_8
MCU_SPI1_D1
pad
0
MCU_SPI1_D1
1.8 V/3.3 V VDDSHV_ Yes
MCU
MCU_GPIO0_9
MCU_UART0_CTSn
MCU_TIMER_IO0
MCU_SPI0_CS2
MCU_GPIO0_1
MCU_UART0_RTSn
MCU_TIMER_IO1
MCU_SPI1_CS2
MCU_GPIO0_0
MCU_UART0_RXD
MCU_GPIO0_3
MCU_UART0_TXD
MCU_GPIO0_2
pad
1
MCU_UART0_CTSn
1.8 V/3.3 V VDDSHV_ Yes
MCU
IO
IO
IO
O
0
1
pad
E8
MCU_UART0_RTSn
OFF
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
PU/PD
IO
IO
IO
I
0
1
pad
1
A9
A8
MCU_UART0_RXD
MCU_UART0_TXD
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
O
pad
1.8 V/3.3 V VDDSHV_ Yes
MCU
IO
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
B8
MCU_UART1_CTSn
MCU_UART1_CTSn
0
1
2
7
0
1
2
7
0
7
0
7
I
1
0
1
OFF
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
MCU_TIMER_IO2
MCU_SPI0_CS3
MCU_GPIO0_16
MCU_UART1_RTSn
MCU_TIMER_IO3
MCU_SPI1_CS3
MCU_GPIO0_17
MCU_UART1_RXD
MCU_GPIO0_14
MCU_UART1_TXD
MCU_GPIO0_15
MMC0_CALPAD
IO
IO
IO
O
pad
B9
MCU_UART1_RTSn
OFF
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
PU/PD
IO
IO
IO
I
0
1
pad
1
C9
MCU_UART1_RXD
MCU_UART1_TXD
MMC0_CALPAD
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
PU/PD
PU/PD
IO
O
pad
D9
1.8 V/3.3 V VDDSHV_ Yes
MCU
IO
A
pad
F18
1.8 V
1.8 V
1.8 V
1.8 V
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
G18
J21
G19
L20
MMC0_CLK
MMC0_CMD
MMC0_DS
MMC0_CLK
MMC0_CMD
MMC0_DS
IO
IO
IO
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
1
1
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
MMC1_CLK
MMC1_CLK
UART2_CTSn
TIMER_IO4
UART4_RXD
GPIO1_75
0
1
2
3
7
IO
I
OFF
7
1.8 V/3.3 V VDDSHV5 Yes
SDIO
PU/PD
0/1
0/1
0/1
0/1
0/1
1
IO
I
0
1
IO
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
J19
MMC1_CMD
MMC1_CMD
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
IO
O
IO
O
IO
I
1
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV5 Yes
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
SDIO
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
UART2_RTSn
TIMER_IO5
UART4_TXD
GPIO1_76
pad
1
D19
C20
MMC1_SDCD
MMC1_SDWP
MMC1_SDCD
UART3_CTSn
TIMER_IO6
UART5_RXD
GPIO1_77
OFF
OFF
LVCMOS
LVCMOS
PU/PD
PU/PD
I
1
IO
I
0
1
IO
I
pad
1
MMC1_SDWP
UART3_RTSn
TIMER_IO7
UART5_TXD
GPIO1_78
O
IO
O
IO
IO
0
pad
1
K20
J20
J18
J17
H17
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT0
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
IO
IO
IO
IO
1
1
1
1
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
H19
MMC0_DAT5
MMC0_DAT5
IO
IO
IO
1
1
1
1.8 V
1.8 V
1.8 V
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
eMMCPHY PU/PD
eMMCPHY PU/PD
eMMCPHY PU/PD
H18
G17
K21
MMC0_DAT6
MMC0_DAT7
MMC1_DAT0
MMC0_DAT6
MMC0_DAT7
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
VDDS_MM
C0,
VDD_MMC
0,
VDD_DLL_
MMC0
MMC1_DAT0
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
7
0
7
IO
I
1
0
0
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV5 Yes
1.8 V/3.3 V VDDSHV5 Yes
1.8 V/3.3 V VDDSHV5 Yes
1.8 V/3.3 V VDDSHV5 Yes
SDIO
SDIO
SDIO
SDIO
PU/PD
PU/PD
PU/PD
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
CP_GEMAC_CPTS0_HW2TSPUSH
TIMER_IO3
IO
O
IO
IO
I
UART3_TXD
GPIO1_74
pad
1
L21
K19
K18
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
MMC1_DAT1
OFF
OFF
OFF
CP_GEMAC_CPTS0_HW1TSPUSH
TIMER_IO2
0
IO
I
0
UART3_RXD
1
GPIO1_73
IO
IO
O
IO
O
IO
IO
O
IO
I
pad
1
MMC1_DAT2
CP_GEMAC_CPTS0_TS_SYNC
TIMER_IO1
0
UART2_TXD
GPIO1_72
pad
1
MMC1_DAT3
CP_GEMAC_CPTS0_TS_COMP
TIMER_IO0
0
UART2_RXD
1
GPIO1_71
IO
O
IO
I
pad
N20
N19
OSPI0_CLK
OSPI0_DQS
OSPI0_CLK
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
GPIO0_0
pad
0
OSPI0_DQS
GPIO0_2
IO
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
N21
L19
L18
K17
OSPI0_LBCLKO
OSPI0_LBCLKO
0
7
0
7
0
7
0
2
7
0
1
2
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
0
7
9
0
7
9
IO
IO
O
0
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
1/1
1/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/0
0/1
0/1
0/1
0/1
0/1
0/1
GPIO0_1
pad
pad
pad
OSPI0_CSn0
OSPI0_CSn1
OSPI0_CSn2
OSPI0_CSn0
GPIO0_11
OFF
OFF
OFF
PU/PD
PU/PD
PU/PD
IO
O
OSPI0_CSn1
GPIO0_12
IO
O
OSPI0_CSn2
OSPI0_RESET_OUT1
GPIO0_13
O
IO
O
pad
L17
OSPI0_CSn3
OSPI0_CSn3
OSPI0_RESET_OUT0
OSPI0_ECC_FAIL
GPIO0_14
OFF
7
1.8 V/3.3 V VDDSHV4 Yes
LVCMOS
PU/PD
O
I
1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
pad
0
M19
M18
M20
M21
P21
P20
N18
M17
OSPI0_D0
OSPI0_D1
OSPI0_D2
OSPI0_D3
OSPI0_D4
OSPI0_D5
OSPI0_D6
OSPI0_D7
OSPI0_D0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
7
7
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
1.8 V/3.3 V VDDSHV4 Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
GPIO0_3
pad
0
OSPI0_D1
GPIO0_4
pad
0
OSPI0_D2
GPIO0_5
pad
0
OSPI0_D3
GPIO0_6
pad
0
OSPI0_D4
GPIO0_7
pad
0
OSPI0_D5
GPIO0_8
pad
0
OSPI0_D6
GPIO0_9
pad
0
OSPI0_D7
GPIO0_10
pad
E17
P3
PORz_OUT
PORz_OUT
PRG0_MDIO0_MDC
GPIO1_41
PD
0
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
PRG0_MDIO0_MDC
O
OFF
IO
pad
GPMC0_A13
PRG0_MDIO0_MDIO
GPIO1_40
OZ
IO
P2
PRG0_MDIO0_MDIO
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
IO
pad
GPMC0_A12
OZ
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y1
PRG0_PRU0_GPO0
PRG0_PRU0_GPO0
0
IO
I
0
0
0
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU0_GPI0
PRG0_RGMII1_RD0
PRG0_PWM3_A0
GPIO1_0
1
2
I
3
IO
IO
I
7
pad
1
UART2_CTSn
10
0
R4
PRG0_PRU0_GPO1
PRG0_PRU0_GPO1
PRG0_PRU0_GPI1
PRG0_RGMII1_RD1
PRG0_PWM3_B0
GPIO1_1
IO
I
0
OFF
PU/PD
1
0
2
I
0
3
IO
IO
O
IO
I
1
7
pad
UART2_TXD
10
0
U2
PRG0_PRU0_GPO2
PRG0_PRU0_GPO2
PRG0_PRU0_GPI2
PRG0_RGMII1_RD2
PRG0_PWM2_A0
GPIO1_2
0
OFF
PU/PD
1
0
2
I
0
3
IO
IO
0
7
pad
GPMC0_A0
9
OZ
O
IO
I
UART2_RTSn
10
0
V2
PRG0_PRU0_GPO3
PRG0_PRU0_GPO3
PRG0_PRU0_GPI3
PRG0_RGMII1_RD3
PRG0_PWM3_A2
GPIO1_3
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
0
3
IO
IO
I
0
7
pad
1
UART3_CTSn
10
0
AA2
PRG0_PRU0_GPO4
PRG0_PRU0_GPO4
PRG0_PRU0_GPI4
PRG0_RGMII1_RX_CTL
PRG0_PWM2_B0
GPIO1_4
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
0
3
IO
IO
OZ
O
IO
I
1
7
pad
GPMC0_A1
9
UART3_TXD
10
0
R3
PRG0_PRU0_GPO5
PRG0_PRU0_GPO5
PRG0_PRU0_GPI5
PRG0_PWM3_B2
GPIO1_5
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
3
IO
IO
O
1
7
pad
UART3_RTSn
10
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
T3
PRG0_PRU0_GPO6
PRG0_PRU0_GPO6
0
IO
I
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU0_GPI6
PRG0_RGMII1_RXC
PRG0_PWM3_A1
GPIO1_6
1
2
I
3
IO
IO
I
7
pad
1
UART4_CTSn
10
0
T1
PRG0_PRU0_GPO7
PRG0_PRU0_GPO7
PRG0_PRU0_GPI7
PRG0_IEP0_EDC_LATCH_IN1
PRG0_PWM3_B1
CPTS0_HW2TSPUSH
CP_GEMAC_CPTS0_HW2TSPUSH
TIMER_IO6
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
0
3
IO
I
1
4
0
5
I
0
6
IO
IO
O
IO
I
0
GPIO1_7
7
pad
UART4_TXD
10
0
T2
PRG0_PRU0_GPO8
PRG0_PRU0_GPO8
PRG0_PRU0_GPI8
PRG0_PWM2_A1
GPIO1_8
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
3
IO
IO
0
7
pad
GPMC0_A2
9
OZ
UART4_RTSn
10
0
O
IO
I
W6
PRG0_PRU0_GPO9
PRG0_PRU0_GPO9
PRG0_PRU0_GPI9
PRG0_UART0_CTSn
PRG0_PWM3_TZ_IN
RGMII1_RX_CTL
RMII1_RX_ER
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
1
3
I
0
4
I
0
5
I
0
PRG0_IEP0_EDIO_DATA_IN_OUT28
GPIO1_9
6
IO
IO
I
0
7
pad
1
UART2_RXD
10
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
AA5
PRG0_PRU0_GPO10
PRG0_PRU0_GPO10
0
1
2
3
4
5
6
7
10
0
1
2
3
7
10
0
1
2
3
7
9
0
1
2
3
6
7
9
0
1
2
3
6
7
9
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU0_GPI10
PRG0_UART0_RTSn
PRG0_PWM2_B1
RGMII1_RXC
O
IO
I
1
0
0
0
RMII_REF_CLK
PRG0_IEP0_EDIO_DATA_IN_OUT29
GPIO1_10
I
IO
IO
I
pad
1
UART3_RXD
Y3
PRG0_PRU0_GPO11
PRG0_PRU0_GPO12
PRG0_PRU0_GPO13
PRG0_PRU0_GPO11
PRG0_PRU0_GPI11
PRG0_RGMII1_TD0
PRG0_PWM3_TZ_OUT
GPIO1_11
IO
I
0
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
0
O
O
IO
I
pad
1
UART4_RXD
AA3
PRG0_PRU0_GPO12
PRG0_PRU0_GPI12
PRG0_RGMII1_TD1
PRG0_PWM0_A0
GPIO1_12
IO
I
0
0
O
IO
IO
0
pad
GPMC0_A14
OZ
IO
I
R6
PRG0_PRU0_GPO13
PRG0_PRU0_GPI13
PRG0_RGMII1_TD2
PRG0_PWM0_B0
SPI3_D0
0
0
O
IO
IO
IO
OZ
IO
I
1
0
GPIO1_13
pad
GPMC0_A15
V4
PRG0_PRU0_GPO14
PRG0_PRU0_GPO14
PRG0_PRU0_GPI14
PRG0_RGMII1_TD3
PRG0_PWM0_A1
SPI3_D1
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
O
IO
IO
IO
OZ
0
0
GPIO1_14
pad
GPMC0_A3
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
T5
PRG0_PRU0_GPO15
PRG0_PRU0_GPO15
0
1
2
3
6
7
9
0
1
2
3
6
7
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
IO
I
0
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU0_GPI15
PRG0_RGMII1_TX_CTL
PRG0_PWM0_B1
SPI3_CS1
O
IO
IO
IO
1
1
GPIO1_15
pad
GPMC0_A16
OZ
IO
I
U4
PRG0_PRU0_GPO16
PRG0_PRU0_GPO16
PRG0_PRU0_GPI16
PRG0_RGMII1_TXC
PRG0_PWM0_A2
SPI3_CLK
0
OFF
PU/PD
0
IO
IO
IO
IO
OZ
IO
I
0
0
0
GPIO1_16
pad
GPMC0_A4
U1
PRG0_PRU0_GPO17
PRG0_PRU0_GPO17
PRG0_PRU0_GPI17
PRG0_IEP0_EDC_SYNC_OUT1
PRG0_PWM0_B2
CPTS0_TS_SYNC
CP_GEMAC_CPTS0_TS_SYNC
SPI3_CS0
0
0
OFF
PU/PD
O
IO
O
O
IO
IO
IO
OZ
IO
I
1
1
GPIO1_17
pad
0
TIMER_IO11
GPMC0_A17
V1
PRG0_PRU0_GPO18
PRG0_PRU0_GPO18
PRG0_PRU0_GPI18
PRG0_IEP0_EDC_LATCH_IN0
PRG0_PWM0_TZ_IN
CPTS0_HW1TSPUSH
CP_GEMAC_CPTS0_HW1TSPUSH
EHRPWM8_A
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0
I
0
I
0
I
0
I
0
IO
IO
I
0
GPIO1_18
pad
1
UART4_CTSn
GPMC0_A5
OZ
I
UART2_RXD
1
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
W1
PRG0_PRU0_GPO19
PRG0_PRU0_GPO19
0
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU0_GPI19
PRG0_IEP0_EDC_SYNC_OUT0
PRG0_PWM0_TZ_OUT
CPTS0_TS_COMP
CP_GEMAC_CPTS0_TS_COMP
EHRPWM8_B
1
2
O
O
O
O
IO
IO
O
3
4
5
6
0
GPIO1_19
7
pad
UART4_RTSn
8
GPMC0_A6
9
OZ
I
UART3_RXD
10
0
1
Y2
W2
V3
PRG0_PRU1_GPO0
PRG0_PRU1_GPO1
PRG0_PRU1_GPO2
PRG0_PRU1_GPO0
PRG0_PRU1_GPI0
PRG0_RGMII2_RD0
GPIO1_20
IO
I
0
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
1
0
2
I
0
7
IO
I
pad
0
EQEP0_A
8
UART5_CTSn
10
0
I
1
PRG0_PRU1_GPO1
PRG0_PRU1_GPI1
PRG0_RGMII2_RD1
GPIO1_21
IO
I
0
1
0
2
I
0
7
IO
I
pad
0
EQEP0_B
8
UART5_TXD
10
0
O
IO
I
PRG0_PRU1_GPO2
PRG0_PRU1_GPI2
PRG0_RGMII2_RD2
PRG0_PWM2_A2
GPIO1_22
0
1
0
2
I
0
3
IO
IO
IO
O
IO
I
0
7
pad
0
EQEP0_S
8
UART5_RTSn
10
0
T4
PRG0_PRU1_GPO3
PRG0_PRU1_GPO3
PRG0_PRU1_GPI3
PRG0_RGMII2_RD3
GPIO1_23
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
0
7
IO
I
pad
0
EQEP1_A
8
GPMC0_A18
9
OZ
I
UART6_CTSn
10
1
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
W3
PRG0_PRU1_GPO4
PRG0_PRU1_GPO4
0
IO
I
0
0
0
1
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU1_GPI4
PRG0_RGMII2_RX_CTL
PRG0_PWM2_B2
GPIO1_24
1
2
I
3
IO
IO
I
7
pad
0
EQEP1_B
8
UART6_TXD
10
0
O
IO
I
P4
R5
PRG0_PRU1_GPO5
PRG0_PRU1_GPO6
PRG0_PRU1_GPO5
PRG0_PRU1_GPI5
GPIO1_25
0
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
1
0
7
IO
IO
O
IO
I
pad
0
EQEP1_S
8
UART6_RTSn
10
0
PRG0_PRU1_GPO6
PRG0_PRU1_GPI6
PRG0_RGMII2_RXC
GPIO1_26
0
1.8 V/3.3 V VDDSHV1 Yes
1
0
2
I
0
7
IO
I
pad
0
EQEP2_A
8
GPMC0_A19
9
OZ
I
UART4_CTSn
10
0
1
W5
PRG0_PRU1_GPO7
PRG0_PRU1_GPO7
PRG0_PRU1_GPI7
PRG0_IEP1_EDC_LATCH_IN1
RGMII1_RD0
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
I
0
4
I
0
RMII1_RXD0
5
I
0
GPIO1_27
7
IO
I
pad
0
EQEP2_B
8
UART4_TXD
10
0
O
IO
I
R1
PRG0_PRU1_GPO8
PRG0_PRU1_GPO8
PRG0_PRU1_GPI8
PRG0_PWM2_TZ_OUT
GPIO1_28
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
3
O
IO
IO
O
7
pad
0
EQEP2_S
8
UART4_RTSn
10
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y5
PRG0_PRU1_GPO9
PRG0_PRU1_GPO9
0
IO
I
0
0
1
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU1_GPI9
PRG0_UART0_RXD
RGMII1_RD1
1
2
I
4
I
RMII1_RXD1
5
I
PRG0_IEP0_EDIO_DATA_IN_OUT30
GPIO1_29
6
IO
IO
IO
I
7
pad
0
EQEP0_I
8
UART5_RXD
10
0
1
V6
PRG0_PRU1_GPO10
PRG0_PRU1_GPO10
PRG0_PRU1_GPI10
PRG0_UART0_TXD
PRG0_PWM2_TZ_IN
RGMII1_RD2
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
O
I
3
0
0
4
I
RMII1_TXD0
5
O
IO
IO
IO
I
PRG0_IEP0_EDIO_DATA_IN_OUT31
GPIO1_30
6
0
7
pad
0
EQEP1_I
8
UART6_RXD
10
0
1
W4
PRG0_PRU1_GPO11
PRG0_PRU1_GPO11
PRG0_PRU1_GPI11
PRG0_RGMII2_TD0
GPIO1_31
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
O
IO
IO
I
7
pad
0
EQEP2_I
8
UART4_RXD
10
0
1
Y4
PRG0_PRU1_GPO12
PRG0_PRU1_GPO12
PRG0_PRU1_GPI12
PRG0_RGMII2_TD1
PRG0_PWM1_A0
GPIO1_32
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
O
IO
IO
I
3
0
7
pad
0
EQEP2_B
8
GPMC0_A7
9
OZ
O
UART4_TXD
10
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
T6
PRG0_PRU1_GPO13
PRG0_PRU1_GPO13
0
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU1_GPI13
PRG0_RGMII2_TD2
PRG0_PWM1_B0
GPIO1_33
1
2
O
3
IO
IO
IO
1
7
pad
0
EQEP0_I
8
GPMC0_A8
9
OZ
I
UART5_RXD
10
0
1
0
0
U6
PRG0_PRU1_GPO14
PRG0_PRU1_GPO14
PRG0_PRU1_GPI14
PRG0_RGMII2_TD3
PRG0_PWM1_A1
GPIO1_34
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
2
O
3
IO
IO
IO
OZ
I
0
7
pad
0
EQEP1_I
8
GPMC0_A9
9
UART6_RXD
10
0
1
0
0
U5
PRG0_PRU1_GPO15
PRG0_PRU1_GPO15
PRG0_PRU1_GPI15
PRG0_RGMII2_TX_CTL
PRG0_PWM1_B1
GPIO1_35
IO
I
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
2
O
3
IO
IO
OZ
IO
IO
I
1
7
pad
GPMC0_A10
9
PRG0_ECAP0_IN_APWM_OUT
PRG0_PRU1_GPO16
PRG0_PRU1_GPI16
PRG0_RGMII2_TXC
PRG0_PWM1_A2
GPIO1_36
10
0
0
AA4
PRG0_PRU1_GPO16
0
OFF
7
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
PU/PD
1
0
2
IO
IO
IO
OZ
O
0
3
0
7
pad
GPMC0_A11
9
PRG0_ECAP0_SYNC_OUT
10
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
V5
PRG0_PRU1_GPO17
PRG0_PRU1_GPO17
0
1
2
3
4
5
7
8
10
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0
4
7
0
4
7
IO
I
0
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
1.8 V/3.3 V VDDSHV1 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG0_PRU1_GPI17
PRG0_IEP1_EDC_SYNC_OUT1
PRG0_PWM1_B2
RGMII1_RD3
O
IO
I
1
0
RMII1_TXD1
O
IO
O
I
GPIO1_37
pad
PRG0_ECAP0_SYNC_OUT
PRG0_ECAP0_SYNC_IN
PRG0_PRU1_GPO18
PRG0_PRU1_GPI18
PRG0_IEP1_EDC_LATCH_IN0
PRG0_PWM1_TZ_IN
MDIO0_MDIO
0
0
0
0
0
0
P5
PRG0_PRU1_GPO18
IO
I
OFF
PU/PD
I
I
IO
O
IO
IO
I
RMII1_TX_EN
EHRPWM7_A
0
GPIO1_38
pad
0
PRG0_ECAP0_SYNC_IN
PRG0_PRU1_GPO19
PRG0_PRU1_GPI19
PRG0_IEP1_EDC_SYNC_OUT0
PRG0_PWM1_TZ_OUT
MDIO0_MDC
R2
PRG0_PRU1_GPO19
IO
I
0
OFF
PU/PD
0
O
O
O
I
RMII1_CRS_DV
0
EHRPWM7_B
IO
IO
IO
O
O
IO
IO
IO
IO
0
GPIO1_39
pad
0
PRG0_ECAP0_IN_APWM_OUT
PRG1_MDIO0_MDC
MDIO0_MDC
Y6
PRG1_MDIO0_MDC
PRG1_MDIO0_MDIO
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
GPIO0_86
pad
0
AA6
PRG1_MDIO0_MDIO
MDIO0_MDIO
0
GPIO0_85
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y7
PRG1_PRU0_GPO0
PRG1_PRU0_GPO0
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
3
4
7
8
IO
I
0
0
0
0
OFF
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU0_GPI0
PRG1_RGMII1_RD0
PRG1_PWM3_A0
GPIO0_45
I
IO
IO
IO
IO
I
pad
0
GPMC0_AD16
U8
W8
V8
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO1
PRG1_PRU0_GPI1
PRG1_RGMII1_RD1
PRG1_PWM3_B0
GPIO0_46
0
OFF
OFF
OFF
OFF
OFF
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
0
I
0
IO
IO
IO
IO
I
1
pad
0
GPMC0_AD17
PRG1_PRU0_GPO2
PRG1_PRU0_GPI2
PRG1_RGMII1_RD2
PRG1_PWM2_A0
GPIO0_47
0
0
I
0
IO
IO
IO
IO
I
0
pad
0
GPMC0_AD18
PRG1_PRU0_GPO3
PRG1_PRU0_GPI3
PRG1_RGMII1_RD3
PRG1_PWM3_A2
GPIO0_48
0
0
I
0
IO
IO
IO
IO
I
0
pad
0
GPMC0_AD19
Y8
PRG1_PRU0_GPO4
PRG1_PRU0_GPI4
PRG1_RGMII1_RX_CTL
PRG1_PWM2_B0
GPIO0_49
0
0
I
0
IO
IO
IO
IO
I
1
pad
0
GPMC0_AD20
V13
PRG1_PRU0_GPO5
PRG1_PRU0_GPI5
PRG1_PWM3_B2
RGMII1_RX_CTL
GPIO0_50
0
0
IO
I
1
0
IO
IO
pad
0
GPMC0_AD21
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
AA7
PRG1_PRU0_GPO6
PRG1_PRU0_GPO6
0
1
2
3
7
8
0
1
2
3
4
5
6
7
8
0
1
3
4
7
8
0
1
2
3
4
5
6
7
8
IO
I
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU0_GPI6
PRG1_RGMII1_RXC
PRG1_PWM3_A1
GPIO0_51
I
IO
IO
IO
IO
I
pad
0
GPMC0_AD22
U13
PRG1_PRU0_GPO7
PRG1_PRU0_GPO7
PRG1_PRU0_GPI7
PRG1_IEP0_EDC_LATCH_IN1
PRG1_PWM3_B1
CPTS0_HW2TSPUSH
CLKOUT0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
0
IO
I
1
0
O
IO
IO
IO
IO
I
TIMER_IO10
0
GPIO0_52
pad
0
GPMC0_AD23
W13
PRG1_PRU0_GPO8
PRG1_PRU0_GPO8
PRG1_PRU0_GPI8
PRG1_PWM2_A1
RGMII1_RXC
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
IO
I
0
0
GPIO0_53
IO
IO
IO
I
pad
0
GPMC0_AD24
U15
PRG1_PRU0_GPO9
PRG1_PRU0_GPO9
PRG1_PRU0_GPI9
PRG1_UART0_CTSn
PRG1_PWM3_TZ_IN
RGMII1_TX_CTL
RMII1_RX_ER
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
1
I
0
O
I
0
PRG1_IEP0_EDIO_DATA_IN_OUT28
GPIO0_54
IO
IO
IO
0
pad
0
GPMC0_AD25
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
U14
PRG1_PRU0_GPO10
PRG1_PRU0_GPO10
0
1
2
3
4
5
6
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
7
8
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU0_GPI10
PRG1_UART0_RTSn
PRG1_PWM2_B1
RGMII1_TXC
O
IO
IO
I
1
0
0
0
RMII_REF_CLK
PRG1_IEP0_EDIO_DATA_IN_OUT29
GPIO0_55
IO
IO
IO
IO
I
pad
0
GPMC0_AD26
AA8
PRG1_PRU0_GPO11
PRG1_PRU0_GPO12
PRG1_PRU0_GPO13
PRG1_PRU0_GPO14
PRG1_PRU0_GPO11
PRG1_PRU0_GPI11
PRG1_RGMII1_TD0
PRG1_PWM3_TZ_OUT
GPIO0_56
0
OFF
OFF
OFF
OFF
7
7
7
7
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
0
O
O
IO
IO
IO
I
pad
0
GPMC0_AD27
U9
PRG1_PRU0_GPO12
PRG1_PRU0_GPI12
PRG1_RGMII1_TD1
PRG1_PWM0_A0
GPIO0_57
0
0
O
IO
IO
IO
IO
I
0
pad
0
GPMC0_AD28
W9
PRG1_PRU0_GPO13
PRG1_PRU0_GPI13
PRG1_RGMII1_TD2
PRG1_PWM0_B0
GPIO0_58
0
0
O
IO
IO
IO
IO
I
1
pad
0
GPMC0_AD29
AA9
PRG1_PRU0_GPO14
PRG1_PRU0_GPI14
PRG1_RGMII1_TD3
PRG1_PWM0_A1
GPIO0_59
0
0
O
IO
IO
IO
0
pad
0
GPMC0_AD30
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y9
PRG1_PRU0_GPO15
PRG1_PRU0_GPO15
0
1
2
3
7
8
0
1
2
3
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
0
1
2
3
4
6
7
8
IO
I
0
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU0_GPI15
PRG1_RGMII1_TX_CTL
PRG1_PWM0_B1
GPIO0_60
O
IO
IO
IO
IO
I
1
pad
0
GPMC0_AD31
V9
PRG1_PRU0_GPO16
PRG1_PRU0_GPO16
PRG1_PRU0_GPI16
PRG1_RGMII1_TXC
PRG1_PWM0_A2
GPIO0_61
0
OFF
PU/PD
0
IO
IO
IO
O
0
0
pad
GPMC0_BE2n
U7
PRG1_PRU0_GPO17
PRG1_PRU0_GPO17
PRG1_PRU0_GPI17
PRG1_IEP0_EDC_SYNC_OUT1
PRG1_PWM0_B2
CPTS0_TS_SYNC
TIMER_IO7
IO
I
0
0
OFF
PU/PD
O
IO
O
1
IO
IO
0
GPIO0_62
pad
GPMC0_A0
OZ
IO
I
V7
PRG1_PRU0_GPO18
PRG1_PRU0_GPO18
PRG1_PRU0_GPI18
PRG1_IEP0_EDC_LATCH_IN0
PRG1_PWM0_TZ_IN
CPTS0_HW1TSPUSH
TIMER_IO8
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
0
I
0
I
0
IO
IO
OZ
IO
I
0
GPIO0_63
pad
GPMC0_A1
W7
PRG1_PRU0_GPO19
PRG1_PRU0_GPO19
PRG1_PRU0_GPI19
PRG1_IEP0_EDC_SYNC_OUT0
PRG1_PWM0_TZ_OUT
CPTS0_TS_COMP
TIMER_IO9
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
O
O
IO
IO
OZ
0
GPIO0_64
pad
GPMC0_A2
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
W11
PRG1_PRU1_GPO0
PRG1_PRU1_GPO0
0
1
2
4
5
7
8
0
1
2
4
5
7
8
0
1
2
3
4
7
8
0
1
2
4
7
8
0
1
2
3
4
5
7
8
IO
0
0
0
0
0
OFF
7
7
7
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU1_GPI0
PRG1_RGMII2_RD0
RGMII2_RD0
I
I
I
RMII2_RXD0
I
GPIO0_65
IO
pad
GPMC0_A3
OZ
IO
I
V11
PRG1_PRU1_GPO1
PRG1_PRU1_GPO1
PRG1_PRU1_GPI1
PRG1_RGMII2_RD1
RGMII2_RD1
0
OFF
PU/PD
0
I
0
I
0
RMII2_RXD1
I
0
GPIO0_66
IO
OZ
IO
I
pad
GPMC0_A4
AA12
PRG1_PRU1_GPO2
PRG1_PRU1_GPO2
PRG1_PRU1_GPI2
PRG1_RGMII2_RD2
PRG1_PWM2_A2
RGMII2_RD2
0
OFF
PU/PD
0
I
0
IO
I
0
0
GPIO0_67
IO
OZ
IO
I
pad
GPMC0_A5
Y12
PRG1_PRU1_GPO3
PRG1_PRU1_GPO3
PRG1_PRU1_GPI3
PRG1_RGMII2_RD3
RGMII2_RD3
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
0
I
0
GPIO0_68
IO
OZ
IO
I
pad
GPMC0_A6
W12
PRG1_PRU1_GPO4
PRG1_PRU1_GPO4
PRG1_PRU1_GPI4
PRG1_RGMII2_RX_CTL
PRG1_PWM2_B2
RGMII2_RX_CTL
RMII2_RX_ER
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
0
IO
I
1
0
I
0
GPIO0_69
IO
OZ
pad
GPMC0_A7
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
AA13
PRG1_PRU1_GPO5
PRG1_PRU1_GPO5
0
1
4
7
8
0
1
2
4
7
8
0
1
2
4
5
6
7
8
0
1
3
4
7
8
0
1
2
4
5
6
7
8
IO
I
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU1_GPI5
RGMII1_RD0
I
GPIO0_70
IO
pad
GPMC0_A8
OZ
IO
I
U11
PRG1_PRU1_GPO6
PRG1_PRU1_GPO6
PRG1_PRU1_GPI6
PRG1_RGMII2_RXC
RGMII2_RXC
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
I
0
I
0
GPIO0_71
IO
OZ
IO
I
pad
GPMC0_A9
V15
PRG1_PRU1_GPO7
PRG1_PRU1_GPO7
PRG1_PRU1_GPI7
PRG1_IEP1_EDC_LATCH_IN1
RGMII1_TD0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
I
O
I
RMII1_RXD0
0
SPI3_CS3
IO
IO
OZ
IO
I
1
GPIO0_72
pad
GPMC0_A10
U12
PRG1_PRU1_GPO8
PRG1_PRU1_GPO8
PRG1_PRU1_GPI8
PRG1_PWM2_TZ_OUT
RGMII1_RD1
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
I
0
GPIO0_73
IO
OZ
IO
I
pad
GPMC0_A11
V14
PRG1_PRU1_GPO9
PRG1_PRU1_GPO9
PRG1_PRU1_GPI9
PRG1_UART0_RXD
RGMII1_TD1
0
0
1
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
I
O
I
RMII1_RXD1
0
PRG1_IEP0_EDIO_DATA_IN_OUT30
GPIO0_74
IO
IO
OZ
0
pad
GPMC0_A12
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
W14
PRG1_PRU1_GPO10
PRG1_PRU1_GPO10
0
1
2
3
4
5
6
7
8
0
1
2
4
5
7
8
0
1
2
3
4
5
7
8
0
1
2
3
4
5
7
8
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU1_GPI10
PRG1_UART0_TXD
PRG1_PWM2_TZ_IN
RGMII1_TD2
O
I
0
O
O
IO
IO
RMII1_TXD0
PRG1_IEP0_EDIO_DATA_IN_OUT31
GPIO0_75
0
pad
GPMC0_A13
OZ
IO
I
AA10
PRG1_PRU1_GPO11
PRG1_PRU1_GPO11
PRG1_PRU1_GPI11
PRG1_RGMII2_TD0
RGMII2_TD0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
O
RMII2_TXD0
O
GPIO0_76
IO
OZ
IO
I
pad
GPMC0_A14
V10
PRG1_PRU1_GPO12
PRG1_PRU1_GPO12
PRG1_PRU1_GPI12
PRG1_RGMII2_TD1
PRG1_PWM1_A0
RGMII2_TD1
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
IO
O
0
RMII2_TXD1
O
GPIO0_77
IO
OZ
IO
I
pad
GPMC0_A15
U10
PRG1_PRU1_GPO13
PRG1_PRU1_GPO13
PRG1_PRU1_GPI13
PRG1_RGMII2_TD2
PRG1_PWM1_B0
RGMII2_TD2
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
IO
O
1
RMII2_CRS_DV
GPIO0_78
I
0
IO
OZ
pad
GPMC0_A16
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
AA11
PRG1_PRU1_GPO14
PRG1_PRU1_GPO14
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
0
1
2
3
4
7
8
0
1
2
3
4
5
7
8
9
IO
I
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
PRG1_PRU1_GPI14
PRG1_RGMII2_TD3
PRG1_PWM1_A1
RGMII2_TD3
O
IO
O
IO
0
GPIO0_79
pad
GPMC0_A17
OZ
IO
I
Y11
PRG1_PRU1_GPO15
PRG1_PRU1_GPO15
PRG1_PRU1_GPI15
PRG1_RGMII2_TX_CTL
PRG1_PWM1_B1
RGMII2_TX_CTL
RMII2_TX_EN
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
IO
O
1
O
GPIO0_80
IO
OZ
IO
I
pad
GPMC0_A18
Y10
PRG1_PRU1_GPO16
PRG1_PRU1_GPO16
PRG1_PRU1_GPI16
PRG1_RGMII2_TXC
PRG1_PWM1_A2
RGMII2_TXC
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
IO
IO
IO
IO
OZ
IO
I
0
0
0
GPIO0_81
pad
GPMC0_A19
AA14
PRG1_PRU1_GPO17
PRG1_PRU1_GPO17
PRG1_PRU1_GPI17
PRG1_IEP1_EDC_SYNC_OUT1
PRG1_PWM1_B2
RGMII1_TD3
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
O
IO
O
1
RMII1_TXD1
O
GPIO0_19
IO
O
pad
GPMC0_BE3n
PRG1_ECAP0_SYNC_OUT
O
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
Y13
PRG1_PRU1_GPO18
PRG1_PRU1_GPO18
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
6
7
8
9
0
0
IO
I
0
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/0
1/1
PRG1_PRU1_GPI18
PRG1_IEP1_EDC_LATCH_IN0
PRG1_PWM1_TZ_IN
RGMII1_RD2
I
I
I
RMII1_TX_EN
O
IO
I
GPIO0_20
pad
1
UART5_CTSn
PRG1_ECAP0_SYNC_IN
PRG1_PRU1_GPO19
PRG1_PRU1_GPI19
PRG1_IEP1_EDC_SYNC_OUT0
PRG1_PWM1_TZ_OUT
RGMII1_RD3
I
0
V12
PRG1_PRU1_GPO19
IO
I
0
OFF
7
1.8 V/3.3 V VDDSHV2 Yes
LVCMOS
PU/PD
0
O
O
I
0
RMII1_CRS_DV
I
0
SPI3_CS2
IO
IO
O
IO
O
I
1
GPIO0_84
pad
UART5_RTSn
PRG1_ECAP0_IN_APWM_OUT
RESETSTATz
0
F16
E18
T13
RESETSTATz
PD
0
0
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
SERDES
PU/PD
PU/PD
RESET_REQz
SERDES0_REXT
RESET_REQz
OFF
SERDES0_REXT
A
1.8 V
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
W16
SERDES0_REFCLK0N
SERDES0_REFCLK0N
IO
1.8 V
VDDA_1P8
_SERDES0
,
SERDES
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
W17
SERDES0_REFCLK0P
SERDES0_REFCLK0P
IO
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
SERDES
SERDES
SERDES
SERDES
SERDES
Y15
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
I
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
Y16
I
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
AA16
O
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
AA17
O
VDDA_1P8
_SERDES0
,
VDDA_0P8
5_SERDES
0,
VDDA_0P8
5_SERDES
0_C
D13
C14
SPI0_CLK
SPI1_CLK
SPI0_CLK
0
7
0
3
7
0
7
IO
IO
IO
I
0
OFF
7
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
GPIO1_44
pad
0
SPI1_CLK
OFF
OFF
1.8 V/3.3 V VDDSHV0 Yes
PU/PD
PU/PD
EHRPWM6_SYNCI
GPIO1_49
0
IO
IO
IO
pad
1
D12
SPI0_CS0
SPI0_CS0
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
GPIO1_42
pad
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
C13
SPI0_CS1
SPI0_CS1
0
1
2
3
4
5
6
7
0
7
0
7
0
3
7
0
1
2
4
5
6
7
8
0
3
7
0
3
7
0
IO
O
1
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1/1
CPTS0_TS_COMP
I2C2_SCL
IOD
IO
O
1
0
TIMER_IO10
PRG0_IEP0_EDIO_OUTVALID
UART6_RXD
ADC_EXT_TRIGGER0
GPIO1_43
I
1
0
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
pad
0
A13
A14
B14
SPI0_D0
SPI0_D1
SPI1_CS0
SPI0_D0
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
GPIO1_45
pad
0
SPI0_D1
GPIO1_46
pad
1
SPI1_CS0
EHRPWM6_A
GPIO1_47
0
pad
1
D14
SPI1_CS1
SPI1_CS1
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
CPTS0_TS_SYNC
I2C2_SDA
IOD
O
1
PRG1_IEP0_EDIO_OUTVALID
UART6_TXD
ADC_EXT_TRIGGER1
GPIO1_48
O
I
0
IO
IO
IO
O
pad
0
TIMER_IO11
SPI1_D0
B15
A15
SPI1_D0
SPI1_D1
0
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
EHRPWM6_SYNCO
GPIO1_50
IO
IO
IO
IO
I
pad
0
SPI1_D1
EHRPWM6_B
GPIO1_51
0
pad
B11
C11
A12
C12
D11
TCK
TDI
TCK
0
0
0
0
0
1.8 V/3.3 V VDDSHV_ Yes
MCU
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
TDI
0
0
0
0
I
OFF
OFF
OFF
1.8 V/3.3 V VDDSHV_ Yes
MCU
1/1
0/0
1/1
1/1
TDO
TMS
TRSTn
TDO
TMS
TRSTn
OZ
1.8 V/3.3 V VDDSHV_ Yes
MCU
I
I
1.8 V/3.3 V VDDSHV_ Yes
MCU
1.8 V/3.3 V VDDSHV_ Yes
MCU
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
B16
UART0_CTSn
UART0_CTSn
0
1
2
3
4
6
7
8
9
0
1
3
4
6
7
8
0
2
7
8
0
2
7
8
0
1
2
3
4
5
6
7
8
I
1
1
0
1
0
0
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SPI0_CS2
IO
I
ADC_EXT_TRIGGER0
UART2_RXD
TIMER_IO6
I
IO
IO
IO
IO
O
O
IO
O
IO
IO
IO
IO
I
SPI4_CLK
GPIO1_54
pad
0
EQEP0_S
CP_GEMAC_CPTS0_TS_SYNC
UART0_RTSn
SPI0_CS3
A16
UART0_RTSn
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
1
UART2_TXD
TIMER_IO7
0
SPI4_D0
0
GPIO1_55
pad
0
EQEP0_I
D15
C16
D16
UART0_RXD
UART0_TXD
UART1_CTSn
UART0_RXD
SPI2_D0
1
OFF
OFF
OFF
7
7
7
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
LVCMOS
PU/PD
PU/PD
PU/PD
IO
IO
I
0
GPIO1_52
pad
0
EQEP0_A
UART0_TXD
SPI2_D1
O
IO
IO
I
0
GPIO1_53
pad
0
EQEP0_B
UART1_CTSn
SPI1_CS2
I
1
IO
I
1
ADC_EXT_TRIGGER1
PCIE0_CLKREQn
UART3_RXD
CP_GEMAC_CPTS0_TS_SYNC
SPI4_D1
0
IO
I
0
1
O
IO
IO
IO
0
GPIO1_58
pad
0
EQEP1_S
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
E16
UART1_RTSn
UART1_RTSn
0
1
4
5
6
7
8
0
2
5
7
8
0
2
5
7
8
O
IO
O
I
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SPI1_CS3
1
UART3_TXD
CP_GEMAC_CPTS0_HW2TSPUSH
SPI4_CS0
0
1
IO
IO
IO
I
GPIO1_59
pad
0
EQEP1_I
E15
E14
UART1_RXD
UART1_TXD
UART1_RXD
1
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
LVCMOS
PU/PD
PU/PD
SPI2_CS0
IO
O
IO
I
1
CP_GEMAC_CPTS0_TS_COMP
GPIO1_56
pad
0
EQEP1_A
UART1_TXD
O
IO
I
1.8 V/3.3 V VDDSHV0 Yes
SPI2_CLK
0
CP_GEMAC_CPTS0_HW1TSPUSH
GPIO1_57
0
IO
I
pad
0
EQEP1_B
AA20
AA19
USB0_DM
USB0_DP
USB0_DM
IO
1.8 V/3.3 V VDDA_3P3
_USB0,
USB2PHY
USB2PHY
VDDA_1P8
_USB0,
VDDA_0P8
5_USB0
USB0_DP
IO
1.8 V/3.3 V VDDA_3P3
_USB0,
VDDA_1P8
_USB0,
VDDA_0P8
5_USB0
E19
U16
USB0_DRVVBUS
USB0_ID
USB0_DRVVBUS
GPIO1_79
0
7
O
IO
A
OFF
7
1.8 V/3.3 V VDDSHV0 Yes
LVCMOS
PU/PD
0/1
0/1
pad
USB0_ID
1.8 V/3.3 V VDDA_3P3
_USB0,
USB2PHY
VDDA_1P8
_USB0,
VDDA_0P8
5_USB0
U17
USB0_RCALIB
USB0_RCALIB
IO
1.8 V/3.3 V VDDA_3P3
_USB0,
USB2PHY
VDDA_1P8
_USB0,
VDDA_0P8
5_USB0
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
PULL UP/
DOWN
TYPE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
T14
USB0_VBUS
USB0_VBUS
A
1.8 V/3.3 V VDDA_3P3
_USB0,
USB2PHY
VDDA_1P8
_USB0,
VDDA_0P8
5_USB0
P12, P13
P11
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_0P85_USB0
VDDA_1P8_SERDES0
VDDA_1P8_USB0
VDDA_3P3_SDIO
VDDA_3P3_USB0
VDDA_ADC
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_0P85_USB0
VDDA_1P8_SERDES0
VDDA_1P8_USB0
VDDA_3P3_SDIO
VDDA_3P3_USB0
VDDA_ADC
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
T12
R14
R15
H15
R13
J13
K12
VDDA_MCU
VDDA_MCU
N12
VDDA_PLL0
VDDA_PLL0
H9
VDDA_PLL1
VDDA_PLL1
J11
VDDA_PLL2
VDDA_PLL2
G11
VDDA_TEMP0
VDDA_TEMP1
VDDR_CORE
VDDSHV0
VDDA_TEMP0
VDDA_TEMP1
VDDR_CORE
VDDSHV0
L11
L10, M13
F11, G12, G14
M7, N6, P7
R10, R8, T9
P14, P15
M14, M15
L14, L15
F9, G10, G8
VDDSHV1
VDDSHV1
VDDSHV2
VDDSHV2
VDDSHV3
VDDSHV3
VDDSHV4
VDDSHV4
VDDSHV5
VDDSHV5
VDDSHV_MCU
VDDS_DDR
VDDSHV_MCU
VDDS_DDR
F7, G6, H7, J6,
K7, L6
J8
VDDS_DDR_C
VDDS_MMC0
VDDS_OSC
VDDS_DDR_C
VDDS_MMC0
VDDS_OSC
VDD_CORE
PWR
PWR
PWR
PWR
J15, K14
H13
J10, J12, K11, K9, VDD_CORE
L12, L8, M11, M9,
N10, N8, P9
H14
K13
K16
E12
F13
VDD_DLL_MMC0
VDD_DLL_MMC0
VDD_MMC0
PWR
PWR
PWR
PWR
PWR
VDD_MMC0
VMON_1P8_MCU
VMON_1P8_SOC
VMON_3P3_MCU
VMON_1P8_MCU
VMON_1P8_SOC
VMON_3P3_MCU
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Table 6-1. Pin Attributes (ALV Package) (continued)
BALL
RESET
REL.
BALL
RESET
REL.
RXACTIVE
PULL UP/
DOWN
TYPE
BALL
RESET
STATE
I/O
VOLTAGE
VALUE
MUX
MODE
BUFFER
TYPE
/
TXDISABL
E
BALL NUMBER
BALL NAME
SIGNAL NAME
TYPE
DSIS
POWER
HYS
STATE
MUXMODE
F14
K10
G15
VMON_3P3_SOC
VMON_3P3_SOC
PWR
VMON_VSYS
VPP
VMON_VSYS
VPP
PWR
PWR
PWR
A1, A21, A5, A6,
AA1, AA15, AA18,
AA21, C10, C15,
C3, D1, E11, E13,
F10, F15, F8, G1,
G16, G3, G7, G9,
H11, H20, H21,
H6, H8, J14, J16,
J7, J9, K6, K8, L1,
L16, L3, L7, L9,
M10, M12, M6,
M8, N11, N13,
VSS
VSS
N15, N7, N9, P1,
P10, P18, P6, P8,
R12, R7, R9, T10,
T11, T15, T16,
T8, U3, V17,
W10, W18, Y14,
Y17, Y19
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
Note
Table 6-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in
Section 6.3, Signal Descriptions.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.
Note
The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions,
while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
c. Bootstrap are Special Configuration Pins, latched on rising edge of MCU_PORz. These are not programable MUXMODE.
d. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
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•
•
•
•
•
•
•
•
•
•
I = Input
O = Output
IO = Input or Output
IOD = Open drain terminal - Input or Output
IOZ = Input, Output or Three-state terminal
OZ = Output or Three-state terminal
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor.
6. BALL RESET STATE: The state of the terminal at power-on reset:
•
•
•
•
•
•
DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable.
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the MCU_RESETSTATz signal.
An empty box means Not Applicable.
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
9. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
10.HYS: Indicates if the input buffer has hysteresis:
•
•
Yes: With hysteresis
No: Without hysteresis
An empty box means No.
For more information, see the hysteresis values in Section 7.7, Electrical Characteristics.
11.BUFFER TYPE: This column describes the associated output buffer type
An empty box means Not Applicable.
For drive strength of the associated output buffer, refer to Section 7.7, Electrical Characteristics.
12.PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled
via software.
•
PU: Internal pullup
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•
•
•
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
An empty box means No pull.
13.DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "pad" level) when the peripheral pin
function is not selected by any of the PINCNTLx registers.
•
•
•
•
0: Logic 0 driven on the input signal port of the peripheral.
1: Logic 1 driven on the input signal port of the peripheral.
pad: Logic state of the pad is driven on the input signal port of the peripheral.
An empty box means Not Applicable.
14.RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
•
•
•
RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
TXDISABLE: 0 = driver enabled, 1 = driver disabled.
An empty box means Not Applicable.
Note
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (HiZ mode is not an input signal).
Note
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
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6.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.
Note
Signal names provided in each Signal Descriptions table, represent the pin layer multiplexed signal
function which is selected via the PADCONFIG registers. Device subsystems may provide an
additional layer of signal multiplexing, which means the signal names described in these tables
may have additional signal functions. For more information, see the respective peripheral chapter
of the device TRM.
2. DESCRIPTION: Description of the signal
3. PIN TYPE: Signal direction and type:
•
•
•
•
•
•
•
•
•
•
I = Input
O = Output
IO = Input or Output
IOD = Open drain terminal - Input or Output
IOZ = Input, Output or Three-state terminal
OZ = Output or Three-state terminal
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
4. BALL: Associated balls bottom
For more information on the I/O cell configurations, see the Pad Configuration Registers section in Device
Configuration chapter of the device TRM.
6.3.1 ADC
Note
The ADC can be configured to operate as eight general-purpose digital inputs. For more information,
see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
6.3.1.1 MAIN Domain
Table 6-2. ADC0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
G20
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
A
A
A
A
A
A
A
A
I
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
ADC Trigger Input
ADC Trigger Input
F20
E21
D20
G21
F21
F19
E20
ADC_EXT_TRIGGER0
ADC_EXT_TRIGGER1
B16, C13
D14, D16
I
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6.3.2 DDRSS
6.3.2.1 MAIN Domain
Table 6-3. DDRSS0 Signal Descriptions
SIGNAL NAME
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
PIN TYPE
DESCRIPTION
ALV
H2
H1
J5
O
DDRSS Activation Command
IO
O
DDRSS Alert
DDRSS Column Address Strobe
DDRSS Command and Address Parity
DDRSS Row Address Strobe
DDRSS Write Enable
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Address Bus
DDRSS Bank Address
DDRSS Bank Address
DDRSS Bank Group
DDRSS Bank Group
IO Pad Calibration Resistor
DDRSS Clock
O
K5
F6
H4
D2
C5
E2
D4
D3
F2
J2
O
O
O
DDR0_A1
O
DDR0_A2
O
DDR0_A3
O
DDR0_A4
O
DDR0_A5
O
DDR0_A6
O
DDR0_A7
O
L5
DDR0_A8
O
J3
DDR0_A9
O
J4
DDR0_A10
DDR0_A11
O
K3
J1
O
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0(1)
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
O
M5
K4
G4
G5
G2
H3
H5
F1
E1
F4
F3
E3
E4
B2
M2
A3
A2
B5
A4
B3
C4
C2
B4
N5
L4
O
O
O
O
O
A
O
O
DDRSS Negative Clock
DDRSS Clock Enable
DDRSS Clock Enable
DDRSS Chip Select 0
DDRSS Chip Select 1
DDRSS Data Mask
DDRSS Data Mask
DDRSS Data
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
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Table 6-3. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME
DDR0_DQ10
PIN TYPE
DESCRIPTION
ALV
IO
IO
IO
IO
IO
IO
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
DDRSS Data
L2
M3
N4
N3
M4
N2
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
Data strobe 0 input/output for byte 0 of the 16-bit data
bus. This signal is output to the DDRSS memory when
writing and input when reading.
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
IO
IO
IO
C1
B1
N1
Data strobe 0 invert
Data strobe 1 input/output for byte 2 of the 16-bit data
bus. This signal is output to the DDRSS memory when
writing and input when reading.
DDR0_DQS1_n
DDR0_ODT0
IO
O
O
O
Data strobe 1 invert
M1
E5
F5
D5
DDRSS On-Die Termination for Chip Select 0
DDRSS On-Die Termination for Chip Select 1
DDRSS Reset
DDR0_ODT1
DDR0_RESET0_n
(1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.3 GPIO
6.3.3.1 MAIN Domain
Table 6-4. GPIO0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
N20
N21
N19
M19
M18
M20
M21
P21
P20
N18
M17
L19
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
GPIO0_8
GPIO0_9
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
IO
General Purpose Input/Output
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
L18
IO
K17
L17
IO
IO
T20
U21
T18
U20
AA14
Y13
V20
V21
V19
IO
IO
IO
IO
IO
IO
IO
IO
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Table 6-4. GPIO0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DESCRIPTION
ALV
T17
R16
W20
W21
V18
Y21
Y20
R17
P16
R18
T21
P17
T19
W19
Y18
N16
N17
R19
R20
P19
R21
Y7
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO0_32
GPIO0_33
GPIO0_34
GPIO0_35
GPIO0_36
GPIO0_37
GPIO0_38
GPIO0_39
GPIO0_40
GPIO0_41
GPIO0_42
GPIO0_43
GPIO0_44
GPIO0_45
GPIO0_46
GPIO0_47
GPIO0_48
GPIO0_49
GPIO0_50
GPIO0_51
GPIO0_52
GPIO0_53
GPIO0_54
GPIO0_55
GPIO0_56
GPIO0_57
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPIO0_63
GPIO0_64
GPIO0_65
GPIO0_66
GPIO0_67
GPIO0_68
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
U8
W8
V8
Y8
V13
AA7
U13
W13
U15
U14
AA8
U9
W9
AA9
Y9
V9
U7
V7
W7
W11
V11
AA12
Y12
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Table 6-4. GPIO0 Signal Descriptions (continued)
SIGNAL NAME
GPIO0_69
GPIO0_70
GPIO0_71
GPIO0_72
GPIO0_73
GPIO0_74
GPIO0_75
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
GPIO0_80
GPIO0_81
GPIO0_82
GPIO0_83
GPIO0_84
GPIO0_85
GPIO0_86
PIN TYPE
DESCRIPTION
ALV
IO
General Purpose Input/Output
W12
AA13
U11
V15
U12
V14
W14
AA10
V10
U10
AA11
Y11
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Y10
U18
U19
V12
AA6
Y6
IO
IO
IO
IO
IO
Table 6-5. GPIO1 Signal Descriptions
SIGNAL NAME
GPIO1_0
PIN TYPE
DESCRIPTION
ALV
Y1
IO
General Purpose Input/Output
GPIO1_1
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
R4
U2
V2
GPIO1_2
IO
GPIO1_3
IO
GPIO1_4
IO
AA2
R3
T3
GPIO1_5
IO
GPIO1_6
IO
GPIO1_7
IO
T1
GPIO1_8
IO
T2
GPIO1_9
IO
W6
AA5
Y3
GPIO1_10
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16
GPIO1_17
GPIO1_18
GPIO1_19
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
IO
IO
IO
AA3
R6
V4
IO
IO
IO
T5
IO
U4
U1
V1
IO
IO
IO
W1
Y2
IO
IO
W2
V3
IO
IO
T4
IO
W3
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Table 6-5. GPIO1 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
DESCRIPTION
ALV
P4
GPIO1_25
GPIO1_26
GPIO1_27
GPIO1_28
GPIO1_29
GPIO1_30
GPIO1_31
GPIO1_32
GPIO1_33
GPIO1_34
GPIO1_35
GPIO1_36
GPIO1_37
GPIO1_38
GPIO1_39
GPIO1_40
GPIO1_41
GPIO1_42
GPIO1_43
GPIO1_44
GPIO1_45
GPIO1_46
GPIO1_47
GPIO1_48
GPIO1_49
GPIO1_50
GPIO1_51
GPIO1_52
GPIO1_53
GPIO1_54
GPIO1_55
GPIO1_56
GPIO1_57
GPIO1_58
GPIO1_59
GPIO1_60
GPIO1_61
GPIO1_62
GPIO1_63
GPIO1_64
GPIO1_65
GPIO1_66
GPIO1_67
GPIO1_68
GPIO1_69
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
R5
W5
R1
Y5
V6
W4
Y4
T6
U6
U5
AA4
V5
P5
R2
P2
P3
D12
C13
D13
A13
A14
B14
D14
C14
B15
A15
D15
C16
B16
A16
E15
E14
D16
E16
A17
B17
C17
D17
A18
B18
C18
B19
D18
A19
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Table 6-5. GPIO1 Signal Descriptions (continued)
SIGNAL NAME
GPIO1_70
PIN TYPE
DESCRIPTION
ALV
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
General Purpose Input/Output
C19
K18
K19
L21
K21
L20
J19
D19
C20
E19
GPIO1_71
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
GPIO1_72
GPIO1_73
GPIO1_74
GPIO1_75
GPIO1_76
GPIO1_77
GPIO1_78
GPIO1_79
6.3.3.2 MCU Domain
Table 6-6. MCU_GPIO0 Signal Descriptions
SIGNAL NAME
MCU_GPIO0_0
MCU_GPIO0_1
MCU_GPIO0_2
MCU_GPIO0_3
MCU_GPIO0_4
MCU_GPIO0_5
MCU_GPIO0_6
MCU_GPIO0_7
MCU_GPIO0_8
MCU_GPIO0_9
MCU_GPIO0_10
MCU_GPIO0_11
MCU_GPIO0_12
MCU_GPIO0_13
MCU_GPIO0_14
MCU_GPIO0_15
MCU_GPIO0_16
MCU_GPIO0_17
MCU_GPIO0_18
MCU_GPIO0_19
MCU_GPIO0_20
MCU_GPIO0_21
MCU_GPIO0_22
PIN TYPE
DESCRIPTION
ALV
E8
IO
General Purpose Input/Output
IO
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
General Purpose Input/Output
D8
A8
IO
IO
A9
IO
B6
IO
A7
IO
B7
IO
D7
C7
C8
E7
IO
IO
IO
IO
E6
IO
C6
D6
C9
D9
B8
IO
IO
IO
IO
IO
B9
IO
E9
IO
A10
A11
B10
B13
IO
IO
IO
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6.3.4 I2C
6.3.4.1 MAIN Domain
Table 6-7. I2C0 Signal Descriptions
SIGNAL NAME
I2C0_SCL
PIN TYPE
DESCRIPTION
ALV
A18
B18
IOD
I2C Clock
I2C Data
I2C0_SDA
IOD
Table 6-8. I2C1 Signal Descriptions
SIGNAL NAME
I2C1_SCL
PIN TYPE
DESCRIPTION
ALV
C18
B19
IOD
I2C Clock
I2C Data
I2C1_SDA
IOD
Table 6-9. I2C2 Signal Descriptions
SIGNAL NAME
I2C2_SCL
PIN TYPE
DESCRIPTION
ALV
IOD
I2C Clock
I2C Data
C13, P19
D14, R21
I2C2_SDA
IOD
Table 6-10. I2C3 Signal Descriptions
SIGNAL NAME
I2C3_SCL
PIN TYPE
DESCRIPTION
ALV
C17
D17
IOD
I2C Clock
I2C Data
I2C3_SDA
IOD
6.3.4.2 MCU Domain
Table 6-11. MCU_I2C0 Signal Descriptions
SIGNAL NAME
MCU_I2C0_SCL
PIN TYPE
DESCRIPTION
ALV
E9
IOD
I2C Clock
I2C Data
MCU_I2C0_SDA
IOD
A10
Table 6-12. MCU_I2C1 Signal Descriptions
SIGNAL NAME
MCU_I2C1_SCL
PIN TYPE
DESCRIPTION
ALV
A11
B10
IOD
I2C Clock
I2C Data
MCU_I2C1_SDA
IOD
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6.3.5 MCAN
6.3.5.1 MAIN Domain
Table 6-13. MCAN0 Signal Descriptions
SIGNAL NAME
MCAN0_RX
PIN TYPE
DESCRIPTION
ALV
I
MCAN Receive Data
MCAN Transmit Data
B17
A17
MCAN0_TX
O
Table 6-14. MCAN1 Signal Descriptions
SIGNAL NAME
MCAN1_RX
PIN TYPE
DESCRIPTION
ALV
D17
C17
I
MCAN Receive Data
MCAN Transmit Data
MCAN1_TX
O
6.3.6 MCSPI
6.3.6.1 MAIN Domain
Table 6-15. MCSPI0 Signal Descriptions
SIGNAL NAME
SPI0_CLK
PIN TYPE
DESCRIPTION
ALV
D13
D12
C13
B16
A16
A13
A14
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI0_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI0_CS1
SPI0_CS2
SPI0_CS3
SPI0_D0
SPI0_D1
SPI Data 1
Table 6-16. MCSPI1 Signal Descriptions
SIGNAL NAME
SPI1_CLK
PIN TYPE
DESCRIPTION
ALV
C14
B14
D14
D16
E16
B15
A15
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI1_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI1_CS1
SPI1_CS2
SPI1_CS3
SPI1_D0
SPI1_D1
SPI Data 1
Table 6-17. MCSPI2 Signal Descriptions
SIGNAL NAME
SPI2_CLK
PIN TYPE
DESCRIPTION
ALV
E14
E15
C18
B19
A19
D15
C16
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI2_CS0
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI2_CS1
SPI2_CS2
SPI2_CS3
SPI2_D0
SPI2_D1
SPI Data 1
Table 6-18. MCSPI3 Signal Descriptions
SIGNAL NAME
SPI3_CLK
PIN TYPE
DESCRIPTION
ALV
U4
IO
IO
IO
SPI Clock
SPI3_CS0
SPI Chip Select 0
SPI Chip Select 1
U1
SPI3_CS1
T5
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Table 6-18. MCSPI3 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
V12
V15
R6
SPI3_CS2
SPI3_CS3
SPI3_D0
SPI3_D1
IO
IO
IO
IO
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI Data 1
V4
Table 6-19. MCSPI4 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
B16
E16
A17
B17
D18
A16
D16
SPI4_CLK
SPI4_CS0
SPI4_CS1
SPI4_CS2
SPI4_CS3
SPI4_D0
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 0
SPI Chip Select 2
SPI Data 0
SPI4_D1
SPI Data 1
6.3.6.2 MCU Domain
Table 6-20. MCU_MCSPI0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
E6
D6
C6
D8
B8
E7
B6
MCU_SPI0_CLK
MCU_SPI0_CS0
MCU_SPI0_CS1
MCU_SPI0_CS2
MCU_SPI0_CS3
MCU_SPI0_D0
MCU_SPI0_D1
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI Data 1
Table 6-21. MCU_MCSPI1 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
D7
A7
B7
E8
B9
C7
C8
MCU_SPI1_CLK
MCU_SPI1_CS0
MCU_SPI1_CS1
MCU_SPI1_CS2
MCU_SPI1_CS3
MCU_SPI1_D0
MCU_SPI1_D1
IO
IO
IO
IO
IO
IO
IO
SPI Clock
SPI Chip Select 0
SPI Chip Select 1
SPI Chip Select 2
SPI Chip Select 3
SPI Data 0
SPI Data 1
6.3.7 UART
6.3.7.1 MAIN Domain
Table 6-22. UART0 Signal Descriptions
SIGNAL NAME
UART0_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Data Carrier Detect (active low)
UART Data Set Ready (active low)
UART Data Terminal Ready (active low)
UART Ring Indicator
ALV
B16
C17
D17
A17
B17
A16
I
I
UART0_DCDn
UART0_DSRn
I
UART0_DTRn
O
I
UART0_RIn
UART0_RTSn
O
UART Request to Send (active low)
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Table 6-22. UART0 Signal Descriptions (continued)
SIGNAL NAME
UART0_RXD
PIN TYPE
DESCRIPTION
ALV
I
UART Receive Data
UART Transmit Data
D15
C16
UART0_TXD
O
Table 6-23. UART1 Signal Descriptions
SIGNAL NAME
UART1_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALV
D16
E16
E15
E14
I
UART1_RTSn
O
I
UART1_RXD
UART1_TXD
O
UART Transmit Data
Table 6-24. UART2 Signal Descriptions
SIGNAL NAME
UART2_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
ALV
I
L20, V19, Y1
J19, T18, U2
UART2_RTSn
O
B16, K18, T20, V1,
W6
UART2_RXD
UART2_TXD
I
UART Receive Data
UART Transmit Data
O
A16, K19, R4, U21
Table 6-25. UART3 Signal Descriptions
SIGNAL NAME
UART3_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
ALV
I
D19, T17, V2
C20, R3, U19
UART3_RTSn
O
AA5, D16, L21, U20,
W1
UART3_RXD
UART3_TXD
I
UART Receive Data
UART Transmit Data
O
AA2, E16, K21, U18
Table 6-26. UART4 Signal Descriptions
SIGNAL NAME
UART4_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
ALV
I
R16, R5, T3, V1
R1, R17, T2, W1
UART4_RTSn
O
A17, L20, V20, W4,
Y3
UART4_RXD
UART4_TXD
I
UART Receive Data
UART Transmit Data
B17, J19, T1, V21,
W5, Y4
O
Table 6-27. UART5 Signal Descriptions
SIGNAL NAME
UART5_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
ALV
I
W20, Y13, Y2
T21, V12, V3
UART5_RTSn
O
C17, D19, P16, T6,
Y5
UART5_RXD
UART5_TXD
I
UART Receive Data
UART Transmit Data
O
C20, D17, R18, W2
Table 6-28. UART6 Signal Descriptions
SIGNAL NAME
UART6_CTSn
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALV
I
A18, T4, W21
B18, P17, P4
C13, U6, V6, Y21
D14, W3, Y20
UART6_RTSn
O
I
UART6_RXD
UART6_TXD
O
UART Transmit Data
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6.3.7.2 MCU Domain
Table 6-29. MCU_UART0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALV
D8
E8
MCU_UART0_CTSn
MCU_UART0_RTSn
MCU_UART0_RXD
MCU_UART0_TXD
I
O
I
A9
O
UART Transmit Data
A8
Table 6-30. MCU_UART1 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
UART Clear to Send (active low)
UART Request to Send (active low)
UART Receive Data
ALV
B8
MCU_UART1_CTSn
MCU_UART1_RTSn
MCU_UART1_RXD
MCU_UART1_TXD
I
O
I
B9
C9
D9
O
UART Transmit Data
6.3.8 MDIO
6.3.8.1 MAIN Domain
Table 6-31. MDIO0 Signal Descriptions
SIGNAL NAME
MDIO0_MDC
PIN TYPE
DESCRIPTION
ALV
O
MDIO Clock
MDIO Data
R2, Y6
AA6, P5
MDIO0_MDIO
IO
6.3.9 CPSW3G
6.3.9.1 MAIN Domain
Table 6-32. CPSW3G0 Signal Descriptions
SIGNAL NAME
RGMII1_RXC
RGMII1_RX_CTL
RGMII1_TXC
PIN TYPE
DESCRIPTION
ALV
AA5, W13
V13, W6
U14
I
I
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Clock
RGMII Receive Control
RGMII Transmit Clock
RGMII Transmit Control
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
RGMII Transmit Data 1
RGMII Transmit Data 2
RGMII Transmit Data 3
RGMII Receive Data 0
RGMII Receive Data 1
RGMII Receive Data 2
RGMII Receive Data 3
RGMII Transmit Data 0
IO
O
I
RGMII1_TX_CTL
RGMII2_RXC
RGMII2_RX_CTL
RGMII2_TXC
U15
U11
I
W12
IO
O
I
Y10
RGMII2_TX_CTL
RGMII1_RD0
Y11
AA13, W5
U12, Y5
V6, Y13
V12, V5
V15
RGMII1_RD1
I
RGMII1_RD2
I
RGMII1_RD3
I
RGMII1_TD0
O
O
O
O
I
RGMII1_TD1
V14
RGMII1_TD2
W14
RGMII1_TD3
AA14
W11
RGMII2_RD0
RGMII2_RD1
I
V11
RGMII2_RD2
I
AA12
Y12
RGMII2_RD3
I
RGMII2_TD0
O
AA10
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Table 6-32. CPSW3G0 Signal Descriptions (continued)
SIGNAL NAME
RGMII2_TD1
PIN TYPE
DESCRIPTION
ALV
O
O
O
I
RGMII Transmit Data 1
V10
U10
RGMII2_TD2
RGMII Transmit Data 2
RGMII Transmit Data 3
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
RMII Carrier Sense / Data Valid
RMII Receive Data Error
RMII Transmit Enable
RMII Receive Data 0
RGMII2_TD3
AA11
RMII1_CRS_DV
RMII1_RX_ER
RMII1_TX_EN
RMII2_CRS_DV
RMII2_RX_ER
RMII2_TX_EN
RMII1_RXD0
R2, V12
U15, W6
P5, Y13
U10
I
O
I
I
W12
O
I
Y11
V15, W5
V14, Y5
V6, W14
AA14, V5
W11
RMII1_RXD1
I
RMII Receive Data 1
RMII1_TXD0
O
O
I
RMII Transmit Data 0
RMII Transmit Data 1
RMII Receive Data 0
RMII1_TXD1
RMII2_RXD0
RMII2_RXD1
I
RMII Receive Data 1
V11
RMII2_TXD0
O
O
I
RMII Transmit Data 0
RMII Transmit Data 1
RMII Reference Clock
AA10
RMII2_TXD1
V10
RMII_REF_CLK
AA5, U14
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6.3.10 ECAP
6.3.10.1 MAIN Domain
Table 6-33. ECAP0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP0_IN_APWM_OUT
IO
D18
Table 6-34. ECAP1 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP1_IN_APWM_OUT
IO
C17
Table 6-35. ECAP2 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP2_IN_APWM_OUT
IO
D17
6.3.11 EQEP
6.3.11.1 MAIN Domain
Table 6-36. EQEP0 Signal Descriptions
SIGNAL NAME
EQEP0_A
PIN TYPE
DESCRIPTION
ALV
I
EQEP Quadrature Input A
D15, N16, Y2
C16, N17, W2
A16, R20, T6, Y5
B16, R19, V3
EQEP0_B
I
EQEP Quadrature Input B
EQEP Index
EQEP0_I
IO
IO
EQEP0_S
EQEP Strobe
Table 6-37. EQEP1 Signal Descriptions
SIGNAL NAME
EQEP1_A
PIN TYPE
DESCRIPTION
ALV
I
EQEP Quadrature Input A
E15, T4, W20
E14, W21, W3
E16, R21, U6, V6
D16, P19, P4
EQEP1_B
I
EQEP Quadrature Input B
EQEP Index
EQEP1_I
IO
IO
EQEP1_S
EQEP Strobe
Table 6-38. EQEP2 Signal Descriptions
SIGNAL NAME
EQEP2_A
PIN TYPE
DESCRIPTION
ALV
C17, R5
I
EQEP Quadrature Input A
EQEP2_B
I
EQEP Quadrature Input B
EQEP Index
D17, W5, Y4
A17, W4
B17, R1
EQEP2_I
IO
IO
EQEP2_S
EQEP Strobe
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6.3.12 EPWM
6.3.12.1 MAIN Domain
Table 6-39. EPWM Signal Descriptions
SIGNAL NAME
EHRPWM_SOCA
PIN TYPE
DESCRIPTION
EHRPWM Start of Conversion A
EHRPWM Start of Conversion B
ALV
O
O
C17
D17
EHRPWM_SOCB
Table 6-40. EPWM0 Signal Descriptions
SIGNAL NAME
EHRPWM0_A
PIN TYPE
DESCRIPTION
ALV
U20
U18
T20
U21
T18
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM0_B
EHRPWM0_SYNCI
EHRPWM0_SYNCO
EHRPWM_TZn_IN0
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 0 (active low)
O
I
Table 6-41. EPWM1 Signal Descriptions
SIGNAL NAME
EHRPWM1_A
PIN TYPE
DESCRIPTION
ALV
U19
V20
V21
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM1_B
EHRPWM_TZn_IN1
EHRPWM Trip Zone Input 1 (active low)
Table 6-42. EPWM2 Signal Descriptions
SIGNAL NAME
EHRPWM2_A
PIN TYPE
DESCRIPTION
ALV
V19
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM2_B
T17
EHRPWM_TZn_IN2
EHRPWM Trip Zone Input 2 (active low)
R16, R20
Table 6-43. EPWM3 Signal Descriptions
SIGNAL NAME
EHRPWM3_A
PIN TYPE
DESCRIPTION
ALV
V18
Y21
Y20
R17
P16
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM3_B
EHRPWM3_SYNCI
EHRPWM3_SYNCO
EHRPWM_TZn_IN3
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
EHRPWM Trip Zone Input 3 (active low)
O
I
Table 6-44. EPWM4 Signal Descriptions
SIGNAL NAME
EHRPWM4_A
PIN TYPE
DESCRIPTION
ALV
R18
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM4_B
T21
EHRPWM_TZn_IN4
EHRPWM Trip Zone Input 4 (active low)
P17, P19
Table 6-45. EPWM5 Signal Descriptions
SIGNAL NAME
EHRPWM5_A
PIN TYPE
DESCRIPTION
ALV
T19
IO
IO
I
EHRPWM Output A
EHRPWM Output B
EHRPWM5_B
W19
EHRPWM_TZn_IN5
EHRPWM Trip Zone Input 5 (active low)
R21, Y18
Table 6-46. EPWM6 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
EHRPWM6_A
IO
EHRPWM Output A
B14, N16
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Table 6-46. EPWM6 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
EHRPWM6_B
IO
I
EHRPWM Output B
A15, N17
EHRPWM6_SYNCI
EHRPWM6_SYNCO
Sync Input to EHRPWM module from an external pin
Sync Output to EHRPWM module to an external pin
C14, R19
B15, R20
O
Table 6-47. EPWM7 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
EHRPWM7_A
EHRPWM7_B
IO
IO
EHRPWM Output A
EHRPWM Output B
P17, P5, W20
R2, W21, Y18
Table 6-48. EPWM8 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
EHRPWM8_A
EHRPWM8_B
IO
IO
EHRPWM Output A
EHRPWM Output B
V1, V21
R16, W1
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6.3.13 SERDES
6.3.13.1 MAIN Domain
Table 6-49. SERDES0 Signal Descriptions
SIGNAL NAME(1)
PCIE0_CLKREQn
PIN TYPE
DESCRIPTION
ALV
IO
A
PCIE Clock Request Signal
D16
T13
SERDES0_REXT(2)
SERDES0_REFCLK0N
SERDES0_REFCLK0P
SERDES0_RX0_N
External Calibration Resistor
IO
IO
I
Serdes Reference Clock Input/Output (negative)
Serdes Reference Clock Input/Output (positive)
SERDES Differential Receive Data (negative)
SERDES Differential Receive Data (positive)
SERDES Differential Transmit Data (negative)
SERDES Differential Transmit Data (positive)
W16
W17
Y15
SERDES0_RX0_P
I
Y16
SERDES0_TX0_N
O
O
AA16
AA17
SERDES0_TX0_P
(1) The functionality of these pins is controlled by SERDES0_LN0_CTRL LANE_FUNC_SEL.
(2) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
6.3.14 USB
6.3.14.1 MAIN Domain
Table 6-50. USB0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
USB 2.0 Differential Data (negative)
USB 2.0 Differential Data (positive)
USB VBUS control output (active high)
USB 2.0 Dual-Role Device Role Select
Pin to connect to calibration resistor
USB Level-shifted VBUS Input
ALV
AA20
AA19
E19
USB0_DM
USB0_DP
IO
IO
O
USB0_DRVVBUS
USB0_ID
A
U16
USB0_RCALIB(1)
USB0_VBUS(2)
IO
A
U17
T14
(1) An external 500 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 9.3.3, USB
Design Guidelines.
6.3.15 OSPI
6.3.15.1 MAIN Domain
Table 6-51. OSPI0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
N20
N19
L17
N21
L19
L18
K17
L17
M19
M18
M20
M21
P21
P20
OSPI0_CLK
OSPI0_DQS
O
I
OSPI Clock
OSPI Data Strobe (DQS) or Loopback Clock Input
OSPI ECC Status
OSPI0_ECC_FAIL
OSPI0_LBCLKO
OSPI0_CSn0
OSPI0_CSn1
OSPI0_CSn2
OSPI0_CSn3
OSPI0_D0
I
IO
O
O
O
O
IO
IO
IO
IO
IO
IO
OSPI Loopback Clock Output
OSPI Chip Select 0 (active low)
OSPI Chip Select 1 (active low)
OSPI Chip Select 2 (active low)
OSPI Chip Select 3 (active low)
OSPI Data 0
OSPI0_D1
OSPI Data 1
OSPI0_D2
OSPI Data 2
OSPI0_D3
OSPI Data 3
OSPI0_D4
OSPI Data 2
OSPI0_D5
OSPI Data 2
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Table 6-51. OSPI0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
N18
M17
L17
K17
OSPI0_D6
OSPI0_D7
IO
IO
O
OSPI Data 2
OSPI Data 2
OSPI Reset
OSPI Reset
OSPI0_RESET_OUT0
OSPI0_RESET_OUT1
O
6.3.16 GPMC
6.3.16.1 MAIN Domain
Table 6-52. GPMC0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
GPMC Address Valid (active low) or Address Latch
Enable
GPMC0_ADVn_ALE
O
P16
GPMC0_CLK
GPMC0_DIR
O
O
GPMC clock
R17
N17
GPMC Data Bus Signal Direction Control
GPMC Output Enable (active low) or Read Enable
(active low)
GPMC0_OEn_REn
O
R18
GPMC0_WEn
GPMC0_WPn
O
O
GPMC Write Enable (active low)
T21
N16
GPMC Flash Write Protect (active low)
GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
GPMC0_A0
GPMC0_A1
GPMC0_A2
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
GPMC0_A11
GPMC0_A12
GPMC0_A13
GPMC0_A14
GPMC0_A15
GPMC0_A16
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
U2, U7
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
AA2, V7
T2, W7
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
V4, W11
U4, V11
AA12, V1
W1, Y12
W12, Y4
AA13, T6
U11, U6
U5, V15
AA4, U12
P2, V14
P3, W14
AA10, AA3
R6, V10
T5, U10
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
GPMC address 10 Output in A/D non-multiplexed mode
and Address 26 in A/D multiplexed mode
GPMC address 11 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 12 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 13 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 14 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 15 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 16 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
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Table 6-52. GPMC0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
GPMC address 17 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC0_A17
OZ
AA11, U1
T4, Y11
R5, Y10
R21
GPMC address 18 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC0_A18
GPMC0_A19
GPMC0_A20
GPMC0_A21
GPMC0_A22
OZ
OZ
OZ
OZ
OZ
GPMC address 19 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 20 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
GPMC address 21 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
Y18
GPMC address 22 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
N16
GPMC Data 0 Input/Output in A/D non-multiplexed mode
and additionally Address 1 Output in A/D multiplexed
mode
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
T20
U21
T18
U20
U18
U19
V20
V21
V19
T17
R16
W20
W21
V18
Y21
GPMC Data 1 Input/Output in A/D non-multiplexed mode
and additionally Address 2 Output in A/D multiplexed
mode
GPMC Data 2 Input/Output in A/D non-multiplexed mode
and additionally Address 3 Output in A/D multiplexed
mode
GPMC Data 3 Input/Output in A/D non-multiplexed mode
and additionally Address 4 Output in A/D multiplexed
mode
GPMC Data 4 Input/Output in A/D non-multiplexed mode
and additionally Address 5 Output in A/D multiplexed
mode
GPMC Data 5 Input/Output in A/D non-multiplexed mode
and additionally Address 6 Output in A/D multiplexed
mode
GPMC Data 6 Input/Output in A/D non-multiplexed mode
and additionally Address 7 Output in A/D multiplexed
mode
GPMC Data 7 Input/Output in A/D non-multiplexed mode
and additionally Address 8 Output in A/D multiplexed
mode
GPMC Data 8 Input/Output in A/D non-multiplexed mode
and additionally Address 9 Output in A/D multiplexed
mode
GPMC Data 9 Input/Output in A/D non-multiplexed mode
and additionally Address 10 Output in A/D multiplexed
mode
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
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Table 6-52. GPMC0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
GPMC0_AD15
GPMC0_AD16
GPMC0_AD17
GPMC0_AD18
GPMC0_AD19
GPMC0_AD20
GPMC0_AD21
GPMC0_AD22
GPMC0_AD23
GPMC0_AD24
GPMC0_AD25
GPMC0_AD26
GPMC0_AD27
GPMC0_AD28
GPMC0_AD29
GPMC0_AD30
GPMC0_AD31
IO
Y20
GPMC Data 16 Input/Output in A/D non-multiplexed
mode and additionally Address 17 Output in A/D
multiplexed mode
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Y7
U8
GPMC Data 17 Input/Output in A/D non-multiplexed
mode and additionally Address 18 Output in A/D
multiplexed mode
GPMC Data 18 Input/Output in A/D non-multiplexed
mode and additionally Address 19 Output in A/D
multiplexed mode
W8
V8
GPMC Data 19 Input/Output in A/D non-multiplexed
mode and additionally Address 20 Output in A/D
multiplexed mode
GPMC Data 20 Input/Output in A/D non-multiplexed
mode and additionally Address 21 Output in A/D
multiplexed mode
Y8
GPMC Data 21 Input/Output in A/D non-multiplexed
mode and additionally Address 22 Output in A/D
multiplexed mode
V13
AA7
U13
W13
U15
U14
AA8
U9
GPMC Data 22 Input/Output in A/D non-multiplexed
mode and additionally Address 23 Output in A/D
multiplexed mode
GPMC Data 23 Input/Output in A/D non-multiplexed
mode and additionally Address 24 Output in A/D
multiplexed mode
GPMC Data 24 Input/Output in A/D non-multiplexed
mode and additionally Address 25 Output in A/D
multiplexed mode
GPMC Data 25 Input/Output in A/D non-multiplexed
mode and additionally Address 26 Output in A/D
multiplexed mode
GPMC Data 26 Input/Output in A/D non-multiplexed
mode and additionally Address 27 Output in A/D
multiplexed mode
GPMC Data 27 Input/Output in A/D non-multiplexed
mode and additionally Address 28 Output in A/D
multiplexed mode
GPMC Data 28 Input/Output in A/D non-multiplexed
mode and additionally Address 29 Output in A/D
multiplexed mode
GPMC Data 29 Input/Output in A/D non-multiplexed
mode and additionally Address 30 Output in A/D
multiplexed mode
W9
AA9
Y9
GPMC Data 30 Input/Output in A/D non-multiplexed
mode and additionally Address 31 Output in A/D
multiplexed mode
GPMC Data 31 Input/Output in A/D non-multiplexed
mode and additionally Address 0 Output in A/D
multiplexed mode
IO
O
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
GPMC0_BE0n_CLE
P17
GPMC0_BE1n
GPMC0_BE2n
GPMC0_BE3n
O
O
O
GPMC Upper-Byte Enable (active low)
GPMC Upper-Byte Enable (active low)
GPMC Upper-Byte Enable (active low)
T19
V9
AA14
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Table 6-52. GPMC0 Signal Descriptions (continued)
SIGNAL NAME
GPMC0_CSn0
PIN TYPE
DESCRIPTION
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC External Indication of Wait
GPMC External Indication of Wait
ALV
O
O
O
O
I
R19
R20
P19
R21
W19
Y18
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
GPMC0_WAIT1
I
6.3.17 MMC
6.3.17.1 MAIN Domain
Table 6-53. MMC0 Signal Descriptions
SIGNAL NAME
MMC0_CALPAD
MMC0_CLK
PIN TYPE
DESCRIPTION
MMC/SD/SDIO Calibration Resistor
MMC/SD/SDIO Clock
MMC/SD/SDIO Command
MMC Data Strobe
ALV
F18
G18
J21
G19
K20
J20
J18
J17
H17
H19
H18
G17
A
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MMC0_CMD
MMC0_DS
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
Table 6-54. MMC1 Signal Descriptions
SIGNAL NAME
MMC1_CLK
PIN TYPE
DESCRIPTION
ALV
L20
J19
D19
C20
K21
L21
K19
K18
IO
IO
I
MMC/SD/SDIO Clock
MMC1_CMD
MMC/SD/SDIO Command
SD Card Detect
MMC1_SDCD
MMC1_SDWP
MMC1_DAT0
I
SD Write Protect
IO
IO
IO
IO
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC/SD/SDIO Data
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
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6.3.18 FSI
6.3.18.1 MAIN Domain
Table 6-55. FSI0 RX Signal Descriptions
SIGNAL NAME
FSI_RX0_CLK
PIN TYPE
DESCRIPTION
ALV
V19
T17
R16
I
I
I
FSI Clock
FSI Data
FSI Data
FSI_RX0_D0
FSI_RX0_D1
Table 6-56. FSI0 TX Signal Descriptions
SIGNAL NAME
FSI_TX0_CLK
PIN TYPE
DESCRIPTION
ALV
T19
Y21
Y20
O
O
O
FSI Clock
FSI Data
FSI Data
FSI_TX0_D0
FSI_TX0_D1
Table 6-57. FSI1 RX Signal Descriptions
SIGNAL NAME
FSI_RX1_CLK
PIN TYPE
DESCRIPTION
ALV
W20
W21
V18
I
I
I
FSI Clock
FSI Data
FSI Data
FSI_RX1_D0
FSI_RX1_D1
Table 6-58. FSI1 TX Signal Descriptions
SIGNAL NAME
FSI_TX1_CLK
PIN TYPE
DESCRIPTION
ALV
N16
P17
Y18
O
O
O
FSI Clock
FSI Data
FSI Data
FSI_TX1_D0
FSI_TX1_D1
Table 6-59. FSI2 RX Signal Descriptions
SIGNAL NAME
FSI_RX2_CLK
PIN TYPE
DESCRIPTION
ALV
T20
U21
T18
I
I
I
FSI Clock
FSI Data
FSI Data
FSI_RX2_D0
FSI_RX2_D1
Table 6-60. FSI3 RX Signal Descriptions
SIGNAL NAME
FSI_RX3_CLK
PIN TYPE
DESCRIPTION
ALV
U20
U18
U19
I
I
I
FSI Clock
FSI Data
FSI Data
FSI_RX3_D0
FSI_RX3_D1
Table 6-61. FSI4 RX Signal Descriptions
SIGNAL NAME
FSI_RX4_CLK
PIN TYPE
DESCRIPTION
ALV
R17
V20
V21
I
I
I
FSI Clock
FSI Data
FSI Data
FSI_RX4_D0
FSI_RX4_D1
Table 6-62. FSI5 RX Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
FSI_RX5_CLK
I
FSI Clock
P16
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Table 6-62. FSI5 RX Signal Descriptions (continued)
SIGNAL NAME
FSI_RX5_D0
PIN TYPE
DESCRIPTION
ALV
I
I
FSI Data
FSI Data
R18
T21
FSI_RX5_D1
6.3.19 CPTS
6.3.19.1 MAIN Domain
Table 6-63. CP GEMAC CPTS0 Signal Descriptions
SIGNAL NAME
CP_GEMAC_CPTS0_RFT_CLK
CP_GEMAC_CPTS0_TS_COMP
CP_GEMAC_CPTS0_TS_SYNC
CP_GEMAC_CPTS0_HW1TSPUSH
CP_GEMAC_CPTS0_HW2TSPUSH
PIN TYPE
DESCRIPTION
ALV
D18
I
O
O
I
CPTS Reference Clock
CPTS Time Stamp Counter Compare
CPTS Time Stamp Counter Bit
E15, K18, W1
B16, D16, K19, U1
E14, L21, V1
E16, K21, T1
CPTS Hardware Time Stamp Push 1
CPTS Hardware Time Stamp Push 2
I
Table 6-64. CPTS0 Signal Descriptions
SIGNAL NAME
CPTS0_RFT_CLK
PIN TYPE
DESCRIPTION
ALV
I
O
O
I
CPTS Reference Clock
D18
CPTS0_TS_COMP
CPTS Time Stamp Counter Compare
CPTS Time Stamp Counter Bit
C13, W1, W7
D14, U1, U7
C18, V1, V7
B19, T1, U13
CPTS0_TS_SYNC
CPTS0_HW1TSPUSH
CPTS0_HW2TSPUSH
CPTS Hardware Time Stamp Push 1
CPTS Hardware Time Stamp Push 2
I
6.3.20 PRU_ICSSG
Note
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in
the device TRM.
6.3.20.1 MAIN Domain
Table 6-65. PRU_ICSSG0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
PRU-ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG0_ECAP0_IN_APWM_OUT
IO
R2, U5
PRG0_ECAP0_SYNC_IN
I
PRU-ICSSG ECAP Sync Input
P5, V5
AA4, V5
C13
PRG0_ECAP0_SYNC_OUT
PRG0_IEP0_EDIO_OUTVALID
O
O
PRU-ICSSG ECAP Sync Output
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRG0_IEP0_EDC_LATCH_IN0
PRG0_IEP0_EDC_LATCH_IN1
PRG0_IEP0_EDC_SYNC_OUT0
PRG0_IEP0_EDC_SYNC_OUT1
PRG0_IEP0_EDIO_DATA_IN_OUT28
PRG0_IEP0_EDIO_DATA_IN_OUT29
I
V1
T1
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
IO
IO
W1
U1
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
W6
AA5
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
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Table 6-65. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRG0_IEP0_EDIO_DATA_IN_OUT30
PRG0_IEP0_EDIO_DATA_IN_OUT31
PRG0_IEP1_EDC_LATCH_IN0
PRG0_IEP1_EDC_LATCH_IN1
PRG0_IEP1_EDC_SYNC_OUT0
PRG0_IEP1_EDC_SYNC_OUT1
IO
Y5
V6
P5
W5
R2
V5
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
IO
I
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRG0_MDIO0_MDC
PRG0_MDIO0_MDIO
PRG0_PRU0_GPI0
PRG0_PRU0_GPI1
PRG0_PRU0_GPI2
PRG0_PRU0_GPI3
PRG0_PRU0_GPI4
PRG0_PRU0_GPI5
PRG0_PRU0_GPI6
PRG0_PRU0_GPI7
PRG0_PRU0_GPI8
PRG0_PRU0_GPI9
PRG0_PRU0_GPI10
PRG0_PRU0_GPI11
PRG0_PRU0_GPI12
PRG0_PRU0_GPI13
PRG0_PRU0_GPI14
PRG0_PRU0_GPI15
PRG0_PRU0_GPI16
PRG0_PRU0_GPI17
PRG0_PRU0_GPI18
PRG0_PRU0_GPI19
PRG0_PRU0_GPO0
PRG0_PRU0_GPO1
PRG0_PRU0_GPO2
PRG0_PRU0_GPO3
PRG0_PRU0_GPO4
PRG0_PRU0_GPO5
PRG0_PRU0_GPO6
PRG0_PRU0_GPO7
PRG0_PRU0_GPO8
PRG0_PRU0_GPO9
PRG0_PRU0_GPO10
PRG0_PRU0_GPO11
PRG0_PRU0_GPO12
O
IO
I
PRU-ICSSG MDIO Clock
P3
P2
PRU-ICSSG MDIO Data
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
Y1
I
R4
U2
V2
I
I
I
AA2
R3
T3
I
I
I
T1
I
T2
I
W6
AA5
Y3
I
I
I
AA3
R6
V4
I
I
I
T5
I
U4
U1
V1
I
I
I
W1
Y1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
R4
U2
V2
AA2
R3
T3
T1
T2
W6
AA5
Y3
AA3
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Table 6-65. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME
PRG0_PRU0_GPO13
PRG0_PRU0_GPO14
PRG0_PRU0_GPO15
PRG0_PRU0_GPO16
PRG0_PRU0_GPO17
PRG0_PRU0_GPO18
PRG0_PRU0_GPO19
PRG0_PRU1_GPI0
PRG0_PRU1_GPI1
PRG0_PRU1_GPI2
PRG0_PRU1_GPI3
PRG0_PRU1_GPI4
PRG0_PRU1_GPI5
PRG0_PRU1_GPI6
PRG0_PRU1_GPI7
PRG0_PRU1_GPI8
PRG0_PRU1_GPI9
PRG0_PRU1_GPI10
PRG0_PRU1_GPI11
PRG0_PRU1_GPI12
PRG0_PRU1_GPI13
PRG0_PRU1_GPI14
PRG0_PRU1_GPI15
PRG0_PRU1_GPI16
PRG0_PRU1_GPI17
PRG0_PRU1_GPI18
PRG0_PRU1_GPI19
PRG0_PRU1_GPO0
PRG0_PRU1_GPO1
PRG0_PRU1_GPO2
PRG0_PRU1_GPO3
PRG0_PRU1_GPO4
PRG0_PRU1_GPO5
PRG0_PRU1_GPO6
PRG0_PRU1_GPO7
PRG0_PRU1_GPO8
PRG0_PRU1_GPO9
PRG0_PRU1_GPO10
PRG0_PRU1_GPO11
PRG0_PRU1_GPO12
PRG0_PRU1_GPO13
PRG0_PRU1_GPO14
PRG0_PRU1_GPO15
PRG0_PRU1_GPO16
PRG0_PRU1_GPO17
PIN TYPE
DESCRIPTION
ALV
IO
IO
IO
IO
IO
IO
IO
I
PRU-ICSSG PRU Data Output
R6
V4
T5
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
U4
U1
V1
W1
Y2
W2
V3
T4
I
I
I
I
W3
P4
R5
W5
R1
Y5
V6
W4
Y4
T6
I
I
I
I
I
I
I
I
I
I
U6
U5
AA4
V5
P5
R2
Y2
W2
V3
T4
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
W3
P4
R5
W5
R1
Y5
V6
W4
Y4
T6
U6
U5
AA4
V5
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Table 6-65. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
P5
PRG0_PRU1_GPO18
PRG0_PRU1_GPO19
PRG0_PWM0_TZ_IN
PRG0_PWM0_TZ_OUT
PRG0_PWM1_TZ_IN
PRG0_PWM1_TZ_OUT
PRG0_PWM2_TZ_IN
PRG0_PWM2_TZ_OUT
PRG0_PWM3_TZ_IN
PRG0_PWM3_TZ_OUT
PRG0_PWM0_A0
IO
IO
I
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Output A
R2
V1
O
I
W1
P5
O
I
R2
T18, V6
R1, U21
P16, W6
R17, Y3
AA3
O
I
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
PRG0_PWM0_A1
PRU_ICSSG PWM Output A
V4
PRG0_PWM0_A2
PRU_ICSSG PWM Output A
U4
PRG0_PWM0_B0
PRU_ICSSG PWM Output B
R6
PRG0_PWM0_B1
PRU_ICSSG PWM Output B
T5
PRG0_PWM0_B2
PRU_ICSSG PWM Output B
U1
PRG0_PWM1_A0
PRU_ICSSG PWM Output A
Y4
PRG0_PWM1_A1
PRU_ICSSG PWM Output A
U6
PRG0_PWM1_A2
PRU_ICSSG PWM Output A
AA4
PRG0_PWM1_B0
PRU_ICSSG PWM Output B
T6
PRG0_PWM1_B1
PRU_ICSSG PWM Output B
U5
PRG0_PWM1_B2
PRU_ICSSG PWM Output B
V5
PRG0_PWM2_A0
PRU_ICSSG PWM Output A
U2, U20
T2, U19
V19, V3
AA2, U18
AA5, V20
T17, W3
V18, Y1
R18, T3
T19, V2
R4, Y21
T1, T21
R3, W19
T3
PRG0_PWM2_A1
PRU_ICSSG PWM Output A
PRG0_PWM2_A2
PRU_ICSSG PWM Output A
PRG0_PWM2_B0
PRU_ICSSG PWM Output B
PRG0_PWM2_B1
PRU_ICSSG PWM Output B
PRG0_PWM2_B2
PRU_ICSSG PWM Output B
PRG0_PWM3_A0
PRU_ICSSG PWM Output A
PRG0_PWM3_A1
PRU_ICSSG PWM Output A
PRG0_PWM3_A2
PRU_ICSSG PWM Output A
PRG0_PWM3_B0
PRU_ICSSG PWM Output B
PRG0_PWM3_B1
PRU_ICSSG PWM Output B
PRG0_PWM3_B2
PRU_ICSSG PWM Output B
PRG0_RGMII1_RXC
PRG0_RGMII1_RX_CTL
PRG0_RGMII1_TXC
PRG0_RGMII1_TX_CTL
PRG0_RGMII2_RXC
PRG0_RGMII2_RX_CTL
PRG0_RGMII2_TXC
PRG0_RGMII2_TX_CTL
PRG0_RGMII1_RD0
PRG0_RGMII1_RD1
PRG0_RGMII1_RD2
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
I
AA2
IO
O
I
U4
T5
R5
I
W3
IO
O
I
AA4
U5
Y1
I
R4
I
U2
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Table 6-65. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME
PRG0_RGMII1_RD3
PRG0_RGMII1_TD0
PRG0_RGMII1_TD1
PRG0_RGMII1_TD2
PRG0_RGMII1_TD3
PRG0_RGMII2_RD0
PRG0_RGMII2_RD1
PRG0_RGMII2_RD2
PRG0_RGMII2_RD3
PRG0_RGMII2_TD0
PRG0_RGMII2_TD1
PRG0_RGMII2_TD2
PRG0_RGMII2_TD3
PRG0_UART0_CTSn
PRG0_UART0_RTSn
PRG0_UART0_RXD
PRG0_UART0_TXD
PIN TYPE
DESCRIPTION
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU-ICSSG UART Clear to Send (active low)
PRU-ICSSG UART Request to Send (active low)
PRU-ICSSG UART Receive Data
PRU-ICSSG UART Transmit Data
ALV
I
V2
Y3
O
O
O
O
I
AA3
R6
V4
Y2
I
W2
V3
I
I
T4
O
O
O
O
I
W4
Y4
T6
U6
W6
AA5
Y5
O
I
O
V6
Table 6-66. PRU_ICSSG1 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
PRU-ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PRG1_ECAP0_IN_APWM_OUT
IO
V12
PRG1_ECAP0_SYNC_IN
I
PRU-ICSSG ECAP Sync Input
Y13
AA14
D14
PRG1_ECAP0_SYNC_OUT
PRG1_IEP0_EDIO_OUTVALID
O
O
PRU-ICSSG ECAP Sync Output
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRG1_IEP0_EDC_LATCH_IN0
PRG1_IEP0_EDC_LATCH_IN1
PRG1_IEP0_EDC_SYNC_OUT0
PRG1_IEP0_EDC_SYNC_OUT1
PRG1_IEP0_EDIO_DATA_IN_OUT28
PRG1_IEP0_EDIO_DATA_IN_OUT29
PRG1_IEP0_EDIO_DATA_IN_OUT30
PRG1_IEP0_EDIO_DATA_IN_OUT31
PRG1_IEP1_EDC_LATCH_IN0
PRG1_IEP1_EDC_LATCH_IN1
PRG1_IEP1_EDC_SYNC_OUT0
I
I
V7
U13
W7
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
O
IO
IO
IO
IO
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
U7
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
U15
U14
V14
W14
Y13
V15
V12
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/
Output
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
PRG1_IEP1_EDC_SYNC_OUT1
PRG1_MDIO0_MDC
O
O
AA14
Y6
PRU-ICSSG MDIO Clock
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Table 6-66. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
AA6
Y7
PRG1_MDIO0_MDIO
PRG1_PRU0_GPI0
PRG1_PRU0_GPI1
PRG1_PRU0_GPI2
PRG1_PRU0_GPI3
PRG1_PRU0_GPI4
PRG1_PRU0_GPI5
PRG1_PRU0_GPI6
PRG1_PRU0_GPI7
PRG1_PRU0_GPI8
PRG1_PRU0_GPI9
PRG1_PRU0_GPI10
PRG1_PRU0_GPI11
PRG1_PRU0_GPI12
PRG1_PRU0_GPI13
PRG1_PRU0_GPI14
PRG1_PRU0_GPI15
PRG1_PRU0_GPI16
PRG1_PRU0_GPI17
PRG1_PRU0_GPI18
PRG1_PRU0_GPI19
PRG1_PRU0_GPO0
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO6
PRG1_PRU0_GPO7
PRG1_PRU0_GPO8
PRG1_PRU0_GPO9
PRG1_PRU0_GPO10
PRG1_PRU0_GPO11
PRG1_PRU0_GPO12
PRG1_PRU0_GPO13
PRG1_PRU0_GPO14
PRG1_PRU0_GPO15
PRG1_PRU0_GPO16
PRG1_PRU0_GPO17
PRG1_PRU0_GPO18
PRG1_PRU0_GPO19
PRG1_PRU1_GPI0
PRG1_PRU1_GPI1
PRG1_PRU1_GPI2
PRG1_PRU1_GPI3
IO
I
PRU-ICSSG MDIO Data
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
I
U8
I
W8
V8
I
I
Y8
I
V13
AA7
U13
W13
U15
U14
AA8
U9
I
I
I
I
I
I
I
I
W9
AA9
Y9
I
I
I
V9
I
U7
I
V7
I
W7
Y7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
U8
W8
V8
Y8
V13
AA7
U13
W13
U15
U14
AA8
U9
W9
AA9
Y9
V9
U7
V7
W7
W11
V11
AA12
Y12
I
I
I
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Table 6-66. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME
PRG1_PRU1_GPI4
PRG1_PRU1_GPI5
PRG1_PRU1_GPI6
PRG1_PRU1_GPI7
PRG1_PRU1_GPI8
PRG1_PRU1_GPI9
PRG1_PRU1_GPI10
PRG1_PRU1_GPI11
PRG1_PRU1_GPI12
PRG1_PRU1_GPI13
PRG1_PRU1_GPI14
PRG1_PRU1_GPI15
PRG1_PRU1_GPI16
PRG1_PRU1_GPI17
PRG1_PRU1_GPI18
PRG1_PRU1_GPI19
PRG1_PRU1_GPO0
PRG1_PRU1_GPO1
PRG1_PRU1_GPO2
PRG1_PRU1_GPO3
PRG1_PRU1_GPO4
PRG1_PRU1_GPO5
PRG1_PRU1_GPO6
PRG1_PRU1_GPO7
PRG1_PRU1_GPO8
PRG1_PRU1_GPO9
PRG1_PRU1_GPO10
PRG1_PRU1_GPO11
PRG1_PRU1_GPO12
PRG1_PRU1_GPO13
PRG1_PRU1_GPO14
PRG1_PRU1_GPO15
PRG1_PRU1_GPO16
PRG1_PRU1_GPO17
PRG1_PRU1_GPO18
PRG1_PRU1_GPO19
PRG1_PWM0_TZ_IN
PRG1_PWM0_TZ_OUT
PRG1_PWM1_TZ_IN
PRG1_PWM1_TZ_OUT
PRG1_PWM2_TZ_IN
PRG1_PWM2_TZ_OUT
PRG1_PWM3_TZ_IN
PRG1_PWM3_TZ_OUT
PRG1_PWM0_A0
PIN TYPE
DESCRIPTION
ALV
I
I
PRU-ICSSG PRU Data Input
W12
AA13
U11
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Input
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU-ICSSG PRU Data Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Trip Zone Input
PRU_ICSSG PWM Trip Zone Output
PRU_ICSSG PWM Output A
I
I
V15
I
U12
I
V14
I
W14
AA10
V10
I
I
I
U10
I
AA11
Y11
I
I
Y10
I
AA14
Y13
I
I
V12
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
W11
V11
AA12
Y12
W12
AA13
U11
V15
U12
V14
W14
AA10
V10
U10
AA11
Y11
Y10
AA14
Y13
V12
V7
O
I
W7
Y13
O
I
V12
P19, W14
R20, U12
U15
O
I
O
IO
AA8
U9
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Table 6-66. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
AA9
V9
PRG1_PWM0_A1
PRG1_PWM0_A2
PRG1_PWM0_B0
PRG1_PWM0_B1
PRG1_PWM0_B2
PRG1_PWM1_A0
PRG1_PWM1_A1
PRG1_PWM1_A2
PRG1_PWM1_B0
PRG1_PWM1_B1
PRG1_PWM1_B2
PRG1_PWM2_A0
PRG1_PWM2_A1
PRG1_PWM2_A2
PRG1_PWM2_B0
PRG1_PWM2_B1
PRG1_PWM2_B2
PRG1_PWM3_A0
PRG1_PWM3_A1
PRG1_PWM3_A2
PRG1_PWM3_B0
PRG1_PWM3_B1
PRG1_PWM3_B2
PRG1_RGMII1_RXC
PRG1_RGMII1_RX_CTL
PRG1_RGMII1_TXC
PRG1_RGMII1_TX_CTL
PRG1_RGMII2_RXC
PRG1_RGMII2_RX_CTL
PRG1_RGMII2_TXC
PRG1_RGMII2_TX_CTL
PRG1_RGMII1_RD0
PRG1_RGMII1_RD1
PRG1_RGMII1_RD2
PRG1_RGMII1_RD3
PRG1_RGMII1_TD0
PRG1_RGMII1_TD1
PRG1_RGMII1_TD2
PRG1_RGMII1_TD3
PRG1_RGMII2_RD0
PRG1_RGMII2_RD1
PRG1_RGMII2_RD2
PRG1_RGMII2_RD3
PRG1_RGMII2_TD0
PRG1_RGMII2_TD1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
W9
PRU_ICSSG PWM Output B
Y9
PRU_ICSSG PWM Output B
U7
PRU_ICSSG PWM Output A
V10
PRU_ICSSG PWM Output A
AA11
Y10
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
U10
PRU_ICSSG PWM Output B
Y11
PRU_ICSSG PWM Output B
AA14
N16, W8
P17, W13
AA12, V21
N17, Y8
U14, Y18
R16, W12
Y7
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output B
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output A
AA7
V8
PRU_ICSSG PWM Output A
PRU_ICSSG PWM Output B
U8
PRU_ICSSG PWM Output B
U13
PRU_ICSSG PWM Output B
V13
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Clock
PRU_ICSSG RGMII Receive Control
PRU_ICSSG RGMII Transmit Clock
PRU_ICSSG RGMII Transmit Control
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Receive Data
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
AA7
Y8
I
IO
O
I
V9
Y9
U11
I
W12
Y10
IO
O
I
Y11
Y7
I
U8
I
W8
I
V8
O
O
O
O
I
AA8
U9
W9
AA9
W11
V11
I
I
AA12
Y12
I
O
O
AA10
V10
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Table 6-66. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME
PRG1_RGMII2_TD2
PRG1_RGMII2_TD3
PRG1_UART0_CTSn
PRG1_UART0_RTSn
PRG1_UART0_RXD
PRG1_UART0_TXD
PIN TYPE
DESCRIPTION
PRU_ICSSG RGMII Transmit Data
PRU_ICSSG RGMII Transmit Data
PRU-ICSSG UART Clear to Send (active low)
PRU-ICSSG UART Request to Send (active low)
PRU-ICSSG UART Receive Data
ALV
O
O
I
U10
AA11
U15
U14
V14
O
I
O
PRU-ICSSG UART Transmit Data
W14
6.3.21 DMTIMER
6.3.21.1 MAIN Domain
Table 6-67. DMTIMER Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO0
IO
C18, K18
Timer Inputs and Outputs (not tied to single timer
instance)
TIMER_IO1
TIMER_IO2
TIMER_IO3
TIMER_IO4
TIMER_IO5
TIMER_IO6
TIMER_IO7
TIMER_IO8
TIMER_IO9
TIMER_IO10
TIMER_IO11
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B19, K19
A17, L21
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
B17, K21
C17, L20
D17, J19
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
B16, D19, T1
A16, C20, U7
P19, V7
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
R21, W7
Timer Inputs and Outputs (not tied to single timer
instance)
C13, U13
D14, U1
Timer Inputs and Outputs (not tied to single timer
instance)
6.3.21.2 MCU Domain
Table 6-68. MCU_DMTIMER Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
Timer Inputs and Outputs (not tied to single timer
instance)
MCU_TIMER_IO0
IO
D8
Timer Inputs and Outputs (not tied to single timer
instance)
MCU_TIMER_IO1
MCU_TIMER_IO2
MCU_TIMER_IO3
IO
IO
IO
E8
B8
B9
Timer Inputs and Outputs (not tied to single timer
instance)
Timer Inputs and Outputs (not tied to single timer
instance)
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6.3.22 Emulation and Debug
6.3.22.1 MAIN Domain
Table 6-69. Trace Signal Descriptions
SIGNAL NAME
TRC_CLK
PIN TYPE
DESCRIPTION
ALV
T20
U21
T18
U20
U18
U19
V20
V21
V19
T17
R16
W20
W21
V18
Y21
Y20
R17
P16
R18
T21
P17
T19
W19
Y18
N16
R19
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Trace Clock
TRC_CTL
Trace Control
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
Trace Data 4
Trace Data 5
Trace Data 6
Trace Data 7
Trace Data 8
Trace Data 9
Trace Data 10
Trace Data 11
Trace Data 12
Trace Data 13
Trace Data 14
Trace Data 15
Trace Data 16
Trace Data 17
Trace Data 18
Trace Data 19
Trace Data 20
Trace Data 21
Trace Data 22
Trace Data 23
TRC_DATA0
TRC_DATA1
TRC_DATA2
TRC_DATA3
TRC_DATA4
TRC_DATA5
TRC_DATA6
TRC_DATA7
TRC_DATA8
TRC_DATA9
TRC_DATA10
TRC_DATA11
TRC_DATA12
TRC_DATA13
TRC_DATA14
TRC_DATA15
TRC_DATA16
TRC_DATA17
TRC_DATA18
TRC_DATA19
TRC_DATA20
TRC_DATA21
TRC_DATA22
TRC_DATA23
6.3.22.2 MCU Domain
Table 6-70. JTAG Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
D10
E10
B11
C11
A12
C12
D11
EMU0
EMU1
TCK
IO
Emulation Control 0
Emulation Control 1
IO
I
JTAG Test Clock Input
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Reset
TDI
I
TDO
OZ
TMS
I
I
TRSTn
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6.3.23 System and Miscellaneous
6.3.23.1 Boot Mode Configuration
6.3.23.1.1 MAIN Domain
Table 6-71. Sysboot Signal Descriptions
SIGNAL NAME
BOOTMODE00
BOOTMODE01
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
BOOTMODE08
BOOTMODE09
BOOTMODE10
BOOTMODE11
BOOTMODE12
BOOTMODE13
BOOTMODE14
BOOTMODE15
PIN TYPE
DESCRIPTION
ALV
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Bootmode pin 0
Bootmode pin 1
Bootmode pin 2
Bootmode pin 3
Bootmode pin 4
Bootmode pin 5
Bootmode pin 6
Bootmode pin 7
Bootmode pin 8
Bootmode pin 9
Bootmode pin 10
Bootmode pin 11
Bootmode pin 12
Bootmode pin 13
Bootmode pin 14
Bootmode pin 15
T20
U21
T18
U20
U18
U19
V20
V21
V19
T17
R16
W20
W21
V18
Y21
Y20
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6.3.23.2 Clock
6.3.23.2.1 MCU Domain
Table 6-72. MCU Clock Signal Descriptions
SIGNAL NAME
MCU_OSC0_XI
PIN TYPE
DESCRIPTION
High frequency oscillator input
High frequency oscillator output
ALV
C21
B20
I
MCU_OSC0_XO
O
6.3.23.3 System
6.3.23.3.1 MAIN Domain
Table 6-73. System Signal Descriptions
SIGNAL NAME
CLKOUT0
PIN TYPE
DESCRIPTION
ALV
RMII Clock Output (50 MHz). This pin is used for clock
source to the external PHY and must be routed back to
the RMII_REF_CLK pin for proper device operation.
O
I
A19, U13
C19
EXTINTn
External Interrupt
External clock input to Main Domain, routed to Timer
clock muxes as one of the selectable input clock sources
for Timer/WDT modules, or as reference clock to
MAIN_PLL2 (PER1 PLL)
EXT_REFCLK1
I
A19
GPMC functional clock output selected through a mux
logic
GPMC0_FCLK_MUX
OBSCLK0
O
O
R17
D17
Observation clock output for test and debug purposes
only
PORz_OUT
O
O
I
Main Domain POR status output
E17
F16
E18
D18
A19
A17
B17
RESETSTATz
RESET_REQz
SYNC0_OUT
SYNC1_OUT
SYNC2_OUT
SYNC3_OUT
Main Domain warm reset status output
Main Domain external warm reset request input
CPTS Time Stamp Generator Bit 0
CPTS Time Stamp Generator Bit 1
CPTS Time Stamp Generator Bit 2
CPTS Time Stamp Generator Bit 3
O
O
O
O
SYSCLK0 output from Main PLL controller (divided by 6)
for test and debug purposes only
SYSCLKOUT0
O
C17
6.3.23.3.2 MCU Domain
Table 6-74. MCU System Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
MCU_EXT_REFCLK0
I
External system clock input
B7
Observation clock output for test and debug purposes
only
MCU_OBSCLK0
O
C6, E10
MCU_PORz
I
O
I
MCU Domain cold reset
B21
B13
B12
A20
MCU_RESETSTATz
MCU_RESETz
MCU Domain warm reset status output
MCU Domain warm reset
MCU_SAFETY_ERRORn
IO
Error signal output from MCU Domain ESM
MCU Domain system clock output for test and debug
purposes only
MCU_SYSCLKOUT0
O
C6
6.3.23.4 VMON
Table 6-75. VMON Signal Description
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
VMON_1P8_MCU
PWR
Voltage monitor for 1.8 V MCU power supply
K16
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Table 6-75. VMON Signal Description (continued)
SIGNAL NAME
VMON_1P8_SOC
PIN TYPE
DESCRIPTION
ALV
PWR
Voltage monitor for 1.8 V SoC power supply
Voltage monitor for 3.3 V MCU power supply
Voltage monitor for 3.3 V SoC power supply
E12
F13
F14
VMON_3P3_MCU
PWR
VMON_3P3_SOC
PWR
Voltage Monitor, fixed 0.45 V (+/-3%) threshold. Use with
external precision voltage divider to monitor a higher
voltage rail such as the PMIC input supply.
VMON_VSYS
PWR
K10
6.3.24 Power Supply
Table 6-76. Power Supply Signal Description
SIGNAL NAME
CAP_VDDS0(1)
CAP_VDDS1(1)
CAP_VDDS2(1)
CAP_VDDS3(1)
CAP_VDDS4(1)
CAP_VDDS5(1)
CAP_VDDSHV_MMC1(2)
CAP_VDDS_MCU(1)
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_0P85_USB0
VDDA_1P8_SERDES0
VDDA_1P8_USB0
VDDA_3P3_SDIO
VDDA_3P3_USB0
VDDA_ADC
PIN TYPE
DESCRIPTION
External capacitor connection for IO group 0
External capacitor connection for IO group 1
External capacitor connection for IO group 2
External capacitor connection for IO group 3
External capacitor connection for IO group 4
External capacitor connection for IO group 5
External capacitor connection for MMC1
External capacitor connection for IO MCU
SERDES0 0.85 V analog supply
SERDES0 clock 0.85 V analog supply
USB0 0.85 V analog supply
ALV
H12
CAP
CAP
T7
CAP
R11
CAP
N14
CAP
M16
CAP
L13
CAP
K15
CAP
H10
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
P12, P13
P11
T12
SERDES0 1.8 V analog supply
USB0 1.8 V analog supply
R14
R15
SDIO 3.3 V analog supply
H15
USB0 3.3 V analog supply
R13
ADC0 analog supply
J13
VDDA_MCU
POR and MCU PLL analog supply
Main, PER1, and R5F PLL analog supply
ARM and DDR PLL analog supply
PER0 PLL analog supply
K12
VDDA_PLL0
N12
VDDA_PLL1
H9
VDDA_PLL2
J11
VDDA_TEMP0
VDDA_TEMP1
VDDR_CORE
TEMP0 analog supply
G11
TEMP1 analog supply
L11
RAM supply
L10, M13
F11, G12, G14
M7, N6, P7
R10, R8, T9
P14, P15
M14, M15
L14, L15
F9, G10, G8
VDDSHV0
IO supply for IO group 0
VDDSHV1
IO supply for IO group 1
VDDSHV2
IO supply for IO group 2
VDDSHV3
IO supply for IO group 3
VDDSHV4
IO supply for IO group 4
VDDSHV5
IO supply for IO group 5
VDDSHV_MCU
IO supply for IO MCU
F7, G6, H7, J6, K7,
L6
VDDS_DDR
PWR
DDR PHY IO supply
VDDS_DDR_C
VDDS_MMC0
VDDS_OSC
PWR
PWR
PWR
DDR clock IO supply
MMC0 PHY IO supply
MCU_OSC0 supply
J8
J15, K14
H13
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Table 6-76. Power Supply Signal Description (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALV
J10, J12, K11, K9,
L12, L8, M11, M9,
N10, N8, P9
VDD_CORE
PWR
Core supply
VDD_DLL_MMC0
VDD_MMC0
VPP
PWR
PWR
PWR
MMC0 PLL analog supply
MMC0 PHY core supply
H14
K13
G15
eFuse ROM programming supply
A1, A21, A5, A6, AA1,
AA15, AA18, AA21,
C10, C15, C3, D1,
E11, E13, F10, F15,
F8, G1, G16, G3, G7,
G9, H11, H20, H21,
H6, H8, J14, J16, J7,
J9, K6, K8, L1, L16,
L3, L7, L9, M10, M12,
M6, M8, N11, N13,
N15, N7, N9, P1,
VSS
PWR
Ground
P10, P18, P6, P8,
R12, R7, R9, T10,
T11, T15, T16, T8,
U3, V17, W10, W18,
Y14, Y17, Y19
(1) This pin must always be connected via a 1-μF capacitor to VSS.
(2) This pin must always be connected via a 3.3-μF ±20% capacitor to VSS.
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6.4 Pin Multiplexing
Note
Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins.
Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are
associated with peripheral logic functions.
Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad
Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device
TRM for information associated with peripheral signal multiplexing.
Note
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
Note
Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the
device TRM.
Note
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal
wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.
For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM.
Table 6-77. Pin Multiplexing (ALV Package)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0x000F4000
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
PADCONFIG N20
_0
OSPI0_CLK
GPIO0_0
0x000F4004
0x000F4008
0x000F400C
0x000F4010
0x000F4014
0x000F4018
PADCONFIG N21
_1
OSPI0_LBCL
KO
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_5
GPIO0_6
PADCONFIG N19
_2
OSPI0_DQS
OSPI0_D0
OSPI0_D1
OSPI0_D2
OSPI0_D3
PADCONFIG M19
_3
PADCONFIG M18
_4
PADCONFIG M20
_5
PADCONFIG M21
_6
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F401C
PADCONFIG P21
_7
OSPI0_D4
GPIO0_7
0x000F4020
0x000F4024
0x000F4028
0x000F402C
0x000F4030
0x000F4034
0x000F4038
0x000F403C
0x000F4040
0x000F4044
0x000F4048
0x000F404C
0x000F4050
0x000F4054
0x000F4058
0x000F405C
0x000F4060
0x000F4064
0x000F4068
0x000F406C
0x000F4070
0x000F4074
0x000F4078
PADCONFIG P20
_8
OSPI0_D5
GPIO0_8
PADCONFIG N18
_9
OSPI0_D6
GPIO0_9
PADCONFIG M17
_10
OSPI0_D7
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
PADCONFIG L19
_11
OSPI0_CSn0
OSPI0_CSn1
OSPI0_CSn2
PADCONFIG L18
_12
PADCONFIG K17
_13
OSPI0_RES
ET_OUT1
PADCONFIG L17
_14
OSPI0_CSn3 OSPI0_RES OSPI0_ECC
ET_OUT0 _FAIL
PADCONFIG T20
_15
GPMC0_AD0 FSI_RX2_CL UART2_RXD EHRPWM0_
SYNCI
TRC_CLK
TRC_CTL
BOOTMODE
00
K
PADCONFIG U21
_16
GPMC0_AD1 FSI_RX2_D0 UART2_TXD EHRPWM0_
SYNCO
PRG0_PWM
2_TZ_OUT
BOOTMODE
01
PADCONFIG T18
_17
GPMC0_AD2 FSI_RX2_D1 UART2_RTS EHRPWM_T
TRC_DATA0 GPIO0_17
TRC_DATA1 GPIO0_18
TRC_DATA2 GPIO0_82
TRC_DATA3 GPIO0_83
TRC_DATA4 GPIO0_21
TRC_DATA5 GPIO0_22
TRC_DATA6 GPIO0_23
TRC_DATA7 GPIO0_24
TRC_DATA8 GPIO0_25
TRC_DATA9 GPIO0_26
PRG0_PWM
2_TZ_IN
BOOTMODE
02
n
Zn_IN0
PADCONFIG U20
_18
GPMC0_AD3 FSI_RX3_CL UART3_RXD EHRPWM0_
PRG0_PWM
2_A0
BOOTMODE
03
K
A
PADCONFIG U18
_19
GPMC0_AD4 FSI_RX3_D0 UART3_TXD EHRPWM0_
B
PRG0_PWM
2_B0
BOOTMODE
04
PADCONFIG U19
_20
GPMC0_AD5 FSI_RX3_D1 UART3_RTS EHRPWM1_
PRG0_PWM
2_A1
BOOTMODE
05
n
A
PADCONFIG V20
_21
GPMC0_AD6 FSI_RX4_D0 UART4_RXD EHRPWM1_
B
PRG0_PWM
2_B1
BOOTMODE
06
PADCONFIG V21
_22
GPMC0_AD7 FSI_RX4_D1 UART4_TXD EHRPWM_T EHRPWM8_
PRG1_PWM
2_A2
BOOTMODE
07
Zn_IN1
A
PADCONFIG V19
_23
GPMC0_AD8 FSI_RX0_CL UART2_CTS EHRPWM2_
PRG0_PWM
2_A2
BOOTMODE
08
K
n
A
PADCONFIG T17
_24
GPMC0_AD9 FSI_RX0_D0 UART3_CTS EHRPWM2_
PRG0_PWM
2_B2
BOOTMODE
09
n
B
PADCONFIG R16
_25
GPMC0_AD1 FSI_RX0_D1 UART4_CTS EHRPWM_T EHRPWM8_
Zn_IN2
PRG1_PWM
2_B2
BOOTMODE
10
0
n
B
PADCONFIG W20
_26
GPMC0_AD1 FSI_RX1_CL UART5_CTS EQEP1_A
1
EHRPWM7_
A
BOOTMODE
11
K
n
PADCONFIG W21
_27
GPMC0_AD1 FSI_RX1_D0 UART6_CTS EQEP1_B
2
TRC_DATA1 GPIO0_27
0
EHRPWM7_
B
BOOTMODE
12
n
PADCONFIG V18
_28
GPMC0_AD1 FSI_RX1_D1
3
EHRPWM3_
A
TRC_DATA1 GPIO0_28
1
PRG0_PWM
3_A0
BOOTMODE
13
PADCONFIG Y21
_29
GPMC0_AD1 FSI_TX0_D0 UART6_RXD EHRPWM3_
4
TRC_DATA1 GPIO0_29
2
PRG0_PWM
3_B0
BOOTMODE
14
B
PADCONFIG Y20
_30
GPMC0_AD1 FSI_TX0_D1 UART6_TXD EHRPWM3_
SYNCI
TRC_DATA1 GPIO0_30
3
BOOTMODE
15
5
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
ADDRESS
BALL
NUMBER
NAME
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F407C
0x000F4084
0x000F4088
0x000F408C
0x000F4090
0x000F4094
0x000F4098
0x000F409C
0x000F40A0
0x000F40A4
0x000F40A8
0x000F40AC
0x000F40B0
0x000F40B4
0x000F40B8
0x000F40BC
0x000F40C0
0x000F40C4
0x000F40C8
0x000F40CC
0x000F40D0
0x000F40D4
PADCONFIG R17
_31
GPMC0_CLK FSI_RX4_CL UART4_RTS EHRPWM3_ GPMC0_FCL
SYNCO K_MUX
TRC_DATA1 GPIO0_31
4
PRG0_PWM
3_TZ_OUT
K
n
PADCONFIG P16
_33
GPMC0_AD FSI_RX5_CL UART5_RXD EHRPWM_T
Vn_ALE Zn_IN3
TRC_DATA1 GPIO0_32
5
PRG0_PWM
3_TZ_IN
K
PADCONFIG R18
_34
GPMC0_OEn FSI_RX5_D0 UART5_TXD EHRPWM4_
_REn
TRC_DATA1 GPIO0_33
6
PRG0_PWM
3_A1
A
PADCONFIG T21
_35
GPMC0_WE FSI_RX5_D1 UART5_RTS EHRPWM4_
TRC_DATA1 GPIO0_34
7
PRG0_PWM
3_B1
n
n
B
PADCONFIG P17
_36
GPMC0_BE0 FSI_TX1_D0 UART6_RTS EHRPWM_T
EHRPWM7_ TRC_DATA1 GPIO0_35
PRG1_PWM
2_A1
n_CLE
n
Zn_IN4
A
8
PADCONFIG T19
_37
GPMC0_BE1 FSI_TX0_CL
EHRPWM5_
A
TRC_DATA1 GPIO0_36
9
PRG0_PWM
3_A2
n
K
PADCONFIG W19
_38
GPMC0_WAI
T0
EHRPWM5_
B
TRC_DATA2 GPIO0_37
0
PRG0_PWM
3_B2
PADCONFIG Y18
_39
GPMC0_WAI FSI_TX1_D1
T1
EHRPWM_T GPMC0_A21 EHRPWM7_ TRC_DATA2 GPIO0_38
Zn_IN5
PRG1_PWM
2_B1
B
1
PADCONFIG N16
_40
GPMC0_WP FSI_TX1_CL
EQEP0_A
GPMC0_A22
TRC_DATA2 GPIO0_39
2
EHRPWM6_ PRG1_PWM
A 2_A0
n
K
PADCONFIG N17
_41
GPMC0_DIR
EQEP0_B
EQEP0_S
EQEP0_I
EQEP1_S
EQEP1_I
GPIO0_40
EHRPWM6_ PRG1_PWM
B
2_B0
PADCONFIG R19
_42
GPMC0_CSn
0
TRC_DATA2 GPIO0_41
3
EHRPWM6_
SYNCI
PADCONFIG R20
_43
GPMC0_CSn
1
EHRPWM_T
Zn_IN2
GPIO0_42
EHRPWM6_ PRG1_PWM
SYNCO
2_TZ_OUT
PADCONFIG P19
_44
GPMC0_CSn I2C2_SCL
2
TIMER_IO8
TIMER_IO9
EHRPWM_T
Zn_IN4
GPIO0_43
PRG1_PWM
2_TZ_IN
PADCONFIG R21
_45
GPMC0_CSn I2C2_SDA
3
GPMC0_A20 EHRPWM_T
Zn_IN5
GPIO0_44
PADCONFIG Y7
_46
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO0 _GPI0 I1_RD0 3_A0
GPIO0_45
GPMC0_AD1
6
PADCONFIG U8
_47
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO1 _GPI1 I1_RD1 3_B0
GPIO0_46
GPMC0_AD1
7
PADCONFIG W8
_48
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO2 _GPI2 I1_RD2 2_A0
GPIO0_47
GPMC0_AD1
8
PADCONFIG V8
_49
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO3 _GPI3 I1_RD3 3_A2
GPIO0_48
GPMC0_AD1
9
PADCONFIG Y8
_50
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO4 _GPI4 I1_RX_CTL 2_B0
GPIO0_49
GPMC0_AD2
0
PADCONFIG V13
_51
PRG1_PRU0 PRG1_PRU0
PRG1_PWM RGMII1_RX_
GPIO0_50
GPMC0_AD2
1
_GPO5 _GPI5 3_B2 CTL
PADCONFIG AA7
_52
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO6 _GPI6 I1_RXC 3_A1
GPIO0_51
GPMC0_AD2
2
PADCONFIG U13
_53
PRG1_PRU0 PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_HW2 CLKOUT0
TIMER_IO10 GPIO0_52
GPMC0_AD2
3
_GPO7
_GPI7
EDC_LATCH 3_B1
_IN1
TSPUSH
0x000F40D8
PADCONFIG W13
_54
PRG1_PRU0 PRG1_PRU0
_GPO8 _GPI8
PRG1_PWM RGMII1_RXC
2_A1
GPIO0_53
GPMC0_AD2
4
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F40DC
PADCONFIG U15
_55
PRG1_PRU0 PRG1_PRU0 PRG1_UART PRG1_PWM RGMII1_TX_ RMII1_RX_E PRG1_IEP0_ GPIO0_54
GPMC0_AD2
5
_GPO9
_GPI9
0_CTSn
3_TZ_IN
CTL
R
EDIO_DATA_
IN_OUT28
0x000F40E0
PADCONFIG U14
_56
PRG1_PRU0 PRG1_PRU0 PRG1_UART PRG1_PWM RGMII1_TXC RMII_REF_C PRG1_IEP0_ GPIO0_55
GPMC0_AD2
6
_GPO10
_GPI10
0_RTSn
2_B1
LK
EDIO_DATA_
IN_OUT29
0x000F40E4
0x000F40E8
0x000F40EC
0x000F40F0
0x000F40F4
0x000F40F8
0x000F40FC
PADCONFIG AA8
_57
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO11 _GPI11 I1_TD0 3_TZ_OUT
GPIO0_56
GPIO0_57
GPIO0_58
GPIO0_59
GPIO0_60
GPIO0_61
GPIO0_62
GPMC0_AD2
7
PADCONFIG U9
_58
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO12 _GPI12 I1_TD1 0_A0
GPMC0_AD2
8
PADCONFIG W9
_59
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO13 _GPI13 I1_TD2 0_B0
GPMC0_AD2
9
PADCONFIG AA9
_60
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO14 _GPI14 I1_TD3 0_A1
GPMC0_AD3
0
PADCONFIG Y9
_61
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO15 _GPI15 I1_TX_CTL 0_B1
GPMC0_AD3
1
PADCONFIG V9
_62
PRG1_PRU0 PRG1_PRU0 PRG1_RGMI PRG1_PWM
_GPO16 _GPI16 I1_TXC 0_A2
GPMC0_BE2
n
PADCONFIG U7
_63
PRG1_PRU0 PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_TS_
TIMER_IO7
TIMER_IO8
TIMER_IO9
GPMC0_A0
GPMC0_A1
GPMC0_A2
_GPO17
_GPI17
EDC_SYNC_ 0_B2
OUT1
SYNC
0x000F4100
0x000F4104
PADCONFIG V7
_64
PRG1_PRU0 PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_HW1
GPIO0_63
GPIO0_64
_GPO18
_GPI18
EDC_LATCH 0_TZ_IN
_IN0
TSPUSH
PADCONFIG W7
_65
PRG1_PRU0 PRG1_PRU0 PRG1_IEP0_ PRG1_PWM CPTS0_TS_
_GPO19
_GPI19
EDC_SYNC_ 0_TZ_OUT
OUT0
COMP
0x000F4108
0x000F410C
0x000F4110
0x000F4114
0x000F4118
0x000F411C
0x000F4120
0x000F4124
PADCONFIG W11
_66
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI
_GPO0 _GPI0 I2_RD0
RGMII2_RD0 RMII2_RXD0
RGMII2_RD1 RMII2_RXD1
GPIO0_65
GPIO0_66
GPIO0_67
GPIO0_68
GPIO0_69
GPIO0_70
GPIO0_71
GPIO0_72
GPMC0_A3
GPMC0_A4
GPMC0_A5
GPMC0_A6
GPMC0_A7
GPMC0_A8
GPMC0_A9
GPMC0_A10
PADCONFIG V11
_67
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI
_GPO1 _GPI1 I2_RD1
PADCONFIG AA12
_68
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_RD2
_GPO2 _GPI2 I2_RD2 2_A2
PADCONFIG Y12
_69
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI
_GPO3 _GPI3 I2_RD3
RGMII2_RD3
PADCONFIG W12
_70
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_RX_ RMII2_RX_E
_GPO4
_GPI4
I2_RX_CTL
2_B2
CTL
R
PADCONFIG AA13
_71
PRG1_PRU1 PRG1_PRU1
_GPO5 _GPI5
RGMII1_RD0
PADCONFIG U11
_72
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI
_GPO6 _GPI6 I2_RXC
RGMII2_RXC
PADCONFIG V15
_73
PRG1_PRU1 PRG1_PRU1 PRG1_IEP1_
RGMII1_TD0 RMII1_RXD0 SPI3_CS3
_GPO7
_GPI7
EDC_LATCH
_IN1
0x000F4128
0x000F412C
PADCONFIG U12
_74
PRG1_PRU1 PRG1_PRU1
_GPO8 _GPI8
PRG1_PWM RGMII1_RD1
2_TZ_OUT
GPIO0_73
GPMC0_A11
GPMC0_A12
PADCONFIG V14
_75
PRG1_PRU1 PRG1_PRU1 PRG1_UART
_GPO9 _GPI9 0_RXD
RGMII1_TD1 RMII1_RXD1 PRG1_IEP0_ GPIO0_74
EDIO_DATA_
IN_OUT30
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
ADDRESS
BALL
NUMBER
NAME
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F4130
PADCONFIG W14
PRG1_PRU1 PRG1_PRU1 PRG1_UART PRG1_PWM RGMII1_TD2 RMII1_TXD0 PRG1_IEP0_ GPIO0_75
GPMC0_A13
_76
_GPO10
_GPI10
0_TXD
2_TZ_IN
EDIO_DATA_
IN_OUT31
0x000F4134
0x000F4138
0x000F413C
0x000F4140
0x000F4144
0x000F4148
0x000F414C
PADCONFIG AA10
_77
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI
_GPO11 _GPI11 I2_TD0
RGMII2_TD0 RMII2_TXD0
GPIO0_76
GPIO0_77
GPIO0_78
GPIO0_79
GPIO0_80
GPIO0_81
GPIO0_19
GPMC0_A14
GPMC0_A15
GPMC0_A16
GPMC0_A17
GPMC0_A18
GPMC0_A19
PADCONFIG V10
_78
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_TD1 RMII2_TXD1
_GPO12 _GPI12 I2_TD1 1_A0
PADCONFIG U10
_79
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_TD2 RMII2_CRS_
_GPO13 _GPI13 I2_TD2 1_B0 DV
PADCONFIG AA11
_80
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_TD3
_GPO14 _GPI14 I2_TD3 1_A1
PADCONFIG Y11
_81
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_TX_ RMII2_TX_E
_GPO15 _GPI15 I2_TX_CTL 1_B1 CTL
N
PADCONFIG Y10
_82
PRG1_PRU1 PRG1_PRU1 PRG1_RGMI PRG1_PWM RGMII2_TXC
_GPO16 _GPI16 I2_TXC 1_A2
PADCONFIG AA14
_83
PRG1_PRU1 PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_TD3 RMII1_TXD1
GPMC0_BE3 PRG1_ECAP
n
_GPO17
_GPI17
EDC_SYNC_ 1_B2
OUT1
0_SYNC_OU
T
0x000F4150
0x000F4154
PADCONFIG Y13
_84
PRG1_PRU1 PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_RD2 RMII1_TX_E
GPIO0_20
GPIO0_84
UART5_CTS PRG1_ECAP
n 0_SYNC_IN
_GPO18
_GPI18
EDC_LATCH 1_TZ_IN
_IN0
N
PADCONFIG V12
_85
PRG1_PRU1 PRG1_PRU1 PRG1_IEP1_ PRG1_PWM RGMII1_RD3 RMII1_CRS_ SPI3_CS2
UART5_RTS PRG1_ECAP
_GPO19
_GPI19
EDC_SYNC_ 1_TZ_OUT
OUT0
DV
n
0_IN_APWM
_OUT
0x000F4158
0x000F415C
0x000F4160
0x000F4164
0x000F4168
0x000F416C
0x000F4170
0x000F4174
0x000F4178
0x000F417C
PADCONFIG AA6
_86
PRG1_MDIO
0_MDIO
MDIO0_MDI
O
GPIO0_85
GPIO0_86
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
PADCONFIG Y6
_87
PRG1_MDIO
0_MDC
MDIO0_MDC
PADCONFIG Y1
_88
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO0 _GPI0 I1_RD0 3_A0
UART2_CTS
n
PADCONFIG R4
_89
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO1 _GPI1 I1_RD1 3_B0
UART2_TXD
PADCONFIG U2
_90
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO2 _GPI2 I1_RD2 2_A0
GPMC0_A0
GPMC0_A1
UART2_RTS
n
PADCONFIG V2
_91
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO3 _GPI3 I1_RD3 3_A2
UART3_CTS
n
PADCONFIG AA2
_92
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO4
UART3_TXD
_GPI4
I1_RX_CTL
2_B0
PADCONFIG R3
_93
PRG0_PRU0 PRG0_PRU0
_GPO5 _GPI5
PRG0_PWM
3_B2
UART3_RTS
n
PADCONFIG T3
_94
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO6 _GPI6 I1_RXC 3_A1
UART4_CTS
n
PADCONFIG T1
_95
PRG0_PRU0 PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_HW2 CP_GEMAC TIMER_IO6
_GPO7
UART4_TXD
_GPI7
EDC_LATCH 3_B1
_IN1
TSPUSH
_CPTS0_HW
2TSPUSH
0x000F4180
PADCONFIG T2
_96
PRG0_PRU0 PRG0_PRU0
_GPO8 _GPI8
PRG0_PWM
2_A1
GPIO1_8
GPMC0_A2
UART4_RTS
n
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F4184
PADCONFIG W6
_97
PRG0_PRU0 PRG0_PRU0 PRG0_UART PRG0_PWM RGMII1_RX_ RMII1_RX_E PRG0_IEP0_ GPIO1_9
UART2_RXD
_GPO9
_GPI9
0_CTSn
3_TZ_IN
CTL
R
EDIO_DATA_
IN_OUT28
0x000F4188
PADCONFIG AA5
_98
PRG0_PRU0 PRG0_PRU0 PRG0_UART PRG0_PWM RGMII1_RXC RMII_REF_C PRG0_IEP0_ GPIO1_10
UART3_RXD
UART4_RXD
_GPO10
_GPI10
0_RTSn
2_B1
LK
EDIO_DATA_
IN_OUT29
0x000F418C
0x000F4190
0x000F4194
0x000F4198
0x000F419C
0x000F41A0
0x000F41A4
PADCONFIG Y3
_99
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO11 _GPI11 I1_TD0 3_TZ_OUT
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16
GPIO1_17
PADCONFIG AA3
_100
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO12 _GPI12 I1_TD1 0_A0
GPMC0_A14
GPMC0_A15
GPMC0_A3
GPMC0_A16
GPMC0_A4
PADCONFIG R6
_101
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO13 _GPI13 I1_TD2 0_B0
SPI3_D0
SPI3_D1
SPI3_CS1
SPI3_CLK
PADCONFIG V4
_102
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO14 _GPI14 I1_TD3 0_A1
PADCONFIG T5
_103
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO15 _GPI15 I1_TX_CTL 0_B1
PADCONFIG U4
_104
PRG0_PRU0 PRG0_PRU0 PRG0_RGMI PRG0_PWM
_GPO16 _GPI16 I1_TXC 0_A2
PADCONFIG U1
_105
PRG0_PRU0 PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_TS_ CP_GEMAC SPI3_CS0
TIMER_IO11 GPMC0_A17
_GPO17
_GPI17
EDC_SYNC_ 0_B2
OUT1
SYNC
_CPTS0_TS
_SYNC
0x000F41A8
0x000F41AC
PADCONFIG V1
_106
PRG0_PRU0 PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_HW1 CP_GEMAC EHRPWM8_ GPIO1_18
UART4_CTS GPMC0_A5
n
UART2_RXD
UART3_RXD
_GPO18
_GPI18
EDC_LATCH 0_TZ_IN
_IN0
TSPUSH
_CPTS0_HW
1TSPUSH
A
PADCONFIG W1
_107
PRG0_PRU0 PRG0_PRU0 PRG0_IEP0_ PRG0_PWM CPTS0_TS_ CP_GEMAC EHRPWM8_ GPIO1_19
UART4_RTS GPMC0_A6
n
_GPO19
_GPI19
EDC_SYNC_ 0_TZ_OUT
OUT0
COMP
_CPTS0_TS
_COMP
B
0x000F41B0
0x000F41B4
0x000F41B8
0x000F41BC
0x000F41C0
0x000F41C4
0x000F41C8
0x000F41CC
PADCONFIG Y2
_108
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI
_GPO0 _GPI0 I2_RD0
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
GPIO1_25
GPIO1_26
GPIO1_27
EQEP0_A
EQEP0_B
EQEP0_S
UART5_CTS
n
PADCONFIG W2
_109
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI
_GPO1 _GPI1 I2_RD1
UART5_TXD
PADCONFIG V3
_110
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO2 _GPI2 I2_RD2 2_A2
UART5_RTS
n
PADCONFIG T4
_111
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI
_GPO3 _GPI3 I2_RD3
EQEP1_A
EQEP1_B
EQEP1_S
EQEP2_A
EQEP2_B
GPMC0_A18 UART6_CTS
n
PADCONFIG W3
_112
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
UART6_TXD
_GPO4
_GPI4
I2_RX_CTL
2_B2
PADCONFIG P4
_113
PRG0_PRU1 PRG0_PRU1
_GPO5 _GPI5
UART6_RTS
n
PADCONFIG R5
_114
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI
_GPO6 _GPI6 I2_RXC
GPMC0_A19 UART4_CTS
n
PADCONFIG W5
_115
PRG0_PRU1 PRG0_PRU1 PRG0_IEP1_
RGMII1_RD0 RMII1_RXD0
UART4_TXD
_GPO7
_GPI7
EDC_LATCH
_IN1
0x000F41D0
0x000F41D4
PADCONFIG R1
_116
PRG0_PRU1 PRG0_PRU1
_GPO8 _GPI8
PRG0_PWM
2_TZ_OUT
GPIO1_28
EQEP2_S
EQEP0_I
UART4_RTS
n
PADCONFIG Y5
_117
PRG0_PRU1 PRG0_PRU1 PRG0_UART
_GPO9 _GPI9 0_RXD
RGMII1_RD1 RMII1_RXD1 PRG0_IEP0_ GPIO1_29
UART5_RXD
EDIO_DATA_
IN_OUT30
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
ADDRESS
BALL
NUMBER
NAME
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F41D8
PADCONFIG V6
PRG0_PRU1 PRG0_PRU1 PRG0_UART PRG0_PWM RGMII1_RD2 RMII1_TXD0 PRG0_IEP0_ GPIO1_30
EQEP1_I
UART6_RXD
_118
_GPO10
_GPI10
0_TXD
2_TZ_IN
EDIO_DATA_
IN_OUT31
0x000F41DC
0x000F41E0
0x000F41E4
0x000F41E8
0x000F41EC
PADCONFIG W4
_119
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI
_GPO11 _GPI11 I2_TD0
GPIO1_31
GPIO1_32
GPIO1_33
GPIO1_34
GPIO1_35
EQEP2_I
EQEP2_B
EQEP0_I
EQEP1_I
UART4_RXD
UART4_TXD
UART5_RXD
UART6_RXD
PADCONFIG Y4
_120
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO12 _GPI12 I2_TD1 1_A0
GPMC0_A7
GPMC0_A8
GPMC0_A9
PADCONFIG T6
_121
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO13 _GPI13 I2_TD2 1_B0
PADCONFIG U6
_122
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO14 _GPI14 I2_TD3 1_A1
PADCONFIG U5
_123
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO15 _GPI15 I2_TX_CTL 1_B1
GPMC0_A10 PRG0_ECAP
0_IN_APWM
_OUT
0x000F41F0
0x000F41F4
0x000F41F8
0x000F41FC
PADCONFIG AA4
_124
PRG0_PRU1 PRG0_PRU1 PRG0_RGMI PRG0_PWM
_GPO16 _GPI16 I2_TXC 1_A2
GPIO1_36
GPIO1_37
GPMC0_A11 PRG0_ECAP
0_SYNC_OU
T
PADCONFIG V5
_125
PRG0_PRU1 PRG0_PRU1 PRG0_IEP1_ PRG0_PWM RGMII1_RD3 RMII1_TXD1
PRG0_ECAP
0_SYNC_OU
T
PRG0_ECAP
0_SYNC_IN
_GPO17
_GPI17
EDC_SYNC_ 1_B2
OUT1
PADCONFIG P5
_126
PRG0_PRU1 PRG0_PRU1 PRG0_IEP1_ PRG0_PWM MDIO0_MDI RMII1_TX_E EHRPWM7_ GPIO1_38
PRG0_ECAP
0_SYNC_IN
_GPO18
_GPI18
EDC_LATCH 1_TZ_IN
_IN0
O
N
A
PADCONFIG R2
_127
PRG0_PRU1 PRG0_PRU1 PRG0_IEP1_ PRG0_PWM MDIO0_MDC RMII1_CRS_ EHRPWM7_ GPIO1_39
PRG0_ECAP
0_IN_APWM
_OUT
_GPO19
_GPI19
EDC_SYNC_ 1_TZ_OUT
OUT0
DV
B
0x000F4200
0x000F4204
0x000F4208
0x000F420C
PADCONFIG P2
_128
PRG0_MDIO
0_MDIO
GPIO1_40
GPIO1_41
GPIO1_42
GPMC0_A12
GPMC0_A13
PADCONFIG P3
_129
PRG0_MDIO
0_MDC
PADCONFIG D12
_130
SPI0_CS0
PADCONFIG C13
_131
SPI0_CS1
CPTS0_TS_ I2C2_SCL
COMP
TIMER_IO10 PRG0_IEP0_ UART6_RXD ADC_EXT_T GPIO1_43
EDIO_OUTV
ALID
RIGGER0
0x000F4210
0x000F4214
0x000F4218
0x000F421C
0x000F4220
PADCONFIG D13
_132
SPI0_CLK
SPI0_D0
SPI0_D1
SPI1_CS0
SPI1_CS1
GPIO1_44
GPIO1_45
GPIO1_46
GPIO1_47
PADCONFIG A13
_133
PADCONFIG A14
_134
PADCONFIG B14
_135
EHRPWM6_
A
PADCONFIG D14
_136
CPTS0_TS_ I2C2_SDA
SYNC
PRG1_IEP0_ UART6_TXD ADC_EXT_T GPIO1_48
TIMER_IO11
EDIO_OUTV
ALID
RIGGER1
0x000F4224
PADCONFIG C14
_137
SPI1_CLK
EHRPWM6_
SYNCI
GPIO1_49
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F4228
PADCONFIG B15
_138
SPI1_D0
EHRPWM6_
SYNCO
GPIO1_50
0x000F422C
0x000F4230
0x000F4234
0x000F4238
PADCONFIG A15
_139
SPI1_D1
EHRPWM6_
B
GPIO1_51
GPIO1_52
GPIO1_53
GPIO1_54
PADCONFIG D15
_140
UART0_RXD
UART0_TXD
SPI2_D0
SPI2_D1
EQEP0_A
EQEP0_B
EQEP0_S
PADCONFIG C16
_141
PADCONFIG B16
_142
UART0_CTS SPI0_CS2
n
ADC_EXT_T UART2_RXD TIMER_IO6
RIGGER0
SPI4_CLK
SPI4_D0
CP_GEMAC
_CPTS0_TS
_SYNC
0x000F423C
0x000F4240
PADCONFIG A16
_143
UART0_RTS SPI0_CS3
n
UART2_TXD TIMER_IO7
SPI2_CS0
GPIO1_55
GPIO1_56
EQEP0_I
EQEP1_A
PADCONFIG E15
_144
UART1_RXD
CP_GEMAC
_CPTS0_TS
_COMP
0x000F4244
0x000F4248
0x000F424C
PADCONFIG E14
_145
UART1_TXD
SPI2_CLK
CP_GEMAC
_CPTS0_HW
1TSPUSH
GPIO1_57
GPIO1_58
GPIO1_59
EQEP1_B
EQEP1_S
EQEP1_I
PADCONFIG D16
_146
UART1_CTS SPI1_CS2
n
ADC_EXT_T PCIE0_CLKR UART3_RXD CP_GEMAC SPI4_D1
RIGGER1
EQn
_CPTS0_TS
_SYNC
PADCONFIG E16
_147
UART1_RTS SPI1_CS3
n
UART3_TXD CP_GEMAC SPI4_CS0
_CPTS0_HW
2TSPUSH
0x000F4250
0x000F4254
0x000F4258
0x000F425C
0x000F4260
0x000F4264
0x000F4268
0x000F426C
0x000F4270
PADCONFIG A17
_148
MCAN0_TX
UART4_RXD TIMER_IO2
SYNC2_OUT
SYNC3_OUT
SPI4_CS1
SPI4_CS2
GPIO1_60
GPIO1_61
EQEP2_I
EQEP2_S
EQEP2_A
EQEP2_B
UART0_DTR
n
PADCONFIG B17
_149
MCAN0_RX UART4_TXD TIMER_IO3
UART0_RIn
PADCONFIG C17
_150
MCAN1_TX
I2C3_SCL
ECAP1_IN_A SYSCLKOUT TIMER_IO4
PWM_OUT
UART5_RXD EHRPWM_S GPIO1_62
OCA
UART0_DCD
n
0
PADCONFIG D17
_151
MCAN1_RX I2C3_SDA
I2C0_SCL
ECAP2_IN_A OBSCLK0
PWM_OUT
TIMER_IO5
UART5_TXD EHRPWM_S GPIO1_63
OCB
UART0_DSR
n
OBSCLK0
PADCONFIG A18
_152
UART6_CTS
n
GPIO1_64
GPIO1_65
GPIO1_66
GPIO1_67
PADCONFIG B18
_153
I2C0_SDA
UART6_RTS
n
PADCONFIG C18
_154
I2C1_SCL
I2C1_SDA
CPTS0_HW1 TIMER_IO0
TSPUSH
SPI2_CS1
PADCONFIG B19
_155
CPTS0_HW2 TIMER_IO1
TSPUSH
SPI2_CS2
PADCONFIG D18
_156
ECAP0_IN_A SYNC0_OUT CPTS0_RFT
PWM_OUT _CLK
CP_GEMAC SPI4_CS3
_CPTS0_RF
GPIO1_68
T_CLK
0x000F4274
0x000F4278
PADCONFIG A19
_157
EXT_REFCL SYNC1_OUT SPI2_CS3
K1
CLKOUT0
GPIO1_69
GPIO1_70
PADCONFIG C19
_158
EXTINTn
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
ADDRESS
BALL
NUMBER
NAME
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x000F427C
0x000F4280
0x000F4284
0x000F4288
PADCONFIG K18
_159
MMC1_DAT3 CP_GEMAC TIMER_IO0
UART2_RXD
GPIO1_71
_CPTS0_TS
_COMP
PADCONFIG K19
_160
MMC1_DAT2 CP_GEMAC TIMER_IO1
UART2_TXD
UART3_RXD
UART3_TXD
GPIO1_72
GPIO1_73
GPIO1_74
_CPTS0_TS
_SYNC
PADCONFIG L21
_161
MMC1_DAT1 CP_GEMAC TIMER_IO2
_CPTS0_HW
1TSPUSH
PADCONFIG K21
_162
MMC1_DAT0 CP_GEMAC TIMER_IO3
_CPTS0_HW
2TSPUSH
0x000F428C
0x000F4294
0x000F4298
0x000F429C
0x000F42A0
0x000F42A4
0x000F42A8
0x000F42AC
0x000F42B0
0x000F42B4
0x000F42B8
0x000F42BC
0x000F42C0
0x000F42C4
0x000F42C8
0x000F42CC
0x04084000
0x04084004
PADCONFIG L20
_163
MMC1_CLK UART2_CTS TIMER_IO4
n
UART4_RXD
UART4_TXD
UART5_RXD
UART5_TXD
GPIO1_75
GPIO1_76
GPIO1_77
GPIO1_78
PADCONFIG J19
_165
MMC1_CMD UART2_RTS TIMER_IO5
n
PADCONFIG D19
_166
MMC1_SDC UART3_CTS TIMER_IO6
D
n
PADCONFIG C20
_167
MMC1_SDW UART3_RTS TIMER_IO7
P
n
PADCONFIG E18
_168
RESET_REQ
z
PADCONFIG F16
_169
RESETSTAT
z
PADCONFIG E19
_170
USB0_DRVV
BUS
GPIO1_79
PADCONFIG E17
_171
PORz_OUT
ADC0_AIN0
ADC0_AIN1
ADC0_AIN2
ADC0_AIN3
ADC0_AIN4
ADC0_AIN5
ADC0_AIN6
ADC0_AIN7
PADCONFIG G20
_172
PADCONFIG F20
_173
PADCONFIG E21
_174
PADCONFIG D20
_175
PADCONFIG G21
_176
PADCONFIG F21
_177
PADCONFIG F19
_178
PADCONFIG E20
_179
MCU_PADC D6
ONFIG_0
MCU_SPI0_
CS0
MCU_GPIO0
_13
MCU_PADC C6
ONFIG_1
MCU_SPI0_ MCU_OBSC MCU_SYSCL
CS1 LK0 KOUT0
MCU_GPIO0
_12
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
NAME
BALL
NUMBER
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x04084008
MCU_PADC E6
ONFIG_2
MCU_SPI0_
CLK
MCU_GPIO0
_11
0x0408400C
0x04084010
0x04084014
0x04084018
0x0408401C
0x04084020
0x04084024
0x04084028
0x0408402C
0x04084030
0x04084034
0x04084038
0x0408403C
0x04084040
0x04084044
0x04084048
0x0408404C
0x04084050
0x04084054
0x04084058
0x0408405C
0x04084060
0x04084064
MCU_PADC E7
ONFIG_3
MCU_SPI0_
D0
MCU_GPIO0
_10
MCU_PADC B6
ONFIG_4
MCU_SPI0_
D1
MCU_GPIO0
_4
MCU_PADC A7
ONFIG_5
MCU_SPI1_
CS0
MCU_GPIO0
_5
MCU_PADC B7
ONFIG_6
MCU_SPI1_ MCU_EXT_R
CS1
MCU_GPIO0
_6
EFCLK0
MCU_PADC D7
ONFIG_7
MCU_SPI1_
CLK
MCU_GPIO0
_7
MCU_PADC C7
ONFIG_8
MCU_SPI1_
D0
MCU_GPIO0
_8
MCU_PADC C8
ONFIG_9
MCU_SPI1_
D1
MCU_GPIO0
_9
MCU_PADC A9
ONFIG_10
MCU_UART0
_RXD
MCU_GPIO0
_3
MCU_PADC A8
ONFIG_11
MCU_UART0
_TXD
MCU_GPIO0
_2
MCU_PADC D8
ONFIG_12
MCU_UART0 MCU_TIMER MCU_SPI0_
_CTSn _IO0 CS2
MCU_GPIO0
_1
MCU_PADC E8
ONFIG_13
MCU_UART0 MCU_TIMER MCU_SPI1_
_RTSn
MCU_GPIO0
_0
_IO1
CS2
MCU_PADC C9
ONFIG_14
MCU_UART1
_RXD
MCU_GPIO0
_14
MCU_PADC D9
ONFIG_15
MCU_UART1
_TXD
MCU_GPIO0
_15
MCU_PADC B8
ONFIG_16
MCU_UART1 MCU_TIMER MCU_SPI0_
_CTSn _IO2 CS3
MCU_GPIO0
_16
MCU_PADC B9
ONFIG_17
MCU_UART1 MCU_TIMER MCU_SPI1_
_RTSn
MCU_GPIO0
_17
_IO3
CS3
MCU_PADC E9
ONFIG_18
MCU_I2C0_
SCL
MCU_GPIO0
_18
MCU_PADC A10
ONFIG_19
MCU_I2C0_
SDA
MCU_GPIO0
_19
MCU_PADC A11
ONFIG_20
MCU_I2C1_
SCL
MCU_GPIO0
_20
MCU_PADC B10
ONFIG_21
MCU_I2C1_
SDA
MCU_GPIO0
_21
MCU_PADC B12
ONFIG_22
MCU_RESE
Tz
MCU_PADC B21
ONFIG_23
MCU_PORz
MCU_PADC B13
ONFIG_24
MCU_RESE
TSTATz
MCU_GPIO0
_22
MCU_PADC A20
ONFIG_25
MCU_SAFET
Y_ERRORn
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Table 6-77. Pin Multiplexing (ALV Package) (continued)
MUXMODE[Bootstrap:0] SETTINGS
REGISTER
ADDRESS
BALL
NUMBER
NAME
0
1
2
3
4
5
6
7
8
9
10
15
Bootstrap
0x04084068
0x0408406C
0x04084070
0x04084074
0x04084078
0x0408407C
0x04084080
MCU_PADC B11
ONFIG_26
TCK
MCU_PADC D11
ONFIG_27
TRSTn
TDI
MCU_PADC C11
ONFIG_28
MCU_PADC A12
ONFIG_29
TDO
MCU_PADC C12
ONFIG_30
TMS
MCU_PADC D10
ONFIG_31
EMU0
EMU1
MCU_PADC E10
ONFIG_32
MCU_OBSC
LK0
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6.5 Connections for Unused Pins
This section describes the Unused/Reserved balls connection requirements.
Note
All power balls must be supplied with the voltages specified in Section 7.4, Recommended Operating
Conditions, unless otherwise specified in Section 6.3, Signal Descriptions.
Table 6-78. Unused Balls Specific Connection Requirements
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
Each of these balls must be connected to VSS through a separate
external pull resistor to ensure these balls are held to a valid logic
low level if unused.
TBD
TBD
TBD
Each of these balls must be connected to the corresponding power
supply through a separate external pull resistor to ensure these balls
are held to a valid logic high level, if unused.(1)
F7
G6
H7
J6,
K7
L6
J8
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR_C
If DDRSS is not used, each of these balls must be connected directly
to VSS.
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Table 6-78. Unused Balls Specific Connection Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
H2
H1
J5
DDR0_ACT_n
DDR0_ALERT_n
DDR0_CAS_n
DDR0_PAR
DDR0_RAS_n
DDR0_WE_n
DDR0_A0
DDR0_A1
DDR0_A2
DDR0_A3
DDR0_A4
K5
F6
H4
D2
C5
E2
D4
D3
F2
J2
DDR0_A5
DDR0_A6
L5
DDR0_A7
J3
DDR0_A8
J4
DDR0_A9
K3
J1
DDR0_A10
DDR0_A11
M5
K4
G4
G5
G2
H3
H5
F1
E1
F4
F3
E3
E4
B2
M2
A3
A2
B5
A4
B3
C4
C2
B4
N5
L4
DDR0_A12
DDR0_A13
DDR0_BA0
DDR0_BA1
DDR0_BG0
DDR0_BG1
DDR0_CAL0
DDR0_CK0
DDR0_CK0_n
DDR0_CKE0
DDR0_CKE1
DDR0_CS0_n
DDR0_CS1_n
DDR0_DM0
DDR0_DM1
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQS0
DDR0_DQS0_n
DDR0_DQS1
DDR0_DQS1_n
DDR0_ODT0
DDR0_ODT1
DDR0_RESET0_n
Leave unconnected.
Note: The DDR0 pins in this list can only be left unconnected when
VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0
pins must be connected as defined in the AM64x DDR Board Design
and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are
connected to a power source.
L2
M3
N4
N3
M4
N2
C1
B1
N1
M1
E5
F5
D5
P12
P13
P11
R14
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_1P8_SERDES0
If SERDES0 is not used, each of these balls must be connected
directly to VSS.
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Table 6-78. Unused Balls Specific Connection Requirements (continued)
BALL NUMBER
BALL NAME
CONNECTION REQUIREMENTS
T13
SERDES0_REXT
Leave unconnected.
W16
W17
Y15
Y16
AA16
AA17
SERDES0_REFCLK0N
SERDES0_REFCLK0P
SERDES0_RX0_N
SERDES0_RX0_P
SERDES0_TX0_N
SERDES0_TX0_P
Note: The SERDES0_REXT pin can only be left unconnected when
VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and
VDDA_1P8_SERDES0 are connected to VSS. The
SERDES0_REXT pin must be connected to VSS through the
appropriate external resistor when VDDA_0P85_SERDES0,
VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are
connected to a power source.
(1) To determine which power supply is associated with any IO refer to Section 6.2, Pin Attributes.
Table 6-79. Reserved Balls Specific Connection Requirements
BALL NUMBER
CONNECTION REQUIREMENTS
D21, F12, F17, G13, H16, K1, K2, V16, W15
These balls must be left unconnected.
Note
All other unused signal balls with a Pad Configuration Register can be left unconnected with their
multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on
the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for
some operating conditions. This may be the case when connected to components with leakage to the
opposite logic level, or when external noise sources couple to signal traces attached to balls which are
only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be
required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state
which could damage the IO cell.
Note
All other unused signal balls without a Pad Configuration Register can be left unconnected.
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7 Specifications
Note
All specifications listed are preliminary and may change during device characterization.
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER
MIN
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
MAX UNIT
VDD_CORE
Core supply
1.05
1.05
1.05
1.05
1.05
1.05
1.05
TBD
TBD
2.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDR_CORE
VDD_MMC0
RAM supply
MMC0 PHY core supply
MMC0 PLL analog supply
SERDES0 0.85 V analog supply
SERDES0 clock 0.85 V analog supply
USB0 0.85 V analog supply
DDR PHY IO supply
VDD_DLL_MMC0
VDDA_0P85_SERDES0
VDDA_0P85_SERDES0_C
VDDA_0P85_USB0
VDDS_DDR
VDDS_DDR_C
VDDS_MMC0
VDDS_OSC
DDR clock IO supply
MMC0 PHY IO supply
MCU_OSC0 supply
2.2
VDDA_MCU
POR and MCU PLL analog supply
ADC0 analog supply
2.2
VDDA_ADC0
VDDA_PLL0
2.2
Main, PER1, and R5F PLL analog supply
ARM and DDR PLL analog supply
PER0 PLL analog supply
SERDES0 1.8 V analog supply
USB0 1.8 V analog supply
TEMP0 analog supply
2.2
VDDA_PLL1
2.2
VDDA_PLL2
2.2
VDDA_1P8_SERDES0
VDDA_1P8_USB0
VDDA_TEMP0
VDDA_TEMP1
VPP
2.2
2.2
2.2
TEMP1 analog supply
2.2
eFuse ROM programming supply
IO supply for IO MCU
TBD
3.8
VDDSHV_MCU
VDDSHV0
IO supply for IO group 0
IO supply for IO group 1
IO supply for IO group 2
IO supply for IO group 3
IO supply for IO group 4
IO supply for IO group 5
USB0 3.3 V analog supply
SDIO 3.3 V analog supply
3.8
VDDSHV1
3.8
VDDSHV2
3.8
VDDSHV3
3.8
VDDSHV4
3.8
VDDSHV5
3.8
VDDA_3P3_USB0
VDDA_3P3_SDIO
3.8
TBD
TBD
Steady-state max voltage at all fail-safe IO pins
MCU_I2C0_SCL, MCU_I2C0_SDA,
I2C0_SCL, I2C0_SDA, EXTINTn,
MCU_PORz
VMON_1P8_MCU, VMON_1P8_SOC
VMON_3P3_MCU, VMON_3P3_SOC
VMON_VSYS(4)
-0.3
-0.3
-0.3
-0.3
-0.3
2.2
3.8
2.2
3.6
V
V
V
V
V
Steady-state max voltage at all other IO pins(3)
USB0_VBUS(6)
All other IO pins
IO supply
voltage + 0.3
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over operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER
MIN
MAX UNIT
Transient overshoot and undershoot at IO pin
20% of IO supply voltage for up to 20%
0.2 × VDD(5)
V
of the signal period (see Figure 7-1, IO
Transient Voltage Ranges)
Latch-up performance
TBD
-55
TBD
mA
°C
TSTG
Storage temperature
+150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4, Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –
0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.4, System Power
Supply Monitor Design Guidelines.
(5) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.3, USB
Design Guidelines.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA,
I2C0_SCL, I2C0_SDA,
EXTINTn, VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, VMON_3P3_SOC, and MCU_PORz are
the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be
limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 7.1.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
A. Tovershoot + Tundershoot < 20% of Tperiod
Figure 7-1. IO Transient Voltage Ranges
7.2 ESD Ratings
VALUE
TBD
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic discharge
(ESD)
V(ESD)
V
TBD
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Power-On Hours (POH)
COMMERCIAL JUNCTION TEMPERATURE RANGE(1) (2) (3)
EXTENDED JUNCTION TEMPERATURE RANGE
JUNCTION TEMP (Tj)
LIFETIME (POH)
JUNCTION TEMP (Tj)
LIFETIME (POH)
TBD
0°C to 90°C
TBD
-40°C to 105°C
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
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(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted
temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
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7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
0.715
NOM
0.75
MAX
0.79
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_CORE
Core supply
0.75-V operation
0.85-V operation
0.81
0.81
0.81
0.81
0.81
0.81
0.81
1.06
1.14
1.06
1.14
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.71
3.135
3.135
3.135
3.135
0
0.85
0.85
0.85
0.85
0.85
0.85
0.85
1.1
0.895
0.895
0.895
0.895
0.895
0.895
0.895
1.17
VDDR_CORE
RAM supply
VDD_MMC0
MMC0 PHY core supply
MMC0 PLL analog supply
VDD_DLL_MMC0
VDDA_0P85_SERDES0
SERDES0 0.85 V analog supply
VDDA_0P85_SERDES0_C SERDES0 clock 0.85 V analog supply
VDDA_0P85_USB0
VDDS_DDR
USB0 0.85 V analog supply
DDR PHY IO supply
1.1-V operation
1.2-V operation
1.1-V operation
1.2-V operation
1.2
1.26
VDDS_DDR_C
DDR clock IO supply
1.1
1.17
1.2
1.26
VDDS_MMC0
VDDS_OSC
MMC0 PHY IO supply
1.8
1.89
MCU_OSC0 supply
1.8
1.89
VDDA_MCU
POR and MCU PLL analog supply
ADC0 analog supply
1.8
1.89
VDDA_ADC0
1.8
1.89
VDDA_PLL0
Main, PER and R5F PLL analog supply
ARM and DDR PLL analog supply
PER0 PLL analog supply
1.8
1.89
VDDA_PLL1
1.8
1.89
VDDA_PLL2
1.8
1.89
VDDA_1P8_SERDES0
VDDA_1P8_USB0
VDDA_TEMP0
VDDA_TEMP1
VPP
SERDES0 1.8 V analog supply
USB0 1.8 V analog supply
1.8
1.89
1.8
1.89
TEMP0 analog supply
1.8
1.89
TEMP1 analog supply
1.8
1.89
eFuse ROM programming supply
Voltage monitor for 1.8 V MCU power supply
Voltage monitor for 1.8 V SoC power supply
USB0 3.3 V analog supply
1.8
1.89
VMON_1P8_MCU
VMON_1P8_SOC
VDDA_3P3_USB0
VDDA_3P3_SDIO
VMON_3P3_MCU
VMON_3P3_SOC
VMON_VSYS
USB0_VBUS
1.8
1.89
1.8
1.89
3.3
3.465
3.465
3.465
3.465
1
SDIO 3.3 V analog supply
3.3
Voltage monitor for 3.3 V MCU power supply
Voltage monitor for 3.3 V SoC power supply
Voltage monitor pin
3.3
3.3
see(1)
see(2)
1.8
USB Level-shifted VBUS Input
Dual-voltage IO supply
0
3.465
1.89
VDDSHV_MCU
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.8-V operation
3.3-V operation
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
1.71
3.135
3.3
3.465
1.89
VDDSHV0
VDDSHV1
VDDSHV2
VDDSHV3
VDDSHV4
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
Dual-voltage IO supply
1.8
3.3
3.465
1.89
1.8
3.3
3.465
1.89
1.8
3.3
3.465
1.89
1.8
3.3
3.465
1.89
1.8
3.3
3.465
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UNIT
SPRSP56 – JANUARY 2021
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
DESCRIPTION
MIN
1.71
NOM
1.8
3.3
MAX
1.89
3.465
VDDSHV5
Dual-voltage IO supply
1.8-V operation
3.3-V operation
Extended
V
V
3.135
-40
0
TJ
Operating junction temperature range
105
90
°C
Commercial
(1) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.4, System Power
Supply Monitor Design Guidelines.
(2) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.3, USB
Design Guidelines.
7.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of each
Operating Performance Point (OPP) for processor clocks and device core clocks.
Table 7-1 describes the maximum supported frequency per speed grade for the device.
Table 7-1. Speed Grade Maximum Frequency
MAXIMUM FREQUENCY (MHz)
DEVICE
SPEED
GRADE
A53SS
R5FSS
M4FSS CBASS0
ICSSG
DMSC-L
DDR4
LPDDR4
AM64x
AM64x
S
K
1000
800
800
400
400
400
250
250
333
250
TBD
TBD
800 (DDR-1600)(1)
800 (DDR-1600)(1)
TBD(1)
TBD(1)
(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
7.6 Power Consumption Summary
For information on the device power consumption contact your TI Representative.
7.7 Electrical Characteristics
Note
The interfaces or signals described in Section 7.7.1 through correspond to the interfaces or signals
available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).
7.7.1 I2C, Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_I2C0_SCL / MCU_I2C0_SDA / I2C0_SCL / I2C0_SDA / EXTINTn
BALL NUMBERS: E9, A10, A18, B18, C19
1.8 V MODE
VIL
Input Low Voltage
0.3 × VDD(1)
0.3 × VDD(1)
TBD
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.7 × VDD(1)
0.7 × VDD(1)
0.1 × VDD(1)
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Output Low Voltage
V
mV
µA
V
VI = 1.8 V or 0 V
VOL(MAX)
±10
0.2 × VDD(1)
VOL
IOL
Low Level Output Current
20
mA
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over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SRI
Input Slew Rate
TBD
V/s
3.3 V MODE (2)
VIL
Input Low Voltage
0.3 × VDD(1)
0.25 × VDD(1)
TBD
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.7 × VDD(1)
0.7 × VDD(1)
0.05 × VDD(1)
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Output Low Voltage
V
mV
µA
V
VI = 3.3 V or 0 V
VOL(MAX)
±10
0.4
VOL
IOL
Low Level Output Current
Input Slew Rate
20
mA
V/s
SRI
TBD
8E + 7
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table
6-1, Pin Attributes, POWER column.
(2) I2C HS-mode is not supported when operating the IO in 3.3 V mode.
7.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_PORz
BALL NUMBERS: B21
VIL
Input Low Voltage
0.3 ×
V
VDDS_OSC
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
TBD
V
V
0.7 ×
VDDS_OSC
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Input Slew Rate
TBD
200
V
mV
µA
V/s
VI = 1.8 V or 0 V
±10
SRI
TBD
7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_OSC0_XI
BALL NUMBERS: C21
VIL
Input Low Voltage
0.35 ×
VDDS_OSC
V
V
VIH
Input High Voltage
0.65 ×
VDDS_OSC
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current.
49
mV
µA
VI = 1.8 V or 0 V
±TBD
7.7.4 eMMCPHY Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MMC0_DAT[7:0] / MMC0_CLK / MMC0_CMD / MMC0_DS
BALL NUMBERS: G17, H18, H19, H17, J17, J18, J20, K20, G18, J21, G19
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over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
Input Low Voltage
-0.3
0.35 ×
VDDS_MMC
0
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
TBD
V
V
0.65 ×
VDDS_MMC
0
VDDS_MMC
0 + 0.3
VIHSS
IIN
Input High Voltage Steady State
Input Leakage Current.
Tri-state Output Leakage Current.
Pull-up Resistor
TBD
V
VI = 1.8 V or 0 V
VO = 1.8 V or 0 V
±10
±10
50
±10
±10
59
pA
pA
kΩ
kΩ
V
IOZ
RPU
RPD
VOL
42
42
Pull-down Resistor
50
59
Output Low Voltage
0.15 ×
VDDS_MMC
0
VOH
Output High Voltage
0.85 ×
VDDS_MMC
0
V
IOL
Low Level Output Current
High Level Output Current
Input Slew Rate
VOL(MAX)
VOH(MIN)
TBD
TBD
TBD
mA
mA
V/s
IOH
SRI
7.7.5 SDIO Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MMC1_DAT[3:0] / MMC1_CLK / MMC1_CMD
BALL NUMBERS: K18, K19, L21, K21, L20, J19
1.8 V MODE
VIL
Input Low Voltage
0.58
0.58
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
1.27
1.7
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
V
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
VOH
40
40
50
50
Pull-down Resistor
60
Output Low Voltage
0.45
Output High Voltage
VDDSHV5 -
0.45
V
IOL
Low Level Output Current
High Level Output Current
Input Slew Rate
VOL(MAX)
VOH(MIN)
4
4
mA
mA
V/s
IOH
SRI
TBD
3.3 V MODE
VIL
Input Low Voltage
0.25 ×
VDDSHV5
V
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.15 ×
VDDSHV5
0.625 ×
VDDSHV5
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over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIHSS
Input High Voltage Steady State
0.625 ×
V
VDDSHV5
VHYS
IIN
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
150
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
60
RPU
RPD
VOL
40
40
50
50
Pull-down Resistor
Output Low Voltage
60
0.125 ×
VDDSHV5
VOH
Output High Voltage
0.75 ×
V
VDDSHV5
IOL
Low Level Output Current
High Level Output Current
Input Slew Rate
VOL(MAX)
VOH(MIN)
6
10
mA
mA
V/s
IOH
SRI
TBD
7.7.6 LVCMOS Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
BALL NAMES: ALL other IOs
BALL NUMBERS: ALL other IOs
1.8-V MODE
VIL
Input Low Voltage
0.35 × VDD(1)
0.3 × VDD(1)
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.65 × VDD(1)
0.85 × VDD
150
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-up Resistor
V
mV
µA
kΩ
kΩ
V
VI = 1.8 V or 0 V
±10
30
RPU
RPD
VOL
VOH
IOL
15
15
22
22
Pull-down Resistor
30
Output Low Voltage
0.45
Output High Voltage
VDD(1) - 0.45
V
Low Level Output Current
High Level Output Current
Input Slew Rate
VOL(MAX)
VOH(MIN)
3
3
mA
mA
V/s
IOH
SRI
TBD
3.3-V MODE
VIL
Input Low Voltage
0.8
0.6
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
2.0
2.0
V
VIHSS
VHYS
IIN
Input High Voltage Steady State
Input Hysteresis Voltage
Input Leakage Current.
Pull-down Resistor
V
150
mV
µA
kΩ
V
VI = 3.3 V or 0 V
±10
30
RPD
VOL
VOH
IOL
15
22
Output Low Voltage
0.4
Output High Voltage
2.4
5
V
Low Level Output Current
High Level Output Current
VOL(MAX)
VOH(MIN)
mA
mA
IOH
9
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over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
SRI
Input Slew Rate
TBD
V/s
(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table
6-1, Pin Attributes, POWER column.
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7.7.7 ADC12B Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
BALL NAMES in Mode 0: ADC0_AIN[7:0]
BALL NUMBERS: TBD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VADC_AIN[7:0]
DNL
Full-scale Input Range
VSS
-1
VDDA_ADC0
V
Differential Non-Linearity
Integral Non-Linearity
Gain Error
0.5
±1
±2
±2
5.5
70
2
LSB
LSB
LSB
LSB
pF
INL
±3
LSBGAIN-ERROR
LSBOFFSET-ERROR
CIN
Offset Error
Input Sampling Capacitance
Signal-to-Noise Ratio
SNR
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
dB
THD
Total Harmonic Distortion
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
75
80
69
dB
dB
dB
Ω
SFDR
Spurious Free Dynamic Range
Signal-to-Noise Plus Distortion
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
SNR(PLUS)
RADC_AIN[0:7]
IIN
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale
Input Impedance of
ADC0_AIN[7:0]
f = input frequency
[1/((65.97 × 10–-12) ×
fSMPL_CLK)]
Input Leakage
ADC0_AIN[7:0] = VSS
4
μA
μA
ADC0_AIN[7:0] = VDDA_ADC0
10
Sampling Dynamics
FSMPL_CLK
tC
SMPL_CLK Frequency
Conversion Time
60
13
MHz
ADC0 SMPL_CLK
Cycles
tACQ
Acquisition time
2
257 ADC0 SMPL_CLK
Cycles
TR
Sampling Rate
ADC0 SMPL_CLK = 60 MHz
4
MSPS
dB
CCISO
Channel to Channel Isolation
100
General Purpose Input Mode (1)
VIL
Input Low Voltage
0.35 × VDDA_ADC0
0.35 × VDDA_ADC0
V
V
V
V
VILSS
VIH
Input Low Voltage Steady State
Input High Voltage
0.65 × VDDA_ADC0
0.65 × VDDA_ADC0
VIHSS
Input High Voltage Steady State
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over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VHYS
II
Input Hysteresis Voltage
Input Leakage Current
200
mV
μA
ADC0_AIN[7:0] = VDDA_ADC0
or VSS
2
(1) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0_CTRL register
(gpi_mode_en = 1).
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7.7.8 USB2PHY Electrical Characteristics
Note
USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000
including ECNs and Errata as applicable.
7.7.9 SERDES Electrical Characteristics
Note
The PCIe interface is compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, February 19, 2014.
Note
USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative
Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26,
2013.
7.7.10 DDR Electrical Characteristics
Note
The DDR interface is compatible with DDR4 and LPDDR4 devices
7.8 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses .
7.8.1 Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
VDD_CORE
Supply voltage range for the core domain during OTP
operation; OPP NOM (BOOT)
See Section 7.4
V
VPP
Supply voltage range for the eFuse ROM domain during
normal operation without hardware support to program
eFuse ROM
NC
0
V
V
V
Supply voltage range for the eFuse ROM domain during
normal operation with hardware support to program eFuse
ROM
Supply voltage range for the eFuse ROM domain during
OTP programming(1)
1.71
1.8
1.89
I(VPP)
SR(VPP)
Tj
VPP current
TBD
6E + 4
85
mA
V/s
°C
VPP Slew Rate
Temperature (ambient)
0
25
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family
is a example device that meets the supply voltage range needed for VPP.
7.8.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The VPP power supply must be disabled when not programming OTP registers.
The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see
Section 7.10.2, Power Supply Sequencing).
7.8.3 Programming Sequence
Programming sequence for OTP eFuses:
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•
•
Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during
power up and normal operation.
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
•
•
•
Apply the voltage on the VPP terminal according to the specification in Section 7.8.1.
Run the software that programs the OTP registers.
After validating the content of the OTP registers, remove the voltage from the VPP terminal.
7.8.4 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that the
e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step.
Further the TI Device may fail to secure boot if the error code correction check fails for the Production Keys or if
the image is not signed and optionally encrypted with the current active Production Keys. These types of
situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices conformed
to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
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7.9 Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in Section 7.4, Recommended Operating Conditions.
7.9.1 Thermal Resistance Characteristics for ALV Package
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
ALV PACKAGE
NO.
PARAMETER
DESCRIPTION
AIR FLOW
(m/s)(2)
°C/W(1) (3)
T1
RΘJC
Junction-to-case
Junction-to-board
Junction-to-free air
0.98
3.87
12.8
TBD
TBD
TBD
0.53
TBD
TBD
TBD
3.74
TBD
TBD
TBD
N/A
N/A
0
T2
RΘJB
T3
T4
1
RΘJA
T5
Junction-to-moving air
2
T6
3
T7
0
T8
1
ΨJT
Junction-to-package top
T9
2
T10
T11
T12
T13
T14
3
0
1
ΨJB
Junction-to-board
2
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
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7.10 Timing and Switching Characteristics
Note
The Timing Requirements and Switching Characteristics values may change following the silicon
characterization result.
Note
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.
7.10.1 Timing Parameters and Information
The timing parameter symbols used in Section 7.10 are created in accordance with JEDEC Standard 100. To
shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 7-2:
Table 7-2. Timing Parameters Subscripts
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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7.10.2 Power Supply Sequencing
This section describes power supply sequencing required to ensure proper device operation. The power supply
names described in this section comprise a superset of a family of compatible devices. Some members of this
family will not include a subset of these power supplies and their associated device modules.
Note
All power sequence timing shown is preliminary and under evaluation. Updates will be provided as
details become known during validation testing.
7.10.2.1 Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 18 mV/µs. For instance, as shown in Figure 7-2, TI recommends
having the supply ramp slew for a 1.8-V supply of more than 100 µs.
Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.
Supply value
t
slew rate < 18 mV/μs
slew > (supply value) / (18 mV/μs)
or
supply value × 55.6 μs/V
SPRT740_ELCH_06
Figure 7-2. Power Supply Slew and Slew Rate
7.10.2.2 Power-Up Sequencing
Figure 7-3 describes the device power-up sequencing.
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VSYS
Note 1
Note 2
VSYS, VMON_VSYS
VMON_VSYS
(3)
(3)
(3)
(3)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(3)
,
(3)
(3)
VDDSHV4 , VDDSHV5 , VDDA_3P3_SDIO, VDDA_USB0,
(4)
VMON_3P3_SOC , VMON_3P3_MCU
(4)
(5)
(5)
(5)
(5)
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(5)
,
(5)
(5)
VDDSHV4 , VDDSHV5 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,
(6)
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU
(6)
VMON_1P8_SOC , VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0
,
(7)
VDDS_DDR , VDDS_DDR_C
(7)
(8)
VDD_CORE
(9)(10)
(10)
VDD_CORE
, VDDR_CORE , VDDA_0P85_SERDES0_C,
VDDA_0P85_SERDES0, VDDA_0P85_USB0,
VDD_DLL_MMC0, VDD_MCU0
Hi-Z
(11)
VPP
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM64x_ELCH_01
Figure 7-3. Power-Up Sequencing
1. VSYS represents the name of a supply which sources power to the entire system. This supply is expected to
be a pre-regulated supply that sources power management devices which source all other supplies.
2. VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see
Section 9.3.4, System Power Supply Monitor Design Guidelines.
3. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO
supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period
defined by this waveform.
4. The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be
connected to the respective 3.3V supply source.
5. VDDSHV_MCU and VDDSHVx [x=0-5] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-5] IO
supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period
defined by this waveform.
6. The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be
connected to the respective 1.8V supply source.
7. VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp
together.
8. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.75V, it shall be ramped
up prior to all 0.85V supplies as shown in this waveform.
9. VDD_CORE can be operated at 0.75V or 0.85V. When VDD_CORE is operating at 0.85V, it shall be ramped
up with other 0.85V supplies during the 0.85V ramp period defined by this waveform.
10.VDD_CORE and VDDR_CORE are expected to be powered by the same source such that they ramp
together when VDD_CORE is operating at 0.85V.
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11.VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/
down sequences and during normal device operation. This supply shall only be sourced while programming
eFuse.
7.10.2.3 Power-Down Sequencing
Figure 7-4 describes the device power-down sequencing.
VSYS
VSYS, VMON_VSYS
VMON_VSYS
(1)
(1)
(1)
(1)
VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(1)
,
(1)
(1)
VDDSHV4 , VDDSHV5 , VDDA_3P3_SDIO, VDDA_USB0,
VMON_3P3_SOC, VMON_3P3_MCU
(2)
(2)
(2)
(2)
VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3
(2)
,
(2)
(2)
VDDSHV4 , VDDSHV5 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,
VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU,
VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0
VDDS_DDR, VDDS_DDR_C
(3)
VDD_CORE
(4)
VDD_CORE , VDDR_CORE, VDDA_0P85_SERDES0_C,
VDDA_0P85_SERDES0, VDDA_0P85_USB0,
VDD_DLL_MMC0, VDD_MCU0
VPP
Hi-Z
MCU_PORz
MCU_OSC0_XI, MCU_OSC0_XO
AM64x_ELCH_02
Figure 7-4. Power-Down Sequencing
1. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.
2. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.
3. VDD_CORE when operating at 0.75V.
4. VDD_CORE when operating at 0.85V.
7.10.3 System Timing
For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-3. System Timing Conditions
PARAMETER
MIN
0.5
3
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
2 V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
30 pF
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7.10.3.1 Reset Timing
Tables and figures provided in this section define timing requirements and switching characteristics for reset
related signals.
Table 7-4. MCU_PORz Timing Requirements
see Figure 7-5
NO.
MIN
MAX UNIT
Hold time, MCU_PORz active (low) at Power-up
after supplies valid (using external crystal)
RST1
9500000
ns
th(SUPPLIES_VALID - MCU_PORz)
Hold time, MCU_PORz active (low) at Power-up
after supplies valid and external clock stable (using
external LVCMOS oscillator)
RST2
1200
1200
ns
ns
Pulse Width minimum, MCU_PORz low after
Power-up (without removal of Power or system
reference clock MCU_OSC0_XI/XO)
RST3 tw(MCU_PORzL)
Figure 7-5. MCU_PORz Timing Requirements
Table 7-5. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-6
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
MCU_RESETSTATz active (low)
RST4 td(MCU_PORzL-MCU_RESETSTATzL)
RST5 td(MCU_PORzH-MCU_RESETSTATzH)
RST6 td(MCU_PORzL-RESETSTATzL)
RST7 td(MCU_PORzH-RESETSTATzH)
RST8 tw(MCU_RESETSTATzL)
0
ns
Delay time, MCU_PORz inactive (high) to
MCU_RESETSTATz inactive (high)
6120*S(1)
0
ns
ns
ns
ns
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
Delay time, MCU_PORz active (low) to
RESETSTATz active (low)
9195*S(1)
4040*S(1)
Pulse Width Minimum MCU_RESETSTATz low
(SW_MCU_WARMRST)
Pulse Width Minimum RESETSTATz low
(SW_MCU_WARMRST, SW_MAIN_PORz, or
SW_MAIN_WARMRST)
RST9 tw(RESETSTATzL)
301200
ns
(1) S = MCU_OSC0_XI/XO clock period
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Figure 7-6. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
Table 7-6. MCU_RESETz Timing Requirements
see Figure 7-7
NO.
MIN
MAX UNIT
(1)
RST10 tw(MCU_RESETzL)
Pulse Width minimum, MCU_RESETz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-7. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 7-7
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_RESETz active (low) to
MCU_RESETSTATz active (low)
RST11 td(MCU_RESETzL-MCU_RESETSTATzL)
0
ns
Delay time, MCU_RESETz inactive (high) to
MCU_RESETSTATz inactive (high)
RST12 td(MCU_RESETzH-MCU_RESETSTATzH)
RST13 td(MCU_RESETzL-RESETSTATzL)
966*S(1)
0
ns
ns
ns
Delay time, MCU_RESETz active (low) to
RESETSTATz active (low)
RST14 td(MCU_RESETzH-RESETSTATzH)
Delay time, MCU_RESETz inactive (high) to
RESETSTATz inactive (high)
4040*S(1)
(1) S = MCU_OSC0_XI/XO clock period
Figure 7-7. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching
Characteristics
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Table 7-8. RESET_REQz Timing Requirements
see Figure 7-8
NO.
MIN
MAX UNIT
(1)
RST15 tw(RESET_REQzL)
Pulse Width minimum, RESET_REQz active (low)
1200
ns
(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 7-9. RESETSTATz Switching Characteristics
see Figure 7-8
NO.
PARAMETER
MIN
MAX UNIT
Delay time, RESET_REQz active (low) to
RESETSTATz active (low)
RST16 td(RESET_REQzL-RESETSTATzL)
T(1)
ns
Delay time, RESET_REQz inactive (high) to
RESETSTATz inactive (high)
RST17 td(RESET_REQzH-RESETSTATzH)
W(2)
ns
(1) T = Reset Isolation Time (Software Dependent)
(2) W = Max [300 μs (Typical) from RESETz_REQz inactive (high), Reset Isolation Time + 300 μs (TYP) from RESET_REQz active (low)]
Figure 7-8. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics
Table 7-10. EMUx Timing Requirements
see Figure 7-9
NO.
MIN
MAX UNIT
Setup time, EMU[1:0] before MCU_PORz inactive
(high)
RST18 tsu(EMUx-MCU_PORz)
3*S(1)
ns
Hold time, EMU[1:0] after MCU_PORz inactive
(high)
RST19 th(MCU_PORz - EMUx)
10
ns
(1) S = MCU_OSC0_XI/XO clock period
Figure 7-9. EMUx Timing Requirements
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Table 7-11. BOOTMODE Timing Requirements
see Figure 7-10
NO.
MIN
MAX UNIT
Setup time, BOOTMODE[15:00] before
PORz_OUT high (External MCU PORz event or
Software SW_MAIN_PORz)
RST23 tsu(BOOTMODE-PORz_OUT)
3*S(1)
ns
Hold time, BOOTMODE[15:00] after PORz_OUT
high (External MCU PORz event, Software
SW_MAIN_PORz)
RST24 th(PORz_OUT - BOOTMODE)
0
ns
(1) S = MCU_OSC0_XI/XO clock period
Table 7-12. PORz_OUT Switching Characteristics
see Figure 7-10
NO.
PARAMETER
MIN
MAX UNIT
Delay time, MCU_PORz active (low) to
PORz_OUT active (low)
RST25 td(MCU_PORzL-PORz_OUT)
0
ns
Delay time, MCU_PORz inactive (high) to
PORz_OUT inactive (high)
RST26 td(MCU_PORzH-PORz_OUT)
RST27 tw(PORz_OUTL)
0
ns
ns
Pulse Width Minimum PORz_OUT low
(MCU_PORz, SW_MAIN_PORz)
1200
Figure 7-10. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics
7.10.3.2 Safety Signal Timing
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn.
Table 7-13. MCU_SAFETY_ERRORn Switching Characteristics
see Figure 7-11
NO.
PARAMETER
MIN
MAX UNIT
Cycle time minimum, MCU_SAFETY_ERRORn
(PWM mode enabled)
SFTY1 tc(MCU_SAFETY_ERRORn)
(P*H)+(P*L)(1) (3) (4)
ns
Pulse width minimum, MCU_SAFETY_ERRORn
active (PWM mode disabled)(5)
SFTY2 tw(MCU_SAFETY_ERRORn)
P*R(1) (2)
50*P(1)
ns
ns
td (ERROR_CONDITION-
Delay time, ERROR CONDITION to
MCU_SAFETY_ERRORn active(5)
SFTY3
MCU_SAFETY_ERRORnL)
(1) P = ESM functional clock
(2) R = Error Pin Counter Pre-Load Register count value
(3) H = Error Pin PWM High Pre-Load Register count value
(4) L = Error Pin PWM Low Pre-Load Register count value
(5) When PWM mode is enabled, MCU_SAFETY_ERRORn stops toggling after RST22 and will maintain its value (either high or low) until
the error is cleared. When PWM mode is disabled, MCU_SAFETY_ERRORn is active low.
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Figure 7-11. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics
7.10.3.3 Clock Timing
Tables and figures provided in this section define timing requirements and switching characteristics for clock
signals.
Table 7-14. Clock Timng Requiements
see Figure 7-12
NO.
MIN
10
MAX UNIT
CLK1 tc(EXT_REFCLK1)
CLK2 tw(EXT_REFCLK1H)
CLK3 tw(EXT_REFCLK1L)
Cycle time minimum, EXT_REFCLK1
ns
Pulse Duration minimum, EXT_REFCLK1 high
Pulse Duration minimum, EXT_REFCLK1 low
E*0.45(1)
E*0.45(1)
E*0.55(1)
E*0.55(1)
ns
ns
(1) E = EXT_REFCLK1 cycle time
Figure 7-12. Clock Timing Requirements
Table 7-15. Clock Switching Characteristics
see Figure 7-13
NO.
PARAMETER
MIN
8
MAX UNIT
CLK4 tc(SYSCLKOUT0)
CLK5 tw(SYSCLKOUT0H)
CLK6 tw(SYSCLKOUT0L)
CLK7 tc(OBSCLK0)
Cycle time minimum,SYSCLKOUT0
Pulse Duration minimum, SYSCLKOUT0 high
Pulse Duration minimum, SYSCLKOUT0 low
Cycle time minimum, OBSCLK0
ns
A*0.4(1)
A*0.4(1)
5
A*0.6(1)
ns
ns
ns
ns
ns
ns
ns
ns
A*0.6(1)
CLK8 tw(OBSCLK0H)
CLK9 tw(OBSCLK0L)
CLK10 tc(CLKOUT0)
Pulse Duration minimum, OBSCLK0 high
Pulse Duration minimum,OBSCLK0 low
Cycle time minimum, CLKOUT0
B*0.45(2)
B*0.45(2)
20
B*0.55(2)
B*0.55(2)
CLK11 tw(CLKOUT0H)
CLK12 tw(CLKOUT0L)
Pulse Duration minimum, CLKOUT0 high
Pulse Duration minimum,CLKOUT0 low
C*0.4(3)
C*0.4(3)
C*0.6(3)
C*0.6(3)
(1) A = SYSCLKOUT0 cycle time
(2) B = OBSCLK0 cycle time
(3) C = CLKOUT0 cycle time
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Figure 7-13. Clock Switching Characteristics
7.10.4 Clock Specifications
7.10.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
•
MCU_OSC0_XO/MCU_OSC0_XI — Еxternal main crystal interface pins connected to internal oscillator
which sources reference clock and provides reference clock to PLLs within MAIN domain.
General purpose clock inputs
•
– MCU_EXT_REFCLK0 — optional external. Provides system clock input (MCU domain).
– EXT_REFCLK1 — optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and
MCASP can be sourced by EXT_REFCLK1 (sourced externally).
– SERDES0_REFCLK0P/N — SerDes reference clock input for PCIe or Optional USB3.0 interfaces.
External CPTS reference clock inputs
•
– CP_GEMAC_CPTS0_RFT_CLK — CPTS reference clock inputs for CP_GEMAC_CPTS0_RFT_CLK.
– CPTS_RFT_CLK — CPTS reference clock inputs for CPTS_RFT_CLK.
Figure 7-14 shows the external input clock sources and the output clocks to peripherals.
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DEVICE
Reference clock output
CLKOUT
Selects Main PLL output divide-by-6
Optional pins to provide reference clock input to the PLLs.
SYSCLKOUT0
MCU_SYSCLKOUT0
MCU_OSC0_XI
MCU_OSC0_XO
External main crystal interface pins connected to internal oscillator
which provides reference clock to PLLs within MCU domain
and MAIN domain.
JTAG Clock Input
TCK
MCU Warm Reset Input / Device Warm Reset Input
MCU_RESETz
MCU_PORz
MCU Power ON Reset / Device Power ON Reset
Boot Mode Configuration / devices select
DDR Differential Clock outputs
BOOTMODE[15:00]
DDR0_CK0/DDR0_CK0_n
SERDES0_REFCLK0P/N
SerDes reference clock input for PCIe or Optional USB3.0 interfaces
Observation clock outputs for MCU Domain clock / MAIN Domain clocks
Optional external System clock inputs - (MCU domain) / (MAIN domain)
MCU_OBSCLK0 / OBSCLK0
MCU_EXT_REFCLK0 / EXT_REFCLK1
CPTS reference clock input for
CP_GEMAC_CPTS0_RFT_CLK / MCU_CPTS_RFT_CLK
CP_GEMAC_CPTS0_RFT_CLK /
CPTS0_RFT_CLK
J7ES_CLOCK_01
Figure 7-14. Input Clocks Interface
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.
7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
Figure 7-15 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit should be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.
Device
MCU_OSC0_XO
MCU_OSC0_XI
Crystal
CL2
CL1
PCB Ground
AM65x_MCU_OSC_INT_01
Figure 7-15. MCU_OSC0 Crystal Implementation
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The crystal must be in the fundamental mode of operation and parallel resonant. Table 7-16 summarizes the
required electrical constraints.
Table 7-16. MCU_OSC0 Crystal Circuit Requirements
PARAMETER
Fxtal
MIN
TYP
25
MAX UNIT
MHz
Crystal Parallel Resonance Frequency
Crystal Frequency Stability and Tolerance
Fxtal
Ethernet RGMII and RMII
not used
±100
ppm
Ethernet RGMII and RMII
using derived clock
±50
CL1+PCBXI
CL2+PCBXO
CL
Capacitance of CL1 + CPCBXI
Capacitance of CL2 + CPCBXO
Crystal Load Capacitance
12
12
6
24
24
12
7
pF
pF
pF
pF
pF
pF
Ω
Cshunt
Crystal Circuit Shunt Capacitance
ESRxtal = 30 Ω
25 MHz
25 MHz
25 MHz
ESRxtal = 40 Ω
ESRxtal = 50 Ω
5
5
ESRxtal
Crystal Effective Series Resistance
100
When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
Table 7-17 details the switching characteristics of the oscillator.
Table 7-17. MCU_OSC0 Switching Characteristics - Crystal Mode
PARAMETER
MIN
TYP
MAX UNIT
TBD
CXI
XI Capacitance
pF
pF
pF
ms
CXO
CXIXO
ts
XO Capacitance
TBD
XI to XO Mutual Capacitance
Start-up Time
TBD
4
VDD_MCU (min.)
VDD_MCU
VSS
VDDS_OSC0 (min.)
VDDS_OSC0
MCU_OSC0_XO
tsX
VSS
Time
AM65x_MCU_OSC_STARTUP_02
Figure 7-16. MCU_OSC0 Start-up Time
7.10.4.1.1.1 Load Capacitance
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1,
CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB
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designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits and
device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 7-17.
Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CL1
CPCBXI
CXI
CL2
CPCBXO
CXO
MCU_OSC0_XO
AM65x_MCU_OSC_CC_05
Figure 7-17. Load Capacitance
Load capacitors, CL1 and CL2 in Figure 7-15, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5
pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF
7.10.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in Table 7-16. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 7-17.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
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Device
Crystal Circuit
Components
PCB
Signal Traces
MCU_OSC0_XI
CPCBXIXO
CXIXO
CO
MCU_OSC0_XO
AM65x_MCU_OSC_SC_06
Figure 7-18. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,
CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.
7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
Figure 7-19 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V
LVCMOS square-wave digital clock source.
Note
A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This
is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that may enter a
unknown state when DC is applied to the input. Therefore, application software should power down
MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.
Device
MCU_OSC0_XO
MCU_OSC0_XI
PCB Ground
AM65x_MCU_OSC_EXT_CLK_03
Figure 7-19. 1.8-V LVCMOS-Compatible Clock Input
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7.10.4.2 Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
•
MCU_SYSCLKOUT0
– SYSCLK0 of from the MCU_PLL controller is divided by 6 and then sent out of the device as a LVCMOS
clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the MCU chip clock is functioning or
not.
•
•
MCU_OBSCLK0
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
SYSCLKOUT0
– SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS
clock signal (SYSCLKOUT0). This signal can be used to test if the MAIN chip clock is functioning or not.
•
•
CLKOUT0
– Reference clock output
OBSCLK0
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
7.10.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from
off-chip power-sources.
There is one PLL in the MCU domain:
•
MCU0_PLL
There are six PLLs in the MAIN domain:
•
•
•
•
ARM0_PLL
MAIN_PLL
PER0_PLL
PER1_PLL
•
•
DDR PLL
R5F PLL
Note
For more information, see:
•
•
Device Configuration / Clocking / PLLs section in the device TRM.
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit
(PRU_ICSSG) section in the device TRM.
Note
The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is
ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.
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7.10.5 Peripherals
7.10.5.1 CPSW3G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
7.10.5.1.1 CPSW3G MDIO Timing
Table 7-18, Table 7-19, Table 7-20, and Figure 7-20 present timing conditions, requirements, and switching
characteristics for CPSW3G MDIO.
Table 7-18. CPSW3G MDIO Timing Conditions
PARAMETER
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
470
Table 7-19. CPSW3G MDIO Timing Requirements
see Figure 7-20
NO.
PARAMETER
MIN
90
0
MAX
UNIT
ns
MDIO1 tsu(MDIO_MDC)
MDIO2 th(MDC_MDIO)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
ns
Table 7-20. CPWS3G MDIO Switching Characteristics
see Figure 7-20
NO.
PARAMETER
MIN
400
160
160
-150
MAX
UNIT
ns
MDIO3 tc(MDC)
Cycle time, MDIO[x]_MDC
MDIO4 tw(MDCH)
MDIO5 tw(MDCL)
MDIO7 td(MDC_MDIO)
Pulse Duration, MDIO[x]_MDC high
Pulse Duration, MDIO[x]_MDC low
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
ns
ns
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-20. CPSW3G MDIO Timing Requirements and Switching Characteristics
7.10.5.1.2 CPSW3G RMII Timing
Table 7-21, Table 7-22, Figure 7-21, Table 7-23, Figure 7-22 Table 7-24, and Figure 7-23 present timing
conditions, requirements, and switching characteristics for CPSW3G RMII.
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MAX UNIT
Table 7-21. CPSW3G RMII Timing Conditions
PARAMETER
MIN
INPUT CONDITIONS
VDDSHVx(1) = 1.8V
VDDSHVx(1) = 3.3V
0.18
0.4
0.54 V/ns
1.2 V/ns
SRI
Input slew rate
OUTPUT CONDITIONS
CL Output load capacitance
3
25
pF
(1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Section 6.2 for more information on IO power rail assinments.
Table 7-22. RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 7-21
NO.
PARAMETER
tc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)
DESCRIPTION
Cycle time, RMII[x]_REF_CLK
MIN
MAX
20.001
13
UNIT
ns
RMII1
RMII2
RMII3
19.999
Pulse Duration, RMII[x]_REF_CLK High
Pulse Duration, RMII[x]_REF_CLK Low
7
7
ns
13
ns
RMII1
RMII2
RMII[x]_REF_CLK
RMII3
Figure 7-21. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode
Table 7-23. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
see Figure 7-22
NO.
PARAMETER
DESCRIPTION
MIN
4
MAX
UNIT
ns
RMII4
tsu(RXD-REF_CLK)
Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK
Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK
Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK
Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK
Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK
Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
4
ns
4
ns
RMII5
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
2
ns
2
ns
RMII4
RMII5
RMII[x]_REF_CLK
RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER
Figure 7-22. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII
Mode
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Table 7-24. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
see Figure 7-23
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII6 td(REF_CLK-TXD)
Delay time, RMII[x]_REF_CLK High to RMII[x]_
TXD[1:0] valid
2
10
ns
td(REF_CLK-TX_EN)
Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN
valid
2
10
ns
RMII6
RMII[x]_REF_CLK
RMII[x]_TXD[1:0], RMII[x]_TX_EN
Figure 7-23. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
7.10.5.1.3 CPSW3G RGMII Timing
Table 7-25, Table 7-26, Table 7-27, Figure 7-24, Table 7-28, Table 7-29, and Figure 7-25 present timing
conditions, requirements, and switching characteristics for CPSW3G RGMII.
Table 7-25. CPSW3G RGMII Timing Conditions
PARAMETER
MIN
2.64
2
MAX UNIT
INPUT CONDITIONS
SRI
Input slew rate
5
V/ns
pF
OUTPUT CONDITIONS
CL
Output load capacitance
20
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0],
RGMII[x]_RX_CTL
50
50
ps
ps
td(Trace Mismatch
Propagation delay mismatch across all traces
Delay)
RGMII[x]_TXC,
RGMII[x]_TD[3:0],
RGMII[x]_TX_CTL
Table 7-26. RGMII[x]_RXC Timing Requirements – RGMII Mode
see Figure 7-24
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_RXC
MODE
10Mbps
MIN
360
36
MAX UNIT
RGMII1 tc(RXC)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
RGMII2 tw(RXCH)
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
RGMII3 tw(RXCL)
100Mbps
1000Mbps
3.6
4.4
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Table 7-27. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode
see Figure 7-24
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1
MAX UNIT
RGMII4 tsu(RD-RXC)
Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC
high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
RGMII5 th(RXC-RD)
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
10Mbps
1
1
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
1
100Mbps
1000Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
Figure 7-24. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII
Mode
Table 7-28. RGMII[x]_TXC Switching Characteristics – RGMII Mode
see Figure 7-25
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_TXC
MODE
10Mbps
MIN
360
36
MAX UNIT
RGMII6 tc(TXC)
RGMII7 tw(TXCH)
RGMII8 tw(TXCL)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
7.2
160
16
8.8
240
24
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
100Mbps
1000Mbps
10Mbps
3.6
160
16
4.4
240
24
100Mbps
1000Mbps
3.6
4.4
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Table 7-29. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
see Figure 7-25
NO.
PARAMETER
DESCRIPTION
MODE
10Mbps
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX UNIT
RGMII9 tosu(TD-TXC)
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
1000Mbps
10Mbps
tosu(TX_CTL-TXC)
Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC
high/low
100Mbps
1000Mbps
10Mbps
RGMII10 toh(TXC-TD)
Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC
high/low
100Mbps
1000Mbps
10Mbps
toh(TXC-TX_CTL)
Output hold time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
100Mbps
1000Mbps
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
Figure 7-25. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics
- RGMII Mode
7.10.5.2 DDRSS
For more details about features and additional description information on the device (LP)DDR4 Memory
Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Table 7-30 and Figure 7-26 present switching characteristics for DDRSS.
Table 7-30. DDRSS Switching Characteristics
see Figure 7-26
NO.
PARAMETER
DDR TYPE
LPDDR4
DDR4
MIN
1.25
1.25
MAX UNIT
20
ns
ns
tc(DDR_CKP/
1
Cycle time, DDR_CKP and DDR_CKN
DDR_CKN)
1.6
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1
DDR0_CKP
DDR0_CKN
Figure 7-26. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
7.10.5.3 ECAP
Table 7-31, Table 7-32, Figure 7-27, Table 7-33, and Figure 7-28 present timing conditions, requirements, and
switching characteristics for ECAP.
Table 7-31. ECAP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-32. ECAP Timing Requirements
see Figure 7-27
NO.
PARAMETER
DESCRIPTION
Pulse duration, CAP (asynchronous)
MIN
2 + 2P(1)
MAX
UNIT
CAP1 tw(CAP)
ns
(1) P = sysclk period in ns.
CAP1
CAP
EPERIPHERALS_TIMNG_01
Figure 7-27. ECAP Timings Requirements
Table 7-33. ECAP Switching Characteristics
see Figure 7-28
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
CAP2 tw(APWM)
Pulse duration, APWMx high/low
-2 + 2P(1)
ns
(1) P = sysclk period in ns.
CAP2
APWM
EPERIPHERALS_TIMNG_02
Figure 7-28. ECAP Switching Characteristics
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
7.10.5.4 EPWM
Table 7-34, Table 7-35, Figure 7-29, Table 7-36, Figure 7-30, Figure 7-31, and Figure 7-32 present timing
conditions, requirements, and switching characteristics for EPWM.
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Table 7-34. EPWM Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-35. EPWM Timing Requirements
see Figure 7-29
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_SYNCI
MIN
2 + 2P(1)
2 + 3P(1)
MAX
UNIT
ns
PWM6 tw(SYNCIN)
PWM7 tw(TZ)
Pulse duration, EHRPWM_TZn_IN low
ns
(1) P = sysclk period in ns.
PWM6
EHRPWM_SYNCI
PWM7
EHRPWM_TZn_IN
EPERIPHERALS_TIMNG_07
Figure 7-29. EPWM Timing Requirements
Table 7-36. EPWM Switching Characteristics
see Figure 7-30, Figure 7-31, and Figure 7-32
NO.
PARAMETER
DESCRIPTION
Pulse duration, EHRPWM_A/B high/low
Pulse duration, EHRPWM_SYNCO
MIN
P - 3(1)
P - 3(1)
MAX
UNIT
PWM1 tw(PWM)
ns
ns
ns
PWM2 tw(SYNCOUT)
PWM3 td(TZ-PWM)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced
high/low
11
11
PWM4 td(TZ-PWMZ)
PWM5 tw(SOC)
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z
Pulse duration, EHRPWM_SOCA/B output
ns
ns
P - 3(1)
(1) P = sysclk period in ns.
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PWM1
EHRPWM_A/B
PWM1
PWM2
EHRPWM_SYNCO
PWM5
EHRPWM_SOCA/B
EPERIPHERALS_TIMNG_04
Figure 7-30. EHRPWM Switching Characteristics
PWM3
EHRPWM_A/B
EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05
Figure 7-31. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics
PWM4
EHRPWM_A/B
EHRPWM_TZn_IN
Figure 7-32. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
7.10.5.5 EQEP
Table 7-37, Table 7-38, Figure 7-33, and Table 7-39 present timing conditions, requirements, and switching
characteristics for EQEP.
Table 7-37. EQEP Timing Conditions
PARAMETER
MIN
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
Table 7-38. EQEP Timing Requirements
see
NO.
PARAMETER
DESCRIPTION
MIN
2 + 2P(1)
2 + 2P(1)
MAX
UNIT
ns
QEP1
QEP2
tw(QEP)
Pulse duration, QEP_A/B
Pulse duration, QEP_I high
tw(QEPIH)
ns
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Table 7-38. EQEP Timing Requirements (continued)
see
NO.
PARAMETER
tw(QEPIL)
tw(QEPSH)
tw(QEPSL)
DESCRIPTION
Pulse duration, QEP_I low
MIN
2 + 2P(1)
2 + 2P(1)
2 + 2P(1)
MAX
UNIT
ns
QEP3
QEP4
QEP5
Pulse duration, QEP_S high
ns
Pulse duration, QEP_S low
ns
(1) P = sysclk period in ns
QEP1
QEP_A/B
QEP2
QEP_I
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
Figure 7-33. EQEP Timing Requirements
Table 7-39. EQEP Switching Characteristics
NO.
PARAMETER
td(QEP-CNTR)
DESCRIPTION
MIN
MAX
UNIT
QEP6
Delay time, external clock to counter increment
24
ns
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
7.10.5.6 FSI
Table 7-40, Table 7-41, Figure 7-34, Table 7-42, Figure 7-35, Table 7-43, and Figure 7-36 present timing
conditions, requirements, and switching characteristics for FSI.
Table 7-40. FSI Timing Conditions
PARAMETER
MIN
0.8
1
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
Table 7-41. FSI Timing Requirements
see Figure 7-34
NO.
MIN
MAX
UNIT
ns
FSIR1 tc(RX_CLK)
Cycle time, FSI_RXn_CLK
20
FSIR2 tw(RX_CLK)
Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high
Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK
Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK
0.5P - 1(1) 0.5P + 1(1)
ns
FSIR3 tsu(RX_D-RX_CLK)
FSIR4 th(RX_CLK-RX_D)
3
ns
2.5
ns
(1) P = FSI_RXn_CLK period in ns.
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FSIR1
FSIR2
FSIR2
FSI_RXn_CLK
FSI_RXn_D0
FSI_RXn_D1
FSIR3
FSIR4
Figure 7-34. FSI Timing Requirements
Table 7-42. FSI Switching Characteristics - FSI Mode
see Figure 7-35
NO.
PARAMETER
MODE
MIN
20
0.5p + 1(1)
0.25P - 2(1)
MAX UNIT
FSIT1 tc(TX_CLK)
Cycle time, FSI_TXn_CLK
FSI Mode
FSI Mode
FSI Mode
ns
FSIT2 tw(TX_CLK)
FSIT3 td(TX_CLK-TX_D)
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high
0.5P - 1(1)
ns
ns
Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK
high or FSI_TXn_CLK low
0.25P +
2.5(1)
(1) P = FSI_TXn_CLK period in ns.
FSIT1
FSIT2
FSIT2
FSI_TXn_CLK
FSI_TXn_D0
FSI_TXn_D1
FSIT3
Figure 7-35. FSI Switching Characteristics - FSI Mode
Table 7-43. FSI Switching Characteristics - SPI Mode
see Figure 7-36
NO.
PARAMETER
MODE
MIN
20
0.5P + 1(1)
MAX UNIT
FSIT4 tc(TX_CLK)
FSIT5 tw(TX_CLK)
Cycle time, FSI_TXn_CLK
SPI Mode
SPI Mode
SPI Mode
SPI Mode
SPI Mode
ns
Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high
0.5P - 1(1)
ns
ns
ns
ns
FSIT6 td(TX_CLKH-TX_D0) Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid
3
FSIT7 td(TX_D1-TX_CLK)
FSIT8 td(TX_CLK-TX_D1)
Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high
Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high
P - 3(1)
P - 2(1)
(1) P = FSI_TXn_CLK period in ns.
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FSIT4
FSIT5
FSIT5
FSI_TXn_CLK
FSIT6
FSI_TXn_D0
FSI_TXn_D1
FSIT8
FSIT7
Figure 7-36. FSI Switching Characteristics - SPI Mode
For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.
7.10.5.7 GPIO
Table 7-44, Table 7-45, and Table 7-46 present timing conditions, requirements, and switching characteristics for
GPIO.
For more details about features and additional description information on the device GPIO, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Note
The device has multiple GPIO modules. GPIOn_x is generic name used to describe a GPIO signal,
where n represents the specific GPIO module and x represents one of the input/output signals
associated with the module.
Table 7-44. GPIO Timing Conditions
PARAMETER
BUFFER TYPE
MIN
MAX UNIT
INPUT CONDITIONS
LVCMOS
0.75
TBD
6.6 V/ns
SRI
Input slew rate
I2C OD FS
TBD V/ns
OUTPUT CONDITIONS
LVCMOS
3
3
10
pF
pF
CL
Output load capacitance
I2C OD FS
100
Table 7-45. GPIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
BUFFER TYPE
MIN
MAX UNIT
LVCMOS
2P + 2.6(1)
2P + 2.6(1)
ns
ns
GPIO1 tw(GPIO_IN)
Pulse width, GPIOn_x
I2C OD FS
(1) P = functional clock period in ns.
Table 7-46. GPIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
BUFFER TYPE
MIN
MAX UNIT
-3.6 +
LVCMOS
ns
ns
0.975P(1)
GPIO2 tw(GPIO_OUT)
Pulse width, GPIOn_x
I2C OD FS
160
(1) P = functional clock period in ns.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
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7.10.5.8 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
Section 7.10.5.8.1.1 and Section 7.10.5.8.1.2 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-37 through Figure 7-41).
7.10.5.8.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
MIN
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
Setup time, input data
GPMC_AD[15:0] valid before output
clock GPMC_CLK high
MODE(2)
UNIT
100 MHz
133 MHz
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.81
1.11
ns
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
1.06
1.78
1.78
1.81
1.06
1.78
1.78
3.50
2.28
1.78
1.11
3.50
2.28
1.78
ns
ns
ns
ns
ns
ns
ns
Hold time, input data
GPMC_AD[15:0] valid after output
clock GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Setup time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GPMC_WAIT[j] valid before output
clock GPMC_CLK high(1)
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Hold time, input wait
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GPMC_WAIT[j] valid after output
clock GPMC_CLK high(1)
not_div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(1) In GPMC_WAIT[j], j is equal to 0 or 1.
(2) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
For not_div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
•
–
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
•
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
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7.10.5.8.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
MIN
100 MHz
10.00
MAX
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(18)
UNIT
(2)
133 MHz
F0 1 / tc(clk)
F1 tw(clkH)
F1 tw(clkL)
tdc(clk)
Period, output clock GPMC_CLK(16)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
7.52
ns
Typical pulse duration, output clock
GPMC_CLK high
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-0.3+0.
-0.3+0.
ns
ns
475*P
475*P
(14)
(14)
Typical pulse duration, output clock
GPMC_CLK low
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-0.3+0.
-0.3+0.
475*P
475*P
(14)
(14)
Duty cycle error, output clock
GPMC_CLK
div_by_1_mode;
GPMC_FCLK_MUX;
-500.00 500.00 -500.00 500.00 ps
TIMEPARAGRANULARITY_X1
tJ(clk)
Jitter standard deviation, output clock
GPMC_CLK(17)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
33.33
2.00
2.00
2.00
2.00
33.33 ps
2.00 ns
2.00 ns
2.00 ns
2.00 ns
tR(clk)
Rise time, output clock GPMC_CLK
Fall time, output clock GPMC_CLK
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
tF(clk)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
tR(do)
Rise time, output data
GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
tF(do)
Fall time, output data
GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F2 td(clkH-csnV)
Delay time, output clock GPMC_CLK
rising edge to output chip select
GPMC_CSn[i] transition(13)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+F 3.75+F -2.2+F 3.75+F ns
(5)
(5)
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK
rising edge to output chip select
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+E 1.3089 -2.2+E 4.5+E ns
(4)
(4)
027178
0544+E
GPMC_CSn[i] invalid(13)
F4 td(aV-clk)
Delay time, output address
GPMC_A[27:1] valid to output clock
GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+B 4.5+B -2.3+B 4.5+B ns
(2)
(2)
F5 td(clkH-aIV)
Delay time, output clock GPMC_CLK
rising edge to output address
GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.30
4.50
-2.30
4.50 ns
F6 td(be[x]nV-clk)
Delay time, output lower byte enable
and command latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
-2.3+B 1.9+B -2.3+B 1.9+B ns
(2)
(2)
GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1
enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK
rising edge to output lower byte
div_by_1_mode;
GPMC_FCLK_MUX;
-2.3+D 1.9+D -2.3+D 1.9+D ns
(3)
(3)
enable and command latch enable
TIMEPARAGRANULARITY_X1
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid(10)
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D -2.3+D 1.9+D ns
(3)
(3)
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MIN
MAX
MIN
MAX
UNIT
NO.
PARAMETER
DESCRIPTION
MODE(18)
(2)
100 MHz
133 MHz
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
invalid(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D -2.3+D 1.9+D ns
(3)
(3)
F8 td(clkH-advn)
F9 td(clkH-advnIV)
F10 td(clkH-oen)
F11 td(clkH-oenIV)
F14 td(clkH-wen)
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+G 4.5+G -2.3+G 4.5+G ns
(6)
(6)
GPMC_ADVn_ALE transition
Delay time, output clock GPMC_CLK
rising edge to output address valid
and address latch enable
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+D 4.5+D -2.3+D 4.5+D ns
(3)
(3)
GPMC_ADVn_ALE invalid
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3H 3.5+H -2.3+H 3.5+H ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output enable
GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+E 3.5+E -2.3+E 3.5+E ns
(7)
(7)
Delay time, output clock GPMC_CLK
rising edge to output write enable
GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+I
4.5+I -2.3+I
4.5+I ns
(8)
(8)
F15 td(clkH-do)
F15 td(clkL-do)
F15 td(clkL-do).
F17 td(clkH-be[x]n)
Delay time, output clock GPMC_CLK
rising edge to output data
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J
2.7+J ns
2.7+J ns
2.7+J ns
1.9+J ns
(9)
(9)
GPMC_AD[15:0] transition(10)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J
(9)
(9)
Delay time, GPMC_CLK falling edge
to GPMC_AD[15:0] data bus
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J -2.3+J
(9)
(9)
Delay time, output clock GPMC_CLK
rising edge to output lower byte
enable and command latch enable
GPMC_BE0n_CLE transition(10)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
(9)
(9)
F17 td(clkL-be[x]n)
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(11)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
1.9+J ns
1.9+J ns
(9)
(9)
F17 td(clkL-be[x]n).
Delay time, GPMC_CLK falling edge
to GPMC_BE0n_CLE, GPMC_BE1n
transition(12)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J -2.3+J
(9)
(9)
F18 tw(csnV)
Pulse duration, output chip select
GPMC_CSn[i] low(13)
Read
Write
Read
Write
0+A
0+A
0+C
0+C
0+A
0+A
0+C
0+C
ns
ns
ns
ns
F19 tw(be[x]nV)
Pulse duration, output lower byte
enable and command latch enable
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low
F20 tw(advnV)
Pulse duration, output address valid
and address latch enable
GPMC_ADVn_ALE low
Read
Write
0+K
0+K
0+K
0+K
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(15)
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
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For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)
(5) For csn falling edge (CS activated):
•
•
Case GPMCFCLKDIVIDER = 0:
F = 0.5 × CSExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
–
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
F = 0.5 × CSExtraDelay × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(15) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For ADV falling edge (ADV activated):
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
•
Case GPMCFCLKDIVIDER = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
G = 0.5 × ADVExtraDelay × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(15) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
–
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–
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
H = 0.5 × OEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
–
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
H = 0.5 × OEExtraDelay × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(15) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For WE falling edge (WE activated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK(15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
For WE rising edge (WE deactivated):
•
Case GPMCFCLKDIVIDER = 0:
I = 0.5 × WEExtraDelay × GPMC_FCLK (15)
Case GPMCFCLKDIVIDER = 1:
–
•
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
–
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) otherwise
•
Case GPMCFCLKDIVIDER = 2:
–
–
–
I = 0.5 × WEExtraDelay × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(15) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) J = GPMC_FCLK(15)
(10) First transfer only for CLK DIV 1 mode.
(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(16) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(17) The jitter probability density can be approximated by a Gaussian function.
(18) For div_by_1_mode:
•
GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
•
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
•
•
GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
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•
•
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
GPMC_A[MSB:1]
Valid Address
F7
F19
F19
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F20
F9
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F12
D 0
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_01
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-37. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
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F1
F0
F1
GPMC_CLK
GPMC_CSn[i]
GPMCA[MSB:1]
F2
F3
F4
F6
Valid Address
F7
GPMC_BE0n_CLE
GPMC_BE1n
F7
F9
F6
F8
F8
GPMC_ADVn_ALE
GPMC_OEn_REn
F10
F11
F13
F13
F12
D 0
F22
F12
D 3
GPMC_AD[15:0]
GPMC_WAIT[j]
D 1
D 2
F21
GPMC_02
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-38. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
F1
F1
F0
GPMC_CLK
GPMC_CSn[i]
F2
F3
F4
F6
Valid Address
GPMC_A[MSB:1]
F17
F17
F17
F17
F17
F17
GPMC_BE0n_CLE
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
GPMC_WEn
F14
F14
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
GPMC_WAIT[j]
D 0
D 3
GPMC_03
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
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B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-39. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[i]
F6
F6
F4
F7
GMPC_BE0n_CLE
Valid
F7
Valid
GPMC_BE1n
GPMC_A[27:17]
Address (MSB)
F5
F12
F13
F4
F12
GPMC_AD[15:0]
Address (LSB)
D0
D1
D2
D3
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
GPMC_WAIT[j]
GPMC_04
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-40. GPMC and Multiplexed NOR Flash — Synchronous Burst Read
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F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[i]
F4
F6
F6
GPMC_A[27:17]
Address (MSB)
F17
F17
F17
F17
F17
F17
GPMC_BE1n
BPMC_BE0n_CLE
F8
F8
F20
F9
GPMC_ADVn_ALE
F14
F14
GPMC_WEn
F15
D 1
F15
D 2
F15
GPMC_AD[15:0]
Address (LSB)
D 0
D 3
F22
F21
GPMC_WAIT[j]
GPMC_05
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-41. GPMC and Multiplexed NOR Flash — Synchronous Burst Write
7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
Section 7.10.5.8.2.1 and Section 7.10.5.8.2.2 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-42 through Figure 7-47).
7.10.5.8.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
FA5(1) tacc(d)
Data access time
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
FA2 tacc1-pgmode(d)
0(2)
Page mode successive data access time
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
P(3) ns
FA2 tacc2-pgmode(d)
1(1)
div_by_1_mode;
GPMC_FCLK_MUX;
H(4) ns
TIMEPARAGRANULARITY_X1
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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7.10.5.8.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
MIN
MAX
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
133 MHz
tR(d)
Rise time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.00 ns
2.00 ns
tF(d)
Fall time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA0 tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
Write
0+N (12) ns
0+N (12)
FA1 tw(csnV)
Pulse duration, output chip select GPMC_CSn[i](13)
low
Read
Write
Read
Write
0+A (1) ns
0+A (1)
FA3 td(csnV-advnIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
-2+B (2)
-2+B (2)
2+B (2) ns
2+B (2)
FA4 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+C (3)
-2+J (9)
-2+J (9)
2+C (3) ns
2+J (9) ns
2+J (9) ns
FA9 td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA10 td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA12 td(csnV-advnV)
FA13 td(csnV-oenV)
FA16 tw(aIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+K (10) 2+K (10) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+L (11) 2+L (11) ns
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0+G (7)
-2+I (8)
0+D (4)
-2+E (5)
-2+F (6)
ns
2+I (8) ns
ns
FA18 td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA20 tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA25 td(csnV-wenV)
FA27 td(csnV-wenIV)
FA28 td(wenV-dV)
FA29 td(dV-csnV)
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2+E (5) ns
2+F (6) ns
2.00 ns
2+J (9) ns
Delay time, output chip select GPMC_CSn[i](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[i](13) valid
div_by_1_mode;
GPMC_FCLK_MUX;
-2+J (9)
TIMEPARAGRANULARITY_X1
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MAX
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MIN
NO. PARAMETER
DESCRIPTION
MODE(15)
UNIT
133 MHz
FA37 td(oenV-aIV)
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX;
2.00 ns
TIMEPARAGRANULARITY_X1
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
•
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
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GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data IN 0
Data IN 0
GPMC_WAIT[j]
GPMC_06
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-42. GPMC and NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA5
FA5
FA1
FA1
GPMC_CSn[i]
FA16
FA9
FA9
Address 0
FA0
Address 1
FA0
GPMC_A[MSB:1]
FA10
FA10
FA10
Valid
FA0
Valid
FA0
GPMC_BE0n_CLE
GPMC_BE1n
Valid
Valid
FA10
FA3
FA3
FA12
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[j]
GPMC_07
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-43. GPMC and NOR Flash — Asynchronous Read — 32–Bit
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GPMC_FCLK
GPMC_CLK
FA20
FA20
Add1
FA21
FA20
Add2
FA1
GPMC_CSn[i]
FA9
Add0
Add3
Add4
GPMC_A[MSB:1]
FA0
FA10
FA10
GPMC_BE0n_CLE
FA0
GPMC_BE1n
FA12
GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D0
D1
D2
D3
GPMC_WAIT[j]
GPMC_08
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input
page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-44. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1]
GPMC_BE0n_CLE
GPMC_BE1n
Valid Address
FA0
FA10
FA10
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
GPMC_AD[15:0]
GPMC_WAIT[j]
FA29
Data OUT
GPMC_09
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-45. GPMC and NOR Flash — Asynchronous Write — Single Word
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GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
Address (MSB)
FA0
GPMC_A[27:17]
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
Valid
FA0
Valid
FA3
FA12
GPMC_ADVn_ALE
GPMC_OEn_REn
FA4
FA13
FA29
FA37
Data IN
Data IN
Address (LSB)
GPMC_AD[15:0]
GPMC_WAIT[j]
GPMC_10
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 7-46. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[i]
GPMC_A[27:17]
FA9
Address (MSB)
FA0
FA10
FA10
GPMC_BE0n_CLE
GPMC_BE1n
FA0
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29
FA28
GPMC_AD[15:0]
Valid Address (LSB)
Data OUT
GPMC_WAIT[j]
GPMC_11
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-47. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word
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7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
Section 7.10.5.8.3.1 and Section 7.10.5.8.3.2 assume testing over the recommended operating conditions and
electrical characteristic conditions below (see Figure 7-48 through Figure 7-51).
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
7.10.5.8.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
MIN
MAX
NO.
PARAMETER
DESCRIPTION
MODE(4)
UNIT
133 MHz
GNF12(1) tacc(d)
Access time, input data GPMC_AD[15:0](3)
div_by_1_mode;
GPMC_FCLK_MUX;
J(2) ns
TIMEPARAGRANULARITY_X1
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
•
For TIMEPARAGRANULARITY_X1:
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
7.10.5.8.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
NO.
PARAMETER
MODE(3)
MIN
MAX UNIT
tR(d)
Rise time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
2.00 ns
TIMEPARAGRANULARITY_X1
tF(d)
Fall time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
2.00 ns
TBD ns
2+B ns
2+C ns
2+D ns
2+E ns
2+F ns
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
0+A
-2+B
-2+C
-2+D
-2+E
-2+F
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
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NO.
PARAMETER
MODE(3)
MIN
MAX UNIT
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+G
2+G ns
GNF7 tw(aleH-wenV)
GNF8 tw(wenIV-aleIV)
GNF9 tc(wen)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+C
-2+F
2+C ns
2+F ns
0+H ns
2+I ns
0+K ns
ns
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF10 td(csnV-oenV)
Delay time, output chip select GPMC_CSn[i](2)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+I
GNF13 tw(oenV)
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF14 tc(oen)
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX;
0+L
TIMEPARAGRANULARITY_X1
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[i](2)
invalid
div_by_1_mode;
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
-2+M
2+M ns
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(3) For div_by_1_mode:
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
GPMC_CLK frequency = GPMC_FCLK frequency
–
For GPMC_FCLK_MUX:
CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
•
For TIMEPARAGRANULARITY_X1:
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF2
GNF6
GNF5
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF0
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-48. GPMC and NAND Flash — Command Latch Cycle
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GPMC_FCLK
GNF1
GNF7
GNF6
GNF8
GPMC_CSn[i]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GPMC_WEn
GNF9
GNF0
GNF3
GNF4
Address
GPMC_AD[15:0]
GPMC_13
A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-49. GPMC and NAND Flash — Address Latch Cycle
GPMC_FCLK
GPMC_CSn[i]
GNF12
GNF10
GNF15
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
GPMC_WAIT[j]
DATA
GPMC_14
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock
edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
Figure 7-50. GPMC and NAND Flash — Data Read Cycle
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GPMC_FCLK
GPMC_CSn[i]
GNF1
GNF6
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
DATA
GPMC_15
A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
Figure 7-51. GPMC and NAND Flash — Data Write Cycle
7.10.5.9 I2C
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Section 7.10.5.9.1, Table 7-47 and Figure 7-52 assume testing over the recommended operating conditions and
electrical characteristic conditions.
7.10.5.9.1 Timing Requirements for I2C Input Timings
NO.(1) (6) PARAMETER
DESCRIPTION
MODE
Standard
Fast
MIN
10000
2500
4700
600
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I1
I2
I3
I4
I5
I6
I7
I8
I9
tc(SCL)
Cycle time, SCL
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tw(SCLL)
Setup time, SCL high before SDA low (for a repeated START
condition)
Standard
Fast
Hold time, SCL low after SDA low (for a START and a repeated Standard
START condition)
4000
900
Fast
Pulse duration, SCL low
Standard
Fast
4700
1300
4000
600
tw(SCLH)
Pulse duration, SCL high
Standard
Fast
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Standard
Fast
250
100 (2)
0(3)
Standard
Fast
3450(4)
900 (4)
0(3)
Pulse duration, SDA high between STOP and START
conditions
Standard
Fast
4700
1300
tr(SDA)
Rise time, SDA
Standard
Fast
1000
20*(Vdd/ 300 (3)(7)
5.5V)(5)(7)
I10
tr(SCL)
Rise time, SCL
Standard
Fast
1000
20*(Vdd/ 300 (3)(7)
ns
ns
5.5V)(5)(7)
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NO.(1) (6) PARAMETER
DESCRIPTION
MODE
Standard
Fast
MIN
MAX
UNIT
ns
I11
I12
tf(SDA)
Fall time, SDA
300
20*(Vdd/ 300 (3)(7)
ns
5.5V)(5)(7)
tf(SCL)
Fall time, SCL
Standard
Fast
300
ns
ns
20*(Vdd/
5.5V)
300
I13
I14
I15
I16
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be supressed)
Skew
Standard
Fast
4000
600
ns
ns
ns
ns
ns
ns
pF
pF
tw(SP)
Standard
Fast
0
50
3
tskew
Standard
Fast
3
Cb
Capacitive load for each bus line
Standard
Fast
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered
down.
(2) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to
the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed
(6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details.
(7) These timings apply only to I2C0 and MCU_I2C0. I2C[3:1] and MCU_I2C1 use standard LVCMOS buffers to emulate open-drain
buffers and their rise/fall times should be referenced in the device IBIS model.
Table 7-47. Timing Requirements for I2C HS–Mode
NO.
PARAMETER
DESCRIPTION
CAPACITANCE
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
100 pF Max
400 pF Max
MIN
294
588
160
160
160
160
160
320
60
MAX UNIT
I1
tc(SCL)
Cycle time, SCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I2
I3
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tw(SCLL)
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
I4
Pulse duration, SCL low
I5
tw(SCLH)
Pulse duration, SCL high
120
10
I6
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
10
I7
0
70
ns
ns
ns
ns
ns
ns
ns
0
150
I13
I14
I15
Setup time, SCL high before SDA high (for
STOP condition)
160
160 (2)
0
tr(SDA)
Pulse duration, spike (must be suppressed)
10 (2)
tskew
Skew
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Table 7-47. Timing Requirements for I2C HS–Mode (continued)
NO.
PARAMETER
DESCRIPTION
CAPACITANCE
MIN
MAX UNIT
I16
Cb(1)
Capacitive Load for SDA and SCL Lines
100 pF Max
100
400
pF
pF
400 pF Max
(1) For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated.
(2) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
I11
I9
I2C[i]_SDA
I2C[i]_SCL
I8
I6
I14
I4
I13
I5
I10
I12
I1
I3
I7
I2
I3
Stop
Start
Repeated
Start
Stop
A. i = 0 to 1 for MCU domain
i = 0 to 3 for MAIN domain
Figure 7-52. I2C Receive Timing
7.10.5.10 MCAN
Table 7-48 and Table 7-49 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.
Table 7-48. MCAN Timing Conditions
PARAMETER
MIN
2
MAX
15
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
5
20
Table 7-49. MCAN Switching Characteristics
NO.
PARAMETER
DESCRIPTION
Delay time, transmit shift register to MCANn_TX
Delay time, MCANn_RX to receive shift register
MIN
MAX
10
UNIT
ns
MCAN1 td(MCAN_TX)
MCAN2 td(MCAN_RX)
10
ns
For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.
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7.10.5.11 MCSPI
For more details about features and additional description information on the device Serial Port Interface, see
the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-50 presents timing conditions for MCSPI.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
Table 7-50. MCSPI Timing Conditions
PARAMETER
MIN
2
MAX
8.5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
6
12
7.10.5.11.1 MCSPI — Master Mode
Table 7-51, Figure 7-53, Table 7-52, and Figure 7-54 present timing requirements and switching characteristics
for SPI – Master Mode.
Table 7-51. MCSPI Timing Requirements – Master Mode
see Figure 7-53
NO.
SM4
SM5
PARAMETER
tsu(MISO-SPICLK)
th(SPICLK-MISO)
DESCRIPTION
MIN
2.8
3
MAX
UNIT
ns
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
ns
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PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
SPI_SCLK (OUT)
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM5
SM5
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
SPI_SCLK (OUT)
SM1
SM3
POL=1
SPI_SCLK (OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_02
Figure 7-53. SPI Master Mode Receive Timing
Table 7-52. MCSPI Switching Characteristics - Master Mode
see Figure 7-54
NO.
PARAMETER
MIN
MAX UNIT
SM1
SM2
SM3
SM6
SM7
SM8
tc(SPICLK)
Cycle time, SPIn_CLK
20
0.5P - 1(1)
0.5P - 1(1)
ns
ns
ns
tw(SPICLKL)
tw(SPICLKH)
td(SPICLK-SIMO)
td(CS-SIMO)
td(CS-SPICLK)
Pulse duration, SPIn_CLK low
Pulse duration, SPIn_CLK high
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
Delay time, SPIn_CSi active to SPIn_CLK first edge
-3
2.5
ns
ns
ns
ns
ns
ns
5
PHA = 0
PHA = 1
PHA = 0
PHA = 1
B - 4 (3)
A - 4 (2)
A - 4(2)
B - 4(3)
SM9
td(SPICLK-CS)
Delay time, SPIn_CLK last edge to SPIn_CSi inactive
(1) P = SPI_CLK period in ns.
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(2) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A =
(TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.
PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SPI_SCLK (OUT)
SM1
SM3
SM2
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (OUT)
SPI_SCLK (OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
SM1
SM3
SPI_SCLK (OUT)
SPI_D[x] (OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
Figure 7-54. SPI Master Mode Transmit Timing
7.10.5.11.2 MCSPI — Slave Mode
Table 7-53, Figure 7-55, Table 7-54, and Figure 7-56 present timing requirements and switching characteristics
for SPI – Slave Mode.
Table 7-53. MCSPI Timing Requirements – Slave Mode
see Figure 7-55
NO.
SS1
SS2
SS3
SS4
SS5
SS8
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
tc(SPICLK)
Cycle time, SPIn_CLK
20
0.45P(1)
0.45P(1)
tw(SPICLKL)
Pulse duration, SPIn_CLK low
ns
tw(SPICLKH)
Pulse duration, SPIn_CLK high
ns
tsu(SIMO-SPICLK)
th(SPICLK-SIMO)
tsu(CS-SPICLK)
Setup time, SPIn_D[x] valid before SPIn_CLK active edge
Hold time, SPIn_D[x] valid after SPIn_CLK active edge
Setup time, SPIn_CSi valid before SPIn_CLK first edge
5
5
5
ns
ns
ns
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Table 7-53. MCSPI Timing Requirements – Slave Mode (continued)
see Figure 7-55
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SS9
th(SPICLK-CS)
Hold time, SPIn_CSi valid after SPIn_CLK last edge
5
ns
(1) P = SPIn_CLK period in ns.
PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
SPI_SCLK (IN)
SS1
SS2
POL=1
SPI_SCLK (IN)
SS5
SS4
SS5
Bit n-2
SS4
Bit n-1
Bit n-3
Bit n-4
Bit 0
SPI_D[x] (IN)
PHA=1
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
SPI_SCLK (IN)
SS1
SS3
POL=1
SPI_SCLK (IN)
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPI_D[x] (IN)
SPRSP08_TIMING_McSPI_04
Figure 7-55. SPI Slave Mode Receive Timing
Table 7-54. MCSPI Switching Characteristics – Slave Mode
see Figure 7-56
NO.
SS6
SS7
PARAMETER
td(SPICLK-SOMI)
tsk(CS-SOMI)
DESCRIPTION
Delay time, SPIn_CLK active edge to SPIn_D[x]
Delay time, SPIn_CSi active edge to SPIn_D[x]
MIN
2
MAX
UNIT
ns
17.12
20.95
ns
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PHA=0
EPOL=1
SPI_CS[i] (IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
SPI_SCLK (IN)
SS1
SS2
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[i] (IN)
SPI_SCLK (IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
SPI_SCLK (IN)
SPI_D[x] (OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
Figure 7-56. SPI Slave Mode Transmit Timing
7.10.5.12 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 sections within Section 6.3,
Signal Descriptions and Section 8, Detailed Description.
Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 7-55 and Table 7-64.
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
7.10.5.12.1 MMC0 - eMMC Interface
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
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•
•
•
•
Legacy speed
High speed SDR
High speed DDR
HS200
Table 7-55 presents the required DLL software configuration settings for MMC0 timing modes.
Table 7-55. MMC0 DLL Delay Mapping for All Timing Modes
REGISTER NAME
BIT FIELD
MMCSD0_SS_PHY_CTRL_4_REG
MMCSD0_SS_PHY_CTRL_5_REG
[31:24]
[20]
[15:12]
[8]
[4:0]
[17:16]
[10:8]
[2:0]
SELDLYTXCLK
SELDLYRXCLK
BIT FIELD NAME
STRBSEL
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
FRQSEL
CLKBUFSEL
OUTPUT
DELAY
ENABLE
OUTPUT
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DLL
DELAY CHAIN
SELECT
DELAY
BUFFER
DURATION
STROBE
DELAY
DLL REF
FREQUENCY
MODE DESCRIPTION
8-bit PHY
Legacy
operating 1.8 V,
SDR
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
NA
NA
0x1
0x1
0x1
0x1
0x10
0xA
0x1
0x1
0x0
0x0
0x0
0x0
0x4
0x0
0x7
0x7
0x7
0x7
25 MHz
High
8-bit PHY
Speed operating 1.8 V,
SDR
High
50 MHz
8-bit PHY
Speed operating 1.8 V,
0x6
0x7
0x3
DDR
50 MHz
8-bit PHY
HS200 operating 1.8 V,
200 MHz
Tuning
Table 7-56 presents timing conditions for MMC0.
Table 7-56. MMC0 Timing Conditions
PARAMETER
MIN
MAX UNIT
INPUT CONDITIONS
Legacy SDR
0.14
0.3
1.44 V/ns
0.9 V/ns
0.9 V/ns
0.9 V/ns
High Speed SDR
SRI
Input slew rate
High Speed DDR (CMD)
High Speed DDR (DAT[7:0])
0.3
0.45
OUTPUT CONDITIONS
Legacy SDR
1
1
1
1
12
12
12
6
pF
pF
pF
pF
High Speed SDR
CL
Output load capacitance
High Speed DDR
HS200
PCB CONNECTIVITY REQUIREMENTS
All modes
td(Trace Delay)
Propagation delay of each trace
126
756
100
8
ps
ps
ps
Legacy SDR, High Speed SDR
High Speed DDR, HS200
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
7.10.5.12.1.1 Legacy SDR Mode
Table 7-57, Figure 7-57, Table 7-58, and Figure 7-58 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 7-57. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 7-57
NO.
PARAMETER
DESCRIPTION
MIN
9.69
MAX
UNIT
ns
SSDR5 tsu(cmdV-clkH)
SSDR6 th(clkH-cmdV)
SSDR7 tsu(dV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
27.97
9.69
ns
ns
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Table 7-57. MMC0 Timing Requirements – Legacy SDR Mode (continued)
see Figure 7-57
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SSDR8 th(clkH-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
27.97
ns
Figure 7-57. MMC0 – Legacy SDR – Receive Mode
Table 7-58. MMC0 Switching Characteristics – Legacy SDR Mode
see Figure 7-58
NO.
PARAMETER
fop(clk)
tc(clk)
DESCRIPTION
Operating frequency, MMC0_CLK
MIN
MAX
UNIT
MHz
ns
25
SSDR1
Cycle time, MMC0_CLK
40
18.7
SSDR2H tw(clkH)
SSDR2L tw(clkL)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
18.7
ns
SSDR3
SSDR4
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-16.1
-16.1
16.1
16.1
ns
td(clkL-dV)
ns
SSDR2L
SSDR1
SSDR2H
MMC0_CLK
MMC0_CMD
SSDR3
SSDR4
MMC0_DAT[7:0]
J7_MMC0_TIMING_02
Figure 7-58. MMC0 – Legacy SDR – Transmit Mode
7.10.5.12.1.2 High Speed SDR Mode
Table 7-59, Figure 7-59, Table 7-60, and Figure 7-60 present timing requirements and switching characteristics
for MMC0 – High Speed SDR Mode.
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Table 7-59. MMC0 Timing Requirements – High Speed SDR Mode
see Figure 7-59
NO.
PARAMETER
DESCRIPTION
MIN
2.99
2.67
2.99
2.67
MAX
UNIT
ns
HSSDR3 tsu(cmdV-clkH)
HSSDR4 th(clkH-cmdV)
HSSDR7 tsu(dV-clkH)
HSSDR8 th(clkH-dV)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
ns
ns
ns
HSSDR1
HSSDR2H
HSSDR2L
MMC0_CLK
MMC0_CMD
HSSDR3
HSSDR4
HSSDR7
HSSDR8
MMC0_DAT[7:0]
J7_MMC0_TIMING_03
Figure 7-59. MMC0 – High Speed SDR Mode – Receive Mode
Table 7-60. MMC0 Switching Characteristics – High Speed SDR Mode
see Figure 7-60
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC0_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
50
HSSDR1 tc(clk)
Cycle time, MMC0_CLK
20
9.2
HSSDR2H tw(clkH)
HSSDR2L tw(clkL)
HSSDR5 td(clkL-cmdV)
HSSDR6 td(clkL-dV)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
-6.35
-6.35
6.35
6.35
ns
ns
HSSDR1
HSSDR2H
HSSDR2L
MMC0_CLK
HSSDR5
HSSDR6
MMC0_CMD
MMC0_DAT[7:0]
J7_MMC0_TIMING_04
Figure 7-60. MMC0 – High Speed SDR Mode – Transmit Mode
7.10.5.12.1.3 High Speed DDR Mode
Table 7-61, Figure 7-61, Table 7-62, and Figure 7-62 present timing requirements and switching characteristics
for MMC0 – High Speed DDR Mode.
Table 7-61. MMC0 Timing Requirements – High Speed DDR Mode
see Figure 7-61
NO.
PARAMETER
tsu(cmdV-clk)
th(clk-cmdV)
tsu(dV-clk)
DESCRIPTION
MIN
3.88
2.67
0.83
MAX
UNIT
ns
DDR3
DDR4
DDR7
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition
ns
ns
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Table 7-61. MMC0 Timing Requirements – High Speed DDR Mode (continued)
see Figure 7-61
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DDR8
th(clk-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition
1.76
ns
DDR1
DDR2H
DDR2L
MMC0_CLK
DDR3
DDR4
MMC0_CMD
DDR8
DDR8
DDR8
DDR8
DDR7
DDR7
DDR7
DDR7
MMC0_DAT[7:0]
J7_MMC0_TIMING_05
Figure 7-61. MMC0 – High Speed DDR Mode – Receive Mode
Table 7-62. MMC0 Switching Characteristics – High Speed DDR Mode
see Figure 7-62
NO.
PARAMETER
fop(clk)
tc(clk)
DESCRIPTION
Operating frequency, MMC0_CLK
MIN
MAX
UNIT
MHz
ns
50
DDR1
Cycle time, MMC0_CLK
20
9.2
DDR2H tw(clkH)
DDR2L tw(clkL)
Pulse duration, MMC0_CLK high
ns
Pulse duration, MMC0_CLK low
9.2
ns
DDR5
DDR6
td(clk-cmdV)
td(clk-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition
3.31
2.81
16.19
6.94
ns
ns
DDR1
DDR2
DDR2
MMC0_CLK
DDR5
DDR5
DDR5
DDR6
DDR5
MMC0_CMD
DDR6
DDR6
DDR6
DDR6
DDR6
MMC0_DAT[7:0]
J7_MMC0_TIMING_06
Figure 7-62. MMC0 – High Speed DDR Mode – Transmit Mode
7.10.5.12.1.4 HS200 Mode
Table 7-63 and Figure 7-63 present switching characteristics for MMC0 – HS200 Mode.
Table 7-63. MMC0 Switching Characteristics – HS200 Mode
see Figure 7-63
NO.
PARAMETER
fop(clk)
tc(clk)
DESCRIPTION
Operating frequency, MMC0_CLK
MIN
MAX
UNIT
MHz
ns
200
HS2001
Cycle time, MMC0_CLK
5
HS2002H tw(clkH)
Pulse duration, MMC0_CLK high
2.08
ns
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Table 7-63. MMC0 Switching Characteristics – HS200 Mode (continued)
see Figure 7-63
NO.
PARAMETER
DESCRIPTION
Pulse duration, MMC0_CLK low
MIN
2.08
0.99
0.99
MAX
UNIT
ns
HS2002L tw(clkL)
HS2005
HS2006
td(clkL-cmdV)
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition
3.28
3.28
ns
ns
HS2001
HS2002L
HS2002H
MMC0_CLK
MMC0_CMD
HS2005
HS2006
HS2005
HS2006
MMC0_DAT[7:0]
J7_MMC0_TIMING_07
Figure 7-63. MMC0 – HS200 Mode – Transmit Mode
7.10.5.12.2 MMC1 - SD/SDIO Interface
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer
Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
•
•
•
•
•
•
•
Default speed
High speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I SDR104
UHS–I DDR50
Table 7-64 presents the required DLL software configuration settings for MMC1 timing modes.
Table 7-64. MMC1 DLL Delay Mapping for All Timing Modes
REGISTER NAME
BIT FIELD
MMCSD1_SS_PHY_CTRL_4_REG
[15:12] [8]
OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL
MMCSD1_SS_PHY_CTRL_5_REG
[20]
[4:0]
[2:0]
BIT FIELD NAME
CLKBUFSEL
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
DELAY
BUFFER
DURATION
DELAY
ENABLE
DELAY
VALUE
MODE
DESCRIPTION
Default
Speed
4-bit PHY operating
3.3 V, 25 MHz
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0xF
0xF
0xC
0x9
0x6
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x7
0x7
0x7
0x7
0x7
0x7
0x7
High
Speed
4-bit PHY operating
3.3 V, 50 MHz
UHS-I
SDR12
4-bit PHY operating
1.8 V, 25 MHz
0x0
UHS-I
SDR25
4-bit PHY operating
1.8 V, 50 MHz
0x0
UHS-I
SDR50
4-bit PHY operating
1.8 V, 100 MHz
Tuning
Tuning
Tuning
UHS-I
DR50
4-bit PHY operating
1.8 V, 50 MHz
UHS-I
SDR104
4-bit PHY operating
1.8, V 200 MHz
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Table 7-65 presents timing conditions for MMC1.
Table 7-65. MMC1 Timing Conditions
PARAMETER
MIN
MAX UNIT
Input Conditions
Default Speed, High Speed
UHS–I SDR12, UHS–I SDR25
UHS–I DDR50
0.69
0.34
1
2.06 V/ns
1.34 V/ns
SRI
Input slew rate
2
V/ns
Output Conditions
UHS–I DDR50
All other modes
3
1
10
10
pF
pF
CL
Output load capacitance
PCB Connectivity Requirements
UHS–I DDR50
240
126
1134
1386
20
ps
ps
ps
ps
td(Trace Delay)
Propagation delay of each trace
All other modes
UHS–I DDR50, UHS–I SDR104
All other modes
td(Trace Mismatch
Propagation delay mismatch across all
traces
Delay)
100
7.10.5.12.2.1 Default Speed Mode
Table 7-66, Figure 7-64, Table 7-67, and Figure 7-65 present timing requirements and switching characteristics
for MMC1 – Default Speed Mode.
Table 7-66. Timing Requirements for MMC1 – Default Speed Mode
see Figure 7-64
NO.
PARAMETER
DESCRIPTION
MIN
2.55
MAX
UNIT
ns
DSSD5 tsu(cmdV-clkH)
DSSD6 th(clkH-cmdV)
DSSD7 tsu(dV-clkH)
DSSD8 th(clkH-dV)
Setup time, MMC1_CMD valid before MMCi_CLK rising edge
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
19.67
2.55
ns
ns
19.67
ns
DSSD2
DSSD1
DSSD0
MMCi_CLK
MMCi_CMD
DSSD6
DSSD5
DSSD8
DSSD7
MMCi_DAT[j:0]
MMC1_01
Figure 7-64. MMC1 – Default Speed – Receive Mode
Table 7-67. Switching Characteristics for MMC1 – Default Speed Mode
see Figure 7-65
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
25
DSSD0 tc(clk)
Cycle time, MMC1_CLK
40
18.7
DSSD1 tw(clkH)
DSSD2 tw(clkL)
DSSD3 td(clkL-cmdV)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
18.7
ns
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
- 14.1
14.1
ns
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Table 7-67. Switching Characteristics for MMC1 – Default Speed Mode (continued)
see Figure 7-65
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DSSD4 td(clkL-dV)
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
- 14.1
14.1
ns
DSSD2
DSSD1
DSSD0
MMCi_CLK
DSSD3
DSSD4
MMCi_CMD
MMCi_DAT[j:0]
MMC1_02
Figure 7-65. MMC1 – Default Speed – Transmit Mode
7.10.5.12.2.2 High Speed Mode
Table 7-68, Figure 7-66, Table 7-69, and Figure 7-67 present timing requirements and switching characteristics
for MMC1 – High Speed Mode.
Table 7-68. Timing Requirements for MMC1 – High Speed Mode
see Figure 7-66
NO.
PARAMETER
DESCRIPTION
MIN
2.55
2.67
2.55
2.67
MAX
UNIT
ns
HSSD3 tsu(cmdV-clkH)
HSSD4 th(clkH-cmdV)
HSSD7 tsu(dV-clkH)
HSSD8 th(clkH-dV)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
ns
ns
ns
HSSD1
HSSD2H
HSSD2L
MMCi_CLK
MMCi_CMD
HSSD4
HSSD3
HSSD7
HSSD8
MMCi_DAT[j:0]
MMC1_03
Figure 7-66. MMC1 – High Speed – Receive Mode
Table 7-69. Switching Characteristics for MMC1 – High Speed Mode
see Figure 7-67
NO.
PARAMETER
fop(clk)
tc(clk)
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
50
HSSD1
Cycle time. MMC1_CLK
20
9.2
HSSD2H tw(clkH)
HSSD2L tw(clkL)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
9.2
ns
HSSD5
td(clkL-cmdV)
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
-7.35
3.35
ns
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Table 7-69. Switching Characteristics for MMC1 – High Speed Mode (continued)
see Figure 7-67
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HSSD6
td(clkL-dV)
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
-7.35
3.35
ns
HSSD1
HSSD2H
HSSD5
HSSD2L
MMCi_CLK
MMCi_CMD
HSSD5
HSSD6
HSSD6
MMCi_DAT[j:0]
MMC1_04
Figure 7-67. MMC1 – High Speed – Transmit Mode
7.10.5.12.2.3 UHS–I SDR12 Mode
Table 7-70, Figure 7-68, Table 7-71, and Figure 7-69 present timing requirements and switching characteristics
for MMC1 – UHS-I SDR12 Mode.
Table 7-70. Timing Requirements for MMC1 – UHS-I SDR12 Mode
see Figure 7-68
NO.
PARAMETER
DESCRIPTION
MIN
21.65
1.67
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
ns
21.65
1.67
ns
ns
SDR122
SDR121
SDR120
MMCi_CLK
MMCi_CMD
SDR126
SDR125
SDR128
SDR127
MMCi_DAT[j:0]
MMC1_05
Figure 7-68. MMC1 – UHS-I SDR12 – Receive Mode
Table 7-71. Switching Characteristics for MMC1 – UHS-I SDR12 Mode
see Figure 7-69
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
25
SDR120 tc(clk)
Cycle time, MMC1_CLK
40
18.7
SDR121 tw(clkH)
SDR122 tw(clkL)
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
18.7
ns
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
-13.6
-13.6
13.6
13.6
ns
ns
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SDR122
SDR121
SDR120
MMCi_CLK
MMCi_CMD
SDR123
SDR124
MMCi_DAT[j:0]
MMC1_06
Figure 7-69. MMC1 – UHS-I SDR12 – Transmit Mode
7.10.5.12.2.4 UHS–I SDR25 Mode
Table 7-72, Figure 7-70, Table 7-73, and Figure 7-71 present timing requirements and switching characteristics
for MMC1 – UHS-I SDR25 Mode.
Table 7-72. Timing Requirements for MMC1 – UHS-I SDR25 Mode
see Figure 7-70
NO.
PARAMETER
DESCRIPTION
MIN
2.15
1.67
2.15
1.67
MAX
UNIT
ns
SDR253 tsu(cmdV-clkH)
SDR254 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge
ns
ns
ns
SDR251
SDR252L
SDR253
SDR252H
MMCi_CLK
MMCi_CMD
SDR254
SDR258
SDR257
MMCi_DAT[j:0]
MMC1_07
Figure 7-70. MMC1 – UHS-I SDR25 – Receive Mode
Table 7-73. Switching Characteristics for MMC1 – UHS-I SDR25 Mode
see Figure 7-71
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
50
SDR251 tc(clk)
Cycle time, MMC1_CLK
20
9.2
SDR252H tw(clkH)
SDR252L tw(clkL)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
9.2
ns
Delay time, MMC1_CLK falling edge to MMC1_CMD transition
Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition
-7.1
-7.1
3.1
3.1
ns
ns
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SDR251
SDR252H
SDR252L
MMCi_CLK
MMCi_CMD
HSSDR255
SDR255
SDR256
SDR256
MMCi_DAT[j:0]
MMC1_08
Figure 7-71. MMC1 – UHS-I SDR25 – Transmit Mode
7.10.5.12.2.5 UHS–I SDR50 Mode
, Table 7-74, and Figure 7-72 presents switching characteristics for MMC1 – UHS-I SDR50 Mode.
Table 7-74. Switching Characteristics for MMC1 – UHS-I SDR50 Mode
see Figure 7-72
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
fop(clk)
100
SDR501 tc(clk)
Cycle time, MMC1_CLK
10
4.45
4.45
1.2
SDR502H tw(clkH)
SDR502L tw(clkL)
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
ns
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
6.35
6.35
ns
1.2
ns
SDR501
SDR502H
SDR505
SDR502L
MMCi_CLK
SDR505
MMCi_CMD
SDR506
SDR506
MMCi_DAT[j:0]
MMC1_10
Figure 7-72. MMC1 – UHS-I SDR50 – Transmit Mode
7.10.5.12.2.6 UHS–I DDR50 Mode
Table 7-75, Figure 7-73, Table 7-76, and Figure 7-74 present timing requirements and switching characteristics
for MMC1 – UHS-I DDR50 Mode.
Table 7-75. Timing Requirements for MMC1 – UHS-I DDR50 Mode
see Figure 7-73
NO.
PARAMETER
tsu(cmdV-clk)
th(clk-cmdV)
tsu(dV-clk)
DESCRIPTION
MIN
2.99
1.91
-0.06
1.91
MAX
UNIT
ns
DDR505
DDR506
DDR507
DDR508
Setup time, MMC1_CMD valid before MMC1_CLK rising edge
Hold time, MMC1_CMD valid after MMC1_CLK rising edge
Setup time, MMC1_DAT[3:0] valid before MMC1_CLK transition
Hold time, MMC1_DAT[3:0] valid after MMC1_CLK transition
ns
ns
th(clk-dV)
ns
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DDR500
DDR501
DDR502
MMCi_CLK
MMCi_CMD
DDR505
DDR506
DDR507
DDR508
DDR507
DDR508
MMCi_DAT[j:0]
MMC1_13
Figure 7-73. MMC1 – UHS-I DDR50 – Receive Mode
Table 7-76. Switching Characteristics for MMC1 – UHS-I DDR50 Mode
see Figure 7-74
NO.
PARAMETER
fop(clk)
tc(clk)
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
MHz
ns
50
DDR500
DDR501
DDR502
DDR503
DDR504
Cycle time, MMC1_CLK
20
9.2
9.2
1.2
1.2
tw(clkH)
Pulse duration, MMC1_CLK high
ns
tw(clkL)
Pulse duration, MMC1_CLK low
ns
td(clk-cmdV)
td(clk-dV)
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition
13.1
6.35
ns
ns
DDR500
DDR501
DDR502
MMCi_CLK
DDR503(max)
DDR503(min)
MMCi_CMD
DDR504(max)
DDR504(min)
DDR504(max)
DDR504(min)
MMCi_DAT[j:0]
MMC1_14
Figure 7-74. MMC1 – UHS-I DDR50 – Transmit Mode
7.10.5.12.2.7 UHS–I SDR104 Mode
Table 7-77, and Figure 7-75 present switching characteristics for MMC1 – UHS-I SDR104 Mode.
Table 7-77. Switching Characteristics for MMC1 – UHS-I SDR104 Mode
see Figure 7-75
NO.
PARAMETER
DESCRIPTION
Operating frequency, MMC1_CLK
MIN
MAX
UNIT
fop(clk)
200
MHz
ns
SDR1041 tc(clk)
Cycle time, MMC1_CLK
5
2.08
2.08
1.12
1.12
SDR1042H tw(clkH)
SDR1042L tw(clkL)
SDR1045 td(clkL-cmdV)
SDR1046 td(clkL-dV)
Pulse duration, MMC1_CLK high
ns
Pulse duration, MMC1_CLK low
ns
Delay time, MMC1_CLK rising edge to MMC1_CMD transition
Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition
3.16
3.16
ns
ns
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SDR1041
SDR1042H
SDR1045
SDR1042L
MMCi_CLK
MMCi_CMD
SDR1045
SDR1046
SDR1046
MMCi_DAT[j:0]
MMC1_12
Figure 7-75. MMC1 – UHS-I SDR104 – Transmit Mode
7.10.5.13 CPTS
Table 7-78, Table 7-79, Figure 7-76, Table 7-80, and Figure 7-77 present timing conditions, requirements, and
switching characteristics for CPTS.
Table 7-78. CPTS Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
Table 7-79. CPTS Timing Requirements
see Figure 7-76
NO.
PARAMETER
DESCRIPTION
Pulse duration, CPTS_HWn_TS_PUSH high
Pulse duration, CPTS_HWn_TS_PUSH low
Cycle time, CPTS_RFT_CLK
MIN
2 + 12P(1)
2 + 12P(1)
5
MAX
UNIT
ns
T1
tw(HWTSPUSHH)
tw(HWTSPUSHL)
tc(RFT_CLK)
T2
ns
T3
8
ns
T4
tw(RFT_CLKH)
Pulse duration, CPTS_RFT_CLK high
0.45 ×
ns
tc(RFT_CLK)
T5
tw(RFT_CLKL)
Pulse duration, CPTS_RFT_CLK low
0.45 ×
ns
tc(RFT_CLK)
(1) P = functional clock period in ns.
T1
T2
CPTS_HWn_TS_PUSH
T3
T4
T5
CPTS_RFT_CLK
Figure 7-76. CPTS Timing Requirements
Table 7-80. CPTS Switching Characteristics
see Figure 7-77
NO.
PARAMETER
DESCRIPTION
Pulse duration, CPTS_TS_COMP high
Pulse duration, CPTS_TS_COMP low
Pulse duration, CPTS_TS_SYNC high
Pulse duration, CPTS_TS_SYNC low
MIN
-2+36P(1)
-2+36P(1)
-2+36P(1)
-2+36P(1)
MAX
UNIT
ns
T6
tw(TS_COMPH)
T7
tw(TS_COMPL)
tw(TS_SYNCH)
tw(TS_SYNCL)
ns
T10
T11
ns
ns
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Table 7-80. CPTS Switching Characteristics (continued)
see Figure 7-77
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
T14
tw(SYNC_OUTH)
Pulse duration, CPTS_TS_SYNC sourcing
CPTS_SYNCn_OUT high
-2+36P(1)
ns
T15
tw(SYNC_OUTL)
Pulse duration, CPTS_TS_SYNC sourcing
CPTS_SYNCn_OUT low
-2+36P(1)
ns
T16
T17
tw(SYNC_OUTH)
tw(SYNC_OUTL)
Pulse duration, GENF sourcing CPTS_SYNCn_OUT high
Pulse duration, GENF sourcing CPTS_SYNCn_OUT low
-2+5P(1)
-2+5P(1)
ns
ns
(1) P = functional clock period in ns.
T6
T7
CPTS_TS_COMP
T8
T9
CPTS_TS_SYNC
T10
T11
CPTS_SYNC_OUT
Figure 7-77. CPTS Switching Characteristics
For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter
in the device TRM.
7.10.5.14 OSPI
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed
Description.
7.10.5.14.1 OSPI With Data Training
7.10.5.14.1.1 OSPI Switching Characteristics – Data Training
PARAMETER
DESCRIPTION
MODE
MIN
6.02
7.52
5.00
7.52
MAX
UNIT
ns
tc(CLK)
Cycle time, CLK
Cycle time, CLK
DDR, 1.8V
DDR, 3.3V
SDR, 1.8V
SDR, 3.3V
ns
tc(CLK)
ns
ns
7.10.5.14.2 OSPI Without Data Training
Note
The I/O Timings provided in this section are only applicable when data training is not implemented.
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL
Delays are configured as described in Table 7-81 found in this section.
Section 7.10.5.14.2.1, Section 7.10.5.14.2.2, Figure 7-78, and Figure 7-79 present switching characteristics for
OSPI DDR and SDR Mode.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
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7.10.5.14.2.1 OSPI Switching Characteristics – DDR Mode
NO.(1) PARAMETER
DESCRIPTION
MODE
1.8V
MIN
19
MAX
UNIT
ns
O1 tc(CLK)
Cycle time, CLK
3.3V
19
ns
O2 tw(CLKL)
O3 tw(CLKH)
O4 td(CLK-CSn)
Pulse duration, CLK low
Pulse duration, CLK high
-0.3+0.475*P
ns
(2)
-0.3+0.475*P
ns
ns
(2)
Delay time, CLK rising edge to CSn active edge 1.8V, OSPI0 DDR TX; -7.7-0.475 * P 0-0.475 * P –
– 0.975 * N * 0.975 * N * R
R (3) (4) (5)
(3) (4) (5)
3.3V, OSPI0 DDR TX; -8-0.475 * P – 0-0.475 * P –
0.975 * N * R 0.975 * N * R
ns
ns
ns
(3) (4) (5)
(3) (4) (5)
O5 td(CLK-CSn)
Delay time, CLK rising edge to CSn inactive
edge
1.8V, OSPI0 DDR TX; -7.7+0.475 * 0+0.475 * P +
P + 0.975 * N 0.975 * N * R
* R (3) (4) (5)
(3) (4) (5)
3.3V, OSPI0 DDR TX; -8+0.475 * P 0+0.475 * P +
+ 0.975 * N * 0.975 * N * R
R (3) (4) (5)
(3) (4) (5)
O6 td(CLK-D)
Delay time, CLK active edge to D[i:0] transition
1.8V, OSPI0 DDR TX;
3.3V, OSPI0 DDR TX;
-7.7
-7.7
-1.56
-1.56
ns
ns
(1) i in [i:0] = 7 for OSPI0
(2) P = CLK cycle time
(3) P = SCLK period
(4) N = OSPI_DEV_DELAY_REG[7-0] D_INIT_FLD
(5) R = refclk
OSPI_CSn
O4
O3
O5
OSPI_CLK
O2
O1
O6
O6
OSPI_D[i:0]
OSPI_TIMING_01
Figure 7-78. OSPI Switching Characteristics – DDR
7.10.5.14.2.2 OSPI Switching Characteristics – SDR Mode
NO.(1) PARAMETER
DESCRIPTION
MODE
1.8V
MIN
7
MAX
UNIT
ns
O7 tc(CLK)
Cycle time, CLK
3.3V
7.52
ns
O8 tw(CLKL)
O9 tw(CLKH)
Pulse duration, CLK low
Pulse duration, CLK high
-0.3+0.475*P
ns
(2)
-0.3+0.475*P
ns
(2)
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NO.(1) PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
O10 td(CLK-CSn)
O11 td(CLK-CSn)
O12 td(CLK-D)
Delay time, CLK rising edge to CSn active edge
1.8V
-1-0.475 * P – 1-0.475 * P –
0.975 * N * R 0.975 * N * R
ns
(3) (4) (5)
(3) (4) (5)
3.3V
1.8V
3.3V
-1-0.475 * P – 1-0.475 * P –
0.975 * N * R 0.975 * N * R
ns
ns
ns
(3) (4) (5)
(3) (4) (5)
Delay time, CLK rising edge to CSn inactive
edge
-1+0.475 * P 1+0.475 * P +
+ 0.975 * N * 0.975 * N * R
R (3) (4) (5)
(3) (4) (5)
-1+0.475 * P 1+0.475 * P +
+ 0.975 * N * 0.975 * N * R
R (3) (4) (5)
(3) (4) (5)
Delay time, CLK active edge to D[i:0] transition
1.8V
3.3V
-1.15
-1.33
1.25
1.51
ns
ns
(1) i in [i:0] = 7 for OSPI0
(2) P = CLK cycle time
(3) P = SCLK period
(4) N = OSPI_DEV_DELAY_REG[7-0] D_INIT_FLD
(5) R = refclk
OSPI_CSn
O11
O10
O7
O9
O8
OSPI_CLK
OSPI_D[i:0]
O12
OSPI_TIMING_02
Figure 7-79. OSPI Switching Characteristics – SDR
Section 7.10.5.14.2.3, Section 7.10.5.14.2.4, Figure 7-80, Figure 7-81, Figure 7-82, and Figure 7-83 presents
timing requirements for OSPI DDR and SDR Mode.
7.10.5.14.2.3 OSPI Timing Requirements – DDR Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
(1)
O13 tsu(D-CLK)
O14 th(CLK-D)
O15 tsu(D-LBCLK)
Setup time, D[i:0] valid before active CLK edge
1.8V, No Loopback Clock; 1.8V,
Internal Pad Loopback Clock
5.23
ns
3.3V, No Loopback Clock; 3.3V,
Internal Pad Loopback Clock
6.19
1.84
2.34
0.52
1.97
ns
ns
ns
ns
ns
Hold time, D[i:0] valid after active CLK edge
1.8V, No Loopback Clock; 1.8V,
Internal Pad Loopback Clock
3.3V, No Loopback Clock; 3.3V,
Internal Pad Loopback Clock
Setup time, D[i:0] valid before active LBCLK (DQS) 1.8V, External Board Loopback
edge
Clock
3.3V, External Board Loopback
Clock
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PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
(1)
O16 th(LBCLK-D)
Hold time, D[i:0] valid after active LBCLK (DQS)
edge
1.8V, External Board Loopback 1.8 (2)
Clock
ns
3.3V, External Board Loopback 2.2 (2)
Clock
ns
O17 tsu(D-DQS)
Setup time, DQS edge to D[i:0] transition
Hold time, DQS edge to D[i:0] transition
1.8V, OSPI0 DQS;
3.3V, OSPI0 DQS;
1.8V, OSPI0 DQS;
3.3V, OSPI0 DQS;
-0.46
-0.66
3.59
7.92
ns
ns
ns
ns
O18 th(DQS-D)
(1) i in [i:0] = 7 for OSPI0
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external
loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.
OSPI_CLK
O13 O14
OSPI_D[i:0]
OSPI_TIMING_03
Figure 7-80. OSPI Timing Requirements – DDR, No Loopback Clock and Internal Pad Loopback Clock
OSPI_DQS
O15 O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 7-81. OSPI Timing Requirements – DDR, External Loopback Clock and DQS
7.10.5.14.2.4 OSPI Timing Requirements – SDR Mode
NO. PARAMETE
DESCRIPTION
MODE
MIN
MAX
UNIT
(1)
R
O19 tsu(D-CLK)
Setup time, D[i:0] valid before active CLK
edge
1.8V, No Loopback Clock
3.3V, No Loopback Clock
-2.18
-1.7
ns
ns
ns
ns
ns
ns
ns
ns
O20 th(CLK-D)
Hold time, D[i:0] valid after active CLK edge
1.8V, No Loopback Clock
7.62
8.1
3.3V, No Loopback Clock
O21 tsu(D-LBCLK)
Setup time, D[i:0] valid before active LBCLK
input (DQS) edge
1.8V, External Board Loopback Clock
3.3V, External Board Loopback Clock
1.8V, External Board Loopback Clock
3.3V, External Board Loopback Clock
-3.24
-2.72
3.81
4.33
O22 th(LBCLK-D)
Hold time, D[i:0] valid after active LBCLK
input (DQS) edge
(1) i in [i:0] = 7 for OSPI0
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OSPI_CLK
OSPI_D[i:0]
O19
O20
OSPI_TIMING_05
Figure 7-82. OSPI Timing Requirements – SDR, No Loopback Clock and Internal Pad Loopback Clock
OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
Figure 7-83. OSPI Timing Requirements – SDR, External Loopback Clock
Table 7-81. OSPI DLL Delay Mapping for Timing Modes
MODE
OSPI_PHY_CONFIGURATION_REG BIT FIELD
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_TX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
PHY_CONFIG_RX_DLL_DELAY_FLD
DELAY VALUE
1.8V, OSPI0 DDR TX
3.3V, OSPI0 DDR TX
1.8V, OSPI0 DQS
3.3V, OSPI0 DQS
All other modes
0x45
0x46
0x14
0x3A
0x0
PHY_CONFIG_TX_DLL_DELAY_FLD,
PHY_CONFIG_RX_DLL_DELAY_FLD
7.10.5.15 PCIe
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
7.10.5.16 PRU_ICSSG
The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU
cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast
real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks
from the other processor cores in the device.
For more details about features and additional description information on the device PRU_ICSSG, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Note
The PRU_ICSSG0 and PRU_ICSSG1 support an internal wrapper multiplexing that expands the
device top-level multiplexing.
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7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
Note
The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The
signal naming in this section matches the naming used in the PRU Module Interface section in the
device TRM.
Table 7-82. PRU_ICSSG PRU Timing Conditions
PARAMETER
MIN
MAX
3
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
1
OUTPUT CONDITIONS
CL
Output load capacitance
2
30
7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
Table 7-83. PRU_ICSSG PRU Switching Characteristics – Direct Output Mode
see Figure 7-84
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRDO1 tsk(GPO-GPO)
Skew, GPO to GPO
3
ns
GPO[n:0]
PRDO1
PRU_TIMING_02
A. n in GPO[n:0] = 19.
Figure 7-84. PRU_ICSSG PRU Direct Output Timing
7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
Table 7-84. PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode
see Figure 7-85 and Figure 7-86
NO.
PARAMETER
DESCRIPTION
MIN
20
10
10
4
MAX
UNIT
ns
PRPC1 tc(CLOCK)
Cycle time, CLOCKIN
PRPC2 tw(CLOCKL)
Pulse duration, CLOCKIN low
ns
PRPC3 tw(CLOCKH)
PRPC4 tsu(DATAIN-CLOCK)
PRPC5 th(CLOCK-DATAIN)
Pulse duration, CLOCKIN high
ns
Setup time, DATAIN valid before CLOCKIN active edge
Hold time, DATAIN valid after CLOCKIN active edge
ns
0
ns
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_03
Figure 7-85. PRU_ICSSG PRU Parallel Capture Timing Requirements – Rising Edge Mode
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PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
PRU_TIMING_04
Figure 7-86. PRU_ICSSG PRU Parallel Capture Timing Requirements – Falling Edge Mode
7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
Table 7-85. PRU_ICSSG PRU Timing Requirements – Shift In Mode
see Figure 7-87
NO.
PARAMETER
DESCRIPTION
Pulse duration, DATAIN high
Pulse duration, DATAIN low
MIN
2+2*P(1)
2+2*P(1)
MAX
UNIT
ns
PRSI1 tw(DATAINH)
PRSI2 tw(DATAINL)
ns
(1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.
PRUn represents the respective PRU0 or PRU1 instance.
PRSI1
PRSI2
DATAIN
PRU_TIMING_05
Figure 7-87. PRU_ICSSG PRU Shift In Timing
Table 7-86. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode
see Figure 7-88
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ns
PRSO1
tc(CLOCKOUT)
Cycle time, CLOCKOUT
10
PRSO2L tw(CLOCKOUTL)
Pulse duration, CLOCKOUT low
-0.3 +
ns
0.475*P*Z(1)(2)
PRSO2H tw(CLOCKOUTH)
Pulse duration, CLOCKOUT high
-0.3 +
ns
ns
0.475*P*Y(1)(3)
PRSO3
td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid
-1
4
(1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the
ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance.
(2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an
EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1).
b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5).
c. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5).
d. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0). If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals
(PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0).
(3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance.
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a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an
EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). If PRUn_GPI_DIV0 is a NON-INTEGER and
PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5).
b. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 *
PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0).
c. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 *
PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high
pulse and Y2 is the second high pulse.
PRSO1
PRSO2H
PRSO2L
CLOCKOUT
DATAOUT
PRSO3
PRU_TIMING_06
Figure 7-88. PRU_ICSSG PRU Shift Out Timing
7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
Table 7-87. PRU_ICSSG PRU Sigma Delta and Peripheral InterfaceTiming Conditions
PARAMETER
MIN
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
1
3
OUTPUT CONDITIONS
CL
Output load capacitance
2
18
7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
Table 7-88. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode
see Figure 7-89 and Figure 7-90
NO.
PARAMETER
DESCRIPTION
MIN
40
20
20
10
5
MAX
UNIT
ns
PRSD1
tc(SD_CLK)
Cycle time, SDx_CLK
PRSD2L tw(SD_CLKL)
PRSD2H tw(SD_CLKH)
Pulse duration, SDx_CLK low
ns
Pulse duration, SDx_CLK high
ns
PRSD3
PRSD4
tsu(SD_D-SD_CLK)
Setup time, SDx_D valid before SDx_CLK active edge
Hold time, SDx_D valid before SDx_CLK active edge
ns
th(SD_CLK-SD_D)
ns
PRSD1
PRSD2H
SDx_CLK
SDx_D
PRSD2L
PRSD4
PRSD3
PRU_TIMING_07
Figure 7-89. PRU_ICSSG PRU SD_CLK Falling Active Edge
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PRSD2L
SDx_CLK
SDx_D
PRSD4
PRSD3
PRU_TIMING_08
Figure 7-90. PRU_ICSSG PRU SD_CLK Rising Active Edge
Table 7-89. PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode
see Figure 7-91
NO.
PARAMETER
DESCRIPTION
Pulse duration, PIF_DATA_IN high
MIN
MAX
UNIT
PRPIF1 tw(PIF_DATA_INH)
2 +
ns
0.475*(4*P)(1)
PRPIF2 tw(PIF_DATA_INL)
Pulse duration, PIF_DATA_IN low
2 +
ns
0.475*(4*P)(1)
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.
PRPIF1
PRPIF2
PIF_DATA_IN
PRUPIF_TIMING_01
Figure 7-91. PRU_ICSSG PRU Peripheral Interface Timing Requirements
Table 7-90. PRU_ICSSG PRU Switching Characteristics – Peripheral Interface Mode
see Figure 7-92
NO.
PARAMETER
DESCRIPTION
MIN
30
0.475*P(1)
0.475*P(1)
-5
MAX
UNIT
ns
PRPIF3 tc(PIF_CLK)
PRPIF4 tw(PIF_CLKH)
PRPIF5 tw(PIF_CLKL)
Cycle time, PIF_CLK
Pulse duration, PIF_CLK high
ns
Pulse duration, PIF_CLK low
ns
PRPIF6 td(PIF_CLK-
Delay time, PIF_CLK fall to PIF_DATA_OUT
5
5
ns
PIF_DATA_OUT)
PRPIF7 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN
-5
ns
(1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the
ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance.
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PRPIF3
PRPIF4 PRPIF5
PIF_CLK
PRPIF6
PRPIF7
PIF_DATA_OUT
PIF_DATA_EN
Figure 7-92. PRU_ICSSG PRU Peripheral Interface Switching Characteristics
7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
Table 7-91. PRU_ICSSG PWM Timing Conditions
PARAMETER
MIN
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
1
4
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
7.10.5.16.2.1 PRU_ICSSG PWM Timing
Table 7-92. PRU_ICSSG PWM Switching Characteristics
see Figure 7-93
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRPWM1 tsk(PWM_A-PWM_B)
Skew, PWM_A to PWM_B
5
ns
PWM_A/B
PRPWM1
PRU_PWM_TIMING_01
Figure 7-93. PRU_ICSSG PWM Timing
7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
Table 7-93. PRU_ICSSG IEP Timing Conditions
PARAMETER
MIN
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
1
3
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
7.10.5.16.3.1 PRU_ICSSG IEP Timing
Table 7-94. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC
see Figure 7-94
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRIEP1 tw(EDC_SYNC_OUTxL)
Pulse duration, EDC_SYNC_OUTx low
-2+20*P(1)
ns
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Table 7-94. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC (continued)
see Figure 7-94
NO.
PARAMETER
DESCRIPTION
MIN
-2+20*P(1)
20
MAX
UNIT
ns
PRIEP2 tw(EDC_SYNC_OUTxH)
Pulse duration, EDC_SYNC_OUTx high
PRIEP3 tsu(EDIO_DATA_IN-
Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active
edge
ns
EDC_SYNC_OUTx)
PRIEP4 th(EDC_SYNC_OUTx-
Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active
edge
20
ns
EDIO_DATA_IN)
(1) P = PRU_ICSSG IEP clock source period in ns.
EDC_SYNC_OUTx
PRIEP2
PRIEP1
PRIEP3
PRIEP4
EDIO_DATA_IN[7:0]
PRU_IEP_TIMING_01
Figure 7-94. PRU_ICSSG IEP SYNC Timing Requirements
Table 7-95. PRU_ICSSG IEP Timing Requirements – Digital IOs
see Figure 7-95
NO.
PARAMETER
DESCRIPTION
Pulse duration, EDIO_OUTVALID low
MIN
-2+14*P(1)
-2+32*P(1)
0
MAX
UNIT
ns
IEPIO1 tw(EDIO_OUTVALIDL)
IEPIO2 tw(EDIO_OUTVALIDH)
Pulse duration, EDIO_OUTVALID high
ns
IEPIO3 td(EDIO_OUTVALID-
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
18*P(1)
ns
EDIO_DATA_OUT)
IEPIO4 tsk(EDIO_DATA_OUT)
EDIO_DATA_OUT skew
5
ns
(1) P = PRU_ICSSG IEP clock source period in ns.
EDIO_DATA_OUT
IEPIO4
PRU_EDIO_DATA_OUT_TIMING_00
Figure 7-95. PRU_ICSSG IEP Digital IOs Timing Requirements
Table 7-96. PRU_ICSSG IEP Timing Requirements – LATCH_INx
see Figure 7-96
NO.
PARAMETER
DESCRIPTION
Pulse duration, EDC_LATCH_INx low
Pulse duration, EDC_LATCH_INx high
MIN
MAX
UNIT
ns
PRLA1 tw(EDC_LATCH_INxL)
PRLA2 tw(EDC_LATCH_INxH)
2+3*P(1)
2+3*P(1)
ns
(1) P = PRU_ICSSG IEP clock source period in ns.
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PRLA1
EDC_LATCH_INx
PRLA2
PRU_IEP_TIMING_02
Figure 7-96. PRU_ICSSG IEP LATCH_INx Timing Requirements
7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
Table 7-97. PRU_ICSSG UART Timing Conditions
PARAMETER
MIN
MAX
0.33
30
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
0.01
1
OUTPUT CONDITIONS
CL
Output load capacitance
7.10.5.16.4.1 PRU_ICSSG UART Timing
Table 7-98. PRU_ICSSG UART Timing Requirements
see Figure 7-97
NO.
PARAMETER
DESCRIPTION
Pulse duration, receive start, stop, data bit high
Pulse duration, receive start, stop, data bit low
MIN
U(1)
-2+U(1)
MAX
UNIT
ns
PRUR1H tw(RXH)
PRUR1L tw(RXL)
ns
(1) U = UART baud time in ns = 1/programmed baud rate.
Table 7-99. PRU_ICSSG UART Switching Characteristics
see Figure 7-97
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
Mbps
ns
f(baud)
Programmed baud rate
12
PRUR3H tw(TXH)
PRUR3L tw(TXL)
Pulse duration, transmit start, stop, data bit high
Pulse duration, transmit start, stop, data bit low
U (1)
-2+U (1)
ns
(1) U = UART baud time in ns = 1/programmed baud rate.
PRUR1L
PRUR1H
Start
Bit
PRGi_UART0_RXD(1)
Data Bits
PRUR3L
PRUR3H
Start
Bit
PRGi_UART0_TXD(1)
Data Bits
PRU_UART_TIMING_01
(1) i in PRGi_UART0_RXD and PRGi_UART0_TXD = 0, 1 or 2
Figure 7-97. PRU_ICSSG UART Timing Requirements and Switching Characteristics
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7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
Table 7-100. PRU_ICSSG ECAP Timing Conditions
PARAMETER
MIN
MAX
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
1
3
7
OUTPUT CONDITIONS
CL
Output load capacitance
2
7.10.5.16.5.1 PRU_ICSSG ECAP Timing
Table 7-101. PRU_ICSSG ECAP Timing Requirements
see Figure 7-98
NO.
PARAMETER
DESCRIPTION
Pulse Duration, CAP (asynchronous)
Pulse Duration, SYNCI (asynchronous)
MIN
2+2*P(1)
2+2*P(1)
MAX
UNIT
ns
PREP1 tw(CAP)
PREP2 tw(SYNCI)
ns
(1) P = CORE_CLK period in ns.
PREP1
PREP2
CAP
SYNCI
Figure 7-98. PRU_ICSSG ECAP Timing
Table 7-102. PRU_ICSSG ECAP Switching Characteristics
see Figure 7-99
NO.
PARAMETER
DESCRIPTION
Pulse Duration, APWM high/low
MIN
2*P(1)
P(1)
MAX
UNIT
ns
PREP3 tw(APWM)
PREP4 tw(SYNCO)
Pulse Duration, SYNCO (asynchronous)
ns
(1) P = CORE_CLK period in ns.
PREP3
PREP4
APWM
SYNCO
Figure 7-99. PRU_ICSSG ECAP Switching Characteristics
7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.
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7.10.5.16.6.1 PRU_ICSSG MDIO Timing
Table 7-103, Table 7-104, Table 7-105, and Figure 7-100 present timing conditions, requirements, and switching
characteristics for PRU_ICSSG MDIO.
Table 7-103. PRU_ICSSG MDIO Timing Conditions
PARAMETER
MIN
0.9
10
MAX
3.6
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
470
Table 7-104. PRU_ICSSG MDIO Timing Requirements
see Figure 7-100
NO.
PARAMETER
MIN
90
0
MAX
UNIT
ns
MDIO1 tsu(MDIO_MDC)
MDIO2 th(MDC_MDIO)
Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high
Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high
ns
Table 7-105. PRU_ICSSG MDIO Switching Characteristics
see Figure 7-100
NO.
PARAMETER
Cycle time, MDIO[x]_MDC
MIN
MAX
UNIT
ns
MDIO3 tc(MDC)
400
160
160
-150
MDIO4 tw(MDCH)
MDIO5 tw(MDCL)
MDIO7 td(MDC_MDIO)
Pulse Duration, MDIO[x]_MDC high
ns
Pulse Duration, MDIO[x]_MDC low
ns
Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid
150
ns
MDIO3
MDIO4
MDIO5
MDIO[x]_MDC
MDIO1
MDIO2
MDIO[x]_MDIO
(input)
MDIO7
MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01
Figure 7-100. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics
7.10.5.16.6.2 PRU_ICSSG MII Timing
Note
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200 MHz,
225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1
register must be set to 0h (default value).
Table 7-106, Table 7-107, Figure 7-101, Table 7-108, Figure 7-102, Table 7-109, Figure 7-103, Table 7-110, and
Figure 7-104 present timing conditions, requirements, and switching characteristics for PRU_ICSSG MII.
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Table 7-106. PRU_ICSSG MII Timing Conditions
PARAMETER
MIN
MAX
3.6
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
0.9
2
OUTPUT CONDITIONS
CL
Output load capacitance
20
Table 7-107. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK
see Figure 7-101
NO.
PARAMETER
DESCRIPTION
Cycle time, MII[x]_RX_CLK
MODE
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX UNIT
399.96 400.04
39.996 40.004
ns
ns
ns
ns
ns
ns
PMIR1 tc(RX_CLK)
PMIR2 tw(RX_CLKH)
PMIR3 tw(RX_CLKL)
140
14
260
26
Pulse Duration, MII[x]_RX_CLK High
Pulse Duration, MII[x]_RX_CLK Low
140
14
260
26
PMIR1
PMIR2
PMIR3
MII_RX_CLK
PRU_MII_RT_TIMING_04
Figure 7-101. PRU_ICSSG MII[x]_RX_CLK Timing
Table 7-108. PRU_ICSSG MII Timing Requirements – MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
see Figure 7-102
NO.
PARAMETER
tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
DESCRIPTION
MODE
MIN
8
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK
Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK
Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK
Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK
Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK
Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK
Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK
10 Mbps
8
8
PMIR4
8
100
Mbps
8
8
8
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
th(RX_CLK-RXD)
10 Mbps
8
8
PMIR5
8
100
Mbps
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
8
8
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PMIR4
PMIR5
MII_RX_CLK
MII_RXD[3:0],
MII_RX_DV, MII_RX_ER
Figure 7-102. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing
Table 7-109. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK
see Figure 7-103
NO.
PARAMETER
DESCRIPTION
Cycle time, MII[x]_TX_CLK
MODE
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX UNIT
399.96 400.04
39.996 40.004
ns
ns
ns
ns
ns
ns
PMIT1 tc(TX_CLK)
PMIT2 tw(TX_CLKH)
PMIT3 tw(TX_CLKL)
140
14
260
26
Pulse Duration, MII[x]_TX_CLK High
Pulse Duration, MII[x]_TX_CLK Low
140
14
260
26
PMIT1
PMIT2
PMIT3
MII_TX_CLK
Figure 7-103. PRU_ICSSG MII[x]_TX_CLK Timing
Table 7-110. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN
see Figure 7-104
NO.
PARAMETER
DESCRIPTION
MODE
MIN
0
MAX
25
UNIT
ns
td(TX_CLK-TXD)
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid
Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid
Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid
10 Mbps
td(TX_CLK-TX_EN)
td(TX_CLK-TXD)
0
25
ns
PMIT4
0
25
ns
100
Mbps
td(TX_CLK-TX_EN)
0
25
ns
PMIT4
MII_TX_CLK
MII_TXD[3:0], MII_TX_EN
Figure 7-104. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing
7.10.5.16.6.3 PRU_ICSSG RGMII Timing
Table 7-111, Table 7-112, Table 7-113, Figure 7-105, Table 7-114, Table 7-115, and Figure 7-106 present timing
conditions, requirements, and switching characteristics for PRU_ICSSG RGMII.
Table 7-111. PRU_ICSSG RGMII Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
2.65
5
V/ns
OUTPUT CONDITIONS
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Table 7-111. PRU_ICSSG RGMII Timing Conditions (continued)
PARAMETER
MIN
MAX
UNIT
CL
Output load capacitance
2
20
pF
Table 7-112. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RXC
see Figure 7-105
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_RXC
MODE
10 Mbps
MIN
360
36
MAX UNIT
RGMII1 tc(RXC)
440
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
44
8.8
240
24
7.2
160
16
RGMII2 tw(RXCH)
Pulse duration, RGMII[x]_RXC high
Pulse duration, RGMII[x]_RXC low
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
RGMII3 tw(RXCL)
100 Mbps
1000 Mbps
3.6
4.4
Table 7-113. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RD[3:0] and RGMII[x]_RX_CTL
see Figure 7-105
NO.
PARAMETER
DESCRIPTION
MODE
10 Mbps
MIN
1
MAX UNIT
RGMII4 tsu(RD-RXC)
Setup time, RGMII[x]_RD[3:0] valid before RXC high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
1
1
tsu(RX_CTL-RXC)
Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC
high/low
1
100 Mbps
1000 Mbps
10 Mbps
1
1
RGMII5 th(RXC-RD)
Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC
high/low
1
100 Mbps
1000 Mbps
10 Mbps
1
1
th(RXC-RX_CTL)
Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC
high/low
1
100 Mbps
1000 Mbps
1
1
RGMII1
RGMII2
RGMII3
RGMII[x]_RXC(A)
RGMII4
RGMII5
RGMII[x]_RD[3:0](B)
RGMII[x]_RX_CTL(B)
1st Half-byte
RXDV
2nd Half-byte
RXERR
A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.
Figure 7-105. PRU_ICSSG RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements -
RGMII Mode
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Table 7-114. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TXC
see Figure 7-106
NO.
PARAMETER
DESCRIPTION
Cycle time, RGMII[x]_TXC
MODE
10 Mbps
MIN
360
36
MAX UNIT
RGMII6 tc(TXC)
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
240
24
RGMII7 tw(TXCH)
Pulse duration, RGMII[x]_TXC high
Pulse duration, RGMII[x]_TXC low
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
RGMII8 tw(TXCL)
100 Mbps
1000 Mbps
3.6
4.4
Table 7-115. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL
see Figure 7-106
NO.
PARAMETER
DESCRIPTION
MODE
10 Mbps
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX UNIT
RGMII9 tosu(TD-TXC)
Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC
high/low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
tosu(TX_CTL-TXC)
Output setup time, RGMII[x]_TX_CTL valid to
RGMII[x]_TXC high/low
100 Mbps
1000 Mbps
10 Mbps
RGMII10 toh(TXC-TD)
Output setup time, RGMII[x]_TD[3:0] valid after
RGMII[x]_TXC high/low
100 Mbps
1000 Mbps
10 Mbps
toh(TXC-TX_CTL)
Output setup time, RGMII[x]_TX_CTL valid after
RGMII[x]_TXC high/low
100 Mbps
1000 Mbps
RGMII6
RGMII7
RGMII8
RGMII[x]_TXC(A)
RGMII9
RGMII[x]_TD[3:0](B)
RGMII[x]_TX_CTL(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
RGMII10
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.
Figure 7-106. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching
Characteristics - RGMII Mode
7.10.5.17 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
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Table 7-116. Timer Timing Conditions
PARAMETER
MIN
0.5
2
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
10
Table 7-117. Timer Input Timing Requirements
see Figure 7-107
NO.
PARAMETER
tw(TINPH)
tw(TINPL)
DESCRIPTION
MODE
MIN
MAX UNIT
T1
Pulse duration, high
Pulse duration, low
CAPTURE 2 + 4P(1)
CAPTURE 2 + 4P(1)
ns
ns
T2
(1) P = functional clock period in ns.
Table 7-118. Timer Output Switching Characteristics
see Figure 7-107
NO.
PARAMETER
tw(TOUTH)
tw(TOUTL)
DESCRIPTION
MODE
PWM
PWM
MIN
-2 + 4P(1)
-2 + 4P(1)
MAX
UNIT
ns
T3
Pulse duration, high
Pulse duration, low
T4
ns
(1) P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
T3
T4
TIMER_IOx (outputs)
TIMER_01
Figure 7-107. Timer Timing Requirements and Switching Characteristics
For more information, see Timers section in Peripherals chapter in the device TRM.
7.10.5.18 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
Table 7-119. UART Timing Conditions
PARAMETER
MIN
0.5
1
MAX
5
UNIT
V/ns
pF
INPUT CONDITIONS
SRI
Input slew rate
OUTPUT CONDITIONS
CL
Output load capacitance
30
Table 7-120. UART Timing Requirements
see Figure 7-108
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
4
tw(RX)
Pulse width, receive data bit, high or low
0.95U(1)
1.05U(1)
ns
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Table 7-120. UART Timing Requirements (continued)
see Figure 7-108
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
5
tw(CTS)
Pulse width, receive start bit, high or low
0.95U(1)
ns
(1) U = UART baud time in ns = 1/programmed baud rate.
Table 7-121. UART Switching Characteristics
see Figure 7-108
NO.
PARAMETER
DESCRIPTION
Programmable baud rate
MODE
15 pF
30 pF
MIN
MAX UNIT
TDB Mbps
0.115 Mbps
ns
f(baud)
1
2
3
td(CTS-TX)
tw(TX)
Delay time, CTS bit to transmit data
30
Pulse width, transmit data bit, high or low
Pulse width, transmit start bit, high or low
U - 2.2(1) U + 2.2(1)
U - 2.2(1)
ns
ns
tw(RTS)
(1) U = UART baud time in ns = 1/programmed baud rate.
Figure 7-108. UART Timing Requirements and Switching Characteristics
For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.
7.10.5.19 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
The USB 3.1 GEN1 subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0.
Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,
Detailed Description.
7.10.6 Emulation and Debug
For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
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7.10.6.1 Trace
Table 7-122. Trace Timing Conditions
PARAMETER
MIN
MAX UNIT
OUTPUT CONDITIONS
CL
Output load capacitance
2
5
pF
PCB CONNECTIVITY REQUIREMENTS
VDDSHV3 = 1.8V
VDDSHV3 =3.3V
200
100
ps
td(Trace Mismatch)
Propagation delay mismatch across all traces
ps
Table 7-123. Trace Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
1.8V Mode
Cycle time, TRC_CLK
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
6.50
2.50
2.50
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
0.81
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
0.81
0.81
0.81
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
3.3V Mode
DBTR1 tc(TRC_CLK)
DBTR2 tw(TRC_CLKH)
DBTR3 tw(TRC_CLKL)
Cycle time, TRC_CLK
8.67
3.58
3.58
ns
ns
ns
Pulse width, TRC_CLK high
Pulse width, TRC_CLK low
tosu(TRC_DATAV-
DBTR4
Output setup time, TRC_DATA valid to TRC_CLK edge
1.08
ns
TRC_CLK)
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge
1.08
1.08
1.08
ns
ns
ns
DBTR7 toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4
DBTR6
DBTR5
DBTR7
DBTR4
DBTR6
DBTR5
DBTR7
TRC_DATA
TRC_CTL
SPRSP08_Debug_01
Figure 7-109. Trace Switching Characteristics
Table 7-124. JTAG Timing Conditions
7.10.6.2 JTAG
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
2.0
V/ns
OUTPUT CONDITIONS
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Table 7-124. JTAG Timing Conditions (continued)
PARAMETER
MIN
MAX
UNIT
CL
Output load capacitance
5
15
pF
Table 7-125. JTAG Timing Requirements
see Figure 7-110
NO.
MIN
45.5
18.2
18.2
4
MAX
UNIT
ns
J1
J2
J3
tc(TCK)
Cycle time minimum, TCK
tw(TCKH)
Pulse width minimum, TCK high
ns
tw(TCKL)
Pulse width minimum, TCK low
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
Input setup time minimum, TDI valid to TCK high
Input setup time minimum, TMS valid to TCK high
Input hold time minimum, TDI valid from TCK high
Input hold time minimum, TMS valid from TCK high
ns
J4
J5
4
ns
2
ns
2
ns
Table 7-126. JTAG Switching Characteristics
see Figure 7-110
NO.
PARAMETER
MIN
MAX
UNIT
ns
J6
J7
td(TCKL-TDOI)
Delay time minimum, TCK low to TDO invalid
Delay time maximum, TCK low to TDO valid
0
td(TCKL-TDOV)
14
ns
J1
J2
J3
TCK
TDI / TMS
TDO
J4
J5
J4
J5
J7
J6
Figure 7-110. JTAG Timing Requirements and Switching Characteristics
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8 Detailed Description
8.1 Overview
AM64x is an extension of the Sitara’s industrial-grade family of heterogeneous Arm processors. AM64x is built
for industrial applications, such as motor drives and programmable logic controllers (PLCs), which require a
unique combination of real-time processing and communications with applications processing. AM64x combines
two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG, up to two Arm Cortex-A53 cores, up to four Cortex-
R5F MCUs and a Cortex-M4F MCU.
AM64x is architected to provide best-in-class real-time performance through the high-performance R5Fs, Tightly-
Coupled Memory banks, configurable SRAM partitioning, and low-latency paths to and from peripherals for rapid
data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control
loops found in servo drives, while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and
absolute encoder interfaces help enable a number of different architectures found in these systems.
The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-
time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term
Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux
world with the real-time world by enabling isolation between Linux applications and real-time streams through
configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and
the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.
The PRU-ICSSG in AM64x provides the flexible industrial communications capability necessary to run gigabit
TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU-ICSSG also enables
additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.
Functional safety features can be enabled through the integrated Cortex-M4F along with its dedicated
peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
Note
For more information on features, subsystems, and architecture of superset device System on Chip
(SoC), see the device TRM.
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8.2 Processor Subsystems
8.2.1 Arm Cortex-A53 Subsystem
The A53SS module supports the following features:
•
Dual Core A53 Cluster
– Full ARM v8-A Architecture Compliant
AArch32 and AArch64 Execution States
All exception levels EL0-3
A32 Instruction Set (Previously ARM instruction set)
T32 instruction set (previously Thumb instruction set)
A64 Instruction Set
•
•
•
•
•
– Advanced SIMD and Floating Point Extensions (NEON)
– ARMv8 Cryptography Extensions
– ARMv8 Cryptography Extensions
– ARM GICv3 architecture
– In-order pipeline with symmetric dual-issue of most instructions
– Harvard L1 with system MMU
•
•
32 KB Instruction Cache
32 KB Data Cache
– 256KB Shared L2 Cache
– Generic Timer(s)
– Debug
•
•
•
•
•
•
128-Bit VBUSM Master Interfaces (for axi_r and axi_r channels)
128-Bit VBUSM Slave Interface (for Accelerator Coherency Port)
64-bit Grey-coded system input time
48-bit Grey-coded debug input time
32-bit VBUSP slave interface for Debug
Integrated PBIST controller with BISOR
For more information, see Dual-A53 MPU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.2 Arm Cortex-R5F
The MCU_ARMSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®
CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and
various wrappers for protocol conversion and address translation for easy integration into the SoC.
Note
The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit
(FPU) extension.
For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the
device TRM.
8.2.3 Arm Cortex-M4F
Note
NOTE TO USERS:
The content of this section is UNDER DEVELOPMENT!
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The M4FSS module on AM64x acts as a safety channel (second channel - working in conjunction with an
external microcontroller) -or- provides a general purpose MCU.
The M4FSS module supports the following features:
•
•
•
•
•
•
•
•
Cortex M4F With MPU
ARMv7-M architecture
Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs
Ability to executed code from internal or external memories
192 KB of SRAM (I-Code)
64 KB of SRAM (D-Code)
External access to internal memories if allowed
Debug Support Including:
– DAP based Debug to the CPU Core
– Full Debug Features of CPU Core are enabled
– Standard ITM trace
– CTM Cross Trigger
– ETM Trace Support
•
Fault Detection and Correction
– SECDED ECC protection on I-CODE
– SECDED ECC protection on D-CODE
– Fault Error Interrupt Output
For more information, see Dual-A53 MPU Subsystem section in Processors and Accelerators chapter in the
device TRM.
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8.3 Accelerators and Coprocessors
8.3.1 PRU_ICSSG
The ICSS_G module supports the following main features:
•
•
2 ICSSG, each with 3 PRUs:
2 Ethernet MII_G_RT configurable connection to PRUs
– 2 ports RGMII/SGMII
– 2 ports MII
– RX Classifier
•
•
•
•
2 Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
1 MDIO
1 UART 16550, with a dedicated 192-MHz clock input to support 12-Mbps Profibus
2 industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast
compensation.
– Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable
pwm outputs.
– Up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.
1 Enhanced Capture Module (ECAP)
1 interrupt controller (INTC)
•
•
– 160 input events supported – 96 external, 64 internal
Flexible power management support
Integrated switched central resource with programmable priority
All memories support ECC
•
•
•
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -
Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.
8.4 Other Subsystems
8.4.1 PDMA Controller
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of
peripherals, which perform data transfers using memory mapped registers accessed via a standard non-
coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require
an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and
supporting only statically configured Transfer Request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer
complexity at each point in the system to match the requirements of whatever is being transferred to or from.
Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO
dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically
for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and
employs round-robin scheduling between channels in order to share the underlying DMA hardware.
There are five PDMA modules in the device.
For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.
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8.4.2 Peripherals
8.4.2.1 ADC
The analog-to-digital converter (ADC) module is an eight-channel general purpose analog-to-digital converter,
which supports 12-bit conversion samples from an analog front end (AFE).
There are two ADC modules in the device.
For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.
8.4.2.2 ATL
The ATL module supports the following features:
•
One ATL module, containing four ATL instances, for HD Radio support and asynchronous sample rate
conversion assistance
•
Each instance tracks the time error between two syncs (local audio word select [AWS] and baseband word
select [BWS])
•
•
Each instance selects between 28 mux choices for BWS and 30 mux choices for AWS.
Each instance generates modulated ATCLK clock signals with software-initiated pulse stealing. The intention
is to use these clocks to derive audio output bit clock on MCASP
Selection between ATL_VCLK clock or functional ATL_PCLK to run error counting timers and to derive
modulated ATCLK clock outputs.
•
•
Clock and reset management: Receives clock and reset signals from the device PSC module. The ATL
module receives hardware reset.
•
•
Power management: The ATL belongs to the PD0 power domain.
Local software reset
The ATL module not supports the following features:
•
•
Smart ATL_CLK_STOP
ATL_MOD_OUT[3:0] clock outputs
For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.
8.4.2.3 AASRC
The AASRC module supports the following main features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High performance Asynchronous Sample Rate Converter with 140dB Signal-to-Noise (SNR)
Up to 8 input and output stereo streams (16 audio channels)
4 input and output clock zones
Support for input and output audio sample rates from 8 kHz to 216 kHz
Automatically sensing/detection of input sample frequencies
Attenuation of sampling clock jitter
16-, 18-, 20-, 24-bit data input/output
Input/output sampling ratios from 16:1 to 1:16
32-sample input and output FIFO for each channel with independently configurable thresholds
Group mode, where multiple AASRC blocks use the same timing loop for input or output
Linear phase FIR filter
Controllable soft mute
Separate DMA events for input and output, for each channel and group
Interrupts for input, output, and error for channels and groups of channels
Channels belonging in an input/output clock zone may be configured and managed as a group or as
individual streams
•
•
Independent clock generator for each input and output clock zone
Independent rate and stamp generator for each input and output clock zone
The AASRC module has the following main constraints:
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•
•
The AASRC output rate divided by input rate must be between 1/16 and 16
Sample rate must be between 8 kHz and 216 kHz
For more information, see Audio Asynchronous Sample Rate Converter (AASRC) section in Peripherals chapter
in the device TRM.
8.4.2.4 DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution
of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The
desired accuracy can be programed based on calculation for each application. The DCC measures the
frequency of a selectable clock source using another input clock as a reference.
The device has sixteen instances of DCC modules.
For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.
8.4.2.5 DDRSS
Integrated in MAIN domain one instance of DDR Subsystem (DDRSS) is used as an interface to external
SDRAM devices which can be utilized for storing program or data. DDRSS provides the following main features:
•
•
•
•
•
•
•
•
•
•
• Support of DDR4 / LPDDR4 memory types
• 16-bit memory bus interface with in-line ECC
• Up to 2 GB memory address range
• System bus interface: little endian only with 256-bit data width
• Configuration bus Interface: little endian only with 32-bit data width
• Support of dual rank configuration
• Support of automatic idle power saving mode when no or low activity is detected
• Class of Service (CoS) - three latency classes supported
• Prioritized refresh scheduling
• Statistical counters for performance management
For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.
8.4.2.6 ECAP
This section describes the Enhanced Capture (ECAP) module for the device.
For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.
8.4.2.7 EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;
instead, the EPWM is built up from smaller single channel modules with separate resources and that can
operate together as required to form a system. This modular approach results in an orthogonal architecture and
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance
on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x
instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so
forth.
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral
modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules
can also operate stand-alone.
The device has six instances of EPWM modules.
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For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.
8.4.2.8 ELM
The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when
reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then
correct the data block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses this
to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome
polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an
optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-
Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome
polynomials.
For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.
8.4.2.9 ESM
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device
into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event
and/or manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an
external controller is able to reset the device or keep the system in safe, known state.
For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.
8.4.2.10 EQEP
The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary
incremental encoder to get position, direction and speed information from a rotating machine for use in high
performance motion and position control system. The disk of an incremental encoder is patterned with a single
track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined
as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is
added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate
an absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position and zero reference.
To derive direction information, the lines on the disk are read out by two different photo-elements that "look" at
the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized with a
reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the disk
rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other.
These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders
is defined as the QEPA channel going positive before the QEPB channel and vise versa.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at a
geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the
QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder
directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 KHz, so
by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the
motor.
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.
8.4.2.11 GPIO
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, user can write to an internal register to
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control the state driven on the output pin. When configured as an input, user can obtain the state of the input by
reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different
interrupt/event generation modes.
For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.
8.4.2.12 GPMC
The GPMC module supports the following features:
•
•
Data path to external memory device can be 32, 16 or 8 bits wide
Support for the following memory types:
– Asynchronous or synchronous 8-bit memory or device (non-burst device)
– Asynchronous or synchronous 16-bit memory or device
– Asynchronous or synchronous 32-bit memory or device
– 16-bit non-multiplexed NOR Flash device
– 16-bit address and 32-bit address and data multiplexed NOR Flash device
– 8-bit and 16-bit NAND flash device
– 16-bit and 32bit pSRAM device
•
Supports Error Code detection using BCH code (t=4, 8 or 16) or Hamming code for 8-bit or 16-bit NAND-
flash, organized with page size of 512 Byte, 1Kbytes, or more. • Supports 1 GByte maximum addressing
capability, which can be divided into 8 independent chip-select with programmable bank size and base
address on 16 MByte, 32 MByte, 64 MByte, or 128 MByte boundary.
Fully-pipelined operation for optimal memory bandwidth usage
Supports external device clock frequency of /1, /2, /3, and /4 divide of interface clock
Supports programmable auto-clock gating when there is no access
Supports MIdlereq/SIdleAck protocol
•
•
•
•
•
Supports the following interface protocols when communicating with external memory or external devices:
– Asynchronous read/write access
– Asynchronous read page access (4-8-16 Word16), 4-8-16 Word32
– Synchronous read/write access
– Synchronous read burst access without wrap capability (4-8-16-32 Word16, 4-8-16 Word32)
– Synchronous read burst access with wrap capability (4-8-16-32 Word16, 4-8-16 Word32)
Address and data multiplexed access
Each chip-select has independent and programmable control signal timing parameters for Setup and Hold
time. Parameters are set according to the memory device timing parameters, with one interface clock cycle
timing granularity.
•
•
•
•
•
•
Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin
Supports bus keeping
Supports bus turn around
Pre-fetch and write posting engine associated with system DMA, to get full performance from NAND device,
and with minimum impact on NOR/SRAM concurrent access monitoring (up to 4 WAIT pins)
For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
8.4.2.13 I2C
The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the multi-
master I2C bus, which allows serial transfer of 8-bit data to and from other I2C master and slave devices,
through a two-wire interface.
The I2C module supports the following main features:
•
Compliant with Philips I2C specification version 2.1
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•
•
Supports OmniVision Serial Camera Control Bus Protocol (SCCB)
Supports standard mode (up to 100K bits/s), fast mode (up to 400K bits/s), and high-speed mode (up to
3.4Mb/s).
•
•
•
•
•
Multi-master transmitter and slave receiver mode
Multi-master receiver and slave transmitter mode
Combined master transmit/receive and receive/transmit modes
7-bit and 10-bit device addressing modes
Built-in FIFO for buffered read or write
– Parameterizable size of 8 to 64 bytes
•
•
•
•
Programmable multi-slave channel (responds to 4 separates addresses)
Programmable clock generation
Support for asynchronous wake-up
Two DMA channels, one interrupt line
For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device
TRM.
8.4.2.14 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed
real-time control with a high level of security. CAN has high immunity to electrical interference and the ability to
self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices
can coexist on the same network without any conflict.
The device supports 2 MCAN modules
For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device
TRM.
8.4.2.15 MCRC Controller
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of a memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the
signature for a set of data and then compare the calculated signature value against a pre-determined good
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC
controller compresses each data being read through CPU read data bus.
For more information, see MCRC Controller section in Interprocessor Communication chapter in the device
TRM.
8.4.2.16 MCSPI
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.
There are total of seven MCSPI modules in the device.
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.
8.4.2.17 MMCSD
There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1.
Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and
MMCSD1 is associated with MMC1.
The MMCSD Host Controller supports:
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•
•
•
•
•
•
•
One controller with 8-bit wide data bus
One controller with 4-bit wide data bus
Support of eMMC5.1 Host Specification (JESD84-B51)
Support of SD Host Controller Standard Specification - SDIO 3.00
Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3
eMMC Electrical Standard 5.1 (JESD84-B51)
Multi-Media card features:
– Backward compatible with earlier eMMC standards
– Legacy MMC SDR: 1.8 V, 8/4/1-bit bus width, 0-25 MHz, 25/12.5/3.125 MB/s
– High Speed SDR: 1.8 V, 8/4/1-bit bus width, 0-50 MHz, 50/25/6.25 MB/s
– High Speed DDR: 1.8 V, 8/4-bit bus width, 0-50 MHz, 100/50 MB/s
– HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s
SD card support: SDIO, SDR12, SDR25, SDR50, DDR50
•
•
System bus interface: CBA 4.0 VBUSM master port with 64-bit data width and 64-bit address, little endian
only
•
Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear
incrementing addressing mode, little endian only
For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.
8.4.2.18 OSPI
The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which
allows single, dual, quad or octal read and write access to external flash devices. This module has a memory
mapped register interface, which provides a direct memory interface for accessing data from external flash
devices, simplifying software requirements.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up
to silently perform some requested operation, signalling its completion via interrupts or status registers. For
indirect operations, data is transferred between system memory and external flash memory via an internal
SRAM which is loaded for writes and unloaded for reads by a device master at low latency system speeds.
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using
user programmable configuration registers.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
8.4.2.19 PCIE
Each PCIe subsystem supports the following main features:
•
•
•
•
•
•
•
•
•
•
•
•
Dual mode – root port (RP) or end point (EP) modes. Selectable through bootstrap pins.
1-lane configuration with up to 5.0GT/lane.
62.5/125 MHz operation on PIPE interface for Gen1/Gen2 respectively
Constant 32-bit PIPE width for Gen1/Gen2 modes
Maximum outbound payload size of 128 bytes
Maximum inbound payload size of 128 bytes
Maximum remote read request size of 4K bytes
Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.
Four virtual channels (4VC)
Resizable BAR capability
SRIS support
Power management
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– L1 Power management substates support
– D1 support
– L1 PM substate power shutoff support
•
•
•
Legacy, MSI, and MSI-X interrupt support
32 outbound address translation regions
Precision time measurement (PTM)
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter in the device TRM.
8.4.2.20 SerDes
Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/
Deserializer (SERDES) Multi-protocol Multi-link modules with the following main blocks:
•
•
Quad lane PHY with common module for peripheral and Tx clocking handling
Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/
decoding and ymbol alignment
•
•
MUX module for device interfaces multiplexing into a single SERDES lane (Tx and Rx)
A wrapper for sending control and reporting status signals from the SerDes and muxes
For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.
8.4.2.21 RTI
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)
functionality for the device.
The Real Time Interrupt module provides timer functionality for operating systems and for benchmarking code.
The module incorporates several counters, which define the timebases needed for scheduling in the operating
system.
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for
Automotive Electronics”) as well as OSEK/Time compliant operating systems.
The timers also provide the ability to benchmark certain areas of code by reading the counter contents at the
beginning and the end of the desired code range and calculating the difference between the values.
For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.
8.4.2.22 DMTIMER
The DMTIMER module supports the following main features:
•
•
•
Interrupts generated on overflow, compare and capture
Free running 32-bit upward counter
Supported modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
•
•
•
•
Programmable divider clock source (2n with n=[0:8])
Dedicated input trigger for capture mode, and dedicated output trigger/PWM (pulse width modulation) signal
On the fly read/write register (while counting)
Generate 1-ms tick with 32768-Hz functional clock
For more information, see Timers section in Peripherals chapter in the device TRM.
8.4.2.23 UART
The UART module supports the following main features:
•
16C750 compatibility
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•
•
•
•
Baud rate from 300 bps up to 3.6864 Mbps (subject to functional clock frequency)
Auto-baud between 1200 bps and 115.2 Kbps
Synchronous mode (USART) support with either external clock or generated clock
Software/hardware flow control
– Programmable Xon/Xoff characters
– Programmable Auto-RTS and Auto CTS
Programmable serial interface characteristics
– 5, 6, 7, or 8-bit characters
•
– Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and
detection
– 1-, 1.5-, or 2-stop bit generation
•
•
•
•
•
•
•
•
Optional multi-drop transmission
Configurable time-guard feature
False start bit detection
Line break generation and detection
Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
Fully prioritized interrupt system controls
Internal test and loopback capabilities
ISO7816 Functions
– Half duplex protocol using TX line in bidirectional mode
– Support for T+0 and T=1 protocols
RS-485 External transceiver auto flow control support
•
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in
Peripherals chapter in the device TRM.
8.4.2.24 USB
The USB module supports the following main features:
USB interface:
•
•
•
•
•
•
•
Compliant with USB 3.1 Gen1 specification
Compliant with xHCI 1.1 specification
Limited USB 2.0 on-the-go support
SuperSpeed Gen1 (5 Gbps), high speed (480 Mbps), and full (12Mbps) Device
SuperSpeed Gen1 (5 Gbps), high speed (480 Mbps), full (12Mbps), and low speed (1.5 Mbps) Host
Single USB2.0 port
Single USB3.1 port
Dual mode operation:
•
•
OTG 2.0 host negotiation protocol (HNP) support
OTG 2.0 session request support (SRP) support
Host mode:
•
•
•
•
•
64 slots supported
Up to 128 periodic endpoints supported simultaneously
256 primary streams supported
MSI support
Root hub functionality
For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device
TRM.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Power Supply Mapping
Note
NOTE TO USERS:
The content of this section is UNDER DEVELOPMENT!
9.2 Device Connection and Layout Fundamentals
9.2.1 Power Supply Decoupling and Bulk Capacitors
9.2.1.1 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that
follow the board design guidelines contained in the application report.
9.2.2 External Oscillator
For more information about External Oscillators, see Section 7.10.4, Clock Specifications
9.2.3 JTAG and EMU
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual
9.2.4 Reset
Note
NOTE TO USERS:
The content of this section is UNDER DEVELOPMENT!
9.2.5 Unused Pins
For more information about Unused Pins, see Section 6.5, Connections for Unused Pins
9.2.6 Hardware Design Guide
Note
NOTE TO USERS:
The content of this section is UNDER DEVELOPMENT!
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9.3 Peripheral- and Interface-Specific Design Information
9.3.1 DDR Board Design and Layout Guidelines
The goal of the AM64x DDR Board Design and Layout Guidelines is to make the DDR system implementation
straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that
allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports
board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document.
9.3.2 OSPI and QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the OSPI and QSPI
interfaces.
9.3.2.1 No Loopback and Internal Pad Loopback
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm
as stripline or ~8cm as microstrip)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-1
Propagation delays and matching:
– A to B < 450 ps
– Matching skew: < 60 ps
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_01
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.
Figure 9-1. OSPI Interface High Level Schematic
9.3.2.2 External Board Loopback
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.
•
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must
be approximately equal to the signal propagation delay of the control and data signals between the flash
device and the SoC device (E to F, or F to E)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-2
Propagation delays and matching:
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– A to B = E to F = (C to D) / 2
– Matching skew: < 60 ps
Note
The OSPI Board Loopback Hold time requirement (described in Section 7.10.5.14, OSPI) is larger
than the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO
pin to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate.
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
R1
0 Ω*
MCU_OSPI[x]_LBCLKO
D
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_02
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine
tuning, if needed.
Figure 9-2. OSPI Interface High Level Schematic
9.3.2.3 DQS (only available in Octal Flash devices)
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS
output pin (C to D)
•
•
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 9-3
Propagation delays and matching:
– A to B = C to D
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– Matching skew: < 60 ps
A
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
D
OSPI device DQS
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
J7ES_OSPI_Board_03
* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.
Figure 9-3. OSPI Interface High Level Schematic
9.3.3 USB Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30 V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the
Figure 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these
external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be
less than 100 nA.
(1)
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Device
USBn_VBUS
16.5 kΩ
1%
3.5 kΩ
1%
VBUS signal
10 kΩ
1%
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
J7ES_USB_VBUS_01
Figure 9-4. USB VBUS Detect Voltage Divider / Clamp Circuit
The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 9-4 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
9.3.4 System Power Supply Monitor Design Guidelines
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a
single pre-regulated power source for the entire system. This supply is monitored by comparing the output of an
external voltage divider circuit sourced by this supply with an internal voltage reference, with a power fail event
being triggered when the voltage applied to VMON_VSYS drops below the internal reference voltage. The actual
system power supply voltage trip point is determined by the system designer when selecting component values
used to implement the external resistor voltage divider circuit.
When designing the resistor divider circuit it is important to understand various factors which contribute to
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the
VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1%
resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This
minimizes variability contributed by resistor value tolerances. Input leakage current associated with
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the
voltage divider output. The VMON_VSYS input leakage current may be in the range of 10 nA to 2.5 µA when
applying 0.45 V.
Note
The resistor voltage divider shall be designed such that its output voltage never exceeds the
maximum value defined in Section 7.4, Recommended Operating Conditions, during normal operating
conditions.
Figure 9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger
threshold is 5 V - 10%, or 4.5 V.
For this example, it is important to understand which variables effect the maximum trigger threshold when
selecting resistor values. It is obvious a device which has a VMON_VSYS input threshold of 0.45 V + 3% needs
to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The
effect of resistor tolerance and input leakage also needs to be considered, but how these contributions effect the
maximum trigger point may not be obvious. When selecting component values which produce a maximum
trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of
R2 is 1% high combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When
implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold
of 4.523 V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
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output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.008 V.
This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.
Approximately 250 mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this
range is introduced by loading error when VMON_VSYS input leakage current is 2.5 µA.
The resistor values selected in this example produces approximately 100 µA of bias current through the resistor
divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to
about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor
divider bias current vs loading error is something the system designer needs to consider when selecting
component values.
The system designer should also consider implementing a noise filter on the voltage divider output since
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done by
installing a capacitor across R1 as shown in Figure 9-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.
Device
VMON_VSYS
R2
VSYS
40.2 kΩ 1%
C1
Value = Determined by system designer
(System Power Supply)
4.81 kΩ
1%
R1
VSS
SPRSP56_VMON_ER_MON_01
Figure 9-5. System Supply Monitor Voltage Divider Circuit
VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8 V power supplies. An
internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can
program each internal resistor divider to create appropriate under voltage and over voltage interrupts.
VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3 V power supplies. An
internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can
program each internal resistor divider to create appropriate under voltage and over voltage interrupts.
9.3.5 High Speed Differential Signal Routing Guidance
The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application
report.
9.3.6 External Capacitors
Note
NOTE TO USERS:
The content of this section is UNDER DEVELOPMENT!
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9.3.7 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application report.
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10 Device and Documentation Support
10.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, AM64x). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of AM64x devices in the ALV package type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.
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10.1.1 Standard Package Symbolization
Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.
aBBBBBBrZfYytPPPQ1
A1 (PIN ONE INDICATOR)
XXXXXXX
G1
ZZZ
YYY
O
Figure 10-1. Printed Device Reference
10.1.2 Device Naming Convention
Table 10-1. Nomenclature Description
FIELD PARAMETER FIELD DESCRIPTION
VALUE
DESCRIPTION
a
Device evolution stage
X
Prototype
P
Preproduction (production test flow, no reliability data)
Production
BLANK
BBBBBB
Base production part
number
AM6442
AM6441
AM6421
See Table 5-1, Device Comparison
AM6412
AM6411
r
Z
f
Device revision
A
S
K
C
D
E
F
SR 1.0
Device Speed Grades
See Table 7-1, Speed Grade Maximum Frequency
Features
(see Table 5-1)
No Additional Features
ICSS Enabled
ICSS + EtherCAT HW Accelerator + CAN-FD Enabled
ICSS + EtherCAT HW Accelerator + CAN-FD + Pre-integrated Stacks
Enabled
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Table 10-1. Nomenclature Description (continued)
FIELD PARAMETER FIELD DESCRIPTION
VALUE
DESCRIPTION
Y
y
t
Functional Safety
G
F
Non-Functional Safety
Functional Safety
Non-Secure
Security
G
Other
A
Secure
Temperature (1)
-40°C to 105°C - Extended Industrial (see Section 7.4, Recommended
Operating Conditions)
PPP
Q1
Package Designator
ALV
Q1
ALV FCBGA-N441 (17.2 mm × 17.2 mm) Package
Auto Qualified (Q100)
Automotive Designator
BLANK
Standard
XXXXXXX
YYY
ZZZ
Lot Trace Code (LTC)
Production Code; For TI use only
Production Code; For TI use only
Pin one designator
O
G1
ECAT—Green package designator
(1) Applies to device max junction temperature.
Note
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
10.2 Tools and Software
The following products support development for AM64x platforms:
Development Tools
Clock Tree Tool for Sitara, Automotive, Vision Analytics, and Digital Signal Processors The Clock Tree
Tool (CTT) for Sitara™ Arm®, Automotive, and Digital Signal Processors is an interactive clock tree
configuration software that provides information about the clocks and modules in these TI devices. It allows the
user to:
•
•
•
•
Visualize the device clock tree
Interact with clock tree elements and view the effect on PRCM registers
Interact with the PRCM registers and view the effect on the device clock tree
View a trace of all the device registers affected by the user interaction with clock tree
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step
of the application development flow. Familiar tools and interfaces allow users to get started faster than ever
before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for
embedded developers.
Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring pin
multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as
C header/code files that can be imported into software development kits (SDKs) or used to configure customer's
custom software. Version 4 of the Pin Mux utility adds the capability of automatically selecting a mux
configuration that satisfies the entered requirements.
Power Estimation Tool (PET) Power Estimation Tool (PET) provides users the ability to gain insight in to the
power consumption of select TI processors. The tool includes the ability for the user to choose multiple
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application scenarios and understand the power consumption as well as how advanced power saving
techniques can be applied to further reduce overall power consumption.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
10.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The following documents describe the AM64x devices.
Technical Reference Manual
AM64x Processors Silicon Revision 1.0 Technical Reference Manual Details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in the
AM64x family of devices.
Errata
AM64x Processors Silicon Revision 1.0 Silicon Errata Describes the known exceptions to the functional
specifications for the device.
10.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.5 Trademarks
Sitara™ is a trademark of Texas Instruments Incorporated.
CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Code Composer Studio™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
Arm®, Cortex®, TrustZone® are registered trademarks of Arm Limited.
PCI-Express® is a registered trademark of PCI-SIG.
EtherCAT® is a registered trademark of Beckhoff Automation GmbH.
All trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AM6411AKCGHAALV
AM6412AKCGHAALV
AM6421ASDGHAALV
AM6441ASDGHAALV
AM6442ASDGHAALV
XAM6442ASFGGAALV
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
ALV
ALV
ALV
ALV
ALV
ALV
441
441
441
441
441
441
84
84
84
84
84
1
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
RoHS (In work)
& Non-Green
SFGGAALV
XAM6442A
709
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ALV0441A
FCBGA - 2.657 mm max height
SCALE 0.900
BALL GRID ARRAY
17.3
17.1
A
B
BALL A1 CORNER
PIN 1 ID
(OPTIONAL)
17.3
17.1
(
12.8)
0.1 C
(
(
10.8)
16.8)
(1.45)
2.652
2.332
0.2 C
C
SEATING PLANE
0.15 C
(0.662)
0.5
TYP
0.3
16 TYP
SYMM
(0.6) TYP
(0.6) TYP
0.8 TYP
AA
Y
W
V
U
T
R
P
N
M
L
SYMM
16
K
J
TYP
H
G
F
E
D
C
B
A
0.55
0.45
C A B
441X
0.25
0.1
1
2
3
4
5
6 7 8 9 10 12 14 16 18 20
11 13 15 17 19 21
C
0.8 TYP
4225999/A 06/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
ALV0441A
FCBGA - 2.657 mm max height
BALL GRID ARRAY
441X ( 0.4)
(0.8) TYP
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16
20 21
17 18 19
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SNOWN
SCALE:6X
0.07 MAX
0.07 MIN
METAL UNDER
SOLDER MASK
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225999/A 06/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ALV0441A
FCBGA - 2.657 mm max height
BALL GRID ARRAY
441X 0.4
(0.8) TYP
1
2 3
4
5
6
7
8
9
10 11 12 13 14 15 16
20 21
17 18 19
A
(0.8) TYP
B
C
D
E
F
G
H
J
K
L
SYMM
M
N
P
R
T
U
V
W
Y
AA
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 6X
4225999/A 06/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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