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AM6546BACDXA [TI]

具有千兆位 PRU-ICSS 的四核 Arm® Cortex®-A53 和双核 Arm Cortex-R5F Sitara™ 处理器 | ACD | 784 | -40 to 105;
AM6546BACDXA
型号： AM6546BACDXA
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有千兆位 PRU-ICSS 的四核 Arm® Cortex®-A53 和双核 Arm Cortex-R5F Sitara™ 处理器 | ACD | 784 | -40 to 105

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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
AM654x、AM652x Sitara™ 处理器  
器件修订版本2.1  
– 8 GB 全部可寻址空间  
• 通用存储器控制器(GPMC)  
1 特性  
处理器内核：  
SafeTI™ 半导体组件：  
• 专为功能安全应用而设计  
• 根据IEC 61508 标准的要求开发  
• 达到SIL-3 的系统完整性  
• 对于MCU 安全岛，包含足够的诊断以达到SIL-2  
的随机故障完整性要求  
• 对于SoC 的其余部分，包含足够的诊断以达到  
SIL-2 的随机故障完整性要求  
• 双核或四核Arm® Cortex®-A53 微处理器子系统  
（高达1.1GHz）  
– 最多两个双核或两个单核Arm® Cortex®-A53 集  
群（具有512KB L2 缓存，包括SECDED）  
– 每个A53 内核具有32KB L1 指令缓存和32K L1  
数据缓存  
• 双核Arm® Cortex®-R5F（高达400MHz）  
• 此外，还需要配置足够的架构指标，以实现考虑特  
定安全概念的SIL-3 的执行（如软件互惠式比较）  
• 提供功能安全手册  
– 支持锁步模式  
– 每个R5F 内核具有16KB 指令缓存、16KB 数据  
缓存和64KB RAM  
• 安全相关认证  
工业子系统：  
• 三个千兆位工业通信子系统(PRU_ICSSG)  
– TÜV SÜD 组件级功能安全认证[正在认证]  
• 功能安全特性：  
– 每个PRU_ICSSG 具有最多两个10/100/1000  
以太网端口  
– 计算临界存储器的ECC 或奇偶校验和内部总线  
互联  
– 有助于防止干扰(FFI) 的防火墙  
– 支持两个SGMII 端口(2)  
– 与10/100Mb PRU-ICSS 兼容  
– 每个PRU_ICSSG 具有24 个PWM  
• 适用于CPU、高端计时器和片上RAM 的内  
置自检(BIST)  
– 针对诊断测试的硬件错误注入支持  
– 用于捕获功能安全相关错误的错误信号模块  
(ESM)  
• 逐周期控制  
• 增强跳闸控制  
– 每个PRU_ICSSG 具有18 个Σ-Δ滤波器  
• 短路逻辑  
• 过流逻辑  
– 电压、温度和时钟监控  
– 多个时钟域内的窗口式和非窗口式看门狗计时器  
• MCU 岛  
– 每个PRU_ICSSG 具有6 个多协议位置编码器  
接口  
– 隔离了双核Arm® Cortex®-R5F 微处理器子系  
统，  
存储器子系统：  
– 独立的电压、时钟、复位和专用外设  
– 与SoC 其余部分的内部MCSPI 连接  
• 高达2MB 的片上L3 RAM（具有SECDED）  
• 多核共享存储器控制器(MSMC)  
– 高达2MB（2 组× 1MB）的SRAM（具有  
SECDED）  
安全：  
• 支持安全启动  
• 共享相干2 级或3 级存储器映射SRAM  
• 共享相干3 级缓存  
– 256 位处理器端口总线和40 位物理地址总线  
– 用于连接处理器或设备主机的相干统一双向接口  
– L2、L3 缓存预热和后清除  
– 硬件强制可信根  
– 支持通过备用秘钥转换可信根  
– 支持接管保护、IP 保护和防回滚保护  
• 支持加密加速  
– 会话感知型加密引擎可基于输入数据流自动切换  
密钥材料  
– 支持加密内核  
– 具有饥饿限制的带宽管理  
– 一个基础设置主接口  
– 单个外部存储器主接口  
– 支持分布式虚拟系统  
– 支持内部DMA 引擎- 数据路由单元(DRU)  
– ECC 错误保护  
• AES –128/192/256 位秘钥大小  
• 3DES –56/112/168 位秘钥大小  
• MD5、SHA1  
• SHA2 –224/256/384/512  
• 具有真随机数生成器的DRBG  
• DDR 子系统(DDRSS)  
– 支持高达DDR-1600 的DDR4 存储器类型  
– 32 位数据总线和7 位SECDED 总线  
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问  
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SPRSP52  
 
AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
• 可在RSA/ECC 处理中提供帮助的PKA（公  
钥加速器）  
多媒体：  
• 显示子系统  
– DMA 支持  
• 调试安全性  
– 与两个显示输出相关联的两个完全输入映射覆盖  
管理器  
– 一个端口MIPI® DPI 并行接口  
– 安全软件控制的调试访问  
– 安全感知调试  
– 1 个OLDI 端口  
• 支持可信执行环境(TEE)  
• PowerVR® SGX544-MP1 3D 图形处理单元(GPU)  
• 一个摄像头串行接口2 (MIPI CSI-2)  
• 一个端口视频捕捉：BT.656/1120（没有嵌入式同  
步）  
– 基于Arm® TrustZone® 的TEE  
– 可实现隔离的广泛防火墙支持  
– 安全DMA 路径和互联  
– 安全监视器/计时器/IPC  
• 安全存储支持  
高速接口：  
• 支持一个千兆位以太网(CPSW) 接口  
• OSPI 接口实时加密和实时认证支持  
• 通过基于数据包的硬件加密引擎为数据（有效载  
荷）加密/认证提供网络安全支持  
• 用于密钥和安全管理的安全协处理器(DMSC)，具  
有用于安全软件的专用设备级互连  
– RMII (10/100) 或RGMII (10/100/1000)  
– IEEE1588（2008 附件D、E 和F）及802.1AS  
PTP  
– 音频/视频桥接(P802.1Qav/D6.0)  
– 节能以太网(802.3az)  
SoC 服务：  
• 设备管理安全控制器(DMSC)  
– 巨型帧（2024 字节）  
– 第45 条MDIO PHY 管理规范  
• 两个PCI-Express® (PCIe®) 修订版3.1 子系统(2)  
– 集中式SoC 系统控制器  
– 管理系统服务，包括初始引导、安保、功能安全  
和时钟/复位/电源管理  
– 支持激活和低功耗模式的电源管理控制器  
– 通过消息管理器与各种处理单元通信  
– 简化的接口可优化未使用的外设  
– 跟踪和调试功能  
– 支持第二代(5.0GT/s) 运行  
– 两个独立的单通道端口或一个双通道端口  
– 支持并发根复合体和端点运行  
• USB 3.1 双角色设备(DRD) 子系统(2)  
– 一个增强型超速第一代端口  
– 一个USB 2.0 端口  
– 每个端口均可独立配置为USB 主机、USB 外设  
或USB DRD  
• 十六个32 位通用计时器  
• 两个数据移动和控制导航器子系统(NAVSS)  
– 环形加速器(RA)  
– 统一DMA (UDMA)  
– 最多2 个计时器管理器(TM)（每个负责1024  
个计时器）  
通用连接：  
• 6 个内部集成电路(I2C™) 端口  
• 5 个可配置UART/IrDA/CIR 模块  
• 2 个同步闪存接口，配置为  
– 两个OSPI 闪存接口  
– 或HyperBus™ 和OSPI1 闪存接口  
• 2 个12 位模数转换器(ADC)  
– 最高每秒400 万个样本  
– 八个多路复用模拟输入  
• 8 个多通道串行外设接口(MCSPI) 控制器  
– 两个具有内部连接  
– 六个具有外部接口  
• 通用I/O (GPIO) 引脚  
控制接口：  
• 6 个增强型高分辨率脉宽调制器(EHRPWM) 模块  
• 一个增强型捕捉(ECAP) 模块  
• 3 个增强型正交编码器脉冲(EQEP) 模块  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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汽车接口：  
模拟/系统集成：  
• 集成了USB VBUS 检测  
• 2 个模块化控制器区域网(MCAN) 模块，具有完整  
CAN-FD 支持  
• 针对DDR 复位的失效防护I/O  
• 复位期间禁用所有I/O 引脚驱动器，以防止总线冲  
突
• 复位期间禁用默认I/O 牵引功能，以防止系统冲突  
• 支持动态I/O Pinmux 配置更改  
音频接口：  
• 3 个多通道音频串行端口(MCASP) 模块  
媒体和数据存储：  
• 2 个多媒体卡™/安全数字® (MMC™/SD®) 接口  
片上系统(SoC) 架构：  
简化的电源管理：  
• 支持从UART、I2C、OSPI、HyperBus、并行  
NOR 闪存、SD 或eMMC™、USB、PCIe 和以太  
网接口的主引导  
• 28nm CMOS 技术  
• 23mm × 23mm、0.8mm 间距、784 引脚FCBGA  
(ACD)  
• 完全支持双电压I/O 的简化电源序列  
• 集成的LDO 可降低电源解决方案的复杂性  
• 集成的SDIO LDO 可为SD 接口处理自动电压转换  
• 集成了上电复位(POR) 发生功能，可降低电源解决  
方案的复杂性  
• 集成了电压监控器，可实现功能安全监控  
• 集成了电源干扰检测器，可检测快速电源瞬变  
2 应用  
• 工业可编程逻辑控制器(PLC)  
• 工厂自动化（具有安全功能）  
• 多协议现场总线通信  
• 工业PC  
• 工业机器人  
• 人机界面(HMI)  
• 电网基础设施保护继电器  
• 机器人电机驱动器  
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3 说明  
AM654x 和AM652x Sitara™ 处理器是Arm® 应用处理器，旨在满足现代工业4.0 嵌入式产品的复杂处理需求。  
AM654x 和 AM652x 器件将四个或两个 Arm® Cortex®-A53 内核与双 Arm® Cortex®-R5F MCU 子系统（包括旨在  
帮助客户实现其最终产品功能安全目标的特性）和三个千兆位工业通信子系统 (PRU_ICSSG) 组合在一起，从而  
为功能安全应用实现支持 SoC 且具有工业连接和处理能力的高性能工业控制。AM65xx 目前正在按照 IEC 61508  
标准要求，接受TÜV SÜD 的认证评估。  
AM654x 中的四个 Arm® Cortex®-A53 内核分布在两个具有共享 L2 存储器的双核集群中，以创建两个处理通道。  
AM652x 中的两个Arm® Cortex®-A53 内核可通过单个双核集群和两个单核集群选项提供。片上存储器、外设和互  
联中包含广泛的 ECC，可确保可靠性。整个 SoC 中包括旨在帮助客户设计可实现他们的功能安全目标的特性  
（正在等待 TÜV SÜD 评估结果）。除了 DMSC 管理的粒度防火墙之外，某些 AM654x 和 AM652x 器件上还提  
供了加密加速和安全启动功能。  
Arm® Cortex®-A53 RISC CPU 及 Arm® Neon™ 扩展可实现可编程性，而双 Arm® Cortex®-R5F MCU 子系统可作  
为两个内核用于一般用途或用于锁步模式，以帮助满足功能安全应用的需求。PRU_ICSSG 子系统可用于提供最  
多六个工业以太网端口，如 Profinet IRT、TSN、Ethernet/IP 或 EtherCAT® 等，或者用于标准千兆位以太网连  
接。  
TI 提供了一整套针对 Arm® 内核的软件和开发工具，其中包括 Processor SDK Linux、Linux-RT、RTOS 和  
Android 以及 C 语言编译器和一个可查看源代码执行情况的调试界面。我们将会提供相关功能安全和安保文档，  
以帮助客户开发功能安全或安保相关的系统。  
器件信息  
器件型号(1)  
封装  
封装尺寸  
AM6548ACD  
AM6528ACD  
AM6546ACD  
AM6526ACD  
FCBGA (784)  
FCBGA (784)  
FCBGA (784)  
FCBGA (784)  
23.0mm x 23.0mm  
23.0mm x 23.0mm  
23.0mm x 23.0mm  
23.0mm x 23.0mm  
(1) 如需更多信息，请参阅节11 机械、封装和可订购信息。  
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3.1 功能方框图  
图3-1 是器件的功能方框图。  
AM654x / AM652x  
Navigator Subsystem  
Industrial Subsystem  
GPU  
®
2xArm
Cortex®-A53
2x Arm®  
Cortex®-A53  
PowerVR®  
SGX544-MP1 3D  
Proxy  
UDMA  
RA  
2x PVU  
INTR  
CPTS  
12x Mailbox  
MCRC  
(C)  
3x PRU_ICSSG  
(up to 6x Ethernet Ports)  
Spinlock  
3x INTA  
2x TIMER-MGR  
DMSC  
512KBL2
withECC
512KB L2  
with ECC  
Channelized FW  
System Services  
Video Input  
Display Subsystem  
Memory Subsystem  
12x GP Timers  
4x RTI/WWDT  
PDMA  
CAL  
2x Video pipeline  
Blend/Scale/CSC  
MSMC  
2MB SRAM with ECC  
MIPI CSI-2  
LVDSRX  
Open LDI  
MIPI DPI  
Debug  
ELM  
BT.656/1120  
GPMC  
EMIF with ECC  
Security Accelerators  
MCU Island  
Navigator Subsystem  
PDMA  
ESM  
4x GP Timers  
2x RTI/WWDT  
AES  
SHA  
PKA  
2x Arm®  
Proxy  
INTA  
Cortex®-R5F  
(with optional Lockstep)  
UDMA  
INTR  
RA  
DRBG  
MD5  
ESM  
3DES  
MCRC  
Channelized FW  
Scratchpad RAM 512B  
MCU-MSRAM 512KB  
Interconnect  
GPIO  
Automotive Interfaces  
High-Speed Serial Interfaces  
Control Interfaces  
General Connectivity  
2x MCAN-FD(A)  
6x EHRPWM  
1x ECAP  
5x MCSPI(B)  
3x MCSPI(A)(B)  
2x ADC(A)  
PCIe®  
2x Single/1x Dual lane  
Gen 2(C)  
2x OSPI  
or 1xQSPI +  
1x HyperBus(A)  
3x EQEP  
1x USB 2.0 DRD  
1x USB 3.1 DRD(C)  
10/100/1000 Ethernet(A)  
5x I2C  
4x UART  
Audio Peripherals  
Media and Data Storage  
2x MMCSD  
3x MCASP  
1x I2C(A)  
1x UART (A)  
intro_001  
A. 该接口位于MCU 岛上，但整个系统都可以访问该接口。  
B. 一个端口仅用于内部连接；不连接到任何引脚。  
C. SGMII、USB3.1 和PCIe 共用总共两个串行器/解串器通道。  
图3-1. AM654x、AM652x 方框图  
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Table of Contents  
7.9 Timing and Switching Characteristics..................... 141  
8 Detailed Description....................................................249  
8.1 Overview.................................................................249  
8.2 Processor Subsystems........................................... 250  
8.3 Accelerators and Coprocessors..............................251  
8.4 Other Subsystems.................................................. 253  
8.5 Identification............................................................260  
8.6 Boot Modes.............................................................261  
9 Applications, Implementation, and Layout............... 262  
9.1 Device Connection and Layout Fundamentals....... 262  
9.2 Peripheral- and Interface-Specific Design  
Information................................................................ 263  
10 Device and Documentation Support........................273  
10.1 Device Nomenclature............................................273  
10.2 Tools and Software............................................... 275  
10.3 Documentation Support........................................ 276  
10.4 支持资源................................................................276  
10.5 Trademarks...........................................................276  
10.6 Electrostatic Discharge Caution............................277  
10.7 Glossary................................................................277  
11 Mechanical, Packaging, and Orderable  
1 特性................................................................................... 1  
2 应用................................................................................... 3  
3 说明................................................................................... 4  
3.1 功能方框图..................................................................5  
4 Revision History.............................................................. 7  
5 Device Comparison.........................................................9  
5.1 Related Products...................................................... 10  
6 Terminal Configuration and Functions........................11  
6.1 Pin Diagram.............................................................. 11  
6.2 Pin Attributes.............................................................12  
6.3 Signal Descriptions................................................... 61  
6.4 Pin Multiplexing.......................................................109  
6.5 Connections for Unused Pins................................. 121  
7 Specifications.............................................................. 124  
7.1 Absolute Maximum Ratings.................................... 124  
7.2 ESD Ratings........................................................... 126  
7.3 Power-On Hours (POH)..........................................127  
7.4 Recommended Operating Conditions.....................127  
7.5 Operating Performance Points................................130  
7.6 Electrical Characteristics.........................................132  
7.7 VPP Specifications for One-Time Programmable  
Information.................................................................. 278  
11.1 Packaging Information.......................................... 278  
(OTP) eFuses............................................................139  
7.8 Thermal Resistance Characteristics....................... 140  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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4 Revision History  
Changes from April 15, 2020 to June 29, 2021 (from Revision A (April 2020) to Revision B  
(June 2021))  
Page  
• 全局：文档产品状态从“预告信息(AI)”更改为“量产数据(PD)”...................................................................1  
• 全局：更新了整个文档中的表格、图和交叉参考的编号格式.............................................................................. 1  
• 全局：DDRSS 的范围；不支持DDR3L 和LPDDR4..........................................................................................1  
•
（功能方框图）：更新了AM654x、AM652x 方框图........................................................................................ 5  
• (Terminal Configuration and Functions): Updated section title......................................................................... 11  
• (Device Information): Updated/Changed table to reflect production part numbers...........................................12  
• (Pin Attributes): Updated/Changed PULL UP/DOWN TYPE "TBD" for MMC0 and MMC1 Ball Numbers....... 12  
• (Pin Attributes): Updated/Changed "VDDS_OCS0" ro "VDDS_OSC1"............................................................12  
• (DDRSS0 Signal Descriptions): Added a footnote reference to DDR_VREF_ZQ............................................63  
• (DDRSS Signal Mapping): ...............................................................................................................................66  
• (Signal Descriptions): Added note to clarify CPTS signal connection.............................................................. 85  
• (Signal Descriptions): Moved MCU CPTS signals from CPSW2G to CPTS section. Moved SYNCn_OUT  
signals from SYSTEM to CPTS section. Updated both sets of signal descriptions..........................................85  
• Updated CLK frequency unit from "KHz" to "kHz".......................................................................................... 104  
• (System0 Signal Descriptions): Added the DESCRIPTION for "GPMC0_FCLK_MUX" SIGNAL NAME....... 104  
• (Power Supply Signal Descriptions): Added associated footnotes for CAP_VDDA_1P8_SDIO,  
CAP_VDDSHV_SDIO, _1P8_SDIO, and VDDA_3P3_SDIO SIGNAL NAMES............................................. 105  
• Updated Reserved Balls Specific Connection Requirements to show MMC0/1_CALPAD should be left floating  
on PG2.0 and PG2.1...................................................................................................................................... 121  
• (Power-On Hours (POH)): Updated/Changed "TBD" for COMMERCIAL/EXTENDED TEMPERATURE  
RANGE "LIFETIME (POH)" for OPP_TURBO ...............................................................................................127  
• (Recommended Operating Conditions): Deleted the "Maximum peak-to-peak supply noise" for  
VDD_DLL_MMC0/1........................................................................................................................................127  
• (Analog ADC DC Electrical Characteristics): Updated/Changed the INL MAX value to "±4" LSB................. 134  
• (3-3V MODE): Added VIH and VIL rows for MMC0_* and MMC1_* signals with MIN voltage values.............137  
• Updated/Changed the associated footnotes, added "VDDS stands for …." and removed the (VIHSS) and  
(VILSS) footnotes............................................................................................................................................. 137  
• Added System Timing Conditions, Safety Error Signals Switching Characteristics table, Clock Timing  
Requirements, and Clock Switching Characteristics under System Timing .................................................. 146  
• Added Safety Error Signals Switching Characteristics table under Reset Electrical Data/Timing .................146  
• Updated description and limits in Timing Requirements for LVDSRX and added Timing Conditions table....166  
• Added timing conditions table for CPSW2G MDIO, RMII, and RGMII. Removed transition time parameters  
from individual timing requirements and switching characteristics tables.......................................................166  
• (RGMII Timing Requirements): Updated input hold time for RD and RXCTL to 1.15 ns................................169  
• Updated description of CSI2 ..........................................................................................................................171  
• Updated pulse width in DSS to 0.475*P......................................................................................................... 173  
• Renamed eHRPWM to ePWM. Added Timing Conditions table. Updated Timing Requirements and Switching  
Characteristics titles and parameter descriptions for eCAP, ePWM, and eQEP timing sections....................174  
• Added GPIO Timing Conditions table.............................................................................................................178  
• Updated Timing specification values in GPMC: Added Timing Conditions table and removed jitter, slew rate,  
and duty cycle information from Switching Characteristics table and diagrams. Also updated CLK parameter  
to tc(clk).......................................................................................................................................................... 179  
• Added Timing Conditions table and updated Timing specification values in HYPERBUS ............................ 200  
• (I2C Timing): Removed timing and switching characteristics tables from I2C section, and added conformance  
to Philips Semiconductors I2C-Bus™ Specification, version 2.1 with notes on exceptions............................202  
• (MCAN Timing): Added Timing Conditions table and updated value for Tdx to 15 ns....................................203  
• (McASP Timing): Added timing conditions table for McASP...........................................................................203  
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• Added MCSPI timing conditions table. Updated Timing Requirements and Switching Characteristics tables.....  
207  
• Updated MMCi Interface Timing Requirements, Switching Characteristics, and DLL Delay Mapping table.  
Also added a Timing Conditions table. Also updated MMCSD speed support description.............................214  
• (Timing Requirements for MMCi - DDR50 Mode) Added associated footnote for "j" value............................220  
• Updated title from NAVSS to CPTS under Peripheral timing section. Added CPTS Timing Conditions table  
and updated table format and descriptions of the parameters in Timing Requirements and Switching  
Characteristics tables..................................................................................................................................... 222  
• Added Timing Conditions table and DLL Delay Mapping table in OSPI. Updated timing requirements and  
switching characteristics table limits. Renamed "No Loopback" mode to "Internal Clock" mode................... 224  
• Updated min input slew rate for 3.3V DDR, Internal Pad Loopback mode to 2 V/ns. Updated input timing  
limits for 3.3V DDR, DQS mode..................................................................................................................... 224  
• Added note clarifying I/O timing is not applicable when OSPI is used with data training .............................. 224  
• Added timing conditions and updated parameter descriptions under PRUsection. Added timnig requirements  
and switching characteristics for 10 Mbps and 100 Mbps modes in RGMII mode. Updated timing limits for  
SHIFT OUT, ECAP, UART modes.................................................................................................................. 231  
• (PRU ICSSG Parallel Capture): Updated input hold time to 0.6 ns................................................................232  
• (PRU ICSSG RGMII) Updated hold time for RXCTL and RD to 1.15 ns........................................................241  
• Added Timing Conditions table in Debug Trace and removed rise/fall time parameters from Switching  
Characteristics table and diagram.................................................................................................................. 247  
• Added JTAG Timing Conditions table. Updated Timing Requirements and Switching Characteristics table  
limits................................................................................................................................................................247  
• Updated/Changed "MCU_OPSI[x]_LBCLKO" typo to "MCU_OSPI[x]_LBCLKO".......................................... 263  
• (LVCMOS External Capacitor Connections): Updated/Changed the "All VDDSHV[8:0] and  
VDDSHV[2:0]_WKUP supplies configured for 1.8V operation" image........................................................... 268  
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5 Device Comparison  
表5-1 shows a comparison between devices, highlighting the differences.  
表5-1. Device Comparison  
REFERENCE  
NAME  
AM6548  
AM6528  
AM6546  
AM6526  
FEATURES  
FEATURES  
CTRLMMR_WKUP_JTAG_DEVICE_ID  
AM6548:  
0x140FA  
AM6528:  
0x140BA  
AM6546:  
0x14178  
AM6526:  
0x14138  
[31:11] DEVICE_ID register bit field value(5)  
AM6548-E:  
0x140FB  
AM6528-E:  
0x140BB  
AM6546-E:  
0x14179  
AM6526-E:  
0x14139  
AM6548-F:  
0x140FE  
AM6528-F:  
0x140BE  
AM6546-F:  
0x1417C  
AM6526-F:  
0x1413C  
AM6548-E,F:  
0x140FF  
AM6528-E,F:  
0x140BF  
AM6546-E,F:  
0x1417D  
AM6526-E,F:  
0x1413D  
PROCESSORS AND ACCELERATORS  
Speed Grades  
See 表7-1, Speed Grade Maximum Frequency  
Arm Cortex-A53 Microprocessor Subsystem  
Arm A53  
Quad Core  
(Cluster 0,  
Cluster 1)  
Dual Core  
(Cluster 0)  
Quad Core  
(Cluster 0,  
Cluster 1)  
Dual Core  
(Cluster 0)  
Dual-Core Arm Cortex-R5F  
Arm R5F  
DMSC  
GPU  
Yes (optional lockstep(4)  
Yes  
)
Device Management Security Controller  
Graphics Accelerator (SGX544-MP1)  
Safety Features  
Yes  
Optional(4)  
Not Supported(1)  
Optional(4)  
Safety  
PROGRAM AND DATA STORAGE  
On-Chip Shared Memory (RAM)  
Multicore Shared Memory Controller  
DDR4 DDR Subsystem(6)  
MCU_MSRAM  
MSMC  
512KB  
2MB (On-Chip Shared SRAM with ECC)  
DDRSS  
SECDED  
GPMC  
Up to 8GB (32-Bit data)  
7-Bit  
Up to 1GB with ECC  
Yes  
General-Purpose Memory Controller  
Error Location Module  
ELM  
PERIPHERALS  
Display Subsystem  
DSS  
Yes  
Modular Controller Area Network Interface  
Peripheral Direct Memory Access  
Navigator Subsystem  
MCAN  
PDMA  
NAVSS  
GPIO  
I2C  
2
Yes  
2
General-Purpose I/O  
Up to 242  
Inter-Integrated Circuit Interface  
Analog-to-Digital Converter  
6
ADC  
2
1 CLK + 4 Data  
Yes  
Camera Adaptation Layer (CAL) with Camera  
Serial Interface (CSI2) and Video Input Port  
(VIN)  
CSI2  
VIN0  
Multichannel Serial Peripheral Interface  
MCSPI  
8
MCASP0  
MCASP1  
MCASP2  
MMCSD0  
MMCSD1  
16 Serializers  
10 Serializers  
4 Serializers  
8-bits  
Multichannel Audio Serial Port  
MultiMedia Card/ Secure Digital Interface  
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表5-1. Device Comparison (continued)  
REFERENCE  
NAME  
AM6548  
AM6528  
AM6546  
AM6526  
FEATURES  
FEATURES  
OSPI0  
OSPI1  
8-bits(3)  
4-bits  
Flash Subsystem (FSS)  
HyperBus  
SA  
Not Supported(1)  
Security Accelerator  
Yes  
Error Signalling Module  
ESM  
Yes  
Up to Two Lanes(2)  
Single Lane(2)  
2x PCI Express 3.1 Port with Integrated PHY  
PCIE0  
PCIE1  
3x Programmable Real-Time Unit Subsystem  
and Industrial Communication Subsystem  
PRU_ICSSG0  
PRU_ICSSG1  
PRU_ICSSG2  
CPSW  
Yes (2× RGMII, 2× MII)  
Yes (2× RGMII, 2× MII)  
Yes (2× RGMII, 2× MII, 2× SGMII(2)  
RMII or RGMII  
)
Gigabit Ethernet Interface  
General-Purpose Timers  
TIMER  
16  
Enhanced High Resolution Pulse-Width  
Modulator Module  
EHRPWM  
6
Enhanced Capture Module  
ECAP  
EQEP  
UART  
1
3
5
Enhanced Quadrature Encoder Pulse Module  
Universal Asynchronous Receiver and  
Transmitter  
Universal Serial Bus (USB3.1) SuperSpeed  
Dual-Role-Device (DRD) Ports with SS PHY  
USB0  
USB1  
Yes(2)  
Yes  
Universal Serial Bus (USB2.0) HighSpeed Dual-  
Role-Device (DRD) Ports with HS/FS PHY  
(1) Features noted as “not supported”, must not be used. Their functionality is not supported by TI for this family of devices. These  
features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been  
retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions.  
(2) SGMII0, SGMII1, USB3.1, PCIE0, and PCIE1 share total of two SerDes lanes.  
(3) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.  
(4) Device supports features to aid in functional safety system designs such as lockstep Arm R5F if the part number is designated with the  
F option.  
(5) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bit field, see the device TRM.  
(6) Only DDR4 is supported. DDR3L and LPDDR4 are not supported.  
5.1 Related Products  
Sitara™ processors  
Scalable processors based on Arm Cortex-A cores with flexible peripherals,  
connectivity & unified software support –perfect for sensors to servers.  
Sitara processors provide scalable solutions for a wide range of applications from  
HMIs and gateways to more complex equipment such as drives and substation  
automation equipment. Sitara Arm processors offer scalability and reliability as  
well as multi-protocol support for industrial communication protocols such as  
EtherCAT, Ethernet/IP and Profinet.  
Sitara™ processors –  
Applications  
Sitara™ processors –  
TI provides many reference designs containing ‘building block’solutions to  
Reference designs  
enable customers to rapidly development of their unique products and solutions.  
Companion Products for  
AM654x, AM652x  
Review products that are frequently purchased or used in conjunction with this  
product.  
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6 Terminal Configuration and Functions  
6.1 Pin Diagram  
Note  
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt  
is made to use "ball" only when referring to the physical package.  
图 6-1 shows the ball locations for the 784 plastic ball grid array (FCBGA) package that are used in conjunction  
with 表6-1 through 图6-1 to locate signal names and ball grid numbers.  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27  
10 12 14 16 18 20 22 24 26 28  
2
4
6
8
图6-1. ACD FCBGA-N784 Package (Bottom View)  
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6.2 Pin Attributes  
表6-1 describes the terminal characteristics and the signals multiplexed on each ball.  
表6-1. Pin Attributes  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
P17  
V17  
W16  
M14  
L15  
CAP_VDDAR_CORE0  
CAP_VDDAR_CORE1  
CAP_VDDAR_CORE2  
CAP_VDDAR_CORE3  
CAP_VDDAR_CORE4  
CAP_VDDAR_MCU  
CAP_VDDAR_CORE0  
CAP  
CAP_VDDAR_CORE1  
CAP_VDDAR_CORE2  
CAP_VDDAR_CORE3  
CAP_VDDAR_CORE4  
CAP_VDDAR_MCU  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
U10  
M12  
N12  
N18  
N15  
Y10  
AA8  
CAP_VDDAR_MPU0_0  
CAP_VDDAR_MPU0_1  
CAP_VDDAR_MPU1_0  
CAP_VDDAR_MPU1_1  
CAP_VDDAR_WKUP  
CAP_VDDAR_MPU0_0  
CAP_VDDAR_MPU0_1  
CAP_VDDAR_MPU1_0  
CAP_VDDAR_MPU1_1  
CAP_VDDAR_WKUP  
CAP_VDDA_1P8_IOLDO_WK CAP_VDDA_1P8_IOLDO_WKUP  
UP  
J17  
G19  
Y19  
H18  
V9  
CAP_VDDA_1P8_SDIO  
CAP_VDDA_1P8_IOLDO0  
CAP_VDDA_1P8_IOLDO1  
CAP_VDDSHV_SDIO  
CAP_VDD_WKUP  
CAP_VDDA_1P8_SDIO  
CAP_VDDA_1P8_IOLDO0  
CAP_VDDA_1P8_IOLDO1  
CAP_VDDSHV_SDIO  
CAP_VDD_WKUP  
CAP  
CAP  
CAP  
CAP  
CAP  
I
G28  
CSI0_RXN0  
CSI0_RXN0  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
PD  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_C  
SI0  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
DPHY  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
H27  
F26  
H25  
G24  
F28  
G27  
G26  
G25  
F24  
CSI0_RXN1  
CSI0_RXN2  
CSI0_RXN3  
CSI0_RXN4  
CSI0_RXP0  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI0_RXP4  
CSI0_RXN1  
CSI0_RXN2  
CSI0_RXN3  
CSI0_RXN4  
CSI0_RXP0  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI0_RXP4  
I
I
I
I
I
I
I
I
I
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
VDDA_1P8_C  
SI0  
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表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
A10  
D9  
C9  
E9  
DDR_AC0  
DDR_AC0  
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.1 V/1.2  
V/1.35 V  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
DDR_AC1  
DDR_AC2  
DDR_AC3  
DDR_AC4  
DDR_AC5  
DDR_AC6  
DDR_AC7  
DDR_AC8  
DDR_AC9  
DDR_AC10  
DDR_AC11  
DDR_AC12  
DDR_AC13  
DDR_AC14  
DDR_AC15  
DDR_AC16  
DDR_AC17  
DDR_AC18  
DDR_AC19  
DDR_AC20  
DDR_AC21  
DDR_AC22  
DDR_AC1  
DDR_AC2  
DDR_AC3  
DDR_AC4  
DDR_AC5  
DDR_AC6  
DDR_AC7  
DDR_AC8  
DDR_AC9  
DDR_AC10  
DDR_AC11  
DDR_AC12  
DDR_AC13  
DDR_AC14  
DDR_AC15  
DDR_AC16  
DDR_AC17  
DDR_AC18  
DDR_AC19  
DDR_AC20  
DDR_AC21  
DDR_AC22  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
A9  
1.1 V/1.2  
V/1.35 V  
E8  
1.1 V/1.2  
V/1.35 V  
F8  
1.1 V/1.2  
V/1.35 V  
C7  
C8  
D7  
E7  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
A6  
1.1 V/1.2  
V/1.35 V  
F7  
1.1 V/1.2  
V/1.35 V  
D6  
C6  
F6  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
E6  
1.1 V/1.2  
V/1.35 V  
E5  
1.1 V/1.2  
V/1.35 V  
D8  
D10  
E10  
C10  
F11  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
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表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
B10  
D11  
B11  
C11  
E11  
E12  
D12  
D5  
DDR_AC23  
DDR_AC23  
DDR_AC24  
DDR_AC25  
DDR_AC26  
DDR_AC27  
DDR_AC28  
DDR_AC29  
DDR_ALERTn  
DDR_CK0N  
DDR_CK0P  
DDR_CK1N  
DDR_CK1P  
DDR_DM0  
DDR_DM1  
DDR_DM2  
DDR_DM3  
DDR_DQ0  
DDR_DQ1  
DDR_DQ2  
DDR_DQ3  
DDR_DQ4  
DDR_DQ5  
DDR_DQ6  
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.1 V/1.2  
V/1.35 V  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
DDR_AC24  
DDR_AC25  
DDR_AC26  
DDR_AC27  
DDR_AC28  
DDR_AC29  
DDR_ALERTn  
DDR_CK0N  
DDR_CK0P  
DDR_CK1N  
DDR_CK1P  
DDR_DM0  
DDR_DM1  
DDR_DM2  
DDR_DM3  
DDR_DQ0  
DDR_DQ1  
DDR_DQ2  
DDR_DQ3  
DDR_DQ4  
DDR_DQ5  
DDR_DQ6  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
B8  
drive 1  
(OFF)  
1.1 V/1.2  
V/1.35 V  
A8  
drive 0  
(OFF)  
1.1 V/1.2  
V/1.35 V  
B7  
drive 1  
(OFF)  
1.1 V/1.2  
V/1.35 V  
A7  
drive 0  
(OFF)  
1.1 V/1.2  
V/1.35 V  
E1  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.1 V/1.2  
V/1.35 V  
C5  
1.1 V/1.2  
V/1.35 V  
D14  
B17  
A3  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
B2  
1.1 V/1.2  
V/1.35 V  
C2  
1.1 V/1.2  
V/1.35 V  
D2  
1.1 V/1.2  
V/1.35 V  
E2  
1.1 V/1.2  
V/1.35 V  
G1  
F2  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
F1  
DDR_DQ7  
DDR_DQ7  
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.1 V/1.2  
V/1.35 V  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
E3  
DDR_DQ8  
DDR_DQ8  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1.1 V/1.2  
V/1.35 V  
C3  
DDR_DQ9  
DDR_DQ9  
1.1 V/1.2  
V/1.35 V  
D3  
DDR_DQ10  
DDR_DQ11  
DDR_DQ12  
DDR_DQ13  
DDR_DQ14  
DDR_DQ15  
DDR_DQ16  
DDR_DQ17  
DDR_DQ18  
DDR_DQ19  
DDR_DQ20  
DDR_DQ21  
DDR_DQ22  
DDR_DQ23  
DDR_DQ24  
DDR_DQ25  
DDR_DQ26  
DDR_DQ27  
DDR_DQ28  
DDR_DQ29  
DDR_DQ10  
DDR_DQ11  
DDR_DQ12  
DDR_DQ13  
DDR_DQ14  
DDR_DQ15  
DDR_DQ16  
DDR_DQ17  
DDR_DQ18  
DDR_DQ19  
DDR_DQ20  
DDR_DQ21  
DDR_DQ22  
DDR_DQ23  
DDR_DQ24  
DDR_DQ25  
DDR_DQ26  
DDR_DQ27  
DDR_DQ28  
DDR_DQ29  
1.1 V/1.2  
V/1.35 V  
B3  
1.1 V/1.2  
V/1.35 V  
D4  
1.1 V/1.2  
V/1.35 V  
C4  
1.1 V/1.2  
V/1.35 V  
B4  
1.1 V/1.2  
V/1.35 V  
B5  
1.1 V/1.2  
V/1.35 V  
E13  
C14  
B14  
A14  
E14  
B13  
C13  
D13  
D15  
C15  
E16  
E15  
D16  
B16  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
C16  
A17  
C1  
DDR_DQ30  
DDR_DQ30  
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.1 V/1.2  
V/1.35 V  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
VDDS_DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
DDR  
LVCMOS  
DDR  
DDR  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PD  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
DDR_DQ31  
DDR_DQ31  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A
1.1 V/1.2  
V/1.35 V  
DDR_DQS0N  
DDR_DQS0P  
DDR_DQS1N  
DDR_DQS1P  
DDR_DQS2N  
DDR_DQS2P  
DDR_DQS3N  
DDR_DQS3P  
DDR_ECC_D0  
DDR_ECC_D1  
DDR_ECC_D2  
DDR_ECC_D3  
DDR_ECC_D4  
DDR_ECC_D5  
DDR_ECC_D6  
DDR_ECC_DM  
DDR_ECC_DQSN  
DDR_ECC_DQSP  
DDR_FS_RESETn  
DDR_RESETn  
DDR_VREF0  
DDR_DQS0N  
DDR_DQS0P  
DDR_DQS1N  
DDR_DQS1P  
DDR_DQS2N  
DDR_DQS2P  
DDR_DQS3N  
DDR_DQS3P  
DDR_ECC_D0  
DDR_ECC_D1  
DDR_ECC_D2  
DDR_ECC_D3  
DDR_ECC_D4  
DDR_ECC_D5  
DDR_ECC_D6  
DDR_ECC_DM  
DDR_ECC_DQSN  
DDR_ECC_DQSP  
DDR_FS_RESETn  
DDR_RESETn  
DDR_VREF0  
1.1 V/1.2  
V/1.35 V  
D1  
1.1 V/1.2  
V/1.35 V  
A4  
1.1 V/1.2  
V/1.35 V  
A5  
1.1 V/1.2  
V/1.35 V  
A12  
A13  
A16  
A15  
B19  
B18  
C18  
D18  
E18  
E17  
D17  
C17  
A18  
A19  
F16  
A11  
F12  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
1.1 V/1.2  
V/1.35 V  
drive 0  
(OFF)  
1.1 V/1.2  
V/1.35 V  
drive 0  
(OFF)  
1.1 V/1.2  
V/1.35 V  
PU/PD  
0.5*VDDS_ VDDS_DDR  
DDR  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
F15  
F13  
DDR_VREF_ZQ  
DDR_VREF_ZQ  
A
VDDS_DDR  
VDDS_DDR  
DDR  
DDR  
No  
No  
DDR_VTP  
DDR_VTP  
A
1.1 V/1.2  
V/1.35 V  
D21  
ECAP0_IN_APWM_OUT  
ECAP0_IN_APWM_OUT  
SYNC0_OUT  
CPTS0_RFT_CLK  
GPIO1_86  
0
IO  
O
I
OFF  
7
1.8 V/3.3 V VDDSHV0  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
7
0
0
0
IO  
IO  
AA2  
AA1  
A22  
EMU0  
EMU0  
PU  
0
0
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
1/1  
1/1  
0/1  
Yes  
Yes  
Yes  
EMU1  
EMU1  
0
IO  
PU  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
EXT_REFCLK1  
EXT_REFCLK1  
SYNC1_OUT  
0
I
OFF  
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
0
0
1
O
IO  
O
O
IO  
I
GPIO1_87  
7
P25  
R28  
GPMC0_ADVn_ALE  
GPMC0_CLK  
GPMC0_ADVn_ALE  
VOUT1_DATA17  
GPIO0_17  
0
OFF  
OFF  
7
7
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1/1  
0/1  
Yes  
Yes  
1
7
0
0
0
BOOTMODE16  
GPMC0_CLK  
Bootstrap  
0
1
2
3
7
0
1
2
3
4
5
6
O
O
I
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
VOUT1_DATA16  
VIN0_PCLK  
0
0
GPMC0_FCLK_MUX  
GPIO0_16  
O
IO  
O
O
I
T24  
GPMC0_DIR  
GPMC0_DIR  
OFF  
7
1.8 V/3.3 V VDDSHV2  
LVCMOS  
PU/PD  
0/1  
Yes  
VOUT1_HSYNC  
VIN0_DATA8  
0
1
PRG2_PWM1_B0  
PRG2_IEP1_EDC_SYNC_OUT0  
TIMER_IO6  
IO  
O
IO  
IO  
0
0
PRG2_IEP0_EDIO_DATA_IN_OUT2  
9
GPIO0_25  
7
IO  
O
O
IO  
I
0
P26  
GPMC0_OEn_REn  
GPMC0_OEn_REn  
VOUT1_DATA18  
GPIO0_18  
0
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
1/1  
Yes  
1
7
0
0
BOOTMODE17  
Bootstrap  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
U28  
GPMC0_WEn  
GPMC0_WEn  
VOUT1_DATA19  
GPIO0_19  
0
O
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
1/1  
Yes  
1
O
IO  
I
7
0
BOOTMODE18  
GPMC0_WPn  
VOUT1_VSYNC  
GPIO0_24  
Bootstrap  
0
T25  
GPMC0_WPn  
GPMC0_AD0  
0
O
O
IO  
IO  
O
I
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
1/1  
Yes  
Yes  
1
7
0
0
M27  
GPMC0_AD0  
VOUT1_DATA0  
VIN0_DATA12  
GPIO0_0  
0
1
2
0
0
0
0
7
IO  
I
BOOTMODE00  
GPMC0_AD1  
VOUT1_DATA1  
VIN0_DATA13  
GPIO0_1  
Bootstrap  
M23  
M28  
M24  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
0
IO  
O
I
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
1/1  
1/1  
1/1  
Yes  
Yes  
Yes  
1
2
0
0
0
0
7
IO  
I
BOOTMODE01  
GPMC0_AD2  
VOUT1_DATA2  
VIN0_DATA14  
GPIO0_2  
Bootstrap  
0
IO  
O
I
1
2
0
0
0
0
7
IO  
I
BOOTMODE02  
GPMC0_AD3  
VOUT1_DATA3  
VIN0_DATA15  
GPIO0_3  
Bootstrap  
0
IO  
O
I
1
2
0
0
0
0
7
IO  
I
BOOTMODE03  
GPMC0_AD4  
VOUT1_DATA4  
GPIO0_4  
Bootstrap  
N24  
N27  
GPMC0_AD4  
GPMC0_AD5  
0
IO  
O
IO  
I
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1/1  
1/1  
Yes  
Yes  
1
7
0
0
0
BOOTMODE04  
GPMC0_AD5  
VOUT1_DATA5  
GPIO0_5  
Bootstrap  
0
IO  
O
IO  
I
1
7
0
0
BOOTMODE05  
Bootstrap  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
N28  
M25  
N23  
GPMC0_AD6  
GPMC0_AD6  
0
IO  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
1/1  
1/1  
1/1  
Yes  
Yes  
Yes  
VOUT1_DATA6  
GPIO0_6  
1
O
IO  
I
7
0
0
0
BOOTMODE06  
GPMC0_AD7  
Bootstrap  
GPMC0_AD7  
GPMC0_AD8  
0
IO  
O
IO  
I
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
VOUT1_DATA7  
GPIO0_7  
1
7
0
0
0
BOOTMODE07  
GPMC0_AD8  
Bootstrap  
0
IO  
O
I
VOUT1_DATA8  
VIN0_DATA0  
1
2
0
0
0
0
0
0
0
PRG2_PRU0_GPO12  
PRG2_PRU0_GPI12  
PRG2_PWM2_A0  
GPIO0_8  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE08  
GPMC0_AD9  
Bootstrap  
M26  
GPMC0_AD9  
0
IO  
O
I
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
1/1  
Yes  
VOUT1_DATA9  
VIN0_DATA1  
1
2
0
0
0
1
0
0
0
PRG2_PRU0_GPO13  
PRG2_PRU0_GPI13  
PRG2_PWM2_B0  
GPIO0_9  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE09  
GPMC0_AD10  
VOUT1_DATA10  
VIN0_DATA2  
Bootstrap  
P28  
GPMC0_AD10  
0
IO  
O
I
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
1/1  
Yes  
1
2
0
0
0
0
0
0
PRG2_PRU0_GPO14  
PRG2_PRU0_GPI14  
PRG2_PWM0_TZ_IN  
GPIO0_10  
3
IO  
I
4
6
I
7
IO  
I
BOOTMODE10  
Bootstrap  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
P27  
N26  
N25  
P24  
GPMC0_AD11  
GPMC0_AD11  
0
IO  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
1/1  
1/1  
1/1  
1/1  
Yes  
Yes  
Yes  
Yes  
VOUT1_DATA11  
VIN0_DATA3  
1
O
I
2
0
0
0
0
0
0
0
PRG2_PRU0_GPO15  
PRG2_PRU0_GPI15  
PRG2_PWM2_A1  
GPIO0_11  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE11  
GPMC0_AD12  
Bootstrap  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
0
IO  
O
I
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
Yes  
VOUT1_DATA12  
VIN0_DATA4  
1
2
0
0
0
1
0
0
0
PRG2_PRU1_GPO12  
PRG2_PRU1_GPI12  
PRG2_PWM2_B1  
GPIO0_12  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE12  
GPMC0_AD13  
Bootstrap  
0
IO  
O
I
VOUT1_DATA13  
VIN0_DATA5  
1
2
0
0
0
0
0
0
0
PRG2_PRU1_GPO13  
PRG2_PRU1_GPI13  
PRG2_PWM2_A2  
GPIO0_13  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE13  
GPMC0_AD14  
Bootstrap  
0
IO  
O
I
VOUT1_DATA14  
VIN0_DATA6  
1
2
0
0
0
PRG2_PRU1_GPO14  
PRG2_PRU1_GPI14  
PRG2_PWM0_TZ_OUT  
GPIO0_14  
3
IO  
I
4
6
O
IO  
I
7
0
0
BOOTMODE14  
Bootstrap  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
R27  
GPMC0_AD15  
GPMC0_AD15  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0
1/1  
Yes  
VOUT1_DATA15  
VIN0_DATA7  
1
O
I
2
0
0
0
1
0
0
PRG2_PRU1_GPO15  
PRG2_PRU1_GPI15  
PRG2_PWM2_B2  
GPIO0_15  
3
IO  
I
4
5
IO  
IO  
I
7
BOOTMODE15  
GPMC0_BE0n_CLE  
VOUT1_DATA20  
GPIO0_20  
Bootstrap  
T28  
P23  
GPMC0_BE0n_CLE  
GPMC0_BE1n  
0
1
7
0
1
2
3
4
5
6
7
0
1
7
0
1
2
3
4
5
6
7
O
O
IO  
O
O
I
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
0
GPMC0_BE1n  
VOUT1_DATA21  
VIN0_HD  
0
0
0
0
0
0
PRG2_PRU0_GPO17  
PRG2_PRU0_GPI17  
TIMER_IO2  
IO  
I
IO  
I
PRG2_PWM2_TZ_IN  
GPIO0_21  
IO  
O
O
IO  
O
O
I
R24  
T23  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn0  
VOUT1_PCLK  
GPIO0_26  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
0
GPMC0_CSn1  
VOUT1_DE  
VIN0_DATA9  
0
0
0
0
PRG2_PRU1_GPO17  
PRG2_PRU1_GPI17  
TIMER_IO7  
IO  
I
IO  
O
IO  
PRG2_PWM2_TZ_OUT  
GPIO0_27  
0
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
R25  
GPMC0_CSn2  
GPMC0_CSn2  
0
O
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
VOUT1_EXTPCLKIN  
VIN0_DATA10  
1
2
3
4
5
6
I
0
I
0
GPMC0_A27  
OZ  
I
PRG2_IEP1_EDC_LATCH_IN1  
I2C2_SDA  
0
1
0
IOD  
IO  
PRG2_IEP0_EDIO_DATA_IN_OUT3  
0
GPIO0_28  
7
0
2
3
4
5
6
IO  
O
0
0
T27  
GPMC0_CSn3  
GPMC0_CSn3  
VIN0_DATA11  
OFF  
7
1.8 V/3.3 V VDDSHV2  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
GPMC0_A26  
OZ  
O
PRG2_IEP1_EDC_SYNC_OUT1  
I2C2_SCL  
IOD  
IO  
1
0
PRG2_IEP0_EDIO_DATA_IN_OUT3  
1
GPIO0_29  
7
0
1
7
0
1
2
3
4
5
6
IO  
I
0
1
R26  
R23  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC0_WAIT0  
VOUT1_DATA22  
GPIO0_22  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2  
1.8 V/3.3 V VDDSHV2  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
O
IO  
I
0
1
GPMC0_WAIT1  
VOUT1_DATA23  
VIN0_VD  
O
I
0
0
0
0
0
PRG2_PWM1_A0  
PRG2_IEP1_EDC_LATCH_IN0  
TIMER_IO3  
IO  
I
IO  
IO  
PRG2_IEP0_EDIO_DATA_IN_OUT2  
8
GPIO0_23  
I2C0_SCL  
7
0
IO  
0
1
D20  
C21  
B21  
I2C0_SCL  
I2C0_SDA  
I2C1_SCL  
IOD  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
Yes  
Yes  
Yes  
LVCMOS- PU/PD  
FS  
1/1  
1/1  
1/1  
Yes  
Yes  
Yes  
I2C0_SDA  
0
IOD  
LVCMOS- PU/PD  
FS  
1
I2C1_SCL  
0
1
0
1
IOD  
LVCMOS- PU/PD  
FS  
1
0
1
0
CPTS0_HW1TSPUSH  
I2C1_SDA  
I
E21  
K2  
I2C1_SDA  
IOD  
OFF  
7
1.8 V/3.3 V VDDSHV0  
Yes  
LVCMOS- PU/PD  
FS  
1/1  
Yes  
No  
CPTS0_HW2TSPUSH  
MCU_ADC0_REFN  
I
MCU_ADC0_REFN  
A
1.8 V  
VDDA_ADC_M  
CU  
Analog  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
K3  
H3  
H2  
K5  
J3  
MCU_ADC0_REFP  
MCU_ADC0_REFP  
A
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_ADC_M  
CU  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
LVCMOS  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
MCU_ADC1_REFN  
MCU_ADC1_REFP  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
MCU_BYP_POR  
MCU_I2C0_SCL  
MCU_ADC1_REFN  
MCU_ADC1_REFP  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
MCU_BYP_POR  
MCU_I2C0_SCL  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
J1  
A
VDDA_ADC_M  
CU  
J5  
A
VDDA_ADC_M  
CU  
K4  
J4  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
J2  
A
VDDA_ADC_M  
CU  
J6  
A
VDDA_ADC_M  
CU  
F4  
G6  
G4  
H5  
F5  
G5  
G3  
H4  
V5  
AD8  
AD7  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
A
VDDA_ADC_M  
CU  
I
OFF  
OFF  
OFF  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
0
IOD  
IOD  
0
0
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
I2C OPEN  
DRAIN  
1
1/0  
1/0  
Yes  
Yes  
MCU_I2C0_SDA  
MCU_I2C0_SDA  
0
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
I2C OPEN  
DRAIN  
1
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
W2  
W1  
L1  
MCU_MCAN0_RX  
MCU_MCAN0_RX  
0
I
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
WKUP_GPIO0_55  
7
0
7
0
7
0
7
0
1
7
0
1
7
0
1
7
0
7
0
1
2
7
0
1
2
7
0
1
7
0
1
7
0
1
7
IO  
O
0
0
0
MCU_MCAN0_TX  
MCU_MDIO0_MDC  
MCU_MDIO0_MDIO  
MCU_OSPI0_CLK  
MCU_MCAN0_TX  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
WKUP_GPIO0_54  
IO  
O
MCU_MDIO0_MDC  
WKUP_GPIO0_47  
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
IO  
IO  
IO  
O
0
0
0
L4  
MCU_MDIO0_MDIO  
WKUP_GPIO0_46  
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
V1  
MCU_OSPI0_CLK  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_CK  
WKUP_GPIO0_12  
O
IO  
I
0
0
0
0
U2  
U1  
MCU_OSPI0_DQS  
MCU_OSPI0_DQS  
MCU_HYPERBUS0_RWDS  
WKUP_GPIO0_14  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
IO  
IO  
O
MCU_OSPI0_LBCLKO  
MCU_OSPI0_LBCLKO  
MCU_HYPERBUS0_CKn  
WKUP_GPIO0_13  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
IO  
O
0
T1  
P2  
MCU_OSPI1_CLK  
MCU_OSPI1_DQS  
MCU_OSPI1_CLK  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
WKUP_GPIO0_25  
IO  
I
0
0
MCU_OSPI1_DQS  
MCU_OSPI0_CSn3  
MCU_HYPERBUS0_INTn  
WKUP_GPIO0_27  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
O
I
1
0
0
IO  
IO  
O
R1  
MCU_OSPI1_LBCLKO  
MCU_OSPI1_LBCLKO  
MCU_OSPI0_CSn2  
MCU_HYPERBUS0_RESETOn  
WKUP_GPIO0_26  
OFF  
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
PU/PD  
0/1  
Yes  
I
1
0
IO  
O
R4  
R5  
U4  
MCU_OSPI0_CSn0  
MCU_OSPI0_CSn1  
MCU_OSPI0_D0  
MCU_OSPI0_CSn0  
MCU_HYPERBUS0_CSn0  
WKUP_GPIO0_23  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
O
IO  
O
0
MCU_OSPI0_CSn1  
MCU_HYPERBUS0_RESETn  
WKUP_GPIO0_24  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
O
IO  
IO  
IO  
IO  
0
0
0
0
MCU_OSPI0_D0  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ0  
WKUP_GPIO0_15  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
U5  
T2  
T3  
T4  
T5  
R2  
R3  
MCU_OSPI0_D1  
MCU_OSPI0_D1  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
MCU_HYPERBUS0_DQ1  
WKUP_GPIO0_16  
MCU_OSPI0_D2  
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
7
0
1
2
3
4
5
7
0
7
0
4
5
7
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MCU_OSPI0_D2  
MCU_OSPI0_D3  
MCU_OSPI0_D4  
MCU_OSPI0_D5  
MCU_OSPI0_D6  
MCU_OSPI0_D7  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ2  
WKUP_GPIO0_17  
MCU_OSPI0_D3  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ3  
WKUP_GPIO0_18  
MCU_OSPI0_D4  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ4  
WKUP_GPIO0_19  
MCU_OSPI0_D5  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ5  
WKUP_GPIO0_20  
MCU_OSPI0_D6  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ6  
WKUP_GPIO0_21  
MCU_OSPI0_D7  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_HYPERBUS0_DQ7  
WKUP_GPIO0_22  
MCU_OSPI1_CSn0  
WKUP_GPIO0_32  
MCU_OSPI1_CSn1  
MCU_HYPERBUS0_WPn  
MCU_TIMER_IO0  
N2  
N3  
MCU_OSPI1_CSn0  
MCU_OSPI1_CSn1  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
O
0
0
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
O
IO  
O
MCU_HYPERBUS0_CSn1  
MCU_UART0_RTSn  
MCU_SPI0_CS2  
O
IO  
IO  
IO  
IO  
IO  
I
1
0
0
0
0
1
1
0
WKUP_GPIO0_33  
MCU_OSPI1_D0  
P3  
P4  
MCU_OSPI1_D0  
MCU_OSPI1_D1  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
WKUP_GPIO0_28  
MCU_OSPI1_D1  
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
MCU_UART0_RXD  
MCU_SPI1_CS1  
IO  
IO  
WKUP_GPIO0_29  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
P5  
P1  
MCU_OSPI1_D2  
MCU_OSPI1_D2  
MCU_UART0_TXD  
MCU_SPI1_CS2  
WKUP_GPIO0_30  
MCU_OSPI1_D3  
MCU_UART0_CTSn  
MCU_SPI0_CS1  
WKUP_GPIO0_31  
MCU_PORz  
0
IO  
OFF  
OFF  
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
PU/PD  
0
0/1  
Yes  
4
5
7
0
4
5
7
O
IO  
IO  
IO  
I
1
0
0
1
1
0
MCU_OSPI1_D3  
7
1.8 V/3.3 V VDDSHV1_WK Yes  
UP  
LVCMOS  
PU/PD  
0/1  
Yes  
IO  
IO  
I
W5  
V2  
MCU_PORz  
OFF  
OFF  
OFF  
PU  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
No  
No  
No  
No  
Yes  
MCU_PORz_OUT  
MCU_RESETSTATz  
MCU_RESETz  
MCU_PORz_OUT  
MCU_RESETSTATz  
MCU_RESETz  
0
0
0
O
O
I
0
0
0
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0/0  
0/0  
1/1  
0/1  
V3  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
W4  
M1  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_RGMII1_RXC  
MCU_RGMII1_RXC  
MCU_RMII1_REF_CLK  
WKUP_GPIO0_41  
MCU_RGMII1_RX_CTL  
MCU_RMII1_RX_ER  
WKUP_GPIO0_35  
MCU_RGMII1_TXC  
MCU_RMII1_TX_EN  
WKUP_GPIO0_40  
MCU_RGMII1_TX_CTL  
MCU_RMII1_CRS_DV  
WKUP_GPIO0_34  
MCU_RGMII1_RD0  
MCU_RMII1_RXD0  
WKUP_GPIO0_45  
MCU_RGMII1_RD1  
MCU_RMII1_RXD1  
WKUP_GPIO0_44  
MCU_RGMII1_RD2  
WKUP_GPIO0_43  
MCU_RGMII1_RD3  
WKUP_GPIO0_42  
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
1
7
0
7
0
7
I
OFF  
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
0
0
0
0
0
0
0
I
IO  
I
N5  
N1  
N4  
L6  
MCU_RGMII1_RX_CTL  
MCU_RGMII1_TXC  
MCU_RGMII1_TX_CTL  
MCU_RGMII1_RD0  
MCU_RGMII1_RD1  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
I
IO  
IO  
O
IO  
O
I
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
0
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
0
0
0
0
0
0
0
0
0
0
0
0
IO  
I
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
I
IO  
I
M6  
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
I
IO  
I
L5  
L2  
MCU_RGMII1_RD2  
MCU_RGMII1_RD3  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
I
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
M5  
M4  
MCU_RGMII1_TD0  
MCU_RGMII1_TD0  
0
O
OFF  
OFF  
7
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
MCU_RMII1_TXD0  
WKUP_GPIO0_39  
MCU_RGMII1_TD1  
MCU_RMII1_TXD1  
WKUP_GPIO0_38  
MCU_RGMII1_TD2  
WKUP_GPIO0_37  
MCU_RGMII1_TD3  
WKUP_GPIO0_36  
MCU_SAFETY_ERRORn  
1
7
0
1
7
0
7
0
7
0
O
IO  
O
0
MCU_RGMII1_TD1  
7
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
O
IO  
O
0
0
0
M3  
M2  
MCU_RGMII1_TD2  
MCU_RGMII1_TD3  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
O
1.8 V/3.3 V VDDSHV2_WK Yes  
UP  
IO  
IO  
W3  
Y1  
MCU_SAFETY_ERRORn  
MCU_SPI0_CLK  
PD  
0
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1/0  
1/1  
No  
MCU_SPI0_CLK  
WKUP_GPIO0_48  
MCU_BOOTMODE06  
MCU_SPI0_CS0  
WKUP_GPIO0_51  
MCU_SPI0_D0  
WKUP_GPIO0_49  
MCU_BOOTMODE07  
MCU_SPI0_D1  
WKUP_GPIO0_50  
MCU_BOOTMODE05  
MMC0_CLK  
0
IO  
IO  
I
OFF  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
Yes  
7
Bootstrap  
Y4  
Y3  
MCU_SPI0_CS0  
MCU_SPI0_D0  
0
IO  
IO  
IO  
IO  
I
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
1/1  
Yes  
Yes  
7
0
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
7
Bootstrap  
Y2  
MCU_SPI0_D1  
0
IO  
IO  
I
OFF  
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
PU/PD  
1/1  
Yes  
7
Bootstrap  
B25  
B27  
C25  
A23  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
0
7
0
7
0
7
0
6
7
0
7
0
7
O
O
IO  
IO  
I
PD  
7
7
7
7
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
No  
No  
No  
Yes  
GPIO1_10  
MMC0_CMD  
PU  
PU/PD  
PU/PD  
PU/PD  
GPIO1_11  
MMC0_DS  
PD  
GPIO1_12  
I
MMC0_SDCD  
MMC0_SDCD  
I
OFF  
1.8 V  
1.8 V  
VDDS_OSC1  
VDDS_OSC1  
Yes  
Yes  
0/1  
0/1  
PRG2_IEP0_EDIO_OUTVALID  
GPIO1_13  
O
IO  
I
0
1
0
1
0
B23  
C27  
MMC0_SDWP  
MMC1_CLK  
MMC0_SDWP  
GPIO1_14  
OFF  
PD  
7
7
LVCMOS  
LVCMOS  
PU/PD  
Yes  
No  
IO  
O
O
MMC1_CLK  
1.8 V/3.3 V VDDSHV7  
GPIO1_77  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
C28  
B24  
C24  
A26  
E25  
C26  
A25  
E24  
MMC1_CMD  
MMC1_CMD  
GPIO1_78  
0
IO  
PU  
7
7
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV7  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
1
No  
7
0
7
0
7
0
7
0
7
0
7
0
7
0
1
5
7
0
1
5
7
0
1
5
7
0
1
5
7
0
7
0
7
0
7
IO  
I
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
MMC1_SDCD  
MMC1_SDWP  
MMC0_DAT0  
MMC0_DAT1  
MMC0_DAT2  
MMC0_DAT3  
MMC0_DAT4  
MMC1_SDCD  
GPIO1_79  
OFF  
OFF  
PU  
1.8 V  
1.8 V  
VDDS_OSC1  
VDDS_OSC1  
Yes  
0/1  
0/1  
Yes  
Yes  
No  
No  
No  
No  
No  
IO  
I
MMC1_SDWP  
GPIO1_80  
Yes  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
MMC0_DAT0  
GPIO1_9  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
MMC0_DAT1  
GPIO1_8  
PU  
MMC0_DAT2  
GPIO1_7  
PU  
MMC0_DAT3  
GPIO1_6  
PU  
MMC0_DAT4  
UART0_RIN  
EQEP2_S  
PU  
IO  
IO  
IO  
O
GPIO1_5  
A24  
B26  
D25  
MMC0_DAT5  
MMC0_DAT6  
MMC0_DAT7  
MMC0_DAT5  
UART0_DTRn  
EQEP2_I  
PU  
PU  
PU  
7
7
7
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
1.8 V/3.3 V VDDSHV6  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
IO  
IO  
IO  
I
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
GPIO1_4  
MMC0_DAT6  
UART0_DSRn  
EQEP2_B  
I
GPIO1_3  
IO  
IO  
I
MMC0_DAT7  
UART0_DCDn  
EQEP2_A  
I
GPIO1_2  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
D28  
E27  
D26  
MMC1_DAT0  
MMC1_DAT1  
MMC1_DAT2  
MMC1_DAT0  
GPIO1_76  
PU  
PU  
PU  
7
7
7
1.8 V/3.3 V VDDSHV7  
1.8 V/3.3 V VDDSHV7  
1.8 V/3.3 V VDDSHV7  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
No  
No  
No  
MMC1_DAT1  
GPIO1_75  
MMC1_DAT2  
GPIO1_74  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
D27  
F18  
MMC1_DAT3  
MMC1_DAT3  
0
IO  
PU  
7
1.8 V/3.3 V VDDSHV7  
LVCMOS  
PU/PD  
1
No  
GPIO1_73  
7
0
6
IO  
I
0
1
0
NMIn  
NMIn  
PU  
0
1.8 V/3.3 V VDDSHV0  
Yes  
LVCMOS- PU/PD  
FS  
1/1  
Yes  
PRG2_PWM1_TZ_IN  
OLDI0_CLKN  
I
L25  
K25  
J28  
K28  
L27  
K27  
K24  
J24  
J26  
K26  
OLDI0_CLKN  
OLDI0_CLKP  
OLDI0_A0N  
OLDI0_A0P  
OLDI0_A1N  
OLDI0_A1P  
OLDI0_A2N  
OLDI0_A2P  
OLDI0_A3N  
OLDI0_A3P  
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
No  
No  
No  
No  
No  
No  
No  
No  
No  
No  
OLDI0_CLKP  
OLDI0_A0N  
OLDI0_A0P  
OLDI0_A1N  
OLDI0_A1P  
OLDI0_A2N  
OLDI0_A2P  
OLDI0_A3N  
OLDI0_A3P  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
VDDA_1P8_O  
LDI0  
OLDI_LVD  
S
C22  
E22  
Y5  
OSC1_XI  
OSC1_XI  
I
OFF  
OFF  
OFF  
1.8 V  
1.8 V  
VDDS_OSC1  
VDDS_OSC1  
Analog  
Analog  
No  
No  
No  
OSC1_XO  
OSC1_XO  
O
O
PMIC_POWER_EN0  
PMIC_POWER_EN0  
0
0
0
0
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
PU/PD  
PU/PD  
0/0  
0/0  
AA5  
PMIC_POWER_EN1  
PMIC_POWER_EN1  
O
OFF  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
No  
E19  
PORz  
PORz  
0
0
0
3
5
7
0
3
5
7
I
OFF  
OFF  
OFF  
0
0
7
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
Yes  
Yes  
Yes  
C19  
PORz_OUT  
PRG0_MDIO0_MDC  
PORz_OUT  
O
PU/PD  
PU/PD  
0/0  
0/1  
AE28  
PRG0_MDIO0_MDC  
PRG2_PWM1_B2  
MCASP2_AXR3  
GPIO1_70  
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1
0
0
0
0
0
0
AE26  
PRG0_MDIO0_MDIO  
PRG0_MDIO0_MDIO  
PRG2_PWM1_A2  
MCASP2_AXR2  
GPIO1_69  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
V24  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPI0  
PRG0_RGMII1_RD0  
PRG0_PWM3_A0  
MCASP0_ACLKX  
GPIO1_29  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
5
7
0
1
3
5
7
I
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
I
IO  
IO  
IO  
IO  
I
W25  
W24  
AA27  
Y24  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPI1  
PRG0_RGMII1_RD1  
PRG0_PWM3_B0  
MCASP0_AFSX  
GPIO1_30  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
Yes  
Yes  
Yes  
I
IO  
IO  
IO  
IO  
I
PRG0_PRU0_GPO2  
PRG0_PRU0_GPI2  
PRG0_RGMII1_RD2  
PRG0_PWM2_A0  
MCASP0_ACLKR  
GPIO1_31  
I
IO  
IO  
IO  
IO  
I
PRG0_PRU0_GPO3  
PRG0_PRU0_GPI3  
PRG0_RGMII1_RD3  
PRG0_PWM3_A2  
MCASP0_AFSR  
GPIO1_32  
I
IO  
IO  
IO  
IO  
I
PRG0_PRU0_GPO4  
PRG0_PRU0_GPI4  
PRG0_RGMII1_RX_CTL  
PRG0_PWM2_B0  
MCASP0_AXR0  
GPIO1_33  
I
IO  
IO  
IO  
IO  
I
V28  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPI5  
PRG0_PWM3_B2  
MCASP0_AXR1  
GPIO1_34  
IO  
IO  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
Y25  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO6  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG0_PRU0_GPI6  
PRG0_RGMII1_RXC  
PRG0_PWM3_A1  
MCASP0_AXR2  
1
2
3
5
7
0
1
2
3
4
5
7
0
1
3
5
7
0
1
2
3
4
5
6
I
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
I
IO  
IO  
IO  
IO  
I
GPIO1_35  
U27  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPI7  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_PWM3_B1  
PRG0_ECAP0_SYNC_IN  
MCASP0_AXR3  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
I
IO  
IO  
IO  
I
GPIO1_36  
V27  
V26  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPI8  
PRG0_PWM2_A1  
MCASP0_AXR4  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
IO  
IO  
IO  
I
GPIO1_37  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPI9  
PRG0_UART0_CTSn  
PRG0_PWM3_TZ_IN  
SPI3_CS1  
1.8 V/3.3 V VDDSHV3  
I
I
IO  
IO  
IO  
MCASP0_AXR5  
PRG0_IEP0_EDIO_DATA_IN_OUT2  
8
GPIO1_38  
7
0
1
2
3
4
5
6
IO  
IO  
I
0
0
0
U25  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPI10  
PRG0_UART0_RTSn  
PRG0_PWM2_B1  
SPI3_CS2  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
IO  
IO  
IO  
1
1
0
0
MCASP0_AXR6  
PRG0_IEP0_EDIO_DATA_IN_OUT2  
9
GPIO1_39  
7
IO  
0
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AB25  
AD27  
AC26  
AD26  
AA24  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPI11  
PRG0_RGMII1_TX_CTL  
PRG0_PWM3_TZ_OUT  
PRG0_PRU0_GPO15  
MCASP0_AXR7  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
I
0
O
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
GPIO1_40  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPI12  
PRG0_RGMII1_TD0  
PRG0_PWM0_A0  
PRG0_PRU0_GPO11  
MCASP0_AXR8  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
Yes  
Yes  
O
IO  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
GPIO1_41  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPI13  
PRG0_RGMII1_TD1  
PRG0_PWM0_B0  
PRG0_PRU0_GPO12  
MCASP0_AXR9  
O
IO  
IO  
IO  
IO  
IO  
I
1
0
0
0
0
0
GPIO1_42  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPI14  
PRG0_RGMII1_TD2  
PRG0_PWM0_A1  
PRG0_PRU0_GPO13  
MCASP0_AXR10  
GPIO1_43  
O
IO  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
PRG0_PRU0_GPO15  
PRG0_PRU0_GPI15  
PRG0_RGMII1_TD3  
PRG0_PWM0_B1  
PRG0_PRU0_GPO14  
MCASP0_AXR11  
GPIO1_44  
O
IO  
IO  
IO  
IO  
1
0
0
0
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AD28  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO16  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG0_PRU0_GPI16  
PRG0_RGMII1_TXC  
PRG0_PWM0_A2  
1
2
3
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
5
7
I
0
0
0
0
0
0
0
0
IO  
IO  
IO  
IO  
IO  
IO  
I
MCASP0_AXR12  
MCASP1_AHCLKR  
GPIO1_45  
U26  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPI17  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_PWM0_B2  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
O
IO  
IO  
IO  
IO  
I
1
PRG0_ECAP0_SYNC_OUT  
MCASP0_AXR13  
0
0
0
0
0
0
0
0
0
0
0
0
0
MCASP1_AHCLKX  
GPIO1_46  
V25  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPI18  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_PWM0_TZ_IN  
PRG0_ECAP0_IN_APWM_OUT  
MCASP0_AXR14  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
I
IO  
IO  
IO  
IO  
IO  
I
MCASP2_AHCLKR  
GPIO1_47  
U24  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPO19  
PRG0_PRU0_GPI19  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_PWM0_TZ_OUT  
MCASP0_AXR15  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
0
0
MCASP2_AHCLKX  
GPIO1_48  
AB28  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPI0  
PRG0_RGMII2_RD0  
MCASP1_ACLKX  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
IO  
GPIO1_49  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AC28  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPI1  
PRG0_RGMII2_RD1  
MCASP1_AFSX  
GPIO1_50  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
5
7
0
1
2
3
5
7
0
1
2
4
5
7
0
1
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
5
7
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
IO  
IO  
IO  
I
AC27  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPI2  
PRG0_RGMII2_RD2  
PRG0_PWM2_A2  
MCASP1_ACLKR  
GPIO1_51  
OFF  
7
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
IO  
IO  
IO  
I
AB26  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPI3  
PRG0_RGMII2_RD3  
EQEP0_A  
OFF  
7
LVCMOS  
PU/PD  
0/1  
Yes  
I
I
MCASP1_AFSR  
GPIO1_52  
IO  
IO  
IO  
I
AA25  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPI4  
PRG0_RGMII2_RX_CTL  
PRG0_PWM2_B2  
EQEP0_B  
OFF  
7
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
I
MCASP1_AXR0  
MCASP0_AHCLKR  
GPIO1_53  
IO  
IO  
IO  
IO  
I
U23  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPI5  
EQEP0_S  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
IO  
IO  
IO  
IO  
IO  
I
MCASP1_AXR1  
MCASP0_AHCLKX  
GPIO1_54  
AB27  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPI6  
PRG0_RGMII2_RXC  
MCASP1_AXR2  
GPIO1_55  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
IO  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
W28  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO7  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG0_PRU1_GPI7  
PRG0_IEP1_EDC_LATCH_IN1  
SPI3_CS0  
1
2
4
5
6
7
0
1
3
5
7
0
1
2
4
5
6
I
0
0
1
0
I
IO  
IO  
O
IO  
IO  
I
MCASP1_AXR3  
UART2_TXD  
GPIO1_56  
0
0
0
W27  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPI8  
PRG0_PWM2_TZ_OUT  
MCASP1_AXR4  
GPIO1_57  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
O
IO  
IO  
IO  
I
0
0
0
0
1
1
0
0
Y28  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPI9  
PRG0_UART0_RXD  
SPI3_CS3  
1.8 V/3.3 V VDDSHV3  
I
IO  
IO  
IO  
MCASP1_AXR5  
PRG0_IEP0_EDIO_DATA_IN_OUT3  
0
GPIO1_58  
7
0
1
2
3
4
5
6
IO  
IO  
I
0
0
0
AA28  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPI10  
PRG0_UART0_TXD  
PRG0_PWM2_TZ_IN  
EQEP0_I  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
I
0
0
0
0
IO  
IO  
IO  
MCASP1_AXR6  
PRG0_IEP0_EDIO_DATA_IN_OUT3  
1
GPIO1_59  
7
0
1
2
4
5
7
IO  
IO  
I
0
0
0
AB24  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPI11  
PRG0_RGMII2_TX_CTL  
PRG0_PRU1_GPO15  
MCASP1_AXR7  
OFF  
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
IO  
IO  
0
0
0
GPIO1_60  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AC25  
AD25  
AD24  
AE27  
AC24  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPI12  
PRG0_RGMII2_TD0  
PRG0_PWM1_A0  
PRG0_PRU1_GPO11  
MCASP1_AXR8  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
0
1
2
3
5
7
I
0
O
IO  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
GPIO1_61  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPI13  
PRG0_RGMII2_TD1  
PRG0_PWM1_B0  
PRG0_PRU1_GPO12  
MCASP1_AXR9  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
1.8 V/3.3 V VDDSHV3  
Yes  
Yes  
Yes  
Yes  
O
IO  
IO  
IO  
IO  
IO  
I
1
0
0
0
0
0
GPIO1_62  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPI14  
PRG0_RGMII2_TD2  
PRG0_PWM1_A1  
PRG0_PRU1_GPO13  
MCASP2_AFSR  
O
IO  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
GPIO1_63  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPI15  
PRG0_RGMII2_TD3  
PRG0_PWM1_B1  
PRG0_PRU1_GPO14  
MCASP2_ACLKR  
GPIO1_64  
O
IO  
IO  
IO  
IO  
IO  
I
1
0
0
0
0
0
0
0
0
0
PRG0_PRU1_GPO16  
PRG0_PRU1_GPI16  
PRG0_RGMII2_TXC  
PRG0_PWM1_A2  
MCASP2_AXR0  
IO  
IO  
IO  
IO  
GPIO1_65  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
Y27  
Y26  
W26  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO17  
0
IO  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV3  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
PRG0_PRU1_GPI17  
PRG0_IEP1_EDC_SYNC_OUT1  
PRG0_PWM1_B2  
SPI3_CLK  
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
3
7
0
1
3
7
0
1
2
3
7
I
0
O
IO  
IO  
IO  
I
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
MCASP2_AXR1  
UART2_RXD  
GPIO1_66  
IO  
IO  
I
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPI18  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_PWM1_TZ_IN  
SPI3_D0  
1.8 V/3.3 V VDDSHV3  
Yes  
I
I
IO  
IO  
I
MCASP2_AFSX  
UART2_CTSn  
GPIO1_67  
IO  
IO  
I
PRG0_PRU1_GPO19  
PRG0_PRU1_GPO19  
PRG0_PRU1_GPI19  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_PWM1_TZ_OUT  
SPI3_D1  
1.8 V/3.3 V VDDSHV3  
Yes  
O
O
IO  
IO  
O
IO  
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
0
0
MCASP2_ACLKX  
UART2_RTSn  
GPIO1_68  
0
AH18  
AD18  
AE22  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
PRG1_PRU0_GPO0  
PRG1_MDIO0_MDC  
SPI1_CS3  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
1
1
0
0
1
0
0
0
0
0
0
0
PRG2_PWM1_B1  
GPIO1_1  
PRG1_MDIO0_MDIO  
SPI1_CS2  
PRG2_PWM1_A1  
GPIO1_0  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPI0  
PRG1_RGMII1_RD0  
PRG1_PWM3_A0  
GPIO0_56  
I
IO  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AG24  
AF23  
AD21  
AG23  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPI1  
PRG1_RGMII1_RD1  
PRG1_PWM3_B0  
GPIO0_57  
0
IO  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
3
7
0
1
2
3
7
0
1
2
3
7
I
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
I
IO  
IO  
IO  
I
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPI2  
PRG1_RGMII1_RD2  
PRG1_PWM2_A0  
GPIO0_58  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
I
IO  
IO  
IO  
I
PRG1_PRU0_GPO3  
PRG1_PRU0_GPI3  
PRG1_RGMII1_RD3  
PRG1_PWM3_A2  
GPIO0_59  
I
IO  
IO  
IO  
I
PRG1_PRU0_GPO4  
PRG1_PRU0_GPI4  
PRG1_RGMII1_RX_CTL  
PRG1_PWM2_B0  
GPIO0_60  
I
IO  
IO  
IO  
I
AF27  
AF22  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPI5  
PRG1_PWM3_B2  
GPIO0_61  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
IO  
IO  
I
PRG1_PRU0_GPO6  
PRG1_PRU0_GPI6  
PRG1_RGMII1_RXC  
PRG1_PWM3_A1  
GPIO0_62  
I
IO  
IO  
IO  
I
AG27  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPI7  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_PWM3_B1  
GPIO0_63  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AF28  
AF26  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO8  
0
IO  
OFF  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG1_PRU0_GPI8  
PRG1_PWM2_A1  
GPIO0_64  
1
3
7
0
1
2
3
4
6
I
0
0
0
0
0
1
0
1
0
IO  
IO  
IO  
I
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPI9  
PRG1_UART0_CTSn  
PRG1_PWM3_TZ_IN  
SPI2_CS1  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
I
IO  
IO  
PRG1_IEP0_EDIO_DATA_IN_OUT2  
8
GPIO0_65  
7
0
1
2
3
4
6
IO  
IO  
I
0
0
0
AH25  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPI10  
PRG1_UART0_RTSn  
PRG1_PWM2_B1  
SPI2_CS2  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
IO  
IO  
1
1
0
PRG1_IEP0_EDIO_DATA_IN_OUT2  
9
GPIO0_66  
7
0
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
5
7
IO  
IO  
I
0
0
0
AF21  
AH20  
AH21  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPI11  
PRG1_RGMII1_TX_CTL  
PRG1_PWM3_TZ_OUT  
PRG1_PRU0_GPO15  
GPIO0_67  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
O
O
IO  
IO  
IO  
I
0
0
0
0
PRG1_PRU0_GPO12  
PRG1_PRU0_GPI12  
PRG1_RGMII1_TD0  
PRG1_PWM0_A0  
PRG1_PRU0_GPO11  
GPIO0_68  
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
PRG1_PRU0_GPO13  
PRG1_PRU0_GPI13  
PRG1_RGMII1_TD1  
PRG1_PWM0_B0  
PRG1_PRU0_GPO12  
GPIO0_69  
O
IO  
IO  
IO  
1
0
0
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AG20  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPI14  
PRG1_RGMII1_TD2  
PRG1_PWM0_A1  
PRG1_PRU0_GPO13  
GPIO0_70  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
3
7
0
1
2
7
I
0
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
AD19  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPI15  
PRG1_RGMII1_TD3  
PRG1_PWM0_B1  
PRG1_PRU0_GPO14  
GPIO0_71  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
IO  
IO  
IO  
I
1
0
0
0
0
0
0
0
0
0
AD20  
AH26  
AG25  
AG26  
AH24  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU1_GPO0  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPI16  
PRG1_RGMII1_TXC  
PRG1_PWM0_A2  
GPIO0_72  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
Yes  
IO  
IO  
IO  
IO  
I
PRG1_PRU0_GPO17  
PRG1_PRU0_GPI17  
PRG1_IEP0_EDC_SYNC_OUT1  
PRG1_PWM0_B2  
GPIO0_73  
O
IO  
IO  
IO  
I
1
0
0
0
0
0
0
0
0
PRG1_PRU0_GPO18  
PRG1_PRU0_GPI18  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_PWM0_TZ_IN  
GPIO0_74  
I
I
IO  
IO  
I
PRG1_PRU0_GPO19  
PRG1_PRU0_GPI19  
PRG1_IEP0_EDC_SYNC_OUT0  
PRG1_PWM0_TZ_OUT  
GPIO0_75  
O
O
IO  
IO  
I
0
0
0
0
0
PRG1_PRU1_GPO0  
PRG1_PRU1_GPI0  
PRG1_RGMII2_RD0  
GPIO0_76  
I
IO  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AH23  
AG21  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO1  
0
IO  
OFF  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG1_PRU1_GPI1  
PRG1_RGMII2_RD1  
GPIO0_77  
1
2
7
0
1
2
3
7
0
1
2
4
7
0
1
2
3
4
7
0
1
4
7
0
1
2
7
0
1
2
4
6
7
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I
IO  
IO  
I
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPO4  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPI2  
PRG1_RGMII2_RD2  
PRG1_PWM2_A2  
GPIO0_78  
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
IO  
IO  
IO  
I
AH22  
AE21  
PRG1_PRU1_GPO3  
PRG1_PRU1_GPI3  
PRG1_RGMII2_RD3  
EQEP1_A  
OFF  
OFF  
7
7
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
I
I
GPIO0_79  
IO  
IO  
I
PRG1_PRU1_GPO4  
PRG1_PRU1_GPI4  
PRG1_RGMII2_RX_CTL  
PRG1_PWM2_B2  
EQEP1_B  
I
IO  
I
GPIO0_80  
IO  
IO  
I
AC22  
AG22  
AD23  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPI5  
EQEP1_S  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
IO  
IO  
IO  
I
GPIO0_81  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPI6  
PRG1_RGMII2_RXC  
GPIO0_82  
I
IO  
IO  
I
PRG1_PRU1_GPO7  
PRG1_PRU1_GPI7  
PRG1_IEP1_EDC_LATCH_IN1  
SPI2_CS0  
I
IO  
O
IO  
UART1_TXD  
GPIO0_83  
0
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AE24  
AF25  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPI8  
PRG1_PWM2_TZ_OUT  
GPIO0_84  
0
IO  
OFF  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
3
7
0
1
2
6
I
0
O
IO  
IO  
I
0
0
0
1
0
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPI9  
PRG1_UART0_RXD  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
PRG1_IEP0_EDIO_DATA_IN_OUT3  
0
IO  
GPIO0_85  
7
0
1
2
3
4
6
IO  
IO  
I
0
0
0
AF24  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPI10  
PRG1_UART0_TXD  
PRG1_PWM2_TZ_IN  
SPI2_CS3  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
I
0
1
0
IO  
IO  
PRG1_IEP0_EDIO_DATA_IN_OUT3  
1
GPIO0_86  
7
0
1
2
4
5
7
0
1
2
3
5
7
0
1
2
3
5
7
IO  
IO  
I
0
0
0
AC20  
AE20  
AF19  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPI11  
PRG1_RGMII2_TX_CTL  
EQEP1_I  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
PRG1_PRU1_GPO15  
GPIO0_87  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPI12  
PRG1_RGMII2_TD0  
PRG1_PWM1_A0  
PRG1_PRU1_GPO11  
GPIO0_88  
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
PRG1_PRU1_GPO13  
PRG1_PRU1_GPI13  
PRG1_RGMII2_TD1  
PRG1_PWM1_B0  
PRG1_PRU1_GPO12  
GPIO0_89  
O
IO  
IO  
IO  
1
0
0
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AH19  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO14  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
PRG1_PRU1_GPI14  
PRG1_RGMII2_TD2  
PRG1_PWM1_A1  
PRG1_PRU1_GPO13  
GPIO0_90  
1
2
3
5
7
0
1
2
3
5
7
0
1
2
3
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
0
O
IO  
IO  
IO  
IO  
I
0
0
0
0
0
AG19  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPI15  
PRG1_RGMII2_TD3  
PRG1_PWM1_B1  
PRG1_PRU1_GPO14  
GPIO0_91  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
IO  
IO  
IO  
IO  
I
1
0
0
0
0
0
0
0
0
0
AE19  
AE23  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPI16  
PRG1_RGMII2_TXC  
PRG1_PWM1_A2  
GPIO0_92  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV4  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
IO  
IO  
IO  
I
PRG1_PRU1_GPO17  
PRG1_PRU1_GPI17  
PRG1_IEP1_EDC_SYNC_OUT1  
PRG1_PWM1_B2  
SPI2_CLK  
1.8 V/3.3 V VDDSHV4  
O
IO  
IO  
O
I
1
0
PRG1_ECAP0_SYNC_OUT  
UART1_RXD  
1
0
0
0
0
0
0
0
1
0
GPIO0_93  
IO  
IO  
I
AD22  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPI18  
PRG1_IEP1_EDC_LATCH_IN0  
PRG1_PWM1_TZ_IN  
SPI2_D0  
OFF  
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
I
IO  
I
PRG1_ECAP0_SYNC_IN  
UART1_CTSn  
I
GPIO0_94  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AC21  
AF18  
AE18  
AH17  
PRG1_PRU1_GPO19  
PRG1_PRU1_GPO19  
PRG1_PRU1_GPI19  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_PWM1_TZ_OUT  
SPI2_D1  
0
IO  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
1.8 V/3.3 V VDDSHV4  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
0
O
O
IO  
IO  
O
IO  
IO  
I
0
0
PRG1_ECAP0_IN_APWM_OUT  
UART1_RTSn  
GPIO0_95  
0
0
0
0
PRG2_PRU0_GPO0  
PRG2_PRU0_GPO1  
PRG2_PRU0_GPO2  
PRG2_PRU0_GPO0  
PRG2_PRU0_GPI0  
PRG2_RGMII1_RD0  
GPMC0_A25  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
Yes  
Yes  
Yes  
I
OZ  
O
I
TRC_CLK  
EHRPWM0_SYNCI  
PRG2_PWM3_A0  
GPIO0_30  
0
0
0
0
0
0
IO  
IO  
IO  
I
PRG2_PRU0_GPO1  
PRG2_PRU0_GPI1  
PRG2_RGMII1_RD1  
GPMC0_A24  
I
OZ  
O
O
O
IO  
IO  
I
TRC_CTL  
EHRPWM0_SYNCO  
SYNC2_OUT  
GPIO0_31  
0
0
0
0
PRG2_PRU0_GPO2  
PRG2_PRU0_GPI2  
PRG2_RGMII1_RD2  
GPMC0_A23  
I
OZ  
O
I
TRC_DATA0  
EHRPWM_TZn_IN0  
SYNC3_OUT  
0
0
O
IO  
GPIO0_32  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AG18  
AG17  
AF17  
AE17  
PRG2_PRU0_GPO3  
PRG2_PRU0_GPO3  
0
IO  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
PRG2_PRU0_GPI3  
PRG2_RGMII1_RD3  
GPMC0_A22  
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
0
0
I
OZ  
O
TRC_DATA1  
EHRPWM0_A  
IO  
IO  
IO  
IO  
I
0
1
0
0
0
0
PRG2_PWM3_B0  
GPIO0_33  
PRG2_PRU0_GPO4  
PRG2_PRU0_GPO5  
PRG2_PRU0_GPO6  
PRG2_PRU0_GPO4  
PRG2_PRU0_GPI4  
PRG2_RGMII1_RX_CTL  
GPMC0_A21  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
Yes  
Yes  
Yes  
I
OZ  
O
TRC_DATA2  
EHRPWM0_B  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
PRG2_PWM0_A0  
GPIO0_34  
PRG2_PRU0_GPO5  
PRG2_PRU0_GPI5  
PRG2_RGMII1_RXC  
GPMC0_A20  
I
OZ  
O
TRC_DATA3  
EHRPWM1_A  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
PRG2_PWM3_A1  
GPIO0_35  
PRG2_PRU0_GPO6  
PRG2_PRU0_GPI6  
PRG2_RGMII1_TX_CTL  
GPMC0_A19  
O
OZ  
O
TRC_DATA4  
EHRPWM1_B  
IO  
IO  
IO  
0
1
0
PRG2_PWM3_B1  
GPIO0_36  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AC19  
PRG2_PRU0_GPO7  
PRG2_PRU0_GPO7  
PRG2_PRU0_GPI7  
PRG2_MDIO0_MDIO  
GPMC0_A18  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
I
0
0
IO  
OZ  
O
TRC_DATA5  
EHRPWM_TZn_IN1  
EHRPWM_SOCA  
GPIO0_37  
I
0
O
IO  
IO  
I
0
0
0
AH16  
PRG2_PRU0_GPO8  
PRG2_PRU0_GPO8  
PRG2_PRU0_GPI8  
PRG2_RGMII1_TD0  
GPMC0_A17  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
OZ  
O
TRC_DATA6  
EHRPWM2_A  
IO  
IO  
IO  
IO  
I
0
1
0
0
0
PRG2_PWM0_B0  
GPIO0_38  
AG16  
PRG2_PRU0_GPO9  
PRG2_PRU0_GPO9  
PRG2_PRU0_GPI9  
PRG2_RGMII1_TD1  
GPMC0_A16  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
OZ  
O
TRC_DATA7  
EHRPWM2_B  
IO  
IO  
IO  
I
0
0
0
0
GPIO0_39  
AF16  
PRG2_PRU0_GPO10  
PRG2_PRU0_GPO10  
PRG2_PRU0_GPI10  
PRG2_RGMII1_TD2  
GPMC0_A15  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
OZ  
O
TRC_DATA8  
EHRPWM_TZn_IN2  
EHRPWM_SOCB  
GPIO0_40  
I
0
0
O
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AE16  
AD16  
AH15  
PRG2_PRU0_GPO11  
PRG2_PRU0_GPO11  
0
IO  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
PRG2_PRU0_GPI11  
PRG2_RGMII1_TD3  
GPMC0_A14  
1
2
3
4
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
0
O
OZ  
O
TRC_DATA9  
PRG2_ECAP0_IN_APWM_OUT  
GPIO0_41  
IO  
IO  
IO  
I
0
0
0
0
0
PRG2_PRU0_GPO16  
PRG2_PRU0_GPO16  
PRG2_PRU0_GPI16  
PRG2_RGMII1_TXC  
GPMC0_A13  
1.8 V/3.3 V VDDSHV5  
Yes  
IO  
OZ  
O
TRC_DATA10  
PRG2_PWM0_A1  
GPIO0_42  
IO  
IO  
IO  
I
0
0
0
0
0
PRG2_PRU1_GPO0  
PRG2_PRU1_GPO0  
PRG2_PRU1_GPI0  
PRG2_RGMII2_RD0  
GPMC0_A12  
1.8 V/3.3 V VDDSHV5  
Yes  
I
OZ  
O
TRC_DATA11  
EHRPWM3_A  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
0
PRG2_PWM3_A2  
GPIO0_43  
AC16  
PRG2_PRU1_GPO1  
PRG2_PRU1_GPO1  
PRG2_PRU1_GPI1  
PRG2_RGMII2_RD1  
GPMC0_A11  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
OZ  
O
TRC_DATA12  
EHRPWM3_B  
IO  
IO  
IO  
0
1
0
PRG2_PWM3_B2  
GPIO0_44  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AD17  
PRG2_PRU1_GPO2  
PRG2_PRU1_GPO2  
PRG2_PRU1_GPI2  
PRG2_RGMII2_RD2  
GPMC0_A10  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
3
4
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
7
I
0
0
I
OZ  
O
I
TRC_DATA13  
EHRPWM3_SYNCI  
PRG2_PWM0_B1  
GPIO0_45  
0
1
0
0
0
0
IO  
IO  
IO  
I
AH14  
PRG2_PRU1_GPO3  
PRG2_PRU1_GPO3  
PRG2_PRU1_GPI3  
PRG2_RGMII2_RD3  
GPMC0_A9  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
OZ  
O
O
IO  
IO  
I
TRC_DATA14  
EHRPWM3_SYNCO  
GPIO0_46  
0
0
0
0
AG14  
PRG2_PRU1_GPO4  
PRG2_PRU1_GPO4  
PRG2_PRU1_GPI4  
PRG2_RGMII2_RX_CTL  
GPMC0_A8  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
OZ  
O
I
TRC_DATA15  
EHRPWM_TZn_IN3  
PRG2_ECAP0_SYNC_OUT  
GPIO0_47  
0
O
IO  
IO  
I
0
0
0
0
AG15  
PRG2_PRU1_GPO5  
PRG2_PRU1_GPO5  
PRG2_PRU1_GPI5  
PRG2_RGMII2_RXC  
GPMC0_A7  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
I
OZ  
O
IO  
IO  
IO  
I
TRC_DATA16  
EHRPWM4_A  
0
0
0
0
GPIO0_48  
AC17  
PRG2_PRU1_GPO6  
PRG2_PRU1_GPO6  
PRG2_PRU1_GPI6  
PRG2_RGMII2_TX_CTL  
GPMC0_A6  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
O
OZ  
O
IO  
IO  
TRC_DATA17  
EHRPWM4_B  
0
0
GPIO0_49  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AE15  
AD15  
AF14  
AC15  
PRG2_PRU1_GPO7  
PRG2_PRU1_GPO7  
0
IO  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
Yes  
PRG2_PRU1_GPI7  
PRG2_MDIO0_MDC  
GPMC0_A5  
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
0
O
OZ  
O
I
TRC_DATA18  
EHRPWM_TZn_IN4  
PRG2_PWM3_TZ_IN  
GPIO0_50  
0
0
0
0
0
I
IO  
IO  
I
PRG2_PRU1_GPO8  
PRG2_PRU1_GPO9  
PRG2_PRU1_GPO10  
PRG2_PRU1_GPO8  
PRG2_PRU1_GPI8  
PRG2_RGMII2_TD0  
GPMC0_A4  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
1.8 V/3.3 V VDDSHV5  
Yes  
Yes  
Yes  
O
OZ  
O
IO  
IO  
IO  
IO  
I
TRC_DATA19  
EHRPWM5_A  
0
0
0
0
0
PRG2_PWM0_A2  
GPIO0_51  
PRG2_PRU1_GPO9  
PRG2_PRU1_GPI9  
PRG2_RGMII2_TD1  
GPMC0_A3  
O
OZ  
O
IO  
O
IO  
IO  
I
TRC_DATA20  
EHRPWM5_B  
0
PRG2_PWM3_TZ_OUT  
GPIO0_52  
0
0
0
PRG2_PRU1_GPO10  
PRG2_PRU1_GPI10  
PRG2_RGMII2_TD2  
GPMC0_A2  
O
OZ  
O
I
TRC_DATA21  
EHRPWM_TZn_IN5  
PRG2_PWM0_B2  
GPIO0_53  
0
1
0
IO  
IO  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AD14  
PRG2_PRU1_GPO11  
PRG2_PRU1_GPO11  
PRG2_PRU1_GPI11  
PRG2_RGMII2_TD3  
GPMC0_A1  
0
IO  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0
0/1  
Yes  
1
2
3
4
6
7
0
1
2
3
4
6
7
I
0
O
OZ  
O
I
TRC_DATA22  
PRG2_ECAP0_SYNC_IN  
GPIO0_54  
0
0
0
0
0
IO  
IO  
I
AE14  
PRG2_PRU1_GPO16  
PRG2_PRU1_GPO16  
PRG2_PRU1_GPI16  
PRG2_RGMII2_TXC  
GPMC0_A0  
OFF  
7
1.8 V/3.3 V VDDSHV5  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
IO  
OZ  
O
O
IO  
O
TRC_DATA23  
PRG2_PWM1_TZ_OUT  
GPIO0_55  
0
AF9  
AF10  
AE8  
AE9  
REFCLK0N  
REFCLK0P  
REFCLK1N  
REFCLK1P  
REFCLK0N  
OFF  
OFF  
OFF  
OFF  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_S  
ERDES0  
LJCB CLK  
LJCB CLK  
LJCB CLK  
LJCB CLK  
No  
No  
No  
No  
REFCLK0P  
REFCLK1N  
REFCLK1P  
O
O
O
VDDA_1P8_S  
ERDES0  
VDDA_1P8_S  
ERDES0  
VDDA_1P8_S  
ERDES0  
D19  
F17  
AG5  
RESETSTATz  
RESETz  
RESETSTATz  
RESETz  
0
0
O
I
OFF  
PU  
0
0
0
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
Yes  
Yes  
LVCMOS  
LVCMOS  
SERDES0  
PU/PD  
PU/PD  
0/0  
1/1  
Yes  
Yes  
No  
SERDES0_REFCLKN  
SERDES0_REFCLKN  
I
OFF  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_S  
ERDES0  
AG6  
AC9  
AH3  
AG2  
AH4  
AG3  
AH6  
AH7  
SERDES0_REFCLKP  
SERDES0_REFRES  
SERDES0_RXN  
SERDES0_REFCLKP  
SERDES0_REFRES  
SERDES0_RXN  
I
OFF  
0
0
0
0
0
0
0
0
VDDA_1P8_S  
ERDES0  
SERDES0  
SERDES0  
SERDES0  
SERDES0  
SERDES0  
SERDES0  
SERDES1  
SERDES1  
No  
No  
No  
No  
No  
No  
No  
No  
A
I
VDDA_1P8_S  
ERDES0  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
VDDA_1P8_S  
ERDES0  
SERDES0_RXP  
SERDES0_RXP  
I
VDDA_1P8_S  
ERDES0  
SERDES0_TXN  
SERDES0_TXN  
O
O
I
VDDA_1P8_S  
ERDES0  
SERDES0_TXP  
SERDES0_TXP  
VDDA_1P8_S  
ERDES0  
SERDES1_REFCLKN  
SERDES1_REFCLKP  
SERDES1_REFCLKN  
SERDES1_REFCLKP  
VDDA_1P8_S  
ERDES0  
I
VDDA_1P8_S  
ERDES0  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AC14  
AG9  
AH10  
AH9  
SERDES1_REFRES  
SERDES1_RXN  
SERDES1_RXP  
SERDES1_TXN  
SERDES1_TXP  
SERDES1_REFRES  
A
0
0
0
0
0
1.8 V  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_1P8_S  
ERDES0  
SERDES1  
SERDES1  
SERDES1  
SERDES1  
SERDES1  
No  
No  
No  
No  
No  
SERDES1_RXN  
SERDES1_RXP  
SERDES1_TXN  
SERDES1_TXP  
I
OFF  
OFF  
OFF  
OFF  
VDDA_1P8_S  
ERDES0  
I
VDDA_1P8_S  
ERDES0  
O
O
VDDA_1P8_S  
ERDES0  
AG8  
VDDA_1P8_S  
ERDES0  
E20  
SOC_SAFETY_ERRORn  
SPI0_CLK  
SOC_SAFETY_ERRORn  
SPI0_CLK  
0
IO  
IO  
IO  
IO  
O
PD  
0
7
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1/0  
0/1  
Yes  
Yes  
AH13  
0
7
0
3
4
7
0
7
0
1
2
6
7
0
7
0
7
0
3
4
6
7
0
1
2
7
OFF  
Yes  
0
GPIO1_17  
0
0
AH12  
SPI1_CLK  
SPI1_CLK  
OFF  
7
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
PRG2_IEP0_EDC_SYNC_OUT0  
PRG2_UART0_RTSn  
GPIO1_22  
O
IO  
IO  
IO  
IO  
O
0
1
0
1
AG13  
AF13  
SPI0_CS0  
SPI0_CS1  
SPI0_CS0  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1  
1.8 V/3.3 V VDDSHV1  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
GPIO1_15  
SPI0_CS1  
CPTS0_TS_COMP  
I2C3_SCL  
IOD  
O
1
PRG1_IEP0_EDIO_OUTVALID  
GPIO1_16  
IO  
IO  
IO  
IO  
IO  
IO  
I
0
0
0
0
0
1
0
1
AE13  
AD13  
AD12  
SPI0_D0  
SPI0_D1  
SPI1_CS0  
SPI0_D0  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV1  
1.8 V/3.3 V VDDSHV1  
1.8 V/3.3 V VDDSHV1  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0/1  
0/1  
0/1  
Yes  
Yes  
Yes  
GPIO1_18  
SPI0_D1  
GPIO1_19  
SPI1_CS0  
PRG2_IEP0_EDC_LATCH_IN0  
PRG2_UART0_CTSn  
PRG0_IEP0_EDIO_OUTVALID  
GPIO1_20  
I
O
IO  
IO  
O
0
1
AG12  
SPI1_CS1  
SPI1_CS1  
OFF  
7
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
CPTS0_TS_SYNC  
I2C3_SDA  
IOD  
IO  
1
0
GPIO1_21  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AE12  
AF12  
AA4  
SPI1_D0  
SPI1_D0  
0
IO  
OFF  
OFF  
PU  
7
7
0
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
0/1  
0/1  
1/1  
Yes  
Yes  
Yes  
PRG2_IEP0_EDC_LATCH_IN1  
PRG2_UART0_RXD  
GPIO1_23  
3
4
7
0
3
4
7
0
I
0
1
0
0
I
IO  
IO  
O
O
IO  
I
SPI1_D1  
SPI1_D1  
1.8 V/3.3 V VDDSHV1  
Yes  
PRG2_IEP0_EDC_SYNC_OUT1  
PRG2_UART0_TXD  
GPIO1_24  
0
TCK  
TCK  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
C20  
A20  
W6  
TDI  
TDI  
0
0
I
PU  
PU  
0
0
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
1.8 V  
Yes  
Yes  
Yes  
Yes  
LVCMOS  
LVCMOS  
Power  
PU/PD  
PU/PD  
1/1  
0/0  
Yes  
Yes  
No  
TDO  
TDO  
OZ  
A
TEMP_DIODE_P  
TIMER_IO0  
TEMP_DIODE_P  
TIMER_IO0  
SYSCLKOUT0  
GPIO1_88  
TIMER_IO1  
OBSCLK0  
GPIO1_89  
TMS  
B22  
0
2
7
0
2
7
0
0
IO  
O
IO  
IO  
O
IO  
I
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV0  
LVCMOS  
PU/PD  
PU/PD  
0
0/1  
0/1  
Yes  
0
0
C23  
TIMER_IO1  
1.8 V/3.3 V VDDSHV0  
1.8 V/3.3 V VDDSHV0  
LVCMOS  
Yes  
0
A21  
AA3  
TMS  
PU  
PD  
0
0
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
1/1  
1/1  
Yes  
Yes  
TRSTn  
TRSTn  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
AG11  
UART0_CTSn  
UART0_CTSn  
TIMER_IO4  
SPI0_CS2  
0
1
2
7
0
1
2
7
0
7
0
7
I
OFF  
7
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
PU/PD  
1
0
1
0
0/1  
Yes  
IO  
IO  
IO  
O
GPIO1_27  
AD11  
UART0_RTSn  
UART0_RTSn  
TIMER_IO5  
SPI0_CS3  
OFF  
7
1.8 V/3.3 V VDDSHV1  
Yes  
LVCMOS  
PU/PD  
0/1  
Yes  
IO  
IO  
IO  
I
0
1
0
1
0
GPIO1_28  
AF11  
AE11  
UART0_RXD  
UART0_TXD  
UART0_RXD  
GPIO1_25  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV1  
1.8 V/3.3 V VDDSHV1  
Yes  
Yes  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
IO  
O
UART0_TXD  
GPIO1_26  
IO  
IO  
0
AE2  
AF1  
USB0_DM  
USB0_DP  
USB0_DM  
OFF  
OFF  
3.3 V  
3.3 V  
VDDA_3P3_U  
SB  
USBHS  
USBHS  
No  
No  
USB0_DP  
IO  
VDDA_3P3_U  
SB  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AD9  
USB0_DRVVBUS  
USB0_DRVVBUS  
0
O
PD  
0
1.8 V/3.3 V VDDSHV8  
Yes  
LVCMOS  
PU/PD  
0/0  
Yes  
GPIO1_71  
USB0_ID  
7
IO  
A
0
AF7  
AE7  
AD2  
AE1  
AC8  
USB0_ID  
3.3 V  
VDDA_3P3_U  
SB  
USBHS  
USBHS  
USBHS  
USBHS  
LVCMOS  
No  
No  
No  
No  
Yes  
USB0_VBUS  
USB1_DM  
USB0_VBUS  
USB1_DM  
USB1_DP  
A
VDDA_3P3_U  
SB  
IO  
IO  
OFF  
OFF  
PD  
3.3 V  
3.3 V  
VDDA_3P3_U  
SB  
USB1_DP  
VDDA_3P3_U  
SB  
USB1_DRVVBUS  
USB1_DRVVBUS  
GPIO1_72  
0
7
O
IO  
A
0
1.8 V/3.3 V VDDSHV8  
Yes  
PU/PD  
0/0  
0
AF5  
AF6  
USB1_ID  
USB1_ID  
3.3 V  
VDDA_3P3_U  
SB  
USBHS  
USBHS  
Power  
No  
No  
No  
USB1_VBUS  
USB1_VBUS  
A
VDDA_3P3_U  
SB  
AB6  
VDDA_1P8_MON_WKUP  
VDDA_1P8_SDIO  
VDDA_1P8_MON0  
VDDA_1P8_SDIO  
VDDA_1P8_CSI0  
VDDA_1P8_MON0  
VDDA_1P8_OLDI0  
VDDA_1P8_SERDES0  
A
1.8 V  
1.8 V  
G17  
PWR  
PWR  
A
L20, M21  
AC6  
VDDA_1P8_CSI0  
VDDA_1P8_MON0  
VDDA_1P8_OLDI0  
VDDA_1P8_SERDES0  
Power  
Power  
No  
No  
L22  
PWR  
PWR  
AA14, AB13,  
AB15  
AB9  
U6  
VDDA_3P3_IOLDO_WKUP  
VDDA_3P3_MON_WKUP  
VDDA_3P3_SDIO  
VDDA_3P3_USB  
VDDA_3P3_IOLDO_WKUP  
VDDA_3P3_MON0  
VDDA_3P3_SDIO  
VDDA_3P3_USB  
PWR  
A
3.3 V  
H17  
AC12  
G18  
AA21  
AC10  
M7, M9  
AB8  
U12  
H15  
H11  
PWR  
PWR  
PWR  
PWR  
A
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
VDDA_3P3_MON0  
VDDA_ADC_MCU  
VDDA_LDO_WKUP  
VDDA_MCU  
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
VDDA_3P3_MON0  
VDDA_ADC_MCU  
VDDA_LDO_WKUP  
VDDA_MCU  
3.3 V  
Power  
No  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_PLL_CORE  
VDDA_PLL_DSS  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_PLL_CORE  
VDDA_PLL_DSS  
Y17  
L21  
L12  
VDDA_PLL_MPU0  
VDDA_PLL_MPU1  
VDDA_PLL_PER0  
VDDA_PLL_MPU0  
VDDA_PLL_MPU1  
VDDA_PLL_PER0  
K15  
AB7  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
Y9  
VDDA_POR_WKUP  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
VDDA_SRAM_MPU0  
VDDA_SRAM_MPU1  
VDDA_VSYS_MON  
VDDA_WKUP  
VDDS0  
VDDA_POR_WKUP  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
VDDA_SRAM_MPU0  
VDDA_SRAM_MPU1  
VDDA_VSYS_MON  
VDDA_WKUP  
VDDS0  
PWR  
PWR  
PWR  
PWR  
PWR  
A
M19  
V16  
K7  
L18  
AC11  
AA9  
G12  
V8  
0.5 V?  
Power  
No  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
VDDS0_WKUP  
VDDS1  
VDDS0_WKUP  
VDDS1  
AA16  
T9  
VDDS1_WKUP  
VDDS2  
VDDS1_WKUP  
VDDS2  
P20  
N8  
VDDS2_WKUP  
VDDS3  
VDDS2_WKUP  
VDDS3  
T20  
Y20  
AC18  
F20  
K20  
AA10  
VDDS4  
VDDS4  
VDDS5  
VDDS5  
VDDS6  
VDDS6  
VDDS7  
VDDS7  
VDDS8  
VDDS8  
G15, H16  
VDDSHV0  
VDDSHV0  
U8, V7, W8, Y7  
AA18, AB17  
R6, R8, T7  
VDDSHV0_WKUP  
VDDSHV1  
VDDSHV0_WKUP  
VDDSHV1  
VDDSHV1_WKUP  
VDDSHV2  
VDDSHV1_WKUP  
VDDSHV2  
N20, N22, P21,  
R20, R22  
N6, P7, P9  
VDDSHV2_WKUP  
VDDSHV3  
VDDSHV2_WKUP  
VDDSHV3  
PWR  
PWR  
T21, U20, U22,  
V21, V23  
AA22, W20, W22, VDDSHV4  
Y21, Y23  
VDDSHV4  
VDDSHV5  
PWR  
PWR  
AA20, AB19,  
AB21, AB23  
VDDSHV5  
G20, H19, H21  
J20, J22, K21  
AB11  
VDDSHV6  
VDDSHV7  
VDDSHV8  
VDDS_DDR  
VDDSHV6  
VDDSHV7  
VDDSHV8  
VDDS_DDR  
PWR  
PWR  
PWR  
PWR  
G10, G14, G8,  
H13, H7, H9  
J16  
VDDS_OSC1  
VDDS_OSC1  
PWR  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AA12, J10, J12,  
J14, J19, J8, K13,  
L14, L19, M13,  
N14, P13, P15,  
P19, R14, R16,  
R18, T13, T15,  
T17, T19, U14,  
U16, U18, V13,  
V15, V19, W14,  
W18, Y11, Y13,  
Y15  
VDD_CORE  
VDD_CORE  
PWR  
G22  
H23  
VDD_DLL_MMC0  
VDD_DLL_MMC1  
VDD_MCU  
VDD_DLL_MMC0  
VDD_DLL_MMC1  
VDD_MCU  
PWR  
PWR  
PWR  
N10, P11, R10,  
R12, T11  
K11, K9, L10, L8, VDD_MPU0  
M11  
VDD_MPU0  
VDD_MPU1  
PWR  
PWR  
K16, K18, L17,  
M16, M18, N17  
VDD_MPU1  
V11, W10, W12  
VDD_WKUP0  
VDD_WKUP1  
VPP_CORE  
VPP_MCU  
VDD_WKUP0  
VDD_WKUP1  
VPP_CORE  
VPP_MCU  
PWR  
PWR  
PWR  
PWR  
M22  
F21  
T6  
OFF  
OFF  
1.8 V  
1.8 V  
Power  
Power  
No  
No  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
A1, A2, A28,  
VSS  
VSS  
GND  
AA11, AA13,  
AA15, AA17,  
AA19, AA23,  
AA26, AA7,  
AB10, AB12,  
AB14, AB16,  
AB18, AB20,  
AB22, AD4,  
AE10, AE25,  
AE5, AF15, AF2,  
AF20, AF8, AG1,  
AG10, AG28,  
AG4, AG7, AH1,  
AH11, AH2,  
AH27, AH28,  
AH5, AH8, B12,  
B15, B20, B6, B9,  
D22, E26, E28,  
E4, F14, F19,  
F22, F25, F27,  
F3, G11, G13,  
G16, G2, G21,  
G23, G7, G9, H1,  
H10, H12, H14,  
H20, H22, H24,  
H26, H28, H6,  
H8, J11, J13, J15,  
J18, J21, J23,  
J25, J27, J7, J9,  
K1, K10, K12,  
K14, K17, K19,  
K22, K23, K6, K8,  
L11, L13, L16,  
L23, L24, L26,  
L28, L3, L7, L9,  
M10, M15, M17,  
M20, M8, N11,  
N13, N16, N19,  
N21, N7, N9,  
P10, P12, P14,  
P16, P18, P22,  
P6, P8, R11, R13,  
R15, R17, R19,  
R21, R7, R9, T10,  
T12, T14, T16,  
T18, T22, T26,  
T8, U11, U13,  
U15, U17, U19,  
U21, U3, U7, U9,  
V10, V12, V14,  
V18, V20, V22,  
V6, W11, W13,  
W15, W17, W19,  
W21, W23, W7,  
W9, Y12, Y14,  
Y16, Y18, Y22,  
Y6, Y8  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
PULL UP/  
BALL  
RESET  
I/O  
VOLTAGE  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DOWN  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
TYPE [12]  
AF4  
AF3  
AE3  
AD1  
AC3  
WKUP_GPIO0_0  
WKUP_GPIO0_0  
0
IO  
OFF  
OFF  
OFF  
OFF  
OFF  
7
7
7
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
PU/PD  
0
1/1  
1/1  
1/1  
1/1  
1/1  
Yes  
Yes  
Yes  
Yes  
Yes  
MCU_SPI1_CLK  
1
IO  
IO  
I
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
WKUP_GPIO0_0  
7
MCU_BOOTMODE00  
WKUP_GPIO0_1  
Bootstrap  
WKUP_GPIO0_1  
WKUP_GPIO0_2  
WKUP_GPIO0_3  
WKUP_GPIO0_4  
0
IO  
IO  
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_SPI1_D0  
1
WKUP_GPIO0_1  
7
MCU_BOOTMODE01  
WKUP_GPIO0_2  
Bootstrap  
0
IO  
IO  
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_SPI1_D1  
1
WKUP_GPIO0_2  
7
MCU_BOOTMODE02  
WKUP_GPIO0_3  
Bootstrap  
0
IO  
IO  
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_SPI1_CS0  
1
WKUP_GPIO0_3  
7
MCU_BOOTMODE03  
WKUP_GPIO0_4  
Bootstrap  
0
IO  
O
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_MCAN1_TX  
MCU_SPI0_CS3  
1
2
1
0
0
0
0
1
1
0
0
0
1
0
0
0
MCU_ADC_EXT_TRIGGER0  
WKUP_GPIO0_4  
3
7
IO  
I
MCU_BOOTMODE04  
WKUP_GPIO0_5  
Bootstrap  
AD3  
WKUP_GPIO0_5  
0
1
2
3
7
0
1
2
7
0
1
2
7
IO  
I
OFF  
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
PU/PD  
0/1  
Yes  
MCU_MCAN1_RX  
MCU_SPI1_CS3  
IO  
I
MCU_ADC_EXT_TRIGGER1  
WKUP_GPIO0_5  
IO  
IO  
I
AC2  
AC1  
WKUP_GPIO0_6  
WKUP_GPIO0_7  
WKUP_GPIO0_6  
OFF  
OFF  
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
0/1  
0/1  
Yes  
Yes  
WKUP_UART0_CTSn  
MCU_CPTS0_HW1TSPUSH  
WKUP_GPIO0_6  
I
IO  
IO  
O
I
WKUP_GPIO0_7  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
WKUP_UART0_RTSn  
MCU_CPTS0_HW2TSPUSH  
WKUP_GPIO0_7  
0
0
IO  
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表6-1. Pin Attributes (continued)  
BALL  
RESET  
REL.  
RXACTIVE  
BALL  
RESET  
I/O  
VOLTAGE  
PULL UP/  
DOWN  
TYPE [12]  
BALL NUMBER  
MUXMOD  
E [4]  
BUFFER  
TYPE [11]  
/
IO Daisy  
BALL NAME [2]  
SIGNAL NAME [3]  
TYPE [5]  
POWER [9]  
HYS [10]  
DSIS [13]  
[1]  
TXDISABL Chain [15]  
E [14]  
STATE [6] MUXMOD VALUE [8]  
E [7]  
AC5  
AB4  
AB3  
WKUP_GPIO0_8  
WKUP_GPIO0_8  
0
IO  
OFF  
OFF  
OFF  
7
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
LVCMOS  
LVCMOS  
PU/PD  
PU/PD  
PU/PD  
0
1/1  
1/1  
0/1  
Yes  
Yes  
Yes  
MCU_CPTS0_TS_SYNC  
WKUP_GPIO0_8  
2
O
IO  
I
7
0
0
0
MCU_BOOTMODE08  
WKUP_GPIO0_9  
Bootstrap  
WKUP_GPIO0_9  
WKUP_GPIO0_10  
0
IO  
O
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
MCU_CPTS0_TS_COMP  
WKUP_GPIO0_9  
2
7
0
0
0
0
0
MCU_BOOTMODE09  
WKUP_GPIO0_10  
MCU_EXT_REFCLK0  
MCU_CPTS0_RFT_CLK  
MCU_SYSCLKOUT0  
WKUP_GPIO0_10  
WKUP_GPIO0_11  
MCU_OBSCLK0  
Bootstrap  
0
1
4
5
7
0
1
4
6
7
0
IO  
I
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
I
O
IO  
IO  
O
IO  
O
IO  
IOD  
0
0
AB2  
WKUP_GPIO0_11  
OFF  
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
PU/PD  
0/1  
Yes  
MCU_TIMER_IO1  
MCU_CLKOUT0  
0
WKUP_GPIO0_11  
WKUP_I2C0_SCL  
0
1
AC7  
AD6  
WKUP_I2C0_SCL  
WKUP_I2C0_SDA  
OFF  
OFF  
0
0
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
I2C OPEN  
DRAIN  
1/0  
1/0  
Yes  
Yes  
WKUP_I2C0_SDA  
0
IOD  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
I2C OPEN  
DRAIN  
1
AE4  
AC4  
AD5  
AE6  
AB1  
WKUP_LFOSC0_XI  
WKUP_LFOSC0_XO  
WKUP_OSC0_XI  
WKUP_LFOSC0_XI  
WKUP_LFOSC0_XO  
WKUP_OSC0_XI  
I
OFF  
OFF  
OFF  
OFF  
OFF  
1.8 V  
1.8 V  
1.8 V  
1.8 V  
VDDA_WKUP  
VDDA_WKUP  
VDDA_WKUP  
VDDA_WKUP  
Analog  
Analog  
Analog  
Analog  
LVCMOS  
No  
No  
No  
No  
Yes  
O
I
WKUP_OSC0_XO  
WKUP_UART0_RXD  
WKUP_OSC0_XO  
WKUP_UART0_RXD  
WKUP_GPIO0_52  
WKUP_UART0_TXD  
WKUP_GPIO0_53  
O
I
0
7
0
7
7
7
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
PU/PD  
PU/PD  
1
0
1
0
0/1  
0/1  
IO  
O
IO  
AB5  
WKUP_UART0_TXD  
OFF  
1.8 V/3.3 V VDDSHV0_WK Yes  
UP  
LVCMOS  
Yes  
The following list describes the table column headers:  
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.  
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).  
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).  
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Note  
表6-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in 节  
6.3, Signal Descriptions.  
4. MUXMODE: Multiplexing mode number:  
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode.  
Note  
The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column.  
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate  
functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.  
c. Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These are not programable MUXMODE.  
d. An empty box means Not Applicable.  
5. TYPE: This column describes functionality of the pin when configured for the given mux mode. It does not represent all capabilities of the pin, and as  
such, there may be other mux mode configurations where these pins operate as a push-pull driver:  
• I = Input  
• O = Output  
• IO = Input or Output  
• IOD = Open drain terminal - Input or Output  
• IOZ = Input, Output or Three-state terminal  
• OZ = Output or Three-state terminal  
• A = Analog  
• PWR = Power  
• GND = Ground  
• CAP = LDO Capacitor.  
6. BALL RESET STATE: The state of the terminal at power-on reset:  
• DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).  
• DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).  
• OFF: High-impedance  
• PD: High-impedance with an active pulldown resistor  
• PU: High-impedance with an active pullup resistor  
• An empty box means Not Applicable.  
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal.  
An empty box means Not Applicable.  
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).  
An empty box means Not Applicable.  
9. POWER: The voltage supply that powers the terminal IO buffers.  
An empty box means Not Applicable.  
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10. HYS: Indicates if the input buffer has hysteresis:  
• Yes: With hysteresis  
• No: Without hysteresis  
An empty box means No.  
For more information, see the hysteresis values in 节7.6, Electrical Characteristics.  
11. BUFFER TYPE: This column describes the associated output buffer type  
An empty box means Not Applicable.  
For drive strength of the associated output buffer, refer to 节7.6, Electrical Characteristics.  
12. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled  
via software.  
• PU: Internal pullup  
• PD: Internal pulldown  
• PU/PD: Internal pullup and pulldown  
• An empty box means No pull.  
13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin  
function is not selected by any of the PINCNTLx registers.  
• 0: Logic 0 driven on the input signal port of the peripheral.  
• 1: Logic 1 driven on the input signal port of the peripheral.  
• An empty box means Not Applicable.  
14. RXACTIVE / TXDISABLE:This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.  
• RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.  
• TXDISABLE: 0 = driver enabled, 1 = driver disabled.  
• An empty box means Not Applicable.  
15. IO Daisy Chain:This column indicates which pins can be included in the daisy chain during low power modes.  
Note  
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the  
proper software configuration (HiZ mode is not an input signal).  
Note  
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be  
avoided.  
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6.3 Signal Descriptions  
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing  
options.  
The following list describes the column headers:  
1. SIGNAL NAME: The name of the signal passing through the pin.  
Note  
In 表6-1 and 表6-76 are not described the subsystem multiplexing signals.  
2. DESCRIPTION: Description of the signal  
3. PIN TYPE: This column describes functionality of the pin when configured for the given mux mode. It does  
not represent all capabilities of the pin, and as such, there may be other mux mode configurations where  
these pins operate as a push-pull driver:  
• I = Input  
• O = Output  
• IO = Input or Output  
• IOD = Open drain terminal - Input or Output  
• IOZ = Input, Output or Three-state terminal  
• OZ = Output or Three-state terminal  
• A = Analog  
• PWR = Power  
• GND = Ground  
• CAP = LDO Capacitor  
4. BALL: Associated balls bottom  
For more information on the I/O cell configurations, see the Pad Configuration Registers section in the  
device TRM.  
6.3.1 ADC  
6.3.1.1 MCU Domain  
表6-2. ADC Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_ADC_EXT_TRIGGER0  
MCU_ADC_EXT_TRIGGER1  
ADC Trigger Input  
ADC Trigger Input  
I
I
AC3  
AD3  
表6-3. ADC0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_ADC0_REFN  
MCU_ADC0_REFP  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
ADC Reference Input (negative)  
ADC Reference Input (positive)  
ADC Analog Input 0  
A
A
A
A
A
A
A
A
A
A
K2  
K3  
K5  
J3  
J1  
J5  
K4  
J4  
J2  
J6  
ADC Analog Input 1  
ADC Analog Input 2  
ADC Analog Input 3  
ADC Analog Input 4  
ADC Analog Input 5  
ADC Analog Input 6  
ADC Analog Input 7  
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表6-4. ADC1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
MCU_ADC1_REFN  
DESCRIPTION [2]  
ADC Reference Input (negative)  
BALL [4]  
[3]  
A
A
A
A
A
A
A
A
A
A
H3  
H2  
F4  
G6  
G4  
H5  
F5  
G5  
G3  
H4  
MCU_ADC1_REFP  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
ADC Reference Input (positive)  
ADC Analog Input 0  
ADC Analog Input 1  
ADC Analog Input 2  
ADC Analog Input 3  
ADC Analog Input 4  
ADC Analog Input 5  
ADC Analog Input 6  
ADC Analog Input 7  
6.3.2 CAL  
6.3.2.1 MAIN Domain  
表6-5. CSI0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
CSI0_RXN0  
CSI0_RXN1  
CSI0_RXN2  
CSI0_RXN3  
CSI0_RXN4(1)  
CSI0_RXP0  
CSI0_RXP1  
CSI0_RXP2  
CSI0_RXP3  
CSI0_RXP4(1)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (negative)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
CSI Differential Receive Input (positive)  
I
I
I
I
I
I
I
I
I
I
G28  
H27  
F26  
H25  
G24  
F28  
G27  
G26  
G25  
F24  
(1) Line 4 (position 5) supports only data. For more information, see the Camera Adapter Layer (CAL) Subsystem section in the device  
TRM.  
表6-6. VIN0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
Video Input Horizontal Sync  
BALL [4]  
[3]  
VIN0_HD  
I
P23  
R28  
R23  
N23  
M26  
P28  
P27  
N26  
N25  
P24  
R27  
T24  
T23  
VIN0_PCLK  
VIN0_VD  
Video Input Pixel Clock  
Video Input Vertical Sync  
Video Input Data 0  
Video Input Data 1  
Video Input Data 2  
Video Input Data 3  
Video Input Data 4  
Video Input Data 5  
Video Input Data 6  
Video Input Data 7  
Video Input Data 8  
Video Input Data 9  
I
I
VIN0_DATA0  
VIN0_DATA1  
VIN0_DATA2  
VIN0_DATA3  
VIN0_DATA4  
VIN0_DATA5  
VIN0_DATA6  
VIN0_DATA7  
VIN0_DATA8  
VIN0_DATA9  
I
I
I
I
I
I
I
I
I
I
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表6-6. VIN0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
VIN0_DATA10  
VIN0_DATA11  
VIN0_DATA12  
VIN0_DATA13  
VIN0_DATA14  
VIN0_DATA15  
Video Input Data 10  
Video Input Data 11  
Video Input Data 12  
Video Input Data 13  
Video Input Data 14  
Video Input Data 15  
I
I
I
I
I
I
R25  
T27  
M27  
M23  
M28  
M24  
6.3.3 CPSW2G  
6.3.3.1 MCU Domain  
表6-7. CPSW2G0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_MDIO0_MDC  
MCU_MDIO0_MDIO  
MCU_RGMII1_RXC  
MCU_RGMII1_RX_CTL  
MCU_RGMII1_TXC  
MCU_RGMII1_TX_CTL  
MCU_RGMII1_RD0  
MCU_RGMII1_RD1  
MCU_RGMII1_RD2  
MCU_RGMII1_RD3  
MCU_RGMII1_TD0  
MCU_RGMII1_TD1  
MCU_RGMII1_TD2  
MCU_RGMII1_TD3  
MCU_RMII1_CRS_DV  
MCU_RMII1_REF_CLK  
MCU_RMII1_RX_ER  
MCU_RMII1_TX_EN  
MCU_RMII1_RXD0  
MCU_RMII1_RXD1  
MCU_RMII1_TXD0  
MCU_RMII1_TXD1  
MDIO Clock  
O
IO  
I
L1  
L4  
MDIO Data  
RGMII Receive Clock  
RGMII Receive Control  
RGMII Transmit Clock  
RGMII Transmit Control  
RGMII Receive Data 0  
RGMII Receive Data 1  
RGMII Receive Data 2  
RGMII Receive Data 3  
RGMII Transmit Data 0  
RGMII Transmit Data 1  
RGMII Transmit Data 2  
RGMII Transmit Data 3  
RMII Carrier Sense / Data Valid  
RMII Reference Clock  
RMII Receive Data Error  
RMII Transmit Enable  
RMII Receive Data 0  
RMII Receive Data 1  
RMII Transmit Data 0  
RMII Transmit Data 1  
M1  
N5  
N1  
N4  
L6  
I
IO  
O
I
I
M6  
L5  
I
I
L2  
O
O
O
O
I
M5  
M4  
M3  
M2  
N4  
M1  
N5  
N1  
L6  
I
I
O
I
I
M6  
M5  
M4  
O
O
6.3.4 DDRSS  
6.3.4.1 MAIN Domain  
表6-8. DDRSS0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
DDR_AC0  
DDR_AC1  
DDR_AC2  
DDR_AC3  
DDR_AC4  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
IO  
IO  
IO  
IO  
IO  
A10  
D9  
C9  
E9  
A9  
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表6-8. DDRSS0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
DDR_AC5  
DDR_AC6  
DDR_AC7  
DDR_AC8  
DDR_AC9  
DDR_AC10  
DDR_AC11  
DDR_AC12  
DDR_AC13  
DDR_AC14  
DDR_AC15  
DDR_AC16  
DDR_AC17  
DDR_AC18  
DDR_AC19  
DDR_AC20  
DDR_AC21  
DDR_AC22  
DDR_AC23  
DDR_AC24  
DDR_AC25  
DDR_AC26  
DDR_AC27  
DDR_AC28  
DDR_AC29  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Address and Command Bus  
DDRSS Parity Error  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
E8  
F8  
C7  
C8  
D7  
E7  
A6  
F7  
D6  
C6  
F6  
E6  
E5  
D8  
D10  
E10  
C10  
F11  
B10  
D11  
B11  
C11  
E11  
E12  
D12  
D5  
B8  
DDR_ALERTn  
DDR_CK0N  
DDR_CK0P  
DDR_CK1N  
DDR_CK1P  
DDR_DM0  
DDR_DM1  
DDR_DM2  
DDR_DM3  
DDR_DQ0  
DDR_DQ1  
DDR_DQ2  
DDR_DQ3  
DDR_DQ4  
DDR_DQ5  
DDR_DQ6  
DDR_DQ7  
DDR_DQ8  
DDR_DQ9  
DDR_DQ10  
DDRSS Differential Clock (negative)  
DDRSS Differential Clock (positive)  
DDRSS Differential Clock (negative)  
DDRSS Differential Clock (positive)  
DDRSS Data Mask  
A8  
B7  
A7  
E1  
DDRSS Data Mask  
C5  
D14  
B17  
A3  
DDRSS Data Mask  
DDRSS Data Mask  
DDRSS Data  
DDRSS Data  
B2  
DDRSS Data  
C2  
D2  
E2  
DDRSS Data  
DDRSS Data  
DDRSS Data  
G1  
F2  
DDRSS Data  
DDRSS Data  
F1  
DDRSS Data  
E3  
DDRSS Data  
C3  
D3  
DDRSS Data  
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表6-8. DDRSS0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
DDR_DQ11  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
DDRSS Data  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A
B3  
DDR_DQ12  
D4  
DDR_DQ13  
C4  
DDR_DQ14  
B4  
DDR_DQ15  
B5  
DDR_DQ16  
E13  
C14  
B14  
A14  
E14  
B13  
C13  
D13  
D15  
C15  
E16  
E15  
D16  
B16  
C16  
A17  
C1  
DDR_DQ17  
DDR_DQ18  
DDR_DQ19  
DDR_DQ20  
DDR_DQ21  
DDR_DQ22  
DDR_DQ23  
DDR_DQ24  
DDR_DQ25  
DDR_DQ26  
DDR_DQ27  
DDR_DQ28  
DDR_DQ29  
DDR_DQ30  
DDR_DQ31  
DDR_DQS0N  
DDR_DQS0P  
DDR_DQS1N  
DDR_DQS1P  
DDR_DQS2N  
DDR_DQS2P  
DDR_DQS3N  
DDR_DQS3P  
DDR_ECC_D0  
DDR_ECC_D1  
DDR_ECC_D2  
DDR_ECC_D3  
DDR_ECC_D4  
DDR_ECC_D5  
DDR_ECC_D6  
DDR_ECC_DM  
DDR_ECC_DQSN  
DDR_ECC_DQSP  
DDR_FS_RESETn(3)  
DDR_RESETn  
DDR_VREF0  
DDR_VREF_ZQ  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
D1  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
A4  
A5  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
A12  
A13  
A16  
A15  
B19  
B18  
C18  
D18  
E18  
E17  
D17  
C17  
A18  
A19  
F16  
A11  
F12  
F15  
DDRSS Complimentary Data Strobe  
DDRSS Data Strobe  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data  
DDRSS ECC Data Mask  
DDRSS ECC Complimentary Data Strobe  
DDRSS ECC Data Strobe  
Reserved  
DDRSS Reset  
DDRSS I/O Voltage Reference(1)  
DDRSS I/O Voltage Reference for ZQ calibration(1)  
A
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表6-8. DDRSS0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
DDRSS Calibration Resistor(2)  
BALL [4]  
[3]  
DDR_VTP  
A
F13  
(1) This pin is intended for observation purpose only. No external voltage should be applied to this pin.  
(2) An external 240Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.  
(3) Do not connect any signal, test point, or board trace to this signal.  
6.3.4.2 DDRSS Mapping  
表6-9 presents DDRSS interface signal mapping per device memory type.  
Note  
DDR3L and LPDDR4 memory types are not supported on this SoC.  
表6-9. DDRSS Signal Mapping  
MEMORY TYPE  
DDR4(1) (2)  
A0  
PIN  
TYPE[3]  
SIGNAL NAME [1]  
DDR_AC0  
BALL[4]  
DDR3L(2)  
A0  
LPDDR4(1)  
CA0_A  
CA1_A  
CA2_A  
CA3_A  
CA4_A  
CA5_A  
CA0_B  
CA1_B  
CA2_B  
CA3_B  
CA4_B  
CA5_B  
CS0_B  
CKE0_B  
CS1_B  
CKE1_B  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A10  
D9  
DDR_AC1  
DDR_AC2  
DDR_AC3  
DDR_AC4  
DDR_AC5  
DDR_AC6  
DDR_AC7  
DDR_AC8  
DDR_AC9  
DDR_AC10  
DDR_AC11  
DDR_AC12  
DDR_AC13  
DDR_AC14  
DDR_AC15  
DDR_AC16  
DDR_AC17  
DDR_AC18  
DDR_AC19  
DDR_AC20  
DDR_AC21  
DDR_AC22  
DDR_AC23  
DDR_AC24  
DDR_AC25  
DDR_AC26  
DDR_AC27  
DDR_AC28  
DDR_AC29  
DDR_ALERTn  
A1  
A1  
A2  
A2  
C9  
A3  
A3  
E9  
A4  
A4  
A9  
A5  
A5  
E8  
A6  
A6  
F8  
A7  
A7  
C7  
A8  
A8  
C8  
A9  
A9  
D7  
A10  
A11  
A12  
A13  
A14  
A15  
WE_n  
CAS_n  
RAS_n  
BA0  
BA1  
BA2  
A10  
E7  
A11  
A6  
A12  
F7  
A13  
D6  
A14/WE_n  
A15/CAS_n  
A16/RAS_n  
A17  
C6  
F6  
E6  
E5  
ACT_n  
BA0  
D8  
D10  
E10  
C10  
F11  
B10  
D11  
B11  
C11  
E11  
E12  
D12  
D5  
BA1  
BG0  
BG1  
PAR  
CS0_n  
ODT0  
CKE0  
CS1_n  
ODT1  
CKE1  
CS0_n  
ODT0  
CKE0  
CS1_n  
ODT1  
CKE1  
ALERT_n  
CS0_A  
CKE0_A  
CS1_A  
CKE1_A  
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表6-9. DDRSS Signal Mapping (continued)  
MEMORY TYPE  
DDR4(1) (2)  
CK0_t  
CK0_c  
CK1_t  
CK1_c  
DQ0  
PIN  
TYPE[3]  
SIGNAL NAME [1]  
BALL[4]  
DDR3L(2)  
CK0  
LPDDR4(1)  
CK_t_A  
CK_c_A  
CK_t_B  
CK_c_B  
DQ0  
DDR_CK0P  
DDR_CK0N  
DDR_CK1P  
DDR_CK1N  
DDR_DQ0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A8  
B8  
CK0_n  
CK1  
A7  
CK1_n  
DQ0  
B7  
A3  
DDR_DQ1  
DQ1  
DQ1  
DQ1  
B2  
DDR_DQ2  
DQ2  
DQ2  
DQ2  
C2  
DDR_DQ3  
DQ3  
DQ3  
DQ3  
D2  
DDR_DQ4  
DQ4  
DQ4  
DQ4  
E2  
DDR_DQ5  
DQ5  
DQ5  
DQ5  
G1  
DDR_DQ6  
DQ6  
DQ6  
DQ6  
F2  
DDR_DQ7  
DQ7  
DQ7  
DQ7  
F1  
DDR_DM0  
DDR_DQ8  
DM0  
DM0_n  
DQ8  
DMI0  
DQ8  
E1  
DQ8  
E3  
DDR_DQ9  
DQ9  
DQ9  
DQ9  
C3  
DDR_DQ10  
DDR_DQ11  
DDR_DQ12  
DDR_DQ13  
DDR_DQ14  
DDR_DQ15  
DDR_DM1  
DDR_DQ16  
DDR_DQ17  
DDR_DQ18  
DDR_DQ19  
DDR_DQ20  
DDR_DQ21  
DDR_DQ22  
DDR_DQ23  
DDR_DM2  
DDR_DQ24  
DDR_DQ25  
DDR_DQ26  
DDR_DQ27  
DDR_DQ28  
DDR_DQ29  
DDR_DQ30  
DDR_DQ31  
DDR_DM3  
DDR_ECC_D0  
DDR_ECC_D1  
DDR_ECC_D2  
DDR_ECC_D3  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DM1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DM1_n  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DM2_n  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DM3_n  
DQ32  
DQ33  
DQ34  
DQ35  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DMI1  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DMI2  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DMI3  
DQ32  
DQ33  
DQ34  
DQ35  
D3  
B3  
D4  
C4  
B4  
B5  
C5  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DM2  
E13  
C14  
B14  
A14  
E14  
B13  
C13  
D13  
D14  
D15  
C15  
E16  
E15  
D16  
B16  
C16  
A17  
B17  
B19  
B18  
C18  
D18  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DM3  
DQ32  
DQ33  
DQ34  
DQ35  
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表6-9. DDRSS Signal Mapping (continued)  
MEMORY TYPE  
DDR4(1) (2)  
DQ36  
PIN  
TYPE[3]  
SIGNAL NAME [1]  
DDR_ECC_D4  
BALL[4]  
DDR3L(2)  
DQ36  
LPDDR4(1)  
DQ36  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A
E18  
E17  
D17  
C17  
D1  
DDR_ECC_D5  
DDR_ECC_D6  
DDR_ECC_DM  
DDR_DQS0P  
DDR_DQS0N  
DDR_DQS1P  
DDR_DQS1N  
DDR_DQS2P  
DDR_DQS2N  
DDR_DQS3P  
DDR_DQS3N  
DDR_ECC_DQSP  
DDR_ECC_DQSN  
DDR_RESETn  
DDR_VREF0  
DDR_VREF_ZQ  
DDR_VTP  
DQ37  
DQ37  
DQ37  
DQ38  
DQ38  
DQ38  
DM4  
DM4_n  
DM4  
DQS0  
DQS0_t  
DQS0_c  
DQS1_t  
DQS1_c  
DQS2_t  
DQS2_c  
DQS3_t  
DQS3_c  
DQS4_t  
DQS4_c  
RESET_n  
VREF0  
DQS0  
DQS0_n  
DQS1  
DQS0_n  
DQS1  
C1  
A5  
DQS1_n  
DQS2  
DQS1_n  
DQS2  
A4  
A13  
A12  
A15  
A16  
A19  
A18  
A11  
F12  
F15  
F13  
DQS2_n  
DQS3  
DQS2_n  
DQS3  
DQS3_n  
DQS4  
DQS3_n  
DQS4  
DQS4_n  
RESET_n  
VREF0  
VREF_ZQ  
VTP  
DQS4_n  
RESET_n  
VREF0  
VREF_ZQ  
VTP  
VREF_ZQ  
VTP  
A
A
(1) This device cannot support two independent channels.  
(2) Only single rank is supported for DDR3L and DDR4.  
6.3.5 DMTIMER  
6.3.5.1 MAIN Domain  
表6-10. DMTIMER Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
B22  
[3]  
Timer Inputs and Outputs (not tied to single timer  
instance)  
TIMER_IO0  
TIMER_IO1  
TIMER_IO2  
TIMER_IO3  
TIMER_IO4  
TIMER_IO5  
TIMER_IO6  
TIMER_IO7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
C23  
Timer Inputs and Outputs (not tied to single timer  
instance)  
P23  
Timer Inputs and Outputs (not tied to single timer  
instance)  
R23  
Timer Inputs and Outputs (not tied to single timer  
instance)  
AG11  
AD11  
T24  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
Timer Inputs and Outputs (not tied to single timer  
instance)  
T23  
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6.3.5.2 MCU Domain  
表6-11. DMTIMER Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
N3  
[3]  
Timer Inputs and Outputs (not tied to single timer  
instance)  
MCU_TIMER_IO0  
MCU_TIMER_IO1  
IO  
IO  
Timer Inputs and Outputs (not tied to single timer  
instance)  
AB2  
6.3.6 DSS  
6.3.6.1 MAIN Domain  
表6-12. DSS0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
VOUT1_DE  
Video Output Data Enable  
Video Output External Pixel Clock Input  
Video Output Horizontal Sync  
Video Output Pixel Clock Output  
Video Output Vertical Sync  
Video Output Data 0  
O
I
T23  
R25  
T24  
R24  
T25  
M27  
M23  
M28  
M24  
N24  
N27  
N28  
M25  
N23  
M26  
P28  
P27  
N26  
N25  
P24  
R27  
R28  
P25  
P26  
U28  
T28  
P23  
R26  
R23  
VOUT1_EXTPCLKIN  
VOUT1_HSYNC  
VOUT1_PCLK  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
VOUT1_VSYNC  
VOUT1_DATA0  
VOUT1_DATA1  
VOUT1_DATA2  
VOUT1_DATA3  
VOUT1_DATA4  
VOUT1_DATA5  
VOUT1_DATA6  
VOUT1_DATA7  
VOUT1_DATA8  
VOUT1_DATA9  
VOUT1_DATA10  
VOUT1_DATA11  
VOUT1_DATA12  
VOUT1_DATA13  
VOUT1_DATA14  
VOUT1_DATA15  
VOUT1_DATA16  
VOUT1_DATA17  
VOUT1_DATA18  
VOUT1_DATA19  
VOUT1_DATA20  
VOUT1_DATA21  
VOUT1_DATA22  
VOUT1_DATA23  
Video Output Data 1  
Video Output Data 2  
Video Output Data 3  
Video Output Data 4  
Video Output Data 5  
Video Output Data 6  
Video Output Data 7  
Video Output Data 8  
Video Output Data 9  
Video Output Data 10  
Video Output Data 11  
Video Output Data 12  
Video Output Data 13  
Video Output Data 14  
Video Output Data 15  
Video Output Data 16  
Video Output Data 17  
Video Output Data 18  
Video Output Data 19  
Video Output Data 20  
Video Output Data 21  
Video Output Data 22  
Video Output Data 23  
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6.3.7 ECAP  
6.3.7.1 MAIN Domain  
表6-13. ECAP0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
ECAP0_IN_APWM_OUT  
DESCRIPTION [2]  
BALL [4]  
[3]  
Enhanced Capture (ECAP) Input or Auxiliary PWM  
(APWM) Ouput  
IO  
D21  
6.3.8 EHRPWM  
6.3.8.1 MAIN Domain  
表6-14. EHRPWM Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM_SOCA  
EHRPWM_SOCB  
EHRPWM_TZn_IN0  
EHRPWM_TZn_IN1  
EHRPWM_TZn_IN2  
EHRPWM_TZn_IN3  
EHRPWM_TZn_IN4  
EHRPWM_TZn_IN5  
EHRPWM Start of Conversion A  
O
O
I
AC19  
AF16  
AH17  
AC19  
AF16  
AG14  
AE15  
AC15  
EHRPWM Start of Conversion B  
EHRPWM Trip Zone Input 0 (active low)  
EHRPWM Trip Zone Input 1 (active low)  
EHRPWM Trip Zone Input 2 (active low)  
EHRPWM Trip Zone Input 3 (active low)  
EHRPWM Trip Zone Input 4 (active low)  
EHRPWM Trip Zone Input 5 (active low)  
I
I
I
I
I
表6-15. EHRPWM0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM0_A  
EHRPWM Output A  
IO  
IO  
I
AG18  
AG17  
AF18  
AE18  
EHRPWM0_B  
EHRPWM Output B  
EHRPWM0_SYNCI  
EHRPWM0_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
O
表6-16. EHRPWM1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM1_A  
EHRPWM1_B  
EHRPWM Output A  
EHRPWM Output B  
IO  
IO  
AF17  
AE17  
表6-17. EHRPWM2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM2_A  
EHRPWM2_B  
EHRPWM Output A  
EHRPWM Output B  
IO  
IO  
AH16  
AG16  
表6-18. EHRPWM3 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM3_A  
EHRPWM Output A  
IO  
IO  
I
AH15  
AC16  
AD17  
AH14  
EHRPWM3_B  
EHRPWM Output B  
EHRPWM3_SYNCI  
EHRPWM3_SYNCO  
Sync Input to EHRPWM module from an external pin  
Sync Output to EHRPWM module to an external pin  
O
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表6-19. EHRPWM4 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM4_A  
EHRPWM4_B  
EHRPWM Output A  
EHRPWM Output B  
IO  
IO  
AG15  
AC17  
表6-20. EHRPWM5 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EHRPWM5_A  
EHRPWM5_B  
EHRPWM Output A  
EHRPWM Output B  
IO  
IO  
AD15  
AF14  
6.3.9 EQEP  
6.3.9.1 MAIN Domain  
表6-21. EQEP0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EQEP0_A  
EQEP0_B  
EQEP0_I  
EQEP0_S  
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
I
AB26  
AA25  
AA28  
U23  
I
IO  
IO  
EQEP Strobe  
表6-22. EQEP1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EQEP1_A  
EQEP1_B  
EQEP1_I  
EQEP1_S  
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
I
AH22  
AE21  
AC20  
AC22  
I
IO  
IO  
EQEP Strobe  
表6-23. EQEP2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
EQEP2_A  
EQEP2_B  
EQEP2_I  
EQEP2_S  
EQEP Quadrature Input A  
EQEP Quadrature Input B  
EQEP Index  
I
D25  
B26  
A24  
E24  
I
IO  
IO  
EQEP Strobe  
6.3.10 GPIO  
6.3.10.1 MAIN Domain  
表6-24. GPIO0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
GPIO0_0  
GPIO0_1  
GPIO0_2  
GPIO0_3  
GPIO0_4  
GPIO0_5  
GPIO0_6  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
M27  
M23  
M28  
M24  
N24  
N27  
N28  
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表6-24. GPIO0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
General Purpose Input/Output  
BALL [4]  
[3]  
GPIO0_7  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
M25  
N23  
GPIO0_8  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
GPIO0_9  
M26  
GPIO0_10  
GPIO0_11  
GPIO0_12  
GPIO0_13  
GPIO0_14  
GPIO0_15  
GPIO0_16  
GPIO0_17  
GPIO0_18  
GPIO0_19  
GPIO0_20  
GPIO0_21  
GPIO0_22  
GPIO0_23  
GPIO0_24  
GPIO0_25  
GPIO0_26  
GPIO0_27  
GPIO0_28  
GPIO0_29  
GPIO0_30  
GPIO0_31  
GPIO0_32  
GPIO0_33  
GPIO0_34  
GPIO0_35  
GPIO0_36  
GPIO0_37  
GPIO0_38  
GPIO0_39  
GPIO0_40  
GPIO0_41  
GPIO0_42  
GPIO0_43  
GPIO0_44  
GPIO0_45  
GPIO0_46  
GPIO0_47  
GPIO0_48  
GPIO0_49  
GPIO0_50  
GPIO0_51  
P28  
P27  
N26  
N25  
P24  
R27  
R28  
P25  
P26  
U28  
T28  
P23  
R26  
R23  
T25  
T24  
R24  
T23  
R25  
T27  
AF18  
AE18  
AH17  
AG18  
AG17  
AF17  
AE17  
AC19  
AH16  
AG16  
AF16  
AE16  
AD16  
AH15  
AC16  
AD17  
AH14  
AG14  
AG15  
AC17  
AE15  
AD15  
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表6-24. GPIO0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
General Purpose Input/Output  
BALL [4]  
[3]  
GPIO0_52  
GPIO0_53  
GPIO0_54  
GPIO0_55  
GPIO0_56  
GPIO0_57  
GPIO0_58  
GPIO0_59  
GPIO0_60  
GPIO0_61  
GPIO0_62  
GPIO0_63  
GPIO0_64  
GPIO0_65  
GPIO0_66  
GPIO0_67  
GPIO0_68  
GPIO0_69  
GPIO0_70  
GPIO0_71  
GPIO0_72  
GPIO0_73  
GPIO0_74  
GPIO0_75  
GPIO0_76  
GPIO0_77  
GPIO0_78  
GPIO0_79  
GPIO0_80  
GPIO0_81  
GPIO0_82  
GPIO0_83  
GPIO0_84  
GPIO0_85  
GPIO0_86  
GPIO0_87  
GPIO0_88  
GPIO0_89  
GPIO0_90  
GPIO0_91  
GPIO0_92  
GPIO0_93  
GPIO0_94  
GPIO0_95  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AF14  
AC15  
AD14  
AE14  
AE22  
AG24  
AF23  
AD21  
AG23  
AF27  
AF22  
AG27  
AF28  
AF26  
AH25  
AF21  
AH20  
AH21  
AG20  
AD19  
AD20  
AH26  
AG25  
AG26  
AH24  
AH23  
AG21  
AH22  
AE21  
AC22  
AG22  
AD23  
AE24  
AF25  
AF24  
AC20  
AE20  
AF19  
AH19  
AG19  
AE19  
AE23  
AD22  
AC21  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
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表6-25. GPIO1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
General Purpose Input/Output  
ACD [4]  
[3]  
GPIO1_0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
AD18  
AH18  
D25  
GPIO1_1  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
GPIO1_2  
GPIO1_3  
B26  
GPIO1_4  
A24  
GPIO1_5  
E24  
GPIO1_6  
A25  
GPIO1_7  
C26  
GPIO1_8  
E25  
GPIO1_9  
A26  
GPIO1_10  
GPIO1_11  
GPIO1_12  
GPIO1_13  
GPIO1_14  
GPIO1_15  
GPIO1_16  
GPIO1_17  
GPIO1_18  
GPIO1_19  
GPIO1_20  
GPIO1_21  
GPIO1_22  
GPIO1_23  
GPIO1_24  
GPIO1_25  
GPIO1_26  
GPIO1_27  
GPIO1_28  
GPIO1_29  
GPIO1_30  
GPIO1_31  
GPIO1_32  
GPIO1_33  
GPIO1_34  
GPIO1_35  
GPIO1_36  
GPIO1_37  
GPIO1_38  
GPIO1_39  
GPIO1_40  
GPIO1_41  
GPIO1_42  
GPIO1_43  
GPIO1_44  
B25  
IO  
I
B27  
C25  
IO(1)  
IO(1)  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
A23  
B23  
AG13  
AF13  
AH13  
AE13  
AD13  
AD12  
AG12  
AH12  
AE12  
AF12  
AF11  
AE11  
AG11  
AD11  
V24  
W25  
W24  
AA27  
Y24  
V28  
Y25  
U27  
V27  
V26  
U25  
AB25  
AD27  
AC26  
AD26  
AA24  
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表6-25. GPIO1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
General Purpose Input/Output  
ACD [4]  
[3]  
GPIO1_45  
GPIO1_46  
GPIO1_47  
GPIO1_48  
GPIO1_49  
GPIO1_50  
GPIO1_51  
GPIO1_52  
GPIO1_53  
GPIO1_54  
GPIO1_55  
GPIO1_56  
GPIO1_57  
GPIO1_58  
GPIO1_59  
GPIO1_60  
GPIO1_61  
GPIO1_62  
GPIO1_63  
GPIO1_64  
GPIO1_65  
GPIO1_66  
GPIO1_67  
GPIO1_68  
GPIO1_69  
GPIO1_70  
GPIO1_71  
GPIO1_72  
GPIO1_73  
GPIO1_74  
GPIO1_75  
GPIO1_76  
GPIO1_77  
GPIO1_78  
GPIO1_79  
GPIO1_80  
GPIO1_86  
GPIO1_87  
GPIO1_88  
GPIO1_89  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
O
AD28  
U26  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
V25  
U24  
AB28  
AC28  
AC27  
AB26  
AA25  
U23  
AB27  
W28  
W27  
Y28  
AA28  
AB24  
AC25  
AD25  
AD24  
AE27  
AC24  
Y27  
Y26  
W26  
AE26  
AE28  
AD9  
AC8  
D27  
D26  
E27  
D28  
C27  
IO  
IO(1)  
IO(1)  
IO  
IO  
IO  
IO  
C28  
B24  
C24  
D21  
A22  
B22  
C23  
(1) When OSC1 is being used with an external crystal, this pin must only be used as an input. The output functionality must be disabled.  
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6.3.10.2 WKUP Domain  
表6-26. GPIO0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
WKUP_GPIO0_0  
DESCRIPTION [2]  
General Purpose Input/Output  
BALL [4]  
[3]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AF4  
AF3  
AE3  
AD1  
AC3  
AD3  
AC2  
AC1  
AC5  
AB4  
AB3  
AB2  
V1  
WKUP_GPIO0_1  
WKUP_GPIO0_2  
WKUP_GPIO0_3  
WKUP_GPIO0_4  
WKUP_GPIO0_5  
WKUP_GPIO0_6  
WKUP_GPIO0_7  
WKUP_GPIO0_8  
WKUP_GPIO0_9  
WKUP_GPIO0_10  
WKUP_GPIO0_11  
WKUP_GPIO0_12  
WKUP_GPIO0_13  
WKUP_GPIO0_14  
WKUP_GPIO0_15  
WKUP_GPIO0_16  
WKUP_GPIO0_17  
WKUP_GPIO0_18  
WKUP_GPIO0_19  
WKUP_GPIO0_20  
WKUP_GPIO0_21  
WKUP_GPIO0_22  
WKUP_GPIO0_23  
WKUP_GPIO0_24  
WKUP_GPIO0_25  
WKUP_GPIO0_26  
WKUP_GPIO0_27  
WKUP_GPIO0_28  
WKUP_GPIO0_29  
WKUP_GPIO0_30  
WKUP_GPIO0_31  
WKUP_GPIO0_32  
WKUP_GPIO0_33  
WKUP_GPIO0_34  
WKUP_GPIO0_35  
WKUP_GPIO0_36  
WKUP_GPIO0_37  
WKUP_GPIO0_38  
WKUP_GPIO0_39  
WKUP_GPIO0_40  
WKUP_GPIO0_41  
WKUP_GPIO0_42  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
U1  
U2  
U4  
U5  
T2  
T3  
T4  
T5  
R2  
R3  
R4  
R5  
T1  
R1  
P2  
P3  
P4  
P5  
P1  
N2  
N3  
N4  
N5  
M2  
M3  
M4  
M5  
N1  
M1  
L2  
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表6-26. GPIO0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
General Purpose Input/Output  
BALL [4]  
[3]  
WKUP_GPIO0_43  
WKUP_GPIO0_44  
WKUP_GPIO0_45  
WKUP_GPIO0_46  
WKUP_GPIO0_47  
WKUP_GPIO0_48  
WKUP_GPIO0_49  
WKUP_GPIO0_50  
WKUP_GPIO0_51  
WKUP_GPIO0_52  
WKUP_GPIO0_53  
WKUP_GPIO0_54  
WKUP_GPIO0_55  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
L5  
M6  
L6  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
General Purpose Input/Output  
L4  
L1  
Y1  
Y3  
Y2  
Y4  
AB1  
AB5  
W1  
W2  
6.3.11 GPMC  
6.3.11.1 MAIN Domain  
表6-27. GPMC0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
GPMC Address Valid (active low) or Address Latch  
Enable  
GPMC0_ADVn_ALE  
O
P25  
GPMC0_CLK  
GPMC0_DIR  
GPMC Clock Output  
O
O
R28  
T24  
GPMC Data Bus Signal Direction Control  
GPMC Output Enable (active low) or Read Enable  
(active low)  
GPMC0_OEn_REn  
O
P26  
GPMC0_WEn  
GPMC0_WPn  
GPMC Write Enable (active low)  
O
O
U28  
T25  
GPMC Flash Write Protect (active low)  
GPMC Address 0 Output. Only used to effectively  
address 8-bit data non-multiplexed memories  
GPMC0_A0  
GPMC0_A1  
GPMC0_A2  
GPMC0_A3  
GPMC0_A4  
GPMC0_A5  
GPMC0_A6  
GPMC0_A7  
GPMC0_A8  
GPMC0_A9  
GPMC0_A10  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
AE14  
AD14  
AC15  
AF14  
AD15  
AE15  
AC17  
AG15  
AG14  
AH14  
AD17  
GPMC address 1 Output in A/D non-multiplexed mode  
and Address 17 in A/D multiplexed mode  
GPMC address 2 Output in A/D non-multiplexed mode  
and Address 18 in A/D multiplexed mode  
GPMC address 3 Output in A/D non-multiplexed mode  
and Address 19 in A/D multiplexed mode  
GPMC address 4 Output in A/D non-multiplexed mode  
and Address 20 in A/D multiplexed mode  
GPMC address 5 Output in A/D non-multiplexed mode  
and Address 21 in A/D multiplexed mode  
GPMC address 6 Output in A/D non-multiplexed mode  
and Address 22 in A/D multiplexed mode  
GPMC address 7 Output in A/D non-multiplexed mode  
and Address 23 in A/D multiplexed mode  
GPMC address 8 Output in A/D non-multiplexed mode  
and Address 24 in A/D multiplexed mode  
GPMC address 9 Output in A/D non-multiplexed mode  
and Address 25 in A/D multiplexed mode  
GPMC address 10 Output in A/D non-multiplexed mode  
and Address 26 in A/D multiplexed mode  
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表6-27. GPMC0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
AC16  
AH15  
AD16  
AE16  
AF16  
AG16  
AH16  
AC19  
AE17  
AF17  
AG17  
AG18  
AH17  
AE18  
AF18  
T27  
[3]  
GPMC address 11 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC0_A11  
GPMC0_A12  
GPMC0_A13  
GPMC0_A14  
GPMC0_A15  
GPMC0_A16  
GPMC0_A17  
GPMC0_A18  
GPMC0_A19  
GPMC0_A20  
GPMC0_A21  
GPMC0_A22  
GPMC0_A23  
GPMC0_A24  
GPMC0_A25  
GPMC0_A26  
GPMC0_A27  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
OZ  
GPMC address 12 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 13 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 14 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 15 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 16 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 17 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 18 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 19 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 20 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 21 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 22 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 23 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 24 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 25 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 26 Output in A/D non-multiplexed mode  
and unused in A/D multiplexed mode  
GPMC address 27 in A/D non-multiplexed mode and  
Address 27 in A/D multiplexed mode  
R25  
GPMC Data 0 Input/Output in A/D non-multiplexed mode  
and additionally Address 1 Output in A/D multiplexed  
mode  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
IO  
IO  
IO  
IO  
IO  
IO  
M27  
M23  
M28  
M24  
N24  
N27  
GPMC Data 1 Input/Output in A/D non-multiplexed mode  
and additionally Address 2 Output in A/D multiplexed  
mode  
GPMC Data 2 Input/Output in A/D non-multiplexed mode  
and additionally Address 3 Output in A/D multiplexed  
mode  
GPMC Data 3 Input/Output in A/D non-multiplexed mode  
and additionally Address 4 Output in A/D multiplexed  
mode  
GPMC Data 4 Input/Output in A/D non-multiplexed mode  
and additionally Address 5 Output in A/D multiplexed  
mode  
GPMC Data 5 Input/Output in A/D non-multiplexed mode  
and additionally Address 6 Output in A/D multiplexed  
mode  
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表6-27. GPMC0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
GPMC Data 6 Input/Output in A/D non-multiplexed mode  
and additionally Address 7 Output in A/D multiplexed  
mode  
GPMC0_AD6  
GPMC0_AD7  
GPMC0_AD8  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
N28  
GPMC Data 7 Input/Output in A/D non-multiplexed mode  
and additionally Address 8 Output in A/D multiplexed  
mode  
M25  
N23  
M26  
P28  
P27  
N26  
N25  
P24  
GPMC Data 8 Input/Output in A/D non-multiplexed mode  
and additionally Address 9 Output in A/D multiplexed  
mode  
GPMC Data 9 Input/Output in A/D non-multiplexed mode  
and additionally Address 10 Output in A/D multiplexed  
mode  
GPMC Data 10 Input/Output in A/D non-multiplexed  
mode and additionally Address 11 Output in A/D  
multiplexed mode  
GPMC Data 11 Input/Output in A/D non-multiplexed  
mode and additionally Address 12 Output in A/D  
multiplexed mode  
GPMC Data 12 Input/Output in A/D non-multiplexed  
mode and additionally Address 13 Output in A/D  
multiplexed mode  
GPMC Data 13 Input/Output in A/D non-multiplexed  
mode and additionally Address 14 Output in A/D  
multiplexed mode  
GPMC Data 14 Input/Output in A/D non-multiplexed  
mode and additionally Address 15 Output in A/D  
multiplexed mode  
GPMC Data 15 Input/Output in A/D non-multiplexed  
mode and additionally Address 16 Output in A/D  
multiplexed mode  
GPMC0_AD15  
IO  
O
R27  
T28  
GPMC Lower-Byte Enable (active low) or Command  
Latch Enable  
GPMC0_BE0n_CLE  
GPMC0_BE1n  
GPMC0_CSn0  
GPMC0_CSn1  
GPMC0_CSn2  
GPMC0_CSn3  
GPMC0_WAIT0  
GPMC0_WAIT1  
GPMC Upper-Byte Enable (active low)  
GPMC Chip Select 0 (active low)  
GPMC Chip Select 1 (active low)  
GPMC Chip Select 2 (active low)  
GPMC Chip Select 3 (active low)  
GPMC External Indication of Wait  
GPMC External Indication of Wait  
O
O
O
O
O
I
P23  
R24  
T23  
R25  
T27  
R26  
R23  
I
6.3.12 HyperBus  
Note  
HyperBus is not available on this device.  
6.3.12.1 MCU Domain  
表6-28. HYPERBUS0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_HYPERBUS0_CK  
MCU_HYPERBUS0_CKn  
MCU_HYPERBUS0_INTn  
Hyperbus Differential Clock (positive)  
Hyperbus Differential Clock (negative)  
Hyperbus Interrupt (active low)  
O
O
I
V1  
U1  
P2  
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表6-28. HYPERBUS0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
MCU_HYPERBUS0_RESETn  
MCU_HYPERBUS0_RESETOn  
DESCRIPTION [2]  
BALL [4]  
R5  
[3]  
Hyperbus Reset (active low) Output  
O
I
Hyperbus Reset Status Indicator (active low) from  
Hyperbus Memory  
R1  
MCU_HYPERBUS0_RWDS  
MCU_HYPERBUS0_WPn  
MCU_HYPERBUS0_CSn0  
MCU_HYPERBUS0_CSn1  
MCU_HYPERBUS0_DQ0  
MCU_HYPERBUS0_DQ1  
MCU_HYPERBUS0_DQ2  
MCU_HYPERBUS0_DQ3  
MCU_HYPERBUS0_DQ4  
MCU_HYPERBUS0_DQ5  
MCU_HYPERBUS0_DQ6  
MCU_HYPERBUS0_DQ7  
Hyperbus Read-Write Data Strobe  
Hyperbus Write Protect (Not in use)  
Hyperbus Chip Select 0  
Hyperbus Chip Select 1  
Hyperbus Data 0  
IO  
O
U2  
N3  
R4  
N3  
U4  
U5  
T2  
T3  
T4  
T5  
R2  
R3  
O
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Hyperbus Data 1  
Hyperbus Data 2  
Hyperbus Data 3  
Hyperbus Data 4  
Hyperbus Data 5  
Hyperbus Data 6  
Hyperbus Data 7  
6.3.13 I2C  
6.3.13.1 MAIN Domain  
表6-29. I2C0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
I2C0_SCL  
I2C0_SDA  
I2C Clock  
I2C Data  
IOD  
IOD  
D20  
C21  
表6-30. I2C1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
I2C1_SCL  
I2C1_SDA  
I2C Clock  
I2C Data  
IOD  
IOD  
B21  
E21  
表6-31. I2C2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
I2C2_SCL  
I2C2_SDA  
I2C Clock  
I2C Data  
IOD  
IOD  
T27  
R25  
表6-32. I2C3 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
I2C3_SCL  
I2C3_SDA  
I2C Clock  
I2C Data  
IOD  
IOD  
AF13  
AG12  
6.3.13.2 MCU Domain  
表6-33. I2C0 Signal Descriptions  
DESCRIPTION [2]  
PIN TYPE  
SIGNAL NAME [1]  
BALL [4]  
[3]  
MCU_I2C0_SCL  
I2C Clock  
IOD  
AD8  
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表6-33. I2C0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_I2C0_SDA  
I2C Data  
IOD  
AD7  
6.3.13.3 WKUP Domain  
表6-34. I2C0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
WKUP_I2C0_SCL  
WKUP_I2C0_SDA  
I2C Clock  
I2C Data  
IOD  
IOD  
AC7  
AD6  
6.3.14 MCAN  
6.3.14.1 MCU Domain  
表6-35. MCAN0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_MCAN0_RX  
MCU_MCAN0_TX  
MCAN Receive Data  
MCAN Transmit Data  
I
W2  
W1  
O
表6-36. MCAN1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_MCAN1_RX  
MCU_MCAN1_TX  
MCAN Receive Data  
MCAN Transmit Data  
I
AD3  
AC3  
O
6.3.15 MCASP  
6.3.15.1 MAIN Domain  
表6-37. MCASP0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCASP0_ACLKR  
MCASP0_ACLKX  
MCASP0_AFSR  
MCASP0_AFSX  
MCASP0_AHCLKR  
MCASP0_AHCLKX  
MCASP0_AXR0  
MCASP0_AXR1  
MCASP0_AXR2  
MCASP0_AXR3  
MCASP0_AXR4  
MCASP0_AXR5  
MCASP0_AXR6  
MCASP0_AXR7  
MCASP0_AXR8  
MCASP0_AXR9  
MCASP0_AXR10  
MCASP0_AXR11  
MCASP Receive Bit Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
W24  
V24  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
AA27  
W25  
AA25  
U23  
MCASP Transmit Frame Sync  
MCASP Receive Master Clock  
MCASP Transmit Master Clock  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
Y24  
V28  
Y25  
U27  
V27  
V26  
U25  
AB25  
AD27  
AC26  
AD26  
AA24  
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表6-37. MCASP0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
MCASP0_AXR12  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
IO  
IO  
IO  
IO  
AD28  
U26  
V25  
MCASP0_AXR13  
MCASP0_AXR14  
MCASP0_AXR15  
U24  
表6-38. MCASP1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCASP1_ACLKR  
MCASP1_ACLKX  
MCASP1_AFSR  
MCASP1_AFSX  
MCASP1_AHCLKR  
MCASP1_AHCLKX  
MCASP1_AXR0  
MCASP1_AXR1  
MCASP1_AXR2  
MCASP1_AXR3  
MCASP1_AXR4  
MCASP1_AXR5  
MCASP1_AXR6  
MCASP1_AXR7  
MCASP1_AXR8  
MCASP1_AXR9  
MCASP Receive Bit Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AC27  
AB28  
AB26  
AC28  
AD28  
U26  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
MCASP Transmit Frame Sync  
MCASP Receive Master Clock  
MCASP Transmit Master Clock  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
AA25  
U23  
AB27  
W28  
W27  
Y28  
AA28  
AB24  
AC25  
AD25  
表6-39. MCASP2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCASP2_ACLKR  
MCASP2_ACLKX  
MCASP2_AFSR  
MCASP2_AFSX  
MCASP2_AHCLKR  
MCASP2_AHCLKX  
MCASP2_AXR0  
MCASP2_AXR1  
MCASP2_AXR2  
MCASP2_AXR3  
MCASP Receive Bit Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AE27  
W26  
AD24  
Y26  
MCASP Transmit Bit Clock  
MCASP Receive Frame Sync  
MCASP Transmit Frame Sync  
MCASP Receive Master Clock  
MCASP Transmit Master Clock  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
MCASP Serial Data (Input/Output)  
V25  
U24  
AC24  
Y27  
AE26  
AE28  
6.3.16 MCSPI  
6.3.16.1 MAIN Domain  
表6-40. MCSPI0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI0_CLK  
SPI0_CS0  
SPI Clock  
IO  
IO  
AH13  
AG13  
SPI Chip Select 0  
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表6-40. MCSPI0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI0_CS1  
SPI0_CS2  
SPI0_CS3  
SPI0_D0  
SPI0_D1  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
IO  
IO  
IO  
IO  
IO  
AF13  
AG11  
AD11  
AE13  
AD13  
SPI Data 1  
表6-41. MCSPI1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI1_CLK  
SPI1_CS0  
SPI1_CS1  
SPI1_CS2  
SPI1_CS3  
SPI1_D0  
SPI Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AH12  
AD12  
AG12  
AD18  
AH18  
AE12  
AF12  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
SPI1_D1  
SPI Data 1  
表6-42. MCSPI2 Signal Descriptions  
PIN TYPE  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI2_CLK  
SPI2_CS0  
SPI2_CS1  
SPI2_CS2  
SPI2_CS3  
SPI2_D0  
SPI Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AE23  
AD23  
AF26  
AH25  
AF24  
AD22  
AC21  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
SPI2_D1  
SPI Data 1  
表6-43. MCSPI3 Signal Descriptions  
PIN TYPE  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI3_CLK  
SPI3_CS0  
SPI3_CS1  
SPI3_CS2  
SPI3_CS3  
SPI3_D0  
SPI Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
Y27  
W28  
V26  
U25  
Y28  
Y26  
W26  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
SPI3_D1  
SPI Data 1  
6.3.16.2 MCU Domain  
表6-44. MCSPI0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_SPI0_CLK  
MCU_SPI0_CS0  
MCU_SPI0_CS1  
MCU_SPI0_CS2  
SPI Clock  
IO  
IO  
IO  
IO  
Y1  
Y4  
P1  
N3  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
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表6-44. MCSPI0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
MCU_SPI0_CS3  
DESCRIPTION [2]  
BALL [4]  
[3]  
SPI Chip Select 3  
SPI Data 0  
IO  
IO  
IO  
AC3  
Y3  
MCU_SPI0_D0  
MCU_SPI0_D1  
SPI Data 1  
Y2  
表6-45. MCSPI1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_SPI1_CLK  
MCU_SPI1_CS0  
MCU_SPI1_CS1  
MCU_SPI1_CS2  
MCU_SPI1_CS3  
MCU_SPI1_D0  
MCU_SPI1_D1  
SPI Clock  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AF4  
AD1  
P4  
SPI Chip Select 0  
SPI Chip Select 1  
SPI Chip Select 2  
SPI Chip Select 3  
SPI Data 0  
P5  
AD3  
AF3  
AE3  
SPI Data 1  
6.3.17 MMCSD  
6.3.17.1 MAIN Domain  
表6-46. MMCSD0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME[1]  
DESCRIPTION[2]  
BALL [4]  
[3]  
MMC0_CLK(1) (2)  
MMC0_CMD(1) (2)  
MMC0_DS  
MMC/SD Clock  
MMC/SD Command  
MMC Data Strobe  
SD Card Detect (active low)  
SD Write Protect  
MMC/SD Data  
O
IO  
I
B25  
B27  
C25  
A23  
B23  
A26  
E25  
C26  
A25  
E24  
A24  
B26  
D25  
MMC0_SDCD  
I
MMC0_SDWP  
MMC0_DAT0(1) (2)  
MMC0_DAT1(1) (2)  
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
MMC/SD Data  
(2)  
MMC0_DAT2(1)  
MMC/SD Data  
MMC0_DAT3(1) (2)  
MMC0_DAT4(1) (2)  
MMC0_DAT5(1) (2)  
MMC0_DAT6(1) (2)  
MMC0_DAT7(1) (2)  
MMC/SD Data  
MMC/SD Data  
MMC/SD Data  
MMC/SD Data  
MMC/SD Data  
(1) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due  
to the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This  
internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is  
secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus  
width. Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for  
eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting.  
(2) Each of these signals should have an external 50kΩpull-up resistor connected to the corresponding power supply.  
表6-47. MMCSD1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
MMC1_CLK(1) (2)  
DESCRIPTION [2]  
BALL [4]  
[3]  
O
IO  
I
MMC/SD Clock  
C27  
C28  
B24  
MMC1_CMD(1) (2)  
MMC/SD Command  
MMC1_SDCD  
SD Card Detect (active low)  
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表6-47. MMCSD1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MMC1_SDWP  
SD Write Protect  
MMC/SD Data  
MMC/SD Data  
MMC/SD Data  
MMC/SD Data  
I
C24  
D28  
E27  
D26  
D27  
MMC1_DAT0(1) (2)  
MMC1_DAT1(1) (2)  
MMC1_DAT2(1) (2)  
MMC1_DAT3(1) (2)  
IO  
IO  
IO  
IO  
(1) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due  
to the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This  
internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is  
secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus  
width. Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for  
eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting.  
(2) Each of these signals should have an external 50kΩpull-up resistor connected to the corresponding power supply.  
6.3.18 CPTS  
Note  
Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals  
are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input  
signals are sent to the peripherals while output signals are sourced from the peripherals. For more  
information, see the Time Sync and Compare Events section in the Time Sync chapter in the device  
TRM.  
6.3.18.1 MCU Domain  
表6-48. CPTS0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
MCU_CPTS0_RFT_CLK  
DESCRIPTION [2]  
CPTS Reference Clock  
BALL [4]  
AB3  
[3]  
I
CPTS Time Stamp Counter Compare from  
MCU_CPSW0_CPTS0  
MCU_CPTS0_TS_COMP  
MCU_CPTS0_TS_SYNC  
MCU_CPTS0_HW1TSPUSH  
MCU_CPTS0_HW2TSPUSH  
O
O
I
AB4  
CPTS Time Stamp Counter Bit from  
MCU_CPSW0_CPTS0  
AC5  
AC2  
AC1  
CPTS Hardware Time Stamp Push 1 input to Time Sync  
Router and MCU_CPSW0_CPTS0  
CPTS Hardware Time Stamp Push 2 input to Time Sync  
Router and MCU_CPSW0_CPTS0  
I
6.3.18.2 MAIN Domain  
表6-49. CPTS0 Signal Descriptions  
DESCRIPTION [2]  
PIN TYPE  
SIGNAL NAME [1]  
CPTS0_RFT_CLK  
BALL [4]  
D21  
[3]  
CPTS Reference Clock  
I
CPTS Time Stamp Counter Compare from  
NAVSS0_CPTS0  
CPTS0_TS_COMP  
O
O
I
AF13  
AG12  
B21  
CPTS0_TS_SYNC  
CPTS Time Stamp Counter Bit from NAVSS0_CPTS0  
CPTS Hardware Time Stamp Push 1 input to Time Sync  
Router  
CPTS0_HW1TSPUSH  
CPTS Hardware Time Stamp Push 2 input to Time Sync  
Router  
CPTS0_HW2TSPUSH  
SYNC0_OUT  
I
E21  
D21  
CPTS Time Stamp Generator Bit 0 from Time Sync  
Router  
O
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表6-49. CPTS0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
A22  
[3]  
CPTS Time Stamp Generator Bit 1 from Time Sync  
Router  
SYNC1_OUT  
SYNC2_OUT  
SYNC3_OUT  
O
O
O
CPTS Time Stamp Generator Bit 2 from Time Sync  
Router  
AE18  
CPTS Time Stamp Generator Bit 3 from Time Sync  
Router  
AH17  
6.3.19 OLDI  
6.3.19.1 MAIN Domain  
表6-50. OLDI0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
OLDI0_CLKN  
OLDI0_CLKP  
OLDI0_A0N  
OLDI0_A0P  
OLDI0_A1N  
OLDI0_A1P  
OLDI0_A2N  
OLDI0_A2P  
OLDI0_A3N  
OLDI0_A3P  
OLDI Differential Clock (negative)  
OLDI Differential Clock (positive)  
OLDI Differential Data (negative)  
OLDI Differential Data (positive)  
OLDI Differential Data (negative)  
OLDI Differential Data (positive)  
OLDI Differential Data (negative)  
OLDI Differential Data (positive)  
OLDI Differential Data (negative)  
OLDI Differential Data (positive)  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
L25  
K25  
J28  
K28  
L27  
K27  
K24  
J24  
J26  
K26  
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6.3.20 OSPI  
6.3.20.1 MCU Domain  
表6-51. OSPI0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_OSPI0_CLK  
MCU_OSPI0_DQS  
MCU_OSPI0_LBCLKO  
MCU_OSPI0_CSn0  
MCU_OSPI0_CSn1  
MCU_OSPI0_CSn2  
MCU_OSPI0_CSn3  
MCU_OSPI0_D0  
MCU_OSPI0_D1  
MCU_OSPI0_D2  
MCU_OSPI0_D3  
MCU_OSPI0_D4  
MCU_OSPI0_D5  
MCU_OSPI0_D6  
MCU_OSPI0_D7  
OSPI Clock  
O
I
V1  
U2  
U1  
R4  
R5  
R1  
P2  
U4  
U5  
T2  
T3  
T4  
T5  
R2  
R3  
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Chip Select 2 (active low)  
OSPI Chip Select 3 (active low)  
OSPI Data 0  
IO  
O
O
O
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
OSPI Data 1  
OSPI Data 2  
OSPI Data 3  
OSPI Data 4  
OSPI Data 5  
OSPI Data 6  
OSPI Data 7  
表6-52. OSPI1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_OSPI1_CLK  
MCU_OSPI1_DQS  
MCU_OSPI1_LBCLKO  
MCU_OSPI1_CSn0  
MCU_OSPI1_CSn1  
MCU_OSPI1_D0  
MCU_OSPI1_D1  
MCU_OSPI1_D2  
MCU_OSPI1_D3  
OSPI Clock  
O
I
T1  
P2  
R1  
N2  
N3  
P3  
P4  
P5  
P1  
OSPI Data Strobe (DQS) or Loopback Clock Input  
OSPI Loopback Clock Output  
OSPI Chip Select 0 (active low)  
OSPI Chip Select 1 (active low)  
OSPI Data 0  
IO  
O
O
IO  
IO  
IO  
IO  
OSPI Data 1  
OSPI Data 2  
OSPI Data 3  
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6.3.21 PRU_ICSSG  
6.3.21.1 MAIN Domain  
Note  
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU  
GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in  
the device TRM.  
表6-53. PRU_ICSSG0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRU_ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Ouput  
PRG0_ECAP0_IN_APWM_OUT  
IO  
V25  
PRG0_ECAP0_SYNC_IN  
PRU_ICSSG ECAP Sync Input  
I
U27  
U26  
PRG0_ECAP0_SYNC_OUT  
PRG0_IEP0_EDIO_OUTVALID  
PRU_ICSSG ECAP Sync Output  
O
O
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
AD12  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRG0_IEP0_EDC_LATCH_IN0  
PRG0_IEP0_EDC_LATCH_IN1  
PRG0_IEP0_EDC_SYNC_OUT0  
PRG0_IEP0_EDC_SYNC_OUT1  
PRG0_IEP0_EDIO_DATA_IN_OUT28  
PRG0_IEP0_EDIO_DATA_IN_OUT29  
PRG0_IEP0_EDIO_DATA_IN_OUT30  
PRG0_IEP0_EDIO_DATA_IN_OUT31  
PRG0_IEP1_EDC_LATCH_IN0  
PRG0_IEP1_EDC_LATCH_IN1  
PRG0_IEP1_EDC_SYNC_OUT0  
PRG0_IEP1_EDC_SYNC_OUT1  
I
V25  
U27  
U24  
U26  
V26  
U25  
Y28  
AA28  
Y26  
W28  
W26  
Y27  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
O
IO  
IO  
IO  
IO  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
PRG0_MDIO0_MDC  
PRG0_MDIO0_MDIO  
PRG0_PRU0_GPI0  
PRG0_PRU0_GPI1  
PRG0_PRU0_GPI2  
PRG0_PRU0_GPI3  
PRG0_PRU0_GPI4  
PRG0_PRU0_GPI5  
PRG0_PRU0_GPI6  
PRG0_PRU0_GPI7  
PRG0_PRU0_GPI8  
PRG0_PRU0_GPI9  
PRU_ICSSG MDIO Clock  
O
AE28  
AE26  
V24  
PRU_ICSSG MDIO Data  
IO  
I
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
I
W25  
W24  
AA27  
Y24  
I
I
I
I
V28  
I
Y25  
I
U27  
V27  
I
I
V26  
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表6-53. PRU_ICSSG0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
PRU_ICSSG PRU Data Input  
BALL [4]  
[3]  
PRG0_PRU0_GPI10  
PRG0_PRU0_GPI11  
PRG0_PRU0_GPI12  
PRG0_PRU0_GPI13  
PRG0_PRU0_GPI14  
PRG0_PRU0_GPI15  
PRG0_PRU0_GPI16  
PRG0_PRU0_GPI17  
PRG0_PRU0_GPI18  
PRG0_PRU0_GPI19  
PRG0_PRU0_GPO0  
PRG0_PRU0_GPO1  
PRG0_PRU0_GPO2  
PRG0_PRU0_GPO3  
PRG0_PRU0_GPO4  
PRG0_PRU0_GPO5  
PRG0_PRU0_GPO6  
PRG0_PRU0_GPO7  
PRG0_PRU0_GPO8  
PRG0_PRU0_GPO9  
PRG0_PRU0_GPO10  
PRG0_PRU0_GPO11  
PRG0_PRU0_GPO12  
PRG0_PRU0_GPO13  
PRG0_PRU0_GPO14  
PRG0_PRU0_GPO15  
PRG0_PRU0_GPO16  
PRG0_PRU0_GPO17  
PRG0_PRU0_GPO18  
PRG0_PRU0_GPO19  
PRG0_PRU1_GPI0  
PRG0_PRU1_GPI1  
PRG0_PRU1_GPI2  
PRG0_PRU1_GPI3  
PRG0_PRU1_GPI4  
PRG0_PRU1_GPI5  
PRG0_PRU1_GPI6  
PRG0_PRU1_GPI7  
PRG0_PRU1_GPI8  
PRG0_PRU1_GPI9  
PRG0_PRU1_GPI10  
PRG0_PRU1_GPI11  
PRG0_PRU1_GPI12  
PRG0_PRU1_GPI13  
PRG0_PRU1_GPI14  
I
I
U25  
AB25  
AD27  
AC26  
AD26  
AA24  
AD28  
U26  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
I
I
I
I
I
I
I
V25  
I
U24  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
V24  
W25  
W24  
AA27  
Y24  
V28  
Y25  
U27  
V27  
V26  
U25  
AB25, AD27  
AC26, AD27  
AC26, AD26  
AA24, AD26  
AA24, AB25  
AD28  
U26  
V25  
U24  
AB28  
AC28  
AC27  
AB26  
AA25  
U23  
I
I
I
I
I
I
AB27  
W28  
I
I
W27  
I
Y28  
I
AA28  
AB24  
AC25  
AD25  
AD24  
I
I
I
I
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表6-53. PRU_ICSSG0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
PRG0_PRU1_GPI15  
DESCRIPTION [2]  
PRU_ICSSG PRU Data Input  
BALL [4]  
[3]  
I
AE27  
AC24  
Y27  
PRG0_PRU1_GPI16  
PRG0_PRU1_GPI17  
PRG0_PRU1_GPI18  
PRG0_PRU1_GPI19  
PRG0_PRU1_GPO0  
PRG0_PRU1_GPO1  
PRG0_PRU1_GPO2  
PRG0_PRU1_GPO3  
PRG0_PRU1_GPO4  
PRG0_PRU1_GPO5  
PRG0_PRU1_GPO6  
PRG0_PRU1_GPO7  
PRG0_PRU1_GPO8  
PRG0_PRU1_GPO9  
PRG0_PRU1_GPO10  
PRG0_PRU1_GPO11  
PRG0_PRU1_GPO12  
PRG0_PRU1_GPO13  
PRG0_PRU1_GPO14  
PRG0_PRU1_GPO15  
PRG0_PRU1_GPO16  
PRG0_PRU1_GPO17  
PRG0_PRU1_GPO18  
PRG0_PRU1_GPO19  
PRG0_PWM0_TZ_IN  
PRG0_PWM0_TZ_OUT  
PRG0_PWM1_TZ_IN  
PRG0_PWM1_TZ_OUT  
PRG0_PWM2_TZ_IN  
PRG0_PWM2_TZ_OUT  
PRG0_PWM3_TZ_IN  
PRG0_PWM3_TZ_OUT  
PRG0_PWM0_A0  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
I
I
I
Y26  
I
W26  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
AB28  
AC28  
AC27  
AB26  
AA25  
U23  
AB27  
W28  
W27  
Y28  
AA28  
AB24, AC25  
AC25, AD25  
AD24, AD25  
AD24, AE27  
AB24, AE27  
AC24  
Y27  
Y26  
W26  
V25  
O
U24  
I
Y26  
O
W26  
I
AA28  
W27  
O
I
V26  
O
AB25  
AD27  
AD26  
AD28  
AC26  
AA24  
U26  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
PRG0_PWM0_A1  
PRG0_PWM0_A2  
PRG0_PWM0_B0  
PRG0_PWM0_B1  
PRG0_PWM0_B2  
PRG0_PWM1_A0  
AC25  
AD24  
AC24  
AD25  
AE27  
Y27  
PRG0_PWM1_A1  
PRG0_PWM1_A2  
PRG0_PWM1_B0  
PRG0_PWM1_B1  
PRG0_PWM1_B2  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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表6-53. PRU_ICSSG0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
PRU_ICSSG PWM Output A  
BALL [4]  
[3]  
PRG0_PWM2_A0  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
W24  
V27  
PRG0_PWM2_A1  
PRU_ICSSG PWM Output A  
PRG0_PWM2_A2  
PRU_ICSSG PWM Output A  
AC27  
Y24  
PRG0_PWM2_B0  
PRU_ICSSG PWM Output B  
PRG0_PWM2_B1  
PRU_ICSSG PWM Output B  
U25  
PRG0_PWM2_B2  
PRU_ICSSG PWM Output B  
AA25  
V24  
PRG0_PWM3_A0  
PRU_ICSSG PWM Output A  
PRG0_PWM3_A1  
PRU_ICSSG PWM Output A  
Y25  
PRG0_PWM3_A2  
PRU_ICSSG PWM Output A  
AA27  
W25  
U27  
PRG0_PWM3_B0  
PRU_ICSSG PWM Output B  
PRG0_PWM3_B1  
PRU_ICSSG PWM Output B  
PRG0_PWM3_B2  
PRU_ICSSG PWM Output B  
V28  
PRG0_RGMII1_RXC  
PRG0_RGMII1_RX_CTL  
PRG0_RGMII1_TXC  
PRG0_RGMII1_TX_CTL  
PRG0_RGMII2_RXC  
PRG0_RGMII2_RX_CTL  
PRG0_RGMII2_TXC  
PRG0_RGMII2_TX_CTL  
PRG0_RGMII1_RD0  
PRG0_RGMII1_RD1  
PRG0_RGMII1_RD2  
PRG0_RGMII1_RD3  
PRG0_RGMII1_TD0  
PRG0_RGMII1_TD1  
PRG0_RGMII1_TD2  
PRG0_RGMII1_TD3  
PRG0_RGMII2_RD0  
PRG0_RGMII2_RD1  
PRG0_RGMII2_RD2  
PRG0_RGMII2_RD3  
PRG0_RGMII2_TD0  
PRG0_RGMII2_TD1  
PRG0_RGMII2_TD2  
PRG0_RGMII2_TD3  
PRG0_UART0_CTSn  
PRG0_UART0_RTSn  
PRG0_UART0_RXD  
PRG0_UART0_TXD  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG UART Clear to Send (active low)  
PRU_ICSSG UART Request to Send (active low)  
PRU_ICSSG UART Receive Data  
PRU_ICSSG UART Transmit Data  
Y25  
I
Y24  
IO  
O
I
AD28  
AB25  
AB27  
AA25  
AC24  
AB24  
V24  
I
IO  
O
I
I
W25  
W24  
AA27  
AD27  
AC26  
AD26  
AA24  
AB28  
AC28  
AC27  
AB26  
AC25  
AD25  
AD24  
AE27  
V26  
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
U25  
Y28  
O
AA28  
表6-54. PRU_ICSSG1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRU_ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Ouput  
PRG1_ECAP0_IN_APWM_OUT  
IO  
AC21  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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表6-54. PRU_ICSSG1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
PRG1_ECAP0_SYNC_IN  
DESCRIPTION [2]  
PRU_ICSSG ECAP Sync Input  
BALL [4]  
[3]  
I
AD22  
AE23  
AF13  
PRG1_ECAP0_SYNC_OUT  
PRU_ICSSG ECAP Sync Output  
O
O
PRG1_IEP0_EDIO_OUTVALID  
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRG1_IEP0_EDC_LATCH_IN0  
PRG1_IEP0_EDC_LATCH_IN1  
PRG1_IEP0_EDC_SYNC_OUT0  
PRG1_IEP0_EDC_SYNC_OUT1  
PRG1_IEP0_EDIO_DATA_IN_OUT28  
PRG1_IEP0_EDIO_DATA_IN_OUT29  
PRG1_IEP0_EDIO_DATA_IN_OUT30  
PRG1_IEP0_EDIO_DATA_IN_OUT31  
PRG1_IEP1_EDC_LATCH_IN0  
PRG1_IEP1_EDC_LATCH_IN1  
PRG1_IEP1_EDC_SYNC_OUT0  
PRG1_IEP1_EDC_SYNC_OUT1  
I
AG25  
AG27  
AG26  
AH26  
AF26  
AH25  
AF25  
AF24  
AD22  
AD23  
AC21  
AE23  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
O
IO  
IO  
IO  
IO  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
I
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
O
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
PRG1_MDIO0_MDC  
PRG1_MDIO0_MDIO  
PRG1_PRU0_GPI0  
PRG1_PRU0_GPI1  
PRG1_PRU0_GPI2  
PRG1_PRU0_GPI3  
PRG1_PRU0_GPI4  
PRG1_PRU0_GPI5  
PRG1_PRU0_GPI6  
PRG1_PRU0_GPI7  
PRG1_PRU0_GPI8  
PRG1_PRU0_GPI9  
PRG1_PRU0_GPI10  
PRG1_PRU0_GPI11  
PRG1_PRU0_GPI12  
PRG1_PRU0_GPI13  
PRG1_PRU0_GPI14  
PRG1_PRU0_GPI15  
PRG1_PRU0_GPI16  
PRG1_PRU0_GPI17  
PRG1_PRU0_GPI18  
PRU_ICSSG MDIO Clock  
O
IO  
I
AH18  
AD18  
AE22  
AG24  
AF23  
AD21  
AG23  
AF27  
AF22  
AG27  
AF28  
AF26  
AH25  
AF21  
AH20  
AH21  
AG20  
AD19  
AD20  
AH26  
AG25  
PRU_ICSSG MDIO Data  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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表6-54. PRU_ICSSG1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
PRU_ICSSG PRU Data Input  
BALL [4]  
[3]  
PRG1_PRU0_GPI19  
PRG1_PRU0_GPO0  
PRG1_PRU0_GPO1  
PRG1_PRU0_GPO2  
PRG1_PRU0_GPO3  
PRG1_PRU0_GPO4  
PRG1_PRU0_GPO5  
PRG1_PRU0_GPO6  
PRG1_PRU0_GPO7  
PRG1_PRU0_GPO8  
PRG1_PRU0_GPO9  
PRG1_PRU0_GPO10  
PRG1_PRU0_GPO11  
PRG1_PRU0_GPO12  
PRG1_PRU0_GPO13  
PRG1_PRU0_GPO14  
PRG1_PRU0_GPO15  
PRG1_PRU0_GPO16  
PRG1_PRU0_GPO17  
PRG1_PRU0_GPO18  
PRG1_PRU0_GPO19  
PRG1_PRU1_GPI0  
PRG1_PRU1_GPI1  
PRG1_PRU1_GPI2  
PRG1_PRU1_GPI3  
PRG1_PRU1_GPI4  
PRG1_PRU1_GPI5  
PRG1_PRU1_GPI6  
PRG1_PRU1_GPI7  
PRG1_PRU1_GPI8  
PRG1_PRU1_GPI9  
PRG1_PRU1_GPI10  
PRG1_PRU1_GPI11  
PRG1_PRU1_GPI12  
PRG1_PRU1_GPI13  
PRG1_PRU1_GPI14  
PRG1_PRU1_GPI15  
PRG1_PRU1_GPI16  
PRG1_PRU1_GPI17  
PRG1_PRU1_GPI18  
PRG1_PRU1_GPI19  
PRG1_PRU1_GPO0  
PRG1_PRU1_GPO1  
PRG1_PRU1_GPO2  
PRG1_PRU1_GPO3  
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
AG26  
AE22  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
AG24  
AF23  
AD21  
AG23  
AF27  
AF22  
AG27  
AF28  
AF26  
AH25  
AF21, AH20  
AH20, AH21  
AG20, AH21  
AD19, AG20  
AD19, AF21  
AD20  
AH26  
AG25  
AG26  
AH24  
I
AH23  
I
AG21  
I
AH22  
I
AE21  
I
AC22  
I
AG22  
I
AD23  
I
AE24  
I
AF25  
I
AF24  
I
AC20  
I
AE20  
I
AF19  
I
AH19  
I
AG19  
I
AE19  
I
AE23  
I
AD22  
I
AC21  
IO  
IO  
IO  
IO  
AH24  
AH23  
AG21  
AH22  
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ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
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表6-54. PRU_ICSSG1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
PRG1_PRU1_GPO4  
DESCRIPTION [2]  
PRU_ICSSG PRU Data Output  
BALL [4]  
[3]  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
AE21  
AC22  
PRG1_PRU1_GPO5  
PRG1_PRU1_GPO6  
PRG1_PRU1_GPO7  
PRG1_PRU1_GPO8  
PRG1_PRU1_GPO9  
PRG1_PRU1_GPO10  
PRG1_PRU1_GPO11  
PRG1_PRU1_GPO12  
PRG1_PRU1_GPO13  
PRG1_PRU1_GPO14  
PRG1_PRU1_GPO15  
PRG1_PRU1_GPO16  
PRG1_PRU1_GPO17  
PRG1_PRU1_GPO18  
PRG1_PRU1_GPO19  
PRG1_PWM0_TZ_IN  
PRG1_PWM0_TZ_OUT  
PRG1_PWM1_TZ_IN  
PRG1_PWM1_TZ_OUT  
PRG1_PWM2_TZ_IN  
PRG1_PWM2_TZ_OUT  
PRG1_PWM3_TZ_IN  
PRG1_PWM3_TZ_OUT  
PRG1_PWM0_A0  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output B  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
PRU_ICSSG PWM Output A  
AG22  
AD23  
AE24  
AF25  
AF24  
AC20, AE20  
AE20, AF19  
AF19, AH19  
AG19, AH19  
AC20, AG19  
AE19  
AE23  
AD22  
AC21  
AG25  
O
AG26  
I
AD22  
O
AC21  
I
AF24  
O
AE24  
I
AF26  
O
AF21  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AH20  
PRG1_PWM0_A1  
AG20  
PRG1_PWM0_A2  
AD20  
PRG1_PWM0_B0  
AH21  
PRG1_PWM0_B1  
AD19  
PRG1_PWM0_B2  
AH26  
PRG1_PWM1_A0  
AE20  
PRG1_PWM1_A1  
AH19  
PRG1_PWM1_A2  
AE19  
PRG1_PWM1_B0  
AF19  
PRG1_PWM1_B1  
AG19  
PRG1_PWM1_B2  
AE23  
PRG1_PWM2_A0  
AF23  
PRG1_PWM2_A1  
AF28  
PRG1_PWM2_A2  
AG21  
PRG1_PWM2_B0  
AG23  
PRG1_PWM2_B1  
AH25  
PRG1_PWM2_B2  
AE21  
PRG1_PWM3_A0  
AE22  
PRG1_PWM3_A1  
AF22  
PRG1_PWM3_A2  
AD21  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-54. PRU_ICSSG1 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
PRU_ICSSG PWM Output B  
BALL [4]  
[3]  
PRG1_PWM3_B0  
IO  
IO  
IO  
I
AG24  
AG27  
AF27  
AF22  
AG23  
AD20  
AF21  
AG22  
AE21  
AE19  
AC20  
AE22  
AG24  
AF23  
AD21  
AH20  
AH21  
AG20  
AD19  
AH24  
AH23  
AG21  
AH22  
AE20  
AF19  
AH19  
AG19  
AF26  
AH25  
AF25  
AF24  
PRG1_PWM3_B1  
PRU_ICSSG PWM Output B  
PRG1_PWM3_B2  
PRU_ICSSG PWM Output B  
PRG1_RGMII1_RXC  
PRG1_RGMII1_RX_CTL  
PRG1_RGMII1_TXC  
PRG1_RGMII1_TX_CTL  
PRG1_RGMII2_RXC  
PRG1_RGMII2_RX_CTL  
PRG1_RGMII2_TXC  
PRG1_RGMII2_TX_CTL  
PRG1_RGMII1_RD0  
PRG1_RGMII1_RD1  
PRG1_RGMII1_RD2  
PRG1_RGMII1_RD3  
PRG1_RGMII1_TD0  
PRG1_RGMII1_TD1  
PRG1_RGMII1_TD2  
PRG1_RGMII1_TD3  
PRG1_RGMII2_RD0  
PRG1_RGMII2_RD1  
PRG1_RGMII2_RD2  
PRG1_RGMII2_RD3  
PRG1_RGMII2_TD0  
PRG1_RGMII2_TD1  
PRG1_RGMII2_TD2  
PRG1_RGMII2_TD3  
PRG1_UART0_CTSn  
PRG1_UART0_RTSn  
PRG1_UART0_RXD  
PRG1_UART0_TXD  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG UART Clear to Send (active low)  
PRU_ICSSG UART Request to Send (active low)  
PRU_ICSSG UART Receive Data  
PRU_ICSSG UART Transmit Data  
I
IO  
O
I
I
IO  
O
I
I
I
I
O
O
O
O
I
I
I
I
O
O
O
O
I
O
I
O
表6-55. PRU_ICSSG2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRU_ICSSG Enhanced Capture (ECAP) Input or  
Auxiliary PWM (APWM) Ouput  
PRG2_ECAP0_IN_APWM_OUT  
IO  
AE16  
PRG2_ECAP0_SYNC_IN  
PRU_ICSSG ECAP Sync Input  
I
AD14  
AG14  
A23  
PRG2_ECAP0_SYNC_OUT  
PRG2_IEP0_EDIO_OUTVALID  
PRU_ICSSG ECAP Sync Output  
O
O(1)  
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRG2_IEP0_EDC_LATCH_IN0  
PRG2_IEP0_EDC_LATCH_IN1  
PRG2_IEP0_EDC_SYNC_OUT0  
I
I
AD12  
AE12  
AH12  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
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表6-55. PRU_ICSSG2 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
PRG2_IEP0_EDC_SYNC_OUT1  
PRG2_IEP0_EDIO_DATA_IN_OUT28  
PRG2_IEP0_EDIO_DATA_IN_OUT29  
PRG2_IEP0_EDIO_DATA_IN_OUT30  
PRG2_IEP0_EDIO_DATA_IN_OUT31  
PRG2_IEP1_EDC_LATCH_IN0  
PRG2_IEP1_EDC_LATCH_IN1  
PRG2_IEP1_EDC_SYNC_OUT0  
PRG2_IEP1_EDC_SYNC_OUT1  
DESCRIPTION [2]  
BALL [4]  
AF12  
R23  
[3]  
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
IO  
IO  
IO  
IO  
I
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
T24  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
R25  
PRU_ICSSG Industrial Ethernet Digital I/O Data Input/  
Output  
T27  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
R23  
PRU_ICSSG Industrial Ethernet Distributed Clock Latch  
Input  
I
R25  
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
O
O
T24  
PRU_ICSSG Industrial Ethernet Distributed Clock Sync  
Output  
T27  
PRG2_MDIO0_MDC  
PRG2_MDIO0_MDIO  
PRG2_PRU0_GPI0  
PRG2_PRU0_GPI1  
PRG2_PRU0_GPI2  
PRG2_PRU0_GPI3  
PRG2_PRU0_GPI4  
PRG2_PRU0_GPI5  
PRG2_PRU0_GPI6  
PRG2_PRU0_GPI7  
PRG2_PRU0_GPI8  
PRG2_PRU0_GPI9  
PRG2_PRU0_GPI10  
PRG2_PRU0_GPI11  
PRG2_PRU0_GPI12  
PRG2_PRU0_GPI13  
PRG2_PRU0_GPI14  
PRG2_PRU0_GPI15  
PRG2_PRU0_GPI16  
PRG2_PRU0_GPI17  
PRG2_PRU0_GPO0  
PRG2_PRU0_GPO1  
PRG2_PRU0_GPO2  
PRG2_PRU0_GPO3  
PRG2_PRU0_GPO4  
PRG2_PRU0_GPO5  
PRG2_PRU0_GPO6  
PRG2_PRU0_GPO7  
PRG2_PRU0_GPO8  
PRU_ICSSG MDIO Clock  
O
AE15  
AC19  
AF18  
AE18  
AH17  
AG18  
AG17  
AF17  
AE17  
AC19  
AH16  
AG16  
AF16  
AE16  
N23  
PRU_ICSSG MDIO Data  
IO  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
M26  
I
P28  
I
P27  
I
AD16  
P23  
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AF18  
AE18  
AH17  
AG18  
AG17  
AF17  
AE17  
AC19  
AH16  
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表6-55. PRU_ICSSG2 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
PRU_ICSSG PRU Data Output  
BALL [4]  
[3]  
PRG2_PRU0_GPO9  
PRG2_PRU0_GPO10  
PRG2_PRU0_GPO11  
PRG2_PRU0_GPO12  
PRG2_PRU0_GPO13  
PRG2_PRU0_GPO14  
PRG2_PRU0_GPO15  
PRG2_PRU0_GPO16  
PRG2_PRU0_GPO17  
PRG2_PRU1_GPI0  
PRG2_PRU1_GPI1  
PRG2_PRU1_GPI2  
PRG2_PRU1_GPI3  
PRG2_PRU1_GPI4  
PRG2_PRU1_GPI5  
PRG2_PRU1_GPI6  
PRG2_PRU1_GPI7  
PRG2_PRU1_GPI8  
PRG2_PRU1_GPI9  
PRG2_PRU1_GPI10  
PRG2_PRU1_GPI11  
PRG2_PRU1_GPI12  
PRG2_PRU1_GPI13  
PRG2_PRU1_GPI14  
PRG2_PRU1_GPI15  
PRG2_PRU1_GPI16  
PRG2_PRU1_GPI17  
PRG2_PRU1_GPO0  
PRG2_PRU1_GPO1  
PRG2_PRU1_GPO2  
PRG2_PRU1_GPO3  
PRG2_PRU1_GPO4  
PRG2_PRU1_GPO5  
PRG2_PRU1_GPO6  
PRG2_PRU1_GPO7  
PRG2_PRU1_GPO8  
PRG2_PRU1_GPO9  
PRG2_PRU1_GPO10  
PRG2_PRU1_GPO11  
PRG2_PRU1_GPO12  
PRG2_PRU1_GPO13  
PRG2_PRU1_GPO14  
PRG2_PRU1_GPO15  
PRG2_PRU1_GPO16  
PRG2_PRU1_GPO17  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
AG16  
AF16  
AE16  
N23  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Input  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
PRU_ICSSG PRU Data Output  
M26  
P28  
P27  
AD16  
P23  
AH15  
AC16  
AD17  
AH14  
AG14  
AG15  
AC17  
AE15  
AD15  
AF14  
AC15  
AD14  
N26  
I
I
I
I
I
I
I
I
I
I
I
I
I
N25  
I
P24  
I
R27  
I
AE14  
T23  
I
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
AH15  
AC16  
AD17  
AH14  
AG14  
AG15  
AC17  
AE15  
AD15  
AF14  
AC15  
AD14  
N26  
N25  
P24  
R27  
AE14  
T23  
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表6-55. PRU_ICSSG2 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
PRG2_PWM0_TZ_IN  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Trip Zone Input  
PRU_ICSSG PWM Trip Zone Output  
PRU_ICSSG PWM Output A  
I
P28  
P24  
PRG2_PWM0_TZ_OUT  
PRG2_PWM1_TZ_IN  
PRG2_PWM1_TZ_OUT  
PRG2_PWM2_TZ_IN  
PRG2_PWM2_TZ_OUT  
PRG2_PWM3_TZ_IN  
PRG2_PWM3_TZ_OUT  
PRG2_PWM0_A0  
O
I
F18  
O
I
AE14  
P23  
O
I
T23  
AE15  
AF14  
AG17  
AD16  
AD15  
AH16  
AD17  
AC15  
R23  
O
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
IO  
I
PRG2_PWM0_A1  
PRU_ICSSG PWM Output A  
PRG2_PWM0_A2  
PRU_ICSSG PWM Output A  
PRG2_PWM0_B0  
PRU_ICSSG PWM Output B  
PRG2_PWM0_B1  
PRU_ICSSG PWM Output B  
PRG2_PWM0_B2  
PRU_ICSSG PWM Output B  
PRG2_PWM1_A0  
PRU_ICSSG PWM Output A  
PRG2_PWM1_A1  
PRU_ICSSG PWM Output A  
AD18  
AE26  
T24  
PRG2_PWM1_A2  
PRU_ICSSG PWM Output A  
PRG2_PWM1_B0  
PRU_ICSSG PWM Output B  
PRG2_PWM1_B1  
PRU_ICSSG PWM Output B  
AH18  
AE28  
N23  
PRG2_PWM1_B2  
PRU_ICSSG PWM Output B  
PRG2_PWM2_A0  
PRU_ICSSG PWM Output A  
PRG2_PWM2_A1  
PRU_ICSSG PWM Output A  
P27  
PRG2_PWM2_A2  
PRU_ICSSG PWM Output A  
N25  
PRG2_PWM2_B0  
PRU_ICSSG PWM Output B  
M26  
PRG2_PWM2_B1  
PRU_ICSSG PWM Output B  
N26  
PRG2_PWM2_B2  
PRU_ICSSG PWM Output B  
R27  
PRG2_PWM3_A0  
PRU_ICSSG PWM Output A  
AF18  
AF17  
AH15  
AG18  
AE17  
AC16  
AF17  
AG17  
AD16  
AE17  
AG15  
AG14  
AE14  
AC17  
AF18  
AE18  
AH17  
AG18  
AH16  
PRG2_PWM3_A1  
PRU_ICSSG PWM Output A  
PRG2_PWM3_A2  
PRU_ICSSG PWM Output A  
PRG2_PWM3_B0  
PRU_ICSSG PWM Output B  
PRG2_PWM3_B1  
PRU_ICSSG PWM Output B  
PRG2_PWM3_B2  
PRU_ICSSG PWM Output B  
PRG2_RGMII1_RXC  
PRG2_RGMII1_RX_CTL  
PRG2_RGMII1_TXC  
PRG2_RGMII1_TX_CTL  
PRG2_RGMII2_RXC  
PRG2_RGMII2_RX_CTL  
PRG2_RGMII2_TXC  
PRG2_RGMII2_TX_CTL  
PRG2_RGMII1_RD0  
PRG2_RGMII1_RD1  
PRG2_RGMII1_RD2  
PRG2_RGMII1_RD3  
PRG2_RGMII1_TD0  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Clock  
PRU_ICSSG RGMII Receive Control  
PRU_ICSSG RGMII Transmit Clock  
PRU_ICSSG RGMII Transmit Control  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
I
IO  
O
I
I
IO  
O
I
I
I
I
O
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表6-55. PRU_ICSSG2 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
PRG2_RGMII1_TD1  
PRG2_RGMII1_TD2  
PRG2_RGMII1_TD3  
PRG2_RGMII2_RD0  
PRG2_RGMII2_RD1  
PRG2_RGMII2_RD2  
PRG2_RGMII2_RD3  
PRG2_RGMII2_TD0  
PRG2_RGMII2_TD1  
PRG2_RGMII2_TD2  
PRG2_RGMII2_TD3  
PRG2_UART0_CTSn  
PRG2_UART0_RTSn  
PRG2_UART0_RXD  
PRG2_UART0_TXD  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Receive Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG RGMII Transmit Data  
PRU_ICSSG UART Clear to Send (active low)  
PRU_ICSSG UART Request to Send (active low)  
PRU_ICSSG UART Receive Data  
PRU_ICSSG UART Transmit Data  
O
O
O
I
AG16  
AF16  
AE16  
AH15  
AC16  
AD17  
AH14  
AD15  
AF14  
AC15  
AD14  
AD12  
AH12  
AE12  
AF12  
I
I
I
O
O
O
O
I
O
I
O
(1) When OSC1 is being used with an external crystal, this signal is unavailable. The output functionality must be disabled.  
6.3.22 SERDES  
6.3.22.1 MAIN Domain  
表6-56. SERDES0 Signal Descriptions  
see (1)  
PIN TYPE  
SIGNAL NAME [1]  
SERDES0_REFCLKN  
DESCRIPTION [2]  
SERDES Clock Input (negative)  
BALL [4]  
[3]  
I
AG5  
AG6  
AC9  
AH3  
AG2  
AH4  
AG3  
SERDES0_REFCLKP  
SERDES0_REFRES  
SERDES0_RXN  
SERDES0_RXP  
SERDES Clock Input (positive)  
SERDES Reference Resistor(2)  
I
A
I
SERDES Differential Receive Data (negative)  
SERDES Differential Receive Data (positive)  
SERDES Differential Transmit Data (negative)  
SERDES Differential Transmit Data (positive)  
I
SERDES0_TXN  
O
O
SERDES0_TXP  
(1) The functionality of these pins is controlled by CTRLMMR_SERDES0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = USB3, 0x1 = PCIe0  
Lane0, 0x2 = ICSS2 SGMII Lane0.  
(2) The required resistor value is 3kΩ ±1%.  
表6-57. SERDES1 Signal Descriptions  
see (1)  
PIN TYPE  
SIGNAL NAME [1]  
SERDES1_REFCLKN  
DESCRIPTION [2]  
SERDES Clock Input (negative)  
BALL [4]  
[3]  
I
AH6  
AH7  
SERDES1_REFCLKP  
SERDES1_REFRES  
SERDES1_RXN  
SERDES Clock Input (positive)  
SERDES Reference Resistor(2)  
I
A
I
AC14  
AG9  
AH10  
AH9  
SERDES Differential Receive Data (negative)  
SERDES Differential Receive Data (positive)  
SERDES Differential Transmit Data (negative)  
SERDES1_RXP  
I
SERDES1_TXN  
O
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表6-57. SERDES1 Signal Descriptions (continued)  
see (1)  
PIN TYPE  
SIGNAL NAME [1]  
SERDES1_TXP  
DESCRIPTION [2]  
BALL [4]  
[3]  
SERDES Differential Transmit Data (positive)  
O
AG8  
(1) The functionality of these pins is controlled by CTRLMMR_SERDES1_CTRL[1:0] LANE_FUNC_SEL. 0x0 = PCIe1 Lane0, 0x1 =  
PCIe0 Lane1, 0x2 = ICSS2 SGMII Lane1.  
6.3.23 UART  
6.3.23.1 MAIN Domain  
表6-58. UART0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
UART0_CTSn  
DESCRIPTION [2]  
UART Clear to Send (active low)  
BALL [4]  
[3]  
I
AG11  
D25  
UART0_DCDn  
UART0_DSRn  
UART0_DTRn  
UART0_RIN  
UART Data Carrier Detect (active low)  
UART Data Set Ready (active low)  
UART Data Terminal Ready (active low)  
UART Ring Indicator  
I
I
B26  
O
I
A24  
E24  
UART0_RTSn  
UART0_RXD  
UART0_TXD  
UART Request to Send (active low)  
UART Receive Data  
O
I
AD11  
AF11  
AE11  
UART Transmit Data  
O
表6-59. UART1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
UART1_CTSn  
UART1_RTSn  
UART1_RXD  
UART1_TXD  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
I
AD22  
AC21  
AE23  
AD23  
O
I
UART Transmit Data  
O
表6-60. UART2 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
UART2_CTSn  
UART2_RTSn  
UART2_RXD  
UART2_TXD  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
I
Y26  
W26  
Y27  
W28  
O
I
UART Transmit Data  
O
6.3.23.2 MCU Domain  
表6-61. UART0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_UART0_CTSn  
MCU_UART0_RTSn  
MCU_UART0_RXD  
MCU_UART0_TXD  
UART Clear to Send (active low)  
UART Request to Send (active low)  
UART Receive Data  
I
P1  
N3  
P4  
P5  
O
I
UART Transmit Data  
O
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6.3.23.3 WKUP Domain  
表6-62. UART0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
UART Clear to Send (active low)  
BALL [4]  
[3]  
WKUP_UART0_CTSn  
WKUP_UART0_RTSn  
WKUP_UART0_RXD  
WKUP_UART0_TXD  
I
AC2  
AC1  
AB1  
AB5  
UART Request to Send (active low)  
UART Receive Data  
O
I
UART Transmit Data  
O
6.3.24 USB  
6.3.24.1 MAIN Domain  
表6-63. USB0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
USB0_DM  
USB 2.0 Differential Data (negative)  
USB 2.0 Differential Data (positive)  
USB VBUS control output (active high)  
USB 2.0 Dual-Role Device Role Select  
USB Level-shifted VBUS Input  
IO  
IO  
O
A
AE2  
AF1  
AD9  
AF7  
AE7  
USB0_DP  
USB0_DRVVBUS  
USB0_ID  
USB0_VBUS(1)  
A
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.2.3, USB Design  
Guidelines.  
表6-64. USB1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
IO  
IO  
O
USB1_DM  
USB1_DP  
USB 2.0 Differential Data (negative)  
USB 2.0 Differential Data (positive)  
USB VBUS control output (active high)  
USB 2.0 Dual-Role Device Role Select  
USB Level-shifted VBUS Input  
AD2  
AE1  
AC8  
AF5  
AF6  
USB1_DRVVBUS  
USB1_ID  
USB1_VBUS(1)  
A
A
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see 节9.2.3, USB Design  
Guidelines.  
6.3.25 Emulation and Debug  
6.3.25.1 MAIN Domain  
表6-65. Emulation and Debug 0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
IO  
IO  
I
EMU0  
Emulation Control 0  
Emulation Control 1  
AA2  
AA1  
EMU1  
TCK  
JTAG Test Clock Input  
JTAG Test Data Input  
JTAG Test Data Output  
JTAG Test Mode Select Input  
JTAG Reset  
AA4  
TDI  
I
C20  
TDO  
OZ  
I
A20  
TMS  
A21  
TRSTn  
TRC_CLK  
TRC_CTL  
TRC_DATA0  
TRC_DATA1  
I
AA3  
Trace Clock  
O
O
O
O
AF18  
AE18  
AH17  
AG18  
Trace Control  
Trace Data 0  
Trace Data 1  
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表6-65. Emulation and Debug 0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
TRC_DATA2  
TRC_DATA3  
TRC_DATA4  
TRC_DATA5  
TRC_DATA6  
TRC_DATA7  
TRC_DATA8  
TRC_DATA9  
Trace Data 2  
Trace Data 3  
Trace Data 4  
Trace Data 5  
Trace Data 6  
Trace Data 7  
Trace Data 8  
Trace Data 9  
Trace Data 10  
Trace Data 11  
Trace Data 12  
Trace Data 13  
Trace Data 14  
Trace Data 15  
Trace Data 16  
Trace Data 17  
Trace Data 18  
Trace Data 19  
Trace Data 20  
Trace Data 21  
Trace Data 22  
Trace Data 23  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AG17  
AF17  
AE17  
AC19  
AH16  
AG16  
AF16  
AE16  
AD16  
AH15  
AC16  
AD17  
AH14  
AG14  
AG15  
AC17  
AE15  
AD15  
AF14  
AC15  
AD14  
AE14  
TRC_DATA10  
TRC_DATA11  
TRC_DATA12  
TRC_DATA13  
TRC_DATA14  
TRC_DATA15  
TRC_DATA16  
TRC_DATA17  
TRC_DATA18  
TRC_DATA19  
TRC_DATA20  
TRC_DATA21  
TRC_DATA22  
TRC_DATA23  
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6.3.26 System and Miscellaneous  
6.3.26.1 Boot Mode Configuration  
6.3.26.1.1 MAIN Domain  
表6-66. Sysboot Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
BOOTMODE00  
BOOTMODE01  
BOOTMODE02  
BOOTMODE03  
BOOTMODE04  
BOOTMODE05  
BOOTMODE06  
BOOTMODE07  
BOOTMODE08  
BOOTMODE09  
BOOTMODE10  
BOOTMODE11  
BOOTMODE12  
BOOTMODE13  
BOOTMODE14  
BOOTMODE15  
BOOTMODE16  
BOOTMODE17  
BOOTMODE18  
Bootmode pin 00  
Bootmode pin 01  
Bootmode pin 02  
Bootmode pin 03  
Bootmode pin 04  
Bootmode pin 05  
Bootmode pin 06  
Bootmode pin 07  
Bootmode pin 08  
Bootmode pin 09  
Bootmode pin 10  
Bootmode pin 11  
Bootmode pin 12  
Bootmode pin 13  
Bootmode pin 14  
Bootmode pin 15  
Bootmode pin 16  
Bootmode pin 17  
Bootmode pin 18  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
M27  
M23  
M28  
M24  
N24  
N27  
N28  
M25  
N23  
M26  
P28  
P27  
N26  
N25  
P24  
R27  
P25  
P26  
U28  
6.3.26.1.2 MCU Domain  
表6-67. Sysboot Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU_BOOTMODE00  
MCU_BOOTMODE01  
MCU_BOOTMODE02  
MCU_BOOTMODE03(1)  
MCU_BOOTMODE04(1)  
MCU_BOOTMODE05(1)  
MCU_BOOTMODE06(1)  
MCU_BOOTMODE07(1)  
MCU_BOOTMODE08(1)  
MCU_BOOTMODE09  
Bootmode pin 00  
Bootmode pin 01  
Bootmode pin 02  
Bootmode pin 03  
Bootmode pin 04  
Bootmode pin 05  
Bootmode pin 06  
Bootmode pin 07  
Bootmode pin 08  
Bootmode pin 09  
I
I
I
I
I
I
I
I
I
I
AF4  
AF3  
AE3  
AD1  
AC3  
Y2  
Y1  
Y3  
AC5  
AB4  
(1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low  
level.  
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6.3.26.2 Clock  
6.3.26.2.1 MAIN Domain  
表6-68. Clock1 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
High frequency oscillator input  
BALL [4]  
[3]  
OSC1_XI  
I
C22  
E22  
OSC1_XO  
High frequency oscillator output  
O
6.3.26.2.2 WKUP Domain  
表6-69. Clock0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
WKUP_LFOSC0_XI  
WKUP_LFOSC0_XO  
WKUP_OSC0_XI  
Low frequency (32.768 kHz) oscillator input  
Low frequency (32.768 kHz) oscillator output  
High frequency oscillator input  
I
AE4  
AC4  
AD5  
AE6  
O
I
WKUP_OSC0_XO  
High frequency oscillator output  
O
6.3.26.3 System  
6.3.26.3.1 MAIN Domain  
表6-70. System0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
External clock input to Main Domain, routed to Timer  
clock muxes as one of the selectable input clock sources  
for Timer/WDT modules, or as reference clock to  
MAIN_PLL2 (PER1 PLL)  
EXT_REFCLK1  
I
A22  
GPMC functional clock output selected through a mux  
logic  
GPMC0_FCLK_MUX  
NMIn  
O
I
R28  
F18  
C23  
External Interrupt  
Observation clock output for test and debug purposes  
only  
OBSCLK0  
O
PORz  
Main Domain cold reset  
I
E19  
C19  
AF9  
AF10  
AE8  
AE9  
D19  
F17  
PORz_OUT  
REFCLK0N  
REFCLK0P  
REFCLK1N  
REFCLK1P  
RESETSTATz  
RESETz  
Main Domain POR status output  
O
O
O
O
O
O
I
SERDES Differential Clock Output (negative)  
SERDES Differential Clock Output (positive)  
SERDES Differential Clock Output (negative)  
SERDES Differential Clock Output (positive)  
Main Domain warm reset status output  
Main Domain warm reset  
SOC_SAFETY_ERRORn  
Error signal output from Main Domain ESM  
IO  
E20  
SYSCLK0 output from Main PLL controller (divided by 4)  
for test and debug purposes only  
SYSCLKOUT0  
O
B22  
6.3.26.3.2 WKUP Domain  
表6-71. System0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
MCU Bypass reset circuitry input. 0 = Internal POR is  
used, 1 = External MCU_PORz signal is used.  
MCU_BYP_POR  
I
V5  
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表6-71. System0 Signal Descriptions (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
Reference clock output for Ethernet PHYs (50MHz or  
25MHz)  
MCU_CLKOUT0  
O
I
AB2  
AB3  
AB2  
MCU_EXT_REFCLK0  
MCU_OBSCLK0  
External system clock input  
Observation clock output for test and debug purposes  
only  
O
MCU_PORz  
MCU Domain cold reset  
I
O
O
I
W5  
V2  
MCU_PORz_OUT  
MCU_RESETSTATz  
MCU_RESETz  
MCU Domain POR status output  
MCU Domain warm reset status output  
MCU Domain warm reset  
V3  
W4  
W3  
MCU_SAFETY_ERRORn  
Error signal output from MCU Domain ESM  
IO  
MCU Domain system clock output (divided by 4) for test  
and debug purposes only  
MCU_SYSCLKOUT0  
O
AB3  
PMIC_POWER_EN0  
PMIC_POWER_EN1  
Power enable output for MAIN Domain supplies  
Power enable output for MAIN Domain supplies  
O
O
Y5  
AA5  
6.3.26.4 Miscellaneous  
6.3.26.4.1 WKUP Domain  
表6-72. Miscellaneous0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
TEMP_DIODE_P(1)  
Reserved  
A
W6  
(1) Do not connect any signal, test point, or board trace to this signal.  
6.3.26.5 EFUSE  
6.3.26.5.1 MAIN Domain  
表6-73. EFUSE0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
VPP_CORE(1)  
DESCRIPTION [2]  
BALL [4]  
[3]  
Programming voltage for MAIN Domain efuses  
PWR  
F21  
(1) This signal is valid only for High-Security devices. For more details, see 节7.7, VPP Specification for One-Time Programmable (OTP)  
eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.  
6.3.26.5.2 MCU Domain  
表6-74. EFUSE0 Signal Descriptions  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
VPP_MCU(1)  
Programming voltage for MCU Domain efuses  
PWR  
T6  
(1) This signal is valid only for High-Security devices. For more details, see 节7.7, VPP Specification for One-Time Programmable (OTP)  
eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.  
6.3.27 Power Supply  
表6-75. Power Supply Signal Description  
PIN TYPE  
SIGNAL NAME [1]  
CAP_VDDAR_CORE0(1)  
DESCRIPTION [2]  
BALL [4]  
[3]  
External capacitor connection for CORE SRAM LDOs  
External capacitor connection for CORE SRAM LDOs  
External capacitor connection for CORE SRAM LDOs  
CAP  
CAP  
CAP  
P17  
V17  
W16  
CAP_VDDAR_CORE1(1)  
CAP_VDDAR_CORE2(1)  
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表6-75. Power Supply Signal Description (continued)  
PIN TYPE  
SIGNAL NAME [1]  
CAP_VDDAR_CORE3(1)  
DESCRIPTION [2]  
BALL [4]  
[3]  
External capacitor connection for MSMC SRAM LDOs  
External capacitor connection for MSMC SRAM LDOs  
External capacitor connection for MCU SRAM LDO  
External capacitor connection for MPU SRAM LDOs  
External capacitor connection for MPU SRAM LDOs  
External capacitor connection for MPU SRAM LDOs  
External capacitor connection for MPU SRAM LDOs  
External capacitor connection for WKUP SRAM LDO  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
CAP  
M14  
L15  
U10  
M12  
N12  
N18  
N15  
Y10  
CAP_VDDAR_CORE4(1)  
CAP_VDDAR_MCU(1)  
CAP_VDDAR_MPU0_0(1)  
CAP_VDDAR_MPU0_1(1)  
CAP_VDDAR_MPU1_0(1)  
CAP_VDDAR_MPU1_1(1)  
CAP_VDDAR_WKUP(1)  
External capacitor connection for IO Bias LDO in WKUP  
domain  
CAP_VDDA_1P8_IOLDO_WKUP(1)  
CAP  
AA8  
CAP_VDDA_1P8_SDIO(2)  
CAP_VDDA_1P8_IOLDO0(1)  
CAP_VDDA_1P8_IOLDO1(1)  
CAP_VDDSHV_SDIO(2) (3)  
CAP_VDD_WKUP(1)  
VDDA_1P8_MON_WKUP  
VDDA_1P8_SDIO(2)  
External capacitor connection for SDIO LDO  
External capacitor connection for IO Bias LDO  
External capacitor connection for IO Bias LDO  
External capacitor connection for SDIO LDO  
External capacitor connection for WKUP LDO  
Supply monitor in WKUP domain  
CAP  
CAP  
CAP  
CAP  
CAP  
A
J17  
G19  
Y19  
H18  
V9  
AB6  
SDIO LDO analog power supply  
PWR  
PWR  
A
G17  
VDDA_1P8_CSI0  
CSI PHY analog power supply  
L20, M21  
AC6  
VDDA_1P8_MON0  
Supply monitor in MAIN domain  
VDDA_1P8_OLDI0  
OLDI analog power supply  
PWR  
PWR  
PWR  
A
L22  
VDDA_1P8_SERDES0  
VDDA_3P3_IOLDO_WKUP  
VDDA_3P3_MON_WKUP  
VDDA_3P3_SDIO(2)  
SERDES0/1 (USB, PCIE) analog power supply  
WKUP IO Bias LDO analog power supply  
Supply monitor in WKUP domain  
AA14, AB13, AB15  
AB9  
U6  
SDIO LDO analog power supply  
PWR  
PWR  
PWR  
PWR  
A
H17  
VDDA_3P3_USB  
USB analog power supply  
AC12  
G18  
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
VDDA_3P3_MON0  
IO Bias LDO analog power supply  
IO Bias LDO analog power supply  
Supply monitor in MAIN domain  
AA21  
AC10  
M7, M9  
AB8  
VDDA_ADC_MCU  
ADC0, ADC1 analog power supply  
WKUP LDO analog power supply  
PWR  
PWR  
VDDA_LDO_WKUP  
MCU SRAM LDO, MCU DPLL, CPSW DPLL analog  
power supply  
VDDA_MCU  
PWR  
U12  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_PLL_CORE  
VDDA_PLL_DSS  
DDR DPLL analog power supply  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
A
H15  
H11  
Y17  
L21  
L12  
K15  
AB7  
Y9  
DDR De-skew DPLL analog power supply  
CORE DPLL, PER1 DPLL analog power supply  
DSS DPLL analog power supply  
VDDA_PLL_MPU0  
VDDA_PLL_MPU1  
VDDA_PLL_PER0  
VDDA_POR_WKUP(5)  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
VDDA_SRAM_MPU0  
VDDA_SRAM_MPU1  
VDDA_VSYS_MON(6)  
MPU0 DPLL analog power supply  
MPU1 DPLL analog power supply  
PER0 DPLL analog power supply  
WKUP POR/POK analog power supply  
CORE SRAM LDOs analog power supply  
CORE SRAM LDOs analog power supply  
MPU SRAM LDOs analog power supply  
MPU SRAM LDOs analog power supply  
Supply monitor for system  
M19  
V16  
K7  
L18  
AC11  
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表6-75. Power Supply Signal Description (continued)  
PIN TYPE  
SIGNAL NAME [1]  
DESCRIPTION [2]  
BALL [4]  
[3]  
WKUP High/Low Frequency Oscillator  
(WKUP_LFOSC0 / WKUP_OSC0), SRAM LDO analog  
power supply  
VDDA_WKUP  
PWR  
AA9  
VDDS0  
IO bias supply for VDDSHV0  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
G12  
V8  
VDDS0_WKUP  
VDDS1  
IO bias supply for VDDSHV0_WKUP  
IO bias supply for VDDSHV1  
AA16  
VDDS1_WKUP  
VDDS2  
IO bias supply for VDDSHV1_WKUP  
IO bias supply for VDDSHV2  
T9  
P20  
VDDS2_WKUP  
VDDS3  
IO bias supply for VDDSHV2_WKUP  
IO bias supply for VDDSHV3  
N8  
T20  
VDDS4  
IO bias supply for VDDSHV4  
Y20  
VDDS5  
IO bias supply for VDDSHV5  
AC18  
VDDS6  
IO bias supply for VDDSHV6  
F20  
VDDS7  
IO bias supply for VDDSHV7  
K20  
VDDS8  
IO bias supply for VDDSHV8  
AA10  
VDDSHV0  
VDDSHV0_WKUP  
VDDSHV1  
VDDSHV1_WKUP  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
G15, H16  
U8, V7, W8, Y7  
AA18, AB17  
R6, R8, T7  
N20, N22, P21, R20,  
R22  
VDDSHV2  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
PWR  
PWR  
PWR  
VDDSHV2_WKUP  
VDDSHV3  
N6, P7, P9  
T21, U20, U22, V21,  
V23  
AA22, W20, W22,  
Y21, Y23  
VDDSHV4  
VDDSHV5  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
PWR  
PWR  
AA20, AB19, AB21,  
AB23  
VDDSHV6  
VDDSHV7  
VDDSHV8  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
Dual-voltage IO domain power supply  
PWR  
PWR  
PWR  
G20, H19, H21  
J20, J22, K21  
AB11  
G10, G14, G8, H13,  
H7, H9  
VDDS_DDR  
DDR IO domain power supply  
PWR  
PWR  
MAIN High Frequency Oscillator (OSC1) analog power  
supply  
VDDS_OSC1  
J16  
AA12, J10, J12, J14,  
J19, J8, K13, L14,  
L19, M13, N14, P13,  
P15, P19, R14, R16,  
R18, T13, T15, T17,  
T19, U14, U16, U18,  
V13, V15, V19, W14,  
W18, Y11, Y13, Y15  
VDD_CORE  
CORE voltage domain supply  
PWR  
VDD_DLL_MMC0  
VDD_DLL_MMC1  
MMC0 PHY DLL voltage supply  
MMC1 PHY DLL voltage supply  
PWR  
PWR  
G22  
H23  
N10, P11, R10, R12,  
T11  
VDD_MCU  
VDD_MPU0  
VDD_MPU1  
MCU voltage domain supply  
MPU0 voltage domain supply  
MPU1 voltage domain supply  
PWR  
PWR  
PWR  
K11, K9, L10, L8, M11  
K16, K18, L17, M16,  
M18, N17  
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表6-75. Power Supply Signal Description (continued)  
PIN TYPE  
SIGNAL NAME [1]  
VDD_WKUP0(4)  
VDD_WKUP1(4)  
DESCRIPTION [2]  
BALL [4]  
[3]  
WKUP voltage domain supply  
WKUP voltage domain supply  
PWR  
PWR  
V11, W10, W12  
M22  
A1, A2, A28, AA11,  
AA13, AA15, AA17,  
AA19, AA23, AA26,  
AA7, AB10, AB12,  
AB14, AB16, AB18,  
AB20, AB22, AD4,  
AE10, AE25, AE5,  
AF15, AF2, AF20,  
AF8, AG1, AG10,  
AG28, AG4, AG7,  
AH1, AH11, AH2,  
AH27, AH28, AH5,  
AH8, B12, B15, B20,  
B6, B9, D22, E26,  
E28, E4, F14, F19,  
F22, F25, F27, F3,  
G11, G13, G16, G2,  
G21, G23, G7, G9,  
H1, H10, H12, H14,  
H20, H22, H24, H26,  
H28, H6, H8, J11,  
J13, J15, J18, J21,  
J23, J25, J27, J7, J9,  
K1, K10, K12, K14,  
K17, K19, K22, K23,  
K6, K8, L11, L13,  
VSS  
Ground  
GND  
L16, L23, L24, L26,  
L28, L3, L7, L9, M10,  
M15, M17, M20, M8,  
N11, N13, N16, N19,  
N21, N7, N9, P10,  
P12, P14, P16, P18,  
P22, P6, P8, R11,  
R13, R15, R17, R19,  
R21, R7, R9, T10,  
T12, T14, T16, T18,  
T22, T26, T8, U11,  
U13, U15, U17, U19,  
U21, U3, U7, U9,  
V10, V12, V14, V18,  
V20, V22, V6, W11,  
W13, W15, W17,  
W19, W21, W23, W7,  
W9, Y12, Y14, Y16,  
Y18, Y22, Y6, Y8  
(1) This pin must always be connected via a 1-µF capacitor to VSS.  
(2) The net connecting CAP_VDDA_1P8_SDIO and VDDA_1P8_SDIO to VDDS6 or VDDS7 must be connected to a 3.3-uF decoupling  
capacitor. VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be connected to VSS,  
when SDIO_LDO is not used with either MMC0 or MMC1.  
(3) When CAP_VDDSHV_SDIO is connected to VDDSHV6 or VDDSHV7, the entire net which connects these pins should not exceed 6-  
uF of decoupling capacitance. VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be  
connected to VSS, when SDIO_LDO is not used with either MMC0 or MMC1.  
(4) These power rails should be connected together on the board level.  
(5) VDDA_POR_WKUP is preferred to be connected to CAP_VDDA_1P8_IOLDO_WKUP when using internal POR feature.  
(6) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the  
appropriate resistor voltage divider source. For more information, see 节9.2.5, System Power Supply Monitor Design Guidelines.  
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6.4 Pin Multiplexing  
表6-76 describes the device pin multiplexing associated with pins.  
Note  
Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins.  
Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are  
associated with peripheral logic functions.  
表 6-76, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see  
section Pad Configuration Registers in the device TRM. Refer to the respective peripheral chapter in the device TRM for information  
associated with peripheral signal multiplexing.  
Note  
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.  
Note  
表 6-76, Pin Multiplexing does not include SerDes signal functions. For more information, see section Serializer/Deserializer (SerDes) in the  
device TRM.  
Note  
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal  
wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.  
For more information on the I/O cell configurations, see section Pad Configuration Registers in the device TRM.  
表6-76. Pin Multiplexing  
MUXMODE[7:0] SETTINGS  
BALL  
ADDRESS  
REGISTER NAME  
NUMBER  
M27  
0
1
2
3
4
5
6
7
Bootstrap  
BOOTMODE00  
BOOTMODE01  
BOOTMODE02  
BOOTMODE03  
BOOTMODE04  
BOOTMODE05  
BOOTMODE06  
BOOTMODE07  
0x0011C000 CTRLMMR_PADCONFIG0  
0x0011C004 CTRLMMR_PADCONFIG1  
0x0011C008 CTRLMMR_PADCONFIG2  
0x0011C00C CTRLMMR_PADCONFIG3  
0x0011C010 CTRLMMR_PADCONFIG4  
0x0011C014 CTRLMMR_PADCONFIG5  
0x0011C018 CTRLMMR_PADCONFIG6  
0x0011C01C CTRLMMR_PADCONFIG7  
GPMC0_AD0  
GPMC0_AD1  
GPMC0_AD2  
GPMC0_AD3  
GPMC0_AD4  
GPMC0_AD5  
GPMC0_AD6  
GPMC0_AD7  
VOUT1_DATA0  
VOUT1_DATA1  
VOUT1_DATA2  
VOUT1_DATA3  
VOUT1_DATA4  
VOUT1_DATA5  
VOUT1_DATA6  
VOUT1_DATA7  
VIN0_DATA12  
VIN0_DATA13  
VIN0_DATA14  
VIN0_DATA15  
GPIO0_0  
M23  
M28  
M24  
N24  
N27  
N28  
M25  
GPIO0_1  
GPIO0_2  
GPIO0_3  
GPIO0_4  
GPIO0_5  
GPIO0_6  
GPIO0_7  
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C020 CTRLMMR_PADCONFIG8  
0x0011C024 CTRLMMR_PADCONFIG9  
0x0011C028 CTRLMMR_PADCONFIG10  
0x0011C02C CTRLMMR_PADCONFIG11  
0x0011C030 CTRLMMR_PADCONFIG12  
0x0011C034 CTRLMMR_PADCONFIG13  
0x0011C038 CTRLMMR_PADCONFIG14  
0x0011C03C CTRLMMR_PADCONFIG15  
0x0011C040 CTRLMMR_PADCONFIG16  
0x0011C044 CTRLMMR_PADCONFIG17  
N23  
GPMC0_AD8  
VOUT1_DATA8  
VIN0_DATA0  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_PWM2_A0  
12 12  
GPIO0_8  
BOOTMODE08  
M26  
P28  
P27  
N26  
N25  
P24  
R27  
R28  
P25  
GPMC0_AD9  
GPMC0_AD10  
GPMC0_AD11  
GPMC0_AD12  
GPMC0_AD13  
GPMC0_AD14  
GPMC0_AD15  
GPMC0_CLK  
VOUT1_DATA9  
VOUT1_DATA10  
VOUT1_DATA11  
VOUT1_DATA12  
VOUT1_DATA13  
VOUT1_DATA14  
VOUT1_DATA15  
VOUT1_DATA16  
VIN0_DATA1  
VIN0_DATA2  
VIN0_DATA3  
VIN0_DATA4  
VIN0_DATA5  
VIN0_DATA6  
VIN0_DATA7  
VIN0_PCLK  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_PWM2_B0  
13 13  
GPIO0_9  
BOOTMODE09  
BOOTMODE10  
BOOTMODE11  
BOOTMODE12  
BOOTMODE13  
BOOTMODE14  
BOOTMODE15  
PRG2_PRU0_GPO PRG2_PRU0_GPI  
14 14  
PRG2_PWM0_TZ_ GPIO0_10  
IN  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_PWM2_A1  
15 15  
GPIO0_11  
GPIO0_12  
GPIO0_13  
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_PWM2_B1  
12 12  
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_PWM2_A2  
13 13  
PRG2_PRU1_GPO PRG2_PRU1_GPI  
14 14  
PRG2_PWM0_TZ_ GPIO0_14  
OUT  
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_PWM2_B2  
GPIO0_15  
GPIO0_16  
GPIO0_17  
15  
15  
GPMC0_FCLK_MU  
X
GPMC0_ADVn_AL VOUT1_DATA17  
E
BOOTMODE16  
0x0011C048 CTRLMMR_PADCONFIG18  
0x0011C04C CTRLMMR_PADCONFIG19  
0x0011C050 CTRLMMR_PADCONFIG20  
P26  
U28  
T28  
GPMC0_OEn_REn VOUT1_DATA18  
GPIO0_18  
GPIO0_19  
GPIO0_20  
BOOTMODE17  
BOOTMODE18  
GPMC0_WEn  
VOUT1_DATA19  
GPMC0_BE0n_CL VOUT1_DATA20  
E
0x0011C054 CTRLMMR_PADCONFIG21  
P23  
GPMC0_BE1n  
VOUT1_DATA21  
VIN0_HD  
PRG2_PRU0_GPO PRG2_PRU0_GPI TIMER_IO2  
17 17  
PRG2_PWM2_TZ_ GPIO0_21  
IN  
0x0011C058 CTRLMMR_PADCONFIG22  
0x0011C05C CTRLMMR_PADCONFIG23  
R26  
R23  
GPMC0_WAIT0  
GPMC0_WAIT1  
VOUT1_DATA22  
VOUT1_DATA23  
GPIO0_22  
VIN0_VD  
PRG2_PWM1_A0 PRG2_IEP1_EDC_ TIMER_IO3  
LATCH_IN0  
PRG2_IEP0_EDIO GPIO0_23  
_DATA_IN_OUT28  
0x0011C060 CTRLMMR_PADCONFIG24  
0x0011C064 CTRLMMR_PADCONFIG25  
T25  
T24  
GPMC0_WPn  
GPMC0_DIR  
VOUT1_VSYNC  
VOUT1_HSYNC  
GPIO0_24  
VIN0_DATA8  
VIN0_DATA9  
PRG2_PWM1_B0 PRG2_IEP1_EDC_ TIMER_IO6  
SYNC_OUT0  
PRG2_IEP0_EDIO GPIO0_25  
_DATA_IN_OUT29  
0x0011C068 CTRLMMR_PADCONFIG26  
0x0011C06C CTRLMMR_PADCONFIG27  
R24  
T23  
GPMC0_CSn0  
GPMC0_CSn1  
VOUT1_PCLK  
VOUT1_DE  
GPIO0_26  
PRG2_PRU1_GPO PRG2_PRU1_GPI TIMER_IO7  
PRG2_PWM2_TZ_ GPIO0_27  
OUT  
17  
17  
0x0011C070 CTRLMMR_PADCONFIG28  
0x0011C074 CTRLMMR_PADCONFIG29  
0x0011C078 CTRLMMR_PADCONFIG30  
0x0011C07C CTRLMMR_PADCONFIG31  
0x0011C080 CTRLMMR_PADCONFIG32  
R25  
GPMC0_CSn2  
GPMC0_CSn3  
VOUT1_EXTPCLKI VIN0_DATA10  
N
GPMC0_A27  
PRG2_IEP1_EDC_ I2C2_SDA  
LATCH_IN1  
PRG2_IEP0_EDIO GPIO0_28  
_DATA_IN_OUT30  
T27  
VIN0_DATA11  
GPMC0_A26  
PRG2_IEP1_EDC_ I2C2_SCL  
SYNC_OUT1  
PRG2_IEP0_EDIO GPIO0_29  
_DATA_IN_OUT31  
AF18  
AE18  
AH17  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RD GPMC0_A25  
0
TRC_CLK  
TRC_CTL  
TRC_DATA0  
EHRPWM0_SYNCI PRG2_PWM3_A0 GPIO0_30  
0
0
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RD GPMC0_A24  
1
EHRPWM0_SYNC SYNC2_OUT  
O
GPIO0_31  
GPIO0_32  
1
1
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RD GPMC0_A23  
2
EHRPWM_TZn_IN SYNC3_OUT  
0
2
2
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C084 CTRLMMR_PADCONFIG33  
0x0011C088 CTRLMMR_PADCONFIG34  
0x0011C08C CTRLMMR_PADCONFIG35  
0x0011C090 CTRLMMR_PADCONFIG36  
0x0011C094 CTRLMMR_PADCONFIG37  
0x0011C098 CTRLMMR_PADCONFIG38  
0x0011C09C CTRLMMR_PADCONFIG39  
0x0011C0A0 CTRLMMR_PADCONFIG40  
0x0011C0A4 CTRLMMR_PADCONFIG41  
0x0011C0A8 CTRLMMR_PADCONFIG42  
0x0011C0AC CTRLMMR_PADCONFIG43  
0x0011C0B0 CTRLMMR_PADCONFIG44  
0x0011C0B4 CTRLMMR_PADCONFIG45  
0x0011C0B8 CTRLMMR_PADCONFIG46  
0x0011C0BC CTRLMMR_PADCONFIG47  
0x0011C0C0 CTRLMMR_PADCONFIG48  
0x0011C0C4 CTRLMMR_PADCONFIG49  
0x0011C0C8 CTRLMMR_PADCONFIG50  
AG18  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RD GPMC0_A22  
TRC_DATA1  
TRC_DATA2  
TRC_DATA3  
TRC_DATA4  
TRC_DATA5  
TRC_DATA6  
TRC_DATA7  
TRC_DATA8  
TRC_DATA9  
TRC_DATA10  
TRC_DATA11  
TRC_DATA12  
TRC_DATA13  
TRC_DATA14  
TRC_DATA15  
TRC_DATA16  
TRC_DATA17  
TRC_DATA18  
TRC_DATA19  
TRC_DATA20  
TRC_DATA21  
TRC_DATA22  
TRC_DATA23  
EHRPWM0_A  
PRG2_PWM3_B0 GPIO0_33  
PRG2_PWM0_A0 GPIO0_34  
PRG2_PWM3_A1 GPIO0_35  
PRG2_PWM3_B1 GPIO0_36  
3
3
3
AG17  
AF17  
AE17  
AC19  
AH16  
AG16  
AF16  
AE16  
AD16  
AH15  
AC16  
AD17  
AH14  
AG14  
AG15  
AC17  
AE15  
AD15  
AF14  
AC15  
AD14  
AE14  
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RX GPMC0_A21  
_CTL  
EHRPWM0_B  
EHRPWM1_A  
EHRPWM1_B  
4
4
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_RX GPMC0_A20  
5
5
C
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TX GPMC0_A19  
_CTL  
6
6
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_MDIO0_MD GPMC0_A18  
IO  
EHRPWM_TZn_IN EHRPWM_SOCA  
1
GPIO0_37  
7
7
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TD GPMC0_A17  
EHRPWM2_A  
PRG2_PWM0_B0 GPIO0_38  
GPIO0_39  
8
8
0
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TD GPMC0_A16  
EHRPWM2_B  
9
9
1
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TD GPMC0_A15  
10 10  
EHRPWM_TZn_IN EHRPWM_SOCB  
2
GPIO0_40  
2
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TD GPMC0_A14  
11 11  
PRG2_ECAP0_IN_ GPIO0_41  
APWM_OUT  
3
PRG2_PRU0_GPO PRG2_PRU0_GPI PRG2_RGMII1_TX GPMC0_A13  
16 16  
PRG2_PWM0_A1 GPIO0_42  
PRG2_PWM3_A2 GPIO0_43  
PRG2_PWM3_B2 GPIO0_44  
C
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RD GPMC0_A12  
EHRPWM3_A  
EHRPWM3_B  
0
0
0
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RD GPMC0_A11  
1
1
1
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RD GPMC0_A10  
EHRPWM3_SYNCI PRG2_PWM0_B1 GPIO0_45  
2
2
2
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RD GPMC0_A9  
EHRPWM3_SYNC  
O
GPIO0_46  
3
3
3
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RX GPMC0_A8  
_CTL  
EHRPWM_TZn_IN PRG2_ECAP0_SY GPIO0_47  
3
4
4
NC_OUT  
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_RX GPMC0_A7  
EHRPWM4_A  
GPIO0_48  
GPIO0_49  
5
5
C
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TX GPMC0_A6  
_CTL  
EHRPWM4_B  
6
6
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_MDIO0_MD GPMC0_A5  
EHRPWM_TZn_IN PRG2_PWM3_TZ_ GPIO0_50  
4
7
7
C
IN  
0x0011C0C CTRLMMR_PADCONFIG51  
C
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TD GPMC0_A4  
EHRPWM5_A  
PRG2_PWM0_A2 GPIO0_51  
8
8
0
0x0011C0D0 CTRLMMR_PADCONFIG52  
0x0011C0D4 CTRLMMR_PADCONFIG53  
0x0011C0D8 CTRLMMR_PADCONFIG54  
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TD GPMC0_A3  
EHRPWM5_B  
PRG2_PWM3_TZ_ GPIO0_52  
OUT  
9
9
1
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TD GPMC0_A2  
10 10  
EHRPWM_TZn_IN PRG2_PWM0_B2 GPIO0_53  
5
2
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TD GPMC0_A1  
11 11  
PRG2_ECAP0_SY GPIO0_54  
NC_IN  
3
0x0011C0D CTRLMMR_PADCONFIG55  
C
PRG2_PRU1_GPO PRG2_PRU1_GPI PRG2_RGMII2_TX GPMC0_A0  
16 16  
PRG2_PWM1_TZ_ GPIO0_55  
OUT  
C
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C0E0 CTRLMMR_PADCONFIG56  
0x0011C0E4 CTRLMMR_PADCONFIG57  
0x0011C0E8 CTRLMMR_PADCONFIG58  
0x0011C0EC CTRLMMR_PADCONFIG59  
0x0011C0F0 CTRLMMR_PADCONFIG60  
0x0011C0F4 CTRLMMR_PADCONFIG61  
0x0011C0F8 CTRLMMR_PADCONFIG62  
0x0011C0FC CTRLMMR_PADCONFIG63  
0x0011C100 CTRLMMR_PADCONFIG64  
0x0011C104 CTRLMMR_PADCONFIG65  
0x0011C108 CTRLMMR_PADCONFIG66  
0x0011C10C CTRLMMR_PADCONFIG67  
0x0011C110 CTRLMMR_PADCONFIG68  
0x0011C114 CTRLMMR_PADCONFIG69  
0x0011C118 CTRLMMR_PADCONFIG70  
0x0011C11C CTRLMMR_PADCONFIG71  
0x0011C120 CTRLMMR_PADCONFIG72  
0x0011C124 CTRLMMR_PADCONFIG73  
0x0011C128 CTRLMMR_PADCONFIG74  
0x0011C12C CTRLMMR_PADCONFIG75  
0x0011C130 CTRLMMR_PADCONFIG76  
0x0011C134 CTRLMMR_PADCONFIG77  
0x0011C138 CTRLMMR_PADCONFIG78  
AE22  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RD PRG1_PWM3_A0  
GPIO0_56  
0
0
0
AG24  
AF23  
AD21  
AG23  
AF27  
AF22  
AG27  
AF28  
AF26  
AH25  
AF21  
AH20  
AH21  
AG20  
AD19  
AD20  
AH26  
AG25  
AG26  
AH24  
AH23  
AG21  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RD PRG1_PWM3_B0  
GPIO0_57  
GPIO0_58  
GPIO0_59  
GPIO0_60  
GPIO0_61  
GPIO0_62  
GPIO0_63  
GPIO0_64  
1
1
1
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RD PRG1_PWM2_A0  
2
2
2
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RD PRG1_PWM3_A2  
3
3
3
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RX PRG1_PWM2_B0  
_CTL  
4
4
PRG1_PRU0_GPO PRG1_PRU0_GPI  
PRG1_PWM3_B2  
5
5
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_RX PRG1_PWM3_A1  
6
6
C
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_IEP0_EDC_ PRG1_PWM3_B1  
LATCH_IN1  
7
7
PRG1_PRU0_GPO PRG1_PRU0_GPI  
PRG1_PWM2_A1  
8
8
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_UART0_CT PRG1_PWM3_TZ_ SPI2_CS1  
Sn IN  
PRG1_IEP0_EDIO GPIO0_65  
_DATA_IN_OUT28  
9
9
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_UART0_RT PRG1_PWM2_B1 SPI2_CS2  
10 10 Sn  
PRG1_IEP0_EDIO GPIO0_66  
_DATA_IN_OUT29  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TX PRG1_PWM3_TZ_  
11 11 _CTL OUT  
PRG1_PRU0_GPO  
15  
GPIO0_67  
GPIO0_68  
GPIO0_69  
GPIO0_70  
GPIO0_71  
GPIO0_72  
GPIO0_73  
GPIO0_74  
GPIO0_75  
GPIO0_76  
GPIO0_77  
GPIO0_78  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TD PRG1_PWM0_A0  
12 12  
PRG1_PRU0_GPO  
11  
0
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TD PRG1_PWM0_B0  
13 13  
PRG1_PRU0_GPO  
12  
1
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TD PRG1_PWM0_A1  
14 14  
PRG1_PRU0_GPO  
13  
2
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TD PRG1_PWM0_B1  
15 15  
PRG1_PRU0_GPO  
14  
3
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_RGMII1_TX PRG1_PWM0_A2  
16 16  
C
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_IEP0_EDC_ PRG1_PWM0_B2  
17 17 SYNC_OUT1  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_IEP0_EDC_ PRG1_PWM0_TZ_  
18 18 LATCH_IN0 IN  
PRG1_PRU0_GPO PRG1_PRU0_GPI PRG1_IEP0_EDC_ PRG1_PWM0_TZ_  
19 19 SYNC_OUT0 OUT  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RD  
0
0
0
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RD  
1
1
1
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RD PRG1_PWM2_A2  
2
2
2
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C13C CTRLMMR_PADCONFIG79  
0x0011C140 CTRLMMR_PADCONFIG80  
0x0011C144 CTRLMMR_PADCONFIG81  
0x0011C148 CTRLMMR_PADCONFIG82  
0x0011C14C CTRLMMR_PADCONFIG83  
0x0011C150 CTRLMMR_PADCONFIG84  
0x0011C154 CTRLMMR_PADCONFIG85  
0x0011C158 CTRLMMR_PADCONFIG86  
0x0011C15C CTRLMMR_PADCONFIG87  
0x0011C160 CTRLMMR_PADCONFIG88  
0x0011C164 CTRLMMR_PADCONFIG89  
0x0011C168 CTRLMMR_PADCONFIG90  
0x0011C16C CTRLMMR_PADCONFIG91  
0x0011C170 CTRLMMR_PADCONFIG92  
0x0011C174 CTRLMMR_PADCONFIG93  
0x0011C178 CTRLMMR_PADCONFIG94  
0x0011C17C CTRLMMR_PADCONFIG95  
0x0011C180 CTRLMMR_PADCONFIG96  
0x0011C184 CTRLMMR_PADCONFIG97  
AH22  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RD  
EQEP1_A  
GPIO0_79  
3
3
3
AE21  
AC22  
AG22  
AD23  
AE24  
AF25  
AF24  
AC20  
AE20  
AF19  
AH19  
AG19  
AE19  
AE23  
AD22  
AC21  
AD18  
AH18  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RX PRG1_PWM2_B2 EQEP1_B  
_CTL  
GPIO0_80  
GPIO0_81  
GPIO0_82  
GPIO0_83  
GPIO0_84  
4
4
PRG1_PRU1_GPO PRG1_PRU1_GPI  
EQEP1_S  
SPI2_CS0  
5
5
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_RX  
6
6
C
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_IEP1_EDC_  
LATCH_IN1  
UART1_TXD  
7
7
PRG1_PRU1_GPO PRG1_PRU1_GPI  
PRG1_PWM2_TZ_  
OUT  
8
8
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_UART0_RX  
PRG1_IEP0_EDIO GPIO0_85  
_DATA_IN_OUT30  
9
9
D
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_UART0_TX PRG1_PWM2_TZ_ SPI2_CS3  
10 10 IN  
PRG1_IEP0_EDIO GPIO0_86  
_DATA_IN_OUT31  
D
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TX  
11 11 _CTL  
EQEP1_I  
PRG1_PRU1_GPO  
15  
GPIO0_87  
GPIO0_88  
GPIO0_89  
GPIO0_90  
GPIO0_91  
GPIO0_92  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TD PRG1_PWM1_A0  
12 12  
PRG1_PRU1_GPO  
11  
0
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TD PRG1_PWM1_B0  
13 13  
PRG1_PRU1_GPO  
12  
1
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TD PRG1_PWM1_A1  
14 14  
PRG1_PRU1_GPO  
13  
2
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TD PRG1_PWM1_B1  
15 15  
PRG1_PRU1_GPO  
14  
3
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_RGMII2_TX PRG1_PWM1_A2  
16 16  
C
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_IEP1_EDC_ PRG1_PWM1_B2 SPI2_CLK  
17 17 SYNC_OUT1  
PRG1_ECAP0_SY UART1_RXD  
NC_OUT  
GPIO0_93  
GPIO0_94  
GPIO0_95  
GPIO1_0  
GPIO1_1  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_IEP1_EDC_ PRG1_PWM1_TZ_ SPI2_D0  
18 18 LATCH_IN0 IN  
PRG1_ECAP0_SY UART1_CTSn  
NC_IN  
PRG1_PRU1_GPO PRG1_PRU1_GPI PRG1_IEP1_EDC_ PRG1_PWM1_TZ_ SPI2_D1  
PRG1_ECAP0_IN_ UART1_RTSn  
APWM_OUT  
19  
19  
SYNC_OUT0  
OUT  
PRG1_MDIO0_MD SPI1_CS2  
IO  
PRG2_PWM1_A1  
PRG1_MDIO0_MD SPI1_CS3  
C
PRG2_PWM1_B1  
0x0011C188 CTRLMMR_PADCONFIG98  
0x0011C18C CTRLMMR_PADCONFIG99  
D25  
B26  
MMC0_DAT7  
MMC0_DAT6  
MMC0_DAT5  
MMC0_DAT4  
MMC0_DAT3  
MMC0_DAT2  
MMC0_DAT1  
MMC0_DAT0  
UART0_DCDn  
EQEP2_A  
EQEP2_B  
EQEP2_I  
EQEP2_S  
GPIO1_2  
GPIO1_3  
GPIO1_4  
GPIO1_5  
GPIO1_6  
GPIO1_7  
GPIO1_8  
GPIO1_9  
UART0_DSRn  
UART0_DTRn  
UART0_RIN  
0x0011C190 CTRLMMR_PADCONFIG100 A24  
0x0011C194 CTRLMMR_PADCONFIG101 E24  
0x0011C198 CTRLMMR_PADCONFIG102 A25  
0x0011C19C CTRLMMR_PADCONFIG103 C26  
0x0011C1A0 CTRLMMR_PADCONFIG104 E25  
0x0011C1A4 CTRLMMR_PADCONFIG105 A26  
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
GPIO1_10  
GPIO1_11  
GPIO1_12  
Bootstrap  
0x0011C1A8 CTRLMMR_PADCONFIG106 B25  
0x0011C1AC CTRLMMR_PADCONFIG107 B27  
0x0011C1B0 CTRLMMR_PADCONFIG108 C25  
0x0011C1B4 CTRLMMR_PADCONFIG109 A23  
MMC0_CLK  
MMC0_CMD  
MMC0_DS  
MMC0_SDCD  
PRG2_IEP0_EDIO GPIO1_13  
_OUTVALID  
0x0011C1B8 CTRLMMR_PADCONFIG110 B23  
0x0011C1BC CTRLMMR_PADCONFIG111 AG13  
0x0011C1C0 CTRLMMR_PADCONFIG112 AF13  
MMC0_SDWP  
SPI0_CS0  
GPIO1_14  
GPIO1_15  
SPI0_CS1  
CPTS0_TS_COMP I2C3_SCL  
PRG1_IEP0_EDIO GPIO1_16  
_OUTVALID  
0x0011C1C4 CTRLMMR_PADCONFIG113 AH13  
0x0011C1C8 CTRLMMR_PADCONFIG114 AE13  
SPI0_CLK  
SPI0_D0  
SPI0_D1  
GPIO1_17  
GPIO1_18  
GPIO1_19  
0x0011C1C CTRLMMR_PADCONFIG115 AD13  
C
0x0011C1D0 CTRLMMR_PADCONFIG116 AD12  
SPI1_CS0  
PRG2_IEP0_EDC_ PRG2_UART0_CT  
LATCH_IN0 Sn  
PRG0_IEP0_EDIO GPIO1_20  
_OUTVALID  
0x0011C1D4 CTRLMMR_PADCONFIG117 AG12  
0x0011C1D8 CTRLMMR_PADCONFIG118 AH12  
SPI1_CS1  
SPI1_CLK  
CPTS0_TS_SYNC I2C3_SDA  
GPIO1_21  
GPIO1_22  
PRG2_IEP0_EDC_ PRG2_UART0_RT  
SYNC_OUT0 Sn  
0x0011C1D CTRLMMR_PADCONFIG119 AE12  
C
SPI1_D0  
SPI1_D1  
PRG2_IEP0_EDC_ PRG2_UART0_RX  
LATCH_IN1  
GPIO1_23  
GPIO1_24  
D
0x0011C1E0 CTRLMMR_PADCONFIG120 AF12  
PRG2_IEP0_EDC_ PRG2_UART0_TX  
SYNC_OUT1  
D
0x0011C1E4 CTRLMMR_PADCONFIG121 AF11  
0x0011C1E8 CTRLMMR_PADCONFIG122 AE11  
0x0011C1EC CTRLMMR_PADCONFIG123 AG11  
0x0011C1F0 CTRLMMR_PADCONFIG124 AD11  
0x0011C1F4 CTRLMMR_PADCONFIG125 V24  
UART0_RXD  
UART0_TXD  
UART0_CTSn  
UART0_RTSn  
GPIO1_25  
GPIO1_26  
GPIO1_27  
GPIO1_28  
GPIO1_29  
TIMER_IO4  
TIMER_IO5  
SPI0_CS2  
SPI0_CS3  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RD PRG0_PWM3_A0  
0
MCASP0_ACLKX  
MCASP0_AFSX  
MCASP0_ACLKR  
MCASP0_AFSR  
MCASP0_AXR0  
MCASP0_AXR1  
MCASP0_AXR2  
0
0
0x0011C1F8 CTRLMMR_PADCONFIG126 W25  
0x0011C1FC CTRLMMR_PADCONFIG127 W24  
0x0011C200 CTRLMMR_PADCONFIG128 AA27  
0x0011C204 CTRLMMR_PADCONFIG129 Y24  
0x0011C208 CTRLMMR_PADCONFIG130 V28  
0x0011C20C CTRLMMR_PADCONFIG131 Y25  
0x0011C210 CTRLMMR_PADCONFIG132 U27  
0x0011C214 CTRLMMR_PADCONFIG133 V27  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RD PRG0_PWM3_B0  
1
GPIO1_30  
GPIO1_31  
GPIO1_32  
GPIO1_33  
GPIO1_34  
GPIO1_35  
GPIO1_36  
GPIO1_37  
1
1
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RD PRG0_PWM2_A0  
2
2
2
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RD PRG0_PWM3_A2  
3
3
3
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RX PRG0_PWM2_B0  
_CTL  
4
4
PRG0_PRU0_GPO PRG0_PRU0_GPI  
5
PRG0_PWM3_B2  
5
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_RX PRG0_PWM3_A1  
6
6
C
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_IEP0_EDC_ PRG0_PWM3_B1 PRG0_ECAP0_SY MCASP0_AXR3  
LATCH_IN1 NC_IN  
7
7
PRG0_PRU0_GPO PRG0_PRU0_GPI  
PRG0_PWM2_A1  
MCASP0_AXR4  
8
8
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C218 CTRLMMR_PADCONFIG134 V26  
0x0011C21C CTRLMMR_PADCONFIG135 U25  
0x0011C220 CTRLMMR_PADCONFIG136 AB25  
0x0011C224 CTRLMMR_PADCONFIG137 AD27  
0x0011C228 CTRLMMR_PADCONFIG138 AC26  
0x0011C22C CTRLMMR_PADCONFIG139 AD26  
0x0011C230 CTRLMMR_PADCONFIG140 AA24  
0x0011C234 CTRLMMR_PADCONFIG141 AD28  
0x0011C238 CTRLMMR_PADCONFIG142 U26  
0x0011C23C CTRLMMR_PADCONFIG143 V25  
0x0011C240 CTRLMMR_PADCONFIG144 U24  
0x0011C244 CTRLMMR_PADCONFIG145 AB28  
0x0011C248 CTRLMMR_PADCONFIG146 AC28  
0x0011C24C CTRLMMR_PADCONFIG147 AC27  
0x0011C250 CTRLMMR_PADCONFIG148 AB26  
0x0011C254 CTRLMMR_PADCONFIG149 AA25  
0x0011C258 CTRLMMR_PADCONFIG150 U23  
0x0011C25C CTRLMMR_PADCONFIG151 AB27  
0x0011C260 CTRLMMR_PADCONFIG152 W28  
0x0011C264 CTRLMMR_PADCONFIG153 W27  
0x0011C268 CTRLMMR_PADCONFIG154 Y28  
0x0011C26C CTRLMMR_PADCONFIG155 AA28  
0x0011C270 CTRLMMR_PADCONFIG156 AB24  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_UART0_CT PRG0_PWM3_TZ_ SPI3_CS1  
Sn IN  
MCASP0_AXR5  
PRG0_IEP0_EDIO GPIO1_38  
_DATA_IN_OUT28  
9
9
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_UART0_RT PRG0_PWM2_B1 SPI3_CS2  
10 10 Sn  
MCASP0_AXR6  
PRG0_IEP0_EDIO GPIO1_39  
_DATA_IN_OUT29  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TX PRG0_PWM3_TZ_ PRG0_PRU0_GPO MCASP0_AXR7  
11 11 _CTL OUT 15  
GPIO1_40  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TD PRG0_PWM0_A0 PRG0_PRU0_GPO MCASP0_AXR8  
12 12 11  
GPIO1_41  
0
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TD PRG0_PWM0_B0 PRG0_PRU0_GPO MCASP0_AXR9  
13 13 12  
GPIO1_42  
1
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TD PRG0_PWM0_A1 PRG0_PRU0_GPO MCASP0_AXR10  
14 14 13  
GPIO1_43  
2
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TD PRG0_PWM0_B1 PRG0_PRU0_GPO MCASP0_AXR11  
15 15 14  
GPIO1_44  
3
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_RGMII1_TX PRG0_PWM0_A2  
16 16  
MCASP0_AXR12  
MCASP1_AHCLKR GPIO1_45  
MCASP1_AHCLKX GPIO1_46  
MCASP2_AHCLKR GPIO1_47  
MCASP2_AHCLKX GPIO1_48  
GPIO1_49  
C
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_IEP0_EDC_ PRG0_PWM0_B2 PRG0_ECAP0_SY MCASP0_AXR13  
17 17 SYNC_OUT1 NC_OUT  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_IEP0_EDC_ PRG0_PWM0_TZ_ PRG0_ECAP0_IN_ MCASP0_AXR14  
18 18 LATCH_IN0 IN APWM_OUT  
PRG0_PRU0_GPO PRG0_PRU0_GPI PRG0_IEP0_EDC_ PRG0_PWM0_TZ_  
19 19 SYNC_OUT0 OUT  
MCASP0_AXR15  
MCASP1_ACLKX  
MCASP1_AFSX  
MCASP1_ACLKR  
MCASP1_AFSR  
MCASP1_AXR0  
MCASP1_AXR1  
MCASP1_AXR2  
MCASP1_AXR3  
MCASP1_AXR4  
MCASP1_AXR5  
MCASP1_AXR6  
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RD  
0
0
0
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RD  
GPIO1_50  
1
1
1
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RD PRG0_PWM2_A2  
GPIO1_51  
2
2
2
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RD  
EQEP0_A  
GPIO1_52  
3
3
3
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RX PRG0_PWM2_B2 EQEP0_B  
_CTL  
MCASP0_AHCLKR GPIO1_53  
MCASP0_AHCLKX GPIO1_54  
GPIO1_55  
4
4
PRG0_PRU1_GPO PRG0_PRU1_GPI  
EQEP0_S  
SPI3_CS0  
SPI3_CS3  
5
5
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_RX  
6
6
C
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_IEP1_EDC_  
LATCH_IN1  
UART2_TXD  
GPIO1_56  
GPIO1_57  
7
7
PRG0_PRU1_GPO PRG0_PRU1_GPI  
PRG0_PWM2_TZ_  
OUT  
8
8
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_UART0_RX  
PRG0_IEP0_EDIO GPIO1_58  
_DATA_IN_OUT30  
9
9
D
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_UART0_TX PRG0_PWM2_TZ_ EQEP0_I  
10 10 IN  
PRG0_IEP0_EDIO GPIO1_59  
_DATA_IN_OUT31  
D
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TX  
11 11 _CTL  
PRG0_PRU1_GPO MCASP1_AXR7  
15  
GPIO1_60  
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AM6548, AM6528, AM6526  
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021  
www.ti.com.cn  
表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C274 CTRLMMR_PADCONFIG157 AC25  
0x0011C278 CTRLMMR_PADCONFIG158 AD25  
0x0011C27C CTRLMMR_PADCONFIG159 AD24  
0x0011C280 CTRLMMR_PADCONFIG160 AE27  
0x0011C284 CTRLMMR_PADCONFIG161 AC24  
0x0011C288 CTRLMMR_PADCONFIG162 Y27  
0x0011C28C CTRLMMR_PADCONFIG163 Y26  
0x0011C290 CTRLMMR_PADCONFIG164 W26  
0x0011C294 CTRLMMR_PADCONFIG165 AE26  
0x0011C298 CTRLMMR_PADCONFIG166 AE28  
0x0011C29C CTRLMMR_PADCONFIG167 F18  
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TD PRG0_PWM1_A0 PRG0_PRU1_GPO MCASP1_AXR8  
12 12 11  
GPIO1_61  
0
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TD PRG0_PWM1_B0 PRG0_PRU1_GPO MCASP1_AXR9  
13 13 12  
GPIO1_62  
GPIO1_63  
GPIO1_64  
GPIO1_65  
GPIO1_66  
GPIO1_67  
GPIO1_68  
GPIO1_69  
GPIO1_70  
1
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TD PRG0_PWM1_A1 PRG0_PRU1_GPO MCASP2_AFSR  
14 14 13  
2
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TD PRG0_PWM1_B1 PRG0_PRU1_GPO MCASP2_ACLKR  
15 15 14  
3
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_RGMII2_TX PRG0_PWM1_A2  
16 16  
MCASP2_AXR0  
MCASP2_AXR1  
MCASP2_AFSX  
MCASP2_ACLKX  
MCASP2_AXR2  
MCASP2_AXR3  
C
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_IEP1_EDC_ PRG0_PWM1_B2 SPI3_CLK  
17 17 SYNC_OUT1  
UART2_RXD  
UART2_CTSn  
UART2_RTSn  
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_IEP1_EDC_ PRG0_PWM1_TZ_ SPI3_D0  
18 18 LATCH_IN0 IN  
PRG0_PRU1_GPO PRG0_PRU1_GPI PRG0_IEP1_EDC_ PRG0_PWM1_TZ_ SPI3_D1  
19  
19  
SYNC_OUT0  
OUT  
PRG0_MDIO0_MD  
IO  
PRG2_PWM1_A2  
PRG0_MDIO0_MD  
C
PRG2_PWM1_B2  
NMIn  
PRG2_PWM1_TZ_  
IN  
0x0011C2A0 CTRLMMR_PADCONFIG168 F17  
0x0011C2A4 CTRLMMR_PADCONFIG169 D19  
0x0011C2A8 CTRLMMR_PADCONFIG170 C19  
0x0011C2AC CTRLMMR_PADCONFIG171 E20  
RESETz  
RESETSTATz  
PORz_OUT  
SOC_SAFETY_ER  
RORn  
0x0011C2B0 CTRLMMR_PADCONFIG172 C20  
0x0011C2B4 CTRLMMR_PADCONFIG173 A20  
0x0011C2B8 CTRLMMR_PADCONFIG174 A21  
0x0011C2BC CTRLMMR_PADCONFIG175 AD9  
0x0011C2C0 CTRLMMR_PADCONFIG176 AC8  
0x0011C2C4 CTRLMMR_PADCONFIG177 D27  
0x0011C2C8 CTRLMMR_PADCONFIG178 D26  
TDI  
TDO  
TMS  
USB0_DRVVBUS  
USB1_DRVVBUS  
MMC1_DAT3  
MMC1_DAT2  
MMC1_DAT1  
GPIO1_71  
GPIO1_72  
GPIO1_73  
GPIO1_74  
GPIO1_75  
0x0011C2C CTRLMMR_PADCONFIG179 E27  
C
0x0011C2D0 CTRLMMR_PADCONFIG180 D28  
0x0011C2D4 CTRLMMR_PADCONFIG181 C27  
0x0011C2D8 CTRLMMR_PADCONFIG182 C28  
MMC1_DAT0  
MMC1_CLK  
MMC1_CMD  
MMC1_SDCD  
GPIO1_76  
GPIO1_77  
GPIO1_78  
GPIO1_79  
0x0011C2D CTRLMMR_PADCONFIG183 B24  
C
0x0011C2E0 CTRLMMR_PADCONFIG184 C24  
0x0011C2E8 CTRLMMR_PADCONFIG186 D20  
0x0011C2EC CTRLMMR_PADCONFIG187 C21  
MMC1_SDWP  
I2C0_SCL  
GPIO1_80  
I2C0_SDA  
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x0011C2F0 CTRLMMR_PADCONFIG188 B21  
0x0011C2F4 CTRLMMR_PADCONFIG189 E21  
0x0011C2F8 CTRLMMR_PADCONFIG190 D21  
I2C1_SCL  
CPTS0_HW1TSPU  
SH  
I2C1_SDA  
CPTS0_HW2TSPU  
SH  
ECAP0_IN_APWM SYNC0_OUT  
_OUT  
CPTS0_RFT_CLK  
GPIO1_86  
0x0011C2FC CTRLMMR_PADCONFIG191 A22  
0x0011C300 CTRLMMR_PADCONFIG192 B22  
0x0011C304 CTRLMMR_PADCONFIG193 C23  
0x0011C308 CTRLMMR_PADCONFIG194 E19  
EXT_REFCLK1  
TIMER_IO0  
TIMER_IO1  
PORz  
SYNC1_OUT  
GPIO1_87  
GPIO1_88  
GPIO1_89  
SYSCLKOUT0  
OBSCLK0  
0x4301C000 CTRLMMR_WKUP_PADCON V1  
FIG0  
MCU_OSPI0_CLK MCU_HYPERBUS  
0_CK  
WKUP_GPIO0_12  
WKUP_GPIO0_13  
WKUP_GPIO0_14  
WKUP_GPIO0_15  
WKUP_GPIO0_16  
WKUP_GPIO0_17  
WKUP_GPIO0_18  
WKUP_GPIO0_19  
WKUP_GPIO0_20  
WKUP_GPIO0_21  
WKUP_GPIO0_22  
WKUP_GPIO0_23  
WKUP_GPIO0_24  
WKUP_GPIO0_25  
WKUP_GPIO0_26  
WKUP_GPIO0_27  
WKUP_GPIO0_28  
WKUP_GPIO0_29  
0x4301C004 CTRLMMR_WKUP_PADCON U1  
FIG1  
MCU_OSPI0_LBC MCU_HYPERBUS  
LKO  
0_CKn  
0x4301C008 CTRLMMR_WKUP_PADCON U2  
FIG2  
MCU_OSPI0_DQS MCU_HYPERBUS  
0_RWDS  
0x4301C00C CTRLMMR_WKUP_PADCON U4  
FIG3  
MCU_OSPI0_D0  
MCU_OSPI0_D1  
MCU_OSPI0_D2  
MCU_OSPI0_D3  
MCU_OSPI0_D4  
MCU_OSPI0_D5  
MCU_OSPI0_D6  
MCU_OSPI0_D7  
MCU_HYPERBUS  
0_DQ0  
0x4301C010 CTRLMMR_WKUP_PADCON U5  
FIG4  
MCU_HYPERBUS  
0_DQ1  
0x4301C014 CTRLMMR_WKUP_PADCON T2  
FIG5  
MCU_HYPERBUS  
0_DQ2  
0x4301C018 CTRLMMR_WKUP_PADCON T3  
FIG6  
MCU_HYPERBUS  
0_DQ3  
0x4301C01C CTRLMMR_WKUP_PADCON T4  
FIG7  
MCU_HYPERBUS  
0_DQ4  
0x4301C020 CTRLMMR_WKUP_PADCON T5  
FIG8  
MCU_HYPERBUS  
0_DQ5  
0x4301C024 CTRLMMR_WKUP_PADCON R2  
FIG9  
MCU_HYPERBUS  
0_DQ6  
0x4301C028 CTRLMMR_WKUP_PADCON R3  
FIG10  
MCU_HYPERBUS  
0_DQ7  
0x4301C02C CTRLMMR_WKUP_PADCON R4  
FIG11  
MCU_OSPI0_CSn MCU_HYPERBUS  
0_CSn0  
0
0x4301C030 CTRLMMR_WKUP_PADCON R5  
FIG12  
MCU_OSPI0_CSn MCU_HYPERBUS  
1
0_RESETn  
0x4301C034 CTRLMMR_WKUP_PADCON T1  
FIG13  
MCU_OSPI1_CLK  
0x4301C038 CTRLMMR_WKUP_PADCON R1  
FIG14  
MCU_OSPI1_LBC MCU_OSPI0_CSn MCU_HYPERBUS  
LKO 0_RESETOn  
2
0x4301C03C CTRLMMR_WKUP_PADCON P2  
FIG15  
MCU_OSPI1_DQS MCU_OSPI0_CSn MCU_HYPERBUS  
0_INTn  
3
0x4301C040 CTRLMMR_WKUP_PADCON P3  
FIG16  
MCU_OSPI1_D0  
0x4301C044 CTRLMMR_WKUP_PADCON P4  
FIG17  
MCU_OSPI1_D1  
MCU_UART0_RXD MCU_SPI1_CS1  
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x4301C048 CTRLMMR_WKUP_PADCON P5  
FIG18  
MCU_OSPI1_D2  
MCU_UART0_TXD MCU_SPI1_CS2  
WKUP_GPIO0_30  
0x4301C04C CTRLMMR_WKUP_PADCON P1  
FIG19  
MCU_OSPI1_D3  
MCU_UART0_CTS MCU_SPI0_CS1  
n
WKUP_GPIO0_31  
WKUP_GPIO0_32  
WKUP_GPIO0_33  
WKUP_GPIO0_34  
WKUP_GPIO0_35  
WKUP_GPIO0_36  
WKUP_GPIO0_37  
WKUP_GPIO0_38  
WKUP_GPIO0_39  
WKUP_GPIO0_40  
WKUP_GPIO0_41  
WKUP_GPIO0_42  
WKUP_GPIO0_43  
WKUP_GPIO0_44  
WKUP_GPIO0_45  
WKUP_GPIO0_46  
WKUP_GPIO0_47  
0x4301C050 CTRLMMR_WKUP_PADCON N2  
FIG20  
MCU_OSPI1_CSn  
0
0x4301C054 CTRLMMR_WKUP_PADCON N3  
FIG21  
MCU_OSPI1_CSn MCU_HYPERBUS MCU_TIMER_IO0 MCU_HYPERBUS MCU_UART0_RTS MCU_SPI0_CS2  
0_WPn 0_CSn1  
1
n
0x4301C058 CTRLMMR_WKUP_PADCON N4  
FIG22  
MCU_RGMII1_TX_ MCU_RMII1_CRS_  
CTL DV  
0x4301C05C CTRLMMR_WKUP_PADCON N5  
FIG23  
MCU_RGMII1_RX_ MCU_RMII1_RX_E  
CTL  
R
0x4301C060 CTRLMMR_WKUP_PADCON M2  
FIG24  
MCU_RGMII1_TD3  
0x4301C064 CTRLMMR_WKUP_PADCON M3  
FIG25  
MCU_RGMII1_TD2  
0x4301C068 CTRLMMR_WKUP_PADCON M4  
FIG26  
MCU_RGMII1_TD1 MCU_RMII1_TXD1  
MCU_RGMII1_TD0 MCU_RMII1_TXD0  
MCU_RGMII1_TX MCU_RMII1_TX_E  
0x4301C06C CTRLMMR_WKUP_PADCON M5  
FIG27  
0x4301C070 CTRLMMR_WKUP_PADCON N1  
FIG28  
C
N
0x4301C074 CTRLMMR_WKUP_PADCON M1  
FIG29  
MCU_RGMII1_RX MCU_RMII1_REF_  
C
CLK  
0x4301C078 CTRLMMR_WKUP_PADCON L2  
FIG30  
MCU_RGMII1_RD  
3
0x4301C07C CTRLMMR_WKUP_PADCON L5  
FIG31  
MCU_RGMII1_RD  
2
0x4301C080 CTRLMMR_WKUP_PADCON M6  
FIG32  
MCU_RGMII1_RD MCU_RMII1_RXD1  
1
0x4301C084 CTRLMMR_WKUP_PADCON L6  
FIG33  
MCU_RGMII1_RD MCU_RMII1_RXD0  
0
0x4301C088 CTRLMMR_WKUP_PADCON L4  
FIG34  
MCU_MDIO0_MDI  
O
0x4301C08C CTRLMMR_WKUP_PADCON L1  
FIG35  
MCU_MDIO0_MD  
C
0x4301C090 CTRLMMR_WKUP_PADCON Y1  
FIG36  
MCU_SPI0_CLK  
MCU_SPI0_D0  
MCU_SPI0_D1  
MCU_SPI0_CS0  
WKUP_GPIO0_48 MCU_BOOTMODE  
06  
0x4301C094 CTRLMMR_WKUP_PADCON Y3  
FIG37  
WKUP_GPIO0_49 MCU_BOOTMODE  
07  
0x4301C098 CTRLMMR_WKUP_PADCON Y2  
FIG38  
WKUP_GPIO0_50 MCU_BOOTMODE  
05  
0x4301C09C CTRLMMR_WKUP_PADCON Y4  
FIG39  
WKUP_GPIO0_51  
0x4301C0A0 CTRLMMR_WKUP_PADCON AB1  
FIG40  
WKUP_UART0_RX  
D
WKUP_GPIO0_52  
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x4301C0A4 CTRLMMR_WKUP_PADCON AB5  
FIG41  
WKUP_UART0_TX  
D
WKUP_GPIO0_53  
0x4301C0A8 CTRLMMR_WKUP_PADCON W1  
FIG42  
MCU_MCAN0_TX  
MCU_MCAN0_RX  
WKUP_GPIO0_0  
WKUP_GPIO0_1  
WKUP_GPIO0_2  
WKUP_GPIO0_3  
WKUP_GPIO0_4  
WKUP_GPIO0_5  
WKUP_GPIO0_6  
WKUP_GPIO0_7  
WKUP_GPIO0_8  
WKUP_GPIO0_9  
WKUP_GPIO0_54  
WKUP_GPIO0_55  
WKUP_GPIO0_0  
WKUP_GPIO0_1  
WKUP_GPIO0_2  
WKUP_GPIO0_3  
WKUP_GPIO0_4  
WKUP_GPIO0_5  
WKUP_GPIO0_6  
WKUP_GPIO0_7  
WKUP_GPIO0_8  
WKUP_GPIO0_9  
WKUP_GPIO0_10  
WKUP_GPIO0_11  
0x4301C0A CTRLMMR_WKUP_PADCON W2  
C
FIG43  
0x4301C0B0 CTRLMMR_WKUP_PADCON AF4  
FIG44  
MCU_SPI1_CLK  
MCU_SPI1_D0  
MCU_SPI1_D1  
MCU_SPI1_CS0  
MCU_BOOTMODE  
00  
0x4301C0B4 CTRLMMR_WKUP_PADCON AF3  
FIG45  
MCU_BOOTMODE  
01  
0x4301C0B8 CTRLMMR_WKUP_PADCON AE3  
FIG46  
MCU_BOOTMODE  
02  
0x4301C0B CTRLMMR_WKUP_PADCON AD1  
MCU_BOOTMODE  
03  
C
FIG47  
0x4301C0C0 CTRLMMR_WKUP_PADCON AC3  
FIG48  
MCU_MCAN1_TX MCU_SPI0_CS3  
MCU_MCAN1_RX MCU_SPI1_CS3  
WKUP_UART0_CT MCU_CPTS0_HW  
MCU_ADC_EXT_T  
RIGGER0  
MCU_BOOTMODE  
04  
0x4301C0C4 CTRLMMR_WKUP_PADCON AD3  
FIG49  
MCU_ADC_EXT_T  
RIGGER1  
0x4301C0C8 CTRLMMR_WKUP_PADCON AC2  
FIG50  
Sn  
1TSPUSH  
0x4301C0C CTRLMMR_WKUP_PADCON AC1  
WKUP_UART0_RT MCU_CPTS0_HW  
Sn  
C
FIG51  
2TSPUSH  
0x4301C0D0 CTRLMMR_WKUP_PADCON AC5  
FIG52  
MCU_CPTS0_TS_  
SYNC  
MCU_BOOTMODE  
08  
0x4301C0D4 CTRLMMR_WKUP_PADCON AB4  
FIG53  
MCU_CPTS0_TS_  
COMP  
MCU_BOOTMODE  
09  
0x4301C0D8 CTRLMMR_WKUP_PADCON AB3  
FIG54  
WKUP_GPIO0_10 MCU_EXT_REFCL  
K0  
MCU_CPTS0_RFT MCU_SYSCLKOU  
_CLK  
T0  
0x4301C0D CTRLMMR_WKUP_PADCON AB2  
WKUP_GPIO0_11 MCU_OBSCLK0  
MCU_TIMER_IO1  
MCU_CLKOUT0  
C
FIG55  
0x4301C0E0 CTRLMMR_WKUP_PADCON AC7  
FIG56  
WKUP_I2C0_SCL  
0x4301C0E4 CTRLMMR_WKUP_PADCON AD6  
FIG57  
WKUP_I2C0_SDA  
0x4301C0E8 CTRLMMR_WKUP_PADCON AD8  
FIG58  
MCU_I2C0_SCL  
0x4301C0E CTRLMMR_WKUP_PADCON AD7  
MCU_I2C0_SDA  
C
FIG59  
0x4301C0F0 CTRLMMR_WKUP_PADCON AA5  
FIG60  
PMIC_POWER_EN  
1
0x4301C0F4 CTRLMMR_WKUP_PADCON W3  
FIG61  
MCU_SAFETY_ER  
RORn  
0x4301C0F8 CTRLMMR_WKUP_PADCON W4  
FIG62  
MCU_RESETz  
0x4301C0FC CTRLMMR_WKUP_PADCON V3  
FIG63  
MCU_RESETSTAT  
z
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表6-76. Pin Multiplexing (continued)  
MUXMODE[7:0] SETTINGS  
BALL  
NUMBER  
ADDRESS  
REGISTER NAME  
0
1
2
3
4
5
6
7
Bootstrap  
0x4301C100 CTRLMMR_WKUP_PADCON V2  
FIG64  
MCU_PORz_OUT  
0x4301C104 CTRLMMR_WKUP_PADCON AA4  
FIG65  
TCK  
0x4301C108 CTRLMMR_WKUP_PADCON AA3  
FIG66  
TRSTn  
EMU0  
EMU1  
0x4301C10C CTRLMMR_WKUP_PADCON AA2  
FIG67  
0x4301C110 CTRLMMR_WKUP_PADCON AA1  
FIG68  
0x4301C114 CTRLMMR_WKUP_PADCON Y5  
FIG69  
PMIC_POWER_EN  
0
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6.5 Connections for Unused Pins  
This section describes the Unused/Reserved balls connection requirements.  
Note  
All power balls must be supplied with the voltages specified in 节 7.4, Recommended Operating  
Conditions, unless otherwise specified in 节6.3, Signal Descriptions.  
表6-77. Unused Balls Specific Connection Requirements  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
C22  
AE4  
AA3  
K2  
K3  
V5  
H2  
H3  
K5  
J3  
OSC1_XI  
WKUP_LFOSC0_XI  
TRSTn  
MCU_ADC0_REFN  
MCU_ADC0_REFP  
MCU_BYP_POR  
MCU_ADC1_REFP  
MCU_ADC1_REFN  
MCU_ADC0_AIN0  
MCU_ADC0_AIN1  
MCU_ADC0_AIN2  
MCU_ADC0_AIN3  
MCU_ADC0_AIN4  
MCU_ADC0_AIN5  
MCU_ADC0_AIN6  
MCU_ADC0_AIN7  
MCU_ADC1_AIN0  
MCU_ADC1_AIN1  
MCU_ADC1_AIN2  
MCU_ADC1_AIN3  
MCU_ADC1_AIN4  
MCU_ADC1_AIN5  
MCU_ADC1_AIN6  
MCU_ADC1_AIN7  
J1  
Each of these balls must be connected to VSS through a separate  
external pull resistor to ensure these balls are held to a valid logic low  
level if unused.  
J5  
K4  
J4  
J2  
J6  
F4  
G6  
G4  
H5  
F5  
G5  
G3  
H4  
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表6-77. Unused Balls Specific Connection Requirements (continued)  
BALL NUMBER  
BALL NAME  
CONNECTION REQUIREMENTS  
F17  
W4  
RESETz  
MCU_RESETz  
MCU_PORz  
W5  
E19  
AA4  
A21  
AC7  
AD6  
AD7  
AD8  
F18  
C20  
A20  
AA1  
AA2  
F21  
T6  
PORz  
TCK  
TMS  
WKUP_I2C0_SCL  
WKUP_I2C0_SDA  
MCU_I2C0_SDA  
MCU_I2C0_SCL  
NMIn  
Each of these balls must be connected to the corresponding power  
supply through a separate external pull resistor to ensure these balls  
are held to a valid logic high level if unused.(1)  
TDI  
TDO  
EMU1  
EMU0  
VPP_CORE  
VPP_MCU  
AG5  
AG6  
AC9  
AH3  
AG2  
AH4  
AG3  
AH6  
AH7  
SERDES0_REFCLKN  
SERDES0_REFCLKP  
SERDES0_REFRES  
SERDES0_RXN  
SERDES0_RXP  
SERDES0_TXN  
SERDES0_TXP  
SERDES1_REFCLKN  
SERDES1_REFCLKP  
SERDES1_REFRES  
SERDES1_RXN  
SERDES1_RXP  
SERDES1_TXN  
SERDES1_TXP  
This ball must be left unconnected if unused.  
AC14  
AG9  
AH10  
AH9  
AG8  
(1) To determine which power supply is associated with any IO refer to 表6-1, Pin Attributes.  
表6-78. Reserved Balls Specific Connection Requirements  
BALLS  
CONNECTION REQUIREMENTS  
AA6 (RSV2), B1 (RSV3), AC23 (RSV4), C12 (RSV5), F9 (RSV6),  
F10 (RSV7), AD10 (RSV8), AC13 (RSV9), B28 (RSV10), A27  
(RSV11), D23 (RSV12), E23 (RSV13), W6 (TEMP_DIODE_P), F16 These balls must be left unconnected.  
(DDR_FS_RESETn), D24 (MMC0_CALPAD), F23  
(MMC1_CALPAD)  
These balls must be connected to VSS through a separate external  
pull resistor to ensure these balls are held to a valid logic low level.  
V4 (RSV1)  
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Note  
All other unused signal balls with a Pad Configuration Register can be left unconnected with their  
multiplexing mode set to GPIO input and internal pulldown resistor enabled.  
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case  
where internal pull resistors are allowed as the only source/sink to hold a valid logic level.  
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on  
the internal pull resistor to hold a valid logic level.  
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for  
some operating conditions. This may be the case when connected to components with leakage to the  
opposite logic level, or when external noise sources couple to signal traces attached to balls which are  
only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be  
required to hold a valid logic level on balls with external connections.  
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state  
which could damage the IO cell.  
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7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1) (2)  
PARAMETERS  
MIN  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
MAX UNIT  
VDD_CORE  
Supply voltage range for CORE domain  
Supply voltage range for R5F MCU domain  
Supply voltage range for A53 MPU0 domain  
Supply voltage range for A53 MPU1 domain  
Supply voltage range for WKUP domain  
Supply voltage range for WKUP domain  
Supply voltage range for MMC0 DLL  
1.3  
1.3  
1.3  
1.3  
1.3  
1.3  
1.3  
1.3  
2.2  
2.2  
2.2  
2.2  
3.8  
V
V
V
V
V
V
V
V
V
V
V
V
V
VDD_MCU  
VDD_MPU0  
VDD_MPU1  
VDD_WKUP0  
VDD_WKUP1  
VDD_DLL_MMC0  
VDD_DLL_MMC1  
VDDA_1P8_CSI0  
VDDA_1P8_OLDI0  
VDDA_1P8_SDIO  
VDDA_1P8_SERDES0  
VDDA_3P3_IOLDO_WKUP  
Supply voltage range for MMC1 DLL  
Supply voltage range for CSI PHY, Analog, 1.8 V  
Supply voltage range for OLDI, Analog, 1.8 V  
Supply voltage range for SDIO LDO, Analog, 1.8 V  
Supply voltage range for USB, PCIE, Analog, 1.8 V  
Supply voltage range for WKUP IO Bias LDO, Analog,  
3.3 V  
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
VDDA_3P3_SDIO  
VDDA_3P3_USB  
VDDA_ADC_MCU  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_LDO_WKUP  
VDDA_MCU  
Supply voltage range for IO Bias LDO, Analog 3.3 V  
Supply voltage range for IO Bias LDO, Analog 3.3 V  
Supply voltage range for SDIO LDO, Analog, 3.3 V  
Supply voltage range for USBPHY, Analog, 3.3 V  
Supply voltage range for ADC0, ADC1, Analog  
Supply voltage range for DDR DPLL, Analog  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
3.8  
3.8  
3.8  
3.8  
2.2  
2.2  
2.2  
2.2  
2.2  
V
V
V
V
V
V
V
V
V
Supply voltage range for DDR De-skew DPLL, Analog  
Supply voltage range for WKUP LDO, Analog  
Supply voltage range for MCU SRAM LDO, MCU  
DPLL, CPSW DPLL, Analog  
VDDA_PLL_CORE  
Supply voltage range for CORE DPLL, PER1 DPLL,  
Analog  
-0.3  
2.2  
V
VDDA_PLL_DSS  
Supply voltage range for DSS DPLL, Analog  
Supply voltage range for MPU0 DPLL, Analog  
Supply voltage range for MPU1 DPLL, Analog  
Supply voltage range for PER0 DPLL, Analog  
Supply voltage range for WKUP POR, Analog  
Supply voltage range for CORE SRAM LDOs, Analog  
Supply voltage range for CORE SRAM LDOs, Analog  
Supply voltage range for MPU SRAM LDOs, Analog  
Supply voltage range for MPU SRAM LDOs, Analog  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
V
V
V
V
V
V
V
V
V
V
VDDA_PLL_MPU0  
VDDA_PLL_MPU1  
VDDA_PLL_PER0  
VDDA_POR_WKUP  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
VDDA_SRAM_MPU0  
VDDA_SRAM_MPU1  
VDDA_WKUP  
Supply voltage range for WKUP OSC, SRAM LDO,  
Analog  
VDDS_DDR  
VDDS_OSC1  
VDDS0  
Supply voltage range for DDR IO domain  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
V
V
V
V
V
V
V
Supply voltage range for CORE HFOSC, Analog  
Supply voltage range for VDDSHV0 IO bias  
Supply voltage range for VDDSHV0_WKUP IO bias  
Supply voltage range for VDDSHV1 IO bias  
Supply voltage range for VDDSHV1_WKUP IO bias  
Supply voltage range for VDDSHV2 IO bias  
VDDS0_WKUP  
VDDS1  
VDDS1_WKUP  
VDDS2  
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over operating free-air temperature range (unless otherwise noted)(1) (2)  
PARAMETERS  
MIN  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
-0.3  
MAX UNIT  
VDDS2_WKUP  
VDDS3  
Supply voltage range for VDDSHV2_WKUP IO bias  
Supply voltage range for VDDSHV3 IO bias  
Supply voltage range for VDDSHV4 IO bias  
Supply voltage range for VDDSHV5 IO bias  
Supply voltage range for VDDSHV6 IO bias  
Supply voltage range for VDDSHV7 IO bias  
Supply voltage range for VDDSHV8 IO bias  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
2.2  
3.8  
NC(8)  
1.89  
1.89  
1.89  
3.8  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDS4  
VDDS5  
VDDS6  
VDDS7  
VDDS8  
VDDSHV0  
Supply voltage range for dual-voltage IO  
domain  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
VDDSHV0_WKUP  
VDDSHV1  
Supply voltage range for dual-voltage IO  
domain  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV1_WKUP  
VDDSHV2  
Supply voltage range for dual-voltage IO  
domain  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV2_WKUP  
VDDSHV3  
Supply voltage range for dual-voltage IO  
domain  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV4  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV5  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV6  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV7  
Supply voltage range for dual-voltage IO  
domain  
VDDSHV8  
Supply voltage range for dual-voltage IO  
domain  
VPP_CORE  
VPP_MCU  
Supply voltage range for CORE EFUSE domain  
Supply voltage range for MCU EFUSE domain  
Voltage range for USB VBUS comparator input  
Voltage range for USB VBUS comparator input  
-0.3  
-0.3  
USB0_VBUS  
USB1_VBUS  
-0.3  
Steady State Max. Voltage at all I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, NMIn,  
–0.3  
fail-safe IO pins  
VDDA_3P3_MON_WKUP, VDDA_3P3_MON0  
VDDA_1P8_MON_WKUP, VDDA_1P8_MON0  
DDR_FS_RESETn  
-0.3  
-0.3  
-0.3  
-0.3  
2.2  
V
V
V
V
2.2  
2.2(7)  
Steady State Max. Voltage at all VDDA_VSYS_MON(4)  
other IO pins(3)  
All other IO pins  
IO supply voltage + 0.3  
0.2 × VDD(5)  
Transient Overshoot and  
20% of IO supply voltage for up to 20% of signal  
V
Undershoot specification at IO pin  
period (see 图7-1, IO Transient Voltage Ranges)  
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over operating free-air temperature range (unless otherwise noted)(1) (2)  
PARAMETERS  
MIN  
MAX UNIT  
(6)  
TSTG  
Storage temperature  
-55  
+150 °C  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under 节7.4, Recommended  
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.  
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For  
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be  
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources  
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage  
range, including power supply ramp-up and ramp-down sequences.  
(4) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the  
appropriate resistor voltage divider source. For more information, see 节9.2.5, System Power Supply Monitor Design Guidelines.  
(5) VDD is the voltage on the corresponding power-supply pin(s) for the IO.  
(6) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends  
returning to ambient room temperature before usage.  
(7) The voltage on the VDDA_VSYS_MON pin should never exceed VDDA_POR_WKUP’s voltage.  
(8) NC stands for No Connect.  
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply  
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO  
power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, NMIn,  
VDDA_1P8_MON_WKUP, VDDA_1P8_MON0, VDDA_3P3_MON_WKUP, and VDDA_3P3_MON0 are the only  
fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to  
the value defined by the Steady State Max. Voltage at all IO pins parameter in 节 7.1, Absolute Maximum  
Ratings.  
Overshoot = 20% of nominal  
IO supply voltage  
Tovershoot  
Tperiod  
Tundershoot  
Undershoot = 20% of nominal  
IO supply voltage  
A. Tovershoot + Tundershoot < 20% of Tperiod  
图7-1. IO Transient Voltage Ranges  
7.2 ESD Ratings  
VALUE  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
± 1000  
Electrostatic discharge  
(ESD)  
V(ESD)  
V
Charged-device model (CDM), per JEDEC specification ANSI/  
ESDA/JEDEC JS-002(2)  
± 250  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
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7.3 Power-On Hours (POH)  
OPERATING  
COMMERCIAL TEMPERATURE RANGE  
EXTENDED TEMPERATURE RANGE  
CONDITION(1) (2) (3)  
JUNCTION  
TEMPERATURE (Tj)  
OPP  
LIFETIME (POH)  
JUNCTION TEMP (Tj)  
LIFETIME (POH)  
OPP_NOM  
OPP_OD  
100k  
100k  
100k  
100k  
100k  
55k  
0°C to 90°C  
-40°C to 105°C  
OPP_TURBO  
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard  
terms and conditions for TI semiconductor products.  
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted  
temperatures.  
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.  
7.4 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)(2)  
SUPPLY NAME  
VDD_CORE(3)  
DESCRIPTION  
MIN(1)  
1.05  
NOM  
1.1  
MAX(1)  
1.15  
UNIT  
V
CORE voltage domain supply  
VDD_MCU(3)  
VDD_MPU0(3)  
MCU voltage domain supply  
MPU0 voltage domain supply  
1.05  
1.1  
1.15  
V
OPP_NOM  
OPP_OD  
V
See 节7.5  
See 节7.5  
See 节7.5  
See 节7.5  
See 节7.5  
See 节7.5  
1.1  
V
OPP_TURBO  
OPP_NOM  
OPP_OD  
V
VDD_MPU1(3)  
MPU1 voltage domain supply  
V
V
OPP_TURBO  
V
VDD_WKUP0  
WKUP voltage domain supply  
WKUP voltage domain supply  
MMC0 PHY DLL voltage supply  
MMC1 PHY DLL voltage supply  
CSI PHY analog power supply  
SDIO LDO analog power supply  
OLDI analog power supply  
1.05  
1.05  
1.05  
1.05  
1.71  
1.71  
1.71  
1.71  
1.15  
1.15  
1.15  
1.15  
1.89  
1.89  
1.89  
1.89  
V
VDD_WKUP1  
1.1  
V
VDD_DLL_MMC0  
VDD_DLL_MMC1  
VDDA_1P8_CSI0  
VDDA_1P8_SDIO  
VDDA_1P8_OLDI0  
VDDA_1P8_SERDES0  
1.1  
V
1.1  
V
1.8  
V
1.8  
V
1.8  
V
SERDES0/1 (USB, PCIE, SGMII) analog power supply  
Maximum peak-to-peak supply noise  
1.8  
V
30 mVPPmax  
VDDA_3P3_IOLDO_WKUP WKUP IO Bias LDO analog power supply  
3.14  
3.14  
3.14  
3.14  
3.14  
1.71  
1.71  
3.14  
3.14  
0
3.3  
3.3  
3.46  
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
VDDA_3P3_SDIO  
VDDA_3P3_USB  
IO Bias LDO analog power supply  
IO Bias LDO analog power supply  
SDIO LDO analog power supply  
USB analog power supply  
3.46  
3.46  
3.46  
3.46  
1.89  
1.89  
3.46  
3.46  
1
3.3  
3.3  
3.3  
VDDA_1P8_MON_WKUP  
VDDA_1P8_MON0  
VDDA_3P3_MON_WKUP  
VDDA_3P3_MON0  
VDDA_VSYS_MON  
VDDA_ADC_MCU  
VDDA_LDO_WKUP  
VDDA_MCU  
1.8V supply monitor in WKUP domain  
1.8V supply monitor in MAIN domain  
3.3V supply monitor in WKUP domain  
3.3V supply monitor in MAIN domain  
Supply monitor for system  
1.8  
1.8  
3.3  
3.3  
see(6)  
ADC0, ADC1 analog power supply  
WKUP LDO analog power supply  
1.71  
1.71  
1.71  
1.8  
1.89  
1.89  
1.89  
1.8  
MCU SRAM LDO, MCU DPLL, CPSW DPLL analog power  
supply  
1.8  
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over operating free-air temperature range (unless otherwise noted)(2)  
SUPPLY NAME  
DESCRIPTION  
CORE DPLL, PER1 DPLL analog power supply  
Maximum peak-to-peak supply noise  
DDR DPLL analog power supply  
MIN(1)  
NOM  
MAX(1)  
1.89  
UNIT  
VDDA_PLL_CORE  
1.71  
1.8  
V
50 mVPPmax  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_PLL_DSS  
VDDA_PLL_MPU0  
VDDA_PLL_MPU1  
VDDA_PLL_PER0  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.89  
V
Maximum peak-to-peak supply noise  
DDR De-skew DPLL analog power supply  
Maximum peak-to-peak supply noise  
DSS DPLL analog power supply  
50 mVPPmax  
1.89  
V
50 mVPPmax  
1.89  
V
Maximum peak-to-peak supply noise  
MPU0 DPLL analog power supply  
50 mVPPmax  
1.89  
V
Maximum peak-to-peak supply noise  
MPU1 DPLL analog power supply  
50 mVPPmax  
1.89  
V
Maximum peak-to-peak supply noise  
PER0 DPLL analog power supply  
50 mVPPmax  
1.89  
V
Maximum peak-to-peak supply noise  
WKUP POR/POK analog power supply  
CORE SRAM LDOs analog power supply  
CORE SRAM LDOs analog power supply  
MPU SRAM LDOs analog power supply  
MPU SRAM LDOs analog power supply  
50 mVPPmax  
VDDA_POR_WKUP  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
VDDA_SRAM_MPU0  
VDDA_SRAM_MPU1  
VDDA_WKUP  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.89  
V
V
V
V
V
V
1.89  
1.89  
1.89  
1.89  
1.89  
WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 /  
WKUP_OSC0), SRAM LDO analog power supply  
VDDS_DDR(4)  
DDR IO domain power supply (DDR3L)  
DDR IO domain power supply (DDR4)  
DDR IO domain power supply (LPDDR4)  
1.28  
1.14  
1.05  
1.71  
1.35  
1.2  
1.1  
1.8  
1.42  
1.26  
1.15  
1.89  
V
V
V
V
VDDS_OSC1  
MAIN High Frequency Oscillator (OSC1) analog power  
supply  
VDDS0  
IO bias supply for VDDSHV0  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VDDS0_WKUP  
VDDS1  
IO bias supply for VDDSHV0_WKUP  
IO bias supply for VDDSHV1  
VDDS1_WKUP  
VDDS2  
IO bias supply for VDDSHV1_WKUP  
IO bias supply for VDDSHV2  
VDDS2_WKUP  
VDDS3  
IO bias supply for VDDSHV2_WKUP  
IO bias supply for VDDSHV3  
VDDS4  
IO bias supply for VDDSHV4  
VDDS5  
IO bias supply for VDDSHV5  
VDDS6  
IO bias supply for VDDSHV6  
VDDS7  
IO bias supply for VDDSHV7  
VDDS8  
IO bias supply for VDDSHV8  
VDDSHV0  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
VDDSHV0_WKUP  
VDDSHV1  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
VDDSHV1_WKUP  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
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over operating free-air temperature range (unless otherwise noted)(2)  
SUPPLY NAME  
DESCRIPTION  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
MIN(1)  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
1.71  
3.14  
0
NOM  
1.8  
MAX(1)  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
3.46  
1.89  
1.89  
UNIT  
V
VDDSHV2  
3.3  
V
VDDSHV2_WKUP  
VDDSHV3  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV4  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV5  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV6  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV7  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
VDDSHV8  
Dual-voltage IO domain power supply 1.8-V operation  
3.3-V operation  
1.8  
V
3.3  
V
USB0_VBUS  
USB1_VBUS  
USB0_ID  
USB1_ID  
VSS  
Voltage range for USB VBUS comparator input  
Voltage range for USB VBUS comparator input  
Voltage range for the USB ID input  
Voltage range for the USB ID input  
Ground  
see(7)  
see(7)  
see(5)  
see(5)  
0
V
0
V
V
V
V
TJ  
Operating junction temperature range Extended  
Commercial  
-40  
0
105  
90  
°C  
°C  
(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This  
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.  
(2) Refer to Power-On-Hour (POH) Limits for limitations.  
(3) This value is without AVS. The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be  
read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn registers address, please refer to section Voltage  
and Thermal Manager (VTM) in the device TRM. The power supply should be adjustable over the following ranges for each required  
OPP:  
•
•
•
OPP_NOM: 0.9 V –1.1 V  
OPP_OD: 0.9 V –1.2 V  
OPP_TURBO: 0.9 V –1.24 V  
The AVS Voltages will be within the above specified ranges.  
(4) VDDS_DDR is required to still be powered with either DDR4 voltage ranges, even If DDR interface is unused.  
(5) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the  
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ωor greater than 100 kΩ. The terminal should  
be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any  
external voltage source.  
(6) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the  
appropriate resistor voltage divider source. For more information, see 节9.2.5, System Power Supply Monitor Design Guidelines.  
(7) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see 节9.2.3, USB Design  
Guidelines.  
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7.5 Operating Performance Points  
This section describes the operating conditions of the device. This section also contains the description of each  
operating performance point for processor clocks and device core clocks.  
Note  
The OPP voltage and frequency values may change following the silicon characterization result.  
表7-1 describes the maximum supported frequency per speed grade for the device.  
表7-1. Speed Grade Maximum Frequency  
MAXIMUM FREQUENCY (MHz)  
DEVICE(1)  
MPU  
1100  
1100  
1100  
1100  
MCU  
400  
400  
400  
400  
DMSC  
200  
GPU  
450  
450  
N/A  
N/A  
CBASS0  
250  
ICSSG  
250  
DDR4  
AM6548xxX  
AM6528xxX  
AM6546xxX  
AM6526xxX  
800 (DDR-1600)  
800 (DDR-1600)  
800 (DDR-1600)  
800 (DDR-1600)  
200  
250  
250  
250  
250  
200  
250  
200  
250  
(1) N/A stands for Not Applicable.  
7.5.1 Voltage and Core Clock Specifications  
表 7-2 through 表 7-3 defines the device Operating Performance Points (OPPs). As shown in these tables, each  
OPP defines a voltage and frequency pair for a given voltage domain supply.  
Note  
This device, when used in a production system, only supports one static OPP over the lifetime of the  
device. When designing a production system, a fixed OPP should be selected based on the maximum  
frequency required by the system. The corresponding OPP voltage must then be exclusively used by  
the device.  
表7-2. VDD_MPU0 OPPs  
VDD_MPU0  
VDD_MPU0 OPPs(1)  
MPU0  
MIN  
1.06  
1.14  
1.2  
NOM  
1.1  
MAX  
1.16  
1.26  
1.28  
OPP_NOM  
OPP_OD  
800 MHz  
1 GHz  
1.2  
OPP_TURBO  
1.24  
1.1 GHz  
(1) For additional details about supported AVS Voltages, refer to the footnotes associated with 节7.4, Recommended Operating  
Conditions.  
表7-3. VDD_MPU1 OPPs  
VDD_MPU1  
VDD_MPU1 OPPs(1)  
MPU1  
MIN  
1.06  
1.14  
1.2  
NOM  
1.1  
MAX  
1.16  
1.26  
1.28  
OPP_NOM  
OPP_OD  
800 MHz  
1 GHz  
1.2  
OPP_TURBO  
1.24  
1.1 GHz  
(1) For additional details about supported AVS Voltages, refer to the footnotes associated with 节7.4, Recommended Operating  
Conditions.  
表7-4 describes the standard processor clocks speed characteristics vs OPP of the device.  
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表7-4. Supported OPP vs Max Frequency  
OPP_NOM  
OPP_OD  
OPP_TURBO  
CLOCK(1) (2)  
MAXIMUM FREQUENCY (MHz) MAXIMUM FREQUENCY (MHz) MAXIMUM FREQUENCY (MHz)  
VD_CORE  
GPU  
450  
800 (DDR-1600)  
250  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
DDR4  
CBASS0  
ICSSG  
250  
VD_MPU0  
MPU0  
800  
800  
400  
200  
1000  
1000  
N/A  
1100  
1100  
N/A  
VD_MPU1  
MPU1  
VD_MCU  
MCU  
VD_WKUP  
DMSC  
N/A  
N/A  
(1) N/A stands for Not Applicable.  
(2) Maximum supported frequency is limited to the device speed grade (see 表7-1, Speed Grade Maximum Frequency).  
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7.6 Electrical Characteristics  
Note  
The interfaces or signals described in 节 7.6.1 through 节 7.6.5.1 correspond to the interfaces or  
signals available in multiplexing mode 0 (Primary Function).  
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical  
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC  
electrical characteristics are specified for the different multiplexing modes (Functions).  
7.6.1 I2C OPEN DRAIN DC Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
BALL NAMES in Mode 0: WKUP_I2C0_SCL / WKUP_I2C0_SDA / MCU_I2C0_SCL / MCU_I2C0_SDA  
BALL NUMBERS: AC7 /AD6 / AD7 / AD8  
I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 1.8 V  
VIH  
High-level input threshold  
0.7 ×  
VDDSHV0_WKUP  
V
V
VIL  
Low-level input threshold  
0.3 ×  
VDDSHV0_WKUP  
VIHSS Input high-level Steady State(1)  
VILSS Input low-level Steady State(2)  
0.70 ×  
VDDSHV0_WKUP  
V
0.30 ×  
V
VDDSHV0_WKUP  
VHYS  
IIN  
Hysteresis  
0.1 ×  
VDDSHV0_WKUP  
V
Input leakage current. This value represents the  
maximum current flowing in or out of the pin while the  
output driver is disabled and the input is swept from VSS  
to VDD.  
12  
12  
µA  
IOZ  
Total leakage current through the driver/receiver  
combination, which may include an internal pull-up or pull-  
down. This value represents the maximum current flowing  
in or out of the pin while the output driver is disabled, the  
pull-up or pull-down is inhibited, and the input is swept  
from VSS to VDD.  
µA  
VOL  
Low-level output voltage at 3-mA sink current  
0.2 ×  
V
VDDSHV0_WKUP  
I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 3.3 V  
VIH  
High-level input voltage  
0.7 ×  
VDDSHV0_WKUP  
V
V
VIL  
Low-level input voltage  
0.3 ×  
VDDSHV0_WKUP  
VIHSS Input high-level Steady State(1)  
VILSS Input low-level Steady State(2)  
0.70 ×  
VDDSHV0_WKUP  
V
0.21 ×  
V
VDDSHV0_WKUP  
VHYS  
IIN  
Hysteresis  
0.05 ×  
VDDSHV0_WKUP  
V
Input leakage current. This value represents the  
maximum current flowing in or out of the pin while the  
output driver is disabled and the input is swept from VSS  
to VDD.  
80  
µA  
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over recommended operating conditions (unless otherwise noted)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
IOZ  
Total leakage current through the driver/receiver  
combination, which may include an internal pull-up or pull-  
down. This value represents the maximum current flowing  
in or out of the pin while the output driver is disabled, the  
pull-up or pull-down is inhibited, and the input is swept  
from VSS to VDD.  
80  
µA  
VOL  
Low-level output voltage at 3-mA sink current  
0.4  
V
(1) Voltage Input High Steady State (VIHSS) should be maintained when the signal is not transitioning.  
(2) Voltage Input Low Steady State (VILSS) should be maintained when the signal is not transitioning.  
7.6.2 Analog OSC Buffers DC Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER(1)  
BALL NAMES: OSC1_XI / WKUP_OSC0_XI  
BALL NUMBERS: C22 / AD5  
MIN  
TYP  
MAX  
UNIT  
HIGH FREQUENCY OSCILLATOR  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
0.65 × VDDS(1)  
V
V
0.35 × VDDS(1)  
BALL NAMES: WKUP_LFOSC0_XI  
BALL NUMBERS: AE4  
LOW FREQUENCY OSCILLATOR  
VIH  
High-level input voltage  
0.65 ×  
VDDA_WKUP  
V
V
VIL  
Low-level input voltage  
0.35 ×  
VDDA_WKUP  
(1) VDDS stands for corresponding power supply. For WKUP_OSC0_XI, the corresponding power supply is VDDA_WKUP. For OSC1_XI,  
the corresponding power supply is VDDS_OSC1.  
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7.6.3 Analog ADC DC Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0] / MCU_ADC0_REFP/N / MCU_ADC1_AIN[7:0] / MCU_ADC1_REFP/N  
BALL NUMBERS: F4 / F5 / G3 / G4 / G5 / G6 / H2 / H3 / H4 / H5 / J1 / J2 / J3 / J4 / J5 / J6 / K2 / K3 / K4 / K5  
Analog Input  
VMCU_ADC0/1_REFP  
MCU_ADC0/1_REFP  
(0.5 ×  
VDDA_ADC_MCU) +  
0.25  
VDDA_ADC_MCU  
V
V
V
VMCU_ADC0/1_REFN  
MCU_ADC0/1_REFN  
0
(0.5 ×  
VDDA_ADC_MCU) -  
0.25  
VMCU_ADC0/1_REFP +  
MCU_ADC0/1_REFP  
+MCU_ADC0/1_REFN  
VDDA_ADC_MCU  
MCU_ADC0/1_REFN  
VMCU_ADC0/1_AIN[7:0]  
DNL  
Full-scale Input Range  
Differential Non-Linearity  
MCU_ADC0/1_REFN  
-1  
MCU_ADC0/1_REFP  
4
V
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
0.5  
±1  
±2  
±2  
LSB  
INL  
Integral Non-Linearity  
Gain Error  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
±4  
LSB  
LSB  
LSB  
LSBGAIN-ERROR  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
LSBOFFSET-ERROR  
Offset Error  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
CIN  
Input Sampling Capacitance  
Signal-to-Noise Ratio  
5.5  
70  
pF  
dB  
SNR  
Input Signal: 200 kHz sine wave  
at -0.5 dB Full Scale,  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
THD  
Total Harmonic Distortion  
Input Signal: 200 kHz sine wave  
at -0.5 dB Full Scale,  
75  
dB  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
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over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SFDR  
Spurious Free Dynamic Range  
Input Signal: 200 kHz sine wave  
at -0.5 dB Full Scale,  
80  
dB  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
SNR(PLUS)  
Signal-to-Noise Plus Distortion  
Input Signal: 200 kHz sine wave  
at -0.5 dB Full Scale,  
69  
dB  
MCU_ADC0/1_REFP =  
VDDA_MCU_ADC0/1,  
MCU_ADC0/1_REFN = VSS  
Rstatic(MCU_ADC0/1_REFP,  
Static Input Impedance of  
MCU_ADC0/1_REFP relative to  
MCU_ADC0/1_REFN  
2.2  
kΩ  
Ω
MCU_ADC0/1_REFN)  
Rdynamic(MCU_ADC0/1_REFP, Dynamic Input Impedance of  
[1/((65.97 × 10-12) ×  
fSMPL_CLK)](1)  
MCU_ADC0/1_REFP relative to  
MCU_ADC0/1_REFN)  
MCU_ADC0/1_REFN  
RMCU_ADC0/1_AIN[0:7]  
IIN  
Input Impedance of  
MCU_ADC0/1_AIN[7:0]  
f = input frequency  
[1/((65.97 × 10-12) ×  
fSMPL_CLK)]  
Ω
ADC0 Input Leakage  
ADC1 Input Leakage  
MCU_ADC0_AIN[7:0] = VSS  
-23  
27  
μA  
μA  
MCU_ADC0_AIN[7:0] =  
VDDA_MCU_ADC0  
IIN  
MCU_ADC1_AIN[7:0] = VSS  
-126  
572  
μA  
μA  
MCU_ADC1_AIN[7:0] =  
VDDA_MCU_ADC1  
Sampling Dynamics  
FSMPL_CLK  
tC  
SMPL_CLK Frequency  
Conversion Time  
60  
13  
MHz  
ADC0/1 SMPL_CLK  
Cycles  
tACQ  
Acquisition time  
2
257 ADC0/1 SMPL_CLK  
Cycles  
TR  
Sampling Rate  
ADC0/1 SMPL_CLK = 60 MHz  
4
MSPS  
dB  
CCISO  
Channel to Channel Isolation  
100  
(1) The MCU_ADC0/1_REFP and MCU_ADC0/1_REFN source impedance should be ≤to 1/10 × (Rdynamic(MCU_ADC0/1_REFP, MCU_ADC0/1_REFN)). For example, for a 60 MHz clock, this source  
should be ≤to 25 Ωon each reference input.  
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7.6.4 DPHY CSI2 Buffers DC Electrical Characteristics  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
MIN  
NOM  
MAX  
UNIT  
BALL NAMES in Mode 0: CSI0_RXN0 / CSI0_RXN3 / CSI0_RXN4 / CSI0_RXP0 / CSI0_RXP3 / CSI0_RXP4 / CSI0_RXN1 /  
CSI0_RXN2 / CSI0_RXP1 / CSI0_RXP2  
BALL NUMBERS: F24 / F26 / F28 / G24 / G25 / G26 / G27 / G28 / H25 / H27  
Low-Power Receiver (LP-RX)  
VIH  
High-level input voltage  
Low-level input voltage  
Hysteresis  
880  
25  
mV  
mV  
mV  
VIL  
550  
300  
VHYS  
Ultra-Low Power Receiver (ULP-RX)  
VITH  
High-level input voltage  
880  
25  
mV  
mV  
mV  
VITL-ULPM  
VHYS  
Low-level input voltage  
Hysteresis  
High Speed Receiver (HS-RX)  
VIDTH  
Differential input high threshold  
70  
mV  
mV  
mV  
mV  
mV  
mV  
VIDTL  
Differential input low threshold  
Maximum differential input voltage  
Single-ended input low voltage  
Single-ended input high voltage  
Common-mode voltage  
-70  
VIDMAX  
VILHS  
270  
-40  
70  
VIHHS  
460  
330  
VCMRXDC  
7.6.5 OLDI LVDS Buffers DC Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
1.8-V MODE  
BALL NAMES in Mode 0: OLDI0_A0P/N / OLDI0_A1P/N / OLDI0_A2P/N / OLDI0_A3P/N / OLDI0_CLKP/N  
BALL NUMBERS: J24 / J26 / J28 / K24 / K25 / K26 / K27 / K28 / L25 / L27  
OLDI LVDS TRANSMITTER  
VOH  
VOL  
VCM  
High Level Output Voltage  
1.3  
1.01  
1.25  
0.9  
1.6  
1.375  
35  
V
V
Differential Load = 100Ω  
Low Level Output Voltage  
0.9  
Common Mode Voltage (OLDI)  
Common Mode Voltage (sub-LVDS)  
1.125  
V
V
Difference in Common Mode Output  
mV  
ΔVCM  
Voltage, between high/low steady-states  
VOD  
Differential Output Voltage  
250  
100  
380  
200  
450  
300  
50  
mV  
mV  
mV  
Reduced Differential Output Voltage  
Difference in Differential Output Voltage,  
between high/low steady states  
ΔVOD  
IOS  
Output Short Circuit Current  
PAD/PADN = 0,  
Differential Load = 100Ω  
-5  
mA  
µA  
IOZ  
Output Tri-State Current  
PAD/PADN = 0/VDDS(1)  
-10  
4
40  
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表6-1,  
POWER [9] column.  
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7.6.5.1 LVCMOS Buffers DC Electrical Characteristics  
over recommended operating conditions (unless otherwise noted)(1)  
PARAMETER  
SPECIFIC BALL  
MIN  
TYP  
MAX UNI  
T
BALL NAMES: ALL LVCMOS IOs as defined in 表6-1, Pin Attributes except those listed in 节7.6.5.1, LVCMOS Buffers DC Electrical  
Characteristics  
BALL NUMBERS: ALL LVCMOS IOs as defined in 表6-1, Pin Attributes except those listed in 节7.6.5.1, LVCMOS Buffers DC Electrical  
Characteristics  
1.8-V MODE  
VIH  
VIL  
Input high-level threshold  
Input low-level threshold  
TCK (AA4)  
All other IOs  
TCK (AA4)  
0.60 × VDDS(1)  
0.65 × VDDS(1)  
V
V
0.30 ×  
VDDS(1)  
All other IOs  
0.35 ×  
VDDS(1)  
VIHSS  
VILSS  
Input high-level Steady State  
Input low-level Steady State  
0.75 × VDDS(1)  
V
V
0.35 ×  
VDDS(1)  
VHYS  
Input hysteresis voltage  
TCK (AA4)  
400  
50  
mV  
PORz (E19),  
MCU_PORz (W5),  
MCU_BYP_POR (V5)  
All other IOs  
100  
VDDS(1) - 0.1  
VDDS(1) - 0.2  
VDDS(1) - 0.3  
VDDS(1) - 0.4  
VOH  
VOL  
IIN  
Output high-level threshold  
Output low-level threshold  
IOH = 100µA  
IOH = 2mA  
IOH = 4mA  
IOH = 6mA  
IOL = 100µA  
IOL = 2mA  
IOL = 4mA  
IOL = 6mA  
V
V
0.1  
0.2  
0.3  
0.4  
Input leakage current, pull-up or pull-down  
inhibited  
11.5 µA  
Input leakage current, pull-down enabled, VI =  
VDDS(1)  
65  
64  
96  
97  
153  
Input leakage current, pull-up enabled, VI = VSS  
154  
IOZ  
Total leakage current through the driver/receiver  
combination, which may include an internal pull-  
up or pull-down. This value represents the  
maximum current flowing in or out of the pin  
while the output driver is disabled, the pull-up or  
pull-down is inhibited, and the input is swept  
from VSS to VDD.  
11.5 µA  
3.3-V MODE  
TCK (AA4)  
2
MMC0_*, MMC1_*  
0.625 *  
VDDSHVn  
VIH  
Input high-level threshold  
V
All other IOs  
2
TCK (AA4)  
0.7  
MMC0_*, MMC1_*  
0.25 *  
VDDSHVn  
VIL  
Input low-level threshold  
V
All other IOs  
0.8  
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over recommended operating conditions (unless otherwise noted)(1)  
PARAMETER  
SPECIFIC BALL  
MIN  
TYP  
MAX UNI  
T
VIHSS  
VILSS  
VHYS  
Input high-level Steady State  
Input low-level Steady State  
Input hysteresis voltage  
2.00  
V
0.75  
V
TCK (AA4)  
400  
50  
mV  
PORz (E19),  
MCU_PORz (W5),  
MCU_BYP_POR (V5)  
All other IOs  
100  
VDDS(1) - 0.1  
VDDS(1) - 0.2  
VDDS(1) - 0.3  
VDDS(1) - 0.45  
VOH  
VOL  
IIN  
Output high-level threshold  
Output low-level threshold  
IOH = 100µA  
IOH = 2mA  
IOH = 4mA  
IOH = 6mA  
IOL = 100µA  
IOL = 2mA  
IOL = 4mA  
IOL = 6mA  
V
V
0.1  
0.2  
0.3  
0.45  
Input leakage current, pull-up or pull-down  
inhibited  
64 µA  
Input leakage current, pull-down enabled, VI =  
VDDS(1)  
67  
63  
100.7  
100.3  
198  
Input leakage current, pull-up enabled, VI = VSS  
160  
64 µA  
IOZ  
Total leakage current through the driver/receiver  
combination, which may include an internal pull-  
up or pull-down. This value represents the  
maximum current flowing in or out of the pin  
while the output driver is disabled, the pull-up or  
pull-down is inhibited, and the input is swept  
from VSS to VDD.  
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see 表6-1,  
Pin Attributes, POWER [9] column.  
7.6.6 USBHS Buffers DC Electrical Characteristics  
Note  
USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0  
Specification dated April 27, 2000 including ECNs and Errata as applicable.  
7.6.7 SERDES Buffers DC Electrical Characteristics  
Note  
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base  
Specification Revision 3.1.  
Note  
USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative  
Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26,  
2013.  
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7.7 VPP Specifications for One-Time Programmable (OTP) eFuses  
This section specifies the operating conditions required for programming the OTP eFuses and is applicable only  
for High-Security Devices.  
7.7.1 Recommended Operating Conditions for OTP eFuse Programming  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER(2)  
DESCRIPTION  
MIN  
NOM  
See 节7.4  
MAX  
UNIT  
VDD_MCU  
Supply voltage range for the core domain  
during OTP operation; OPP NOM (BOOT)  
V
VPP_CORE  
VPP_MCU  
Supply voltage range for the eFuse ROM  
domain during normal operation  
NC  
NC  
NC  
1.8  
V
V
V
V
Supply voltage range for the eFuse ROM  
domain during OTP programming(1)  
Supply voltage range for the eFuse ROM  
domain during normal operation  
Supply voltage range for the eFuse ROM  
domain during OTP programming(1)  
1.71  
0
1.89  
I(VPP_MCU)  
Tj  
100  
85  
mA  
°C  
Temperature (junction)  
25  
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family  
meet the supply voltage range needed for VPP_MCU.  
(2) NC stands for No Connect.  
7.7.2 Hardware Requirements  
The following hardware requirements must be met when programming keys in the OTP eFuses:  
• The VPP_MCU power supply must be disabled when not programming OTP registers.  
• The VPP_MCU power supply must be ramped up after the proper device power-up sequence (for more  
details, see 节7.9.2, Power Supply Sequencing).  
7.7.3 Programming Sequence  
Programming sequence for OTP eFuses:  
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP_MCU terminal  
during power up and normal operation.  
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP  
software package).  
• Apply the voltage on the VPP_MCU terminal according to the specification in 节7.7.1.  
• Run the software that programs the OTP registers.  
• After validating the content of the OTP registers, remove the voltage from the VPP_MCU terminal.  
7.7.4 Impact to Your Hardware Warranty  
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that the  
e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step.  
Further the TI Device may fail to secure boot if the error code correction check fails for the Production Keys or if  
the image is not signed and optionally encrypted with the current active Production Keys. These types of  
situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices conformed  
to their specifications prior to the attempted e-Fuse.  
CONSEQUENTLY, TI WILL HAVE NO LIABILITY (WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT  
HAVE BEEN e-FUSED WITH SECURITY KEYS.  
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7.8 Thermal Resistance Characteristics  
This section provides the thermal resistance characteristics used on this device.  
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or below  
the TJ value identified in 节7.4, Recommended Operating Conditions.  
7.8.1 Thermal Resistance Characteristics  
It is recommended to perform thermal simulations at the system level with the worst case device power consumption  
ACD  
AIR FLOW  
(m/s)(2)  
NO.  
NAME  
RΘJC  
DESCRIPTION  
°C/W(1) (3)  
T1  
0.2  
3.1  
12.8  
7.4  
6.5  
6
N/A  
N/A  
0
Junction-to-case  
Junction-to-board  
Junction-to-free air  
T2  
RΘJB  
T3  
T4  
1
RΘJA  
T5  
Junction-to-moving air  
2
T6  
3
T7  
0.1  
0.1  
0.1  
0.1  
2.9  
2.4  
2.3  
2.3  
0
T8  
1
Junction-to-package top  
ΨJT  
T9  
2
T10  
T11  
T12  
T13  
T14  
3
0
1
Junction-to-board  
ΨJB  
2
3
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a  
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/  
JEDEC standards:  
•
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Packages  
(2) m/s = meters per second.  
(3) °C/W = degrees Celsius per watt.  
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7.9 Timing and Switching Characteristics  
Note  
The Timing Requirements and Switching Characteristics values may change following the silicon  
characterization result.  
Note  
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,  
unless specific instructions are given otherwise.  
7.9.1 Timing Parameters and Information  
The timing parameter symbols used in 节 7.9 are created in accordance with JEDEC Standard 100. To shorten  
the symbols, some pin names and other related terminologies have been abbreviated in 表7-5:  
表7-5. Timing Parameters Subscripts  
SYMBOL  
PARAMETER  
c
d
Cycle time (period)  
Delay time  
dis  
en  
h
Disable time  
Enable time  
Hold time  
su  
START  
t
Setup time  
Start bit  
Transition time  
Valid time  
v
w
Pulse duration (width)  
Unknown, changing, or don't care level  
Fall time  
X
F
H
High  
L
Low  
R
Rise time  
V
Valid  
IV  
AE  
FE  
LE  
Z
Invalid  
Active Edge  
First Edge  
Last Edge  
High impedance  
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7.9.2 Power Supply Sequencing  
This section describes the power-up sequence required to ensure proper device operation. The power supply  
names described in this section comprise a superset of a family of compatible devices. Some members of this  
family will not include a subset of these power supplies and their associated device modules.  
Note  
All timing requirements and switching characteristics in 节 7.9.3 should be strictly followed unless  
otherwise specified.  
7.9.2.1 Power Supply Slew Rate Requirement  
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the  
maximum slew rate of supplies to be less than 100 mV/μs. For instance, as shown in 图 7-2, TI recommends  
having the supply ramp slew for a 1.8-V supply of more than 18 μs.  
图7-2 describes the Power Supply Slew Rate Requirement of the device.  
Supply value  
t
slew rate < 100 mV/µs  
slew > (supply value) / (100 mV/µs)  
or  
supply value x 10 µs  
SPRSP08_ELCH_06  
图7-2. Power Supply Slew and Slew Rate  
7.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement  
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the  
maximum slew rate of VDDA_1P8_SERDES0 supplies to be less than 40 mV/μs. For instance, as shown in 图  
7-3, TI recommends having the supply ramp slew for a 1.8-V supply of more than 45 μs.  
图7-3 describes the VDDA_1P8_SERDES0 Supply Slew Rate Requirement of the device.  
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Supply value  
t
slew rate < 40 mV/µs  
slew > (supply value) / (40 mV/µs)  
or  
supply value x 25 µs  
SPRSP08_ELCH_11  
图7-3. VDDA_1P8_SERDES0 Supply Slew and Slew Rate  
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7.9.2.3 Power-Up Sequencing  
图7-4 describes the Power-Up Sequencing using On Chip Power-on-reset (POR) of the device.  
VDDA_3P3_IOLDO_WKUP,  
VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1,  
VDDA_3P3_SDIO, VDDA_3P3_USB  
VDDS0_WKUP(2), VDDS1_WKUP(2), VDDS2_WKUP(2), VDDS0(2),  
VDDS1(2),VDDS2(2), VDDS3(2), VDDS4(2), VDDS5(2), VDDS6(2),  
VDDS7(2), VDDS8(2), VDDA_1P8_CSI0, VDDA_1P8_OLDI0,  
VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE,  
VDDA_PLL0_DDR, VDDA_PLL1_DDR, VDDA_PLL_DSS,  
VDDA_PLL_MPU0, VDDA_PLL_MPU1, VDDA_PLL_PER0,  
VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP,  
VDDA_SRAM_CORE0, VDDA_SRAM_CORE1, VDDA_SRAM_MPU0,  
VDDA_SRAM_MPU1, VDDA_WKUP, VDDS_OSC1  
VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP,  
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4,  
VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8  
Note 6  
VDDS_DDR  
Note 10  
VDD_WKUP0, VDD_WKUP1  
VDD_MCU  
VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1  
VDD_MPU0, VDD_MPU1  
WKUP_OSC0_XI, WKUP_OSC0_XO(12)  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO(3)(12)  
(optional)  
OSC1_XI, OSC1_XO(9)(12)  
(optional)  
Note 7  
PORz, MCU_PORz(4)  
PORz_OUT, MCU_PORz_OUT(11)  
MCU_BYP_POR  
Note 8  
RESETz, MCU_RESETz  
RESETSTATz, MCU_RESETSTATz  
SPRSP08_ELCH_03  
图7-4. Power-Up Sequencing using On Chip Power-on-reset (POR)  
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图 7-5 describes the Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip POR  
circuit of the device.  
VDDA_3P3_IOLDO_WKUP,  
VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1,  
VDDA_3P3_SDIO, VDDA_3P3_USB  
VDDS0_WKUP(2), VDDS1_WKUP(2), VDDS2_WKUP(2), VDDS0(2)  
VDDS1(2),VDDS2(2), VDDS3(2), VDDS4(2), VDDS5(2), VDDS6(2)  
,
,
VDDS7(2), VDDS8(2), VDDA_1P8_CSI0, VDDA_1P8_OLDI0,  
VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE,  
VDDA_PLL0_DDR, VDDA_PLL1_DDR, VDDA_PLL_DSS,  
VDDA_PLL_MPU0, VDDA_PLL_MPU1, VDDA_PLL_PER0,  
VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP,  
VDDA_SRAM_CORE0, VDDA_SRAM_CORE1, VDDA_SRAM_MPU0,  
VDDA_SRAM_MPU1, VDDA_WKUP, VDDS_OSC1  
VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP,  
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4,  
VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8  
Note 6  
VDDS_DDR  
VDD_WKUP0, VDD_WKUP1  
VDD_MCU  
Note 11  
VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1  
VDD_MPU0, VDD_MPU1  
WKUP_OSC0_XI, WKUP_OSC0_XO(13)  
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO(3)(13)  
(optional)  
OSC1_XI, OSC1_XO(9)(13)  
(optional)  
PORz, MCU_PORz(4)  
PORz_OUT, MCU_PORz_OUT(12)  
Note 7  
Note 8  
MCU_BYP_POR(5)  
RESETz, MCU_RESETz  
RESETSTATz, MCU_RESETSTATz  
SPRSP08_ELCH_04  
图7-5. Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip POR circuit  
7.9.2.4 Power-Down Sequencing  
A typical power down sequence is to have the Power-on-Reset asserted, clock shut down, and ramp down all  
the power supplies sequentially in the exact reverse order of the power-up sequencing. In other words, the  
power supply that has been ramped up first should be the last one that is ramped down.  
For AM654x/AM652x, there are no specific power-down sequencing requirements, except for asserting Power-  
on-Reset before ramping down the rails while bypassing internal POR.  
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7.9.3 System Timing  
For more details about features and additional description information on the subsystem multiplexing signals,  
see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-6. System Timing Conditions  
PARAMETER  
MIN  
0.5  
3
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
5
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30  
7.9.3.1 Reset Electrical Data/Timing  
表7-7, 表7-8, 图7-6, 图7-7, and 图7-8 present the reset timing requirements and switching characteristics.  
表7-7. Reset Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PORz Pin  
RST1 tw(PORzL)  
Pulse Width minimum, PORz low  
Hold time, PORz active (low) after all supplies valid  
RESETz Pin  
2000  
ns  
ns  
RST2 th(SUPPLIES VALID - PORz)  
2000000  
RST5 tw(RESETzL)  
Pulse Width minimum, RESETz low  
MCU_PORz Pin  
400  
ns  
RST13 tw(MCU_PORzL)  
Pulse Width minimum, MCU_PORz  
Hold time, MCU_PORz active (low) after all supplies valid  
2000  
ns  
ns  
RST8 th(SUPPLIES VALID -  
2000000  
MCU_PORz)  
MCU_RESETz Pin  
Pulse Width minimum, MCU_RESETz  
MCU_BYP_POR Pin  
RST9 tw(MCU_RESETzL)  
400  
ns  
ns  
RST12 tsu(MCU_BYP_POR-MCU_PORz) Setup time, MCU_BYP_POR active (high) before all supplies are  
valid  
1000000  
表7-8. Reset Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PORz Pin  
RST3 td(PORz-PORz_OUT low)  
RST4 td(PORz-PORz_OUT high)  
Delay time, PORz active (low) to PORz_OUT active (low)  
Delay time, PORz inactive (high) to PORz_OUT inactive (high)  
RESETz Pin  
0
0
ns  
ns  
RST6 td(RESETz-RESETSTATz low)  
RST7 td(RESETz-RESETSTATz high)  
Delay time, RESETz active (low) to RESETSTATz active (low)  
4106  
ns  
ns  
Delay time, RESETz inactive (high) to RESETSTATz inactive  
(high)  
380000  
MCU_RESETSTATz Pin  
RST10 td(MCU_RESETz-  
Delay time, MCU_RESETz active (low) to MCU_RESETSTATz  
active (low)  
4106  
ns  
ns  
MCU_RESETSTATz low)  
RST11 td(MCU_RESETz-  
Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz  
inactive (high)  
289000  
MCU_RESETSTATz high)  
MCU_PORz Pin  
RST14 td(MCU_PORz-MCU_PORz_OUT Delay time, MCU_PORz active (low) to MCU_PORz_OUT active  
0
0
ns  
ns  
(low)  
low)  
RST15 td(MCU_PORz-MCU_PORz_OUT Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT  
inactive (high)  
high)  
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RST1  
PORz  
RST4  
RST3  
PORz_OUT  
All Supplies Valid  
RST2  
RST13  
RST8  
MCU_PORz  
RST15  
RST14  
MCU_PORz_OUT  
RST12  
MCU_BYP_POR  
SPRSP08_PORz_Reset_Timing  
图7-6. PORz Reset Timing  
RST5  
RESETz  
RST7  
RST6  
RESETSTATz  
SPRSP08_RESETz_Timing  
图7-7. RESETz and RESETSTATz Timing  
RST9  
MCU_RESETz  
RST11  
RST10  
MCU_RESETSTATz  
SPRSP08__MCU_RESETz_Timing  
图7-8. MCU_RESETz and MCU_RESETSTATz Timing  
表7-9 and 图7-9 present the boot configuration timing requirements.  
表7-9. Boot Configuration Timing Requirements  
NO.  
BC1  
BC2  
BC3  
PARAMETER  
MIN  
2000  
0
MAX  
UNIT  
ns  
tsu(BOOTMODE-PORz)  
th(PORz - BOOTMODE)  
Setup time, All Bootmode pins active to PORz inactive (high)  
Hold time, All Bootmode pins active after PORz inactive (high)  
ns  
tsu(MCU_BOOTMODE-MCU_PORz) Setup time, All Bootmode pins active to MCU_PORz inactive  
(high)  
2000  
ns  
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表7-9. Boot Configuration Timing Requirements (continued)  
NO.  
PARAMETER  
MIN  
MAX  
UNIT  
BC4  
th(MCU_PORz -  
Hold time, All Bootmode pins active after MCU_PORz inactive  
(high)  
0
ns  
MCU_BOOTMODE)  
BC1  
PORz  
BOOTMODE[18:00]  
BC2  
BC3  
MCU_PORz  
MCU_BOOTMODE[09:00]  
BC4  
图7-9. Boot Configuration Timing  
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7.9.3.2 Safety Signal Timing  
Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn and  
SOC_SAFETY_ERRORn.  
表7-10. MCU_SAFETY_ERRORn Switching Characteristics  
see 图7-10  
NO.  
PARAMETER  
MIN  
MAX UNIT  
SFTY1 tw(MCU_SAFETY_ERRORn)  
Pulse width, MCU_SAFETY_ERRORn active  
Delay time, ERROR CONDITION to  
P*R(1) (2)  
ns  
SFTY2 td (ERROR_CONDITION-MCU_SAFETY_ERRORnL) MCU_SAFETY_ERRORn  
active  
50*P(1)  
ns  
(1) P = ESM functional clock.  
(2) R = Error Pin Counter Pre-Load Register count value.  
Internal Error Condition  
(Active High)  
SFTY1  
SFTY2  
MCU_SAFETY_ERRORn  
(PWM Mode Disabled)  
图7-10. MCU_SAFETY_ERRORn Switching Characteristics  
表7-11. SOC_SAFETY_ERRORn Switching Characteristics  
see 图7-11  
NO.  
PARAMETER  
MIN  
MAX UNIT  
SFTY3 tw(SOC_SAFETY_ERRORn)  
Pulse width,SOC_SAFETY_ERRORn active  
Delay time, ERROR CONDITION to  
P*R(1) (2)  
ns  
SFTY4 td (ERROR_CONDITION-SOC_SAFETY_ERRORnL) SOC_SAFETY_ERRORn  
active  
50*P(1)  
ns  
(1) P = ESM functional clock.  
(2) R = Error Pin Counter Pre-Load Register count value.  
Internal Error Condition  
(Active High)  
SFTY3  
SFTY4  
SOC_SAFETY_ERRORn  
(PWM Mode Disabled)  
图7-11. SOC_SAFETY_ERRORn Switching Characteristics  
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7.9.3.3 Clock Timing  
Tables and figures provided in this section define timing requirements and switching characteristics for clock  
signals.  
表7-12. Clock Timing Requirements  
see 图7-12  
NO.  
MIN  
18.52  
MAX UNIT  
CLK1 tc(EXT_REFCLK1)  
CLK2 tw(EXT_REFCLK1H)  
CLK3 tw(EXT_REFCLK1L)  
CLK13 tc(MCU_EXT_REFCLK0)  
CLK14 tw(MCU_EXT_REFCLK0H)  
CLK15 tw(MCU_EXT_REFCLK0L)  
Cycle time, EXT_REFCLK1  
ns  
Pulse Duration, EXT_REFCLK1 high  
Pulse Duration, EXT_REFCLK1 low  
Cycle time, MCU_EXT_REFCLK0  
Pulse Duration, MCU_EXT_REFCLK0 high  
Pulse Duration, MCU_EXT_REFCLK0 low  
E*0.45(1)  
E*0.45(1)  
18.52  
E*0.55(1)  
ns  
ns  
ns  
ns  
ns  
E*0.55(1)  
F*0.45(2)  
F*0.45(2)  
F*0.55(2)  
F*0.55(2)  
(1) E = EXT_REFCLK1 cycle time.  
(2) F = MCU_EXT_REFCLK0 cycle time.  
图7-12. Clock Timing Requirements  
表7-13. Clock Switching Characteristics  
see 图7-13  
NO.  
PARAMETER  
MIN  
6
MAX UNIT  
CLK4 tc(SYSCLKOUT0)  
CLK5 tw(SYSCLKOUT0H)  
CLK6 tw(SYSCLKOUT0L)  
CLK7 tc(OBSCLK0)  
Cycle time minimum,SYSCLKOUT0  
Pulse Duration minimum, SYSCLKOUT0 high  
Pulse Duration minimum, SYSCLKOUT0 low  
Cycle time minimum, OBSCLK0  
ns  
A*0.4(1)  
A*0.4(1)  
5
A*0.6(1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A*0.6(1)  
CLK8 tw(OBSCLK0H)  
CLK9 tw(OBSCLK0L)  
CLK10 tc(CLKOUT0)  
Pulse Duration minimum, OBSCLK0 high  
Pulse Duration minimum,OBSCLK0 low  
Cycle time minimum, MCU_CLKOUT0  
Pulse Duration minimum, MCU_CLKOUT0 high  
Pulse Duration minimum,MCU_CLKOUT0 low  
Cycle time minimum,MCU_SYSCLKOUT0  
B*0.45(2)  
B*0.45(2)  
20  
B*0.55(2)  
B*0.55(2)  
40  
CLK11 tw(CLKOUT0H)  
CLK12 tw(CLKOUT0L)  
CLK16 tc(MCU_SYSCLKOUT0)  
C*0.4(3)  
C*0.4(3)  
6
C*0.6(3)  
C*0.6(3)  
Pulse Duration minimum, MCU_SYSCLKOUT0  
high  
CLK17 tw(MCU_SYSCLKOUT0H)  
A*0.4(1)  
A*0.6(1)  
A*0.6(1)  
ns  
CLK18 tw(MCU_SYSCLKOUT0L)  
CLK19 tc(MCU_OBSCLK0)  
CLK20 tw(MCU_OBSCLK0H)  
CLK21 tw(MCU_OBSCLK0L)  
Pulse Duration minimum, MCU_SYSCLKOUT0 low  
Cycle time minimum, MCU_OBSCLK0  
A*0.4(1)  
5
ns  
ns  
ns  
ns  
Pulse Duration minimum, MCU_OBSCLK0 high  
Pulse Duration minimum,MCU_OBSCLK0 low  
B*0.45(2)  
B*0.45(2)  
B*0.55(2)  
B*0.55(2)  
(1) A = SYSCLKOUT0 cycle time in MAIN domain; A = MCU_SYSCLKOUT0 in MCU domain.  
(2) B = OBSCLK0 cycle time in MAIN domain; B = MCU_OBSCLK0 in MCU domain.  
(3) C = MCU_CLKOUT0 cycle time.  
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图7-13. Clock Switching Characteristics  
7.9.4 Clock Specifications  
7.9.4.1 Input Clocks / Oscillators  
Various external clock inputs are needed to drive the device. Summary of these input clock signals are:  
• OSC1_XO/OSC1_XI —Еxternal main crystal interface pins connected to internal oscillator which sources  
reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-  
frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.  
• WKUP_OSC0_XO/WKUP_OSC0_XI —Еxternal main crystal interface pins connected to internal oscillator  
which sources reference clock and provides reference clock to PLLs within MCU domain and MAIN domain.  
• WKUP_LFOSC_XO/WKUP_LFOSC_XI —External main crystal interface pins connected to internal oscillator  
which sources reference clock provides a clock for low power operation in deeper sleep modes.  
• MCU_EXT_REFCLK0 —Optional external system clock input (MCU domain).  
• EXT_REFCLK1—Optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and MCASP  
can be sourced by EXT_REFCLK1 (sourced externally).  
• SERDES0_REFCLK P/N and SERDES1_REFCLK P/N —SerDes reference clock for PCIe or Optional  
USB3.0 PHY.  
• MCU_CPTS0_RFT_CLK —CPTS reference clock inputs for MCU_CPTS0_RFT_CLK.  
• CPTS_RFT0_CLK —CPTS reference clock inputs for CPTS0_RFT_CLK.  
• VOUT1_EXTPCLKIN —Optional for the DPI1 Port of DSS.  
• REFCLK0 P/N and REFCLK1 P/N —There are 2 differential clock output pins to support 2 PCIe devices.  
图7-14 shows the external input clock sources to peripherals.  
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DEVICE  
Selects Main PLL output divide-by-4  
SYSCLK0  
Optional pins to provide reference clock input to the PLLs.  
Observation clock output for MCU Domain clocks  
MCU_SYSCLKOUT0  
MCU_OBSCLK0  
WKUP_OSC0_XI  
Еxternal main crystal interface pins connected to  
internal oscillator whichsources reference clock.  
Provides reference clock to PLLs within WKUP and MAIN domain.  
WKUP_OSC0_XO  
WKUP_LFOSC0_XI  
Optional external low frequency crystal interface pins connected  
to internal oscillator which provides a 32.768 kHz clock for  
low power operation in deeper sleep modes.  
WKUP_LFOSC0_XO  
OSC1_XI  
Optional external crystal interface pins connected to internal  
oscillator which sources reference clock. Provides reference clock to  
PLLs within MCU domain and MAIN domain. This high-frequency oscillator  
is used to provide audio clock frequencies to MCASPs.  
OSC1_XO  
JTAG Clock Input  
TCK  
EXT_REFCLK1  
Optional external System clock input (MAIN domain)  
MCU Warm Reset Input / Device Warm Reset Input  
MCU_RESETz/ RESETz  
MCU_PORz / PORz  
MCU Power ON Reset / Device Power ON Reset  
Boot Mode Configuration / devices select  
BOOTMODE[18:00]  
MCU_BOOTMODE[09:00]  
DDR_CK0P/DDR_CK0N  
DDR_CK1P/DDR_CK1N  
MCU Boot Mode system clock speed and fail-safe boot device  
DDR Differential Clock outputs  
REFCLK0 P/N  
REFCLK1 P/N  
There are 2 differential clock output pins to support 2 PCIe  
devices  
Observation clock output for MAIN and MCU Domain clocks  
SerDes reference clock input for PCIe or Optional USB3SS0 PHY  
OBSCLK0  
SERDES0_REFCLK P/N  
SERDES1_REFCLK P/N  
MCU_CPTS0_RFT_CLK  
CPTS reference clock input for MCU_CPTS_RFT_CLK  
MCU_EXT_REFCLK0  
VOUT1_EXTPCLKIN  
CPTS0_RFT_CLK  
Optional external system clock input (MCU domain)  
Optional for the DPI1 Port of DSS  
CPTS reference clock input for CPTS_RFT_CLK  
SPRSP08_CLOCK_01  
图7-14. Input Clocks Interface  
For more information about Input clock interfaces, see the Clocking section in the device TRM.  
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7.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source  
图 7-15 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board  
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator  
operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd  
is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator  
performance with production crystal circuit components installed on preproduction PCBs.  
Device  
WKUP_OSC0_XO  
WKUP_OSC0_XI  
Rd  
(Optional)  
Crystal  
(Optional)  
Rbias  
Cf2  
Cf1  
PCB Ground  
SPRSP08_PCB_CLK_OSC_2  
图7-15. WKUP_OSC0 Crystal Implementation  
Note  
The load capacitors, Cf1 and Cf2 in the load capacitance equation (1) below, should be chosen such  
that the below equation is satisfied. CL in the equation is the load specified by the crystal  
manufacturer. All discrete components used to implement the oscillator circuit should be placed as  
close as possible to the associated oscillator WKUP_OSC0_XI, WKUP_OSC0_XO, and VSS pins.  
Cf1Cf2  
C
= (Cf1+Cf2)  
L
SPRS932_CLOCK_03  
(1)  
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-14 summarizes the  
required electrical constraints.  
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MAX UNIT  
表7-14. WKUP_OSC0 Crystal Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
fp  
Parallel resonance crystal frequency  
19.2, 20, 24, 25, 26, 27  
MHz  
pF  
Cf1  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Crystal ESR  
12  
12  
24  
Cf2  
24  
100  
7
pF  
ESR(Cf1,Cf2)  
CO  
Ω
Crystal shunt capacitance  
19.2 MHz, 20 MHz, 24  
MHz, 25 MHz, 26 MHz, 27  
MHz  
pF  
ESR = 30 Ω  
ESR = 40 Ω  
19.2 MHz, 20 MHz  
7
5
pF  
pF  
ESR = 50 Ω  
ESR = 60 Ω  
ESR = 80 Ω  
ESR = 100 Ω  
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
19.2 MHz, 20 MHz  
7
5
3
pF  
-
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
Not Supported  
19.2 MHz, 20 MHz  
pF  
-
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
Not Supported  
Not Supported  
19.2 MHz, 20 MHz  
pF  
-
24 MHz, 25 MHz, 26 MHz,  
27 MHz  
LM  
Crystal motional inductance for fp = 20 MHz  
Crystal motional capacitance  
10.16  
3.42  
mH  
fF  
CM  
fj(WKUP_OSC0_XI)  
Frequency accuracy, WKUP_OSC0_XI  
Ethernet RGMII and RMII  
not used  
±100 ppm  
Ethernet RGMII and RMII  
using derived clock  
±50  
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based  
on the worst case environment and expected life expectancy of the system.  
表7-15 details the switching characteristics of the oscillator and the requirements of the input clock.  
表7-15. WKUP_OSC0 Switching Characteristics –Crystal Mode  
NAME  
fp  
tsX  
DESCRIPTION  
Oscillation frequency  
Start-up time  
MIN  
TYP  
MAX  
UNIT  
MHz  
ms  
19.2, 20, 24, 25, 26, 27  
2(1)  
(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:  
Tsu = K×Lm/ (Ro-ESR) + Δt  
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K  
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.  
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VDD_WKUP (min.)  
VSS  
VDD_WKUP  
VDDA_WKUP (min.)  
VDDA_WKUP  
WKUP_OSC0_XO  
tsX  
VSS  
Time  
图7-16. WKUP_OSC0 Start-up Time  
7.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source  
图 7-17 shows the recommended oscillator connections when WKUP_OSC0 is connected to an LVCMOS  
square-wave digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to the  
WKUP_OSC0_XI pin. In this mode of operation, the WKUP_OSC0_XO pin is left unconnected and should not  
be used to source any external components.  
Device  
WKUP_OSC0_XO  
VSS  
WKUP_OSC0_XI  
NC  
PCB Ground  
SPRSP08_CLK_02  
图7-17. 1.8-V LVCMOS-Compatible Clock Input  
表7-16 summarizes the WKUP_OSC0 input clock electrical characteristics  
表7-16. WKUP_OSC0 Switching Characteristics –Crystal Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
f
Frequency  
19.2, 20, 24, 25, 26, 27  
CIN  
IIN  
Input capacitance  
Input current (3.3V mode)  
2.184  
4
2.384  
6
2.584  
10  
pF  
µA  
表7-17 details the WKUP_OSC0 input clock timing requirements.  
表7-17. WKUP_OSC0 Input Clock Timing Requirements  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
CK0  
1 / tc(WKUP_OSC0_XI) Frequency, WKUP_OSC0_XI  
19.2, 20, 24, 25, 26, 27  
MHz  
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表7-17. WKUP_OSC0 Input Clock Timing Requirements (continued)  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
CK1  
tw(WKUP_OSC0_XI)  
Pulse duration, WKUP_OSC0_XI low or high  
Period jitter, WKUP_OSC0_XI  
0.45 ×  
tc(WKUP_OSC0_XI)  
0.55 ×  
tc(WKUP_OSC0_XI)  
ns  
tj(WKUP_OSC0_XI)  
0.01 ×  
ns  
tc(WKUP_OSC0_XI)  
tR(WKUP_OSC0_XI)  
tF(WKUP_OSC0_XI)  
tj(WKUP_OSC0_XI)  
Rise time, WKUP_OSC0_XI  
Fall time, WKUP_OSC0_XI  
5
5
ns  
ns  
Frequency accuracy,  
WKUP_OSC0_XI  
Ethernet RGMII and RMII  
not used  
±100  
ppm  
Ethernet RGMII and RMII  
using derived clock  
±50  
CK0  
CK1  
CK1  
WKUP_OSC0_XI  
图7-18. WKUP_OSC0_XI Input Clock  
7.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source  
图 7-19 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board  
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator  
operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd  
is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator  
performance with production crystal circuit components installed on preproduction PCBs.  
Device  
OSC1_XO  
OSC1_XI  
Rd  
(Optional)  
Crystal  
(Optional)  
Rbias  
Cf2  
Cf1  
PCB Ground  
SPRSP08_PCB_CLK_OSC_1  
图7-19. OSC1 Crystal Implementation  
Note  
The load capacitors, Cf1 and Cf2 in 图 7-20, should be chosen such that the below equation is  
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components  
used to implement the oscillator circuit should be placed as close as possible to the associated  
oscillator OSC1_XI, OSC1_XO, and VSS pins.  
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Cf1Cf2  
= (Cf1+Cf2)  
C
L
SPRS932_CLOCK_03  
图7-20. Load Capacitance Equation  
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-18 summarizes the  
required electrical constraints.  
表7-18. OSC1 Crystal Electrical Characteristics  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX UNIT  
fp  
Parallel resonance crystal frequency  
19.2, 20, 24, 25, 26, 27  
MHz  
24 pF  
24 pF  
Cf1  
Cf2  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
12  
12  
ESR(Cf1,Cf2) Crystal ESR  
100  
Ω
pF  
pF  
pF  
pF  
-
CO  
Crystal shunt capacitance  
19.2 MHz, 20 MHz, 24 MHz, 25  
MHz, 26 MHz, 27 MHz  
7
ESR = 30 Ω  
ESR = 40 Ω  
19.2 MHz, 20 MHz  
7
5
ESR = 50 Ω  
ESR = 60 Ω  
ESR = 80 Ω  
ESR = 100 Ω  
24 MHz, 25 MHz, 26 MHz, 27  
MHz  
19.2 MHz, 20 MHz  
7
5
3
24 MHz, 25 MHz, 26 MHz, 27  
MHz  
Not Supported  
Not Supported  
Not Supported  
19.2 MHz, 20 MHz  
pF  
-
24 MHz, 25 MHz, 26 MHz, 27  
MHz  
19.2 MHz, 20 MHz  
pF  
-
24 MHz, 25 MHz, 26 MHz, 27  
MHz  
LM  
Crystal motional inductance for fp = 20 MHz  
10.16  
3.42  
mH  
fF  
CM  
Crystal motional capacitance  
Frequency accuracy, OSC1_XI  
fj(OSC1_XI)  
Ethernet RGMII and RMII not  
used  
±100  
±50  
ppm  
Ethernet RGMII and RMII using  
derived clock  
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based  
on the worst case environment and expected life expectancy of the system.  
表7-19 details the switching characteristics of the oscillator and the requirements of the input clock.  
表7-19. OSC1 Switching Characteristics –Crystal Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
ms  
fp  
Oscillation frequency  
Start-up time  
19.2, 20, 24, 25, 26, 27  
tsX  
2(1)  
(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:  
Tsu = K×Lm/ (Ro-ESR) + Δt  
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K  
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.  
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VDD_CORE (min.)  
VSS  
VDD_CORE  
VDDS_OSC1  
VDDS_OSC1 (min.)  
OSC1_XO  
tsX  
VSS  
Time  
图7-21. OSC1 Start-up Time  
7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source  
图 7-22 shows the recommended oscillator connections when OSC1 is connected to an LVCMOS square-wave  
digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to the OSC1_XI pin. In this mode  
of operation, the OSC1_XO pin is left unconnected and should not be used to source any external components.  
Device  
OSC1_XO  
VSS  
OSC1_XI  
NC  
PCB Ground  
SPRSP08_CLK_01  
图7-22. 1.8-V LVCMOS-Compatible Clock Input  
表7-20 summarizes the OSC1 input clock electrical characteristics.  
表7-20. OSC1 Switching Characteristics –Crystal Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
MHz  
f
Frequency  
19.2, 20, 24, 25, 26, 27  
CIN  
IIN  
Input capacitance  
Input current (3.3V mode)  
2.184  
4
2.384  
6
2.584  
10  
pF  
µA  
表7-21 details the OSC1 input clock timing requirements.  
表7-21. OSC1 Input Clock Timing Requirements  
NAME DESCRIPTION  
CK0 1 / tc(OSC1_XI)  
MIN  
TYP  
MAX  
UNIT  
Frequency, OSC1_XI  
19.2, 20, 24, 25, 26, 27  
MHz  
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表7-21. OSC1 Input Clock Timing Requirements (continued)  
NAME DESCRIPTION  
MIN  
TYP  
MAX  
0.55 ×  
UNIT  
CK1  
tw(OSC1_XI)  
Pulse duration, OSC1_XI low or high  
Period jitter, OSC1_XI  
0.45 ×  
tc(OSC1_XI)  
ns  
tc(OSC1_XI)  
tj(OSC1_XI)  
0.01 ×  
ns  
tc(OSC1_XI)  
tR(OSC1_XI)  
tF(OSC1_XI)  
tj(OSC1_XI)  
Rise time, OSC1_XI  
5
5
ns  
ns  
Fall time, OSC1_XI  
Frequency accuracy, OSC1_XI  
Ethernet RGMII and RMII  
not used  
±100  
ppm  
Ethernet RGMII and RMII  
using derived clock  
±50  
CK0  
CK1  
CK1  
OSC1_XI  
图7-23. OSC1_XI Input Clock  
7.9.4.1.5 Auxiliary OSC1 Not Used  
For more Information see 节6.5, Connections for Unused Pins.  
7.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source  
Note  
WKUP_LFOSC_XO/WKUP_LFOSC_XI - External main crystal interface pins connected to internal  
oscillator which sources reference clock provides a clock for low power operation in deeper sleep  
modes. For a list of supported low power modes for this device, please refer to Overview of Device  
Low-Power Modes section in the device TRM.  
图 7-24 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board  
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator  
operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd  
is a 0 ohm resistor. These resistors may be removed from production PCB designs after evaluating oscillator  
performance with production crystal circuit components installed on preproduction PCBs.  
Device  
WKUP_LFOSC0_XO  
WKUP_LFOSC0_XI  
Rd  
Crystal  
(Optional)  
(Optional)  
Rbias  
Cf2  
Cf1  
PCB Ground  
SPRSP08_PCB_CLK_OSC_3  
图7-24. WKUP_LFOSC0 Crystal Implementation  
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Note  
The load capacitors, Cf1 and Cf2 in 图 7-25, should be chosen such that the below equation is  
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components  
used to implement the oscillator circuit should be placed as close as possible to the associated  
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.  
Cf1Cf2  
C
= (Cf1+Cf2)  
L
SPRS932_CLOCK_03  
图7-25. Load Capacitance Equation  
The crystal must be in the fundamental mode of operation and parallel resonant. 表 7-22 summarizes the  
required electrical constraints  
表7-22. WKUP_LFOSC0 Crystal Electrical Characteristics  
NAME  
fp  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
Hz  
Parallel resonance crystal frequency  
32768  
Cf1  
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2  
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2  
12  
12  
24  
pF  
pF  
Cf2  
24  
1.35  
65  
Cshunt Shunt capacitance  
pF  
ESR  
Crystal effective series resistance  
kΩ  
When selecting a crystal, the system design must consider the temperature and aging characteristics of a based  
on the worst case environment and expected life expectancy of the system.  
表7-23 details the switching characteristics of the oscillator and the requirements of the input clock.  
表7-23. WKUP_LFOSC0 Switching Characteristics –Crystal Mode  
NAME  
fxtal  
tSX  
DESCRIPTION  
Oscillation frequency  
Start-up time  
MIN  
TYP  
32768  
MAX  
UNIT  
Hz  
s
(1)  
(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:  
Tsu = K×Lm/ (Ro-ESR) + Δt  
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K  
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.  
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VDD_WKUP (min.)  
VSS  
VDD_WKUP  
VDDA_WKUP (min.)  
VDDA_WKUP  
WKUP_LFOSC0_XO  
tsX  
VSS  
Time  
图7-26. WKUP_LFOSC0 Start-up Time  
7.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source  
Note  
WKUP_LFOSC_XO/WKUP_LFOSC_XI - External main crystal interface pins connected to internal  
oscillator which sources reference clock provides a clock for low power operation in deeper sleep  
modes. For a list of supported low power modes for this device, please refer to Overview of Device  
Low-Power Modes section in the device TRM.  
图 7-27 shows the recommended oscillator connections when WKUP_LFOSC0 is connected to an LVCMOS  
square-wave digital clock source. The 1.8-V LVCMOS-Compatible clock source is connected to the  
WKUP_LFOSC0_XI pin. In this mode of operation, the WKUP_LFOSC0_XO pin is left unconnected and should  
not be used to source any external components.  
Device  
WKUP_LFOSC0_XO  
VSS  
WKUP_LFOSC0_XI  
NC  
PCB Ground  
图7-27. 1.8-V LVCMOS-Compatible Clock Input  
表7-24 summarizes the WKUP_LFOSC0 input clock electrical characteristics.  
表7-24. WKUP_LFOSC0 Oscillator Input Clock Electrical Characteristics—Bypass Mode  
NAME  
DESCRIPTION  
MIN  
TYP  
MAX  
UNIT  
kHz  
ns  
CK0  
CK1  
1/tc(WKUP_LFOSC0_XI)  
tw(WKUP_LFOSC0_XI)  
Frequency, WKUP_LFOSC0_XI  
32.768  
Pulse duration, WKUP_LFOSC0_XI low or  
high  
0.45 ×  
tc(WKUP_LF  
0.55 ×  
tc(WKUP_LF  
OSC0_XI)  
OSC0_XI)  
CIN  
Input capacitance  
2.178  
2.378  
2.578  
pF  
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表7-24. WKUP_LFOSC0 Oscillator Input Clock Electrical Characteristics—Bypass Mode (continued)  
NAME  
DESCRIPTION  
Input current (3.3V mode)  
Start-up time  
MIN  
TYP  
MAX  
UNIT  
μA  
ms  
IIN  
4
6
10  
tsX  
see(1)  
(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in  
application mode and receives a wave. The switching time in this case is about 100 μs.  
CK0  
CK1  
CK1  
WKUP_LFOSC0_XI  
图7-28. WKUP_LFOSC0_XI Input Clock  
7.9.4.1.8 WKUP_LFOSC0 Not Used  
For more Information see 节6.5, Connections for Unused Pins.  
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7.9.4.2 Output Clocks  
The device provides several system clock outputs. Summary of these output clocks are as follows:  
• MCU_SYSCLKOUT0  
– SYSCLK0 of WKUP_PLLCTRL0 is divided by 4 and then sent out of the device as a LVCMOS clock signal  
(MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.  
• MCU_OBSCLK0  
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.  
• SYSCLKOUT0  
– SYSCLK0 from the MAIN_PLL controller is divided by 4 and then sent out of the device as a LVCMOS  
clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.  
• OBSCLK0  
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.  
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7.9.4.3 PLLs  
Power is supplied to the PLL by internal regulators that derive power from the off-chip power-supply.  
There are total nine Phase Locked Loops (PLLs) in the device:  
• MCU_PLL0 (MCU PLL) with WKUP_PLL_CTRL0: The MCU PLL —which is used to drive the switch fabrics,  
accelerators, and a majority of the peripheral clocks —requires a PLL controller to manage the various clock  
divisions, gating, and synchronization in WKUP domain and MCU domain.  
• MCU_PLL1 (CPSW PLL): The MCU_PLL1, which is used to drive the CPSW.  
• PLL0 (MAIN PLL) with PLL_CTRL0: The Main PLL —which is used to drive the switch fabrics, accelerators,  
and a majority of the peripheral clocks —requires a PLL controller to manage the various clock divisions,  
gating, and synchronization in MAIN domain.  
• PLL1 (PER0 PLL): The PER0 PLL, which is used to drive the Peripherals in MAIN Domain.  
• PLL2 (PER1 PLL): The PER1 PLL, which is used to drive the PRU_ICSSG.  
• PLL3 (DDR PLL): The DDR PLL is used to drive the DDR PHY for the DDRSS.  
• PLL4 (DSS PLL): The DSS PLL, which is used to drive the Display Subsystem.  
• PLL6 (ARM0 PLL): The ARM0 PLL, which is used to drive the ARM0.  
• PLL7 (ARM1 PLL): The ARM1 PLL, which is used to drive the ARM1.  
Most of the Device is driven by the output from the main PLL except the following items:  
• Arm subsystem has its own dedicated PLL.  
• MCU subsystem has its own dedicated PLL.  
• EMIF DDR subsystem has its own dedicated PLL to drive DDR PHY and DDRSS.  
• PRU_ICSSG has clocks sourced from several PLLs:  
– PER0 PLL to generate UART clock,  
– PER1 PLL to generate Core clock,  
– MAIN PLL to generate Industrial Ethernet Peripheral clock,  
– CPSW PLL to generate Ethernet clocks.  
• DSS has its own dedicated PLL, to generate Pixel Clock.  
• PCIESS require separate reference clocks to drive SERDES PHYs.  
Note  
For more information, see the:  
• Device Configuration, Clocking, and PLLs sections of the device TRM  
• Peripherals and Display Subsystem Overview sections of the device TRM  
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit  
(PRU_ICSSG) section of the device TRM  
Note  
The input reference clock (OSC1_XI/OSC1_XO) are specified and the lock time is ensured by the PLL  
controller, as documented in the Device Configuration chapter of the device TRM.  
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图7-29 shows the power supply connectivity implemented in the device.  
MCU_PLL0  
(MCU PLL)  
PLL3  
(DDR PLL)  
VDDA_MCU  
VDDA_PLL0_DDR  
MCU_PLL1  
(CPSW PLL)  
PLL4  
(DSS PLL)  
VDDA_PLL_DSS  
VDDA_PLL_MPU0  
PLL0  
(MAIN PLL)  
VDDA_PLL_CORE  
PLL6  
(ARM0 PLL)  
PLL2  
(PER1 PLL)  
PLL1  
(PER0 PLL)  
PLL7  
(ARM1 PLL)  
VDDA_PLL_PER0  
VDDA_PLL_MPU1  
SPRSP08_PLL_PWR_01  
图7-29. PLL Power Supply Connectivity  
7.9.4.4 Recommended Clock and Control Signal Transition Behavior  
All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic  
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input transitions are  
more susceptible to glitches due to noise, and special care must be taken for slow input clocks.  
7.9.4.5 Module and Peripheral Clock Frequencies  
The maximum operating frequency associated with module functional and interface clocks internal to the device  
is managed by the DMSC firmware. For more details about the clocking structure for a specific module or  
peripheral, see Device Configurations chapter in the device TRM.  
节 7.9.5, Peripherals documents the maximum frequency associated with the peripheral clocks in and out of the  
device.  
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7.9.5 Peripherals  
7.9.5.1 VIN  
表7-26, 图7-30, and 图7-31 present timing requirements for LVDSRX interface.  
表7-25 presents timing conditions for LVDSRX.  
表7-25. LVDSRX Timing Conditions  
PARAMETER  
MODE  
MIN  
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
1.8 V  
3.3 V  
1.3  
1.5  
2.64  
2.64  
V/ns  
V/ns  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Mismatch Delay) Propagation delay mismatch across all traces  
50  
ps  
表7-26. Timing Requirements for LVDSRX  
NO.  
V1  
V2  
V3  
V4  
PARAMETER  
DESCRIPTION  
MIN  
5.76(1)  
0.45 × P(2)  
0.45 × P(2)  
MAX  
UNIT  
ns  
tc(PCLK)  
Cycle time, VIN0_PCLK  
tw(PCLKH)  
Pulse duration, VIN0_PCLK high  
Pulse duration, VIN0_PCLK low  
ns  
tw(PCLKL)  
ns  
tsu(PCLK-CTL/DATA)  
Input setup time, control (VIN0_HD, VIN0_VD) and data  
(VIN0_DATA[15:0]) valid to VIN0_PCLK transition  
ns  
2.42  
0.52  
V5  
th(CTL/DAT-PCLK)  
Input hold time, VIN0_PCLK transition to control (VIN0_HD,  
VIN0_VD) valid  
ns  
(1) For maximum frequency of 165 MHz  
(2) P = VIN0_PCLK period  
V2  
V1  
V3  
VIN0_PCLK  
CAL_CCDC_TIMINGS_01  
图7-30. LVDSRX Input Clock Signal  
VIN0_PCLK  
(Positive-edge clocking)  
VIN0_PCLK  
(Negative-edge clocking)  
V4  
V5  
VIN_DATA[15:0]  
CAL_CCDC_TIMINGS_02  
图7-31. LVDSRX Input Timings  
7.9.5.2 CPSW2G  
For more details about features and additional description information on the device Gigabit Ethernet MAC, see  
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
7.9.5.2.1 CPSW2G MDIO Interface Timings  
表7-28, 表7-29, and 图7-32 present timing requirements for MDIO.  
表7-27 presents timing conditions for CPSW2G MDIO.  
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表7-27. CPSW2G MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
表7-28. Timing Requirements for MDIO Input  
NO.  
PARAMETER  
MIN  
90  
0
MAX  
UNIT  
ns  
MDIO1 tsu(MDIO_MDC)  
MDIO2 th(MDIO_MDC)  
Setup time, MDIO_MDIO valid before MDIO_MDC high  
Hold time, MDIO_MDIO valid after MDIO_MDC high  
ns  
表7-29. Switching Characteristics Over Recommended Operating Conditions for MDIO Output  
NO.  
PARAMETER  
MIN  
400  
160  
160  
-150  
MAX  
UNIT  
MDIO3 tc(MDC)  
MDIO4 tw(MDCH)  
MDIO5 tw(MDCL)  
MDIO7 td(MDC_MDIO)  
Cycle time, MDIO_MDC  
ns  
Pulse Duration, MDIO_MDC high  
ns  
Pulse Duration, MDIO_MDC low  
ns  
Delay time, MDIO_MDC low to MDIO_MDIO valid  
150  
ns  
MDIO3  
MDIO4  
MDIO5  
MDIO[x]_MDC  
MDIO1  
MDIO2  
MDIO[x]_MDIO  
(input)  
MDIO7  
MDIO[x]_MDIO  
(output)  
CPSW2G_MDIO_TIMING_01  
图7-32. CPSW2G MDIO Diagrams Receive and Transmit  
7.9.5.2.2 CPSW2G RMII Timings  
节7.9.5.2.2.1, 节7.9.5.2.2.2, 图7-33, and 图7-34 present timing requirements for CPSW2G RMII receive.  
表7-30 presents timing conditions for CPSW2G RMII.  
表7-30. CPSW2G RMII Timing Conditions  
PARAMETER  
MIN  
0.9  
3
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
25  
7.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
19.999  
TYP  
MAX  
20.001  
UNIT  
ns  
RMII1 tc(REF_CLK)  
Cycle time, REF_CLK  
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NO.  
PARAMETER  
DESCRIPTION  
MIN  
7
TYP  
MAX  
UNIT  
ns  
RMII2 tw(REF_CLKH)  
RMII3 tw(REF_CLKL)  
Pulse Duration, REF_CLK High  
Pulse Duration, REF_CLK Low  
13  
13  
7
ns  
RMII1  
RMII2  
RMII[x]_REFCLK  
(input)  
RMII3  
图7-33. RMII[x]_REFCLK Timing - RMII Mode  
7.9.5.2.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
4
TYP  
MAX  
UNIT  
ns  
RMII4 tsu(RXD-REF_CLK)  
Setup time, RXD[1:0] valid before REF_CLK  
tsu(CRS_DV-REF_CLK) Setup time, CRS_DV valid before REF_CLK  
4
ns  
tsu(RX_ER-REF_CLK)  
RMII5 th(REF_CLK-RXD)  
th(REF_CLK-CRS_DV)  
Setup time, RX_ER valid before REF_CLK  
Hold time RXD[1:0] valid after REF_CLK  
Hold time, CRS_DV valid after REF_CLK  
Hold time, RX_ER valid after REF_CLK  
4
ns  
2
ns  
2
ns  
th(REF_CLK-RX_ER)  
2
ns  
RMII4  
RMII5  
RMII[x]_REFCLK (input)  
RMII[x]_RXD[1:0],  
RMII[x]_CRS_DV, RMII[x]_RXER (inputs)  
SPRSP08_CPSW2G_RMIIRX  
图7-34. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode  
节7.9.5.2.2.3, and 节7.9.5.2.2.3 present switching characteristics for CPSW2G RMII Transmit.  
7.9.5.2.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode  
NO.  
PARAMETER  
MIN  
2
TYP  
MAX  
UNIT  
ns  
RMII6 td(REF_CLK-TXD)  
td(REF_CLK-TXEN)  
Delay time, REF_CLK High to TXD[1:0] valid  
Delay time, REF_CLK to TXEN valid  
13  
13  
2
ns  
RMII6  
RMII[x]_REF_CLK  
RMII[x]_TXD[1:0], RMII[x]_TX_EN  
图7-35. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics –RMII Mode  
7.9.5.2.3 CPSW2G RGMII Timings  
节7.9.5.2.3.1, 节7.9.5.2.3.2, and 图7-36 present timing requirements for receive RGMII operation.  
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表7-31 presents timing conditions for CPSW2G RGMII.  
表7-31. CPSW2G RGMII Timing Conditions  
PARAMETER  
MIN  
2.64  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL Output load capacitance  
20  
PCB CONNECTIVITY REQUIREMENTS  
RGMII[x]_RXC,  
RGMII[x]_RD[3:  
0],  
50  
50  
ps  
ps  
RGMII[x]_RX_C  
TL  
td(Trace Mismatch Delay) Propagation delay mismatch across all traces  
RGMII[x]_TXC,  
RGMII[x]_TD[3:  
0],  
RGMII[x]_TX_C  
TL  
7.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
TYP  
MAX UNIT  
RGMII1 tc(RXC)  
RGMII2 tw(RXCH)  
RGMII3 tw(RXCL)  
Cycle time, RXC  
360  
36  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, RXC high  
Pulse duration, RXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
100Mbps  
1000Mbps  
3.6  
4.4  
7.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
TYP  
MAX UNIT  
RGMII4 tsu(RD-RXC)  
Setup time, RD[3:0] valid before RXC high/low  
1
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
1
1
tsu(RX_CTL-RXC)  
Setup time, RX_CTL valid before RXC high/low  
Hold time, RD[3:0] valid after RXC high/low  
Hold time, RX_CTL valid after RXC high/low  
1
1
100Mbps  
1000Mbps  
10Mbps  
1
RGMII5 th(RXC-RD)  
1
100Mbps  
1000Mbps  
10Mbps  
1
1.15  
1
th(RXC-RX_CTL)  
100Mbps  
1000Mbps  
1
1.15  
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RGMII1  
RGMII2  
RGMII3  
RGMII[x]_RXC(A)  
RGMII4  
RGMII5  
RGMII[x]_RD[3:0](B)  
1st Half-byte  
2nd Half-byte  
RXERR  
RGMII[x]_RX_CTL(B)  
RXDV  
A. RGMII_RXC must be externally delayed relative to the data and control pins.  
B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of  
RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC  
and RXERR on falling edge of RGMII_RXC.  
图7-36. CPSW2G Receive Interface Timing, RGMII operation  
节7.9.5.2.3.3, 节7.9.5.2.3.4, and 图7-37 present switching characteristics for transmit - RGMII for 10 Mbps, 100  
Mbps, and 1000 Mbps.  
7.9.5.2.3.3 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10Mbps  
MIN  
360  
36  
TYP  
MAX UNIT  
RGMII1 tc(TXC)  
RGMII2 tw(TXCH)  
RGMII3 tw(TXCL)  
Cycle time, TXC  
440  
44  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100Mbps  
1000Mbps  
10Mbps  
7.2  
160  
16  
8.8  
240  
24  
Pulse duration, TXC high  
Pulse duration, TXC low  
100Mbps  
1000Mbps  
10Mbps  
3.6  
160  
16  
4.4  
240  
24  
100Mbps  
1000Mbps  
3.6  
4.4  
7.9.5.2.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode  
NO.  
PARAMETER  
MODE  
MIN  
1.2  
TYP  
MAX UNIT  
RGMII9 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to  
RGMII[x]_TXC high/low  
10/100 Mbps  
1000 Mbps  
10/100 Mbps  
1000 Mbps  
10/100 Mbps  
1000 Mbps  
10/100 Mbps  
1000 Mbps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1.05(1)  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to  
RGMII[x]_TXC high/low  
1.2  
1.05(1)  
1.2  
RGMII1 toh(TD-TXC)  
0
Output hold time, RGMII[x]_TD[3:0] valid after  
RGMII[x]_TXC high/low  
1.05(1)  
toh(TX_CTL-TXC)  
Output hold time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
1.2  
1.05(1)  
(1) 1000Mbps operation requires that the 4 data pins (RGMII[x]_TD[3:0]) and RGMII[x]_TX_CTL have their board propagation delays  
matched to within 50 ps of RGMII[x]_TXC.  
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RGMII6  
RGMII7  
RGMII8  
RGMII[x]_TXC(A)  
RGMII9  
RGMII[x]_TD[3:0](B)  
RGMII[x]_TX_CTL(B)  
1st Half-byte  
TXEN  
2nd Half-byte  
TXERR  
RGMII10  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC  
and RTXERR on falling edge of RGMII_TXC.  
图7-37. CPSW2G Transmit Interface Timing RGMII Mode  
For more information, see section Gigabit Ethernet MAC (MCU_CPSW0) in the device TRM.  
7.9.5.3 CSI2  
Note  
For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM.  
The camera adaptation layer (CAL) delas with the processing of pixel data coming from an external image  
sensor and data from memory. It is a key component for the following multimedia applications: camera  
viewfinder, video record, and still image capture.  
The device includes one instantiation of CAL Subsystem named CALSS0, with a single companion  
CAMERARX0 instance.  
CALSS0 is a very flexible subsystem that enables 3 different connections to cameras. It supports MIPI CSI-2  
over D-PHY serial interface; a LVDS serial interface; and a traditional parallel interface.  
The CALSS0 is compliant with the MIPI D-PHY RX specification v1.01.00 and the MIPI CSI-2 specification, with  
4 data differential lanes plus 1 clock differential lane in synchronous mode, double data rate:  
• 1.2 Gbps (600 MHz) for each lane.  
7.9.5.4 DDRSS  
For more details about features and additional description information on the device DDR4 Memory Interfaces,  
see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
The device has dedicated interfaces to DDR4 SDRAM. It supports JESD79-4B standard-compliant DDR4  
SDRAM devices with the following features:  
• 16-bit or 32-bit data path to external SDRAM memory  
• Memory device capacity: Up to 8 GB address space available over one chip select  
表7-32 and 图7-38 present switching characteristics for DDRSS.  
表7-32. Switching Characteristics for DDRSS  
NO.  
PARAMETER  
DDR TYPE  
MODE  
MIN  
MAX UNIT  
tc(DDR_CKP/  
1
Cycle time, DDR_CKP and DDR_CKN  
DDR4  
1.25  
1.6 ns  
DDR_CKN)  
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1
DDR_CK[1:0]P  
DDR_CK[1:0]N  
图7-38. DDRSS Memory Interface Clock Timing  
For more information, see section DDR Subsystem (DDRSS) in the device TRM.  
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7.9.5.5 DSS  
For more details about features and additional description information on the device Display Subsystem –Video  
Output Ports, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表 7-33, 表 7-34, 图 7-39 and 图 7-40 assume testing over the recommended operating conditions and electrical  
characteristic conditions.  
表7-33. DPI Video Output Switching Characteristics  
NO.  
D1  
D2  
D3  
D4  
PARAMETER  
MIN  
6.06  
MAX UNIT  
tc(VOUT1_PCLK)  
tw(VOUT1_PCLKL)  
tw(VOUT1_PCLKH)  
Cycle time, VOUT1_PCLK  
ns  
ns  
Pulse duration, VOUT1_PCLK low  
Pulse duration, VOUT1_PCLK high  
Delay time, VOUT1_PCLK to VOUT1_DATA[23:0]  
0.475 * P(1)  
0.475 * P(1)  
-0.68  
ns  
td(VOUT1_PCLK-  
1.78 ns  
VOUT_DATA)  
D5  
td(VOUT1_PCLK-  
Delay time, VOUT1_PCLK to VOUT1_VSYNC, VOUT1_HSYNC,  
VOUT1_DE  
-0.68  
1.78 ns  
VOUT_CTRL)  
(1) P = output VOUT1_PCLK period in ns.  
D2  
D3  
D1  
Falling-edge Clock Reference  
Rising-edge Clock Reference  
VOUT1_PCLK  
VOUT1_PCLK  
D5  
VOUT1_VSYNC  
D5  
VOUT1_HSYNC  
D4  
VOUT1_DATA[23:0]  
VOUT1_DE  
data_1 data_2  
D5  
data_n  
DPI_01  
A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.  
B. The polarity and the pulse width of VOUT1_HSYNC and VOUT1_VSYNC are programmable, refer to section Display Subsystem (DSS)  
in the device TRM.  
C. The VOUT1_PCLK frequency can be configured, refer to section Display Subsystem (DSS) in the device TRM.  
图7-39. DPI Video Output  
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表7-34. DPI External Pixel Clock Input Timing Requirements  
NO.  
D6  
D7  
D8  
MIN  
6.06  
MAX UNIT  
tc(VOUT1_EXTPCLKIN)  
tw(VOUT1_EXTPCLKIN)  
tw(VOUT1_EXTPCLKIN)  
Cycle time, VOUT1_EXTPCLKIN  
ns  
ns  
ns  
Pulse duration, VOUT1_EXTPCLKIN low  
Pulse duration, VOUT1_EXTPCLKIN high  
0.475 * P(1)  
0.475 * P(1)  
(1) P = output VOUT1_PCLK period in ns.  
D7  
D8  
D6  
Falling-edge Clock Reference  
Rising-edge Clock Reference  
VOUT1_EXTPCLKIN  
VOUT1_EXTPCLKIN  
DPI_02  
图7-40. DPI External Pixel Clock Input  
For more information, see section Display Subsystem (DSS) in the device TRM.  
7.9.5.6 eCAP  
The supported features by the device eCAP are:  
• 32-bit time base counter  
• 4-event time-stamp registers (each 32 bits)  
• Independent edge polarity selection for up to four sequenced time-stamp capture events  
• Interrupt capabilities on any of the four capture events  
• Input capture signal pre-scaling (from 1 to 16)  
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp  
capture or difference mode time-stamp capture)  
表7-35 represents eCAP timing conditions.  
表7-35. eCAP Timing Conditionns  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节7.9.5.6.1 and 节7.9.5.6.2 present timing and switching characteristics for eCAP (see 图7-41 and 图7-42).  
7.9.5.6.1 eCAP Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
CAP1 tw(CAP)  
Pulse duration, CAP (asynchronous)  
3 + 2P(1)  
ns  
(1) P = sysclk period in ns.  
CAP1  
CAP  
EPERIPHERALS_TIMNG_01  
图7-41. eCAP Timing Requirements  
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7.9.5.6.2 eCAP Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
CAP2 tw(APWM)  
Pulse duration, APWMx  
-3 + 2P(1)  
ns  
(1) P = sysclk period in ns.  
CAP2  
APWM  
EPERIPHERALS_TIMNG_02  
图7-42. eCAP Switching Characteristics  
For more information, see section Enhanced Capture (ECAP) Module in the device TRM.  
7.9.5.7 ePWM  
The supported features by the device ePWM are:  
• Dedicated 16-bit time-base counter with period and frequency control  
• Two independent PWM outputs which can be used in different configurations (with single-edge operation,  
with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)  
• Asynchronous override control of PWM signals during fault conditions  
• Programmable phase-control support for lag or lead operation relative to other EPWM modules  
• Dead-band generation with independent rising and falling edge delay control  
• Programmable trip zone allocation of both latched and un-latched fault conditions  
• Events enabling to trigger both CPU interrupts and start of ADC conversions  
表7-36 represents ePWM timing conditions.  
表7-36. ePWM Timing Conditionns  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节 7.9.5.7.1 and 节 7.9.5.7.2 present timing and switching characteristics for eHRPWM (see 图 7-43, 图 7-44, 图  
7-45, and 图7-46).  
7.9.5.7.1 ePWM Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PWM6 tw(SYNCIN)  
Pulse duration, eHRPWM_SYNCI  
3 + 2P(1)  
ns  
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NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PWM7 tw(TZ)  
Pulse duration, eHRPWM_TZn_IN low  
3 + 3P(1)  
ns  
(1) P = sysclk period in ns  
PWM6  
EHRPWM_SYNCI  
PWM7  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMNG_07  
图7-43. ePWM Timing Requirements  
7.9.5.7.2 ePWM Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
-3 + P(1)  
-3 + P(1)  
MAX  
UNIT  
ns  
PWM1 tw(PWM)  
Pulse duration, EHRPWM_A/B high/low  
Pulse duration, EHRPWM_SYNCO  
PWM2 tw(SYNCOUT)  
PWM3 td(TZ-PWM)  
ns  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced  
high/low  
11  
11  
ns  
PWM4 td(TZ-PWMZ)  
Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z  
ns  
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NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PWM5 tw(SOC)  
Pulse duration, EHRPWM_SOCA/B output  
-3 + P(1)  
ns  
(1) P = sysclk period in ns  
PWM1  
EHRPWM_A/B  
PWM1  
PWM2  
EHRPWM_SYNCO  
EHRPWM_SOCA/B  
PWM5  
EPERIPHERALS_TIMNG_04  
图7-44. EHRPWM Switching Characteristics  
PWM3  
EHRPWM_A/B  
EHRPWM_TZn_IN  
EPERIPHERALS_TIMING_05  
图7-45. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics  
PWM4  
EHRPWM_A/B  
EHRPWM_TZn_IN  
图7-46. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics  
For more information, see section Enhanced Pulse Width Modulation (EPWM) Module in the device TRM.  
7.9.5.8 eQEP  
The supported features by the device eQEP are:  
• Input Synchronization  
• Three Stage/Six Stage Digital Noise Filter  
• Quadrature Decoder Unit  
• Position Counter and Control unit for position measurement  
• Quadrature Edge Capture unit for low speed measurement  
• Unit Time base for speed/frequency measurement  
• Watchdog Timer for detecting stalls  
表7-37 represents eQEP timing conditions.  
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表7-37. eQEP Timing Conditionns  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
节 7.9.5.8.1 and 节 7.9.5.8.2 present Timing Requirements and Switching Characteristics for eQEP (see 图  
7-47).  
7.9.5.8.1 eQEP Timing Requirements  
NO.  
PARAMETER  
tw(QEP)  
DESCRIPTION  
MIN  
3 + 2P(1)  
3 + 2P(1)  
3 + 2P(1)  
3 + 2P(1)  
3 + 2P(1)  
MAX  
UNIT  
ns  
QEP1  
QEP2  
QEP3  
QEP4  
QEP5  
Pulse duration, QEP_A/B  
Pulse duration, QEP_I high  
Pulse duration, QEP_I low  
Pulse duration, QEP_S high  
Pulse duration, QEP_S low  
tw(QEPIH)  
tw(QEPIL)  
tw(QEPSH)  
tw(QEPSL)  
ns  
ns  
ns  
ns  
(1) P = sysclk period in ns.  
QEP1  
QEP_A/B  
QEP2  
QEP_I  
QEP3  
QEP4  
QEP_S  
QEP5  
EPERIPHERALS_TIMNG_03  
图7-47. eQEP Timing Requirements  
7.9.5.8.2 eQEP Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
QEP6  
td(QEP-CNTR)  
Delay time, external clock to counter increment  
24  
ns  
For more information, see section Enhanced Quadrature Encoder Pulse (EQEP) Module in the device TRM.  
7.9.5.9 GPIO  
The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per bank),  
which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output  
capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins.  
Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this Device, general  
purpose interface supports up to 242 pins.  
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For more details about features and additional description information on the device General-Purpose Interface,  
see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
Note  
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.  
表7-38 presents timing conditions of the GPIO interface.  
表7-38. GPIO Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
0.75  
3
MAX  
6.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
节7.9.5.9.1 and 节7.9.5.9.2 present timings and switching characteristics of the GPIO Interface.  
7.9.5.9.1 GPIO Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
GP2  
tw(GPIO_IN)  
Minimum Input Pulse Width  
3.6 + 2P(1)  
ns  
(1) P = functional clock period in ns.  
7.9.5.9.2 GPIO Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
GP1  
tw(GPIO_OUT)  
Minimum Output Pulse Width  
-4.6 +  
ns  
0.975P(1)  
(1) P = functional clock period in ns.  
For more information, see section General-Purpose Interface (GPIO) in the device TRM.  
7.9.5.10 GPMC  
For more details about features and additional description information on the device General-Purpose Memory  
Controller, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-39 presents the timing conditions for GPMC.  
表7-39. GPMC Timing Conditions  
PARAMETER  
Input Conditions  
SRI  
DESCRIPTION  
MIN  
1.65  
5
MAX  
4
UNIT  
V/ns  
pF  
Input slew rate  
Output Conditions  
CL  
Output load capacitance  
20  
7.9.5.10.1 GPMC and NOR Flash—Synchronous Mode  
节 7.9.5.10.1.1 and 节 7.9.5.10.1.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-48 through 图7-52).  
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7.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode  
NO. PARAMETER  
DESCRIPTION  
MODE(2)  
MIN  
MAX UNIT  
F12 tsu(dV-clkH)  
Setup time, input data GPMC_AD[15:0] valid  
before output clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
2.17  
ns  
not_div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
3.46  
1.78  
1.78  
2.17  
3.46  
1.78  
1.78  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
F13 th(clkH-dV)  
Hold time, input data GPMC_AD[15:0] valid after  
output clock GPMC_CLK high  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
not_div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
F21 tsu(waitV-clkH)  
Setup time, input wait GPMC_WAIT[x] valid before  
output clock GPMC_CLK high (1)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
not_div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
F22 th(clkH-waitV)  
Hold time, input wait GPMC_WAIT[x] valid after  
output clock GPMC_CLK high (1)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
not_div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
(1) In GPMC_WAIT[x], x is equal to 0 or 1.  
(2) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For not_div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:  
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)  
For GPMC_FCLK_MUX_100:  
gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
•
•
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
7.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode  
NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
MIN  
MAX UNIT  
F0 tc(clk)  
Period, output clock GPMC_CLK (18)  
div_by_1_mode;  
10  
ns  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
F1 tw(clkH)  
Typical pulse duration, output clock GPMC_CLK  
high  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-0.3+0.4  
75*P (15)  
ns  
ns  
F1 tw(clkL)  
Typical pulse duration, output clock GPMC_CLK  
low  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-0.3+0.4  
75*P (15)  
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NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
MIN  
MAX UNIT  
F2 td(clkH-csnV)  
Delay time, output clock GPMC_CLK rising edge to  
output chip select GPMC_CSn[x] transition (14)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.2+F (6) 4.5+F (6) ns  
F3 td(clkH-csnIV)  
Delay time, output clock GPMC_CLK rising edge to  
output chip select GPMC_CSn[x] invalid (14)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.2+E 4.5+E (5) ns  
(5)  
F4 td(aV-clk)  
Delay time, output address GPMC_A[27:1] valid to  
output clock GPMC_CLK first edge  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+B 4.5+B (2) ns  
(2)  
F5 td(clkH-aIV)  
Delay time, output clock GPMC_CLK rising edge to  
output address GPMC_A[27:1] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3  
4.5 ns  
F6 td(be[x]nV-clk)  
Delay time, output lower byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper byte enable GPMC_BE1n valid to output  
clock GPMC_CLK first edge  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+B 1.9+B (2) ns  
(2)  
F7 td(clkH-be[x]nIV)  
Delay time, output clock GPMC_CLK rising edge to  
output lower byte enable and command latch  
enable GPMC_BE0n_CLE, output upper byte  
enable GPMC_BE1n invalid (11)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+D 1.9+D (4) ns  
(4)  
F7 td(clkL-be[x]nIV)  
F7 td(clkL-be[x]nIV).  
F8 td(clkH-advn)  
Delay time, GPMC_CLK falling edge to  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+D 1.9+D (4) ns  
GPMC_BE0n_CLE, GPMC_BE1n invalid (12)  
(4)  
Delay time, GPMC_CLK falling edge to  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+D 1.9+D (4) ns  
GPMC_BE0n_CLE, GPMC_BE1n invalid (13)  
(4)  
Delay time, output clock GPMC_CLK rising edge to  
output address valid and address latch enable  
GPMC_ADVn_ALE transition  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3+G 4.5+G (7) ns  
(7)  
F9 td(clkH-advnIV)  
F10 td(clkH-oen)  
F11 td(clkH-oenIV)  
F14 td(clkH-wen)  
Delay time, output clock GPMC_CLK rising edge to  
output address valid and address latch enable  
GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3+D 4.5+D (4) ns  
(4)  
Delay time, output clock GPMC_CLK rising edge to  
output enable GPMC_OEn_REn transition  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3H (8) 3.5+H (8) ns  
Delay time, output clock GPMC_CLK rising edge to  
output enable GPMC_OEn_REn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3+E 3.5+E (8) ns  
(8)  
Delay time, output clock GPMC_CLK rising edge to  
output write enable GPMC_WEn transition  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1;  
no extra_delay  
-2.3+I (9) 4.5+I (9) ns  
F15 td(clkH-do)  
F15 td(clkL-do)  
F15 td(clkL-do).  
F17 td(clkH-be[x]n)  
Delay time, output clock GPMC_CLK rising edge to  
output data GPMC_AD[15:0] transition (11)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 2.7+J (10) ns  
(10)  
Delay time, GPMC_CLK falling edge to  
GPMC_AD[15:0] data bus transition (12)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 2.7+J (10) ns  
(10)  
Delay time, GPMC_CLK falling edge to  
GPMC_AD[15:0] data bus transition (13)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 2.7+J (10) ns  
(10)  
Delay time, output clock GPMC_CLK rising edge to  
output lower byte enable and command latch  
enable GPMC_BE0n_CLE transition (11)  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 1.9+J (10) ns  
(10)  
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MAX UNIT  
NO.(2) PARAMETER  
DESCRIPTION  
MODE(19)  
MIN  
F17 td(clkL-be[x]n)  
Delay time, GPMC_CLK falling edge to  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 1.9+J (10) ns  
GPMC_BE0n_CLE, GPMC_BE1n transition (12)  
(10)  
F17 td(clkL-be[x]n).  
Delay time, GPMC_CLK falling edge to  
div_by_1_mode;  
GPMC_FCLK_MUX_100;  
TIMEPARAGRANULARITY_X1  
-2.3+J 1.9+J (10) ns  
GPMC_BE0n_CLE, GPMC_BE1n transition (13)  
(10)  
F18 tw(csnV)  
Pulse duration, output chip select GPMC_CSn[x]  
low (14)  
Read  
Write  
Read  
Write  
0+A (1)  
0+A (1)  
0+C (3)  
0+C (3)  
ns  
ns  
ns  
ns  
F19 tw(be[x]nV)  
Pulse duration, output lower byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper byte enable GPMC_BE1n low  
F20 tw(advnV)  
Pulse duration, output address valid and address  
latch enable GPMC_ADVn_ALE low  
Read  
Write  
0+K (16)  
0+K (16)  
ns  
ns  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
With n being the page burst access number.  
(2) B = ClkActivationTime × GPMC_FCLK(17)  
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
With n being the page burst access number.  
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(6) For csn falling edge (CS activated):  
•
Case GpmcFCLKDivider = 0:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and  
CSOnTime are even)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)  
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)  
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)  
(7) For ADV falling edge (ADV activated):  
•
Case GpmcFCLKDivider = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and  
ADVOnTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Reading mode:  
•
Case GpmcFCLKDivider = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
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– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and  
ADVRdOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)  
For ADV rising edge (ADV deactivated) in Writing mode:  
•
Case GpmcFCLKDivider = 0:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and  
ADVWrOffTime are even)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)  
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)  
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)  
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):  
•
Case GpmcFCLKDivider = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and  
OEOnTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For OE rising edge (OE deactivated):  
•
Case GpmcFCLKDivider = 0:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and  
OEOffTime are even)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)  
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(9) For WE falling edge (WE activated):  
•
Case GpmcFCLKDivider = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17)  
•
Case GpmcFCLKDivider = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and  
WEOnTime are even)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)  
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– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)  
For WE rising edge (WE deactivated):  
•
Case GpmcFCLKDivider = 0:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)  
•
Case GpmcFCLKDivider = 1:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and  
WEOffTime are even)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise  
•
Case GpmcFCLKDivider = 2:  
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)  
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)  
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)  
(10) J = GPMC_FCLK(17)  
(11) First transfer only for CLK DIV 1 mode.  
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.  
(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.  
(14) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
(15) P = GPMC_CLK period in ns  
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)  
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the  
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.  
(19) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX_100:  
gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
For no extra_delay:  
•
•
•
•
GPMC_CONFIG2_i Register : CSEXTRADELAY = 0h = CS i Timing control signal is not delayed  
GPMC_CONFIG4_i Register : WEEXTRADELAY = 0h = nWE timing control signal is not delayed  
GPMC_CONFIG4_i Register : OEEXTRADELAY = 0h = nOE timing control signal is not delayed  
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[x]  
F4  
F6  
GPMC_A[MSB:1]  
Valid Address  
F19  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F19  
F6  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F12  
D 0  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
GPMC_01  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-48. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)  
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F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[x]  
F4  
GPMCA[MSB:1]  
Valid Address  
F6  
F7  
F7  
GPMC_BE0n_CLE  
GPMC_BE1n  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
F10  
F11  
F13  
F13  
F12  
F12  
D 0  
F22  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
D 1  
D 2  
D 3  
F21  
GPMC_02  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-49. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)  
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F1  
F1  
F0  
GPMC_CLK  
F2  
F3  
GPMC_CSn[x]  
F4  
F6  
Valid Address  
GPMC_A[MSB:1]  
F17  
F17  
F17  
F17  
F17  
GPMC_BE0n_CLE  
GPMC_BE1n  
F17  
F6  
F8  
F8  
F9  
GPMC_ADVn_ALE  
GPMC_WEn  
F14  
F14  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
D 0  
D 3  
GPMC_03  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-50. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)  
F1  
F0  
F1  
GPMC_CLK  
F2  
F3  
GPMC_CSn[x]  
F6  
F6  
F4  
F7  
GMPC_BE0n_CLE  
Valid  
F7  
Valid  
GPMC_BE1n  
GPMC_A[27:17]  
Address (MSB)  
F5  
F12  
F13  
F4  
F12  
GPMC_AD[15:0]  
Address (LSB)  
D0  
D1  
D2  
D3  
F8  
F8  
F9  
GPMC_ADVn_ALE  
F10  
F11  
GPMC_OEn_REn  
GPMC_WAIT[x]  
GPMC_04  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
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B. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-51. GPMC and Multiplexed NOR Flash—Synchronous Burst Read  
F1  
F1  
F0  
GPMC_CLK  
F2  
F3  
F18  
GPMC_CSn[x]  
F4  
F6  
F6  
GPMC_A[27:17]  
Address (MSB)  
F17  
F17  
F17  
F17  
F17  
F17  
GPMC_BE1n  
BPMC_BE0n_CLE  
F8  
F8  
F20  
F9  
GPMC_ADVn_ALE  
F14  
F14  
GPMC_WEn  
F15  
D 1  
F15  
D 2  
F15  
GPMC_AD[15:0]  
Address (LSB)  
D 0  
D 3  
F22  
F21  
GPMC_WAIT[x]  
GPMC_05  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
B. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-52. GPMC and Multiplexed NOR Flash—Synchronous Burst Write  
7.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode  
节 7.9.5.10.2.1 and 节 7.9.5.10.2.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-53 through 图7-58).  
7.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode  
NO.  
PARAMETER  
DESCRIPTION  
Data access time  
MODE  
MIN  
MAX UNIT  
FA5(1) tacc(d)  
div_by_1_mode;  
H (4) ns  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
FA20(2) tacc1-pgmode(d)  
Page mode successive data access time  
Page mode first data access time  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
P (3) ns  
FA21(1) tacc2-pgmode(d)  
div_by_1_mode;  
H (4) ns  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active  
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.  
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of  
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional  
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.  
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
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(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)  
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
7.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode  
NO. PARAMETER  
DESCRIPTION  
MODE(15)  
Read  
MIN  
MAX UNIT  
0+N (12) ns  
0+N (12)  
FA0 tw(be[x]nV)  
Pulse duration, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid time  
Write  
FA1 tw(csnV)  
Pulse duration, output chip select GPMC_CSn[x]  
(13) low  
Read  
Write  
Read  
Write  
0+A (1) ns  
0+A (1)  
FA3 td(csnV-advnIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
-2+B (2)  
-2+B (2)  
2+B (2) ns  
2+B (2)  
FA4 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output enable GPMC_OEn_REn invalid  
(Single read)  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+C (3)  
-2+J (9)  
-2+J (9)  
2+C (3) ns  
2+J (9) ns  
2+J (9) ns  
FA9 td(aV-csnV)  
Delay time, output address GPMC_A[27:1] valid to  
output chip select GPMC_CSn[x](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
FA10 td(be[x]nV-csnV)  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE, output  
upper-byte enable GPMC_BE1n valid to output  
chip select GPMC_CSn[x](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
FA12 td(csnV-advnV)  
FA13 td(csnV-oenV)  
FA16 tw(aIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output address valid and address latch  
enable GPMC_ADVn_ALE valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+K (10) 2+K (10) ns  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+L (11) 2+L (11) ns  
Pulse duration output address GPMC_A[26:1]  
invalid between 2 successive read and write  
accesses  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
0+G (7)  
-2+I (8)  
0+D (4)  
-2+E (5)  
-2+F (6)  
ns  
2+I (8) ns  
ns  
FA18 td(csnV-oenIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output enable GPMC_OEn_REn invalid  
(Burst read)  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
FA20 tw(aV)  
Pulse duration, output address GPMC_A[27:1]  
valid - 2nd, 3rd, and 4th accesses  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
FA25 td(csnV-wenV)  
FA27 td(csnV-wenIV)  
FA28 td(wenV-dV)  
FA29 td(dV-csnV)  
FA37 td(oenV-aIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
2+E (5) ns  
2+F (6) ns  
2.8 ns  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output write enable GPMC_WEn invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn valid  
to output data GPMC_AD[15:0] valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
Delay time, output data GPMC_AD[15:0] valid to  
output chip select GPMC_CSn[x](13) valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+J (9)  
2+J (9) ns  
Delay time, output enable GPMC_OEn_REn valid  
to output address GPMC_AD[15:0] phase end  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
2.8 ns  
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
with n being the page burst access number  
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(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×  
GPMC_FCLK(14)  
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)  
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))  
× GPMC_FCLK(14)  
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)  
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX_133:  
gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
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GPMC_FCLK  
GPMC_CLK  
FA5  
FA1  
GPMC_CSn[x]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
FA10  
FA3  
FA12  
GPMC_ADVn_ALE  
FA4  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data IN 0  
Data IN 0  
GPMC_WAIT[x]  
GPMC_06  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-53. GPMC and NOR Flash—Asynchronous Read—Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA5  
FA5  
FA1  
FA1  
GPMC_CSn[x]  
FA16  
FA9  
FA9  
Address 0  
FA0  
Address 1  
FA0  
GPMC_A[MSB:1]  
FA10  
FA10  
Valid  
FA0  
Valid  
FA0  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
Valid  
FA10  
FA10  
FA3  
FA3  
FA12  
FA12  
GPMC_ADCn_ALE  
FA4  
FA4  
FA13  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
Data Upper  
GPMC_WAIT[x]  
GPMC_07  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-54. GPMC and NOR Flash—Asynchronous Read—32-Bit  
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GPMC_FCLK  
GPMC_CLK  
FA20  
Add3  
FA20  
Add1  
FA21  
FA20  
Add2  
FA1  
GPMC_CSn[x]  
FA9  
Add0  
Add4  
GPMC_A[MSB:1]  
FA0  
FA10  
FA10  
GPMC_BE0n_CLE  
FA0  
GPMC_BE1n  
FA12  
GPMC_ADVn_ALE  
FA18  
FA13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
D3  
D0  
D1  
D2  
D3  
GPMC_WAIT[x]  
GPMC_08  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC  
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by  
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.  
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC  
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock  
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first  
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.  
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-55. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[x]  
FA9  
GPMC_A[MSB:1]  
Valid Address  
FA0  
FA10  
GPMC_BE0n_CLE  
FA0  
FA10  
GPMC_BE1n  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
Data OUT  
GPMC_09  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-56. GPMC and NOR Flash—Asynchronous Write—Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
FA5  
GPMC_CSn[x]  
FA9  
Address (MSB)  
FA0  
GPMC_A[27:17]  
FA10  
FA10  
GPMC_BE0n_CLE  
GPMC_BE1n  
Valid  
FA0  
Valid  
FA3  
FA12  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
FA4  
FA13  
FA29  
FA37  
Data IN  
Data IN  
Address (LSB)  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
GPMC_10  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock  
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock  
edge. FA5 value must be stored inside AccessTime register bits field.  
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
图7-57. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word  
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GPMC_FCLK  
GPMC_CLK  
FA1  
GPMC_CSn[x]  
FA9  
GPMC_A[27:17]  
Address (MSB)  
FA0  
FA10  
GPMC_BE0n_CLE  
FA0  
FA10  
GPMC_BE1n  
FA3  
FA12  
GPMC_ADVn_ALE  
FA27  
FA25  
GPMC_WEn  
FA29  
FA28  
GPMC_AD[15:0]  
Valid Address (LSB)  
Data OUT  
GPMC_WAIT[x]  
GPMC_11  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-58. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word  
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7.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode  
节 7.9.5.10.3.1 and 节 7.9.5.10.3.2 assume testing over the recommended operating conditions and electrical  
characteristic conditions below (see 图7-59 through 图7-62).  
7.9.5.10.3.1 GPMC and NAND Flash Timing Requirements—Asynchronous Mode  
NO.  
PARAMETER  
DESCRIPTION  
MODE(4)  
MIN  
MAX UNIT  
GNF12(1) tacc(d)  
Access time, input data GPMC_AD[15:0] (3)  
div_by_1_mode;  
J (2) ns  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC  
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the  
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.  
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)  
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(4) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX_133:  
gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
7.9.5.10.3.2 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode  
NO.  
PARAMETER  
MODE(15)  
MIN  
MAX UNIT  
tR(d)  
Rise time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
2
ns  
ns  
ns  
tF(d)  
Fall time, output data GPMC_AD[15:0]  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
2
GNF0 tw(wenV)  
Pulse duration, output write enable GPMC_WEn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
0+A (1)  
GNF1 td(csnV-wenV)  
GNF2 tw(cleH-wenV)  
GNF3 tw(wenV-dV)  
GNF4 tw(wenIV-dIV)  
GNF5 tw(wenIV-cleIV)  
GNF6 tw(wenIV-csnIV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+B (2) 2+B (2) ns  
-2+C (3) 2+C (3) ns  
-2+D (4) 2.8+D (4) ns  
-2+E (5) 2.8+E (5) ns  
Delay time, output lower-byte enable and  
command latch enable GPMC_BE0n_CLE high  
to output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
Delay time, output data GPMC_AD[15:0] valid to  
output write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output data GPMC_AD[15:0] invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
Delay time, output write enable GPMC_WEn  
invalid to output lower-byte enable and command  
latch enable GPMC_BE0n_CLE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+F (6)  
2+F (6) ns  
Delay time, output write enable GPMC_WEn  
invalid to output chip select GPMC_CSn[x](13)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+G (7) 2+G (7) ns  
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MAX UNIT  
NO.  
PARAMETER  
MODE(15)  
MIN  
GNF7 tw(aleH-wenV)  
Delay time, output address valid and address  
latch enable GPMC_ADVn_ALE high to output  
write enable GPMC_WEn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+C (3) 2+C (3) ns  
GNF8 tw(wenIV-aleIV)  
Delay time, output write enable GPMC_WEn  
invalid to output address valid and address latch  
enable GPMC_ADVn_ALE invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+F (6)  
-2+I (9)  
0+L (11)  
2+F (6) ns  
0+H (8) ns  
2+I (9) ns  
0+K (10) ns  
ns  
GNF9 tc(wen)  
Cycle time, write  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
GNF10 td(csnV-oenV)  
Delay time, output chip select GPMC_CSn[x](13)  
valid to output enable GPMC_OEn_REn valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
GNF13 tw(oenV)  
Pulse duration, output enable GPMC_OEn_REn  
valid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
GNF14 tc(oen)  
Cycle time, read  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
GNF15 tw(oenIV-csnIV)  
Delay time, output enable GPMC_OEn_REn  
invalid to output chip select GPMC_CSn[x](13)  
invalid  
div_by_1_mode;  
GPMC_FCLK_MUX_133;  
TIMEPARAGRANULARITY_X1  
-2+M (12) 2+M (12) ns  
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)  
(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)  
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)  
(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)  
(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)  
(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)  
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)  
(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)  
(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)  
(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.  
(15) For div_by_1_mode:  
•
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:  
– GPMC_CLK frequency = GPMC_FCLK frequency  
For GPMC_FCLK_MUX_133:  
gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz  
For TIMEPARAGRANULARITY_X1:  
•
•
GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/  
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,  
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,  
WRDATAONADMUXBUS)  
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GPMC_FCLK  
GNF1  
GNF2  
GNF6  
GNF5  
GPMC_CSn[x]  
GPMC_BE0n_CLE  
GPMC_ADCn_ALE  
GPMC_OEn_REn  
GPMC_WEn  
GNF0  
GNF3  
GNF4  
GPMC_AD[15:0]  
Command  
GPMC_12  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
图7-59. GPMC and NAND Flash—Command Latch Cycle  
GPMC_FCLK  
GPMC_CSn[x]  
GNF1  
GNF6  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF7  
GNF8  
GPMC_OEn_REn  
GPMC_WEn  
GNF9  
GNF0  
GNF3  
GNF4  
Address  
GPMC_AD[15:0]  
GPMC_13  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
图7-60. GPMC and NAND Flash—Address Latch Cycle  
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GPMC_FCLK  
GNF12  
GNF10  
GNF15  
GPMC_CSn[x]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GNF14  
GNF13  
GPMC_OEn_REn  
GPMC_AD[15:0]  
GPMC_WAIT[x]  
DATA  
GPMC_14  
A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional  
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional  
clock edge. GNF12 value must be stored inside AccessTime register bits field.  
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.  
C. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.  
图7-61. GPMC and NAND Flash—Data Read Cycle  
GPMC_FCLK  
GNF1  
GNF6  
GPMC_CSn[x]  
GPMC_BE0n_CLE  
GPMC_ADVn_ALE  
GPMC_OEn_REn  
GNF9  
GNF0  
GPMC_WEn  
GNF3  
GNF4  
GPMC_AD[15:0]  
DATA  
GPMC_15  
A. In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.  
图7-62. GPMC and NAND Flash—Data Write Cycle  
For more information, see section General-Purpose Memory Controller (GPMC) in the device TRM.  
7.9.5.11 HyperBus  
Note  
HyperBus is not available on this device.  
For more details about features and additional description information on the device Hyperbus, see the  
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
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节 7.9.5.11.1, 节 7.9.5.11.2, and 节 7.9.5.11.3 assume testing over the recommended operating conditions and  
electrical characteristic conditions (see 图7-63, 图7-64, and 图7-65).  
表7-40 presents timing conditions for HyperBus.  
表7-40. HyperBus Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
1.5  
10  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Mismatch  
Propagation delay mismatch between CK and CKn;  
ps  
ps  
10  
traces  
RWDS and DQ[7:0]  
Delay)  
CK/CKn and RWDS;  
CK/CKn and CSn  
260  
CK/CKn and DQ[7:0]  
RESETn and CSn[1:0]  
80  
ps  
ps  
340  
7.9.5.11.1 Timing Requirements for HyperBus Initialization  
NO.  
D1  
D2  
D3  
D4  
PARAMETER  
tw(RESETn)  
DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
RESETn Pulse Width  
200  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(csnL)  
Chip Select Pulse Width  
1000  
td(RESETnH-csnL)  
td(csnL-RWDSL)  
Delay time, RESETn inactive to CSn active  
Delay time, CSn active to RWDS falling  
200.34  
166 MHz  
100 MHz  
166 MHz  
100 MHz  
186  
182  
D5  
tskn(rwdsX-dV)  
Input skew, RWDS transitioning to D0:D7 valid  
-0.46  
-0.81  
0.46  
0.81  
LFD5  
7.9.5.11.2 HyperBus 166 MHz Switching Characteristics  
NO.  
D6  
PARAMETER  
tc(clk/clkn)  
DESCRIPTION  
MIN  
6
MAX  
UNIT  
ns  
CLK period, CLK/CLKn  
D7  
tw(clk/clkn)  
Pulse width, CLK/CLKn  
2.7  
6
ns  
D8  
tw(csIV)  
Pulse width, CS0 invalid between operations  
Delay time, CS0 active to CLK rising/ CLKn falling  
Delay time, last falling CLK/ rising CLKn edge to CS0 inactive  
Delay time, CLK transition to RWDS valid  
Delay time, CLK transitioning to D0:7 valid  
ns  
D9  
td(clkH-csL)  
-3.34  
ns  
D10  
D11  
D12  
td(clkL[LE]-csH)  
td(clkX-rwdsV)  
td(clkX-d[0:7]V)  
0.34  
0.94  
0.76  
ns  
2.08  
2.26  
ns  
ns  
7.9.5.11.3 HyperBus 100 MHz Switching Characteristics  
NO.  
PARAMETER  
tc(clk)  
DESCRIPTION  
MIN  
10  
MAX  
UNIT  
ns  
LFD6  
LFD7  
LFD8  
LFD9  
CLK period, CLK  
tw(clk)  
Pulse width, CLK  
4.5  
10  
ns  
tw(csIV)  
Pulse width, CS0 invalid between operations  
Delay time, CS0 active to CLK rising  
Delay time, last falling CLK edge to CS0 inactive  
Delay time, CLK transition to RWDS valid  
Delay time, CLK transitioning to D0:7 valid  
ns  
td(clkH-csL)  
-3.39  
ns  
LFD10 td(clkL[LE]-csH)  
LFD11 td(clkX-rwdsV)  
LFD12 td(clkX-d[0:7]V)  
0.39  
1.39  
1.21  
ns  
3.62  
3.8  
ns  
ns  
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D8/LFD8  
D2  
CS#  
D9/LFD9  
D10/LFD10  
CK, CK#  
D6/LFD6  
D7/LFD7  
D4  
D11/LFD11  
RWDS  
D12/LFD12  
Dn Dn+1 Dn+1  
D12/LFD12  
Dn  
A
39:32 31:24 23:16  
7:0  
47:40  
15:8  
DQ[7:0]  
B
A
B
CK and Data are center aligned  
Command-Address  
Host drives DQ[7:0] and Memory drives RWDS  
Host drives DQ[7:0] and RWDS  
HYPERBUS_TIMING_01  
图7-63. HyperBus Timing Diagrams - Transmitter Mode  
D8/LFD8  
D2  
CS#  
CK, CK#  
RWDS  
D9/LFD9  
D10/LFD10  
D6/LFD6  
D4  
D7/LFD7  
D5/LFD5  
D12/LFD12  
D5/LFD5  
Dn  
A
Dn  
B
Dn+1 Dn+1  
A
39:32 31:24 23:16  
7:0  
47:40  
15:8  
DQ[7:0]  
B
CK and Data are center aligned  
Command-Address  
Host drives DQ[7:0] and Memory drives RWDS  
Host drives DQ[7:0] and RWDS  
HYPERBUS_TIMING_02  
图7-64. HyperBus Timing Diagrams - Receiver Mode  
D1  
RESET#  
D3  
CS#  
HYPERBUS_TIMING_03  
图7-65. HyperBus Timing Diagrams - Reset  
For more information, see section HyperBus Interface in the device TRM.  
7.9.5.12 I2C  
The device includes 6 inter-integrated circuit (I2C) modules which provide an interface to other devices  
compliant with the Philips Semiconductors Inter-IC bus (I2C BUS™) specification version 2.1.  
Note  
HS-mode is only supported on MAIN_I2C[0:3]. HS-mode is not supported on MCU_I2C0 and  
WKUP_I2C0.  
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Note  
Philips I2C specification rise/fall timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3]  
use standard LVCMOS buffers to emulate open-drain buffers, and their rise/fall times should be  
referenced using the device IBIS model.  
Note  
I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current  
when the device is powered down.  
For more details about features and additional description information on the device Inter-Integrated Circuit, see  
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
7.9.5.13 MCAN  
For more details about features and additional description information on the device Controller Area Network  
Interface, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-41 presents timing conditions for MCANi interface. 表7-42 presents timing parameters for MCANi Interface.  
表7-41. MCAN Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
2
15  
V/ns  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
5
20  
pF  
表7-42. MCAN Register to Pin Timings  
NO.  
M1  
M2  
PARAMETER  
tp(MCANi_TX)  
tp(MCANi_RX)  
DESCRIPTION  
MIN  
MAX  
15  
UNIT  
Delay Time Max, Transmit Shift Register to MCANi_TX pin  
Delay Time Max, MCANi_RX pin to receive shift register  
ns  
ns  
15  
For more information, see section Controller Area Network (MCAN) in the device TRM.  
7.9.5.14 MCASP  
For more details about features and additional description information on the device Multichannel Audio Serial  
Port, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-43 presents timing conditions for MCASP0 to MCASP2.  
节7.9.5.14.1 present timing requirements and switching characteristics for MCASP0 to MCASP2.  
表7-43. MCASP Timing Conditions  
PARAMETER  
MIN  
0.7  
1
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
PCB CONNECTIVITY REQUIREMENTS  
td(Trace Delay)  
Propagation delay of each trace  
Propagation delay mismatch across all traces  
140  
1080  
100  
ps  
ps  
td(Trace Mismatch Delay)  
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7.9.5.14.1 MCASP Timing Requirements and Switching Characteristics  
表7-44. MCASP Timing Requirements  
NO. PARAMETER  
ASP1 tc(AHCLKRX)  
ASP2 tw(AHCLKRX)  
ASP3 tc(ACLKRX)  
ASP4 tw(ACLKRX)  
DESCRIPTION(1)  
Mode  
MIN  
MAX UNIT  
Cycle time, AHCLKR/X  
15.25  
0.5P - 2.5(2)  
ns  
ns  
ns  
ns  
ns  
Pulse duration, AHCLKR/X high or low  
Cycle time, ACLKR/X  
15.25  
0.5R - 2.5(3)  
Pulse duration, ACLKR/X high or low  
ASP5 tsu(AFSRX-ACLKRX) Setup time, AFSR/X input valid before ACLKR/X  
ACLKR/X int  
10.995  
ACLKR/X ext in/out  
ACLKR/X int  
4
-1  
ASP6 th(ACLKRX-AFSRX) Hold time, AFSR/X input valid after ACLKR/X  
ns  
ns  
ns  
ACLKR/X ext in/out  
ACLKR/X int  
1.6  
ASP7 tsu(AXR-ACLKRX)  
Setup time, AXR input valid before ACLKR/X  
Hold time, AXR input valid after ACLKR/X  
10.995  
4
ACLKR/X ext in/out  
ACLKR/X int  
ASP8 th(ACLKRX-AXR)  
-1  
ACLKR/X ext in/out  
1.6  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKR/X period in ns.  
(3) R = ACLKR/X period in ns.  
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ASP2  
ASP2  
ASP1  
MCASP[x]_ACLKR/X (Falling Edge Polarity)  
MCASP[x]_AHCLKR/X (Rising Edge Polarity)  
ASP4  
ASP4  
ASP3  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B)  
ASP6  
ASP5  
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)  
ASP8  
ASP7  
MCASP[x]_AXR[x] (Data In/Receive)  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured  
for falling edge (to shift data in).  
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured  
for rising edge (to shift data in).  
图7-66. MCASP Input Timing  
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表 7-45 and 图 7-67 present switching characteristics over recommended operating conditions for MCASP0 to  
MCASP2.  
表7-45. MCASP Switching Characteristics  
NO. PARAMETER  
ASP9 tc(AHCLKRX)  
ASP10 tw(AHCLKRX)  
ASP11 tc(ACLKRX)  
ASP12 tw(ACLKRX)  
DESCRIPTION(1)  
Mode  
MIN  
MAX UNIT  
Cycle time, AHCLKR/X  
20  
ns  
ns  
ns  
ns  
Pulse duration, AHCLKR/X high or low  
Cycle time, ACLKR/X  
0.5P - 2.5(2)  
20  
Pulse duration, ACLKR/X high or low  
0.5R - 2.5(3)  
ASP13 td(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSR/X  
output valid  
ACLKR/X int  
0
2
6.5  
14  
ns  
ns  
ns  
ACLKR/X ext in/out  
ASP14 td(ACLKX-AXR)  
Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int  
0
6.5  
14  
ACLKR/X ext in/out  
ACLKR/X int  
2
ASP15 tdis(ACLKX-AXR)  
Disable time, ACLKX transmit edge to AXR output  
high impedance  
- 0.2  
6.61  
ACLKR/X ext in/out  
1.71 15.383  
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1  
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0  
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1  
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1  
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0  
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1  
(2) P = AHCLKR/X period in ns.  
(3) R = ACLKR/X period in ns.  
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ASP10  
ASP10  
ASP9  
MCASP[x]_ACLKR/X (Falling Edge Polarity)  
MCASP[x]_AHCLKR/X (Rising Edge Polarity)  
ASP12  
ASP12  
ASP11  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)  
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B)  
ASP13  
ASP13  
ASP13  
ASP13  
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)  
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)  
ASP13  
ASP13  
ASP13  
MCASP[x]_AXR[x] (Data Out/Transmit)  
ASP14  
ASP15  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured  
for rising edge (to shift data in).  
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured  
for falling edge (to shift data in).  
图7-67. MCASP Output Timing  
For more information, see section Controller Area Network (MCAN) in the device TRM.  
7.9.5.15 MCSPI  
For more details about features and additional description information on the device Serial Port Interface, see  
the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-46 presents the timing conditions of SPI.  
表7-46. SPI Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
2
8.5  
V/ns  
OUTPUT CONDITIONS  
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表7-46. SPI Timing Conditions (continued)  
PARAMETER  
MIN  
MAX  
24  
UNIT  
CL  
Output load capacitance  
2
pF  
7.9.5.15.1 SPI—Master Mode  
表 7-47, 表 7-48, 图 7-68, 图 7-69 present Timing Requirements and Switching Characteristics for SPI - Master  
Mode.  
表7-47. SPI Timing Requirements - Master Mode  
NO.  
SM4  
SM5  
MIN  
2
MAX  
UNIT  
ns  
tsu(MISO-SPICLK)  
th(SPICLK-MISO)  
Setup time, SPI_D[x] valid before SPI_CLK active edge  
Hold time, SPI_D[x] valid after SPI_CLK active edge  
3
ns  
表7-48. SPI Switching Characteristics - Master Mode  
NO.  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
SM1 tc(SPICLK)  
SM2 tw(SPICLKL)  
Cycle time, SPI_CLK  
20.8  
ns  
ns  
Typical Pulse duration, SPI_CLK low  
Typical Pulse duration, SPI_CLK high  
-1 +  
0.5P(1)  
SM3 tw(SPICLKH)  
-1 +  
ns  
0.5P(1)  
SM6 td(SPICLK-SIMO)  
SM7 tsk(CS-SIMO)  
SM8 td(SPICLK-CS)  
Delay time, SPI_CLK active edge to SPI_D[x] transition  
Delay time, SPI_CS[x] active to SPI_D[x] transition  
Delay time, SPI_CS[x] active to SPI_CLK first edge  
-3  
5
2
ns  
ns  
ns  
Master_PHA0_POL0;  
Master_PHA0_POL1;  
-4 + B(2)  
-4 + A(3)  
-4 + A(3)  
-4 + B(2)  
Master_PHA1_POL0;  
Master_PHA1_POL1;  
ns  
ns  
ns  
SM9 td(SPICLK-CS)  
Delay time, SPI_CLK last edge to SPI_CS[x] inactive  
Master_PHA0_POL0;  
Master_PHA0_POL1;  
Master_PHA1_POL0;  
Master_PHA1_POL1;  
(1) P = SPICLK period  
(2) B = (TCS + .5) × TSPICLKREF x Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.  
(3) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.  
When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.  
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PHA=0  
EPOL=1  
SPI_CS[x] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
POL=1  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
SPI_SCLK (OUT)  
SM5  
SM5  
SM4  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[x] (OUT)  
SPI_SCLK (OUT)  
SM2  
SM1  
SM8  
SM3  
SM2  
SM9  
POL=0  
POL=1  
SM1  
SM3  
SPI_SCLK (OUT)  
SM5  
SM4  
SM5  
SM4  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_02  
图7-68. SPI Timing Requirements - Master Mode  
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PHA=0  
EPOL=1  
SPI_CS[x] (OUT)  
SM1  
SM3  
SM8  
SM2  
SM9  
POL=0  
SPI_SCLK (OUT)  
SM1  
SM3  
SM2  
POL=1  
SPI_SCLK (OUT)  
SM7  
SM6  
Bit n-2  
SM6  
Bit n-3  
Bit n-1  
Bit n-4  
Bit 0  
SPI_D[x] (OUT)  
PHA=1  
EPOL=1  
SPI_CS[x] (OUT)  
SM1  
SM2  
SM8  
SM3  
SM2  
SM9  
POL=0  
SPI_SCLK (OUT)  
SM1  
SM3  
POL=1  
SPI_SCLK (OUT)  
SM6  
Bit n-1  
SM6  
Bit n-2  
SM6  
Bit n-3  
SM6  
Bit 1  
Bit0  
SPI_D[x] (OUT)  
SPRSP08_TIMING_McSPI_01  
图7-69. SPI Switching Characteristics - Master Mode  
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7.9.5.15.2 SPI—Slave Mode  
表7-49, 表7-50, 图7-70and 图7-71 present Timing Requirements and Switching Characteristics for SPI - Slave  
Mode.  
表7-49. SPI Timing Requirements - Slave Mode  
NO.  
SS1  
SS2  
SS3  
SS4  
SS5  
SS8  
SS9  
PARAMETER  
tc(SPICLK)  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
Cycle time, SPI_CLK  
20.8  
tw(SPICLKL)  
Typical Pulse duration, SPI_CLK low  
0.45P(1)  
ns  
tw(SPICLKH)  
Typical Pulse duration, SPI_CLK high  
Setup time, SPI_D[x] valid before SPI_CLK active edge  
Hold time, SPI_D[x] valid after SPI_CLK active edge  
Setup time, SPI_CS[x] valid before SPI_CLK first edge  
Hold time, SPI_CS[x] valid after SPI_CLK last edge  
0.45P(1)  
ns  
tsu(SIMO-SPICLK)  
th(SPICLK-SIMO)  
tsu(CS-SPICLK)  
th(SPICLK-CS)  
5
5
5
5
ns  
ns  
ns  
ns  
表7-50. SPI Switching Characteristics - Slave Mode  
DESCRIPTION  
NO.  
SS6  
SS7  
PARAMETER  
td(SPICLK-SOMI)  
tsk(CS-SOMI)  
MIN  
2
MAX  
UNIT  
ns  
Delay time, SPI_CLK active edge to mcspi_somi transition  
Delay time, SPI_CS[x] active edge to mcspi_somi transition  
5
20.95  
ns  
(1) P = SPICLK period.  
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PHA=0  
EPOL=1  
SPI_CS[x] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS2  
POL=1  
SPI_SCLK (IN)  
SS5  
SS4  
SS4  
SS5  
Bit n-2  
Bit n-1  
Bit n-3  
Bit n-4  
Bit 0  
SPI_D[x] (IN)  
PHA=1  
EPOL=1  
SPI_CS[x] (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
SPI_SCLK (IN)  
SS1  
SS3  
POL=1  
SPI_SCLK (IN)  
SS4  
SS5  
SS4  
SS5  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 1  
Bit 0  
SPI_D[x] (IN)  
SPRSP08_TIMING_McSPI_04  
图7-70. SPI Timing Requirements - Slave Mode  
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PHA=0  
EPOL=1  
SPI_CS[x] (IN)  
SS1  
SS2  
SS8  
SS3  
SS3  
SS9  
POL=0  
POL=1  
SPI_SCLK (IN)  
SS1  
SS2  
SPI_SCLK (IN)  
SPI_D[x] (OUT)  
SS7  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
Bit n-4  
Bit 0  
PHA=1  
EPOL=1  
SPI_CS[x] (IN)  
SPI_SCLK (IN)  
SS1  
SS2  
SS8  
SS3  
SS2  
SS9  
POL=0  
POL=1  
SS1  
SS3  
SPI_SCLK (IN)  
SPI_D[x] (OUT)  
SS6  
Bit n-1  
SS6  
Bit n-2  
SS6  
Bit n-3  
SS6  
Bit 1  
Bit 0  
SPRSP08_TIMING_McSPI_03  
图7-71. SPI Switching Characteristics - Slave Mode  
For more information, see section Multichannel Serial Peripheral Interface (MCSPI) in the device TRM.  
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7.9.5.16 MMCSD  
Note  
The I/O Timings provided in this section are valid only when the corresponding DLL Delays are  
configured for some MMC usage modes, as described in 表7-52.  
Note  
The MMCi (i = 0 to 1) controller is also referred to as MMCi.  
For more details about features and additional description information on the device Multi Media Card, see the  
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
7.9.5.16.1 MMCSDi —eMMC/SD/SDIO Card Interface  
MMCi interface is compliant with the SD Standard v3.01 as well as JEDEC eMMC standard v4.5 and it supports  
the following SD Card and eMMC applications:  
• SD Default Speed; JEDEC 3.3V Legacy SDR  
• SD High speed; JEDEC 3.3V High Speed SDR  
• SD UHS-I SDR12; JEDEC 1.8V Legacy SDR  
• SD UHS-I SDR25; JEDEC 1.8V High Speed SDR  
• SD UHS-I SDR50  
• SD UHS-I SDR104; JEDEC HS200  
• UHS-I DDR50; JEDEC High Speed DDR (DDR52)  
Note  
For more information, see section Multimedia Card/Secure Digital () Interface in the device TRM.  
表7-51 presents the timing conditions for MMC interface.  
表7-51. MMC Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
Default Speed; 3.3V Legacy SDR  
0.26  
0.69  
0.14  
0.3  
2.64  
2.06  
1.44  
1.34  
2.06  
2.06  
V/ns  
V/ns  
V/ns  
V/ns  
V/ns  
V/ns  
High Speed; 3.3V High Speed SDR  
UHS-I SDR12; 1.8V Legacy SDR  
UHS-I SDR25; 1.8V High Speed SDR  
3.3V High Speed DDR CMD  
0.69  
1.03  
SRI  
Input slew rate  
3.3V High Speed DDR DAT  
UHS-I DDR50 CMD; 1.8V High Speed  
DDR CMD  
0.3  
1.34  
1.34  
V/ns  
V/ns  
UHS-I DDR50 CMD; 1.8V High Speed  
DDR DAT  
0.34  
OUTPUT CONDITIONS  
SDR50  
1
1
1
10  
6
pF  
pF  
pF  
CL  
Output load capacitance  
SDR104; HS200  
All other modes  
12  
PCB CONNECTIVITY REQUIREMENTS  
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表7-51. MMC Timing Conditions (continued)  
PARAMETER  
MIN  
MAX  
UNIT  
Default Speed; SDR12  
134  
1474  
ps  
SDR50; SDR104  
High Speed; SDR25  
DDR50  
Propagation delay of each  
trace - SD Specification  
134  
255  
1139  
ps  
ps  
11394  
td(Trace Delay)  
1.8V, 3.3V Legacy SDR  
1.8V, 3.3V High Speed SDR  
HS200  
134  
168  
670  
ps  
Propagation delay of each  
trace - JEDEC eMMC  
1.8V/ 3.3 V High Speed DDR (DDR52)  
Default Speed; 3.3V Legacy SDR  
3.3V High Speed SDR; HS400 DAT  
All other modes  
670  
100  
8
ps  
ps  
ps  
ps  
Propagation delay  
td(Trace Mismatch Delay)  
mismatch across all traces  
20  
表7-52 shows the required DLL software configuration settings for MMC timing modes.  
表7-52. MMC DLL Delay Mapping for All Timing Modes  
REGISTER NAME  
MMCSDn_SS_PHY_CTRL_4_REG  
MMCSDn_SS_PHY_CTRL_5_REG  
BIT FIELD  
[27:24]  
[20] [15:12] [8]  
[4:0]  
[17:16]  
[9:8]]  
[2:0]  
SELDLYTXCL  
STRBSE OTAPDLYEN OTAPDLYSE ITAPDLYEN ITAPDLYS  
K
SEL100  
SEL50  
CLKBUFS  
EL  
BIT FIELD NAME  
L
A
L
A
EL  
SELDLYRXCL  
K
DELAY  
BUFFER  
DURATIO  
N
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL  
DLL REF  
DESCRIPTIO STROBE  
MODE  
DELAY CHAIN FREQUEN  
N
DELAY  
SELECT  
CY  
4- or 8-bit PHY  
Default operating 3.3  
0x0  
0x0  
0x0  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x0  
0xF  
0xF  
0x8  
0x5  
0x4  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0xA  
0x1  
0x3  
0x0  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
0x7  
Speed  
V,  
25 MHz mode  
4- or 8-bit PHY  
operating 3.3  
V,  
High  
Speed  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x3  
0x3  
0x3  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x2  
0x1  
0x1  
50 MHz mode  
4- or 8-bit PHY  
operating 1.8  
V,  
SDR12  
SDR25  
SDR50  
0xA  
25 MHz mode  
4- or 8-bit PHY  
operating 1.8  
V,  
0x1  
50 MHz mode  
4- or 8-bit PHY  
operating 1.8  
V,  
Tuning  
0x0  
100 MHz  
High  
Speed  
DDR  
4- or 8-bit PHY,  
1.8V or 3.3V,  
JEDEC 50  
MHz  
(DDR52)  
4- or 8-bit PHY,  
1.8V or 3.3V,  
SD/SDIO 50  
MHz  
DDR50  
Tuning  
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表7-52. MMC DLL Delay Mapping for All Timing Modes (continued)  
REGISTER NAME  
BIT FIELD  
MMCSDn_SS_PHY_CTRL_4_REG  
MMCSDn_SS_PHY_CTRL_5_REG  
[27:24]  
[20] [15:12] [8]  
[4:0]  
[17:16]  
[9:8]]  
[2:0]  
SELDLYTXCL  
STRBSE OTAPDLYEN OTAPDLYSE ITAPDLYEN ITAPDLYS  
K
SEL100  
SEL50  
CLKBUFS  
EL  
BIT FIELD NAME  
L
A
L
A
EL  
SELDLYRXCL  
K
DELAY  
BUFFER  
DURATIO  
N
OUTPUT  
DELAY  
ENABLE  
OUTPUT  
DELAY  
VALUE  
INPUT  
DELAY  
ENABLE  
INPUT  
DELAY  
VALUE  
DLL  
DLL REF  
DESCRIPTIO STROBE  
MODE  
DELAY CHAIN FREQUEN  
N
DELAY  
SELECT  
CY  
4- or 8-bit PHY  
operating 1.8  
V,  
SD/SDIO 200  
MHz  
SDR104  
0x0  
0x1  
0x1  
0x7  
0x5  
0x1  
0x1  
Tuning  
Tuning  
0x0  
0x0  
0x7  
0x7  
4- or 8-bit PHY  
operating 1.8  
V,  
HS200  
0x0  
0x0  
0x0  
JEDEC 200  
MHz  
For more information, see section Multimedia Card/Secure Digital (eMMC/SD/SDIO) Interface in the device  
TRM.  
7.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode  
表 7-53 and 表 7-54 present Timing requirements and Switching characteristics for MMCi - Default Speed, 3.3V  
Legacy SDR in receiver and transmitter mode (see 图7-72 and 图7-73)  
表7-53. Timing Requirements for MMCi - Default Speed Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2.15  
MAX  
UNIT  
ns  
DSSD5 tsu(cmdV-clkH)  
DSSD6 th(clkH-cmdV)  
DSSD7 tsu(dV-clkH)  
DSSD8 th(clkH-dV)  
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge  
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge  
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge  
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge  
19.67  
2.15  
ns  
ns  
19.67  
ns  
表7-54. Switching Characteristics for MMCi - Default Speed Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
DSSD0 fop(clk)  
Operating frequency, MMCi_CLK  
Pulse duration, MMCi_CLK high  
25  
DSSD1 tw(clkH)  
DSSD2 tw(clkL)  
DSSD3 td(clkL-cmdV)  
DSSD4 td(clkL-dV)  
18.7  
18.7  
Pulse duration, MMCi_CLK low  
ns  
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition  
-14.1  
-14.1  
14.1  
14.1  
ns  
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]  
transition  
ns  
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图7-72. eMMC/SD/SDIO in - Default Speed - Receiver Mode  
图7-73. eMMC/SD/SDIO in - Default Speed - Transmitter Mode  
7.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode  
表7-55 and 表7-56 present Timing requirements and Switching characteristics for MMCi - High Speed and 3.3V  
High Speed SDR in receiver and transmitter mode (see 图7-74 and 图7-75).  
表7-55. Timing Requirements for MMCi - High Speed Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2.91  
2.76  
2.91  
2.76  
MAX  
UNIT  
ns  
HSSD3 tsu(cmdV-clkH)  
HSSD4 th(clkH-cmdV)  
HSSD7 tsu(dV-clkH)  
HSSD8 th(clkH-dV)  
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge  
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge  
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge  
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge  
ns  
ns  
ns  
表7-56. Switching Characteristics for MMCi - High Speed Mode  
DESCRIPTION  
NO.  
PARAMETER  
fop(clk)  
MIN  
MAX  
UNIT  
MHz  
ns  
HSSD1  
Operating frequency, MMCi_CLK  
50  
HSSD2H tw(clkH)  
HSSD2L tw(clkL)  
Pulse duration, MMCi_CLK high  
9.2  
9.2  
Pulse duration, MMCi_CLK low  
ns  
HSSD5  
HSSD6  
td(clkL-cmdV)  
td(clkL-dV)  
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition  
-6.44  
-6.44  
3.44  
3.44  
ns  
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]  
transition  
ns  
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图7-74. eMMC/SD/SDIO in - High Speed - Receiver Mode  
图7-75. eMMC/SD/SDIO in - High Speed - Transmitter Mode  
7.9.5.16.1.3 UHS-I SDR12, 1.8-V Legacy SDR Mode  
表 7-57 and 表 7-58 present Timing requirements and Switching characteristics for MMCi - SDR12, 1.8V Legacy  
SDR in receiver and transmitter mode (see 图7-76 and 图7-77).  
表7-57. Timing Requirements for MMCi - SDR12, 1.8-V Legacy SDR Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
10.04  
1.75  
MAX  
UNIT  
ns  
SDR121 tsu(cmdV-clkH)  
SDR122 th(clkH-cmdV)  
SDR123 tsu(dV-clkH)  
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge  
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge  
ns  
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock  
edge  
10.04  
ns  
SDR124 th(clkH-dV)  
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge  
1.75  
ns  
表7-58. Switching Characteristics for MMCi - SDR12, 1.8-V Legacy SDR Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR125 fop(clk)  
SDR126 tw(clkH)  
SDR127 tw(clkL)  
SDR128 td(clkH-cmdV)  
Operating frequency, MMCi_CLK  
Pulse duration, MMCi_CLK high  
25  
18.7  
18.7  
1.12  
Pulse duration, MMCi_CLK low  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition  
35.68  
ns  
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表7-58. Switching Characteristics for MMCi - SDR12, 1.8-V Legacy SDR Mode (continued)  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
SDR129 td(clkH-dV)  
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]  
transition  
1.12  
35.68  
ns  
A. There are two modules in MMCi: MMC0 and MMC1  
MMC[x]_CLK  
SDR122  
SDR124  
SDR121  
SDR123  
MMC[x]_CMD  
MMC[x]_DAT[3:0]  
图7-76. eMMC/SD/SDIO in - SDR12, 1.8-V Legacy SDR - Receiver Mode  
SDR125  
SDR126  
SDR127  
MMC[x]_CLK  
MMC[x]_CMD  
SDR128  
SDR128  
SDR129  
SDR129  
MMC[x]_DAT[3:0]  
图7-77. eMMC/SD/SDIO in - SDR12, 1.8-V Legacy SDR - Transmitter Mode  
7.9.5.16.1.4 UHS-I SDR25 Mode  
表 7-59 and 表 7-60 present Timing requirements and Switching characteristics for MMCi - SDR25, 1.8V High  
Speed SDR in receiver and transmitter mode (see 图7-78 and 图7-79).  
表7-59. Timing Requirements for MMCi - SDR25, 1.8-V High-Speed SDR Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
SDR251 tsu(cmdV-clkH)  
SDR252 th(clkH-cmdV)  
SDR253 tsu(dV-clkH)  
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge  
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge  
2.9  
1.75  
2.9  
ns  
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock  
edge  
ns  
SDR254 th(clkH-dV)  
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge  
1.75  
ns  
表7-60. Switching Characteristics for MMCi - SDR25, 1.8-V High-Speed SDR Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR255 fop(clk)  
Operating frequency, MMCi_CLK  
Pulse duration, MMCi_CLK high  
50  
SDR256 tw(clkH)  
SDR257 tw(clkL)  
SDR258 td(clkH-cmdV)  
SDR259 td(clkH-dV)  
9.2  
9.2  
Pulse duration, MMCi_CLK low  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition  
2.32  
2.32  
13.18  
13.18  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]  
transition  
ns  
A. There are two MMCi modules: MMC0 and MMC1  
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MMC[x]_CLK  
MMC[x]_CMD  
SDR252  
SDR254  
SDR251  
SDR253  
MMC[x]_DAT[3:0]  
图7-78. eMMC/SD/SDIO in - SDR25, 1.8-V High-Speed SDR - Receiver Mode  
SDR255  
SDR256  
SDR257  
MMC[x]_CLK  
MMC[x]_CMD  
SDR258  
SDR258  
SDR259  
SDR259  
MMC[x]_DAT[3:0]  
图7-79. eMMC/SD/SDIO in - SDR25, 1.8-V High-Speed SDR - Transmitter Mode  
7.9.5.16.1.5 UHS-I DDR50 Mode  
表 7-61 and 表 7-62 present Timing requirements and Switching characteristics for MMCi - DDR50, 1.8-V and  
3.3-V High-Speed DDR in receiver and transmitter mode (see 图7-80 and 图7-81).  
表7-61. MMCi - 1.8-V, 3.3-V High-Speed DDR Timing Requirements  
NO.(1)  
PARAMETER(2)  
MIN  
8.08  
1.99  
2.59  
1.75  
MAX  
UNIT  
ns  
DDR505  
DDR506  
DDR507  
DDR508  
tsu(cmdV-clkH)  
th(clkH-cmdV)  
tsu(dV-clk)  
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge  
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge  
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK transition  
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK transition  
ns  
ns  
th(clk-dV)  
ns  
(1) j in [j:0] is equal to 7 (for MMC0).  
(2) Timing requirements for 50 MHz DDR is only applicable when interfacing with JEDEC eMMC devices. Tuning should be done if  
interfacing to SD/SDIO devices.  
表7-62. MMCi - DDR50, 1.8-V/3.3-V High-Speed DDR Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
DDR500  
DDR501  
DDR502  
DDR503  
DDR504  
fop(clk)  
Operating frequency, MMCi_CLK  
40  
tw(clkH)  
Pulse duration, MMCi_CLK high  
11.58  
11.58  
3.32  
tw(clkL)  
Pulse duration, MMCi_CLK low  
ns  
td(clk-cmdV)  
td(clk-dV)  
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition  
Delay time, MMCi_CLK transition to MMCi_DAT[j:0] transition  
18.06  
8.87  
ns  
2.82  
ns  
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图7-80. eMMC/SD/SDIO - High-Speed DDR - Receive Mode  
图7-81. eMMC/SD/SDIO - High-Speed DDR - DDR50 - Transmit Mode  
7.9.5.16.1.6 UHS-I SDR50 Mode  
表7-63 present Switching Characteristics for MMCi - SDR50 in transmitter mode (see 图7-82).  
表7-63. Switching Characteristics for MMCi - SDR50 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR501 fop(clk)  
SDR502H tw(clkH)  
SDR502L tw(clkL)  
SDR505 td(clkH-cmdV)  
SDR506 td(clkH-dV)  
Operating frequency, MMCi_CLK  
Pulse duration, MMCi_CLK high  
100  
4.45  
4.45  
1.12  
1.12  
Pulse duration, MMCi_CLK low  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition  
6.43  
6.43  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]  
transition  
ns  
图7-82. eMMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode  
7.9.5.16.1.7 UHS-I SDR104 / HS200 Mode  
表7-64 presents Switching characteristics for MMCi - SDR104, HS200 in transmitter mode (see 图7-83)  
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表7-64. Switching Characteristics for MMCi - SDR104, HS200 Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
SDR1041 fop(clk)  
SDR1042H tw(clkH)  
SDR1042L tw(clkL)  
SDR1045 td(clkH-cmdV)  
SDR1046 td(clkH-dV)  
Operating frequency, MMCi_CLK  
200  
Pulse duration, MMCi_CLK high  
2.08  
2.08  
1.12  
1.12  
Pulse duration, MMCi_CLK low  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition  
3.16  
3.16  
ns  
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]  
transition  
ns  
图7-83. eMMC/SD/SDIO in - High Speed SDR104, HS200 - Transmitter Mode  
For more information, see section Multimedia Card/Secure Digital (eMMC/SD/SDIO) Interface in the device  
TRM.  
7.9.5.17 CPTS  
表7-65 presents CPTS Timing Conditions.  
表7-65. CPTS Timing Conditions  
PARAMETER  
DESCRIPTION  
MIN  
0.5  
2
MAX  
5
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
10  
节7.9.5.17.1, 节7.9.5.17.2, 图7-84, and 图7-85 present timing requirement and switching characteristics of the  
CPTS interface.  
7.9.5.17.1 CPTS Timing Requirements  
NO.  
T1  
T2  
T3  
T4  
T5  
PARAMETER  
tw(HWTSPUSHH)  
tw(HWTSPUSHL)  
tc(RFT_CLK)  
DESCRIPTION  
MIN  
6 + 12P(1)  
6 + 12P(1)  
5
MAX  
UNIT  
ns  
HWnTSPUSH(2) pulse duration, high  
HWnTSPUSH(2) pulse duration, low  
RFT_CLK cycle time  
ns  
8
ns  
tw(RFT_CLKH)  
tw(RFT_CLKL)  
RFT_CLK pulse duration, high  
RFT_CLK pulse duration, low  
0.45 * T(3)  
0.45 * T(3)  
ns  
ns  
(1) P = functional clock period in ns.  
(2) In HWnTSPUSH, n = 1 to 2.  
(3) T = RFT_CLK period in ns.  
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T1  
T2  
HWn_TSPUSH  
T3  
T4  
T5  
RFT_CLK  
图7-84. CPTS Input Timing  
7.9.5.17.2 CPTS Switching Characteristics  
NO.  
T6  
PARAMETER  
tw(TS_COMPH)  
tw(TS_COMPL)  
tw(TS_SYNCH)  
tw(TS_SYNCL)  
tw(SYNC_OUTH)  
DESCRIPTION  
SOURCE  
MIN  
-6+36P(1)  
-6+36P(1)  
-6+36P(1)  
-6+36P(1)  
-6+36P(1)  
-6+5P(1)  
-6+36P(1)  
-6+5P(1)  
MAX UNIT  
Pulse duration, TS_COMP high  
Pulse duration, TS_COMP low  
Pulse duration, TS_SYNC high  
Pulse duration, TS_SYNC low  
Pulse duration, SYNCn_OUT(2) high  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T7  
T8  
T9  
T10  
TS_SYNC  
TS_GENF  
TS_SYNC  
TS_GENF  
T11  
tw(SYNC_OUTL)  
Pulse duration, SYNCn_OUT(2) low  
(1) P = functional clock period in ns.  
(2) n = 0 to 3 in SYNCn_OUT  
T6  
T7  
TS_COMP  
T8  
T9  
TS_SYNC  
T10  
T11  
SYNCn_OUT  
图7-85. CPTS Switching Characteristics  
For more information, see section Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA)  
chapter in the device TRM.  
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7.9.5.18 OSPI  
For more details about features and additional description information on the device Octal Serial Peripheral  
Interface, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-66 presents timing conditions for OSPI.  
表7-66. OSPI Timing Conditions  
PARAMETER  
MIN  
1
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
All modes  
All modes  
6
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
3
10  
PCB CONNECTIVITY REQUIREMENTS  
Propagation delay  
OSPI_CLK trace  
Internal Loopback;  
Internal Pad Loopback  
450  
2*L(2)+30  
L(2)+30  
ps  
ps  
ps  
Propagation delay  
td(Trace Delay)  
External Board Loopback  
DQS  
2*L(2)-30  
L(2)-30  
OSPI_LBCLKO trace  
Propagation delay  
OSPI_DQS trace  
Propagation delay mismatch  
OSPI_D[i:0](1), OSPI_CSn  
relative to OSPI_CLK  
td(Trace Mismatch  
All modes  
60  
ps  
Delay)  
(1) i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1  
(2) L = Propagation delay of OSPI_CLK trace  
7.9.5.18.1 OSPI with Data Training  
Note  
I/O timing requirements and switching characteristics are not applicable when OSPI is used with data  
training. Follow the 节 9.2.2, OSPI and QSPI Board Design and Layout Guidelines to ensure proper  
operation.  
7.9.5.18.1.1 OSPI Switching Characteristics - Data Training  
PARAMETER  
MODE  
MIN  
5.00  
MAX  
UNIT  
1.8V, SDR  
3.3V, SDR  
1.8V, DDR  
3.3V, DDR  
ns  
ns  
ns  
ns  
7.52  
6.02  
7.52  
tc(CLK)  
Cycle time, CLK  
7.9.5.18.2 OSPI without Data Training  
Note  
The I/O Timings provided in this section are only applicable when data training is not implemented.  
Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL  
Delays are configured as described in 表7-67 found in this section.  
节 7.9.5.18.2.4, 节 7.9.5.18.2.2, 图 7-90, and 图 7-88 present switching characteristics for OSPI DDR and SDR  
Mode.  
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7.9.5.18.2.1 OSPI Timing Requirements - SDR Mode  
表7-67. OSPI DLL Delay Mapping - SDR Timing Modes  
OSPI_PHY_CONFIGURATION_REG  
BIT FIELD  
MODE  
DELAY VALUE  
All modes  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
0x0  
0x0  
see 图7-86 and 图7-87  
NO.  
MODE  
MIN  
-2.18  
-1.7  
MAX UNIT  
O19 tsu(D-CLK)  
Setup time, D[i:0] valid before active CLK  
1.8V, Internal Loopback  
3.3V, Internal Loopback  
1.8V, Internal Loopback  
3.3V, Internal Loopback  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
edge(1)  
O20 th(CLK-D)  
Hold time, D[i:0] valid after active CLK  
edge(1)  
7.62  
8.1  
O21 tsu(D-LBCLK)  
Setup time, D[i:0] valid before active LBCLK 1.8V, External Board Loopback  
-3.24  
-2.72  
3.81  
4.33  
input (DQS) edge(1)  
3.3V, External Board Loopback  
O22 th(LBCLK-D)  
Hold time, D[i:0] valid after active LBCLK  
input (DQS) edge(1)  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
OSPI_CLK  
O19  
O20  
OSPI_D[i:0]  
OSPI_TIMING_05  
图7-86. OSPI Timing Requirements - SDR, Internal Clock and Internal Pad Loopback Clock  
OSPI_DQS  
O21  
O22  
OSPI_D[i:0]  
OSPI_TIMING_06  
图7-87. OSPI Timing Requirements - SDR, External Loopback Clock  
7.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode  
NO.  
DESCRIPTION(1)  
MODE  
MIN  
7
MAX  
UNIT  
ns  
1.8V  
3.3V  
O7 tc(CLK)  
Cycle time, CLK  
7.52  
ns  
-0.3+0.475×P  
O8 tw(CLKL)  
O9 tw(CLKH)  
Pulse duration, CLK low  
Pulse duration, CLK high  
ns  
ns  
(1)  
-0.3+0.475×P  
(1)  
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NO.  
DESCRIPTION(1)  
MODE  
MIN  
MAX  
0.475 × P +  
UNIT  
0.475 × P +  
1.8V  
3.3V  
1.8V  
3.3V  
0.975 × N × R 0.975 × N × R  
ns  
- 1(1) (2) (4)  
+ 1 (1) (2) (4)  
O10 td(CLK-CSn)  
Delay time, CLK rising edge to CSn active edge  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
ns  
ns  
ns  
- 1(1) (2) (4)  
+ 1 (1) (2) (4)  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
- 1 (1) (3) (4)  
(1) (3) (4)  
Delay time, CLK rising edge to CSn inactive  
edge  
O11 td(CLK-CSn)  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
- 1(1) (3) (4)  
+ 1 (1) (3) (4)  
1.8V  
3.3V  
-1.15  
1.25  
ns  
ns  
O12 td(CLK-D)  
Delay time, CLK active edge to D[i:0] transition  
-1.33  
1.51  
(1) P = CLK cycle time = SCLK period  
(2) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(4) R = refclk  
OSPI_CSn  
O11  
O10  
O7  
O9  
O8  
OSPI_CLK  
OSPI_D[i:0]  
O12  
OSPI_TIMING_02  
图7-88. OSPI Switching Characteristics - SDR  
节 7.9.5.18.2.3, 节 7.9.5.18.2.1, 图 7-89, and 图 7-87 presents timing requirements for OSPI DDR and SDR  
Mode.  
7.9.5.18.2.3 OSPI Timing Requirements - DDR Mode  
表7-68. OSPI DLL Delay Mapping - DDR Timing Modes  
OSPI_PHY_CONFIGURATION_REG BIT  
FIELD  
OSPI Instance  
MODE  
DELAY VALUE  
1.8V  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_TX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
PHY_CONFIG_RX_DLL_DELAY_FLD  
0x41  
0x46  
0x16  
0x3E  
0x0  
3.3V  
OSPI0  
1.8V DQS  
3.3V DQS  
Non-PHY mode  
1.8V  
0x44  
0x4C  
0x16  
0x40  
0x0  
3.3V  
OSPI1  
1.8V DQS  
3.3V DQS  
Non-PHY mode  
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表7-69. OSPI Timing Requirements - DDR Mode  
see 图7-89  
NO.  
MODE  
MIN  
0.52  
MAX  
UNIT  
ns  
O15 tsu(D-LBCLK)  
O16 th(LBCLK-D)  
O17 tsu(D-DQS)  
O18 th(DQS-D)  
Setup time, D[i:0](1) valid before active LBCLK  
(DQS) edge  
1.8V, External Board Loopback  
3.3V, External Board Loopback  
1.97  
ns  
Hold time, D[i:0](1) valid after active LBCLK (DQS) 1.8V, External Board Loopback  
1.24 (2)  
1.44 (2)  
-0.46  
-0.66  
3.59  
ns  
edge  
3.3V, External Board Loopback  
ns  
Setup time, D[i:0](1) valid before active DQS edge  
1.8V, DQS  
3.3V, DQS  
1.8V, DQS  
3.3V, DQS  
ns  
ns  
Hold time, D[i:0](1) valid after active DQS edge  
ns  
8.89  
ns  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC  
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to 节9.2.2 for more details.  
OSPI_DQS  
O15 O16  
OSPI_D[i:0]  
OSPI_TIMING_04  
图7-89. OSPI Timing Requirements - DDR, External Loopback Clock and DQS  
7.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode  
NO. PARAMETER DESCRIPTION  
MODE  
MIN  
MAX  
UNIT  
ns  
O1 tc(CLK)  
Cycle time, CLK  
19  
O2 tw(CLKL)  
Pulse duration, CLK low  
-0.3+0.475×P  
ns  
(2)  
O3 tw(CLKH)  
Pulse duration, CLK high  
-0.3+0.475×P  
ns  
ns  
(2)  
O4 td(CLK-CSn)  
Delay time, CSn active edge to CLK rising edge  
1.8 V  
3.3 V  
1.8 V  
3.3 V  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
(2) (3) (5)  
+ 7.7 (2) (3) (5)  
0.475 × P +  
0.475 × P +  
ns  
ns  
ns  
0.975 × N × R 0.975 × N × R  
(2) (3) (5)  
+ 8 (2) (3) (5)  
O5 td(CLK-CSn)  
Delay time, CLK rising edge to CSn inactive  
edge  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
- 7.7(2) (4) (5)  
(2) (4) (5)  
0.475 × P +  
0.475 × P +  
0.975 × N × R 0.975 × N × R  
(2) (4) (5)  
- 8(2) (4) (5)  
O6 td(CLK-D)  
Delay time, CLK active edge to D[i:0](1)  
transition  
1.8 V  
3.3 V  
-7.7  
-7.7  
-1.56  
-1.56  
ns  
ns  
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1  
(2) P = CLK cycle time = SCLK period  
(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]  
(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]  
(5) R = refclk  
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OSPI_CSn  
O4  
O3  
O5  
OSPI_CLK  
O2  
O6  
O6  
O1  
OSPI_D[i:0]  
OSPI_TIMING_01  
图7-90. OSPI Switching Characteristics - DDR  
For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM.  
7.9.5.19 OLDI  
7.9.5.19.1 OLDI Switching Characteristics  
PARAME  
NO.  
DESCRIPTION(1)  
MIN  
TYP  
MAX  
UNIT  
TER  
OLDI1 tt(LHTT)  
Low-to-high transition time of LVDS differential signals:  
OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0  
(Fast rise/fall disabled)  
0.5  
ns  
Low-to-high transition time of LVDS differential signals:  
OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1  
(Fast rise/fall enabled)  
0.25  
0.5  
ns  
ns  
ns  
OLDI2 tt(HLTT)  
High-to-low transition time of LVDS differential signals:  
OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0  
(Fast rise/fall disabled)  
High-to-low transition time of LVDS differential signals:  
OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1  
(Fast rise/fall enabled)  
0.25  
OLDI3 tc(CLK)  
OLDI4 tw(BIT)  
Output pixel clock period (OLDI0_CLKP/N)  
Output bit width (OLDI0_AxP/N, x = [3:0])  
6.06  
110.01  
ns  
1
UI(2)  
UI(2)  
OLDI5 t(TPPx,  
Output pulse positions normalized for each bit (OLDI0_AxP/N, x =  
[3:0])  
7-1  
x=[6:0])  
OLDI6  
Variation of pulse positions for each bit from their normalized center  
(OLDI0_AxP/N, x = [3:0])  
0.1  
50  
UI(2)  
ps  
Δt(TPP)  
OLDI7 tsk(TCCS)  
Output channel to channel skew (OLDI0_CLKP/N, OLDI0_AxP/N, x  
= [3:0])  
OLDI8 tj(TJCC)  
OLDI9 tj(IJIT)  
Output jitter cycle-to-cycle (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0])  
0.04  
0.25  
UI(2)  
UI(2)  
Total jitter tolerance (Includes data to clock skew, pulse position  
variation from normalized edges (OLDI0_AxP/N, x = [3:0])  
(1) Measured based on 20% - 80% transitions and PCB trace of ~2in with 100 Ω termination on differential lines.  
(2) UI = tc(CLK) / 7  
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OLDI3  
OLDI0_CLKP/N  
OLDI0_AxP/N  
bit 0  
bit 1  
bit 0  
3UI  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
1UI  
tTPP0  
tTPP1  
tTPP2  
tTPP3  
tTPP4  
tTPP5  
tTPP6  
2UI  
OLDI6  
OLDI5  
4UI  
5UI  
6UI  
7UI  
A. x in OLDI0_AxP/N = [3:0]  
图7-91. OLDI Output Pulse Positions  
Ideal Data  
Bit Beginning  
Ideal Data  
Bit End  
Sampling  
Window  
VTH  
0V  
VTL  
OLDI0_AxP/N  
DATA_TOL  
Right  
DATA_TOL  
Left  
Ideal Center Position (tBIT/2)  
OLDI4  
A. OLDI9 = DATA_TOL (Left+Right)  
B. x in OLDI0_AxP/N = [3:0]  
图7-92. OLDI Data Output Jitter  
+VOD  
80%  
80%  
VSS = 2|VOD|  
OLDI0_CLKP/N,  
OLDI0_AxP/N  
0V  
20%  
20%  
OLDI2  
-VOD  
OLDI1  
A. x in OLDI0_AxP/N = [3:0]  
图7-93. LVDS Output Transition Times  
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+
OLDI0_AxP/N  
100 Ω  
+,  
OLDI0_CLKP/N  
-
-,  
OLDI0_AxP/N  
OLDI0_CLKP/N  
SPRSP08_OLDI_TEST  
A. x in OLDI0_AxP/N = [3:0]  
图7-94. LVDS Output Load  
For more information, see section Display Subsystem (DSS) in the device TRM.  
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7.9.5.20 PCIE  
The PCI-Express Subsystem is compliant with the PCI Express Base Specification, revision 3.1. Refer to the  
specification for timing details.  
For more details about features and additional description information on the device Peripheral Component  
Interconnect Express, see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed  
Description.  
7.9.5.21 PRU_ICSSG  
The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and  
PRU_ICSSG2). The programmable nature of the PRU cores, along with their access to pins, events and all  
device resources, provides flexibility in implementing fast real-time responses, specialized data handling  
operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.  
For more details about features and additional description information on the device Programmable Real-Time  
Unit Subsystem and Industrial Communication Subsystem - Gigabit, see the corresponding sections within 节  
6.3, Signal Descriptions and 节8, Detailed Description.  
7.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)  
Note  
The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The  
signal naming in this section matches the naming used in the PRU Module Interface section in the  
device TRM.  
表7-70 presents the PRU timing conditions.  
表7-70. PRU_ICSSG PRU Timing Conditions  
PARAMETER  
MIN  
1.5  
2
MAX  
3
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
30  
7.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing  
7.9.5.21.1.1.1 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode  
NO.  
PARAMETER  
Skew, GPO to GPO  
MIN  
MAX  
UNIT  
PRDO1 tsk(GPO-GPO)  
4
ns  
GPO[n:0]  
PRDO1  
SPRS91x_TIMING_PRU_02  
图7-95. PRU_ICSSG PRU Direct Output Timing  
A. n in GPO[n:0] = 19.  
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7.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing  
7.9.5.21.1.2.1 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode  
See 图7-96 and 图7-97  
NO.  
MIN  
20  
10  
10  
4
MAX  
UNIT  
ns  
PRPC1 tc(CLOCK)  
Cycle time, CLOCKIN  
PRPC2 tw(CLOCKL)  
Pulse Duration, CLOCKIN Low  
ns  
PRPC3 tw(CLOCKH)  
PRPC4 tsu(DATAIN-CLOCK)  
PRPC5 th(CLOCK-DATAIN)  
Pulse Duration, CLOCKIN High  
ns  
Setup time, DATAIN valid before CLOCKIN active edge  
Hold time, DATAIN valid after CLOCKIN active edge  
ns  
0.6  
ns  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
SPRS91x_TIMING_PRU_03  
图7-96. PRU_ICSSG PRU Parallel Capture Timing –Rising Edge Mode  
PRPC1  
PRPC3  
PRPC2  
CLOCKIN  
DATAIN  
PRPC5  
PRPC4  
SPRS91x_TIMING_PRU_04  
图7-97. PRU_ICSSG PRU Parallel Capture Timing –Falling Edge Mode  
7.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing  
7.9.5.21.1.3.1 PRU_ICSSG PRU Timing Requirements - Shift In Mode  
NO.  
MIN  
2+2×P (1)  
2+2×P (1)  
MAX  
UNIT  
ns  
PRSI1 tw(PRU_DATAINL)  
PRSI2 tw(PRU_DATAINH)  
Pulse Duration, PRU_DATAIN Low  
Pulse Duration, PRU_DATAIN High  
ns  
(1) P = Internal shift in clock period, defined by PRU0_GPI_DIV0 and PRU0_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register.  
PRSI1  
PRSI2  
DATAIN  
SPRSP08_TIMING_PRU_05  
图7-98. PRU_ICSSG PRU Shift In Timing  
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7.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode  
NO.  
PARAMETER  
Cycle time, CLKOUT  
MIN  
10  
MAX  
UNIT  
PRSO1  
PRSO2  
tc(CLKOUT)  
ns  
tw(CLKOUTL)  
Pulse Duration, CLKOUT Low  
-0.3 +  
0.475×P×Z  
ns  
(1) (2)  
PRSO3  
PRSO4  
tw(CLKOUTH)  
Pulse Duration, CLKOUT High  
-0.3 +  
0.475×P×Y  
ns  
ns  
(1) (3)  
td(CLKOUT-DATAOUT)  
Delay time, CLKOUT to DATAOUT Valid  
-1  
4
(1) P = Software programmable shift out clock period, defined by PRU0_GPO_DIV0 and PRU0_GPO_DIV1 bit fields in the GPCFGn  
register.  
(2) The Z parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-  
INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a  
NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 + 0.5). If  
PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Z equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 +  
0.5 × PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Z equals (PRU0_GPI_DIV0 ×  
PRU0_GPI_DIV1 + 0.25 × PRU0_GPI_DIV0).  
(3) The Y parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NON-  
INTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a  
NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 - 0.5). If  
PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Y equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 -  
0.5 × PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRU0_GPI_DIV0 ×  
PRU0_GPI_DIV1 - 0.25 × PRU0_GPI_DIV0) and Y2 equals (PRU0_GPI_DIV0 × PRU0_GPI_DIV1 + 0.25 × PRU0_GPI_DIV0), where  
Y1 is the first high pulse and Y2 is the second high pulse.  
PRSO1  
PRSO2H  
PRSO2L  
CLOCKOUT  
DATAOUT  
PRSO3  
SPRSP08_TIMING_PRU_06  
图7-99. PRU_ICSSG PRU Shift Out Timing  
7.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing  
表7-71 presents PRU Sigma Delta and Peripheral timing conditions.  
表7-71. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
3
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
18  
7.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode  
NO.  
MIN  
40  
MAX  
UNIT  
ns  
PRSD1  
PRSD2L  
PRSD2H  
PRSD3  
tc(SD_CLK)  
tw(SD_CLKL)  
Cycle time, SD_CLK  
Pulse Duration, SD_CLK Low  
20  
ns  
tw(SD_CLKH)  
Pulse Duration, SD_CLK High  
20  
ns  
tsu(SD_DATA-SD_CLK)  
Setup time, SD_DATA valid before SD_CLK active edge  
10  
ns  
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NO.  
MIN  
MAX  
UNIT  
PRSD4  
th(SD_CLK-SD_DATA)  
Hold time, SD_DATA valid before SD_CLK active edge  
5
ns  
PRSD1  
PRSD2H  
SDx_CLK  
SDx_D  
PRSD2L  
PRSD4  
PRSD3  
SPRSP08_TIMING_PRU_07  
图7-100. PRU_ICSSG PRU SD_CLK Falling Active Edge  
PRSD2L  
SDx_CLK  
SDx_D  
PRSD4  
PRSD3  
SPRSP08_TIMING_PRU_08  
图7-101. PRU_ICSSG PRU SD_CLK Rising Active Edge  
7.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRPIF1 tw(PIF_DATA_INH)  
Pulse Duration, PIF_DATA_IN High  
2 + 0.475×  
(4×P) (1)  
ns  
PRPIF2 tw(PIF_DATA_INL)  
Pulse Duration, PIF_DATA_IN Low  
2 + 0.475×  
(4×P) (1)  
ns  
(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_Pn_TXCFG register.  
PRPIF1 PRPIF2  
PIF_DATA_IN  
SPRSP08_TIMING_PIF_01  
图7-102. PRU_ICSSG PRU Peripheral Interface Timing  
7.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode  
NO.  
DESCRIPTION  
Cycle time, PIF_CLK  
MIN  
MAX UNIT  
PRPIF1 tc(PIF_CLK)  
30  
ns  
ns  
0 + 0.475×P  
PRPIF2H tw(PIF_DATA_INH)  
PRPIF2L tw(PIF_DATA_INL)  
Pulse Duration, PIF_CLK High  
Pulse Duration, PIF_CLK Low  
(1)  
0 + 0.475×P  
ns  
(1)  
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NO.  
DESCRIPTION  
MIN  
-5  
MAX UNIT  
5 ns  
td(PIF_CLK-  
PRPIF3  
Delay time, PIF_CLK fall to PIF_DATA_OUT  
PIF_DATA_OUT)  
PRPIF4 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN  
-5  
5 ns  
(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the ICSSG_PRUn_ED_TX_CFG_REG,  
where n = 0 or 1.  
PRPIF1  
PRPIF2H  
PRPIF2L  
PIF_CLK  
PRPIF3  
PIF_DATA_OUT  
PRPIF4  
PIF_DATA_EN  
SPRSP08_TIMING_PIF_02  
图7-103. PRU_ICSSG PRU Peripheral Interface Switching Characteristics  
7.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)  
7.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing  
表7-72 presents the PRU_ICSSG PWM timing conditions.  
表7-72. PRU_ICSSG PWM Timing Conditions  
PARAMETER  
MIN  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
4
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRPWM1 tsk(PWM_A/B)  
PWM_A/B skew  
5
ns  
PWM_A/B  
PRPWM1  
SPRSP08_TIMING_PRU_PWM_01  
图7-104. PRU_ICSSG PRU PWM Timing  
7.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)  
7.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing  
7.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx  
NO.  
MIN  
MAX  
UNIT  
-2+20×P  
PRIEP1 tw(EDC_SYNCx_OUTL)  
Pulse Duration, EDC_SYNCx_OUT Low  
ns  
(1)  
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NO.  
MIN  
MAX  
UNIT  
-2+20×P  
PRIEP2 tw(EDC_SYNCx_OUTH)  
Pulse Duration, EDC_SYNCx_OUT High  
ns  
(1)  
tsu(EDIO_DATA_IN-  
PRIEP3  
Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active  
edge  
20  
20  
ns  
ns  
EDC_SYNCx_OUT)  
th(EDC_SYNCx_OUT-  
PRIEP4  
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active  
edge  
EDIO_DATA_IN)  
(1) P = PRU-ICSS IEP clock source period.  
EDC_SYNCx_OUT  
PRIEP2  
PRIEP1  
PRIEP3  
PRIEP4  
EDIO_DATA_IN[7:0]  
SPRSP08_TIMING_PRU_IEP_01  
图7-105. PRU_ICSSG PRU IEP SYNCx Timing  
7.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs  
NO.  
MIN  
MAX  
UNIT  
IEPIO1 tw(EDIO_OUTVALIDL)  
Pulse Duration, EDIO_OUTVALID Low  
Pulse Duration, EDIO_OUTVALID High  
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT  
EDIO_DATA_OUT skew  
-2+14×P  
ns  
(1)  
IEPIO2 tw(EDIO_OUTVALIDH)  
-2+32×P  
ns  
ns  
ns  
(1)  
IEPIO3 td(EDIO_OUTVALID-  
0
5
0+18×P  
(1)  
EDIO_DATA_OUT)  
IEPIO4 tsk(EDIO_DATA_OUT)  
(1) P = PRU-ICSS IEP clock source period.  
EDIO_DATA_OUT  
IEPIO4  
SPRSP08_TIMING_PRU_EDIO_DATA_OUT  
图7-106. PRU_ICSSG PRU IEP Digital IOs Timing  
7.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN  
NO.  
MIN  
2+3×P(1)  
2+3×P (1)  
MAX  
UNIT  
ns  
PRLA1 tw(EDC_LATCHx_INL)  
PRLA2 tw(EDC_LATCHx_INH)  
Pulse Duration, EDC_LATCHx_IN Low  
Pulse Duration, EDC_LATCHx_IN High  
ns  
(1) P = PRU-ICSS IEP clock source period.  
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PRLA1  
EDC_LATCHx_IN  
PRLA2  
SPRSP08_TIMING_PRU_IEP_02  
图7-107. PRU_ICSSG PRU IEP LATCHx_IN Timing  
7.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)  
7.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing  
表7-73 presents the PRU_ICSSG UART timing conditions.  
表7-73. PRU_ICSSG UART Timing Conditions  
PARAMETER  
MIN  
0.01  
1
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
0.33  
30  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
7.9.5.21.4.1.1 PRU_ICSSG UART Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRUR1H tw(RXH)  
Pulse Duration, Receive start, stop, data bit High  
2+0.95*U  
ns  
(1)  
PRUR1L tw(RXL)  
Pulse Duration, Receive start, stop, data bit Low  
2+0.95*U  
ns  
(1)  
(1) U = UART baud time = 1/programmed baud rate.  
7.9.5.21.4.1.2 PRU_ICSSG UART Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
MHz  
ns  
f(baud)  
Programmable baud rate  
12  
PRUR3L tw(TXH)  
PRUR3H tw(TXL)  
Pulse Duration, Transmit start, stop, data bit High  
Pulse Duration, Transmit start, stop, data bit Low  
-2+U(1)  
-2+U(1)  
ns  
(1) U = UART baud time = 1/programmed baud rate.  
PRUR1L  
PRUR1H  
Start  
Bit  
PRGi_UART0_RXD(1)  
Data Bits  
PRUR3L  
PRUR3H  
Start  
Bit  
PRGi_UART0_TXD(1)  
Data Bits  
(1) i in PRGi_UART0_RXD and PRGi_UART0_TXD = 0, 1 or 2  
SPRS91x_TIMING_PRU_UART_01  
图7-108. PRU_ICSSG UART Timing  
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7.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)  
7.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing  
表7-74 presents ECAP timing conditions.  
表7-74. PRU_ICSSG ECAP Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
1
3
7
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
7.9.5.21.5.1.1 PRU_ICSSG ECAP Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
2+2×P (1)  
2+2×P (1)  
MAX  
UNIT  
ns  
PREP1 tw(CAP)  
Pulse Duration, Capture input (asynchronous)  
Pulse Duration, Sync input (asynchronous)  
PREP2 tw(SYNCI)  
ns  
(1) P = core_clk period  
PREP1  
PREP2  
CAP  
SYNCI  
SPRSP08_TIMING_ECAP_01  
图7-109. PRU_ICSSG ECAP Timing  
7.9.5.21.5.1.2 PRU_ICSSG ECAP Switching Characteristics  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
-2+2×P (1)  
-2+P (1)  
MAX  
UNIT  
ns  
PREP3 tw(APWM)  
PREP4 tw(SYNCO)  
Pulse Duration, APWM high/low  
Pulse Duration, SYNCO (asynchronous)  
ns  
(1) P = CORE_CLK period in ns  
PREP3  
APWM  
SYNCO  
SPRSP08_TIMING_ECAP_02  
图7-110. PRU_ICSSG ECAP Switching Characteristics  
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7.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch  
7.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing  
表7-75 presents MDIO timing conditions.  
表7-75. PRU_ICSSG MDIO Timing Conditions  
PARAMETER  
MIN  
0.9  
10  
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
470  
7.9.5.21.6.1.1 PRU_ICSSG MDIO Timing Requirements  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
90  
0
MAX  
UNIT  
ns  
PRMDI1 tsu(MDIO-MDC)  
PRMDI2 th(MDC-MDIO)  
Setup time, MDIO valid before MDC High  
Hold time, MDIO valid after MDC High  
ns  
PRMDI1  
PRMDI2  
MDIO_CLK (Output)  
MDIO_DATA (Input)  
SPRS91x_TIMING_PRU_MII_RT_01  
图7-111. PRU_ICSSG MDIO_DATA Timing –Input Mode  
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7.9.5.21.6.1.2 PRU_ICSSG MDIO Switching Characteristics - MDIO_CLK  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
400  
160  
160  
MAX  
UNIT  
ns  
PRMC1 tc(MDC)  
PRMC2 tw(MDCH)  
PRMC3 tw(MDCL)  
Cycle time, MDC  
Pulse Duration, MDC High  
Pulse Duration, MDC Low  
ns  
ns  
PRMC1  
PRMC4  
PRMC2  
PRMC3  
MDIO_CLK  
PRMC4  
SPRS91x_TIMING_PRU_MII_RT_02  
图7-112. PRU_ICSSG MDIO_CLK Switching Characteristics  
7.9.5.21.6.1.3 PRU_ICSSG MDIO Switching Characteristics –MDIO_DATA  
NO.  
PARAMETER  
DESCRIPTION  
MIN  
MAX  
UNIT  
PRMDO1 td(MDC-MDIO)  
Delay time, MDC low to MDIO valid  
-150  
150  
MHz  
PRMDO1  
MDIO_CLK (Output)  
MDIO_DATA (Output)  
SPRS91x_TIMING_PRU_MII_RT_03  
图7-113. PRU_ICSSG MDIO_DATA Switching Characteristics  
7.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing  
表7-76 presents the PRU_ICSSG RGMII timing conditions.  
表7-76. PRU_ICSSG RGMII Timing Conditions  
PARAMETER  
MODE  
MIN  
2.65  
2
MAX UNIT  
INPUT CONDITIONS  
SRI  
Input slew rate  
5
V/ns  
pF  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
PCB Connectivity Requirements  
RXC,  
RD[3:0],RX_CTL  
50  
50  
ps  
ps  
td(Trace Mismatch  
Propagation delay mismatch across all traces  
Delay)  
TXC,  
TD[3:0],TX_CTL  
7.9.5.21.6.2.1 PRU_ICSSG RGMII Timing Requirements - RGMII_RXC  
NO.  
MODE  
10 Mbps  
100 Mbps  
1000 Mbps  
MIN  
MAX UNIT  
360  
36  
440  
44  
ns  
ns  
ns  
PRRG1 tc(RXC)  
Cycle time, RXC  
7.2  
8.8  
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NO.  
MODE  
10 Mbps  
MIN  
160  
16  
MAX UNIT  
240  
24  
ns  
ns  
ns  
ns  
ns  
ns  
PRRG2 tw(RXCH)  
Pulse duration, RXC high  
Pulse duration, RXC low  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
PRRG3 tw(RXCL)  
100 Mbps  
1000 Mbps  
3.6  
4.4  
PRRG1  
PRRG2  
PRRG3  
RGMII_RXC  
PRRG4  
SPRS91x_TIMING_PRU_RGMII_RT_04  
图7-114. PRU_ICSSG RGMII_RCLK Timing Requirements  
7.9.5.21.6.2.2 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RX_CTL  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
PRRG5 tsu(RD-RXC)  
Setup time, RD[3:0] valid before RXC high/low  
10 Mbps  
100 Mbps  
1000 Mbps  
1
ns  
tsu(RX_CTL-RXC)  
Setup time, RX_CTL valid before RXC high/low  
Hold time, RD[3:0] valid after RXC high/low  
Hold time, RX_CTL valid after RXC high/low  
10 Mbps  
100 Mbps  
1000 Mbps  
1
1.15  
1.15  
ns  
ns  
ns  
PRRG6 th(RXC-RD)  
10 Mbps  
100 Mbps  
1000 Mbps  
th(RXC-RX_CTL)  
10 Mbps  
100 Mbps  
1000 Mbps  
PRPG5  
PRPG6  
RGMII_RXCLK (Input)  
RGMII_RXD[3:0],  
RGMII_RXDV,  
RGMII_RXER (Inputs)  
PRPG7  
SPRS91x_TIMING_PRU_RGMII_RT_05  
图7-115. PRU_ICSSG RGMII_RD[3:0] and RGMII_RX_CTL Timing Requirements  
7.9.5.21.6.2.3 PRU_ICSSG RGMII Switching Characteristics - RGMII_TXC  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
360  
36  
MAX UNIT  
PRRG8 tc(TXC)  
Cycle time, TXC  
440  
44  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
7.2  
8.8  
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MAX UNIT  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
MIN  
160  
16  
PRRG9 tw(TXCH)  
Pulse duration, TXC high  
240  
24  
ns  
ns  
ns  
ns  
ns  
ns  
100 Mbps  
1000 Mbps  
10 Mbps  
3.6  
160  
16  
4.4  
240  
24  
PRRG10 tw(TXCL)  
Pulse duration, TXC low  
100 Mbps  
1000 Mbps  
3.6  
4.4  
PRRG11  
PRRG8  
PRRG9  
PRRG10  
RGMII_TXC  
PRRG11  
SPRS91x_TIMING_PRU_RGMII_RT_06  
图7-116. PRU_ICSSG RGMII_TXC Switching Characteristics  
7.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
TYP  
MAX UNIT  
PRRG12 tosu(TD-TXC)  
Output setup time, RGMII[x]_TD[3:0] valid to  
RGMII[x]_TXC high/low  
10 Mbps  
100 Mbps  
1.2  
ns  
1000 Mbps  
1.05(1)  
1.2  
ns  
ns  
tosu(TX_CTL-TXC)  
Output setup time, RGMII[x]_TX_CTL valid to  
RGMII[x]_TXC high/low  
10 Mbps  
100 Mbps  
1000 Mbps  
1.05(1)  
1.2  
ns  
ns  
PRRG13 toh(TD-TXC)  
Output hold time, RGMII[x]_TD[3:0] valid after  
RGMII[x]_TXC high/low  
10 Mbps  
100 Mbps  
1000 Mbps  
1.05(1)  
1.2  
ns  
ns  
toh(TX_CTL-TXC)  
Output hold time, RGMII[x]_TX_CTL valid after  
RGMII[x]_TXC high/low  
10 Mbps  
100 Mbps  
1000 Mbps  
1.05(1)  
ns  
(1) 1000Mbps operation requires that the 4 data pins (RGMII[x]_TD[3:0]) and RGMII[x]_TX_CTL have their board propagation delays  
matched to within 50 ps of RGMII[x]_TXC.  
A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.  
B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of  
RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC  
and RTXERR on falling edge of RGMII_TXC.  
图7-117. PRU_ICSSG Transmit Interface Timing RGMII Mode  
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7.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing  
Note  
The PRU_ICSSG are contains a second layer of multiplexing to enable additional functionality  
(including MII functionality) on the PRU GPO and GPI signals. This internal wrapper multiplexing is  
described in the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem  
- Gigabit (PRU_ICSSG) section in Peripherals chapter in the device TRM.  
Note  
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the  
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz,  
225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1  
register must be set to 0h (default value).  
表7-77 presents PRU_ICSSG MII timing conditions.  
表7-77. PRU_ICSSG MII Timing Conditions  
PARAMETER  
MIN  
0.9  
2
MAX  
3.6  
UNIT  
V/ns  
pF  
INPUT CONDITIONS  
SRI  
Input slew rate  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
20  
7.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements –MII_RX_CLK  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
PMIR1 tc(RX_CLK)  
PMIR2 tw(RX_CLKH)  
PMIR3 tw(RX_CLKL)  
Cycle time, RX_CLK  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
Pulse Duration, RX_CLK High  
Pulse Duration, RX_CLK Low  
140  
14  
260  
26  
140  
14  
260  
26  
PMIR1  
PMIR2  
PMIR3  
MII_RXCLK  
SPRS91x_TIMING_PRU_MII_RT_04  
图7-118. PRU_ICSSG MII_RXCLK Timing  
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7.9.5.21.6.3.2 PRU_ICSSG MII_RT Timing Requirements –MII_RXD[3:0], MII_RX_DV, and MII_RX_ER  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
8
MAX  
UNIT  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PMIR4 tsu(RXD-RX_CLK)  
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
tsu(RXD-RX_CLK)  
Setup time, RXD[3:0] valid before RX_CLK  
Setup time, RX_DV valid before RX_CLK  
Setup time, RX_ER valid before RX_CLK  
Setup time, RXD[3:0] valid before RX_CLK  
Setup time, RX_DV valid before RX_CLK  
Setup time, RX_ER valid before RX_CLK  
Hold time, RXD[3:0] valid after RX_CLK  
Hold time, RX_DV valid after RX_CLK  
Hold time, RX_ER valid after RX_CLK  
Hold time, RXD[3:0] valid after RX_CLK  
Hold time, RX_DV valid after RX_CLK  
Hold time, RX_ER valid after RX_CLK  
10 Mbps  
8
8
100  
Mbps  
8
tsu(RX_DV-RX_CLK)  
tsu(RX_ER-RX_CLK)  
PMIR5 th(RX_CLK-RXD)  
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
th(RX_CLK-RXD)  
8
8
10 Mbps  
8
8
8
100  
Mbps  
8
th(RX_CLK-RX_DV)  
th(RX_CLK-RX_ER)  
8
8
PMIR4  
PMIR5  
MII_MRCLK (Input)  
MII_RXD[3:0],  
MII_RXDV,  
MII_RXER (Inputs)  
SPRS91x_TIMING_PRU_MII_RT_06  
图7-119. PRU_ICSSG MII_RXD[3:0], MII_RXDV, and MII_RXER Timing  
7.9.5.21.6.3.3 PRU_ICSSG MII_RT Switching Characteristics –MII_TX_CLK  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
10 Mbps  
100 Mbps  
MIN  
MAX UNIT  
PMIT1 tc(TX_CLK)  
PMIT2 tw(TX_CLKH)  
PMIT3 tw(TX_CLKL)  
Cycle time, TX_CLK  
399.96 400.04  
39.996 40.004  
ns  
ns  
ns  
ns  
ns  
ns  
Pulse Duration, TX_CLK High  
Pulse Duration, TX_CLK Low  
140  
14  
260  
26  
140  
14  
260  
26  
PMIT1  
PMIT4  
PMIT2  
PMIT3  
MII_TXCLK  
PMIT4  
SPRS91x_TIMING_PRU_MII_RT_05  
图7-120. PRU_ICSSG MII_TX_CLK Switching Characteristics  
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7.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics –MII_TXD[3:0] and MII_TXEN  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
MIN  
0
MAX  
25  
UNIT  
ns  
PMIT5 td(TX_CLK-TXD)  
td(TX_CLK-TX_EN)  
td(TX_CLK-TXD)  
Delay time, TX_CLK High to TXD[3:0] valid  
Delay time, TX_CLK to TX_EN valid  
Delay time, TX_CLK High to TXD[3:0] valid  
Delay time, TX_CLK to TX_EN valid  
10 Mbps  
0
25  
ns  
100  
Mbps  
0
25  
ns  
td(TX_CLK-TX_EN)  
0
25  
ns  
PMIT5  
MII_TXCLK (input)  
MII_TXD[3:0],  
MII_TXEN (outputs)  
SPRS91x_TIMING_PRU_MII_RT_07  
图7-121. PRU_ICSSG MII_TXD[3:0], MII_TXEN Timing  
For more information, see section Programmable Real-Time Unit Subsystem and Industrial Communication  
Subsystem - Gigabit (PRU_ICSSG) in the device TRM.  
7.9.5.22 Timers  
For more details about features and additional description information on the device Timers, see the  
corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
节7.9.5.22.1, 节7.9.5.22.2 and 图7-122 present timings and switching characteristics of the Timers.  
7.9.5.22.1 Timing Requirements for Timers  
NO.  
T1  
PARAMETER  
tw(TINPH)  
DESCRIPTION  
MODE  
MIN  
MAX UNIT  
Pulse duration, high  
Pulse duration, low  
CAPTURE 5 + 4P(1)  
CAPTURE 5 + 4P(1)  
ns  
ns  
T2  
tw(TINPL)  
(1) P = functional clock period in ns.  
7.9.5.22.2 Switching Characteristics for Timers  
NO.  
T3  
PARAMETER  
tw(TOUTH)  
DESCRIPTION  
MODE  
PWM  
PWM  
MIN  
-3 + 4P(1)  
-3 + 4P(1)  
MAX  
UNIT  
ns  
Pulse duration, high  
Pulse duration, low  
T4  
tw(TOUTL)  
ns  
(1) P = functional clock period in ns.  
T1  
T2  
TIMIx  
T3  
T4  
TIMOx  
TIMER_01  
图7-122. Timer Timing  
For more information, see section Timers in the device TRM.  
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7.9.5.23 UART  
For more details about features and additional description information on the device Universal Asynchronous  
Receiver Transmitter, see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed  
Description.  
节 7.9.5.23.1, 节 7.9.5.23.2, and 图 7-123 present Timing Requirements and Switching Characteristics for UART  
interface.  
7.9.5.23.1 Timing Requirements for UART  
NO.  
4
PARAMETER  
tw(RX)  
DESCRIPTION  
MIN  
0.95U(1)  
0.95U(1)  
P(2)  
MAX  
1.05U(1)  
1.05U(1)  
UNIT  
ns  
Pulse width, receive data bit, 15/30 pF high or low  
Pulse width, receive start bit, 15/30 pF high or low  
Delay time, transmit start bit to transmit data  
Delay time, receive start bit to transmit data  
5
tw(CTS)  
ns  
td(RTS-TX)  
td(CTS-TX)  
ns  
P(2)  
ns  
(1) U = UART baud time = 1/Programmed baud rate  
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192 MHz)  
7.9.5.23.2 Switching Characteristics Over Recommended Operating Conditions for UART  
NO.  
PARAMETER  
DESCRIPTION  
MODE  
15 pF  
30 pF  
MIN  
MAX  
12  
UNIT  
f(baud)  
Maximum programmable baud rate  
MHz  
0.115  
U + 2(1)  
U + 2(1)  
2
3
tw(TX)  
Pulse width, transmit data bit, 15/30 pF high or low  
Pulse width, transmit start bit, 15/30 pF high or low  
U - 2(1)  
U - 2(1)  
ns  
ns  
tw(RTS)  
(1) U = UART baud time = 1/Programmed baud rate  
3
2
Start  
Bit  
UARTi_TXD  
Data Bits  
5
4
Start  
Bit  
UARTi_RXD  
Data Bits  
图7-123. UART Timing  
For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in the device TRM.  
7.9.5.24 USB  
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the  
specification for timing details.  
The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1  
Specification, revision 1.0. Refer to the specification for timing details.  
For more details about features and additional description information on the device Universal Serial Bus  
Subsystem (USB), see the corresponding sections within 节 6.3, Signal Descriptions and 节 8, Detailed  
Description.  
For more information, see the Universal Serial Bus (USB) Subsystem section in the device TRM.  
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7.9.5.25 Emulation and Debug  
7.9.5.25.1 Debug Trace  
表 7-79 and 图 7-124 assume testing over the recommended operating conditions and electrical characteristic  
conditions.  
表7-78. Debug Trace Timing Conditions  
PARAMETER  
MIN  
MAX  
UNIT  
OUTPUT CONDITIONS  
CL  
Output load capacitance  
2
5
pF  
PCB CONNECTIVITY REQUIREMENTS  
Propagation delay mismatch across  
all traces  
td(Trace Mismatch)  
200  
ps  
表7-79. Debug Trace Switching Characteristics  
DESCRIPTION  
NO.  
PARAMETER  
MIN  
10.16  
4.33  
MAX  
UNIT  
DBTR1 tc(TRC_CLK)  
DBTR2 tw(TRC_CLKH)  
DBTR3 tw(TRC_CLKL)  
Cycle time, TRC_CLK  
ns  
ns  
ns  
ns  
Pulse width, TRC_CLK high  
Pulse width, TRC_CLK low  
4.33  
DBTR4 tosu(TRC_DATAV-  
Output setup time, TRC_DATA valid to TRC_CLK edge  
1.27  
TRC_CLK)  
DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid  
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge  
1.27  
1.27  
1.27  
ns  
ns  
ns  
DBTR7 toh(TRC_CLK-TRC_CTLI)  
Output hold time, TRC_CLK edge to TRC_CTL invalid  
DBTR1  
DBTR2  
DBTR3  
TRC_CLK  
(Worst Case 1)  
(Ideal)  
(Worst Case 2)  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
DBTR4  
DBTR6  
DBTR5  
DBTR7  
TRC_DATA  
TRC_CTL  
SPRSP08_Debug_01  
图7-124. Debug Trace Switching Characteristics  
7.9.5.25.2 JTAG  
For more details about features and additional description information on the device IEEE 1149.1 Standard-Test-  
Access Port, see the corresponding sections within 节6.3, Signal Descriptions and 节8, Detailed Description.  
表7-80 presents the timing conditions for JTAG.  
表7-80. JTAG Timing Conditions  
PARAMETER  
SIGNAL  
MIN  
MAX  
UNIT  
INPUT CONDITIONS  
TCK  
0.5  
2.00  
2.00  
V/ns  
V/ns  
SRI  
Input slew rate  
TDI, TMS  
0.25  
OUTPUT CONDITIONS  
CL Output load capacitance  
TDO  
5
15  
pF  
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7.9.5.25.2.1 JTAG Electrical Data and Timing  
节 7.9.5.25.2.1.1, 节 7.9.5.25.2.1.2, and 图 7-125 assume testing over the recommended operating conditions  
and electrical characteristic conditions.  
7.9.5.25.2.1.1 JTAG Timing Requirements  
NO.  
J1  
PARAMETER  
tc(TCK)  
DESCRIPTION  
MIN  
60  
24  
24  
7
MAX  
UNIT  
ns  
Cycle time minimum, TCK  
J2  
tw(TCKH)  
Pulse width minimum, TCK high  
ns  
J3  
tw(TCKL)  
Pulse width minimum, TCK low  
ns  
J4  
tsu(TDI-TCK)  
tsu(TMS-TCK)  
th(TCK-TDI)  
th(TCK-TMS)  
Input setup time minimum, TDI valid to TCK high  
Input setup time minimum, TMS valid to TCK high  
Input hold time minimum, TDI valid from TCK high  
Input hold time minimum, TMS valid from TCK high  
ns  
7
ns  
J5  
4
ns  
4
ns  
7.9.5.25.2.1.2 JTAG Switching Characteristics  
NO.  
J6  
PARAMETER  
td(TCKL-TDOI)  
td(TCKL-TDOV)  
DESCRIPTION  
MIN  
MAX  
UNIT  
ns  
Delay time minimum, TCK low to TDO invalid  
Delay time maximum, TCK low to TDO valid  
0
J7  
24  
ns  
J1  
J2  
J3  
TCK  
TDI / TMS  
TDO  
J4  
J5  
J4  
J5  
J7  
J6  
图7-125. JTAG Test-Port Timing  
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8 Detailed Description  
8.1 Overview  
AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing  
needs of modern industry 4.0 embedded products.  
The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Cortex-R5F MCU  
subsystem which includes features intended to help customers achieve their functional safety goals for their end  
products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of  
high-performance industrial controls with industrial connectivity and processing for functional safety applications.  
AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.  
The four A53 cores are arranged in two dual-core clusters with shared L2 memory to create two processing  
channels. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC  
as a whole includes features intended to help customers design systems that can achieve their functional safety  
goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on  
AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.  
Programmability is provided by the quad-core Arm Cortex-A53 RISC CPUs with Neon extension, and the dual  
Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to  
help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up  
to six ports of industrial Ethernet such as Profinet IRT, TSN, or EtherCAT® (among many others), or they can be  
used for standard Gigabit Ethernet connectivity.  
TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux,  
Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code  
execution. Applicable safety documentation will be made available to assist customers in developing their  
functional safety related systems.  
Note  
For more information on features, subsystems, and architecture of superset device System on Chip  
(SoC), see the device TRM.  
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8.2 Processor Subsystems  
8.2.1 Arm Cortex-A53  
The SoC implements two Dual-Core Arm Cortex-A53 Subsystems (CC_ARMSS0 and CC_ARMSS1), which are  
both integrated inside the Compute Cluster (along with the MSMC module). The Cortex-A53 cores are general-  
purpose processors that can be used for running customer applications.  
The CC_ARMSS is built around the Cortex-A53 MPCore (Arm A53 Cluster), which is provided by Arm and  
configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high  
performance and optimal power management, debug and emulation capabilities.  
The A53 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 Instruction and  
Data Caches, compatible with Arm®v8-A architecture. It delivers significantly more performance than its  
predecessors at a higher level of power efficiency.  
For more information, see Compute Cluster Arm Cortex-A53 Subsystem section in the device TRM.  
8.2.2 Arm Cortex-R5F  
The MCU_ARMSS is a dual-core implementation of the Arm Cortex-R5F processor configured for split/lock  
operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm®  
CoreSight® debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and  
various other modules for protocol conversion and address translation for easy integration into the SoC.  
For more information, see MCU Arm Cortex-R5F Subsystem section in the device TRM.  
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8.3 Accelerators and Coprocessors  
8.3.1 PRU_ICSSG  
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)  
consists of:  
• Two 32-bit load/store RISC CPU cores —Programmable Real-Time Units (PRU0 and PRU1)  
• Two auxiliary 32-bit load/store RISC CPU cores —Auxiliary Programmable Real-Time Units (RTU_PRU0 and  
RTU_PRU1)  
• Data RAMs per PRU core  
• Instruction RAMs per PRU and per RTU_PRU cores  
• Shared RAM  
• Peripheral modules: UART0, ECAP0, PWM, IEP0 and IEP1  
• Interrupt controller (INTC)  
The programmable nature of the PRU cores, along with their access to pins, events and all device resources,  
provides flexibility in implementing fast real-time responses, specialized data handling operations, custom  
peripheral interfaces, and in offloading tasks from the other processor cores of the device.  
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate  
independently or in coordination with each other and can also work in coordination with the device-level host  
CPU. This interaction between processors is determined by the nature of the firmware loaded into the PRU’s  
instruction memory.  
8.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores  
The PRU is a processor optimized for performing embedded tasks that require manipulation of packed memory  
mapped data structures, handling of system events that have tight real-time constraints and interfacing with  
systems external to the SoC. The PRU is both very small and very efficient at handling such tasks.  
8.3.1.2 PRU_ICSSG Broadside Accelerators Overview  
The PRU_ICSSG supports a broadside interface, which uses the XFR (XIN, XOUT, or XCHG) instruction to  
transfer the contents of PRUn or RTU_PRUn (where n = 0 or 1) registers to or from accelerators with the  
PRU_ICSSG. This interface enables up to 31 registers (R0-R30, or 124 bytes) to be transferred in a single  
instruction. The PRU_ICSSG broadside accelerators are divided into two categories – data processing  
accelerators and data movement accelerators.  
8.3.1.3 PRU_ICSSG UART Module  
The PRU_ICSSG UART0 peripheral is based on the industry standard TL16C550 asynchronous  
communications element, which in turn is a functional upgrade of the TL16C450.  
The PRU_ICSSG UART0 performs serial-to-parallel conversions on data received from a peripheral device and  
parallel-to-serial conversion on data received from the CPU. The CPU can read the PRU_ICSSG UART0 status  
at any time. The PRU_ICSSG UART0 includes control capability and a processor interrupt system that can be  
tailored to minimize software management of the communications link.  
8.3.1.4 PRU_ICSSG ECAP Module  
A single instance of an Enhanced Capture event module (ECAP0) is integrated in each device PRU_ICSSG0,  
PRU_ICSSG1 and PRU_ICSSG2 subsystem.  
This module provides accurate timing of events. When not being used for event capture, its resources can be  
used to generate a single channel of asymmetrical PWM waveforms (configurable as either one capture input, or  
as one auxiliary PWM output).  
8.3.1.5 PRU_ICSSG PWM Module  
Each of the PRU_ICSSG modules integrates one Pulse Width Modulation module (PWM). The PWM module  
uses the PRU_ICSSG IEP0 and IEP1 compare events to produce the PWM outputs.  
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8.3.1.6 PRU_ICSSG MII_G_RT Module  
The Real-time Media Independent Interface (MII_G_RT) provides a programmable I/O interface for the PRUs to  
access and control up to two MII ports. The MII_G_RT module can also be configured to push and pull data  
independent of the PRU cores.  
8.3.1.7 PRU_ICSSG MII MDIO Module  
The PRU_ICSSG MII MDIO management I/F module implements the 802.3 serial management interface to  
interrogate and control two Ethernet PHYs simultaneously using a shared two-wire bus.  
8.3.1.8 PRU_ICSSG IEP  
The Industrial Ethernet Peripheral (IEP) performs hardware work required for Industrial Ethernet functions. The  
IEP module features an industrial ethernet timer with 16 compare events, industrial ethernet sync generator and  
latch capture, industrial ethernet watchdog timer, and a digital I/O port (DIGIO).  
For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem -  
Gigabit (PRU_ICSSG) section in the device TRM.  
8.3.2 GPU  
The Graphics Processing Unit (GPU) accelerates 2-dimensional (2D) and 3-dimensional (3D) graphics and  
compute applications.  
The GPU module is a scalable architecture which efficiently processes a number of differing multimedia data  
types concurrently:  
• Pixel Data  
• Vertex Data  
• General Purpose Processing  
For more information, see Graphics Accelerator (GPU) section in the device TRM.  
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8.4 Other Subsystems  
8.4.1 DMSC  
Integrated in WKUP domain Device Management and Security Controller (WKUP_DMSC) provides control over  
the device boot sequencing, device management, power management, and security. With the factory-sealed  
firmware, DMSC main functions include:  
• Device management  
• On-chip power management and wake-up control  
• Device boot configuration and sequence  
• Secure boot setup  
• Authentication routines (all modes), including R5F island only boot modes  
• Decryption routines  
• Firewall control for isolation and Security  
• Runtime Security Management and resource allocation  
• Arm Cortex-M3 based DMSC acts as system security master and protects critical security assets during run-  
time. As part of booting on High Security (HS) device, DMSC uses on-chip keys to establish root-of-trust and  
authenticate images to reinforce trust. DMSC controls the power management of device, hence is  
responsible to bring device cleanly out of reset and enforce clock and reset rules. DMSC power management  
functions are critical to bring device to low power modes and sense wakeup events to bring device back to  
active state. DMSC acts also as main boot processor and as such is the very first subsystem that is brought  
out of reset after device power-on-reset.  
For more information, see WKUP Device Management and Security Controller (DMSC) section in the device  
TRM.  
8.4.2 MSMC  
The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster  
(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected  
processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute  
cluster.  
For more information, see Multicore Shared Memory Controller (MSMC) section in the device TRM.  
8.4.3 NAVSS  
8.4.3.1 NAVSS0  
Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and  
Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), and a North Bridge (NBSS).  
UDMASS –UDMASS is the essential part of the DMA Architecture. UDMASS consists of:  
• Unified DMA Controller  
• Ring Accelerator  
• Packet Streaming Interface (PSI-L)  
MODSS – MODSS is a collection of peripherals with different system-level functions, for example,  
interprocessor communication and time sync, among others. NAVSS0 contains the following modules:  
• Mailbox  
• Spinlock  
• Two Timer Managers (Timer banks)  
• Time Stamp Module (CPTS)  
• Memory CRC module  
• Infrastructure components such as:  
– CBASS  
– Proxies  
– Interrupt aggregators  
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– Interrupt router  
NBSS –This is a north bridge infrastructure  
8.4.3.2 MCU_NAVSS0  
MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated  
in the MCU domain.  
MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator  
(UDMASS), and Peripherals (Module subsystem [MODSS]).  
UDMASS –UDMASS is the essential part of the DMA Architecture. UDMASS consists of:  
• Unified DMA Controller  
• Ring Accelerator  
• Packet Streaming Interface (PSILSS)  
MODSS – MODSS is a collection of peripherals with different system-level functions. NAVSS0 contains the  
following modules:  
• Memory CRC module  
• Infrastructure components such as CBASS, proxies, interrupt aggregators, and an interrupt router  
ECC aggregators –for SEC/DED memory protection.  
For more information, see Navigator Subsystem (NAVSS) section in the device TRM.  
8.4.4 PDMA Controller  
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of  
peripherals, which perform data transfers using memory mapped registers (MMRs) accessed via a standard  
non-coherent bus fabric. The PDMA module is located close to one or more peripherals which require an  
external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting  
only statically configured Transfer Request (TR) operations.  
The PDMA is only responsible for performing the data movement transactions which interact with the peripherals  
themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data  
stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of  
the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to  
a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral.  
For more information, see PDMA Controller section in the device TRM.  
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8.4.5 Peripherals  
8.4.5.1 ADC  
The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1  
of 8 analog inputs (channels).  
For more information, see Analog-to-Digital Converter (ADC) section in the device TRM.  
8.4.5.2 CAL  
The Camera Adapter Layer Subsystem (CALSS) is based on a Camera Adaptation Layer (CAL) module, which  
enables connection to multiple camera sensors through shared MIPI D-PHY module and LVDS receiver.  
CAL Module (CALSS0) is a very flexible subsystem that enables connection to multiple cameras supporting MIPI  
CSI-2 over D-PHY serial interface, a LVDS serial interface, and a traditional parallel interface. It also includes an  
internal write DMA engine connected to VBUSM interface.  
For more information, see Camera Adapter Layer (CAL) Subsystem section in the device TRM.  
8.4.5.3 CPSW2G  
The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication for the  
device and is configured in a similar manner as a two-port Ethernet switch. MCU_CPSW0 features the Reduced  
Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the  
Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.  
For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in the device TRM.  
8.4.5.4 DCC  
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution  
of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The  
desired accuracy can be programed based on calculation for each application. The DCC measures the  
frequency of a selectable clock source using another input clock as a reference.  
For more information, see Dual Clock Comparator (DCC) section in the device TRM.  
8.4.5.5 DDRSS  
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these  
blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to  
external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC,  
and not directly through the system interconnect.  
For more information, see DDR Subsystem (DDRSS) section in the device TRM.  
8.4.5.6 DSS  
The Display Subsystem (DSS) is a flexible, multi-pipeline subsystem that supports high-resolution display  
outputs. DSS includes input pipelines providing multi-layer blending with transparency to enable on-the-fly  
composition. Various pixel processing capabilities are supported, such as color space conversion and scaling,  
among others. DSS includes a DMA engine, which allows direct access to the frame buffer (device system  
memory). Display outputs can connect seamlessly to an Open LVDS Display Interface transmitter (OLDITX), or  
can directly drive device pads as a parallel video output interface.  
For more information, see Display Subsystem (DSS) section in the device TRM.  
8.4.5.7 ЕCAP  
Integrated in the MAIN domain one Enhanced Capture (ECAP) module provides accurate timing of events.  
When not being used for event capture, its resources can be used to generate a single channel of asymmetrical  
PWM waveforms (configurable as either one capture input, or as one auxiliary PWM output).  
ECAP module can be used for:  
• Sample rate measurements of audio inputs  
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• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)  
• Elapsed time measurements between position sensor pulses  
• Period and duty cycle measurements of pulse train signals  
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.  
For more information, see Enhanced Capture (ECAP) Module section in the device TRM.  
8.4.5.8 EPWM  
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU  
overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand  
and use. The EPWM unit described here addresses these requirements by allocating all needed timing and  
control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided;  
instead, the EPWM is built up from smaller single channel modules with separate resources and that can  
operate together as required to form a system. This modular approach results in an orthogonal architecture and  
provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.  
For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in the device TRM.  
8.4.5.9 ELM  
The ELM is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash page  
and stored in GPMC registers are passed to the ELM. A host processor can then correct the data block by  
flipping the bits to which the ELM error-location outputs point.  
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND  
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is  
delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash.  
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses this  
to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome  
polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an  
optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-  
Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome  
polynomials.  
Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and give  
the location of each error bit. The actual data is not required to complete the error-correction algorithm. Errors  
can be reported anywhere in the NAND flash block, including in the parity bits.  
For more information, see Error Location Module (ELM) section in the device TRM.  
8.4.5.10 ESM  
The Error Signaling Module (ESM) aggregates safety-related events and errors from throughout the device into  
one location. It can signal both low and high priority interrupts to a processor to deal with a safety event and/or  
manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an external  
controller is able to reset the device or keep the system in a safe, known state.  
For more information, see Error Signaling Module (ESM) section in the device TRM.  
8.4.5.11 EQEP  
The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary  
incremental encoder to get position, direction and speed information from a rotating machine for use in high  
performance motion and position control system.  
For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in the device TRM.  
8.4.5.12 GPIO  
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be  
configured as either inputs or outputs. When configured as an output, the user can write to an internal register to  
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control the state driven on the output pin. When configured as an input, user can obtain the state of the input by  
reading the state of an internal register.  
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different  
interrupt/event generation modes.  
The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per bank and  
9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose pins  
with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks  
× 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this  
device, general purpose interface supports up to 242 pins.  
For more information, see General-Purpose Interface (GPIO) section in the device TRM.  
8.4.5.13 GPMC  
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external  
memory devices like:  
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices  
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash  
devices  
• NAND flash  
• Pseudo-SRAM devices  
For more information, see General-Purpose Memory Controller (GPMC) section in the device TRM.  
8.4.5.14 HyperBus  
Note  
HyperBus is not available on this device.  
The HyperBus module is a part of the device Flash Subsystem (FSS).  
The HyperBus module is a low pin count memory interface that provides high read/write performance. The  
HyperBus module connects to HyperBus memory (HyperFlash or HyperRAM) and uses simple HyperBus  
protocol for read and write transactions.  
There is one HyperBus™ module inside the device. The HyperBus module includes one HyperBus Memory  
Controller (HBMC).  
For more information, see HyperBus Interface section in the device TRM.  
8.4.5.15 I2C  
The device contains six multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface  
between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via the I2C serial  
bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to and  
from the LH device through the 2-wire I2C interface.  
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.  
The WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and support fast  
mode (up to 400 Kbps).The I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with standard LVCMOS I/O  
and connected to emulate open drain.The I2C emulation is achieved by configuring the LVCMOS buffers to  
output Hi-Z instead of driving high when transmitting logic 1.  
For more information, see Inter-Integrated Circuit (I2C) Interface section in the device TRM.  
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8.4.5.16 MCAN  
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed  
real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are  
broadcast to the entire network, which provides for data consistency in every node of the system.  
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN  
FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices  
can coexist on the same network without any conflict.  
The device supports two MCAN modules - MCU_MCAN0 and MCU_MCAN1. They connect to the physical layer  
of the CAN network through external (for the device) transceivers. Each MCAN module supports flexible bit rates  
greater than 1 Mbps and is compliant to ISO 11898-1:2015.  
For more information, see Modular Controller Area Network (MCAN) section in the device TRM.  
8.4.5.17 MCASP  
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio  
applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for  
time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for  
an intercomponent digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly connect  
to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.  
Although intercomponent digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not  
natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows  
an easy connection to external DIR components (for example, S/PDIF to I2S format converters).  
For more information, see Multichannel Audio Serial Port (MCASP) section in the device TRM.  
8.4.5.18 MCRC  
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the  
integrity of a memory system. A signature representing the contents of the memory is obtained when the  
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the  
signature for a set of data and then compare the calculated signature value against a predetermined good  
signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in  
parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC  
controller compresses each data being read through CPU read data bus.  
For more information, see Memory Cyclic Redundancy Check (MCRC) Controller section in the device TRM.  
8.4.5.19 MCSPI  
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.  
There are total of eight MCSPI modules in the device.  
MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:  
• MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and MCSPI3  
may be optionally mapped to external device pads.  
• MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and  
MCU_MCSPI2 are not pinned out externally.  
For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in the device TRM.  
8.4.5.20 MMCSD  
There are two MMCSD modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module includes  
one MMCSD Host Controller.  
Each controller has the following data bus width:  
• MMCSD0 - 8-bit wide data bus  
• MMCSD1 - 4-bit wide data bus  
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The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure  
Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMCSD/SDIO  
protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion,  
and checking for syntactical correctness.  
For more information, see Multimedia Card/Secure Digital (MMCSD) Interface section in the device TRM.  
8.4.5.21 OSPI  
The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI) module  
which allows single, dual, quad or octal read and write access to external flash devices.  
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor  
wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up  
to silently perform some requested operation, signaling its completion via interrupts or status registers. For  
indirect operations, data is transferred between system memory and external flash memory via an internal  
SRAM which is loaded for writes and unloaded for reads by a device master at low latency system speeds.  
Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using  
user programmable configuration registers.  
For more information, see Octal Serial Peripheral Interface (OSPI) section in the device TRM.  
8.4.5.22 PCIE  
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe  
controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 5.0 Gbps  
per lane for serial links on backplanes and printed wiring boards.  
The device includes two instantiations of PCIe subsystem named PCIE0 and PCIE1.  
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in the device  
TRM.  
8.4.5.23 SerDes  
The goal of the SerDes is to convert device (SoC) parallel data into serialized data that can be output over a  
high-speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel  
data that can be processed by the device. To this end, the SerDes contains a variety of functional blocks to  
handle both the external analog interface as well as the internal digital logic.  
For more information, see Serializer/Deserializer (SerDes) section in the device TRM.  
8.4.5.24 RTI  
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)  
functionality for the device.  
The Real Time Interrupt module provides timer functionality for operating systems and for benchmarking code.  
The module incorporates several counters, which define the timebases needed for scheduling in the operating  
system.  
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren  
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for  
Automotive Electronics”) as well as OSEK/Time compliant operating systems.  
The timers also provide the ability to benchmark certain areas of code by reading the counter contents at the  
beginning and the end of the desired code range and calculating the difference between the values.  
For more information, see Real Time Interrupt (RTI) Module section in the device TRM.  
8.4.5.25 Timers  
There are sixteen timer modules in the device.  
All timers include specific functions to generate accurate tick interrupts to the operating system.  
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Each timer can be clocked from several different independent clocks. The selection of clock source is made from  
registers in the MCU_CTRL_MMR0/CTRL_MMR0.  
In the MCU domain the device provides 2 timer pins to be used as MCU Timer Capture inputs or as MCU Timer  
PWM outputs. In order to provide maximum flexibility, these 2 pins may be used with any of MCU_TIMER0  
through MCU_TIMER3 instances. System level muxes are used to control the capture source pin for each  
MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0] PWM output  
In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM  
outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11 instances.  
System level muxes are used to control the capture source pin for each TIMER[11-0] and the TIMER[11-0]  
source for each TIMER_IO[7-0] PWM output.  
For more information, see Timers section in the device TRM.  
8.4.5.26 UART  
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There  
are five UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function  
clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral  
devices or interprocessor communication between devices.  
The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a programmable  
t period) to encompass the various formats of infrared encoding for remote-control applications. The CIR logic  
transmits data packets based on a user-definable frame structure and packet content.  
For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in the  
device TRM.  
8.4.5.27 USB  
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange  
between a host device and a wide range of simultaneously accessible peripherals.  
The device supports two USB subsystems, both instantiated in the MAIN system domain:  
• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)  
PHY and HS/FS/LS (USB2.0) PHY  
• USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS/LS  
(USB2.0) PHY  
For more information, see Universal Serial Bus (USB) Subsystem section in the device TRM.  
8.5 Identification  
8.5.1 Revision Identification  
For more information about Revision Identification, see 节10.1, Device Nomenclature.  
8.5.2 Die Identification  
The device part number identification data can be read in the CTRLMMR_WKUP_JTAG_DEVICE_ID register.  
For more information about Die Identification, see Device Identification section in the device TRM.  
8.5.3 JTAG Identification  
The manufacturer identity, the boundary scan part number, and the silicon revision of the device can be read in  
the CTRLMMR_WKUP_JTAGID register.  
For more information about JTAG Identification, see Device Identification section in the device TRM.  
8.5.4 ROM Code Identification  
The ROM code uses several global memories in the MSRAM that are useful for debugging.  
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For more information about ROM Code Identification, see Global Memory Addresses Used by ROM Code  
section in the device TRM.  
8.6 Boot Modes  
This device supports primary boot from the UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™,  
USB, PCIe, and Ethernet interfaces. If the primary boot fails, the device also supports a secondary backup boot  
from the UART, I2C, OSPI (legacy SPI mode only), HyperBus, SD, USB, and Ethernet interfaces.  
The Boot Mode pins (BOOTMODE[18:00] and MCU_BOOTMODE[09:00]) provide the means to select the  
desired boot mode before the device is powered up. It is the user’s responsibility to properly set the  
(MCU_)BOOTMODE pins (via pullups or pulldowns) depending on the desired boot scenario.  
For more detailed information about the primary/secondary Boot Modes, including the Boot Mode pins, usage,  
and selections, see the Boot Mode Pins section in the device TRM.  
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9 Applications, Implementation, and Layout  
Note  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TI’s customers are responsible for determining  
suitability of components for their purposes. Customers should validate and test design  
implementation to confirm system functionality.  
9.1 Device Connection and Layout Fundamentals  
9.1.1 Power Supply Decoupling and Bulk Capacitors  
9.1.1.1 Power Distribution Network Implementation Guidance  
The Sitara™ Processor Power Distribution Networks: Implementation and Analysis provides guidance for  
successful implementation of the power distribution network. This includes PCB stackup guidance as well as  
guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that  
follow the board design guidelines contained in the application report.  
9.1.2 External Oscillator  
For more information, see 节7.9.4.1, Input Clocks / Oscillators.  
9.1.3 JTAG and EMU  
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various  
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target  
Connection Guide.  
For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual.  
9.1.4 Reset  
The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESETz) and four  
reset status pins (MCU_PORz_OUT, MCU_RESETSTATz, PORz_OUT, and RESETSTATz). Additional reset  
modes are available through internal registers and emulation.  
The device integrates an on-chip Power-on-Reset (POR) generator. Additionally, this device supports an external  
POR generation through a PORz and MCU_PORz input pin. The MCU_BYPASS_POR pin selects the POR  
source. When the MCU_BYPASS_POR pin is set high at power-up, on-chip POR generation will be completely  
bypassed and the external POR used. When it is low, the POR is generated internally. However, the four  
external reset inputs must all be pulled high to enable this internal POR generation.  
9.1.5 Unused Pins  
For more information about Unused Pins, see 节6.5, Connections for Unused Pins.  
9.1.6 Hardware Design Guide for AM65x/DRA80xM Devices  
The Hardware Design Guide for AM65x/DRA80xM Devices document describes hardware system design  
considerations for the AM65x/DRA80xM family of processors.This design guideis intended to be used as an aid  
during the development of application hardware.  
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9.2 Peripheral- and Interface-Specific Design Information  
9.2.1 DDR Board Design and Layout Guidelines  
The goal of the AM65x/DRA80xM DDR Board Design and Layout Guidelines is to make the DDR4 system  
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and  
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.  
TI only supports board designs using DDR4 memories that follow the guidelines in this document.  
9.2.2 OSPI Board Design and Layout Guidelines  
The following section details the routing guidelines that must be observed when routing the OSPI interfaces.  
9.2.2.1 No Loopback and Internal Pad Loopback  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS (~7cm  
as stripline or ~8cm as microstrip)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-1  
• Propagation delays and matching:  
– A to B < 450ps  
– Matching skew: < 60pS  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
OSPI_Board_01  
*0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed  
图9-1. OSPI Interface High Level Schematic  
9.2.2.2 External Board Loopback  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input  
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to half of the signal propagation delay from the MCU_OSPI[x]_LBCLKO pin to  
the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.  
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must  
be approximately equal to the signal propagation delay of the control and data signals between the flash  
device and the SoC device (E to F, or F to E)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-2  
• Propagation delays and matching:  
– A to B = E to F = (C to D) / 2  
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– Matching skew: < 60pS  
Note  
The OSPI Board Loopback Hold time requirement (described in 节 7.9.5.18, OSPI) is larger than the  
Hold time provided by a typical flash device. Therefore, the length of MCU_OSPI[x]_LBCLKO pin to  
the MCU_OSPI[x]_DQS pin (C to D) may need to be shortened to compensate.  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
C
R1  
0 Ω*  
MCU_OSPI[x]_LBCLKO  
D
MCU_OSPI[x]_DQS  
E
F
MCU_OSPI[x]_D[y],  
MCU_OSPI[x]_CSn[z]  
OSPI/QSPI/SPI  
device IOy, CS#  
OSPI_Board_02  
*0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is placeholder for fine  
tuning, if needed  
图9-2. OSPI Interface High Level Schematic  
9.2.2.3 DQS (Only Available in Octal Flash Devices)  
• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device  
• The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal  
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)  
should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS  
output pin (C to D)  
• 50 ΩPCB routing is recommended along with series terminations, as shown in 图9-3  
• Propagation delays and matching:  
– A to B = C to D  
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– Matching skew: < 60pS  
A
B
R1  
0 Ω*  
OSPI/QSPI/SPI  
device clock input  
MCU_OSPI[x]_CLK  
C
D
OSPI device DQS  
MCU_OSPI[x]_DQS  
OSPI_Board_03  
*0 Ωresistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed  
图9-3. OSPI Interface High Level Schematic  
9.2.3 USB Design Guidelines  
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as  
20 V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to  
be 30 V.  
The AM65xx device requires the VBUS signal voltage be scaled down using an external resistor divider (as  
shown in the 图 9-4), which limits the voltage applied to the actual device pin (USB0_VBUS, USB1_VBUS). The  
tolerance of these external resistors should be equal to or less than 1%, and the leakage current of zener diode  
at 5 V should be less than 100 nA.  
(1)  
Device  
USBn_VBUS  
76.8 kΩ  
1%  
16 kΩ  
1%  
VBUS signal  
23.2 kΩ  
1%  
6.8V  
(BZX84C6V8 or equivalent)  
VSS  
VSS  
SPRSP08_USB_VBUS_01  
图9-4. USB VBUS Detect Voltage Divider / Clamp Circuit  
The USB0_VBUS and USB1_VBUS pins may be considered to be fail-safe because the external circuit in 图9-4  
limits the input current to the actual device pin in a case where VBUS is applied while the device is powered off.  
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9.2.4 High Speed Differential Signal Routing Guidance  
The High-Speed Interface Layout Guidelines provides guidance for successful routing of the high speed  
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and  
spacing limits. TI supports only designs that follow the board design guidelines contained in the application  
report.  
9.2.5 System Power Supply Monitor Design Guidelines  
The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless  
implemented with the appropriate resistor voltage divider source. This pin should be sourced with a resistor  
voltage divider that receives its power from the system power supply.  
The output of the resistor voltage divider is connected to the VDDA_VSYS_MON pin which has a trigger voltage  
of 0.5 V ± 5%. The resistor voltage divider should be implemented such that it has a reference current in the  
range of 1 µA to 50 µA, output voltage that never exceeds the maximum value defined in 节 7.1, Absolute  
Maximums Ratings, and output voltage of 0.54 V when the system supply drops to its lowest desired operating  
voltage.  
The recommended output voltage of 0.54 V provides 40 mV of margin that includes 5% for tolerance of the  
voltage monitor, 1% for tolerance of each resistor, plus 5 mV of potential error introduced by input leakage  
current. This value ensures the voltage monitor will never trigger before reaching the expected trigger voltage.  
图 9-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger  
threshold is -10% or 4.5 V.  
Device  
VDDA_VSYS_MON  
220 kΩ  
1%  
VSYS  
(System Power Suplpy)  
30 kΩ  
1%  
VSS  
SPRSP08_VSYS_MON_01  
图9-5. System Supply Monitor Voltage Divider Circuit  
In this example the voltage divider ratio should be (4.5 V / 0.54 V) = 8.33 V. This ratio produces a 0.54 V  
potential on the VDDA_VSYS_MON pin when the system power supply is 4.5 V. In this case, the voltage monitor  
will trigger in the range of 3.88 V to 4.5 V. Precision 1% resistors with similar thermal coefficient are  
recommended for implementing the resistor voltage divider.  
9.2.6 MMC Design Guidelines  
The MMC peripheral on this device contains an integrated SDIO LDO for handling automatic voltage transitions  
for SD Interfaces. For details about how to connect the device pins associated with the SDIO LDO, refer to 图  
9-10 through 图9-12.  
9.2.7 Integrated Power Management Features  
The device offers integrated power management features that simplify design and cost/BOM of the system level  
power solution. Simplicity of the system design enables modular and scalable solutions suitable for platform  
design and re-use. The AM65x Power Management Features User Guide introduces the integrated power  
management features and advantages for system level power solution.  
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9.2.8 External Capacitors  
图9-6 shows an example of the external decoupling capacitor connections.  
Compute  
Cluster  
Device  
VDD_MPU1  
CORE  
A53  
MSMC  
VDD_MPU0  
VDD_CORE  
MCU  
Domain  
VDD_MCU  
VPP_MCU  
VDDA_ADC_MCU  
VDDA_MCU  
MCU PLL  
SRAM LDO  
CPSW PLL  
CAP_VDDAR_MCU  
Wakeup  
Domain  
VDDA_3P3_IOLDO_WKUP  
I/O Bias LDO  
VDDSHV0_WKUP(1)  
VDDSHV1_WKUP(1)  
VDDSHV2_WKUP(1)  
CAP_VDDA_1P8_IOLDO_WKUP  
VDDA_POR_WKUP  
VDDS0_WKUP(1)  
VDDS1_WKUP(1)  
VDDS2_WKUP(1)  
LF OSC  
HF OSC  
VDDA_WKUP  
SRAM LDO  
WKUP LDO  
CAP_VDDAR_WKUP  
CAP_VDD_WKUP  
VDDA_LDO_WKUP  
VDD_WKUP0(2)  
VDD_WKUP1(2)  
Main  
Domain  
PCIE0  
VDDA_1P8_OLDI0  
VDDA_1P8_CSI0  
VDDS_OSC1  
PCIE1  
USB0 (1.8V)  
USB1 (1.8V)  
USB0 (3.3V)  
USB1 (3.3V)  
VDDA_1P8_SERDES0  
VDDA_3P3_USB  
VDDA_DLL_MMC0  
VDDA_DLL_MMC1  
VDDA_PLL0_DDR  
VDDA_PLL1_DDR  
VDDA_PLL_CORE  
VDDA_PLL_PER0  
VDDA_PLL_DSS  
SRAM LDO  
CAP_VDDAR_CORE0  
VDDA_SRAM_CORE0  
VDDA_SRAM_CORE1  
SRAM LDO  
SRAM LDO  
SRAM LDO  
SRAM LDO  
SRAM LDO  
CAP_VDDAR_CORE1  
CAP_VDDAR_CORE2  
CAP_VDDAR_CORE3  
CAP_VDDAR_MPU0_0  
CAP_VDDAR_MPU0_1  
VDDA_PLL_MPU0  
VDDA_SRAM_MPU0  
SRAM LDO  
SRAM LDO  
SRAM LDO  
CAP_VDDAR_CORE4  
CAP_VDDAR_MPU1_0  
CAP_VDDAR_MPU1_1  
VDDA_PLL_MPU1  
VDDA_SRAM_MPU1  
VDDS_DDR  
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
I/O Bias LDO  
I/O Bias LDO  
CAP_VDDA_1P8_IOLDO0  
CAP_VDDA_1P8_IOLDO1  
VDDSHV0(1)  
VDDSHV1(1)  
VDDSHV2(1)  
VDDSHV3(1)  
VDDSHV4(1)  
VDDSHV5(1)  
VDDSHV6(1)(3)  
VDDSHV7(1)(3)  
VDDSHV8(1)  
VDDS0(1)  
VDDS1(1)  
VDDS2(1)  
VDDS3(1)  
VDDS4(1)  
VDDS5(1)  
VDDS6(1)(3)  
VDDS7(1)(3)  
VDDS8(1)  
VPP_CORE  
MMCSD  
VDDA_1P8_SDIO  
CAP_VDDA_1P8_SDIO  
CAP_VDDSHV_SDIO  
VDDA_3P3_SDIO  
SDIO LDO  
SPRSP08_DECOUPLING_CAPS_01  
图9-6. External Decoupling Capacitor Connections  
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9.2.8.1 LVCMOS External Capacitor Connections  
Each VDDSHV[8:0], and VDDSHV[2:0]_WKUP can be configured as 1.8 V or 3.3 V. 图 9-7 through 图 9-10  
illustrate different system configurations for the dual-voltage I/O supplies.  
VDDSHV[8:0], and VDDSHV[2:0]_WKUP are the dual-voltage LVCMOS I/O supplies, while VDDS[8:0] are the  
dual-voltage LVCMOS I/O bias supplies. If any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are configured for  
3.3 V operation, the corresponding VDDS[8:0] or VDDS[2:0]_WKUP should be sourced from the internal I/O Bias  
LDO. When any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are configured for 1.8 V operation, both  
VDDS[8:0] and VDDSHV[8:0] or VDDS[2:0]_WKUP and VDDSHV[2:0]_WKUP should be supplied from the  
same source.  
Two I/O Bias LDOs are integrated on this device to share load current. The recommended load sharing is as  
follows:  
• IOLDO0 : VDDS0, VDDS1, VDDS2, VDDS5, VDDS7, VDDS8  
• IOLDO1 : VDDS3, VDDS4, VDDS6  
图9-7 shows all VDDSHV[8:0], and VDDSHV[2:0]_WKUP supplies configured for 3.3V operation.  
Device  
Wakeup  
Domain  
VDDA_3P3_IOLDO_WKUP  
I/O Bias LDO  
VDDSHV0_WKUP  
VDDSHV1_WKUP  
VDDSHV2_WKUP  
CAP_VDDA_1P8_IOLDO_WKUP  
VDDA_POR_WKUP  
VDDS1_WKUP  
VDDS2_WKUP  
VDDS0_WKUP  
Main  
Domain  
CAP_VDDA_1P8_IOLDO1  
CAP_VDDA_1P8_IOLDO0  
I/O Bias LDO  
I/O Bias LDO  
VDDA_3P3_IOLDO1  
VDDA_3P3_IOLDO0  
VDDSHV0  
VDDSHV1  
VDDSHV2  
VDDSHV5  
VDDS0  
VDDS1  
VDDS2  
VDDS5  
VDDSHV8  
VDDS8  
VDDS3  
VDDS4  
VDDSHV3  
VDDSHV4  
VDDSHV6  
VDDS6  
VDDSHV7  
VDDS7  
SPRSP08_DECOUPLING_CAPS_01  
图9-7. All VDDSHV[8:0], and VDDSHV[2:0]_WKUP Supplies Configured for 3.3 V Operation  
图9-8 shows all VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for 1.8 V operation.  
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Device  
Wakeup  
Domain  
VDDA_3P3_IOLDO_WKUP  
I/O Bias LDO  
CAP_VDDA_1P8_IOLDO_WKUP  
VDDA_POR_WKUP  
VDDS0_WKUP(2)  
VDDSHV0_WKUP  
VDDSHV1_WKUP  
VDDS1_WKUP(2)  
VDDSHV2_WKUP  
(2)  
VDDS2_WKUP  
Main  
Domain  
VDDA_3P3_IOLDO0  
VDDA_3P3_IOLDO1  
I/O Bias LDO  
I/O Bias LDO  
CAP_VDDA_1P8_IOLDO0  
CAP_VDDA_1P8_IOLDO1  
VDDSHV0  
VDDSHV1  
VDDSHV2  
VDDSHV3  
VDDSHV4  
VDDSHV5  
VDDSHV6  
VDDSHV7  
VDDSHV8  
VDDS0(2)  
VDDS1(2)  
VDDS2(2)  
VDDS3(2)  
VDDS4(2)  
VDDS5(2)  
VDDS6(2)  
VDDS7(2)  
VDDS8(2)  
SPRSP08_DECOUPLING_CAPS_03  
图9-8. All VDDSHV[8:0] and VDDSHV[2:0]_WKUP Supplies Configured for 1.8V Operation  
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图 9-9 shows a split configuration where VDDSHV[0, 1, 2, 5, 8] and VDDSHV0_WKUP are configured for 3.3 V  
operation, while VDDSHV[3, 4, 6, 7] and VDDSHV[2:1]_WKUP are configured for 1.8 V operation. Note the  
colors indicate rails that are tied to the same source.  
Device  
Wakeup  
Domain  
VDDA_3P3_IOLDO_WKUP  
I/O Bias LDO  
VDDSHV0_WKUP  
VDDSHV1_WKUP  
CAP_VDDA_1P8_IOLDO_WKUP  
VDDA_POR_WKUP  
VDDS0_WKUP  
VDDS1_WKUP(2)  
VDDS2_WKUP(2)  
VDDSHV2_WKUP  
Main  
Domain  
I/O Bias LDO  
I/O Bias LDO  
VDDA_3P3_IOLDO1  
VDDA_3P3_IOLDO0  
CAP_VDDA_1P8_IOLDO1  
CAP_VDDA_1P8_IOLDO0  
VDDSHV0  
VDDSHV1  
VDDSHV2  
VDDSHV5  
VDDS0  
VDDS1  
VDDS2  
VDDS5  
VDDS8  
VDDSHV8  
VDDSHV3  
VDDS3(2)  
VDDS4(2)  
VDDSHV4  
VDDSHV6  
VDDSHV7  
VDDS6(2)  
VDDS7(2)  
SPRSP08_DECOUPLING_CAPS_04  
图9-9. VDDSHV[8:0] and VDDSHV[2:0]_WKUP Supplies Configured for Combination of 1.8 V or 3.3 V  
Operation  
图 9-10 through 图 9-12 illustrates the system configuration when VDDSHV6 or VDDSHV7 is used as the  
MMCSD supply.  
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Device  
MMCSD  
VDDA_1P8_SDIO  
CAP_VDDA_1P8_SDIO  
CAP_VDDSHV_SDIO  
VDDA_3P3_SDIO  
SDIO LDO  
VSS  
VDDSHVn (1)  
VSS  
VDDSn(1)  
1.8V  
SPRSP08_DECOUPLING_CAPS_06  
图9-10. VDDSHV6 or VDDSHV7 Used as the MMCSD Supply for Fixed 1.8V IO  
Device  
MMCSD  
VDDA_1P8_SDIO  
3.3V  
CAP_VDDA_1P8_SDIO  
VDDA_3P3_SDIO  
VDDSHVn (1)  
SDIO LDO  
CAP_VDDSHV_SDIO  
VDDSn(1)  
SPRSP08_DECOUPLING_CAPS_07  
图9-11. VDDSHV6 or VDDSHV7 Used as the MMCSD Supply for Fixed 3.3V IO  
Device  
MMCSD  
VDDA_1P8_SDIO  
3.3V  
CAP_VDDA_1P8_SDIO  
VDDA_3P3_SDIO  
SDIO LDO  
CAP_VDDSHV_SDIO  
VDDSHVn (1)  
VDDSn(1)  
SPRSP08_DECOUPLING_CAPS_05  
图9-12. VDDSHV6 or VDDSHV7 Used as the MMCSD Supply for Dynamic 3.3V/1.8V IO  
9.2.9 Thermal Solution Guidance  
The Thermal Design Guide for DSP and Arm Application Processors Application Note provides guidance for  
successful implementation of a thermal solution for system designs containing this device. This document  
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provides background information on common terms and methods related to thermal solutions. TI only supports  
designs that follow system design guidelines contained in the application report.  
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10 Device and Documentation Support  
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,  
generate code, and develop solutions are listed below.  
10.1 Device Nomenclature  
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all  
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for  
example, AM654x). Texas Instruments recommends two of three possible prefix designators for its support tools:  
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering  
prototypes (TMDX) through fully qualified production devices and tools (TMDS).  
Device development evolutionary flow:  
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and  
may not use production assembly flow.  
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical  
specifications.  
null Production version of the silicon die that is fully qualified.  
Support tool development evolutionary flow:  
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.  
TMDS Fully-qualified development-support product.  
X and P devices and TMDX development-support tools are shipped against the following disclaimer:  
"Developmental product is intended for internal evaluation purposes."  
Production devices and TMDS development-support tools have been characterized fully, and the quality and  
reliability of the device have been demonstrated fully. TI's standard warranty applies.  
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production  
devices. Texas Instruments recommends that these devices not be used in any production system because their  
expected end-use failure rate still is undefined. Only qualified production devices are to be used.  
For orderable part numbers of AM65xx devices in the ACD package type, see the Package Option Addendum of  
this document, the TI website (ti.com), or contact your TI sales representative.  
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10.1.1 Standard Package Symbolization  
SITARA™  
aBBBBBBrPPPzYyTtFSs  
PIN ONE INDICATOR  
XXXXXXX  
G1  
ZZZ  
YYY  
O
SPRSP08_PACK_01  
图10-1. Printed Device Reference  
10.1.2 Device Naming Convention  
表10-1. Nomenclature Description  
FIELD PARAMETER  
FIELD DESCRIPTION  
VALUE  
DESCRIPTION  
a
Device evolution stage  
X
P
Prototype  
Preproduction (production test flow, no reliability data)  
BLANK Production  
BBBBBB  
Base production part  
number  
AM6548  
AM6528  
AM6546  
AM6526  
Quad Core High Tier (See 表5-1, Device Comparison)  
Dual Core High Tier (See 表5-1, Device Comparison)  
Quad Core Low Tier (See 表5-1, Device Comparison)  
Dual Core Low Tier (See 表5-1, Device Comparison)  
r
Device revision  
BLANK SR 1.0  
A
B
SR 2.0  
SR 2.1  
PPP  
z
Package Designator  
Device Speed  
ACD  
X
ACD FCBGA-N784 (23mm × 23mm) Package  
High speed grade (see 表7-1, Speed Grade Maximum Frequency)  
OTHER Alternate speed grade  
All industrial protocols enabled (basic protocols plus EtherCAT slave and  
POWERLINK slave)  
Yy  
Device type  
E
BLANK Basic Industrial protocols enabled  
Tt  
F
Temperature (1)  
A
Extended (see 节7.4, Recommended Operating Conditions)  
BLANK  
BLANK No safety features  
Commercial (see 节7.4, Recommended Operating Conditions)  
Functional Safety  
F
Safety features enabled including lock-step MCU  
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表10-1. Nomenclature Description (continued)  
FIELD PARAMETER  
FIELD DESCRIPTION  
VALUE  
DESCRIPTION  
High-Security device, Secure Boot Supported  
Dummy key High-Security device, Secure Boot Supported  
Ss  
Security Identifier  
S1  
SB  
BLANK General purpose device  
XXXXXXX  
YYY  
ZZZ  
Lot Trace Code (LTC)  
Production Code; For TI use only  
Production Code; For TI use only  
Pin one designator  
O
G1  
ECAT—Green package designator  
(1) Applies to device max junction temperature.  
Note  
X6580ACD is a prototype part that is functionally equivalent to XAM6548ACDXEAF.  
Note  
BLANK in the symbol or part number is collapsed so there are no gaps between characters.  
10.2 Tools and Software  
The following products support development for AM65xx platforms:  
Design kits and evaluation modules  
AM65x evaluation module The AM65x Evaluation Module provides a platform to quickly start evaluation of Sitara  
™ Arm® Cortex®-A53 AM65x Processors (AM6548, AM6546, AM6528, AM6526) and accelerate development  
for HMI, networking, patient monitoring, and other industrial applications. It is a development platform based on  
the quad core Cortex-A53, dual Cortex-R5F processor that is integrated with ample connectivity such as PCIe,  
USB 3.0/2.0, Gigabit Ethernet, and more.  
Development tools  
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors The Clock Tree Tool (CTT)  
for Sitara™ Arm®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software  
that provides information about the clocks and modules in these TI devices. It allows the user to:  
• Visualize the device clock tree  
• Interact with clock tree elements and view the effect on PRCM registers  
• Interact with the PRCM registers and view the effect on the device clock tree  
• View a trace of all the device registers affected by the user interaction with clock tree  
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for Sitara Arm Processors Code  
Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and  
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug  
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,  
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through  
each step of the application development flow. Familiar tools and interfaces allow users to get started faster than  
ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced  
embedded debug capabilities from TI resulting in a compelling feature-rich development environment for  
embedded developers.  
Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring pin  
multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as  
C header/code files that can be imported into software development kits (SDKs) or used to configure customer's  
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custom software. Version 4 of the Pin Mux utility adds the capability of automatically selecting a mux  
configuration that satisfies the entered requirements.  
Models  
AM654x/DRA80xM BSDL Model BSDL Model  
AM654x/DRA80xM IBIS File IBIS Model  
AM654x/DRA80xM Thermal Models Thermal Model  
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments  
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized  
distributor.  
10.3 Documentation Support  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
The following documents describe the AM65xx devices.  
Technical Reference Manual  
AM65x/DRA80xM ProcessorsTechnical Reference Manual Details the integration, the environment, the  
functional description, and the programming models for each peripheral and subsystem in the AM65xx family of  
devices.  
Errata  
AM65x/DRA80xM Processors Silicon Revision 2.1/2.0/1.0 Silicon Errata Describes the known exceptions to the  
functional specifications for the device.  
10.4 支持资源  
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅  
TI 的《使用条款》。  
10.5 Trademarks  
SafeTI™, Sitara™, and Code Composer Studio™ are trademarks of TI.  
I2C™ is a trademark of NXP Semiconductors.  
HyperBus™ is a trademark of Mobiveil Inc.  
多媒体卡™, MMC™, and eMMC™ are trademarks of MultiMediaCard Association.  
Neon™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.  
I2C BUS™ is a trademark of NXP Semiconductor.  
TI E2E™ is a trademark of Texas Instruments.  
Arm®, Cortex®, TrustZone®, CoreSight® are registered trademarks of Arm Limited (or its subsidiaries) in the US  
and/or elsewhere.  
MIPI® is a registered trademark of MIPI Alliance, Inc.  
PowerVR® is a registered trademark of Imagination Technologies Limited.  
PCI-Express® and PCIe® are registered trademarks of PCI-SIG.  
安全数字® and SD® are registered trademarks of SD Card Association.  
EtherCAT® are registered trademarks of Beckhoff Automation GmbH.  
所有商标均为其各自所有者的财产。  
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10.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
10.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
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11 Mechanical, Packaging, and Orderable Information  
11.1 Packaging Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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重要声明和免责声明  
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没  
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。  
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可  
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知  
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。  
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI  
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明  
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2021，德州仪器(TI) 公司  
PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Oct-2022  
PACKAGING INFORMATION  
Orderable Device  
AM6526BACDXA  
AM6526BACDXEAF  
AM6528BACDXEA  
AM6546BACDXA  
AM6548BACDXEAF  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
-40 to 105  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
ACTIVE  
FCCSP  
FCCSP  
FCCSP  
FCCSP  
FCCSP  
ACD  
784  
784  
784  
784  
784  
60  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
Call TI  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
Level-3-250C-168 HR  
AM6526BACDXA  
Samples  
Samples  
Samples  
Samples  
Samples  
900  
900 ACD  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACD  
ACD  
ACD  
ACD  
60  
60  
60  
60  
Call TI  
Call TI  
Call TI  
Call TI  
AM6526BACDXEAF  
900  
900 ACD  
AM6528BACDXEA  
900  
900 ACD  
AM6546BACDXA  
900  
900 ACD  
AM6548BACDXEAF  
900  
900 ACD  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Oct-2022  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
28-Oct-2022  
TRAY  
L - Outer tray length without tabs  
KO -  
Outer  
tray  
height  
W -  
Outer  
tray  
width  
Text  
P1 - Tray unit pocket pitch  
CW - Measurement for tray edge (Y direction) to corner pocket center  
CL - Measurement for tray edge (X direction) to corner pocket center  
Chamfer on Tray corner indicates Pin 1 orientation of packed units.  
*All dimensions are nominal  
Device  
Package Package Pins SPQ Unit array  
Max  
matrix temperature  
(°C)  
L (mm)  
W
K0  
P1  
CL  
CW  
Name  
Type  
(mm) (µm) (mm) (mm) (mm)  
AM6526BACDXA  
AM6526BACDXEAF  
AM6528BACDXEA  
AM6546BACDXA  
AM6548BACDXEAF  
ACD  
ACD  
ACD  
ACD  
ACD  
FCCSP  
FCCSP  
FCCSP  
FCCSP  
FCCSP  
784  
784  
784  
784  
784  
60  
60  
60  
60  
60  
5 x 12  
5 x 12  
5 x 12  
5 x 12  
5 x 12  
150  
150  
150  
150  
150  
322.6 135.9 7620 25.5 17.25 16.95  
322.6 135.9 7620 25.5 17.25 16.95  
322.6 135.9 7620 25.5 17.25 16.95  
322.6 135.9 7620 25.5 17.25 16.95  
322.6 135.9 7620 25.5 17.25 16.95  
Pack Materials-Page 1  
PACKAGE OUTLINE  
ACD0784A  
FCBGA - 1.63 mm max height  
SCALE 0.600  
BALL GRID ARRAY  
23.1  
22.9  
A
B
BALL A1  
CORNER  
23.1  
22.9  
(
17)  
4X (R1)  
(0.4)  
C
(0.635)  
1.63 MAX  
SEATING PLANE  
0.2 C  
BALL TYP  
0.42  
0.32  
21.6  
TYP  
SYMM  
(0.7) TYP  
(0.7) TYP  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
Y
W
V
U
T
R
P
N
M
L
SYMM  
21.6  
TYP  
K
J
0.57  
784X  
H
G
0.47  
F
E
D
C
0.8  
TYP  
0.2  
C A B  
C
0.08  
B
A
1
2
6
3 4 5 7  
8 10 11  
9
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28  
0.8 TYP  
4223579/B 01/2019  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
ACD0784A  
FCBGA - 1.63 mm max height  
BALL GRID ARRAY  
(0.8) TYP  
784X ( 0.4)  
(0.8) TYP  
17 18 19 20 21 22 23 24 25 26 27 28  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
1
A
B
C
D
E
F
G
H
J
K
L
M
N
SYMM  
P
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
SYMM  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE: 4X  
METAL UNDER  
SOLDER MASK  
0.05 MIN  
0.05 MAX  
(
0.4)  
METAL  
(
0.4)  
EXPOSED  
METAL  
SOLDER MASK  
OPENING  
EXPOSED  
METAL  
SOLDER MASK  
OPENING  
NON-SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
NOT TO SCALE  
4223579/B 01/2019  
NOTES: (continued)  
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
See Texas Instruments Literature No. SPRU811 (www.ti.com/lit/spru811).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
ACD0784A  
FCBGA - 1.63 mm max height  
BALL GRID ARRAY  
(0.8) TYP  
784X ( 0.4)  
17 18 19 20 21 22 23 24 25 26 27 28  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16  
1
A
B
C
D
E
(0.8) TYP  
F
G
H
J
K
L
M
N
SYMM  
P
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.15 mm THICK STENCIL  
SCALE: 4X  
4223579/B 01/2019  
NOTES: (continued)  
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
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Copyright © 2022，德州仪器 (TI) 公司  

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