AMC1035-Q1 [TI]

具有 ±1V 双极性输入和 2.5V 基准输出的汽车精密 Δ-Σ 调制器;


型号：	AMC1035-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有 ±1V 双极性输入和 2.5V 基准输出的汽车精密 Δ-Σ 调制器
文件：	总33页 (文件大小：1776K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

具有 ±1V 双极输入和 2.5V 基准电压输出的 AMC1035-Q1 Δ-Σ 调制器

1 特性

3 说明

•

符合面向汽车应用的 AEC-Q100 标准：

温度等级 1：-40°C 至 +125°C，T_A

针对电压和温度检测进行了优化的 Δ-Σ 调制器：

AMC1035-Q1是一款精密 Δ-Σ 调制器，可在 3.0V 至

5.5V 单电源下运行，并具有外部供电的 9MHz 至

21MHz 时钟信号。在曼彻斯特模式下，额定时钟范围

为 9MHz 至 11MHz。该器件的差分 ±1V 输入结构针

对电压和温度检测渲染进行了优化。

–

•

–

输入电压范围：±1V

高差分输入电阻：1.6GΩ（典型值）

集成 2.5V、±5mA 基准，可实现比例测量

AMC1035-Q1 可选择曼彻斯特编码式输出位流，这样

便无需考虑接收器件的设置和保留时间要求，并可减少

总体电路布局工作。当用于与数字滤波器（例如集成到

TMS320F28004x、TMS320F2807x 或

•

出色的直流性能：

–

失调电压误差：±0.5mV（最大值）

温漂：±6µV/°C（最大值）

增益误差：±0.25%（最大值）

增益漂移：±45ppm/°C（最大值）

比例增益漂移：±15ppm/°C（最大值）

TMS320F2837x 微控制器系列中）一起抽取输出位流

时，该器件可在 82 kSPS 的数据速率下实现具有

87dB 动态范围的 16 位分辨率。

•

可选曼彻斯特编码式或未编码式位流输出

AMC1035-Q1 的内部基准资源支持比例电路架构，可

最大限度降低电源电压变化和温漂对测量精度的负面影

响。

2 应用

•

用于以下器件的电压和温度检测：

–

牵引逆变器

AMC1035-Q1 还可用于与数字隔离器和隔离式电源一

起进行共模交流电压检测。

车载充电器

直流/直流转换器

集成电源模块

器件信息⁽¹⁾

器件型号

封装

SOIC (8)

封装尺寸（标称值）

AMC1035-Q1

4.90mm × 3.90mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

应用示例

3.3 V or 5 V

AMC1035-Q1

VDD

2.5 V, 3.3 V or 5 V

REFOUT

AINP

Voltage

Reference

ISO7721-Q1

VDD1 VDD2

OUTA

INA

CLKIN

DOUT

ûꢀ-Modulator

Manchester

Coding

INB

OUTB

GND2

AINN

GND

MCE

GND1

GND2

GND1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS941

AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

www.ti.com.cn

7.4 Device Functional Modes........................................ 18

Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical Applications ................................................ 20

Power Supply Recommendations...................... 24

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings Automotive .......................................... 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 7

6.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 14

7.1 Overview ................................................................. 14

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 25

11 器件和文档支持 ..................................................... 26

11.1 文档支持 ............................................................... 26

11.2 接收文档更新通知 ................................................. 26

11.3 社区资源................................................................ 26

11.4 商标....................................................................... 26

11.5 静电放电警告......................................................... 26

11.6 Glossary................................................................ 26

12 机械、封装和可订购信息....................................... 26

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (May 2019) to Revision A

Page

•

已更改将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1

AMC1035-Q1

www.ti.com.cn

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

MCE

AINP

VDD

CLKIN

DOUT

GND

AINN

REFOUT

Not to scale

Pin Functions

I/O

NO.

NAME

DESCRIPTION

Manchester coding enabled, active high, with internal pulldown resistor (typical value: 200 kΩ).

The polarity of this signal must not be changed when the clock signal is applied.

MCE

AINP

AINN

Noninverting analog input.

Inverting analog input.

REFOUT

GND

—

Reference output: 2.5 V nominal, maximum ±5-mA sink and source capability.

Ground reference.

Modulator bitstream data output, updated with the rising edge of the clock signal present on CLKIN.

DOUT

This pin is a Manchester coded output if MCE is pulled high. Use the rising edge of the clock to latch the

modulator bitstream at the input of the digital filter device.

Modulator clock input: 9 MHz to 21 MHz with an internal pulldown resistor (typical value: 200 kΩ).

CLKIN

VDD

The clock signal must be applied continuously for proper device operation; see the Clock Input section for

additional details.

Power supply, 3.0 V to 5.5 V.

See the Power Supply Recommendations section for decoupling recommendations.

—

AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

see⁽¹⁾

PARAMETER

MIN

–0.3

MAX

UNIT

Supply voltage

VDD to GND

VDD + 0.5

Analog input voltage

Analog output voltage

Digital input voltage

Digital output voltage

Input current

At AINP or AINN

At REFOUT

GND – 5

GND – 0.5

–10

At CLKIN or MCE

At DOUT

Any pin except supply pins

Maximum virtual junction, T_J

Storage, T_stg

150

Temperature

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings Automotive

VALUE

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD Classification Level 2

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per AEC

Q100-011

CDM ESD Classification Level C6

Corner pins (1, 4, 5, and 8)

Other pins

±1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

3.3

MAX

UNIT

POWER SUPPLY

VDD

Supply voltage

VDD to GND

3.0

5.5

ANALOG INPUT

V_Clipping

V_FSR

Differential input voltage before clipping output

V_IN= V_AINP– V_AINN

±1.25

Specified linear differential full-scale voltage

Absolute common-mode input voltage⁽¹⁾

V_IN= V_AINP– V_AINN

–1

–2

(V_AINP+ V_AINN) / 2 to GND

VDD

(V_AINP+ V_AINN) / 2 to GND,

3.0 V ≤ VDD < 4 V,

V_AINP= V_AINN

VDD –

1.4

–1.4

–0.8

–1.4

–0.8

(V_AINP+ V_AINN) / 2 to GND,

3.0 V ≤ VDD < 4.5 V,

|V_AINP– V_AINN| = 1.25 V

VDD –

2.4

V_CM

Operating common-mode input voltage⁽²⁾

(V_AINP+ V_AINN) / 2 to GND,

4 V ≤ VDD ≤ 5.5 V,

V_AINP= V_AINN

2.7

2.1

(V_AINP+ V_AINN) / 2 to GND,

4.5 V ≤ VDD ≤ 5.5 V,

|V_AINP– V_AINN| = 1.25 V

DIGITAL INPUT

Input voltage

TEMPERATURE RANGE

T_AOperating ambient temperature

V_MCEor V_CLKINto GND

GND

–40

VDD

125

°C

(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage V_CMfor normal

operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) See the Analog Input section for more details.

AMC1035-Q1

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ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

6.4 Thermal Information

AMC1035-Q1

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

120

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

°C/W

R_ΘJC(top)Junction-to-case (top) thermal resistance

R_ΘJB

Y_JT

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Y_JB

R_ΘJC(bot)Junction-to-case (bottom) thermal resistance

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

minimum and maximum specifications are at T_A= –40°C to 125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN = 0 V,

and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C, CLKIN = 20 MHz, and VDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Negative common-mode

undervoltage detection

level

(V_AINP+ V_AINN) / 2 to GND, V_AINP= V_AINN

–1.45

–0.85

V_CMuv

(V_AINP+ V_AINN) / 2 to GND, |V_AINP– V_AINN| = 1.25 V

(V_AINP+ V_AINN) / 2 to GND, V_AINP= V_AINN

3.0 V ≤ VDD < 4.5 V

VDD – 1.35

VDD – 2.35

(V_AINP+ V_AINN) / 2 to GND, |V_AINP– V_AINN| = 1.25 V,

3.0 V ≤ VDD < 4.5 V

Positive common-mode

overvoltage detection level

V_CMov

(V_AINP+ V_AINN) / 2 to GND, V_AINP= V_AINN

4.5 V ≤ VDD ≤ 5.5 V

2.75

2.15

(V_AINP+ V_AINN) / 2 to GND, |V_AINP– V_AINN| = 1.25 V,

4.5 V ≤ VDD ≤ 5.5 V

Single-ended input

resistance

R_IN

AINN = GND

0.1

0.4

1.6

GΩ

R_IND

C_IN

Differential input resistance

0.16

Single-ended input

capacitance

Differential input

capacitance

C_IND

I_IB

Input bias current

AINP = AINN = GND; I_IB= (I_IBP+ I_IBN) / 2

I_IO= I_IBP- I_IBN

–10

–5

±3

±5

pA/°C

TCI_IB

I_IO

Input bias current drift

Input offset current

±1

f_IN= 0 Hz, V_CMmin≤ V_IN≤ V_CMmax

f_INfrom 0.1 Hz to 50 kHz, V_CMmin≤ V_IN≤ V_CMmax

–104

–88

Common-mode rejection

ratio

CMRR

DC ACCURACY

Resolution

Decimation filter output set to 16 bits

Resolution: 16 bits

–12

Bit

LSB

INL

Integral nonlinearity

Offset error

±2

±0.03

±0.1

±0.02

±20

0.5

E_O

Initial, at 25°C, AINP = AINN = GND

–0.5

–6

TCE_O

Offset error thermal drift

µV/°C

Initial, at 25°C

–0.25

–0.3

–45

0.25

0.3

E_G

Gain error

Initial, at 25°C, ratiometric mode

TCE_G

Gain error thermal drift

ppm/°C

ratiometric mode

–15

±4

AINP = AINN = GND, VDD from 3.0 V to 5.5 V, at DC

–90

Power-supply rejection

ratio

PSRR

AINP = AINN = GND, VDD from 3.0 V to 5.5 V,

10 kHz / 100 mV ripple

–84

AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

minimum and maximum specifications are at T_A= –40°C to 125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN = 0 V,

and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A= 25°C, CLKIN = 20 MHz, and VDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

SINAD

THD

Signal-to-noise + distortion f_IN= 1 kHz

Total harmonic distortion

f_IN= 1 kHz

–87

–78

Spurious-free dynamic

range

SFDR

REFERENCE OUTPUT

V_REF

Reference output voltage

Initial, at 25°C, no load

2.495

–50

–5

2.5

2.505

Reference output voltage

drift

TCV_REF

I_REF

±20

ppm/°C

Reference output current

Load regulation

C_LOAD< 1 nF

Load to GND or VDD, 0mA to 5mA

REFOUT to GND

0.15

0.35

mV/mA

I_SC

Short-circuit current

REFOUT to VDD

–21

Power-supply rejection

ratio

PSRR

–200

±30

200

μV/V

DIGITAL INPUT/OUTPUT

I_IN

Input current

GND ≤ V_IN≤ VDD

μA

C_IN

V_IH

Input capacitance

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 x VDD

–0.3

VDD + 0.3

0.3 x VDD

V_IL

C_LOAD

f_CLKIN= 21 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

VDD – 0.1

VDD – 0.4

V_OH

High-level output voltage

0.1

0.4

V_OL

POWER SUPPLY

Low-level output voltage

I_OL= 4 mA

3.0 V ≤ VDD ≤ 3.6 V, I_REFOUT= 0 mA, MCE = 0,

C_LOAD= 15 pF

5.2

4.6

6.4

5.4

6.8

6.1

8.3

7.2

3.0 V ≤ VDD ≤ 3.6 V, I_REFOUT= 0 mA, MCE = 1,

C_LOAD= 15 pF

I_VDD

Supply current

4.5 V ≤ VDD ≤ 5.5 V, I_REFOUT= 0 mA, MCE = 0,

C_LOAD= 15 pF

4.5 V ≤ VDD ≤ 5.5 V, I_REFOUT= 0 mA, MCE = 1,

C_LOAD= 15 pF

AMC1035-Q1

www.ti.com.cn

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

6.6 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MCE = 0

MCE = 1

f_CLK

CLKIN clock frequency

MHz

Duty_CycleCLKIN duty cycle

40%

50%

60%

t_H1

t_H2

t_H3

t_D1

t_D2

t_D3

DOUT hold time after rising edge of CLKIN

MCE = 0, C_LOAD= 15 pF

DOUT hold time after rising edge of CLKIN

DOUT hold time after falling edge of CLKIN

Rising edge of CLKIN to DOUT valid delay

Falling edge of CLKIN to DOUT valid delay

MCE = 1, C_LOAD= 15 pF

MCE = 0, C_LOAD= 15 pF

MCE = 1, C_LOAD= 15 pF

10% to 90%, 3.0 V ≼ VDD ≼ 3.6 V, C_LOAD= 15 pF

10% to 90%, 4.5 V ≼ VDD ≼ 5.5 V, C_LOAD= 15 pF

10% to 90%, 3.0 V ≼ VDD ≼ 3.6 V, C_LOAD= 15 pF

10% to 90%, 4.5 V ≼ VDD ≼ 5.5 V,C_LOAD= 15 pF

VDD step to 3.0 V; 0.1%-settling, clock applied

2.5

1.5

t_r

DOUT rise time

3.5

5.8

4.4

2.5

t_f

DOUT fall time

1.8

t_ASTART

Analog startup time

0.25

t_CLKIN

CLKIN

t_HIGH

t_H1

t_LOW

t_D1

t_r/ t_f

DOUT

(MCE = 0)

t_D2

t_D3

t_H2

t_H3

t_r/ t_f

DOUT

(MCE = 1)

图 1. Digital Interface Timing

VDD

t_ASTART

CLKIN

DOUT

...

Bitstream not valid (analog settling)

Valid bitstream

图 2. Device Startup Timing

AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

www.ti.com.cn

6.7 Typical Characteristics

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

-20

7.5

-40

2.5

-60

-2.5

-5

-80

-100

-7.5

-10

-120

-0.65 -0.3

0.05

0.4

0.75

V_CM(V)

1.1

1.45

1.8

2.15

0.01

0.1

100

1000

f_IN(kHz)

D001

D002

VDD = 5.5 V

图 3. Input Bias Current vs

图 4. Common-Mode Rejection Ratio vs

Common-Mode Input Voltage

Input Signal Frequency

MCE = 0, f_CLKIN= 20 MHz

MCE = 1, f_CLKIN= 10 MHz

-3

-6

-9

-12

-1

-0.75 -0.5 -0.25

V_IN(mV)

0.25

0.5

0.75

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D031

D003

图 5. Integral Nonlinearity vs Input Voltage

图 6. Integral Nonlinearity vs Temperature

0.5

0.4

0.3

0.2

0.1

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Device 1

Device 2

Device 3

3.5

4.5

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

VDD (V)

D004

D005

图 7. Offset Error vs Supply Voltage

图 8. Offset Error vs Temperature

AMC1035-Q1

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ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

Typical Characteristics (接下页)

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

0.5

0.4

0.3

0.2

0.1

0.3

0.2

0.1

MCE = 0

MCE = 1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

10 11 12 13 14 15 16 17 18 19 20 21

f_CLKIN(MHz)

3.5

4.5

5.5

VDD (V)

D006

D007

图 9. Offset Error vs Clock Frequency

图 10. Gain Error vs Supply Voltage

0.25

0.2

0.3

0.2

0.1

Device 1

Device 2

Device 3

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

-0.25

-0.1

-0.2

-0.3

Device 1

Device 2

Device 3

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D008

D009

图 11. Gain Error vs Temperature

图 12. Ratiometric Gain Error vs Temperature

0.3

0.2

0.1

-20

MCE = 0

MCE = 1

-40

-60

-0.1

-0.2

-0.3

-80

-100

-120

f_CLKIN(MHz)

0.1

Ripple Frequency (kHz)

100

1000

D010

D011

图 13. Gain Error vs Clock Frequency

图 14. Power-Supply Rejection Ratio vs

Ripple Frequency

AMC1035-Q1

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Typical Characteristics (接下页)

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

SNR

SINAD

SNR

SINAD

3.5

4.5

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

VDD (V)

D012

D013

图 15. Signal-to-Noise Ratio and

图 16. Signal-to-Noise Ratio and

Signal-to-Noise + Distortion vs Supply Voltage

Signal-to-Noise + Distortion vs Temperature

SNR, MCE = 0

SNR, MCE = 1

SINAD, MCE = 0

SINAD, MCE = 1

SNR

SINAD

f_CLKIN(MHz)

0.1

100

f_IN(kHz)

D014

D015

图 17. Signal-to-Noise Ratio and

Signal-to-Noise + Distortion vs Clock Frequency

图 18. Signal-to-Noise Ratio and

Signal-to-Noise + Distortion vs Input Signal Frequency

100

-76

SNR

SINAD

-80

-84

-88

-92

-96

-100

-104

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

V_IN(Vpp)

3.5

4.5

5.5

VDD (V)

D016

D017

图 19. Signal-to-Noise Ratio and

Signal-to-Noise + Distortion vs Input Signal Voltage

图 20. Total Harmonic Distortion vs Supply Voltage

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Typical Characteristics (接下页)

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

-76

MCE = 0

MCE = 1

-80

-84

-88

-92

-96

-100

-104

-100

-104

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D018

D019

图 21. Total Harmonic Distortion vs Temperature

图 22. Total Harmonic Distortion vs Clock Frequency

-76

-80

-76

-80

-84

-88

-92

-96

-100

-104

-100

-104

0.1

f_IN(kHz)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

V_IN(Vpp)

D020

D021

图 23. Total Harmonic Distortion vs

图 24. Total Harmonic Distortion vs

Input Signal Frequency

Input Signal Voltage

109

105

101

109

105

101

3.5

4.5

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

VDD (V)

D022

D023

图 25. Spurious-Free Dynamic Range vs

图 26. Spurious-Free Dynamic Range vs

Supply Voltage

Temperature

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Typical Characteristics (接下页)

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

109

105

101

109

105

101

MCE = 0

MCE = 1

f_CLKIN(MHz)

0.1

f_IN(kHz)

D024

D025

图 27. Spurious-Free Dynamic Range vs

图 28. Spurious-Free Dynamic Range vs

Clock Frequency

Input Signal Frequency

109

105

101

-20

-40

-60

-80

-100

-120

-140

-160

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

V_IN(Vpp)

Frequency (kHz)

D026

D027

4096-point FFT, V_IN= 2 V_PP

图 30. Frequency Spectrum With 1-kHz Input Signal

图 29. Spurious-Free Dynamic Range vs

Input Signal Voltage

-20

2.505

2.503

2.501

2.499

2.497

2.495

-40

-60

-80

-100

-120

-140

-160

Frequency (kHz)

3.5

4.5

5.5

VDD (V)

D028

D029

4096-point FFT, V_IN= 2 V_PP

图 31. Frequency Spectrum With 5-kHz Input Signal

图 32. Reference Output Voltage vs Supply Voltage

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Typical Characteristics (接下页)

at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, f_CLKIN= 20 MHz, MCE = 0, and sinc³filter with OSR = 256 (unless

otherwise noted)

2.52

2.515

2.51

Device 1

Device 2

Device 3

MCE = 0

MCE = 1

2.505

2.5

2.495

2.49

2.485

2.48

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.5

4.5

5.5

VDD (V)

D030

D032

图 33. Reference Output Voltage vs Temperature

图 34. Supply Current vs Supply Voltage

MCE = 0

MCE = 1

MCE = 0

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D033

D034

图 35. Supply Current vs Temperature

图 36. Supply Current vs Clock Frequency

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7 Detailed Description

7.1 Overview

The differential analog input (comprised of input signals AINP and AINN) of the AMC1035-Q1 is a chopper-

stabilized buffer, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage

that digitizes the input signal into a 1-bit output stream. The data output DOUT of the converter provides a

stream of digital ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin

with a frequency in the range of 9 MHz to 21 MHz. The time average of this serial bitstream output is proportional

to the analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1035-Q1. The 1.6-GΩ

differential input resistance of the analog input stage supports low gain-error signal sensing in high-voltage

applications using resistive dividers. The external clock input simplifies the synchronization of multiple

measurement channels on the system level. The extended frequency range of up to 21 MHz supports higher

performance levels compared to the other solutions available on the market.

7.2 Functional Block Diagram

VDD

MCE

Manchester

Coding

DOUT

CLKIN

AINP

AINN

ûꢀ-Modulator

Voltage

Reference

REFOUT

GND

7.3 Feature Description

7.3.1 Analog Input

The AMC1035-Q1 incorporates front-end circuitry that contains a buffered sampling stage, followed by a ΔΣ

modulator. To support a bipolar input range, the device uses a charge pump that allows single-supply operation

to simplify the overall system design and minimize the circuit cost. For reduced offset and offset drift, the input

buffer is chopper-stabilized with the switching frequency set at f_CLKIN/ 32. 图 37 shows the spur created by the

switching frequency.

-20

-40

-60

-80

-100

-120

-140

-160

0.1

10 100

Frequency (kHz)

1000

10000

D036

sinc³filter, OSR = 2, f_CLKIN= 20 MHz, f_IN= 1 kHz

图 37. Quantization Noise Shaping

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Feature Description (接下页)

The linearity and noise performance of the device are ensured only when the differential analog input voltage

remains within the specified linear full-scale range (FSR), that is ±1 V, and within the specified input common-

mode range.

图 38 shows the specified common-mode input voltage that applies for the full-scale input voltage range as

specified in this document along with the corresponding common-mode undervoltage and overvoltage threshold

levels.

If smaller input signals are used, the operational common-mode input voltage range widens. 图 39 shows the

common-mode input voltage that applies with no differential input signal; that is, when the voltage applied on

AINP is equal to the voltage applied on AINN. The common-mode input voltage range scales with the actual

differential input voltage between this range and the range in 图 38.

V_CMov

V_CMuv

V_CMov

V_CMuv

Specified V_CM

Range

Specified V_CM

Range

-1

-2

3.25

3.5

3.75

4.25

4.5

5.5

3.25

3.5

3.75

4.25

4.5

5.5

VDD (V)

图 38. Common-Mode Input Voltage Range With a

Full-Scale Differential Input Signal of ±1.25 V

图 39. Common-Mode Input Voltage Range With a

Zero Differential Input Signal

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Feature Description (接下页)

7.3.2 Modulator

The modulator implemented in the AMC1035-Q1 (such as the one conceptualized in 图 40) is a second-order,

switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage V_INand the output V₅of the 1-bit

digital-to-analog converter (DAC) are subtracted, providing an analog voltage V₁at the input of the first integrator

stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage

V₃that is summed with the input signal V_INand the output of the first integrator V₂. Depending on the polarity of

the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the

next clock pulse by changing the associated analog output voltage V₅, causing the integrators to progress in the

opposite direction and forcing the value of the integrator output to track the average value of the input.

f_CLKIN

V₁

V₂

V₃

V₄

V_IN

Integrator 1

Integrator 2

ꢀ

CMP

0 V

V₅

DAC

图 40. Block Diagram of a Second-Order Modulator

As depicted in 图 37, the modulator shifts the quantization noise to high frequencies. Therefore, use a low-pass

digital filter at the output of the device to increase the overall performance. This filter is also used to convert from

the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's

microcontroller families TMS320F28004x, TMS320F2807x, and TMS320F2837x offer a suitable programmable,

hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1035-Q1.

Alternatively, a field-programmable gate array (FPGA) can be used to implement the filter.

7.3.3 Reference Output

The AMC1035-Q1 offers a voltage reference output that can source or sink current to significantly reduce the

gain error thermal drift in ratiometric applications as specified in the Electrical Characteristics table. The IGBT

Temperature Sensing section provides an example of a ratiometric use case for the AMC1035-Q1.

The reference output can drive capacitive loads less than 1 nF. Use a series resistor to avoid oscillations and

degradation of performance for capacitive loads ≥ 1 nF. 表 1 lists the recommended series resistor values for

given capacitor value examples. Interpolate for capacitive loads with a value between the given examples.

表 1. Series Resistor Value for Capacitive Loads ≥ 1 nF on the REFOUT Pin

CAPACITIVE LOAD ON THE REFOUT PIN

RECOMMENDED SERIES RESISTOR

1 nF

3.3 nF

10 nF

33 nF

100 nF

330 nF

1 μF

33 Ω

56 Ω

47 Ω

33 Ω

15 Ω

10 Ω

5.6 Ω

3.3 Ω

1.8 Ω

3.3 μF

10 μF

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7.3.4 Clock Input

The AMC1035-Q1 system clock is provided externally at the CLKIN pin. The clock signal must be applied

continuously for proper device operation.

To support the bipolar input voltage range with a single supply, the AMC1035-Q1 includes a charge pump. This

charge pump stops operating if the clock signal is below the specified frequency range or if the signal is paused

or missing. Additionally, the input bias current increases beyond the specified range and significantly reduces the

input resistance of the device. When the clock signal is paused or missing, the modulator stops the analog signal

conversion and the digital output signal remains frozen in the last logic state. When the clock signal is applied

again after a pause, the internal analog circuitry biasing must settle for proper device performance. In this case,

consider the t_ASTARTspecification in the Switching Characteristics table.

7.3.5 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of

resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V

produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit

resolution. These input voltages are also the specified linear range of the AMC1035-Q1 with performance as

specified in this document. If the input voltage value exceeds this range, the output of the modulator shows

nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only

zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal

to 1.25 V. In this case, however, the AMC1035-Q1 generates a single 1 (if the input is at negative full-scale) or 0

every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). 图

41 shows the input voltage versus the output modulator signal.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

图 41. Analog Input versus the AMC1035-Q1 Modulator Output

公式 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception of a

full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):

V_IN+ V_Clipping

2ì V_Clipping

(1)

The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN

pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.

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7.3.6 Manchester Coding Feature

The AMC1035-Q1 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one

transition per bit to support clock signal recovery from the bitstream. The Manchester coding combines the clock

and data information using exclusive-OR (XOR) logical operation that results in a bitstream free of DC

components. 图 42 shows the resulting bitstream from this coding. The duty cycle of the Manchester encoded

bitstream depends on the duty cycle of the input clock CLKIN. To enable Manchester coding on the AMC1035-

Q1, pull the input pin MCE high. The DOUT signal is inverted if the MCE status changes when CLKIN is high.

Clock

Uncoded

Bitstream

Machester

Coded

Bitstream

图 42. Manchester Coded Output of the AMC1035-Q1

7.4 Device Functional Modes

The AMC1035-Q1 is operational when the power supply VDD and clock signal CLKIN are applied, as specified in

the Recommended Operating Conditions and Switching Characteristics tables.

7.4.1 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1035-Q1 (that is, |V_IN| ≥ |V_Clipping|), the device generates a single

one or zero every 128 bits at DOUT, as shown in 图 43, depending on the actual polarity of the signal being

sensed. This feature is also supported with a Manchester coded output and allows full-scale and invalid input

signals to be identified as described in the Fail-Safe Output section and can be used for advanced system-level

diagnostics.

127 CLKIN cycles

CLKIN

...

DOUT

(MCE = 0)

(V_AINPt V_AINN) ≤ t1.25 V

...

DOUT

(MCE = 1)

...

DOUT

(MCE = 0)

(V_AINPt V_AINN) ≥ 1.25 V

...

DOUT

(MCE = 1)

图 43. Overrange Output of the AMC1035-Q1

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Device Functional Modes (接下页)

7.4.2 Fail-Safe Output

图 44 shows that if the common-mode voltage of the input reaches or exceeds the specified common-mode

undervoltage, V_CMuv, or overvoltage detection level, V_CMovas defined in the Electrical Characteristics table, the

DOUT of the AMC1035-Q1 is held at steady-state high.

V_CMuv< V_CM< V_CMov

V_CMovG ë_CMor V_CMG ë_CMuv

V_CM

CLKIN

DOUT

(MCE = 0)

DOUT

(MCE = 1)

图 44. Fail-Safe Output of the AMC1035-Q1

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Digital Filter Usage

The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). 公式 2 shows a sinc³-type filter, which is a

very simple filter, built with minimal effort and hardware:

-OSR

≈

’

1- z

H z =

( )

∆

1- z^-1

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an oversampling

ratio (OSR) of 256 and an output word width of 16 bits.

An example code for implementing a sinc³filter in an FPGA is discussed in the Combining the ADS1202 with an

FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for

download at www.ti.com.

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8.2 Typical Applications

8.2.1 Voltage Sensing

ΔΣ modulators are widely used in high-efficiency systems because of their high AC and DC performance. In

automotive applications, the AMC1035-Q1 can be used in traction inverters, on-board chargers, DC/DC

converters, and as parts of integrated power modules.

图 45 shows a simplified schematic of a traction inverter application with the AMC1035-Q1 used for the DC-link

and output phase voltage sensing. In this example, all resistive dividers reference to the negative DC-link voltage

that is also used as a ground reference point for the microcontroller. An additional fifth AMC1035-Q1 can be

used for temperature sensing of the insulated-gate bipolar transistor (IGBT) module; see the IGBT Temperature

Sensing section for more details.

Current feedback is performed with shunt resistors (R_SHUNT) and TI's AMC1305M25-Q1 isolated modulators.

Depending on the system design, either all three or only two motor phase currents are sensed.

Depending on the overall digital processing power requirements, and with a total of eight ΔΣ modulator

bitstreams to be processed by the MCU, a derivate from either the low-cost single-core TMS320F2807x or the

dual-core TMS320F2837x families can be used in this application.

+V_BUS

Motor

I_DC

R_SHUNT

V_BUS

R_DC1

R_DC2

R_SHUNT

I_AC

R_SHUNT

R_AC1

5 V_ISO

3.3 V

AMC1305M25-Q1

AVDD

AINP

DVDD

DOUT

R_FLT

C_FLT

R_FLT

R_AC2

AINN

CLKIN

R_DC3

AGND DGND

R_AC3

3.3 V

AMC1035-Q1

-V_BUS

MCE

VDD

R_FLT

C_FLT

R_FLT

5 V_ISO

TMS320F28x7x

AINP

DOUT

5 V_ISO

3.3 V

SDFM1

SD1_D1

AMC1305M25-Q1

AINN

CLKIN

REFOUT GND

AVDD

AINP

DVDD

DOUT

R_FLT

C_FLT

R_FLT

SD1_D2

SD1_D3

SD1_D4

SD1_C1

SD1_C2

SD1_C3

SD1_C4

3.3 V

AMC1305M25-Q1

AINN

CLKIN

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

AGND DGND

AINP

3.3 V

AMC1035-Q1

AINN

CLKIN

AGND DGND

MCE

VDD

R_FLT

C_FLT

R_FLT

AINP

DOUT

SDFM2

SD2_D1

3.3 V

AMC1035-Q1

AINN

CLKIN

SD2_D2

SD2_D3

SD2_D4

SD2_C1

SD2_C2

SD2_C3

SD2_C4

MCE

VDD

R_FLT

C_FLT

R_FLT

REFOUT GND

AINP

DOUT

AINN

CLKIN

REFOUT GND

3.3 V

AMC1035-Q1

MCE

AINP

VDD

R_FLT

C_FLT

R_FLT

DOUT

AINN

CLKIN

PWMx

REFOUT GND

LMK00804B-Q1

VDD

VDDO

3.3 V

VDD

VDDO

3.3 V

CLK_SEL

GND

CLK_SEL

GND

LVCMOS_CLK

图 45. The AMC1035-Q1 in a Traction Inverter Application

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Typical Applications (接下页)

8.2.1.1 Design Requirements

表 2 lists the parameters for this typical application.

表 2. Design Requirements

PARAMETER

VALUE

3.3 V

Supply voltage

Voltage drop across the sensing resistor R_DC1for a linear response

Voltage drop across the sensing resistors R_ACxfor a linear response

Current through the sensing resistors R_ACx

1 V (maximum)

±1 V (maximum)

±100 µV (maximum)

8.2.1.2 Detailed Design Procedure

Use Ohm's Law to calculate the minimum total resistance of the resistive dividers to limit the cross current to the

desired values:

•

For the voltage sensing on the DC bus: R_DC1+ R_DC2+ R_DC3= V_BUS/ I_DC

For the voltage sensing on the output phases U, V, and W: R_AC1+ R_AC2+ R_AC3= V_{PHASE (max)}/ I_AC

Consider the following two restrictions to choose the proper value of the resistors R_DC3and R_AC3

•

The voltage drop caused by the nominal voltage range of the system must not exceed the recommended

input voltage range of the AMC1035-Q1: V_xC3≤ V_FSR

•

The voltage drop caused by the maximum allowed system overvoltage must not exceed the input voltage that

causes a clipping output: V_xC3≤ V_Clipping

Use similar approach for calculation of the shunt resistor values R_SHUNTand see the AMC1305M25-Q1 data

sheet for further details.

表 3 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V on

the DC bus.

表 3. Resistor Value Examples for DC Bus Sensing

PARAMETER

600-V DC BUS

3.01 MΩ

10 kΩ

800-V DC BUS

4.22 MΩ

10.5 kΩ

Resistive divider resistor R_DC1

Resistive divider resistor R_DC2

Sense resistor R_DC3

Resulting current through resistive divider I_DC

Resulting voltage drop on sense resistor V_RDC3

99.5 µA

94.7 µA

0.995 V

0.994 V

表 4 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 400 V and 690 V on

the output phases.

表 4. Resistor Value Examples for Output Phase Voltage Sensing

PARAMETER

±400-V_ACPHASE

2.0 MΩ

±690-V_ACPHASE

3.48 MΩ

Resistive divider resistor R_AC1

Resistive divider resistor R_AC2

2.0 MΩ

3.48 MΩ

Sense resistor R_AC3

10.0 kΩ

Resulting current through resistive divider I_AC

Resulting voltage drop on sense resistor V_RAC3

99.8 µA

99.0 µA

±0.998 V

±0.990 V

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Use a power supply with a nominal voltage of 3.3 V to directly connect all modulators to the microcontroller.

For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers

(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These MCU families support up to eight

channels of dedicated hardwired filter structures called sigma-delta filter modules (SDFMs) that significantly

simplify system level design by offering two filtering paths per channel: one providing high accuracy results for

the control loop and one that offers a fast response path for overcurrent detection. Use one of the pulse-width

modulation (PWM) sources inside the MCU to generate the clock for the modulators and for easy

synchronization of all feedback signals and the switching control of the gate drivers.

图 45 uses a clock buffer to distribute the clock reference signal generated on one of the PWM outputs of the

MCU (called PWMx in 图 45) to all modulators used in the circuit and as a reference for the digital filters in the

MCU. In this example, TI's LMK00804B-Q1 is used for this purpose. Each LMK00804B-Q1 output can drive two

modulator or two SDFM clock inputs.

8.2.1.3 Application Curve

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. 图

46 shows the ENOB of the AMC1035-Q1 with different oversampling ratios on a sinc3 filter. This number is

calculated from the SINAD by using following equation: SINAD = 1.76 dB + 6.02 × ENOB.

100

OSR

1000

D035

sinc3 filter

图 46. Measured Effective Number of Bits vs Oversampling Ratio

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8.2.2 IGBT Temperature Sensing

The high input impedance of the AMC1035-Q1 is optimized for usage in voltage-sensing applications.

Additionally, the internal voltage reference supports temperature sensing using a positive temperature coefficient

(PTC) or a negative temperature coefficient (NTC) sensor often integrated in the IGBT module.

The same reference is internally used by the modulator, resulting in a ratiometric system solution that minimizes

the overall temperature drift of the sensing path. 图 47 shows a simplified schematic of the AMC1035-Q1 used

for temperature sensing of the IGBT module. See the Application Example on the front page of this document for

an application solution that requires isolating the temperature sensor.

3.3 V

VDD

REFOUT

MCE

TMS320F28x7x

AMC1035-Q1

IGBT Module

Digital

Filter

AINP

AINN

DOUT

CLKIN

SD-Dx

SD-Cx

GND

PWMx

图 47. Using the AMC1035-Q1 for Temperature Sensing

8.2.3 What to Do and What Not to Do

Do not leave the analog inputs of the AMC1035-Q1 unconnected (floating) when the device is powered up. If

either modulator input is left floating, the input bias current can drive this input beyond the specified common-

mode input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes. In both

cases, the modulator outputs a fail-safe bitstream as described in the Fail-Safe Output section.

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9 Power Supply Recommendations

To decouple the power supply, place a 0.1-µF capacitor as close to the VDD pin of the AMC1035-Q1 as

possible, as shown in 图 48, followed by an additional capacitor in the range of 1 µF to 10 µF.

Phase X

R₁

AMC1035-Q1

VDD

GND

3.0 V to 3.6 V

0.1 ꢀF

2.2 ꢀF

MCE

optional

anti-aliasing filter

R₂

R₃

TMS320F2837x

DOUT

CLKIN

AINP

AINN

SD-Dx

ûꢁ Modulator

SD-Cx

PWMx

图 48. Decoupling the AMC1035-Q1

Safety considerations or high common-mode voltage levels can require the AMC1035-Q1 to be galvanically

isolated from other parts of the system. 图 49 shows an example of a circuit that uses the ISO7721-Q1 to isolate

the signal path and the SN6501-Q1 and a transformer are used to generate the required isolated power.

AMC1035-Q1

ISO7721-Q1

AINP

AINN

DOUT

CLKIN

DATA

CLK

ûꢀ Modulator

VDD2

VDD1

VDD

GND

VDD1

GND1

VDD2

GND2

2.2 …F 0.1 …F

0.1 …F

MCE

GND2

GND1

TPS7B6933-Q1

OUT IN

SN6501-Q1

D1 VCC

10 …F

0.1 …F 10 …F

20 V

GND

0.1 …F

D2 GND

GND1

10 …F

20 V

GND1

GND2

图 49. Galvanic Isolation of the AMC1035-Q1

AMC1035-Q1

www.ti.com.cn

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

10 Layout

10.1 Layout Guidelines

图 50 shows two layout recommendations for designs based on 1206-SMD or 0603-SMD size decoupling

capacitors placed as close as possible to the AMC1035-Q1. For best performance, place the AMC1035-Q1 as

close as possible to the source of the analog signal to be converted and keep the layout of the AINP and AINN

traces symmetrical.

10.2 Layout Example

0.1

µF

2.2

µF

AMC1035-Q1

0603

MCE

VDD

MCE

VDD

AINP

CLKIN

DOUT

GND

AINP

CLKIN

DOUT

GND

digital

filter

digital

filter

0.1 µF

1206

2.2 µF

1206

Sensor

AINN

REFOUT

LEGEND

Copper Pour and Traces

Via to Ground Plane

Via to Supply Plane

图 50. Recommended Layout of the AMC1035-Q1

AMC1035-Q1

ZHCSJR9A –MAY 2019–REVISED NOVEMBER 2019

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《TMS320F28004x Piccolo™ 微控制器》产品说明书

德州仪器 (TI)，《TMS320F2807x Piccolo™ 微控制器》产品说明书

德州仪器 (TI)，《TMS320F2837xD 双核 Delfino™ 微控制器》产品说明书

德州仪器 (TI)，EMC 性能优异的 ISO772x-Q1 高速、增强型双通道数字隔离器数据表

德州仪器 (TI)，《将 ADS1202 与 FPGA 数字滤波器结合，以便在电机控制应用中进行电流测量》应用报告

德州仪器 (TI)，AMC1305x-Q1 高精度、增强型隔离式 Δ-Σ 调制器数据表

德州仪器 (TI)，LMK00804B-Q1 1.5V 至 3.3V、1 路至 4 路高性能 LVCMOS 扇出缓冲器和电平转换器数据表

德州仪器 (TI)，TPS7B69xx-Q1 高电压超低 I_Q低压降稳压器数据表

德州仪器 (TI)，《SN6501-Q1 用于隔离式电源的变压器驱动器》数据表

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1035QDRQ1

ACTIVE

SOIC

2500 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

A1035Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1035QDRQ1

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jul-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

340.5 336.1 25.0

AMC1035QDRQ1

2500

Pack Materials-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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AMC1035-Q1 [TI]

相关型号：

AMC1035D

AMC1035DR

AMC1035QDRQ1

AMC105SN0-1

AMC10DCKD

AMC10DCKD-S288

AMC10DCKH

AMC10DCKH-S288

AMC10DCKI

AMC10DCKI-S288

AMC10DCKN

AMC10DCKN-S288