AMC1204-Q1_15 [TI]
20 MHz, Second-Order, Isolated Delta-Sigma Modulator for Current-Shunt Measurement;
| 型号： | AMC1204-Q1_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20 MHz, Second-Order, Isolated Delta-Sigma Modulator for Current-Shunt Measurement |
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AMC1204-Q1
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SLAS886B –JULY 2012–REVISED JANUARY 2013
20 MHz, Second-Order, Isolated Delta-Sigma Modulator
for Current-Shunt Measurement
Check for Samples: AMC1204-Q1
1
FEATURES
DESCRIPTION
The AMC1204-Q1 is a 1-bit digital output, isolated
•
•
Qualified for Automotive Applications
delta-sigma (ΔΣ) modulators that can be clocked at
up to 20 MHz. The digital isolation of the modulator
output is provided by a silicon dioxide (SiO2) barrier
that is highly resistant to magnetic interference. This
barrier has been certified to provide basic galvanic
isolation of up to 4250 VPEAK according to UL1577,
IEC60747-5-2, and CSA standards or specifications.
AEC-Q100 Qualified With the Following
Results
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C3B
The AMC1204-Q1 provides a single-chip solution for
measuring the small signal of a shunt resistor across
an isolated barrier. These types of resistors are
typically used to sense currents in motor control
inverters, green energy generation systems, and
other industrial applications. The AMC1204-Q1
differential inputs easily connect to the shunt resistor
or other low-level signal sources. An internal
reference eliminates the need for external
components. When used with an appropriate external
digital filter, an effective number of bits (ENOB) of 14
is achieved at a data rate of 78 kSPS.
•
•
±250-mV Input Voltage Range Optimized for
Shunt Resistors
Certified Digital Isolation:
–
–
–
–
CSA, IEC60747-5-2, and UL1577 Approved
Isolation Voltage: 4250 VPEAK
Working Voltage: 1200 VPEAK
Transient Immunity: 15 kV/µs
•
•
•
Long Isolation Barrier Lifetime (see
Application Report SLLA197)
A
5-V analog supply (AVDD) is used by the
High Electromagnetic Field Immunity
(see Application Note SLLA181A)
modulator while the isolated digital interface operates
from a 3-V, 3.3-V, or 5-V supply (DVDD). The
AMC1204-Q1 is available in SO-16 (DW) packages
and are specified from –40°C to 125°C.
Outstanding AC Performance:
–
–
SNR: 84 dB (min)
THD: –80 dB (max)
AVDD
DVDD
•
Excellent DC Precision:
–
–
INL: ±8 LSB (max)
VINP
VINN
DS
DATA
Gain Error: ±2.5% (max)
Modulator
•
•
External Clock Input for Easier
Synchronization
2.5V
Ref
CLKIN
Fully Specified Over the Extended Automotive
Temperature Range
APPLICATION
AGND
DGND
•
Shunt Resistor Based Current Sensing in:
–
–
–
–
Motor Control
Green Energy
Inverter Applications
Uninterruptible Power Supplies
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
AMC1204-Q1
SLAS886B –JULY 2012–REVISED JANUARY 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE
MODULATOR
CLOCK (MHz)
GAIN ERROR
(%)
PART NUMBER(2)
DIGITAL SUPPLY CLOCK SOURCE
3 V, 3.3 V, or 5 V External
INL (LSB)
THD (dB)
AMC1204QDWRQ1
20
±8
±2.5
–80
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
Over the operating ambient temperature range, unless otherwise noted.
AMC1204-Q1
PARAMETER
Supply voltage, AVDD to AGND or DVDD to DGND
Analog input voltage at VINP, VINN
MIN
–0.3
MAX
UNIT
V
6
AVDD + 0.5
DVDD + 0.3
10
AGND – 0.5
DGND – 0.3
–10
V
Digital input voltage at CLKIN
V
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
Operating ambient temperature range, TOA
mA
°C
°C
150
–40
125
Human body model (HBM) AEC-Q100 Classification
Level H2
–2000
2000
750
V
V
Electrostatic discharge
(ESD),
all pins
Charged device model (CDM) AEC-Q100 Classification
Level C3B
–750
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
AMC1204-Q1
THERMAL METRIC(1)
UNIT
DW (16 PINS)
78.5
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
41.3
50.2
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.5
ψJB
41.2
θJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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REGULATORY INFORMATION
VDE/IEC
CSA
UL
Approved under CSA component
acceptance notice
Recognized under 1577 component
recognition program
Certified according to IEC 60747-5-2
File number: 40016131
File number: 2350550
File number: E181974
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of
a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and
is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then
the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
θJA = 78.5°C/W, VI = 5.5 V,
TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
10
mA
TC Maximum case temperature
150
°C
IEC 61000-4-5 RATINGS
PARAMETER
TEST CONDITIONS
VALUE
±6000
UNIT
VIOSM
Surge immunity
1.2/50 μs voltage surge and 8/20 μs current surge
V
IEC 60664-1 RATINGS
PARAMETER
TEST CONDITIONS
Material group
SPECIFICATION
Basic isolation group
II
Rated mains voltage ≤ 150 VRMS
Rated mains voltage < 300 VRMS
Rated mains voltage < 400 VRMS
Rated mains voltage < 600 VRMS
I-IV
I-IV
I-III
I-III
Installation classification
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ISOLATION CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Maximum working insulation voltage per
VIORM
IEC
1200
VPEAK
t = 1s (100% production test),
VPD(t)
VIOTM
Partial discharge test voltage per IEC
Transient overvoltage
2250
VPEAK
partial discharge < 5 pC
t = 60 s (qualification test)
t = 1 s (100% production test)
VIO = 500 V at TS
4250
5100
> 109
2
VPEAK
VPEAK
Ω
RS
Isolation resistance
Pollution degree
PD
Degrees
ISOLATOR CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shortest terminal to terminal distance
through air
L(I01) Minimum air gap (clearance)
7.9
mm
Shortest terminal to terminal distance
across the package surface
L(I02) Minimum external tracking (creepage)
7.9
> 400
0.014
mm
V
Tracking resistance
CTI
DIN IEC 60112/VDE 0303 part 1
Distance through the insulation
(comparative tracking index)
Minimum internal gap
(internal clearance)
mm
Input to output, VIO = 500 V, all pins on
each side of the barrier tied together to
create a two-terminal device, TA < 85°C
> 1012
> 1011
Ω
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V,
100°C ≤ TA < TA max
CIO
CI
Barrier capacitance input to output
Input capacitance to ground
VI = 0.8 VPP at 1 MHz
VI = 0.8 VPP at 1 MHz
1.2
3
pF
pF
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific
application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting
pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal
according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves and/or ribs on
the PCB are used to help increase these specifications.
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ELECTRICAL CHARACTERISTICS
All minimum/maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
AVDD = 5 V, and DVDD = 3.3 V.
AMC1204-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA
RESOLUTION
Resolution
DC ACCURACY
Specified ambient temperature range
–40
125
°C
16
Bits
TA = –40°C to 85°C
–8
-16
–1
±2
±5
8
16
1
LSB
LSB
LSB
mV
INL
Integral linearity error(1)
TA = –40°C to 125°C
DNL
Differential nonlinearity(2)
Offset error(3)
VOS
–1
±0.1
±1
1
TCVOS
GERR
Offset error thermal drift
Gain error(3)
–3.5
–2.5
3.5
2.5
μV/°C
%
±0.5
±30
79
TCGERR
PSRR
Gain error thermal drift
Power-supply rejection ratio
ppm/°C
dB
ANALOG INPUTS
FSR
Full-scale differential voltage input range
VINP – VINN
VINP or VINN
±320
mV
mV
mV
pF
Specified FSR
–250
–160
250
VCM
CI
Operating common-mode signal(2)
Input capacitance to AGND
Differential input capacitance
Differential input resistance
AVDD
7
3.5
CID
RID
pF
12.5
kΩ
VINP – VINN = ±250 mV
VINP – VINN = ±320 mV
–10
–50
15
10
50
μA
IIL
Input leakage current
μA
CMTI
CMRR
Common-mode transient immunity
Common-mode rejection ratio
kV/μs
dB
VIN from 0 V to 5 V at 0 Hz
108
114
VIN from 0 V to 5 V at 100 kHz
dB
EXTERNAL CLOCK
tCLKIN Clock period
fCLKIN
45.5
5
50
20
50
50
200
22
ns
MHz
%
Input clock frequency
Duty cycle
5 MHz ≤ fCLKIN < 20 MHz
20 MHz ≤ fCLKIN ≤ 22 MHz
40
45
60
DutyCLKIN
55
%
AC ACCURACY
fIN = 1 kHz, TA = –40°C to 105°C
fIN = 1 kHz, TA = –40°C to 125°C
fIN = 1 kHz, TA = –40°C to 105°C
fIN = 1 kHz, TA = –40°C to 125°C
fIN = 1 kHz, TA = –40°C to 105°C
fIN = 1 kHz, TA = –40°C to 125°C
fIN = 1 kHz, TA = –40°C to 105°C
fIN = 1 kHz, TA = –40°C to 125°C
70
69
83
82
87
87
dB
dB
dB
dB
dB
dB
dB
dB
SINAD
SNR
Signal-to-noise + distortion
88
Signal-to-noise ratio
88
–96
–96
96
–70
–69
THD
Total harmonic distortion
72
71
SFDR
Spurious-free dynamic range
96
DIGITAL INPUTS(2)
IIN
Input current
Input capacitance
VIN = DVDD to DGND
–10
10
μA
CIN
5
pF
CMOS logic family
CMOS with Schmitt-trigger
VIH
VIL
High-level input voltage
Low-level input voltage
DVDD = 4.5 V to 5.5 V
DVDD = 4.5 V to 5.5 V
0.7 DVDD
–0.3
DVDD + 0.3
0.3 DVDD
V
V
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified 500 mV input range.
(2) Ensured by design.
(3) Maximum values, including temperature drift, are ensured over the full specified temperature range.
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ELECTRICAL CHARACTERISTICS (continued)
All minimum/maximum specifications at TA = –40°C to 125°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250
mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C,
AVDD = 5 V, and DVDD = 3.3 V.
AMC1204-Q1
PARAMETER
TEST CONDITIONS
MIN
TYP
LVCMOS
MAX
UNIT
LVCMOS logic family
VIH
VIL
High-level input voltage
Low-level input voltage
DVDD = 2.7 V to 3.6 V
DVDD = 2.7 V to 3.6 V
2
DVDD + 0.3
0.8
V
V
–0.3
DIGITAL OUTPUTS(2)
COUT
Output capacitance
Load capacitance
5
V
V
CLOAD
30
CMOS logic family
CMOS
VOH
VOL
High-level output voltage
Low-level output voltage
DVDD = 4.5 V, IOH = –100 µA
DVDD = 4.5 V, IOL = 100 µA
4.4
V
V
0.5
LVCMOS logic family
LVCMOS
IOH = 20 µA
DVDD – 0.1
DVDD – 0.4
V
V
IOH = –4 mA,
2.7 V ≤ DVDD ≤ 3.6 V
VOH
High-level output voltage
IOH = –4 mA,
4.5 V ≤ DVDD ≤ 5.5 V
DVDD – 0.8
V
IOL = 20 µA
IOL = 4 mA
0.1
0.4
V
V
VOL
Low-level output voltage
POWER SUPPLY
AVDD
DVDD
IAVDD
High-side supply voltage
4.5
2.7
5
5.5
5.5
16
V
Controller-side supply voltage
High-side supply current
3.3
11
V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ DVDD ≤ 3.6 V
4.5 V ≤ DVDD ≤ 5.5 V
AVDD = 5.5 V, DVDD = 3.6 V
mA
mA
mA
mW
2
4
IDVDD
PD
Controller-side supply current
Power dissipation
2.8
61.6
5
102.4
6
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PIN CONFIGURATION
DW PACKAGE
SO-16
(TOP VIEW)
AVDD
VINP
DGND
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VINN
AGND
DVDD
CLKIN
NC
NC(1)
NC
DATA
NC
NC
AGND
DGND
(1) NC = no internal connection.
PIN DESCRIPTIONS
PIN NAME
AVDD
VINP
PIN NO.
FUNCTION DESCRIPTION
1
Power High-side power supply
2
Analog input Noninverting analog input
Analog input Inverting analog input
VINN
3
AGND
DGND
DATA
CLKIN
DVDD
NC
4, 8(1)
Power
Power
High-side ground
9, 16
Controller-side ground
11
Digital output Modulator data output
Digital input Modulator clock input
13
14
Power
—
Controller-side power supply
No internal connection; can be tied to any potential or left unconnected
5, 6, 7, 10, 12, 15
(1) Both pins are connected internally via a low-impedance path; thus, only one of the pins must be tied to the ground plane.
TIMING INFORMATION
tCLK
tHIGH
CLKIN
tLOW
tD
DATA
Figure 1. Modulator Output Timing
TIMING CHARACTERISTICS FOR Figure 1
Over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted.
PARAMETER
MIN
45.5
20
TYP
50
MAX
200
120
120
15
UNIT
ns
tCLK
tHIGH
tLOW
tD
CLKIN clock period
CLKIN clock high time
25
ns
CLKIN clock low time
20
25
ns
Delayed falling edge of CLKIN to DATA valid
2
ns
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TYPICAL CHARACTERISTICS
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
INTEGRAL NONLINEARITY
vs INPUT SIGNAL AMPLITUDE
INTEGRAL NONLINEARITY vs TEMPERATURE
8
7
6
5
4
3
2
1
0
16
14
12
10
8
6
4
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−250 −200 −150 −100 −50
0
50 100 150 200 250
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Input Signal Amplitude (mV)
Figure 2.
Figure 3.
OFFSET ERROR
vs ANALOG SUPPLY VOLTAGE
OFFSET ERROR vs TEMPERATURE
1
0.8
1
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
4.5
5
5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
AVDD (V)
Temperature (°C)
Figure 4.
Figure 5.
OFFSET ERROR vs CLOCK FREQUENCY
OFFSET ERROR vs CLOCK DUTY CYCLE
1
0.8
1
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
5
10
15
20
25
40
45
50
55
60
Clock Freuency (MHz)
Clock Duty Cycle (%)
Figure 6.
Figure 7.
8
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
GAIN ERROR vs ANALOG SUPPLY VOLTAGE
GAIN ERROR vs TEMPERATURE
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−1.5
−2
4.5
−2
5
5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
AVDD (V)
Temperature (°C)
Figure 8.
Figure 9.
GAIN ERROR vs CLOCK FREQUENCY
GAIN ERROR vs CLOCK DUTY CYCLE
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−2
−1.5
−2
5
10
15
20
25
40
45
50
55
60
Clock Frequency (MHz)
Clock Duty Cycle (%)
Figure 10.
Figure 11.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
COMMON-MODE REJECTION RATIO
vs INPUT SIGNAL FREQUENCY
100
90
80
70
60
140
130
120
110
100
90
Unfiltered
sinc3, OSR = 256
80
0.1
0.1
1
10
100
1
10
100
1000
Frequency (kHz)
Input Signal Frequency (kHz)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
SINAD AND SNR vs ANALOG SUPPLY VOLTAGE
SINAD AND SNR vs TEMPERATURE
100
90
80
70
60
100
90
80
70
60
SINAD
SNR
SINAD
SNR
4.5
5
5.5
100
25
−40 −25 −10
5
20 35 50 65 80 95 110 125
AVDD (V)
Temperature (°C)
Figure 14.
Figure 15.
SINAD AND SNR vs INPUT SIGNAL FREQUENCY
SINAD AND SNR vs INPUT SIGNAL AMPLITUDE
100
90
80
70
60
100
90
80
70
60
50
40
30
20
10
0
SINAD
SNR
SINAD
SNR
0.1
1
10
0.1
1
10
100
1000
Input Signal Frequency (kHz)
Input Signal Amplitude (mVpp)
Figure 16.
Figure 17.
SINAD AND SNR vs CLOCK FREQUENCY
SINAD AND SNR vs CLOCK DUTY CYCLE
100
90
80
70
60
100
90
80
70
60
SINAD
SNR
SINAD
SNR
5
10
15
20
40
45
50
55
60
Clock Frequency (MHz)
Clock Duty Cycle (%)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
TOTAL HARMONIC DISTORTION
vs ANALOG SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
−60
−70
−60
−70
−80
−80
−90
−90
−100
−110
−120
−100
−110
−120
4.5
5
5.5
100
25
−40 −25 −10
5
20 35 50 65 80 95 110 125
AVDD (V)
Temperature (°C)
Figure 20.
Figure 21.
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL AMPLITUDE
−60
−70
0
−10
−20
−30
−80
−40
−50
−90
−60
−70
−100
−110
−120
−80
−90
−100
−110
−120
0.1
1
10
0.1
1
10
100
1000
Input Signal Frequency (kHz)
Input Signal Amplitude (mVpp)
Figure 22.
Figure 23.
TOTAL HARMONIC DISTORTION
vs CLOCK FREQUENCY
TOTAL HARMONIC DISTORTION
vs CLOCK DUTY CYCLE
−60
−70
−60
−70
−80
−80
−90
−90
−100
−110
−120
−100
−110
−120
5
10
15
20
40
45
50
55
60
Clock Frequency (MHz)
Clock Duty Cycle (%)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
SPURIOUS-FREE DYNAMIC RANGE
vs ANALOG SUPPLY VOLTAGE
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
120
110
100
90
120
110
100
90
80
80
70
70
60
60
4.5
5
5.5
100
25
−40 −25 −10
5
20 35 50 65 80 95 110 125
AVDD (V)
Temperature (°C)
Figure 26.
Figure 27.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SUGNAL FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SIGNAL AMPLITUDE
120
110
100
90
120
110
100
90
80
70
60
50
40
30
20
10
0
80
70
60
0.1
1
10
0.1
1
10
100
1000
Input Signal Frequency (kHz)
Input Signal Amplitude (mVpp)
Figure 28.
Figure 29.
SPURIOUS-FREE DYNAMIC RANGE
vs CLOCK FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs CLOCK DUTY CYCLE
120
110
100
90
120
110
100
90
80
80
70
70
60
60
5
10
15
20
40
45
50
55
60
Clock Frequency (MHz)
Clock Duty Cycle (%)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 point FFT, fIN = 1 kHz, 056 VPP
)
(4096 point FFT, fIN = 5 kHz, 056 VPP)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (kHz)
Frequency (kHz)
Figure 32.
Figure 33.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT vs TEMPERATURE
16
14
12
10
8
16
14
12
10
8
6
6
4
4
2
2
0
4.5
0
5
5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
AVDD (V)
Figure 34.
Figure 35.
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY
vs DIGITAL SUPPLY VOLTAGE (3 V)
16
16
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
2.7
5
10
15
20
25
3
3.3
3.6
Clock Frequency (MHz)
DVDD (V)
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
At AVDD = 5 V, DVDD = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise
noted.
DIGITAL SUPPLY CURRENT
vs DIGITAL SUPPLY VOLTAGE (5 V)
DIGITAL SUPPLY CURRENT vs TEMPERATURE
16
14
12
10
8
16
14
12
10
8
DVDD = 3.3V
DVDD = 5V
6
6
4
4
2
2
0
4.5
0
5
5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
DVDD (V)
Figure 38.
Figure 39.
DIGITAL SUPPLY CURRENT
vs CLOCK FREQUENCY
16
DVDD = 3.3V
DVDD = 5V
14
12
10
8
6
4
2
0
5
10
15
20
25
Clock Frequency (MHz)
Figure 40.
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GENERAL DESCRIPTION
The AMC1204-Q1 is a single-channel, second-order, delta-sigma (ΔΣ) modulators designed for medium- to high-
resolution analog-to-digital conversions. The isolated output of the converter (DATA) provides a stream of digital
ones and zeros. The time average of this serial output is proportional to the analog input voltage.
Figure 41 shows a detailed block diagram of the AMC1204-Q1. The analog input range is tailored to directly
accommodate a voltage drop across a shunt resistor used for current sensing. The SiO2-based capacitive
isolation barrier supports a high level of magnetic field immunity as described in the application report ISO72x
Digital Isolator Magnetic-Field Immunity (SLLA181A, available for download at www.ti.com). The external clock
input simplifies the synchronization of multiple current sense channels on system level. The extended frequency
range of up to 20 MHz supports higher performance levels compared to the other solutions available on the
market.
Isolation Barrier
+
-
VINP
3-State
Output
Buffer
2nd-Order
DS Modulator
VREF
DATA
+
VINN
-
POR
+
Buffer
-
VREF
CLKIN
+
2.5V
VREF
-
Figure 41. Detailed Block Diagram
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THEORY OF OPERATION
The differential analog input of the AMC1204-Q1 is implemented with a switched-capacitor circuit. This switched-
capacitor circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output
stream. The externally-provided clock source at the CLKIN pin is used by the capacitor circuit and the modulator
and should be in the range of 5 MHz to 22 MHz. The analog input signal is continuously sampled by the
modulator and compared to an internal voltage reference. A digital stream, accurately representing the analog
input voltage over time, appears at the output of the converter at the DATA pin.
ANALOG INPUT
The AMC1204-Q1 measures the differential input signal VIN = (VINP – VINN) against the internal reference of 2.5
V using internal capacitors that are continuously charged and discharged. Figure 42 shows the simplified
schematic of the ADC input circuitry; the right side of Figure 42 illustrates the input circuitry with the capacitors
and switches replaced by an equivalent circuit.
In Figure 42, the S1 switches close during the input sampling phase. With the S1 switches closed, CDIFF charges
to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first and then
both S2 switches close. CDIFF discharges approximately to AGND + 0.8 V during this phase. This two-phase
sample/discharge cycle repeats with a period of tCLKIN = 1/fCLKIN. fCLKIN is the operating frequency of the
modulator. The capacitors CIP and CIN are of parasitic nature and caused by bonding wires and the internal ESD
protection structure.
AVDD
AGND
AGND
CIP = 3pF
3pF
200W
200W
Equivalent
Circuit
VINP
VINN
VINP
VINN
AGND + 0.8V
AGND + 0.8V
S1
S1
S2
S2
REFF = 12.5kW
CDIFF = 4pF
3pF
CIN = 3pF
AGND
1
CLKIN ´ CDIFF
REFF
=
f
AGND
AGND
(fCLKIN = 20MHz)
Figure 42. Equivalent Analog Input Circuit
The input impedance becomes a consideration in designs with high input signal source impedance. This high
impedance may cause degradation in gain, linearity, and THD. The importance of this effect, however, depends
on the desired system performance. This input stage provides the mechanism to achieve low system noise, high
common-mode rejection (105 dB), and excellent power-supply rejection.
There are two restrictions on the analog input signals VINP and VINN. First, if the input voltage exceeds the
range AGND – 0.5 V to AVDD + 0.3 V, the input current must be limited to 10 mA because the input protection
diodes on the front end of the converter begin to turn on. In addition, the linearity and the noise performance of
the device are ensured only when the differential analog input voltage remains within ±250 mV.
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MODULATOR
The modulator topology of the AMC1204-Q1 is fundamentally a second-order, switched-capacitor, ΔΣ modulator,
such as the one conceptualized in Figure 43. The analog input voltage (X(t)) and the output of the 1-bit digital-to-
analog converter (DAC) are differentiated, providing an analog voltage (X2) at the input of the first integrator or
modulator stage. The output of the first integrator is further differentiated with the DAC output; the resulting
voltage (X3) feeds the input of the second integrator stage. When the value of the integrated signal (X4) at the
output of the second stage equals the comparator reference voltage, the output of the comparator switches from
high to low, or vice versa, depending on its previous state. In this case, the 1-bit DAC responds on the next clock
pulse by changing its analog output voltage (X6), causing the integrators to progress in the opposite direction,
while forcing the value of the integrator output to track the average of the input.
fCLK
X2
X3
X4
X(t)
fS
Integrator 1
Integrator 2
DATA
VREF
Comparator
X6
DAC
Figure 43. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 44; therefore, a low-pass
digital filter should be used at the output of the device to increase the overall performance. This filter is also used
to convert from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate
(decimation). A digital signal processor (DSP), microcontroller (µC), or field programmable gate array (FPGA)
can be used to implement the filter. Another option is to use a suitable application-specific device such as the
AMC1210, a four-channel digital sinc-filter.
0
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k
100k
1G
10G
Frequency (Hz)
Figure 44. Quantization Noise Shaping
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DIGITAL OUTPUT
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of 250 mV produces a stream of ones and zeros that are high 78.1% of
the time. A differential input of –250 mV produces a stream of ones and zeros that are high 21.9% of the time.
This is also the specified linear input range of the modulator with the performance as specified in this data sheet.
The range between 250 mV and 320 mV (absolute values) is the non-linear range of the modulator. The output
of the modulator clips with a stream of only zeros with an input less than or equal to –320 mV or with a stream of
only ones with an input greater than or equal to 320 mV. The input voltage versus the output modulator signal is
shown in Figure 45.
The system clock of the AMC1204-Q1 is typically 20 MHz and is provided externally at the CLKIN pin. The data
are synchronously provided at 20 MHz at the DATA output pin. The data are changing at the falling edge of
CLKIN; for more details see the Timing Information section.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 45. Analog Input versus AMC1204-Q1 Modulator Output
FILTER USAGE
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort
and hardware, is a sinc3-type filter, as shown in Equation 1:
3
-OSR
1 - z
1 - z
H(z) =
-1
(1)
This filter provides the best output performance at the lowest hardware size (count of digital gates). For an
oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this
document is also done with a sinc3 filter with OSR = 256 and an output word width of 16 bits.
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In a sinc3 filter response (shown in Figure 46 and Figure 47), the location of the first notch occurs at the
frequency of output data rate fDATA = fCLK/OSR. The –3 dB point is located at half the Nyquist frequency or
fDATA/4. For some applications, it may be necessary to use another filter type with different frequency response.
Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could
be built of a sinc3 filter with a low OSR and the second stage using a high-order filter.
0
-10
-20
-30
-40
-50
-60
-70
-80
30k
25k
20k
15k
10k
5k
fDATA = 20MHz/64 = 312.5kHz
-3dB: 81.9kHz
fMOD = 20MHz
OSR = 64
FSR = 32768
ENOB = 12 Bits
Settling Time =
3 ´ 1/fDATA = 9.6ms
OSR = 64
0
0
200
400
600
800 1000 1200 1400 1600
0
5
10
15
20
25
30
35
40
Frequency (kHz)
Number of Output Clocks
Figure 46. Frequency Response of the Sinc3 Filter
Figure 47. Pole Response of the Sinc3 Filter
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 48 illustrates the ENOB of the AMC1204-Q1 with different oversampling ratios. In this data sheet, this
number is calculated from SNR using Equation 2:
SNR = 1.76dB + 6.02dB ´ ENOB
(2)
In motor control applications, a very fast response time for overcurrent detection is required. The time for fully
settling the filter depends on its order; that is, a sinc3 filter requires three data clocks for full settling (with fDATA
=
fCLK/OSR). Therefore, for overcurrent protection, filter types other than sinc3 might be a better choice; an
alternative is the sinc2 filter. Figure 49 compares the settling times of different filter orders with sincfast being a
modified sinc2 filter with behavior as shown in Equation 3.
2
-OSR
1 - z
-1
1 - z
-2OSR
H(z) =
(1 + z
)
(3)
16
16
14
12
10
8
sinc3
14
12
10
8
sincfast
sinc2
sinc3
sincfast
sinc2
6
6
sinc1
sinc1
4
4
2
2
0
0
1
10
100
1000
0
1
2
3
4
5
6
7
8
9
10 11 12 13
OSR
Settling Time (ms)
Figure 48. Measured Effective Number of Bits
versus Oversampling Ratio
Figure 49. Measured Effective Number of Bits
versus Settling Time
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An example code for an implementation of a sinc3 filter in an FPGA follows. For more information, see the
application note Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control
Applications (SBAA094), available for download at www.ti.com.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5 : out std_logic_vector(23 downto 0));
end FLT;
architecture RTL of FLT is
signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0);
signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0);
signal DELTA1 : std_logic_vector(23 downto 0);
begin
process(MCLK, RESn)
begin
if RESn = '0' then
DELTA1 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
if MOUT = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
process(RESN, MCLK)
begin
if RESN = '0' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif CNR'event and CNR = '1' then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
CN5 <= CN4 - DN5;
end RTL;
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APPLICATION INFORMATION
A typical operation of the AMC1204-Q1 in a motor control application is shown in Figure 50. Measurement of the
motor phase current is done via the shunt resistor RSHUNT (in this case, a two-terminal shunt). For better
performance, the differential signal is filtered using RC filters (components R2, R3, and C2). Optionally, C3 and C4
can be used to reduce charge dumping from the inputs. In this case, care should be taken when choosing the
quality of these capacitors—mismatch in values of these capacitors leads to a common-mode error at the input of
the modulator.
The high-side power supply (AVDD) for the AMC1204-Q1 is derived from the power supply of the upper gate
driver. For lowest cost, a zener diode can be used to limit the voltage to 5 V ±10%. A decoupling capacitor of 0.1
µF is recommended for filtering this power-supply path. This capacitor (C1 in Figure 50) should be placed as
close as possible to the AVDD pin for best performance. If better filtering is required, an additional 1 µF to 10 µF
capacitor can be used. The floating ground reference AGND is derived from the end of the shunt resistor, which
is connected to the negative input (VINN) of the AMC1204-Q1. If a four-terminal shunt is used, the inputs of
AMC1204-Q1 are connected to the inner leads, while AGND is connected to one of the outer leads of the shunt.
Both digital signals, CLKIN and DATA, can be directly connected to a digital filter (for example, the AMC1210);
see Figure 51.
Floating
Power Supply
Isolation
HV+
Barrier
Gated
Drive
R1
AMC1204-Q1
Circuit
AVDD DVDD
(1)
C1
0.1mF
D1
R2
5.1V
12W
VINP
VINN
DATA
C2
R3
330pF
RSHUNT
12W
To Load
CLKIN
C3
C4
10pF
10pF
(optional)
(optional)
Power
Supply
AGND DGND
Gated
Drive
Circuit
HV-
(1) Place C1 close to the AMC1204-Q1.
Figure 50. Typical Application Diagram
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Figure 51 shows an example of two AMC1204-Q1 devices and one ADS1209 (a dual-channel, 10 MHz, non-
isolated modulator) connected to an AMC1210, building the entire analog front-end of a resolver-based motor
control application.
For detailed information on the ADS1209 and AMC1210, visit the respective device product folders at
www.ti.com.
Resolver
AMC1210
Control Module
PWM1
PWM2
Signal
Generator
Filter Module 1
Comparator
Filter
IN1
CLK
RST
INT
CLK1
Interrupt
Unit
Input
Control
Sinc Filter/
Integrator
ADS1209
ACK
IN2
Time
Measurement
CS
ALE
RD
Filter
Module 2
WR
M0
Register
Map
CLK2
Interface
Module
M1
IN3
Current
Shunt
Resistor
AD0
Filter
Module 3
AMC1204-Q1
CLK3
AD7
IN4
Current
Shunt
Resistor
Filter
Module 4
AMC1204-Q1
CLK4
Figure 51. Example of a Resolver-Based Motor Control Analog Front-End
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A layout recommendation showing the critical placement of the decoupling capacitor on the high-side and
placement of the other components required by the AMC1204-Q1 is presented in Figure 52.
Top View
Clearance Area
Keep Free of Any Conductive Materials
AVDD
VINP
VINN
AGND
NC
DGND
NC
0.1mF
SMD
0603
0.1mF
12W
SMD 0603
330pF
SMD
0603
To
Shunt
12W
SMD 0603
SMD
1206
DVDD
CLKIN
NC
From
AMC1210
AMC1204-Q1
To
AMC1210
NC
DATA
NC
NC
AGND
DGND
LEGEND
Top layer; copper pour and traces
High-Side Area
Controller-Side Area
Via
Figure 52. Recommended Layout
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ISOLATION GLOSSARY
Creepage Distance: The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance: The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that
supplies the primary circuit electric power.
Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate
isolated source.
Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
Insulation:
Operational insulation—Insulation needed for the correct operation of the equipment.
Basic insulation—Insulation to provide basic protection against electric shock.
Supplementary insulation—Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation—Insulation comprising both basic and supplementary insulation.
Reinforced insulation—A single insulation system that provides a degree of protection against electric shock
equivalent to double insulation.
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AMC1204-Q1
www.ti.com
SLAS886B –JULY 2012–REVISED JANUARY 2013
Pollution Degree:
Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on
device performance.
Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation is to be expected.
Pollution Degree 3—Conductive pollution, or dry nonconductive pollution that becomes conductive because of
condensation, occurs. Condensation is to be expected.
Pollution Degree 4—Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category—This section is directed at insulation coordination by identifying the transient overvoltages
that may occur, and by assigning four different levels as indicated in IEC 60664.
1. Signal Level: Special equipment or parts of equipment.
2. Local Level: Portable equipment, etc.
3. Distribution Level: Fixed installation.
4. Primary Supply Level: Overhead lines, cable systems.
Each category should be subject to smaller transients than the previous category.
Copyright © 2012–2013, Texas Instruments Incorporated
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Product Folder Links: AMC1204-Q1
AMC1204-Q1
SLAS886B –JULY 2012–REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (October, 2012) to Revision B
Page
•
•
•
•
Changed VPEAK from 4000 to 4250. ...................................................................................................................................... 1
Changed VPEAK from 4000 to 4250. ...................................................................................................................................... 1
Changed VIOTMwith t = 60 s (qualification test) test condition from 4000 to 4250. ............................................................... 4
Changed VIOTM with t = 1 s (100% production test) test condition from 4000 to 5100. ........................................................ 4
26
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: AMC1204-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
AMC1204QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1204Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1204-Q1 :
Catalog: AMC1204
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1204QDWRQ1
SOIC
DW
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
AMC1204QDWRQ1
2000
Pack Materials-Page 2
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