AMC1300DWV [TI]
±250mV 输入、精密电流检测增强型隔离式放大器
| DWV | 8 | -40 to 125;型号: | AMC1300DWV |
厂家: | TEXAS INSTRUMENTS |
描述: | ±250mV 输入、精密电流检测增强型隔离式放大器 | DWV | 8 | -40 to 125 放大器 |
文件: | 总39页 (文件大小:2004K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AMC1300
ZHCSI99D –MAY 2018 –REVISED MAY 2022
AMC1300 精密、±250mV 输入、增强型隔离放大器
1 特性
3 说明
• ±250mV 输入电压范围,针对使用分流电阻器测量
电流进行了优化
• 固定增益:8.2
AMC1300 是一款隔离式精密放大器,此放大器的输出
与输入电路由抗电磁干扰性能极强的隔离栅隔开。根据
VDE V 0884-11 和 UL1577 标准,该隔离栅经认证可
提供高达5kVRMS 的增强型电隔离。与隔离式电源结合
使用时,该隔离放大器可将以不同共模电压电平运行的
系统的各器件隔开,并防止较低电压器件损坏。
• 低直流误差:
– AMC1300B:
• 失调电压误差:±0.2mV(最大值)
• 温漂:±0.9µV/°C(最大值)
• 增益误差:±0.3%(最大值)
• 增益漂移:±30ppm/°C(最大值)
– AMC1300:
AMC1300 的输入经过优化,可直接连接至分流电阻器
或其他低电压电平信号源。该器件出色的性能可实现精
确电流控制,从而降低系统级功耗,特别是对于电机控
制应用,能够降低扭矩纹波。AMC1300 的集成式共模
过压和无高侧电源电压检测功能可简化系统级设计和诊
断。
• 失调电压误差:±2mV(最大值)
• 温漂:±4µV/°C(最大值)
• 增益误差:±1%(最大值)
AMC1300 提供两种性能级别选项:AMC1300B 和
AMC1300,两者的额定扩展工业温度范围分别为 –
55°C 至+125°C 和–40°C 至+125°C。
• 增益漂移:±50ppm/°C(典型值)
– 非线性度:0.03%(最大值)
• 高侧3.3V 工作电压(AMC1300B)
• 高CMTI:100kV/µs(最小值)(AMC1300B)
• 低EMI,符合CISPR-11 和CISPR-25 标准
• 系统级诊断功能
器件信息(1)
封装尺寸(标称值)
器件型号
AMC1300
封装
SOIC (8)
5.85mm × 7.50mm
• 安全相关认证:
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
– 7071-VPK 增强型隔离,符合DIN VDE V
0884-11:2017-01
– 符合UL1577 标准且长达1 分钟的5000VRMS
隔离
2 应用
• 基于分流电阻器的电流感应,可用于:
– 电机驱动器
– 变频器
– 不间断电源
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
AMC1300B
VDD1
VDD2
OUTP
I
INP
+250 mV
mV
0 V
VCMout
±2.05 V
ADC
–
INN
OUTN
GND2
GND1
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBAS895
AMC1300
ZHCSI99D –MAY 2018 –REVISED MAY 2022
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Table of Contents
8.1 Overview...................................................................21
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................23
9 Application and Implementation..................................24
9.1 Application Information............................................. 24
9.2 Typical Application.................................................... 24
9.3 What To Do and What Not To Do..............................27
10 Power Supply Recommendations..............................28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Documentation Support.......................................... 30
12.2 接收文档更新通知................................................... 30
12.3 支持资源..................................................................30
12.4 Trademarks.............................................................30
12.5 Electrostatic Discharge Caution..............................30
12.6 术语表..................................................................... 30
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................7
7.5 Power Ratings ............................................................7
7.6 Insulation Specifications ............................................ 8
7.7 Safety-Related Certifications ..................................... 9
7.8 Safety Limiting Values ................................................9
7.9 Electrical Characteristics ..........................................10
7.10 Switching Characteristics .......................................12
7.11 Timing Diagram.......................................................12
7.12 Insulation Characteristics Curves........................... 13
7.13 Typical Characteristics............................................14
8 Detailed Description......................................................21
Information.................................................................... 30
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision C (June 2021) to Revision D (May 2022)
Page
• Changed CDM ESD standard from JESD22-C101 to ANSI/ESDA/JEDEC JS-002 .........................................6
• Changed TA (max) for AMC1300 from 105 ℃to 125 ℃. .................................................................................. 6
• Updated VDE standard references is Safety-Related Certifications table..........................................................9
Changes from Revision B (April 2020) to Revision C (June 2021)
Page
• 更改了特性部分..................................................................................................................................................1
• 通篇更改了多个图(仅限编辑更改).................................................................................................................. 1
• Changed TCVOS, TCEG, and CMTI values in AMC1300B column of Device Comparison Table ......................4
• Changed CIO from ~1 pF to ~1.5 pF...................................................................................................................8
• Changed VCMov hysteresis from 95 mV to 60 mV.............................................................................................10
• Changed TCVOS (AMC1300B) from ±3 to ±0.9 µV/℃and typical value from ±1 to ±0.1 µV/℃....................... 10
• Changed TCEG (AMC1300B) from ±50 to ±30 ppm/℃and typical value from ±15 to ±5 ppm/℃....................10
• Changed SNR (min), fIN = 1 kHz from 80 dB to 81.5 dB.................................................................................. 10
• Added VCLIPout specification............................................................................................................................. 10
• Changed VFAILSAFE from * / –2.6 V / –2.5 V to –2.63 V / –2.57 V / –2.53 V (min / typ /max)....................10
• Changed output short-circuit current from ±13 mA to 14 mA (sourcing or sinking)..........................................10
• Changed CMTI (AMC1300B) min from 75 to 100 kV/µs and typ from 140 to 150 kV/µs................................. 10
• Changed VDD1UV from 1.75 V / 2.53 V / 2.7 V to 2.4 V / 2.6 V / 2.8 V (min / typ / max).............................. 10
• Changed Analog Input section..........................................................................................................................21
• Changed Analog Output section.......................................................................................................................23
• Changed Detailed Design Procedure section...................................................................................................25
• Added Shunt Resistor Sizing section................................................................................................................25
• Added Input Filter Design section.....................................................................................................................25
• Added Differential to Single-Ended Output Conversion section....................................................................... 26
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• Changed Application Curves section................................................................................................................27
• Added layout recommendations to What To Do and What Not To Do section................................................. 27
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5 Device Comparison Table
PARAMETER
High-side supply voltage, VDD1
Specified ambient temperature, TA
AMC1300B
3.0 V to 5.5 V
AMC1300
4.5 V to 5.5 V
–40°C to +125°C
±2 mV
–55°C to +125°C
4.5 V ≤VDD1 ≤5.5 V
3.0 V ≤VDD1 ≤4.5 V
Input offset voltage, VOS
±0.2 mV
Not applicable
Input offset drift, TCVOS
Gain error, EG
±0.9 µV/°C (max)
±0.3%
±4 µV/°C (max)
±1%
Gain error drift, TCEG
±5 ppm/°C (typ), ±30 ppm/°C (max)
100 kV/µs (min), 150 kV/µs (typ)
250 kHz (min), 310 kHz (typ)
3 µs (max)
±50 ppm/°C (typ)
15 kV/µs (min), 30 kV/µs (typ)
170 kHz (min), 230 kHz (typ)
3.4 µs (max)
Common-mode transient immunity, CMTI
Output bandwidth, BW
INP, INN to OUTP, OUTN signal delay (50% –90%)
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6 Pin Configuration and Functions
VDD1
INP
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
INN
GND1
Not to scale
图6-1. DWV Package, 8-Pin SOIC, Top View
表6-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
2
VDD1
INP
High-side power
Analog input
High-side power supply.(1)
Noninverting analog input. Either INP or INN must have a DC current path to GND1
to define the common-mode input voltage.(2)
Inverting analog input. Either INP or INN must have a DC current path to GND1 to
define the common-mode input voltage.(2)
3
INN
Analog input
4
5
6
7
8
GND1
GND2
OUTN
OUTP
VDD2
High-side ground
Low-side ground
Analog output
High-side analog ground.
Low-side analog ground.
Inverting analog output.
Noninverting analog output.
Low-side power supply.(1)
Analog output
Low-side power
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
(2) See the Layout section for details.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
High-side VDD1 to GND1
Power-supply voltage
6.5
6.5
V
Low-side VDD2 to GND2
–0.3
Analog input voltage
Output voltage
Input current
INP, INN
VDD1 + 0.5
VDD2 + 0.5
10
V
V
GND1 –6
GND2 –0.5
–10
OUTP, OUTN
Continuous, any pin except power-supply pins
mA
°C
°C
Junction, TJ
Storage, Tstg
150
Temperature
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
VDD1 to GND1, AMC1300
VDD1 to GND1, AMC1300B
VDD2 to GND2
4.5
3
5
5
5.5
5.5
5.5
V
V
Low-side power supply
ANALOG INPUT
VClipping Differential input voltage before clipping output
3
3.3
VIN = VINP - VINN
±320
mV
mV
V
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage(1)
VIN = VINP - VINN
250
VDD1
–250
–2
(VINP+VINN) / 2 to GND1
VDD1 –
2.1
VCM
Operating common-mode input voltage
(VINP+VINN) / 2 to GND1
V
–0.16
TEMPERTURE RANGE
TA Specified ambient temperature
AMC1300
125
125
°C
°C
–40
–55
AMC1300B
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in Absolute Maximum Ratings.
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7.4 Thermal Information
AMC1300x
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
85.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
26.8
43.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.8
ψJT
41.2
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD1 = VDD2 = 5.5 V
VALUE
99
UNIT
PD
Maximum power dissipation (both sides)
mW
VDD1 = VDD2 = 3.6 V, AMC1300B only
VDD1 = 5.5 V
57
54
PD1
Maximum power dissipation (high-side)
Maximum power dissipation (low-side)
mW
mW
VDD1 = 3.6 V, AMC1300B only
VDD2 = 5.5 V
31
45
PD2
VDD2 = 3.6 V
26
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UNIT
7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
CPG
External clearance(1)
External Creepage(1)
Shortest terminal-to-terminal distance through air
mm
mm
≥8.5
≥8.5
Shortest terminal-to-terminal distance across the
package surface
Minimum internal gap (internal clearance) of the
double isolation (2 x 0.0105 mm)
DTI
CTI
Distance through the insulation
mm
V
≥0.021
Comparative tracking index
Material Group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥600
I
I-IV
I-III
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category
DIN VDE 0884-11 (VDE V 0884-11): 2017-01
VIORM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
1500
VPK
AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test; see Figure 4
VRMS
VIOWM
Maximum isolation working voltage
DC voltage
2121
7071
8485
VDC
VPK
VPK
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = VIOTM, t = 1 s (100% production test)
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage(2)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
VIOSM
8000
VPK
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545
VPK, tm = 10 s
≤5
Method a: After environmental tests subgroup 1,
qpd
Apparent charge(3)
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM
3394 VPK, tm = 10 s
=
pC
≤5
≤5
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(4)
Insulation resistance, input to output(4)
~1.5
> 1012
> 1011
> 109
2
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
55/125/21
UL 1577
VTEST = VISO = 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Careshould be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator onthe printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases.Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 62368-1: 2016-05,
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
EN 62368-1: 2014, and IEC 62368-1: 2014
Reinforced insulation
Single protection
Certificate number: 40040142
Certificate number: E181974
7.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-
heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 85.4°C/W, VDDx = 5.5 V,
IS
IS
Safety input, output, or supply current
266
mA
TJ = 150°C, TA = 25°C
θJA = 85.4°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 85.4°C/W, TJ = 150°C, TA = 25°C
R
Safety input, output, or supply current
407
mA
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1464
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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7.9 Electrical Characteristics
minimum and maximum specifications of the AMC1300 apply from TA = –40°C to+105°C, VDD1 = 4.5 V to 5.5 V, VDD2 =
3.0 V to 5.5 V, INP = –250 mV to + 250 mV, and INN = GND1; minimum and maximum specifications of the AMC1300B
apply fromTA = –55°C to+125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP = –250 mV to + 250 mV, and INN =
GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT
Common-mode overvoltage
detection level
VCMov
(VINP+VINN) / 2 to GND1
V
VDD1 –2
Hysteresis of common-mode
overvoltage detection level
60
±0.01
±0.01
±0.01
mV
AMC1300, initial, at TA = 25°C, VINP
VINN = GND1
=
2
–2
–0.2
–0.2
AMC1300B, initial, at TA = 25°C, VINP
VINN = GND1, 4.5 V ≤VDD1 ≤5.5 V
=
0.2
0.2
VOS
Input offset voltage(1) (2)
mV
AMC1300B, initial, at TA = 25°C, VINP
VINN = GND1, 3.0 V ≤VDD1 ≤5.5 V
=
AMC1300
±1.3
±0.1
4
–4
TCVOS
CMRR
Input offset drift(1) (2) (4)
uV/°C
dB
AMC1300B
0.9
–0.9
fIN = 0 Hz, VCM min
≤
VCM ≤VCM max
≤VCM ≤VCM max
–100
–98
19
Common-mode rejection ratio
fIN = 10 kHz, VCM min
INN = GND1
RIN
RIND
IIB
Single-ended input resistance
Differential input resistance
Input bias current
kΩ
22
INP = INN = GND1; IIB = (IIBP+IIBN) / 2
IIO = IIBP - IIBN
uA
nA
–41
–30
±5
–24
IIO
Input offset current
CIN
CIND
Single-ended input capacitance
Differential input capacitance
INN = GND1, fIN = 275 kHz
fIN = 275 kHz
2
pF
1
ANALOG OUTPUT
Nominal gain
8.2
0.4%
±0.05%
±50
AMC1300, initial, at TA = 25°C
AMC1300B, initial, at TA = 25°C
AMC1300
1%
–1%
EG
Gain error(1)
0.3%
–0.3%
TCEG
Gain error drift(1) (5)
ppm/°C
AMC1300B
±5
30
–30
Nonlinearity(1)
±0.01
–85
0.03
%
–0.03
THD
SNR
Total harmonic distortion(3)
fIN = 10 kHz
dB
INP = INN = GND1, fIN = 0 Hz, BW = 100
kHz brickwall filter
Output noise
230
µVRMS
dB
fIN = 1 kHz, BW = 10 kHz
fIN = 10 kHz, BW = 100 kHz
PSRR vs VDD1, at DC
81.5
85
72
Signal-to-noise ratio
–103
PSRR vs VDD1, 100-mV and 10-kHz
ripple
–96
–106
–86
PSRR
Power-supply rejection ratio(2)
dB
PSRR vs VDD2, at DC
PSRR vs VDD2, 100-mV and 10-kHz
ripple
VCMout
Common-mode output voltage
1.39
–2.52
–2.63
1.44
1.49
2.52
V
V
V
VOUT = (VOUTP –VOUTN);
|VIN| = |VINP –VINN| > |VClipping
VCLIPout
Clipping differential output voltage
±2.49
|
VFAILSAFE Failsafe differential output voltage
VCM ≥VCMov, or VDD1 missing
–2.57
–2.53
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7.9 Electrical Characteristics (continued)
minimum and maximum specifications of the AMC1300 apply from TA = –40°C to+105°C, VDD1 = 4.5 V to 5.5 V, VDD2 =
3.0 V to 5.5 V, INP = –250 mV to + 250 mV, and INN = GND1; minimum and maximum specifications of the AMC1300B
apply fromTA = –55°C to+125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP = –250 mV to + 250 mV, and INN =
GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted)
PARAMETER
Output bandwidth
Output resistance
TEST CONDITIONS
MIN
170
250
TYP
MAX UNIT
AMC1300
230
BWOUT
ROUT
kHz
AMC1300B
310
On OUTP or OUTN
< 0.2
Ω
On OUTP or OUTN, sourcing or sinking,
INN = INP = GND1, outputs shorted to
either GND2 or VDD2
Output short-circuit current
14
mA
15
30
|GND1 –GND2| = 1 kV, AMC1300
|GND1 –GND2| = 1 kV, AMC1300B
CMTI
Common-mode transient immunity
kV/µs
100
150
POWER SUPPLY
VDD1 undervoltage detection
threshold voltage
VDD1UV
IDD1
VDD1 falling
2.4
2.6
2.8
V
6.3
7.2
5.3
5.9
8.5
9.8
7.2
8.1
AMC1300B only, 3.0 V ≤VDD1 ≤3.6 V
4.5 V ≤VDD1 ≤5.5 V
High-side supply current
mA
3.0 V ≤VDD2 ≤3.6 V
IDD2
Low-side supply current
mA
4.5 V ≤VDD2 ≤5.5 V
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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7.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Output signal rise time
Output signal fall time
TEST CONDITIONS
MIN
TYP
1.3
1.3
1.5
1
MAX
UNIT
µs
tr
tf
µs
AMC1300, unfiltered output
AMC1300B, unfiltered output
AMC1300, unfiltered output
AMC1300B, unfiltered output
AMC1300, unfiltered output
AMC1300B, unfiltered output
2.2
1.5
2.7
2.1
3.4
3
VINx to VOUTx signal delay (50% - 10%)
VINx to VOUTx signal delay (50% - 50%)
µs
µs
2
1.6
2.7
2.5
VINx to VOUTx signal delay (50% - 90%)
Analog settling time
µs
µs
VDD1 step to 3.0 V with VDD2 ≥3.0 V,
to VOUTP, VOUTN valid, 0.1% settling
tAS
500
7.11 Timing Diagram
250 mV
INP - INN
0
– 250 mV
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90%
图7-1. Rise, Fall, and Delay Time Waveforms
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7.12 Insulation Characteristics Curves
500
1600
1400
1200
1000
800
600
400
200
0
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
400
300
200
100
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D002
D001
图7-3. Thermal Derating Curve for Safety-Limiting Power per
图7-2. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
87.5%
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS
)
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 year
图7-4. Reinforced Isolation Capacitor Lifetime Projection
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7.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.4
3
3.3
3.25
3.2
3.15
3.1
2.6
2.2
1.8
1.4
1
3.05
3
2.95
2.9
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD1 (V)
5
5.25 5.5
D004
D003
–55°C ≤TA < –40°C for AMC1300B only
图7-6. Common-Mode Overvoltage Detection Level vs
图7-5. Common-Mode Overvoltage Detection Level vs High-
Temperature
Side Supply Voltage
200
200
vs VDD1
vs VDD2
Device 1
Device 2
Device 3
150
100
50
150
100
50
0
0
-50
-50
-100
-150
-200
-100
-150
-200
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D006
D007
AMC1300
图7-8. Input Offset Voltage vs Temperature
3 V ≤VDD1 < 4.5 V for AMC1300B only
图7-7. Input Offset Voltage vs Supply Voltage
200
150
100
50
0
-20
Device 1
Device 2
Device 3
-40
0
-60
-50
-80
-100
-150
-200
-100
-120
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0.001
0.01
0.1
1
fIN (kHz)
10
100
1000
D008
D010
AMC1300B
图7-9. Input Offset Voltage vs Temperature
图7-10. Common-Mode Rejection Ratio vs Input Frequency
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
-70
-75
25
15
-80
5
-85
-5
-90
-15
-25
-35
-45
-95
-100
-105
-110
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-0.5
0
0.5
1
1.5
2
2.5
3
VCM (V)
D011
D012
–55°C ≤TA < –40°C for AMC1300B only
图7-11. Common-Mode Rejection Ratio vs Temperature
图7-12. Input Bias Current vs Common-Mode Input Voltage
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD1 (V)
5
5.25 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D013
D014
–55°C ≤TA < –40°C for AMC1300B only
图7-14. Input Bias Current vs Temperature
图7-13. Input Bias Current vs High-Side Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
-0.1
-0.2
-0.4
-0.6
-0.8
-1
-0.2
AMC1300 vs VDD1
AMC1300 vs VDD2
AMC1300B vs VDD1
AMC1300B vs VDD1
-0.3
Device 1
Device 2
Device 3
-0.4
-0.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D015
D016
AMC1300
图7-16. Gain Error vs Temperature
图7-15. Gain Error vs Supply Voltage
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.3
0.2
0.1
0
5
0
Device 1
Device 2
Device 3
-5
-10
-15
-20
-25
-30
-35
-40
-0.1
-0.2
-0.3
AMC1300B
AMC1300
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
1
10
100
1000
fIN (kHz)
D017
D020
AMC1300B
图7-17. Gain Error vs Temperature
图7-18. Normalized Gain vs Input Frequency
0°
5
4.5
4
VOUTN
VOUTP
-45°
-90°
3.5
3
-135°
-180°
-225°
-270°
-315°
-360°
2.5
2
1.5
1
AMC1300B
AMC1300
0.5
0
1
10
100
1000
-350
-250
-150
-50
50
150
Differential Input Voltage (mV)
250
350
fIN (kHz)
D021
D022
图7-19. Output Phase vs Input Frequency
图7-20. Output Voltage vs Input Voltage
0.03
0.025
0.02
0.03
vs VDD1
vs VDD2
0.02
0.01
0
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-0.01
-0.02
-0.03
-250 -200 -150 -100 -50
0
Differential Input Voltage (mV)
50 100 150 200 250
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D023
D024
图7-21. Nonlinearity vs Input Voltage
图7-22. Nonlinearity vs Supply Voltage
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.03
0.02
0.01
0
-70
Device 1
Device 2
Device 3
vs VDD1
vs VDD2
-75
-80
-85
-0.01
-0.02
-0.03
-90
-95
-100
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D025
D026
–55°C ≤TA < –40°C for AMC1300B only
图7-23. Nonlinearity vs Temperature
3 V ≤VDD1 < 4.5 V for AMC1300B only
图7-24. Total Harmonic Distortion vs Supply Voltage
-70
-75
10000
1000
100
10
-80
-85
-90
Device 1
Device 2
Device 3
-95
-100
0.1
1
10
Frequency (kHz)
100
1000
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D028
D027
–55°C ≤TA < –40°C for AMC1300B only
图7-25. Total Harmonic Distortion vs Temperature
图7-26. Input-Referred Noise Density vs Frequency
80
80
vs VDD1
vs VDD2
77.5
75
75
70
65
60
55
50
45
40
72.5
70
67.5
65
62.5
60
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
0
50
100
150
|VINP - VINN| (mV)
200
250
300
D030
D029
3 V ≤VDD1 < 4.5 V for AMC1300B only
图7-28. Signal-to-Noise Ratio vs Supply Voltage
图7-27. Signal-to-Noise Ratio vs Input Voltage
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
80
77.5
75
0
-20
-40
72.5
70
-60
67.5
65
-80
Device 1
Device 2
Device 3
-100
62.5
60
vs VDD2
vs VDD1
-120
0.001
0.01
0.1
1
10
Ripple Frequency (kHz)
100
1000
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D032
D031
–55°C ≤TA < –40°C for AMC1300B only
图7-30. Power-Supply Rejection Ratio vs Ripple Frequency
图7-29. Signal-to-Noise Ratio vs Temperature
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.39
1.39
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D033
D034
–55°C ≤TA < –40°C for AMC1300B only
图7-31. Output Common-Mode Voltage vs Low-Side Supply
图7-32. Output Common-Mode Voltage vs Temperature
Voltage
340
340
AMC1300B
AMC1300
AMC1300B
AMC1300
320
320
300
280
260
240
220
200
300
280
260
240
220
200
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D035
D036
图7-33. Output Bandwidth vs Low-Side Supply Voltage
图7-34. Output Bandwidth vs Temperature
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
8.5
8
8.5
8
7.5
7
7.5
7
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4
4.5
4
IDD1 vs VDD1
IDD2 vs VDD2
IDD1
IDD2
3.5
3.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D037
D038
3 V ≤VDD1 < 4.5 V for AMC1300B only
图7-35. Supply Current vs Supply Voltage
–55°C ≤TA < –40°C for AMC1300B only
图7-36. Supply Current vs Temperature
4
3.5
3
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D039
D040
–55°C ≤TA < –40°C for AMC1300B only
图7-38. Output Rise and Fall Time vs Temperature
图7-37. Output Rise and Fall Time vs Low-Side Supply
3.8
3.4
3
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
2.6
2.2
1.8
1.4
1
1
50% - 90%
50% - 50%
50% - 10%
0.6
0.2
0.6
0.2
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
D042
D041
AMC1300B
AMC1300
图7-40. VIN to VOUT Signal Delay vs Low-Side Supply Voltage
图7-39. VIN to VOUT Signal Delay vs Low-Side Supply Voltage
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7.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted)
3.8
3.4
3
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
2.6
2.2
1.8
1.4
1
50% - 90%
50% - 50%
50% - 10%
0.6
0.6
0.2
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D043
D044
AMC1300
AMC1300B
图7-42. VIN to VOUT Signal Delay vs Temperature
图7-41. VIN to VOUT Signal Delay vs Temperature
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8 Detailed Description
8.1 Overview
The AMC1300 is a fully differential, precision, isolated amplifier. The input stage of the device consists of a fully
differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog
input signal into a digital bitstream that is transferred across the isolation barrier that separates the high-side
from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter that
outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1300
to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability
and common-mode transient immunity.
8.2 Functional Block Diagram
VDD1
VDD2
OUTP
OUTN
GND2
AMC1300B
Diagnostics
Analog Filter
INP
ΔΣ Modulator
INN
GND1
8.3 Feature Description
8.3.1 Analog Input
The differential amplifier input stage of the AMC1300 feeds a second-order, switched-capacitor, feed-forward
ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input
impedance of RIND. The modulator converts the analog input signal into a bitstream that is transferred across the
isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals INP and INN. First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the
absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity
and parametric performance of the device are ensured only when the analog input voltage remains within the
linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
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8.3.2 Isolation Channel Signal Transmission
The AMC1300 uses an on-off keying (OOK) modulation scheme, as shown in 图 8-1, to transmit the modulator
output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the Functional Block
Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to represent a
digital one and does not send a signal to represent a digital zero. The nominal frequency of the carrier used
inside the AMC1300 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the
input to the fourth-order analog filter. The AMC1300 transmission channel is optimized to achieve the highest
level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-
frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图8-1. OOK-Based Modulation Scheme
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8.3.3 Analog Output
The AMC1300 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input
voltages (VINP – VINN) in the range from –250 mV to +250 mV, the device provides a linear response with a
nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage (VOUTP
–VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage
VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than
250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with reduced
linearity performance. The outputs saturate at a differential output voltage of VCLIPout, as shown in 图 8-2, if the
differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VOUTN
VCLIPout
VOUTP
VFAILSAFE
VCMout
320 mV
250 mV
320 mV
250 mV
0
Differential Input Voltage (VINP – VINN
)
图8-2. Output Behavior of the AMC1300
The AMC1300 offers a fail-safe feature that simplifies diagnostics on system level. 图 8-2 shows the fail-safe
potential that is a negative differential output voltage that does not occur under normal operating conditions. The
fail-safe output is active in two cases:
• When the high-side supply is missing or below the VDD1UV threshold
• When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the common-mode
overvoltage detection level VCMov
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for fail-
safe detection on system level.
8.4 Device Functional Modes
The AMC1300 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The low analog input voltage range, excellent accuracy, and low temperature drift make the AMC1300 a high-
performance solution for industrial applications where shunt-based current sensing in the presence of high
common-mode voltage levels is required.
9.2 Typical Application
The AMC1300 is ideally suited for shunt-based current sensing applications where accurate current monitoring is
required in the presence of high common-mode voltages.
图 9-1 shows the AMC1300 in a typical application. The load current flowing through an external shunt resistor
RSHUNT produces a voltage drop that is sensed by the AMC1300. The AMC1300 digitizes the analog input
signal on the high-side, transfers the data across the isolation barrier to the low-side, reconstructs the analog
signal, and presents that signal as a differential voltage on the output pins.
The differential input, differential output, and the high common-mode transient immunity (CMTI) of the AMC1300
ensure reliable and accurate operation even in high-noise environments.
Floating Gate
Driver Supply
+ DC Link
Low-side supply
(3.3 V or 5 V)
1 uF 100 nF
1 uF 100 nF
AMC1300B
VDD1
VDD2
OUTP
OUTN
GND2
10
10
10 nF
INP
RSHUNT
ADC
INN
Load
GND1
– DC Link
图9-1. Using the AMC1300 for Current Sensing in a Typical Application
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9.2.1 Design Requirements
表9-1 lists the parameters for this typical application.
表9-1. Design Requirements
PARAMETER
High-side supply voltage
VALUE
3.3 V or 5 V
Low-side supply voltage
3.3 V or 5 V
Voltage drop across RSHUNT for a linear response
Signal delay (50% VIN to 90% OUTP, OUTN)
± 250 mV (maximum)
3 µs (maximum)
9.2.2 Detailed Design Procedure
In 图 9-1, the high-side power supply (VDD1) for the AMC1300 is derived from the floating power supply of the
upper gate driver.
The floating ground reference (GND1) is derived from the end of the shunt resistor that is connected to the
negative input of the AMC1300 (INN). If a four-pin shunt is used, the inputs of the AMC1300 are connected to
the inner leads and GND1 is connected to the outer lead on the INN-side of the shunt. To minimize offset and
improve accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor
rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more details.
9.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range for a linear response: |VSHUNT| ≤|VFSR
|
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤|VClipping
|
9.2.2.2 Input Filter Design
TI recommends placing an RC filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (20
MHz) of the ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
• The impedances measured from the analog inputs are equal
For most applications, the structure shown in 图9-2 achieves excellent performance.
AMC1300B
VDD1
VDD2
OUTP
OUTN
GND2
10
10
10 nF
INP
INN
GND1
图9-2. Differential Input Filter
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9.2.2.3 Differential-to-Single-Ended Output Conversion
图 9-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using single-
ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩand C1 = C2 = 330 pF yields good performance.
C1
AMC1300B
R2
VDD1
VDD2
OUTP
OUTN
GND2
R1
R3
INP
–
+
ADC
To MCU
INN
TLV6001
GND1
C2
R4
VREF
图9-3. Connecting the AMC1300 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the
18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
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9.2.3 Application Curves
One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the
switching devices and passive components from damage. To power off the system quickly in the event of an
overcurrent condition, a low delay caused by the isolated amplifier is required. 图 9-4 shows the typical full-scale
step response of the AMC1300.
VOUTP
VOUTN
VIN
图9-4. Step Response of the AMC1300
9.3 What To Do and What Not To Do
Do not leave the inputs of the AMC1300 unconnected (floating) when the device is powered up. If the device
inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the operating
common-mode input voltage and the device outputs the fail-safe voltage as described in the Analog Output
section.
Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current
path between INN and GND1 is required to define the input common-mode voltage. Do not exceed the input
common-mode range specified in the Recommended Operating Conditions table. For best accuracy, route the
ground connection as a separate trace that connects directly to the shunt resistor rather than shorting GND1 to
INN directly at the input to the device. See the Layout section for more details.
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10 Power Supply Recommendations
The AMC1300 does not require any specific power up sequencing. The high-side power-supply (VDD1) is
decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-µF capacitor (C2). The low-side
power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-µF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.
The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected
to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in 图 10-1) to
make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt is
used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the INN-
side of the shunt.
INP
VDD1
VDD2
C2 1 µF
C1 100 nF
R2 10
C4 1 µF
AMC1300B
I
C3 100 nF
VDD1
VDD2
OUTP
OUTN
GND2
INP
to RC filter / ADC
to RC filter / ADC
C5
10 nF
R1 10
INN
GND1
图10-1. Decoupling of the AMC1300
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
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11 Layout
11.1 Layout Guidelines
图 11-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1300 supply pins) and placement of the other components required by the device. For best
performance, place the shunt resistor close to the INP and INN inputs of the AMC1300 and keep the layout of
both connections symmetrical.
11.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C2
C1
C4
C3
INP
R2
R1
to RC filter / ADC
to RC filter / ADC
OUTP
OUTN
AMC1300B
INN
GND2
GND1
Top Metal
Inner or Bottom Layer Metal
Via
图11-1. Recommended Layout of the AMC1300
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1300BDWV
AMC1300BDWVR
AMC1300DWV
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DWV
DWV
DWV
DWV
8
8
8
8
64
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-40 to 125
-40 to 125
AMC1300B
1000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
AMC1300B
AMC1300
AMC1300
AMC1300DWVR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1300BDWVR
AMC1300DWVR
SOIC
SOIC
DWV
DWV
8
8
1000
1000
330.0
330.0
16.4
16.4
12.15
12.15
6.2
6.2
3.05
3.05
16.0
16.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
AMC1300BDWVR
AMC1300DWVR
SOIC
SOIC
DWV
DWV
8
8
1000
1000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
AMC1300BDWV
AMC1300DWV
DWV
DWV
SOIC
SOIC
8
8
64
64
505.46
505.46
13.94
13.94
4826
4826
6.6
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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