AMC1302 [TI]

±50mV 输入、精密电流检测增强型隔离式放大器;


型号：	AMC1302
厂家：	TEXAS INSTRUMENTS
描述：	±50mV 输入、精密电流检测增强型隔离式放大器放大器
文件：	总35页 (文件大小：2291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMC1302

ZHCSIF3D –JUNE 2018 –REVISED JUNE 2021

AMC1302 精密、±50mV 输入、增强型隔离放大器

1 特性

3 说明

• ±50mV 输入电压范围，针对基于分流器的电流测量

进行了优化

• 固定增益：41

• 低直流误差：

AMC1302 是一款隔离式精密放大器，此放大器的输出

与输入电路由抗电磁干扰性能极强的隔离层隔开。该隔

离栅经认证可提供高达 5kV_RMS的增强型电隔离，符合

VDE V 0884-11 和 UL1577 标准，并且可支持最高

1.5kV_RMS的工作电压。

– 失调电压误差：±50µV（最大值）

– 温漂：±0.8µV/°C（最大值）

– 增益误差：±0.2%（最大值）

– 增益漂移：±35ppm/°C（最大值）

– 非线性度：0.03%（最大值）

• 高侧和低侧以3.3V 或5V 电压运行

• 失效防护输出

• 高CMTI：100kV/µs（最小值）

• 低EMI，符合CISPR-11 和CISPR-25 标准

• 安全相关认证：

该隔离栅可将系统中以不同共模电压电平运行的各器件

隔开，并保护电压较低的器件免受高电压冲击。

AMC1302 的输入针对直接连接低阻抗分流电阻器或其

他具有低信号电平的低阻抗电压源的情况进行了优化。

出色的直流精度和低温漂支持在 –40°C 至 +125°C 的

工业级工作温度范围内，在 PFC 级、直流/直流转换

器、交流电机和伺服驱动器中进行精确的电流控制。

集成的无分流器和无高侧电源检测功能可简化系统级设

计和诊断。

– 7071-V_PK增强型隔离，符合DIN VDE V

0884-11：2017-01

器件信息⁽¹⁾

– 符合UL1577 标准且长达1 分钟的5000V_RMS

隔离

封装尺寸（标称值）

器件型号

AMC1302

封装

SOIC (8)

5.85mm × 7.50mm

• 可在工业级工作温度范围内正常工作：–40°C 至

+125°C

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 可用于以下应用的隔离式电流感应：

– 保护继电器

– 电机驱动器

– 电源

– 光电逆变器

High-side supply

(3.3 V or 5 V)

Low-side supply

(3.3 V or 5 V)

AMC1302

VDD1

INP

VDD2

OUTP

+50 mV

0 V

V^CMout

±2.05 V

ADC

–

INN

OUTN

GND2

GND1

典型应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS812

AMC1302

ZHCSIF3D –JUNE 2018 –REVISED JUNE 2021

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Table of Contents

7.1 Overview...................................................................17

7.2 Functional Block Diagram.........................................17

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................19

8 Application and Implementation..................................20

8.1 Application Information............................................. 20

8.2 Typical Application.................................................... 20

8.3 What to Do and What Not to Do............................... 22

9 Power Supply Recommendations................................23

10 Layout...........................................................................24

10.1 Layout Guidelines................................................... 24

10.2 Layout Example...................................................... 24

11 Device and Documentation Support..........................25

11.1 Documentation Support.......................................... 25

11.2 Trademarks............................................................. 25

11.3 Electrostatic Discharge Caution..............................25

11.4 术语表..................................................................... 25

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................4

6.4 Thermal Information ...................................................5

6.5 Power Ratings ............................................................5

6.6 Insulation Specification .............................................. 6

6.7 Safety-Related Certifications ..................................... 7

6.8 Safety Limiting Values ................................................7

6.9 Electrical Characteristics ............................................8

6.10 Switching Characteristics .........................................9

6.11 Timing Diagram.........................................................9

6.12 Insulation Characteristics Curves........................... 10

6.13 Typical Characteristics............................................ 11

7 Detailed Description......................................................17

Information.................................................................... 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (October 2019) to Revision D (June 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式........................................................................................1

• Changed C_IOfrom ~1 pF to ~1.5 pF...................................................................................................................6

• Changed V_OSfrom –100 µV / ±10 µV / 100 µV to –50 µV / ±2.5 µV / 50 µV (min / typ / max ).......................8

• Changed E_Gfrom –0.3% / ±0.05% / 0.3% to –0.2% / ±0.04% / 0.2% (min / typ / max) ................................ 8

• Changed TCE_Gfrom –50 ppm/℃/ ±15 ppm/℃/ 50 ppm/℃to –35 ppm/℃/ ±3 ppm/℃/ 35 ppm/℃(min /

typ / max) ...........................................................................................................................................................8

• Changed V_Failsafefrom –2.6 V / –2.5 V (typ / max) to –2.63 V / –2.57 V / –2.53 V (min / typ / max).......... 8

• Changed CMTI from 55 kV/µs / 80 kV/µs to 100 kV/µs / 150 kV/µs (min / typ) .................................................8

• Changed VDD1_PORfrom 1.75 V / 2.15 V / 2.7 V to 2.4 V / 2.6 V / 2.8 V (min / typ / max)................................. 8

• Changed Rise, Fall, and Delay Time Waveforms image.................................................................................... 9

Changes from Revision B (November 2018) to Revision C (October 2019)

Page

• 将安全相关认证特性项目符号中的VDE 认证从“DIN V VDE V 0884-11 (VDE V 0884-11)”更改为DIN VDE

V 0884-11 ...........................................................................................................................................................1

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5 Pin Configuration and Functions

VDD1

INP

VDD2

OUTP

OUTN

GND2

INN

GND1

Not to scale

图5-1. DWV Package, 8-Pin SOIC, Top View

表5-1. Pin Functions

NAME

TYPE

DESCRIPTION

NO.

VDD1

INP

High-side power

Analog input

High-side power supply.⁽¹⁾

Noninverting analog input. Either INP or INN must have a DC current path to GND1

to define the common-mode input voltage.⁽²⁾

Inverting analog input. Either INP or INN must have a DC current path to GND1 to

define the common-mode input voltage.⁽²⁾

INN

Analog input

GND1

GND2

OUTN

OUTP

VDD2

High-side ground

Low-side ground

Analog output

High-side analog ground.

Low-side analog ground.

Inverting analog output.

Noninverting analog output.

Low-side power supply.⁽¹⁾

Analog output

Low-side power

(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.

(2) See the Layout section for details.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

High-side VDD1 to GND1

Power-supply voltage

6.5

Low-side VDD2 to GND2

–0.3

Analog input voltage

Output voltage

Input current

INP, INN

VDD1 + 0.5

VDD2 + 0.5

GND1 –6

GND2 –0.5

–10

OUTP, OUTN

Continuous, any pin except power-supply pins

Junction, T_J

Storage, T_stg

150

Temperature

°C

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

Charged device model (CDM), per JESD22-C101 ⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

High-side power supply

Low-side power supply

ANALOG INPUT

V_ClippingDifferential input voltage before clipping output

VDD1 to GND1

VDD2 to GND2

5.5

3.3

±64

V_IN= V_INP–V_INN

V_FSR

V_CM

Specified linear differential full-scale voltage

Operating common-mode input voltage

–50

VDD1 –

(V_INP+ V_INN) / 2 to GND1

–0.032

2.2

TEMPERATURE RANGE

T_ASpecified ambient temperature

125

°C

–55

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6.4 Thermal Information

AMC1302

THERMAL METRIC⁽¹⁾

DWV (SOIC)

8 PINS

85.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

26.8

43.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.8

ψ_JT

41.2

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

VALUE

UNIT

P_D

Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5 V

VDD1 = 3.6 V

Maximum power dissipation (high-side)

VDD1 = 5.5 V

P_D1

VDD2 = 3.6 V

Maximum power dissipation (low-side)

VDD2 = 5.5 V

P_D2

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UNIT

6.6 Insulation Specification

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

GENERAL

CLR

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air

≥8.5

Shortest terminal-to-terminal distance across the package

surface

CPG

External creepage⁽¹⁾

Minimum internal gap (internal clearance) of the double

isolation (2 x 0.0105 mm)

DTI

CTI

Distance through the insulation

≥0.021

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥600

I -IV

I-III

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage category

DIN V VDE 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage

2121

V_PK

AC voltage (sine wave)

1500

2121

7071

8485

V_RMS

V_DC

V_PK

Maximum isolation working

voltage

V_IOWM

DC voltage

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= V_IOTM, t = 1 s (100% production test)

Maximum transient isolation

voltage

V_IOTM

V_PK

Maximum surge isolation

voltage⁽¹⁾

Test method per IEC 60065, 1.2/50 µs waveform, V_TEST= 1.6 ×

V_IOSM= 12800 V_PK(qualification)

V_IOSM

8000

≤5

V_PK

Method a: After I/O safety test subgroup 2/3, V_ini= V_IOTM, t_ini

60 s; V_pd(m)= 1.2 × V_IORM= 2545 V_PK, t_m= 10 s

Method a: After environmental tests subgroup 1, V_ini= V_IOTM

q_pd

Apparent charge⁽³⁾

t_ini= 60 s; V_pd(m)= 1.6 × V_IORM= 3394 V_PK, t_m= 10 s

Method b1: At routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s; V_pd(m)= 1.875

× V_IORM= 3977 V_PK, t_m= 1 s

≤5

Barrier capacitance, input to

output⁽⁴⁾

C_IO

R_IO

~1.5

V_IO= 0.4 × sin (2 πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Insulation resistance, input to

output⁽⁴⁾

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/21

UL 1577

V_TEST= V_ISO= 5000 V_RMS, t = 60 s (qualification), V_TEST= 1.2

× V_ISO= 6000 V_RMS, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Apparent charge is electrical discharge caused by a partial discharge (pd).

(4) All pins on each side of the barrier tied together creating a two-pin device.

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6.7 Safety-Related Certifications

VDE

Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,

DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and

DIN EN 60065 (VDE 0860): 2005-11

Recognized under 1577 component recognition and

CSA component acceptance NO 5 programs

Reinforced insulation

Single protection

Certificate number: 40040142

Certificate number: E181974

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-

heat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

_θJA= 85.4°C/W, VDDx = 5.5 V,

I_S

Safety input, output, or supply current

266

T_J= 150°C, T_A= 25°C

_θJA= 85.4°C/W, VDDx = 3.6 V,

T_J= 150°C, T_A= 25°C

_θJA= 85.4°C/W, T_J= 150°C, T_A= 25°C

Safety input, output, or supply current

407

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1464

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_Sand P_S. These

limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum junction temperature.

P_S= I_S× VDD_max, where VDD_maxis the maximum supply voltage for high-side and low-side.

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6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A= –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V_,

INP = –50 mV to + 50 mV, and INN = GND1; typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG INPUT

Common-mode overvoltage

detection level

V_CMov

(V_INP+ V_INN) / 2 to GND1

VDD1 –2

Hysteresis of common-mode

overvoltage detection level

V_OS

Input offset voltage^{(1) (2)}

Input offset drift^{(1) (2) (3)}

T_A= 25°C, V_INP= V_INN= GND1

±2.5

µV

–50

TCV_OS

±0.15

0.8 µV/°C

–0.8

f_IN= 0 Hz, V_{CM min}≤V_CM≤V_{VCM max}

f_IN= 10 kHz, V_{CM min}≤V_CM≤V_{CM max}

INN = GND1, f_IN= 300 kHz

f_IN= 300 kHz

–100

–98

CMRR

Common-mode rejection ratio

C_IN

Single-ended input capacitance

Differential input capacitance

Single-ended input resistance

Differential input resistance

Input bias current

C_IND

R_IN

INN = GND1

4.75

4.9

kΩ

R_IND

I_IB

INP = INN = GND1; I_IB= (I_IBP+ I_IBN) / 2

nA/°C

–48.5

–36

±1.5

±10

–28.5

TCI_IB

I_IO

Input bias current drift

Input offset current

I_IO= I_IBP–I_IBN

ANALOG OUTPUT

Nominal gain

±0.04%

±3

E_G

Gain error⁽¹⁾

T_A= 25°C

0.2%

–0.2%

–35

TCE_G

Gain error drift^{(1) (4)}

Nonlinearity⁽¹⁾

35 ppm/°C

0.03%

±0.01%

–0.03%

Nonlinearity drift

Total harmonic distortion

ppm/°C

THD

SNR

f_IN= 10 kHz

–85

INP = INN = GND1, f_IN= 0 Hz,

BW = 100 kHz brickwall filter

Output noise

260

µV_RMS

f_IN= 1 kHz, BW = 10 kHz

f_IN= 10 kHz, BW = 100 kHz

PSRR vs VDD1, at DC

Signal-to-noise ratio

–113

PSRR vs VDD1,

100-mV and 10-kHz ripple

–108

–116

–87

PSRR

Power-supply rejection ratio⁽²⁾

PSRR vs VDD2, at DC

PSRR vs VDD2,

100-mV and 10-kHz ripple

V_CMout

Common-mode output voltage

1.39

1.44

1.49

2.52

V_OUT= (V_OUTP–V_OUTN);

|V_IN| = |V_INP–V_INN| > |V_Clipping

V_CLIPout

Clipping differential output voltage

±2.49

–2.52

V_Failsafe

Failsafe differential output voltage

Output bandwidth

kHz

_CM≥V_CMov, or VDD1 missing

–2.63

–2.57

280

–2.53

220

R_OUT

Output resistance

On OUTP or OUTN

< 0.2

On OUTP or OUTN, sourcing or sinking,

INN = INP = GND1, outputs shorted to

either GND2 or VDD2

Output short-circuit current

±14

150

CMTI

Common-mode transient immunity

100

kV/µs

|GND1 –GND2| = 1 kV

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6.9 Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V_,

INP = –50 mV to + 50 mV, and INN = GND1; typical specifications are at T_A= 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY

VDD1 power-on-reset threshold

voltage

VDD1_POR

IDD1

VDD1 falling

2.4

2.6

2.8

6.2

7.2

5.3

5.9

8.5

9.8

7.2

8.1

3.0 V ≤VDD1 ≤3.6 V

4.5 V ≤VDD1 ≤5.5 V

3.0 V ≤VDD2 ≤3.6 V

4.5 V ≤VDD2 ≤5.5 V

High-side supply current

Low-side supply current

IDD2

(1) The typical value includes one standard deviation ("sigma") at nominal operating conditions.

(2) This parameter is input referred.

(3) Offset error temperature drift is calculated using the box method, as described by the following equation:

TCV_OS= (Value_MAX- Value_MIN) / TempRange

(4) Gain error temperature drift is calculated using the box method, as described by the following equation:

TCE_G(ppm) = (Value_MAX- Value_MIN) / (Value_(T=25℃)x TempRange) x 10⁶

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µs

t_r

t_f

Output signal rise time

1.5

Output signal fall time

µs

unfiltered output

1.5

2.1

µs

V_INxto V_OUTxsignal delay (50% –10%)

V_INxto V_OUTxsignal delay (50% –50%)

V_INxto V_OUTxsignal delay (50% –90%)

unfiltered output

1.6

2.5

µs

VDD1 step to 3.0 V with VDD2 ≥3.0 V,

to OUTP and OUTN valid, 0.1% settling

t_AS

Analog settling time

500

µs

6.11 Timing Diagram

50 mV

INP - INN

– 50 mV

t_f

t_r

OUTN

OUTP

V_CMout

50% - 10%

50% - 50%

50% - 90%

图6-1. Rise, Fall, and Delay Time Waveforms

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6.12 Insulation Characteristics Curves

450

1600

1400

1200

1000

800

600

400

200

VDD1 = VDD2 = 3.6 V

VDD1 = VDD2 = 5.5 V

400

350

300

250

200

150

100

T_A(°C)

100

125

150

T_A(°C)

100

125

150

D002

D001

图6-3. Thermal Derating Curve for Safety-Limiting Power per

图6-2. Thermal Derating Curve for Safety-Limiting Current per

VDE

T_Aup to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 V_RMS, operating lifetime = 135 years

图6-4. Reinforced Isolation Capacitor Lifetime Projection

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6.13 Typical Characteristics

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

3.8

3.4

3.3

3.25

3.2

3.15

3.1

2.6

2.2

1.8

1.4

3.05

2.95

2.9

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

3.25 3.5 3.75

4.25 4.5 4.75

VDD1 (V)

5.25 5.5

D004

D003

图6-6. Common-Mode Overvoltage Detection Level vs

图6-5. Common-Mode Overvoltage Detection Level vs High-

Temperature

Side Supply Voltage

100

vs VDD1

vs VDD2

Device 1

Device 2

Device 3

-25

-50

-75

-100

-25

-50

-75

-100

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D007

D009

图6-7. Input Offset Voltage vs Supply Voltage

图6-8. Input Offset Voltage vs Temperature

-20

-75

-80

-85

-40

-90

-60

-95

-100

-105

-110

-115

-80

-100

-120

0.001

0.01

0.1

f_IN(kHz)

100

1000

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D012

D013

图6-9. Common-Mode Rejection Ratio vs Input Frequency

图6-10. Common-Mode Rejection Ratio vs Temperature

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6.13 Typical Characteristics (continued)

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

-27

-29

-31

-33

-35

-37

-39

-41

-43

-45

-20

-40

-60

-80

-0.5

0.5

1.5

V_CM(V)

2.5

3.5

3.25 3.5 3.75

4.25 4.5 4.75

VDD1 (V)

5.25 5.5

D014

D015

图6-11. Input Bias Current vs Common-Mode Input Voltage

图6-12. Input Bias Current vs High-Side Supply Voltage

-27

-29

-31

-33

-35

-37

-39

-41

-43

-45

0.3

0.2

0.1

-0.1

-0.2

vs VDD1

vs VDD2

-0.3

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5 5.25 5.5

D016

D019

图6-13. Input Bias Current vs Temperature

图6-14. Gain Error vs Supply Voltage

0.3

0.2

0.1

-5

-10

-15

-20

-25

-30

-35

-40

-0.1

-0.2

-0.3

Device 1

Device 2

Device 3

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

0.01

0.1

100

1000

f_IN(kHz)

D020

D023

图6-15. Gain Error vs Temperature

图6-16. Normalized Gain vs Input Frequency

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6.13 Typical Characteristics (continued)

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

0°

-45°

4.5

V_OUTN

V_OUTP

-90°

3.5

-135°

-180°

-225°

-270°

-315°

-360°

2.5

1.5

0.5

0.01

0.1

100

1000

-70 -60 -50 -40 -30 -20 -10

Differential Input Voltage (mV)

10 20 30 40 50 60 70

f_IN(kHz)

D024

D025

图6-17. Output Phase vs Input Frequency

图6-18. Output Voltage vs Input Voltage

0.03

0.02

0.01

0.03

0.02

0.01

vs VDD1

vs VDD2

-0.01

-0.02

-0.03

-0.01

-0.02

-0.03

-50 -40 -30 -20 -10

Differential Input Voltage (mV)

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5.25 5.5

D026

D027

图6-19. Nonlinearity vs Input Voltage

图6-20. Nonlinearity vs Supply Voltage

0.03

0.02

0.01

-70

-75

vs VDD1

vs VDD2

-80

-85

-0.01

-0.02

-0.03

-90

Device 1

Device 2

Device 3

-95

-100

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5.25 5.5

D028

D029

图6-21. Nonlinearity vs Temperature

图6-22. Total Harmonic Distortion vs Supply Voltage

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6.13 Typical Characteristics (continued)

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

-70

-75

-80

-85

-90

Device 1

Device 2

Device 3

-95

-100

0.1

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

Frequency (kHz)

100

1000

D030

D031

图6-23. Total Harmonic Distortion vs Temperature

图6-24. Output Noise Density vs Frequency

vs VDD1

vs VDD2

10 15 20 25 30 35 40 45 50 55

|VINP - VINN| (mV)

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5.25 5.5

D032

D033

图6-25. Signal-to-Noise Ratio vs Input Voltage

图6-26. Signal-to-Noise Ratio vs Supply Voltage

vs VDD2

vs VDD1

-20

-40

-60

-80

-100

-120

Device 1

Device 2

Device 3

0.001

0.01

0.1

Ripple Frequency (kHz)

100

1000

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D035

D034

图6-28. Power-Supply Rejection Ratio vs Ripple Frequency

图6-27. Signal-to-Noise Ratio vs Temperature

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6.13 Typical Characteristics (continued)

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.39

3.25 3.5 3.75

4.25 4.5 4.75

VDD2 (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D036

D037

图6-29. Output Common-Mode Voltage vs Low-Side Supply

图6-30. Output Common-Mode Voltage vs Temperature

Voltage

320

310

300

290

280

270

260

250

240

320

310

300

290

280

270

260

250

240

3.25 3.5 3.75

4.25 4.5 4.75

VDD2 (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D038

D039

图6-31. Output Bandwidth vs Low-Side Supply Voltage

图6-32. Output Bandwidth vs Temperature

8.5

7.5

6.5

5.5

IDD1 at VDD1 = 5 V

IDD1 at VDD1 = 3.3 V

IDD2 at VDD2 = 5 V

IDD2 at VDD2 = 3.3 V

4.5

IDD1 vs VDD1

IDD2 vs VDD2

3.5

3.25 3.5 3.75

4.25 4.5 4.75

VDDx (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D040

D041

图6-33. Supply Current vs Supply Voltage

图6-34. Supply Current vs Temperature

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6.13 Typical Characteristics (continued)

at T_A= 25°C, VDD1 = 5 V, VDD2 = 3.3 V, INP = –50 mV to 50 mV, INN = GND1, and f_IN= 10 kHz (unless otherwise noted)

3.8

3.4

3.8

3.4

2.6

2.2

1.8

1.4

2.6

2.2

1.8

1.4

0.6

0.2

0.6

0.2

3.25 3.5 3.75

4.25 4.5 4.75

VDD2 (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D042

D043

图6-35. Output Rise and Fall Time vs Low-Side Supply Voltage

图6-36. Output Rise and Fall Time vs Temperature

3.8

50% - 90%

50% - 50%

50% - 10%

50% - 90%

50% - 50%

50% - 10%

3.4

2.6

2.2

1.8

1.4

2.6

2.2

1.8

1.4

0.6

0.2

0.6

0.2

3.25 3.5 3.75

4.25 4.5 4.75

VDD2 (V)

5.25 5.5

-55 -40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D044

D045

图6-37. V_INto V_OUTSignal Delay vs Low-Side Supply Voltage

图6-38. V_INto V_OUTSignal Delay vs Temperature

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7 Detailed Description

7.1 Overview

The AMC1302 is a fully differential, precision, isolated amplifier. The input stage of the device consists of a fully

differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog

input signal into a digital bitstream that is transferred across the isolation barrier that separates the high-side

from the low-side. On the low-side, the received bitstream is processed by a fourth-order analog filter that

outputs a differential signal at the OUTP and OUTN pins that is proportional to the input signal.

The SiO₂-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the

ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1302

to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability

and common-mode transient immunity.

7.2 Functional Block Diagram

VDD1

VDD2

OUTP

OUTN

GND2

AMC1302

Diagnostics

Analog Filter

INP

ΔΣ Modulator

INN

GND1

7.3 Feature Description

7.3.1 Analog Input

The differential amplifier input stage of the AMC1302 feeds a second-order, switched-capacitor, feed-forward

ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input

impedance of R_IND. The modulator converts the analog input signal into a bitstream that is transferred across the

isolation barrier, as described in the Isolation Channel Signal Transmission section.

There are two restrictions on the analog input signals INP and INN. First, if the input voltages V_INPor V_INN

exceed the range specified in the Absolute Maximum Ratings table, the input currents must be limited to the

absolute maximum value, because the electrostatic discharge (ESD) protection turns on. In addition, the linearity

and parametric performance of the device are ensured only when the analog input voltage remains within the

linear full-scale range (V_FSR) and within the common-mode input voltage range (V_CM) as specified in the

Recommended Operating Conditions table.

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7.3.2 Isolation Channel Signal Transmission

The AMC1302 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the modulator

output bitstream across the SiO₂-based isolation barrier. The transmit driver (TX) shown in the Functional Block

Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to represent a

digital one and does not send a signal to represent a digital zero. The nominal frequency of the carrier used

inside the AMC1302 is 480 MHz.

The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the

input to the 4th-order analog filter. The AMC1302 transmission channel is optimized to achieve the highest level

of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-

frequency carrier and RX/TX buffer switching.

Internal Clock

Modulator Bitstream

on High-side

Signal Across Isolation Barrier

Recovered Sigal

on Low-side

图7-1. OOK-Based Modulation Scheme

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7.3.3 Analog Output

The AMC1302 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input

voltages (V_INP– V_INN) in the range from –50 mV to 50 mV, the device provides a linear response with a

nominal gain of 41. For example, for a differential input voltage of 50 mV, the differential output voltage (V_OUTP

–V_OUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage

V_CMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than 50

mV but less than 64 mV, the differential output voltage continues to increase in magnitude but with reduced

linearity performance. The outputs saturate at a differential output voltage of V_CLIPout, as shown in 图 7-2, if the

differential input voltage exceeds the V_Clippingvalue.

Maximum input range before clipping (V_Clipping

)

Linear input range (V_FSR

)

V_OUTN

V_CLIPout

V_OUTP

V_FAILSAFE

V_CMout

64 mV

50 mV

64 mV

50 mV

Differential Input Voltage (V_INP– V_INN

)

图7-2. Output Behavior of the AMC1302

The AMC1302 offers a fail-safe feature that simplifies diagnostics on system level. 图 7-2 shows the fail-safe

mode, in which the AMC1302 outputs a negative differential output voltage that does not occur under normal

operating conditions. The fail-safe output is active in two cases:

• When the high-side supply is missing or below the VDD1_UVthreshold

• When the common-mode input voltage, that is V_CM= (V_INP+ V_INN) / 2, exceeds the common-mode

overvoltage detection level V_CMov

Use the maximum V_FAILSAFEvoltage specified in the Electrical Characteristics table as a reference value for fail-

safe detection on system level.

7.4 Device Functional Modes

The AMC1302 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the

Recommended Operating Conditions table.

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8 Application and Implementation

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The low analog input voltage range, excellent accuracy, and low temperature drift make the a high-performance

solution for industrial applications where shunt-based current sensing in the presence of high common-mode

voltage levels is required.

8.2 Typical Application

The AMC1302 is ideally suited for shunt-based current sensing applications where accurate current monitoring is

required in the presence of high common-mode voltages.

图 8-1 shows the AMC1302 in a typical application. The load current flowing through an external shunt resistor

RSHUNT produces a voltage drop that is sensed by the AMC1302. The AMC1302 digitizes the analog input

signal on the high-side, transfers the data across the isolation barrier to the low-side, reconstructs the analog

signal, and presents that signal as a differential voltage on the output pins.

The differential input, differential output, and the high common-mode transient immunity (CMTI) of the AMC1302

ensure reliable and accurate operation even in high-noise environments.

Floating Gate

Driver Supply

+ DC Link

Low-side supply

(3.3 V or 5 V)

1 uF 100 nF

AMC1302

VDD1

VDD2

OUTP

OUTN

GND2

10 nF

INP

RSHUNT

ADC

INN

Load

GND1

– DC Link

图8-1. Using the AMC1302 for Current Sensing in a Typical Application

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8.2.1 Design Requirements

表8-1 lists the parameters for this typical application.

表8-1. Design Requirements

PARAMETER

High-side supply voltage

VALUE

3.3 V or 5 V

Low-side supply voltage

3.3 V or 5 V

Voltage drop across RSHUNT for a linear response

Signal delay (50% V_INto 90% OUTP, OUTN)

±50 mV (maximum)

3 µs (maximum)

8.2.2 Detailed Design Procedure

In 图 8-1, the high-side power supply (VDD1) for the AMC1302 is derived from the floating power supply of the

upper gate driver.

The floating ground reference (GND1) is derived from the end of the shunt resistor that is connected to the

negative input of the AMC1302 (INN). If a four-pin shunt is used, the inputs of the AMC1302 are connected to

the inner leads and GND1 is connected to the outer lead on the INN-side of the shunt. To minimize offset and

improve accuracy, route the ground connection as a separate trace that connects directly to the shunt resistor

rather than shorting GND1 to INN directly at the input to the device. See the Layout section for more details.

8.2.2.1 Shunt Resistor Sizing

Use Ohm's Law to calculate the voltage drop across the shunt resistor (V_SHUNT) for the desired measured

current: V_SHUNT= I × RSHUNT.

Consider the following two restrictions when selecting the value of the shunt resistor, RSHUNT:

• The voltage drop caused by the nominal current range must not exceed the recommended differential input

voltage range for a linear response: |V_SHUNT| ≤|V_FSR

• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes

a clipping output: |V_SHUNT| ≤|V_Clipping

8.2.2.2 Input Filter Design

TI recommends placing an RC-filter in front of the isolated amplifier to improve signal-to-noise performance of

the signal path. Design the input filter such that:

• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency

(20 MHz) of the ΔΣmodulator

• The input bias current does not generate significant voltage drop across the DC impedance of the input filter

• The impedances measured from the analog inputs are equal

For most applications, the structure shown in 图8-2 achieves excellent performance.

AMC1302

VDD1

VDD2

OUTP

OUTN

GND2

10 nF

INP

INN

GND1

图8-2. Differential Input Filter

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8.2.2.3 Differential to Single-Ended Output Conversion

图 8-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using single-

ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage

equals (V_OUTP– V_OUTN) + V_REF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the

system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩand C1 = C2 = 330 pF yields good performance.

AMC1302

VDD1

VDD2

OUTP

OUTN

GND2

INP

–

ADC

To MCU

INN

TLV6001

GND1

V_REF

图8-3. Connecting the AMC1302 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the

18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data

Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.

8.2.3 Application Curve

One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the

switching devices and passive components from damage. To power off the system quickly in the event of an

overcurrent condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale

step response of the AMC1302.

VOUTN

VIN

VOUTP

图8-4. Step Response of the AMC1302

8.3 What to Do and What Not to Do

Do not leave the inputs of the AMC1302 unconnected (floating) when the device is powered up. If the device

inputs are left floating, the input bias current may drive the inputs to a positive value that exceeds the operating

common-mode input voltage and the device outputs the fail-safe voltage as described in the Analog Output

section.

Connect the high-side ground (GND1) to INN, either by a hard short or through a resistive path. A DC current

path between INN and GND1 is required to define the input common-mode voltage. Do not exceed the input

common-mode range as specified in the Recommended Operating Conditions table. For best accuracy, route

the ground connection as a separate trace that connects directly to the shunt resistor rather than shorting GND1

to INN directly at the input to the device. See the Layout section for more details.

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9 Power Supply Recommendations

The AMC1302 does not require any specific power up sequencing. The high-side power-supply (VDD1) is

decoupled with a low-ESR 100-nF capacitor (C1) parallel to a low-ESR 1-µF capacitor (C2). The low-side power

supply (VDD2) is equally decoupled with a low-ESR 100-nF capacitor (C3) parallel to a low-ESR 1-µF capacitor

(C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.

The ground reference for the high-side (GND1) is derived from the end of the shunt resistor, which is connected

to the negative input (INN) of the device. For best DC accuracy, use a separate trace (as shown in 图 9-1) to

make this connection instead of shorting GND1 to INN directly at the device input. If a four-terminal shunt is

used, the device inputs are connected to the inner leads and GND1 is connected to the outer lead on the INN-

side of the shunt.

INP

VDD1

VDD2

C2 1 µF

C1 100 nF

R2 10

C4 1 µF

AMC1302

C3 100 nF

VDD1

VDD2

OUTP

OUTN

GND2

INP

to RC filter / ADC

10 nF

R1 10

INN

GND1

图9-1. Decoupling of the AMC1302

Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they

experience in the application. Multilayer ceramic capacitors (MLCCs) typically exhibit only a fraction of their

nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting

these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is

higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves

that greatly simplify component selection.

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10 Layout

10.1 Layout Guidelines

图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as

possible to the AMC1302 supply pins) and placement of the other components required by the device. For best

performance, place the shunt resistor close to the INP and INN inputs of the AMC1302 and keep the layout of

both connections symmetrical.

10.2 Layout Example

Clearance area, to be

kept free of any

conductive materials.

INP

to RC filter / ADC

OUTP

OUTN

AMC1302

INN

GND2

GND1

Top Metal

Inner or Bottom Layer Metal

Via

图10-1. Recommended Layout of the AMC1302

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Isolation Glossary application report

• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report

• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report

• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive

Systems data sheet

• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise

reference guide

• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference

guide

• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool

11.2 Trademarks

所有商标均为其各自所有者的财产。

11.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.4 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: AMC1302

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jan-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1302DWV

ACTIVE

SOIC

DWV

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-55 to 125

AMC1302

AMC1302DWVR

1000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Jan-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1302DWVR

SOIC

DWV

1000

330.0

16.4

12.05 6.15

3.3

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DWV

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AMC1302DWVR

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DWV SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

AMC1302DWV

505.46

13.94

4826

6.6

Pack Materials-Page 3

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AMC1302 [TI]

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