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AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

AMC1304x 具有 LDO 的高精度、

增强隔离式 Δ-Σ 调制器

1 特性

3 说明

1

•

针对基于分流电阻的电流测量进行优化的引脚兼容

系列：

AMC1304 是一款高精度 Δ-Σ (ΔΣ) 调制器，通过磁场

抗扰度较高的电容式双隔离栅隔离输出与输入电路。根

据 DIN V VDE V 0884-10、UL1577 和 CSA 标准，该

隔离栅经认证可提供高达 7000 V_PEAK的增强型隔离。

当与隔离电源配合使用时，该器件可防止共模高电压线

路上的噪声电流进入本地系统接地，从而干扰或损害低

电压电路。

–

输入电压范围为 ±50mV 或 ±250mV

CMOS 或 LVDS 数字接口选项

•

出色的直流性能，支持系统级高精度感测：

–

偏移误差：±50µV 或 ±100µV（最大值）

偏移漂移：1.3µV/°C（最大值）

增益误差：±0.2% 或 ±0.3%（最大值）

增益漂移：±40ppm/°C（最大值）

AMC1304 的输入针对直接连接分流电阻或其他低电压

等级信号源进行了优化。凭借独特的 ±50mV 低输入电

压范围，器件可通过分流显著降低功耗，同时具有出色

的交流和直流性能。通过使用适当的数字滤波器（即集

成于 TMS320F2807x 或 TMS320F2837x 系列）来抽

取位流，该器件可在 78kSPS 数据速率下实现 81dB

(13.2 ENOB) 动态范围的 16 位分辨率。

•

安全相关认证：

–

7000 V_PK增强型隔离，符合 DIN V VDE V

0884-10 (VDE V 0884-10): 2006-12 标准

符合 UL 1577 标准且长达 1 分钟的 5000 V_RMS

隔离

CAN/CSA No. 5A 组件接受服务通知、IEC

60950-1 和 IEC 60065 终端设备标准

在高侧，调制器由集成的低压降 (LDO) 稳压器供电，

该稳压器支持介于 4V 和 18V 之间的未经稳压的输入

电压 (LDOIN)。隔离数字接口由 3.3V 或 5V 电源

(DVDD) 供电。

•

瞬态抗扰度：15kV/µs（最小值）

高电磁场抗扰度

（请参见应用手册 SLLA181A）

•

外部 5MHz 至 20MHz 时钟输入

可更加轻松地实现系统级同步

AMC1304 采用宽体小外形尺寸集成电路 (SOIC)-16

(DW) 封装，工作温度范围为 –40°C 至 +125°C。

•

18V 片载低压降 (LDO) 稳压器

可在扩展工业温度范围内运行

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

2 应用

AMC1304x

SOIC (16)

10.30mm x 7.50mm

•

基于分流电阻的电流感测用于下列应用：

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

–

工业电机驱动

光电逆变器

不间断电源

•

隔离电压测量

简化电路原理图

Floating

Power Supply

AMC1304

HV+

4 V to 18 V

LDOIN

VCAP

DVDD

DGND

3.3 V or 5.0 V

AGND

AINN

AINP

TMS320F2837x

R_SHUNT

To Load

DOUT

CLKIN

SD-Dx

SD-Cx

PWMx

HV-

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS655

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

www.ti.com.cn

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 21

8.4 Device Functional Modes........................................ 24

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Applications ................................................ 26

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configurations and Functions....................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Power Ratings........................................................... 5

7.6 Insulation Specifications............................................ 6

7.7 Safety-Related Certifications..................................... 7

7.8 Safety Limiting Values .............................................. 7

7.9 Electrical Characteristics: AMC1304x05................... 8

7.10 Electrical Characteristics: AMC1304x25............... 10

7.11 Switching Characteristics...................................... 12

7.12 Insulation Characteristics Curves ......................... 13

7.13 Typical Characteristics.......................................... 14

Detailed Description ............................................ 21

9

10 Power-Supply Recommendations ..................... 30

11 Layout................................................................... 31

11.1 Layout Guidelines ................................................. 31

11.2 Layout Examples................................................... 31

12 器件和文档支持 ..................................................... 33

12.1 文档支持................................................................ 33

12.2 相关链接................................................................ 33

12.3 接收文档更新通知 ................................................. 33

12.4 社区资源................................................................ 33

12.5 商标....................................................................... 33

12.6 静电放电警告......................................................... 33

12.7 Glossary................................................................ 34

13 机械、封装和可订购信息....................................... 34

8

4 修订历史记录

Changes from Revision D (August 2016) to Revision E

Page

•

Changed V_(ESD)for Human-body model (HBM) from ±2000 V to ±2500 V............................................................................. 5

Changed 1G and 10G to 1M and 10M, respectively, in Quantization Noise Shaping figure ............................................... 22

Changes from Revision C (September 2015) to Revision D

Page

•

已更改“特性”部分：删除了经过认证的隔离隔栅分项，增加了安全相关认证和瞬态抗扰度分项.............................................. 1

已更改简化原理图 .................................................................................................................................................................. 1

Changed Specifications section to comply with ISO data sheet format ................................................................................ 5

Changed Maximum virtual junction parameter to Junction temperature in Absolute Maximum Ratings table ..................... 5

Moved Power Rating, Insulation Specifications, Safety-Related Certifications, and Safety Limiting Values tables,

changed to current standards................................................................................................................................................. 5

•

Changed Insulation Specifications table as per ISO standard .............................................................................................. 6

Added Safety and Insulation Characteristics section .......................................................................................................... 13

Changed Figure 54 (The AMC1304 in a Frequency Inverter Application) ........................................................................... 26

Changed Figure 58 (Decoupling the AMC1304) .................................................................................................................. 30

Changes from Revision B (July 2015) to Revision C

Page

•

已将文档状态更改为完整量产数据：已将 AMC1304Mx5 发布为量产数据............................................................................. 1

Changed status of AMC1304Mx5 rows to Production in Device Comparison Table ............................................................ 4

Changed title of AMC1304x05 Electrical Characteristics table from AMC1304L05 to AMC1304x05 ................................... 8

Changed typical specification in second row of DC Accuracy, PSRR parameter of AMC1304x05 Electrical

Characteristics table ............................................................................................................................................................... 8

•

Added CMOS Logic Family (AMC1304M05) section to AMC1304x05 Electrical Characteristics table................................. 9

2

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

www.ti.com.cn

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

•

Added last two rows to the Power Supply, I_DVDDand P_DVDDparameters of AMC1304x05 Electrical Characteristics table... 9

Changed title of AMC1304x25 Electrical Characteristics table from AMC1304L25 to AMC1304x25.................................. 10

Changed typical specification in second row of DC Accuracy, PSRR parameter of AMC1304x25 Electrical

Characteristics table ............................................................................................................................................................ 10

•

Added CMOS Logic Family (AMC1304M05) section to AMC1304x25 Electrical Characteristics table .............................. 11

Added footnote 4 to AMC1304x25 Electrical Characteristics table...................................................................................... 11

Added last two rows to the Power Supply, I_DVDDand P_DVDDparameters of AMC1304x25 Electrical Characteristics

table ..................................................................................................................................................................................... 11

•

Changed legends of Figure 6 and Figure 7 to include all devices, changed conditions of Figure 10 and Figure 11 ......... 14

Changed conditions of Figure 12, Figure 13, and Figure 14 ............................................................................................... 15

Changed legends of Figure 19 to Figure 22, changed conditions of Figure 23 .................................................................. 16

Changed conditions of Figure 24 and Figure 29 ................................................................................................................. 17

Changed conditions of Figure 30 and Figure 35 ................................................................................................................. 18

Changed conditions of Figure 36 to Figure 40 .................................................................................................................... 19

Added CMOS curve to Figure 44 to Figure 47 .................................................................................................................... 20

Changed legend of Figure 57 .............................................................................................................................................. 29

Changes from Revision A (May 2015) to Revision B

Page

•

已将 AMC1304L25 发布为量产数据 ....................................................................................................................................... 1

已更改第二个特性要点的偏移误差和增益误差分项，以包括 AMC1304L25 规范................................................................. 1

Changed status of second row to Production ....................................................................................................................... 4

Changed table order in Specifications section to match correct SDS flow ............................................................................ 8

Added AMC1304L25 Electrical Characteristics table .......................................................................................................... 10

Changed Typical Characteristics section: changed condition statement to reflect AINP difference between device,

added AMC1304L25 related curves..................................................................................................................................... 14

•

Added AMC1304L25 plot to Figure 6 and Figure 7 ............................................................................................................. 14

Changed Figure 10 .............................................................................................................................................................. 14

Added Figure 11 .................................................................................................................................................................. 14

Added Figure 12 and condition to Figure 13 ....................................................................................................................... 15

Changed Figure 14 .............................................................................................................................................................. 15

Added AMC1304L25 plot to Figure 19, Figure 20, Figure 21, and Figure 22 ..................................................................... 16

Added Figure 23 .................................................................................................................................................................. 16

Added Figure 29 and condition to Figure 24 ....................................................................................................................... 17

Added condition to Figure 30 .............................................................................................................................................. 18

Added Figure 35 .................................................................................................................................................................. 18

Added condition to Figure 36 .............................................................................................................................................. 19

Added device name to conditions of Figure 37 and Figure 38 ............................................................................................ 19

Added Figure 39 and Figure 40 ........................................................................................................................................... 19

Changes from Original (September 2014) to Revision A

Page

•

已更改产品预览文档；已将 AMC1304L05 发布为量产数据 ................................................................................................... 1

3

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

www.ti.com.cn

5 Device Comparison Table

INPUT VOLTAGE

DIFFERENTIAL INPUT

RESISTANCE

DIGITAL OUTPUT

DEVICE

RANGE

±50 mV

±250 mV

±50 mV

±250 mV

INTERFACE

AMC1304L05

AMC1304L25

AMC1304M05

AMC1304M25

5 kΩ

25 kΩ

5 kΩ

LVDS

CMOS

25 kΩ

CMOS

6 Pin Configurations and Functions

DW Package: LVDS Interface Versions (AMC1304Lx)

DW Package: CMOS Interface Versions (AMC1304Mx)

16-Pin SOIC

Top View

16-Pin SOIC

Top View

NC

AINP

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DGND

NC

AINP

1

2

3

4

5

6

7

8

16 DGND

NC

15

14

13

12

11

10

9

AINN

AGND

NC

DVDD

CLKIN

CLKIN_N

DOUT

DOUT_N

DGND

AINN

AGND

NC

DVDD

CLKIN

NC

LDOIN

VCAP

AGND

LDOIN

VCAP

AGND

DOUT

NC

DGND

Pin Functions

NO.

I/O

NAME

AMC1304Lx

(LVDS)

AMC1304Mx

(CMOS)

DESCRIPTION

4

8

4

8

—

I

This pin is internally connected to pin 8 and can be left unconnected or tied to high-side ground

High-side ground reference

AGND

AINN

3

Inverting analog input

AINP

2

I

Noninverting analog input

CLKIN

CLKIN_N

DGND

DOUT

DOUT_N

13

12

9, 16

11

10

13

—

9, 16

11

—

I

Modulator clock input, 5 MHz to 20.1 MHz

Inverted modulator clock input

I

—

O

Controller-side ground reference

Modulator data output

Inverted modulator data output

Controller-side power supply, 3.0 V to 5.5 V.

See the Power-Supply Recommendations section for decoupling recommendations.

DVDD

LDOIN

14

—

6

1

6

1

—

Low dropout regulator input, 4 V to 18 V

This pin can be connected to VCAP or left unconnected

This pin can be left unconnected or tied to AGND only

These pins have no internal connection

5

NC

—

15

10, 12

15

This pin can be left unconnected or tied to DVDD only

LDO output. See the Power-Supply Recommendations section for decoupling

recommendations.

VCAP

7

—

4

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

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ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V

Supply voltage

DVDD to DGND

LDOIN to AGND

6.5

LDO input voltage

–0.3

26

3.7

V

Analog input voltage at AINP, AINN

AGND – 6

DGND – 0.3

–10

V

Digital input voltage at CLKIN, CLKIN_N

Input current to any pin except supply pins

Junction temperature, T_J

DVDD + 0.3

10

V

mA

°C

150

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.0

NOM

15.0

3.3

MAX

UNIT

LDOIN

DVDD

T_A

LDO input supply voltage (LDOIN pin)

18.0

5.5

V

Digital (controller-side) supply voltage (DVDD pin)

Operating ambient temperature range

3.0

–40

125

°C

7.4 Thermal Information

AMC1304x

(1)

THERMAL METRIC

DW (SOIC)

16 PINS

80.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

°C/W

R_θJC(top)

R_θJB

40.5

45.1

ψ_JT

11.9

ψ_JB

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

44.5

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

PARAMETER

TEST CONDITIONS

LDOIN = 18 V, DVDD = 5.5 V

LDOIN = 18 V

VALUE

161

UNIT

mW

P_D

Maximum power dissipation (both sides)

Maximum power dissipation (high-side supply)

Maximum power dissipation (low-side supply)

P_D1

P_D2

117

DVDD = 5.5 V, LVDS, R_LOAD= 100 Ω

44

5

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

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UNIT

7.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

GENERAL

CLR

Minimum air gap (clearance)⁽¹⁾

Shortest pin-to-pin distance through air

≥ 8

mm

Shortest pin-to-pin distance across the package

surface

CPG

Minimum external tracking (creepage)⁽¹⁾

Minimum internal gap (internal clearance) of the

double insulation (2 × 0.0135 mm)

DTI

CTI

Distance through insulation

0.027

mm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 600

I

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

I-II

Overvoltage category per IEC 60664-1

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12⁽²⁾

Maximum repetitive peak isolation

voltage

V_IORM

At ac voltage (bipolar or unipolar)

1414

V_PK

At ac voltage (sine wave)

At dc voltage

1000

1500

7000

V_RMS

V_DC

Maximum-rated isolation working

voltage

V_IOWM

V_TEST= V_IOTM, t = 60 s (qualification test)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

V_TEST= 1.2 x V_IOTM, t = 1 s (100% production

test)

8400

Test method per IEC 60065, 1.2/50-μs

waveform, V_TEST= 1.6 x V_IOSM= 10000 V_PK

(qualification)

V_IOSM

6250

V_PK

pC

Method a, after input/output safety test subgroup

2 / 3, V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.2 x V_IORM

= 1697 V_PK, t_m= 10 s

≤ 5

Method a, after environmental tests subgroup 1,

q_pd

Apparent charge⁽⁴⁾

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.6 x V_IORM

2263 V_PK, t_m= 10 s

=

Method b1, at routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s,

V_pd(m)= 1.875 x V_IORM= 2652 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

Pollution degree

V_IO= 0.5 V_PPat 1 MHz

1.2

> 10⁹

2

pF

V_IO= 500 V at T_S= 150°C

Ω

Climatic category

40/125/21

UL1577

V_TEST= V_ISO= 5000 V_RMSor 7000 V_DC, t = 60 s

(qualification test), V_TEST= 1.2 x V_ISO= 6000

V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves or ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

6

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

www.ti.com.cn

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

7.7 Safety-Related Certifications

VDE

UL

Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):

2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN

60095 (VDE 0860): 2005-11

Recognized under UL1577 component recognition and CSA

component acceptance NO 5 programs

Reinforced insulation

Single protection

File number: 40040142

File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A

failure of the I/O circuitry may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient

power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

θ_JA= 80.2°C/W, LDOIN = 18 V, T_J= 150°C,

T_A= 25°C, see Figure 3

I_S

Safety input, output, or supply current

86.5

mA

P_SSafety input, output, or total power

T_SMaximum safety temperature

θ_JA= 80.2°C/W, T_J= 150°C, T_A= 25°C, see Figure 4

1558⁽¹⁾

150

mW

°C

(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that

of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended

maximum input voltage times the current. The junction temperature is then the ambient temperature plus the

power times the junction-to-air thermal resistance.

7

AMC1304L05, AMC1304L25, AMC1304M05, AMC1304M25

ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

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7.9 Electrical Characteristics: AMC1304x05

All minimum and maximum specifications are at T_A= –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A=

25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Maximum differential voltage input range

(AINP-AINN)

V_Clipping

FSR

±62.5

mV

Specified linear full-scale range

(AINP-AINN)

–50

50

V_CM

C_ID

I_IB

Operating common-mode input range

Differential input capacitance

Input bias current

–0.032

1.2

V

pF

2

–72

5

Inputs shorted to AGND

–97

15

–57

μA

R_ID

I_IO

Differential input resistance

Input offset current

kΩ

±5

nA

CMTI

Common-mode transient immunity

kV/μs

f_IN= 0 Hz,

_{CM min}≤ V_IN≤ V_{CM max}

–98

V

CMRR

BW

Common-mode rejection ratio

Input bandwidth

dB

f_INfrom 0.1 Hz to 50 kHz,

_{CM min}≤ V_IN≤ V_{CM max}

–85

800

V

kHz

DC ACCURACY

DNL

INL

Differential nonlinearity

Resolution: 16 bits

Initial, at 25°C

–0.99

–4

0.99

4

LSB

µV

(1)

Integral nonlinearity

Offset error

±1.5

±2.5

E_O

–50

50

(2)

TCE_O

E_G

Offset error thermal drift

Gain error

–1.3

–0.3%

–40

1.3

0.3%

40

μV/°C

Initial, at 25°C

–0.02%

±20

(3)

TCE_G

Gain error thermal drift

ppm/°C

dB

LDOIN from 4 V to 18 V, at dc

–110

PSRR

Power-supply rejection ratio

LDOIN from 4 V to 18 V, from 0.1 Hz to

50 kHz

–110

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

76

81.5

81

dB

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious-free dynamic range

–90

90

–81

SFDR

81

DIGITAL INPUTS/OUTPUTS

External Clock

f_CLKIN

Input clock frequency

Duty cycle

5

20

20.1

60%

MHz

Duty_CLKIN

5 MHz ≤ f_CLKIN≤ 20.1 MHz

40%

50%

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).

(2) Offset error drift is calculated using the box method, as described by the following equation:

value_MAX- value_MIN

TCE_O

=

TempRange

(3) Gain error drift is calculated using the box method, as described by the following equation:

≈ value _MAX- value _MIN

’

6

∆

÷

TCE_G( ppm) =

ì10

value ìTempRange

«

◊

8

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Electrical Characteristics: AMC1304x05 (continued)

All minimum and maximum specifications are at T_A= –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A=

25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS Logic Family (AMC1304M05, CMOS with Schmitt Trigger)

I_IN

Input current

DGND ≤ V_IN≤ DVDD

–1

1

μA

pF

V

C_IN

V_IH

Input capacitance

5

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

V

C_LOAD

f_CLKIN= 20 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

30

pF

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

V

0.1

0.4

V_OL

Low-level output voltage

I_OL= 4 mA

LVDS Logic Family (AMC1304L05)⁽⁴⁾

V_T

Differential output voltage

Common-mode output voltage

Differential input voltage

Common-mode input voltage

Receiver input current

R_LOAD= 100 Ω

250

1.125

100

350

1.23

350

1.25

0

450

1.375

600

mV

V

V_OC

V_ID

V_IC

I_I

mV

V

V_ID= 100 mV

0.05

–24

3.25

20

DGND ≤ V_IN≤ 3.3 V

µA

POWER SUPPLY

LDOIN

VCAP

I_LDOIN

LDOIN pin input voltage

4.0

3.0

15.0

3.45

5.3

18.0

V

VCAP pin voltage

LDOIN pin input current

Controller-side supply voltage

6.5

5.5

8

mA

V

DVDD

3.3

LVDS, R_LOAD= 100 Ω

6.1

CMOS, 3.0 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 5 pF

2.7

3.2

4.0

5.5

I_DVDD

Controller-side supply current

mA

CMOS, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 5 pF

(4) For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface

Circuits for TIA/EIA-644 (LVDS).

9

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7.10 Electrical Characteristics: AMC1304x25

All minimum and maximum specifications are at T_A= –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V,

AINP = –250 mV to 250 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A

= 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Maximum differential voltage input range

(AINP-AINN)

V_Clipping

FSR

±312.5

mV

Specified linear full-scale range

(AINP-AINN)

–250

250

1.2

V_CM

C_ID

I_IB

Operating common-mode input range

Differential input capacitance

Input bias current

–0.16

V

pF

1

–60

25

Inputs shorted to AGND

–82

15

–48

μA

R_ID

I_IO

Differential input resistance

Input offset current

kΩ

±5

nA

CMTI

Common-mode transient immunity

kV/μs

f_IN= 0 Hz,

_{CM min}≤ V_IN≤ V_{CM max}

–98

V

CMRR

BW

Common-mode rejection ratio

Input bandwidth

dB

f_INfrom 0.1 Hz to 50 kHz,

_{CM min}≤ V_IN≤ V_{CM max}

–98

V

1000

kHz

DC ACCURACY

DNL

INL

Differential nonlinearity

Integral nonlinearity⁽¹⁾

Resolution: 16 bits

Initial, at 25°C

–0.99

–4

0.99

4

LSB

µV

±1.5

±25

E_O

Offset error

–100

–1.3

–0.2%

–40

100

1.3

TCE_O

E_G

Offset error thermal drift⁽²⁾

Gain error

Gain error thermal drift⁽³⁾

μV/°C

Initial, at 25°C

–0.05%

±20

0.2%

40

TCE_G

ppm/°C

dB

LDOIN from 4 V to 18 V, at dc

–110

PSRR

Power-supply rejection ratio

LDOIN from 4 V to 18 V,

from 0.1 Hz to 50 kHz

–110

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

82

80

85

84

dB

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious-free dynamic range

–90

90

–81

SFDR

81

DIGITAL INPUTS/OUTPUTS

External Clock

f_CLKIN

Input clock frequency

Duty cycle

5

20

20.1

60%

MHz

Duty_CLKIN

5 MHz ≤ f_CLKIN≤ 20.1 MHz

40%

50%

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(2) Offset error drift is calculated using the box method as described by the following equation:

value_MAX- value_MIN

TCE_O

=

TempRange

.

(3) Gain error drift is calculated using the box method as described by the following equation:

≈ value _MAX- value _MIN

’

6

∆

÷

TCE_G( ppm) =

ì10

value ìTempRange

«

◊

.

10

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Electrical Characteristics: AMC1304x25 (continued)

All minimum and maximum specifications are at T_A= –40°C to 125°C, LDOIN = 4.0 V to 18.0 V, DVDD = 3.0 V to 5.5 V,

AINP = –250 mV to 250 mV, AINN = 0 V, and sinc³filter with OSR = 256, unless otherwise noted. Typical values are at T_A

= 25°C, CLKIN = 20 MHz, LDOIN = 15.0 V, and DVDD = 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS Logic Family (AMC1304M25, CMOS with Schmitt Trigger)

I_IN

Input current

DGND ≤ V_IN≤ DVDD

–1

1

μA

pF

V

C_IN

V_IH

Input capacitance

5

High-level input voltage

Low-level input voltage

Output load capacitance

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

V_IL

V

C_LOAD

f_CLKIN= 20 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

30

pF

V

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

V

0.1

0.4

V

V_OL

Low-level output voltage

I_OL= 4 mA

V

LVDS Logic Family (AMC1304L25)⁽⁴⁾

V_T

Differential output voltage

Common-mode output voltage

Differential input voltage

Common-mode input voltage

Receiver input current

R_LOAD= 100 Ω

250

1.125

100

350

1.23

350

1.25

0

450

1.375

600

mV

V

V_OC

V_ID

V_IC

I_I

mV

V

V_ID= 100 mV

0.05

–24

3.25

20

DGND ≤ V_IN≤ 3.3 V

µA

POWER SUPPLY

LDOIN

VCAP

I_LDOIN

LDOIN pin input voltage

4.0

3.0

15.0

3.45

5.3

18.0

V

VCAP pin voltage

LDOIN pin input current

Controller-side supply voltage

6.5

5.5

8.0

mA

V

DVDD

3.3

LVDS, R_LOAD= 100 Ω

6.1

CMOS, 3.0 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 5 pF

2.7

3.2

4.0

5.5

I_DVDD

Controller-side supply current

mA

CMOS, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 5 pF

(4) For further information on electrical characteristics of LVDS interface circuits, see the TIA-644-A standard and design note Interface

Circuits for TIA/EIA-644 (LVDS).

11

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ZHCSDX9E –SEPTEMBER 2014–REVISED JANUARY 2017

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7.11 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

49.75

19.9

TYP

50

MAX

UNIT

ns

t_CLK

CLKIN, CLKIN_N clock period

CLKIN, CLKIN_N clock high time

CLKIN, CLKIN_N clock low time

200

120

t_HIGH

t_LOW

25

ns

19.9

25

ns

Falling edge of CLKIN, CLKIN_N to

DOUT, DOUT_N valid delay

t_D

0

15

32

ns

DVDD at 3.0 V (min) to DOUT,

DOUT_N valid with LDO_IN > 4 V

CLKIN

cycles

t_ISTART

t_ASTART

Interface startup time

Analog startup time

32

LDOIN step to 4 V with DVDD ≥ 3.0 V,

and 0.1 µF at VCAP pin

1

ms

t_CLK

t_HIGH

/[YLb

/[YLb_b

t_LOW

t_D

5hÜÇ

5hÜÇ_b

Figure 1. Digital Interface Timing

5ë55

/[YLb

5hÜÇ

...

5ata not valid

ëalid data

t_ISTART= 32 CLKIN cycles

Figure 2. Digital Interface Startup Timing

12

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7.12 Insulation Characteristics Curves

100

90

80

70

60

50

40

30

20

10

0

1600

1400

1200

1000

800

600

400

200

0

50

100

150

200

0

50

100

150

200

T_A(°C)

D043

D044

LDOIN = 18 V (worst case)

Figure 3. Thermal Derating Curve for Safety Limiting

Current per VDE

Figure 4. Thermal Derating Curve for Safety Limiting Power

per VDE

T_Aup to 150°C, stress voltage frequency = 60 Hz

Figure 5. Reinforced Isolation Capacitor Lifetime Projection

13

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7.13 Typical Characteristics

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

20

0

-20

AMC1304x05

AMC1304x25

-20

-40

-60

-80

-100

-40

-60

-80

-100

AMC1304x05

AMC1304x25

-120

-0.2

0

0.2

0.4

V_CM(V)

0.6

0.8

1

1.2

0.001

0.01

0.1 0.2 0.5

f_IN(kHz)

1

2 3 5 710 20 50 100

D001

D002

Figure 6. Input Current vs Input Common-Mode Voltage

Figure 7. Common-Mode Rejection Ratio vs

Input Signal Frequency

4

3.5

3

4

3

2

1

0

2.5

2

1.5

1

-1

-2

-3

-4

0.5

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

-50 -40 -30 -20 -10

0

10

20

30

40

50

V_IN(mV)

D004

D003

Figure 9. Integral Nonlinearity vs Temperature

Figure 8. Integral Nonlinearity vs Input Signal Amplitude

100

50

40

80

60

30

40

20

10

0

-20

-40

-60

-80

-100

-10

-20

-30

-40

-50

4

6

8

10

12

14

16

18

4

6

8

10

12

14

16

18

V_LDOIN(V)

D005

D006

AMC1304x25

AMC1304x05

Figure 10. Offset Error vs LDO Input Supply Voltage

Figure 11. Offset Error vs LDO Input Supply Voltage

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

100

50

80

40

60

30

40

20

10

0

-20

-40

-60

-80

-100

-10

-20

-30

-40

-50

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

D007

D008

AMC1304x25

AMC1304x05

Figure 12. Offset Error vs Temperature

Figure 13. Offset Error vs Temperature

100

80

0.3

0.2

0.1

0

AMC1304x05

AMC1304x25

60

40

20

0

-20

-40

-60

-80

-100

-0.1

-0.2

-0.3

5

10

15

20

4

6

8

10

12

14

16

18

f_CLKIN(MHz)

V_LDOIN(V)

D009

D010

Figure 14. Offset Error vs Clock Frequency

Figure 15. Gain Error vs LDO Input Supply Voltage

0.3

0.2

0.1

0

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (èC)

5

10

15

20

f_CLKIN(MHz)

D011

D012

Figure 16. Gain Error vs Temperature

Figure 17. Gain Error vs Clock Frequency

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

100

95

90

85

80

75

70

65

60

0

SNR (AMC1304x05)

SINAD (AMC1304x05)

SNR (AMC1304x25)

SINAD (AMC1304x25)

-20

-40

-60

-80

-100

-120

0.001

4

6

8

10

12

14

16

18

0.01

0.1

1

10

100

V_LDOIN(V)

Ripple Frequency (kHz)

D014

D013

Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs LDO Input Supply Voltage

Figure 18. Power-Supply Rejection Ratio vs

Ripple Frequency

100

95

90

85

80

75

70

65

60

100

SNR (AMC1304x05)

SINAD (AMC1304x05)

SNR (AMC1304x25)

SINAD (AMC1304x25)

SINAD (AMC1304x05)

SNR (AMC1304x25)

SINAD (AMC1304x25)

95

90

85

80

75

70

65

60

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

10

15

20

f_CLKIN(MHz)

D015

D016

Figure 20. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Temperature

Figure 21. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Clock Frequency

100

SNR (AMC1304x05)

SINAD (AMC1304x05)

SNR (AMC1304x25)

SINAD (AMC1304x25)

SNR

SINAD

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

0.1 0.2 0.3 0.5

1

2

3 4 567 10

20 30 50 70100

0

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D017

D018

AMC1304x25

Figure 22. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Frequency

Figure 23. SNR and SINAD vs Input Signal Amplitude

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

100

95

90

85

80

75

70

65

60

55

50

-60

SNR

SINAD

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

0

10

20

30

40

50

60

70

80

90 100

4

6

8

10

12

14

16

18

V_IN(mVpp)

V_LDOIN(V)

D019

D020

AMC1304x05

Figure 24. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Amplitude

Figure 25. Total Harmonic Distortion vs

LDO Input Supply Voltage

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

10

15

20

f_CLKIN(MHz)

D021

D022

Figure 26. Total Harmonic Distortion vs Temperature

Figure 27. Total Harmonic Distortion vs Clock Frequency

-60

-65

-70

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

0.1

1

10

100

0

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D023

D024

AMC1304x25

Figure 28. Total Harmonic Distortion vs

Input Signal Frequency

Figure 29. Total Harmonic Distortion vs

Input Signal Amplitude

17

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

-60

110

105

100

95

-65

-70

-75

-80

90

-85

85

-90

80

-95

75

-100

-105

-110

70

65

60

0

50

100

150

4

5

0

6

8

10

12

14

16

18

V_IN(mVpp)

V_LDOIN(V)

D025

D026

AMC1304x05

Figure 30. Total Harmonic Distortion vs

Input Signal Amplitude

Figure 31. Spurious-Free Dynamic Range vs

LDO Input Supply Voltage

110

105

100

95

110

105

100

95

90

85

80

75

70

65

60

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

10

15

20

f_CLKIN(MHz)

D027

D028

Figure 32. Spurious-Free Dynamic Range vs Temperature

Figure 33. Spurious-Free Dynamic Range vs

Clock Frequency

110

105

100

95

110

105

100

95

90

85

80

75

70

65

60

0.1

1

10

100

50 100 150 200 250 300 350 400 450 500

V_IN(mVpp)

f_IN(kHz)

D029

D030

AMC1304x25

Figure 34. Spurious-Free Dynamic Range vs

Input Signal Frequency

Figure 35. Spurious-Free Dynamic Range vs

Input Signal Amplitude

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

110

105

100

95

0

-20

-40

90

-60

85

-80

80

75

-100

-120

-140

70

65

60

0

50

100

150

0

5

10

15

20

25

30

35

40

V_IN(mVpp)

Frequency (kHz)

D031

D032

AMC1304x05

AMC1304x05, 4096-point FFT, V_IN= 100 mV_PP

Figure 36. Spurious-Free Dynamic Range vs

Input Signal Amplitude

Figure 37. Frequency Spectrum with 1-kHz Input Signal

0

-20

-40

-60

-80

0

-20

-40

-60

-80

-100

-120

-140

-120

-140

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Frequency (kHz)

D034

D033

AMC1304x25, 4096-point FFT, V_IN= 500 mV_PP

AMC1304x05, 4096-point FFT, V_IN= 100 mV_PP

Figure 39. Frequency Spectrum with 1-kHz Input Signal

Figure 38. Frequency Spectrum with 5-kHz Input Signal

0

10

-20

-40

-60

-80

9

8

7

6

5

4

3

-100

-120

-140

0

5

10

15

20

25

30

35

40

4

6

8

10

12

14

16

18

Frequency (kHz)

V_LDOIN(V)

D035

D036

AMC1304x25, 4096-point FFT, V_IN= 500 mV_PP

Figure 40. Frequency Spectrum with 5-kHz Input Signal

Figure 41. LDO Input Supply Current vs

LDO Input Supply Voltage

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Typical Characteristics (continued)

At LDOIN = 15.0 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV (AMC1304x05) or –250 mV to 250 mV (AMC1304x25),

AINN = 0 V, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256, unless otherwise noted.

12

11

10

9

10

9

8

7

6

5

4

3

4

2

1

3

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

10

15

20

f_CLKIN(MHz)

D037

D038

Figure 42. LDO Input Supply Current vs Temperature

Figure 43. LDO Input Supply Current vs Clock Frequency

12

11

10

9

12

LVDS

CMOS

LVDS

CMOS

11

10

9

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

3

3.1

3.2

3.3

3.4

3.5

3.6

4.5 4.6 4.7 4.8 4.9

5

5.1 5.2 5.3 5.4 5.5

DVDD (V)

D039

D040

Figure 44. Controller-Side Supply Current vs

Controller-Side Supply Voltage (3.3 V, min)

Figure 45. Controller-Side Supply Current vs

Controller-Side Supply Voltage (5 V, min)

12

11

10

9

12

11

10

9

LVDS 5 V

LVDS 3.3 V

CMOS 5 V

LVDS 5 V

LVDS 3.3 V

CMOS 5 V

CMOS 3.3 V

8

7

6

5

4

3

2

1

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

5

10

15

20

Clock Frequency (MHz)

D041

D042

Figure 46. Controller-Side Supply Current vs Temperature

Figure 47. Controller-Side Supply Current vs

Clock Frequency

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8 Detailed Description

8.1 Overview

The differential analog input (AINP and AINN) of the AMC1304 is a fully-differential amplifier feeding the

switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes the input signal into a

1-bit output stream. The isolated data output (DOUT and DOUT_N) of the converter provides a stream of digital

ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in

the range of 5 MHz to 20.1 MHz. The time average of this serial bit-stream output is proportional to the analog

input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1304. The analog input range

is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The SiO₂-

based capacitive isolation barrier supports a high level of magnetic field immunity as described in the ISO72x

Digital Isolator Magnetic-Field Immunity application report (SLLA181A), available for download at www.ti.com.

The external clock input simplifies the synchronization of multiple current-sensing channels on the system level.

The extended frequency range of up to 20 MHz supports higher performance levels compared to the other

solutions available on the market.

8.2 Functional Block Diagram

DVDD

VCAP

Voltage Regulator

(LDO)

LDOIN

AINP

BUF

TX

DOUT

-

ûꢀ-Modulator

+

DOUT_N (AMC1304Lx only)

AINN

BUF

TX

CLKIN

1.25-V

Reference

BUF

CLKIN_N (AMC1304Lx only)

TX

AMC1304

AGND

DGND

8.3 Feature Description

8.3.1 Analog Input

The AMC1304 incorporates a front-end circuitry that contains a differential amplifier and sampling stage, followed

by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 for

devices with a specified input voltage range of ±250 mV (this value is for the AMC1304x25), or to a factor of 20

in devices with a ±50-mV input voltage range (for the AMC1304x05), resulting in a differential input impedance of

5 kΩ (for the AMC1304x05) or 25 kΩ (for the AMC1304x25).

Consider the input impedance of the AMC1304 in designs with high-impedance signal sources that can cause

degradation of gain and offset specifications. The importance of this effect, however, depends on the desired

system performance. Additionally, the input bias current caused by the internal common-mode voltage at the

output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal.

See the Isolated Voltage Sensing section for more details on reducing these effects.

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the

range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic

discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only

when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is

±250 mV (for the AMC1304x25) or ±50 mV (for the AMC1304x05), and within the specified input common-mode

range.

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Feature Description (continued)

8.3.2 Modulator

The modulator implemented in the AMC1304 is a second-order, switched-capacitor, feed-forward ΔΣ modulator,

such as the one conceptualized in Figure 48. The analog input voltage V_INand the output V₅of the 1-bit digital-

to-analog converter (DAC) are differentiated, providing an analog voltage V₁at the input of the first integrator

stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage

V₃that is differentiated with the input signal V_INand the output of the first integrator V₂. Depending on the polarity

of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the

next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in the opposite

direction and forcing the value of the integrator output to track the average value of the input.

f_/[YLb

ë₁

ë₂

ë₃

ë₄

ë_Lb

Integrator 1

Integrator 2

ꢀ

/at

0 ë

ë₅

DAC

Figure 48. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a low-

pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert

from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's

microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter

structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304 family. Also,

SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc-

filters, thus offering a system-level solution for multichannel, isolated current sensing. An additional option is to

use a suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a

field-programmable gate array (FPGA) can be used to implement the digital filter.

0

-20

-40

-60

-80

-100

-120

-140

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 49. Quantization Noise Shaping

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Feature Description (continued)

8.3.3 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 250 mV (for the AMC1304x25) or 50 mV (for the AMC1304x05) produces a stream of ones

and zeros that are high 90% of the time. A differential input of –250 mV (–50 mV for the AMC1304x05) produces

a stream of ones and zeros that are high 10% of the time. These input voltages are also the specified linear

ranges of the different AMC1304 versions with performance as specified in this data sheet. If the input voltage

value exceeds these ranges, the output of the modulator shows non-linear behavior when the quantization noise

increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to

–312.5 mV (–62.5 mV for the AMC1304x05) or with a stream of only ones with an input greater than or equal to

312.5 mV (62.5 mV for the AMC1304x05). In this case, however, the AMC1304 generates a single 1 (if the input

is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-Safe Output

section for more details). The input voltage versus the output modulator signal is shown in Figure 50.

The density of ones in the output bit-stream for any input voltage value (with the exception of a full-scale input

signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using

Equation 1:

V _IN+ V_Clipping

2 * V_Clipping

(1)

The AMC1304 system clock is typically 20 MHz and is provided externally at the CLKIN pin. Data are

synchronously provided at 20 MHz at the DOUT pin. Data change at the CLKIN falling edge. For more details,

see the Switching Characteristics table.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

Figure 50. Analog Input versus AMC1304 Modulator Output

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8.4 Device Functional Modes

8.4.1 Fail-Safe Output

In the case of a missing high-side supply voltage (LDOIN), the output of a ΔΣ modulator is not defined and can

cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.

Therefore, the AMC1304 implements a fail-safe output function that ensures the device maintains its output level

in case of a missing LDOIN, as shown in Figure 51.

/[YLb

[5hLb

5hÜÇ

[5hLb Dhh5

[5hLb C!L[

Figure 51. Fail-Safe Output of the AMC1304

8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1304 (that is, V_IN≥ V_Clipping), the device generates a single one or

zero every 128 bits at DOUT, depending on the actual polarity of the signal being sensed, as shown in Figure 52.

In this way, differentiating between a missing LDOIN and a full-scale input signal is possible on the system level.

/[YLb

...

5hÜÇ

ëLb ≤ -312.5 mV (AMC1304x05: -61.5 mV)

...

ëLb ≥ 312.5 mV (AMC1304x05: 61.5 mV)

127 /[YLb cycles

Figure 52. Overrange Output of the AMC1304

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Digital Filter Usage

The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort

and hardware, is a sinc³-type filter, as shown in Equation 2:

3

-OSR

≈

’

1- z

∆

÷

H(z) =

1- z^-1

«

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an oversampling

ratio (OSR) of 256 and an output word duration of 16 bits.

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.

Figure 53 shows the ENOB of the AMC1304 with different oversampling ratios. In this document, this number is

calculated from the SNR by using Equation 3:

SNR =1.76dB+ 6.02dB*ENOB

(3)

16

14

12

10

8

6

4

sinc1

sinc2

sinc3

2

0

1

10

100

1000

OSR

D053

Figure 53. Measured Effective Number of Bits versus Oversampling Ratio

An example code for implementing a sinc³filter in an FPGA is discussed in the Combining ADS1202 with FPGA

Digital Filter for Current Measurement in Motor Control Applications application note (SBAA094), available for

download at www.ti.com.

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9.2 Typical Applications

9.2.1 Frequency Inverter Application

Isolated ΔΣ modulators are being widely used in new-generation frequency inverter designs because of their high

ac and dc performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters

(string and central inverters), uninterruptible power supplies (UPS), electrical and hybrid electrical vehicles, and

other industrial applications. The input structure of the AMC1304 is optimized for use with low-impedance shunt

resistors and is therefore tailored for isolated current sensing using shunts.

DC link

Gate Driver

R_SHUNT

L1

R_SHUNT

L3

L2

R_SHUNT

Gate Driver

AMC1304

TMS320F28x7x

SD-D1

15 V

LDOIN

DVDD

3.3 V

AINP

AINN

AGND

DOUT

CLKIN

DGND

SD-C1

AMC1304

15 V

LDOIN

DVDD

3.3 V

AINP

AINN

AGND

DOUT

CLKIN

DGND

SD-D2

SD-C2

AMC1304

LDOIN DVDD

AMC1304

15 V

LDOIN

DVDD

3.3 V

AINP

AINN

AGND

DOUT

CLKIN

DGND

AINP

AINN

AGND

DOUT

CLKIN

DGND

SD-D3

SD-C3

PWMx

SD-D4

SD-C4

Figure 54. The AMC1304 in a Frequency Inverter Application

9.2.1.1 Design Requirements

A typical operation of the device in a frequency inverter application is shown in Figure 54. When the inverter

stage is part of a motor drive system, measurement of the motor phase current is done via the shunt resistors

(R_SHUNT). Depending on the system design, either all three or only two phase currents are sensed.

In this example, an additional fourth AMC1304 is used to support isolated voltage sensing of the dc link. This

high voltage is reduced using a high-impedance resistive divider before being sensed by the device across a

smaller resistor. The value of this resistor can degrade the performance of the measurement, as described in the

Isolated Voltage Sensing section.

9.2.1.2 Detailed Design Procedure

The typically recommended RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the

signal path is not required for the AMC1304. By design, the input bandwidth of the analog front-end of the device

is limited to 1 MHz.

For modulator output bit-stream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers

(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These families support up to eight

channels of dedicated hardwired filter structures that significantly simplify system level design by offering two

filtering paths per channel: one providing high accuracy results for the control loop and one fast response path

for overcurrent detection.

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Typical Applications (continued)

9.2.1.3 Application Curve

In motor control applications, a very fast response time for overcurrent detection is required. The time for fully

settling the filter in case of a step-signal at the input of the modulator depends on its order; that is, a sinc³filter

requires three data updates for full settling (with f_DATA= f_CLK/ OSR). Therefore, for overcurrent protection, filter

types other than sinc³can be a better choice; an alternative is the sinc²filter. Figure 55 compares the settling

times of different filter orders.

The delay time of the sinc filter with a continuous signal is half of its settling time.

16

14

12

10

8

6

4

sinc1

sinc2

sinc3

2

0

2

4

6

8

10

12

14

16

18

20

settling time (µs)

D054

Figure 55. Measured Effective Number of Bits versus Settling Time

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Typical Applications (continued)

9.2.2 Isolated Voltage Sensing

The AMC1304 is optimized for usage in current-sensing applications using low-impedance shunts. However, the

device can also be used in isolated voltage-sensing applications if the affect of the (usually higher) impedance of

the resistor used in this case is considered.

High Voltage

Potential

15 V

R1

LDOIN

AINP

AMC1304

R2

R3

R4

R5

I_IB

-

r_ID

ûꢀ Modulator

+

AINN

R3'

R4'

R5'

AGND

V_CM= 2 V

GND

Figure 56. Using the AMC1304 for Isolated Voltage Sensing

9.2.2.1 Design Requirements

Figure 56 shows a simplified circuit typically used in high-voltage-sensing applications. The high impedance

resistors (R1 and R2) are used as voltage dividers and dominate the current value definition. The resistance of

the sensing resistor R3 is chosen to meet the input voltage range of the AMC1304. This resistor and the

differential input impedance of the device (the AMC1304x25 is 25 kΩ, the AMC1304x05 is 5 kΩ) also create a

voltage divider that results in an additional gain error. With the assumption of R1, R2, and R_INhaving a

considerably higher value than R3, the resulting total gain error can be estimated using Equation 4, with E_G

being the gain error of the AMC1304.

R3

E_Gtot= E_G

+

R_IN

(4)

This gain error can be easily minimized during the initial system-level gain calibration procedure.

9.2.2.2 Detailed Design Procedure

As indicated in Figure 56, the output of the integrated differential amplifier is internally biased to a common-mode

voltage of 2 V. This voltage results in a bias current I_IBthrough the resistive network R4 and R5 (or R4' and R5')

used for setting the gain of the amplifier. The value range of this current is specified in the Electrical

Characteristics table. This bias current generates additional offset error that depends on the value of the resistor

R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as

illustrated in Figure 57), the initial system offset calibration does not minimize its effect. Therefore, in systems

with high accuracy requirements, TI recommends using a series resistor at the negative input (AINN) of the

AMC1304 with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 56) to eliminate the affect of the

bias current.

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Typical Applications (continued)

This additional series resistor (R3') influences the gain error of the circuit. The effect can be calculated using

Equation 5 with R5 = R5' = 50 kΩ and R4 = R4' = 2.5 kΩ (for the AMC1304x05) or 12.5 kΩ (for the

AMC1304x25).

R4

≈

’

÷

E (%) = 1 -

*100%

∆

G

R4'+R3'

«

◊

(5)

9.2.2.3 Application Curve

Figure 57 shows the dependency of the input bias current on the common-mode voltage at the input of the

AMC1304.

20

0

-20

-40

-60

-80

AMC1304x05

AMC1304x25

-100

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

V_CM(V)

D001

Figure 57. Input Current vs Input Common-Mode Voltage

9.2.3 Do's and Don'ts

Do not leave the inputs of the AMC1304 unconnected (floating) when the device is powered up. If both modulator

inputs are left floating, the input bias current drives them to the output common-mode of the analog front end of

approximately 2 V that is above the specified input common-mode range. As a result, the front gain diminishes

and the modulator outputs a bitstream resembling a zero input differential voltage.

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10 Power-Supply Recommendations

In a typical frequency-inverter application, the high-side power supply (LDOIN) for the device is directly derived

from the floating power supply of the upper gate driver. A low-ESR decoupling capacitor of 0.1 µF is

recommended for filtering this power-supply path. Place this capacitor (C2 in Figure 58) as close as possible to

the LDOIN pin of the AMC1304 for best performance. If better filtering is required, an additional 10-µF capacitor

can be used. The output of the internal LDO requires a decoupling capacitor of 0.1 µF to be connected between

the VCAP pin and AGND as close as possible to the device.

The floating ground reference (AGND) is derived from the end of the shunt resistor, which is connected to the

negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads

and AGND is connected to one of the outer leads of the shunt.

For decoupling of the digital power supply on the controller side, TI recommends using a 0.1-µF capacitor

assembled as close to the DVDD pin of the AMC1304 as possible, followed by an additional capacitor in the

range of 1 µF to 10 µF.

Floating

Power Supply

HV+

18 V (max)

AMC1304

3.3 V or 5.0 V

LDOIN

DVDD

C1

C2

C4

C5

Gate Driver

10ꢀF

0.1ꢀF

2.2ꢀF

VCAP

DGND

C3

0.1ꢀF

TMS320F28x7x

SD-Dx

AGND

AINN

AINP

R_SHUNT

to load

DOUT

CLKIN

SD-Cx

PWMx

Gate Driver

HV-

Figure 58. Decoupling the AMC1304

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11 Layout

11.1 Layout Guidelines

A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the

AMC1304) and placement of the other components required by the device is shown in Figure 59. For best

performance, place the shunt resistor close to the VINP and VINN inputs of the AMC1304 and keep the layout of

both connections symmetrical.

For the AMC1304Lx version, place the 100-Ω termination resistor as close as possible to the CLKIN, CLKIN_N

inputs of the device to achieve highest signal integrity. If not integrated, an additional termination resistor is

required as close as possible to the LVDS data inputs of the MCU or filter device; see Figure 60.

11.2 Layout Examples

Top View

Clearance area,

to be kept free of any

conductive materials.

1

NC

DGND

NC

16

2.2 µF

0.1 µF

AINP

AINN

AGND

NC

SMD

0603

SMD

0603

DVDD

CLKIN

NC

AMC1304Mxx

To or From

MCU

(Filter)

0.1 µF

SMD

0603

To Floating

Power

Supply

DOUT

NC

LDOIN

VCAP

AGND

LEGEND

Top Layer:

Copper Pour and Traces

0.1 µF

High-Side Area

SMD

0603

Controller-Side Area

DGND

Via to Ground Plane

Via to Supply Plane

Figure 59. Recommended Layout of the AMC1304Mx

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Layout Examples (continued)

Top View

Clearance area,

to be kept free of any

conductive materials.

1

DGND

NC

16

0.1 µF

2.2 µF

AINP

AINN

AGND

NC

SMD

0603

SMD

0603

DVDD

CLKIN

CLKIN_N

DOUT

DOUT_N

DGND

100 W

AMC1304Lxx

SMD

0603

0.1 µF

To or From

MCU

SMD

0603

(Filter)

To Floating

Power

Supply

LDOIN

VCAP

AGND

LEGEND

100 W

Top Layer:

Copper Pour and Traces

SMD

0603

0.1 µF

High-Side Area

SMD

0603

Controller-Side Area

Via to Ground Plane

Via to Supply Plane

Figure 60. Recommended Layout of the AMC1304Lx

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12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ


型号：	AMC1304L25DW
厂家：	TEXAS INSTRUMENTS
描述：	具有 LDO 和 LVDS 接口的 ±250mV 输入、精密电流检测增强型隔离式调制器 \| DW \| 16 \| -40 to 125 光电二极管
文件：	总44页 (文件大小：2268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AMC1304L25DW [TI]

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