AMC1336DWVR [TI]

±1V 输入、精密电压检测增强型隔离式调制器

| DWV | 8 | -40 to 125;


型号：	AMC1336DWVR
厂家：	TEXAS INSTRUMENTS
描述：	±1V 输入、精密电压检测增强型隔离式调制器 \| DWV \| 8 \| -40 to 125
文件：	总41页 (文件大小：2007K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

用于电压检测应用的 AMC1336 小型、高精度、增强型隔离式 Δ-Σ 调制器

驱动器

1 特性

3 说明

•

输入结构专为电压测量而优化：

AMC1336 是一款精密 Δ-Σ 调制器，通过抗电磁干扰性

能极强的电容式双隔离隔栅将输出与输入电路隔离开。

该隔离层经过认证，可以按照 DIN VDE V 0884-11 和

UL1577 标准提供高达 8000V_PEAK的增强型隔离。与

隔离式电源结合使用时，该隔离式调制器可将以不同共

模电压等级运行的系统的各器件隔开，并防止较低电压

器件损坏。

–

输入电压范围：±1V

输入电阻：1.5GΩ（典型值）

•

出色的直流性能：

–

失调电压误差：±0.5mV（最大值）

温漂：±4µV/°C（最大值）

增益误差：±0.25%（最大值）

增益漂移：±40ppm/°C（最大值）

AMC1336 独有的双极 ±1V 宽输入电压范围及其高输

入电阻支持与高电压应用中的电阻分压器直接连接。

与数字滤波器（例如集成到 TMS320F28004x、

TMS320F2807x 或 TMS320F2837x 微控制器系列中

的数字滤波器）配合使用以抽取输出位流时，该器件可

在 82kSPS 的数据速率下实现具有 87dB 动态范围的

16 位分辨率。

•

瞬态抗扰性：115kV/µs（典型值）

高侧电源缺失检测

安全相关认证：

–

符合 DIN VDE V 0884-11: 2017-01 标准的

8000V_PEAK增强型隔离

符合 UL1577 标准且长达 1 分钟的 5700V_RMS

隔离

在高侧，AMC1336 由

IEC 62368-1 终端设备标准

3.3V 或 5V 电源供电。隔离式数字接口由 3.0V、3.3V

或 5V 电源供电。

2 应用

•

以下器件的隔离式交流和直流电压测量：

AMC1336 的额定扩展工业温度范围为 –40°C 至

+125°C。

–

不间断电源

光电逆变器

电机驱动器

器件信息⁽¹⁾

器件型号

AMC1336

封装

SOIC (8)

封装尺寸（标称值）

5.85mm × 7.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

Phase1

3.3 V or 5.0 V

3.0 V, 3.3 V, or 5.0 V

AMC1336

DVDD

AVDD

Diagnostics

DGND

DOUT

CLKIN

AGND

AINP

TMS320F28x

SD-Dx

SD-Cx

PWMx

AINN

Phase2

or N

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS951

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 17

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 24

8.1 Application Information............................................ 24

8.2 Typical Application .................................................. 25

Power Supply Recommendations...................... 29

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Power Ratings........................................................... 5

6.6 Insulation Specifications............................................ 6

6.7 Safety-Related Certifications..................................... 7

6.8 Safety Limiting Values .............................................. 7

6.9 Electrical Characteristics........................................... 7

6.10 Switching Characteristics........................................ 9

6.11 Insulation Characteristics Curves ......................... 10

6.12 Typical Characteristics.......................................... 11

Detailed Description ............................................ 17

7.1 Overview ................................................................. 17

10 Layout................................................................... 30

10.1 Layout Guidelines ................................................. 30

10.2 Layout Example .................................................... 30

11 器件和文档支持 ..................................................... 31

11.1 器件支持................................................................ 31

11.2 文档支持................................................................ 31

11.3 接收文档更新通知 ................................................. 31

11.4 社区资源................................................................ 31

11.5 商标....................................................................... 31

11.6 静电放电警告......................................................... 31

11.7 Glossary................................................................ 31

12 机械、封装和可订购信息....................................... 32

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (December 2019) to Revision B

Page

•

Changed P_D(AVDD = DVDD = 5.5 V) from 88 mW to 90.75 mW......................................................................................... 5

Changed P_D1(AVDD = 5.5 V) from 55 mW to 57.75 mW...................................................................................................... 5

Added UL certification file number.......................................................................................................................................... 7

Changes from Original (August 2019) to Revision A

Page

•

已更改将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

5 Pin Configuration and Functions

DWV Package

8-Pin SOIC

Top View

AVDD

AINP

DVDD

CLKIN

DOUT

DGND

AINN

AGND

Not to scale

Pin Functions

I/O

NO.

NAME

DESCRIPTION

Analog (high-side) power supply, 3.0 V to 5.5 V.

AVDD

—

See the Power Supply Recommendations section for decoupling recommendations.

AINP

AINN

Noninverting analog input

Inverting analog input

AGND

DGND

—

Analog (high-side) ground reference

Digital (controller-side) ground reference

Modulator bitstream output, updated with the rising edge of the clock signal present on CLKIN. Use the rising

edge of the clock to latch the modulator bitstream at the input of the digital filter device.

DOUT

CLKIN

DVDD

Modulator clock input with internal pulldown resistor (typical value: 1 MΩ). The clock signal must be applied

continuously for proper device operation; see the Clock Input section for additional details.

Digital (controller-side) power supply, 2.7 V to 5.5 V.

See the Power Supply Recommendations section for decoupling recommendations.

—

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

see⁽¹⁾

MIN

–0.3

MAX

6.5

UNIT

AVDD to AGND

Power-supply voltage

DVDD to DGND

–0.3

6.5

Analog input voltage

Digital input voltage

Digital output voltage

Input current

On the AINP and AINN pins

On the CLKIN pin

AGND – 5

DGND – 0.5

–10

AVDD + 0.5

DVDD + 0.5

On the DOUT pin

Continuous, any pin except power-supply pins

Junction, T_J

150

Temperature

°C

Storage, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVDD

DVDD

High-side supply voltage

Controller-side

AVDD to AGND

DVDD to DGND

3.0

2.7

5.0

3.3

5.5

ANALOG INPUT

V_ClippingDifferential input voltage before clipping output

V_FSR

V_IN= V_AINP– V_AINN

±1.25

Specified linear differential full-scale voltage

Absolute common-mode input voltage⁽¹⁾

V_IN= V_AINP– V_AINN

–1

–2

(V_AINP+ V_AINN) / 2 to AGND

AVDD

(V_AINP+ V_AINN) / 2 to AGND,

3.0 V ≤ AVDD < 4 V,

V_AINP= V_AINN

–1.4

–0.8

–1.4

–0.8

AVDD – 1.4

AVDD – 2.4

2.7

(V_AINP+ V_AINN) / 2 to AGND,

3.0 V ≤ AVDD < 4.5 V,

|V_AINP– V_AINN| = 1.25 V

V_CM

Operating common-mode input voltage⁽²⁾

(V_AINP+ V_AINN) / 2 to AGND,

4 V ≤ AVDD ≤ 5.5 V,

V_AINP= V_AINN

(V_AINP+ V_AINN) / 2 to AGND,

4.5 V ≤ AVDD ≤ 5.5 V,

|V_AINP– V_AINN| = 1.25 V

2.1

DIGITAL INPUT

Input voltage

TEMPERATURE RANGE

T_AOperating ambient temperature

V_CLKINto DGND

DGND

–40

DVDD

125

°C

(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage V_CMfor normal

operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) See the Analog Input section for more details.

AMC1336

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ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

6.4 Thermal Information

AMC1336

THERMAL METRIC⁽¹⁾

DWV (SOIC)

8 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

46.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

11.5

ψ_JB

44.4

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

AVDD = DVDD = 5.5 V

VALUE

90.75

50.4

57.75

32.4

UNIT

P_D

Maximum power dissipation (both sides)

AVDD = DVDD = 3.6 V

AVDD = 5.5 V

P_D1

P_D2

Maximum power dissipation (high-side supply)

AVDD = 3.6 V

DVDD = 5.5 V

Maximum power dissipation (controller-side supply)

DVDD = 3.6 V

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

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6.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

External clearance⁽¹⁾

External creepage⁽¹⁾

Distance through insulation

Comparative tracking index

Material group

Shortest pin-to-pin distance through air

Shortest pin-to-pin distance across the package surface

Minimum internal gap (internal clearance) of the double insulation

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 8.5

≥ 0.021

≥ 600

CPG

DTI

CTI

Rated mains voltage ≤ 600 V_RMS

I-IV

Overvoltage category

per IEC 60664-1

Rated mains voltage ≤ 1000 V_RMS

I-III

DIN VDE V 0884-11: 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

At AC voltage

2121

V_PK

At AC voltage (sine wave); see 图 5

At DC voltage

1500

2121

8000

9600

V_RMS

V_DC

Maximum-rated isolation

working voltage

V_IOWM

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production test)

Maximum transient

V_IOTM

V_PK

isolation voltage

Maximum surge

V_IOSM

Test method per IEC 60065, 1.2/50-µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

8000

≤ 5

isolation voltage⁽³⁾

Method a, after input/output safety test subgroups 2 & 3,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method a, after environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s, V_pd(m)= 1.6 × V_IORM, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

Method b1, at routine test (100% production) and preconditioning (type test),

V_ini= V_IOTM, t_ini= 1 s, V_pd(m)= 1.875 × V_IORM, t_m= 1 s

Barrier capacitance,

input to output⁽⁵⁾

C_IO

R_IO

V_IO= 0.5 V_PPat 1 MHz

> 10¹²

> 10¹¹

> 10⁹

V_IO= 500 V at T_A= 25°C

Insulation resistance,

input to output⁽⁵⁾

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/21

UL1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification),

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100% production test)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves, ribs, or both on a PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

6.7 Safety-Related Certifications

VDE

Certified according to DIN VDE V 0884-11: 2017-01,

DIN EN 62368-1: 2016-05, EN 62368-1: 2014,

and IEC 62368-1: 2014

Recognized under 1577 component recognition

Reinforced insulation

Single protection

Certificate number: 40040142

File number: E181974

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

_θJA= 94°C/W, T_J= 150°C, T_A= 25°C,

241

AVDD = DVDD = 5.5 V, see 图 3

_θJA= 94°C/W, T_J= 150°C, T_A= 25°C,

AVDD = DVDD = 3.6 V, see 图 3

_θJA= 94°C/W, T_J= 150°C, T_A= 25°C, see

Safety input, output,

or supply current

I_S

369

Safety input, output,

or total power⁽¹⁾

图 4

P_S

T_S

1329

150

°C

Maximum safety temperature

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_Sand P_S. These

limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum junction temperature.

P_S= I_S× AVDD_max+ I_S× DVDD_max, where AVDD_maxis the maximum high-side voltage and DVDD_maxis the maximum controller-side

supply voltage.

6.9 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, and

f_CLKIN= 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

R_IN

Single-ended input resistance

Differential input resistance

Single-ended input capacitance

Differential input capacitance

Input bias current

AINN = AGND

0.1

1.5

GΩ

R_IND

C_IN

0.16

AINN = AGND, f_CLKIN= 20 MHz

f_CLKIN= 20 MHz

C_IND

I_IB

AINP = AINN = AGND; I_IB= (I_AINP+ I_AINN) / 2

I_IO= I_AINP– I_AINN

–10

±3

TCI_IB

I_IO

Input bias current drift

–14

±1

pA/°C

Input offset current

–5

CMTI

Common-mode transient immunity

|AGND – DGND| = 1 kV

115

kV/µs

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, and

f_CLKIN= 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

Resolution

Decimation filter output set to 16 bits

Resolution: 16 bits

–4

Bit

LSB

INL

Integral nonlinearity⁽¹⁾

±1.6

±0.03

±0.6

0.5

E_O

Offset error

Initial, at T_A= 25°C, AINP = AINN = AGND

–0.5

–4

TCE_O

Offset error drift⁽²⁾

µV/°C

Initial, at T_A= 25°C,

V_AINP= 1 V or V_AINN= –1 V, AINN = AGND

E_G

Gain error⁽³⁾

–0.25

–40

±0.02

0.25

TCE_G

Gain error drift⁽⁴⁾

±20

–104

–96

ppm/°C

AINP = AINN, f_IN= 0 Hz, V_{CM min}≤ V_CM≤ V_{CM max}

AINP = AINN, f_IN= 10 kHz, –0.5 V ≤ V_IN≤ 0.5 V

PSRR vs AVDD, at DC

CMRR

PSRR

Common-mode rejection ratio

Power-supply rejection ratio

–83

PSRR vs AVDD, 100-mV and 10-kHz ripple

–83

AC ACCURACY

SNR

Signal-to-noise ratio

V_IN= 2 V_PP, f_IN= 1 kHz

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious-free dynamic range

–91

–80

SFDR

DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)

I_IN

Input current

DGND ≤ V_IN≤ DVDD

µA

C_IN

V_IH

V_IL

Input capacitance

High-level input voltage

Low-level input voltage

0.7 x DVDD

–0.3

DVDD + 0.3

0.3 x DVDD

DIGITAL OUTPUT (CMOS)

C_LOADOutput load capacitance

f_CLKIN= 21 MHz

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

Low-level output voltage

0.1

0.4

V_OL

I_OL= 4 mA

POWER SUPPLY

AVDD_PORAVDD power-on reset threshold voltage AVDD falling

2.4

2.6

6.8

7.8

3.4

3.7

2.8

3 V ≤ AVDD ≤ 3.6 V

I_AVDD

High-side supply current

4.5 V ≤ AVDD ≤ 5.5 V

10.5

2.7 V ≤ DVDD ≤ 3.6 V, C_LOAD= 15 pF

4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD= 15 pF

I_DVDD

Controller-side supply current

(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(2) Offset error drift is calculated using the box method, as described by the following equation:

TCE_O= (value_MAX- value_MIN) / TempRange

(3) The typical value includes one sigma statistical variation.

(4) Gain error drift is calculated using the box method, as described by the following equation:

TCE_G(ppm) = ((value_MAX- value_MIN) / (value x TempRange)) X 10⁶

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

6.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3.0 V ≤ AVDD ≤ 5.5 V

4.5 V ≤ AVDD ≤ 5.5 V

f_CLKIN

CLKIN clock frequency

MHz

CLKIN duty cycle

40%

3.5

50%

60%

t_H1

t_D1

DOUT hold time after rising edge of CLKIN

Rising edge of CLKIN to DOUT valid delay

C_LOAD= 15 pF

10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V_,C_LOAD= 15 pF

10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V_,C_LOAD= 15 pF

10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V_,C_LOAD= 15 pF

10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, C_LOAD= 15 pF

AVDD step to 3.0 V; 0.1%-settling, clock applied

2.5

3.2

t_r

t_f

DOUT rise time

DOUT fall time

2.2

2.9

t_ASTARTAnalog start-up time

0.25

t_CLKIN

t_HIGH

CLKIN

t_LOW

t_H

t_D

t_r/ t_f

DOUT

图 1. Digital Interface Timing

AVDD

DVDD

t_ASTART

CLKIN

DOUT

...

Bitstream not valid (analog settling)

Valid bitstream

图 2. Device Start-Up Timing

AMC1336

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www.ti.com.cn

6.11 Insulation Characteristics Curves

400

1600

1400

1200

1000

800

600

400

200

AVDD = DVDD = 3.6 V

AVDD = DVDD = 5.5 V

350

300

250

200

150

100

T_A(°C)

125

150

175

200

100

T_A(°C)

125

150

175

200

D001

D002

图 3. Thermal Derating Curve for Safety-Limiting Current per

图 4. Thermal Derating Curve for Safety-Limiting

VDE

Power per VDE

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

1.E+10

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

87.5%

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

T_Aup to 150°C, stress-voltage frequency = 60 Hz,

isolation working voltage = 1500 V_RMS, operating lifetime = 135 years

图 5. Reinforced Isolation Capacitor Lifetime Projection

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6.12 Typical Characteristics

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

7.5

2.5

-1

-2

-3

-4

-2.5

-5

-7.5

-10

-0.65 -0.3

0.05

0.4

0.75

V_CM(V)

1.1

1.45

1.8

2.15

-1

-0.75 -0.5 -0.25

V_IN(mV)

0.25

0.5

0.75

D003

D004

图 6. Input Bias Current vs

Common-Mode Input Voltage

图 7. Integral Nonlinearity vs

Input Voltage

3.5

2.5

1.5

0.5

D038

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

E_O(mV)

D005

图 9. Offset Error Histogram

图 8. Integral Nonlinearity vs Temperature

0.5

0.4

0.3

0.2

0.1

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

Device 1

Device 2

Device 3

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D006

D007

图 10. Offset Error vs High-Side Supply Voltage

图 11. Offset Error vs Temperature

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Typical Characteristics (接下页)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

D039

10 11 12 13 14 15 16 17 18 19 20 21

f_CLKIN(MHz)

E_G(%)

D008

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 12. Offset Error vs Clock Frequency

图 13. Gain Error Histogram

0.25

0.2

0.5

0.4

0.3

0.2

0.1

0.15

0.1

0.05

-0.05

-0.1

-0.15

-0.2

-0.25

-0.1

-0.2

-0.3

-0.4

-0.5

Device 1

Device 2

Device 3

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D011

D012

图 14. Gain Error vs High-Side Supply Voltage

图 15. Gain Error vs Temperature

-20

0.25

0.2

OSR = 8

OSR = 256

0.15

0.1

-40

-60

0.05

-80

-0.05

-0.1

-0.15

-0.2

-0.25

-100

-120

-140

-160

f_CLKIN(MHz)

0.01

0.1

100

1000

f_IN(kHz)

D013

D009

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 16. Gain Error vs Clock Frequency

图 17. Common-Mode Rejection Ratio vs

Input Signal Frequency

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Typical Characteristics (接下页)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

SNR

SINAD

-20

-40

-60

-80

-100

-120

-140

-160

0.01

0.1

100

1000

3.5

4.5

AVDD (V)

5.5

f_RIPPLE(kHz)

D010

D014

图 18. Power-Supply Rejection Ratio vs

图 19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion

vs High-Side Supply Voltage

Ripple Frequency

SNR

SINAD

SNR

SINAD

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

f_CLKIN(MHz)

19 21

D015

D016

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion

图 21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion

vs Temperature

vs Clock Frequency

100

SNR

SINAD

SNR

SINAD

0.01

0.1

f_IN(kHz)

100

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

V_IN(Vpp)

D017

D018

图 22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion

图 23. Signal-to-Noise Ratio and Signal-to-Noise + Distortion

vs Input Signal Frequency

vs Input Signal Amplitude

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Typical Characteristics (接下页)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

-76

-80

-84

-88

-92

-96

-100

-104

-100

-104

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D019

D020

图 24. Total Harmonic Distortion vs

图 25. Total Harmonic Distortion vs Temperature

High-Side Supply Voltage

-76

-80

-76

-80

-84

-88

-92

-96

-100

-104

-100

-104

f_CLKIN(MHz)

0.01

0.1

f_IN(kHz)

D021

D022

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 26. Total Harmonic Distortion vs Clock Frequency

图 27. Total Harmonic Distortion vs

Input Signal Frequency

-80

-84

112

108

104

100

-88

-92

-96

-100

-104

-108

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

V_IN(Vpp)

3.5

4.5

AVDD (V)

5.5

D023

D024

图 28. Total Harmonic Distortion vs

图 29. Spurious-Free Dynamic Range vs

Input Signal Amplitude

High-Side Supply Voltage

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Typical Characteristics (接下页)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

112

108

104

100

112

108

104

100

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

f_CLKIN(MHz)

D025

D026

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 30. Spurious-Free Dynamic Range vs Temperature

图 31. Spurious-Free Dynamic Range vs

Clock Frequency

112

108

104

100

109

105

101

0.01

0.1

0.2 0.4 0.6 0.8

1 1.2 1.4 1.6 1.8

V_IN(Vpp)

f_IN(kHz)

D027

D028

图 32. Spurious-Free Dynamic Range vs

图 33. Spurious-Free Dynamic Range vs

Input Signal Frequency

Input Signal Amplitude

-20

-40

-60

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

Frequency (kHz)

D029

D030

156,250-point DFT, V_IN= 2 V_PP

图 34. Frequency Spectrum with 1-kHz Input Signal

156,250-point DFT, V_IN= 2 V_PP

图 35. Frequency Spectrum with 10-kHz Input Signal

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Typical Characteristics (接下页)

at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with OSR = 256 (unless

otherwise noted)

10.5

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

10.5

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

I_AVDD

I_DVDD

I_AVDDvs AVDD

I_DVDDvs DVDD

2.7

3.1

3.5

3.9

xVDD (V)

4.3

4.7

5.1

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D031

D032

图 36. Supply Current vs Supply Voltage

图 37. Supply Current vs Temperature

10.5

I_AVDD

I_DVDD

9.5

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

f_CLKIN(MHz)

D033

f_CLKIN< 9 MHz with AVDD ≥ 4.5 V only

图 38. Supply Current vs Clock Frequency

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7 Detailed Description

7.1 Overview

The differential analog input (comprised of input signals AINP and AINN) of the AMC1336 is a chopper-stabilized

instrumentation amplifier, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator

stage that digitizes the input signal into a 1-bit output stream. The data output DOUT of the converter provides a

stream of digital ones and zeros that is synchronous to the externally provided clock source at the CLKIN pin

with a frequency in the range of 5 MHz to 21 MHz. The time average of this serial bitstream output is proportional

to the analog input voltage. The Functional Block Diagram section shows a detailed block diagram of the

AMC1336. The 1.6-GΩ differential input resistance of the analog input stage supports low gain-error signal

sensing in high-voltage applications using resistive dividers. The external clock input simplifies the

synchronization of multiple current-sensing channels on the system level.

The silicon-dioxide (SiO₂)-based capacitive isolation barrier supports a high level of magnetic field immunity, as

described in the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at

www.ti.com.

7.2 Functional Block Diagram

AVDD

DVDD

Reinforced

Isolation

Barrier

AMC1336

AINP

AINN

ûꢀ Modulator

DOUT

Band-Gap

Reference

CLKIN

Charge

Pump

AVDD

Diagnostic

AGND

DGND

7.3 Feature Description

7.3.1 Analog Input

The AMC1336 incorporates front-end circuitry that contains an instrumentation amplifier, followed by a ΔΣ

modulator. To support a bipolar input range with a unipolar high-side supply AVDD, the device uses a charge

pump to simplify the overall system design and minimize circuit cost. For reduced offset and offset drift, the input

buffer is chopper-stabilized with the switching frequency set at f_CLKIN/ 32. 图 39 illustrates the spur created by the

switching frequency.

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Feature Description (接下页)

-20

-40

-60

-80

-100

-120

-140

-160

0.1

10 100

Frequency (kHz)

1000

10000

D037

sinc³filter, OSR = 1, f_CLKIN= 20 MHz, f_IN= 1 kHz

图 39. Quantization Noise Shaping

The linearity and noise performance of the device are ensured only when the differential analog input voltage

remains within the specified linear full-scale range (FSR), that is ±1 V, and within the specified input common-

mode range.

图 40 shows the specified common-mode input voltage that applies for the full-scale input voltage range as

specified in this document.

If smaller input signals are used, the operational common-mode input voltage range widens. 图 41 shows the

common-mode input voltage that applies with no differential input signal; that is, when the voltage applied on

AINP is equal to the voltage applied on AINN. The common-mode input voltage range scales with the actual

differential input voltage between this range and the range in 图 40.

Specified V_CM

Range

Specified V_CM

Range

-1

-2

-1

-2

3.25

3.5

3.75

4.25

4.5

5.5

3.25

3.5

3.75

4.25

4.5

5.5

VDD (V)

图 40. Common-Mode Input Voltage Range With a

图 41. Common-Mode Input Voltage Range With a

Clipping Differential Input Signal of ±1.25 V

Zero Differential Input Signal

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Feature Description (接下页)

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the

range AGND – 5 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input

electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are

ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR)

and within the specified input common-mode range.

7.3.2 Modulator

The modulator implemented in the AMC1336, as conceptualized in 图 42, is a second-order, switched-capacitor,

feed-forward ΔΣ modulator. The analog input voltage V_INand the output V₅of the 1-bit digital-to-analog converter

(DAC) are subtracted, providing an analog voltage V₁at the input of the first integrator stage. The output of the

first integrator feeds the input of the second integrator stage, resulting in an output voltage V₃that is

differentiated with the input signal V_INand the output of the first integrator V₂. Depending on the polarity of the

resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next

clock pulse by changing the associated analog output voltage V₅, causing the integrators to progress in the

opposite direction and forcing the value of the integrator output to track the average value of the input.

f_CLKIN

V₁

V₂

V₃

V₄

V_IN

Integrator 1

Integrator 2

ꢀ

CMP

0 V

V₅

DAC

图 42. Block Diagram of a Second-Order Modulator

As depicted in 图 39, the modulator shifts the quantization noise to high frequencies. Therefore, use a low-pass

digital filter at the output of the device to increase the overall performance. This filter is also used to convert from

the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's

microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter

structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1336. Furthermore, the

SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc

filters for a simple system-level solution for multichannel, isolated current sensing. An additional option is to use a

suitable application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-

programmable gate array (FPGA) can be used to implement the filter.

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Feature Description (接下页)

7.3.3 Isolation Channel Signal Transmission

The AMC1336 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream

across the capacitive SiO₂-based isolation barrier. The transmitter modulates the bitstream at TX IN in 图 43 with

an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and sends a no

signal to represent the digital zero. The receiver demodulates the signal after advanced signal conditioning and

produces the output. The symmetrical design of each isolation channel improves the common-mode transient

immunity (CMTI) performance and reduces the radiated emissions caused by the high-frequency carrier. 图 43

shows the block diagram of an isolation channel integrated in the AMC1336.

Transmitter

Receiver

OOK

Modulation

SiO₂-Based

Capacitive

Reinforced

Isolation

TX IN

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

RX OUT

Barrier

Oscillator

图 43. Block Diagram of an Isolation Channel

图 44 shows the concept of the on-off keying scheme.

TX IN

Carrier Signal Across

the Isolation Barrier

RX OUT

图 44. OOK-Based Modulation Scheme

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Feature Description (接下页)

7.3.4 Clock Input

The AMC1336 system clock is provided externally at the CLKIN pin. The clock signal must be applied

continuously for proper device operation.

To support the bipolar input voltage range with a unipolar high-side supply AVDD, the AMC1336 includes a

charge pump. This charge pump stops operating if the clock signal is below the specified frequency range or if

the signal is paused or missing. In that case, the input bias current increases beyond the specified range and

significantly reduces the input resistance of the device. When the clock signal is paused or missing, the

modulator stops the analog signal conversion and the digital output signal remains frozen in the last logic state.

When the clock signal is applied again after a pause, the internal analog circuitry biasing must settle for proper

device performance. In this case, consider the t_ASTARTspecification in the Switching Characteristics table.

7.3.5 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of

resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V

produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit

resolution. These input voltages are also the specified linear range of the AMC1336 with performance as

specified in this document. If the input voltage value exceeds this range, the output of the modulator shows

nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only

zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal

to 1.25 V. In this case, however, the AMC1336 generates a single 1 (if the input is at negative full-scale) or 0

every 128 clock cycles to indicate proper device function (see the AVDD Diagnostics and Fail-Safe Output

section for more details). 图 45 shows the input voltage versus the output modulator signal.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

图 45. Analog Input versus the AMC1336 Modulator Output

公式 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception of a

full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):

V_IN+ V_Clipping

2ì V_Clipping

(1)

The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN

pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.

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Feature Description (接下页)

The AMC1336 features a slew-rate-controlled output stage that reduces the over- and undershoots of the output

amplitude and radiated emissions of the DOUT line in the system. 图 46 and 图 47 show examples of rising and

falling edges of DOUT with different capacitive loads.

1.2

C_LOAD= 10 pF

C_LOAD= 15 pF

C_LOAD= 30 pF

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

C_LOAD= 10 pF

C_LOAD= 15 pF

C_LOAD= 30 pF

t (ns)

D035

D036

图 46. DOUT Rising Edge With Different Capacitive Loads

图 47. DOUT Falling Edge With Different Capacitive Loads

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7.4 Device Functional Modes

The AMC1336 is operational when the power supplies AVDD and DVDD, and the clock signal CLKIN are

applied, as specified in the Recommended Operating Conditions and Switching Characteristics tables.

7.4.1 Output Behavior in Case of a Full-Scale Input

图 48 shows that if a full-scale input signal is applied to the AMC1336 (that is, V_IN≥ V_Clipping), the device

generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being

sensed. This feature can be used for advanced system-level diagnostics to differentiate between system failures

caused by missing high-side supply AVDD or input overvoltage events.

CLKIN

...

DOUT

VIN ≤ -1.25 V

...

VIN ≥ 1.25 V

127 CLKIN cycles

图 48. Out-of-Range Output of the AMC1336

7.4.2 AVDD Diagnostics and Fail-Safe Output

In the case of a missing high-side supply voltage AVDD, the output of a ΔΣ modulator is not defined and can

cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. As shown

in 图 49, the AMC1336 implements an AVDD diagnostics and fail-safe output function that ensures that the

output DOUT of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD. Sample at

least 128 CLKIN cycles in order to distinguish a missing AVDD condition from an input underrange condition.

t_ASTART

CLKIN

...

AVDD

AVDD good

Missing AVDD

AVDD good

DOUT Valid bitstream

”0‘

Bitstream not valid

Valid bitstream

图 49. Fail-Safe Output of the AMC1336

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Digital Filter Usage

The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). 公式 2 shows a sinc³-type filter, which is a

very simple filter that is built with minimal effort and hardware:

-OSR

≈

’

1- z

H z =

( )

∆

1- z^-1

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an oversampling

ratio (OSR) of 256 and an output word width of 16 bits.

An example code for implementing a sinc³filter in an FPGA is discussed in the Combining the ADS1202 with an

FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for

download at www.ti.com.

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8.2 Typical Application

Isolated ΔΣ modulators are widely used in frequency inverter designs because of their high AC and DC

performance. Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string and

central inverters), uninterruptible power supplies (UPS), and other industrial applications.

图 50 shows a simplified schematic of a frequency inverter application with the AMC1336 used for the DC-link

and output phase voltage sensing. In this example, the ground reference point for the microcontroller is not

connected by any means to the power stage. This configuration is usually the case in systems with the

microcontroller located on a dedicated control card or PCB.

Current feedback is performed with shunt resistors (R_SHUNT) and TI's AMC1306M25 isolated modulators.

Depending on the system design, either all three or only two motor phase currents are sensed.

Depending on the overall digital processing power requirements and with a total of eight ΔΣ modulator bitstreams

to be processed by the microcontroller (MCU), a derivate from either the low-cost single-core TMS320F2807x or

the dual-core TMS320F2837x families can be used in this application.

+V_BUS

Load

I_DC

R_SHUNT

V_BUS

R_DC1

R_DC2

R_SHUNT

I_AC

R_SHUNT

R_AC1

3.3V_ISO7

3.3 V

AMC1306M25

AVDD

AINP

DVDD

DOUT

R_FLT

C_FLT

R_FLT

3.3 V_ISO6

R_AC2

AINN

CLKIN

R_DC3

AGND DGND

R_AC3

3.3 V

AMC1336

-V_BUS

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

3.3 V_ISO5

AINP

TMS320F28x7x

3.3 V_ISO3

3.3 V

SDFM1

SD1_D1

AMC1306M25

CLKIN

AINN

AGND DGND

AVDD

AINP

DVDD

DOUT

R_FLT

C_FLT

R_FLT

3.3 V_ISO2

SD1_D2

SD1_D3

SD1_D4

SD1_C1

SD1_C2

SD1_C3

SD1_C4

3.3 V

AMC1306M25

AINN

CLKIN

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

3.3 V_ISO4

AGND DGND

AINP

3.3 V

AMC1336

AINN

CLKIN

AGND DGND

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

AINP

SDFM2

SD2_D1

3.3 V

AMC1336

CLKIN

AINN

SD2_D2

SD2_D3

SD2_D4

SD2_C1

SD2_C2

SD2_C3

SD2_C4

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

AGND DGND

AINP

CLKIN

AINN

AGND DGND

3.3 V_ISO1

3.3 V

AMC1336

AVDD

DVDD

DOUT

R_FLT

C_FLT

R_FLT

AINP

CDCLVC1106

CLKIN

AINN

PWMx

AGND DGND

3.3 V

CLKIN

图 50. The AMC1336 in a Frequency Inverter Application

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

Typical Application (接下页)

图 51 shows an additional example of the AMC1336 used for input phase and DC-link voltage sensing. Also in

this case, the microcontroller is located on a dedicated control card and the AMC1306M25 is used for shunt-

based current sensing.

+V_BUS

R_DC1

R_DC2

R_DC3

R_SHUNT

Rectifier

Inverter

LOAD

R_SHUNT

-V_BUS

AMC1306M25

R_FLT

3.3 V_ISO8AVDD

AINP

AINN

DVDD 3.3 V

DOUT

CLKIN

C_FLT

AGND DGND

AMC1336

R_FLT

3.3 V_ISO7

3.3 V

AVDD

AINP

AINN

DVDD

DOUT

CLKIN

C_FLT

AGND DGND

AMC1306M25

R_FLT

3.3 V_ISO6

3.3 V

AVDD

AINP

AINN

DVDD

DOUT

CLKIN

C_FLT

AGND DGND

TMS320F28x7x

AMC1306M25

SDFM1

R_FLT

3.3 V_ISO5

3.3 V

AVDD

AINP

AINN

DVDD

DOUT

CLKIN

SD1_D1

SD1_D2

SD1_D3

SD1_D4

AGND DGND

AMC1306M25

SD1_C1

SD1_C2

SD1_C3

SD1_C4

R_AC1

R_AC2

R_AC3

R_FLT

3.3 V_ISO4AVDD

AINP

AINN

DVDD 3.3 V

DOUT

CLKIN

AGND DGND

AMC1336

SDFM2

R_FLT

3.3 V_ISO3AVDD

AINP

AINN

DVDD 3.3 V

DOUT

CLKIN

C_FLT

R_AC1

R_AC2

R_AC3

SD2_D1

SD2_D2

SD2_D3

SD2_D4

AGND DGND

AMC1336

SD2_C1

SD2_C2

SD2_C3

SD2_C4

R_FLT

3.3 V_ISO2

3.3 V

AVDD

AINP

AINN

DVDD

DOUT

CLKIN

R_AC1

R_AC2

R_AC3

AGND DGND

CDCLVC1106

AMC1336

PWMx

R_FLT

3.3 V_ISO1AVDD

AINP

AINN

DVDD 3.3 V

DOUT

CLKIN

AGND DGND

3.3 V

CLKIN

图 51. Input Phase Voltage Sensing Application with AMC1336

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

Typical Application (接下页)

8.2.1 Design Requirements

表 1 lists the parameters for this typical application.

表 1. Design Requirements

PARAMETER

VALUE

3.3 V

Supply voltage

Voltage drop across the sensing resistor R_DC1for a linear response

Voltage drop across the sensing resistors R_ACxfor a linear response

Current through the sensing resistors R_ACx

1 V (maximum)

±1 V (maximum)

±100 µA (maximum)

8.2.2 Detailed Design Procedure

Use Ohm's Law to calculate the minimum total resistance of the resistive dividers to limit the cross current to the

desired values:

•

For the voltage sensing on the DC bus: R_DC1+ R_DC2+ R_DC3= V_BUS/ I_DC

For the voltage sensing on the output phases U, V, and W: R_AC1+ R_AC2+ R_AC3= V_{PHASE (max)}/ I_AC

Consider the following two restrictions to choose the proper value of the resistors R_DC3and R_AC3

•

The voltage drop caused by the nominal voltage range of the system must not exceed the recommended

input voltage range of the AMC1336: V_xC3≤ V_FSR

•

The voltage drop caused by the maximum allowed system overvoltage must not exceed the input voltage that

causes a clipping output: V_xC3≤ V_Clipping

Use similar approach for calculation of the shunt resistor values R_SHUNTand see the AMC1306M25 data sheet

for further details.

表 2 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V on

the DC bus.

表 2. Resistor Value Examples for DC Bus Sensing

PARAMETER

600-V DC BUS

3.01 MΩ

10 kΩ

800-V DC BUS

4.22 MΩ

10.5 kΩ

Resistive divider resistor R_DC1

Resistive divider resistor R_DC2

Sense resistor R_DC3

Resulting current through resistive divider I_DC

Resulting voltage drop on sense resistor V_RDC3

99.5 µA

94.7 µA

0.995 V

0.994 V

表 3 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 230 V and 690 V on

the input or output phases.

表 3. Resistor Value Examples for Phase Voltage Sensing

PARAMETER

±400-V_ACPHASE

2.0 MΩ

±690-V_ACPHASE

3.48 MΩ

Resistive divider resistor R_AC1

Resistive divider resistor R_AC2

2.0 MΩ

3.48 MΩ

Sense resistor R_AC3

10.0 kΩ

Resulting current through resistive divider I_AC

Resulting voltage drop on sense resistor V_RAC3

99.8 µA

99.0 µA

±0.998 V

±0.990 V

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

Use a power supply with a nominal voltage of 3.3 V for DVDD to directly connect all modulators to the

microcontroller.

For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers

(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These MCU families support up to eight

channels of dedicated hardwired filter structures called sigma-delta filter modules (SDFMs) that significantly

simplify system level design by offering two filtering paths per channel: one providing high accuracy results for

the control loop and one that offers a fast response path for overcurrent detection. Use one of the pulse-width

modulation (PWM) sources inside the MCU to generate the clock for the modulators and for easy

synchronization of all feedback signals and the switching control of the gate drivers.

The application examples in 图 50 and 图 51 use a clock buffer to distribute the clock reference signal generated

on one of the PWMx outputs of the MCU to all modulators used in the circuit and as a reference for the digital

filters in the MCU. In this example, TI's CDCLVC1106 is used for this purpose. Each CDCLVC1106 output can

drive a load of 8 pF that is sufficient to drive up to two modulator and up to four SDFM clock inputs.

8.2.3 Application Curve

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. 图

52 shows the ENOB of the AMC1336 with different oversampling ratios. In this document, this number is

calculated from the SINAD by using following equation: SINAD = 1.76 dB + 6.02 × ENOB.

sinc³

sinc²

sinc¹

100

OSR

1000

10000

D034

图 52. Measured Effective Number of Bits versus Oversampling Ratio

8.2.4 What to Do and What Not to Do

Do not leave the inputs of the AMC1336 unconnected (floating) when the device is powered up. If either

modulator input is left floating, the input bias current can drive this input beyond the specified common-mode

input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes and the output

bitstream is not valid.

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

9 Power Supply Recommendations

In a typical frequency-inverter application, the high-side power supply (AVDD) for the AMC1336 is generated

from the controller-side supply (DVDD) of the device by an isolated dc/dc converter circuit. 图 53 shows a low-

cost solution based on the push-pull driver SN6501 and a transformer that supports the desired isolation voltage

ratings. TI recommends using a low-ESR decoupling capacitor of 0.1 µF and an additional capacitor of minimum

1 µF for both supplies of the AMC1336. Place these decoupling capacitors as close as possible to the device

power-supply pins to minimize supply current loops and electromagnetic emissions.

The AMC1336 does not require any specific power up sequencing. Consider the analog settling time t_ASTARTas

specified in the Switching Characteristics table after ramp up of the AVDD high-side supply.

Connect the high-side ground pin AGND of the AMC1336 to one of the analog inputs AINx to avoid common-

mode input voltage range violations.

AMC1336

AINP

AINN

DOUT

CLKIN

DVDD

AVDD

AGND

DVDD

DGND

10 …F 0.1 …F

0.1 …F 2.2 …F

DGND

AGND

TLV70450

OUT

SN6501

D1 VCC

10 …F

1 …F

20 V

GND

0.1 …F

D2 GND

AGND

10 …F

20 V

AGND

DGND

图 53. Decoupling the AMC1336

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

图 54 shows an example layout that is used on the AMC1336 evaluation module. For best performance, place

the smaller 0.1-µF decoupling capacitors (C7 and C9) as close as possible to the AMC1336 power-supply pins,

followed by the additional C1 and C11 capacitors with a minimum value of 1 µF. The resistors and capacitors

used for the analog input filter (R1, R2, C4, C5, and C8) are placed next to the decoupling capacitors. Use 1206-

size, SMD-type, ceramic decoupling capacitors and route the traces to the AINx pins underneath. Connect the

supply voltage sources in a way that allows the supply current to flow through the pads of the decoupling

capacitors before powering the device.

Consider use of RC filters on the digital clock and data lines to reduce reflections and slew rate that cause

radiated emissions. The AMC1336 evaluation module offers placeholders for RC filters (termed R8 and C13 in 图

54) for the CLKIN line, and R7 and C12 for the DOUT line.

10.2 Layout Example

Clearance area,

to be kept free of any

conductive materials

CLKIN

DOUT

图 54. Recommended Layout of the AMC1336

AMC1336

www.ti.com.cn

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

11.1.1.1 隔离相关术语

请参阅《隔离相关术语》

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《TMS320F28004x Piccolo™ 微控制器》数据表

德州仪器 (TI)，《TMS320F2807x Piccolo™ 微控制器》数据表

德州仪器 (TI)，《TMS320F2837xD 双核 Delfino™ 微控制器》数据表

德州仪器 (TI)，《ISO72x 数字隔离器磁场抗扰度》

德州仪器 (TI)，《MSP430F677x 多相位仪表计量片上系统》数据表

德州仪器 (TI)，《适用于二阶 Δ-Σ 调制器的 AMC1210 四路数字滤波器》数据表

德州仪器 (TI)，《将 ADS1202 与 FPGA 数字滤波器结合，以便在电机控制应用中进行电流测量》应用报告

德州仪器 (TI)，《具有高 CMTI 的 AMC1306x 小型、高精度、增强型隔离式 Δ-Σ 调制器》数据表

德州仪器 (TI)，《CDCLVC11xx 3.3V 和 2.5V LVCMOS 高性能时钟缓冲器系列》数据表

德州仪器 (TI)，《SN6501 用于隔离电源的变压器驱动器》数据表

德州仪器 (TI)，《AMC1303、AMC1306 和 AMC1336 评估模块》用户指南

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

AMC1336

ZHCSK30B –AUGUST 2019–REVISED APRIL 2020

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1336DWV

ACTIVE

SOIC

DWV

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

AMC1336

AMC1336DWVR

1000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1336DWVR

SOIC

DWV

1000

330.0

16.4

12.05 6.15

3.3

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DWV

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

AMC1336DWVR

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DWV SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

AMC1336DWV

505.46

13.94

4826

6.6

Pack Materials-Page 3

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AMC1336DWVR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E