AMC1336QDWVRQ1 [TI]
汽车类 ±1V 输入、精密电压检测增强型隔离式 Δ-Σ 调制器 | DWV | 8 | -40 to 125;
| 型号： | AMC1336QDWVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 ±1V 输入、精密电压检测增强型隔离式 Δ-Σ 调制器 | DWV | 8 | -40 to 125 |
| 文件： | 总40页 (文件大小：1667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AMC1336-Q1
SBASA51 –MAY 2020
AMC1336-Q1 Small, High-Precision, Reinforced Isolated Delta-Sigma Modulator
for Voltage Sensing Applications
1 Features
3 Description
The AMC1336-Q1 is a precision, delta-sigma (ΔΣ)
modulator with the output separated from the input
circuitry by a capacitive double isolation barrier that is
highly resistant to magnetic interference. This barrier
is certified to provide reinforced isolation of up to
8000 VPEAK according to the DIN VDE V 0884-11 and
UL1577 standards. Used in conjunction with isolated
power supplies, this isolated modulator separates
parts of the system that operate on different common-
mode voltage levels and protects lower-voltage parts
from damage.
1
•
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to 125°C, TA
–
•
•
Input structure optimized for voltage
measurements:
–
–
Input voltage range: ±1 V
Input resistance: 1.5 GΩ (typ)
Excellent DC performance:
–
–
–
–
Offset error: ±0.5 mV (max)
Offset drift: ±4 µV/°C (max)
Gain error: ±0.2% (max)
The unique wide, bipolar. ±1-V input voltage range of
theAMC1336-Q1 and its high input resistance support
direct connection of the device to resistive dividers in
high-voltage applications. When used with a digital
filter (for instance, as integrated in the
Gain drift: ±40 ppm/°C (max)
•
•
•
Transient immunity: 115 kV/µs (typ)
Missing high-side supply detection
Safety-related certifications:
TMS320F28004x,
TMS320F2807x,
or
TMS320F2837x microcontroller families) to decimate
the output bitstream, the device can achieve 16 bits
of resolution with a dynamic range of 87 dB at a data
rate of 82 kSPS.
–
8000-VPEAK reinforced isolation per DIN VDE V
0884-11: 2017-01
–
–
5700-VRMS isolation for 1 minute per UL1577
IEC 62368-1 end equipment standard
On the high-side, the AMC1336-Q1 is supplied by a
3.3-V or 5-V power supply. The isolated digital
interface operates from a 3.0-V, 3.3-V or 5-V power
supply.
2 Applications
•
Isolated AC and DC voltage measurement in:
The AMC1336-Q1 performance is specified over the
extended industrial temperature range of –40°C to
+125°C.
–
–
–
HEV/EV on-board chargers (OBC)
HEV/EV DC/DC converters
HEV/EV traction inverters
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
AMC1336-Q1
SOIC (8)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Phase1
3.3 V or 5.0 V
3.0 V, 3.3 V, or 5.0 V
AMC1336-Q1
DVDD
AVDD
R1
R2
R3
AVDD
Diagnostics
DGND
DOUT
CLKIN
AGND
AINP
TMS320F28x
SD-Dx
SD-Cx
PWMx
AINN
Phase2
or N
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1336-Q1
SBASA51 –MAY 2020
www.ti.com
Table of Contents
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Application .................................................. 25
Power Supply Recommendations...................... 29
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications............................................ 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety Limiting Values .............................................. 7
6.9 Electrical Characteristics........................................... 7
6.10 Switching Characteristics........................................ 9
6.11 Insulation Characteristics Curves ......................... 10
6.12 Typical Characteristics.......................................... 11
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
8
9
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 30
11 Device and Documentation Support ................. 31
11.1 Device Support...................................................... 31
11.2 Documentation Support ........................................ 31
11.3 Receiving Notification of Documentation Updates 31
11.4 Support Resources ............................................... 31
11.5 Trademarks........................................................... 31
11.6 Electrostatic Discharge Caution............................ 31
11.7 Glossary................................................................ 31
12 Mechanical, Packaging, and Orderable
7
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
May 2020
*
Initial release.
2
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5 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
AVDD
AINP
1
2
3
4
8
7
6
5
DVDD
CLKIN
DOUT
DGND
AINN
AGND
Not to scale
Pin Functions
PIN
I/O
NO.
NAME
DESCRIPTION
Analog (high-side) power supply, 3.0 V to 5.5 V.
1
AVDD
—
See the Power Supply Recommendations section for decoupling recommendations.
2
3
4
5
AINP
AINN
I
Noninverting analog input
I
Inverting analog input
AGND
DGND
—
—
Analog (high-side) ground reference
Digital (controller-side) ground reference
Modulator bitstream output, updated with the rising edge of the clock signal present on CLKIN. Use the rising
edge of the clock to latch the modulator bitstream at the input of the digital filter device.
6
7
8
DOUT
CLKIN
DVDD
O
I
Modulator clock input with internal pulldown resistor (typical value: 1 MΩ). The clock signal must be applied
continuously for proper device operation; see the Clock Input section for additional details.
Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
—
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
AVDD to AGND
6.5
6.5
Power-supply voltage
V
DVDD to DGND
–0.3
Analog input voltage
Digital input voltage
Digital output voltage
Input current
On the AINP and AINN pins
On the CLKIN pin
AGND – 5
DGND – 0.5
DGND – 0.5
–10
AVDD + 0.5
DVDD + 0.5
DVDD + 0.5
10
V
V
On the DOUT pin
V
Continuous, any pin except power-supply pins
Junction, TJ
mA
150
Temperature
°C
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1), HBM ESD classification Level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011, CDM ESD classification Level
C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD
DVDD
High-side supply voltage
Controller-side
AVDD to AGND
DVDD to DGND
3.0
2.7
5.0
3.3
5.5
5.5
V
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
VFSR
VIN = VAINP – VAINN
±1.25
V
V
V
Specified linear differential full-scale voltage
Absolute common-mode input voltage(1)
VIN = VAINP – VAINN
–1
–2
1
(VAINP + VAINN) / 2 to AGND
AVDD
(VAINP + VAINN) / 2 to AGND,
3.0 V ≤ AVDD < 4 V,
VAINP = VAINN
–1.4
–0.8
–1.4
–0.8
AVDD – 1.4
AVDD – 2.4
2.7
(VAINP + VAINN) / 2 to AGND,
3.0 V ≤ AVDD < 4.5 V,
|VAINP – VAINN| = 1.25 V
VCM
Operating common-mode input voltage(2)
V
(VAINP + VAINN) / 2 to AGND,
4 V ≤ AVDD ≤ 5.5 V,
VAINP = VAINN
(VAINP + VAINN) / 2 to AGND,
4.5 V ≤ AVDD ≤ 5.5 V,
|VAINP – VAINN| = 1.25 V
2.1
DIGITAL INPUT
Input voltage
TEMPERATURE RANGE
TA Operating ambient temperature
VCLKIN to DGND
DGND
–40
DVDD
125
V
25
°C
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) See the Analog Input section for more details.
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6.4 Thermal Information
AMC1336-Q1
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
94
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36
Junction-to-board thermal resistance
46.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
11.5
ψJB
44.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
AVDD = DVDD = 5.5 V
VALUE
90.75
50.4
57.75
32.4
33
UNIT
PD
Maximum power dissipation (both sides)
mW
AVDD = DVDD = 3.6 V
AVDD = 5.5 V
PD1
PD2
Maximum power dissipation (high-side supply)
mW
mW
AVDD = 3.6 V
DVDD = 5.5 V
Maximum power dissipation (controller-side supply)
DVDD = 3.6 V
18
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
External creepage(1)
Distance through insulation
Comparative tracking index
Material group
Shortest pin-to-pin distance through air
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double insulation
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 8.5
≥ 8.5
≥ 0.021
≥ 600
I
mm
mm
mm
V
CPG
DTI
CTI
Rated mains voltage ≤ 600 VRMS
I-IV
Overvoltage category
per IEC 60664-1
Rated mains voltage ≤ 1000 VRMS
I-III
DIN VDE V 0884-11: 2017-01(2)
Maximum repetitive peak
isolation voltage
VIORM
At AC voltage
2121
VPK
At AC voltage (sine wave); see Figure 5
At DC voltage
1500
2121
8000
9600
VRMS
VDC
Maximum-rated isolation
working voltage
VIOWM
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
VIOTM
VPK
VPK
isolation voltage
Maximum surge
VIOSM
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
≤ 5
≤ 5
≤ 5
~1
isolation voltage(3)
Method a, after input/output safety test subgroups 2 & 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
pF
> 1012
> 1011
> 109
VIO = 500 V at TA = 25°C
Insulation resistance,
input to output(5)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5700
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
6
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11: 2017-01,
DIN EN 62368-1: 2016-05, EN 62368-1: 2014,
and IEC 62368-1: 2014
Recognized under 1577 component recognition
Reinforced insulation
Single protection
Certificate number: 40040142
File number: pending
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 94°C/W, TJ = 150°C, TA = 25°C,
241
AVDD = DVDD = 5.5 V, see Figure 3
θJA = 94°C/W, TJ = 150°C, TA = 25°C,
AVDD = DVDD = 3.6 V, see Figure 3
θJA = 94°C/W, TJ = 150°C, TA = 25°C,
Safety input, output,
or supply current
IS
mA
R
369
Safety input, output,
or total power(1)
R
PS
TS
1329
150
mW
°C
see Figure 4
Maximum safety temperature
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × AVDDmax + IS × DVDDmax, where AVDDmax is the maximum high-side voltage and DVDDmax is the maximum controller-side
supply voltage.
6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and
fCLKIN = 20 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
Differential input resistance
Single-ended input capacitance
Differential input capacitance
Input bias current
AINN = AGND
0.1
1.5
1.5
2
GΩ
GΩ
pF
RIND
CIN
0.16
AINN = AGND, fCLKIN = 20 MHz
fCLKIN = 20 MHz
CIND
IIB
2
pF
AINP = AINN = AGND; IIB = (IAINP + IAINN) / 2
AINP = AINN = AGND; IIB = (IAINP + IAINN) / 2
IIO = IAINP – IAINN
–10
±3
10
5
nA
TCIIB
IIO
Input bias current drift
–14
±1
pA/°C
nA
Input offset current
–5
80
CMTI
Common-mode transient immunity
|AGND – DGND| = 1 kV
115
kV/µs
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and
fCLKIN = 20 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
Decimation filter output set to 16 bits
Resolution: 16 bits
16
–4
Bit
LSB
mV
INL
Integral nonlinearity(1)
±1.6
±0.03
±0.6
4
0.5
4
EO
Offset error
Initial, at TA = 25°C, AINP = AINN = AGND
–0.5
–4
TCEO
Offset error drift(2)
µV/°C
Initial, at TA = 25°C,
VAINP = 1 V or VAINN = –1 V, AINN = AGND
EG
Gain error(3)
–0.2
–40
±0.02
0.2
40
%
TCEG
Gain error drift(4)
±20
–104
–96
ppm/°C
AINP = AINN, fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max
AINP = AINN, fIN = 10 kHz, –0.5 V ≤ VIN ≤ 0.5 V
PSRR vs AVDD, at DC
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
–83
PSRR vs AVDD, 100-mV and 10-kHz ripple
–83
AC ACCURACY
SNR
Signal-to-noise ratio
VIN = 2 VPP, fIN = 1 kHz
VIN = 2 VPP, fIN = 1 kHz
82
79
87
85
dB
dB
SINAD
Signal-to-noise + distortion
Total harmonic distortion
Spurious-free dynamic range
VIN = 2 VPP, fIN = 1 kHz; single-ended input (AINN
= AGND = 0V)
-91
-80
-78
dB
THD
VIN = 2 VPP, fIN = 1 kHz; Differential input over full
CM range
-92
92
dB
dB
SFDR
VIN = 2 VPP, fIN = 1 kHz
80
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
IIN
Input current
DGND ≤ VIN ≤ DVDD
7
µA
pF
V
CIN
VIH
VIL
Input capacitance
High-level input voltage
Low-level input voltage
4
0.7 x DVDD
–0.3
DVDD + 0.3
0.3 x DVDD
V
DIGITAL OUTPUT (CMOS)
CLOAD Output load capacitance
fCLKIN = 21 MHz
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
15
30
pF
V
DVDD – 0.1
DVDD – 0.4
VOH
High-level output voltage
Low-level output voltage
0.1
0.4
VOL
V
IOL = 4 mA
POWER SUPPLY
AVDDPOR AVDD power-on reset threshold voltage AVDD falling
2.4
2.6
6.8
7.8
3.4
3.7
2.8
9
V
3 V ≤ AVDD ≤ 3.6 V
IAVDD
High-side supply current
mA
4.5 V ≤ AVDD ≤ 5.5 V
10.5
5
2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF
4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF
IDVDD
Controller-side supply current
mA
6
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(2) Offset error drift is calculated using the box method, as described by the following equation:
TCEO = (valueMAX - valueMIN) / TempRange
(3) The typical value includes one sigma statistical variation.
(4) Gain error drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((valueMAX - valueMIN) / (value x TempRange)) x 106.
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
9
TYP
20
MAX
21
UNIT
3.0 V ≤ AVDD ≤ 5.5 V
4.5 V ≤ AVDD ≤ 5.5 V
fCLKIN
CLKIN clock frequency
MHz
5
20
21
CLKIN duty cycle
40%
3.5
50%
60%
tH1
tD1
DOUT hold time after rising edge of CLKIN
Rising edge of CLKIN to DOUT valid delay
CLOAD = 15 pF
ns
ns
CLOAD = 15 pF
15
6
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V, CLOAD = 15 pF
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V, CLOAD = 15 pF
AVDD step to 3.0 V; 0.1%-settling, clock applied
2.5
3.2
tr
tf
DOUT rise time
DOUT fall time
ns
6
2.2
6
ns
2.9
6
tASTART Analog start-up time
0.25
ms
tCLKIN
tHIGH
CLKIN
tLOW
tH
tD
tr / tf
DOUT
Figure 1. Digital Interface Timing
AVDD
DVDD
tASTART
CLKIN
DOUT
...
Bitstream not valid (analog settling)
Valid bitstream
Figure 2. Device Start-Up Timing
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6.11 Insulation Characteristics Curves
400
1600
1400
1200
1000
800
600
400
200
0
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
350
300
250
200
150
100
50
0
0
25
50
75
100
TA (°C)
125
150
175
200
0
25
50
75
100
TA (°C)
125
150
175
200
D001
D002
Figure 3. Thermal Derating Curve for Safety-Limiting
Current per VDE
Figure 4. Thermal Derating Curve for Safety-Limiting
Power per VDE
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
87.5%
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
1.E+1
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS
)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
Figure 5. Reinforced Isolation Capacitor Lifetime Projection
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6.12 Typical Characteristics
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
4
3
10
7.5
5
2
1
2.5
0
0
-1
-2
-3
-4
-2.5
-5
-7.5
-10
-0.65 -0.3
0.05
0.4
0.75
VCM (V)
1.1
1.45
1.8
2.15
-1
-0.75 -0.5 -0.25
0
VIN (mV)
0.25
0.5
0.75
1
D003
D004
Figure 6. Input Bias Current vs
Common-Mode Input Voltage
Figure 7. Integral Nonlinearity vs
Input Voltage
4
3.5
3
40
35
30
25
20
15
10
5
2.5
2
1.5
1
0.5
0
0
D038
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
EO (mV)
D005
Figure 9. Offset Error Histogram
Figure 8. Integral Nonlinearity vs Temperature
0.5
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Device 1
Device 2
Device 3
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D006
D007
Figure 10. Offset Error vs High-Side Supply Voltage
Figure 11. Offset Error vs Temperature
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Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
30
25
20
15
10
5
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
D039
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
EG (%)
D008
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 13. Gain Error Histogram
Figure 12. Offset Error vs Clock Frequency
0.25
0.2
0.5
0.4
0.3
0.2
0.1
0
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.1
-0.2
-0.3
-0.4
-0.5
Device 1
Device 2
Device 3
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D011
D012
Figure 14. Gain Error vs High-Side Supply Voltage
Figure 15. Gain Error vs Temperature
0
-20
0.25
OSR = 8
OSR = 256
0.2
0.15
0.1
-40
-60
0.05
0
-80
-0.05
-0.1
-0.15
-0.2
-0.25
-100
-120
-140
-160
5
7
9
11
13
fCLKIN (MHz)
15
17
19
21
0.01
0.1
1
10
100
1000
fIN (kHz)
D013
D009
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 16. Gain Error vs Clock Frequency
Figure 17. Common-Mode Rejection Ratio vs
Input Signal Frequency
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Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
0
91
89
87
85
83
81
79
77
SNR
SINAD
-20
-40
-60
-80
-100
-120
-140
-160
0.01
0.1
1
10
100
1000
3
3.5
4
4.5
AVDD (V)
5
5.5
fRIPPLE (kHz)
D010
D014
Figure 18. Power-Supply Rejection Ratio vs
Ripple Frequency
Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs High-Side Supply Voltage
91
89
87
85
83
81
79
77
91
89
87
85
83
81
SNR
SINAD
79
SNR
SINAD
77
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
5
7
9
11
13
fCLKIN (MHz)
15
17
19 21
D015
D016
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 20. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Temperature
Figure 21. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Clock Frequency
100
91
89
87
85
83
81
79
77
SNR
SINAD
95
90
85
80
75
70
65
60
55
50
SNR
SINAD
75
73
0.01
0.1
1
fIN (kHz)
10
100
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
D017
D018
Figure 22. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Input Signal Frequency
Figure 23. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Input Signal Amplitude
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Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
-76
-76
-80
-80
-84
-84
-88
-88
-92
-92
-96
-96
-100
-104
-100
-104
3
3.5
4
4.5
AVDD (V)
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D019
D020
Figure 24. Total Harmonic Distortion vs
High-Side Supply Voltage
Figure 25. Total Harmonic Distortion vs Temperature
-76
-80
-76
-80
-84
-84
-88
-88
-92
-92
-96
-96
-100
-104
-100
-104
5
7
9
11
13
fCLKIN (MHz)
15
17
19
21
0.01
0.1
1
10
fIN (kHz)
D021
D022
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 26. Total Harmonic Distortion vs Clock Frequency
Figure 27. Total Harmonic Distortion vs
Input Signal Frequency
-80
-84
112
108
104
100
96
-88
-92
-96
92
-100
-104
-108
88
84
80
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
3
3.5
4
4.5
AVDD (V)
5
5.5
D023
D024
Figure 28. Total Harmonic Distortion vs
Input Signal Amplitude
Figure 29. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
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Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
112
108
104
100
96
112
108
104
100
96
92
92
88
88
84
84
80
80
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
5
7
9
11
13
fCLKIN (MHz)
15
17
19
21
D025
D026
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 30. Spurious-Free Dynamic Range vs Temperature
Figure 31. Spurious-Free Dynamic Range vs
Clock Frequency
112
108
104
100
96
109
105
101
97
93
92
89
88
85
84
81
77
80
0.01
0.1
1
10
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
fIN (kHz)
D027
D028
Figure 32. Spurious-Free Dynamic Range vs
Input Signal Frequency
Figure 33. Spurious-Free Dynamic Range vs
Input Signal Amplitude
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
Frequency (kHz)
20
25
30
35
40
0
5
10
15
Frequency (kHz)
20
25
30
35
40
D029
D030
156,250-point DFT, VIN = 2 VPP
156,250-point DFT, VIN = 2 VPP
Figure 35. Frequency Spectrum with 10-kHz Input Signal
Figure 34. Frequency Spectrum with 1-kHz Input Signal
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Typical Characteristics (continued)
at AVDD = 5 V, DVDD = 3.3 V, AINP = –1 V to 1 V, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with OSR = 256 (unless
otherwise noted)
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
10.5
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
IAVDD
IDVDD
IAVDD vs AVDD
IDVDD vs DVDD
2.7
3.1
3.5
3.9
xVDD (V)
4.3
4.7
5.1
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D031
D032
Figure 36. Supply Current vs Supply Voltage
Figure 37. Supply Current vs Temperature
10.5
IAVDD
IDVDD
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
5
7
9
11
13
fCLKIN (MHz)
15
17
19
21
D033
fCLKIN < 9 MHz with AVDD ≥ 4.5 V only
Figure 38. Supply Current vs Clock Frequency
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7 Detailed Description
7.1 Overview
The differential analog input (comprised of input signals AINP and AINN) of the AMC1336-Q1 is a chopper-
stabilized instrumentation amplifier, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ)
modulator stage that digitizes the input signal into a 1-bit output stream. The data output DOUT of the converter
provides a stream of digital ones and zeros that is synchronous to the externally provided clock source at the
CLKIN pin with a frequency in the range of 5 MHz to 21 MHz. The time average of this serial bitstream output is
proportional to the analog input voltage. The Functional Block Diagram section shows a detailed block diagram of
the AMC1336-Q1. The 1.6-GΩ differential input resistance of the analog input stage supports low gain-error
signal sensing in high-voltage applications using resistive dividers. The external clock input simplifies the
synchronization of multiple current-sensing channels on the system level.
The silicon-dioxide (SiO2)-based capacitive isolation barrier supports a high level of magnetic field immunity, as
described in the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at
www.ti.com.
7.2 Functional Block Diagram
AVDD
DVDD
Reinforced
Isolation
Barrier
AMC1336-Q1
AINP
AINN
ûꢀ Modulator
DOUT
Band-Gap
Reference
CLKIN
Charge
Pump
AVDD
Diagnostic
AGND
DGND
7.3 Feature Description
7.3.1 Analog Input
The AMC1336-Q1 incorporates front-end circuitry that contains an instrumentation amplifier, followed by a ΔΣ
modulator. To support a bipolar input range with a unipolar high-side supply AVDD, the device uses a charge
pump to simplify the overall system design and minimize circuit cost. For reduced offset and offset drift, the input
buffer is chopper-stabilized with the switching frequency set at fCLKIN / 32. Figure 39 illustrates the spur created
by the switching frequency.
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Feature Description (continued)
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10 100
Frequency (kHz)
1000
10000
D037
sinc3 filter, OSR = 1, fCLKIN = 20 MHz, fIN = 1 kHz
Figure 39. Quantization Noise Shaping
The linearity and noise performance of the device are ensured only when the differential analog input voltage
remains within the specified linear full-scale range (FSR), that is ±1 V, and within the specified input common-
mode range.
Figure 40 shows the specified common-mode input voltage that applies for the full-scale input voltage range as
specified in this document.
If smaller input signals are used, the operational common-mode input voltage range widens. Figure 41 shows the
common-mode input voltage that applies with no differential input signal; that is, when the voltage applied on
AINP is equal to the voltage applied on AINN. The common-mode input voltage range scales with the actual
differential input voltage between this range and the range in Figure 40.
4
3
2
1
0
4
3
2
1
0
Specified VCM
Range
Specified VCM
Range
-1
-2
-1
-2
3
3.25
3.5
3.75
4
4.25
4.5
5
5.5
3
3.25
3.5
3.75
4
4.25
4.5
5
5.5
VDD (V)
VDD (V)
Figure 40. Common-Mode Input Voltage Range With a
Clipping Differential Input Signal of ±1.25 V
Figure 41. Common-Mode Input Voltage Range With a
Zero Differential Input Signal
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Feature Description (continued)
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range AGND – 5 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are
ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR)
and within the specified input common-mode range.
7.3.2 Modulator
The modulator implemented in the AMC1336-Q1, as conceptualized in Figure 42, is a second-order, switched-
capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog
converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator stage. The
output of the first integrator feeds the input of the second integrator stage, resulting in an output voltage V3 that is
differentiated with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the
resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next
clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the
opposite direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
V3
V4
VIN
Integrator 1
Integrator 2
ꢀ
ꢀ
CMP
0 V
V5
DAC
Figure 42. Block Diagram of a Second-Order Modulator
As depicted in Figure 39, the modulator shifts the quantization noise to high frequencies. Therefore, use a low-
pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert
from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter
structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1336-Q1. Furthermore,
the SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated sinc
filters for a simple system-level solution for multichannel, isolated current sensing. Alternatively, a field-
programmable gate array (FPGA) can be used to implement the filter.
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Feature Description (continued)
7.3.3 Isolation Channel Signal Transmission
The AMC1336-Q1 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the capacitive SiO2-based isolation barrier. The transmitter modulates the bitstream at TX IN in Figure 43
with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and sends a
no signal to represent the digital zero. The receiver demodulates the signal after advanced signal conditioning
and produces the output. The symmetrical design of each isolation channel improves the common-mode
transient immunity (CMTI) performance and reduces the radiated emissions caused by the high-frequency
carrier. Figure 43 shows the block diagram of an isolation channel integrated in the AMC1336-Q1.
Transmitter
Receiver
OOK
Modulation
SiO2-Based
Capacitive
Reinforced
Isolation
TX IN
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
RX OUT
Barrier
Oscillator
Figure 43. Block Diagram of an Isolation Channel
Figure 44 shows the concept of the on-off keying scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 44. OOK-Based Modulation Scheme
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Feature Description (continued)
7.3.4 Clock Input
The AMC1336-Q1 system clock is provided externally at the CLKIN pin. The clock signal must be applied
continuously for proper device operation.
To support the bipolar input voltage range with a unipolar high-side supply AVDD, the AMC1336-Q1 includes a
charge pump. This charge pump stops operating if the clock signal is below the specified frequency range or if
the signal is paused or missing. In that case, the input bias current increases beyond the specified range and
significantly reduces the input resistance of the device. When the clock signal is paused or missing, the
modulator stops the analog signal conversion and the digital output signal remains frozen in the last logic state.
When the clock signal is applied again after a pause, the internal analog circuitry biasing must settle for proper
device performance. In this case, consider the tASTART specification in the Switching Characteristics table.
7.3.5 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of
resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V
produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit
resolution. These input voltages are also the specified linear range of the AMC1336-Q1 with performance as
specified in this document. If the input voltage value exceeds this range, the output of the modulator shows
nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only
zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal
to 1.25 V. In this case, however, the AMC1336-Q1 generates a single 1 (if the input is at negative full-scale) or 0
every 128 clock cycles to indicate proper device function (see the AVDD Diagnostics and Fail-Safe Output
section for more details). Figure 45 shows the input voltage versus the output modulator signal.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 45. Analog Input versus the AMC1336-Q1 Modulator Output
Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception
of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN + VClipping
2ì VClipping
(1)
The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN
pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.
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Feature Description (continued)
The AMC1336-Q1 features a slew-rate-controlled output stage that reduces the over- and undershoots of the
output amplitude and radiated emissions of the DOUT line in the system. Figure 46 and Figure 47 show
examples of rising and falling edges of DOUT with different capacitive loads.
1.2
1
1.2
1
CLOAD = 10 pF
CLOAD = 15 pF
CLOAD = 30 pF
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
CLOAD = 10 pF
CLOAD = 15 pF
CLOAD = 30 pF
0
2
4
6
8
10
t (ns)
12
14
16
18
20
0
2
4
6
8
10
t (ns)
12
14
16
18
20
D035
D036
Figure 46. DOUT Rising Edge With Different Capacitive
Loads
Figure 47. DOUT Falling Edge With Different Capacitive
Loads
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7.4 Device Functional Modes
The AMC1336-Q1 is operational when the power supplies AVDD and DVDD, and the clock signal CLKIN are
applied, as specified in the Recommended Operating Conditions and Switching Characteristics tables.
7.4.1 Output Behavior in Case of a Full-Scale Input
Figure 48 shows that if a full-scale input signal is applied to the AMC1336-Q1 (that is, VIN ≥ VClipping), the device
generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being
sensed. This feature can be used for advanced system-level diagnostics to differentiate between system failures
caused by missing high-side supply AVDD or input overvoltage events.
CLKIN
...
...
DOUT
DOUT
VIN ≤ -1.25 V
...
...
...
...
VIN ≥ 1.25 V
127 CLKIN cycles
127 CLKIN cycles
Figure 48. Out-of-Range Output of the AMC1336-Q1
7.4.2 AVDD Diagnostics and Fail-Safe Output
In the case of a missing high-side supply voltage AVDD, the output of a ΔΣ modulator is not defined and can
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable. As shown
in Figure 49, the AMC1336-Q1 implements an AVDD diagnostics and fail-safe output function that ensures that
the output DOUT of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD. Sample at
least 128 CLKIN cycles in order to distinguish a missing AVDD condition from an input underrange condition.
tASTART
CLKIN
...
AVDD
AVDD good
Missing AVDD
AVDD good
DOUT Valid bitstream
”0‘
Bitstream not valid
Valid bitstream
Figure 49. Fail-Safe Output of the AMC1336-Q1
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). Equation 2 shows a sinc3-type filter, which
is a very simple filter that is built with minimal effort and hardware:
3
-OSR
≈
’
1- z
H z =
( )
∆
∆
÷
÷
1- z-1
«
◊
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling
ratio (OSR) of 256 and an output word width of 16 bits.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
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8.2 Typical Application
Isolated ΔΣ modulators are widely used in onboard charger (OBC) and traction inverter designs because of their
high AC and DC performance. The input structure of the AMC1336-Q1 is optimized for use with high-impedance
resistor dividers. The ±1-V, differential input enables sensing of positive and negative voltages in the system.
Figure 50 shows a simplified schematic of a traction inverter application with the AMC1336-Q1 used for output
phase voltage sensing. In this example, the ground reference point for the microcontroller is not connected by
any means to the power stage. This configuration is usually the case in systems with the microcontroller located
on a dedicated control card or PCB.
Current feedback is performed with shunt resistors (RSHUNT) and TI's AMC1305M05-Q1 isolated modulators.
Depending on the system design, either all three or only two motor phase currents are sensed.
Depending on the overall digital processing power requirements and with a total of eight ΔΣ modulator bitstreams
to be processed by the microcontroller (MCU), a derivate from either the low-cost single-core TMS320F2807x or
the dual-core TMS320F2837x families can be used in this application.
Inverter
+VBUS
RSHUNT,U
U
V
W
RSHUNT,V
M
RSHUNT,W
VISO2
3.3 V
AMC1305-Q1
RAC1,U
RAC2,V
RAC3,W
RAC1,U
RAC2,V
RAC3,W
RAC1,U
RAC2,V
RAC3,W
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
VISO3
3.3 V
AMC1305-Q1
AVDD
DVDD
DOUT
CLKIN
DGND
œ VBUS
AINP
AINN
AGND
TMS320F28x7x
SD1_D1
SD1_C1
SD1_D2
SD1_C2
SD1_D3
SD1_C3
PWMx
VISO4
3.3 V
AMC1305-Q1
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
SD2_D1
SD2_C1
SD2_D2
SD2_C2
SD2_D3
SD2_C3
VISO1
3.3 V
AMC1336-Q1
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
VISO1
3.3 V
AMC1336-Q1
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
VISO1
3.3 V
AMC1336-Q1
AVDD
DVDD
AINP
AINN
AGND
DOUT
CLKIN
DGND
Figure 50. The AMC1336-Q1 in a Frequency Inverter Application
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Typical Application (continued)
Figure 51 shows an additional example of the AMC1336-Q1 used for DC-link and VBUS voltage sensing in an
onboard charger. Also in this case, the microcontroller is located on a dedicated control card and the
AMC1305M05-Q1 is used for shunt-based current sensing.
RSHUNT,DC
RSHUNT,BUS
+ VBUS
DC-Link
PFC
DC/DC
RDC1
RDC2
RDC3
RBUS1
RBUS2
RBUS3
L1
L2
L3
To Battery Management System
N
œ VBUS
VISO2
3.3 V
VISO4
3.3 V
AMC1305-Q1
AMC1305-Q1
TMS320F28x7x
AVDD
DVDD
DOUT
CLKIN
DGND
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
AINP
AINN
AGND
SD1_D1
SD1_C1
SD1_D2
SD1_C2
PWMx
VISO1
3.3 V
VISO3
3.3 V
AMC1336-Q1
AMC1336-Q1
SD2_D1
SD2_C1
SD2_D2
SD2_C2
AVDD
DVDD
DOUT
CLKIN
DGND
AVDD
DVDD
DOUT
CLKIN
DGND
AINP
AINN
AGND
AINP
AINN
AGND
Figure 51. The in an On-Board Charger Application
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 lists the parameters for this typical application.
Table 1. Design Requirements
PARAMETER
VALUE
3.3 V
Supply voltage
Voltage drop across the sensing resistor RDC1 for a linear response
Voltage drop across the sensing resistors RAC3 for a linear response
Current through the sensing resistors RACx
1 V (maximum)
±1 V (maximum)
±100 µA (maximum)
8.2.2 Detailed Design Procedure
Use Ohm's Law to calculate the minimum total resistance of the resistive dividers to limit the cross current to the
desired values:
•
•
For the voltage sensing on the DC bus: RDC1 + RDC2 + RDC3 = VBUS / IDC
For the voltage sensing on the output phases U, V, and W: RAC1 + RAC2 + RAC3 = VPHASE (max) / IAC
Consider the following two restrictions to choose the proper value of the resistors RDC3 and RAC3
:
•
The voltage drop caused by the nominal voltage range of the system must not exceed the recommended
input voltage range for a linear response of the AMC1336-Q1: VxC3 ≤ VFSR
•
The voltage drop caused by the maximum allowed system overvoltage must not exceed the input voltage that
causes a clipping output: VxC3 ≤ VClipping
Use similar approach for calculation of the shunt resistor values RSHUNT and see the AMC1305M05-Q1 for further
details.
Table 2 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V
on the DC bus.
Table 2. Resistor Value Examples for DC Bus Sensing
PARAMETER
600-V DC BUS
3.01 MΩ
3.01 MΩ
10 kΩ
800-V DC BUS
4.22 MΩ
4.22 MΩ
10.5 kΩ
Resistive divider resistor RDC1
Resistive divider resistor RDC2
Sense resistor RDC3
Resulting current through resistive divider IDC
Resulting voltage drop on sense resistor VRDC3
99.5 µA
94.7 µA
0.995 V
0.994 V
Table 3 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 230 V and 690 V
on the input or output phases.
Table 3. Resistor Value Examples for Phase Voltage Sensing
PARAMETER
±400-VAC PHASE
2.0 MΩ
±690-VAC PHASE
3.48 MΩ
Resistive divider resistor RAC1
Resistive divider resistor RAC2
2.0 MΩ
3.48 MΩ
Sense resistor RAC3
10.0 kΩ
10.0 kΩ
Resulting current through resistive divider IAC
Resulting voltage drop on sense resistor VRAC3
99.8 µA
99.0 µA
±0.998 V
±0.990 V
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Use a power supply with a nominal voltage of 3.3 V for DVDD to directly connect all modulators to the
microcontroller.
For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers
(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These MCU families support up to eight
channels of dedicated hardwired filter structures called sigma-delta filter modules (SDFMs) that significantly
simplify system level design by offering two filtering paths per channel: one providing high accuracy results for
the control loop and one that offers a fast response path for overcurrent detection. Use one of the pulse-width
modulation (PWM) sources inside the MCU to generate the clock for the modulators and for easy
synchronization of all feedback signals and the switching control of the gate drivers.
8.2.3 Input Filter Design
TI recommends placing an RC filter in front of a ΔΣ modulator to improve signal-to-noise performance of the
signal path. Design the input filter such that:
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency of the
ΔΣ modulator
•
•
The DC impedance of the filter does not generate significant voltage drop in the analog input lines
The source impedance of the analog inputs are equal
For most applications, the structure shown in Figure 52 achieves excellent performance.
10 Ω
8.2 nF
AINP
AINN
AMC1336-Q1
10 Ω
AGND
Figure 52. Differential Input Filter
8.2.4 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
Figure 53 shows the ENOB of the AMC1336-Q1 with different oversampling ratios. In this document, this number
is calculated from the SINAD by using following equation: SINAD = 1.76 dB + 6.02 × ENOB.
16
14
12
10
8
6
4
sinc3
sinc2
sinc1
2
0
1
10
100
OSR
1000
10000
D034
Figure 53. Measured Effective Number of Bits versus Oversampling Ratio
8.2.5 What to Do and What Not to Do
Do not leave the inputs of the AMC1336-Q1 unconnected (floating) when the device is powered up. If either
modulator input is left floating, the input bias current can drive this input beyond the specified common-mode
input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes and the output
bitstream is not valid.
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9 Power Supply Recommendations
In a typical frequency-inverter application, the high-side power supply (AVDD) for the AMC1336-Q1 is generated
from the controller-side supply (DVDD) of the device by an isolated dc/dc converter circuit. Figure 54 shows a
low-cost solution based on the push-pull driver SN6501 and a transformer that supports the desired isolation
voltage ratings. TI recommends using a low-ESR decoupling capacitor of 0.1 µF and an additional capacitor of
minimum 1 µF for both supplies of the AMC1336-Q1. Place these decoupling capacitors as close as possible to
the device power-supply pins to minimize supply current loops and electromagnetic emissions.
The AMC1336-Q1 does not require any specific power up sequencing. Consider the analog settling time tASTART
as specified in the Switching Characteristics table after ramp up of the AVDD high-side supply.
Connect the high-side ground pin AGND of the AMC1336-Q1 to one of the analog inputs AINx to avoid common-
mode input voltage range violations.
AMC1336-Q1
AINP
AINN
DOUT
CLKIN
DVDD
AVDD
AVDD
AGND
DVDD
DGND
10 …F 0.1 …F
0.1 …F 2.2 …F
DGND
AGND
TPS76350-Q1
OUT IN
GND EN
SN6501-Q1
D1 VCC
4.7 …F
1 …F
20 V
0.1 …F
D2 GND
AGND
10 …F
20 V
AGND
DGND
Figure 54. Decoupling the AMC1336-Q1
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10 Layout
10.1 Layout Guidelines
Figure 55 shows an example layout that is used on the AMC1336-Q1 evaluation module. For best performance,
place the smaller 0.1-µF decoupling capacitors (C7 and C9) as close as possible to the AMC1336-Q1 power-
supply pins, followed by the additional C1 and C11 capacitors with a minimum value of 1 µF. The resistors and
capacitors used for the analog input filter (R1, R2, C4, C5, and C8) are placed next to the decoupling capacitors.
Use 1206-size, SMD-type, ceramic decoupling capacitors and route the traces to the AINx pins underneath.
Connect the supply voltage sources in a way that allows the supply current to flow through the pads of the
decoupling capacitors before powering the device.
Consider use of RC filters on the digital clock and data lines to reduce reflections and slew rate that cause
radiated emissions. The AMC1336-Q1 evaluation module offers placeholders for RC filters (termed R8 and C13
in Figure 55) for the CLKIN line, and R7 and C12 for the DOUT line.
10.2 Layout Example
Clearance area,
to be kept free of any
conductive materials
Figure 55. Recommended Layout of the AMC1336-Q1
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Isolation Glossary
See the Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
Texas Instruments, TMS320F28004x Piccolo™ Microcontrollers data sheet
Texas Instruments, TMS320F2807x Piccolo™ Microcontrollers data sheet
Texas Instruments, TMS320F2837xD Dual-Core Delfino™ Microcontrollers data sheet
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity
Texas Instruments, MSP430F677x Polyphase Metering SoCs data sheet
Texas Instruments, AMC1210 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator data sheet
Texas Instruments, Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor
Control Applications application report
•
•
Texas Instruments, AMC1306x Small, High-Precision, Reinforced Isolated Delta-Sigma Modulators With High
CMTI data sheet
Texas Instruments, CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family data
sheet
•
•
Texas Instruments, SN6501 ransformer Driver for Isolated Power Supplies data sheet
Texas Instruments, AMC1303, AMC1306, and AMC1336 Evaluation Module user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1336QDWVRQ1
ACTIVE
SOIC
DWV
8
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1336Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1336-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: AMC1336
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1336QDWVRQ1
SOIC
DWV
8
1000
330.0
16.4
12.05 6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DWV
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
AMC1336QDWVRQ1
8
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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