AMC3301DWER [TI]
具有集成直流/直流的 ±250mV 输入、精密电流检测增强型隔离式放大器 | DWE | 16 | -40 to 125;
| 型号： | AMC3301DWER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成直流/直流的 ±250mV 输入、精密电流检测增强型隔离式放大器 | DWE | 16 | -40 to 125 放大器 |
| 文件： | 总38页 (文件大小：2357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC3301
ZHCSHK2B –AUGUST 2019 –REVISED MAY 2021
AMC3301 具有集成直流/直流转换器的精密、±250mV 输入、增强型隔离放大
器
1 特性
3 说明
• 3.3V 或5V 单电源，具有集成直流/直流转换器
• ±250mV 输入电压范围，针对使用分流电阻器测量
电流进行了优化
• 固定增益：8.2
• 低直流误差：
– 失调电压：±150μV（最大值）
– 温漂：±1µV/°C（最大值）
– 增益误差：±0.2%（最大值）
– 增益误差漂移：±40ppm/°C（最大值）
– 非线性度：±0.04%（最大值）
• 高CMTI：85kV/µs（最小值）
• 系统级诊断功能
AMC3301 是一款精密的隔离放大器，针对基于分流器
的电流测量进行了优化。这款完全集成的隔离式直流/
直流转换器可实现器件低侧的单电源运行，使该器件成
为空间受限应用的独特解决方案。增强型电容式隔离栅
已通过 VDE V 0884-11 和 UL1577 认证，并支持高达
1.2kVRMS 的工作电压。
该隔离栅可将系统中以不同共模电压电平运行的各器件
隔开，并保护电压较低的器件免受高电压冲击。
AMC3301 的输入针对直接连接低阻抗分流电阻器或其
他具有低信号电平的低阻抗电压源的情况进行了优化。
出色的直流精度和低温漂支持在 –40°C 至 +125°C 的
工业级工作温度范围内进行精确的电流测量。
• 符合CISPR-11 和CISPR-25 EMI 标准
• 安全相关认证：
AMC3301 的集成直流/直流转换器故障检测和诊断输出
引脚可简化系统级设计和诊断。
– 符合DIN VDE V 0884-11 标准的6000VPK 增强
型隔离
– 符合UL1577 标准且长达1 分钟的4250VRMS
隔离
器件信息(1)
封装尺寸（标称值）
器件型号
AMC3301
封装
SOIC (16)
10.30mm × 7.50mm
• 可在工业级工作温度范围内正常工作：–40°C 至
+125°C
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 基于分流器的隔离式电流检测，用于：
– 保护继电器
– 电机驱动器
– 电源
– 光电逆变器
Low-side supply
(3.3 V or 5 V)
DCDC_OUT
DCDC_IN
DCDC_HGND
Isolated
DCDC_GND
Isolated
Power
Power
HLDO_IN
DIAG
To MCU (optional)
I
NC
LDO_OUT
VDD
HLDO_OUT
INP
OUTP
OUTN
GND
+250 mV
0 V
VCMout
2.05 V
ADC
INN
œ 250 mV
HGND
AMC3301
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS917
AMC3301
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ZHCSHK2B –AUGUST 2019 –REVISED MAY 2021
Table of Contents
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Documentation Support.......................................... 28
11.3 Receiving Notification of Documentation Updates..28
11.4 支持资源..................................................................28
11.5 Trademarks............................................................. 28
11.6 Electrostatic Discharge Caution..............................28
11.7 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .......................................10
6.11 Timing Diagram.......................................................10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................12
7 Detailed Description......................................................18
7.1 Overview...................................................................18
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (July 2020) to Revision B (May 2021)
Page
• 更改了“特性”部分：更改了低直流误差要点中的失调电压和温漂子要点，重新排列了各要点，添加了最后
一个要点............................................................................................................................................................. 1
• 将应用部分的目标应用从隔离式电压检测更改为基于分流器的隔离式电流检测.............................................. 1
• Changed Pin Configuration and Functions section.............................................................................................3
• Changed Absolute Maximum Ratings: changed max for DIAG pin from 5.5 V to 6.5 V.....................................4
• Changed overvoltage category for rated mains voltage ≤600 V from I-IV to I-III and for rated mains voltage
≤1000 V from I-III to I-II .................................................................................................................................... 6
• Changed output bandwidth (BW) (min) from 250 kHz to 290 kHz......................................................................8
• Changed Typical Characteristics section. Removed histograms, editorial changes.........................................12
• Changed Functional Block Diagram figure....................................................................................................... 18
• Changed Data Isolation Channel Signal Transmission section........................................................................ 19
• Changed Analog Output section.......................................................................................................................20
• Changed Diagnostic Output section: added DIAG Output Under Different Operating Conditions figure......... 21
• Changed Typical Application section................................................................................................................22
• Changed Input Filter Design section: changed Differential Input Filter figure...................................................23
• Added Differential to Single-Ended Output Conversion section....................................................................... 24
• Changed Step Response of the AMC3301 figure.............................................................................................24
• Changed Power Supply Recommendations section: changed nominal value in the first sentence from 3.3 V
(or 5 V) ± 10 V to 3.3 V or 5 V, changed primary-side to low-side, secondary-side to high-side, and
Decoupling the AMC3301 figure.......................................................................................................................26
• Changed Recommended Layout of the AMC3301 figure.................................................................................27
Changes from Revision * (August 2019) to Revision A (July 2020)
Page
• 将文档状态从预告信息更改为量产数据...............................................................................................................1
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5 Pin Configuration and Functions
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCDC_IN
DCDC_GND
DIAG
LDO_OUT
VDD
HLDO_OUT
INP
OUTP
INN
OUTN
HGND
GND
Not to scale
图5-1. DWE Package, 16-Pin SOIC, Top View
表5-1. Pin Functions
PIN
NAME
DCDC_OUT
TYPE
DESCRIPTION
NO.
1
Power
High-side output of the isolated DC/DC converter; connect this pin to the HLDO_IN pin.(1)
High-side ground reference for the isolated DC/DC converter; connect this pin to the
2
DCDC_HGND High-side power ground
HGND pin.
3
4
5
HLDO_IN
NC
Power
Input of the high-side LDO; connect this pin to the DCDC_OUT pin.(1)
No internal connection; connect this pin to HGND or leave this pin unconnected.
Output of the high-side LDO.(1)
—
HLDO_OUT
Power
Noninverting analog input. Either INP or INN must have a DC current path to HGND to
define the common-mode input voltage.(2)
6
7
INP
INN
Analog input
Analog input
Inverting analog input. Either INP or INN must have a DC current path to HGND to define
the common-mode input voltage.(2)
8
HGND
GND
High-side signal ground High-side analog ground; connect this pin to the DCDC_HGND pin.
Low-side signal ground Low-side analog ground; connect this pin to the DCDC_GND pin.
9
10
11
12
OUTN
OUTP
VDD
Analog output
Analog output
Low-side power
Inverting analog output.
Noninverting analog output.
Low-side power supply.(1)
Output of the low-side LDO; connect this pin to the DCDC_IN pin. The output of the LDO
must not be loaded by external circuitry.(1)
13
14
LDO_OUT
DIAG
Power
Active-low, open-drain status indicator output; connect this pin to the pullup supply (for
example, VDD) using a resistor or leave this pin floating if not used.
Digital output
Low-side ground reference for the isolated DC/DC converter; connect this pin to the GND
pin.
15
16
DCDC_GND
DCDC_IN
Low-side power ground
Power
Low-side input of the isolated DC/DC converter; connect this pin to the LDO_OUT pin.(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
(2) See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
–0.3
MAX
UNIT
V
Power-supply voltage
Analog input voltage
Analog output voltage
Digital output voltage
Input current
VDD to GND
6.5
INP, INN
VHLDO_OUT + 0.5
V
HGND –6
GND –0.5
GND –0.5
–10
OUTP, OUTN
VDD + 0.5
6.5
V
DIAG
V
Continuous, any pin except power-supply pins
10
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged device model (CDM), per JESD22-C101 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
3.3
MAX
UNIT
POWER SUPPLY
VDD
Low-side power supply
VDD to GND
3
5.5
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
±320
mV
mV
V
VIN = VINP –VINN
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage (1)
Operating common-mode input voltage
250
VHLDO_OUT
1
VIN = VINP –VINN
–250
–2
(VINP + VINN) / 2 to HGND
(VINP + VINN) / 2 to HGND
VCM
V
–0.16
TEMPERATURE RANGE
TA Specified ambient temperature
125
°C
–40
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
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6.4 Thermal Information
AMC3301
THERMAL METRIC(1)
DWE (SOIC)
16 PINS
73.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
31
RθJB
ψJT
Junction-to-board thermal resistance
44
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.7
42.8
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD = 5.5 V
MIN
TYP
MAX
231
UNIT
PD
Maximum power dissipation
mW
VDD = 3.6 V
151
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance (1)
External creepage (1)
Shortest pin-to-pin distance through air
mm
mm
≥8
≥8
≥21
≥120
≥600
I
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance - capacitive signal isolation)
Minimum internal gap (internal clearance - transformer power isolation)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
CTI
Distance through the insulation
µm
V
Comparative tracking index
Material group
According to IEC 60664-1
I-III
Rated mains voltage ≤600 VRMS
Overvoltage category
per IEC 60664-1
I-II
Rated mains voltage ≤1000 VRMS
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
Maximum repetitive peak isolation
voltage
VIORM
At AC voltage (bipolar)
1700
1200
VPK
At AC voltage (sine wave); time-dependent dielectric breakdown (TDDB)
test
VRMS
Maximum-rated isolation
working voltage
VIOWM
At DC voltage
1700
6000
7200
VDC
VPK
VPK
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
VIOTM
isolation voltage
Maximum surge
VIOSM
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
6250
≤5
≤5
VPK
isolation voltage(3)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and preconditioning (type
test),
≤5
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
VIO = 0.5 VPP at 1 MHz
~3.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(5)
RIO
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL1577
VTEST = VISO = 4250 VRMS or 6000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
VISO
Withstand isolation voltage
4250
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
ofthe I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 73.5°C/W, VDD = 5.5 V,
309
TJ = 150°C, TA = 25°C
θJA = 73.5°C/W, VDD = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 73.5°C/W,
TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
mA
R
472
R
PS
TS
Safety input, output, or total power
Maximum safety temperature
1700
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum low-side voltage.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –250 mV to +250
mV, INN = HGND = 0 V, and the external components listed in the Typical Application section; typical specifications are at TA
= 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
Differential input resistance
INN = HGND
19
22
kΩ
RIND
INP = INN = HGND; IIB = (IIBP
IIBN) / 2
+
IIB
Input bias current
µA
–41
–30
–24
TCIIB
IIO
Input bias current drift
0.8
1.4
2
nA/°C
nA
Input offset current
IIO = |IIBP –IIBN
|
CIN
Single-ended input capacitance
Differential input capacitance
INN = HGND, fIN = 275 kHz
fIN = 275 kHz
pF
CIND
1
ANALOG OUTPUT
Nominal gain
8.2
V/V
V
VCMout
Common-mode output voltage
1.39
1.44
1.49
-2.5
VOUT = (VOUTP –VOUTN);
|VIN| = |VINP –VINN| > VClipping
VCLIPout
Clipping differential output voltage
±2.49
V
VOUT = (VOUTP –VOUTN);
VFailsafe
Failsafe differential output voltage
V
V
V
DCDC_OUT ≤VDCDCUV, or
HLDO_OUT ≤VHLDOUV
–2.57
BW
Output bandwidth
Output resistance
290
85
334
0.2
kHz
ROUT
On OUTP or OUTN
Ω
On OUTP or OUTN, sourcing or
sinking, INP = INN = HGND, outputs
shorted to either GND or VDD
Output short-circuit current
14
mA
CMTI
Common-mode transient immunity
135
kV/µs
|HGND –GND| = 2 kV
ACCURACY
VOS
Input offset voltage(1) (2)
Input offset drift(1) (2) (4)
Gain error(1)
TA = 25°C, INP = INN = HGND
±0.02
±0.15
±0.04%
±6
0.15
1
mV
–0.15
–1
TCVOS
EG
uV/°C
TA = 25°C
0.2%
40
–0.2%
–40
TCEG
Gain error drift(1) (5)
Nonlinearity(1)
ppm/°C
ppm/°C
±0.002%
0.9
0.04%
–0.04%
Nonlinearity drift(1)
VIN = 0.5 VPP, fIN = 1 kHz, BW = 10
kHz, 10 kHz filter
80
67
85
71
SNR
THD
Signal-to-noise ratio
dB
VIN = 0.5 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter
VIN = 0.5 Vpp, fIN = 10 kHz,
BW = 100 kHz
Total harmonic distortion(3)
Output noise
dB
–85
INP = INN = HGND, fIN = 0 Hz,
BW = 100 kHz
300
–97
–98
µVRMS
fIN = 0 Hz, VCM min ≤VCM ≤VCM max
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
fIN = 10 kHz, VCM min ≤VCM ≤VCM
max
VDD from 3.0 V to 5.5 V, at dc, input
referred
–109
–98
INP = INN = HGND, VDD from 3.0 V
to 5.5 V, 10 kHz / 100 mV ripple,
input referred
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –250 mV to +250
mV, INN = HGND = 0 V, and the external components listed in the Typical Application section; typical specifications are at TA
= 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
no external load on HLDO
1 mA external load on HLDO
DCDC_OUT to HGND
27.5
29.5
3.5
40
42
IDD
Low-side supply current
mA
VDCDC_OUT DCDC output voltage
DCDC output undervoltage detection
3.1
2.1
4.65
V
V
VDCDCUV
DCDC output falling
2.25
3.2
threshold voltage
HLDO to HGND, up to 1 mA external
load
VHLDO_OUT High-side LDO output voltage
3
3.4
V
V
High-side LDO output undervoltage
VHLDOUV
HLDO output falling
2.4
2.6
detection threshold voltage
High-side supply current for auxiliary Load connected from HLDO_OUT to
IH
1
mA
ms
circuitry
HGND, non-switching
VDD step to 3.0 V, to OUTP and
OUTN valid, 0.1% settling
tAS
Analog settling time
0.9
1.4
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
1.3
1
MAX
UNIT
µs
tr
tf
Output signal rise time
Output signal fall time
µs
Unfiltered output
Unfiltered output
Unfiltered output
1.5
2.1
3
µs
VINx to VOUTx signal delay (50% –10%)
VINx to VOUTx signal delay (50% –50%)
VINx to VOUTx signal delay (50% –90%)
1.6
2.5
µs
µs
6.11 Timing Diagram
250 mV
INP - INN
0
œ 250 mV
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90 %
图6-1. Rise, Fall, and Delay Time Waveforms
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6.12 Insulation Characteristics Curves
500
1800
1600
1400
1200
1000
800
VDD = 3.6 V
VDD = 5.5 V
400
300
200
100
0
600
400
200
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D070
D069
图6-3. Thermal Derating Curve for Safety-Limiting Power per
图6-2. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
1.E+11
87.5%
1.E+10
143 Yrs
76 Yrs
1.E+09
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
Operating Zone
VDE Safety Margin Zone
20 %
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
Applied Voltage (VRMS
)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1200 VRMS, operating lifetime = 76 years
图6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
-10
-15
-20
-25
-30
-35
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
3
3.5
4
4.5
5
5.5
VCM (V)
VDD (V)
D003
D004
图6-5. Input Bias Current vs Common-Mode Input Voltage
图6-6. Input Bias Current vs Supply Voltage
-23
-25
-27
-29
-31
-33
-35
-37
-39
-41
5
VOUTN
VOUTP
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-350
-250
-150
-50
50
Differential Input Voltage (mV)
150
250
350
D005
D022
图6-7. Input Bias Current vs Temperature
图6-8. Output Voltage vs Input Voltage
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.39
1.39
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D009
D010
图6-9. Output Common-Mode Voltage vs Supply Voltage
图6-10. Output Common-Mode Voltage vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
5
0
0°
-45°
-5
-90°
-10
-15
-20
-25
-30
-35
-40
-135°
-180°
-225°
-270°
-315°
-360°
1
10
100
1000
1
10
100
1000
fIN (kHz)
fIN (kHz)
D007
D008
图6-11. Normalized Gain vs Input Frequency
图6-12. Output Phase vs Input Frequency
350
340
330
320
310
300
350
340
330
320
310
300
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D011
D012
图6-13. Output Bandwidth vs Supply Voltage
图6-14. Output Bandwidth vs Temperature
100
100
75
Device 1
Device 2
Device 3
75
50
50
25
25
0
0
-25
-50
-75
-100
-25
-50
-75
-100
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D027
D026
图6-15. Input Offset Voltage vs Supply Voltage
图6-16. Input Offset Voltage vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D020
D021
图6-17. Gain Error vs Supply Voltage
图6-18. Gain Error vs Temperature
0.03
0.02
0.01
0
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.01
-0.02
-0.03
-250 -200 -150 -100 -50
0
Differential Input Voltage (mV)
50 100 150 200 250
3
3.5
4
4.5
5
5.5
VDD (V)
D002419
D028
图6-19. Nonlinearity vs Input Voltage
图6-20. Nonlinearity vs Supply Voltage
0.03
0.02
0.01
0
80
75
70
65
60
55
50
45
40
Device 1
Device 2
Device 3
-0.01
-0.02
-0.03
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
50
100
150
|VINP - VINN| (mV)
200
250
300
D030
D032
VIN = 0.5 Vpp, fIN = 10 kHz
图6-21. Nonlinearity vs Temperature
图6-22. Signal-to-Noise Ratio vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
80
77.5
75
80
77.5
75
72.5
70
72.5
70
67.5
65
67.5
65
Device 1
Device 2
Device 3
62.5
60
62.5
60
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D034
D035
VIN = 0.5 Vpp, fIN = 10 kHz
VIN = 0.5 Vpp, fIN = 10 kHz
图6-24. Signal-to-Noise Ratio vs Temperature
图6-23. Signal-to-Noise Ratio vs Supply Voltage
-70
-70
-75
-80
-75
-80
-85
-85
-90
-90
Device 1
Device 2
Device 3
-95
-95
-100
-100
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D056
D059
图6-25. Total Harmonic Distortion vs Supply Voltage
图6-26. Total Harmonic Distortion vs Temperature
10000
0
-20
-40
1000
100
10
-60
-80
-100
-120
0.01
0.1
1 10
Frequency (kHz)
100
1000
0.001
0.01
0.1
1
fIN (kHz)
10
100
1000
D017
D038
图6-27. Input-Referred Noise Density vs Frequency
图6-28. Common-Mode Rejection Ratio vs Input Frequency
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
-70
-75
0
-20
-80
-40
-85
-90
-60
-95
-80
-100
-105
-110
-100
-120
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0.01
0.1
1
10
Ripple Frequency (kHz)
100
1000
D039
D041
图6-29. Common-Mode Rejection Ratio vs Temperature
图6-30. Power-Supply Rejection Ratio vs Ripple Frequency
32.5
32.5
30
27.5
25
30
27.5
25
22.5
22.5
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D043
D044
图6-31. Supply Current vs Supply Voltage
图6-32. Supply Current vs Temperature
3.4
3.35
3.3
4
3.5
3
3.25
3.2
2.5
2
3.15
3.1
1.5
1
3.05
3
0.5
0
3
3.5
4
4.5
5
5.5
3
3.5
4
4.5
5
5.5
VDD (V)
VDD (V)
D046
D065
图6-33. High-Side LDO Line Regulation
图6-34. Output Rise and Fall time vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –250 mV to +250 mV, INN = HGND = 0 V, and fIN = 10 kHz (unless otherwise noted)
4
3.5
3
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
2.5
2
1.5
1
0.5
0
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
5
5.5
VDD (V)
D066
D067
图6-35. Output Rise and Fall Time vs Temperature
图6-36. VIN to VOUT Signal Delay vs Supply Voltage
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D068
图6-37. VIN to VOUT Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC3301 is a fully differential, precision, isolated amplifier with a fully integrated DC/DC converter that can
supply the device from a single 3.3-V or 5-V voltage supply on the low-side. The input stage of the device
consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator
uses an internal voltage reference and clock generator to convert the analog input signal to a digital bitstream.
The drivers (termed TX in the Functional Block Diagram) transfer the output of the modulator across the isolation
barrier that separates the high-side and low-side voltage domains. As shown in the Functional Block Diagram,
the received bitstream and clock are synchronized and processed by a fourth-order analog filter on the low-side
and presented as a differential output of the device
The signal path is isolated by a double capacitive silicon dioxide (SiO2) insuation barrier, whereas power
isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material.
7.2 Functional Block Diagram
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
Resonator
And
Driver
Rectifier
Diagnostics
LDO_OUT
VDD
LDO
AMC3301
LDO
HLDO_OUT
INP
Analog Filter
OUTP
ûꢀ Modulator
INN
OUTN
HGND
GND
7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC3301 feeds a second-order, switched-capacitor, feed-forward
ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors with a differential input
impedance of RIND. The modulator converts the analog signal into a bitstream that is transferred across the
isolation barrier, as described in the Data Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signals (INP and INN). First, if the input voltages VINP or VINN
exceed the range specified in the Absolute Maximum Ratings table, the input current must be limited to the
absolute maximum value, because the device input electrostatic discharge (ESD) diodes turns on. In addition,
the linearity and parametric performance of the device are ensured only when the analog input voltage remains
within linear full-scale range (VFSR) and within the common-mode input voltage range (VCM) as specified in the
Recommended Operating Conditions table.
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7.3.2 Data Isolation Channel Signal Transmission
The AMC3301 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the modulator
output bitstream across the capacitive SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to
represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC3301 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and produces
the output. The AMC3301 transmission channel is optimized to achieve the highest level of common-mode
transient immunity (CMTI) and lowest level of radiated emissions caused by the high-frequency carrier and
RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC3301 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input
voltages (VINP – VINN) in the range from –250 mV to +250 mV, the device provides a linear response with a
nominal gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage (VOUTP
–VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage
VCMout, as specified in the Electrical Characteristics table. For absolute differential input voltages greater than
250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but with reduced
linearity performance. The outputs saturate at a differential output voltage of VCLIPout as shown in 图 7-2 if the
differential input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VOUTN
VCLIPout
VOUTP
VFAILSAFE
VCMout
œ 320 mV
œ 250 mV
320 mV
0
250 mV
Differential Input Voltage (VINP œ VINN
)
图7-2. Output Behavior of the AMC3301
The AMC3301 provides a fail-safe output that simplifies diagnostics on system level. 图 7-2 shows the fail-safe
mode, in which the AMC3301 outputs a negative differential output voltage that does not occur under normal
operating conditions. The fail-safe output is active in two cases:
• The low-side does not receive data from the high-side (for example, because of a loss of power on the high
side).
• The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out).
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for the
fail-safe detection on the system level.
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7.3.4 Isolated DC/DC Converter
The AMC3301 offers a fully integrated isolated DC/DC converter that includes the following components as
illustrated in the Functional Block Diagram:
• Low-dropout regulator (LDO) on the low-side to stabilize the supply voltage VDD that drives the low-side of
the converter. This circuit does not output a constant voltage and is not intended for driving any external load.
• Low-side full-bridge inverter and drivers
• Laminate-based, air-core transformer for high-immunity to magnetic fields
• High-side full-bridge rectifier
• High-side LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the
signal path. The high-side LDO outputs a constant voltage and can provide a limited amount of current to
power external circuitry.
The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of the
electromagnetic radiation. The resonator frequency is synchronized to the operation of the ΔΣ modulator to
minimize the interference with data transmission and support the high analog performance of the device.
The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3301 and can
source up to IH of additional DC current for an optional auxiliary circuit such as an active filter, preamplifier, or
comparator. IH is specified in the Electrical Characteristics table as a DC, non-switching current.
7.3.5 Diagnostic Output
The open-drain DIAG pin can be monitored to confirm the device is operational and the output voltage is valid.
As shown in 图 7-3, during power-up, the DIAG pin is actively held low until the high-side supply is in regulation
and the device operates properly. During normal operation, the DIAG pin is in high-impedance (Hi-Z) state and is
pulled high through an external pullup resistor. The DIAG pin is actively pulled low if:
• The low-side does not receive data from the high-side (for example, because of a loss of power on the high
side). In this case, the amplifier outputs are driven to the VFAILSAFE value that is shown in 图7-2.
• The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out). In this case, the low-side may still
receive data from the high-side but the data may not be valid. The amplifier outputs are driven to the
VFAILSAFE value that is shown in 图7-2.
Normal
Operation
Normal
Operation
DIAG
Power-up
High-side supply undervoltage
图7-3. DIAG Output Under Different Operating Conditions
During normal operation, the DIAG pin is in a high-impedance state. Connect the DIAG pin to a pullup resistor or
leave open if not used.
7.4 Device Functional Modes
The AMC3301 is operational when the power supply VDD is applied, as specified in the Recommended
Operating Conditions table.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The low input voltage range, low nonlinearity, and low temperature drift make the AMC3301 a high-performance
solution for industrial applications where shunt-based current sensing with high common-mode voltage levels is
required.
8.2 Typical Application
The AMC3301 is ideally suited for shunt-based current sensing applications where accurate current monitoring is
required in the presence of high common-mode voltages. The AMC3301 integrates an isolated power supply for
the high-voltage side and therefore makes the device particularly easy to use in applications that do not have a
high-side supply readily available or where a high-side supply is referenced to a different ground potential than
the signal to be measured.
图 8-1 shows a simplified schematic of the AMC3301 in a solar inverter where the phase current is measured on
the grid-side of an LCL filter. Although the system offers a supply for the high-side gate driver, there is a large
common-mode voltage between the gate driver supply ground reference and the shunt resistor on the other side
of the LCL filter. Therefore, the gate driver supply is not suitable for powering the high-side of an isolated
amplifier that measures the voltage across the shunt. The integrated isolated power supply of the AMC3301
solves that problem and enables current sensing at locations that is optimal for the system.
The diagram also shows the AMC3330 being used for sensing the AC output voltage.
DC+
SW
HS Gate
Driver
Supply
N
PGND
IPHASE
SW
to grid (L1)
RSHUNT
PGND
RL11
LS Gate
Driver
Supply
RL1SNS
DC-
PGND
RL12
N
AMC3301
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
47 kΩ
to uC (optional)
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
INP
3.3 V / 5 V supply
10 Ω
10 Ω
10 nF
OUTP
ADS8363
to MCU
16-Bit ADC
INN
OUTN
HGND
GND
GND
AMC3330
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
47 kΩ
to uC (optional)
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
INP
3.3 V / 5 V supply
OUTP
ADS8363
to MCU
16-Bit ADC
INN
OUTN
HGND
GND
GND
图8-1. The AMC3301 in a Solar Inverter Application
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8.2.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
Supply voltage
VALUE
3.3 V or 5 V
Voltage drop across the shunt for a linear response (VSHUNT
)
±250 mV (maximum)
8.2.2 Detailed Design Procedure
The AMC3301 requires a single 3.3-V or 5-V supply on its low-side. The high-side supply is internally generated
by an integrated DC/DC converter as explained in the Isolated DC/DC Converter section.
The ground reference (HGND) is derived from the terminal of the shunt resistor that is connected to the negative
input of the AMC3301 (INN). If a four-pin shunt is used, the inputs of the AMC3301 are connected to the inner
leads and HGND is connected to one of the outer shunt leads. To minimize offset and improve accuracy, set the
ground connection to a separate trace that connects directly to the shunt resistor rather than shorting HGND to
INN directly at the input to the device. See the Layout section for more details.
8.2.2.1 Shunt Resistor Sizing
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT
Consider the following two restrictions to choose the proper value of the shunt resistor, RSHUNT
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: |VSHUNT| ≤|VFSR
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
.
:
|
a clipping output: |VSHUNT| ≤|VClipping
|
8.2.2.2 Input Filter Design
TI recommends placing an RC filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
• The impedances measured from the analog inputs are equal
For most applications, the structure shown in 图8-2 achieves excellent performance.
AMC3301
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
LDO_OUT
VDD
HLDO_OUT
INP
10 Ω
10 Ω
10 nF
OUTP
INN
OUTN
HGND
GND
图8-2. Differential Input Filter
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8.2.2.3 Differential to Single-Ended Output Conversion
图 8-3 shows an example of a TLV6001 based signal conversion and filter circuit for systems using single-
ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩand C1 = C2 = 330 pF yields good performance.
AMC3301
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
C1
R2
LDO_OUT
VDD
HLDO_OUT
INP
R1
R3
OUTP
œ
ADC
To MCU
+
INN
OUTN
TLV6001
GND
HGND
GND
C2
R4
GND
VREF
GND
图8-3. Connecting the AMC3301 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of successive-
approximation-register (SAR) ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest
Distortion and Noise reference guide and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power
reference guide, available for download at www.ti.com.
8.2.3 Application Curve
In frequency inverter applications, the power switches must be protected in case of an overcurrent condition. To
allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. 图 8-4 shows
the typical full-scale step response of the AMC3301. Consider the delay of the required window comparator and
the MCU to calculate the overall response time of the system.
VOUTN
VOUTP
VIN
图8-4. Step Response of the AMC3301
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8.2.4 What To Do and What Not To Do
Do not leave the analog inputs INP and INN of the AMC3301 unconnected (floating) when the device is powered
up. If the device inputs are left floating, the input bias current may drive the inputs to a positive value that
exceeds the operating common-mode input voltage and the output of the device is undetermined.
Connect the negative input (INN) to the high-side ground (HGND), either by a hard short or through a resistive
path. A DC current path between INN and HGND is required to define the input common-mode voltage. Take
care not to exceed the input common-mode range as specified in the Recommended Operating Conditions
table. For best accuracy, route the ground connection as a separate trace that connects directly to the shunt
resistor rather than shorting AGND to INN directly at the input to the device. See the Layout section for more
details.
The high-side LDO can source a limited amount of current (IH) to power external circuitry. Take care not to
overload the high-side LDO.
The low-side LDO does not output a constant voltage and is not intended for powering any external circuitry. Do
not connect any external load to the HLDO_OUT pin.
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9 Power Supply Recommendations
The AMC3301 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V or 5 V. TI
recommends a low-ESR decoupling capacitor of 1 nF (C8 in 图 9-1) placed as close as possible to the VDD pin,
followed by a 1-µF capacitor (C9) to filter this power-supply path.
The low-side of the DC/DC converter is decoupled with a low-ESR 100-nF capacitor (C4) positioned close to the
device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the high side in
addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to the
DCDC_OUT and DCDC_HGND pins.
For the high-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the AMC3301,
followed by a 100-nF decoupling capacitor (C5).
The ground reference for the high-side (HGND) is derived from the terminal of the shunt resistor which is
connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this
connection instead of shorting HGND to INN directly at the device input. The high-side DC/DC ground terminal
(DCDC_HGND) is shorted to HGND directly at the device pins.
C2 C3
1 µF 1 nF
C4
100 nF
AMC3301
DCDC_OUT
DCDC_IN
DCDC_GND
DIAG
DCDC_HGND
HLDO_IN
NC
R1
47 kΩ
C1 100 nF
C6
to uC (optional)
I
LDO_OUT
VDD
C5
C8 C9
1 nF 1 µF
100 nF 1 nF
HLDO_OUT
INP
3.3 V / 5 V supply
to RC filter / ADC
to RC filter / ADC
R2
10 Ω
C10
10 nF
OUTP
INN
OUTN
R4 10 Ω
HGND
GND
图9-1. Decoupling the AMC3301
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
表 9-1 lists components suitable for use with the AMC3301. This list is not exhaustive. Other components may
exist that are equally suitable (or better), however these listed components have been validated during the
development of the AMC3301.
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表9-1. Recommended External Components
DESCRIPTION
PART NUMBER
MANUFACTURER
SIZE (EIA, L x W)
VDD
C8
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
12065C102KAT2A
12063C105KAT2A
AVX
AVX
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C9
DC/DC CONVERTER
C4
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C0603C102K5RACTU
Kemet
Kemet
TDK
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
C3
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
C2
CGA3E1X7R1E105K080AC
HLDO
C1
100 nF ± 10%, X7R, 50 V
100 nF ± 5%, NP0, 50 V
1 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C3216NP01H104J160AA
12065C102KAT2A
Kemet
TDK
0603, 1.6 mm x 0.8 mm
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C5
C6
AVX
10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors. The same
component reference designators are used as in the Power Supply Recommendations section. Decoupling
capacitors are placed as close as possible to the AMC3301 supply pins. For best performance, place the shunt
resistor close to the INP and INN inputs of the AMC3301 and keep the layout of both connections symmetrical.
To avoid causing errors in the measurement by the input bias currents of the AMC3301, connect the high-side
ground pin (HGND) to the INN-side of the shunt resistor. Use a separate trace in the layout to make this
connection to maintain equal currents in the INN and INP traces.
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
DIAG To MCU I/O (optional)
AMC3301
VDD 3.3-V or 5-V supply
INP
R2
OUTP To analog filter / ADC / MCU
OUTN To analog filter / ADC / MCU
R4
INN
GND
HGND
Top Metal
Inner or Bottom Layer Metal
Via
图10-1. Recommended Layout of the AMC3301
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Texas Instruments, Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier data sheet
• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC3301DWE
ACTIVE
ACTIVE
SOIC
SOIC
DWE
DWE
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
AMC3301
AMC3301
AMC3301DWER
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC3301DWER
SOIC
DWE
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DWE 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
AMC3301DWER
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DWE SO-MOD
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
AMC3301DWE
16
40
506.98
12.7
4826
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
8
9
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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