AMC3302_V01 [TI]
AMC3302 Precision, ±50-mV Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter;
| 型号： | AMC3302_V01 |
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TEXAS INSTRUMENTS |
| 描述： | AMC3302 Precision, ±50-mV Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter |
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AMC3302
SBASA11 – AUGUST 2020
AMC3302 Precision, ±50-mV Input, Reinforced Isolated Amplifier
With Integrated DC/DC Converter
1 Features
3 Description
•
3.3-V or 5-V single supply with integrated DC/DC
The AMC3302 is a precision, isolated amplifier with a
converter
fully integrated, isolated DC/DC converter that allows
single-supply operation from the low-side of the
device. The reinforced capacitive isolation barrier is
certified according to VDE V 0884-11 and UL1577
and separates sections of the system that operate on
different common-mode voltage levels and protects
low-voltage domains from damage.
•
±50-mV linear input voltage range optimized for
current measurement using shunt resistors
Fixed gain: 41
•
•
Low DC errors:
– Input offset voltage: ±100 µV (max)
– Input offset drift: ±0.8 µV/°C (max)
– Gain error: ±0.3% (max)
– Gain error drift: ±50 ppm/°C (max)
– Nonlinearity: ±0.03% (max)
High CMTI: 85 kV/µs (min)
The input of the AMC3302 is optimized for direct
connection to shunt resistors or other low voltage-
level signal sources. The integrated isolated DC/DC
converter allows flexible placement of the shunt and
the AMC3302, and makes the device a unique
solution for space-constrained applications.
•
•
•
System-level diagnostic features
Safety-related certifications:
The excellent performance of the device supports
accurate current monitoring and control, which is an
important feature to achieve low torque ripple in motor
control applications. The integrated DC/DC converter
fault-detection and diagnostic output pin of the
AMC3302 simplify system-level design and
diagnostics.
– 6000-VPK reinforced isolation per DIN VDE V
0884-11
– 4250-VRMS isolation for 1 minute per UL1577
Meets CISPR-11 and CISPR-25 EMI standards
•
2 Applications
•
Isolated voltage sensing in:
– Motor drives
– Photovoltaic inverters
– Power delivery systems
– Electricity meters
The AMC3302 is specified over the industrial
temperature range of –40°C to +125°C.
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
AMC3302
SOIC (16)
10.30 mm × 7.50 mm
– Protection relays
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
Resonator
And
Driver
Rectifier
DCDC_GND
DIAG
Diagnostics
To MCU (optional)
LDO_OUT
VDD
LDO
LDO
HLDO_OUT
INP
I
3.3 V / 5 V
OUTP
ADS8363
16-Bit ADC
INN
OUTN
HGND
GND
AMC3302
GND
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
AMC3302
SBASA11 – AUGUST 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .........................................9
6.11 Timing Diagram.........................................................9
6.12 Insulation Characteristics Curves........................... 10
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................13
8 Application and Implementation..................................14
8.1 Application Information............................................. 14
8.2 Typical Application.................................................... 14
8.3 What to Do and What Not to Do............................... 15
9 Power Supply Recommendations................................16
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 Device Support........................................................19
11.2 Documentation Support.......................................... 19
11.3 Receiving Notification of Documentation Updates..19
11.4 Support Resources................................................. 19
11.5 Trademarks............................................................. 19
11.6 Electrostatic Discharge Caution..............................19
11.7 Glossary..................................................................19
12 Mechanical, Packaging, and Orderable
Information.................................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2020
*
Initial Release
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5 Pin Configuration and Functions
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCDC_IN
DCDC_GND
DIAG
LDO_OUT
VDD
HLDO_OUT
INP
OUTP
INN
OUTN
HGND
GND
Not to scale
Figure 5-1. DWE Package, 16-Pin SOIC, Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
2
DCDC_OUT
Power
Power
High-side output of the isolated DC/DC converter; connect this pin to the HLDO_IN pin.(1)
High-side ground reference for the isolated DC/DC converter; connect this pin to the HGND
pin.
DCDC_HGND
3
4
5
HLDO_IN
NC
Power
—
Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin(1)
No internal connection; connect this pin to HGND or leave this pin unconnected (floating).
Output of the high-side LDO.(1)
HLDO_OUT
Power
Noninverting analog input. Either INP or INN must have a DC current path to HGND to
define the common-mode input voltage. See Section 10 for details.
6
7
INP
INN
Input
Input
Inverting analog input. Either INP or INN must have a DC current path to HGND to define
the common-mode input voltage. See Section 10 for details.
8
9
HGND
GND
Analog
Analog
Output
Output
Power
Power
High-side analog ground; connect this pin to the DCDC_HGND pin.
Low-side analog ground; connect this pin to the DCDC_GND pin.
Inverting analog output.
10
11
12
13
OUTN
OUTP
Noninverting analog output.
VDD
Low-side power supply.(1)
LDO_OUT
Output of the primary-side LDO; connect this pin to the DCDC_IN pin.(1)
Active-low, open-drain status indicator output; connect this pin to the pullup supply (for
example, VDD) using a resistor or leave this pin floating if not used.
14
DIAG
Output
Low-side ground reference for the isolated DC/DC converter; connect this pin to the GND
pin.
15
16
DCDC_GND
DCDC_IN
Power
Power
Primary-side input of the isolated DC/DC converter; connect this pin to the LDO_OUT pin.(1)
(1) See Section 9 for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
–0.3
MAX
UNIT
V
Power-supply voltage
Analog input voltage
Analog output voltage
Digital output voltage
Input current
VDD to GND
6.5
VHLDOout+ 0.5
VDD + 0.5
5.5
INP, INN
HGND – 6
GND – 0.5
GND – 0.5
–10
V
OUTP, OUTN
V
DIAG
V
Continuous, any pin except power-supply pins
10
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged device model (CDM), per JESD22-C101 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
3.3
MAX
UNIT
POWER SUPPLY
VDD
Low-side power supply
VDD to GND
3
5.5
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
VIN = VINP – VINN
±64
mV
mV
V
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage (1)
Operating common-mode input voltage
VIN = VINP – VINN
–50
–2
50
VHLDOout
1
(VINP + VINN) / 2 to HGND
(VINP + VINN) / 2 to HGND
VCM
–0.032
V
TEMPERATURE RANGE
TA Specified ambient temperature
–40
125
°C
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in Section 6.1.
6.4 Thermal Information
AMC3302
THERMAL METRIC(1)
DWE (SOIC)
16 PINS
73.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
31
RθJB
YJT
Junction-to-board thermal resistance
44
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.7
YJB
42.8
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD = 5.5 V
MIN
TYP
MAX
231
UNIT
PD
Maximum power dissipation
mW
VDD = 3.6 V
151
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UNIT
SBASA11 – AUGUST 2020
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance (1)
External creepage (1)
Shortest pin-to-pin distance through air
≥ 8
≥ 8
mm
mm
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance - capacitive signal
isolation)
≥ 21
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance - transformer power
isolation)
≥ 120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 600
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category
per IEC 60664-1
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
Maximum repetitive peak
isolation voltage
VIORM
At AC voltage (bipolar)
1700
1200
VPK
At AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test
VRMS
Maximum-rated isolation
working voltage
VIOWM
At DC voltage
1700
6000
7200
VDC
VPK
VPK
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
isolation voltage
VIOTM
Maximum surge
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
VIOSM
6250
≤ 5
VPK
isolation voltage(3)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤ 5
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and
preconditioning (type test),
≤ 5
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
~3.5
pF
Ω
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(5)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
2
40/125/21
UL1577
VTEST = VISO = 4250 VRMS or 6000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
VISO
Withstand isolation voltage
4250
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
Certificate planned
6.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output
circuitry. A failure ofthe I/O can allow low resistance to ground or the supply and, without current limiting,
dissipate sufficient power to overheatthe die and damage the isolation barrier potentially leading to secondary
system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 73.5°C/W, VDD = 5.5 V, TJ =
150°C, TA = 25°C
309
IS
Safety input, output, or supply current
mA
RθJA = 73.5°C/W, VDD = 3.6 V, TJ =
150°C, TA = 25°C
472
PS
TS
Safety input, output, or total power
Maximum safety temperature
RθJA = 73.5°C/W, TJ = 150°C, TA = 25°C
1700
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 6.4 table is that of a device installed on a high-K test board for leaded
surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum low-side voltage.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –50 mV to
+50 mV, INN = HGND = 0 V, and the external components listed in the Typical Application section; typical
specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
Single-ended input resistance
Differential input resistance
Input bias current
INN = HGND
4.75
4.9
–36
±1.5
±10
4
kΩ
RIND
IIB
INP = INN = HGND; IIB = (IIBP + IIBN) / 2
–48.5
–28.5
µA
nA/°C
nA
TCIIB
IIO
Input bias current drift
Input offset current
IIO = |IIBP – IIBN|
CIN
Single-ended input capacitance
Differential input capacitance
INN = HGND, fIN = 275 kHz
fIN = 275 kHz
pF
CIND
2
ANALOG OUTPUT
Nominal gain
Common-mode output voltage
41
VCMout
1.39
250
85
1.44
1.49
-2.5
V
V
VOUT = (VOUTP-VOUTN); |VIN| = |VINP-VINN
> VClipping
|
VCLIPout Clipping differential output voltage
±2.49
–2.57
VOUT = (VOUTP-VOUTN); VDCDCout
VDCDCUV, or VHLDOout ≤ VHLDOUV
≤
VFailsafe
Failsafe differential output voltage
V
BWOUT
ROUT
Output bandwidth
Output resistance
334
0.2
kHz
Ω
On OUTP or OUTN
On OUTP or OUTN, sourcing or sinking,
INP = INN = HGND, outputs shorted to
either GND or VDD
Output short-circuit current
14
mA
CMTI
Common-mode transient immunity
|HGND – GND| = 2 kV
135
kV/µs
ACCURACY
EG
Gain error (1)
TA = 25°C
–0.3% ±0.05%
0.3%
TCEG
VOS
Gain error drift (1)
Input offset voltage (1)
Input offset drift (1)
Nonlinearity (1)
–50
–100
±15
50 ppm/°C
TA = 25°C, INP = INN = HGND
100
µV
TCVOS
–0.8
±0.15
0.8 uV/°C
–0.03%
0.03%
Nonlinearity drift (1)
1
ppm/°C
dB
VIN = 0.5 VPP, fIN = 1 kHz, BW = 10 kHz,
10 kHz filter
80
84
SNR
Signal-to-noise ratio
VIN = 0.5 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter
70
VIN = 0.5 Vpp, fIN = 10 kHz,
BW = 100 kHz
THD
Total harmonic distortion
–85
dB
dB
fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max
fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max
–100
–98
CMRR
Common-mode rejection ratio
VDD from 3.0 V to 5.5 V, at dc, input
referred
–109
–98
PSRR
Power-supply rejection ratio
dB
INP = INN = HGND, VDD from 3.0 V to
5.5 V, 10 kHz / 100 mV ripple, input
referred
POWER SUPPLY
no external load on HLDO
1 mA external load on HLDO
DCDCout to HGND
27.5
29.5
3.5
40
42
IDD
Low-side supply current
mA
V
VDCDCout DCDC output voltage
3.1
4.65
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minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –50 mV to
+50 mV, INN = HGND = 0 V, and the external components listed in the Typical Application section; typical
specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.1
3
TYP
2.25
3.2
MAX
UNIT
DCDC output undervoltage detection
threshold voltage
VDCDCUV
DCDC output falling
V
V
V
VHLDOout High-side LDO output voltage
HLDO to HGND, up to 1 mA external load
HLDO output falling
3.4
High-side LDO output undervoltage
VHLDOUV
2.4
2.6
detection threshold voltage
High-side supply current for auxiliary
circuitry
Load connected from HLDOout to HGND,
non-switching
IH
1
mA
ms
VDD step to 3.0 V, to OUTP and OUTN
valid, 0.1% settling
tAS
Analog settling time
0.9
1.4
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditions.
6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
1.3
1
MAX
UNIT
µs
tr
tf
Output signal rise time
Output signal fall time
µs
VINx to VOUTx signal delay (50% - 10%)
VINx to VOUTx signal delay (50% - 50%)
VINx to VOUTx signal delay (50% - 90%)
Unfiltered output
1.5
2.1
3
µs
Unfiltered output
Unfiltered output
1.6
2.5
µs
µs
6.11 Timing Diagram
250 mV
INP - INN
0
œ 250 mV
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90 %
Figure 6-1. Rise, Fall, and Delay Time Waveforms
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6.12 Insulation Characteristics Curves
500
1800
1600
1400
1200
1000
800
VDD = 3.6 V
VDD = 5.5 V
400
300
200
100
0
600
400
200
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D070
D069
Figure 6-3. Thermal Derating Curve for Safety-
Limiting Power per VDE
Figure 6-2. Thermal Derating Curve for Safety-
Limiting Current per VDE
1.E+11
87.5%
1.E+10
143 Yrs
76 Yrs
1.E+09
1.E+08
1.E+07
TDDB Line (< 1 ppm Fail Rate)
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
Operating Zone
VDE Safety Margin Zone
20 %
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
5500
6000
6500
Applied Voltage (VRMS
)
Working Isolation Voltage = 1200 VRMS
TA upto 150 o
Projected Insulation Lifetime = 76 Yrs
Applied Voltage Frequency = 60 Hz
C
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1000 VRMS, operating lifetime = 1184 years
Figure 6-4. Reinforced Isolation Capacitor Lifetime Projection
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7 Detailed Description
7.1 Overview
The AMC3302 is a fully differential, precision, isolated amplifier with a fully integrated DC/DC converter that can
supply the device from a single 3.3-V or 5-V voltage supply on the low-side. The input stage of the device
consists of a fully differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator
uses an internal voltage reference and clock generator to convert the analog input signal to a digital bitstream.
The drivers (termed TX in Section 7.2) transfer the output of the modulator across the isolation barrier that
separates the high-side and low-side voltage domains. As shown in Section 7.2, the received bitstream and
clock are synchronized and processed by a fourth-order analog filter on the low-side and presented as a
differential output of the device
The signal path is isolated by a double capacitive silicon dioxide (SiO2) insuation barrier, whereas power
isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material.
7.2 Functional Block Diagram
DCDC_OUT
DCDC_IN
DCDC_GND
DIAG
Resonator and
Driver
Rectifier
DCDC_HGND
HLDO_IN
Diagnostics
LDO
LDO
HLDO_OUT
LDO_OUT
VDD
Bandgap
Reference
Isolation
Barrier
INP
INN
Retiming and
4th-Order
Active
Low-Pass
Filter
OUTP
OUTN
ûꢀ Modulator
TX
RX
RX
TX
Oscillator
AMC3302
HGND
GND
7.3 Feature Description
7.3.1 Analog Input
The differential amplifier input stage of the AMC3302 feeds a second-order, switched-capacitor, feed-forward ΔΣ
modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 with a
differential input impedance of 22 kΩ. The modulator converts the analog signal into a bitstream that is
transferred over the isolation barrier, as described in Section 7.3.2.
There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the range
HGND – 6 V to HLDO_OUT + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) diodes turns on. In addition, the linearity and noise performance of the device are
ensured only when the analog input voltage remains within the specified linear full-scale range (FSR) and within
the specified common-mode input voltage range.
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7.3.2 Data Isolation Channel Signal Transmission
The AMC3302 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the capacitive SiO2-based isolation barrier. Figure 7-1 shows the block diagram of an isolation channel.
The transmitter modulates the bitstream at TX IN with an internally generated, 480-MHz carrier and sends a
burst across the isolation barrier to represent a digital one and sends a no signal to represent the digital zero.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The
symmetrical design of each isolation channel improves the common-mode transient immunity (CMTI)
performance and reduces the radiated emissions caused by the high-frequency carrier.
Transmitter
Receiver
OOK
Modulation
SiO2-Based
Capacitive
Reinforced
Isolation
TX IN
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
RX OUT
Barrier
Oscillator
Figure 7-1. Block Diagram of a Data Isolation Channel
Figure 7-2 shows the concept of the OOK scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 7-2. OOK-Based Modulation Scheme
7.3.3 Analog Output
The AMC3302 offers a differential analog output comprised of the OUTP and OUTN pins. For differential input
voltages (VINP – VINN) in the range from –50 mV to 50 mV, the device provides a linear response with a nominal
gain of 8.2. For example, for a differential input voltage of 250 mV, the differential output voltage (VOUTP
–
VOUTN) is 2.05 V. At zero input (INP shorted to INN), both pins output the same common-mode output voltage
VCMout, as specified in the Electrical Characteristics table in Section 6. For absolute differential input voltages
greater than 250 mV but less than 320 mV, the differential output voltage continues to increase in magnitude but
with reduced linearity performance. The outputs saturate at a differential output voltage of VCLIPout as shown in
Figure 7-3 if the differential input voltage exceeds the VClipping value.
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Maximum input range before clipping (VClipping
Linear input range (VFSR
)
)
VOUTN
Clipping output voltage
(VCLIPout
)
Common mode output voltage
(VCMout
)
VOUTP
œ 64 mV
œ 50 mV
64 mV
50 mV
0
Differential Input Voltage (VINP œ VINN
)
Figure 7-3. AMC3302 Output Behavior
7.3.4 Isolated DC/DC Converter
The AMC3302 offers a fully integrated isolated DC/DC converter stage that includes following components
illustrated in Section 7.2:
•
Low-dropout regulator (LDO) on the primary side to stabilize the supply voltage VDD that drives the primary
side of the converter
•
•
•
•
Primary full-bridge inverter and drivers
Laminate-based, air-core transformer for high immunity to magnetic fields
Secondary full-bridge rectifier
Secondary LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the
signal path
The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of the
electromagnetic radiation. The resonator frequency is synchronized to the operation of the ΔΣ modulator to
minimize the interference with data transmission and support the high analog performance of the device.
The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3302 and can
source up to IH of additional DC current for an optional auxiliary circuit such as an active filter, pre-amplifier or
comparator. IH is specified in the Electrical Characteristics table in Section 6 as a DC, non-switching current.
7.3.5 Diagnostic Output
The open-drain DIAG pin can be monitored to confirm the device is operational and the output voltage is valid.
During power-up, the DIAG pin is actively held low until the high-side supply is in regulation and the device
operates properly. During normal operation, the DIAG pin is in high-impedance (HiZ) state and is pulled high
through an external pullup resistor. The DIAG pin is actively pulled low if:
•
The low-side does not receive data from the high-side (for example, because of a loss of power on the high
side). In this case, the amplifier outputs are driven to negative full scale.
•
The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out). In this case, the low-side may still
receive data from the high-side but the data may not be valid. The amplifier outputs are driven to negative
full-scale.
During normal operation, the DIAG pin is in a high-impedance state. Connect the DIAG pin to a pullup supply
through a resistor or leave open if not used.
7.4 Device Functional Modes
The AMC3302 is operational when the power supply VDD is applied, as specified in the Recommended
Operating Conditions table in Section 6.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The low input voltage range, low nonlinearity, and low temperature drift make the AMC3302 a high-performance
solution for industrial applications where shunt-based current sensing with high common-mode voltage levels is
required. The integrated isolated DC/DC converter offers additional flexibility for placement of the shunt and the
AMC3302, enabling system layout optimization and smaller printed circuit board (PCB) size comparing to
solutions based on discrete components.
8.2 Typical Application
Isolated amplifiers are widely used for shunt-based current measurements in high-voltage applications that must
be isolated from a low-voltage domain. Typical applications are phase current measurements in motor and servo
drives or solar inverters, or DC current measurements at the output of a power factor correction (PFC) stage or
DC/DC converter. The AMC3302 integrates an isolated power supply for the high-voltage side and therefore is
particularly easy to use in applications that do not have a high-side supply readily available or where a high-side
supply is referenced to a different ground potential than the signal to be measured.
Figure 8-1 shows a simplified schematic using the AMC3302 to measure the phase current in the output stage of
a solar inverter. At this location in the system, there is no supply readily available for powering the isolated
amplifier. The integrated isolated power supply solves this problem and, together with its bipolar input voltage
range, makes the AMC3302 ideally suited for AC current sensing. In this example, the AC line-voltage is sensed
by the AMC3302 on the grid-side where there is also no suitable supply available for powering the isolated
amplifier. The integrated power supply, high input impedance, and bipolar input voltage range of the AMC3302
makes the device ideally suited for grid-side AC voltage sensing applications.
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DC+
SW
SW
HS Gate
Driver
Supply
N
PGND
IPHASE
to grid (L1)
RSHUNT
PGND
RL11
LS Gate
Driver
Supply
RL1SNS
DC-
PGND
RL12
AMC3302
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
N
DCDC_GND
DIAG
47 kΩ
to uC (optional)
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
INP
3.3 V / 5 V supply
10 Ω
10 Ω
8.2 nF
OUTP
ADS8363
to MCU
16-Bit ADC
INN
OUTN
HGND
GND
GND
AMC3330
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
47 kΩ
to uC (optional)
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
INP
3.3 V / 5 V supply
10 Ω
8.2 nF
OUTP
ADS8363
to MCU
16-Bit ADC
INN
OUTN
10 Ω
HGND
GND
GND
Figure 8-1. The AMC3302 in a Solar Inverter Application
8.2.1 Design Requirements
Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER
Supply voltage
VALUE
3.3 V or 5 V
Voltage drop across the shunt for a linear response (VSHUNT
)
±50 mV (maximum)
8.2.2 Detailed Design Procedure
The AMC3302 requires a single 3.3-V or 5-V supply on its low side. The high-side supply is internally generated
by an integrated DC/DC converter as explained in Section 7.3.4.
The ground reference (HGND) is derived from the terminal of the shunt resistor that is connected to the negative
input of the AMC3302 (INN). If a four-pin shunt is used, the inputs of the AMC3302 are connected to the inner
leads and HGND is connected to one of the outer shunt leads. To minimize offset and improve accuracy, set the
ground connection to a separate trace that connects directly to the shunt resistor rather than shorting HGND to
INN directly at the input to the device. See Section 10 for more details.
8.3 What to Do and What Not to Do
Do not leave the analog inputs INP and INN of the AMC3302 unconnected (floating) when the device is powered
up. If the device input is left floating, the input bias current may drive the inputs to a positive value that exceeds
the operating common-mode input voltage and the output of the device is undetermined.
Connect the high-side ground (HGND) to INN, either directly or through a resistive path. A DC current path
between INN and HGND is required to define the input common-mode voltage. Take care not to exceed the input
common-mode range as specified in the Electrical Characteristics table in Section 6. For best accuracy, set the
ground connection to a separate trace that connects directly to the shunt resistor rather than shorting HGND to
INN directly at the input to the device. See Section 10 for more details.
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9 Power Supply Recommendations
The AMC3302 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V (or 5 V) ± 10%.
TI recommends a low-ESR decoupling capacitor of 1 nF (C8 in Figure 9-1) placed as close as possible to the
VDD pin, followed by a 1-µF capacitor (C9) to filter this power-supply path.
The primary-side of the DC/DC converter is decoupled with a low-ESR 100-nF capacitor (C4) positioned close to
the device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the secondary
side in addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to
the DCDC_OUT and DCDC_HGND pins.
For the secondary-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the
AMC3302, followed by a 100-nF decoupling capacitor (C5).
The ground reference for the secondary-side (HGND) is derived from the terminal of the shunt resistor which is
connected to the negative input (INN) of the device. For best DC accuracy, use a separate trace to make this
connection instead of shorting HGND to INN directly at the device input. The high-side DC/DC ground terminal
(DCDC_HGND) is shorted to HGND directly at the device pins.
C2 C3
1 µF 1nF
C4
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
Resonator
And
Driver
Rectifier
R1
47 kΩ
Diagnostics
to MCU (optional)
C1
100 nF
LDO_OUT
VDD
LDO
LDO
C5 C6
100 nF 1 nF
C8 C9
1 nF 1 µF
HLDO_OUT
INP
I
3.3 V / 5 V supply
R2
C10
10 Ω 8.2 nF
OUTP
to ADC
INN
OUTN
to ADC
R4
10 Ω
HGND
GND
AMC3302
GND
Figure 9-1. Decoupling the AMC3302
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Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
Table 9-1 lists components suitable for use with the AMC3302. This list is not exhaustive. Other components
may exist that are equally suitable (or better), however these listed components have been validated during the
development of the AMC3302.
Table 9-1. Recommended External Components
DESCRIPTION
PART NUMBER
MANUFACTURER
SIZE (EIA, L x W)
VDD
C8
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
12065C102KAT2A
12063C105KAT2A
AVX
AVX
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C9
DC/DC CONVERTER
C4
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C0603C102K5RACTU
Kemet
Kemet
TDK
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
C3
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
C2
CGA3E1X7R1E105K080AC
HLDO
C1
100 nF ± 10%, X7R, 50 V
100 nF ± 5%, NP0, 50 V
1 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C3216NP01H104J160AA
12065C102KAT2A
Kemet
TDK
0603, 1.6 mm x 0.8 mm
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C5
C6
AVX
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10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors. The same
component reference designators are used as in Section 9. Decoupling capacitors are placed as close as
possible to the AMC3302 supply pins. For best performance, place the shunt resistor close to the INP and INN
inputs of the AMC3302 and keep the layout of both connections symmetrical.
To avoid causing errors in the measurement by the input bias currents of the AMC3302, connect the high-side
ground pin (HGND) to the IIN-side of the shunt resistor. Use a separate trace in the layout to make this
connection to maintain equal currents in the IIN and INP traces.
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
DIAG To MCU I/O (optional)
AMC3302
VDD 3.3-V or 5-V supply
INP
R2
OUTP To analog filter / ADC / MCU
OUTN To analog filter / ADC / MCU
R4
INN
GND
HGND
Top Metal
Inner or Bottom Layer Metal
Via
Figure 10-1. Recommended Layout of the AMC3302
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Texas Instruments, Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier data sheet
Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
•
•
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC3302DWE
AMC3302DWER
PAMC3302DWER
PREVIEW
SOIC
SOIC
SOIC
DWE
16
16
16
40
RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
PREVIEW
ACTIVE
DWE
2000 RoHS (In work)
& Non-Green
Call TI
Call TI
DWE
2000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
8
9
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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