AMC3330DWER [TI]
AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter;
| 型号： | AMC3330DWER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AMC3330 Precision, ±1-V Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter |
| 文件： | 总37页 (文件大小：1878K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX8108, TMUX8109
SCDS435A – SEPTEMBER 2021 – REVISED DECEMBER 2021
TMUX810x 100-V, Flat RON, Single 8:1 and Dual 4:1 Multiplexers
with Latch-Up Immunity and 1.8-V Logic
1 Features
3 Description
•
High supply voltage capable:
The TMUX8108 and TMUX8109 are modern high
voltage capable analog multiplexers in 8:1 (single
ended) and 4:1 (differential) configurations. The
devices work well with dual supplies, a single supply,
or asymmetric supplies up to a maximum supply
voltage of 100 V. The TMUX810x devices provide
consistent analog parametric performance across the
entire supply voltage range. The TMUX8108 and
TMUX8109 support bidirectional analog and digital
signals on the source (Sx) and drain (Dx) pins.
– Dual supply: ±10 V to ±50 V
– Single supply: 10 V to 100 V
– Asymmetric dual supply operation
Consistent parametrics across supply voltages
Latch-up immune
•
•
•
•
•
•
•
•
•
•
•
•
•
Low crosstalk: –110 dB
Low input leakage: 40 pA
Low on resistance flatness: 0.5 Ω
Removes need for additional logic rail (VL)
1.8 V Logic capable
Fail-safe logic: up to 48 V independent of supply
Integrated pull-down resistor on logic pins
Bidirectional signal path
All logic inputs support logic levels of 1.8 V, 3.3 V, 5V
and can be connected as high as 48 V, allowing for
system flexibility with control signal voltage. Fail-safe
logic circuitry allows voltages on the logic pins to be
applied before the supply pin, protecting the device
from potential damage.
Break-before-make switching
Wide operating temperature TA: –40°C to 125°C
Industry-standard TSSOP and
smaller WQFN packages
The device family provides latch-up immunity,
preventing undesirable high current events between
parasitic structures within the device. A latch-up
condition typically continues until the power supply
rails are turned off and can lead to device failure.
The latch-up immunity feature allows this family of
multiplexers to be used in harsh environments.
2 Applications
•
•
•
•
•
•
•
•
•
•
High voltage bidirectional switching
Analog and digital multiplexing and demultiplexing
Semiconductor test equipment
LCD test equipment
Battery test equipment
Data acquisition systems (DAQ)
Digital multi-meter (DMM)
Factory automation and control
Programmable logic controllers (PLC)
Analog input modules
Device Information
PART NUMBER(1)
PACKAGE
TSSOP (16)
WQFN (16)(2)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
TMUX8108
TMUX8109
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Preview package.
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A0
A1
A2
A0
A1
EN
Logic Decoder
EN
Logic Decoder
TMUX8108
TMUX8109
TMUX8108 and TMUX8109 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX8108, TMUX8109
SCDS435A – SEPTEMBER 2021 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings: TMUX810x Devices...... 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions:
8.6 Transition Time......................................................... 20
8.7 Charge Injection........................................................21
8.8 Off Isolation...............................................................21
8.9 Crosstalk...................................................................22
8.10 Bandwidth............................................................... 23
8.11 THD + Noise............................................................23
9 Detailed Description......................................................24
9.1 Overview...................................................................24
9.2 Functional Block Diagram.........................................24
9.3 Feature Description...................................................24
9.4 Device Functional Modes..........................................26
10 Application and Implementation................................27
10.1 Application Information........................................... 27
10.2 Typical Application.................................................. 27
11 Power Supply Recommendations..............................29
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 30
13 Device and Documentation Support..........................31
13.1 Documentation Support.......................................... 31
13.2 Receiving Notification of Documentation Updates..31
13.3 Support Resources................................................. 31
13.4 Trademarks.............................................................31
13.5 Electrostatic Discharge Caution..............................31
13.6 Glossary..................................................................31
14 Mechanical, Packaging, and Orderable
TMUX810x Devices.......................................................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics (Global): TMUX810x
Devices..........................................................................7
7.6 Electrical Characteristics (±15-V Dual Supply)........... 7
7.7 Electrical Characteristics (±36-V Dual Supply)........... 8
7.8 Electrical Characteristics (±50-V Dual Supply)........... 9
7.9 Electrical Characteristics (72-V Single Supply).........10
7.10 Electrical Characteristics (100-V Single Supply).....11
7.11 Switching Characteristics: TMUX810x Devices...... 12
7.12 Typical Characteristics............................................13
8 Parameter Measurement Information..........................18
8.1 On-Resistance.......................................................... 18
8.2 Off-Leakage Current................................................. 18
8.3 On-Leakage Current................................................. 19
8.4 Break-Before-Make Delay.........................................19
8.5 Enable Turn-on and Turn-off Time............................20
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2021) to Revision A (December 2021)
Page
•
Changed the status of the data sheet from: Advanced Information to: Production Data ...................................1
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SCDS435A – SEPTEMBER 2021 – REVISED DECEMBER 2021
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5 Device Comparison Table
PRODUCT
TMUX8108
TMUX8109
DESCRIPTION
Single channel 8:1 multiplexer
Dual channel 4:1 multiplexer
6 Pin Configuration and Functions
A0
EN
VSS
S1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
A2
GND
VDD
S5
VSS
S1
1
2
3
4
12
11
10
9
GND
VDD
S5
Thermal
Pad
S2
S2
S3
S6
S3
S6
S4
S7
D
S8
Not to scale
Not to scale
Figure 6-2. RUM Package 16-Pin WQFN Top View
Figure 6-1. PW Package 16-Pin TSSOP Top View
Table 6-1. Pin Functions: TMUX8108
PIN
TSSOP
1
TYPE(1)
DESCRIPTION
NAME
WQFN
A0
15
I
I
Logic control input address 0 (A0).
Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when
the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
EN
2
3
16
1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor
ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
P
S1
S2
S3
S4
D
4
5
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Source pin 3. Can be an input or output.
Source pin 4. Can be an input or output.
Drain pin. Can be an input or output.
Source pin 8. Can be an input or output.
Source pin 7. Can be an input or output.
Source pin 6. Can be an input or output.
Source pin 5. Can be an input or output.
6
4
7
5
8
6
S8
S7
S6
S5
9
7
10
11
12
8
9
10
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect
a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
13
11
P
GND
A2
14
15
16
12
13
14
P
I
Ground (0 V) reference
Logic control input address 2 (A2).
Logic control input address 1 (A1).
A1
I
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for the
best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power
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A0
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A1
GND
VDD
S1B
S2B
S3B
S4B
DB
VSS
S1A
S2A
S3A
S4A
DA
VSS
S1A
S2A
S3A
1
2
3
4
12
11
10
9
VDD
S1B
S2B
S3B
Thermal
Pad
Not to scale
Not to scale
Figure 6-4. RUM Package 16-Pin WQFN Top View
Table 6-2. Pin Functions: TMUX8109
Figure 6-3. PW Package 16-Pin TSSOP Top View
PIN
TSSOP
1
TYPE(1)
DESCRIPTION
NAME
WQFN
A0
15
I
I
Logic control input address 0 (A0).
Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when
the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
EN
2
3
16
1
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor
ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
P
S1A
S2A
S3A
S4A
DA
4
5
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1A. Can be an input or output.
Source pin 2A. Can be an input or output.
Source pin 3A. Can be an input or output.
Source pin 4A. Can be an input or output.
Drain terminal A. Can be an input or output.
Drain terminal B. Can be an input or output
Source pin 4B. Can be an input or output.
Source pin 3B. Can be an input or output.
Source pin 2B. Can be an input or output.
Source pin 1B. Can be an input or output.
6
4
7
5
8
6
DB
9
7
S4B
S3B
S2B
S1B
10
11
12
13
8
9
10
11
Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect
a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
14
12
P
GND
A1
15
16
13
14
P
I
Ground (0 V) reference
Logic control input address 1 (A1).
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for the
best performance.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
110
110
0.5
UNIT
V
VDD–VSS
VDD
Supply voltage
–0.5
–110
–0.5
–30
V
VSS
V
VAx or VEN
IAx or IEN
VS or VD
IDC (CONT)
Logic control input pin voltage (Ax, EN)
Logic control input pin current (Ax, EN)
Source or drain voltage (Sx, D)
Source or drain continuous current (Sx, D)
Diode clamp current at 85°C
Diode clamp current at 125°C
Storage temperature
50
V
30
mA
V
VSS–2
–100
–100
–15
VDD+2
100
100
15
mA
mA
mA
°C
°C
°C
mW
(2)
IIK
Tstg
TA
–65
150
150
150
720
Ambient temperature
–55
TJ
Junction temperature
(3)
Ptot
Total power dissipation (TSSOP)
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(3) For TSSOP package: Ptot derates linearly above TA = 70°C by 10.5 mW/°C
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
±2000
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
UNIT
V
(1)
VDD – VSS
VDD
Power supply voltage differential
100
100
VDD
48
Positive power supply voltage
10
V
(2)
VS or VD
VA or VEN
TA
Signal path input/output voltage (source or drain pin)
Address or enable pin voltage
VSS
0
V
V
Ambient temperature
–40
VSS
–40
125
VDD
125
100
75
°C
V
(2)
VS or VD
TA
Signal path input/output voltage (source or drain pin)
Ambient temperature
°C
mA
mA
mA
mA
IDC 1ch.(3)
Continuous current through switch for TSSOP or QFN on 1 channel
TA = 25°C
Continuous current through switch on all channels at the
same time, TSSOP package
IDC All ch.(4)
TA = 85°C
50
TA = 125°C
25
(1) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 100 V, and the minimum VDD is met.
(2) VS or VD is the voltage on any Source or Drain pins.
(3) Max continuous current shown for a single channel at a time.
(4) Max continuous current shown for all channels at a time. Refer to max power dissipation (Ptot) to ensure package limitations are not
violated.
7.4 Thermal Information
TMUX8108
PW (TSSOP)
16 PINS
97.0
TMUX8109
PW (TSSOP)
16 PINS
96.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
26.7
26.5
43.8
43.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
1.1
ΨJB
43.1
42.5
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics (Global): TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
LOGIC INPUTS
VIH
VIL
IIH
Logic voltage high
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
1.3
0
48
0.8
3.8
V
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
Logic inputs = 0 V, 5 V, or 48 V
Logic inputs = 0 V, 5 V, or 48 V
0.4
µA
µA
pF
IIL
–0.2 –0.005
3
CIN
POWER SUPPLY
25°C
250
250
500
500
500
420
420
420
µA
µA
µA
µA
µA
µA
IDD
VDD supply current
Logic inputs = 0 V, 5 V, or 48 V
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +85°C
–40°C to +125°C
25°C
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
7.6 Electrical Characteristics (±15-V Dual Supply)
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
38
55
VS = –10 V to +10 V
ID = –5 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
75
90
Ω
Ω
0.65
On-resistance mismatch between VS = –10 V to +10 V
ΔRON
–40°C to +85°C
–40°C to +125°C
1.5
2.1
channels
ID = –5 mA
VS = –10 V to +10 V
ID = –5 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.5
Ω
VS = 0 V, IS = –5 mA
–40°C to +125°C
25°C
0.25
0.01
Ω/°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
IS(OFF)
–15
15
VD = –10 V / +10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
0.04
0.04
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
ID(OFF)
–40
40
VD = –10 V / +10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
5
50
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
900
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 Electrical Characteristics (±36-V Dual Supply)
VDD = +36 V ± 10%, VSS = –36 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
38
48
VS = -25 V to +25 V
ID = –5 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
65
80
Ω
Ω
0.65
On-resistance mismatch between VS = -25 V to +25 V
ΔRON
–40°C to +85°C
–40°C to +125°C
1.5
2.1
channels
ID = –5 mA
VS = -25 V to +25 V
ID = –5 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.9
Ω
VS = 0 V, IS = –5 mA
–40°C to +125°C
25°C
0.25
0.01
Ω/°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
IS(OFF)
–15
15
VD = –25 V / +25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
0.06
0.06
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
ID(OFF)
–40
40
VD = –25 V / +25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
5
30
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
100
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 Electrical Characteristics (±50-V Dual Supply)
VDD = +50 V, VSS = –50 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
38
48
VS = –45 V to +45 V
ID = –5 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
65
80
Ω
Ω
0.65
On-resistance mismatch between VS = –45 V to +45 V
ΔRON
–40°C to +85°C
–40°C to +125°C
1.5
2.1
channels
ID = –5 mA
VS = –45 V to +45 V
ID = –5 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
1
Ω
VS = 0 V, IS = –5 mA
–40°C to +125°C
25°C
0.25
0.02
Ω/°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
nA
nA
nA
pA
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
IS(OFF)
–15
15
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
0.09
0.09
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
ID(OFF)
–40
40
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
IS(ON)
ID(ON)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
10
40
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
85°C
125°C
170
(1) When VS is positive,VD is negative. And when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.9 Electrical Characteristics (72-V Single Supply)
VDD = +72 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
38
48
VS = 0 V to +60 V
ID = –5 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
65
80
Ω
Ω
0.65
On-resistance mismatch between VS = 0 V to +60 V
ΔRON
–40°C to +85°C
–40°C to +125°C
1.5
2.1
channels
ID = –5 mA
VS = 0 V to +60 V
ID = –5 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.6
Ω
VS = 0 V, IS = –5 mA
–40°C to +125°C
25°C
0.25
0.02
Ω/°C
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
nA
pA
–15
15
0.06
0.07
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
IS(ON)
ID(ON)
Switch state is on
VS = VD = 1 V / +60 V
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
20
50
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +60 V
85°C
125°C
120
(1) When VS is 60 V, VD is 1 V. Or when VS is 1 V, VD is 60 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Electrical Characteristics (100-V Single Supply)
VDD = +100 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
38
48
VS = 0 V to +95 V
ID = –5 mA
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
65
80
Ω
Ω
0.65
On-resistance mismatch between VS = 0 V to +95 V
ΔRON
–40°C to +85°C
–40°C to +125°C
1.5
2.1
channels
ID = –5 mA
VS = 0 V to +95 V
ID = –5 mA
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
25°C
0.6
Ω
VS = 0 V, IS = –5 mA
–40°C to +125°C
25°C
0.25
0.02
Ω/°C
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
IS(OFF)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
25°C
–3
3
nA
nA
nA
pA
–15
15
0.09
0.1
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
ID(OFF)
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
IS(ON)
ID(ON)
Switch state is on
VS = VD = 1 V / +95 V
–40°C to +85°C
–40°C to +125°C
25°C
–8
8
–40
40
50
120
350
ΔIS(ON)
ΔID(ON)
Leakage current mismatch
between channels(2)
Switch state is on
VS = VD = 1 V / +95 V
85°C
125°C
(1) When VS is 95 V, VD is 1 V. Or when VS is 1 V, VD is 95 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.11 Switching Characteristics: TMUX810x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
3
VS = 10 V
RL = 10 kΩ, CL = 15 pF
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
10
12
µs
µs
µs
3
0.65
3
VS = 10 V
RL = 10 kΩ, CL = 15 pF
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
14
15
(EN)
VS = 10 V
RL = 10 kΩ, CL = 15 pF
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
3
3
(EN)
VS = 10 V,
RL = 10 kΩ, CL = 15 pF
tBBM
–40°C to +85°C
–40°C to +125°C
0.1
0.1
µs
µs
VDD ramp rate = 1 V/µs,
VS = 10 V,
RL = 10 kΩ, CL = 15pF
Device turn on time
(VDD to output)
TON (VDD)
25°C
75
tPD
Propagation delay
Charge injection
RL = 50 Ω , CL = 5 pF
25°C
25°C
550
ps
QINJ
VS = (VDD + VSS) / 2, CL = 1 nF
–150
pC
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
OISO
Off isolation
Crosstalk
25°C
25°C
–110
–110
dB
dB
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1MHz
XTALK
BW
BW
–3dB bandwidth (TMUX8108)
–3dB bandwidth (TMUX8109)
200
380
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2
25°C
25°C
MHz
dB
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
IL
Insertion loss
–2.8
Dual supply voltage
VPP = 5 V, VBIAS = (VDD + VSS) / 2
RL = 1 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total harmonic distortion + Noise
Source off capacitance
25°C
0.003
%
CS(OFF)
CD(OFF)
VS = (VDD + VSS) / 2, f = 1 MHz
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
25°C
3
pF
pF
Drain off capacitance
(TMUX8108)
20
Drain off
capacitance (TMUX8109)
CD(OFF)
VS = (VDD + VSS) / 2, f = 1 MHz
VS = (VDD + VSS) / 2, f = 1 MHz
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
25°C
25°C
10
21
12
pF
pF
pF
CS(ON),
CD(ON)
On capacitance (TMUX8108)
On capacitance (TMUX8109)
CS(ON),
CD(ON)
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7.12 Typical Characteristics
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
Flatest Ron Region
VDD = 36 V, VSS = –36 V
Figure 7-2. On-Resistance vs Source or Drain Voltage
Figure 7-1. On-Resistance vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
Dual Supply Voltages
Figure 7-3. On-Resistance vs Source or Drain Voltage
Figure 7-4. On-Resistance vs Source or Drain Voltage
VDD = 15 V, VSS = –15 V
VDD = 15 V, VSS = –15 V
Figure 7-5. On-Resistance vs Source or Drain Voltage
Figure 7-6. On-Resistance vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 72 V, VSS = 0 V
VDD = 72 V, VSS = 0 V
Figure 7-7. On-Resistance vs Source or Drain Voltage
Figure 7-8. On-Resistance vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
VDD = 100 V, VSS = 0 V
Figure 7-9. On-Resistance vs Source or Drain Voltage
Figure 7-10. On-Resistance vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
TMUX8108
VDD = 36 V, VSS = –36 V
TMUX8109
Figure 7-11. Leakage Current vs Temperature
Figure 7-12. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
TMUX8108
VDD = 36 V, VSS = –36 V
TMUX8109
Figure 7-13. Leakage Current vs Temperature
Figure 7-14. Leakage Current vs Temperature
VDD = 72 V, VSS = 0 V
TMUX8108
VDD = 72 V, VSS = 0 V
TMUX8109
Figure 7-15. Leakage Current vs Temperature
Figure 7-16. Leakage Current vs Temperature
VDD = 100 V, VSS = 0 V
TMUX8108
VDD = 100 V, VSS = 0 V
TMUX8109
Figure 7-17. Leakage Current vs Temperature
Figure 7-18. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
VDD = 36 V, VSS = –36 V
TMUX8108
TMUX8109 and TMUX8109
Figure 7-19. IS(OFF) Leakage Current vs Source or Drain Voltage
Figure 7-20. Leakage Current vs Source or Drain Voltage
VDD = 36 V, VSS = –36 V
TMUX8109
VDD = 100 V, VSS = 0 V
TMUX8108 and TMUX8109
Figure 7-21. Leakage Current vs Source or Drain Voltage
Figure 7-22. IS(OFF) Leakage Current vs Source or Drain Voltage
VDD = 100 V, VSS = 0 V
TMUX8108
VDD = 100 V, VSS = 0 V
TMUX8109
Figure 7-23. Leakage Current vs Source or Drain Voltage
Figure 7-24. Leakage Current vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
VDD = 36 V, VSS = –36 V
.
Figure 7-25. Charge Injection vs Source Voltage
Figure 7-26. Supply Current vs Temperature
VDD = 36 V, VSS = –36 V
TA = 25°C
Figure 7-27. Turn-On and Turn-Off Times vs Source Voltage
Figure 7-28. Off Isolation vs Frequency
TA = 25°C
Bandwidth
Figure 7-29. Crosstalk vs Frequency
Figure 7-30. Insertion Loss vs Frequency
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX8108 and TMUX8109 is the ohmic resistance across the source (Sx) and drain
(Dx) pins of the device. The on-resistance varies with input voltage and supply voltage. Figure 8-1 shows how
the symbol RON is used to denote on-resistance. The measurement setup used to measure RON is shown in .
ΔRON represents the difference between the RON of any two channels, while RON_FLAT denotes the flatness that
is defined as the difference between the maximum and minimum value of on-resistance measured over the
specified analog signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
Figure 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
Figure 8-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
SW
SW
SW
SW
S1
S2
S1
S2
ID (OFF)
VS
D
D
A
GND
VD
SW
SW
S8
S8
VD
GND
VS
GND
GND
GND
GND
IS(OFF)
ID(OFF)
Figure 8-2. Off-Leakage Measurement Setup
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. Figure 8-3 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
IS(ON)
A
SW
SW
SW
SW
S1
S2
S1
S2
N.C.
ID(ON)
A
D
D
VS
GND
N.C.
SW
SW
VD
S8
S8
GND
VS
VS
GND
GND
GND
GND
IS(ON)
ID(ON)
Figure 8-3. On-Leakage Measurement Setup
8.4 Break-Before-Make Delay
The break-before-make delay is a safety feature of the TMUX8108 and TMUX8109. The ON switches first break
the connection before the OFF switches make connection. The time delay between the break and the make
is known as break-before-make delay. Figure 8-4 shows the setup used to measure break-before-make delay,
denoted by the symbol tBBM
.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
D
tr < 20 ns
VA
tf < 20 ns
0 V
CL
RL
GND
GND
SW
SW
S7
S8
GND
VS
0.8 VS
Output
A0
A1
tBBM
1
tBBM 2
VS
EN
0 V
Decoder
tBBM = min ( tBBM 1, tBBM 2)
A2
GND
VEN
VA
GND
GND
GND
Figure 8-4. Break-Before-Make Delay Measurement Setup
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8.5 Enable Turn-on and Turn-off Time
tON(EN) time is defined as the time taken by the output of the TMUX8108 and TMUX8109 to rise to a 90% final
value after the EN signal has risen to a 50% final value. tOFF(EN) is defined as the time taken by the output of
the TMUX8108 and TMUX8109 to fall to a 10% final value after the EN signal has fallen to a 50% initial value.
Figure 8-5 shows the setup used to measure the enable delay time.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
3 V
0 V
VS
D
tr < 20 ns
tf < 20 ns
50%
50%
VEN
GND
RL
GND
CL
SW
S8
0.9
GND
tOFF(EN)
0.1
GND
tON(EN)
Output
A0
A1
EN
Decoder
A2
VEN
GND
GND
GND
Figure 8-5. Enable Delay Measurement Setup
8.6 Transition Time
Transition time is defined as the time taken by the output of the device to rise (to 90% of the transition) or fall (to
10% of the transition) after the address signal (Ax) has fallen or risen to 50% of the transition. Figure 8-6 shows
the setup used to measure transition time, denoted by the symbol tTRAN
.
VDD
VSS
0.1 µF
0.1 µF
GND
VDD
VSS
GND
S1
SW
SW
3 V
S2
tr < 20 ns
tf < 20 ns
50%
50%
VA
VS
D
0 V
GND
RL
GND
0.9
CL
SW
S8
Output
tTRAN
1
tTRAN
2
GND
0.1
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
A0
A1
EN
Decoder
A2
VEN
VA
GND
GND
GND
Figure 8-6. Transition Time Measurement Setup
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8.7 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during
switching, and is denoted by the symbol QINJ. Figure 8-7 shows the setup used to measure charge injection from
the source to drain.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
SW
SW
S1
S2
Output
VS
D
3 V
VEN
0 V
GND
CL
SW
S8
tr < 20 ns
tf < 20 ns
GND
GND
A0
A1
Output
VS
EN
VOUT
QINJ = CL ×
VOUT
Decoder
A2
VEN
GND
GND
GND
Figure 8-7. Charge-Injection Measurement Setup
8.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance for the measurement (ZO) is 50 Ω. Figure 8-8
shows the setup used to measure off isolation.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
50Ω
Ax, EN
VAX
VEN
GND
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
Figure 8-8. Off Isolation Measurement Setup
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8.9 Crosstalk
There are two types of crosstalk that can be defined for the devices:
1. Intra-channel crosstalk (XTALK(INTRA)): the voltage at the source pin (Sx) of an off-switch input when a signal
is applied at the source pin of an on-switch input in the same channel, as shown in Figure 8-9 .
2. Inter-channel crosstalk (XTALK(INTER)): the voltage at the source pin (Sx) of an on-switch input when a
signal is applied at the source pin of an on-switch input in a different channel, as shown in Figure 8-10.
Inter-channel crosstalk applies only to the TMUX8109 device.
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SW
S1/S1X
D/ DX
VOUT
S2/S2X
RS
RL
Other
Sx/ Dx
Pins
50Ω
SW
VS
N.C.
Ax, EN
GND
VAX
VEN
8176
+JPN= F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-9. Intra-channel Crosstalk Measurement Setup
VDD
VSS
0.1 µF
GND
0.1 µF
GND
VDD
VSS
Network Analyzer
SW
SxA
DA
Other
SxA Pins
SW
SW
N.C.
N.C.
RS
RL
VOUT
SxB
DB
Other
SxB Pins
SW
50Ω
RL
VS
Ax, EN
GND
VAX
VEN
8176
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8
5
Figure 8-10. Inter-channel Crosstalk Measurement Setup
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8.10 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D or Dx) of the TMUX810x.
Figure 8-11 shows the setup used to measure bandwidth of the switch.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Network Analyzer
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
50Ω
Ax, EN
VAX
VEN
GND
8176
$=J@SE@PD = 20 × .KC
8
5
Figure 8-11. Bandwidth Measurement Setup
8.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at
the multiplexer output. The on-resistance of the TMUX8108 and TMUX8109 varies with the amplitude of the
input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic
distortion plus noise is denoted as THD+N. Figure 8-12 shows the setup used to measure THD+N of the
devices.
VDD
VSS
0.1 µF
GND
0.1 µF
VDD
VSS
Audio Precision
GND
SW
SW
SX
N.C.
N.C.
Other
Sx/ Dx
Pins
RS
SW
VOUT
D/ DX
VS
RL
Ax, EN
GND
VAX
VEN
Figure 8-12. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX8108 and TMUX8109 are modern complementary metal-oxide semiconductor (CMOS) analog
multiplexers in 8:1 (single ended) and 4:1 (differential) configurations. The devices work well with dual supplies,
a single supply, or asymmetric supplies up to 100 V.
9.2 Functional Block Diagram
VDD
VSS
VDD
VSS
SW
SW
SW
S1
S2
S1A
DA
DB
SW
SW
S4A
S1B
D
SW
SW
S4B
S8
A0
A1
A2
A0
A1
EN
Logic Decoder
EN
Logic Decoder
TMUX8108
TMUX8109
9.3 Feature Description
9.3.1 Bidirectional Operation
The TMUX8108 and TMUX8109 conduct equally well from source (Sx) to drain (D or Dx) or from drain (D or Dx)
to source (Sx). Each signal path has very similar characteristics in both directions.
9.3.2 Flat On – Resistance
The TMUX8108 and TMUX8109 are designed with a special switch architecture to produce ultra-flat on-
resistance (RON) across most of the switch input operating region. The flat RON response allows the device
to be used in precision sensor applications since the RON is controlled regardless of the signals sampled. The
architecture is implemented without a charge pump so no unwanted noise is produced from the device to affect
sampling accuracy.
The flatest on-resistance region extends from VSS to roughly 5 V below VDD. Once the signal is within 5 V of VDD
the on-resistance will exponentially increase and may impact desired signal transmission.
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9.3.3 Protection Features
The TMUX8108 and TMUX8109 offer a number of protection features to enable robust system implementations.
9.3.3.1 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. Additionaly the fail safe logic feature allows the logic inputs of the mux to be
interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present.
The logic inputs are protected against positive faults of up to +48 V in powered-off condition, but do not offer
protection against negative overvoltage condition.
Fail-safe logic also allows the devices to interface with a voltage greater than VDD on the control pins during
normal operation to add maximum flexibility in system design. For example, with a VDD = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 48 V.
9.3.3.2 ESD Protection
All pins on the TMUX8108 and TMUX8109 support HBM ESD protection level up to ±2 kV, which helps protect
the devices from ESD events during the manufacturing process.
9.3.3.3 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX8108 and TMUX8109 devices, an insulating oxide layer is placed on top of the silicon substrate
to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all
circumstances by device construction.
The TMUX8108 and TMUX8109 devices are constructed on silicon on insulator (SOI) based process where
an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic
structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch
up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX8108 and
TMUX8109 to be used in harsh environments. For more information on latch-up immunity refer to Using Latch
Up Immune Multiplexers to Help Improve System Reliability.
9.3.4 1.8 V Logic Compatible Inputs
The TMUX8108 and TMUX8109 devices have 1.8 V logic compatible control for all logic control inputs. 1.8
V logic level inputs allows the TMUX8108 and TMUX8109 to interface with processors that have lower logic
I/O rails and eliminates the need for an external translator, which saves both space and bill of materials cost.
For more information on 1.8 V logic implementations, refer to Simplifying Design with 1.8 V logic Muxes and
Switches.
9.3.5 Integrated Pull-Down Resistor on Logic Pins
The TMUX8108 and TMUX8109 have internal weak pull-down resistors to GND to ensure the logic pins are not
left floating. The value of this pull-down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher
voltages. This feature integrates up to four external components and reduces system size and cost.
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9.4 Device Functional Modes
9.4.1 Normal Mode
In Normal Mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to
drain (D or Dx) or from drain (D or Dx) to source (Sx). Table 9-1 and Table 9-2 shows the address (Ax) pins and
the enable (EN) pin determines which switch path to turn on. The following conditions must be satisfied for the
switch to stay in the ON condition:
•
The difference between the primary supplies (VDD – VSS) must be greater than or equal to 10 V. With a
minimum VDD of 10 V.
•
•
The input signals on the source (Sx) or the drain (Dx) must be be between VDD and VSS.
The logic control address pins (Ax) must have selected the switch path.
9.4.2 Truth Tables
Table 9-1 shows the truth tables for the TMUX8108.
Table 9-1. TMUX8108 Truth Table
EN
0
A2
X(1)
0
A1
X(1)
0
A0
X(1)
0
Normal Condition
None
S1
1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
S8
(1) "X" means "do not care."
Table 9-2 shows the truth tables for the TMUX8109.
Table 9-2. TMUX8109 Truth Table
EN
0
A1
X(1)
0
A0
Normal Condition
X(1)
None
S1x
S2x
S3x
S4x
1
0
1
0
1
1
1
0
1
1
1
(1) "X" means "do not care."
If unused, address (Ax) pins must be tied to GND or Logic High in to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx
or Dx) should be connected to GND for best performance.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMUX8108 and TMUX8109 are high voltage multiplexers capable of supporting analog and digital signals.
The high voltage capability of these multiplexers allow them to be used in systems with high voltage signal
swings or in systems with high common mode voltages.
Additionally, the TMUX810x devices provide consistent analog parametric performance across the entire supply
voltage range allowing the devices to be powered by the most convient supply rails in the system while still
providing excellent performance.
10.2 Typical Application
Many analog front end data acquistion systems are designed to support differential input signals with a wide
range of output voltages. In systems where the output sensor is separated from the rest of the signal chain
by long cables, a high common mode voltage shift can superimpose on the signal lines. One solution to this
problem is to use a high voltage multiplexer in combination with a high voltage op amp level translation stage to
properly scale the input signals to the correct input requirements of the ADC. The TMUX8109 allows the system
to be designed for a differential, four channel, multiplexed data acquisition system.
+50V
REF
RC Filter
OPA
RC Filter
+
-
Differential
Input Signals
Up to 50V CM
+50V
Reference Driver
Gain Network
Gain Network
OPA454
+
+
-50V
+50V
TMUX8109
+50V
REF
-
+
OPA454
VINP
Charge
Kickback
Filter
+
Gain Network
OPA454
+
Differential
Input Signals
Up to 50V CM
TI ADC
-50V
-50V
VINM
-
-50V
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
ADC Stage
Figure 10-1. Typical Application
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10.2.1 Design Requirements
Table 10-1. Design Parameters
PARAMETER
Positive supply (VDD) mux and Op Amps
Negative supply (VSS) mux and Op Amps
Maximum input / output signals with common mode shift
Mux control logic thresholds
VALUE
+50 V
-50 V
-50 V to 50 V
1.8 V compatible, up to 48 V
-40°C to +125°C
Mux temperature range
10.2.2 Detailed Design Procedure
The multiplexed data aquistion circuit allows the system designer to have flexibility over both size and cost of
the end product. Utilizing a multiplexer can reduce board size and cost by reducing the number of op amp
circuits required for a multi-channel design. Additionally, the high voltage multiplexer can be paired with many
implementations of high voltage level translation circuits such as difference amplifiers, instrumentation amplifiers,
or fully differential amplifiers depending on the gain, noise requirements, and cost targets of the system.
In the example application, the TMUX8109 is paired with a difference amplifier and buffer stage op amps on both
the positive and negative differential signals. Many data aquistion systems will place a buffer op amp following
the mux for two reasons. The first reason is to eliminate the impact of the multiplexer on-resistance change
across the signal range, preventing gain errors in the system. Secondly, depending on the output impedance
of the sensors being interfaced, a high input impedance stage may be required to achieve system specification
targets. The TMUX810x multiplexers have exceptionally flat on-resistance and low leakge currents across the
signal voltage range and can potentially eliminate the need for buffer stage op amps depending on system
requirements. Additionally, excellent crosstalk and off-isolation performance, paired with low capacitance ratings
makes the TMUX810x multiplexers very flexible for system design of data aqusition systems.
A difference amplifier stage follows the multiplexer to eliminate the common mode voltage shift and can be used
to scale the input signals to match the dynamic range of the selected ADC. In this example, both the op amp and
multiplexer are rated for performance up to ±50 V. To find the maximum common mode voltage shift allowed, the
system designer should take the maximum supply voltage and subtract the maximum voltage of the differential
signal; the resulting voltage is the maximum common mode shift that can be accomodated without exceding the
input voltage requirements of the multiplexer. The difference amplifier circuit relies on the matched resistor for
good CMRR performance and typically has lower voltage gains and lower input impedances. If higher gains are
required, or for better CMRR performance, an instrumentation amplifier can be swapped into the circuit. Both
op amp solutions can be utilized to remove the common mode voltage offset and extract the true differential
signal. The high voltage multiplexer at the front end of the design requires the system to have high voltage
power supply rails to pass signals within VSS and VDD, this should be considered in the overal architecture of the
system design. This multiplexed application becomes increasingly valuable with larger number of input channels
by greatly reducing the total component count.
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10.2.3 Application Curves
The example application utilizes the excellent leakage and crosstalk performance of the TMUX810x devices to
reduce any impact introduced from a multiplexed system architecture. Figure 10-2 shows the leakage current for
both ON and OFF cases with a varrying temperature. Figure 10-3 shows the excellent crosstalk performance of
the TMUX810x devices. These features make the TMUX8108 and TMUX8109 an ideal solution for multiplexed
data acquisition applications that require excellent linearity and low distortion.
.
.
Figure 10-2. Leakage Current
Figure 10-3. Crosstalk
11 Power Supply Recommendations
The TMUX8108 and TMUX8109 operate across a wide supply range of ±10 V to ±50 V (10 V to 100 V in
single-supply mode). They also perform well with asymmetric supplies such as VDD = 50 V and VSS= –10 V.
For improved supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the
VDD and VSS pins to ground. An additional 0.1 µF capacitor placed closest to the supply pins will provide the
best supply decoupling solution. Always ensure the ground (GND) connection is established before supplies are
ramped.
12 Layout
12.1 Layout Guidelines
The following images illustrate an example of a PCB layout with the TMUX8108 and TMUX8109. Some key
considerations are:
•
For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and VSS to GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to
the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
•
•
•
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12.2 Layout Example
Via to
ground plane
Via to
ground plane
A0
A1
A2
Wide (low inductance)
trace for power
C
C
EN
C
C
VSS
GND
VDD
S5
Via to
ground plane
Wide (low inductance)
trace for power
S1
S2
S3
S4
D
TMUX8108
S6
S7
S8
Figure 12-1. TMUX8108 TSSOP Layout Example
Wide (low inductance)
trace for power
GND
VDD
S5
VSS
S1
Wide (low inductance)
trace for power
S2
S6
S3
Via to ground plane
Figure 12-2. TMUX8108 QFN Layout Example
Via to
ground plane
Via to
ground plane
Wide (low inductance)
trace for power
A0
EN
VSS
A1
C
C
C
C
Wide (low inductance)
trace for power
GND
VDD
S1B
S2B
S3B
S4B
DB
S1A
S2A
S3A
S4A
DA
TMUX8109
Figure 12-3. TMUX8109 TSSOP Layout Example
Wide (low inductance)
trace for power
VDD
S1B
S2B
S3B
VSS
S1A
S2A
S3A
Wide (low inductance)
trace for power
Via to ground plane
Figure 12-4. TMUX8109 QFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
Texas Instruments, Multiplexers and Signal Switches Glossary application report
Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMUX8108PWR
PTMUX8109PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000
2000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
Addendum-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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