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AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

AMC7836 12 位高密度模拟监视和控制解决方案，具有多通道模数转换器

(ADC)、双极数模转换器 (DAC)、温度传感器和通用输入输出 (GPIO) 端口

1 特性

3 说明

1

•

16 个单调性 12 位 DAC

AMC7836 是一款高度集成的低功耗、模拟监视和控制

解决方案。该器件包含一个 21 通道 12 位模数转换器

(ADC)、16 个具有可编程输出范围的 12 位数模转换器

(DAC)、8 个 GPIO、一个内部基准电压以及一个本地

温度传感器通道。该器件的高度集成特性显著减少组件

数量，同时简化了闭环系统设计，因此非常适合对电

路板空间、尺寸和低功耗严格要求的多通道应用。

–

可选范围：–10V 至 0V、–5V 至 0V、0V 至

5V、0V 至 10V

–

高电流驱动能力：高达 ±15mA

自动范围检测器

可选钳位电压

•

12 位逐次逼近寄存器 (SAR) ADC

–

21 个外部模拟输入

该器件具有低功耗、超高集成度和宽工作温度范围等诸

多优势，因此适合用作多通道射频 (RF) 通信系统中功

率放大器 (PA) 的一体化、低成本偏置控制电路。凭借

灵活的 DAC 输出范围，该器件可用作适用于多种晶体

管技术（例如 LDMOS、GaA 和 GaN）的偏置解决方

案。AMC7836 功能集对通用监视器和控制系统而言同

样有益。

–

16 个双极输入：-12.5V 至 12.5V

5 个高精度输入：0V 至 5V

–

可编程超限报警

•

2.5V 内部电压基准

内部温度传感器

–

运行温度范围：–40°C 至 +125°C

±2.5°C 精度

为满足各类应用对不同通道数、附加特性、或转换器

分辨率的需求，德州仪器 (TI) 提供了完备的模拟监视

和控制 (AMC) 产品系列。更多信息，敬请访问

www.ti.com.cn/amc。

•

8 个通用 I/O 端口 (GPIO)

兼容串行外设接口 (SPI) 的低功耗串行接口

–

4 线制模式，运行电压为 1.8V 至 5.5V

•

工作温度范围：-40°C 至 +125°C

器件信息⁽¹⁾

采用 64 引脚耐热增强型薄型四方扁平 (HTQFP) 封

装 PowerPAD™IC 封装

器件型号

AMC7836

封装

封装尺寸（标称值）

HTQFP (64)

10.00mm x 10.00mm

2 应用

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

•

通信基础设施：

–

蜂窝基站

微波回程

光纤网络

AMC7836

2.5-V Reference

•

通用监视器和控制

数据采集系统

ADC

DAC-0

Temperature

Sensor

DAC-15

GPIO Control

8 GPIOs

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLAS986

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

7.2 Functional Block Diagram ....................................... 24

7.3 Feature Description................................................. 25

7.4 Device Functional Modes........................................ 39

7.5 Programming........................................................... 42

7.6 Register Maps......................................................... 44

Application and Implementation ........................ 71

8.1 Application Information............................................ 71

8.2 Typical Application ................................................. 74

Power Supply Recommendations...................... 77

9.1 Device Reset Options ............................................. 78

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics: DAC ................................ 8

8

9

10 Layout................................................................... 78

10.1 Layout Guidelines ................................................. 78

10.2 Layout Example .................................................... 79

11 器件和文档支持 ..................................................... 80

11.1 文档支持................................................................ 80

11.2 接收文档更新通知 ................................................. 80

11.3 社区资源................................................................ 80

11.4 商标....................................................................... 80

11.5 静电放电警告......................................................... 80

11.6 Glossary................................................................ 80

12 机械、封装和可订购信息....................................... 80

6.6 Electrical Characteristics: ADC and Temperature

Sensor...................................................................... 10

6.7 Electrical Characteristics: General.......................... 11

6.8 Timing Requirements.............................................. 12

6.9 Typical Characteristics: DAC .................................. 14

6.10 Typical Characteristics: ADC ................................ 20

6.11 Typical Characteristics: Reference ....................... 22

6.12 Typical Characteristics: Temperature Sensor....... 22

Detailed Description ............................................ 23

7.1 Overview ................................................................. 23

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (April 2016) to Revision D

Page

•

Changed 4.5 V to 4.7 V in AV_DDdescription in Pin Functions .............................................................................................. 4

Changed 4.5 V to 4.7 V in DV_DDdescription in Pin Functions .............................................................................................. 5

Changed Supply voltage, AV_DDMIN value from 4.5 V to 4.7 V ............................................................................................ 7

Changed Supply voltage, DV_DDMIN value from 4.5 V to 4.7 V ............................................................................................ 7

Changed Supply voltage, AV_CCMIN value from 4.5 V to 4.7 V ............................................................................................ 7

Changed AV_DD= DV_DD= 4.5 to 5.5 V to AV_DD= DV_DD= 4.7 to 5.5 V in Electrical Characteristics: DAC conditions............ 8

Changed AV_DD= DV_DD= 4.5 to 5.5 V to AV_DD= DV_DD= 4.7 to 5.5 V in Electrical Characteristics: ADC and

Temperature Sensor conditions .......................................................................................................................................... 10

•

Changed AV_DD= DV_DD= 4.5 to 5.5 V to AV_DD= DV_DD= 4.7 to 5.5 V in Electrical Characteristics: General conditions .... 11

Changed AV_DD= DV_DD= 4.5 to 5.5 V to AV_DD= DV_DD= 4.7 to 5.5 V in Timing Requirements conditions ........................ 12

Added paragraph and Figure 59 to Internal Reference section ........................................................................................... 37

Changed 4.5 V to 4.7 V in All-Negative DAC Range Mode section .................................................................................... 40

已添加 paragraph to Power Supply Recommendations section .......................................................................................... 77

已添加 paragraph to Power Supply Recommendations section .......................................................................................... 78

Changes from Revision B (February 2015) to Revision C

Page

•

Changed Figure 117; corrected pins 63 and 64................................................................................................................... 74

Changes from Revision A (November 2014) to Revision B

Page

•

器件状态“产品预览”至“量产数据” ............................................................................................................................................ 1

2

AMC7836

www.ti.com.cn

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

5 Pin Configuration and Functions

PAP Package

64-Pin HTQFP With Exposed Thermal Pad

Top View

IOVDD_

RESET

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AGND2

ADC_0

2

SDO

3

ADC_1

SDI

4

ADC_2

SCLK

5

ADC_3

CS

6

ADC_4

GPIO0/ALARMIN

GPIO0/ALARMOUT

GPIO2/ADCTRIG

GPIO3/DAV

GPIO4

7

ADC_5

8

ADC_6

9

ADC_7

10

11

12

13

14

15

16

LV_ADC16

LV_ADC17

LV_ADC18

LV_ADC19

LV_ADC20

ADC_8

GPIO5

GPIO6

GPIO7

DAC_A0

DAC_A1

ADC_9

3

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

Pin Functions

DESCRIPTION

NAME

NO.

47

46

45

44

43

42

41

40

34

33

32

31

30

29

28

27

21

48

56

I/O

ADC_0

ADC_1

ADC_2

ADC_3

ADC_4

ADC_5

ADC_6

ADC_7

ADC_8

ADC_9

ADC_10

ADC_11

ADC_12

ADC_13

ADC_14

ADC_15

AGND1

AGND2

AGND3

I

Bipolar analog inputs. These pins are typically used to monitor the DAC group-C outputs. The

input range of these channels is –12.5 to 12.5 V.

Bipolar analog inputs. These pins are typically used to monitor the DAC group-D outputs. The

input range of these channels is –12.5 to 12.5 V.

Bipolar analog inputs. These pins are typically used to monitor the DAC group-B outputs. The

input range of these channels is –12.5 to 12.5 V.

Bipolar analog inputs. These pins are typically used to monitor the DAC group-A outputs. The

input range of these channels is –12.5 to 12.5 V.

Analog ground. These pins are the ground reference point for all analog circuitry on the device.

Connect the AGND1, AGND2, and AGND3 pins to the same potential (AGND). Ideally, the

analog and digital grounds should be at the same potential (GND) and must not differ by more

than ±0.3 V.

Positive analog power for DAC groups A and B. The AV_{CC_AB}and AV_{CC_CD}pins must be

connected to the same potential (AV_CC).

AV_{CC_AB}

20

I

Positive analog power for DAC groups C and D. The AV_{CC_AB}and AV_{CC_CD}pins must be

connected to the same potential (AV_CC).

AV_{CC_CD}

AV_DD

57

50

I

Analog supply voltage (4.7 V to 5.5 V). This pin must have the same value as the DV_DDpin.

Lowest potential in the system. This pin is typically tied to a negative supply voltage but if all

DACs are set in a positive output range, this pin can be connected to the analog ground. This

pin also acts as the negative analog supply for DAC group A. This pin sets the power-on-reset

and clamp voltage values for the DAC group A.

AV_EE

17

I

Negative analog supply for DAC group B. This pin sets the power-on-reset and clamp voltage

values for the DAC group B. This pin is typically tied to the AV_EEpin for the negative output

ranges or AGND for the positive output ranges.

AV_SSB

AV_SSC

24

53

I

Negative analog supply for DAC group C. This pin sets the power-on-reset and clamp voltage

values for the DAC group C. This pin is typically tied to the AV_EEpin for the negative output

ranges or AGND for the positive output ranges.

Negative analog supply for DAC group D. This pin sets the power-on-reset and clamp voltage

values for the DAC group D. This pin is typically tied to the AV_EEpin for the negative output

ranges or AGND for the positive output ranges.

AV_SSD

CS

60

6

I

Active-low serial-data enable. This input is the frame-synchronization signal for the serial data.

When this signal goes low, it enables the serial interface input shift register.

DAC_A0

DAC_A1

DAC_A2

DAC_A3

DAC_B4

DAC_B5

DAC_B6

DAC_B7

15

16

18

19

22

23

25

26

O

DAC group A. These DAC channels share the same range and clamp voltage. If any of the

other DAC groups is in a negative voltage range, DAC group A should be in a negative

voltage range as well.

DAC group B. These DAC channels share the same range and clamp voltage.

4

AMC7836

www.ti.com.cn

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

Pin Functions (continued)

DESCRIPTION

NAME

NO.

51

52

54

55

58

59

61

62

I/O

O

DAC_C8

DAC_C9

DAC_C10

DAC_C11

DAC_D12

DAC_D13

DAC_D14

DAC_D15

DAC group C. These DAC channels share the same range and clamp voltage.

DAC group D. These DAC channels share the same range and clamp voltage.

Digital ground. This pin is the ground reference point for all digital circuitry on the device.

Ideally, the analog and digital grounds should be at the same potential (GND) and must not

differ by more than ±0.3 V.

DGND

DV_DD

64

63

I

Digital supply voltage (4.7 V to 5.5 V). This pin must have the same value as the AV_DDpin.

General-purpose digital I/O 0 (default). This pin is a bidirectional digital input/output (I/O) with

an internal 48-kΩ pullup resistor to the IOV_DDpin. Alternatively the pin can be set to operate

as the digital input ALARMIN which is an active-low alarm-control signal. If unused this pin can

be left floating.

GPIO0/ALARMIN

7

8

9

I/O

General purpose digital I/O 1 (default). This pin is a bidirectional digital I/O with an internal 48-

kΩ pullup resistor to the IOV_DDpin. Alternatively the pin can be set to operate as ALARMOUT

which is an open drain global alarm output. This pin goes low (active) when an alarm event is

detected. If unused this pin can be left floating.

GPIO0/ALARMOUT

GPIO2/ADCTRIG

General purpose digital I/O 2 (default). This pin is a bidirectional digital I/O with internal 48-kΩ

pullup resistor to the IOV_DDpin. Alternatively the pin can be set to operate as ADCTRIG which

is an active-low external conversion trigger. The falling edge of this pin begins the sampling

and conversion of the ADC. If unused this pin can be left floating.

General purpose digital I/O 3 (default). This pin is a bidirectional digital I/O with internal 48-kΩ

pullup resistor to the IOV_DDpin. Alternatively the pin can be set to operate as DAV which is an

active-low data-available indicator output. In direct mode, the DAV pin goes low (active) when

the conversion ends. In auto mode, a 1-µs pulse (active low) appears on this pin when a

conversion cycle finishes. The DAV pin remains high when deactivated. If unused this pin can

be left floating.

GPIO3/DAV

10

I/O

GPIO4

GPIO5

GPIO6

GPIO7

11

12

13

14

I/O

General purpose digital I/O. These pins are bidirectional digital I/Os with an internal 48-kΩ

pullup resistor to the IOV_DDpin. If unused these pins can be left floating.

I/O supply voltage (1.8 V to 5.5 V). This pin sets the I/O operating voltage and threshold levels.

The voltage on this pin must not be greater than the value of the DV_DDpin.

IOV_DD

1

I

LV_ADC16

LV_ADC17

LV_ADC18

LV_ADC19

LV_ADC20

39

38

37

36

35

I

General purpose analog inputs. These channels are used for general monitoring. The input

range of these pins is 0 to 2 × V_ref

.

Internal-reference compensation-capacitor connection. Connect a 4.7-μF capacitor between

this pin and the AGND2 pin.

REF_CMP

49

O

RESET

SCLK

2

5

I

Active-low reset input. Logic low on this pin causes the device to perform a hardware reset.

Serial interface clock.

Serial-interface data input. Data is clocked into the input shift register on each rising edge of

the SCLK pin.

SDI

4

3

I

O

I

Serial-interface data output. The SDO pin is in high impedance when the CS pin is high. Data

is clocked out of the input shift register on each falling edge of the SCLK pin.

SDO

The thermal pad is located on the bottom-side of the device package. The thermal pad should

be tied to the same potential as the AV_EEpin or left disconnected.

Thermal Pad

—

5

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

UNIT

AV_DDto GND

DV_DDto GND

IOV_DDto GND

AV_CCto GND

6

–0.3

6

–0.3

6

–0.3

18

0.3

Supply Voltage

AV_EEto GND

–13

V

AV_SSB, AV_SSC, AV_SSDto AV_EE

AV_CCto AV_SSB, AV_SSC, or AV_SSD

AV_CCto AV_EE

–0.3

13

–0.3

26

–0.3

26

DGND to AGND

–0.3

0.3

ADC_[0-15] analog input voltage to GND

LV_ADC[16-20] analog input voltage to GND

DAC_A[0-3] outputs to GND

DAC_B[4-7] outputs to GND

DAC_C[8-11] outputs to GND

DAC_D[12-15] outputs to GND

REF_CMP to GND

–13

13

–0.3

AV_DD+ 0.3

AV_CC+ 0.3

AV_DD+ 0.3

IOV_DD+ 0.3

10

AV_EE– 0.3

AV_SSB– 0.3

AV_SSC– 0.3

AV_SSD– 0.3

–0.3

Pin Voltage

V

CS, SCLK, SDI and RESET to GND

SDO to GND

–0.3

GPIO[0-7] to GND

–0.3

ADC_[0:15] analog input current

LV_ADC[16:20] analog input current

GPIO[0:7] sinking current

–10

Pin Current

–10

10

mA

5

Operating temperature

–40

125

°C

Junction temperature, T_Jmax

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±250

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6

AMC7836

www.ti.com.cn

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.7

NOM

MAX

5.5

12.5

0

UNIT

AV_DD

5

(1)

DV_DD

4.7

(2)

IOV_DD

1.8

Supply voltage

AV_CC

V

4.7

12

AV_EE

AV_SSB, AV_SSC, AV_SSD

–12.5

AV_EE

–40

–12

0

Specified operating temperature

Operating temperature

25

105

125

°C

(1) The value of the DV_DDpin must be equal to that of the AV_DDpin.

(2) The value of the IOV_DDpin must be less than or equal to that of the DV_DDpin.

6.4 Thermal Information

AMC7836

THERMAL METRIC⁽¹⁾

PAP (HTQFP)

UNIT

64 PINS

26.2

7.2

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

9.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

9

R_θJC(bot)

0.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

6.5 Electrical Characteristics: DAC

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AV_DD= DV_DD= 4.7 to 5.5 V, AV_CC= 12 V, IOV_DD= 1.8 to 5.5 V, AGND = DGND = 0 V, AV_EE

=

AV_SSB= AV_SSC= AV_SSD= –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output

range = 0 to 10 V for all groups, no load on the DACs, T_A= –40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC DC ACCURACY

Resolution

12

Bits

Measured by line passing through codes 020h and

FFFh. 0 to 10 V and –10 to 0 V ranges

±0.3

±0.5

±1

±1.5

±1

INL

Relative accuracy

LSB

Measured by line passing through codes 040h and

FFFh. 0 to 5 V and –5 to 0 V ranges

Specified monotonic. Measured by line passing

through codes 020h and FFFh. 0 to 10 V and –10 to

0 V ranges

±0.03

DNL

Differential nonlinearity

Total unadjusted error⁽¹⁾

LSB

Specified monotonic. Measured by line passing

through codes 020h and FFFh. 0 to 5 V and –5 to 0

V ranges

±0.06

±1

T_A= 25°C, 0 to 10 V range

T_A= 25°C, –10 to 0 V range

T_A= 25°C, 0 to 5 V range

T_A= 25°C, –5 to 0 V range

±2.5

±20

±15

±5

TUE

mV

±1.5

T_A= 25°C, Measured by line passing through codes

020h and FFFh. 0 to 10 V range

±0.25

Offset error

mV

T_A= 25°C, Measured by line passing through codes

040h and FFFh. 0 to 5 V range

±0.25

±5

T_A= 25°C, Code 000h, –10 to 0 V range

T_A= 25°C, Code 000h, –5 to 0 V range

±1

±25

Zero-code error

T_A= 25°C, Measured by line passing through codes

020h and FFFh, 0 to 10 V range

±0.01

±0.2

T_A= 25°C, Measured by line passing through codes

020h and FFFh, –10 to 0 V range

±0.01

±0.2

Gain error⁽¹⁾

%FSR

T_A= 25°C, Measured by line passing through codes

040h and FFFh, 0 to 5 V range

T_A= 25°C, Measured by line passing through codes

040h and FFFh, –5 to 0 V range

0 to 10 V range

0 to 5 V range

–10 to 0 V range

–5 to 0 V range

0 to 10 V range

–10 to 0 V range

0 to 5 V range

–5 to 0 V range

±1

Offset temperature coefficient

ppm/°C

±2

Zero-code temperature coefficient

±2

±2.5

Gain temperature coefficient⁽¹⁾

ppm/°C

(1) The internal reference contribution not included.

8

AMC7836

www.ti.com.cn

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

Electrical Characteristics: DAC (continued)

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AV_DD= DV_DD= 4.7 to 5.5 V, AV_CC= 12 V, IOV_DD= 1.8 to 5.5 V, AGND = DGND = 0 V, AV_EE

=

AV_SSB= AV_SSC= AV_SSD= –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output

range = 0 to 10 V for all groups, no load on the DACs, T_A= –40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC OUTPUT CHARACTERISTICS

Set at power-up or reset through auto-range

–10

0

detection. The output range can be modified after

power-up or reset through the DAC range registers

(address 0x1E through 0x1F). DAC-RANGE = 100b

The output range can be modified after power-up or

reset through the DAC range registers (address 0x1E

through 0x1F). DAC-RANGE = 101b

–5

0

5

Full-scale output voltage range⁽²⁾

V

Set at power-up or reset through auto-range

detection. The output range can be modified after

power-up or reset through the DAC range registers

(address 0x1E through 0x1F). DAC-RANGE = 111b

The output range can be modified after power-up or

reset through the DAC range registers (address 0x1E

through 0x1F). DAC-RANGE = 110b

0

10

Transition: Code 400h to C00h to within ½ LSB, R_L

2 kΩ, C_L= 200 pF. 0 to 10 V and –10 to 0 V ranges

=

10

Output voltage settling time

µs

Transition: Code 400h to C00h to within ½ LSB, R_L

=

2 kΩ, C_L= 200 pF. 0 to 5 V and –5 to 0 V ranges

Transition: Code 400h to C00h, 10% to 90%, R_L= 2

kΩ, C_L= 200 pF. 0 to 10 V and –10 to 0 V ranges

1.25

±45

Slew rate

V/µs

mA

Transition: Code 400h to C00h, 10% to 90%, R_L= 2

kΩ, C_L= 200 pF. 0 to 5 V and –5 to 0 V ranges

Full-scale current shorted to the DAC group AV_SSor

AV_CCvoltage

Short circuit current

Load current⁽³⁾

Source or sink with 1-V headroom from the DAC

group AV_CCor AV_SSvoltage, voltage drop < 25 mV

±15

±10

0

mA

Source or sink with 300-mV headroom from the DAC

group AV_CCor AV_SSvoltage, voltage drop < 25 mV

Maximum capacitive load⁽⁴⁾

DC output impedance

R_L= ∞

10

nF

Code set to 800h, ±15mA

1

Ω

AV_EE= AV_SSB= AV_SSC= AV_SSD= AGND, AV_CC= 0

to 12 V, 2-ms ramp

10

Power-on overshoot

Glitch energy

mV

nV-s

Transition: Code 7FFh to 800h; 800h to 7FFh

1

T_A= 25°C, 1 kHz, code 800h, includes internal

reference noise

520

nV/√Hz

Output noise

T_A= 25°C, integrated noise from 0.1 Hz to 10 Hz,

code 800h, includes internal reference noise

20

µV_PP

CLAMP OUTPUTS

DAC output range: 0 to 10 V, AV_SS= AGND

DAC output range: 0 to 5 V, AV_SS= AGND

DAC output range: –10 to 0 V, AV_SS= –12 V

DAC output range: –5 to 0 V, AV_SS= –6 V

0

Clamp output voltage⁽⁵⁾

V

AV_SS+ 2

AV_SS+ 1

8

Clamp output impedance

kΩ

(2) The output voltage of each DAC group must not be greater than that of the corresponding AV_CCpin (AV_{CC_AB}or AV_{CC_CD}) or lower than

that of the corresponding AV_SSpin (AV_EE, AV_SSB, AV_SSCor AV_SSD). See the DAC Output Range and Clamp Configuration section for

more details.

(3) If all channels are simultaneously loaded, care must be taken to ensure the thermal conditions for the device are not exceeded.

(4) To be sampled during initial release to ensure compliance; not subject to production testing.

(5) No DAC load to the DAC group AV_SSpin.

9

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

6.6 Electrical Characteristics: ADC and Temperature Sensor

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AV_DD= DV_DD= 4.7 to 5.5 V, AV_CC= 12 V, IOV_DD= 1.8 to 5.5 V, AGND = DGND = 0 V, AV_EE

=

AV_SSB= AV_SSC= AV_SSD= –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output

range = 0 to 10 V for all groups, no load on the DACs, T_A= –40°C to 105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

12

Bits

Unipolar input channels

±0.5

±1

±1.5

±1

Integral nonlinearity

LSB

Bipolar input channels

Differential nonlinearity

Specified monotonic. All input channels

UNIPOLAR ANALOG INPUTS: LV_ADC16 to LV_ADC20

Absolute input voltage range

AGND – 0.2

0

AV_DD+ 0.2

2 × V_ref

V

Full scale input range

Input capacitance

DC input leakage current

Offset error

V_refmeasured at REF_CMP pin

V

34

pF

Unselected ADC input

±10

±5

µA

±1

±0.5

±1

LSB

µs

Offset error match

Gain error⁽¹⁾

±5

Gain error match

Update time

Single unipolar input, temperature sensor disabled

11.5

BIPOLAR ANALOG INPUTS: ADC_0 to ADC_15

Absolute input voltage range

Full scale input range

Input resistance

–13

13

V

–12.5

12.5

175

±0.25

±0.5

kΩ

LSB

µs

Offset error

Gain error⁽¹⁾

±5

Update time

Single bipolar input, temperature sensor disabled

34.5

TEMPERATURE SENSOR

Operating range

Accuracy

–40

3.7

125

°C

µs

T_A= –40°C to 125°C, AV_DD= 5 V

LSB size

±1.25

0.25

256

±2.5

Resolution

Update time

All ADC input channels disabled

ADC UPDATE TIME

Internal oscillator frequency

4

4.3

MHz

µs

All 21 ADC inputs enabled, temperature sensor

disabled.

609.5

ADC update time

All 21 ADC inputs enabled, temperature sensor

enabled.

865.5

µs

INTERNAL REFERENCE (INTERNAL REFERENCE NOT ACCESSIBLE)

Initial accuracy

T_A= 25°C

2.4925

2.5

12

2.5075

35

V

Reference temperature coefficient

INTERNAL ADC REFERENCE BUFFER

Reference buffer offset

ppm/°C

T_A= 25°C

±5

mV

(1) Internal reference contribution not included.

10

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6.7 Electrical Characteristics: General

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of

the product containing it. AV_DD= DV_DD= 4.7 to 5.5 V, AV_CC= 12 V, IOV_VDD= 1.8 to 5.5 V, AGND = DGND = 0 V, AV_EE

=

AV_SSB= AV_SSC= AV_SSD= –12 V (for DAC groups in negative range) or 0 V (for DAC groups in positive ranges), DAC output

range = 0 to 10 V for all groups, no load on the DACs, T_A= –40°C to 105°C

PARAMETER

AV_SSDETECTOR

AV_SSthreshold detector (AV_SSTH

DIGITAL LOGIC: GPIO

TEST CONDITIONS

MIN

TYP

MAX

UNIT

)

–3.5

–1.5

V

High-level input voltage

IOV_DD= 1.8 to 5.5 V

0.7 × IOV_DD

V

IOV_DD= 1.8 V

0.45

0.3 × IOV_DD

0.4

Low-level input voltage

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 V, I_(LOAD)= –2 mA

IOV_DD= 5.5 V, I_(LOAD)= –5 mA

To IOV_DD

Low-level output voltage

V

0.4

Input impedance

DIGITAL LOGIC: ALL EXCEPT GPIO

High-level input voltage

48

kΩ

IOV_DD= 1.8 to 5.5 V

IOV_DD= 1.8 V

0.7 × IOV_DD

IOV_DD– 0.4

V

0.45

Low-level input voltage

IOV_DD= 2.7 to 5.5 V

I_(LOAD)= –1 mA

0.3 × IOV_DD

V

High-level output voltage

Low-level output voltage

High impedance leakage

V

I_(LOAD)= 1 mA

0.4

±5

V

µA

High impedance output

capacitance

10

pF

POWER REQUIREMENTS

I_AVDD

I_AVCC

I_AVSS

I_AVEE

I_DVDD

I_IOVDD

AV_DDsupply current

AV_CCsupply current

AV_SSsupply current

AV_EEsupply current

DV_DDsupply current

IOV_DDsupply current

Power consumption

AV_DDsupply current

AV_CCsupply current

AV_SSsupply current

AV_EEsupply current

DV_DDsupply current

IOV_DDsupply current

Power consumption

6

7.5

–5

13.5

–13.5

–3.5

mA

No DAC load, all DACs at 800h code and ADC at

the fastest auto conversion rate

–1.75

1

3

1.5

215

2.5

1

15

µA

mW

I_AVDD

I_AVCC

I_AVSS

I_AVEE

I_DVDD

I_IOVDD

5

2.5

–5

–3

-3

mA

Power-down mode

–1.75

0.75

1.5

90

1.5

15

µA

mW

11

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

6.8 Timing Requirements

AV_DD= DV_DD= 4.7 to 5.5 V, AV_CC= 12 V, AV_EE= –12 V, AGND = DGND = AV_SSB= AV_SSC= AV_SSD= 0 V, DAC output range

= 0 to 10 V for all groups, no load on the DACs, T_A= –40°C to 105°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

SERIAL INTERFACE⁽¹⁾

ƒ_(SCLK)SCLK frequency

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

IOV_DD= 1.8 to 2.7 V

IOV_DD= 2.7 to 5.5 V

15

20

MHz

ns

66.67

50

30

23

30

23

10

0

t_p

SCLK period⁽²⁾

t_PH

SCLK pulse width high⁽²⁾

SCLK pulse width low⁽²⁾

SDI setup⁽²⁾

t_PL

t_su

t_h

SDI hold⁽²⁾

15

9

SDO driven to tri-

state⁽³⁾⁽⁴⁾

t_(ODZ)

t_(OZD)

t_(OD)

t_su(CS)

t_h(CS)

t_(IAG)

0

23

15

23

15

SDO tri-state to

driven⁽³⁾⁽⁴⁾

0

SDO output delay⁽³⁾⁽⁴⁾

CS setup⁽²⁾

0

5

20

10

CS hold⁽²⁾

Inter-access gap⁽²⁾

DIGITAL LOGIC

Reset delay; delay-to-normal operation from reset

Power-down recovery time

Clamp shutdown delay

100

250

70

µs

ns

Convert pulse width

20

Reset pulse width

ADC WAIT state⁽⁵⁾; the wait time from when the ADC enters the IDLE state

to when the ADC is ready for trigger

2

µs

(1) Specified by design and characterization. Not tested during production.

(2) See Figure 1 and Figure 2.

(3) SDO loaded with 10 pF load capacitance for SDO timing specifications.

(4) See Figure 2.

(5) Specified by design; not subject to production testing. See the ADC Sequencing section for more details.

12

AMC7836

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

t_(IAG)

t_h(CS)

t_su(CS)

CS

t_p

t_PL

SCLK

SDI

t_PH

Bit 23

Bit 1

Bit 0

t_h

t_su

Figure 1. Serial Interface Write Timing Diagram

t_(ODZ)

t_(IAG)

t_h(CS)

t_su(CS)

CS

t_p

t_PL

SCLK

SDI

t_PH

Bit 23

Bit 8

t_h

t_su

SDO

Bit 7

Bit 0

t_(OZD)

t_(OD)

Figure 2. Serial Interface Read Timing Diagram

13

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

6.9 Typical Characteristics: DAC

At T_A= 25°C (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.2

-0.4

-0.6

-0.8

-1

A0

B4

C8

D12

A1

B5

C9

D13

A2

B6

C10

D14

A3

B7

C11

D15

A0

A1

A2

A3

-0.6

-0.8

-1

B4

B5

B6

B7

C8

D12

C9

D13

C10

D14

C11

D15

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 3. DAC Linearity Error vs Code

DAC Range: 0 to 10 V

Figure 4. DAC Differential Linearity Error vs Code

DAC Range: 0 to 10 V

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

A0

A1

A2

A3

A0

A1

A2

A3

B4

B5

B6

B7

B4

B5

B6

B7

C8

D12

C9

D13

C10

D14

C11

D15

C8

D12

C9

D13

C10

D14

C11

D15

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 5. DAC Linearity Error vs Code

DAC Range: –10 to 0 V

Figure 6. DAC Differential Linearity Error vs Code

DAC Range: –10 to 0 V

1

0.8

0.6

0.4

0.2

0

1

A0

A1

A2

A3

B4

B5

B6

B7

0.8

0.6

0.4

0.2

0

C8

D12

C9

D13

C10

D14

C11

D15

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

A0

A1

A2

A3

B4

B5

B6

B7

C8

D12

C9

D13

C10

D14

C11

D15

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 7. DAC Linearity Error vs Code

DAC Range: 0 to 5 V

Figure 8. DAC Differential Linearity Error vs Code

DAC Range: 0 to 5 V

14

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Typical Characteristics: DAC (continued)

At T_A= 25°C (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.2

-0.4

-0.6

-0.8

-1

A0

B4

C8

D12

A1

B5

C9

D13

A2

B6

C10

D14

A3

B7

C11

D15

A0

A1

A2

A3

-0.6

-0.8

-1

B4

B5

B6

B7

C8

D12

C9

D13

C10

D14

C11

D15

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 9. DAC Linearity Error vs Code

DAC Range: –5 to 0 V

Figure 10. DAC Differential Linearity Error vs Code

DAC Range: –5 to 0 V

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

INL MAX

INL MIN

DNL MAX

DNL MIN

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 11. DAC Linearity Error vs Temperature

DAC Range: 0 to 10 V

Figure 12. DAC Differential Linearity Error vs Temperature

DAC Range: 0 to 10 V

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.2

œ0.4

œ0.6

INL MAX

INL MIN

DNL MAX

DNL MIN

œ0.8

œ1.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 13. DAC Linearity Error vs Temperature

DAC Range: –10 to 0 V

Figure 14. DAC Differential Linearity Error vs Temperature

DAC Range: –10 to 0 V

15

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

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Typical Characteristics: DAC (continued)

At T_A= 25°C (unless otherwise noted)

1.5

1.0

0.8

1.2

0.9

0.6

0.4

0.3

0.2

0.0

œ0.3

œ0.6

œ0.9

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

INL MAX

DNL MAX

DNL MIN

œ1.2

œ1.5

INL MIN

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 15. DAC Linearity Error vs Temperature

DAC Range: 0 to 5 V

Figure 16. DAC Differential Linearity Error vs Temperature

DAC Range: 0 to 5 V

1.5

1.2

1.0

0.8

0.9

0.6

0.4

0.3

0.2

0.0

œ0.3

œ0.6

œ0.9

œ1.2

œ1.5

œ0.2

œ0.4

œ0.6

INL MAX

INL MIN

DNL MAX

DNL MIN

œ0.8

œ1.0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 17. DAC Linearity Error vs Temperature

DAC Range: –5 to 0 V

Figure 18. DAC Differential Linearity Error vs Temperature

DAC Range: –5 to 0 V

5

4

25

20

15

10

5

3

2

1

0

œ1

œ2

œ3

œ4

œ5

œ10

œ15

0V to 10V Range

0V to 5V Range

-10V to 0V Range

œ20

-5V to 0V Range

œ25

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 19. DAC Offset Error vs Temperature

Figure 20. DAC Zero Code Error vs Temperature

16

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

Typical Characteristics: DAC (continued)

At T_A= 25°C (unless otherwise noted)

10

9

8

7

6

5

4

3

2

1

0

0.20

0.15

0.10

0.05

0.00

œ0.05

0V to 10V Range

œ0.10

0V to 5V Range

-10V to 0V Range

-5V to 0V Range

œ0.15

œ0.20

-50 -40 -30 -20 -10

0

10

20

30

40

50

-40 -25 -10

5

20 35 50 65 80 95 110 125

I_LOAD(mA)

T_A(°C)

C001

Code 0x800, DAC range: 0 to 10 V

Figure 22. DAC Output Voltage vs Load Current

Figure 21. DAC Gain Error vs Temperature

10

9.95

9.9

0.25

0.2

0.15

0.1

0.05

0

9.85

9.8

9.75

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1

I_LOAD(mA)

0

I_LOAD(mA)

C001

Code 0xFFF, DAC range: 0 to 10 V, AV_CC= 10 V, AV_EE= 0 V

Code 0x000, DAC range: 0 to 10 V, AV_CC= 10 V, AV_EE= 0 V

Figure 23. DAC Source Current

Figure 24. DAC Sink Current

15

10nF, Rising Edge

10nF, Falling Edge

200pF, Rising Edge

200pF, Falling Edge

10

5

10

5

0

-5

-10

-15

-10

-15

0

5

10

15

Time (µs)

20

25

0

5

10

15

Time (µs)

20

25

C001

Code 0x400 to 0xC00 to within ½ LSB

Code 0xC00 to 0x400 to within ½ LSB

Figure 26. DAC Settling Time vs Load Capacitance

Figure 25. DAC Settling Time vs Load Capacitance

17

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www.ti.com.cn

Typical Characteristics: DAC (continued)

At T_A= 25°C (unless otherwise noted)

5000

10

5

15

12

9

4000

3000

2000

1000

0

6

3

0

œ3

œ6

œ9

œ5

œ10

DAC OUTPUT

AVCC

œ12

œ15

-2

-1

0

1

2

3

4

5

10

100

1k

10k

100k

1M

10M

Time (ms)

C002

Frequency (Hz)

C001

AV_SS= AV_EE= AGND, AV_CC= 0 to 12 V, 2-ms ramp

Code 0x800

Figure 28. DAC Power On Overshoot, Single Supply

Figure 27. DAC Output Noise vs Frequency

15

10

5

0

-2

-4

-6

-8

0

-5

AVCC

AVSS

-10

-15

-10

DVDD/AVDD

DAC output

-12

-12.5

0

1

2

3

œ1

-10

-7.5

AV_SS(V)

-5

-2.5

0

Time (ms)

C001

C020

AV_SS= AV_EE= –12 V, AV_CC= 0 to 12 V, 2-ms ramp

No load

Figure 30. DAC Clamp Output vs AV_SS

Figure 29. DAC Power On Overshoot, Dual Supply

5

0

5.0

15

10

5

DVDD/AVDD

AVCC

AVSS

IOVDD

DAC OUT

2.5

0.0

œ5

0

-5

œ10

œ15

œ2.5

DAC Output

-10

DAC Output Small Signal

œ5.0

-15

-5

0

5

10

15

20

25

30

35

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

Time (µs)

C031

Time (ms)

C001

Code 0xFFF, DAC range: –10 to 0 V, no load

Figure 32. DAC Output With AV_DDand DV_DDSupply

Collapse

Figure 31. DAC Clamp Recovery

18

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Typical Characteristics: DAC (continued)

At T_A= 25°C (unless otherwise noted)

15

10

5

DVDD/AVDD

AVCC

AVSS

IOVDD

DAC OUT

DVDD/AVDD

AVCC

AVSS

IOVDD

DAC OUT

10

5

0

-5

-10

-15

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

Time (ms)

C001

Code 0xFFF, DAC range: –10 to 0 V, no load

Code 0xC00, DAC range: –10 to 0 V, no load

Figure 33. DAC Output With IOV_DDSupply Collapse

Figure 34. DAC Output With AV_SSSupply Collapse

15

DVDD/AVDD

AVCC

AVSS

IOVDD

DAC OUT

10

5

0

-5

-10

-15

-0.25

0

0.25

0.5

0.75

1

1.25

1.5

Time (ms)

C001

Code 0xFFF, DAC range: –10 to 0 V, no load

Figure 35. DAC Output With AV_CCSupply Collapse

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6.10 Typical Characteristics: ADC

At T_A= 25°C (unless otherwise noted)

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 36. ADC Linearity Error vs Code

Unipolar Input

Figure 37. ADC Differential Linearity Error vs Code

Unipolar Input

1.0

1.5

1.2

0.8

0.6

0.9

0.4

0.6

0.2

0.3

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.3

œ0.6

œ0.9

œ1.2

œ1.5

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Code

C001

Figure 39. ADC Differential Linearity Error vs Code

Bipolar Input

Figure 38. ADC Linearity Error vs Code

Bipolar Input

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

INL MAX

INL MIN

DNL MAX

DNL MIN

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 40. ADC Linearity Error vs Temperature

Unipolar Input

Figure 41. ADC Differential Linearity Error vs Temperature

Unipolar Input

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Typical Characteristics: ADC (continued)

At T_A= 25°C (unless otherwise noted)

1.5

1.0

0.8

1.2

0.9

0.6

0.4

0.3

0.2

0.0

œ0.3

œ0.6

œ0.9

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

INL MAX

DNL MAX

DNL MIN

œ1.2

œ1.5

INL MIN

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 42. ADC Linearity Error vs Temperature

Bipolar Input

Figure 43. ADC Differential Linearity Error vs Temperature

Bipolar Input

10

8

5

4

6

3

4

2

1

0

œ2

œ4

œ6

œ8

œ10

œ1

œ2

œ3

Unipolar

Bipolar

Unipolar

Bipolar

œ4

œ5

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_A(°C)

C001

Figure 44. ADC Gain Error vs Temperature

Figure 45. ADC Offset Error vs Temperature

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6.11 Typical Characteristics: Reference

At T_A= 25°C (unless otherwise noted)

2.505

2.504

2.503

2.502

2.501

2.5

2.499

2.498

2.497

2.496

2.495

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

C001

10 units, measured at REF_CMP

Figure 46. Reference Voltage vs Temperature

6.12 Typical Characteristics: Temperature Sensor

At T_A= 25°C (unless otherwise noted)

2.5

2.0

1.5

1.0

0.5

0.0

œ0.5

œ1.0

œ1.5

œ2.0

œ2.5

5

20 35 50 65 80 95 110 125

œ40 œ25 œ10

T_A(°C)

C001

10 units

Figure 47. Temperature Sensor Error vs Temperature

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7 Detailed Description

7.1 Overview

The AMC7836 device is a highly-integrated analog-monitoring and control solution capable of voltage and

temperature supervision. The AMC7836 device includes the following features:

•

Sixteen 12-bit digital-to-analog converters (DACs) with adjustable output ranges

–

Output ranges: –10 to 0 V, –5 to 0 V, 0 to 5 V, and 0 to 10 V

Auto-range detector on device power-up and reset events

The DACs power-on and clamp voltages can be pin-selected between AGND and a negative voltage

The DACs can be configured to clamp automatically upon detection of an alarm event

•

A multi-channel, 12-bit analog-to-digital converter (ADC) for voltage and temperature sensing

–

Sixteen bipolar inputs: –12.5 to 12.5 V input range

Five precision inputs with programmable threshold detectors: 0 to 5 V input range

Internal temperature sensor

•

Internal 2.5 V precision reference

Eight general purpose I/O (GPIO) ports

Communication with the device occurs through a 4-wire SPI-compatible interface supporting 1.8 to 5.5 V

operation

The AMC7836 device is characterized for operation over the temperature range of –40ºC to 125ºC which makes

the device suitable for harsh-condition applications. The device is available in a 10-mm × 10-mm 64-pin HTQFP

PowerPAD IC package.

The very high-integration of the AMC7836 device makes it an ideal all-in-one, low-cost, bias-control circuit for the

power amplifiers (PAs) found in multi-channel RF-communication systems. The flexible DAC output ranges allow

the device to be used as a biasing solution for a large variety of transistor technologies such as LDMOS, GaAs,

and GaN. The AMC7836 feature set is similarly beneficial in general-purpose monitor and control systems.

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7.2 Functional Block Diagram

REF_CMP

AMC7836

Reference

(2.5 V)

ADC_0

ADC_1

ADC_2

ADC_3

ADC_4

ADC_5

ADC

Trigger

DAC

Trigger

DAC-0

12-b

DAC_A12

DAC_A13

DAC_A14

DAC_A15

ADC_6

Bipolar

ADC_7

Inputs

ADC_8

Scaling

ADC_9

ADC_10

ADC_11

ADC_12

ADC_13

ADC_14

ADC_15

DAC-3

12-b

ADC

12-b

DAC-4

12-b

LV_ADC16

LV_ADC17

LV_ADC18

LV_ADC19

LV_ADC20

DAC_B8

DAC_B9

DAC_B10

DAC_B11

Local

Temperature

Sensor

DAC-7

12-b

GPIO0/ALARMIN

GPIO1/ALARMOUT

GPIO2/ADCTRIG

DAC-8

12-b

DAC_C0

DAC_C1

DAC_C2

DAC_C3

GPIO

Controller

GPIO3/DAV

GPIO4

GPIO5

GPIO6

GPIO7

DAC-11

12-b

DAC-12

12-b

DAC_D4

DAC_D5

DAC_D6

DAC_D7

Control, Limits, and

Status Registers

DAC-15

12-b

DAC

Range

and

Clamp

Setup

Synchronization

Logic

Serial Interface Register

and Control

DV

DD

IOV

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7.3 Feature Description

7.3.1 Digital-to-Analog Converters (DACs)

The AMC7836 device features an analog-control system centered on sixteen 12-bit DACs that operate from the

internal reference of the device. Each DAC core consists of a string DAC and output-voltage buffer.

The resistor-string structure consists of a series of resistors, each with a value of R. The code loaded to the DAC

determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string to the amplifier (see Figure 48). This architecture

has inherent monotonicity, voltage output, and low glitch. This architecture is also linear because all the resistors

are of equal value.

R

To Output

Amplifier

R

Figure 48. DAC Resistor String

7.3.1.1 DAC Output Range and Clamp Configuration

The 16 DACs are split into four groups, each with four DACs. All of the DACs in a given group share the same

output range and clamp voltage value, however, these settings can be set independently for each DAC group.

After power-on or a reset event the following actions take place: the DAC outputs are directed automatically to

the corresponding clamp value; the DAC groups output ranges are set by the auto-range detector and; all DAC

data registers and data latches are set to the default values. Figure 49 shows a high level block diagram of each

DAC in the AMC7836 device.

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Feature Description (continued)

AV_CC

Serial Interface DAC Data Register

WRITE

READ

READBACK bit

1

0

DAC

Buffer

Register

DAC

Active

Register

0

DAC

Output Range

Configuration

Resistor String

V_O

DAC output

0x000

1

UPDATE

command

Clear State

Clamp State

(register or alarm-

generated)

(reset event or

DAC power down)

Clamp

Offset

⁵Ÿ ₆× AV_SS

AV_SS

Figure 49. DAC Block Diagram

7.3.1.1.1 Auto-Range Detection

After power-on or a reset event the output range for each DAC group is set automatically by the voltage present

in the corresponding AV_SSpin (AV_EE, AV_SSB, AV_SSCor AV_SSD). When the AV_SSvoltage of a DAC group is lower

than the threshold value, AV_SSTH, the output for that DAC group is automatically configured to the –10 to 0 V

range. Conversely, if the DAC group AV_SSvoltage is higher than AV_SSTH, the DAC-group output is automatically

set to the 0 to 5 V range. The auto-range detector results for each DAC group are stored in the general status

register (address 0x72).

In addition to a power-on or reset event, the auto-range detector is also enabled by a register write to the DAC

power down registers (address 0xB2 through 0xB3) or the device configuration register (address 0x02).

Although the initial output-range setting is determined by the auto-range detector, the output range for each

DAC-group can be afterwards configured to any of the available output ranges (–10 to 0 V, –5 to 0 V, 0 to 5 V, or

0 to 10 V) through the DAC range registers (address 0x1E through 0x1F).

NOTE

The power-on-reset and clamp-voltage value of each DAC group is set by the

corresponding AV_SSpin and is independent of the DAC output range. In some

applications, matching the clamp-voltage setting to the operating voltage range is

imperative. For those applications, the recommended connections for the AV_SSpin are:

AGND for the positive output ranges, in which case the clamp voltage is 0 V; a negative

supply voltage with a lower value than the minimum DAC output voltage (–5 V or –10 V)

for the selected negative output range, in which case the unloaded clamp voltage is

determined by the value of the negative supply voltage (see Figure 50).

Although not a recommended operating condition, the device allows a DAC group to

operate in a positive output range even if its clamp voltage is negative (AV_SSconnected to

a negative supply voltage).

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Feature Description (continued)

0

-2

-4

-6

-8

-10

-12

-12.5

-10

-7.5

AV_SS(V)

-5

-2.5

0

C020

Figure 50. DAC Clamp Output vs AV_SS

A special distinction must be made for DAC group A as the AV_SSpin of this group is the dual-function AV_EEpin.

Aside from setting the clamp voltage and default output range for the DAC group A, the AV_EEpin is also the

lowest potential in the device. As a consequence the AV_EEvoltage is dependent on the other AV_SSpin

connections. The AV_EEpin can only be connected to the analog ground if all the other AV_SSpins are also

connected to the analog ground. If any of the AV_SSpins is connected to a negative voltage, the AV_EEpin must

also be connected to that voltage (see Table 1).

The full-scale output range for each DAC group is limited by the corresponding AV_CCand AV_SSvalues. The

maximum and minimum outputs cannot exceed the AV_CCvoltage or be lower than the AV_SSvoltage, respectively.

Table 1. Recommended DAC Group Configuration

AUTO-RANGE

AND CLAMP

VOLTAGE

AV_EE= AGND

AV_EE= V_NEG

DAC

GROUP

DAC

CLAMP VOLTAGE

OUTPUT RANGE

SELECTION

CONNECTION

(AV_SS

)

DAC_A0

DAC_A1

DAC_A2

DAC_A3

DAC_B4

DAC_B5

DAC_B6

DAC_B7

DAC_C8

DAC_C9

DAC_C10

DAC_C11

DAC_D12

DAC_D13

DAC_D14

DAC_D15

A

B

C

D

AV_EE

0 to 5 V or 0 to 10 V

AGND

–5 to 0 V or –10 to 0 V

V_NEG

–5 to 0 V or –10 to 0 V

0 to 5 V or 0 to 10 V

–5 to 0 V or –10 to 0 V

0 to 5 V or 0 to 10 V

–5 to 0 V or –10 to 0 V

0 to 5 V or 0 to 10 V

V_NEG≤ AV_SSB≤ –5 V

AGND

AV_SSB

AV_SSC

AV_SSD

0 to 5 V or 0 to 10 V

AGND

V_NEG≤ AV_SSC≤ –5 V

AGND

V_NEG≤ AV_SSD≤ –5 V

AGND

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7.3.1.2 DAC Register Structure

The input data of the DACs is written to the individual DAC data registers (address 0x50 through 0x6F) in straight

binary format for all output ranges (see Table 2).

Table 2. DAC Data Format

DAC OUTPUT VOLTAGE (V)

DIGITAL CODE

0 to 5 V RANGE

0 to 10 V RANGE

–5 to 0 V RANGE

–5

–10 to 0 V RANGE

–10

0000 0000 0000

0000 0000 0001

1000 0000 0000

1111 1111 1110

1111 1111 1111

0

0.00122

2.5

0.00244

5

–4.99878

–2.5

–9.99756

–5

4.99756

4.99878

9.99512

9.99756

–0.00244

–0.00122

–0.00488

–0.00244

Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the

DAC buffer registers to the active registers is initiated by an update command in the register update register

(address 0x0F). When the active registers are updated, the DAC outputs change to the new values.

The host has the option to read from either the buffer registers or the active registers when accessing the DAC

data registers. The DAC read back option is configured by the READBACK bit in the interface configuration 1

register (address 0x01).

7.3.1.3 DAC Clear Operation

Each DAC can be set to a CLEAR state using either hardware or software. When a DAC goes to CLEAR state, it

is loaded with a zero-code input and the output voltage is set according to the auto-range detector output range.

The DAC buffer or active registers do not change when the DACs enter the CLEAR state which makes it

possible to return to the same voltage output before the clear event was issued. Even though the contents of the

active register do not change while a DAC is in CLEAR state, a data-register read operation from the active

registers while in this state returns zero-code. This functionality enables the ability to determine the DAC output

voltage regardless of the operating state (CLEAR or NORMAL).

NOTE

The DAC buffer and active registers can be updated while the DACs are in CLEAR state

allowing the DACs to output new values upon return to normal operation. When the DACs

exit the CLEAR state, the DACs are immediately loaded with the data in the DAC active

registers and the output is set back to the corresponding level to restore operation.

The DAC clear registers (address 0xB0 through 0xB1) enable independent control of each DAC CLEAR state

through software. The DACs can also be forced to enter a CLEAR state through hardware using the ALARMIN

pin. See the Programmable Out-of-Range Alarms section for a detailed description of this method.

The ALARMIN-controlled clear mechanism is just a special case of the device capability to force the DACs into

the CLEAR state as a response to an alarm event. To enable this function, the alarm events must first be

enabled as DAC-clear alarm sources in the DAC clear source registers (address 0x1A through 0x1B). The DAC

outputs to be cleared by the selected alarm events must also be specified in the DAC clear enable registers

(address 0x18 through 0x19).

An alarm event sets the corresponding alarm bit in the alarm status registers. In addition all the DACs set to

clear in response to the alarm event in the DAC clear enable registers enter a CLEAR state. Once the alarm bit

is cleared, as long as no other CLEAR-state controlling alarm events have been triggered, the DACs are

reloaded with the contents of the DAC active registers and the outputs update accordingly.

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7.3.2 Analog-to-Digital Converter (ADC)

The AMC7836 features a monitoring system centered on a 12-bit SAR (successive approximation register) ADC

fronted by a 22-channel multiplexer and an on-chip track-and-hold circuit. The monitoring systems is capable of

sensing up to 16 external bipolar inputs (–12.5 to 12.5 V range), five external unipolar inputs (0 to 5 V range),

and an internal analog temperature sensor.

The ADC operates from an internal 2.5 V reference (V_ref, measured at the REF_CMP pin) and the input range is

0 V to 2 × V_ref. The external bipolar inputs to the ADC are internally mapped to this range. The ADC timing

signals are derived from an on-chip temperature-compensated oscillator. The conversion results can be

accessed through the device serial interface.

7.3.2.1 Analog Inputs

The AMC7836 has 21 analog inputs for external voltage sensing. Sixteen of these inputs (ADC_0 through

ADC_15) are bipolar and the other five (LV_ADC16 through LV_ADC20) are unipolar. Figure 51 shows the

equivalent circuit for the external analog-input pins. All switches are open while the ADC is in the IDLE state.

Scaling Network

3.125 V

C_(SAMPLE)

S_(W)

R_S

R_(MUX)

ADC_0

3.125 V

S_(W)is closed during acquisition.

S_(W)is open during conversion.

ADC_15

AV_DD

LV_ADC16

LV_ADC20

AGND

AV_DD

Figure 51. ADC External Inputs Equivalent Circuit

To achieve the specified performance, especially at higher input frequencies, driving each analog input pin with a

low impedance source is recommended. An external amplifier can also be used to drive the input pins.

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7.3.2.1.1 Bipolar Analog Inputs

The AMC7836 can support up to 16 bipolar analog inputs. The analog input range for these channels is –12.5 to

12.5 V. The bipolar signal is scaled internally through a resistor divider so that it maps to the native input range

of the ADC (0 V to 2 × V_ref). The input resistance of the scaling network is 175 kΩ.

The bipolar analog input conversion values are stored in straight binary format in the ADC data registers

(address 0x20 through 0x49). The LSB (least-significant bit) size for these channels is 25 × V_ref/ 4096. With the

internal reference equal to 2.5 V, the input voltage is calculated by Equation 1.

CODE ì 5

≈

’

Voltage = 5

- 2.5

∆

«

÷

◊

4096

(1)

A typical application for the bipolar channels is monitoring of the 16 DAC outputs in the device. In this application

the bipolar inputs can be driven directly. However, in applications where the signal source has high impedance,

buffering the analog input is recommended. When driven from a low impedance source such as the AMC7836

DAC outputs, the network is designed to settle before the start of conversion. Additional impedance can affect

the settling and divider accuracy of this network.

7.3.2.1.2 Unipolar Analog Inputs

In addition to the bipolar input channels, the AMC7836 device includes five unipolar analog inputs. The analog

input range for these channels is 0 V to 2 × V_refand the LSB size for these channels is 2 × V_ref/ 4096.

The unipolar analog input conversion values are stored in straight binary format in the ADC-Data registers

(address 0x40 through 0x49). With the internal reference equal to 2.5 V, the input voltage is calculated by

Equation 2.

CODE ì 5

Voltage =

4096

(2)

In applications where the signal source has high impedance, externally buffering the unipolar analog input is

recommended.

7.3.2.2 ADC Sequencing

The AMC7836 ADC conversion sequence is shown in Figure 52. The ADC supports direct mode and auto mode

conversion. The conversion method is selected in the ADC configuration register (address 0x10). The default

conversion method is direct mode.

In both methods, the single channel or sequence of channels to be converted by the ADC must be first

configured in the ADC MUX configuration registers (address 0x13 through 0x15). The input channels to the ADC

include 16 external bipolar inputs, five external unipolar inputs, and the internal temperature sensor.

In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger

signal. After the last enabled channel is converted, the ADC enters IDLE state and waits for a new trigger.

In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is

initiated by issuing an ADC trigger. Upon completion of the first conversion sequence another sequence is

automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is

stopped by issuing a second trigger signal.

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Start

(Reset)

ADC IDLE state

Yes

ADC-register

changes?

ADC WAIT state

(2 µs)

No

ADC trigger?

Yes

First conversion

Update registers

and issue data

available indicator

Yes

Is this the last

conversion?

Direct mode?

No

Convert next

channel

ADC trigger?

No

Figure 52. ADC Conversion Sequence

Regardless of the selected conversion method, the following ADC registers should only be updated while the

ADC is in IDLE state:

•

ADC configuration register (address 0x10)

False alarm configuration register (address 0x11)

ADC MUX configuration registers (address 0x13 through 0x15)

Threshold registers (0x80 through 0x97)

Hysteresis register (0xA0 through 0xA5)

NOTE

After updating any of the ADC registers listed above, a minimum 2 µs wait time should be

implemented before issuing an ADC trigger.

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7.3.2.3 ADC Synchronization

A trigger signal must occur for the ADC to enter and exit the IDLE state. The ADC trigger can be generated

either through software (ICONV bit in the ADC trigger register, 0xC0) or hardware (GPIO2/ADCTRIG, pin 9). To

use the GPIO2/ADCTRIG pin as an ADC trigger, the pin must be configured accordingly in the GPIO

configuration register (address 0x12). When the pin is configured as a trigger, a falling edge on it begins the

sampling and conversion of the ADC.

In auto mode the ADC and temperature data registers (0x20 through 0x4B) are accessed by first issuing an ADC

UPDATE command in the register update register (address 0x0F). The ADC UPDATE command ensures the

latest available data for each input channel can be accessed without the need for complex synchronization

schemes between the AMC7836 device and the host controller. A single ADC UPDATE command updates all

ADC and temperature data registers. Therefore issuing multiple UPDATE commands is not necessary when

reading more than one ADC data register.

NOTE

The ADC UPDATE command and accessing of the ADC and Temperature data registers

does not interfere with the conversion process which ensures continuous ADC operation.

In direct mode the ADC and temperature data registers (0x20 through 0x4B) should only be accessed while the

ADC is in the IDLE state (see Figure 53). Although the total update time can be easily calculated, the device

provides a data-available indicator signal to track the ADC status. Failure to satisfy the synchronization

requirements could lead to erroneous data reads.

The data-available indicator signal is output through the GPIO3/DAV pin and as a data-available flag that is

accessible through the serial interface (DAVF bit in the general status register, 0x72). The GPIO3/DAV pin must

be configured in the GPIO configuration register (address 0x12) as an interrupt. After a direct-mode conversion is

complete and the ADC returns to the IDLE state, the DAVF bit is immediately set to 1 and the DAV pin is active

(low) which indicates that new data is available. The pin and flag are cleared automatically when a new

conversion begins or one of the ADC data or temperature data registers is accessed.

a) Direct Mode, Software Trigger

Trigger

Command

Read

Command

Trigger

Command

Read

Command

CS

1^stinternal

trigger

2^ndinternal

trigger

> 2 µs

DAV

First CONVERSION of the channels

specified in the ADC MUX Registers

Second CONVERSION of the channels

specified in the ADC MUX Registers

b) Direct Mode, Hardware Trigger

ADCTRIG

CS

1^sttrigger

2^ndtrigger

3^rdtrigger

> 2 µs

Read

Command

Read

Command

DAV

First CONVERSION of the channels

specified in the ADC MUX Registers

Second CONVERSION of the channels

specified in the ADC MUX Registers

Third CONVERSION of the channels

specified in the ADC MUX Registers

Figure 53. ADC Direct-Mode Trigger Synchronization

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7.3.2.4 Programmable Out-of-Range Alarms

The AMC7836 device is capable of continuously analyzing the five external unipolar inputs and internal

temperature sensor conversion results for normal operation.

Normal operation is established through the lower and upper threshold registers (address 0x80 through 0x97).

When any of the monitored inputs is out of the specified range, an alarm event is issued and the global alarm bit,

GALR in the general status register (0x72), is set (see Figure 54). Use the alarm status registers (0x70 through

0x71) to determine the source of the alarm event.

RESERVED

7

6

5

4

3

2

1

0

RESERVED

LV_ADC20 Alarm

LV_ADC19 Alarm

LV_ADC18 Alarm

LV_ADC17 Alarm

LV_ADC16 Alarm

ALARM STATUS 0

0x70

GALR

RESERVED

7

6

5

4

3

2

1

0

RESERVED

ALARM STATUS 1

0x71

ALARMIN Alarm

Die Temperature Alarm

Temperature Sensor High Alarm

Temperature Sensor Low Alarm

Figure 54. Alarm Status Register

The ALARM-LATCH-DIS bit in the ALARMOUT source 1 register (address 0x1D) sets the latching behavior for

all alarms (except for the ALARMIN alarm which is always unlatched). When the ALARM-LATCH-DIS bit is

cleared to 0 the alarm bits in the alarm status registers are latched. The alarm bits are referred to as being

latched because they remain set until read by software. This design ensures that out-of-limit events cannot be

missed if the software is polling the device periodically. All bits are cleared when reading the alarm status

registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle, unless

otherwise noted. When the ALARM-LATCH-DIS bit is set to 1, the alarm bits are not latched. The alarm bits in

the alarm status registers are set to 0 when the error condition subsides, regardless of whether the bit is read or

not.

All of the alarms can be set to activate the ALARMOUT pin. To enable this functionality, the GPIO1/ALARMOUT

pin must be configured accordingly in the GPIO configuration register (address 0x12). The ALARMOUT pin

works as an interrupt to the host so that it can query the alarm status registers to determine the alarm source.

Any alarm event can activate the pin as long as the alarm is not masked in the ALARMOUT source registers

(address 0x1C through 0x1D). When an alarm event is masked, the occurrence of the event sets the

corresponding status bit in the alarm status registers, but does not activate the ALARMOUT pin.

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7.3.2.4.1 Unipolar Inputs Out-of-Range Alarms

The AMC7836 device provides out-of-range detection for the five external unipolar ADC inputs (LV_ADC16

through LV_ADC20, pins 35 through 39). Figure 55 shows the out-of-range detection block. When the

measurement is out-of-range, the corresponding alarm bit in the alarm status 0 register (address 0x70) is set to 1

to flag the out-of-range condition. The values in the ADC upper and lower Threshold registers (address 0x80

through 0x93) define the upper and lower bound thresholds for all five inputs.

ADCn-Upper-

Threshold Value

(upper bound)

œ

+

LV_ADCn

Conversion Value

(n = 16 to 20)

ADCn-ALR

Bit

œ

ADCn-Lower-

Threshold Value

(lower bound)

+

Figure 55. Unipolar Inputs Out-of-Range Alarms

7.3.2.4.2 Unipolar Inputs Out-of-Range Alarms

The AMC7836 includes high-limit and low-limit detection for the internal temperature sensor. Figure 56 shows the

temperature detection block. The values in the LT upper and lower threshold registers (address 0x94 through

0x97) set the limits for the temperature sensor. The temperature sensor detector can issue either a high-alarm

(LT-HIGH-ALR bit) or a low-alarm (LT-LOW-ALR bit) in the alarm status 1 register (address 0x71) depending on

whether the high or low thresholds were exceeded. To implement single, upper-bound threshold detection for the

temperature sensor, the host processor can set the upper-bound threshold to the desired value and the lower-

bound threshold to the default value. For lower-bound threshold detection, the host processor can set the lower-

bound threshold to the desired value and the upper-bound threshold to the default value.

In addition to the programmable threshold alarms the temperature sensor detection circuit also includes a die

thermal-alarm flag which continuously monitors the die temperature. When the die temperatures exceeds 150˚C

the die thermal alarm flag (THERM-ALR bit) in the alarm status 1 register (address 0x71) is set. The internal

temperature sensor must be enabled for this alarm to be functional.

Temperature

High Threshold

(upper bound)

œ

LT-HIGH-ALR Bit

THERM-ALR Bit

+

150°C

œ

Temperature

Data

+

œ

LT-LOW-ALR Bit

Temperature

Low Threshold

(lower bound)

+

Figure 56. Internal Temperature Out-of-Range Alarms

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7.3.2.4.3 ALARMIN Alarm

The AMC7836 device offers the option of using an external interrupt signal, such as the output of a comparator

as an alarm event. The GPIO0/ALARMIN pin is used as the alarm input and must be configured accordingly in

the GPIO configuration register (address 0x12). The pin is active low when configured as an alarm input.

A typical application for ALARMIN pin is to use it as a hardware interrupt that is responsible for forcing one or

more DACs to a CLEAR state. The DAC is loaded with a zero-code input and the output voltage is set according

to the operating output range, however the DAC buffer or active registers do not change (see the Digital-to-

Analog Converters (DACs) section for more details). To enable this functionality the ALARMIN pin must be

enabled as a DAC clear-alarm source in the DAC clear source 1 register (address 0x1B). Additionally the DAC

outputs to be cleared by the ALARMIN pin must be specified in the DAC clear enable registers (address 0x18

through 0x19).

In this application when the ALARMIN pin goes low, all the DACs that are set to clear in response to the

ALARMIN alarm in the DAC-clear enable registers enter a CLEAR state. When the ALARMIN pin goes back high

the DACs are reloaded with the contents of the DAC active registers which allows the DAC outputs to return to

the previous operating point without any additional commands.

7.3.2.4.4 Hysteresis

If a monitored signal is out of range and the alarm is enabled, the corresponding alarm bit is set to 1. However,

the alarm condition is cleared only when the conversion result returns either a value lower than the high

threshold register setting or higher than the low threshold register setting by the number of codes specified in the

hysteresis setting (see Figure 57). The ADC and LT hysteresis registers (address 0xA0 through 0xA4) store the

hysteresis value for the external unipolar inputs and internal temperature sensor programmable alarms. The

hysteresis is a programmable value between 0 LSB to 127 LSB for the unipolar inputs alarms and 0°C to 31°C

for the internal temperature-sensor alarms. The die thermal alarm hysteresis is fixed at 8°C.

High Threshold

Hysteresis

Low Threshold

Over High Alarm

Below Low Alarm

Figure 57. Device Hysteresis

7.3.2.4.5 False-Alarm Protection

To prevent false alarms, an alarm event is only registered when the monitored signal is out of range for an N

number of consecutive conversions. If the monitored signal returns to the normal range before N consecutive

conversions, an alarm event is not issued. The false alarm factor, N, for the unipolar input and local temperature

sensor out-of-range alarms can be configured in the false alarm configuration register (address 0x11).

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7.3.3 Internal Temperature Sensor

The AMC7836 device has an on-chip temperature sensor that measures the device die temperature. The normal

operating temperature range for the internal temperature sensor is limited by the operating temperature range of

the device (–40°C to 125°C).

The temperature sensor results are converted by the device ADC at a lower speed than the analog input

channels. The temperature can be monitored either continuously or as a single-time conversion depending on

whether the ADC is configured in auto mode or direct mode (see the Analog-to-Digital Converter (ADC) section

for more details). If the temperature sensor is not needed, it can be disabled in the ADC MUX configuration 2

register (address 0x15). When disabled, the temperature sensor output is not converted by the ADC.

The temperature sensor provides 0.25°C resolution over the operating temperature range. The temperature

value is stored in 12-bit two’s complement format in the temperature data registers (address 0x78 through 0x79).

Table 3. Temperature Sensor Data Format

TEMPERATURE (°C)

DIGITAL CODE

1111 0110 0000

1111 1001 1100

1111 1101 1000

1111 1111 1111

0000 0000 0000

0000 0000 0001

0000 0010 1000

0000 0110 0100

0000 1100 1000

0001 0010 1100

0001 1001 0000

0001 1010 0100

0001 1111 0100

–40

–25

–10

–0.25

0

0.25

10

25

50

75

100

105

125

Use Equation 3 and Equation 4 to calculate the positive or negative temperature according to the polarity of the

temperature data MSB (0 - positive, 1 - negative).

ADC _Code

Positive Temperature (èC) =

4

(3)

(4)

4096 - ADC_Code

Negative Temperature (èC) =

4

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7.3.4 Internal Reference

The AMC7836 device includes a high-performance internal reference for the on-chip ADC and 16 DACs (see

Figure 58). The internal reference is a 2.5 V, bipolar transistor-based, precision bandgap reference. A

compensation capacitor (4.7 μF, typical) should be connected between the REF_CMP pin and the AGND2 pin.

The AMC7836 device includes a buffer to drive the ADC and should not be used to drive any external circuitry.

The ADC reference buffer is powered down by default and should be enabled in the ADC configuration register

(address 0x10) during device initialization.

Internal

Reference

(2.5 V)

C > 4.7 µF

(Minimize

inductance to pin)

REF_CMP

AGND2

DAC-0

12-b

DAC-1

12-b

ADC

12-b

Local

Temperatu

re Sensor

DAC-15

12-b

Figure 58. AMC7836 Internal Reference

The internal reference is typically established after power-up in less than 5 ms at T_A= 25°C however the

reference settling time is highly dependent on temperature. Figure 59 shows typical reference settling time as a

function of temperature.

160

140

120

100

80

60

40

20

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature (°C)

D001

Figure 59. Internal Reference Settling Time vs Temperature

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7.3.5 General Purpose I/Os

The AMC7836 device includes eight GPIO pins, each with an internal 48-kΩ pullup resistor to the IOV_DDpin. The

GPIO[0:3] pins have dual functionality and can be programmed as either bidirectional digital I/O pins or interrupt

signals in the GPIO configuration register (address 0x12). The GPIO[4:7] pins are dedicated GPIOs. Table 4 lists

the dual function of the GPIO[0:3] pins.

Table 4. Dual Functionality GPIO Pins

ALTERNATIVE

DEFAULT PIN NAME

ALTERNATIVE PIN NAME

FUNCTIONALITY

DAC clear control signal.

Global alarm output.

7

8

GPIO0

GPIO1

GPIO2

GPIO3

ALARMIN

ALARMOUT

ADCTRIG

DAV

9

External ADC conversion trigger.

ADC data available indicator.

10

The GPIOs can receive an input or produce an output. When the GPIOn pin acts as an output, the status of the

pin is determined by the corresponding GPIO bit in the GPIO register (address 0x7A).

To use a GPIOn pin as an input, the corresponding GPIO bit in the GPIO register must be set to 1. When a

GPIOn pin acts as input, the digital value on the pin is acquired by reading the corresponding GPIO bit. After a

power-on reset (POR) or any forced reset, all GPIO bits are set to 1, and the GPIOn pins have a 48-kΩ input

impedance to the IOV_DDpin (see Figure 60). The unused GPIO pins can be left floating.

IOV_DD

48 kΩ

GPIOn

ENABLE

GPIOn Bit

(when writing)

GPIOn Bit

(when reading)

Figure 60. AMC7836 GPIO Pin

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7.4 Device Functional Modes

The sixteen DACs in the AMC7836 device are split into four groups, each with four DACs. The output range and

clamp voltage for each DAC group is set independently which enables the device to operate in one of the

following modes:

•

All-positive DAC range mode

All-negative DAC range mode

Mixed DAC range mode

7.4.1 All-Positive DAC Range Mode

In the AMC7836 all-positive DAC range mode, each of the four DAC groups is set to a positive voltage output

range (0 to 5 V or 0 to 10 V).

Because the maximum DAC output for each group cannot exceed the common AV_CCvoltage for the device

(AV_CC= AV_{CC_AB}= AV_{CC_CD}), a DAC group in the 0 to 10 V output range forces the AV_CCvoltage to a value

greater or equal to 10 V even if the remaining DAC groups are set in the 0 to 5 V range. If all DAC groups are

set in the 0 to 5 V range the AV_CCvoltage can be set to a value as low as 5 V.

The minimum DAC output for each group cannot be lower than the AV_SSvoltage but because the minimum DAC

output is 0 V in the all-positive DAC range mode, all of the AV_SSpins (AV_EE, AV_SSB, AV_SSC, and AV_SSD) as well

as the device thermal pad can be tied to AGND thus simplifying the board design. Table 5 lists the typical

configurations for this mode.

Table 5. All-positive DAC Range Mode Typical Configuration

NOTES

TYPICAL CONNECTION

AV_DD

DV_DD

IOV_DD

5 V

DV_DDmust be equal to AV_DD

.

5 V

IOV_DDmust be equal to or less than DV_DD

.

1.8 V to 5 V

The AV_{CC_AB}and AV_{CC_CD}pins must be tied

to the same potential (AV_CC).

AV_CCmust be greater or equal than the

maximum possible output voltage for any of

the sixteen DACs.

AV_CC≥ 5 V

AV_CC≥ 10 V

AV_{CC_AB}, AV_{CC_CD}

AV_EE

AGND

AV_SSB, AV_SSC, AV_SSD

Thermal Pad

After power-on or a reset event the output range for each DAC group is set automatically by the voltage present

on the corresponding AV_SSpin. In the all-positive DAC range mode all AV_SSpins are connected to AGND and

consequently all four DAC groups will initialize by default to the 0 to 5 V range. The output for any of the DAC

groups can be modified to the 0 to 10 V range after initialization by setting the corresponding DAC range register

(address 0x1E to 0x1F) to 110b.

In addition to setting the default output range, the AV_SSpins also set the clamp voltage for each DAC group.

Because the clamp voltage is only dependent on the voltage in the AV_SSpin, changes to the DAC range

registers do not affect the clamp setting. With the AV_SSpins connected to AGND, the clamp voltage for all

sixteen DACs is 0 V.

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7.4.2 All-Negative DAC Range Mode

In the AMC7836 all-negative DAC range mode, each of the four DAC groups is set to a negative voltage output

range (–5 to 0 V or –10 to 0 V).

Although the maximum DAC output does not exceed 0 V, the common AV_CCvoltage (AV_CC= AV_{CC_AB}

=

AV_{CC_CD}) must still satisfy a minimum voltage of 4.7 V to comply with the device operating conditions. In this

case a recommended approach is to tie the AV_CC, AV_DD, and DV_DDsupply pins to a common potential.

The minimum DAC output for each group cannot be lower than the voltage on the corresponding AV_SSpins

(AV_EE, AV_SSB, AV_SSC, and AV_SSD). The AV_SSpins are not required to be tied to the same potential and typically

the negative voltage at each AV_SSpin is dictated by the desired operating DAC negative output range. One

exception is the AV_EEpin which must be the lowest potential in the device. The thermal pad should be either tied

to the same potential as the AV_EEpin or left disconnected. Table 6 lists the typical configurations for this mode.

Table 6. All-Negative DAC Range Mode Typical Configuration

NOTES

TYPICAL CONNECTION

AV_DD

DV_DD

IOV_DD

5 V

DV_DDmust be equal to AV_DD

.

5 V

IOV_DDmust be equal to or less than DV_DD

.

1.8 V to 5 V

The AV_{CC_AB}and AV_{CC_CD}pins must be tied

to the same potential (AV_CC).

AV_{CC_AB}, AV_{CC_CD}

5 V

AV_EEmust be the lowest potential in the

device.

AV_EEmust be less than or equal to the

minimum possible output voltage for DAC

group A.

AV_EE≤ –5 V

AV_EE≤ –10 V

AV_EE

AV_SSnmust be less than or equal to the

minimum possible output voltage for DAC

group n (n = B, C, D).

AV_EE≤ AV_SSn≤ –5 V

AV_EE≤ AV_SSn≤ –10 V

AV_SSB, AV_SSC, AV_SSD

Thermal Pad

AV_EEor,

Floating

After power-on or a reset event the output range for each DAC group is set automatically by the voltage present

in the corresponding AV_SSpin. In the all-negative DAC range mode all AV_SSpins should be connected to a

voltage lower than AV_SSTH. If this condition is satisfied, all four DAC groups will initialize by default to the –10- to

0-V range. Because the negative clamp voltage is only dependent on the voltage in the AV_SSpin, the default

–10- to 0-V output range presents no risk even when the AV_SSvoltage is greater than –10 V. In this case the

DAC group output should be modified to the –5 to 0 V range after initialization by setting the corresponding DAC

range register (address 0x1E to 0x1F) to 101b.

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7.4.3 Mixed DAC Range Mode

In the AMC7836 mixed DAC range mode, a combination of DAC groups is set to a negative voltage output range

(–5 to 0 V or –10 to 0 V) and a positive voltage output range (0 to 5 V or 0 to 10 V).

Because the maximum DAC output for each group cannot exceed the common AV_CCvoltage for the device

(AV_CC= AV_{CC_AB}= AV_{CC_CD}), a DAC group in the 0 to 10 V output range forces the AV_CCvoltage to a value

greater or equal to 10 V. If all positive DAC groups are in the 0 to 5 V range the AV_CCvoltage can be set to a

value as low as 5 V.

The minimum DAC output for each group cannot be lower than the voltage on the corresponding AV_SSpins

(AV_EE, AV_SSB, AV_SSCand AV_SSD). The AV_SSpins are not required to be tied to the same potential and typically

the negative voltage at each AV_SSpin is dictated by the desired operating DAC negative output range. One

exception is the AV_EEpin which must be the lowest potential in the device. The implication of this requirement is

that if either DAC group B, C or D is set to a negative output range, DAC group A must also be set to a negative

range. The thermal pad should be either tied to the same potential as the AV_EEpin or left disconnected. Table 7

lists the typical configurations for this mode.

Table 7. Mixed DAC Range Mode Typical Configuration

NOTES

TYPICAL CONNECTION

AV_DD

DV_DD

IOV_DD

5 V

DV_DDmust be equal to AV_DD

.

5 V

IOV_DDmust be equal to or less than DV_DD

.

1.8 V to 5 V

The AV_{CC_AB}and AV_{CC_CD}pins must be tied to the

same potential (AV_CC).

AV_CCmust be greater or equal to the maximum

possible output voltage for any of the positive

output range DACs.

AV_CC≥ 5 V

AV_CC≥ 10 V

AV_{CC_AB}, AV_{CC_CD}

AVEE must be the lowest potential in the device.

AV_EEmust be less than or equal to the minimum

possible output voltage for DAC group A.

AVEE ≤ –5 V

AVEE ≤ –10 V

AV_EE

AV_EE≤ AV_SSn≤ –5 V

AV_EE≤ AV_SSn≤ –10 V

AV_SSnmust be less than or equal than the minimum

possible output voltage for DAC group n (n = B, C,

D).

Negative Range

Positive Range

AV_SSB, AV_SSC, AV_SSD

Thermal Pad

AGND

AV_EEor,

Floating

After power-on or a reset event the output range for each DAC group is set automatically by the voltage present

in the corresponding AV_SSpin. When the AV_SSvoltage of a DAC group is lower than the threshold value, AV_SSTH

,

the output for that DAC group is automatically configured to the –10 to 0 V range. Conversely, if the AV_SSvoltage

of the DAC group is higher than AV_SSTH, the DAC-group output is automatically set to the 0 to 5 V range. The

output for any of the DAC groups can be modified after initialization by setting the corresponding DAC range

register (address 0x1E to 0x1F).

In addition to setting the default output range, the AV_SSpins also set the clamp voltage for each DAC group.

Because the clamp voltage is only dependent on the voltage in the AV_SSpin, changes to the DAC range

registers do not affect the clamp setting.

NOTE

Although not a recommended operating condition, the device allows a DAC group to

operate in a positive output range even if the clamp voltage is negative (AV_SSconnected

to a negative supply voltage).

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7.5 Programming

The AMC7836 device is controlled through a flexible four-wire serial interface that is compatible with SPI-type

interfaces used on many microcontrollers and DSP controllers. The interface provides read and write (R/W)

access to all registers of the AMC7836 device.

Each serial-interface access cycle is exactly (N + 2) bytes long, where N is the number of data bytes. Asserting

the CS pin low initiates a frame. The frame ends when the CS pin is deasserted high. In MSB-first mode, the first

bit transferred is the R/W bit. The next 15 bits are the register address (32768 addressable registers), and the

remaining bits are data. For all writes, data is committed in bytes as the eight data bit of a data field that is

clocked in on the rising edge of SCLK. If the write access is not an even multiple of 8 clocks, the trailing data bits

are not committed. On a read access, data is clocked out on the falling edge of the serial interface clock, SCLK,

on the SDO pin.

Figure 61 and Figure 62 show the access protocol used by the interface.

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK

SDI

R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 61. Serial Interface Write Bus Cycle

CS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK

SDI

R/W

A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

SDO

D7 D6 D5 D4 D3 D2 D1 D0

Figure 62. Serial Interface Read Bus Cycle

Streaming mode is supported for operations that require large amounts of data to be passed to or from the

AMC7836. In streaming mode multiple bytes of data can be written to or read from the AMC7836 without

specifically providing instructions for each byte. Streaming mode is implemented by continually holding the CS

pin active and continuing to shift new data in or old data out of the device.

The instruction phase includes the starting address. The AMC7836 device begins reading or writing data to this

address and continues as long as the CS pin is asserted and single byte writes have not been enabled in the

interface configuration 1 register (address 0x01). The AMC7836 device automatically increments or decrements

the address depending on the setting of the address ascension bit in the interface configuration 0 register

(address 0x00).

If the address is decrementing and address 0x0000 is reached, the next address used is 0x7FFF. If the address

is incrementing and address 0x7FFF is reached, the next address used is 0x0000. Care should be taken when

writing to address 0x0000 and 0x0001 as writing to these addresses may change the configuration of the serial

interface. Therefore address 0x0010 should be the first (ascending) or last (descending) address accessed in

streaming mode.

Figure 63 and Figure 64 show the access protocol used in streaming mode.

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Programming (continued)

CS

1

2

3

4

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SCLK

SDI

Addr N+1 (ascending)

Addr N-1 (descending)

Address N

R/W A14 A13 A12

A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO

Figure 63. Serial Interface Streaming Write Example

CS

1

2

3

4

14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

SCLK

SDI

Addr N+1 (ascending)

Addr N-1 (descending)

Address N

A2 A1 A0

R/W A14 A13 A12

SDO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 64. Serial Interface Streaming Read Example

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7.6 Register Maps

Table 8. Register Map

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07 – 0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

TYPE

R/W

R

DEFAULT

30

00

03

08

36

0C

00

—

REGISTER NAME

Interface Configuration 0

Interface Configuration 1

Device Configuration

Chip Type

R

Chip ID (Low Byte)

Chip ID (High Byte)

Chip Version

R

—

Reserved

R

51

04

—

Manufacturer ID (Low Byte)

Manufacturer ID (High Byte)

Reserved

R

—

R/W

—

00

70

00

—

Register Update

ADC Configuration

False Alarm Configuration

GPIO Configuration

ADC MUX Configuration 0

ADC MUX Configuration 1

ADC MUX Configuration 2

Reserved

—

Reserved

R/W

R

00

DAC Clear Enable 0

DAC Clear Enable 1

DAC Clear Source 0

DAC Clear Source 1

ALARMOUT Source0

ALARMOUT Source1

DAC Range 0

DAC Range 1

ADC0-Data (Low Byte)

ADC0-Data (High Byte)

ADC1-Data (Low Byte)

ADC1-Data (High Byte)

ADC2-Data (Low Byte)

ADC2-Data (High Byte)

ADC3-Data (Low Byte)

ADC3-Data (High Byte)

ADC4-Data (Low Byte)

ADC4-Data (High Byte)

ADC5-Data (Low Byte)

ADC5-Data (High Byte)

ADC6-Data (Low Byte)

ADC6-Data (High Byte)

ADC7-Data (Low Byte)

ADC7-Data (High Byte)

ADC8-Data (Low Byte)

R

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Table 8. Register Map (continued)

ADDRESS

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C - 0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

TYPE

R

DEFAULT

00

—

REGISTER NAME

ADC8-Data (High Byte)

ADC9-Data (Low Byte)

ADC9-Data (High Byte)

ADC10-Data (Low Byte)

ADC10-Data (High Byte)

ADC11-Data (Low Byte)

ADC11-Data (High Byte)

ADC12-Data (Low Byte)

ADC12-Data (High Byte)

ADC13-Data (Low Byte)

ADC13-Data (High Byte)

ADC14-Data (Low Byte)

ADC14-Data (High Byte)

ADC15-Data (Low Byte)

ADC15-Data (High Byte)

ADC16-Data (Low Byte)

ADC16-Data (High Byte)

ADC17-Data (Low Byte)

ADC17-Data (High Byte)

ADC18-Data (Low Byte)

ADC18-Data (High Byte)

ADC19-Data (Low Byte)

ADC19-Data (High Byte)

ADC20-Data (Low Byte)

ADC20-Data (High Byte)

Temperature Data (Low Byte)

Temperature Data (High Byte)

Reserved

R

—

R/W

00

DACA0-Data (Low Byte)

DACA0-Data (High Byte)

DACA1-Data (Low Byte)

DACA1-Data (High Byte)

DACA2-Data (Low Byte)

DACA2-Data (High Byte)

DACA3-Data (Low Byte)

DACA3-Data (High Byte)

DACB4-Data (Low Byte)

DACB4-Data (High Byte)

DACB5-Data (Low Byte)

DACB5-Data (High Byte)

DACB6-Data (Low Byte)

DACB6-Data (High Byte)

DACB7-Data (Low Byte)

DACB7-Data (High Byte)

DACC8-Data (Low Byte)

DACC8-Data (High Byte)

DACC9-Data (Low Byte)

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Table 8. Register Map (continued)

ADDRESS

0x63

TYPE

R/W

R

DEFAULT

00

0C

—

REGISTER NAME

DACC9-Data (High Byte)

DACC10-Data (Low Byte)

DACC10-Data (High Byte)

DACC11-Data (Low Byte)

DACC11-Data (High Byte)

DACD12-Data (Low Byte)

DACD12-Data (High Byte)

DACD13-Data (Low Byte)

DACD13-Data (High Byte)

DACD14-Data (Low Byte)

DACD14-Data (High Byte)

DACD15-Data (Low Byte)

DACD15-Data (High Byte)

Alarm Status 0

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

R

Alarm Status 1

0x72

R

General Status

0x73 - 0x79

0x7A

0x7B - 0x7F

0x80

—

Reserved

R/W

—

FF

—

GPIO

Reserved

R/W

—

FF

0F

00

FF

0F

00

FF

0F

00

FF

0F

00

FF

0F

00

FF

07

00

08

—

ADC16-Upper-Thresh (Low Byte)

ADC16-Upper-Thresh (High Byte)

ADC16-Lower-Thresh (Low Byte)

ADC16-Lower-Thresh (High Byte)

ADC17-Upper-Thresh (Low Byte)

ADC17-Upper-Thresh (High Byte)

ADC17-Lower-Thresh (Low Byte)

ADC17-Lower-Thresh (High Byte)

ADC18-Upper-Thresh (Low Byte)

ADC18-Upper-Thresh (High Byte)

ADC18-Lower-Thresh (Low Byte)

ADC18-Lower-Thresh (High Byte)

ADC19-Upper-Thresh (Low Byte)

ADC19-Upper-Thresh (High Byte)

ADC19-Lower-Thresh (Low Byte)

ADC19-Lower-Thresh (High Byte)

ADC20-Upper-Thresh (Low Byte)

ADC20-Upper-Thresh (High Byte)

ADC20-Lower-Thresh (Low Byte)

ADC20-Lower-Thresh (High Byte)

LT-Upper-Thresh (Low Byte)

LT-Upper-Thresh (High Byte)

LT-Lower-Thresh (Low Byte)

LT-Lower-Thresh (High Byte)

Reserved

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98 - 0x9F

0xA0

0xA1

0xA2

R/W

08

ADC16-Hysteresis

ADC17-Hysteresis

ADC18-Hysteresis

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Table 8. Register Map (continued)

ADDRESS

0xA3

TYPE

R/W

—

DEFAULT

REGISTER NAME

ADC19-Hysteresis

ADC20-Hysteresis

LT-Hysteresis

Reserved

08

—

00

—

00

0xA4

0xA5

0xA6 - 0xAF

0xB0

R/W

—

DAC Clear 0

0xB1

DAC Clear 1

0xB2

Power-Down 0

Power-Down 1

Power-Down 2

Reserved

0xB3

0xB4

0xB5 - 0xBF

0xC0

R/W

ADC Trigger

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7.6.1 Interface Configuration: Address 0x00 – 0x02

7.6.1.1 Interface Configuration 0 Register (address = 0x00) [reset = 0x30]

Figure 65. Interface Configuration 0 (Interface Config 0) Register (R/W)

7

6

5

4

3

2

1

0

SOFT-RESET

Reserved

ADDR-

Reserved

ASCEND

R/W-0

R/W-1

R/W-All zeros

Table 9. Interface Config 0 Register Field Descriptions (R/W)

Bit

Field

Type

Reset

Description

7

SOFT-RESET

R/W

0

Soft reset (self-clearing)

0: no action

1: reset – resets everything except address 0x00, 0x01

Reserved for factory use

6

5

Reserved

R/W

0

1

ADDR-ASCEND

Address Ascend

0: Descend

– decrements address while streaming

(address wrap from 0x0000 to 0x7FFF)

1: Ascend – increments address while streaming (address

wrap from 0x7FFF to 0x0000)

4

Reserved

R/W

1

Reserved for factory use

3-0

All zeros

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7.6.1.2 Interface Configuration 1 Register (address = 0x01) [reset = 0x00]

Figure 66. Interface Configuration 1 (Interface Config 1) Register (R/W)

7

6

5

4

3

2

1

0

SINGLE-INSTR

R/W-0

Reserved

R/W-0

READBACK

R/W-0

Reserved

R/W-All zeros

Table 10. Interface Config 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SINGLE-INSTR

R/W

0

Single instruction enable

0: streaming mode (default)

1: single instruction

6

5

Reserved

R/W

0

Reserved for factory use

Read back

READBACK

0: DAC read back from active registers (default)

1: DAC read back from buffer registers

4-0

Reserved

R/W

All zeros

Reserved for factory use

7.6.1.3 Device Configuration Register (address = 0x02) [reset = 0x03]

Figure 67. Device Configuration (Device Config) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

POWER-MODE

R/W-11

R/W-All Zeros

Table 11. Device Config Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

All zeros

Reserved for factory use

Mode:

1-0

POWER-MODE

R/W

11

00: Normal operation – full power and full performance

11: Power Down – lowest power, non-operational except

SPI

One time overwrite of the power-down registers (0xB2 and

0xB3)

7.6.2 Device Identification: Address 0x03 – 0x0D

7.6.2.1 Chip Type Register (address = 0x03) [reset = 0x08]

Figure 68. Chip Type Register (R)

7

6

5

4

3

2

1

0

Reserved

R-0x0

CHIP-TYPE

R-0x8

Table 12. Chip Type Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R

0x0

Reserved for factory use

3-0

CHIP-TYPE

R

0x8

Identifies the device as a precision analog monitor and control

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7.6.2.2 Chip ID Low Byte Register (address = 0x04) [reset = 0x36]

Figure 69. Chip ID Low Byte Register (R)

7

6

5

4

3

2

1

0

CHIPID-LOW

R-0x36

Table 13. Chip ID Low Byte Register Field Descriptions

Bit

Field

CHIPID-LOW

Type

Reset

Description

7-0

R

0x36

Chip ID. Low byte

7.6.2.3 Chip ID High Byte Register (address = 0x05) [reset = 0x0C]

Figure 70. Chip ID High Byte Register (R)

7

6

5

4

3

2

1

0

CHIPID-HIGH

R-0x0C

Table 14. Chip ID High Byte Register Field Descriptions

Bit

Field

CHIPID-HIGH

Type

Reset

Description

7-0

R

0x0C

Chip ID. High byte

7.6.2.4 Version ID Register (address = 0x06) [reset = 0x00]

Figure 71. Version ID Register (R)

7

6

5

4

3

2

1

VERSIONID

R-0x00

Table 15. Version ID Register Field Descriptions

Bit

Field

Type

Reset

Description

AMC7836 version ID. Subject to change

7-0

VERSIONID

R

0x00

7.6.2.5 Manufacturer ID Low Byte Register (address = 0x0C) [reset = 0x51]

Figure 72. Manufacturer ID Low Byte Register (R)

7

6

5

4

3

2

1

VENDORID-LOW

R-0x51

Table 16. Manufacturer ID Low Byte Register Field Descriptions

Bit

Field

VENDORID-LOW

Type

Reset

Description

7-0

R

0x51

Manufacturer ID. Low byte

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7.6.2.6 Manufacturer ID High Byte Register (address = 0x0D) [reset = 0x04]

Figure 73. Manufacturer ID High Byte Register

7

6

5

4

3

2

1

0

VENDORID-HIGH

R-0x04

Table 17. Manufacturer ID High Byte Register Field Descriptions

Bit

Field

VENDORID-HIGH

Type

Reset

Description

7-0

R

0x04

Manufacturer ID. High byte

7.6.3 Register Update (Buffered Registers): Address 0x0F

7.6.3.1 Register Update Register (address = 0x0F) [reset = 0x00]

Figure 74. Register Update Register (Self Clearing) [R/W]

7

6

5

4

3

2

1

0

Reserved

R/W-All Zeros

ADC-UPDATE

R/W-0

Reserved

R/W-All Zeros

UPDATE

R/W-0

Table 18. Register Update Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use

4

ADC-UPDATE

R/W

0

When set transfers the latest ADC and temperature conversion

data to the ADC and Temperature Data registers. This function

is needed when operating the ADC in auto-cycle mode

3-1

0

Reserved

R/W

All zeros

0

Reserved for factory use

DAC-UPDATE

DAC update (self clearing)

0: disabled

1: enabled – transfers data from buffers to active registers

(DAC registers only)

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7.6.4 General Device Configuration: Address 0x10 through 0x17

7.6.4.1 ADC Configuration Register (address = 0x10) [reset = 0x00]

Figure 75. ADC Configuration Register (R/W)

7

6

5

4

3

2

1

0

CMODE

CONV-RATE[1:0]

ADC-REF-

BUFF

Reserved

R/W-0

R/W-00

R/W-0

R/W-All zeros

Table 19. ADC Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7

CMODE

R/W

0

ADC Conversion Mode Bit. This bit selects the ADC conversion

mode.

0: Direct mode. The analog inputs specified in the ADC

channel registers are converted sequentially one time.

When one set of conversions is complete, the ADC is idle

and waits for a new trigger.

1: Auto mode. The analog inputs specified in the AMC

channel registers are converted sequentially and

repeatedly. When one set of conversions is complete, the

ADC multiplexer returns to the first channel and repeats the

process. The ADC-UPDATE bit in register 0x0F must be

used to initiate the transfer of the latest conversion data to

the ADC Data registers.

6-5

4

CONV-RATE[1:0]

ADC-REF-BUFF

R/W

00

0

ADC Conversion rate. See Table 20 to configure this setting.

ADC Reference Buffer bit. This bit must be set to 1 after device

power-up to enable the internal reference buffer driving the

ADC.

0: ADC reference buffer is disabled.

1: ADC reference buffer is enabled.

3-0

Reserved

R/W

All zeros

Reserved for factory use

Table 20. CONV-RATE[1:0] Bit Configuration

Bipolar Channel Sample

CONV-RATE[1:0]

Unipolar Channel Sample Time (µs)

Time (µs)

00

01

10

11

11.5

23

34.5

69

34.5

69

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7.6.4.2 False Alarm Configuration Register (address = 0x11) [reset = 0x70]

Figure 76. False Alarm Configuration Register (R/W)

7

6

5

4

3

2

1

0

CH-FALR-CT[2:0]

R/W-011

TEMP-FALR-CT[1:0]

R/W–10

Reserved

R/W-All zeros

Table 21. False Alarm Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

CH-FALR-CT[2:0]

R/W

011

False alarm protection for ADC channels. See Table 22 to

configure this bit.

4-3

2-0

TEMP-FALR-CT[1:0]

Reserved

R/W

10

False alarm protection for temperature sensor. See Table 23 to

configure this bit.

All zeros

Reserved for factory use

Table 22. CH-FALR-CT Bit Configuration

N Consecutive Samples Before

CH-FALR-CT

Alarm is Set

000

001

010

011

100

101

110

111

1

4

8

16

32

64

128

256

Table 23. TEMP-FALR-CT Bit Configuration

N Consecutive Samples Before

TEMP-FALR-CT

Alarm is Set

00

01

10

11

1

2

4

8

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7.6.4.3 GPIO Configuration Register (address = 0x12) [reset = 0x00]

Figure 77. GPIO Configuration Register (R/W)

7

6

5

4

3

2

1

0

Reserved

EN-DAV

EN-ADCTRIG

EN-

EN-ALARMIN

ALARMOUT

R/W-All zeros

R/W-0

Table 24. GPIO Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use

4

3

Reserved

EN-DAV

R/W

0

DAV pin enable

0: GPIO3 operation (default)

1: DAV operation

2

1

0

EN-ADCTRIG

EN-ALARMOUT

EN-ALARMIN

R/W

0

ADCTRIG pin enable

0: GPIO2 operation (default)

1: ADCTRIG operation

ALARMOUT pin enable

0: GPIO1 operation (default)

1: ALARMOUT operation

ALARMIN pin enable

0: GPIO0 operation (default)

1: ALARMIN operation

7.6.4.4 ADC MUX Configuration 0 Register (address = 0x13) [reset = 0x00]

Figure 78. ADC MUX Configuration 0 Register (R/W)

7

6

5

4

3

2

1

0

CH7

R/W-0

CH6

R/W-0

CH5

R/W-0

CH4

R/W-0

CH3

R/W-0

CH2

R/W-0

CH1

R/W-0

CH0

R/W-0

Table 25. ADC MUX Configuration 0 Register Field Descriptions

Bit

Field

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

Type

R/W

Reset

Description

7

6

5

4

3

2

1

0

When set to 1 the corresponding analog input channel ADC_n is

accessed during an ADC conversion cycle.

When cleared to 0 the corresponding input channel ADC_n is

ignored during an ADC conversion cycle.

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7.6.4.5 ADC MUX Configuration 1 Register (address = 0x14) [reset = 0x00]

Figure 79. ADC MUX Configuration 1 Register (R/W)

7

6

5

4

3

2

1

0

CH15

R/W-0

CH14

R/W-0

CH13

R/W-0

CH12

R/W-0

CH11

R/W-0

CH10

R/W-0

CH9

R/W-0

CH8

R/W-0

Table 26. ADC MUX Configuration 1 Register Field Descriptions

Bit

Field

CH15

CH14

CH13

CH12

CH11

CH10

CH9

Type

R/W

Reset

Description

7

6

5

4

3

2

1

0

When set to 1 the corresponding analog input channel ADC_n is

accessed during an ADC conversion cycle.

When cleared to 0 the corresponding input channel ADC_n is

ignored during an ADC conversion cycle.

CH8

7.6.4.6 ADC MUX Configuration 2 Register (address = 0x15) [reset = 0x00]

Figure 80. ADC MUX Configuration 2 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

TEMP-CH

R/W-0

CH20

R/W-0

CH19

R/W-0

CH18

R/W-0

CH17

R/W-0

CH16

R/W-0

R/W-All Zeros

Table 27. ADC MUX Configuration 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

R/W

All Zeros

Reserved for factory use

5

TEMP-CH

R/W

0

When set to 1 the local temperature sensor is enabled for ADC

conversion.

When cleared to 0 the local temperature sensor is ignored.

4

3

2

1

0

CH20

CH19

CH18

CH17

CH16

R/W

0

When set to 1 the corresponding analog input channel ADC_n is

accessed during an ADC conversion cycle.

When cleared to 0 the corresponding input channel ADC_n is

ignored during an ADC conversion cycle.

55

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7.6.4.7 DAC Clear Enable 0 Register (address = 0x18) [reset = 0x00]

Figure 81. DAC Clear Enable 0 Register (R/W)

7

6

5

4

3

2

1

0

CLREN-B7

R/W-0

CLREN-B6

R/W-0

CLREN-B5

R/W-0

CLREN-B4

R/W-0

CLREN-A3

R/W-0

CLREN-A2

R/W-0

CLREN-A1

R/W-0

CLREN-A0

R/W-0

Table 28. DAC Clear Enable 0 Register Field Descriptions

Bit

7

Field

CLREN-B7

Type

R/W

Reset

Description

0

This register determines which DACs go into clear state when a

clear event is detected as configured in the DAC-CLEAR-

SOURCE registers.

6

CLREN-B6

CLREN-B5

CLREN-B4

CLREN-A3

CLREN-A2

CLREN-A1

CLREN-A0

5

If CLRENn = 1, DAC_n is forced into a clear state with a

clear event.

4

3

If CLRENn = 0, a clear event does not affect the state of

DAC_n.

2

1

0

7.6.4.8 DAC Clear Enable 1 Register (address = 0x19) [reset = 0x00]

Figure 82. DAC Clear Enable 1 Register (R/W)

7

6

5

4

3

2

1

0

CLREN-D15

R/W-0

CLREN-D14

R/W-0

CLREN-D13

R/W-0

CLREN-D12

R/W-0

CLREN-C11

R/W-0

CLREN-C10

R/W-0

CLREN-C9

R/W-0

CLREN-C8

R/W-0

Table 29. DAC Clear Enable 1 Register Field Descriptions

Bit

7

Field

CLREN-D15

Type

R/W

Reset

Description

0

This register determines which DACs go into clear state when a

clear event is detected as configured in the DAC-CLEAR-

SOURCE registers.

6

CLREN-D14

CLREN-D13

CLREN-D12

CLREN-C11

CLREN-C10

CLREN-C9

CLREN-C8

5

If CLRENn = 1, DAC_n is forced into a clear state with a

clear event.

4

3

If CLRENn = 0, a clear event does not affect the state of

DAC_n.

2

1

0

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7.6.5 DAC Clear and ALARMOUT Source Select: Address 0x1A through 0x1D

7.6.5.1 DAC Clear Source 0 Register (address = 0x1A) [reset = 0x00]

Figure 83. DAC Clear Source 0 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

ADC20-ALR-

CLR

ADC19-ALR-

CLR

ADC18-ALR-

CLR

ADC17-ALR-

CLR

ADC16-ALR-

CLR

R/W-All zeros

R/W-0

Table 30. DAC Clear Source 0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use

4

3

2

1

0

ADC20-ALR-CLR

ADC19-ALR-CLR

ADC18-ALR-CLR

ADC17-ALR-CLR

ADC16-ALR-CLR

R/W

0

This register selects which alarm forces DACs into a clear state,

regardless of which DAC operation mode is active, auto or

manual. In order for DAC_n to go into clear mode, it must be

enabled in the DAC Clear Enable registers.

7.6.5.2 DAC Clear Source 1 Register (address = 0x1B) [reset = 0x00]

Figure 84. DAC Clear Source 1 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

ALARMIN-ALR

R/W-0

THERM-ALR

R/W-0

LT-HIGH-ALR

R/W-0

LT-LOW-ALR

R/W-0

R/W-All zeros

Table 31. DAC Clear Source 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use

3

2

1

0

ALARMIN-ALR

THERM-ALR

LT-HIGH-ALR

LT-LOW-ALR

R/W

0

This register selects which alarm forces DACs into a clear state,

regardless of which DAC operation mode is active, auto or

manual. In order for DAC_n to go into clear mode, it must be

enabled in the DAC Clear Enable registers.

7.6.5.3 ALARMOUT Source 0 Register (address = 0x1c) [reset = 0x00]

Figure 85. ALARMOUT Source 0 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

ADC20-ALR-

OUT

ADC19-ALR-

OUT

ADC18-ALR-

OUT

ADC17-ALR-

OUT

ADC16-ALR-

OUT

R/W-All zeros

R/W-0

Table 32. ALARMOUT Source 0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use

4

3

2

1

0

ADC20-ALR-OUT

ADC19-ALR-OUT

ADC18-ALR-OUT

ADC17-ALR-OUT

ADC16-ALR-OUT

R/W

0

This register selects which alarms can activate the ALARMOUT

pin. The ALARMOUT must be enabled for this function to take

effect.

57

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7.6.5.4 ALARMOUT Source 1 Register (address = 0x1D) [reset = 0x00]

Figure 86. ALARMOUT Source 1 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

ALARM-

LATCH-DIS

ALRIN-ALR-

OUT

THERM-ALR- LT-HIGH-ALR- LT-LOW-ALR-

OUT

R/W-All zeros

R/W-0

Table 33. ALARMOUT Source 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use

Alarm latch disable bit.

4

ALARM-LATCH-DIS

R/W

0

When cleared to 0 the alarm bits are latched. When an alarm

occurs, the corresponding alarm bit is set to “1”. The alarm bit

remains until the error condition subsides and the alarm register

is read. Before reading, the alarm bit is not cleared even if the

alarm condition disappears. When set to 1 the alarm bits are not

latched. When the alarm condition subsides, the alarm bits are

cleared regardless of whether the alarm bits have been read or

not.

3

2

1

0

ALRIN-ALR-OUT

THERM-ALR-OUT

LT-HIGH-ALR-OUT

LT-LOW-ALR-OUT

R/W

0

This register selects which alarms can activate the ALARMOUT

pin. The ALARMOUT must be enabled for this function to take

effect.

7.6.6 DAC Range: Address 0x1E

7.6.6.1 DAC Range Register (address = 0x1E) [reset = 0x00]

Figure 87. DAC Range Register (R/W)

7

6

5

4

3

2

1

0

Reserved

R/W-0

DAC-RANGEB[2:0]

R/W-All zeros

Reserved

R/W-0

DAC-RANGEA[2:0]

R/W-All zeros

Table 34. DAC Range Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Reserved

R/W

0

Reserved for factory use

6-4

DAC-RANGEB[2:0]

R/W

All zeros

DAC group B output voltage selection. Overrides output range

set by the auto-range detection circuit. See Table 35 to

configure this setting.

3

2

Reserved

R/W

0

Reserved for factory use

DAC-RANGEA[2:0]

All zeros

DAC group A output voltage selection. Overrides output range

set by the auto-range detection circuit. See Table 35 to

configure this setting.

Table 35. DAC-RANGEx Bit Configuration

DAC-RANGEx[2:0]

DAC Group x Output Voltage Range

0xx

100

101

110

111

Range set by auto-range detection circuit

–10 to 0 V

-5 to 0 V

0 to 10 V

0 to 5 V

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7.6.6.2 DAC Range 1 Register (address = 0x1F) [reset = 0x00]

Figure 88. DAC Range 1 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

R/W-0

DAC-RANGED[2:0]

R/W-All zeros

Reserved

R/W-0

DAC-RANGEC[2:0]

R/W-All zeros

Table 36. DAC Range 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Reserved

R/W

0

Reserved for factory use

6-4

DAC-RANGED[2:0]

R/W

All zeros

DAC group D output voltage selection. Overrides output range

set by the auto-range detection circuit. See Table 35 to

configure this setting.

3

2

Reserved

R/W

0

Reserved for factory use

DAC-RANGEC[2:0]

All zeros

DAC group C output voltage selection. Overrides output range

set by the auto-range detection circuit. See Table 35 to

configure this setting.

7.6.7 ADC and Temperature Data: Address 0x20 through 0x4B

7.6.7.1 ADCn-Data (Low Byte) Register (address = 0x20 through 0x49) [reset = 0x00]

Figure 89. ADCn-Data (Low Byte) Register (R)

7

6

5

4

3

2

1

0

ADCn-DATA(7:0)

R-All zeros

Table 37. ADCn-Data (Low Byte) Register Field Descriptions

Bit

Field

ADCn-DATA(7:0)

Type

Reset

Description

7-0

R

All zeros

Stores the 12-bit ADC_n conversion results in straight binary

format for both types of inputs channels (unipolar and bipolar)

7.6.7.2 ADCn-Data (High Byte) Register (address = 0x20 through 0x49) [reset = 0x00]

Figure 90. ADCn-Data (High Byte) Register (R)

7

6

5

4

3

2

1

0

Reserved

ADCn-DATA (11:8)

R-All zeros

Table 38. ADCn-Data (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R

All zeros

Reserved for factory use

3-0

ADCn-DATA (11:8)

R

All zeros

Stores the 12-bit ADC_n conversion results in straight binary

format for both types of inputs channels (unipolar and bipolar).

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7.6.7.3 Temperature Data (Low Byte) Register (address = 0x4A) [reset = 0x00]

Figure 91. Temperature Data (Low Byte) Register (R)

7

6

5

4

3

2

1

0

TEMP-DATA(7:0)

R-All zeros

Table 39. Temperature Data (Low Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

TEMP-DATA(7:0)

R

All zeros

Stores the temperature sensor reading in twos complement

format.

7.6.7.4 Temperature Data (High Byte) Register (address = 0x4B) [reset = 0x00]

Figure 92. Temperature Data (High Byte) Register (R)

7

6

5

4

3

2

1

0

Reserved

TEMP-DATA(11:8)

R-All zeros

Table 40. Temperature Data (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R

All zeros

Reserved for factory use.

3-0

TEMP-DATA(11:8)

R

All zeros

Stores the temperature sensor reading in twos complement

format.

7.6.8 DAC Data: Address 0x50 through 0x6F

7.6.8.1 DACn-Data (Low Byte) Register (address = 0x50 through 0x6F) [reset = 0x00]

Figure 93. DACn-Data (Low Byte) Register (R/W)

7

6

5

4

3

2

1

0

DACn-DATA (7:0)

R/W-All zeros

Table 41. DACn-Data (Low Byte) Register Field Descriptions

Bit

Field

DACn-DATA (7:0)

Type

Reset

Description

7-0

R/W

All zeros

Stores the 12-bit data to be loaded to the DAC_n latches in

straight binary format. The straight binary format is used for all

DAC ranges.

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7.6.8.2 DACn Data (High Byte) Register (address = 0x50 through 0x6F) [reset = 0x00]

Figure 94. DACn Data (High Byte) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

DACn-DATA (11:8)

R/W-All zeros

Table 42. DACn Data (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use

3-0

DACn-DATA (11:8)

R/W

All zeros

Stores the 12-bit data to be loaded to the DAC_n latches in

straight binary format. The straight binary format is used for all

DAC ranges.

7.6.9 Status Registers: Address 0x70 through 0x72

The AMC7836 device continuously monitors all general purpose analog inputs and local temperature sensor

during normal operation. When any input is out of the specified range N consecutive times, the corresponding

alarm bit is set (1). If the input returns to the normal range before N consecutive times, the corresponding alarm

bit remains clear (0). This configuration avoids any false alarms. When an alarm status occurs, the

corresponding alarm bit is set (1). When the corresponding bit in the ALARMOUT Source Registers is cleared

(0), the ALARMOUT pin is latched.

Whenever an alarm status bit is set, it remains set until the event that caused it is resolved and its status register

is read. Reading the Alarm Status Registers clears the alarm status bits. The alarm bit can only be cleared by

reading its Alarm Status register after the event is resolved, or by hardware reset, software reset, or power-on

reset. All alarm status bits are cleared when reading the Alarm Status registers, and all these bits are reasserted

if the out-of-limit condition still exists after the next conversion cycle, unless otherwise noted.

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7.6.9.1 Alarm Status 0 Register (address = 0x70) [reset = 0x00]

Figure 95. Alarm Status 0 Register (R)

7

6

5

4

3

2

1

0

Reserved

R-All zeros

ADC20-ALR

R-0

ADC19-ALR

R-0

ADC18-ALR

R-0

ADC17-ALR

R-0

ADC16-ALR

R-0

Table 43. Alarm Status 0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R

All zeros

Reserved for factory use

4

3

2

1

0

ADC20-ALR

R

0

ADC20-ALR = 1 when ADC20 is out of the range defined by the

corresponding threshold registers.

ADC20-ALR = 0 when the analog input is not out of the

specified range.

ADC19-ALR

ADC18-ALR

ADC17-ALR

ADC16-ALR

ADC19-ALR = 1 when ADC19 is out of the range defined by the

corresponding threshold registers.

ADC19-ALR = 0 when the analog input is not out of the

specified range.

ADC18-ALR = 1 when ADC18 is out of the range defined by the

corresponding threshold registers.

ADC18-ALR = 0 when the analog input is not out of the

specified range.

ADC17-ALR = 1 when ADC17 is out of the range defined by the

corresponding threshold registers.

ADC17-ALR = 0 when the analog input is not out of the

specified range.

ADC16-ALR = 1 when ADC16 is out of the range defined by the

corresponding threshold registers.

ADC16-ALR = 0 when the analog input is not out of the

specified range.

7.6.9.2 Alarm Status 1 Register (address = 0x71) [reset = 0x00]

Figure 96. Alarm Status 1 Register (R)

7

6

5

4

3

ALARMIN-ALR

R-0

2

1

0

Reserved

THERM-ALR

R-0

LT-HIGH-ALR

R-0

LT-LOW-ALR

R-0

R-All zeros

Table 44. Alarm Status 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R

All zeros

Reserved for factory use

3

ALARMIN-ALR

R

0

The ALARMIN-ALR is set to 1 if the ALARMIN pin is enabled

and set high.

2

THERM-ALR

R

0

Thermal alarm flag. When the die temperature is equal to or

greater than +150°C, the bit is set (1) and the THERM-ALR flag

activates. The on-chip temperature sensor (LT) monitors the die

temperature. If LT is disabled, the THERM-ALR bit is always 0.

The hysteresis of this alarm is 8°C.

1

0

LT-HIGH-ALR

LT-LOW-ALR

R

0

LT-HIGH-ALR = 1 when the temperature sensor is out of the

range defined by the upper threshold.

LT-LOW-ALR = 1 when the temperature sensor is out of the

range defined by the lower threshold.

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7.6.9.3 General Status Register (address = 0x72) [reset = 0x0C]

Figure 97. General Status Register (R)

7

AVSSD

—

6

AVSSC

—

5

AVSSB

—

4

AVSSA

—

3

2

1

0

ADC_IDLE

R-1

Reserved

R-1

GALR

R-0

DAVF

R-0

Table 45. General Status Register Field Descriptions

Bit

Field

Type

Reset

Description

7

AVSSD

—

This bit is the auto-range detection output for DAC group D. This

bit is set to 1 when AV_SSD< AV_SSTH(–10- to 0-V output range),

and 0 when A_VSSD> AV_SSTH(0- to 5-V output range).

6

5

4

3

AVSSC

AVSSB

AVSSA

—

1

This bit is the auto-range detection output for DAC group C. This

bit is set to 1 when AV_SSC< AV_SSTH(–10- to 0-V output range),

and 0 when AV_SSC> AV_SSTH(0- to 5-V output range).

This bit is the auto-range detection output for DAC group B. This

bit is set to 1 when AV_SSB< AV_SSTH(–10- to 0-V output range),

and 0 when AV_SSB> AV_SSTH(0- to 5-V output range).

This bit is the auto-range detection output for DAC group A. This

bit is set to 1 when AV_EE< AV_SSTH(–10- to 0-V output range),

and 0 when AV_EE> AV_SSTH(0- to 5-V output range).

ADC_IDLE

R

ADC Idle indicator.

Auto mode: 1 by default; goes to 0 once the ADC is

triggered and is running. Remains 0 until ADC is stopped,

then ADC_IDLE returns to 1.

Direct mode: 1 by default; goes to 0 once the ADC is

triggered and direct conversions are running and returns to

1 when direct mode conversions are completed.

2

1

Reserved

GALR

R

1

0

Reserved for factory use

Global alarm bit.

This bit is the OR function or all individual alarm bits of the

status register. This bit is set to 1 when any alarm condition

occurs and remains set until the status register is read. This bit

is cleared after reading the Status Register.

0

DAVF

R

0

ADC Data available flag bit. Direct mode only. Always cleared in

Auto mode.

0: ADC conversion is in progress or ADC is in Auto mode

1: ADC conversions are complete and new data is available

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7.6.10 GPIO: Address 0x7A

7.6.10.1 GPIO Register (address = 0x7A) [reset = 0xFF]

Figure 98. GPIO Register (R/W)

7

6

5

4

3

2

1

0

GPIO-7

R/W-1

GPIO-6

R/W-1

GPIO-5

R/W-1

GPIO-4

R/W-1

GPIO-3

R/W-1

GPIO-2

R/W-1

GPIO-1

R/W-1

GPIO-0

R/W-1

Table 46. GPIO Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

GPIO-7

GPIO-6

GPIO-5

GPIO-4

GPIO-3

GPIO-2

GPIO-1

GPIO-0

1

For write operation the GPIO pin operates as an output. Writing

a 1 to the GPIO-n bit sets the GPIO-N pin to high impedance.

Writing a 0 sets the GPIO-n pin to logic low.

6

5

For read operations the GPIO pin operates as an input. Read

the GPIO-n bit to receive the status of the GPIO-n pin.

4

3

The GPIO-n pin has 48-kΩ input impedance to IOV_DD

.

2

1

0

7.6.11 Out-Of-Range ADC Thresholds: Address 0x80 through 0x93

The unipolar analog inputs (LV_ADC16 to LV_ADC20) and the local temperature sensor implement an out-of-

range alarm function. The Upper-Thresh and Lower-Thresh registers define the upper bound and lower bounds

for these inputs. This window determines whether the analog input or temperature is out-of-range. When the

input is outside the window, the corresponding CH-ALR-n bit in the Status Register is set to 1. For normal

operation, the value of the upper threshold must be greater than the value of lower threshold; otherwise, an

alarm is always indicated. The analog input threshold values are specified in straight binary format while the local

temperature ones are specified in two’s complement format.

7.6.11.1 ADCn-Upper-Thresh (Low Byte) Register (address = 0x80 through 0x93) [reset = 0xFF]

Figure 99. ADCn-Upper-Thresh (Low Byte) Register (R/W)

7

6

5

4

3

2

1

0

THRUn(7:0)

R/W-All ones

Table 47. ADCn-Upper-Thresh (Low Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

THRUn(7:0)

R/W

All ones

Sets 12-bit upper threshold value for the ADC_n channel in

straight binary format.

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7.6.11.2 ADCn-Upper-Thresh (High Byte) Register (address = 0x80 through 0x93) [reset = 0x0F]

Figure 100. ADCn-Upper-Thresh (High Byte) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

THRUn(11:8)

R/W-0xF

R/W-All zeros

Table 48. ADCn-Upper-Thresh (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use.

3-0

THRUn(11:8)

R/W

0xF

Sets 12-bit upper threshold value for the ADC_n channel in

straight binary format.

7.6.11.3 ADCn-Lower-Thresh (Low Byte) Register (address = 0x80 through 0x93) [reset = 0x00]

Figure 101. ADCn-Lower-Thresh (Low Byte) Register (R/W)

7

6

5

4

3

2

1

0

THRLn(7:0)

R/W-All zeros

Table 49. ADCn-Lower-Thresh (Low Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

THRLn(7:0)

R/W

All zeros

Sets 12-bit lower threshold value for the ADC_n channel in

straight binary format.

7.6.11.4 ADCn-Lower-Thresh (High Byte) Register (address = 0x80 through 0x93) [reset = 0x00]

Figure 102. ADCn-Lower-Thresh (High Byte) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

THRLn(11:8)

R/W-All zeros

Table 50. ADCn-Lower-Thresh (High Byte) Register Field Descriptions Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use.

3-0

THRLn(11:8)

R/W

All zeros

Sets 12-bit lower threshold value for ADC_n channel in straight

binary format.

7.6.11.5 LT-Upper-Thresh (Low Byte) Register (address = 0x94) [reset = 0xFF]

Figure 103. LT-Upper-Thresh (Low Byte) Register (R/W)

7

6

5

4

3

2

1

0

THRU-LT(7:0)

R/W-All ones

Table 51. LT-Upper-Thresh (Low Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

THRU-LT(7:0)

R/W

All ones

Sets 12-bit upper threshold value for the local temperature

sensor in two’s complement format.

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7.6.11.6 LT-Upper-Thresh (High Byte) Register (address = 0x95) [reset = 0x07]

Figure 104. LT-Upper-Thresh (High Byte) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

THRU-LT(11:8)

R/W-0x7

R/W-All zeros

Table 52. LT-Upper-Thresh (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use.

3-0

THRU-LT(11:8)

R/W

0x7

Sets 12-bit upper threshold value for the local temperature

sensor in two’s complement format.

7.6.11.7 LT-Lower-Thresh (Low Byte) Register (address = 0x96) [reset = 0x00]

Figure 105. LT-Lower-Thresh (Low Byte) Register (R/W

7

6

5

4

3

2

1

0

THRL-LT(7:0)

R/W-All zeros

Table 53. LT-Lower-Thresh (Low Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

THRL-LT(7:0)

R/W

All zeros

Sets 12-bit lower threshold value for the local temperature

sensor in two’s complement format.

7.6.11.8 LT-Lower-Thresh (High Byte) Register (address = 0x97) [reset = 0x08]

Figure 106. LT-Lower-Thresh (High Byte) Register (R/W)

7

6

5

4

3

2

1

0

Reserved

THRL-LT(11:8)

R/W-0x8

R/W-All zeros

Table 54. LT-Lower-Thresh (High Byte) Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Reserved

R/W

All zeros

Reserved for factory use.

3-0

THRL-LT(11:8)

R/W

0x8

Sets 12-bit lower threshold value for the local temperature

sensor in two’s complement format.

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7.6.12 Alarm Hysteresis Configuration: Address 0xA0 and 0xA5

The hysteresis registers define the hysteresis in the out-of-range alarms.

7.6.12.1 ADCn-Hysteresis Register (address = 0xA0 through 0xA4) [reset = 0x08]

Figure 107. ADCn-Hysteresis Register (R/W)

7

6

5

4

3

2

1

0

Reserved

R/W-0

HYSTn(6:0)

R/W-0x08

Table 55. ADCn-Hysteresis Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Reserved

R/W

0

Reserved for factory use.

6-0

HYSTn(6:0)

R/W

0x08

Hysteresis of general purpose ADC_n, 1 LSB per step

7.6.12.2 LT-Hysteresis Register (address = 0xA5) [reset = 0x08]

Figure 108. LT-Hysteresis Register (R/W)

7

6

5

4

3

2

1

0

Reserved

R/W-All zeros

HYST-LT(4:0)

R/W-0x08

Table 56. LT-Hysteresis Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

Reserved

R/W

All zeros

Reserved for factory use.

4-0

HYST-LT(4:0)

R/W

0x08

Hysteresis of local temperature sensor, 1°C per step. The range

is 0°C to 31°C.

7.6.13 Clear and Power-Down Registers: Address 0xB0 through 0XB4

7.6.13.1 DAC Clear 0 Register (address = 0xB0) [reset = 0x00]

Figure 109. DAC Clear 0 Register (R/W)

7

6

5

4

3

2

1

0

CLR-B7

R/W-0

CLR-B6

R/W-0

CLR-B5

R/W-0

CLR-B4

R/W-0

CLR-A3

R/W-0

CLR-A2

R/W-0

CLR-A1

R/W-0

CLR-A0

R/W-0

Table 57. DAC Clear 0 Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

CLR-B7

CLR-B6

CLR-B5

CLR-B4

CLR-A3

CLR-A2

CLR-A1

CLR-A0

0

This register uses software to force the DAC into a clear state.

If CLRn = 1, DAC_n is forced into a clear state.

6

5

If CLRn = 0, DAC_n is restored to normal operation.

4

3

2

1

0

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7.6.13.2 DAC Clear 1 Register (address = 0xB1) [reset = 0x00]

Figure 110. DAC Clear 1 Register (R/W)

7

6

5

4

3

2

1

0

CLR-D15

R/W-0

CLR-D14

R/W-0

CLR-D13

R/W-0

CLR-D12

R/W-0

CLR-C11

R/W-0

CLR-C10

R/W-0

CLR-C9

R/W-0

CLR-C8

R/W-0

Table 58. DAC Clear 1 Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

CLR-D15

CLR-D14

CLR-D13

CLR-D12

CLR-C11

CLR-C10

CLR-C9

0

This register uses software to force the DAC into a clear state.

If CLRn = 1, DAC_n is forced into a clear state.

6

5

If CLRn = 0, DAC_n is restored to normal operation.

4

3

2

1

0

CLR-C8

7.6.13.3 Power-Down 0 Register (address = 0xB2) [reset = 0x00]

Figure 111. Power-Down 0 Register (R/W)

7

6

5

4

3

2

1

0

PDAC-B7

R/W-0

PDAC-B6

R/W-0

PDAC-B5

R/W-0

PDAC-B4

R/W-0

PDAC-A3

R/W-0

PDAC-A2

R/W-0

PDAC-A1

R/W-0

PDAC-A0

R/W-0

Table 59. Power-Down 0 Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

PDAC-B7

PDAC-B6

PDAC-B5

PDAC-B4

PDAC-A3

PDAC-A2

PDAC-A1

PDAC-A0

0

After power-on or reset, all bits in the power-down register are

cleared to 0, and all the components controlled by this register

are either powered-down or off. The power-down register allows

the host to manage the AMC7836 power dissipation. When not

required, any of the DACs can be put into clamp mode and the

ADC and internal reference into an inactive low-power mode to

reduce current drain from the supply. The bits in the power-down

register control this power-down function. Set the respective bit

to 1 to activate the corresponding function.

6

5

4

3

2

1

0

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7.6.13.4 Power-Down 1 Register (address = 0xB3) [reset = 0x00]

Figure 112. Power-Down 1 Register (R/W)

7

6

5

4

3

2

1

0

PDAC-D15

R/W-0

PDAC-D14

R/W-0

PDAC-D13

R/W-0

PDAC-D12

R/W-0

PDAC-C11

R/W-0

PDAC-C10

R/W-0

PDAC-C9

R/W-0

PDAC-C8

R/W-0

Table 60. Power-Down 1 Register Field Descriptions

Bit

7

Field

PDAC-D15

Type

R/W

Reset

Description

0

After power-on or reset, all bits in the power-down register are

cleared to 0, and all the components controlled by this register

are either powered-down or off. The power-down register allows

the host to manage the AMC7836 power dissipation. When not

required, any of the DACs can be put into clamp mode and the

ADC and internal reference into an inactive low-power mode to

reduce current drain from the supply. The bits in the power-down

register control this power-down function. Set the respective bit

to 1 to activate the corresponding function.

6

PDAC-D14

PDAC-D13

PDAC-D12

PDAC-C11

PDAC-C10

PDAC-C9

PDAC-C8

5

4

3

2

1

0

7.6.13.5 Power-Down 2 Register (address = 0xB4) [reset = 0x00]

Figure 113. Power-Down 2 Register (R/W)

7

6

5

4

3

2

1

0

Reserved

PREF

R/W-0

PADC

R/W-0

R/W-All zeros

Table 61. Power-Down 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

Reserved

R/W

All zeros

Reserved for factory use.

1

0

PREF

PADC

R/W

0

After power-on or reset, all bits in the power-down register are

cleared to 0, and all the components controlled by this register

are either powered-down or off. The power-down register allows

the host to manage the AMC7836 power dissipation. When not

required, any of the DACs can be put into clamp mode and the

ADC and internal reference into an inactive low-power mode to

reduce current drain from the supply. The bits in the power-down

register control this power-down function. Set the respective bit

to 1 to activate the corresponding function.

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7.6.14 ADC Trigger: Address 0xC0

7.6.14.1 ADC Trigger Register (address = 0xC0) [reset = 0x00]

Figure 114. ADC Trigger Register (R/W)

7

6

5

4

3

2

1

0

Reserved

ICONV

R/W-0

R/W-All zeros

Table 62. ADC Trigger Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Reserved

R/W

All zeros

Reserved for factory use

Internal ADC conversion bit.

0

ICONV

R/W

0

Set this bit to 1 to start the ADC conversion internally. The bit is

automatically cleared to 0 after the ADC conversion starts.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The AMC7836 device is a highly integrated, low-power, analog monitoring and control solution that includes a

21-channel (12-bit) ADC, 16-channel (12-bit) DACs, eight GPIO, and a local temperature sensor. Although the

device can be used in many different closed-loop systems, including industrial control and test and

measurement, the device is largely used as a power amplifier controller in multi-channel RF communication

applications.

Power amplifiers (PAs) include transistor technologies that are extremely temperature sensitive, and require DC

biasing circuits to optimize RF performance, power efficiency, and stability. The AMC7836 device provides 16

DAC channels which can be used to adjust the power amplifier bias points in response to temperature changes.

The device also includes an internal local temperature sensor, and 21 ADC channels for general-purpose

monitoring.

Current and temperature sensing are typically implemented in power amplifier controller applications. PA drain

current sensing is implemented by measuring the differential voltage drop across a shunt resistor. Temperature

variations during PA operation can be detected either through the AMC7836 internal temperature sensor or

through remote temperature ICs or thermistors configured to interface with the ADC analog inputs available in

the device. 图 115 shows the block diagram for these different systems.

AMC7836

GPIO

MUX

ADC

Local

Temperature

Sensor

DAC

Current

Sense

Amplifier

Power

∆V

R_(shunt)

Power

Amplifier

Power

Amplifier

RF IN

Temperature

Sensor

Heat Sink

Current Sensing

Temperature Sensing

图 115. AMC7836 Example Control and Monitor System

71

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Application Information (接下页)

8.1.1 Temperature Sensing Applications

The AMC7836 device contains one local temperature and five unipolar analog inputs that are easily configurable

to interface with remote temperature-sensor circuits. The integrated temperature sensor and analog input

registers automatically update with every conversion. 图 116 shows an example of a remote temperature sensor

connection.

The selected temperature sensor is the LM50 device, a high precision integrated-circuit temperature sensor that

operates in the –40°C to 125°C temperature range using a single positive supply. The full-scale output of the

temperature sensor ranges from 100 mV to 1.75 V for the operational temperature range. In an extremely noisy

environment, additional filtering is recommended. A typical value for the bypass capacitor is 0.1 µF from the V+

pin to GND. A high-quality ceramic type NP0 or X7R is recommended because of optimal performance across

temperature and very low dissipation factor.

LM50

DV

DD

4

3

1

V⁺

LV_ADC15

VO

NC

0.1 µF

GND

5

2

图 116. Temperature Sensing Application With LM50

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Application Information (接下页)

8.1.2 Current Sensing Applications

In applications that require current sensing of the power amplifier, an external high-side current sense amplifier

can be added and configured to the unipolar ADC inputs. 图 117 shows this design.

The LMP8480 device is a precision current sense device that amplifies the small differential voltage developed

across a current-sense resistor in the presence of high input common-mode voltages. The LMP8480 device

accepts input signals with a common-mode voltage range from 4 V to 76 V with a bandwidth of 270 kHz. The

LMP8480 device offers different fixed gain settings. The optimal gain setting is dependent on the accuracy

requirement of the application. To maintain precision over temperature, the output of the LMP8480 device should

be directly connected to the AMC7836 unipolar ADC inputs. If the output range of the LMP8480 device is scaled

by a voltage divider, as shown in 图 117, an output amplifier may be required to drive the ADC unipolar input to

ensure a low impedance source. If the series resistance, in this case R4, is low enough then the buffer may not

be required because the LMP8480 device is capable of driving the input of the AMC7836 unipolar ADC channel.

注

The external resistors will cause some small error because of temperature drift and the

input bias current of the operation amplifier.

图 117 also shows a simple method to ensure proper power sequencing of the power amplifier by adding a

series PMOS transistor to the PA drain terminal. The activation of the PMOS transistor connects the PAV_DD

voltage supply to the drain pin of the power amplifier. The PMOS transistor is driven with a voltage divider that

swings from the PAV_DDvoltage to PAV_DD× (R2 / (R1 + R2)). The NMOS shown in 图 117 is connected to a

microcontroller output that controls the state of the PMOS transistor.

PAV

DD

+

R4

ADC Input

VOUT

NC

V

CC

R3

RSP

RSN

R1

R

(SENSE)

GND

LMP8480

R2

Drain

Gate

PA

DAC Voltage

mC GPIO

Source

图 117. Current-Sense Application With PMOS ON and OFF

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8.2 Typical Application

图 118 shows an example schematic incorporating the AMC7836 device.

DAC OUTPUTS connect to the gate (V_G) of the PA modules

0.1 µF

AV_EE

AV_CC

AV_DD

0.1 µF

DV_DD

0.1 µF

IOV_DD

VDD

IOV_DD

0.1 µF

64

63

62

61 60

59 58 57

56 55 54 53

52 51

50 49

4.7 µF

48

AGND2

1

IOV_DD

2

RESET

MISO

RESET

SDO

3

4

5

MOSI

SDI

47

46

45

44

43

42

41

40

39

38

37

36

35

34

ADC_0

ADC_1

ADC_2

ADC_3

SCLK

CS

SCLK

CS

6

7

GPIO0 (ALARMIN)

8

9

GPIO1 (ALARMOUT)

ADC_4

ADC_5

GPIO2 (ADCTRIG)

GPIO3 (DAV)

GPIO4

10

AMC7836

GPIO

11

12

ADC_6

ADC_7

GPIO5

GPIO6

GPIO7

13

14

LV_ADC16

LV_ADC17

Unipolar

Monitor Connection

LV_ADC16 œ

LV_ADC18

LV_ADC19

LV_ADC20

ADC_8

GND

33

ADC_9

15

16

DAC_A0

DAC_A1

Bipolar ADC inputs

connected to

PA module gate for

voltage monitoring

0 ꢀ

AV_EE

22 23

25

26

17

18 19 20

21

24

29

27 28

30 31 32

AV_EE

0.1 µF

Analog

GND

Digital

GND

AV_CC

DAC OUTPUTS connect to the gate (V_G) of the PA modules

图 118. AMC7836 Example Schematic

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Typical Application (接下页)

8.2.1 Design Requirements

The AMC7836 example schematic uses the majority of the design parameters listed in 表 63.

表 63. Design Parameters

DESIGN PARAMETER

AV_CC

EXAMPLE VALUE

5 V

AV_EE

–12 V

IOV_DD

3.3 V

DV_DD

5 V

AV_DD

5 V

AV_SSbanks

ADC bipolar inputs

ADC unipolar inputs

DAC outputs

AV_EE

ADC[0-15]: –12.5 to 12.5 V input range

LV_ADC[16-20]: 0 to 5 V range

Sixteen Monotonic 12-bit DACs

Selectable ranges: 0 to 5 V, 0 to 10 V, –10 to 0 V or –5 to 0 V

Remote temperature sensing

IC temperature sensor (LM50) or thermistor

8.2.2 Detailed Design Procedure

Use the following parameters to facilitate the design process:

•

AV_CCand AV_EEvoltage values

ADC input voltage range

DAC Output voltage Ranges

8.2.2.1 ADC Input Conditioning

The AMC7836 device has an ADC with 21 analog inputs for external voltage sensing. Sixteen of these inputs are

bipolar and the other five are unipolar. The bipolar inputs (ADC_0 through ADC_15) range is –12.5 to 12.5 V,

and the unipolar analog inputs (LV_ADC16 through LV_ADC20) range is 0 to 2 × V_ref. The ADC operates from

an internal 2.5 V reference (V_ref, measured at the REF_CMP pin). For additional noise filtering, a 4.7-µF

capacitor should be connected between the REF_CMP and AGND2 pins. A high-quality ceramic type NP0 or

X7R is recommended because of the optimal performance of the capacitor across temperature and very-low

dissipation factor.

The ADC timing signals are driven from an on-chip temperature compensated 4-MHz oscillator. The on-chip

oscillator is primarily responsible for the sampling frequency of the ADC. The sampling frequency of the ADC is

dynamic and dependent on the acquisition and conversion time of each channel. 表 64 lists the relationship

between the total update time and the internal oscillator frequency.

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表 64. ADC Conversion Rate and Total Update Number of Clocks

t_S(ACQUISITION +

CONVERSION)

NUMBER OF CLOCKS

ADC CONVERSION

RATE

ADC INPUT CHANNEL

ACQUISITION CLOCKS CONVERSION CLOCKS

Bipolar

124.5

32.5

13.5

138

46

Unipolar

00

01

10

11

Internal Temperature

Sensor

—

1025

Bipolar

124.5

78.5

13.5

138

92

Unipolar

Internal Temperature

Sensor

—

1025

Bipolar

124.5

13.5

138

Unipolar

Internal Temperature

Sensor

—

1025

Bipolar

262.5

13.5

276

Unipolar

Internal Temperature

Sensor

—

1025

The minimum and maximum oscillator frequency specifications in conjunction with the number of clocks required

for the unipolar, bipolar and temperature sensor inputs should be applied to 公式 5 to calculate the total update

time range.

(B_CLKì #B_CH+ U_CLKì #U_CH+ T_CLKì #T_CH

)

T_S=

ƒ_OSC

where

•

T_Sis the total update time

B_CLKis the total bipolar clocks

#B_CHis the number of active bipolar inputs

U_CLKis the total unipolar clocks

#U_CHis the number of active unipolar inputs

T_CKLis the total internal temperature-sensor clocks

#T_CHis the number of active internal temperature sensor channels; either 1 or 0

ƒ_OSCis the internal oscillator frequency

(5)

The following is an example of a complete calculation of the total update time range. In this example, the ADC

conversion rate is set to 00 and the following ADC input channels are used:

•

Bipolar channels: ADC_1 through ADC_5 (5 active bipolar channels)

Unipolar channels: LV_ADC16 through LV_ADC18 (3 active unipolar channels)

Internal temperature sensor (1 active temperature channel)

表 64 gives the total number of clocks required for each ADC input under the example conditions.

For the minimum specified oscillator frequency of 3.7 MHz, and with the ADC conversion rate set to 00, use 公式

6 to calculate the total maximum update time for this example.

(138 ì 5 + 46 ì 3 +1025 ì 1)

T_S=

=500.811µs

3.7 MHz

(6)

For the maximum specified oscillator frequency of 4.3 MHz, use 公式 7 to calculate the total minimum update

time for this example.

(138 ì 5 + 46 ì 3 +1025 ì 1)

T_S=

=430.93 µs

4.3 MHz

(7)

Therefore, the total update time range is 430.93 µs to 500.811 µs.

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

During the conversion, the input current per channel varies with the total update time which is determined by the

number and type of channels (NCH) and the conversion rate setting of the CONV-RATE bit in the ADC

configuration register (address 0x10).

注

The source of the analog input voltage must be able to charge the input capacitance to a

12-bit settling level within the acquisition time.

8.2.2.2 DAC Output Range Selection

The AMC7836 device includes 16 DACs split into four groups, each with four DACs. All of the DACs in a given

group share the same output voltage range. The output range for each DAC group is independent and is

programmable to either –10 to 0 V, –5 to 0 V, 0 to 10 V or 0 to 5 V. The DAC output ranges are configured by

following the configuration settings listed in Table 1.

Each DAC includes an output buffer is capable of generating rail-to rail voltages. The Electrical Characteristics:

DAC table lists the maximum source and sink capability of this internal amplifier. The graphs in the Application

Curves section show the relationship of both stability and settling time with different capacitive loading structures.

8.2.3 Application Curves

15

10

5

15

10

5

10nF, Rising Edge

200pF, Rising Edge

10nF, Falling Edge

200pF, Falling Edge

0

-5

-10

-15

-10

-15

0

5

10

15

Time (µs)

20

25

0

5

10

15

Time (µs)

20

25

C001

Code 0x400 to 0xC00 to within ½ LSB

Code 0xC00 to 0x400 to within ½ LSB

图 119. DAC Settling Time vs Load Capacitance

图 120. DAC Settling Time vs Load Capacitance

9 Power Supply Recommendations

The preferred (not required) pin order for applying power is IOV_DD, DV_DDand AV_DD, AV_CCand lastly AV_EE

,

AV_SSB, AV_SSC, and AV_SSD.When power sequencing, ensure that all digital pins are not powered or in an active

state while the IOV_DDpin ramps. Proper sequencing of the digital pins can be accomplished by attaching 10-kΩ

pullup resistors to the IOV_DDpin, or pulldown resistors to the DGND pin. See the supply voltage ranges in the

Recommended Operating Conditions table.

In applications where a negative voltage is applied to AV_EE, AV_SSB, AV_SSC, and AV_SSDfirst, the user may notice

some small negative voltages at other supply pins, such as the AV_DD, DV_DD, and AV_CCpins. The negative

voltages at the supply pins may exceed the values listed in the Absolute Maximum Ratings table, but because

these voltages are created from intrinsic circuitry, the voltage levels are safe for operation.

In the case where all DAC outputs are in clamp state with AVEE = AVSSB = AVSSC = AVSSD = –12 V, the

negative voltage observed on the other supply pins can be as low as –620 mV.

Although these negative voltages are observed on the pins, the user must still adhere to the guidelines specified

in the Absolute Maximum Ratings table and verify that the inputs are driven within the range specified in the

table. The user should also ensure that current is only applied when operating with voltages between the ranges

listed in the Absolute Maximum Ratings table.

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In applications where the DAC channels are driving a large capacitive load and the output changes significantly

(a full scale transition, for instance), the output current of the affected channels may drive to the short circuit

current value as described in the specification table (see 表 64) while the capacitive load is being charged. This

temporary increase in output current may inadvertently cause the AVCC or AVSS to collapse, potentially

resulting in a POR event. It is recommended that the power supply solution for AVCC and AVSS be capable of

supplying short circuit current for all DAC channels with capacitive loads simultaneously to ensure proper device

performance.

9.1 Device Reset Options

9.1.1 Power-on-Reset (POR)

The AMC7836 device includes a power-on reset (POR) function. After all supplies have been established, a POR

event is issued. The POR causes all registers to initialize to the default values, and communication with the

device is valid only after a 250 µs power-on reset delay.

The default operation is power-down mode (register 0x02) in which the device is non-operational except for the

communication interface as determined by the power-down registers. Before enabling normal operation, a

hardware reset should be issued.

A power failure on DV_DD, AV_DD, AV_CCor IOV_DDhas the potential to initiate a power-on-reset event. As long as

DV_DD, AV_DD, AV_CC, and IOV_DDremain above the minimum recommended operating conditions a power failure

event will not occur. When any of these supplies drops below the minimum recommended operating condition

the device may or may not imitate a POR. In this case, issuing a hardware reset or proper POR is recommended

to resume proper operation. To ensure a proper POR event, the DV_DDsupply must fall below 750 mV. If the

DV_DDsupply falls below 2.7 V a hardware reset or proper POR must be issued.

9.1.2 Hardware Reset

A device hardware reset event is initiated by a minimum 20-ns logic low on the RESET pin. A hardware reset

causes all registers to initialize to the default values and communication with the device is valid only after a 250-

µs reset delay.

9.1.2.1 Software Reset

A software reset event is initiated by setting the SOFT-RESET bit in the interface configuration 0 register (0x00).

A software reset causes all registers, except 0x00 and 0x01, to initialize to the default values and communication

with the device is valid only after a 100-ns delay.

10 Layout

10.1 Layout Guidelines

•

All power supply pins should be bypassed to ground with a low-ESR ceramic bypass capacitor. The typical

recommended bypass capacitor has a value of 10-µF and is ceramic with a X7R or NP0 dielectric.

To minimize interaction between the analog and digital return currents, the digital and analog sections should

have separate ground planes that eventually connect at some point.

To reduce noise on the internal reference, a 4.7-µF capacitor is recommended between the REF_CMP pin

and ground.

A high-quality ceramic type NP0 or X7R capacitor is recommended because of the optimal performance

across temperature very-low dissipation factor of the capacitor.

The digital and analog sections should have proper placement with respect to the digital pins and analog pins

of the AMC7836 device (see 图 122). The separation of analog and digital blocks allows for better design and

practice as it ensures less coupling into neighboring blocks and minimizes the interaction between analog and

digital return currents.

78

AMC7836

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ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

10.2 Layout Example

Bypass Capacitor

close to supply pins: DV

Bypass Capacitor

,

DD

close to AV

0.1 µF

CC

AV , AV and AV

SS

DD

0.1 µF

4.7 µF

Compensation Capacitor

close to REF_CMP pin and

connect to AGND2

0.1 µF

AGND2

IOV

DD

1

48

RESET

ADC_0

ADC_1

ADC_2

ADC_3

ADC_4

2

3

47

46

SDO

SDI

4

5

45

44

SCLK

CS

6

7

43

42

ADC_5

GPIO0/ALARMIN

ADC_6

8

9

41

40

GPIO1/ALARMOUT

GPIO2/ADCTRIG

GPIO3/DAV

GPIO4

ADC_7

LV_ADC16

10

11

39

38

LV_ADC17

LV_ADC18

GPIO5

12

13

37

36

GPIO6

LV_ADC19

LV_ADC20

GPIO7

14

15

35

34

DAC_A0

ADC_8

ADC_9

DAC_A1

16

33

0.1 µF

Bypass Capacitor

close to AV , AV

,

EE

CC

and AV

SS

图 121. AMC7836 Example Board Layout

1

48

2

3

47

46

4

5

45

44

6

7

43

42

8

9

41

40

10

11

39

38

12

13

37

36

14

15

35

34

16

33

图 122. AMC7836 Example Board Layout — Component Placement

79

AMC7836

ZHCSDC6D –NOVEMBER 2014–REVISED FEBRUARY 2018

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

如需相关文档，请参阅：

•

《LMP8480/LMP8481 具有电压输出的高精度 76V 高侧电流感测放大器》，SNVS829

《LM50/LM50-Q1 SOT-23 单电源摄氏温度传感器》，SNIS118

11.2 接收文档更新通知

要接收文档更新通知，请导航至 Ti.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

80

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC7836IPAPR

HTQFP

PAP

64

1000

330.0

24.4

13.0

1.5

16.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTQFP PAP 64

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 55.0

AMC7836IPAPR

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

AMC7836IPAP

PAP

HTQFP

64

160

8 X 20

150

322.6 135.9 7620 15.2

13.1

13

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PAP 64

10 x 10, 0.5 mm pitch

HTQFP - 1.2 mm max height

QUAD FLATPACK

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226442/A

www.ti.com

PACKAGE OUTLINE

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

SCALE 1.300

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

16

33

17

32

A

0.27

64X

60X 0.5

0.17

0.08

C A B

4X 7.5

C

SEATING PLANE

1.2 MAX

(0.127)

TYP

SEE DETAIL A

17

32

0.25

GAGE PLANE

(1)

33

16

0.15

0.05

0.08 C

0 -7

0.75

0.45

65

7.00

5.99

DETAIL A

A

17

TYPICAL

1

48

49

64

4218924/A 01/2022

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs.

4. Strap features may not be present.

5. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

8)

NOTE 8

(

7)

SYMM

SOLDER MASK

49

64

DEFINED PAD

64X (1.5)

(R0.05)

TYP

1

48

64X (0.3)

65

(11.4)

SYMM

(1.3 TYP)

60X (0.5)

33

16

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

17

32

SEE DETAILS

(1.3 TYP)

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218924/A 01/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,

plugged or tented.

10. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

7)

BASED ON 0.125

THICK STENCIL

SYMM

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

64

49

64X (1.5)

1

48

64X (0.3)

(R0.05) TYP

SYMM

65

(11.4)

60X (0.5)

33

16

METAL COVERED

BY SOLDER MASK

17

32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

7.83 X 7.83

7.0 X 7.0 (SHOWN)

6.39 X 6.39

0.125

0.15

0.175

5.92 X 5.92

4218924/A 01/2022

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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型号：	AMC7836
厂家：	TEXAS INSTRUMENTS
描述：	高密度、12 位模拟监视和控制解决方案，双极 DAC
文件：	总90页 (文件大小：4285K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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