AMC7891_14 [TI]
Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs;
| 型号： | AMC7891_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Analog Monitor and Control Circuit with 10-Bit, Multi-Channel ADC and Four DACs, Temperature Sensor, and 12 GPIOs |
| 文件： | 总41页 (文件大小：934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC7891
www.ti.com
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
Analog Monitor and Control Circuit
with 10-Bit, Multi-Channel ADC and Four DACs, Temperature
Sensor, and 12 GPIOs
Check for Samples: AMC7891
1
FEATURES
APPLICATIONS
23
•
10-Bit, 500-kSPS SAR ADC:
•
•
•
•
Cellular Base Stations
–
–
8 External Analog Inputs
RF Communication Systems
Optical Networks
VREF, 2 × VREF Input Ranges
•
Four 10-Bit Monotonic DACs:
General-Purpose Monitor and Control
–
–
–
0 to 5-V Output Range
DESCRIPTION
The AMC7891 is a highly-integrated, low-power,
complete analog monitoring and control system in a
very small package.
Up to 10-mA Sink and Source Capability
Power-On Reset to 0 V
•
•
Internal 2.5-V Reference
Internal Temperature Sensor:
For monitoring functions, the AMC7891 has
8
–
–
–40°C to +125°C Operation
Accuracy of ±2.5°C
uncommitted inputs multiplexed into a 10-bit SAR
analog-to-digital converter (ADC) and an accurate
on-chip temperature sensor. Control signals are
generated through four, independent, 10-bit
digital-to-analog converters (DACs). Additional digital
signal monitoring and control is accomplished through
twelve configurable GPIOs. An internal reference can
be used to drive the ADC and DACs.
•
•
12 General-Purpose I/O Ports:
1.8-V to 5.5-V Operation
Low-Power SPI™-Compatible Serial Interface:
–
–
–
4-Wire Mode, 1.8-V to 5.5-V Operation
SCLK up to 30 MHz
Communication to the device is performed through a
versatile, four-wire serial interface compatible with
•
•
Temperature Range: –40°C to +105°C
Low Power: 32.5 mW at 5 V, Full Operating
Conditions
industry-standard
microprocessors
and
microcontrollers. The serial interface can operate at
clock rates up to 30 MHz, allowing quick access to
critical system data.
•
Space-Saving Package: 36-pin,
6-mm x 6-mm QFN
The device is characterized for operation over the
temperature range of –40ºC to 105ºC and is available
in a very small, 36-pin, 6-mm x 6-mm QFN package.
AMC7891
2.5-V Reference
DAC
The AMC7891’s low power, small size and
high-integration make it an ideal low-cost, bias control
circuit for modern RF transistor modules such as the
power amplifiers (PA) and low-noise amplifiers (LNA)
found in RF communication systems. The AMC7891
feature set is similarly beneficial in general purpose
monitor and control systems.
MUX
ADC
DAC
DAC
DAC
TEMP
SENSOR
For applications that require a different channel
count, additional features, or converter resolutions,
Texas Instruments offers a complete family of Analog
Monitor and Control (AMC) Products. See
http://www.ti.com/amc.
GPIO Control
12 GPIOs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
RHH PACKAGE
QFN-36
(TOP VIEW)
36 35 34 33 32 31 30 29 28
AVDD
1
2
3
4
5
6
7
8
9
27 GPIOA0
26 GPIOA1
25 GPIOA2
24 GPIOA3
AGND1
DGND
GPIOVDD
SPIVDD
23
GPIOB0
22 GPIOB1
21 GPIOB2
20 GPIOB3
19 DAV
CS
SCLK
SDI
SDO
10 11 12 13 14 15 16 17 18
AMC7891 Pin Functions
PIN
NAME
AVDD
I/O
DESCRIPTION
NO.
1
I
I
Analog supply voltage. (4.75 V to 5.5 V)
2
AGND1
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and
AGND2 to the same potential, AGND.
3
4
5
DGND
I
I
I
Digital ground. Ground reference point for all digital circuitry on the device. Ideally, AGND and DGND should
be at the same potential and must not differ by more than 0.3 V.
GPIOVDD
SPIVDD
GPIO supply voltage. (1.8 V to 5.5 V)
Sets the GPIO operating voltage and threshold levels.
Serial interface supply voltage. (1.8 V to 5.5 V)
Sets the serial interface operating voltage and threshold levels.
6
CS
I
Active low serial data enable. Schmitt-trigger logic input.
This input is the frame synchronization signal for the serial data. When this signal goes low, it enables the
input shift register and data is sampled on subsequent falling clock edges. The DAC output and register
settings update following the 24th clock. If CS goes high before the 23th clock edge, the command is
ignored.
7
8
SCLK
SDI
I
Serial interface clock. Schmitt-trigger logic input.
Maximum SCLK rate is 30MHz.
I
Serial interface data input. Schmitt-trigger logic input.
Data is clocked into the input shift register on each falling edge of SCLK.
9
SDO
O
O
Serial interface data output. The SDO pin is in high impedance when CS is high.
Data is clocked out of the input shift register on each rising edge of SCLK.
10
DACOUT3
DAC3 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
2
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AMC7891
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SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
AMC7891 Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
11
DACOUT2
O
DAC2 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
12
13
14
DACOUT1
DACOUT0
AGND2
O
O
I
DAC1 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
DAC0 buffered output. (0 V to AVDD).
Can source/sink up to 10 mA.
Analog ground. Ground reference point for all analog circuitry on the device, AGND. Connect AGND1 and
AGND2 to the same potential, AGND.
15
16
17
18
19
GPIOC3
GPIOC2
GPIOC1
GPIOC0
DAV
I/O
I/O
I/O
I/O
O
General purpose digital I/O C3. Maximum voltage is set by GPIOVDD
General purpose digital I/O C2. Maximum voltage is set by GPIOVDD
General purpose digital I/O C1. Maximum voltage is set by GPIOVDD
General purpose digital I/O C0. Maximum voltage is set by GPIOVDD
ADC data available indicator. Open-drain, active low output.
In direct-mode, DAV goes low when an ADC conversion cycle finishes. In auto-mode a 1µs pulse appears
on this pin when the conversion cycle finishes (see ADC Operation for details). DAV stays high when
deactivated. If used, an external 10 kΩ pull-up resistor to GPIOVDD is required. If unused, the pin can be
connected to DGND.
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
AIN0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O B3. Maximum voltage is set by GPIOVDD
General purpose digital I/O B2. Maximum voltage is set by GPIOVDD
General purpose digital I/O B1. Maximum voltage is set by GPIOVDD
General purpose digital I/O B1. Maximum voltage is set by GPIOVDD
General purpose digital I/O A3. Maximum voltage is set by GPIOVDD
General purpose digital I/O A2. Maximum voltage is set by GPIOVDD
General purpose digital I/O A1. Maximum voltage is set by GPIOVDD
General purpose digital I/O A1. Maximum voltage is set by GPIOVDD
Uncommitted analog input 0. (0 V to 5 V)
AIN1
I
Uncommitted analog input 1. (0 V to 5 V)
AIN2
I
Uncommitted analog input 2. (0 V to 5 V)
AIN3
I
Uncommitted analog input 3. (0 V to 5 V)
AIN4
I
Uncommitted analog input 4. (0 V to 5 V)
AIN5
I
Uncommitted analog input 5. (0 V to 5 V)
AIN6
I
Uncommitted analog input 6. (0 V to 5 V)
AIN7
I
Uncommitted analog input 7. (0 V to 5 V)
REF
I/O
Used as external ADC reference input when the internal reference buffer is disabled in register AMC_power,
ref_on = ‘0’ (default). A decoupling capacitor is recommended between the external reference output an
AGND for noise filtering.
Used as internal reference output when the internal reference buffer is enabled in register AMC_power,
ref_on = ‘1’. Requires a 4.7 µF decoupling capacitor to AGND when used as reference output. An external
buffer amplifier with high impedance input is required to drive an external load.
–
THERMAL
PAD
–
The thermal pad is located on the package underside. Connect to the board ground plane using multiple
vias.
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AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
AMC7891
Internal Reference
(2.5V)
REF
ref_on
AIN0
AIN1
AIN2
AIN3
AIN4
DAC0
10-Bit
DACOUT0
DACOUT1
DACOUT2
DACOUT3
10-Bit
ADC
dac0_clear
dac1_clear
dac2_clear
dac3_clear
DAC1
10-Bit
AIN5
AIN6
AIN7
Temperature
Sensor
DAC2
10-Bit
Configuration
Registers
DAV
DAC3
10-Bit
CS
SCLK
SDI
AVDD
SDO
GPIOVDD
SPIVDD
GPIO Control
4
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Product Folder Link(s): AMC7891
AMC7891
www.ti.com
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
ORDERING INFORMATION(1)
PACKAGE
TRANSPORT
QUANTITY
MEDIA
TA
–40°C to 105°C
ORDER CODE
DRAWING/TYPE(2)(3)
AMC7891SRHHT
AMC7891SRHHR
250
RHH / 36-QFN Quad Flatpack No-Lead
Tape and Reel
2000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
(2) Thermal Pad Size: 4.39 mm x 4.39 mm
(3) MSL Peak Temperature: Level-3-260C-168 HR
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
6
AVDD to AGND(2)
V
V
GPIOVDD to DGND
6
Supply voltage range
Pin voltage range
SPIVDD to DGND
6
V
AGND to DGND
0.3
V
AIN[0:7], DACOUT[0:3], REF to AGND
CS, SCLK, SDI to DGND
SDO to DGND
AVDD + 0.3
V
6
V
SPIVDD + 0.3
V
GPIOA[0:3], GPIOB[0:3], GPIOC[0:3] to DGND
GPIOVDD + 0.3
V
DAV to DGND
6
V
(3) (4)
Operating free-air temperature range, TA: AMC7891
Storage temperature range
105
150
2.5
1.0
°C
°C
kV
kV
–40
Human body model (HBM)
ESD ratings:
Charged device model (CDM)
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
(2) AGND1 and AGND2 must be tied together as AGND.
(3) Air flow or heat sinking reduces θJA and may be required for sustained operation at 105°C and maximum operating conditions.
(4) Soldering the device thermal pad to the board ground plane is strongly recommended.
THERMAL INFORMATION
AMC7891
THERMAL METRIC(1)
RHH PACKAGE
UNITS
36 PINS
30.6
16.0
5.3
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.3
θJCbot
0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
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AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
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ELECTRICAL CHARACTERISTICS (DAC SPECIFICATIONS)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD
,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
STATIC ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
Bits
LSB
LSB
mV
INL
Relative accuracy
±0.05
±0.1
±0.5
±0.025
±1
±1
±1
±5
DNL Differential nonlinearity
Offset error
Specified monotonic
Code 0x008
Gain error
±0.2 %FSR
ppm/°C
Offset temperature coefficient
Gain temperature coefficient
±1
ppm/°C
(1)
DAC OUTPUT
Full scale output voltage range
0
AVDD
V
Transition: Code 0x008 to 0x3F8 to within 1/2 LSB,
CL = 2 nF, RL = ∞
Output voltage settling time
5
µs
Slew rate
2
±30
±10
V/µs
mA
Short circuit current
Load current
Full-scale current shorted to ground or pulled to AVDD
Source and/or sink within 300 mV of supply
RL = ∞
mA
Capacitive load stability
DC output impedance
Power-on overshoot
Glitch energy
10
nF
1
10
Ω
AVDD 0 to 5 V, 2 ms ramp
mV
Transition: Code 0x1FF to 0x200; 0x200 to 0x1FF
TA = 25°C, 1 kHz
0.15
260
20
nV-s
nV/√Hz
µVPP
Output noise
Integrated noise from 0.1 Hz to 10 Hz
(1) Specified by design and characterization. Not tested during production.
6
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SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS – (ADC SPECIFICATIONS)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD
,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
DC ACCURACY
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resolution
10
Bits
INL
Integral nonlinearity
Differential nonlinearity
Offset error
±0.1
±0.1
±0.5
±0.4
±0.5
±0.4
±1
±1
±2
LSB
LSB
LSB
LSB
LSB
LSB
DNL
Specified monotonic
Offset error match
Gain error
±2
Gain error match
CONVERSION TIME
ADC conversion rate
500
16
kSPS
Autocycle update rate
Throughput rate
All 8 ADC input channels enabled
SCLK ≥ 12 MHz, single analog channel
Delay from trigger to conversion start
µs
500 kSPS
Conversion delay
2
4
µs
ANALOG INPUT
Absolute input voltage range
Independent of gain setting
Gain = 1, adcn_gain = '0'
Gain = 2, adcn_gain = '1'
AGND – 0.2
AVDD + 0.2
VREF
V
V
0
0
Full scale input voltage range
2 × VREF
V
Input capacitance(1)
40
pF
µA
DC input leakage current
Measured with ADC in Hold mode
±1
AC PERFORMANCE
SFDR
SNR
Spurious Free Dynamic Range
Signal to Noise Ratio
fIN = 1 kHz, –1 dBFS sine wave
fIN = 1 kHz, –1 dBFS sine wave
fIN = 1 kHz, –1 dBFS sine wave
76
61
dBc
dBc
dBc
SINAD Signal to Noise+Distortion Ratio
60.5
fIN = 1 kHz, –1 dBFS sine wave, Measured
up to the fifth harmonic
THD
Total Harmonic Distortion
75
dBc
(2)
INTERNAL ADC REFERENCE
Internal ADC reference buffered output at
REF pin
VREF
Reference output voltage
2.5
V
Reference buffer power
AVDD = 5 V
360
10
µA
Reference temperature coefficient
ppm/°C
EXTERNAL ADC REFERENCE
VREF
Reference input voltage
Input resistance(1)
External ADC reference input to REF pin
VREF = 5 V, AIN = 5 V
0.3
AVDD
V
20
kΩ
TEMPERATURE SENSOR
Operating range
Accuracy
–40
125
°C
°C
°C
ms
TA = –40°C to 125°C, AVDD = 5 V
±1
0.125
15
±2.5
Resolution
LSB size
Conversion time
(1) Specified by design. Not tested during production.
(2) Use an external buffer amplifier with high impedance input to drive any external load.
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AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
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ELECTRICAL CHARACTERISTICS – GENERAL SPECIFICATIONS
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD
,
TA = –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL PURPOSE I/O
GPIOVDD = 1.8 V
0.7×GPIOVDD
V
V
VIH
VIL
High-level input voltage
Low-level input voltage
GPIOVDD = 3.3 to 5.5 V
GPIOVDD = 1.8 V
2.1
0.3
0.8
V
V
GPIOVDD = 3.3 to 5.5 V
Iload = 1.6 mA, GPIOVDD = 1.8V, All GPIOs
loaded and set to '1'
GPIOVDD - 0.25
GPIOVDD - 0.2
V
V
VOH
High-level output voltage
Low-level output voltage
Iload = 1.6 mA, GPIOVDD = 3.3 to 5.5V, All
GPIOs loaded and set to '1'
VOL
Iload = -1.6 mA, All GPIOs loaded
0.4
V
(1)
Input capacitance
1
1
pF
High impedance output
pF
(1)
capacitance
LOGIC INPUTS: CS, SDI, SCLK
SPIVDD = 1.8 V
0.7×SPIVDD
V
V
VIH
VIL
High-level input voltage
SPIVDD = 3.3 to 5.5 V
SPIVDD = 1.8 V
2.1
0.3
0.7
±1
V
Low-level input voltage
Input current
SPIVDD = 3.3 to 5.5 V
V
µA
pF
(1)
Input capacitance
1
1
High impedance output
pF
(1)
capacitance
LOGIC OUTPUT: SDO
VOH
VOL
High-level output voltage
Low-level output voltage
Iload = 1.6 mA
Iload = -1.6 mA
SPIVDD - 0.2
V
V
0.4
0.4
LOGIC OUTPUT: DAV
VOL
Low-level output voltage
Iload = -2 mA
V
POWER REQUIREMENTS
AVDD
4.75
1.8
5
5.5
5.5
5.5
V
V
V
GPIOVDD
SPIVDD
1.8
Total supply current, AVDD
GPIOVDD + SPIVDD
+
IDD
Operating mode(2)
6.5
10
mA
Power down mode
Operating mode(2)
Power down mode
1.25
32.5
6.25
2
55
11
mA
mW
mW
Power consumption
OPERATING RANGE
Specified temperature range
(1) Specified by design. Not tested in production.
(2) AVDD = GPIOVDD = SPIVDD = 5 V. No DAC load, all DACs at 0x200 code and ADC at the fastest auto conversion rate.
–40
25
105
°C
8
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SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
TIMING SPECIFICATIONS(1)(2)
AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD
,
TA = –40°C to 105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SPIVDD = 5.5 V
30
15
10
2
MHz
MHz
MHz
ns
fSCLK
SCLK frequency
SPIVDD = 2.7 V
SPIVDD = 1.8 V
10% to 90% of SPIVDD
10% to 90% of SPIVDD
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
SPIVDD = 5.5 V
SPIVDD = 2.7 V
SPIVDD = 1.8 V
tR
tF
Input rise time
Input fall time
2
ns
33
66
100
13
30
50
13
26
40
5
ns
t1
t2
t3
SCLK cycle time
SCLK high time
SCLK low time
ns
ns
ns
ns
ns
ns
ns
ns
t4
t5
t6
t7
t8
Frame start time
SDI setup time
SDI hold time
Frame stop time
CS high time
CS falling edge to SCLK rising edge
SDI valid to falling edge of SCLK
SDI valid after falling edge of SCLK
SCLK falling edge to CS rising edge
ns
4
ns
12
15
50
5
ns
ns
ns
SPIVDD = 5.5 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 4 ns
SPIVDD = 2.7 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 5 ns
SPIVDD = 1.8 V, CL = 10 pF, 2 ns ≤ tR,F(SDO) ≤ 8 ns
CS rising edge to next SCLK rising edge
16
22
39
ns
t9
SDO delay
Wait time
6
ns
8
ns
t10
5
ns
(1) Specified by design. Not tested during production.
(2) Digital inputs and outputs timed from a voltage level of SPIVDD/2.
TIMING INFORMATION
t8
t4
t7
CS
t10
t1
tf
t3
t2
SCLK
SDI
tr
Bit 23
Bit 1
Bit 0
t5
t6
Figure 1. Serial Interface Write Timing Diagram
t
8
t
t
7
4
CS
tf
t
t
1
r
t
t
SCLK
3
2
Read Command
Any Command
Bit 23
Bit 0
Bit 23
Bit 23
Bit 1
Bit 1
Bit 0
Bit 0
SDI
t9
t
t
6
5
SDO
Data read from the register selected in previous operation
Figure 2. Serial Interface Read Timing Diagram
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TYPICAL CHARACTERISTICS: DAC
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
1.000
0.750
1.000
0.750
0.500
0.500
0.250
0.250
0.000
0.000
−0.250
−0.500
−0.750
−1.000
−0.250
−0.500
−0.750
T=25ºC
T=25ºC
−1.000
0
128
256
384
512
640
768
896 1024
0
128
256
384
512
640
768
896 1024
Code
Code
G001
G002
Figure 3. DAC INTEGRAL NON-LINEARITY
Figure 4. DAC DIFFERENTIAL NON-LINEARITY
1.000
0.750
1.000
0.750
INL Max
DNL Max
0.500
0.500
0.250
0.250
0.000
0.000
−0.250
−0.500
−0.750
−1.000
−0.250
−0.500
−0.750
−1.000
INL Min
DNL Min
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
G003
G004
Figure 5. DAC INL vs. TEMPERATURE
Figure 6. DAC DNL vs. TEMPERATURE
5
200
150
100
50
4
3
2
1
0
0
−1
−2
−3
−4
−5
−50
−100
−150
−200
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
G005
G006
Figure 7. DAC OFFSET ERROR vs. TEMPERATURE
Figure 8. DAC GAIN ERROR vs. TEMPERATURE
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TYPICAL CHARACTERISTICS: DAC (continued)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
2.502
2.501
2.500
2.499
2.498
5.000
4.950
4.900
4.850
4.800
4.750
4.700
Code = 0x200
10
Code = 0x3FF
10
−10 −8
−6
−4
−2
0
2
4
6
8
0
1
2
3
4
5
6
7
8
9
Load Current (mA)
Source Current (mA)
G007
G008
Figure 9. DAC OUTPUT VOLTAGE vs. LOAD CURRENT
Figure 10. DAC SOURCE CURRENT
0.300
0.250
0.200
0.150
0.100
0.050
0.000
Code = 0x000
0
1
2
3
4
5
6
7
8
9
10
Sink Current (mA)
G009
Figure 11. DAC SINK CURRENT
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TYPICAL CHARACTERISTICS: ADC
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
1.000
0.750
1.000
0.750
0.500
0.500
0.250
0.250
0.000
0.000
−0.250
−0.500
−0.750
−1.000
−0.250
−0.500
−0.750
T=25ºC
T=25ºC
−1.000
0
128
256
384
512
640
768
896 1024
0
128
256
384
512
640
768
896 1024
Code
Code
G013
G014
Figure 12. ADC INTEGRAL NON-LINEARITY
Figure 13. ADC DIFFERENTIAL NON-LINEARITY
1.000
0.750
1.000
0.750
INL Max
DNL Max
0.500
0.500
0.250
0.250
0.000
0.000
−0.250
−0.500
−0.750
−1.000
−0.250
−0.500
−0.750
−1.000
INL Min
DNL Min
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
G015
G016
Figure 14. ADC INL vs. TEMPERATURE
Figure 15. ADC DNL vs. TEMPERATURE
2.000
2.000
1.500
1.500
1.000
1.000
0.500
0.500
0.000
0.000
−0.500
−1.000
−1.500
−2.000
−0.500
−1.000
−1.500
−2.000
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
G017
G017
Figure 16. ADC OFFSET ERROR vs. TEMPERATURE
Figure 17. ADC GAIN ERROR vs. TEMPERATURE
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SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS: ADC (continued)
AVDD = 5 V, GPIOVDD = 5 V, SPIVDD = 5 V, AGND = DGND = 0 V, External ADC reference = AVDD
(unless otherwise noted)
2.000
1.500
2.000
1.500
1.000
1.000
0.500
0.500
0.000
0.000
−0.500
−1.000
−1.500
−2.000
−0.500
−1.000
−1.500
−2.000
AVDD = 5 V
AVDD = 5 V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
External ADC Vref (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
External ADC Vref (V)
G019
G020
Figure 18. ADC OFFSET ERROR vs. REFERENCE
VOLTAGE
Figure 19. ADC GAIN ERROR vs. REFERENCE VOLTAGE
2.505
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
2.496
15 units
2.495
2.5
3.0
3.5
4.0
4.5
5.0
5.5
−40
−20
0
20
40
60
80
100
120
AVDD (V)
Temperature (°C)
G021
G022
Figure 20. ADC INTERNAL REFERENCE vs. AVDD
Figure 21. ADC INTERNAL REFERENCE vs.
TEMPERATURE
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
15 units
−40
−20
0
20
40
60
80
100
120
Temperature (°C)
G000
Figure 22. TEMPERATURE SENSOR ERROR vs TEMPERATURE
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THEORY OF OPERATION
SERIAL INTERFACE
The AMC7891 is controlled through a flexible four-wire serial interface compatible with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers of the AMC7891
with clock rates up to 30 MHz.
The interface is compatible with most synchronous transfer formats and is configured as a 4 pin interface. SCLK
is the serial interface input clock and CS is serial interface enable. Data is input into SDI and latched into the
24-bit wide SPI shift register on SCLK falling edges, while CS is low. Data is clocked out of SDO on SCLK rising
edges, while CS is low. The contents of the SPI shift register are loaded into the device internal register on a CS
rising edge after some delay. When CS is high, both SCLK and SDI inputs are blocked out and the SDO output
is in high-impedance state.
The serial interface works with both a continuous and a non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock to
latch the data.
Each SPI command is input to SDI and framed by signal CS (Serial Data Enable) asserted low. The frame’s first
byte into SDI is the instruction cycle which identifies the request as a read or write as well as the 7-bit address to
be accessed. The following two bytes in the frame form the data cycle.
Instruction Cycle
Data Cycle
CS
SCLK
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23. Serial Interface Command
Bit 23
R/W. Identifies the communication as a read or write command to the addressed register. Bit =
‘0’ sets the write operation. Bit = ‘1’ sets the read operation.
Bits[22:16]
Bits[15:0]
A[6:0]. Register address; specifies the register to be accessed during the read or write
operation.
D[15:0]. Data cycle bits.
If a write command, the data cycle bits are the values to be written to the register with address
A[6:0].
If a read command, the data cycle bits are don’t care values.
A read command causes an output on the SDO pin during the next SPI command cycle. The SDO read value
frame is formed by the previous communication instruction cycle and the data read from the specified register.
Table 1. Serial Data Format
INSTRUCTION CYCLE
DATA CYLE
Bits [15:0]
SPI FRAME
PIN
Bit 23
0 (R/W)
Bits [22:16]
SDI
SDO
SDI
A[6:0]
Data In[15:0]
Write Command
Frame
Undefined or Read Value Frame depending on previous
command
1 (R/W)
A[6:0]
Don’t care
Read Command
Frame
Undefined or Read Value Frame depending on previous
command
SDO
SDI
New Write or Read Command Frame
Read Value Frame
SDO
1 (R/W)
A[6:0]
Data Out[15:0]
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The serial clock can be continuous or gated as long as there are exactly 24 falling clock edges within the frame.
A write command issued in frames whose width is not 24 bits is incorrect and ignored by the AMC7891. A read
command frame not equal to 24 bits may result in abnormal data on SDO and must be ignored by the host
processor. In order for another serial transfer to occur, CS must be brought low again to start a new cycle.
Figure 24 and Figure 25 show multiple write and read operations.
CS
SDI
W0
XX
W1
XX
W2
XX
W3
XX
SDO
Wn = Write Command for Register N
XX = Don’t care, undefined
Figure 24. Serial Interface Write Operation
CS
Any Command
SDI
R0
R1
R2
R3
XX
D0
D1
D2
SDO
D3
Rn = Read Command for Register N
Dn = Data from Register N
XX = Don’t care, undefined
Figure 25. Serial Interface Read Operation
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REGISTER MAP
The AMC7891 has 16-bit registers containing device configuration and conversion results. A 7-bit register
address indicates the proper register.
Table 2. Register Map
MSB
LSB
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
NAME
ADDR
0x00
DEFAULT
0x0000
TEMP_data
TEMP_config
0
0
0
0
0
0
0
0
tempdata(11:0)
temp_
en
0x0A
0x0008
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP_rate
ADC0_data
ADC1_data
ADC2_data
ADC3_data
ADC4_data
ADC5_data
ADC6_data
ADC7_data
DAC0_data
DAC1_data
DAC2_data
DAC3_data
DAC0_clear
DAC1_clear
DAC2_clear
DAC3_clear
0x0B
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x0007
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
temp_rate(2:0)
adc0_data(9:0)
adc1_data(9:0)
adc2_data(9:0)
adc3_data(9:0)
adc4_data(9:0)
adc5_data(9:0)
adc6_data(9:0)
adc7_data(9:0)
dac0_data(9:0)
dac1_data(9:0)
dac2_data(9:0)
dac3_data(9:0)
dac0_clear(9:0)
dac1_clear(9:0)
dac2_clear(9:0)
dac3_clear(9:0)
ioc3_
io
ioc2_
io
ioc1_
io
ioc0_
io
iob3_
io
iob2_
io
iob1_
io
iob0_
io
ioa3_
io
ioa2_
io
ioa1_
io
ioa0_
io
GPIO_config
GPIO_out
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x0000
0x0000
NA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ioc3_
out
ioc2_
out
ioc1_
out
ioc0_
out
iob3_
out
iob2_
out
iob1_
out
iob0_
out
ioa3_
out
ioa2_
out
ioa1_
out
ioa0_
out
ioc3_
in
ioc2_
in
ioc1_
in
ioc0_
in
iob3_
in
iob2_
in
iob1_
in
iob0_
in
ioa3_
in
ioa2_
in
ioa1_
in
ioa0_
in
GPIO_in
adc_
mode
adc_tr dac_lo
adc_r
eady
AMC_config
ADC_enable
ADC_gain
DAC_clear
DAC_sync
AMC_power
0x2000
0x0000
0xFF00
0x0000
0x0000
0x0000
resvd
adc_rate(1:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ig
ad
adc0_ adc1_
en en
adc2_ adc3_
en en
adc4_ adc5_ adc6_ adc7_
en
resvd
resvd
en
en
en
adc0_ adc1_ adc2_ adc3_ adc4_ adc5_ adc6_ adc7_
0
0
0
gain
gain
gain
gain
gain
gain
gain
gain
dac3_ dac2_ dac1_ dac0_
clear clear clear clear
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
dac3_ dac2_ dac1_ dac0_
sync
0
0
0
0
0
0
0
0
0
0
sync
sync
sync
adc_o
n
dac0_ dac1_ dac2_ dac3_
on on on on
ref_on
0
0
0
0
AMC_reset
AMC_ID
0x3E
0x40
0x0000
0x0044
reset(15:0)
device_id(15:0)
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REGISTER DESCRIPTIONS
Register name: temp_data – Address: 0x00, Default: 0x0000 (READ ONLY)
Register
Name
Address Bit
Name
Function
Default Value
temp_data
0x00
15:12
11:0
Reserved
Reserved for factory use.
All zeros
temp_data(11:0) Stores the temperature sensor reading in twos complement format.
0x000
0.125°C/LSB.
Register name: temp_config – Address: 0x0A, Default: 0x0008 (READ/WRITE)
Register
Name
Address Bit
Name
Function
Default Value
temp_config
0x0A 15:4
Reserved
temp_en
Reserved
Reserved for factory use.
All zeros
1
3
When set to ‘1’, the on-chip temperature sensor is enabled.
Reserved for factory use.
2:0
All zeros
Register name: temp_rate – Address: 0x0B, Default: 0x0007 (READ/WRITE)
Register
Name
Address Bit
Name
Function
Default Value
temp_rate
0x0B
15:3
2:0
Reserved
temp_rate(2:0)
Reserved for factory use.
Sets the temperature sensor ADC conversion time
All zeros
111
temp_rate(2:0)
Conversion time
000
001
010
011
100
101
110
111
128x
64x
32x
16x
8x
4x
2x
15 ms
Register name: ADCn_data – Address: 0x23 to 0x2A, Default: 0x0000 (READ ONLY)(1)
Register
Name
Address Bit
Name
Function
Default Value
ADCn_
data
0x23 to 15:10 Reserved
0x2A
Reserved for factory use.
All zeros
All zeros
9:0
adcn_data(9:0) Stores the 10-bit ADCn conversion results in straight binary format.
Input Channel
ADC Register Value
Register
Address
AIN_0
AIN_1
AIN_2
AIN_3
AIN_4
AIN_5
AIN_6
AIN_7
adc0_data(9:0)
adc1_data(9:0)
adc2_data(9:0)
adc3_data(9:0)
adc4_data(9:0)
adc5_data(9:0)
adc6_data(9:0)
adc7_data(9:0)
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
(1) All ADCn_data registers are formatted in the manner shown here. n = 0, 1, …, 7
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Register name: DACn_data – Address: 0x2B to 0x2E, Default: 0x0000 (READ/WRITE)(1)
Register
Name
Addres Bit
s
Name
Function
Default
Value
DACn_ data 0x2B to 15:10 Reserved
0x2E
Reserved for factory use.
All zeros
All zeros
9:0
dacn_data(9:0)
Stores the 10-bit data to be loaded to the DACn latches in straight
binary format.
Output Channel
DAC Register
Value
Register
Address
DACOUT_0
DACOUT_1
DACOUT_2
DACOUT_3
dac0_data(9:0)
dac1_data(9:0)
dac2_data(9:0)
dac3_data(9:0)
0x2B
0x2C
0x2D
0x2E
(1) All DACn_data registers are formatted in the manner shown here. n = 0, 1, …, 3
Register name: DACn_clear – Address: 0x2F to 0x32, Default: 0x0000 (READ/WRITE)(1)
Register
Name
Address Bit
Name
Function
Default
Value
DACn_ clear
0x2F to
0x32
15:10
9:0
Reserved
Reserved for factory use.
All zeros
All zeros
dacn_clear(9:0 Stores the 10-bit data to be loaded to the DACn when cleared.
)
Straight binary format.
Output Channel
DAC Clear Value
Register
Address
DACOUT_0
DACOUT_1
DACOUT_2
DACOUT_3
dac0_clear(9:0)
dac1_clear(9:0)
dac2_clear(9:0)
dac3_clear(9:0)
0x2F
0x30
0x31
0x32
(1) All DACn_data registers are formatted in the manner shown here. n = 0, 1, …, 3
Register name: GPIO_config – Address: 0x33, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
GPIO_config
0x33
15:12
11
Reserved Reserved for factory use.
All zeros
0
ioc3_io
When cleared to ‘0’ the corresponding GPIO is configured as an input and
set on high-impedance state (default).
10
9
8
7
6
5
4
3
2
1
0
ioc2_io
ioc1_io
ioc0_io
iob3_io
iob2_io
iob1_io
iob0_io
ioa3_io
ioa2_io
ioa1_io
ioa0_io
0
0
0
0
0
0
0
0
0
0
0
When set to ‘1’ the corresponding GPIO is configured as an output.
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Register name: GPIO_out – Address: 0x34, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
GPIO_out
0x34
15:12 Reserved
Reserved for factory use.
All zeros
11
10
9
ioc3_out
ioc2_out
ioc1_out
ioc0_out
iob3_out
iob2_out
iob1_out
iob0_out
ioa3_out
ioa2_out
ioa1_out
ioa0_out
If the corresponding GPIO is configured as an output in register
GPIO_config, 0x33, the value on this bit sets the digital output.
0
0
0
0
0
0
0
0
0
0
0
0
If the corresponding GPIO is configured as an input in register
GPIO_config, 0x33, this bit is a don’t care.
8
7
6
5
4
3
2
1
0
Register name: GPIO_in – Address: 0x35, Default: NA (READ ONLY)
Register
Name
Address
Bit
Name
Function
Default
Value
GPIO_in
0x35
15:12 Reserved
Reserved for factory use.
All zeros
0
11
ioc3_in
If the corresponding GPIO is configured as an output in register
GPIO_config, 0x33, the value on this bit correspods to the digital output.
10
9
8
7
6
5
4
3
2
1
0
ioc2_in
ioc1_in
ioc0_in
iob3_in
iob2_in
iob1_in
iob0_in
ioa3_in
ioa2_in
ioa1_in
ioa0_in
0
0
0
0
0
0
0
0
0
0
0
If the corresponding GPIO is configured as an output in register
GPIO_config 0x33, this bit matches the corresponding value in register
GPIO_out, 0x34.
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Register name: AMC_config – Address: 0x36, Default: 0x2000 (READ/WRITE)
Register
Name
Address Bit
Name
Function
Default
Value
AMC_config
0x36 15:4
Reserved
adc_mode
Reserved for factory use.
All zeros
1
13
When set to ‘1’, the ADC is in Auto-mode conversion.
When cleared to ‘0’, the ADC is in Direct-mode conversion.
12
11
adc_trig
When set to ‘1’ triggers a new ADC conversion cycle. The bit is
cleared to ‘0’ automatically after the ADC conversion cycle starts.
0
0
dac_load
When set to ‘1’ data is loaded into the DAC output channels set to
synchronous mode in register dac_sync, 0x3A.
The AMC7891 updates the DAC output only if the corresponding
dacn_data register has been accessed since the last dac_load
trigger. Any DAC channels that have not been accessed are not
reloaded again.
10
Reserved
Reserved for factory use.
0
9:8
adc_rate(1:0)
Sets the primary ADC conversion rate
00
adc_rate(1:0)
Conversion time (kSPS)
00
01
10
11
500
250
125
62.5
7
adc_ready
ADC data available indicator in Direct-mode conversion. Always
0
cleared to ‘0’ in Auto-mode conversion.
A ‘1’ read from this bit indicates the ADC conversion cycle is
complete and new data is available.
A ‘0’ read from this bit indicates the ADC conversion cycle is in
progress or the ADC is in Auto-mode.
To clear this bit one of the following events has to occur:
1. Reading the adcn_data registers.
2. Starting a new ADC conversion cycle.
6:0
Reserved
Reserved for factory use.
All zeros
Register name: ADC_enable – Address: 0x37, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
ADC_enable
0x37
15
14
13
11
10
8
Reserved
adc0_en
adc1_en
adc2_en
adc3_en
adc4_en
adc5_en
adc6_en
adc7_en
Reserved
Reserved for factory use.
All zeros
When set to ‘1’ the corresponding analog input channel AIN_n
(n = 0, 1, …, 7) is accessed during an ADC conversion cycle.
0
0
When cleared to ‘0’ the corresponding input channel AIN_n
(n = 0, 1, …, 7) is ignored during an ADC conversion cycle.
0
0
0
7
0
6
0
0
5
12,9
Reserved for factory use. Must be set to 0 for proper device
All zeros
operation.
4:0
Reserved
Reserved for factory use.
All zeros
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Register name: ADC_gain – Address: 0x38, Default: 0xFF00 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
ADC_gain
0x38
15
adc0_gain
When set to ‘1’ the corresponding analog input channel AIN_n (n = 0, 1,
…, 7) input range is 2 × VREF
1
.
14
13
adc1_gain
adc2_gain
1
1
When cleared to ‘0’ the corresponding input channel AIN_n (n = 0, 1, …,
7) input range is VREF
.
12
11
10
9
adc3_gain
adc4_gain
adc5_gain
adc6_gain
adc7_gain
Reserved
1
1
1
1
1
8
7:0
Reserved for factory use.
All zeros
Register name: DAC_clear – Address: 0x39, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
ADC_clear
0x39
15:4
Reserved
Reserved for factory use.
All zeros
3
2
1
dac3_clear When set to ‘1’ clears the corresponding DACout_n (n = 0, 1, …, 3)
0
0
0
output to the value specified in register dacn_clear, 0x2F to 0x32.
dac2_clear
dac1_clear When cleared to ‘0’ the corresponding DACout_n (n = 0, 1, …, 3)
output returns to normal operation.
0
dac0_clear
0
Register name: DAC_sync – Address: 0x3A, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
DAC_sync
0x3A
15:4
Reserved
dac3_sync
dac2_sync
dac1_sync
Reserved for factory use.
All zeros
3
2
1
When set to ‘1’ clears the corresponding DACout_n (n = 0, 1, …, 3) is set to
synchronous-mode.
0
0
0
When cleared to ‘0’ the corresponding DACout_n (n = 0, 1, …, 3) is set to
asynchronous-mode.
0
dac0_sync
0
Register name: AMC_power – Address: 0x3B, Default: 0x0000 (READ/WRITE)
Register
Name
Address
Bit
Name
Function
Default
Value
AMC_power
0x3B
15
14
Reserved
adc_on
Reserved for factory use.
0
0
When cleared to '0' the primary ADC is in power-down mode.
When set to '1' the primary ADC is in active mode.
13
ref_on
When cleared to '0' the internal reference buffer is in power-down mode; the
device is in External ADC Reference mode and the REF pin is an input.
0
When set to '1' the internal reference buffer is active; the device is in
Internal ADC Reference mode and the REF pin is an output.
12
11
10
9
dac0_on
dac1_on
dac2_on
dac3_on
Reserved
When cleared to '0' DAC0 is in power-down mode. DACout_0 is in
high-impedance state.
When set to '1' DAC0 is in active mode.
0
When cleared to '0' DAC1 is in power-down mode. DACout_1 is in
high-impedance state.
When set to '1' DAC1 is in active mode.
0
When cleared to '0' DAC2 is in power-down mode. DACout_2 is in
high-impedance state.
When set to '1' DAC2 is in active mode.
0
0
When cleared to '0' DAC3 is in power-down mode. DACout_3 is in
high-impedance state.
When set to '1' DAC3 is in active mode.
8:0
Reserved for factory use.
All zeros
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Register name: AMC_reset – Address: 0x3E, Default: 0x0000 (READ/WRITE)
Register
Name
Address Bit
Name
Function
Default Value
AMC_reset
0x3E 15:0
reset(15:0)
Writing 0x6600 to this register forces a reset operation. During reset,
all SPI communication is blocked. After issuing the reset, there is a
wait of at least 30 μs before communication can be resumed.
All zeros
Register name: AMC_ID – Address: 0x40, Default: 0x0044 (READ ONLY)
Register
Name
Address Bit
Name
Function
Default Value
AMC_ID
0x40 15:0
device_id(15:0) A hardwired register that contains the AMC7891 ID.
0x0044
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ADC OPERATION
The AMC7891 has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary
ADC consists of an 8-channel multiplexer, an on-chip track-and-hold, and a successive approximation register
(SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at rates up to 500 kSPS and
converts the uncommitted analog channel inputs, AIN0 to AIN7.
The analog input range for the device can be selected as 0 V to VREF or 0 V to (2 × VREF). The AMC7891 has an
on-chip buffered 2.5V reference that can be disabled when an external reference is preferred. The secondary
ADC is a part of the on-chip temperature sensing function.
PRIMARY ADC OPERATION
The following sections describe the operation of the primary ADC. The temperature sensor ADC always operates
in the background.
ANALOG INPUT FULL SCALE RANGE
The values in register ADC_gain determine the full-scale range of the analog inputs. The full-scale range for
input channel AINn is VREF when bit adcn_gain = 0, or 2 × VREF when adcn_gain = 1. Each input must not
exceed the supply value of AVDD + 0.2 V or AGND – 0.2 V.
When internal ADC reference is enabled, the buffered internal reference is used as the ADC reference. When
external ADC reference is selected, an external reference voltage applied to the REF pin is the ADC reference.
ANALOG INPUTS
The AMC7891 has 8 uncommitted single-ended analog inputs. Figure 26 shows the equivalent input circuit of the
AMC7891. The (peak) input current through the analog inputs depends on the sample rate, input voltage, and
source impedance. The current into the AMC7891 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input
voltage must be able to charge the input capacitance to a 10-bit settling level within the acquisition time. When
the converter goes into hold mode, the input impedance is greater than 1 GΩ.
In applications where the signal source has high impedance, it is recommended to buffer the analog input before
applying it to the ADC. The analog input range can be programmed to be either 0 V to VREF or 0 V to (2 × VREF).
With a gain of 2, the input is effectively divided by two before the conversion takes place. Note that the voltage
with respect to AGND on the ADC analog input cannot exceed AVDD
.
AVDD
40 W
40 pF
50 W
50 W
50 W
AIN0
AIN7
AVDD
Device in Hold Mode
40 W
40 pF
AGND
Figure 26. ADC Equivalent Input Circuit
ADC TRIGGER SIGNALS
The ADC can be triggered internally by writing to the adc_trig bit in register AMC_config. When a new trigger
activates, the ADC stops any existing conversion immediately and starts a new cycle. For example, the ADC is
programmed to sample input channels 0 to channel 3 repeatedly (auto-mode). During the conversion of channel
1, a trigger is activated. The ADC stops the conversion of channel 1 immediately and starts the conversion of
channel 0 again, instead of proceeding to convert channel 2.
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CONVERSION MODES
Two types of ADC conversions are available: direct-mode and auto-mode. adc_mode bit (AMC_config register,
bit 13) sets the conversion mode. The default conversion mode is auto-mode (adc_mode = '1').
In direct-mode conversion, each analog channel within the specified group in register ADC_enable is converted a
single time. After the last channel is converted, the ADC goes into an idle state and waits for a new trigger.
Auto-mode conversion, on the other hand, is a continuous operation. In auto-mode, each analog channel within
the specified group is converted sequentially and repeatedly.
The flow chart of the ADC conversion sequence in Figure 27 shows the conversion process.
Start
(Reset)
Wait for
ADC Trigger
First Conversion
New Trigger
or
Yes
adc_mode Changed?
No
Input Channel
Yes
Stop current conversion
Register been
Rewritten?
No
Yes
Is this the last conversion?
No
Yes
Direct Mode
Convert next channel
No
Figure 27. ADC Conversion Sequence
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When any of the following events occur, the current conversion cycle stops immediately:
•
•
•
A new trigger is issued.
The conversion mode changes.
Either ADC channe register is rewritten.
When a new trigger activates, the ADC starts a new conversion cycle. The trigger should not be issued at the
same time the conversion mode is changed. If a ‘1’ is simultaneously written to the adc_trig bit when changing
the adc_mode bit from ‘0’ to '1', the current conversion stops and immediately returns to the wait for ADC trigger
state.
To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the
conversion process time immediately after the ADC conversion starts.
DOUBLE-BUFFERED ADC DATA REGISTER
The host can access all eight, double-buffered ADCn_data registers, as shown in Figure 28. The conversion
result from the analog input with channel address n, (where n = 0 to 7) is stored in adcn_data[9:0] in straight
binary format. When the conversion of an individual channel is completed, the data is immediately transferred
into the corresponding adcn_tmpry temporary register, the first stage of the data buffer. When the conversion of
the last channel completes, all data in the adcn_tmpry registers is simultaneously transferred to the
corresponding adcn_data[9:0] value, the second stage of the data buffer.
In the case when a data transfer is in progress between any ADCn_data register and the AMC7891 shift register,
all ADCn_data registers are not updated until the data transfer is complete.
AIN0
AIN1
AIN2
AIN3
To Shift
Register
ADC
adc0_tmpry
adc0_data
AIN4
AIN5
AIN6
AIN7
.
.
.
Input Range
Selection
adc_trig
(Internal Trigger)
adc7_tmpry
adc7_data
GPIOVDD
10 kW
adc_ready
DAV
Figure 28. ADC Structure
PROGRAMMABLE CONVERSION RATE
The maximum ADC conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 3. The
conversion rate is programmable through adc_rate[1:0] (AMC_config register, [9:8] bits). When more than one
channel is selected, the conversion rate is divided by the number of channels selected in register ADC_enable.
In auto mode, the adc_rate[1:0] value determines the actual conversion rate. In direct mode, adc_rate[1:0] limits
the maximum possible conversion rate. The actual conversion rate in direct mode is determined by the rate of
the conversion trigger. Note that when a trigger is issued, there may be a delay of up to 4 μs to internally
synchronize and initiate the start of the sequential channel conversion process. In both direct- and auto- modes,
when adc_rate[1:0] is set to a value other than the maximum rate ('00'), nap mode is activated between
conversions. By activating nap mode, the AVDD supply current is reduced.
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Table 3. ADC Conversion Rate
tACQ
(µs)
tCONV
(µs)
NAP
ENABLED
THROUGHPUT
adc_rate[1:0]
(Single-Channel Auto Mode)
500 kSPS (default)
250 kSPS
00
01
10
11
0.375
2.375
6.375
14.375
1.625
1.625
1.625
1.625
No
Yes
Yes
Yes
125 kSPS
62.5 kSPS
HANDSHAKING WITH THE HOST
The DAV pin and adc_ready bit (AMC_config register, bit 7) provide handshaking with the host. The DAV pin is
an open-drain, active low output. If used, an external 10 kΩ pull-up resistor to GPIOVDD is required. If unused,
the pin can be connected to DGND. Pin and bit status depend on the conversion mode (direct or auto), as shown
in Figure 29.
In direct mode, after the ADCn_data registers of all the selected channels in register adc_enable are updated,
adc_ready is set immediately to '1' and the DAV pin is active (low) to signify that new data is available.
The adc_ready bit is reset to '0' and the DAV pin goes back to inactive (high) either by reading any of the
ADCn_data registers or when a new ADC conversion is started by issuing a trigger by adc_trig. The update
takes place immediately after the read command frame indicating the read operation or trigger event.
In auto-mode, after the adcn_data[9:0] values are updated, a pulse of 1μs (low) appears on the DAV pin to
signify that new data is available. However, the adc_trig bit is inactive and always set to ‘0’.
a) Direct Mode
CS
adc_trig
set to “1”
adc_trig
set to “1”
Read Data
Command Frame
Read Data
Command Frame
1st internal
trigger
2nd internal
trigger
Read
Instruction
Read
Instruction
SDI
DAV
1st CONVERSION of the
channels specified in the ADC
Channel Register
2nd CONVERSION of the
channels specified in the ADC
Channel Register
b) Auto Mode
CS
adc_trig
set to “1”
1st internal
trigger
SDI
DAV
1µs
1st CONVERSION of the
2nd CONVERSION
3rd CONVERSION
channels specified in the ADC
Channel Register
Figure 29. ADC Handshaking
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TEMPERATURE SENSOR OPERATION (SECONDARY ADC)
The AMC7891 contains an on-chip temperature sensor used to measure the device temperature. The
temperature sensor is continuously monitoring, and new readings are automatically available every cycle. The
analog temperature reading is converted by a secondary ADC that runs in the background at a lower speed than
the primary ADC.
The temperature measurement relies on the characteristics of a semiconductor junction operating at a fixed
current level. The forward voltage of the diode (VBE) depends on the current passing through it and the ambient
temperature. The change in VBE when the diode operates at two different currents (a low current of ILOW and a
high current of IHIGH, is shown in Equation 1:
VBE_HIGH – VBE_LOW = ηkT/q × ln(IHIGH/ILOW
)
(1)
Where:
k is Boltzmann’s constant.
q is the charge of the carrier.
T is the absolute temperature in Kelvins (K).
η is the ideality of the transistor as sensor.
IHIGH
ILOW
SW1
SW2
Secon ADC
and Signal
Processing
LPF and Signal
Conditioning
temp _data
register
Mux
Diode
Temperature
Sensor
Figure 30. Integrated Temperature Sensor
The temperature sensor can be disabled by clearing to ‘0’ the temp_en bit (TEMP_config register, bit 3). When
disabled, the sensor is not converted. The AMC7891 continuously monitors the temperature sensor in the
background, leaving the user free to perform conversions on the primary ADC. When one monitor cycle finishes,
a signal passes to the control logic to automatically initiate a new conversion.
The analog sensing signal is preprocessed by a low-pass filter and signal conditioning circuitry, and then
digitized by the secondary ADC. The resulting digital signal is further processed by the digital filter and
processing unit. The final result is stored as a 12-bit value in the TEMP_data register as tempdata[11:0]. The
format of the final result is in twos complement, as shown in Table 4. Note that the device measures the
temperature from –40°C to 150°C.
If a data transfer is in progress between the TEMP_data register and the AMC Shift Register, the TEMP_data
register is frozen until the data transfer is complete.
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Table 4. Temperature Data Format
TEMPERATURE (°C)
DIGITAL CODE
011111111111
010010110000
001100100000
000110010000
000011001000
000000001000
000000000000
111111111000
111100111000
111001110000
110011100000
101101010000
100000000000
+255.875
+150
+100
+50
+25
+1
0
–1
–25
–50
–100
–150
–256
The temperature conversion time is by default 15 ms but it can be increased by setting temp_rate[2:0]
(TEMP_rate register, bits [2:0]) as shown in Table 5.
Table 5. Temperature Conversion Time
adc_rate[2:0]
CONVERSION TIME
000
001
010
011
100
101
110
111
128x
64x
32x
16x
8x
4x
2x
15 ms
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REFERENCE OPERATION
The AMC7891 includes a buffered internal reference for the ADC, DACs and temperature sensor. The internal
reference is a 2.5 V, bipolar transistor-based, precision bandgap reference.
The internal reference always drives the DACs and the internal temperature sensor directly (unbuffered);
however the ADC can be driven either by the internal reference (buffered) or by an external one as determined
by the ref_on bit (AMC_power register, bit 13). If used, the external reference is applied to the dual purpose REF
pin. A decoupling capacitor is recommended between the external reference output an AGND for noise filtering.
In internal ADC reference mode, the buffered internal reference is available at the REF pin. A compensating
4.7µF capacitor is recommended between the internal buffered reference output and AGND.
On power-up, the AMC7891 is configured for ADC external reference (ref_on bit cleared to ‘0’). In this case it is
important that the external reference source is not input into the REF pin until AVDD is stable. If using the internal
reference to drive the ADC, the ref_on must be set to ‘1’ to enable the internal reference buffer.
ref_on = 0
ADC Reference
Internal Reference
(2.5 V)
External
Reference
DAC and Temp Sensor
Reference
DAC0
10-b
DACOUT0
DACOUT1
DACOUT2
DACOUT3
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DAC1
10-b
ADC
10-b
DAC2
10-b
DAC3
10-b
Temperature
Sensor
Figure 31. External ADC Reference
ref_on = 1
Internal Reference
(2.5 V)
C>4.7 mF
(Minimize
inductance to pin)
ADC Reference
DAC and Temp Sensor
Reference
DAC0
10-b
DACOUT0
DACOUT1
DACOUT2
DACOUT3
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DAC1
10-b
DAC2
10-b
ADC
10-b
DAC3
10-b
Temperature
Sensor
Figure 32. Internal ADC Reference
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DAC OPERATION
The AMC7891 contains 4 independent DACs that provide analog control with 10 bits of resolution using an
internal reference. Each DAC core consists of a 10-bit string DAC and an output voltage buffer.
The DAC latch stores the code that determines the output voltage from the DAC string. The code is transferred
from the DACn_data registers to the DACn data latches when the internal DAC load signal is generated.
dacn_data
Register Value
DACn
Data Latch
10-bit
Resistor String
V
OUT
DACOUTn
DAC Load (1)
(1) Internal DAC load is generated by writing '1' to the dac_load bit in synchronous mode. In
asynchronous mode, the DAC latch is transparent.
Figure 33. DAC Block Diagram
The resistor string structure is shown in Figure 34. It consists of a string of resistors, each of value R. The code
loaded to the DAC Latch determines at which node on the string the voltage is tapped off to be fed into the
output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier.
This architecture has inherent monotonicity, voltage output, and low glitch. It is also linear because all the
resistors are of equal value.
R
R
To Output
R
Amplifier
R
R
Figure 34. Resistor String
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DAC OUTPUT
The full-scale output range of each DAC is set by the product of the internal reference voltage times a fixed gain
of 2 in the DAC output buffer (2 × VREF). The full-scale output range of each DAC is limited by the analog power
supply. The maximum and minimum outputs from the DAC cannot exceed AVDD or be lower than AGND,
respectively.
After power-on or a reset event, the DAC output buffers are in power-down mode. In this mode all dacn_data
registers and DACn data latches are set to their default values, the output buffers are in a high-impedance state
and each DACoutn output pin connects to AGND through an internal 10 kΩ resistor.
DOUBLE-BUFFERED DAC DATA REGISTERS
There are 4 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data is initially written to the individual DACn_data register as the value dacn_data[9:0] and then
transferred to its corresponding DACn latch. When the DACn latch is updated, the output from pin DACoutn
changes to the newly set value. When the host reads from DACn_data, the value held in the DACn latch is
returned (not the value held in the data register).
The DACs update mode is determined by the dacn_sync setting in the DAC_sync register. When dacn_sync is
cleared to ‘0’, the DACn is in asynchronous mode. In asynchronous mode, a write to the DACn_data register
results in an immediate update of the DACn latch and corresponding DACoutn output.
Synchronous mode is selected by setting dacn_sync to ‘1’. In synchronous mode writing to the DACn_data
register does not update the DACn latch DACout_n output. Instead, the update occurs only until the dac_load bit
(AMC_config register, bit 11) is set to ‘1’. By setting the DAC_sync register properly, several DACs can be
updated at the same time.
Table 6. DAC Output Modes
WRITING TO
dac_load
MODE
dacn_sync
OPERATION
Asynchronous
0
Don’t care
Update DACn individually. The DACn latch and DACoutn output are immediately
updated after writing to DACn_data.
Synchronous
1
1
Simultaneously update all DACs by internal trigger. Writing ‘1’ to dac_load generates
an internal load DAC trigger signal that updates the DACn latches and DACoutn
outputs with the contents of the corresponding dacn_data[9:0] register values.
The AMC7891 updates the DAC latches only if it has been accessed since the last time dac_load was issued,
thereby eliminating any unnecessary glitch. Any DAC channels that have not been accessed are not reloaded
again. When the DAC latch is updated, the corresponding output changes to the new level immediately.
CLEAR DACS
Each DAC can be cleared using the DAC_clear register. When setting the corresponding dacn_clear bit to ‘1’,
DACn goes to a clear state in which the DACoutn is immediately updated with the predefined value in the
DACn_clear register, regardless of the dacn_sync status. The data register value dacn_data[9:0] does not
change.
When the DAC goes back to normal operation, the DACoutn output is set back to the DACn latch value
regardless of the dac_sync status.
dacn_data
Register Value
DACn
Data Latch
0
DACn
1
dacn_clear
Register Value
dacn_clear
Figure 35. Clear DAC Operation
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AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
www.ti.com
GENERAL PURPOSE INPUT/OUTPUT PINS
The AMC7891 has twelve GPIO pins. Each GPIO provides a bidirectional, digital I/O signal. These pins can
receive an input or produce an output as configured by the GPIO_config register.
To configure the GPIOxx pin as an output, the corresponding ioxx_io bit needs to be set to ‘1’. The GPIOxx is an
output driver with a pull to the value of the corresponding ioxx_out bit in register GPIO_out.
To set the GPIOxx pin as an input, the corresponding ioxx_io bit has to be cleared to ‘0’. In this mode the
GPIOxx pin is in high-impedance state and the read value is stored in the corresponding ioutxx_in bit in register
GPIO_in. When set as an input, writes to the GPIO_out register do not affect the GPIO values.
After a power-on or reset event, all the GPIO pins are set as inputs and, hence in high-impedance state.
POWER-UP SEQUENCE
After all supplies are established, serial communication with the AMC7891 is valid only after a 200 µs power-up
reset delay. Following this, a software reset should be issued to ensure proper operation of the AMC7891. A
software reset is issued by writing the value ‘0x6600’ to reset[15:0] in register AMC_reset. Communication to the
AMC7891 is re-established after a 200 µS delay from the reset operation (measured from the rising edge of CS
establishing the end of the reset command frame).
At power-up or after a software-reset command all registers are set to the default values (see Table 6). The
default state of all analog blocks is off as determined by the default value of the AMC_power register.
For the device to work properly, AVDD must power up before applying any inputs to the GPIO pins. In addition, if
using an external ADC reference AVDD must power up before the external reference voltage is applied to the
REF pin.
The following power-up sequence is recommended for the AMC7891.
1. No input should be applied to the GPIO pins. Also, if using an external ADC reference, it should not be
applied to the REF pin.
2. Supply all voltages (AVDD, GPIOVDD and SPIVDD). If possible, it is recommended to apply IOVDD before
AVDD. However, the supplies can be powered up simultaneously or in any order with no detrimental effect to
the device.
3. After AVDD has been applied there is a 200 µs power-up reset delay. No serial communication should be
attempted during this time.
4. Issue a software-reset command by writing the value ‘0x6600’ to reset[15:0] in register AMC_reset.
5. Wait at least 200 µs from the rising edge of CS to complete the software-reset.
6. Program the registers according to the desired mode of operation.
32
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Product Folder Link(s): AMC7891
AMC7891
www.ti.com
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
APPLICATION INFORMATION
BASE STATION AMPLIFIER MONITOR AND CONTROL
The AMC7891 is a highly integrated, low-power, complete analog monitoring and control system in a small
package; all of these features make the AMC7891’s an ideal low-cost, bias control circuit for modern RF
transistor modules such as the power amplifiers (PA) and low-noise amplifiers (LNA) found in RF communication
systems.
The AMC7891 is used in RF amplifier signal chains to set the transistor’s optimal bias condition as well as to
monitor for any possible malfunction. The AMC7891 four independent DAC outputs allow control of the
transistor’s gate bias voltages as well as of any variable-gain amplifiers (VGAs) in the signal chain. The
AMC7891 twelve configurable GPIOs enable digital signal control and monitoring. Additionally, the device has 8
uncommitted analog inputs driving a highly precise ADC and an accurate on-chip temperature sensor that allow
continuous monitoring of the main factors determining optimal amplifier operation such as temperature, supply
voltages as well as drain bias currents through external current shunt monitors. The use of external current shunt
monitors gives the system designer the flexibility to choose the optimal number of current measurements for the
amplifier topology as well as the accuracy, voltage range and gain setting according to the drain current level to
be measured. The Texas Instruments’ INA282 family, which includes the INA282, INA283, INA284, INA285 and
INA286 devices, are highly-accurate, wide common-mode range current shunt monitors with gains going from
50V/V to 1000V/V.
The circuit in Figure 36 shows a typical multi-stage Doherty PA monitoring and control system using the
AMC7891. The AMC7891 DAC outputs are used to set the bias gate voltage of each LDMOS transistor in the PA
as well as to set the gain of the VGA driving the PA. The AMC7891 ADC inputs are used to monitor the most
important parameters in the PA operation: supply voltages, drain bias currents as well as the TX and RX signal
power. The GPIOs give additional system flexibility. In the system example below three GPIOs are used to
address an external 8:1 multiplexer used for giving additional inputs to the AMC7891 ADC.
CS
SCLK
SDI
AMC7891
SPI
DAC
µController
SDO
DAC
DAC
DAC
DAV
ADC
TEMP
SENSOR
MUX
GPIO
Digital I/O
VGA
Pre-amplifier
Doherty Amplifier
RF In
VDD
Carrier PA
Bidirectional Coupler
RF Out
Peak PA
Figure 36. PA Monitor and Control System
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AMC7891
SBAS518A –AUGUST 2011–REVISED DECEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (August 2011) to Revision A
Page
•
•
•
Changed from a 3 page Product Preview To a Prodcution Data Sheet ............................................................................... 1
Added the TYPICAL CHARACTERISTICS: DAC section .................................................................................................. 10
Added the TYPICAL CHARACTERISTICS: ADC section .................................................................................................. 12
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Product Folder Link(s): AMC7891
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
AMC7891SRHHR
AMC7891SRHHT
ACTIVE
ACTIVE
VQFN
VQFN
RHH
RHH
36
36
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC7891SRHHR
AMC7891SRHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
AMC7891SRHHR
AMC7891SRHHT
VQFN
VQFN
RHH
RHH
36
36
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
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