AWR1243FBIGABLRQ1 [TI]
76GHz 至 81GHz 高性能汽车类 MMIC | ABL | 161 | -40 to 125;
| 型号： | AWR1243FBIGABLRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 76GHz 至 81GHz 高性能汽车类 MMIC | ABL | 161 | -40 to 125 |
| 文件： | 总52页 (文件大小：2272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AWR1243
ZHCSHS1D –MAY 2017 –REVISED DECEMBER 2021
AWR1243 单芯片77GHz 和79GHz FMCW 收发器
• 符合功能安全标准
1 特性
– 专为功能安全应用开发
– 文档有助于使ISO 26262 功能安全系统设计满
足ASIL-D 级要求
– 硬件完整性高达ASIL-B 级
– 安全相关认证
• FMCW 收发器
– 集成PLL、发送器、接收器、基带和ADC
– 76GHz 至81GHz 的覆盖范围，具有4GHz 的可
用带宽
• 经TUV SUD 进行ISO 26262 认证达到ASIL
B 级
• 符合AEC-Q100 标准
• 器件高级特性
– 四个接收通道
– 三个发送通道（可以同时使用两个通道）
– 基于分数N PLL 的超精确线性调频脉冲引擎
– TX 功率：12dBm
– RX 噪声系数：
– 嵌入式自监控，无需使用主机处理器
– 复基带架构
– 嵌入式干扰检测功能
• 电源管理
• 14dB（76 至77GHz）
• 15dB（77 至81GHz）
– 1MHz 时的相位噪声：
– 内置LDO 网络，可增强PSRR
– I/O 支持双电压3.3V/1.8V
• 时钟源
• –95dBc/Hz（76 至77GHz）
• –93dBc/Hz（77 至81GHz）
• 内置校准和自检
– 支持外部驱动、频率为40MHz 的时钟（方波/正
弦波）
– 支持40MHz 晶体与负载电容器相连接
• 轻松的硬件设计
– 内置固件(ROM)
– 针对工艺和温度进行自校准的系统
• 主机接口
– 通过SPI 与外部处理器进行控制连接
– 通过MIPI D-PHY 和CSI2 V1.1 与外部处理器进
行数据连接
– 0.65mm 间距、161 引脚10.4mm × 10.4mm 覆
晶BGA 封装，可实现轻松组装和低成本PCB
设计
– 用于故障报告的中断
– 小尺寸解决方案
• 运行条件
– 结温范围：–40°C 至125°C
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS188
AWR1243
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ZHCSHS1D –MAY 2017 –REVISED DECEMBER 2021
• 自动紧急刹车
• 自适应巡航控制
2 应用
• 用于测量距离、速度和角度的汽车传感器
• 自动公路驾驶
Crystal
Power Management
RX1
RX2
Antenna
Structure
SPI/I2C
RX3
External
MCU
Interface to
External
Peripherals
RX4
mmWave Sensor
CSI2 (4 Lane Data + 1 Clock lane)
TX1
TX2
Reset
Error
TX3
MCU Clock
图2-1. 适用于汽车应用的自主雷达传感器
3 说明
AWR1243 器件是一款能够在76 至81GHz 频带内运行的集成式单芯片FMCW 收发器。该器件在极小的封装中实
现了出色的集成度。AWR1243 是适用于汽车领域中的低功耗、自监控、超精确雷达系统的理想解决方案。
AWR1243 器件是一种自包含FMCW 收发器单芯片解决方案，能够简化76 至81GHz 频带中的汽车雷达传感器实
施。它基于 TI 的低功耗 45nm RFCMOS 工艺构建，从而实现了一个具有内置 PLL 和 ADC 转换器的单片实施
3TX、4RX 系统。简单编程模型更改可支持各种传感器实施（近距离、中距离和远距离），并且能够进行动态重
新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，其中包括 TI 参考设计、软件
驱动程序、示例配置、API 指南以及用户文档。
器件信息
器件型号(2)
AWR1243FBIGABLQ1
AWR1243FBIGABLRQ1
封装(1)
托盘/卷带包装
封装尺寸
托盘
FCBGA (161)
10.4mm × 10.4mm
卷带包装
(1) 如需更多信息，请参阅节13 机械、封装和可订购信息。
(2) 如需更多信息，请参阅节12.1，器件命名规则。
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4 Functional Block Diagram
图4-1 shows the functional block diagram of the device.
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Digital Front-end
(Decimation filter
chain)
ADC output
interface
ADC Buffer
CSI2
16KB PING/PONG
PA
û-
û-
û-
Phase
Shifter
Control (A)
Synth
(20 GHz)
Ramp Generator
PA
PA
x4
Host control
interface
Synth Cycle
Counter
SPI/I2C
RF Control / BIST
Temp(B)
GPADC
Osc.
VMON
RF/Analog Subsystem
Digital
A. Phase Shift Control:
0° / 180° BPM for AWR1243
B. Internal temperature sensor accuracy is ± 7 °C.
•
图4-1. Functional Block Diagram
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Table of Contents
9.1 Overview...................................................................33
9.2 Functional Block Diagram.........................................33
9.3 Subsystems.............................................................. 34
9.4 Other Subsystems.................................................... 37
10 Monitoring and Diagnostics....................................... 39
10.1 Monitoring and Diagnostic Mechanisms................. 39
11 Applications, Implementation, and Layout............... 42
11.1 Application Information............................................42
11.2 Short-, Medium-, and Long-Range Radar ..............42
11.3 Reference Schematic..............................................43
12 Device and Documentation Support..........................44
12.1 Device Nomenclature..............................................44
12.2 Tools and Software................................................. 45
12.3 Documentation Support.......................................... 45
12.4 支持资源..................................................................45
12.5 Trademarks.............................................................46
12.6 Electrostatic Discharge Caution..............................46
12.7 术语表..................................................................... 46
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagram................................................................ 8
7.2 Signal Descriptions................................................... 12
8 Specifications................................................................ 16
8.1 Absolute Maximum Ratings...................................... 16
8.2 ESD Ratings............................................................. 16
8.3 Power-On Hours (POH)............................................17
8.4 Recommended Operating Conditions.......................17
8.5 Power Supply Specifications.....................................18
8.6 Power Consumption Summary................................. 19
8.7 RF Specification........................................................20
8.8 Thermal Resistance Characteristics for FCBGA
Information.................................................................... 47
13.1 Packaging Information............................................ 47
13.2 Tray Information for ................................................47
Package [ABL0161].....................................................21
8.9 Timing and Switching Characteristics....................... 21
9 Detailed Description......................................................33
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5 Revision History
Changes from May 1, 2020 to December 8, 2021 (from Revision C (May 2020) to Revision D
(December 2021))
Page
• 通篇：进行了更新，以反映功能安全合规性及相关认证资料.............................................................................. 1
• 通篇：将“A2D”替换为“ADC”；将“主子系统”和“主R4F”更改为“主要子系统”和“主要R4F”；在
主/从术语方面改用了更具包容性的措辞..............................................................................................................1
•
•
•
（特性）：提及了毫米波传感器的额定工作温度范围.........................................................................................1
（应用）：修订了图示并更新了应用链接...........................................................................................................2
（器件信息）：从表格中删除了可订购的预量产器件型号(XA1243FPBGABL) 及其相关特性.......................... 2
• Updated/Changed Functional Block Diagram to remove XA1243FPBGABL OPN specific features................. 3
• (Device Comparison) : Removed a row on Functionaly-Safety compliance and instead added a table-note for
this and LVDS Interface; modified the existing table-note on simultaneous TX operation; Additional
information on Device security added.................................................................................................................6
• (Device Comparison) : Updated/Changed RF Specification Receiver from "Max real sampling rate (Msps)" to
"Max real/complex 2x sampling rate (Msps)"; and "Max complex sampling rate (Msps)" to "Max complex 1x
sampling rate (Msps)".........................................................................................................................................6
• (Signal Descriptions): Removed XA1243FPBGABL OPN specific pin functions; updated descriptions for
CLKP and CLKM pins for Reference Oscillator................................................................................................12
• (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and
a table-note for the signal level applied on TX..................................................................................................16
• (Power Supply Specifications): Updated/Changed footnote in 表8-1 ............................................................. 18
• (Maximum Current Rating at Power Terminals): Updated footnotes section to add estimation assumption for
VIOIN rail.......................................................................................................................................................... 19
• (Average Power Consumption at Power Terminals): Removed 3TX, 4RX power numbers since only 2TX are
operational simultaneously in the device..........................................................................................................19
• (RF Specification): Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "ADC
sampling rate (complex 1x)"; and "A2D sampling rate (real)" to "ADC sampling rate (real/complex 2x)"........ 20
• (RF Specification): Updated/Changed the table to remove XA1243FPBGABL specific features.....................20
• (Synchronized Frame Triggering): Updated the maximum pulse width to 4ns................................................. 22
• (Clock Specifications): Updated/Changed 表8-6 to reflect correct device operating temperature range........ 24
• (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppm..24
• (Switching Characteristics for Output Timing versus Load Capacitance): Updated/Modified the table to
remove Slew Rate = 1 condition; removed a footnote......................................................................................30
• 图9-1: Updated the figure to remove XA1243FPBGABL OPN specific features. ........................................... 33
• (Monitoring and Diagnostic Mechanisms): Added a new section..................................................................... 39
• (Reference Schematics) : Added weblinks to AWR1243 EVM documentation collateral ................................43
• (Device Nomenclature):Updated/changed Device Nomenclature ................................................................... 44
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6 Device Comparison
FUNCTION
AWR1243(1)
AWR1443
AWR1642
AWR1843
Number of receivers
Number of transmitters
On-chip memory
4
3
4
3
4
2
4
3
576KB
5
1.5MB
5
2MB
10
—
15
Max I/F (Intermediate Frequency) (MHz)
Max real/complex 2x sampling rate (Msps)
Max complex 1x sampling rate (Msps)
Device Security(2)
37.5
18.75
12.5
6.25
—
12.5
6.25
Yes
25
12.5
Yes
—
Processor
MCU (R4F)
Yes
Yes
Yes
Yes
Yes
—
—
DSP (C674x)
—
Peripherals
Serial Peripheral Interface (SPI) ports
Quad Serial Peripheral Interface (QSPI)
Inter-Integrated Circuit (I2C) interface
Controller Area Network (DCAN) interface
CAN-FD
1
1
2
2
Yes
1
Yes
1
Yes
1
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
Trace
—
PWM
—
—
Hardware In Loop (HIL/DMM)
—
—
GPADC
Yes
Yes
—
LVDS/Debug(3)
Yes
Yes
CSI2
—
—
—
—
Hardware accelerator
1-V bypass mode
Yes
Yes
Yes
Yes
—
Yes
Yes
Cascade (20-GHz sync)
JTAG
—
—
2
—
Yes
2
—
Yes
2
—
Yes
3(4)
Yes
Number of Tx that can be simultaneously used
Per chirp configurable Tx phase shifter
—
—
—
PRODUCT PREVIEW (PP),
Product
ADVANCE INFORMATION (AI),
status(5)
PD
PD
PD
PD
or PRODUCTION DATA (PD)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation
for more details.
(2) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part
variants as indicated by the Device Type identifier in Section 3, Device Information table.
(3) The LVDS interface is not a production interface and is only used for debug.
(4) 3 Tx Simultaneous operation is supported only in AWR1843 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply
needs to be fed on the VOUT PA pin. Rest of the other devices only support simultaneous operation of 2 Transmitters.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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6.1 Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors
TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for automotive
applications.
Automotive
mmWave Sensors
TI’s automotive mmWave sensor portfolio offers high-performance radar front end to
ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable
sensor portfolio enables design and development of ADAS system solution for every
performance, application and sensor configuration ranging from comfort functions to
safety functions in all vehicles.
Companion
Products for
AWR1243
Review products that are frequently purchased or used in conjunction with this product.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
图 7-1 shows the pin locations for the 161-pin FCBGA package. 图 7-2, 图 7-3, 图 7-4, and 图 7-5 show the
same pins, but split into four quadrants.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOUT
_14APLL
VOUT
_14SYNTH
OSC
_CLKOUT
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
VSSA
VSSA
FM_CW
_SYNCIN1
VIN
_18CLK
VIN
_18VCO
FM_CW
_CLKOUT
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VSSA
VSSA
VBGAP
VSSA
VSSA
VIN
_13RF2
ANAMUX
VSENSE
VSSA
VSSA
VSSA
VSSA
VSSA
FM_CW
_SYNCOUT
VIN
_13RF2
VIOIN
_18DIFF
FM_CW
_SYNCIN2
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
RX4
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VDDIN
Reserved
TDI
CLKP
CLKM
VSSA
VIN_18BB
VSS
VSS
VSS
VIN
_13RF1
CSI2
_TXM[0]
CSI2
_TXP[0]
G
H
J
VSSA
RX3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VIN
_13RF1
CSI2
_TXM[1]
CSI2
_TXP[1]
VSS
VIN
_13RF1
VSSA
RX2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDO
CSI2_CLKM
CSI2_CLKP
CSI2
_TXM[2]
CSI2
_TXP[2]
K
L
VIN_18BB
VSS
VIOIN_18
CSI2
_TXM[3]
CSI2
_TXP[3]
VSSA
RX1
VSS
VSS
TMS
HS_M
_Debug1
HS_P
_Debug1
M
N
P
R
TCK
WARM
_RESET
HS_M
_Debug2
HS_P
_Debug2
VSSA
GPIO[0]
Reserved
Reserved
RS232_RX
RS232_TX
GPIO[1]
NERROR_OUTMCU_CLK_OUT
Sync_in
QSPI[3]
VDDIN
Sync_out
QSPI[0]
GPIO[2]
Analog Test 1 Analog Test 2 Analog Test 3
MISO_1 SPI_HOST_INTR_NERROR_IN
QSPI_CS
MOSI_1
QSPI[1]
NRESET PMIC_CLK_OUT
VNWA
VDDIN
Analog Test 4
VSSA
Reserved
Reserved
VDDIN
SPI_CS_1
SPI_CLK_1
QSPI_CLK
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
图7-1. Pin Diagram
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1
2
3
4
5
6
7
8
A
B
C
D
E
F
VSSA
VOUT_PA
VSSA
VSSA
VSSA
FM_CW
_SYNCIN1
VOUT_PA
VSSA
VSSA
TX1
VSSA
VSSA
TX2
VSSA
VSSA
TX3
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
FM_CW
_SYNCOUT
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
RX4
VIN_18BB
VIN
_13RF1
G
VSSA
VSSA
VSS
VSS
VSS
Not to scale
1
2
4
3
图7-2. Top Left Quadrant
9
10
11
12
13
14
15
VOUT
_14APLL
VOUT
_14SYNTH
OSC
_CLKOUT
A
VSSA
VSSA
VIN
_18CLK
VIN
_18VCO
FM_CW
_CLKOUT
B
C
D
E
F
VSSA
VSSA
VBGAP
VSSA
VSSA
ANAMUX
VSENSE
VSSA
VIOIN
_18DIFF
FM_CW
_SYNCIN2
VSS
VSS
VSS
VSSA
VDDIN
CLKP
CLKM
VSSA
VSS
CSI2
_TXM[0]
CSI2
_TXP[0]
G
VSS
Reserved
Not to scale
1
3
2
4
图7-3. Top Right Quadrant
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1
2
3
4
5
6
7
8
VIN
_13RF1
H
RX3
VSSA
VSS
VIN
_13RF1
J
VSSA
VSSA
RX2
VSSA
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
K
L
VIN_18BB
VSSA
VSSA
RX1
VSS
VSS
M
N
P
R
VSSA
VSSA
GPIO[0]
Reserved
Reserved
RS232_RX
RS232_TX
GPIO[1]
NERROR_OUT
Analog Test 1 Analog Test 2 Analog Test 3
MISO_1 SPI_HOST_INTR_NERROR_IN
QSPI_CS
Analog Test 4
VSSA
Reserved
Reserved
VDDIN
SPI_CS_1
MOSI_1
Not to scale
1
3
2
4
图7-4. Bottom Left Quadrant
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9
10
11
12
13
14
15
CSI2
_TXM[1]
CSI2
_TXP[1]
H
J
VSS
VSS
TDI
VSS
VSS
VSS
TDO
VIOIN_18
TMS
CSI2_CLKM
CSI2_CLKP
CSI2
_TXM[2]
CSI2
_TXP[2]
K
L
VSS
VSS
CSI2
_TXM[3]
CSI2
_TXP[3]
HS_M
_Debug1
HS_P
_Debug1
M
N
P
R
TCK
WARM
_RESET
HS_M
_Debug2
HS_P
_Debug2
MCU_CLK_OUT
Sync_in
QSPI[3]
VDDIN
Sync_out
QSPI[0]
GPIO[2]
QSPI[1]
NRESET PMIC_CLK_OUT
VNWA
VDDIN
SPI_CLK_1
QSPI_CLK
QSPI[2]
VIOIN
VIN_SRAM
VSS
Not to scale
1
3
2
4
图7-5. Bottom Right Quadrant
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7.2 Signal Descriptions
节7.2.1 lists the pins by function and describes that function.
备注
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;
hence, care needs to be taken that they are not driven externally without the VIO supply being present
to the device.
7.2.1 Signal Descriptions
PIN
PIN
DEFAULT PULL
STATUS(1)
FUNCTION
SIGNAL NAME
DESCRIPTION
NUMBER TYPE
TX1
B4
B6
O
O
O
I
Single-ended transmitter1 o/p
Single-ended transmitter2 o/p
Single-ended transmitter3 o/p
Single-ended receiver1 i/p
Single-ended receiver2 i/p
Single-ended receiver3 i/p
Single-ended receiver4 i/p
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Transmitters
TX2
TX3
B8
RX1
M2
RX2
K2
I
Receivers
RX3
H2
I
RX4
F2
I
CSI2_TXP[0]
CSI2_TXM[0]
CSI2_CLKP
CSI2_CLKM
CSI2_TXP[1]
CSI2_TXM[1]
CSI2_TXP[2]
CSI2_TXM[2]
CSI2_TXP[3]
CSI2_TXM[3]
HS_DEBUG1_P
HS_DEBUG1_M
HS_DEBUG2_P
HS_DEBUG2_M
FM_CW_CLKOUT
FM_CW_SYNCOUT
FM_CW_SYNCIN1
FM_CW_SYNCIN2
G15
G14
J15
J14
H15
H14
K15
K14
L15
L14
M15
M14
N15
N14
B15
D1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential data Out –Lane 0 (for CSI and LVDS
debug interface)
Differential clock Out (for CSI and LVDS debug
interface)
Differential data Out –Lane 1 (for CSI and LVDS
debug interface)
Differential data Out –Lane 2 (for CSI and LVDS
debug interface)
CSI2 TX
Differential data Out –Lane 3 (for CSI and LVDS
debug interface)
Differential debug port 1 (for LVDS debug interface)
Differential debug port 2 (for LVDS debug interface)
Reserved Signal. Not applicable in AWR1243.
Reserved Signal. Not applicable in AWR1243.
O
I
—
—
Reserved
Space
B1
D15
Reference clock output from clocking subsystem
after cleanup PLL. Can be used by peripheral chip in
multichip cascading
Reference clock OSC_CLKOUT
SYNC_OUT
A14
P11
N10
O
O
I
—
Low-frequency frame synchronization signal output.
Can be used by peripheral chip in multichip
cascading
Pull Down
Pull Down
System
synchronization
Low-frequency frame synchronization signal input.
This signal could also be used as a hardware trigger
for frame start
SYNC_IN
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FUNCTION
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PIN
PIN
DEFAULT PULL
STATUS(1)
SIGNAL NAME
DESCRIPTION
NUMBER TYPE
SPI_CS_1
R7
R9
R8
P5
P6
I
I
Pull Up
Pull Down
Pull Up
SPI chip select
SPI clock
SPI control
interface from
external MCU
(default
peripheral
mode)
SPI_CLK_1
MOSI_1
I
SPI data input
SPI data output
SPI interrupt to host
MISO_1
O
O
Pull Up
SPI_HOST_INTR_1
Pull Down
R3, R4, R5,
P4
RESERVED
NRESET
—
—
P12
I
Power on reset for chip. Active low
Open-drain fail-safe warm reset signal. Can be
driven from PMIC for diagnostic or can be used as
status signal that the device is going through reset.
Reset
WARM_RESET(2)
N12
IO
Open Drain
SOP2
P13
P11
I
I
The SOP pins are driven externally (weak drive) and
the AWR device senses the state of these pins
during bootup to decide the bootup mode. After boot
the same pins have other functionality.
[SOP2 SOP1 SOP0] = [0 0 1] →Functional SPI
mode
Sense on Power SOP1
SOP0
—
J13
I
[SOP2 SOP1 SOP0] = [1 0 1] →Flashing mode
[SOP2 SOP1 SOP0] = [0 1 1] →debug mode
Open-drain fail-safe output signal. Connected to
PMIC/Processor/MCU to indicate that some severe
criticality fault has happened. Recovery would be
through reset.
NERROR_OUT
N8
P7
O
I
Open Drain
Open Drain
Safety
JTAG
Fail-safe input to the device. Error output from any
other device can be concentrated in the error
signaling monitor module inside the device and
appropriate action can be taken by firmware
NERROR_IN
TMS
TCK
TDI
L13
M13
H13
J13
I
I
Pull Up
Pull Down
Pull Up
—
JTAG port for TI internal development
I
TDO
O
In XTAL mode: Input for the reference crystal
In External clock mode: Single ended input
reference clock port
CLKP
E14
I
—
Reference
oscillator
In XTAL mode: Feedback drive for the reference
crystal
In External clock mode: Connect this port to ground
CLKM
F14
B10
O
O
—
—
Band-gap
voltage
VBGAP
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PIN
PIN
DEFAULT PULL
STATUS(1)
FUNCTION
SIGNAL NAME
DESCRIPTION
NUMBER TYPE
F13,N11,P15
POW
VDDIN
1.2-V digital power supply
—
,R6
VIN_SRAM
VNWA
R14
P14
POW
POW
1.2-V power rail for internal SRAM
—
—
1.2-V power rail for SRAM array back bias
I/O supply (3.3-V or 1.8-V): All CMOS I/Os would
operate on this supply.
VIOIN
R13
POW
—
VIOIN_18
K13
B11
POW
POW
POW
POW
POW
POW
POW
POW
1.8-V supply for CMOS IO
1.8-V supply for clock module
1.8-V supply for CSI2 port
No connect
—
—
—
—
—
—
—
—
VIN_18CLK
VIOIN_18DIFF
Reserved
D13
G13
VIN_13RF1
VIN_13RF2
VIN_18BB
G5,J5,H5
C2,D2
K5,F5
B12
1.3-V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
1.8-V Analog baseband power supply
1.8-V RF VCO supply
VIN_18VCO
E5,E6,E8,E1
0,E11,F9,F1
1,G6,G7,G8,
G10,H7,H9,
Power supply
VSS
H11,J6,J7,J8 GND
,J10,K7,K8,K
9,K10,K11,L
5,L6,L8,L10,
R15
Digital ground
—
A1,A3,A5,A7
,A9,A15,B3,
B5,B7,B9,B1
3,B14,C1,C3
,C4,C5,C6,C
7,C8,C9,C15
,E1,E2,E3,E GND
13,E15,F3,G
1,G2,G3,H3,
J1,J2,J3,K3,
L1,L2,L3,
VSSA
Analog ground
—
M3,N1,N2,N
3,R1
VOUT_14APLL
A10
A13
O
O
—
—
VOUT_14SYNTH
When internal PA LDO is used this pin provides the
output voltage of the LDO. When the internal PA
LDO is bypassed and disabled 1V supply should be
fed on this pin. This is mandatory in 3TX
simultaneous use case.
Internal LDO
output/inputs
VOUT_PA
A2,B2
IO
—
PMIC_CLK_OUT
MCU_CLK_OUT
P13
N9
O
O
Dithered clock input to PMIC
—
—
External clock
out
Programmable clock given out to external MCU or
the processor
GPIO[0]
GPIO[1]
GPIO[2]
N4
N7
IO
IO
IO
Pull Down
Pull Down
Pull Down
General-purpose IO
General-purpose IO
General-purpose IO
General-
purpose I/Os
N13
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FUNCTION
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PIN
PIN
DEFAULT PULL
STATUS(1)
SIGNAL NAME
QSPI_CS
DESCRIPTION
NUMBER TYPE
Chip-select output from the device. Device is a
controller connected to serial flash peripheral.
P8
O
O
Pull Up
Clock output from the device. Device is a controller
connected to serial flash peripheral.
QSPI_CLK
R10
Pull Down
QSPI for Serial
Flash
QSPI[0]
QSPI[1]
QSPI[2]
QSPI[3]
RS232_TX
R11
P9
IO
IO
IO
IO
O
Pull Down
Pull Down
Pull Up
Data IN/OUT
Data IN/OUT
Data IN/OUT
Data IN/OUT
R12
P10
N6
Pull Up
Flash
Pull Down
programming
and RS232
UART
UART pins for programming external flash
RS232_RX
N5
I
Pull Up
Analog Test1
Analog Test2
Analog Test3
Analog Test4
ANAMUX
P1
P2
IO
IO
IO
IO
IO
IO
Internal test signal
Internal test signal
Internal test signal
Internal test signal
Internal test signal
Internal test signal
—
—
—
—
—
—
Test and Debug
output for
preproduction
phase. Can be
pinned out on
production
P3
R2
C13
C14
hardware for
field debug
VSENSE
(1) Status of PULL structures associated with the IO after device POWER UP.
(2) For the AWR1243 WARM_RESET can be used as an output only pin for status indication.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
PARAMETERS(1) (2)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VDDIN
1.2 V digital power supply
1.4
1.4
1.4
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
VIOIN
3.8
V
–0.5
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for CSI2 port
2
2
2
V
V
V
–0.5
–0.5
–0.5
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
1.45
V
–0.5
1-V Internal LDO bypass mode. Device supports mode where
external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
1.4
V
–0.5
VIN_13RF2
VIN_18BB
VIN_18VCO supply
RX1-4
1.8-V Analog baseband power supply
1.8-V RF VCO supply
2
V
–0.5
–0.5
2
V
Externally applied power on RF inputs
Externally applied power on RF outputs(3)
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
10
10
dBm
dBm
TX1-3
VIOIN + 0.3
VIOIN + 20% up to
–0.3V
Input and output
voltage range
V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
20% of signal period
CLKP, CLKM
Clamp current
Input ports for reference crystal
2
V
–0.5
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
20
mA
–20
TJ
Operating junction temperature range
125
150
°C
°C
–40
–55
TSTG
Storage temperature range after soldered onto PC board
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on
the TX output.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All other pins
Corner pins
V
Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Power-On Hours (POH)
JUNCTION
OPERATING
TEMPERATURE (Tj)
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
CONDITION
(1) (2)
600 (6%)
2000 (20%)
6500 (65%)
900 (9%)
–40°C
75°C
100% duty cycle
95°C
1.2
125°C
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard
terms and conditions for TI semiconductor products.
(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would
not be applicable, if the Tx gain table is overwritten using an API.
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.14
1.14
1.14
3.135
1.71
1.71
1.71
1.71
NOM
1.2
1.2
1.2
3.3
1.8
1.8
1.8
1.8
MAX
1.32
1.32
1.32
3.465
1.89
1.9
UNIT
VDDIN
1.2 V digital power supply
V
V
V
VIN_SRAM
VNWA
1.2 V power rail for internal SRAM
1.2 V power rail for SRAM array back bias
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
VIOIN
V
VIOIN_18
1.8 V supply for CMOS IO
1.8 V supply for clock module
1.8 V supply for CSI2 port
V
V
V
VIN_18CLK
VIOIN_18DIFF
VIN_13RF1
VIN_13RF2
1.9
1.9
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
VIN_13RF1
(1-V Internal LDO
bypass mode)
0.95
1
1.05
V
VIN_13RF2
(1-V Internal LDO
bypass mode)
VIN18BB
1.8-V Analog baseband power supply
1.8V RF VCO supply
1.71
1.71
1.17
2.25
1.8
1.8
1.9
1.9
V
V
VIN_18VCO
Voltage Input High (1.8 V mode)
Voltage Input High (3.3 V mode)
Voltage Input Low (1.8 V mode)
Voltage Input Low (3.3 V mode)
High-level output threshold (IOH = 6 mA)
Low-level output threshold (IOL = 6 mA)
VIL (1.8V Mode)
VIH
VIL
V
V
0.3*VIOIN
0.62
VOH
VOL
mV
mV
VIOIN –450
450
0.2
VIH (1.8V Mode)
0.96
1.57
NRESET
SOP[2:0]
V
VIL (3.3V Mode)
0.3
VIH (3.3V Mode)
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8.5 Power Supply Specifications
表8-1 describes the four rails from an external power supply block of the AWR1243 device.
表8-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, CSI2
1.8 V
1.3 V (or 1 V in internal
LDO bypass mode)(1)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
(1) The device only supports simultanoeus operation of 2 transmitters. In the 1-V LDO bypass mode, 1V supply needs to be fed on the
VOUT PA pin.
The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in 表 8-2 are defined to meet a target
spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship,
for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms
levels for a sinusoidal input applied at the specified frequency.
表8-2. Ripple Specifications
RF RAIL
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
1.3 V (µVRMS
)
1.8 V (µVRMS)
(µVRMS
)
137.5
275
7
5
648
76
22
4
83
21
11
6
550
3
1100
2200
4400
6600
2
11
13
22
82
93
117
13
19
29
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8.6 Power Consumption Summary
表8-3 and 表8-4 summarize the power consumption at the power terminals.
表8-3. Maximum Current Ratings at Power Terminals
PARAMETER
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Total current drawn by all
nodes driven by 1.2V rail
VDDIN, VIN_SRAM, VNWA
500
Total current drawn by all
nodes driven by 1.3V (or
1V in LDO Bypass mode)
rail
VIN_13RF1, VIN_13RF2
2000
850
Current consumption(1)
mA
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by all
nodes driven by 1.8V rail
Total current drawn by all
nodes driven by 3.3V
rail(2)
VIOIN
50
(1) The specified current values are at typical supply voltage level.
(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.
表8-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
MIN
TYP
MAX UNIT
1.0-V internal
LDO bypass
mode
1TX, 4RX
2TX, 4RX
1TX, 4RX
2TX, 4RX
1.62
1.79
1.80
2.01
Sampling: 16.66 MSps complex
Transceiver, 40-ms frame time, 512
chirps, 512 samples/chirp, 8.5-μs
interchirp time (50% duty cycle)
Data Port: MIPI-CSI-2
Average power
consumption
W
1.3-V internal
LDO enabled
mode
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8.7 RF Specification
over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETER
MIN
TYP
14
15
–8
48
24
2
MAX UNIT
76 to 77 GHz (VCO1)
77 to 81 GHz (VCO2)
Noise figure
dB
1-dB compression point (Out Of Band)(1)
Maximum gain
dBm
dB
Gain range
dB
Gain step size
dB
Image Rejection Ratio (IMRR)
IF bandwidth(2)
30
dB
15 MHz
ADC sampling rate (real/complex 2x)
ADC sampling rate (complex 1x)
ADC resolution
37.5 Msps
18.75 Msps
Receiver
12
<–10
±0.5
±3
Bits
dB
dB
°
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS
In-band IIP2
16
24
dBm
dBm
RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm
Out-of-band IIP2
Idle Channel Spurs
Output power
dBFS
dBm
–90
12
Transmitter
Amplitude noise
Frequency range
Ramp rate
dBc/Hz
–145
76
81 GHz
100 MHz/µs
Clock
subsystem
76 to 77 GHz (VCO1)
77 to 81 GHz (VCO2)
–95
–93
Phase noise at 1-MHz offset
dBc/Hz
(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off
frequency.
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set
of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
HPF2
175, 235, 350, 700
350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
•
•
Less than ±0.5 dB pass-band ripple/droop, and
Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
图8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.
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18
16
14
12
10
8
-18
NF (dB)
In-band P1DB (dBm)
-24
-30
-36
-42
-48
30
32
34
36
38 40
RX Gain (dB)
42
44
46
48
图8-1. Noise Figure, In-band P1dB vs Receiver Gain
8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
THERMAL METRICS(1)
°C/W(2) (3)
5
Junction-to-case
RΘJC
RΘJB
RΘJA
RΘJMA
PsiJT
5.9
Junction-to-board
21.6
15.3 (4)
0.69
5.8
Junction-to-free air
Junction-to-moving air
Junction-to-package top
Junction-to-board
PsiJB
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(4) Air flow = 1 m/s
8.9 Timing and Switching Characteristics
8.9.1 Power Supply Sequencing and Reset Timing
The AWR1243 device expects all external voltage rails and SOP lines to be stable before reset is deasserted. 图
8-2 describes the device wake-up sequence.
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SOP
Setup
Time
SOP
Hold time to
nRESET
DC power
MSS
BOOT
START
nRESET
ASSERT
tPGDEL
DC
Power
notOK
Stable before
nRESET
release
DC
Power
OK
QSPI
READ
VDDIN,
VIN_SRAM
VNWA
VIOIN_18
VIN18_CLK
VIOIN_18DIFF
VIN18_BB
VIN_13RF1
VIN_13RF2
VIOIN
SOP[2.1.0]
nRESET
Warm reset
delay for crystal
or ext osc
WARMRESET
OUTPUT
VBGAP
OUTPUT
CLKP, CLKM
Using Crystal
MCUCLK
OUTPUT (1)
QSPI_CS
OUTPUT
7ms (XTAL Mode)
500 µs (REFCLK Mode)
图8-2. Device Wake-up Sequence
8.9.2 Synchronized Frame Triggering
The AWR1243 device supports a hardware based mechanism to trigger radar frames. An external host can
pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of the
external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional
programmable delay that the user can set to control the frame start time.
The periodicity of the external SYNC_IN pulse should be always greater than the programmed frame periodic in
the frame configurations in all instances.
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Tactive_frame
SYNC_IN
(Hardware
Trigger)
Radar
Frames
Tpulse
Tlag
Frame-2
Frame-1
图8-3. Sync In Hardware Trigger
表8-5. Frame Trigger Timing
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
Tactive_frame
Tpulse
Active frame duration
User defined
25
ns
4000
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8.9.3 Input Clocks and Oscillators
8.9.3.1 Clock Specifications
An external crystal is connected to the device pins. 图8-4 shows the crystal implementation.
Cf1
CLKP
Cp
40 MHz
CLKM
Cf2
图8-4. Crystal Implementation
备注
The load capacitors, Cf1 and Cf2 in 图 8-4, should be chosen such that 方程式 1 is satisfied. CL in the
equation is the load specified by the crystal manufacturer. All discrete components used to implement
the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and
CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.
C f2
CL = C f1
´
+CP
C
f1 +C f2
(1)
表8-6 lists the electrical characteristics of the clock crystal.
表8-6. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
fP
Parallel resonance crystal frequency
40
CL
Crystal load capacitance
Crystal ESR
5
8
12
ESR
50
Ω
Temperature range Expected temperature range of operation
125
°C
–40
Frequency
Crystal frequency tolerance(1) (2)
tolerance
200
200
ppm
µW
–200
Drive level
50
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM
is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. 表 8-7 lists
the electrical characteristics of the external clock signal.
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表8-7. External Clock Mode Specifications
SPECIFICATION
PARAMETER
UNIT
MIN
TYP
MAX
Frequency
40
MHz
mV (pp)
ns
AC-Amplitude
700
1200
10
DC-trise/fall
Phase Noise at 1 kHz
Phase Noise at 10 kHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
Duty Cycle
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
%
–132
–143
–152
–153
65
Input Clock:
External AC-coupled sine wave or DC-
coupled square wave
Phase Noise referred to 40 MHz
35
Freq Tolerance
100
ppm
–100
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8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.9.4.1 Peripheral Description
The SPI uses a MibSPI Protocol by TI.
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream to be shifted
into and out of the device at a programmed bit-transfer rate. The MibSPI/SPI is normally used for communication
between the microcontroller and external peripherals or another microcontroller.
节 8.9.4.1.2 and 节 8.9.4.1.3 assume the operating conditions stated in 节 8.9.4.1.1. 节 8.9.4.1.2, 节 8.9.4.1.3,
and 图8-5 describe the timing and switching characteristics of the MibSPI.
8.9.4.1.1 SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
tF
Input rise time
Input fall time
1
1
3
3
ns
ns
Output Conditions
CLOAD Output load capacitance
2
15
pF
8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
NO.
1
PARAMETER
Cycle time, SPICLK
MIN
25
TYP
MAX
UNIT
ns
tc(SPC)S
2
tw(SPCH)S
Pulse duration, SPICLK high
10
ns
3
tw(SPCL)S
Pulse duration, SPICLK low
10
ns
4
td(SPCL-SOMI)S
th(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low
Hold time, SPISOMI data valid after SPICLK low
10
ns
5
2
ns
8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
NO.
MIN
3
TYP
MAX UNIT
6
7
tsu(SIMO-SPCH)S
th(SPCH-SIMO)S
Setup time, SPISIMO before SPICLK high
ns
ns
Hold time, SPISIMO data valid after SPICLK high
1
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图8-5. SPI Peripheral Mode External Timing
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8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
1. Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI
clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
图8-6 shows the SPI communication timing of the typical interface protocol.
图8-6. SPI Communication
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8.9.5 LVDS Interface Configuration
The AWR1243 supports seven differential LVDS IOs/Lanes to support debug where raw ADC data could be
extracted. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane
(LVDS_CLKP/M) one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data
rates:
• 900 Mbps (450 MHz DDR Clock)
• 600 Mbps (300 MHz DDR Clock)
• 450 Mbps (225 MHz DDR Clock)
• 400 Mbps (200 MHz DDR Clock)
• 300 Mbps (150 MHz DDR Clock)
• 225 Mbps (112.5 MHz DDR Clock)
• 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
图8-7. LVDS Interface Lane Configuration And Relative Timings
8.9.5.1 LVDS Interface Timings
表8-8. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Duty Cycle Requirements
max 1 pF lumped capacitive load on
LVDS lanes
48%
52%
Output Differential Voltage
peak-to-peak single-ended with 100 Ω
resistive load between differential pairs
250
450
mV
Output Offset Voltage
Trise and Tfall
1125
1275
mV
ps
20%-80%, 900 Mbps
900 Mbps
330
80
Jitter (pk-pk)
ps
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Trise
LVDS_CLK
Clock Jitter = 6sigma
LVDS_TXP/M
LVDS_FRCLKP/M
1100 ps
图8-8. Timing Parameters
8.9.6 General-Purpose Input/Output
节8.9.6.1 lists the switching characteristics of output timing relative to load capacitance.
8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
PARAMETER(1)
TEST CONDITIONS
CL = 20 pF
VIOIN = 1.8V
VIOIN = 3.3V
UNIT
2.8
6.4
9.4
2.8
6.4
9.4
3.0
6.9
tr
Max rise time
CL = 50 pF
CL = 75 pF
CL = 20 pF
CL = 50 pF
CL = 75 pF
ns
10.2
2.8
tf
Max fall time
6.6
ns
9.8
(1) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
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8.9.7 Camera Serial Interface (CSI)
The CSI is a MIPI D-PHY compliant interface for connecting this device to a camera receiver module. This
interface is made of four differential lanes; each lane is configurable for carrying data or clock. The polarity of
each wire of a lane is also configurable. 节 8.9.7.1, 图 8-9, 图 8-10, and 图 8-11 describe the clock and data
timing of the CSI.The clock is always ON once the CSI IP is enabled. Hence it remains in HS mode.
8.9.7.1 CSI Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
HPTX
HSTXDBR
fCLK
Data bit rate
(1/2/4 data lane PHY)
(1/2/4 data lane PHY)
150
75
600 Mbps
DDR clock frequency
300
50
MHz
mV
UI
Common-level variation
ΔVCMTX(LF)
tR and tF
LPTX DRIVER
tEOT
–50
20% to 80% rise time and fall time
0.3
Time from start of THS-TRAIL period to start of LP-11 state
105 +
12*UI
ns
DATA-CLOCK Timing Specification
UINOM
Nominal Unit Interval
1.67
1.131
13.33
ns
ns
UIINST,MIN
TSKEW[TX]
Minimum instantaneous Unit Interval
Data to clock skew measured at transmitter
0.15 UIINST,
MIN
–0.15
CSI2 TIMING SPECIFICATION
TCLK-PRE
Time that the HS clock shall be driven by the transmitter before
any associated data lane beginning the transition from LP to HS
mode.
8
38
ns
TCLK-PREPARE
Time that the transmitter drives the clock lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission.
95
ns
TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state
before starting the clock.
300
ns
ns
ns
TEOT
Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL
,
105 ns
+ 12*UI
to the start of the LP-11 state following a HS burst.
THS-PREPARE
Time that the transmitter drives the data lane LP-00 line state
immediately before the HS-0 line state starting the HS
transmission
40 + 4*UI
85 +
6*UI
THS-PREPARE + THS-ZERO
THS-PREPARE + time that the transmitter drives the HS-0 state prior
to transmitting the Sync sequence.
145 ns +
10*UI
ns
THS-EXIT
Time that the transmitter drives LP-11 following a HS burst.
100
ns
ns
THS-TRAIL
Time that the transmitter drives the flipped differential state after
last payload data bit of a HS transmission burst
max(8*UI, 60
ns + 4*UI)
TLPX
TXXXransmitted length of any low-power state period
50
ns
CSI2_CLK(P/M)
0.5UI + Tskew
CSI2_TX(P/M)
1 UI
图8-9. Clock and Data Timing in HS Transmission
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Clock
Lane
Data Lane
Dp/Dn
TLPX
THS-ZERO
THS-SYNC
Disconnect
Terminator
VOH
THS-PREPARE
VIH(min)
VIL(max)
VOL
TREOT
Capture
1st Data Bit
TD-TERM-EN
THS-SKIP
TEOT
THS-TRAIL
LP-11
LP-11
LP-01
LP-00
THS-SETTLE
THS-EXIT
LOW-POWER TO
HIGH-SPEED
TRANSITION
START OF
HS-ZERO TRANSMISSION
SEQUENCE
HIGH-SPEED TO
HS-TRAIL LOW-POWER
TRANSITION
HIGH-SPEED DATA
TRANSMISSION
图8-10. High-Speed Data Transmission Burst
Disconnect
Terminator
Clock Lane
Dp/Dn
T
CLK-SETTLE
VIH(min)
VIL(max)
T
LPX
T
T
CLK-PRE
CLK-ZERO
T
CLK-PREPARE
Data Lane
Dp/Dn
T
HS-PREPARE
Disconnect
Terminator
T
LPX
VIH(min)
VIL(max)
T
HS-SKIP
T
HS-SETTLE
A. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
图8-11. Switching the Clock Lane Between Clock Transmission and Low-Power Mode
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9 Detailed Description
9.1 Overview
The AWR1243 device is a single-chip highly integrated 77-GHz transceiver and front end that includes three
transmit and four receive chains. The device can be used in long-range automotive radar applications such as
automatic emergency braking and automatic adaptive cruise control. The AWR1243 has extremely small form
factor and provides ultra-high resolution with very low power consumption. This device, when used with the
TDA3X or TD2X, offers higher levels of performance and flexibility through a programmable digital signal
processor (DSP); thus addressing the standard short-, mid-, and long-range automotive radar applications.
9.2 Functional Block Diagram
LNA
LNA
LNA
LNA
IF
IF
IF
IF
ADC
ADC
ADC
ADC
Digital Front-end
(Decimation filter
chain)
ADC output
interface
ADC Buffer
16KB PING/PONG
CSI2
PA
û-
û-
û-
Phase
Shifter
Control (A)
Synth
(20 GHz)
Ramp Generator
PA
PA
x4
Host control
interface
Synth Cycle
Counter
SPI/I2C
RF Control / BIST
Temp(B)
GPADC
Osc.
VMON
RF/Analog Subsystem
Digital
A. Phase Shift Control:
0° / 180° BPM for AWR1243
B. Internal temperature sensor accuracy is ± 7 °C.
•
图9-1. Functional Block Diagram
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9.3 Subsystems
9.3.1 RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,
IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit
channels can be operated simultaneously for transmit beamforming purpose as required; whereas the four
receive channels can all be operated simultaneously.
Please note that AWR1243 device supports simultaneous operation of 2 transmitters only.
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9.3.1.1 Clock Subsystem
The AWR1243 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has a
built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF
synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.
The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective
sensor operation.
The output of the RF synthesizer is available at the device pin boundary for multichip cascaded configuration.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the
quality of the generated clock.
图9-2 describes the clock subsystem.
RX LO
x4
MULT
TX LO
SYNC_OUT
SYNC_IN
Timing
Engine
RFSYNTH
Lock Detect
SoC Clock
Clean-Up
PLL
XO /
Slicer
CLK Detect
40 MHz
* These pins are 20GHz LO input pins. Connect LO to one pin while grounding the
other pin.
图9-2. Clock Subsystem
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9.3.1.2 Transmit Subsystem
The AWR1243 transmit subsystem consists of three parallel transmit chains, each with independent phase and
amplitude control. A maximum of two transmit chains can be operational at the same time, however all three
chains can be operated together in a time-multiplexed fashion. The device supports binary phase modulation for
MIMO radar and interference mitigation.
Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also
support programmable backoff for system optimization.
图9-3 describes the transmit subsystem.
Loopback Path
Fine Phase Shifter Control
PCB
6 bits
12dBm
@ 50 Ω
û-
LO
0/180°
(from Timing Engine)
Self Test
图9-3. Transmit Subsystem (Per Channel)
9.3.1.3 Receive Subsystem
The AWR1243 receive subsystem consists of four parallel channels. A single receive channel consists of an
LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the
same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the AWR1243 device supports a complex baseband architecture, which
uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver
channel. The AWR1243 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff
frequencies above 175 kHz and can support bandwidths up to 15 MHz.
图9-4 describes the receive subsystem.
Self Test
DAC
Loopback
Path
DSM
PCB
I
RSSI
50 W
GSG
LO
Q
DSM
DAC
图9-4. Receive Subsystem (Per Channel)
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9.3.2 Host Interface
The AWR1243 device communicates with the host radar processor over the following main interfaces:
• Reference Clock –Reference clock available for host processor after device wakeup
• Control –4-port standard SPI (peripheral) for host control along with HOST INTR pin for async events.. All
radio control commands (and response) flow through this interface.
• Data –High-speed serial port following the MIPI CSI2 format. Four data and one clock lane (all differential).
Data from different receive channels can be multiplexed on a single data lane to optimize board routing. This
is a unidirectional interface used for data transfer only.
• Reset –Active-low reset for device wakeup from host
• Out-of-band interrupt
• Error –Used for notifying the host in case the radio controller detects a fault
9.4 Other Subsystems
9.4.1 ADC Data Format Over CSI2 Interface
The AWR1243 device uses MIPI D-PHY / CSI2-based format to transfer the raw ADC samples to the external
MCU. This is shown in 图9-5.
• Supports four data lanes
• CSI-2 data rate scalable from 150 Mbps to 600 Mbps per lane
• Virtual channel based
• CRC generation
Normal Mode
Frame Period
Acquisition Period
Frame
Ramp/Chirp
1
2
3
N
Data Ready
F
L
H
L
L
H
L
L
H
L
L
H
L
F
S
S
S
E
S
S
E
S
S
E
S
S
E
E
Short
Packet
Short
Packet
Long
Packet
Short
Packet
ST SP ET
LPS
ST SP ET
.5μs-.8μs
ST PH
DATA
PF ET LPS
ST SP ET
LPS
LPS
Chirp 1 data
Data rate/Lane should be such that "Chirp + Interchirp" period
should be able to accommodate the data transfer
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Frame Start –CSi2 VSYNC Start Short PacketLine Start –CSI2 HSYNC Start Short PacketLine End –CSI2 HSYNC End Short
PacketFrame End –CSi2 VSYNC End Short Packet
图9-5. CSI-2 Transmission Format
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The data payload is constructed with the following three types of information:
• Chirp profile information
• The actual chirp number
• ADC data corresponding to chirps of all four channels
– Interleaved fashion
• Chirp quality data (configurable)
The payload is then split across the four physical data lanes and transmitted to the receiving D-PHY. The data
packet packing format is shown in 图9-6
First
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CH Chirp
Profile
Channel
Number
NU
NU
NU
NU
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
5
1
11
CH Chirp
Profile
Channel
Number
Chirp Num
11
Channel 0 Sample 0 i
Channel 1 Sample 0 i
Channel 2 Sample 0 i
Channel 3 Sample 0 i
Channel 0 Sample 1 i
Channel 1 Sample 1 i
Channel 2 Sample 1 i
Channel 3 Sample 1 i
CQ Data [11:0]
Channel 0 Sample 0 q
11
Channel 1 Sample 0 q
11
Channel 2 Sample 0 q
11
Channel 3 Sample 0 q
11
Channel 0 Sample 1 q
11
Channel 1 Sample 1 q
11
Channel 2 Sample 1 q
11
Channel 3 Sample 1 q
Continues till the
last sample. Max 1023
11
CQ Data [23:12]
11
CQ Data [35:24]
CQ Data [47:36]
11
CQ Data [59:48]
NU
CQ Data [63:60]
Last
图9-6. Data Packet Packing Format for 12-Bit Complex Configuration
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10 Monitoring and Diagnostics
10.1 Monitoring and Diagnostic Mechanisms
Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR1243.
MSS R4F is the processor used for running TI's Functional Firmware stored in the ROM that helps in the
execution of the API calls issued by the host processor (It is not a customer programmable core).
表10-1. Monitoring and Diagnostic Mechanisms for AWR1243
S No
Feature
Description
AWR1243 architecture supports hardware logic BIST (LBIST) engine self-test Controller
(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the MSS
R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level.
LBIST for the CPU and VIM are triggered by the bootloader.
Boot time LBIST For MSS
R4F Core and associated
VIM
1
MSS R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and
TCMB1. AWR1243 architecture supports a hardware programmable memory BIST (PBIST)
engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the
implemented MSS R4F TCMs at a transistor level.
PBIST for TCM memories is triggered by Bootloader at the boot time . CPU stays there in
while loop and does not proceed further if a fault is identified.
Boot time PBIST for MSS
R4F TCM Memories
2
3
TCMs diagnostic is supported by Single error correction double error detection (SECDED)
ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64-
bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme
provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU is
configured to have predetermined response (Ignore or Abort generation) to single and
double bit error conditions.
End to End ECC for MSS
R4F TCM Memories
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an
ECC fault.Further, bit multiplexing scheme implemented such that the bits accessed to
generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the
probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest
as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a
logical word, this scheme improves the usefulness of the TCM ECC diagnostic.
MSS R4F TCM bit
multiplexing
4
AWR1243 architecture supports Three Digital Clock Comparators (DCCs) and an internal
RCOSC. Dual functionality is provided by these modules –Clock detection and Clock
Monitoring.
DCCint is used to check the availability/range of Reference clock at boot otherwise the
device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This
provides debug capability). DCCint is only used by boot loader during boot time. It is
disabled once the APLL is enabled and locked.
5
Clock Monitor
DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided
version with the Reference input clock of the device. Initially (before configuring APLL),
DCC1 is used by bootloader to identify the precise frequency of reference input clock
against the internal RCOSC clock source. Failure detection for DCC1 would cause the
device to go into limp mode.
Clock Compare module (CCC) module is used to compare the APLL divided down
frequency with reference clock (XTAL). Failure detection is indicated by the nERROR OUT
signal.
Internal watchdog is enabled by the bootloader in a windowed watchdog (DWWD) mode..
Watchdog expiry issues an internal warm reset and nERROR OUT signal to the host.
6
7
RTI/WD for MSS R4F
MPU for MSS R4F
Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial
separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It
is expected that the operating system controls the MPU and changes the MPU settings
based on the needs of each task. A violation of a configured memory protection policy
results in a CPU abort.
AWR1243 architecture supports a hardware programmable memory BIST (PBIST) engine
for Peripheral SRAMs as well.
PBIST for Peripheral interface PBIST for peripheral SRAM memories is triggered by the bootloader. The PBIST tests are
8
SRAMs - SPI, I2C
destructive to memory contents, and as such are typically run only at boot time. .
Any fault detected by the PBIST results in an error indicated in PBIST and boot status
response message.
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表10-1. Monitoring and Diagnostic Mechanisms for AWR1243 (continued)
S No
Feature
Description
Peripheral interface SRAMs diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. When a single or double bit error is detected the error
is indicated by nERROR (double bit error) or via SPI message (single bit error).
ECC for Peripheral interface
SRAMs –SPI, I2C
9
Cyclic Redundancy Check (CRC) module is available for the Main SS. The firmware uses
this feature for data transfer checks in mailbox and SPI communication.
Cyclic Redundancy Check –
Main SS
10
11
AWR1243 architecture supports MPUs on Main SS DMAs. The firmware uses this for stack
protection.
MPU for DMAs
AWR1243 architecture supports hardware logic BIST (LBIST) even for BIST R4F core and
associated VIM module. This logic provides very high diagnostic coverage (>90%) on the
BIST R4F CPU core and VIM.
This is triggered by MSS R4F boot loader at boot time and it does not proceed further if the
fault is detected.
Boot time LBIST For BIST
R4F Core and associated
VIM
12
AWR1243 architecture supports a hardware programmable memory BIST (PBIST) engine
for BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST
R4F TCMs.
Boot time PBIST for BIST
R4F TCM Memories
13
14
15
PBIST is triggered at the power up of the BIST R4F.
BIST R4F TCMs diagnostic is supported by Single error correction double error detection
(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while
double bit error is communicated to MSS R4F as an interrupt which sends a async event to
the host.
End to End ECC for BIST
R4F TCM Memories
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults
resulting in logical multi-bit faults.
BIST R4F TCM bit
multiplexing
AWR1243 architecture supports various temperature sensors all across the device (next to
power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame
period.(1)
16
17
18
Temperature Sensors
Tx Power Monitors
AWR1243 architecture supports power detectors at the Tx output.(2)
When a diagnostic detects a fault, the error must be indicated. The AWR1243 architecture
provides aggregation of fault indication from internal monitoring/diagnostic mechanisms
using nERROR signaling or async event over SPI interface.
Error Signaling
Error Output
Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and
comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if
any, are detected and reported.
Synthesizer (Chirp) frequency
monitor
19
20
AWR1243 architecture supports a ball break detection mechanism based on Impedance
measurement at the TX output(s) to detect and report any large deviations that can indicate
a ball break.
Ball break detection for TX
ports (TX Ball break monitor) Monitoring is done by TIs code running on BIST R4F and failure is reported to the host.
It is completely up to customer SW to decide on the appropriate action based on the
message from BIST R4F.
Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,
inter-RX balance, etc.
21
22
23
RX loopback test
Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect
IF loopback test
failure.
Provision to detect ADC saturation due to excessive incoming signal level and/or
RX saturation detect
interference.
(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the
temperature sensed via API by customer application.
a. Report the temperature sensed after every N frames
b. Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
(2) Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
a. Report the power detected after every N frames
b. Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
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备注
Refer to the Device Safety Manual or other relevant collaterals for more details on applicability of all
diagnostics mechanisms. For certification details, refer to the device product folder.
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11 Applications, Implementation, and Layout
备注
Information in the following Applications section is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI's customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
11.1 Application Information
A typical application addresses the standard short-, mid-, long-range, and high-performance imaging radar
applications with this radar front end and external programmable MCU. 图 11-1 shows a short-, medium-, or
long-range radar application.
11.2 Short-, Medium-, and Long-Range Radar
Crystal
Power Management
Antenna
Structure
RX1
RX2
SPI
External
MCU
(For Example
TDA3x)
RX3
Automotive
Interface PHY
RX4
AWR1243
CSI2 (4 Lane Data + 1 Clock lane)
TX1
TX2
Reset
Error
TX3
MCU Clock
Copyright © 2017, Texas Instruments Incorporated
图11-1. Short-, Medium-, and Long-Range Radar
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11.3 Reference Schematic
The reference schematic and power supply information can be found in the AWR1243 EVM Documentation.
Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.
• Altium AWR1243 EVM Design Files
• AWR1243 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions follow.
12.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, AWR1243). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ABL0161 ALB0161), the temperature range (for example, blank is the default commercial
temperature range). 图12-1 provides a legend for reading the complete device name for any AWR1243 device.
For orderable part numbers of AWR1243 devices in the ABL0161 package types, see the Package Option
Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AWR1243 Device Errata .
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1
2
43
B
I
AWR
G
ABL
Q1
Qualification
Q1 = AEC-Q100
Blank = no special Qual
Prefix
XA = Pre-Production
AWR = Production
Generation
Tray or Tape & Reel
R = Big Reel
Blank = Tray
1 = 76 œ 81 GHz
Variant
Package
ABL = BGA
2 = FE
4 = FE + FFT + MCU
6 = FE + MCU + DSP
8 = FE + FFT + MCU + DSP
Security
Num RX/TX Channels
G = General
S = Secure
D = Development Secure
RX = 1,2,3,4
TX = 1,2,3
Silicon PG Revision
Blank = Rev 1.0
E = Rev 2.0
Temperature (Tj)
C = 0°C to 70°C
K = œ40°C to 85°C
A = œ40°C to 105°C
I = œ40°C to 125°C
F = Rev 3.0
Features
Blank = Baseline
Safety
B = Functional Safety Complaint, ASIL-B
图12-1. Device Nomenclature
12.2 Tools and Software
Development Tools
AWR1243 cascade application note
Describes TI's cascaded mmWave radar system.
Models
AWR1243 BSDL model
AWR1x43 IBIS model
Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
AWR1243 checklist for
schematic review, layout
review, bringup/wakeup
A set of steps in spreadsheet form to select system functions and pinmux options.
Specific EVM schematic and layout notes to apply to customer engineering. A
bringup checklist is suggested for customers.
12.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral follows.
Errata
AWR1243 device errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
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链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
13.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
13.2 Tray Information for
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
AWR1243FBIGABLQ1
AWR1243FBIGABLRQ1
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
FCCSP
FCCSP
ABL
161
161
176
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
AWR1243
Samples
Samples
IG
964FC
ACTIVE
ABL
1000 RoHS & Green
Call TI
-40 to 125
AWR1243
IG
964FC
ABL G1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AWR1243FBIGABLQ1
ABL
FCCSP
161
176
8 x 22
150
315 135.9 7620 13.4
16.8
17.2
Pack Materials-Page 1
GENERIC PACKAGE VIEW
ABL 161
10.4 x 10.4, 0.65 mm pitch
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225978/A
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