AWR6843ABGABLRQ1_技术文档

AWR6843

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AWR6843 Single-Chip 60- to 64-GHz mmWave Sensor

•

Other interfaces available to user application

– Up to 6 ADC channels (low sample rate

monitoring)

1 Features

•

FMCW transceiver

– Integrated PLL, transmitter, receiver, Baseband,

and A2D

– Up to 2 SPI ports

– Up to 2 UARTs

– 60- to 64-GHz coverage with 4-GHz continuous

bandwidth

– 2 CAN-FD interfaces

– I2C

– Four receive channels

– Three transmit channels

– Supports 6-bit phase shifter

– Ultra-accurate chirp engine based on fractional-

N PLL

– GPIOs

– 2 lane LVDS interface for raw ADC data and

debug instrumentation

•

Functional Safety-Compliant targeted

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Hardware integrity up to ASIL-B targeted

– Safety-related certification ISO 26262

certification by TUV Sud planned

Non-Functional safety variants

AEC-Q100 qualified

– TX power: 12 dBm

– RX noise figure:

•

12 dB

– Phase noise at 1 MHz:

–93 dBc/Hz

•

Built-in calibration and self-test

– ARM^®Cortex^®-R4F-based radio control system

– Built-in firmware (ROM)

•

Power management

– Self-calibrating system across frequency and

temperature

– Embedded self-monitoring with no host

processor involvement on Functional Safety-

Compliant targeted devices

C674x DSP for advanced signal processing

Hardware accelerator for FFT, filtering, and CFAR

processing

Memory compression

ARM-R4F microcontroller for object detection, and

interface control

– Supports autonomous mode (loading user

application from QSPI flash memory)

Internal memory with ECC

– Built-in LDO network for enhanced PSRR

– I/Os support dual voltage 3.3 V/1.8 V

Clock source

– 40.0 MHz crystal with internal oscillator

– Supports external oscillator at 40 MHz

– Supports externally driven clock (square/sine)

at 40 MHz

•

Easy hardware design

•

– 0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip

chip BGA package for easy assembly and low-

cost PCB design

– Small solution size

Supports automotive temperature operating range

•

– 1.75 MB, divided into MSS program RAM (512

KB), MSS data RAM (192 KB), DSP L1RAM

(64KB) and L2 RAM (256 KB), and L3 radar

data cube RAM (768 KB)

– Technical reference manual includes allowed

size modifications

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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•

Gesture detection

Driver vital sign monitoring

Kick sensor/access sensor

2 Applications

•

Interior Cabin sensing

Child presence detection

Occupancy detection

Seat belt reminder

3 Description

The AWR6843 is an integrated single chip mmWave sensor based on FMCW radar technology capable of

operation in the 60-GHz to 64-GHz band. It is built with TI’s low power45-nm RFCMOS process and enables

unprecedented levels of integration in an extremely small formfactor. The AWR6843 is an ideal solution for low

power, self-monitored, ultra-accurate radar systems in the automotive space. Multiple automotive qualified

variants are currently available including Functional Safety-Compliant targeted devices and non-functional safety

devices.

Device Information

BODY SIZE

PART NUMBER

PACKAGE⁽¹⁾

FCBGA (161)

TRAY / TAPE AND REEL

AWR6843AQGABLRQ1

AWR6843AQGABLQ1

AWR6843ABGABLRQ1

AWR6843ABGABLQ1

10.4 mm × 10.4mm

Tape and Reel (Non-Functional Safety)

Tray (Non-Functional Safety)

Tape and Reel (Functional Safety-Compliant targeted, ASIL-B)

Tray (Functional Safety-Compliant targeted, ASIL-B)

(1) For more information, see Section 12 , Mechanical, Packaging, and Orderable information.

2

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4 Functional Block Diagram

Figure 4-1 shows the functional block diagram of the device.

Serial Flash Interface

QSPI

Cortex R4F

@ 200MHz

LNA

IF

ADC

Optional External

MCU Interface

SPI

(User Programmable)

Digital

Front-End

PMIC Control

SPI / I2C

CAN-FD

UARTs

Prog RAM

(512kB)

Data RAM

(192kB)

Boot

ROM

(Decimation

Filter Chain)

Primary Communication

Interfaces (Automotive)

Radar Hardware Accelerator

(FFT, Log Mag, And Others)

DMA

Master Sub-System

(Customer Programmed)

Test/

Debug

JTAG For Debug/

Development

ADC

Buffer

PA

´Å

Mailbox

High-Speed ADC Output

Interface (For Recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

PA

x3

High-Speed Input For

Hardware-In-Loop Verification

C674x DSP

@ 600 MHz

Radio (BIST)

Processor

PA

GPADC

Osc.

6

(For RF Calibration

& Self-Test œ TI

Programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

Temp

DMA

CRC

Radar Data Memory

768 kB

Radio Processor

Sub-System

(TI Programmed)

DSP Sub-System

(Customer Programmed)

RF/Analog Sub-System

Figure 4-1. Functional Block Diagram

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SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................2

3 Description.......................................................................2

4 Functional Block Diagram.............................................. 3

Revision History................................................................. 5

5 Device Comparison.........................................................7

5.1 Related Products........................................................ 8

6 Terminal Configuration and Functions..........................9

6.1 Pin Diagram................................................................ 9

6.2 Pin Attributes.............................................................14

6.3 Signal Descriptions................................................... 22

7 Specifications................................................................ 27

7.1 Absolute Maximum Ratings...................................... 27

7.2 ESD Ratings............................................................. 27

7.3 Power-On Hours (POH)............................................28

7.4 Recommended Operating Conditions.......................29

7.5 Power Supply Specifications.....................................29

7.6 Power Consumption Summary................................. 30

7.7 RF Specification........................................................31

7.8 CPU Specifications................................................... 31

7.9 Thermal Resistance Characteristics for FCBGA

8 Detailed Description......................................................56

8.1 Overview...................................................................56

8.2 Functional Block Diagram.........................................56

8.3 Subsystems.............................................................. 57

8.4 Other Subsystems.................................................... 61

9 Monitoring and Diagnostics......................................... 63

9.1 Monitoring and Diagnostic Mechanisms................... 63

10 Applications, Implementation, and Layout............... 68

10.1 Application Information........................................... 68

10.2 Reference Schematic..............................................68

11 Device and Documentation Support..........................69

11.1 Device Nomenclature..............................................69

11.2 Tools and Software..................................................70

11.3 Documentation Support.......................................... 70

11.4 Support Resources................................................. 70

11.5 Trademarks............................................................. 71

11.6 Electrostatic Discharge Caution..............................71

11.7 Glossary..................................................................71

12 Mechanical, Packaging, and Orderable

Information.................................................................... 72

12.1 Packaging Information............................................ 72

12.2 Tray Information for ABL, 10.4 × 10.4 mm..............76

Package [ABL0161] ....................................................32

7.10 Timing and Switching Characteristics..................... 33

4

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Revision History

Changes from August 1, 2020 to September 30, 2020 (from Revision A (August 2020) to

Revision B (September 2020))

Page

•

Global: Updated/Changed AWR6843 Functional Safety-Compliant targeted Product Status from "Advance

Information (AI)" to "Production Data (PD)"........................................................................................................1

Features: Added "Embedded self-monitoring with no host processor involvement on Functional Safety-

compliant devices" .............................................................................................................................................1

Applications: Changed / Updated link for Interior Cabin Sensing ......................................................................2

Device Information: Added Functional Safety-Compliant targeted production parts AWR6843ABGABLR and

AWR6843ABGABL. Removed XA6843ABGABL................................................................................................2

Device Features Comparison: Changed/Updated ASIL-B variant product status to PD.................................... 7

RF Specification: (RF Specification): Updated/Changed the "1-db Compression Point …" footnote...............31

Section 7.9 (Thermal Resistance Characteristics for FCBGA Package [ABL0161]): Removed "A junction

temperature of 105°C is assumed." from footnote............................................................................................32

Section 9.1 (Monitoring and Diagnostic Mechanisms): Added Monitoring and Diagnostic Chapter.................63

Section 12.2 (Tray Information for ABL, 10.4 × 10.4 mm): Added new section with tray information...............72

•

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SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

Changes from April 30, 2020 to July 31, 2020 (from Revision * (April 2020) to Revision A (July

2020))

Page

•

Global: Updated/Changed the numbering format for tables, figures, and cross-references throughout the

document............................................................................................................................................................1

Global: Added Non-functional safety variants ....................................................................................................1

Features: Updated/Changed Phase Noise at 1 MHz from "–92 dBc/Hz" to "–93 dBc/Hz"................................. 1

Features: Updated/Changed RX noise figure: from "14 dB " to "12 dB".............................................................1

Features: Updated/Changed TX power: from "10 dBm" to "12 dBm".................................................................1

Description: Updated description/paragragh...................................................................................................... 2

Device Information: Added Non-Functional Safety production parts "AWR6843AQGABLRQ1" part number

(PD), "AWR6843AQGABLQ1" part number (PD) and "TRAY / TAPE AND REEL" column................................2

Figure 4-1: Updated block diagram.................................................................................................................... 3

Device Features Comparison: Added 2nd column under AWR6843 for non-functional safety variant ..............7

Signal Descriptions: Added Added NOTE about IO pins and GPIO state during power supply ramp. ............22

Recommended Operating Conditions: Updated/Changed MAX value of NRESET SOP [2:0], V_IL(1.8V Mode)

from 0.2 to 0.45 and V_IL(3.3V Mode) from 0.3 to 0.65.....................................................................................29

Power Supply Specifications: Added " Ripple Specifications" table and the preceeding paragraph. Added

table note for Power Supply Rails Characteristics............................................................................................29

Power Consumption Summary: Updated Average Power Consumption at Power Terminals and added table

notes.................................................................................................................................................................30

RF Specification: Updated table Receiver parameters and values ................................................................. 31

RF and Analog Subsystem: Updated/Changed section................................................................................... 57

Transmit Subsystem: Removed "Tx Beam forming applications and interference mitigation" from paragraph ...

59

•

Processor Subsystem: Updated/Changed figure to include the 2nd CAN instance ........................................ 60

Figure 11-1 Added "AWR = Production Automotive" under Prefix and "Q1 = AEC-Q100" under Qualification,

updated/changed the "Features" field to "R = Antenna on Package (AoP)" ....................................................69

6

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5 Device Comparison

Table 5-1. Device Features Comparison

FUNCTION

AWR6843

AWR1843

AWR1642

AWR1443

Antenna on Package (AOP)

Number of receivers

Number of transmitters

RF frequency range

On-chip memory

—

4

—

4

3⁽¹⁾

2

76 to 81 GHz

1.5MB

B-Targeted

—

3

60 to 64 GHz

76 to 81 GHz

1.75MB

—

2MB

B-Targeted

—

576KB

—

ASIL

B-Targeted

Non-Functional Safety

Max I/F (Intermediate Frequency) (MHz)

Max real sampling rate (Msps)

Max complex sampling rate (Msps)

Processors

—

10

Yes

10

Yes

5

10

5

25

12.5

6.25

12.5

6.25

MCU (R4F)

Yes

—

DSP (C674x)

Peripherals

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

Inter-Integrated Circuit (I²C) interface

Controller Area Network (DCAN) interface

Controller Area Network (CAN-FD) interface

Trace

2

1

Yes

1

Yes

1

Yes

1

Yes

1

Yes

1

—

1

2

1

—

Yes

—

Yes

—

Yes

—

Yes

—

PWM

—

Hardware In Loop (HIL/DMM)

GPADC

—

Yes

—

LVDS/Debug

CSI2

Hardware accelerator

1-V bypass mode

Yes

—

Yes

JTAG

Product Preview (PP),

Product

Advance Information (AI),

status

PD⁽²⁾

or Production Data (PD)

(1) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to

be fed on the VOUT PA pin.

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty.

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5.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less

power using the smallest footprint mmWave sensor portfolio for automotive applications.

Automotive

TI’s automotive mmWave sensor portfolio offers high-performance radar front end to

mmWave sensors ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable

sensor portfolio enables design and development of ADAS system solution for every

performance, application and sensor configuration ranging from comfort functions to

safety functions in all vehicles.

Companion

products for

AWR6843

Review products that are frequently purchased or used in conjunction with this product.

Reference designs TI Designs Reference Design Library is a robust reference design library spanning

for AWR6843

analog, embedded processor and connectivity. Created by TI experts to help you jump-

start your system design, all TI Designs include schematic or block diagrams, BOMs, and

design files to speed your time to market. Search and download designs at ti.com/

tidesigns.

Vehicle occupant

This reference design demonstrates the use of the AWR6843 60GHz single-chip

detection reference mmWave sensor with integrated DSP, as a Vehicle Occupant Detection (VOD) and Child

design

Presence Detection (CPD) Sensor enabling the detection of life forms in a vehicle. This

design provides a reference software processing chain which runs on the C674x DSP,

enabling the generation of a heat map to detect occupants in a Field of View (FOV) of

±60 degrees.

8

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6 Terminal Configuration and Functions

6.1 Pin Diagram

Figure 6-1 shows the pin locations for the 161-pin FCBGA package. Figure 6-2, Figure 6-3, Figure 6-4, and

Figure 6-5 show the same pins, but split into four quadrants.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

VOUT

_14APLL

OSC

_CLKOUT

VSSA

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

VOUT_

14SYNTH

VIN

_18CLK

VIN

_18VCO

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VSSA

VBGAP

VSSA

CLKP

CLKM

VIN

_13RF2

VSSA

GPADC5

VIOIN_

18DIFF

VIN

_13RF2

SPIA_MOSI

GPADC6

VSSA

RX4

VSSA

VSS

SPIA_CLK

SPIA_MISO

SPIB_CLK

SPIB_MISO

SPIA_CS_N

SPIB_MOSI

VIN_18BB

VSS

VIOIN

VIN

_13RF1

G

H

J

VSSA

RX3

VSSA

VSS

SYNC_OUT

GPIO_0

GPIO_1

GPIO_2

VPP

VIN_SRAM

VIN

_13RF1

VSSA

VSS

SPIB_CS_N

VDDIN

VIN

_13RF1

VSSA

RX2

VSSA

VSS

LVDS_TXP[0] LVDS_TXM[0]

LVDS_TXP[1] LVDS_TXM[1]

LVDS_CLKP LVDS_CLKM

K

L

VSSA

VIN_18BB

VSS

VSSA

RX1

VSSA

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

M

N

P

R

VSSA

NERROR

_OUT

MCU

_CLKOUT

WARM

_RESET

VSSA

GPADC1

VSSA

GPADC2

GPADC4

VSSA

RS232_RX

RS232_TX

GPIO_32

GPIO_33

NERROR_IN

GPIO_36

TMS

TCK

VDDIN

QSPI_CS_N

TDI

QSPI[1]

QSPI[3]

TDO

DMM_SYNC

GPIO_47

VDDIN

PMIC

_CLKOUT

SPI_HOST

_INTR

GPIO_34

VDDIN

GPADC3

NRESET

SYNC_IN

GPIO_31

GPIO_38

GPIO_37

VNWA

GPIO_35

VIOIN_18

VIOIN

QSPI_CLK

QSPI[0]

QSPI[2]

VSS

Not to scale

Figure 6-1. Pin Diagram

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1

2

3

4

5

6

7

8

A

B

C

D

E

F

VSSA

VOUT_PA

VSSA

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VIN

_13RF2

VSSA

VIN

_13RF2

VSSA

VSS

RX4

VIN_18BB

VIN

_13RF1

G

VSSA

VSS

Not to scale

1

3

2

4

Figure 6-2. Top Left Quadrant

10

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9

10

11

12

13

14

15

VOUT

OSC

A

B

C

D

E

F

VSSA

_14APLL

_CLKOUT

VIN

_18CLK

VIN

VOUT

VSSA

VBGAP

VSSA

CLKP

CLKM

_18VCO

_14SYNTH

GPADC5

SPIA_MOSI

SPIA_CLK

SPIB_MOSI

SYNC_OUT

VIOIN

_18DIFF

GPADC6

SPIA_MISO

SPIB_CLK

SPIB_MISO

SPIA_CS_N

VSS

VIOIN

VSS

VIN_SRAM

G

Not to scale

1

3

2

4

Figure 6-3. Top Right Quadrant

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1

2

3

4

5

6

7

8

VIN

_13RF1

H

RX3

VSSA

VSS

VIN

_13RF1

J

VSSA

VSS

K

L

RX2

VIN_18BB

VSSA

VSS

M

N

P

R

RX1

VSSA

NERROR

_OUT

MCU

_CLKOUT

VSSA

GPADC1

VSSA

RS232_RX

SYNC_IN

GPIO_31

RS232_TX

GPIO_32

GPIO_33

NERROR_IN

GPADC2

GPADC4

GPADC3

NRESET

GPIO_34

GPIO_36

GPIO_38

VDDIN

GPIO_35

GPIO_37

Not to scale

1

3

2

4

Figure 6-4. Bottom Left Quadrant

12

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9

10

11

12

13

14

15

H

J

VSS

GPIO_0

SPIB_CS_N

VDDIN

VSS

GPIO_1

GPIO_2

VPP

LVDS_TXP[0] LVDS_TXM[0]

LVDS_TXP[1] LVDS_TXM[1]

LVDS_CLKP LVDS_CLKM

K

L

VSS

LVDS

_FRCLKP

LVDS

_FRCLKM

M

N

P

R

WARM

_RESET

GPIO_47

VDDIN

TMS

TCK

VDDIN

QSPI_CS_N

TDI

QSPI[1]

QSPI[3]

QSPI_clk

TDO

DMM_SYNC

PMIC

_CLKOUT

SPI_HOST_

INTR_1

VNWA

VIOIN_18

VIOIN

QSPI[0]

QSPI[2]

VSS

Not to scale

1

3

2

4

Figure 6-5. Bottom Right Quadrant

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6.3 Signal Descriptions

Note

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe;

hence, care needs to be taken that they are not driven externally without the VIO supply being present

to the device.

Note

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should

be used to isolate the GPIO output from the radar device and a pull resister used to define the

required state in the application. The NRESET signal to the radar device could be used to control the

output enable (OE) of the tri-state buffer.

6.3.1 Signal Descriptions - Digital

SIGNAL NAME

BSS_UART_TX

PIN TYPE

DESCRIPTION

Debug UART Transmit [Radar Block]

BALL NO.

F14, H14, K13, N10, N13,

N4, N5, R8

O

CAN1_FD_RX

CAN1_FD_TX

CAN2_FD_RX

CAN2_FD_TX

DMM0

I

O

I

CAN1 FD (MCAN) Receive Signal

D13, F14, N10, N4, P12

CAN1 FD (MCAN) Transmit Signal

E14, H14, N5, P10, R14

CAN2 FD (MCAN) Receive Signal

E13

E15

R4

P5

IO

I

CAN2 FD (MCAN) Transmit Signal

Debug Interface (Hardware In Loop) - Data Line

Debug Interface (Hardware In Loop) - Clock

DMM1

I

DMM2

I

R5

P6

DMM3

I

DMM4

I

R7

P7

DMM5

I

DMM6

I

R8

P8

DMM7

I

DMM_CLK

I

N15

Debug Interface (Hardware In Loop) Mux Select between DMM1 and

DMM2 (Two Instances)

DMM_MUX_IN

I

G13, J13, P4

DMM_SYNC

DSS_UART_TX

EPWM1A

I

Debug Interface (Hardware In Loop) - Sync

Debug UART Transmit [DSP]

PWM Module 1 - Output A

N14

O

I

D13, E13, G14, P8, R12

N5, N8

EPWM1B

PWM Module 1 - Output B

H13, N5, P9

EPWM1SYNCI

EPWM2A

J13

O

IO

PWM Module 2- Output A

PWM Module 2 - Output B

H13, N4, N5, P9

EPWM2B

N4

R7

EPWM2SYNCO

EPWM3A

PWM Module 3 - Output A

N4

EPWM3SYNCO

GPIO_0

P6

General-purpose I/O

H13

J13

K13

E13

H14

F14

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

22

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SIGNAL NAME

SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

PIN TYPE

IO

O

DESCRIPTION

BALL NO.

P11

R12

R13

N12

R14

P12

P13

H13

N5

GPIO_6

General-purpose I/O

I2C Clock

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

N4

GPIO_16

J13

GPIO_17

P10

N10

D13

E14

F13

G14

R11

N13

N8

GPIO_18

GPIO_19

GPIO_20

GPIO_21

GPIO_22

GPIO_23

GPIO_24

GPIO_25

GPIO_26

K13

P9

GPIO_27

GPIO_28

P4

GPIO_29

G13

C13

R4

GPIO_30

GPIO_31

GPIO_32

P5

GPIO_33

R5

GPIO_34

P6

GPIO_35

R7

GPIO_36

P7

GPIO_37

R8

GPIO_38

P8

GPIO_47

N15

G14, N4

F13, N5

J14

I2C_SCL

I2C_SDA

I2C Data

LVDS_TXP[0]

LVDS_TXM[0]

LVDS_TXP[1]

LVDS_TXM[1]

LVDS_CLKP

LVDS_CLKM

LVDS_FRCLKP

LVDS_FRCLKM

MCU_CLKOUT

MSS_UARTA_RX

Differential data Out – Lane 0

Differential data Out – Lane 1

Differential clock Out

O

J15

O

K14

K15

L14

L15

M14

M15

O

Differential Frame Clock

O

Programmable clock given out to external MCU or the processor

Master Subsystem - UART A Receive

N8

I

F14, N4, R11

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SIGNAL NAME

MSS_UARTA_TX

MSS_UARTB_RX

PIN TYPE

DESCRIPTION

Master Subsystem - UART A Transmit

O

H14, N13, N5, R4

N4, P4

IO

Master Subsystem - UART B Receive

F14, H14, K13, N13, N5,

P10, P7

MSS_UARTB_TX

NDMM_EN

O

I

Master Subsystem - UART B Transmit

Debug Interface (Hardware In Loop) Enable - Active Low Signal

N13, N5

Failsafe input to the device. Nerror output from any other device can

be concentrated in the error signaling monitor module inside the

device and appropriate action can be taken by Firmware

NERROR_IN

I

N7

Open drain fail safe output signal. Connected to PMIC/

Processor/MCU to indicate that some severe criticality fault has

happened. Recovery would be through reset.

NERROR_OUT

O

N6

PMIC_CLKOUT

QSPI[0]

O

IO

I

Output Clock from AWR6843 device for PMIC

QSPI Data Line #0 (Used with Serial Data Flash)

QSPI Data Line #1 (Used with Serial Data Flash)

QSPI Data Line #2 (Used with Serial Data Flash)

QSPI Data Line #3 (Used with Serial Data Flash)

QSPI Clock (Used with Serial Data Flash)

QSPI Chip Select (Used with Serial Data Flash)

Debug UART (Operates as Bus Master) - Receive Signal

Debug UART (Operates as Bus Master) - Transmit Signal

Sense On Power - Line#0

H13, K13, P9

R13

QSPI[1]

N12

QSPI[2]

I

R14

QSPI[3]

I

P12

QSPI_CLK

QSPI_CLK_EXT

QSPI_CS_N

RS232_RX

RS232_TX

SOP[0]

O

I

R12

H14

O

I

P11

N4

O

I

N5

N13

SOP[1]

I

Sense On Power - Line#1

G13

SOP[2]

I

Sense On Power - Line#2

P9

SPIA_CLK

SPIA_CS_N

SPIA_MISO

SPIA_MOSI

SPIB_CLK

SPIB_CS_N

SPIB_CS_N_1

SPIB_CS_N_2

SPIB_MISO

SPIB_MOSI

SPI_HOST_INTR

SYNC_IN

IO

O

I

SPI Channel A - Clock

E13

SPI Channel A - Chip Select

E15

SPI Channel A - Master In Slave Out

SPI Channel A - Master Out Slave In

SPI Channel B - Clock

E14

D13

F14, R12

SPI Channel B Chip Select (Instance ID 0)

SPI Channel B Chip Select (Instance ID 1)

SPI Channel B Chip Select (Instance ID 2)

SPI Channel B - Master In Slave Out

SPI Channel B - Master Out Slave In

Out of Band Interrupt to an external host communicating over SPI

Low frequency Synchronization signal input

Low Frequency Synchronization Signal output

JTAG Test Clock

H14, P11

G13, J13, P13

G13, J13, N12

G14, R13

F13, N12

P13

P4

SYNC_OUT

TCK

O

I

G13, J13, K13, P4

P10

R11

N13

N10

N15

N14

R4

TDI

I

JTAG Test Data Input

TDO

O

I

JTAG Test Data Output

TMS

JTAG Test Mode Signal

TRACE_CLK

TRACE_CTL

TRACE_DATA_0

TRACE_DATA_1

TRACE_DATA_2

TRACE_DATA_3

TRACE_DATA_4

O

Debug Trace Output - Clock

Debug Trace Output - Control

Debug Trace Output - Data Line

P5

Debug Trace Output - Data Line

R5

Debug Trace Output - Data Line

P6

Debug Trace Output - Data Line

R7

24

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SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

PIN TYPE

DESCRIPTION

Debug Trace Output - Data Line

BALL NO.

P7

TRACE_DATA_5

TRACE_DATA_6

TRACE_DATA_7

FRAME_START

CHIRP_START

CHIRP_END

O

Debug Trace Output - Data Line

R8

Debug Trace Output - Data Line

P8

Pulse signal indicating the start of each frame

Pulse signal indicating the start of each chirp

Pulse signal indicating the end of each chirp

When high, indicating valid ADC samples

N8, K13, P9

P13, H13

ADC_VALID

Open drain fail safe warm reset signal. Can be driven from PMIC for

diagnostic or can be used as status signal that the device is going

through reset.

WARM_RESET

IO

N9

6.3.2 Signal Descriptions - Analog

TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

Single ended transmitter1 o/p

BALL NO.

TX1

TX2

TX3

RX1

RX2

RX3

RX4

O

I

B4

B6

B8

M2

K2

H2

F2

R3

Transmitters

Single ended transmitter2 o/p

Single ended transmitter3 o/p

Single ended receiver1 i/p

Single ended receiver2 i/p

Single ended receiver3 i/p

Single ended receiver4 i/p

Power on reset for chip. Active low

I

Receivers

Reset

I

NRESET

I

In XTAL mode: Differential port for reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

I

B15

Reference

Oscillator

In XTAL mode: Differential port for reference crystal

In External clock mode: Connect this port to ground

CLKM

C15

A14

Reference clock output from clocking subsystem

after cleanup PLL (1.4V output voltage swing).

Reference clock

Bandgap voltage

OSC_CLKOUT

O

VBGAP

VDDIN

Device's Band Gap Reference Output

B10

H15, N11, P15, R6

G15

Power 1.2V digital power supply

VIN_SRAM

VNWA

Power 1.2V power rail for internal SRAM

Power 1.2V power rail for SRAM array back bias

P14

I/O Supply (3.3V or 1.8V): All CMOS I/Os would

operate on this supply

VIOIN

Power

R10, F15

Power supply

VIOIN_18

VIN_18CLK

VIOIN_18DIFF

VPP

Power 1.8V supply for CMOS IO

Power 1.8V supply for clock module

Power 1.8V supply for LVDS port

Power Voltage supply for fuse chain

R9

B11

D15

L13

1.3V Analog and RF supply,VIN_13RF1 and

Power

VIN_13RF1

G5, H5, J5

VIN_13RF2 could be shorted on the board

VIN_13RF2

VIN_18BB

VIN_18VCO

Power 1.3V Analog and RF supply

Power 1.8V Analog base band power supply

Power 1.8V RF VCO supply

C2,D2

K5, F5

B12

Power supply

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TYPE

INTERFACE

SIGNAL NAME

DESCRIPTION

L5, L6, L8, L10, K7,

K8, K9, K10, K11,

J6, J7, J8, J10, H7,

H9, H11, G6, G7,

G8, G10, F9, F11,

E5, E6, E8, E10,

E11, R15

VSS

Ground Digital ground

A1, A3, A5, A7, A9,

A13, A15, B1, B3,

B5, B7, B9, B14,

C1, C3, C4, C5, C6,

C7, C8, C9, C14,

E1, E2, E3, F3, G1,

G2, G3, H3, J1, J2,

J3, K3, L1, L2, L3,

M3, N1, N2, N3, R1

VSSA

Ground Analog ground

VOUT_14APLL

O

Internal LDO output

A10

B13

A2, B2

P1

Internal LDO output/

inputs

VOUT_14SYNTH

O

Internal LDO output

VOUT_PA

IO

Internal LDO output

Analog Test1 / GPADC1

Analog Test2 / GPADC2

Analog Test3 / GPADC3

Analog Test4 / GPADC4

ANAMUX / GPADC5

VSENSE / GPADC6

Analog IO dedicated for ADC service

Test and Debug

output for pre-

production phase.

Can be pinned out

on production

hardware for field

debug

P2

P3

R2

C13

D14

26

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SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

7 Specifications

7.1 Absolute Maximum Ratings

PARAMETERS ^{(1) (2)}

1.2 V digital power supply

MIN

–0.5

MAX

1.4

UNIT

VDDIN

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.4

1.2 V power rail for SRAM array back bias

1.4

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

–0.5

3.8

V

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

–0.5

2

V

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board.

–0.5

1.45

V

VIN_13RF1

(1-V Internal LDO

bypass mode)

Device supports mode where external Power Management

block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In

this configuration, the internal LDO of the device would be kept

bypassed.

–0.5

1.4

V

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN_18BB

1.8-V Analog baseband power supply

1.8-V RF VCO supply

–0.5

2

V

VIN_18VCO supply

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

–0.3V

VIOIN + 0.3

Input and output

voltage range

V

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

VIOIN + 20% up to

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

–0.5

2

V

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

–20

20

mA

T_J

Operating junction temperature range

–40

–55

125

150

°C

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Corner pins are rated as ±750 V

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7.3 Power-On Hours (POH)

OPERATING

CONDITION

JUNCTION TEMPERATURE (T_j) ^{(1) (2)}

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

–40°C

75°C

600 (6%)

2000 (20%)

6500 (65%)

900 (9%)

100% duty cycle

1.2

95°C

125°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

28

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7.4 Recommended Operating Conditions

MIN

1.14

3.15

1.71

NOM

1.2

3.3

1.8

MAX

1.32

3.45

1.89

1.9

UNIT

VDDIN

1.2 V digital power supply

V

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

V

VIOIN_18

1.8 V supply for CMOS IO

1.8 V supply for clock module

1.8 V supply for LVDS port

V

VIN_18CLK

VIOIN_18DIFF

VIN_13RF1

VIN_13RF2

1.9

1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board

1.23

1.3

1.36

V

VIN_13RF1

(1-V Internal LDO

bypass mode)

Device supports mode where external Power Management

block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In

this configuration, the internal LDO of the device would be

kept bypassed.

0.95

1

1.05

V

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.17

2.25

1.8

1.9

V

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

V

0.3*VIOIN

0.62

V_OH

V_OL

VIOIN – 450

mV

450

0.45

V_IH(1.8V Mode)

0.96

1.57

NRESET

SOP[2:0]

V

V_IL(3.3V Mode)

0.65

V_IH(3.3V Mode)

7.5 Power Supply Specifications

Table 7-1 describes the four rails from an external power supply block of the AWR6843 device.

Table 7-1. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOS IN THE DEVICE

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, LVDS

1.8 V

1.3 V (or 1 V in internal

LDO bypass mode)⁽¹⁾

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/Os

Input VIOIN

1.2 V

Core Digital and SRAMs

Input: VDDIN, VIN_SRAM

(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin.

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The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in Table 7-2 are defined to meet a

target spur level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB

relationship, for example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted

are rms levels for a sinusoidal input applied at the specified frequency.

Table 7-2. Ripple Specifications

RF RAIL

VCO/IF RAIL

FREQUENCY (kHz)

1.0 V (INTERNAL LDO BYPASS)

1.3 V (µV_RMS

)

1.8 V (µV_RMS)

(µV_RMS

)

137.5

275

7

5

648

76

22

4

83

21

11

6

550

3

1100

2200

4400

6600

2

11

13

22

82

93

117

13

19

29

7.6 Power Consumption Summary

Table 7-3 and Table 7-4 summarize the power consumption at the power terminals.

Table 7-3. Maximum Current Ratings at Power Terminals

PARAMETER

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Total current drawn by all

nodes driven by 1.2V rail

VDDIN, VIN_SRAM, VNWA

1000

Total current drawn by all

nodes driven by 1.3V or

1.0V rail (2TX, 4 RX

simultaneously)⁽³⁾

VIN_13RF1, VIN_13RF2

2000

850

Current consumption⁽¹⁾

mA

VIOIN_18, VIN_18CLK,

VIOIN_18DIFF, VIN_18BB,

VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail

Total current drawn by all

nodes driven by 3.3V

rail⁽²⁾

VIOIN

50

(1) The specified current values are at typical supply voltage level.

(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.

(3) Simultaneous 3 Transmitter operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply

needs to be fed on the VOUT_PA pin. In this case, the peak 1-V supply current goes up to 2500 mA. To enable the LDO bypass mode,

see the Interface Control document in the mmWave software development kit (SDK).

Table 7-4. Average Power Consumption at Power Terminals

PARAMETER

CONDITION

DESCRIPTION

MIN

TYP MAX UNIT

1TX, 4RX

Regular power ADC mode 6.4

Msps complex transceiver,

13.13-ms frame, 64 chirps, 256

samples/chirp, 8.5-µs interchirp

time, DSP + Hardware

1.19

24% duty cycle

2TX, 4RX⁽¹⁾

1TX, 4RX

1.25

1.0-V internal

LDO bypass

mode

accelerator active

Average power

consumption ⁽¹⁾

W

Regular power ADC mode 6.4

Msps complex transceiver,

13.13-ms frame, 64 chirps, 256

samples/chirp, 8.5-µs interchirp

time, DSP + Hardware

1.62

48% duty cycle

2TX, 4RX⁽¹⁾

1.75

accelerator active

(1) Two TX antennas are on simultaneously.

30

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7.7 RF Specification

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

12

MAX UNIT

dB

Noise figure

60 to 64 GHz

1-dB compression point (Out Of Band )⁽¹⁾

–12

48

dBm

Maximum gain

dB

Gain range

18

dB

Gain step size

2

dB

Receiver

IF bandwidth⁽²⁾

10 MHz

25 Msps

12.5 Msps

Bits

A2D sampling rate (real)

A2D sampling rate (complex 1x)

A2D resolution

12

–90

12

Idle Channel Spurs

Output power

dBFS

dBm

Transmitter

Power backoff range

Frequency range

26

dB

60

64 GHz

250 MHz/µs

dBc/Hz

Clock

subsystem

Ramp rate

Phase noise at 1-MHz offset

60 to 64 GHz

–93

(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off

frequency.

(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set

of available HPF corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

HPF1

HPF2

175, 235, 350, 700

350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

7.8 CPU Specifications

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

600

32

MAX UNIT

Clock Speed

DSP

MHz

KB

L1 Code Memory

Subsystem

(C674

Family)

L1 Data Memory

32

KB

L2 Memory

256

200

512

192

KB

Master

Clock Speed

MHz

KB

Controller

Subsystem

(R4F Family)

Tightly Coupled Memory - A (Program)

Tightly Coupled Memory - B (Data)

KB

Shared

Memory

Shared L3 Memory

768

KB

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7.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

RΘ_JC

RΘ_JB

RΘ_JA

RΘ_JMA

Psi_JT

Psi_JB

Junction-to-case

4.92

6.57

22.3

N/A⁽⁴⁾

4.92

6.4

Junction-to-board

Junction-to-free air

Junction-to-moving air

Junction-to-package top

Junction-to-board

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) N/A = not applicable

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7.10 Timing and Switching Characteristics

7.10.1 Power Supply Sequencing and Reset Timing

The AWR6843 device expects all external voltage rails to be stable before reset is deasserted. Figure 7-1

describes the device wake-up sequence.

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

Stable before

nRESET

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

DC

Power

notOK

DC

Power

OK

QSPI

READ

release

VDDIN,

VIN_SRAM

VNWA

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

SOP IO

Reuse

SOP IO‘s can be used as functional IO‘s

SOP[2.1.0]

nRESET

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT (1)

QSPI_CS

OUTPUT

8 ms (XTAL Mode)

850 µs (REFCLK Mode)

A. MCU_CLK_OUT in autonomous mode, where AWR6843 application is booted from the serial flash, MCU_CLK_OUT is not enabled by

default by the device bootloader.

Figure 7-1. Device Wake-up Sequence

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7.10.2 Input Clocks and Oscillators

7.10.2.1 Clock Specifications

The AWR6843 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for initial

boot and as a reference for an internal APLL hosted in the device. An external crystal is connected to the device

pins. Figure 7-2 shows the crystal implementation.

C_f1

XTALP

C_p

40 MHz

XTALM

C_f2

Figure 7-2. Crystal Implementation

Note

The load capacitors, C_f1and C_f2in Figure 7-2, should be chosen such that Equation 1 is satisfied. C_L

in the equation is the load specified by the crystal manufacturer. All discrete components used to

implement the oscillator circuit should be placed as close as possible to the associated oscillator

CLKP and CLKM pins.

C _f2

C_L= C _f1

´

+C_P

C

_f1+C _f2

(1)

Table 7-5 lists the electrical characteristics of the clock crystal.

Table 7-5. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

pF

f_P

Parallel resonance crystal frequency

40

C_L

Crystal load capacitance

Crystal ESR

5

8

12

50

ESR

Ω

Temperature range Expected temperature range of operation

–40

–50

105

°C

Frequency

Crystal frequency tolerance^{(1) (2) (3)}

tolerance

50

ppm

µW

Drive level

50

200

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

(3) Crystal tolerance affects radar sensor accuracy.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 7-6

lists the electrical characteristics of the external clock signal.

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Table 7-6. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

40

MHz

mV (pp)

V

AC-Amplitude

700

0.00

1.6

1200

0.20

1.95

–132

–143

–152

–153

65

DC-V_il

DC-V_ih

V

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

dBc/Hz

%

Phase Noise referred to 40 MHz

35

Freq Tolerance

–50

50

ppm

50

ppm

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7.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

7.10.3.1 Peripheral Description

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The

MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or another

microcontroller.

Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

8-bit baud clock generator

SPICLK can be internally-generated (master mode) or received from an external clock source

(slave mode)

•

Each word transferred can have a unique format.

SPI I/Os not used in the communication can be used as digital input/output signals

7.10.3.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit

transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be

partitioned into multiple transfer group with variable number of buffers each.

Section 7.10.3.2.2 and Section 7.10.3.2.3 assume the operating conditions stated in Section 7.10.3.2.1.

7.10.3.2.1 SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOADOutput load capacitance

2

15

pF

7.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

NO.^{(1) (2) (3)}

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

25

TYP

MAX UNIT

1

t_c(SPC)M

256_tc(VCLK)

0.5t_c(SPC)M+ 4

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M– 3

2⁽⁴⁾

ns

3⁽⁴⁾

ns

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock

polarity = 0)

SIMO)M

4⁽⁴⁾

5⁽⁴⁾

6⁽⁵⁾

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M– 3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock 0.5t_c(SPC)M– 10.5

polarity = 0)

SIMO)M

ns

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock 0.5t_c(SPC)M– 10.5

polarity = 1)

SIMO)M

CSHOLD = 0

(C2TDELAY

+2)*t_c(VCLK)– 7.5

(C2TDELAY+2)

* t_c(VCLK)+ 7

Setup time CS active until SPICLK

high

(clock polarity = 0)

t_C2TDELAY

CSHOLD = 1

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

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PARAMETER

MIN

TYP

MAX UNIT

(C2TDELAY+2)

CSHOLD = 0

CSHOLD = 1

(C2TDELAY

+2)*t_c(VCLK)– 7.5

Setup time CS active until SPICLK

* t_c(VCLK)+ 7

low

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

(clock polarity = 1)

Hold time, SPICLK low until CS inactive (clock polarity =

0)

0.5*t_c(SPC)M

(T2CDELAY + 1)

*t_c(VCLK)– 7

+

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

7.5

+

7⁽⁵⁾

t_T2CDELAY

ns

Hold time, SPICLK high until CS inactive (clock polarity =

1)

0.5*t_c(SPC)M

(T2CDELAY + 1)

*t_c(VCLK)– 7

+

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

+

7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

5

3

SPCL)M

8⁽⁴⁾

ns

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25ns, where

PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

11

SPICLK

(clock polarity = 0)

2

1

3

SPICLK

(clock polarity = 1

4

5

Master Out Data Is Valid

SPISIMO

1

8

9

Master In Data

Must Be Valid

SPISOMI

Figure 7-3. SPI Master Mode External Timing (CLOCK PHASE = 0)

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Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

Master Out Data Is Valid

6

7

SPICSn

Figure 7-4. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

7.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

NO.^{(1) (2) (3)}

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

25

TYP

MAX UNIT

1

t_c(SPC)M

256t_c(VCLK)

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M+ 4

2⁽⁴⁾

ns

3⁽⁴⁾

ns

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock polarity 0.5t_c(SPC)M– 3

= 0)

SIMO)M

4⁽⁴⁾

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M– 3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

5⁽⁴⁾

ns

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

t_C2TDELAY

Setup time CS active until SPICLK

high

(clock polarity = 0)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

+

(C2TDELAY +

2)*t_c(VCLK)– 7

0.5*t_c(SPC)M

(C2TDELAY

+2) * t_c(VCLK)

7.5

+

0.5*t_c(SPC)M

(C2TDELAY +

2)*t_c(VCLK)– 7

+

0.5*t_c(SPC)M

+

(C2TDELAY

+2) * t_c(VCLK)

+

7.5

6⁽⁵⁾

ns

0.5*t_c(SPC)M

(C2TDELAY

+2)*t_c(VCLK)

0.5*t_c(SPC)M

+

0.5*t_c(SPC)M

+

(C2TDELAY

–

7

+2) * t_c(VCLK)

+

Setup time CS active until SPICLK

low

(clock polarity = 1)

7.5

+

0.5*t_c(SPC)M

+

(C2TDELAY

+3)*t_c(VCLK)

–

7

+3) * t_c(VCLK)+

7.5

Hold time, SPICLK low until CS inactive (clock polarity = 0)

Hold time, SPICLK high until CS inactive (clock polarity = 1)

(T2CDELAY +

1) *t_c(VCLK)

(T2CDELAY +

1) *t_c(VCLK)+ 7

–

7.5

7⁽⁵⁾

t_T2CDELAY

ns

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

8⁽⁴⁾

5

SPCL)M

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PARAMETER

MIN

TYP

MAX UNIT

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

5

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

3

SOMI)M

9⁽⁴⁾

ns

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

8

9

Master In Data

Must Be Valid

SPISOMI

Figure 7-5. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

6

7

Figure 7-6. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

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7.10.3.3 SPI Slave Mode I/O Timings

7.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output) ^{(1) (2) (3)}

NO.

PARAMETER

MIN

25

TYP

MAX

UNIT

1

t_c(SPC)S

Cycle time, SPICLK⁽⁴⁾

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

10

2⁽⁵⁾

ns

10

3⁽⁵⁾

10

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0)

10

4⁽⁵⁾

ns

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

2

5⁽⁵⁾

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

10

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

2

3

1

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity =

1; clock phase = 1)

t_{su(SIMO-SPCL)S}

Setup time, SPISIMO before SPICLK high (clock

t_{su(SIMO-SPCH)S}polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

t_{h(SPCL-SIMO)S}

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

t_{h(SPCL-SIMO)S}

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)}= master subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(4) When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns, where

PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥ 25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 7-7. SPI Slave Mode External Timing (CLOCK PHASE = 0)

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 7-8. SPI Slave Mode External Timing (CLOCK PHASE = 1)

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7.10.3.4 Typical Interface Protocol Diagram (Slave Mode)

1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

Figure 7-9 shows the SPI communication timing of the typical interface protocol.

2 SPI clocks

CS

CLK

0x4321

0x1234

CRC

0x5678

0x8765

MOSI

MISO

IRQ

0xDCBA

0xABCD

CRC

16 bytes

Figure 7-9. SPI Communication

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7.10.4 LVDS Interface Configuration

The supported AWR6843 LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane

(LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The

LVDS interface supports the following data rates:

•

900 Mbps (450 MHz DDR Clock)

600 Mbps (300 MHz DDR Clock)

450 Mbps (225 MHz DDR Clock)

400 Mbps (200 MHz DDR Clock)

300 Mbps (150 MHz DDR Clock)

225 Mbps (112.5 MHz DDR Clock)

150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

Figure 7-10. LVDS Interface Lane Configuration And Relative Timings

7.10.4.1 LVDS Interface Timings

Table 7-7. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty Cycle Requirements

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

450

mV

Output Offset Voltage

Trise and Tfall

1125

1275

mV

ps

20%-80%, 900 Mbps

900 Mbps

330

80

Jitter (pk-pk)

ps

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Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

Figure 7-11. Timing Parameters

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7.10.5 General-Purpose Input/Output

Section 7.10.5.1 lists the switching characteristics of output timing relative to load capacitance.

7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L) ^{(1) (2)}

PARAMETER

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

ns

C_L= 75 pF

10.2

2.8

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

6.6

ns

9.8

3.3

7.2

10.5

3.1

Slew control = 1

6.6

9.6

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

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7.10.6 Controller Area Network - Flexible Data-rate (CAN-FD)

The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.

CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD

devices can coexist on the same network without any conflict.

The CAN-FD has the following features:

•

Conforms with CAN Protocol 2.0 A, B and ISO 11898-1

Full CAN FD support (up to 64 data bytes per frame)

AUTOSAR and SAE J1939 support

Up to 32 dedicated Transmit Buffers

Configurable Transmit FIFO, up to 32 elements

Configurable Transmit Queue, up to 32 elements

Configurable Transmit Event FIFO, up to 32 elements

Up to 64 dedicated Receive Buffers

Two configurable Receive FIFOs, up to 64 elements each

Up to 128 11-bit filter elements

Internal Loopback mode for self-test

Mask-able interrupts, two interrupt lines

Two clock domains (CAN clock / Host clock)

Parity / ECC support - Message RAM single error correction and double error detection (SECDED)

mechanism

•

Full Message Memory capacity (4352 words).

7.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

t_{d(CAN_FD_tx)}

t_{d(CAN_FD_rx)}

Delay time, transmit shift register to CAN_FD_tx

pin⁽¹⁾

15

ns

Delay time, CAN_FD_rx pin to receive shift

register⁽¹⁾

10

ns

(1) These values do not include rise/fall times of the output buffer.

7.10.7 Serial Communication Interface (SCI)

The SCI has the following features:

•

Standard universal asynchronous receiver-transmitter (UART) communication

Standard non-return to zero (NRZ) format

Double-buffered receive and transmit functions

Asynchronous or iso-synchronous communication modes with no CLK pin

Capability to use Direct Memory Access (DMA) for transmit and receive data

Two external pins: RS232_RX and RS232_TX

7.10.7.1 SCI Timing Requirements

MIN

TYP

921.6

MAX

UNIT

f(baud)

Supported baud rate at 20 pF

kHz

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7.10.8 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface between

devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I²C-bus™.

This module will support any slave or master I2C compatible device.

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398

393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– General call

– START byte

– Multi-master transmitter/ slave receiver mode

– Multi-master receiver/ slave transmitter mode

– Combined master transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

•

Note

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C sends the slave address second byte every

time it sends the slave address first byte)

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7.10.8.1 I2C Timing Requirements

(1)

STANDARD MODE

FAST MODE

UNIT

MIN

10

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

4

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

4

0.6

0

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(2) (3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 7-12. I2C Timing Diagram

Note

•

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period

(tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode

I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

.

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7.10.9 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or quad read

access to external SPI devices. This module has a memory mapped register interface, which provides a direct

interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI

works as a master only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash

memories.

The QSPI supports the following features:

•

Programmable clock divider

Six-pin interface

Programmable length (from 1 to 128 bits) of the words transferred

Programmable number (from 1 to 4096) of the words transferred

Support for 3-, 4-, or 6-pin SPI interface

Optional interrupt generation on word or frame (number of words) completion

Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles

Section 7.10.9.2 and Section 7.10.9.3 assume the operating conditions stated in Section 7.10.9.1.

7.10.9.1 QSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

7.10.9.2 Timing Requirements for QSPI Input (Read) Timings

Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation. ⁽¹⁾

MIN

7.3

TYP

MAX

UNIT

ns

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

t_h(SCLK-D)

Setup time, d[3:0] valid before falling sclk edge

Hold time, d[3:0] valid after falling sclk edge

1.5

ns

Setup time, final d[3:0] bit valid before final falling sclk edge

Hold time, final d[3:0] bit valid after final falling sclk edge

7.3 – P⁽²⁾

1.5 + P⁽²⁾

ns

(1) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although non-

standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(2) P = SCLK period in ns.

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7.10.9.3 QSPI Switching Characteristics

NO.

Q1

Q2

Q3

PARAMETER

Cycle time, sclk

MIN

12.5

TYP

MAX

UNIT

ns

t_c(SCLK)

t_w(SCLKL)

t_w(SCLKH)

t_d(CS-SCLK)

Pulse duration, sclk low

Y*P – 3^{(1) (2)}

Y*P – 3⁽¹⁾

ns

Pulse duration, sclk high

ns

Delay time, sclk falling edge to cs active edge

–M*P + 2.5⁽¹⁾

ns

Q4

Q5

–M*P – 1^{(1) (3)}

N*P – 1^{(1) (3)}

(3)

t_d(SCLK-CS)

Delay time, sclk falling edge to cs inactive edge

N*P + 2.5⁽¹⁾

ns

(3)

Q6

Q7

Q8

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

t_d(SCLK-D1)

Delay time, sclk falling edge to d[1] transition

Enable time, cs active edge to d[1] driven (lo-z)

Disable time, cs active edge to d[1] tri-stated (hi-z)

–3.5

–P – 4⁽³⁾

7

–P +1⁽³⁾

ns

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

Q9

–3.5 – P⁽³⁾

7 – P⁽³⁾

Q12

Q13

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

Setup time, d[3:0] valid before falling sclk edge

Hold time, d[3:0] valid after falling sclk edge

7.3

1.5

ns

Setup time, final d[3:0] bit valid before final falling

sclk edge

Q14

Q15

7.3 — P⁽³⁾

1.5 + P⁽³⁾

t_h(SCLK-D)

Hold time, final d[3:0] bit valid after final falling sclk

edge

ns

(1) The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/

2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. All

required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.

(2) P = SCLK period in ns.

(3) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q12

Q13

Q12 Q13

Read Data

Bit 0

Q6

Q7

Q9

Command

Bit n-1

Command

Bit n-2

Read Data

Bit 1

d[0]

Q12 Q13

Read Data

Bit 1

Q12 Q13

Read Data

Bit 0

d[3:1]

SPRS85v_TIMING_OSPI1_02

Figure 7-13. QSPI Read (Clock Mode 0)

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PHA=0

cs

Q5

Q4

Q1

Q2

Q3

POL=0

sclk

Q8

Q6

Q7

Q9

Q6

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

Figure 7-14. QSPI Write (Clock Mode 0)

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7.10.10 ETM Trace Interface

Section 7.10.10.2 and List item. assume the recommended operating conditions stated in Section 7.10.10.1.

7.10.10.1 ETMTRACE Timing Conditions

MIN

TYP

MAX

UNIT

Output Conditions

C_LOAD

Output load capacitance

2

20

pF

7.10.10.2 ETM TRACE Switching Characteristics

NO.

1

PARAMETER

Cycle time, TRACECLK period

Pulse Duration, TRACECLK High

Pulse Duration, TRACECLK Low

Clock and data rise time

MIN

TYP

MAX

UNIT

ns

t_cyc(ETM)

t_h(ETM)

t_l(ETM)

20

9

2

ns

3

9

ns

4

t_r(ETM)

t_f(ETM)

3.3

7

ns

5

Clock and data fall time

ns

t_d(ETMTRACEDelay time, ETM trace clock high to ETM data valid

1

ns

6

7

CLKH-

ETMDATAV)

t_d(ETMTRACEDelay time, ETM trace clock low to ETM data valid

7

ns

CLKl-

ETMDATAV)

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

Figure 7-15. ETMTRACECLKOUT Timing

Figure 7-16. ETMDATA Timing

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7.10.11 Data Modification Module (DMM)

A Data Modification Module (DMM) gives the ability to write external data into the device memory.

The DMM has the following features:

•

Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention

Writes to memory locations specified in the received packet (leverages packets defined by trace mode of the

RAM trace port [RTP] module)

•

Writes received data to consecutive addresses, which are specified by the DMM (leverages packets defined

by direct data mode of RTP module)

•

Configurable port width (1, 2, 4, 8 pins)

Up to 100 Mbit/s pin data rate

7.10.11.1 DMM Timing Requirements

MIN

10

1

TYP

MAX

UNIT

ns

t_cyc(DMM)

t_R

Clock period

Clock rise time

3

ns

t_F

Clock fall time

1

ns

t_h(DMM)

t_l(DMM)

t_ssu(DMM)

t_sh(DMM)

t_dsu(DMM)

t_dh(DMM)

High pulse width

6

ns

Low pulse width

6

ns

SYNC active to clk falling edge setup time

DMM clk falling edge to SYNC deactive hold time

DATA to DMM clk falling edge setup time

DMM clk falling edge to DATA hold time

2

ns

3

ns

2

ns

3

ns

t_l(DMM)

t_h(DMM)

t_f

t_r

t_cyc(DMM)

Figure 7-17. DMMCLK Timing

t_ssu(DMM)

t_sh(DMM)

DMMSYNC

DMMCLK

DMMDATA

t_dsu(DMM)

t_dh(DMM)

Figure 7-18. DMMDATA Timing

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7.10.12 JTAG Interface

Section 7.10.12.2 and Section 7.10.12.3 assume the operating conditions stated in Section 7.10.12.1.

7.10.12.1 JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

1

3

ns

Output Conditions

C_LOAD

Output load capacitance

2

15

pF

7.10.12.2 Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

TYP

MAX

UNIT

ns

1

t_c(TCK)

Cycle time TCK

66.66

26.67

2.5

1a

1b

t_w(TCKH)

Pulse duration TCK high (40% of tc)

Pulse duration TCK low(40% of tc)

Input setup time TDI valid to TCK high

Input setup time TMS valid to TCK high

Input hold time TDI valid from TCK high

Input hold time TMS valid from TCK high

ns

t_w(TCKL)

ns

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

ns

3

4

2.5

ns

18

ns

18

ns

7.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

25

ns

1

1a

1b

TCK

TDO

2

3

4

TDI/TMS

SPRS91v_JTAG_01

Figure 7-19. JTAG Timing

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8 Detailed Description

8.1 Overview

The AWR6843 device includes the entire Millimeter Wave blocks and analog baseband signal chain for two

transmitters and four receivers, as well as a customer-programmable MCU. This device is applicable as a radar-

on-a-chip in use-cases with modest requirements for memory, processing capacity, and application code size.

These could be cost-sensitive automotive applications that are evolving from 24-GHz narrowband

implementation and some emerging simple ultra-short-range radar applications. Typical application examples for

this device include: child presence detection, occupant detection, seat belt reminder, gesture detection, driver

vital sign monitoring.

In terms of scalability, the AWR6843 device could be paired with a low-end external MCU, to address more

complex applications that might require additional memory for larger application software footprint and faster

interfaces. Because the AWR6843 device also provides high speed data interfaces like Serial-LVDS, it is suitable

for interfacing with more capable external processing blocks. Here system designers can choose the AWR6843

to provide raw ADC data.

8.2 Functional Block Diagram

Serial Flash Interface

QSPI

Cortex R4F

@ 200MHz

LNA

IF

ADC

Optional External

MCU Interface

SPI

(User Programmable)

Digital

Front-End

PMIC Control

SPI / I2C

CAN-FD

UARTs

Prog RAM

(512kB)

Data RAM

(192kB)

Boot

ROM

(Decimation

Filter Chain)

Primary Communication

Interfaces (Automotive)

Radar Hardware Accelerator

(FFT, Log Mag, And Others)

DMA

Master Sub-System

(Customer Programmed)

Test/

Debug

JTAG For Debug/

Development

ADC

Buffer

PA

´Å

Mailbox

High-Speed ADC Output

Interface (For Recording)

LVDS

HIL

Synth

(20 GHz)

Ramp

Generator

PA

x3

High-Speed Input For

Hardware-In-Loop Verification

C674x DSP

@ 600 MHz

Radio (BIST)

Processor

PA

GPADC

Osc.

6

(For RF Calibration

& Self-Test œ TI

Programmed)

L1P

(32kB)

L1D

(32kB)

L2 (256kB)

Prog RAM

& ROM

Data

RAM

Temp

DMA

CRC

Radar Data Memory

768 kB

Radio Processor

Sub-System

(TI Programmed)

DSP Sub-System

(Customer Programmed)

RF/Analog Sub-System

Figure 8-1. Functional Block Diagram

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8.3 Subsystems

8.3.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit

channels can be operated up to a maximum of two at a time (simultaneously) in 1.3-V mode. The three Transmit

channels simultaneous operation is supported only with 1-V LDO bypass and PA LDO disabled mode for

transmit beamforming purpose, as required. In this mode, the 1-V supply needs to be fed on the VIN_13RF1,

VIN_13RF2, and VOUT PA pin; whereas, the four receive channels can all be operated simultaneously.

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8.3.1.1 Clock Subsystem

The AWR6843 clock subsystem generates 60 to 64 GHz from an input reference of 40-MHz crystal. It has a

built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X3 multiplier to create the required frequency in the 60 to 64 GHz spectrum.

The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective

sensor operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

Figure 8-2 describes the clock subsystem.

Self Test

SYNC_OUT

RX LO

Timing Engine

x3 MULT

SYNC_IN

TX LO

RFSYNTH

Lock Detect

Clean-Up

PLL

SoC

Clock

XO / Slicer

CLK Detect

OSC_CLKOUT

40 MHz

Figure 8-2. Clock Subsystem

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8.3.1.2 Transmit Subsystem

The AWR6843 transmit subsystem consists of three parallel transmit chains, each with independent phase and

amplitude control. The device supports 6-bit linear phase modulation for MIMO radar.

The transmit chains also support programmable backoff for system optimization.

Figure 8-3 describes the transmit subsystem.

Loopback

Path

Self Test

0 or 180°

(from Timing Engine)

PCB

50 W

DF

LO

6-bit Linear Phase

Shifter

Figure 8-3. Transmit Subsystem (Per Channel)

8.3.1.3 Receive Subsystem

The AWR6843 receive subsystem consists of four parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational at the

same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the AWR6843 device supports a complex baseband architecture, which

uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver

channel. The AWR6843 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff

frequencies above 175 kHz and can support bandwidths up to 10 MHz.

Figure 8-4 describes the receive subsystem.

Self Test

DAC

Loopback

Path

DSM

PCB

I

RSSI

50 W

GSG

LO

Q

DSM

DAC

Figure 8-4. Receive Subsystem (Per Channel)

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8.3.2 Processor Subsystem

Unified

128 KB x 2

ROM

L2

Cache/

RAM

TCM A 512 KB

TCM B 192 KB

L1P

32 KB

EDMA

Master

R4F

DSP

HWA

HIL

JTAG

CRC

HIL

L1d

DSP/HWA Interconnect œ 128 bit @ 200 MHz

Master Interconnect

BSS Interconnect

Data

Handshake

Memory

CRC

ADC Buffer

Mail

Box

MSS

DMA

L3

32 KB

32 KB Ping-Pong

(static sharing

with R4F Space)

Interconnect

LVDS

PWM,

PMIC

CLK

I²C

QSPI

UART

SPI

CAN-FD

Figure 8-5. Processor Subsystem

Figure 8-5shows the block diagram for customer programmable processor subsystems in the AWR6843 device.

At a high level there are two customer programmable subsystems, as shown separated by a dotted line in the

diagram. Left hand side shows the DSP Subsystem which contains TI's high-performance C674x DSP, hardware

accelerator, a high-bandwidth interconnect for high performance (128-bit, 200MHz), and associated peripherals

– four DMAs for data transfer,

LVDS interface for Measurement data output, L3 Radar data cube memory, ADC buffers, CRC engine, and data

handshake memory (additional memory provided on interconnect).

The right side of the diagram shows the Master subsystem. Master subsystem as name suggests is the master

of the device and controls all the device peripherals and house-keeping activities of the device. Master

subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and house-keeping

components such as DMAs, CRC and Peripherals (I²C, UART, SPIs, CAN, PMIC clocking module, PWM, and

others) connected to Master Interconnect through Peripheral Central Resource (PCR interconnect).

Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748.

HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the

captured data from outside into the device without involving the RF subsystem. HIL on master SS is for

controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL modules

uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of the two.

8.3.3 Automotive Interface

The AWR6843 communicates with the automotive network over the following main interfaces:

•

2 CAN-FD modules

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8.3.4 Host Interface

The host interface can be provided through a SPI, UART, or CAN-FD interface. In some cases the serial

interface for automotive applications is transcoded to a different serial standard.

This device communicates with the host radar processor over the following main interfaces:

•

Reference Clock – Reference clock available for host processor after device wakeup

Control – 4-port standard SPI (slave) for host control . All radio control commands (and response) flow

through this interface.

•

Reset – Active-low reset for device wakeup from host

Host Interrupt - an indication that the mmwave sensor needs host interface

Error – Used for notifying the host in case the radio controller detects a fault

8.3.5 Master Subsystem Cortex-R4F

The master system includes an ARM Cortex R4F processor, clock with a maximum operating frequency of 200

MHz. User applications executing on this processor control the overall operation of the device, including radar

control through well-defined API messages, radar signal processing (assisted by the radar hardware

accelerator), and peripherals for external interfaces.

See the Technical Reference Manual for a complete description and memory map.

8.3.6 DSP Subsystem

The DSP subsystem includes TI’s standard TMS320C674x megamodule and several blocks of internal memory

(L1P, L1D, and L2). For complete information including memory map, please refer to Technical Reference

Manual.

8.3.7 Hardware Accelerator

The Radar Hardware Accelerator (HWA) is an IP that enables off-loading the burden of certain frequently used

computations in FMCW radar signal processing from the main processor. FMCW radar signal processing

involves the use of FFT and Log-Magnitude computations to obtain a radar image across the range, velocity, and

angle dimensions. Some of the frequently used functions in FMCW radar signal processing can be done within

the radar hardware accelerator, while still retaining the flexibility of implementing other proprietary algorithms in

the main processor. See the Radar Hardware Accelerator User's Guide for a functional description and features

of this module and see the Technical Reference Manual for a complete list of register and memory map.

8.4 Other Subsystems

8.4.1 ADC Channels (Service) for User Application

The AWR6843 device includes provision for an ADC service for user application, where the

GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2,

ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

•

ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s

external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST subsystem. This API

could be linked with the user application running on the Master R4.

•

BIST subsystem firmware will internally schedule these measurements along with other RF and Analog

monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and

number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the

readings will be reported for each of the monitored voltages.

GPADC Specifications:

•

625 Ksps SAR ADC

0 to 1.8V input range

10-bit resolution

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•

For 5 out of the 6 inputs, an optional internal buffer (0.4-1.4V input range) is available. Without the buffer, the

ADC has a switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic

capacitance (GPADC channel 6, the internal buffer is not available).

5

ANALOG TEST 1-4,

GPADC

ANAMUX

5

VSENSE

A. GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±7°C.

Figure 8-6. ADC Path

8.4.1.1 GP-ADC Parameter

PARAMETER

TYP

1.8

UNIT

V

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

0 – 1.8

0.4 – 1.3

10

V

bits

LSB

Ksps

ns

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

400

10

ADC INL

ADC sample rate⁽²⁾

ADC sampling time⁽²⁾

ADC internal cap

pF

ADC buffer input capacitance

ADC input leakage current

2

pF

3

uA

(1) Outside of given range, the buffer output will become nonlinear.

(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.

62

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9 Monitoring and Diagnostics

9.1 Monitoring and Diagnostic Mechanisms

Table 9-1 is a list of the main monitoring and diagnostic mechanisms available in the Functional Safety-

Compliant targeted devices

Table 9-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices

NO

FEATURE

DESCRIPTION

Device architecture supports hardware logic BIST (LBIST) engine self-test Controller (STC).

This logic is used to provide a very high diagnostic coverage (>90%) on the Master R4F

CPU core and Vectored Interrupt Module (VIM) at a transistor level.

LBIST for the CPU and VIM need to be triggered by application code before starting the

functional safety application. CPU stays there in while loop and does not proceed further if a

fault is identified.

Boot time LBIST For Master

R4F Core and associated

VIM

1

Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and

TCMB1. Device architecture supports a hardware programmable memory BIST (PBIST)

engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the

implemented Master R4F TCMs at a transistor level.

PBIST for TCM memories is triggered by Bootloader at the boot time before starting

download of application from Flash or peripheral interface. CPU stays there in while loop

and does not proceed further if a fault is identified.

Boot time PBIST for Master

R4F TCM Memories

2

3

TCMs diagnostic is supported by Single error correction double error detection (SECDED)

ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64-

bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme

provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU can be

configured to have predetermined response (Ignore or Abort generation) to single and

double bit error conditions.

End to End ECC for Master

R4F TCM Memories

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an

ECC fault.

Further, bit multiplexing scheme implemented such that the bits accessed to generate a

logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability

of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple

single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word,

this scheme improves the usefulness of the TCM ECC diagnostic.

Master R4F TCM bit

multiplexing

4

Both these features are hardware features and cannot be enabled or disabled by application

software.

Device architecture supports Three Digital Clock Comparators (DCCs) and an internal

RCOSC. Dual functionality is provided by these modules – Clock detection and Clock

Monitoring.

DCCint is used to check the availability/range of Reference clock at boot otherwise the

device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This

provides debug capability). DCCint is only used by boot loader during boot time. It is

disabled once the APLL is enabled and locked.

DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided

version with the Reference input clock of the device. Initially (before configuring APLL),

DCC1 is used by bootloader to identify the precise frequency of reference input clock

against the internal RCOSC clock source. Failure detection for DCC1 would cause the

device to go into limp mode.

5

Clock Monitor

DCC2 module is one which is available for user software . From the list of clock options

given in detailed spec, any two clocks can be compared. One example usage is to compare

the CPU clock with the Reference or internal RCOSC clock source. Failure detection is

indicated to the Master R4F CPU via Error Signaling Module (ESM).

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Table 9-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices

(continued)

NO

FEATURE

DESCRIPTION

Device architecture supports the use of an internal watchdog that is implemented in the real-

time interrupt (RTI) module. The internal watchdog has two modes of operation: digital

watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are

mutually exclusive; the designer can elect to use one mode or the other but not both at the

same time.

7

RTI/WD for Master R4F

Watchdog can issue either an internal (warm) system reset or a CPU non-mask able

interrupt upon detection of a failure.

The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot

process. Once the application code takes up the control, Watchdog can be configured again

for mode and timings based on specific customer requirements.

Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial

separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It

is expected that the operating system controls the MPU and changes the MPU settings

based on the needs of each task. A violation of a configured memory protection policy

results in a CPU abort.

8

9

MPU for Master R4F

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

Peripheral SRAMs as well.

PBIST for peripheral SRAM memories can be triggered by the application. User can elect to

PBIST for Peripheral interface run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which

SRAMs - SPIs, CANs

can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory

contents, and as such are typically run only at boot time. However, the user has the freedom

to initiate the tests at any time if peripheral communication can be hindered.

Any fault detected by the PBIST results in an error indicated in PBIST status registers.

Peripheral interface SRAMs diagnostic is supported by Single error correction double error

detection (SECDED) ECC diagnostic. When a single or double bit error is detected the

ECC for Peripheral interface Master R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset.

10

SRAMs – SPIs, CANs

Software must configure and enable this feature in the peripheral and ESM module. ECC

failure (both single bit corrected and double bit uncorrectable error conditions) is reported to

the Master R4F as an interrupt via ESM module.

All the Master SS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are

connected to interconnect via Peripheral Central resource (PCR). This provides two

diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated

per peripheral chip select in the PCR. This can be utilized to disable unused features such

that they cannot interfere. In addition, each peripheral chip select can be programmed to

limit access based on privilege level of transaction. This feature can be used to limit access

to entire peripherals to privileged operating system code only.

Configuration registers

protection for Master SS

peripherals

11

These diagnostic mechanisms are disabled after reset. Software must configure and enable

these mechanisms. Protection violation also generates an ‘aerror’ that result in abort to

Master R4F or error response to other masters such as DMAs.

Device architecture supports hardware CRC engine on Master SS implementing the below

polynomials.

•

CRC16 CCITT – 0x10

CRC32 Ethernet – 0x04C11DB7

CRC64

CRC 32C – CASTAGNOLI – 0x1EDC6F4

CRC32P4 – E2E Profile4 – 0xF4ACFB1

CRC-8 – H2F Autosar – 0x2F

CRC-8 – VDA CAN – 0x1D

Cyclic Redundancy Check –

Master SS

12

The read operation of the SRAM contents to the CRC can be done by CPU or by DMA. The

comparison of results, indication of fault, and fault response are the responsibility of the

software managing the test.

Device architecture supports MPUs on Master SS DMAs. Failure detection by MPU is

reported to the Master R4F CPU core as an interrupt via ESM.

13

MPU for DMAs

DSPSS’s high performance EDMAs also includes MPUs on both read and writes master

ports. EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP

core as an interrupt via local ESM.

64

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Table 9-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices

(continued)

NO

FEATURE

DESCRIPTION

Device architecture supports hardware logic BIST (LBIST) even for BIST R4F core and

associated VIM module. This logic provides very high diagnostic coverage (>90%) on the

BIST R4F CPU core and VIM.

This is triggered by Master R4F boot loader at boot time and it does not proceed further if

the fault is detected.

Boot time LBIST For BIST

R4F Core and associated

VIM

14

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST

R4F TCMs.

PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed

further if the fault is detected.

Boot time PBIST for BIST

R4F TCM Memories

15

16

BIST R4F TCMs diagnostic is supported by Single error correction double error detection

(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while

double bit error is communicated to Master R4F as an interrupt so that application code

becomes aware of this and takes appropriate action.

End to End ECC for BIST

R4F TCM Memories

Logical TCM word and its associated ECC code is split and stored in two physical SRAM

banks. This scheme provides an inherent diagnostic mechanism for address decode failures

in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults

resulting in logical multi-bit faults.

BIST R4F TCM bit

multiplexing

17

18

Device architecture supports an internal watchdog for BIST R4F. Timeout condition is

reported via an interrupt to Master R4F and rest is left to application code to either go for SW

reset for BIST SS or warm reset for the device to come out of faulty condition.

RTI/WD for BIST R4F

Device architecture supports a hardware programmable memory BIST (PBIST) engine for

DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic coverage

(March-13n).

PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed

further if the fault is detected.

Boot time PBIST for L1P,

L1D, L2 and L3 Memories

19

20

Device architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is

reported to the CPU as an interrupt.

Note:- L1D memory is not covered by parity or ECC and need to be covered by application

level diagnostics.

Parity on L1P

Device architecture supports both Parity Single error correction double error detection

(SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB of memory

used to store program and Data sections for the DSP. A 12-bit code word is used to store the

ECC data as calculated over the 256-bit data bus (logical instruction fetch size). The ECC

logic for the L2 access is located in the DSP and evaluation is done by the ECC control logic

inside the DSP. This scheme provides end-to-end diagnostics on the transmissions between

DSP and L2. Byte aligned Parity mechanism is also available on L2 to take care of data

section.

21

ECC on DSP’s L2 Memory

L3 memory is used as Radar data section in Device. Device architecture supports Single

error correction double error detection (SECDED) ECC diagnostic on L3 memory. An 8-bit

code word is used to store the ECC data as calculated over the 64-bit data bus.

Failure detection by ECC logic is reported to the Master R4F CPU core as an interrupt via

ESM.

ECC on Radar Data Cube

(L3) Memory

22

23

Device architecture supports the use of an internal watchdog for BIST R4F that is

implemented in the real-time interrupt (RTI) module – replication of same module as used in

Master SS. This module supports same features as that of RTI/WD for Master/BIST R4F.

This watchdog is enabled by customer application code and Timeout condition is reported

via an interrupt to Master R4F and rest is left to application code in Master R4F to either go

for SW reset for DSP SS or warm reset for the device to come out of faulty condition.

RTI/WD for DSP Core

Device architecture supports dedicated hardware CRC on DSPSS implementing the below

polynomials.

•

CRC16 CCITT - 0x10

CRC32 Ethernet - 0x04C11DB7

CRC64

24

CRC for DSP Sub-System

The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The

comparison of results, indication of fault, and fault response are the responsibility of the

software managing the test.

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Table 9-1. Monitoring and Diagnostic Mechanisms for Functional Safety-Compliant Targeted Devices

(continued)

NO

FEATURE

DESCRIPTION

Device architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2

memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by

MPU is reported to the DSP core as an abort.

25

MPU for DSP

Device architecture supports various temperature sensors all across the device (next to

power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame

period.⁽¹⁾

26

27

Temperature Sensors

Tx Power Monitors

Device architecture supports power detectors at the Tx output.⁽²⁾

When a diagnostic detects a fault, the error must be indicated. The device architecture

provides aggregation of fault indication from internal monitoring/diagnostic mechanisms

using a peripheral logic known as the Error Signaling Module (ESM). The ESM provides

mechanisms to classify errors by severity and to provide programmable error response.

ESM module is configured by customer application code and specific error signals can be

enabled or masked to generate an interrupt (Low/High priority) for the Master R4F CPU.

Device supports Nerror output signal (IO) which can be monitored externally to identify any

kind of high severity faults in the design which could not be handled by the R4F.

Error Signaling

Error Output

28

Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and

comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if

any, are detected and reported.

Synthesizer (Chirp) frequency

monitor

29

30

Device architecture supports a ball break detection mechanism based on Impedance

measurement at the TX output(s) to detect and report any large deviations that can indicate

a ball break.

Monitoring is done by TIs code running on BIST R4F and failure is reported to the Master

R4F via Mailbox.

Ball break detection for TX

ports (TX Ball break monitor)

It is completely up to customer SW to decide on the appropriate action based on the

message from BIST R4F.

Built-in TX to RX loopback to enable detection of failures in the RX path(s), including Gain,

inter-RX balance, etc.

31

32

33

34

RX loopback test

Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect

failure.

IF loopback test

Provision to detect ADC saturation due to excessive incoming signal level and/or

interference.

RX saturation detect

Boot time LBIST for DSP core

Device device supports boot time LBIST for the DSP Core. LBIST can be triggered by the

Master R4F application code during boot time.

(1) Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the

temperature sensed via API by customer application.

a. Report the temperature sensed after every N frames

b. Report the condition once the temperature crosses programmed threshold.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.

(2) Monitoring is done by the TI's code running on BIST R4F.

There are two modes in which it could be configured to report the detected output power via API by customer application.

a. Report the power detected after every N frames

b. Report the condition once the output power degrades by more than configured threshold from the configured.

It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.

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9.1.1 Error Signaling Module

When a diagnostic detects a fault, the error must be indicated. architecture provides aggregation of fault

indication from internal diagnostic mechanisms using a peripheral logic known as the error signaling module

(ESM). The ESM provides mechanisms to classify faults by severity and allows programmable error response.

Below is the high level block diagram for ESM module.

Low Priority

Interrupt

Interrupy

Handing

Error Group 1

Interrupt Enable

High Priority

Interrupt

Handing

High Priority

Interrupy

Interrupt Priority

Error Group 2

Error Group 3

Nerror Enable

Error Signal

Handling

Device Output

Figure 9-1. ESM Module Diagram

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10 Applications, Implementation, and Layout

Note

Information in the following Applications section is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

Application information can be found on AWR Application web page.

10.2 Reference Schematic

Please check the device product page for latest Hardware design information under Design Kits - typically, at

Design & development.

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.

•

Altium XWR6843 EVM Design Files

XWR6843 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials

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11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

11.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AWR6843). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

XA Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

XA and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (XA or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, ABL0161), the temperature range (for example, blank is the default automotive temperature

range). Figure 11-1 provides a legend for reading the complete device name for any AWR6843 device.

For orderable part numbers of AWR6843 devices in the ABL0161 package types, see the Package Option

Addendum of this document, the TI website ( www.ti.com ),or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the xWR6843 Device Errata.

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6

8

43

A

B

AWR

G

ABL

Qualification

Prefix

XA = Pre-production Automotive

AWR = Production Automotive

Blank = no special qual

Q1 = AEC-Q100

Generation

1 = 77 GHz Band

6 = 60 GHz Band

Variant

Tray or Tape & Reel

R = Tape & Reel

Blank = Tray

2 = FE

Package

4 = FE + FFT + MCU

6 = FE + MCU + DSP

8 = FE + MCU + FFT + DSP

ABL = BGA

Security

G = General

S = Secure

Num RX/TX Channels

RX = 1,2,3,4

TX = 1,2,3

Silicon PG Revision

blank = Rev1.0

A = Rev 2.0

Features

blank = baseline

R = Antenna on Package (AoP)

Safety Level

Q = Non-Functional Safety

B = ASIL B

Figure 11-1. Device Nomenclature

11.2 Tools and Software

Models

xWR6843 BSDL model

xWR6843 IBIS model

Boundary scan database of testable input and output pins for IEEE 1149.1 of

the specific device.

IO buffer information model for the IO buffers of the device. For simulation on

a circuit board, see IBIS Open Forum.

xWR6843 checklist for

schematic review, layout

review,bringup/wakeup

A set of steps in spreadsheet form to select system functions and pinmux

options. Specific EVM schematic and layout notes to apply to customer

engineering. A bring up checklist is suggested for customers.

11.3 Documentation Support

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com ( AWR6843 ). In the upper right corner, click the "Alert me" button. This registers you to receive

a weekly digest of product information that has changed (if any). For change details, check the revision history of

any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral follows.

Errata

xWR6843 Device Errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

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11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

ARM^®and Cortex^®are registered trademarks of ARM Limited.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

12.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

ABL0161B

FCBGA - 1.17 mm max height

SCALE 1.400

PLASTIC BALL GRID ARRAY

10.5

10.3

B

A

BALL A1 CORNER

10.5

10.3

1.17 MAX

C

SEATING PLANE

0.1 C

BALL TYP

0.37

0.27

TYP

9.1 TYP

PKG

(0.65) TYP

R

P

N

M

L

K

J

PKG

H

G

F

9.1

TYP

E

D

C

0.45

161X

0.35

0.15

0.08

C A B

C

B

A

0.65 TYP

BALL A1 CORNER

1

2

3

4

5

6

7

8

9 10 11

12 13 14 15

0.65 TYP

4223365/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.65) TYP

D

E

F

G

H

J

PKG

K

L

M

N

P

R

PKG

LAND PATTERN EXAMPLE

SCALE:10X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

( 0.32)

METAL

(

0.32)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223365/A 10/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

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EXAMPLE STENCIL DESIGN

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

A

B

C

(0.65) TYP

D

E

F

G

H

J

PKG

K

L

M

N

P

R

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4223365/A 10/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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75

Product Folder Links: AWR6843

AWR6843

www.ti.com

SWRS248B – APRIL 2020 – REVISED SEPTEMBER 2020

12.2 Tray Information for ABL, 10.4 × 10.4 mm

Package

Type

Package

Name

Unit Array

Matrix

Max Temp.

(°C)

L

W

(mm)

K0

(mm)

P1

(mm)

CL

(mm)

CW

(mm)

Device

Pins

SPQ

(mm)

AWR6843AQGABLQ1

AWR6843ABGABLQ1

FC/CSP

ABL

161

176

8 × 22

150

315.0

135.9

7.62

13.40

16.80

17.20

76

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PACKAGE MATERIALS INFORMATION

www.ti.com

16-Oct-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AWR6843ABGABLRQ1 FC/CSP

AWR6843AQGABLRQ1 FC/CSP

ABL

161

1000

330.0

24.4

10.7

1.65

16.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Oct-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AWR6843ABGABLRQ1

AWR6843AQGABLRQ1

FC/CSP

ABL

161

1000

336.6

41.3

Pack Materials-Page 2

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	AWR6843ABGABLRQ1
厂家：	TEXAS INSTRUMENTS
描述：	AWR6843 Single-Chip 60- to 64-GHz mmWave Sensor
文件：	总81页 (文件大小：2621K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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