BQ2004 [TI]
Fast-Charge IC; 快速充电IC
| 型号： | BQ2004 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fast-Charge IC |
| 文件： | 总16页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2004
Fast-Charge IC
of the battery, or switch depression.
For safety, fast charge is inhibited
unless/until the battery tempera-
ture and voltage are within config-
ured limits.
Features
General Description
➤ Fast charge and conditioning of
nickel cadmium or nickel-metal
hydride batteries
The bq2004 Fast Charge IC provides
comprehensive fast charge control
functions together with high-speed
switching power control circuitry on a
monolithic CMOS device.
Temperature, voltage, and time are
monitored throughout fast charge.
Fast charge is terminated by any of
the following:
➤ Hysteretic PWM switch-mode
current regulation or gated con-
trol of an external regulator
Integration of closed-loop current
control circuitry allows the bq2004
to be the basis of a cost-effective so-
lution for stand-alone and system-
integrated chargers for batteries of
one or more cells.
➤ Easily integrated into systems or
n
Rate of temperature time
(∆T/∆t)
used as a stand-alone charger
➤ Pre-charge qualification of tem-
n
n
n
n
n
Peak voltage detection (PVD)
Negative delta voltage (-∆V)
Maximum voltage
perature and voltage
Switch-activated discharge-before-
charge allows bq2004-based chargers
to support battery conditioning and
capacity determination.
➤ Configurable, direct LED outputs
display battery and charge status
➤ Fast-charge termination by ∆ tem-
perature/∆ time, peak volume de-
tection, -∆V, maximum voltage,
maximum temperature, and maxi-
mum time
Maximum temperature
Maximum time
High-efficiency power conversion is
accomplished using the bq2004 as a
hysteretic PWM controller for
switch-mode regulation of the charg-
ing current. The bq2004 may alterna-
tively be used to gate an externally
regulated charging current.
After fast charge, optional top-off
and pulsed current maintenance
phases are available.
➤ Optional top-off charge and
pulsed current maintenance
charging
Fast charge may begin on application
of the charging supply, replacement
➤ Logic-level controlled low-power
mode (< 5µA standby current)
Pin Names
Pin Connections
SNS
LED1
LED2
VSS
Sense resistor input
Charge status output 1
Charge status output 2
System ground
DCMD
DSEL
VSEL
Discharge command
Display select
DCMD
DSEL
VSEL
1
2
3
4
5
6
16
15
14
13
12
11
INH
Voltage termination
select
DIS
MOD
TM1
TM2
TCO
TS
Timer mode select 1
Timer mode select 2
Temperature cutoff
Temperature sense
Battery voltage
VCC
5.0V 10% power
TM
TM
V
V
1
CC
2
SS
MOD
DIS
Charge current control
TCO
LED
2
Discharge control
output
TS
7
8
10
9
LED
1
BAT
SNS
INH
Charge inhibit input
BAT
16-Pin Narrow DIP
or Narrow SOIC
PN2004E01.eps
SLUS063–JUNE 1999 F
1
bq2004
Charging current sense input
SNS
Pin Descriptions
SNS controls the switching of MOD based on
an external sense resistor in the current
path of the battery. SNS is the reference po-
tential for both the TS and BAT pins. If
SNS is connected to VSS, then MOD switches
high at the beginning of charge and low at
the end of charge.
Discharge-before-charge control input
DCMD
The DCMD input controls the conditions
that enable discharge-before-charge. DCMD
is pulled up internally. A negative-going
pulse on DCMD initiates a discharge to end-
of-discharge voltage (EDV) on the BAT pin,
followed by a new charge cycle start. Tying
DCMD to ground enables automatic
discharge-before-charge on every new charge
cycle start.
Charge status outputs
LED1–
LED2
Push-pull outputs indicating charging
status. See Table 2.
Display select input
DSEL
VSEL
Ground
VSS
VCC
This three-state input configures the charge
status display mode of the LED1 and LED2
outputs. See Table 2.
VCC supply input
5.0V, 10% power input.
Charge current control output
Voltage termination select input
MOD
This three-state input controls the voltage-
termination technique used by the bq2004.
When high, PVD is active. When floating,
-∆V is used. When pulled low, both PVD and
-∆V are disabled.
MOD is a push-pull output that is used to
control the charging current to the battery.
MOD switches high to enable charging cur-
rent to flow and low to inhibit charging
current flow.
Timer mode inputs
TM1–
TM2
Discharge control output
DIS
Push-pull output used to control an external
transistor to discharge the battery before
charging.
TM1 and TM2 are three-state inputs that
configure the fast charge safety timer, voltage
termination hold-off time, “top-off”, and
trickle charge control. See Table 1.
Charge inhibit input
INH
Temperature cut-off threshold input
TCO
When low, the bq2004 suspends all charge
actions, drives all outputs to high imped-
ance, and assumes a low-power operational
state. When transitioning from low to high, a
new charge cycle is started.
Input to set maximum allowable battery
temperature. If the potential between TS
and SNS is less than the voltage at the TCO
input, then fast charge or top-off charge is ter-
minated.
Temperature sense input
TS
Input, referenced to SNS, for an external
thermister monitoring battery temperature.
Battery voltage input
BAT
BAT is the battery voltage sense input, refer-
enced to SNS. This is created by a high-
impedance resistor-divider network con-
nected between the positive and the negative
terminals of the battery.
2
bq2004
Functional Description
Discharge-Before-Charge
Figure 3 shows a block diagram and Figure 4 shows a
state diagram of the bq2004.
The DCMD input is used to command discharge-before-
charge via the DIS output. Once activated, DIS becomes
active (high) until VCELL falls below VEDV, at which time
DIS goes low and a new fast charge cycle begins.
Battery Voltage and Temperature
Measurements
The DCMD input is internally pulled up to VCC (its inac-
tive state). Leaving the input unconnected, therefore,
results in disabling discharge-before-charge. A negative
going pulse on DCMD initiates discharge-before-charge
at any time regardless of the current state of the
bq2004. If DCMD is tied to VSS, discharge-before-charge
will be the first step in all newly started charge cycles.
Battery voltage and temperature are monitored for
maximum allowable values. The voltage presented on
the battery sense input, BAT, should represent a
two-cell potential for the battery under charge.
resistor-divider ratio of:
A
RB1
RB2
N
2
=
- 1
Starting a Charge Cycle
is recommended to maintain the battery voltage within
the valid range, where N is the number of cells, RB1 is
the resistor connected to the positive battery terminal,
and RB2 is the resistor connected to the negative bat-
tery terminal. See Figure 1.
A new charge cycle (see Figure 2) is started by:
1.
VCC rising above 4.5V
2. VCELL falling through the maximum cell voltage,
V
MCV where:
VMCV = 0.8 ∗ VCC 30mV
Note: This resistor-divider network input impedance to
end-to-end should be at least 200kΩ and less than 1MΩ.
3. A transition on the INH input from low to high.
A ground-referenced negative temperature coefficient ther-
mistor placed in proximity to the battery may be used as a
low-cost temperature-to-voltage transducer. The tempera-
ture sense voltage input at TS is developed using a
If DCMD is tied low, a discharge-before-charge is exe-
cuted as the first step of the new charge cycle. Other-
wise, pre-charge qualification testing is the first step.
resistor-thermistor network between VCC and VSS
. See
The battery must be within the configured temperature
and voltage limits before fast charging begins.
Figure 1. Both the BAT and TS inputs are referenced to
SNS, so the signals used inside the IC are:
The valid battery voltage range is VEDV < VBAT < VMCV
where:
V
BAT - VSNS = VCELL
and
TS - VSNS = VTEMP
VEDV = 0.4 ∗ VCC 30mV
V
The valid temperature range is VHTF < VTEMP < VLTF
,
where:
Negative Temperature
Coefficient Thermister
V
CC
PACK +
RT1
PACK+
PACK-
T
S
RB1
bq2004
N
T
C
bq2004
RT2
BAT
RB2
SNS
PACK -
SNS
Fg2004a.eps
Figure 1. Voltage and Temperature Monitoring
3
bq2004
Charge
Pending*
(Pulse-Trickle)
Dis-
Top-Off
Pulse-Trickle
Fast Charging
(Optional)
charge
(Optional)
DIS
260 s
260 s
Switch-mode
Configuration
MOD
or
Note*
260 s
2080 s
260 s
External
MOD Regulation
Note*
2080 s
(SNS Grounded)
Mode 1, LED Status Output
2
Mode 1, LED Status Output
1
Mode 2, LED Status Output
2
Mode 2, LED Status Output
1
Mode 3, LED Status Output
2
Mode 3, LED Status Output
1
Battery within temperature/voltage limits.
Battery discharged to 0.4 Battery outside
V
CC.
*
temperature/voltage limits.
Discharge-Before-Charge started
TD200401a.eps
*See Table 3 for pulse-trickle period.
Figure 2. Charge Cycle Phases
4
bq2004
VLTF = 0.4 ∗ VCC 30mV
sulting sample periods (9.17ms and 18.18ms, respec-
tively) filter out harmonics centered around 55Hz and
109Hz. This technique minimizes the effect of any AC
line ripple that may feed through the power supply from
either 50Hz or 60Hz AC sources. Tolerance on all tim-
ing is 16%.
VHTF = [(1/4 ∗ VLTF) + (3/4 ∗ VTCO)] 30mV
Note: The low temperature fault (LTF) threshold is not
enforced if the IC is configured for PVD termination
(VSEL = high).
V
TCO is the voltage presented at the TCO input pin, and is
configured by the user with a resistor divider between VCC
and ground. The allowed range is 0.2 to 0.4 ∗ VCC
Voltage Termination Hold-off
A hold-off period occurs at the start of fast charging.
During the hold-off period, -∆V termination is disabled.
This avoids premature termination on the voltage
spikes sometimes produced by older batteries when
fast-charge current is first applied. ∆T/∆t, maximum
voltage and maximum temperature terminations are
not affected by the hold-off period.
.
If the temperature of the battery is out of range, or the
voltage is too low, the chip enters the charge pending
state and waits for both conditions to fall within their al-
lowed limits. The MOD output is modulated to provide
the configured trickle charge rate in the charge pending
state. There is no time limit on the charge pending
state; the charger remains in this state as long as the
voltage or temperature conditons are outside of the al-
lowed limits. If the voltage is too high, the chip goes to
the battery absent state and waits until a new charge
cycle is started.
∆T/∆t Termination
The bq2004 samples at the voltage at the TS pin every
34s, and compares it to the value measured two samples
earlier. If VTEMP has fallen 16mV 4mV or more, fast
charge is terminated. If VSEL = high, the ∆T/∆t termi-
nation test is valid only when VTCO < VTEMP < VTCO
0.2 ∗ VCC. Otherwise the ∆T/∆t termination test is valid
only when VTCO < VTEMP < VLTF
+
Fast charge continues until termination by one or more
of the six possible termination conditions:
.
n
n
n
n
n
n
Delta temperature/delta time (∆T/∆t)
Peak voltage detection (PVD)
Negative delta voltage (-∆V)
Maximum voltage
Temperature Sampling
Each sample is an average of 16 voltage measurements
taken 57µs apart. The resulting sample period
(18.18ms) filters out harmonics around 55Hz. This tech-
nique minimizes the effect of any AC line ripple that
may feed through the power supply from either 50Hz or
60Hz AC sources. Tolerance on all timing is 16%.
Maximum temperature
Maximum time
Maximum Voltage, Temperature, and Time
PVD and -∆V Termination
Anytime VCELL rises above VMCV, the LEDs go off and
charging ceases immediately. If VCELL then falls back be-
low VMCV before tMCV = 1.5s 0.5s, the chip transitions to
the Charge Complete state (maximum voltage termina-
tion). If VCELL remains above VMCV at the expiration of
tMCV, the bq2004 transitions to the Battery Absent state
(battery removal). See Figure 4.
The bq2004 samples the voltage at the BAT pin once
every 34s. When -∆V termination is selected, if VCELL is
lower than any previously measured value by 12mV
4mV (6mV/cell), fast charge is terminated. When PVD
termination is selected, if VCELL is lower than any previ-
ously measured value by 6mV 2mV (3mV/cell), fast
charge is terminated. The PVD and -∆V tests are valid
Maximum temperature termination occurs anytime
VTEMP falls below the temperature cutoff threshold
in the range 0.4 ∗ VCC < VCELL < 0.8 ∗ VCC
.
VTCO. Unless PVD termination is enabled (VSEL =
VSEL Input
Low
Voltage Termination
high), charge will also be terminated if VTEMP rises
above the low temperature fault threshold, VLTF, after
fast charge begins. The VLTF threshold is not enforced
when the IC is configured for PVD termination.
Disabled
-∆V
PVD
Float
High
Maximum charge time is configured using the TM pin.
Time settings are available for corresponding charge
rates of C/4, C/2, 1C, and 2C. Maximum time-out termi-
nation is enforced on the fast-charge phase, then reset,
and enforced again on the top-off phase, if selected.
There is no time limit on the trickle-charge phase.
Voltage Sampling
Each sample is an average of voltage measurements
taken 57µs apart. The IC takes 32 measurements in
PVD mode and 16 measurements in -∆V mode. The re-
5
bq2004
Top-off Charge
Charge Status Indication
An optional top-off charge phase may be selected to
follow fast charge termination for the C/2 through 4C
rates. This phase may be necessary on NiMH or other
battery chemistries that have a tendency to terminate
charge prior to reaching full capacity. With top-off en-
abled, charging continues at a reduced rate after
fast-charge termination for a period of time equal to
the fast-charge safety time (See Table 1.) During top-
off, the MOD pin is enabled at a duty cycle of 260µs ac-
tive for every 1820µs inactive. This modulation results
in an average rate 1/8th that of the fast charge rate.
Maximum voltage, time, and temperature are the only
termination methods enabled during top-off.
Charge status is indicated by the LED1 and LED2 out-
puts. The state of these outputs in the various charge cy-
cle phases is given in Table 2 and illustrated in Figure 2.
In all cases, if VCELL exceeds the voltage at the MCV
pin, both LED1 and LED2 outputs are held low regard-
less of other conditions. Both can be used to directly
drive an LED.
Charge Current Control
The bq2004 controls charge current through the MOD
output pin. The current control circuitry is designed to
support implementation of a constant-current switching
regulator or to gate an externally regulated current
source.
Pulse-Trickle Charge
Pulse-trickle charging follows the fast charge and op-
tional top-off charge phases to compensate for self-
discharge of the battery while it is idle in the charger.
The configured pulse-trickle rate is also applied in the
charge pending state to raise the voltage of an over-
discharged battery up to the minimum required before
fast charge can begin.
When used in switch mode configuration, the nominal
regulated current is:
I
REG = 0.225V/RSNS
Charge current is monitored at the SNS input by the
voltage drop across a sense resistor, RSNS, between the
low side of the battery pack and ground. RSNS is sized to
provide the desired fast charge current.
In the pulse-trickle mode, MOD is active for 260µs of a
period specified by the settings of TM1 and TM2. See
Table 1. The resulting trickle-charge rate is C/64 when
top-off is enabled and C/32 when top-off is disabled.
Both pulse trickle and top-off may be disabled by tying
If the voltage at the SNS pin is less than VSNSLO, the
MOD output is switched high to pass charge current to
the battery.
TM1 and TM2 to VSS
.
Table 1. Fast-Charge Safety Time/Hold-Off/Top-Off Table
Corresponding
Fast-Charge
Rate
Typical
Typical
Pulse-
Trickle
Rate
Pulse-
Trickle
Fast-Charge Safety PVD, -∆V Hold-Off Top-Off
TM1
Low
TM2
Low
Time (minutes)
Time (seconds)
Rate
Period (Hz)
C/4
C/2
1C
2C
4C
C/2
1C
2C
4C
360
180
90
137
820
410
200
100
820
410
200
100
Disabled Disabled
Disabled
240
120
60
Float
High
Low
Low
Disabled
Disabled
Disabled
Disabled
C/16
C/32
C/32
C/32
C/32
C/64
C/64
C/64
C/64
Low
Float
Float
Float
High
High
High
45
Float
High
Low
23
30
180
90
120
60
C/8
Float
High
45
C/4
30
23
C/2
15
Note:
Typical conditions = 25°C, VCC = 5.0V.
6
bq2004
When used to gate an externally regulated current
source, the SNS pin is connected to VSS, and no sense re-
sisitor is required.
When the SNS voltage is greater than VSNSHI, the MOD
output is switched low—shutting off charging current to
the battery.
VSNSLO = 0.04 ∗ VCC 25mV
VSNSHI = 0.05 ∗ VCC 25mV
Table 2. bq2004 LED Status Display Options
Mode 1
DSEL = VSS
Mode 2
Charge Status
LED1
Low
High
Low
High
LED1
Low
High
Low
LED2
Low
High
High
Low
LED2
Low
Low
High
High
LED2
Low
Battery absent
Fast charge pending or discharge-before-charge in progress
Fast charge in progress
Charge complete, top-off, and/or trickle
Charge Status
Battery absent, fast charge in progress or complete
Fast charge pending
DSEL = Floating
Mode 3
Discharge in progress
Top-off in progress
High
LED1
Low
Charge Status
Battery absent
1/8s high
1/8s low
Fast charge pending or discharge-before-charge in progress
Low
DSEL = VCC
Fast charge in progress
Fast charge complete, top-off, and/or trickle
Low
High
High
Low
TM1 TM2
TCO
Timing
Control
TCO
Check
TS
OSC
LED1
LED2
DSEL
LTF
Check
Display
Control
V
- V
TS SNS
A/D
SNS
BAT
V
- V
BAT SNS
DCMD
DVEN
Charge Control
State Machine
EDV
Check
MOD
Control
PWR
Control
MCV
Check
Discharge
Control
DIS
MOD
INH
V
V
CC SS
BD200401.eps
Figure 3. Block Diagram
7
bq2004
New Charge Cycle Started by
Any One of:
Rising Edge
on DCMD
V
Rising to Valid Level
CC
Yes
V
Battery Replacement
DCMD Tied to Ground?
No
(V
Falling through V
)
CELL
MCV
Inhibit (INH) Released
< V
Discharge-
Before-Charge
CELL
EDV
V
< V
< V
CELL MCV
EDV
Battery Voltage?
Charge
Pending
V
< V
V
> V
CELL
EDV
CELL
MCV
V
> V
CELL
MCV
V
V
> V
or
TEMP
LTF
< V
HTF
TEMP
V
>
CELL
Pulse
Trickle
V
MCV
Battery Temperature?
Charge
V
< V
< V
*
LTF
HTF
TEMP
Battery
Absent
V
< V
< V
EDV
CELL
MCV
and
V
< V
< V
*
HTF
TEMP
LTF
t > tMCV
Pulse
Trickle
Charge
Pulse
Trickle
Charge
Fast
Charge
V
V
MCV
>
CELL
-
V or
V
V
<
CELL
MCV
T/ t or
V
or
<
V
TCO
Charge
TEMP
Complete
V
V
V
V
>
>
CELL
MCV
CELL
MCV
Maximum Time Out
Pulse
Trickle
Charge
Top-Off
Selected?
Top-Off
Charge
Yes
V
< V
TCO
TEMP
No
or Maximum
Time Out
*VSEL = High disables LTF threshold enforcement
SD2004.eps
Figure 4. State Diagram
8
bq2004
Absolute Maximum Ratings
Symbol
VCC
Parameter
VCC relative to VSS
Minimum
Maximum
Unit
Notes
-0.3
+7.0
V
DC voltage applied on any pin ex-
cluding VCC relative to VSS
VT
-0.3
+7.0
V
TOPR
Operating ambient temperature
Storage temperature
-20
-55
-
+70
+125
+260
+85
°C
°C
°C
°C
Commercial
TSTG
TSOLDER
TBIAS
Soldering temperature
10 sec max.
Temperature under bias
-40
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Thresholds (T = T
; V 10%)
OPR CC
A
Symbol
Parameter
Rating
Tolerance
Unit
Notes
High threshold at SNS result-
ing in MOD = Low
0.05 VCC
*
VSNSHI
0.025
V
Low threshold at SNS result-
ing in MOD = High
VSNSLO
VLTF
0.04 * VCC
0.010
0.030
0.030
0.030
0.030
4
V
V
VTEMP ≥ VLTF inhib-
its/terminates charge
VTEMP ≤ VHTF inhibits
charge
VCELL < VEDV inhibits
fast charge
VCELL > VMCV inhibits/
terminates charge
0.4 VCC
*
Low-temperature fault
High-temperature fault
End-of-discharge voltage
Maximum cell voltage
(1/4 VLTF) + (2/3 VTCO
)
VHTF
VEDV
VMCV
VTHERM
-∆V
V
*
*
0.4 VCC
*
V
0.8 VCC
*
V
TS input change for∆T/∆t
detection
VCC = 5V, TA = 25°C
VCC = 5V, TA = 25°C
VCC = 5V, TA = 25°C
-16
-12
-6
mV
mV
mV
BAT input change for -∆V
detection
BAT input change for PVD
detection
4
PVD
2
9
bq2004
Recommended DC Operating Conditions (T = T
A
OPR)
Symbol
VCC
Condition
Supply voltage
Minimum
Typical Maximum
Unit
V
Notes
4.5
0
5.0
5.5
VBAT
Battery input
-
-
-
-
-
-
-
-
-
VCC
VCC
VCC
VCC
V
VCELL
VTS
VTEMP
VTCO
BAT voltage potential
Thermistor input
TS voltage potential
Temperature cutoff
Logic input high
Logic input high
Logic input low
0
V
VBAT - VSNS
0
V
0
V
VTS - VSNS
0.2 VCC
*
0.4 VCC
*
V
Valid ∆T/∆t range
DCMD, INH
2.0
-
V
VIH
VCC - 0.3
-
V
TM1, TM2, DSEL, VSEL
DCMD, INH
-
-
0.8
0.3
V
VIL
Logic input low
V
TM1, TM2, DSEL, VSEL
DIS, MOD, LED1, LED2,
VOH
VCC - 0.8
Logic output high
Logic output low
-
-
-
V
V
IOH ≤ -10mA
DIS, MOD, LED1, LED2,
IOL ≤ 10mA
VOL
-
0.8
ICC
ISB
IOH
IOL
Supply current
-
-
1
-
3
1
mA Outputs unloaded
µA
INH = VIL
Standby current
DIS, LED1, LED2, MOD source
DIS, LED1, LED2, MOD sink
Input leakage
-10
10
-
-
-
mA @VOH = VCC - 0.8V
mA @VOL = VSS + 0.8V
-
-
-
1
µA
µA
INH, BAT, V = VSS to VCC
IL
Input leakage
50
-
400
DCMD, V = VSS to VCC
TM1, TM2, DSEL, VSEL,
V = VSS to VSS + 0.3V
µA
µA
IIL
Logic input low source
Logic input high source
-
-
-
70
-
TM1, TM2, DSEL, VSEL,
V = VCC - 0.3V to VCC
IIH
-70
TM1, TM2, DSEL, and VSEL
should be left disconnected
(floating) for Z logic input state
µA
IIZ
Tri-state
-2
-
2
Note:
All voltages relative to VSS except as noted.
10
bq2004
Impedance
Symbol
Parameter
Minimum
Typical
Maximum
Unit
MΩ
MΩ
MΩ
MΩ
RBAT
RTS
Battery input impedance
TS input impedance
50
50
50
50
-
-
-
-
-
-
-
-
RTCO
RSNS
TCO input impedance
SNS input impedance
Timing (T = 0 to +70°C; V
10%)
CC
A
Symbol
Parameter
Minimum Typical Maximum
Unit
Notes
Pulse width for DCMD
and INH pulse command
Pulse start for charge or discharge
before charge
µs
tPW
dFCV
fREG
1
-16
-
-
-
-
-
Time base variation
16
%
VCC = 4.75V to 5.25V
MOD output regulation
frequency
300
kHz
Maximum voltage termi-
nation time limit
Time limit to distinguish battery re-
moved from charge complete.
tMCV
1
-
2
s
Note:
Typical is at TA = 25°C, VCC = 5.0V.
11
bq2004
16-Pin DIP Narrow (PN)
(
)
16-Pin PN 0.300" DIP
Inches
Millimeters
Min.
Dimension
Min.
Max.
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
Max.
4.57
1.02
0.56
1.65
0.33
19.56
8.26
7.11
9.40
2.79
3.81
1.02
A
A1
B
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
4.06
0.38
0.38
1.40
0.20
18.80
7.62
5.84
7.62
2.29
2.92
0.51
B1
C
D
E
E1
e
G
L
S
12
bq2004
16-Pin SOIC Narrow (SN)
(
)
16-Pin SN 0.150" SOIC
Inches
Millimeters
Dimension
Min.
Max.
Min.
Max.
1.78
0.25
0.51
0.25
10.16
4.06
1.40
6.22
0.89
D
B
e
A
A1
B
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
1.52
0.10
0.33
0.18
9.78
3.81
1.14
5.72
0.38
E
C
D
E
H
e
A
C
H
L
A1
.004
L
13
bq2004
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
1
2
10
9
Standby current ISB
VBSNSLO Rating
Was 5 µA max; is 1 µA max
Was: VSNSHI - (0.01 * VCC
Is: 0.04 * VCC
)
2
2
2
2
3
4
5
7
3
Correction in Peak Voltage Detect Termination section Was VCELL; is VBAT
Added block diagram
Diagram insertion
Table insertion
7
Added VSEL/termination table
Added values to Table 3
8
Top-off rate values
Low, High changed
Clarification
7
VSEL/Termination
All
9
Revised and expanded format of this data sheet
Corrected VHTF rating
Was: (1/3 ∗ VLTF) + (2/3 ∗
VTCO
)
Is: (1/4 ∗ VLTF) + (3/4 ∗ VTCO
)
6
9
TOPR
Deleted industrial tempera-
ture range
Notes:
Change 1 = Apr. 1994 B “Final” changes from Dec. 1993 A “Preliminary.”
Change 2 = Sept. 1996 C changes from Apr. 1994 B.
Change 3 = April 1997 C changes from Sept. 1996 C.
Change 4 = Oct. 1997 D changes from April 1997 C.
Change 5 = Jan. 1998 E changes from Oct. 1997 D.
Change 6 = June 1999 F changes from Jan. 1998 E.
14
bq2004
Ordering Information
bq2004
Package Option:
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC
Device:
bq2004 Fast-Charge IC
15
IMPORTANT NOTICE
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product or service without notice, and advise customers to obtain the latest version of relevant information to verify,
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accor-
dance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, ex-
cept those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,
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Copyright © 1999, Texas Instruments Incorporated
16
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