BQ2050SN-D119TR_技术文档

bq2050

Lithium Ion Power Gauge™ IC

supports a simple single-line bidi-

Features

General Description

rectional serial link to an external

➤ Conservative and repeatable

measurement of available capac-

ity in Lithium Ion rechargeable

batteries

The bq2050 Lithium Ion Power

Gauge™ IC is intended for battery-

pack or in-system installation to

maintain an accurate record of

available battery capacity. The IC

monitors a voltage drop across a

sense resistor connected in series

between the negative battery termi-

nal and ground to determine

charge and discharge activity of

the battery. Compensations for bat-

tery temperature and rate of charge

or discharge are applied to the

charge, discharge, and self-discharge

calculations to provide available ca-

pacity information across a wide

range of operating conditions. Bat-

tery capacity is automatically recali-

brated, or “learned,” in the course of

a discharge cycle from full to empty.

processor (common ground). The

bq2050 outputs battery information

in response to external commands

over the serial link.

➤ Designed for battery pack inte-

The bq2050 may operate directly

from one cell (V_BAT> 3V). With the

REF output and an external transis-

tor, a simple, inexpensive regulator

can be built for systems with more

than one series cell.

gration

- ¹²⁰µA typical operating

current

- ^{Small size enables imple-}

Internal registers include available

capacity, temperature, scaled avail-

able energy, battery ID, battery

status, and programming pin set-

tings. To support subassembly test-

ing, the outputs may also be con-

trolled. The external processor may

also overwrite some of the bq2050

power gauge data registers.

1

mentations in as little as

2

square inch of PCB

➤ Integrate within a system or as a

stand-alone device

- ^{Display capacity via single-}

wire serial communication

port or direct drive of LEDs

Nominal available capacity may be

directly indicated using a five-

segment LED display. These seg-

ments are used to graphically indi-

cate available capacity. The bq2050

➤ Measurements compensated for

current and temperature

➤ Self-discharge compensation us-

ing internal temperature sensor

➤ 16-pin narrow SOIC

Pin Connections

Pin Names

LCOM

LED common output

REF

N/C

DQ

Voltage reference output

No connect

SEG₁/PROG₁LED segment 1/

program 1 input

LCOM

1

2

3

4

5

6

16

15

14

13

12

11

V

CC

SEG /PROG

REF

N/C

DQ

RBI

SB

Serial communications

input/output

1

SEG₂/PROG₂LED segment 2/

program 2 input

SEG /PROG

2

RBI

SB

Register backup input

Battery sense input

Display control input

Sense resistor input

3.0–6.5V

SEG /PROG

3

SEG₃/PROG₃LED segment 3/

program 3 input

SEG /PROG

4

SEG /PROG

5

SEG₄/PROG₄LED segment 4/

program 4 input

DISP

SR

PROG

7

8

10

9

DISP

SR

6

V

SS

SEG₅/PROG₅LED segment 5/

program 5 input

V_CC

V_SS

16-Pin Narrow SOIC

PN205001.eps

PROG₆

Program 6 input

System ground

9/96 C

1

bq2050

Sense resistor input

SR

Pin Descriptions

The voltage drop (V_SR) across the sense re-

sistor R_Sis monitored and integrated over

time to interpret charge and discharge activ-

ity. The SR input is tied between the nega-

tive terminal of the battery and the sense re-

sistor. V_SR< V_SSindicates discharge, and V_SR

> V_SSindicates charge. The effective voltage

LED common output

LCOM

Open-drain output switches V_CCto source

current for the LEDs. The switch is off dur-

ing initialization to allow reading of the soft

pull-up or pull-down program resistors.

LCOM is also high impedance when the dis-

play is off.

drop, V_SRO, as seen by the bq2050 is V_SR

V_OS

+

.

LED display segment outputs (dual func-

tion with PROG₁–PROG₆)

SEG₁–

SEG₅

Display control input

DISP

Each output may activate an LED to sink

the current sourced from LCOM.

DISP high disables the LED display. DISP

tied to V_CCallows PROG_Xto connect directly

to V_CCor V_SSinstead of through a pull-up or

pull-down resistor. DISP floating allows the

LED display to be active during charge.

DISP low activates the display. See Table 1.

Programmed full count selection inputs

(dual function with SEG₁–SEG₂)

PROG₁–

PROG₂

These three-level input pins define the pro-

grammed full count (PFC) thresholds de-

scribed in Table 2.

Secondary battery input

SB

This input monitors the battery cell voltage

potential through a high-impedance resis-

tive divider network for end-of-discharge

voltage (EDV) thresholds, and battery re-

moved.

Power gauge rate selection inputs (dual

function with SEG₃–SEG₄)

PROG₃–

PROG₄

These three-level input pins define the scale

factor described in Table 2.

Register backup input

RBI

Self-discharge rate selection (dual func-

tion with SEG₅)

PROG₅

This pin is used to provide backup potential to

the bq2050 registers during periods when

V_CC≤ 3V. A storage capacitor or a battery

can be connected to RBI.

This three-level input pin defines the

selfdischarge and battery compensation fac-

tors as shown in Table 1.

Serial I/O pin

DQ

Capacity initialization selection

PROG₆

N/C

This is an open-drain bidirectional pin.

Voltage reference output for regulator

This three-level pin defines the battery state

of charge at reset as shown in Table 1.

REF

No connect

REF provides a voltage reference output for

an optional micro-regulator.

Supply voltage input

Ground

V_CC

V_SS

2

bq2050

scaled available energy measurement is corrected for

the environmental and operating conditions.

Functional Description

Figure 1 shows a typical battery pack application of the

bq2050 using the LED display capability as a charge-

state indicator. The bq2050 is configured to display ca-

pacity in relative display mode. The relative display

mode uses the last measured discharge capacity of the

battery as the battery “full” reference. A push-button

display feature is available for momentarily enabling

the LED display.

General Operation

The bq2050 determines battery capacity by monitor-

ing the amount of current input to or removed from a

rechargeable battery. The bq2050 measures dis-

charge and charge currents, measures battery volt-

age, estimates self-discharge, monitors the battery

for low battery voltage thresholds, and compensates

for temperature and charge/discharge rates. The cur-

rent measurement is made by monitoring the voltage

across a small-value series sense resistor between the

negative battery terminal and ground. The estimate of

scaled available energy is made using the remaining

average battery voltage during the discharge cycle

and the remaining nominal available charge. The

The bq2050 monitors the charge and discharge currents

as a voltage across a sense resistor (see R_Sin Figure 1).

A filter between the negative battery terminal and the

SR pin may be required if the rate of change of the bat-

tery current is too great.

R

1

1M

bq2050

Power Gauge IC

REF

Q1

ZVNL110A

C1

0.1 F

RB

1

V

LCOM

CC

SEG /PROG

1

SB

1

2

3

4

5

V

CC

C2

SEG /PROG

2

DISP

SR

SEG /PROG

3

SEG /PROG

4

SEG /PROG

5

R

S

V

PROG

6

SS

RBI

DQ

PSTAT

Charger

Indicates optional.

Load

Directly connect to V

CC

across 1 cell (V > 3V).

BAT

Otherwise, R1, C1, and Q1 are needed for regulation of > 1 cell.

Programming resistors (6 max.) and ESD-protection diodes are not shown.

R-C on SR may be required, application-specific.

A series Zener may be used to limit discharge current at low voltages

in designs using 3 or more cells.

FG205001.eps

Figure 1. Battery Pack Application Diagram—LED Display

3

bq2050

Voltage Thresholds

TMP (hex)

Temperature Range

< -30°C

In conjunction with monitoring V_SRfor charge/discharge

currents, the bq2050 monitors the battery potential

through the SB pin. The voltage is determined through

a resistor-divider network per the following equation:

0x

1x

2x

3x

4x

5x

6x

7x

8x

9x

Ax

Bx

Cx

-30°C to -20°C

-20°C to -10°C

-10°C to 0°C

0°C to 10°C

10°C to 20°C

20°C to 30°C

30°C to 40°C

40°C to 50°C

50°C to 60°C

60°C to 70°C

70°C to 80°C

> 80°C

RB1

RB2

= 2N − 1

where N is the number of cells, RB1 is connected to the

positive battery terminal, and RB2 is connected to the

negative battery terminal. The single-cell battery volt-

age is monitored for the end-of-discharge voltage (EDV).

EDV threshold levels are used to determine when the

battery has reached an “empty” state.

Two EDV thresholds for the bq2050 are programmable

with the default values fixed at:

EDV1 (early warning) = 1.52V

EDVF (empty) = 1.47V

If V_SBis below either of the two EDV thresholds, the as-

sociated flag is latched and remains latched, independ-

ent of V_SB, until the next valid charge. The V_SBvalue is

also available over the serial port.

During discharge and charge, the bq2050 monitors V_SR

for various thresholds used to compensate the charge

and discharge rates. Refer to the count compensation

section for details. EDV monitoring is disabled if the

discharge rate is greater than 2C (typical) and resumes

1

₂second after the rate falls below 2C.

Layout Considerations

RBI Input

The bq2050 measures the voltage differential between

the SR and V_SSpins. V_OS(the offset voltage at the SR

pin) is greatly affected by PC board layout. For optimal

results, the PC board layout should follow the strict rule

of a single-point ground return. Sharing high-current

ground with small signal ground causes undesirable

noise on the small signal nodes. Additionally:

The RBI input pin is intended to be used with a storage ca-

pacitor or external supply to provide backup potential to the

internal bq2050 registers when V_CCdrops below 3.0V. V_CC

is output on RBI when V_CCis above 3.0V. A diode is re-

quired to isolate the external supply.

Reset

n

The capacitors (C1 and C2) should be placed as

close as possible to the V_CCand SB pins,

The bq2050 can be reset either by removing V_CCand

grounding the RBI pin for 15 seconds or by writing 0x80

to register 0x39.

respectively, and their paths to V_SSshould be as

short as possible. A high-quality ceramic capacitor

of 0.1µf is recommended for V_CC

.

Temperature

n

The sense resistor capacitor should be placed as close

as possible to the SR pin.

The bq2050 internally determines the temperature in

10°C steps centered from approximately -35°C to +85°C.

The temperature steps are used to adapt charge and dis-

charge rate compensations, self-discharge counting, and

available charge display translation. The temperature

range is available over the serial port in 10°C incre-

ments as shown in the following table:

The sense resistor (R_S) should be as close as possible to

the bq2050.

4

bq2050

The battery's initial capacity is equal to the Pro-

grammed Full Count (PFC) shown in Table 2. Until

LMD is updated, NAC counts up to but not beyond this

threshold during subsequent charges. This approach al-

lows the gas gauge to be charger-independent and com-

patible with any type of charge regime.

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates

the operation of the bq2050. The bq2050 accumulates a

measure of charge and discharge currents, as well as an

estimation of self-discharge. Charge and discharge cur-

rents are temperature and rate compensated, whereas

self-discharge is only temperature compensated.

1. Last Measured Discharge (LMD) or learned

battery capacity:

The main counter, Nominal Available Capacity (NAC),

represents the available battery capacity at any given

time. Battery charging increments the NAC register,

while battery discharging and self-discharge decrement

the NAC register and increment the DCR (Discharge

Count Register).

LMD is the last measured discharge capacity of the

battery. On initialization (application of V_CCor bat-

tery replacement), LMD = PFC. During subsequent

discharges, the LMD is updated with the latest

measured capacity in the Discharge Count Register

(DCR) representing a discharge from full to below

EDV1. A qualified discharge is necessary for a capac-

ity transfer from the DCR to the LMD register. The

LMD also serves as the 100% reference threshold

used by the relative display mode.

The Discharge Count Register (DCR) is used to update

the Last Measured Discharge (LMD) register only if a

complete battery discharge from full to empty occurs

without any partial battery charges. Therefore, the

bq2050 adapts its capacity determination based on the

actual conditions of discharge.

Charge

Inputs

Discharge

Current

Self-Discharge

Timer

Current

Rate and

Temperature

Compensation

Rate and

Temperature

Compensation

Temperature

Compensation

+

-

Nominal

Available

Charge

(NAC)

Last

Measured

Discharged Qualified Register

(LMD) (DCR)

Transfer

Discharge

Count

+

<

Main Counters

and Capacity

Reference (LMD)

Temperature Step,

Other Data

Temperature

Translation

Compensated

Available Charge

LED Display, etc.

Serial

Port

Outputs

FG205002.eps

Figure 2. Operational Overview

5

bq2050

2. Programmed Full Count (PFC) or initial bat-

tery capacity:

Example: Selecting a PFC Value

Given:

The initial LMD and gas gauge rate values are pro-

grammed by using PROG₁–PROG₄. The bq2050 is

configured for a given application by selecting a

PFC value from Table 2. The correct PFC may be

determined by multiplying the rated battery capac-

ity in mAh by the sense resistor value:

Sense resistor = 0.05Ω

Number of cells = 2

Capacity = 1000mAh, Li-Ion battery, coke-anode

Current range = 50mA to 1A

Relative display mode

Serial port only

Self-discharge =

NAC

Battery capacity (mAh) sense resistor (Ω) =

₅₁₂per day @ 25°C

*

Voltage drop over sense resistor = 2.5mV to 50mV

Nominal discharge voltage = 3.6V

PFC (mVh)

Selecting a PFC slightly less than the rated capac-

ity provides a conservative capacity reference until

the bq2050 “learns” a new capacity reference.

Therefore:

1000mAh 0.05Ω = 50mVh

*

Table 1. bq2050 Programming

Connection

PROG₅Compensation/

PROG₆

NAC on Reset

DISP

Display State

Self-Discharge

H

Z

Table 4/Disabled

PFC

LEDs disabled

LEDs on when charging

LEDs on for 4 sec.

NAC

Table 4/

512

0

NAC

Table 3/

512

L

Note:

PROG₅and PROG₆states are independent.

Table 2. bq2050 Programmed Full Count mVh Selections

Pro-

grammed

Full

PROG_x

PROG₄= L

PROG₄= Z

Count

(PFC)

Units

1

2

PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L

SCALE =

1/80

SCALE =

1/160

SCALE =

1/320

SCALE =

1/640

SCALE =

1/1280

SCALE =

1/2560

mVh/

count

-

H

Z

H

Z

49152

45056

40960

36864

33792

30720

27648

25600

22528

614

563

512

461

422

384

346

320

282

307

282

256

230

211

192

173

160

141

154

141

128

115

106

96.0

86.4

80.0

70.4

76.8

70.4

64.0

57.6

53.0

48.0

43.2

40.0

35.2

38.4

35.2

32.0

28.8

26.4

24.0

21.6

20.0

17.6

19.2

17.6

16.0

14.4

13.2

12.0

10.8

10.0

8.8

mVh

L

H

Z

L

H

Z

L

VSR equivalent to 2

counts/sec. (nom.)

90

45

22.5

11.25

5.6

2.8

mV

6

bq2050

Select:

E(mWh) = (SAEH * 256 + SAEL) *

2.4 ∗ SCALE ∗ (R_B1+ R_B2

R_S∗ R_B2

)

PFC = 30720 counts or 48mVh

PROG₁= float

PROG₂= low

PROG₃= high

where R_B1, R_B2and R_Sare resistor values in ohms.

SCALE is the selected scale from Table 2. SAEH

and SAEL are digital values read via DQ.

PROG₄= float

PROG₅= float

PROG₆= float

6. Compensated Available Capacity (CAC)

The initial full battery capacity is 48mVh (960mAh)

until the bq2050 “learns” a new capacity with a

qualified discharge from full to EDV1.

CAC counts similar to NAC, but contains the avail-

able capacity compensated for discharge rate and

temperature.

3. Nominal Available Capacity (NAC):

Charge Counting

NAC counts up during charge to a maximum value

of LMD and down during discharge and self-dis-

charge to 0. NAC is reset to 0 on initialization and on

the first valid charge following discharge to EDV1. To

prevent overstatement of charge during periods of

overcharge, NAC stops incrementing when NAC =

LMD.

Charge activity is detected based on a positive voltage

on the V_SRinput. If charge activity is detected, the

bq2050 increments NAC at a rate proportional to V_SRand,

if enabled, activates an LED display. Charge actions in-

crement the NAC after compensation for temperature.

The bq2050 determines charge activity sustained at a

continuous rate equivalent to V_SRO> V_SRQ. A valid

charge equates to sustained charge activity greater

than 256 NAC counts. Once a valid charge is detected,

charge counting continues until V_SRO(V_SR+ V_OS) falls

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent of

NAC and could continue increasing after NAC has

decremented to 0. Prior to NAC = 0 (empty battery),

both discharge and self-discharge increment the

DCR. After NAC = 0, only discharge increments the

DCR. The DCR resets to 0 when NAC = LMD. The

DCR does not roll over but stops counting when it

reaches FFFFh.

below V_SRQ

. V_SRQis 210µV, and is described in the

Digital Magnitude Filter section.

Discharge Counting

Discharge activity is detected based on a negative voltage

on the V_SRinput. All discharge counts where V_SRO< V_SRD

cause the NAC register to decrement and the DCR to

increment. V_SRDis -200µV, and is described in the

Digital Magnitude Filter section.

The DCR value becomes the new LMD value on the

first charge after a valid discharge to V_EDV1if:

No valid charge initiations (charges greater than

256 NAC counts, where V_SRO> V_SRQ) occurred dur-

ing the period between NAC = LMD and EDV1 de-

tected.

Self-Discharge Estimation

The bq2050 continuously decrements NAC and increments

DCR for self-discharge based on time and temperature. The

self-discharge count rate is programmed to be a nominal

The self-discharge count is not more than 4096

counts (8% to 18% of PFC, specific percentage

threshold determined by PFC).

1

NAC per day or disabled. This is the rate for a bat-

512

*

tery whose temperature is between 20°–30°C. The NAC

register cannot be decremented below 0.

The temperature is ≥ 0°C when the EDV1 level is

reached during discharge.

The valid discharge flag (VDQ) indicates whether

the present discharge is valid for LMD update.

Count Compensations

Discharge Compensation

5. Scaled Available Energy (SAE):

Corrections for the rate of discharge, temperature, and anode

type are made by adjusting an internal compensation factor.

This factor is based on the measured rate of discharge of the

battery. Tables 3A and 3B outline the correction factor typi-

cally used for graphite anode Li-Ion batteries, and Tables 4A

and 4B outline the factors typically used for coke anode

Li-Ion batteries. The compensation factor is applied to

CAC and is based on discharge rate and temperature.

SAE is useful in determining the available energy

within the battery, and may provide a more useful

capacity reference in battery chemistries with

sloped voltage profiles during discharge. SAE may

be converted to a mWh value using the following

formula:

7

bq2050

Charge Compensation

Table 3A. Graphite Anode

The bq2050 applies the following temperature compen-

sation to NAC during charge:

Discharge

Compensation

Factor

Approximate

Discharge Rate

Efficiency

100%

Temperature

Compensation

< 0.5C

≥ 0.5C

1.00

1.05

Temperature

< 10°C

Factor

Efficiency

95%

0.95

≥ 10°C

1.00

100%

This compensation applies to both types of Li-Ion cells.

Table 3B. Graphite Anode

Self-Discharge Compensation

The self-discharge compensation is programmed for a

Temperature

1

nominal rate of

NAC per day. This is the rate for a

Compensation

512

*

battery within the 20°C–30°C temperature range. This

rate varies across 8 ranges from < 10°C to > 70°C, chang-

ing with each higher temperature (approximately 10°C).

See Table 5 below:

Temperature

Factor

Efficiency

≥ 10°C

0°C to 10°C

-10°C to 0°C

≤ -10°C

1.00

100%

90%

74%

40%

1.10

1.35

Table 5. Self-Discharge Compensation

2.50

Typical Rate

Temperature Range

< 10°C

PROG₅= Z or L

NAC

2048

NAC

1024

10–20°C

Table 4A. Coke Anode

NAC

512

20–30°C

Discharge

Compensation

Factor

NAC

256

30–40°C

Approximate

NAC

128

Discharge Rate

Efficiency

100%

40–50°C

NAC

64

50–60°C

<0.5C

1.00

1.15

NAC

32

60–70°C

≥ 0.5C

86%

NAC

16

> 70°C

Self-discharge may be disabled by connecting PROG₅= H.

Table 4B. Coke Anode

Digital Magnitude Filter

The bq2050 has a digital filter to eliminate charge and dis-

charge counting below a set threshold. The bq2050 setting

Temperature

Compensation

is 200µV for V_SRDand 210µV for V_SRQ

.

Temperature

Factor

Efficiency

100%

80%

≥ 10°C

0°C to 10°C

-10°C to 0°C

≤ -10°C

1.00

1.25

2.00

50%

8.00

12%

8

bq2050

Table 6. bq2050 Current-Sensing Errors

Symbol

INL

INR

Parameter

Typical

Maximum

Units

Notes

Integrated non-linearity

error

Add 0.1% per °C above or below 25°C

and 1% per volt above or below 4.25V.

2

4

%

Integrated non-

repeatability error

Measurement repeatability given

similar operating conditions.

1

2

%

eight bits that have a maximum transmission rate of

333 bits/sec. The least-significant bit of a command or

data byte is transmitted first. The protocol is simple

enough that it can be implemented by most host proces-

sors using either polled or interrupt processing. Data

input from the bq2050 may be sampled using the pulse-

width capture timers available on some microcontrol-

lers.

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no

updates occur. On initialization, the LMD value in-

cludes the error between the programmed full capacity

and the actual capacity. This error is present until a

valid discharge occurs and LMD is updated (see the

DCR description on page 7). The other cause of LMD er-

ror is battery wear-out. As the battery ages, the meas-

ured capacity must be adjusted to account for changes in

actual battery capacity.

If a communication error occurs, e.g. t_CYCB> 6ms, the

bq2050 should be sent a BREAK to reinitiate the serial

interface. A BREAK is detected when the DQ pin is

driven to a logic-low state for a time, t_Bor greater. The

DQ pin should then be returned to its normal ready-

high logic state for a time, t_BR. The bq2050 is now ready

to receive a command from the host processor.

A Capacity Inaccurate counter (CPI) is maintained and

incremented each time a valid charge occurs (qualified

by NAC; see the CPI register description) and is reset

whenever LMD is updated from the DCR. The counter

does not wrap around but stops counting at 255. The ca-

pacity inaccurate flag (CI) is set if LMD has not been up-

dated following 64 valid charges.

The return-to-one data bit frame consists of three dis-

tinct sections. The first section is used to start the

transmission by either the host or the bq2050 taking the

DQ pin to a logic-low state for a period, t_STRH,B

. The

next section is the actual data transmission, where the

data should be valid by a period, t_DSU, after the negative

edge used to start communication. The data should be

held for a period, t_DV, to allow the host or bq2050 to

sample the data bit.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func-

tion of V_SRO. A digital filter eliminates charge and dis-

charge counts to the NAC register when V_SROis between

The final section is used to stop the transmission by re-

turning the DQ pin to a logic-high state by at least a pe-

riod, t_SSU, after the negative edge used to start commu-

nication. The final logic-high state should be held until

a period, t_SV, to allow time to ensure that the bit trans-

mission was stopped properly. The timings for data and

break communication are given in the serial communi-

cation timing specification and illustration sections.

V_SRQand V_SRD.

Communicating With the bq2050

The bq2050 includes a simple single-pin (DQ plus re-

turn) serial data interface. A host processor uses the in-

terface to access various bq2050 registers. Battery char-

acteristics may be easily monitored by adding a single

contact to the battery pack. The open-drain DQ pin on

the bq2050 should be pulled up by the host system, or may

be left floating if the serial interface is not used.

Communication with the bq2050 is always performed with

the least-significant bit being transmitted first. Figure 3

shows an example of a communication sequence to read

the bq2050 NAC register.

The interface uses a command-based protocol, where the

host processor sends a command byte to the bq2050.

The command directs the bq2050 to either store the next

eight bits of data received to a register specified by the

command byte or output the eight bits of data specified

by the command byte.

The communication protocol is asynchronous return-to-

one. Command and data bytes consist of a stream of

9

bq2050

Written by Host to bq2050

CMDR = 03h

Received by Host to bq2050

NAC = 65h

LSB

MSB

LSB

MSB

Break 1 1 0 0 0 0 0 0

1 0 1 0 0 1 1 0

DQ

TD205002.eps

Figure 3. Typical Communication With the bq2050

Primary Status Flags Register (FLGS1)

bq2050 Registers

The read-only FLGS1 register (address=01h) contains

the primary bq2050 flags.

The bq2050 command and status registers are listed in

Table 7 and described below.

The charge status flag (CHGS) is asserted when a

valid charge rate is detected. Charge rate is deemed

valid when V_SRO> V_SRQ. A V_SROof less than V_SRQor

discharge activity clears CHGS.

Command Register (CMDR)

The write-only CMDR register is accessed when eight

valid command bits have been received by the bq2050.

The CMDR register contains two fields:

The CHGS values are:

n

W/R bit

FLGS1 Bits

n

Command address

7

6

-

5

4

3

2

1

0

The W/R bit of the command register is used to select whether

the received command is for a read or a write function.

CHGS

-

Where CHGS is:

The W/R values are:

0

Either discharge activity detected or V_SRO

V_SRQ

<

CMDR Bits

7

6

-

5

4

3

2

1

0

1

V_SRO> V_SRQ

W/R

-

The battery replaced flag (BRP) is asserted whenever

the bq2050 is reset either by application of V_CCor by a

serial port command. BRP is reset when either a valid

charge action increments NAC to be equal to LMD, or a

valid charge action is detected after the EDV1 flag is as-

serted. BRP = 1 signifies that the device has been reset.

Where W/R is:

0

The bq2050 outputs the requested register con-

tents specified by the address portion of CMDR.

1

The following eight bits should be written

to the register specified by the address por-

tion of CMDR.

The BRP values are:

FLGS1 Bits

The lower seven-bit field of CMDR contains the address

portion of the register to be accessed. Attempts to write

to invalid addresses are ignored.

7

6

5

4

3

2

1

0

-

BRP

-

CMDR Bits

Where BRP is:

7

6

5

4

3

2

1

0

Battery is charged until NAC = LMD or dis-

charged until the EDV1 flag is asserted

AD0

(LSB)

-

AD6 AD5 AD4 AD3 AD2 AD1

1

bq2050 is reset

10

bq2050

Table 7. bq2050 Command and Status Registers

Loc. Read/

(hex) Write

Control Field

Register Name

Symbol

7(MSB)

6

5

4

3

2

1

0(LSB)

CMDR Command register

00h Write W/R

01h Read CHGS

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Primary status flags

FLGS1

register

BRP

n/u

CI

VDQ

GG3

n/u

EDV1 EDVF

GG1 GG0

TMP

Temperature register 02h Read TMP3

Nominal available ca-

TMP2

TMP1 TMP0

GG2

NACH pacity high byte reg- 03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

ister

Nominal available

NACL capacity low byte

register

Battery

BATID identification

register

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

Last measured dis-

charge register

LMD

05h R/W LMD7

LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

Secondary status

FLGS2

06h Read

07h Read

08h Read

n/u

DR2

n/u

DR1

PPD6 PPD5

PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

DR0

n/u

OVLD

flags register

Program pin pull-

down register

Program pin pull-up

register

PPD

PPD4 PPD3 PPD2 PPD1

PPU

n/u

Capacity

CPI

inaccurate count reg- 09h Read CPI7

ister

CPI6

CPI5

CPI4

CPI3

VSB3 VSB2 VSB1

VTS3 VTS2 VTS1

CPI2

CPI1

CPI0

Battery voltage

0Bh Read VSB7

register

End-of-discharge thresh-

0Ch R/W VTS7

old select register

VSB

VTS

VSB6

VTS6

VSB5 VSB4

VTS5 VTS4

VSB0

VTS0

Compensated avail-

CACH able capacity high byte 0Dh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0

register

Compensated

CACL available capacity low 0Eh Read CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0

byte register

Scaled available

SAEH energy high byte reg- 0Fh Read SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0

ister

Scaled available

SAEL

energy low byte regis- 10h Read SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0

ter

RST

Reset register

n/u = not used

39h Write RST

0

Note:

11

bq2050

The EDV1 values are:

The capacity inaccurate flag (CI) is used to warn the

user that the battery has been charged a substantial

number of times since LMD has been updated. The CI

flag is asserted on the 64th charge after the last LMD

update or when the bq2050 is reset. The flag is cleared

after an LMD update.

FLGS1 Bits

7

6

5

4

3

2

1

0

-

EDV1

-

The CI values are:

Where EDV1 is:

FLGS1 Bits

0

1

Valid charge action detected, V_SB≥ V_TS

7

6

5

4

3

2

1

0

V_SB< V_TSproviding that the discharge rate is

< 2C

-

CI

-

The final end-of-discharge warning flag (EDVF) flag

is used to warn that battery power is at a failure condi-

tion. All segment drivers are turned off. The EDVF flag

is latched until a valid charge has been detected. The

EDVF threshold is set 50mV below the EDV1 threshold.

Where CI is:

0

When LMD is updated with a valid full dis-

charge

1

After the 64th valid charge action with no

LMD updates or the bq2050 is reset

The EDVF values are:

The valid discharge flag (VDQ) is asserted when the

bq2050 is discharged from NAC=LMD. The flag remains

set until either LMD is updated or one of three actions

that can clear VDQ occurs:

FLGS1 Bits

7

6

5

4

3

2

1

0

-

EDVF

n

The self-discharge count register (SDCR) has

exceeded the maximum acceptable value (4096

counts) for an LMD update.

Where EDVF is:

0

Valid charge action detected, V_SB≥ (V_TS-

50mV)

n

A valid charge action sustained at V_SRO> V_SRQfor at

least 256 NAC counts.

1

V

_SB< (V_TS- 50mV) providing the discharge

rate is < 2C

The EDV1 flag was set at a temperature below 0°C

The VDQ values are:

Temperature Register (TMP)

The read-only TMP register (address=02h) contains the

battery temperature.

FLGS1 Bits

7

6

5

4

3

2

1

0

-

VDQ

-

TMP Temperature Bits

7

6

5

4

3

2

1

0

Where VDQ is:

TMP4 TMP3 TMP2 TMP1

-

0

SDCR ≥ 4096, subsequent valid charge ac-

tion detected, or EDV1 is asserted with the

temperature less than 0°C

The bq2050 contains an internal temperature sensor.

The temperature is used to set charge and discharge ef-

ficiency factors as well as to adjust the self-discharge co-

efficient. The temperature register contents may be

translated as shown in Table 7.

1

On first discharge after NAC = LMD

The first end-of-discharge warning flag (EDV1)

warns the user that the battery is almost empty. The

first segment pin, SEG₁, is modulated at a 4Hz rate if

the display is enabled once EDV1 is asserted, which

should warn the user that loss of battery power is immi-

nent. The EDV1 flag is latched until a valid charge has

been detected. The EDV1 threshold is externally con-

trolled via the VTS register (see Voltage Threshold Reg-

ister on this page).

The bq2050 calculates the gas gauge bits, GG3-GG0 as a

function of CACH and LMD. The results of the calculation

1

15

give available capacity in ₁₆increments from 0 to

.

16

12

bq2050

Table 7. Temperature Register

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the

bq2050 uses as a measured full reference. The bq2050

adjusts LMD based on the measured discharge capacity

of the battery from full to empty. In this way the bq2050

updates the capacity of the battery. LMD is set to PFC

during a bq2050 reset.

TMP3

TMP2

TMP1

TMP0

Temperature

T < -30°C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-30°C < T < -20°C

-20°C < T < -10°C

-10°C < T < 0°C

0°C < T < 10°C

10°C < T < 20°C

20°C < T < 30°C

30°C < T < 40°C

40°C < T < 50°C

50°C < T < 60°C

60°C < T < 70°C

70°C < T < 80°C

T > 80°C

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains

the secondary bq2050 flags.

FLGS2 Bits

7

6

5

4

3

2

1

0

-

DR2

DR1

DR0

-

The discharge rate flags, DR2–0, are bits 6–4.

DR2

DR1

DR0

Discharge Rate

0

1

0

1

0

DRATE < 0.5C

0.5C ≤ DRATE < 2C

DRATE ≥ 2C (OVLD = 1)

TMPGG Gas Gauge Bits

They are used to determine the current discharge re-

gime as follows:

7

6

5

4

3

2

1

0

-

GG3 GG2 GG1 GG0

FLGS2 Bits

Nominal Available Charge Registers

(NACH/NACL)

7

6

5

4

3

2

1

0

-

OVLD

The read/write NACH high-byte register (address=03h) and

the read-only NACL low-byte register (address=17h) are

the main gas gauging register for the bq2050. The NAC

registers are incremented during charge actions and decre-

mented during discharge and self-discharge actions. The

correction factors for charge/discharge efficiency are applied

automatically to NAC. NACH and NACL are set to 0 dur-

ing a bq2050 reset.

The overload flag (OVLD) is asserted when a discharge

rate in excess of 2C is detected. OVLD remains asserted

as long as the condition persists and is cleared 0.5 sec-

onds after the rate drops below 2C. The overload condi-

tion is used to stop sampling of the battery terminal char-

acteristics for end-of-discharge determination.

Program Pin Pull-Down Register (PPD)

Writing to the NAC registers affects the available charge

counts and, therefore, affects the bq2050 gas gauge opera-

tion. Do not write the NAC registers to a value greater than

LMD.

The read-only PPD register (address=07h) contains some

of the programming pin information for the bq2050. The

segment drivers, SEG_1–6, have a corresponding PPD regis-

ter location, PPD_1–6. A given location is set if a pull-down

resistor has been detected on its corresponding segment

driver. For example, if SEG₁and SEG₄have pull-down

resistors, the contents of PPD are xx001001.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail-

able for use by the system to determine the type of bat-

tery pack. The BATID contents are retained as long as

V_CCis greater than 2V. The contents of BATID have no

effect on the operation of the bq2050. There is no de-

fault setting for this register.

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the rest

of the programming pin information for the bq2050. The

segment drivers, SEG_1–6, have a corresponding PPU regis-

ter location, PPU_1–6. A given location is set if a pull-up re-

sistor has been detected on its corresponding segment

13

bq2050

driver. For example, if SEG₃and SEG₆have pull-up resis-

tors, the contents of PPU are xx100100.

VTS Register Bits

7

6

5

4

3

2

1

0

PPD/PPU Bits

VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

7

-

6

-

5

4

3

2

1

0

Compensated Available Charge Registers

(CACH/CACL)

PPU₆PPU₅PPU₄PPU₃PPU₂PPU₁

PPD₆PPD₅PPD₄PPD₃PPD₂PPD₁

-

The read-only CACH high-byte register (address = 0Dh)

and the read-only CACL low-byte register (address =

0Eh) represent the available charge compensated for

discharge rate and temperature. CACH and CACL use

piece-wise corrections as outlined in Tables 3A, 3B, 4A,

and 4B, and will vary as conditions change. The NAC

and LMD registers are not affected by the discharge

rate and temperature.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in-

dicate the number of times a battery has been charged

without an LMD update. Because the capacity of a re-

chargeable battery varies with age and operating condi-

tions, the bq2050 adapts to the changing capacity over

time. A complete discharge from full (NAC=LMD) to

empty (EDV1=1) is required to perform an LMD update

assuming there have been no intervening valid charges,

the temperature is greater than or equal to 0°C, and the

self-discharge counter is less than 4096 counts.

Scaled Available Energy Registers

(SAEH/SAEL)

The read-only SAEH high-byte register (address = 0Fh)

and the read only SAEL low-byte register (address =

10h) are used to scale battery voltage and CAC to a

value which can be translated to watt-hours remaining

under the present conditions. SAEL and SAEH may be

converted to mWh using the formula on page 7.

The CPI register is incremented every time a valid

charge is detected. When NAC > 0.94 LMD, however,

*

the CPI register increments on the first valid charge;

CPI does not increment again for a valid charge until

NAC < 0.94

LMC. This prevents continuous trickle

*

Reset Register (RST)

charging from incrementing CPI if self-discharge decre-

ments NAC. The CPI register increments to 255 with-

out rolling over. When the contents of CPI are incre-

mented to 64, the capacity inaccurate flag, CI, is as-

serted in the FLGS1 register. The CPI register is reset

whenever an update of the LMD register is performed,

and the CI flag is also cleared.

The reset register (address = 39h) enables a software-

controlled reset of the device. By writing the RST regis-

ter contents from 00h to 80h, a bq2050 reset is per-

formed. Setting any bit other than the most-significant

bit of the RST register is not allowed and results in im-

proper operation of the bq2050.

Battery Voltage Register (VSB)

Resetting the bq2050 sets the following:

The read-only battery voltage register is used to read the

single-cell battery voltage on the SB pin. The VSB regis-

ter (address = 0Bh) is updated approximately once per sec-

n

LMD = PFC

CPI, VDQ, NACH, and NACL = 0

CI and BRP = 1

ond with the present value of the battery voltage. V_SB

2.4V (VSB/256).

=

*

Note: Self-discharge is disabled when PROG₅= H.

VSB Register Bits

Display

7

6

5

4

3

2

1

0

VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

The bq2050 can directly display capacity information

using low-power LEDs. If LEDs are used, the program

pins should be resistively tied to V_CCor V_SSfor a pro-

gram high or program low, respectively.

Voltage Threshold Register (VTS)

The end-of-discharge threshold voltages (EDV1 and

EDVF) can be set using the VTS register (address =

0Ch). The read/write VTS register sets the EDV1 trip

point. EDVF is set 50mV below EDV1. The default

value in the VTS register is A2h, representing EDV1 =

The bq2050 displays the battery charge state in relative

mode. In relative mode, the battery charge is represented

as a percentage of the LMD. Each LED segment repre-

sents 20% of the LMD.

1.52V and EDVF = 1.47V. EDV1 = 2.4V (VTS/256).

*

The capacity display is also adjusted for the present bat-

tery temperature. The temperature adjustment reflects

the available capacity at a given temperature but does

14

bq2050

not affect the NAC register. The temperature adjust-

ments are detailed in the CACH and CACL register de-

scriptions.

SEG₁blinks at a 4Hz rate whenever V_SBhas been de-

tected to be below V_EDV1(EDV1 = 1), indicating a low-

battery condition. V_SBbelow V_EDVF(EDVF = 1) disables

the display output.

When DISP is tied to V_CC, the SEG_1–5outputs are inac-

tive. When DISP is left floating, the display becomes ac-

tive whenever the bq2050 detects a charge in progress

V_SRO> V_SRQ. When pulled low, the segment outputs be-

come active for a period of four seconds, 0.5 seconds.

Microregulator

The bq2050 can operate directly from one cell. A micro-

power source for the bq2050 can be inexpensively built

using the FET and an external resistor to accommodate

a greater number of cells; see Figure 1.

The segment outputs are modulated as two banks, with

segments 1, 3, and 5 alternating with segments 2 and 4.

The segment outputs are modulated at approximately

100Hz with each segment bank active for 30% of the pe-

riod.

15

bq2050

Absolute Maximum Ratings

Symbol

V_CC

Parameter

Relative to V_SS

Minimum

-0.3

Maximum

7.0

Unit

V

Notes

All other pins

REF

-0.3

7.0

V

-0.3

8.5

V

Current limited by R1 (see Figure 1)

Minimum 100Ω series resistor should

be used to protect SR in case of a

shorted battery (see the bq2050 appli-

cation note for details).

V_SR

Relative to V_SS

-0.3

7.0

V

0

70

85

°C

Commercial

Industrial

Operating tempera-

ture

T_OPR

-40

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-

ditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T = T

; V = 3.0 to 6.5V)

OPR

A

Symbol

V_EDVF

V_EDV1

V_SRO

Parameter

Final empty warning

First empty warning

SR sense range

Minimum

1.44

1.49

-300

210

Typical

Maximum

1.50

Unit

V

Notes

1.47

SB

1.52

1.55

V

-

2000

-

mV SR, V_SR+ V_OS

V_SRQ

Valid charge

-

µV

V

V_SR+ V_OS(see note)

V_SRD

Valid discharge

-

-200

2.30

V_SR+ V_OS(see note)

SB

V_MCV

Maximum single-cell voltage

2.20

2.25

Note:

V_OSis affected by PC board layout. Proper layout guidelines should be followed for optimal performance.

See “Layout Considerations.”

16

bq2050

DC Electrical Characteristics (T = T

)

A

OPR

Symbol

V_CC

Parameter

Supply voltage

Minimum Typical Maximum

Unit

Notes

V_CCexcursion from < 2.0V to ≥

3.0V initializes the unit.

3.0

4.25

6.5

V

V_OS

Offset referred to V_SR

Reference at 25°C

DISP = V_CC

I_REF= 5µA

-

5.7

4.5

2.0

-

50

150

6.3

7.5

-

µV

V

6.0

V_REF

R_REF

Reference at -40°C to +85°C

Reference input impedance

-

V

5.0

MΩ V_REF= 3V

µA V_CC= 3.0V, DQ = 0

µA V_CC= 4.25V, DQ = 0

90

135

180

250

V_CC

-

I_CC

Normal operation

-

120

-

170

µA

V

V_CC= 6.5V, DQ = 0

V_SB

Battery input

0

-

R_SBmax

I_DISP

I_LCOM

I_RBI

SB input impedance

DISP input leakage

LCOM input leakage

RBI data retention current

Internal pulldown

10

-

MΩ 0 < V_SB< V_CC

µA V_DISP= V_SS

µA DISP = V_CC

nA V_RBI> V_CC< 3V

KΩ

5

-0.2

-

0.2

100

-

R_DQ

500

V_SR< V_SS= discharge;

_SR> V_SS= charge

V_SR

Sense resistor input

-0.3

-

2.0

V

R_SR

V_IH

V_IL

V_IZ

SR input impedance

Logic input high

Logic input low

Logic input Z

10

V_CC- 0.2

-

MΩ -200mV < V_SR< V_CC

V

PROG₁–PROG₆

V_SS+ 0.2

float

V_CC= 3V, I_OLS≤ 1.75mA

V_OLSL

V_OLSH

SEG_Xoutput low, low V_CC

SEG_Xoutput low, high V_CC

-

0.1

0.4

-

V

SEG₁–SEG₅

V_CC= 6.5V, I_OLS≤ 11.0mA

SEG₁–SEG₅

V_OHLCLLCOM output high, low V_CC

V_OHLCHLCOM output high, high V_CC

V_CC- 0.3

-

V

V_CC= 3V, I_OHLCOM= -5.25mA

V_CC= 6.5V, I_OHLCOM= -33.0mA

V_CC- 0.6

-

I_IH

I_IL

PROG_1-6input high current

PROG_1-6input low current

-

1.2

-

µA V_PROG= V_CC/2

mA At V_OHLCH= V_CC- 0.6V

mA At V_OLSH= 0.4V

-

I_OHLCOMLCOM source current

-33

-

I_OLS

SEG_1-5sink current

-

11.0

At V_OL= V_SS+ 0.3V

I_OL

Open-drain sink current

-

5.0

mA

DQ

V_OL

Open-drain output low

DQ input high

-

2.5

-

0.5

-

V

I_OL≤ 5mA, DQ

DQ

V_IHDQ

V_ILDQ

DQ input low

0.8

Soft pull-up or pull-down resis-

tor value (for programming)

R_PROG

R_FLOAT

Note:

PROG₁–PROG₆

-

200

-

KΩ

Float state external impedance

5

MΩ PROG₁–PROG₆

All voltages relative to V_SS

.

17

bq2050

Serial Communication Timing Specification (T = T

)

A

OPR

Symbol

t_CYCH

t_CYCB

t_STRH

t_STRB

t_DSU

t_DH

Parameter

Cycle time, host to bq2050

Cycle time, bq2050 to host

Start hold, host to bq2050

Start hold, bq2050 to host

Data setup

Minimum

Typical

Maximum

Unit

ms

ns

Notes

See note

3

-

6

5

-

500

-

µs

750

µs

Data hold

750

1.50

-

µs

t_DV

Data valid

-

ms

µs

t_SSU

t_SH

Stop setup

2.25

Stop hold

700

2.95

3

-

t_SV

Stop valid

ms

t_B

Break

t_BR

Break recovery

1

Notes:

The open-drain DQ pin should be pulled to at least V_CCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

Serial Communication Timing

DQ

(R/W "1")

t

STRH

DQ

t

STRB

(R/W "0")

t

DH

DSU

t

DV

t

SH

SSU

DQ

t

SV

(BREAK)

t

BR

CYCH, CYCB, B

TD201002.eps

18

bq2050

16-Pin SOIC Narrow (SN)

(

)

16-Pin SN 0.150" SOIC

Inches

Millimeters

D

B

Min.

Max.

Min.

Max.

1.78

0.25

0.51

0.25

10.16

4.06

1.40

6.22

0.89

Dimension

e

A

A1

B

0.060

0.004

0.013

0.007

0.385

0.150

0.045

0.225

0.015

0.070

0.010

0.020

0.010

0.400

0.160

0.055

0.245

0.035

1.52

0.10

0.33

0.18

9.78

3.81

1.14

5.72

0.38

E

C

H

D

E

A

e

C

A1

H

L

.004

L

Data Sheet Revision History

Change No. Page No.

Description

Nature of Change

1

4

Changed reset procedure

Was:

Is:

Reset by issuing command over serial port

Reset by removing V_CCand grounding RBI for

15 s.

1

2

11, 14

16

Deleted reset register

Changed values

V_EDVF

:

Min. was 1.45; Max. was 1.49

Min. now is 1.44; Max. now is 1.50

Min. was 1.50; Min. now is 1.49

V_EDV1

V_CC

:

2

17

Changed values

:

Min. was 2.5; Min. now is 3.0

4, 11, 13, 14 Reinserted reset register

Maximum offset

9

V_OS

:

Max. was 150

Max. now is 180

Notes:

Change 1 = June 1995 B changes from Dec. 1994.

Change 2 = Sept. 1996 C changes from June 1995 B.

19

bq2050

Ordering Information

bq2050

Temperature Range:

blank = Commercial (-20 to +70°C)

N = Industrial (-40 to +85°C)*

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2040 Gas Gauge IC With SMB Interface

* Contact factory for availability.

17919 Waterview Parkway

Dallas, Texas 75252

Fax: (972) 437-9198

Tel: (972) 437-9195

www.benchmarq.com or www.unitrode.com

form or means, without express permission from Unitrode. Unitrode reserves the right to make changes in its prod-

ucts without notice.

Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intel-

lectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied.

Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may

cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibili-

ties and indemnifies Unitrode from all liability or damages.

Benchmarq is a registered trademark of Unitrode Corporation.

Printed in U.S.A.

20

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	BQ2050SN-D119TR
厂家：	TEXAS INSTRUMENTS
描述：	具有单总线 (DQ) 接口和 5 个 LED 驱动器的锂离子电池电量监测计 \| D \| 16 \| 0 to 70 电池驱动光电二极管电源管理电路电源电路驱动器
文件：	总21页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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