BQ2058TSN [TI]
Lithium Ion Pack Supervisor For 2-Cell Packs; 锂离子电池组监督员为2节包
| 型号： | BQ2058TSN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Lithium Ion Pack Supervisor For 2-Cell Packs |
| 文件： | 总18页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2058T
Lithium Ion Pack Supervisor
For 2-Cell Packs
charge to the battery pack. This safety
Features
General Description
feature prevents overcharge of any cell
within the battery pack. After an over-
voltage condition occurs, each cell must
fall below VCE (charge enable voltage)
for the bq2058T to re-enable charging.
➤ Protects and individually moni-
tors two Li-Ion series cells for
overvoltage, undervoltage
The bq2058T Lithium Ion Pack Su-
pervisor is designed to control the
charge and discharge cell voltage lim-
its for two lithium-ion (Li-Ion) series
cells, accommodating battery packs
containing series/parallel configura-
tions. The low operating current does
not overdischarge the cells during pe-
riods of storage and does not signifi-
cantly increase the system discharge
load. The bq2058T can be part of a
low-cost Li-Ion charge control system
within the battery pack.
➤ Monitors pack for overcurrent
The bq2058T protects batteries from
overdischarge. If the voltage on any
cell falls below VUV (undervoltage
limit) for a user-configurable delay pe-
riod (tUVD), the DSG output is driven
low, shutting off the battery discharge.
This safety feature prevents overdis-
charge of any cell within the battery
pack.
➤ Designed for battery pack inte-
gration
➤ Minimal external components
➤ Drives external FET switches
➤ S elect a ble over volt a ge (VOV
)
thresholds
The bq2058T controls two external
FETs to limit the charge and discharge
potentials. The bq2058T allows charg-
ing when each individual cell voltage is
below VOV (overvoltage limit). If the
voltage on any cell exceeds VOV for a
user-configurable delay period (tOVD),
the open-drain CHG pin goes to the
high-impedance state, shutting off
The bq2058T also stops discharge on
detection of an overcurrent condition,
such as a short circuit. If an overcur-
r en t con dit ion occu r s for a u ser-
configurable delay period (tOCD), the
DSG output is driven low, disconnect-
ing the load from the pack. DSG re-
mains low until removal of the short
circuit or overcurrent condition.
- Mask programmable by
Benchmarq
- Standard version–4.25V
➤ Supply current: 12µA typical
➤ Sleep current: 0.7µA typical
➤ 16-pin 150-mil narrow SOIC
Pin Names
Pin Connections
DSG
UVD
OVD
OCD
VCC
Discharge control output
Undervoltage delay input
Overvoltage delay input
Overcurrent delay input
High potential input
CHG
CTL
VSS
Charge control output
Pack disable input
Low potential input
CHG
CTL
1
2
3
4
5
6
16
15
14
13
12
11
DSG
V
CC
V
SS
UVD
OVD
OCD
CSL
CSL
Overcurrent sense low-side
input
BAT
2N
BAT
2N
V
CC
BAT2N
BAT1N
Battery 2 negative input
Battery 1 negative input
CSH
Overcurrent sense high-side
input
BAT
BAT
7
8
10
9
CSH
2N
BAT
1P
1N
BAT1P
Battery 1 positive input
16-Pin Narrow SOIC
PN2058T1.eps
July 1997
1
bq2058T
UVD
OVD
OCD
Un der voltage delay in pu t
Pin Descriptions
This input uses an external capacitor to VCC
to set the undervoltage delay timing.
CHG
Ch ar ge con tr ol ou tpu t
This open-drain output controls the charge
path to the battery pack. Charging is allowed
when high.
Over voltage delay in pu t
This input uses an external capacitor to VCC
to set the overvoltage delay timing.
CTL
Pack disable in pu t
Over cu r r en t delay in pu t
When high, this input allows an external
source to disable the pack by making both
DSG and CHG inactive. For normal opera-
tion, the CTL pin is low.
This input uses an external capacitor to VCC
to set the overcurrent delay timing.
VCC
High poten tial in pu ts (2 pin s)
VSS
Low poten tial in pu t
CSH
Overcurrent sense high-side input
CSL
Over cu r r en t sen se low-side in pu t
T h is in p u t is con n e ct e d b e t w e e n t h e
high-side discharge FET (or sense resistor)
and BAT1P to enable overcurrent sense in
the battery pack’s positive supply path.
This input is connected between the low-side
discharge FET (or sense resistor) and BAT2N to
enable overcurrent sensing in the battery
pack’s ground path.
BAT1P
Batter y 1 positive in pu t
BAT2N
BAT1N
DSG
Batter y 2 n egative in pu ts (3 pin s)
This input is connected to the positive terminal
of the cell designated BAT1 in Figure 2.
These pins are connected to the negative termi-
nal of the cell designated BAT2 in Figure 2.
Batter y 1 n egative in pu t
This input is connected to the negative termi-
nal of the cell designated BAT1 in Figure 2.
Disch ar ge con tr ol ou tpu t
This push-pull output controls the discharge
path to the battery pack. Discharge is al-
lowed when high.
July 1997
2
bq2058T
Sel2
Sel1
Cell Inputs
Pin 9 B1P
Pin 8 B1N
+
-
B2N
Pin 7
Pin 3
V
OV
+
Over_charge
D
CK
D
Q
Pin 1
Chip Negative
Supply
CK
Any_Above_V
OV
Sel2
Sel1
QB
CHG
Edge
Out
QB
Reset
Non-Retrigger
Reset
D
Q
Charge Control
Output (open drain)
Oneshot
CK
QB
Capacitor
OVD
Pin 13
Discharge Off Delay Capacitor Input
All_Below_V
CE
Any_Below_V
UV
Sleep
D
Pin 16
DSG
+
CK
D
Q
QB
Edge
Out
CK
QB
Sel2
Sel1
V
Reset
CE
Non-Retrigger
Discharge Control
Output (totem pole)
Oneshot
Reset
D
Q
Capacitor
CK
UVD
Pin 14
QB
Charge Off Delay Capacitor Input
CSH
Pin 10
70mV
B1P
Pin 9
+
CSL
Pin 4
70mV
B2N
Pin 7
+
D
Q
Over_current
CK
QB
+
D
Q
Edge
Out
CK
QB
Reset
Sel2
Sel1
Non-Retrigger
Overcurrent Delay
Capacitor Input
V
Oneshot
Reset
UV
D
Q
Capacitor
Pin 12
OCD
CK
CSH
B1P
Pin 10
Pin 9
160mV
+
QB
CSL
B2N
Pin 4
Pin 7
160mV
+
CTL
External Output Control
Pin 2
BD2058T1.eps
Figure 1. Block Diagram
July 1997
3
bq2058T
The bq2058T samples a cell every 60ms (typical). Every
sample is a fully differential measurement of each cell.
During this sample period, the bq2058T compares the
measurements with these thresholds to determine if any
Functional Description
Figure 1 is a block diagram outlining the major compo-
nents of the bq2058T. Figure 2 shows a low-side control
connection diagram. The following sections detail the
various functional aspects of the bq2058T.
of the these conditions exist: VOV, VUV, and VCE
.
Overcurrent and charge detect are conditions that are
not sampled, but are continuously monitored.
Thresholds
Initialization
The bq2058T monitors the lithium ion pack for the con-
ditions listed below. Shown with these conditions are
the respective thresholds used to determine if that con-
dition exists:
On initial power-up, such as connecting the battery pack
for the first time to the bq2058T, the bq2058T enters the
low-power sleep mode, disabling the DSG output. It is
r ecom m en d ed th a t a top to bottom cell con n ection
be m a d e a t p a ck a ssem bly for p r op er in itia liza -
tion . A charging supply must be applied to the bq2058T
circuit to enable the pack. See Low-Power Sleep Mode
and Charge Detect sections.
■
■
■
■
■
Overvoltage (VOV
Undervoltage (VUV
Overcurrent (VOCH, VOCL
Charge Enable (VCE
)
)
)
)
Charge Detect (VCD
)
POS
CHG
CTL
DSG
V
CC
C
1
V
UVD
OVD
OCD
SS
C
2
CSL
BAT
BAT1
2N
C
3
C
4
BAT
BAT
BAT
V
CC
CSH
BAT
2N
2N
1N
R
2
1P
bq2058T
R
1
BAT2
C
5
C
7
Q
Q
2
1
C
6
NEG
FG2058T1.eps
Figure 2. 2-Cell Connection Diagram, Low-Side Control
July 1997
4
bq2058T
Table 1. Overvoltage Threshold Options
Low-Power Sleep Mode
The bq2058T enters the low-power sleep mode in two
different ways:
Part #
VOV Limit
4.25V
bq2058T
1. On initial power-up.
bq2058TR
4.35V
2. Aft er t h e det ect ion of a n u n der volt a ge con di-
tion–VUV
.
Th e over volta ge th r esh old lim its a r e p r ogr a m m ed
a t Ben ch m a r q. Th e bq2058T is th e sta n d a r d op -
tion th a t is m or e r ea d ily a va ila ble for sa m p lin g
a n d p r ototyp in g p u r p oses. P lea se con ta ct Ben ch -
m a r q for oth er volta ge th r esh old a n d toler a n ce
op tion s.
When the bq2058T enters the low-power sleep mode,
DSG is driven low and the device consumes 0.7µA (typi-
cal). The bq2058T only comes out of low-power sleep
mode when a valid charge detect condition exists.
Charge Detect
Charge Enable
The bq2058T continuously monitors for a charge detect
condition. A valid charge detect condition exists when ei-
ther of the conditions is true:
A valid charge enable indicates that an overvoltage
(overcharge) condition no longer exists and that the
pack is ready to accept further charge. Once overvoltage
protection is asserted, charging will not be enabled un-
til all cell voltages fall below VCE. The VCE threshold is
a function of VOV, and changes with different VOV lim-
its.
CSL < BAT2N - 70mV (VCD
)
CSH > BAT1P + 70mV (VCD
)
A valid charge detect enables the DSG output, allowing
charging of the lithium ion cells. This is accomplished
by applying the charging supply to the pack.
VCE = VOV - 150mV
Overcurrent
Undervoltage
The bq2058T detects an overcurrent (or short circuit)
condition only in the discharge direction. Overcurrent
protection is asserted when either of the conditions oc-
Undervoltage (or overdischarge) protection is asserted
when any cell voltage drops below the VUV threshold
a n d r em a in s below t h e VU V t h r esh old for a t im e
exceeding a user-configurable delay (tUVD). The DSG
output is driven low, disabling the discharge of the pack.
The bq2058T then enters the low-power sleep mode.
VUV is defined as follows:
cu r s a n d r e m a in for
configurable delay (tOCD):
a t im e e xce e d in g a u s e r -
CSL > BAT2N + VOCL
CSH < BAT1P - VOCH
VUV = 2.25V
where:
Overvoltage
VOCL = 160mV (low-side detect)
VOCH = 160mV (high-side detect)
Overvoltage (or overcharge) protection is asserted when
any cell voltage exceeds the VOV threshold and remains
above the VOV threshold for a time exceeding a user-
configurable delay (tOVD). The CHG pin goes to the
high impedance state, disabling charge into the battery
pack. Since the charge control output is an open drain
output, a pull-down resistor is needed from the CHG pin
to the negative side of the pack. This pulls the gate of
the charge FET low when the CHG pin goes to high im-
pedance. Charging is disabled until a valid charge en-
able exists. See Charge Enable section.
When either of these conditions occurs, DSG is driven
low, disconnecting the load from the pack. DSG remains
low until both of the voltage conditions are false, indi-
cating removal of the short-circuit condition. The user
can facilitate clearing these conditions by inserting the
battery pack into a charger.
The high-side overcurrent sense can be disabled by con-
necting CSH to BAT1P. This ensures that CSH is never
Im p or ta n t n ote: If a n y ba tter y p in floa ts (BAT1P
,
BAT1N, BAT2N), th e bq2058T a ssu m es a n over volt-
a ge h a s occu r r ed .
greater than BAT1P
low-side detection must be used with CSL.
. If high-side detection is disabled,
Because of different manufacturers’ specifications for
overvoltage thresholds, the bq2058T can be available
with different VOV options. Table 1 summarizes these
different voltage thresholds.
July 1997
The FETs in the charge/discharge path controlled by the
CHG and DSG pins affect the overcurrent level. The
on-resistance of these FETs need to be taken into ac-
count when determining overcurrent levels.
5
bq2058T
I m p o r t a n t n o t e : I f C T L flo a t s , it is in t e r n a lly
p u lled h igh m a k in g both DSG a n d CHG in a ctive,
th u s d isa blin g th e p a ck . If CTL is n ot u sed , it
CHG and DSG States
The CHG and DSG output truth table is shown below:
sh ou ld be tied to VSS
.
Condition
Normal operation
Overvoltage
CHG pin
DSG pin
High
The polarity of CTL is mask-programmable at Bench-
marq. Please contact Benchmarq for other polarity op-
tions.
High
Z
High
Undervoltage
High
High
Z
Low
Protection Delay Timers
Overcurrent
Low
Floating battery input
CTL = high
Indeterminate
Low
The delay time between the detection of an overcurrent,
overvoltage, or undervoltage condition and the deactiva-
tion of the CHG and/or DSG outputs is user-configurable
by the selection of capacitor values between VCC and OCD,
OVD, and UVD pins (respectively. See Table 2 below.
Z
The polarities of CHG and DSG are mask programmable
at Benchmarq. Push-pull vs. open-drain configuration is
also mask-configurable at Benchmarq. Please contact
Benchmarq for availability of these variations.
The fault condition must persist through the entire de-
lay period, or the bq2058T may not deactivate either
FET control output.
Pack Disable Input–CTL
F igu r e 3 sh ows a st ep-by-st ep even t cycle for t h e
bq2058T.
The CTL pin is used to electrically disconnect the bat-
tery from the pack terminals through an externally sup-
plied signal. When CTL is taken high, CHG goes to the
high impedance state and DSG is driven low. Any load
on the pack terminals will be interpreted as an overcur-
rent condition by the bq2058T with the overcurrent de-
lay timer held in reset. When the CTL pin is driven low,
the overcurrent delay timer is allowed to start. If the
programmed delay (tOCD) is too short, the overcurrent
recovery circuit, if implemented, will be unable to cor-
rect the overcurrent situation prior to the delay time-
out. It is recommended that a delay time of greater than
10ms (COCD ≥ 0.01µF) be used if the CTL pin function
is to be utilized.
Table 2. Protection Delay Timers
Typical
Protection
Feature
Delay
Period
Capacitor from
VCC to:
Tolerance
Capacitor
0.010µF
0.100µF
0.100µF
Time
12ms
Overcurrent
Overvoltage
Undervoltage
tOCD
tOVD
tUVD
OCD
OVD
UVD
±40%
±40%
±40%
950ms
950ms
Notes:
1. The delay time versus capacitance can be approximated by the following equations:.
For tOCD
For tOVD, tUVD
:
t(s) ≈ 1.2 C(µf)
t(s) ≈ 9.5 C(µf)
,
,
where 0.001µF ≤ C ≤ 0.1µF
where 0.01µF ≤ C ≤ 1µF
:
2. Overvoltage and undervoltage conditions are sampled by the bq2058T. The delay in Table 2 is in
addition to the time required for the bq2058T to detect the violation, which may vary from 0 to
120 ms depending on where in the sampling period the violation occurs. Overcurrent is continuously
monitored and is subject to a delay of approximately 1.5ms.
July 1997
6
bq2058T
0
1
2
3
4
5
6
7
8
9
10
11 12
V
OV
V
CE
V
UV
Cell Voltage
CSL
BAT
BAT
+ 160mV (V
- 70mV (V
)
2N
OCL
)
2N
CD
DSG
CHG
t
t
UVD
OCD
t
OVD
CTL
TD2058T1.eps
Figure 3. Protector Event Diagram
Even t Defin ition :
0:
1:
The bq2058T is in the low-power sleep mode because one or more of the cell voltages are below VUV.
A charger is applied to the pack, causing the difference between CSL and BAT2N to become greater
than 70mV. This awakens the bq2058T, and the discharge pin DSG goes high.
2:
One or more cells charge to a voltage equal to VOV, initiating the overvoltage delay timer.
The overvoltage delay time expires, causing CHG to go to high impedance (pulled low externally).
All cell voltages fall below VCE, causing CHG to go high.
3:
4:
5:
Stop charging, apply a load.
6:
An overcurrent condition is detected, initiating the overcurrent delay timer.
The overcurrent delay time expires, causing DSG to go low.
7:
8:
The overcurrent condition is no longer present. DSG is driven high.
Pin CTL is driven high; both DSG and CHG go inactive.
9:
10:
11:
12:
Pin CTL is driven low; both DSG and CHG go active resuming their normal function.
One or more cells fall below VUV, initiating the overdischarge delay timer.
Once the overdischarge delay timer expires, if any of the cells is below VUV, the bq2058T drives
DSG low and enters the low-power sleep mode.
July 15, 1997
7
bq2058T
Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
18
Unit
V
Conditions
Relative to VSS
Supply voltage
TOPR
TSTG
TSOLDER
IIN
Operating temperature
Storage temperature
Soldering temperature
Maximum input current
-30 to +70
-55 to +125
260
°C
°C
°C
For 10 seconds
All pins except VCC, VSS
±100
µA
Notes:
1
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional
operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to conditions beyond the operational limits for extended periods of time may affect device
reliability.
2. Internal protection diodes are in place on every pin relative to VCC and VSS. See picture below.
V
V
CC
CC
Any pin
(except CHG)
CHG pin
V
SS
FG2058tx .eps
July 1997
8
bq2058T
DC Electrical Characteristics (T = T
A
OPR)
Symbol
VOH
Parameter
Output high voltage
Output low voltage
Operating voltage
Input low voltage
Input high voltage
Active current
Minimum
Typical
Maximum
Unit
V
Conditions/Notes
VCC - 0.5
-
-
-
IOH = 10µA, CHG, DSG
IOL = 10µA, CHG, DSG
VCC relative to VSS
Pin CTL
VOL
VOP
VIL
-
VSS + 0.5
V
0
-
9.0
V
-
-
VSS + 0.5
V
VIH
VSS + 2.0
-
-
25
1.5
-
V
Pin CTL
ICCA
ICCS
RCELL
-
-
-
12
0.7
10
µA
µA
MΩ
Sleep current
Input impedance
Pins BAT2N, BAT1N, and BAT1P
DC Thresholds (T = T
A
OPR)
Symbol
Parameter
Value
Unit
Tolerance
Conditons
4.25
V
See note 1
±55mV
V
Overvoltage threshold
OV
Table 1
Customer option
VCE
VUV
Charge enable threshold VOV - 150mV
V
V
±55mV
Undervoltage threshold
2.25
160
±100mV
Overcurrent detect
high-side
V
OCH
mV
±35mV
Overcurrent detect
low-side
V
160
70
mV
mV
±35mV
OCL
VCD
Charge detect threshold
-60mV, +80mV
COVD = 0.100µF
TA = 30°C
See note 2
Overvoltage delay
threshold
tOVD
950
ms
±40%
CUVD = 0.100µF
TA = 30°C
See note 2
Undervoltage delay
threshold
tUVD
950
12
ms
ms
±40%
±40%
Overcurrent delay thresh-
old
C
T
OCD = 0.01µF
A = 30°C
t
OCD
Notes:
1. Standard device. Contact Benchmarq for different thresholds and tolerance options
2. Does not include cell sampling delay, which may add up to 120ms of additional delay until the
condition is detected.
July 1997
9
bq2058T
Typical Characteristics
bq2058T 4.25V OVERVOLTAGE THRESHOLD
VS
FREE-AIR TEMPERATURE
4.280
4.270
4.260
4.250
4.240
4.230
4.220
4.210
Measurement accuracy ± 2mV
-30 -20 -10
0
10 20 30 40 50 60 70
T
– Free-Air Temperature – ˚C
A
Figure 4
July 1997
10
bq2058T
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
1
5
CHG pin output state
CHG pin state at overvoltage and floating battery
input was low, is now Z
1
1
9
9
Overcurrent limits
Was: VOCL = 100mV ±25mV
Is: VOCL = 150mV ±25mV
Charge detect threshold
Was: 70mV +10mV, +80mV
Is: 70mV -60mV, +80mV
2
2
4
4
Overvoltage options, Table 1
Figure 2
Added bq2058TR
Corrected schematic
Was: tOCD = 10ms ±30%
tOVD = 800ms ±30%
tUVD = 800ms ±30%
Is: tOCD = 12ms ±40%
tOVD = 950ms ±40%
2
2
6, 9
7
Delay thresholds
t
UVD = 950ms ±40%
DSG and CHG timing diagram
Inverted lines for proper logic levels
Was: CSH timing
Is: CSL timing
2
2
7
8
Timing Diagram
Maximum input current
Added IIN
Was: ±50mV
Is: ±55mV
2
2
9
9
V
tolerance
OV
Was: VOCH = 160mV +25mV
VOCL = 150mV +25mV
Overcurrent limits
Is: VOCH = 160mV +35mV
VOCL = 160mV +35mV
Was: 0V min, 18V max
Is: 4V min, 9V max
2
9
V
OP
Note:
Change 1 = June 19, 1997 changes from April 22, 1997.
Change 2 = July 1997 changes from June 19, 1997
July 1997
11
bq2058T
(
)
SN: 16-Pin SN 0.150" SOIC
(
)
16-Pin SN 0.150" SOIC
Inches
Millimeters
Min.
Max.
Min.
Max.
Dimension
D
B
e
A
A1
B
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
1.52
0.10
0.33
0.18
9.78
3.81
1.14
5.72
0.38
1.78
0.25
0.51
0.25
10.16
4.06
1.40
6.22
0.89
E
C
H
D
E
A
C
e
A1
H
L
.004
L
July 1997
12
bq2058T
Ordering Information
bq2058T
XXXX
Sta n d a r d Device:
Blank = Standard device
XXXX = Customer code assigned by Benchmarq
Pa ck a ge Op tion :
SN = 16-pin narrow SOIC
Over volta ge Th r esh old
Blank = 4.25V (Standard device)
Contact factory for availability of other thresholds
Device:
bq2058T Lithium Ion Pack Supervisor
Package Devices
T
V
Threshold
4.25V
16-pin Narrow SOIC (SN)
bq2058TSN
A
OV
-30°C to
+70°C
4.35V
bq2058TRSN
Note: bq2058TSN is Standard Device
Contact factory for availability of other thresholds and tolerances.
July 1997
13
Notes
July 1997
14
Notes
July 1997
15
bq2058T
BENCHMARQ Microelectronics, Inc.
17919 Waterview Parkway
Dallas, Texas 75252
Fax: (972) 437-9198
Tel: (972) 437-9195
E-mail: benchmarq @ benchmarq.com
World Wide Web: http://www.benchmarq.com
Copyright © 1997, BENCHMARQ Microelectronics, Inc. All rights reserved.
No part of this data sheet may be reproduced in any form or means, without express permission from Benchmarq.
Benchmarq reserves the right to make changes in its products without notice.
Benchmarq assumes no responsibility for use of any products or circuitry described within. No license for use of in-
tellectual property (patents, copyrights, or other rights) owned by Benchmarq or other parties is granted or implied.
Benchmarq does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Benchmarq components are used in life-support systems, the user assumes all responsi-
bilities and indemnifies Benchmarq from all liability or damages.
Benchmarq is a registered trademark of BENCHMARQ Microelectronics, Inc.
Printed in U.S.A.
July 1997
16
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
Drawing
BQ2058TRSN-C2
BQ2058TSN-C2
OBSOLETE
OBSOLETE
D
D
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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