BQ20Z655DBTR-R1 [TI]
SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION; SBS 1.1标准的电量监测计和保护
| 型号： | BQ20Z655DBTR-R1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION |
| 文件： | 总25页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq20z655-R1
www.ti.com
SLUSAN9 –AUGUST 2011
SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION
ENABLED WITH IMPEDANCE TRACK™
Check for Samples: bq20z655-R1
1
FEATURES
APPLICATIONS
2
•
Next Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
•
•
•
•
Medical and Test Equipment
Portable Instrumentation
Rechargeable Battery Packs
Industrial Equipment
–
Better Than 1% Error Over the Lifetime of
the Battery
•
•
•
•
Supports the Smart Battery Specification
SBS V1.1
DESCRIPTION
The bq20z655-R1 SBS-compliant gas gauge and
protection IC, incorporating patented Impedance
Track™ technology, is a single IC solution designed
for battery-pack or in-system installation. The
bq20z655-R1 measures and maintains an accurate
record of available charge in Li-ion or Li-polymer
batteries using its integrated high-performance
analog peripherals. The bq20z655-R1 monitors
capacity change, battery impedance, open-circuit
voltage, and other critical parameters of the battery
pack which reports the information to the system host
controller over a serial-communication bus. Together
with the integrated analog front-end (AFE)
Flexible Configuration for 2-Series to 4-Series
Li-Ion and Li-Polymer Cells
Powerful 8-Bit RISC CPU with Ultralow Power
Modes
Charge Enable (CE) Affects the Normal
Operation on the Charge FET when the Battery
Is in Charge/Relax Mode
•
Full Array of Programmable Protection
Features
–
Voltage, Current, and Temperature
•
•
Satisfies JEITA Guidelines
short-circuit
and
overload
protection,
the
bq20z655-R1 maximizes functionality and safety
while minimizing external component count, cost, and
size in smart battery circuits.
Added Flexibility to Handle More Complex
Charging Profiles
•
•
Lifetime Data Logging
The implemented Impedance Track™ gas gauging
technology continuously analyzes the battery
impedance, resulting in superior gas-gauging
accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
aging all accounted for during each stage of every
cycle with high accuracy.
Drives 3, 4, or 5 Segment Liquid Crystal
Display and LED for Battery-Pack Conditions
•
•
Supports SHA-1 Authentication
Complete Battery Protection and Gas Gauge
Solution in One Package
•
Available in a 44-Pin TSSOP (DBT) Package
Table 1. AVAILABLE OPTIONS
PACKAGE(1)
TA
44-PIN TSSOP (DBT) Tube
44-PIN TSSOP (DBT) Tape and Reel
–40°C to 85°C
bq20z655-R1DBT(2)
bq20z655-R1DBTR(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 40 units.
(3) A single reel quantity is 2000 units.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
bq20z655-R1
SLUSAN9 –AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
THERMAL INFORMATION
bq20z655-R1
THERMAL METRIC(1)
TSSOP
44 PINS
60.9
UNITS
θJA, High K
θJC(top)
θJB
Junction-to-ambient thermal resistance(2)
Junction-to-case(top) thermal resistance
(3)
15.3
(4)
Junction-to-board thermal resistance
30.2
°C/W
(5)
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.3
(6)
(7)
ψJB
27.2
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
SYSTEM PARTITIONING DIAGRAM
PACK+
RBI
DISP
PreCharge FET
& GPOD Drive
N Channel FET
Drive
Power Mode
Control
Fuse Blow
Detection & Logic
LED Display
Oscillator
MSRT
RESET
SMBD
SMBC
SMB 1.1
System Control
AFE HW Control
Watchdog
ALERT
VCELL+
Voltage
Measurement
Cell Voltage
Multiplexer
+
Data Flash
Memory
VDD
OUT
CD
VC1
VC2
VC3
VC4
VC1
VC2
VC3
VC4
+
+
GND
Over
Temperature
Protection
Over & Under
Voltage
Protection
Impedance
Track™ Gas
Gauging
JEITA and
Enhanced
Charging
Algorithm
Cell Balancing
+
bq294xx
VC5
REG33
REG25
HW Over
Current & Short
Circuit Protection
SHA-1
Authentication
Temperature
Measurement
Over Current
Protection
Coulomb
Counter
Regulators
RSNS
PACK–
5 mΩ – 20 mΩ typ
2
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SLUSAN9 –AUGUST 2011
PACKAGE PINOUT DIAGRAM
bq20z655-R1
DBT PACKAGE
(TOP VIEW)
DSG
PACK
1
2
3
4
5
6
7
8
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CHG
BAT
VC1
VC2
VC3
VCC
ZVCHG
GPOD/ALARM
PMS
VC4
VSS
VC5
REG33
TOUT
ASRP
ASRN
VCELL+
¯A¯L¯E¯R¯T¯
COM
10
11
12
13
14
15
16
17
18
19
20
21
22
R¯¯E¯S¯E¯T¯
VSS
RBI
TS1
REG25
VSS
TS2
P¯¯R¯E¯S¯
P¯F¯¯IN¯
M¯¯R¯S¯¯T
GSRN
SAFE
GSRP
SMBD
CE
LED5/SEG5
LED4/SEG4
LED3/SEG3
LED2/SEG2
SMBC
¯¯¯¯
DISP
VSS
LED1/SEG1
Figure 1. Package Pinout
Copyright © 2011, Texas Instruments Incorporated
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TYPICAL LCD IMPLEMENTATION
Figure 2 shows a typical LCD implementation.
bq20z655-R1
SEG5
27
S5
S4
S3
S2
S1
SEG4
26
SEG3
25
SEG2
24
SEG1
23
BP
COM
12
KΩ
330
(x6)
8
REG33
DSPL
220 KΩ
21
0.1
µF
Figure 2. Typical LCD Implementation
4
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SLUSAN9 –AUGUST 2011
TERMINAL FUNCTIONS
TERMINAL
I/O(1)
DESCRIPTION
NO.
NAME
1
DSG
O
High side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
mode.
2
PACK
IA, P
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input
3
4
5
VCC
P
O
ZVCHG
GPOD
P-chan pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition
OD
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
6
PMS
I
7
8
9
VSS
REG33
TOUT
P
P
P
Negative supply voltage input. Connect all VSS pins together for operation of device
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS
Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
VSS
10
11
VCELL+
ALERT
—
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
OD
12
13
14
15
COM/TP
TS1
—
IA
IA
I
Output / open drain: LCD common connection
1st Thermistor voltage input connection to monitor temperature
2nd Thermistor voltage input connection to monitor temperature
Active low input to sense system insertion. Typically requires additional ESD protection.
TS2
PRES
Active low input to detect secondary protector status, and to allow the bq20z655-R1 to report the
status of the 2nd level protection input.
16
17
18
PFIN
SAFE
SMBD
I
OD
I/OD
Active high output to enforce additional level of safety protection; e.g., fuse blow.
SMBus data open-drain bidirectional pin used to transfer address and data to and from the
bq20z655-R1
A logical high on this pin only affects the normal operation on the charge FET when the battery is in
charge/relax mode. For a logic low, the normal bq20z655-R1 firmware controls the charge FET.
19
20
CE
—
SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the
bq20z655-R1
SMBC
I/OD
21
22
23
24
25
26
27
28
29
DISP
I
P
I
Input: In LED mode, this is the display enable input.
VSS
Negative supply voltage input. Connect all VSS pins together for operation of device
Output / open drain: LED 1 current sink. LCD segment 1
LED1/SEG1
LED2/SEG2
LED3/SEG3
LED4/SEG4
LED5/SEG5
GSRP
I
Output / open drain: LED 2 current sink. LCD segment 2
I
Output / open drain: LED 3 current sink. LCD segment 3
I
Output / open drain: LED 4 current sink. LCD segment 4
I
Output / open drain: LED 5 current sink. LCD segment 5
IA
IA
Coulomb counter differential input. Connect to one side of the sense resistor
Coulomb counter differential input. Connect to one side of the sense resistor
GSRN
Master reset input that forces the device into reset when held low. Must be held high for normal
operation. Connect to RESET for correct operation of device
30
MRST
I
31
32
VSS
P
P
Negative supply voltage input. Connect all VSS pins together for operation of device
2.5V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS
REG25
RAM / Register backup input. Connect a capacitor to this pin and VSS to protect loss of
RAM/Register data in case of short circuit condition.
33
RBI
P
34
35
36
37
VSS
RESET
ASRN
ASRP
P
O
Negative supply voltage input. Connect all VSS pins together for operation of device
Reset output. Connect to MSRT.
IA
IA
Short circuit and overload detection differential input. Connect to sense resistor
Short circuit and overload detection differential input. Connect to sense resistor
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O(1)
DESCRIPTION
NO.
NAME
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
stack.
38
VC5
IA, P
IA, P
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in cell stack.
39
40
VC4
VC3
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
cell stack and the negative voltage of the second highest cell in 4 cell applications.
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
41
VC2
IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack
applications.
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4 cell applications. Connect to VC2 in 2- or 3-stack applications.
42
VC1
IA, P
43
44
BAT
I, P
O
Battery stack voltage sense input.
CHG
High side N-channel charge FET gate drive
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature (unless otherwise noted)
(1)
PIN
UNIT
BAT, VCC
–0.3 V to 34 V
–0.3 V to 34 V
–0.3 V to 8.5 V
–0.3 V to 34 V
–0.3 V to 1 V
PACK, PMS
VSS
Supply voltage range
Input voltage range
VC(n)–VC(n+1); n = 1, 2, 3, 4
VC1, VC2, VC3, VC4
VC5
PFIN, SMBD, SMBC. LED1, LED2, LED3,
LED4, LED5, DISP
–0.3 V to 6 V
TS1, TS2, SAFE, VCELL+, PRES, ALERT
MRST, GSRN, GSRP, RBI
ASRN, ASRP
–0.3 V to V(REG25) + 0.3 V
–0.3 V to V(REG25) + 0.3 V
–1 V to 1 V
VIN
DSG, CHG, GPOD
ZVCHG
–0.3 V to 34 V
–0.3 V to V (BAT)
–0.3 V to 6 V
VOUT Output voltage range
TOUT, ALERT, REG33
RESET
–0.3 V to 7 V
REG25
–0.3 V to 2.75 V
PRES, PFIN, SMBD, SMBC, LED1, LED2,
LED3, LED4, LED5
ISS
Maximum combined sink current for input pins
50 mA
TA
Operating free-air temperature range
Functional temperature
–40°C to 85°C
–40°C to 100°C
–65°C to 150°C
TF
Tstg
Storage temperature range
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
PIN
MIN NOM
MAX UNIT
VSS
Supply voltage
VCC, BAT
VCC, BAT, PACK
4.5
5.5
25
V
V
V(STARTUP)
Minimum startup voltage
6
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RECOMMENDED OPERATING CONDITIONS (continued)
Over operating free-air temperature range (unless otherwise noted)
PIN
MIN NOM
MAX UNIT
VC(n)-VC(n+1); n = 1,2,3,4
VC1, VC2, VC3, VC4
0
0
5
VSS
0.5
0.5
25
25
1
V
V
VIN
Input voltage range
VC5
0
V
ASRN, ASRP
PACK, PMS
GPOD
–0.5
0
V
V
V(GPOD)
I(GPOD)
Output voltage range
Drain current(1)
0
V
GPOD
mA
µF
µF
µF
kΩ
C(REG25)
C(REG33)
C(VCELL+)
R(PACK)
2.5V LDO capacitor
REG25
REG33
VCELL+
PACK
1
3.3V LDO capacitor
2.2
0.1
1
Cell voltage output capacitor
PACK input block resistor(2)
(1) Use an external resistor to limit the current to GPOD to 1 mA in high voltage application.
(2) Use an external resistor to limit the inrush current PACK pin required.
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(NORMAL)
I(SLEEP)
Firmware running
Sleep mode
550
µA
µA
µA
µA
µA
CHG FET on; DSG FET on
124
90
CHG FET off; DSG FET on
CHG FET off; DSG FET off
52
I(SHUTDOWN)
Shutdown mode
0.1
1
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
Shutdown exit at VSTARTUP
threshold
I(PACK)
1
µA
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
Positive or negative wake
threshold with 1.00 mV, 2.25
mV, 4.5 mV and 9 mV
V(WAKE)
1.25
10
mV
programmable options
V (WAKE) = 1 mV;
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1;
-0.7
-0.8
0.7
0.8
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
V(WAKE_ACR)
Accuracy of V(WAKE)
mV
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
-1.0
-1.4
1.0
1.4
V(WAKE) = 9 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
Temperature drift of V(WAKE)
accuracy
V(WAKE_TCO)
0.5
1
%/°C
Time from application of
current and wake of
bq20z655-R1
t(WAKE)
10
ms
WATCHDOG TIMER
tWDTINT Watchdog start up detect time
tWDWT Watchdog detect time
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
250
50
500
100
1000
150
ms
µs
V(REG25)
Regulator output voltage
I(REG25OUT) ≤ 16 mA;
TA = –40°C to 100°C
2.41
2.5
2.59
V
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ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Regulator output change with I(REG25OUT) = 2 mA;
ΔV(REG25TEMP)
ΔV(REG25LINE)
±0.2
%
temperature
TA = –40°C to 100°C
5.4 < VCC or BAT < 25 V;
I(REG25OUT) = 2 mA
Line regulation
3
10
mV
mV
mA
0.2 mA ≤ I(REG25OUT) ≤ 2 mA
0.2 mA ≤ I(REG25OUT) ≤ 16 mA
7
25
50
ΔV(REG25LOAD)
Load regulation
Current limit
25
drawing current until
REG25 = 2 V to 0 V
I(REG25MAX)
5
3
40
75
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V(REG33)
Regulator output voltage
I(REG33OUT) ≤ 25 mA;
3.3
3.6
V
TA = –40°C to 100°C
Regulator output change with I(REG33OUT) = 2 mA;
ΔV(REG33TEMP)
ΔV(REG33LINE)
±0.2
%
temperature
TA = –40°C to 100°C
5.4 < VCC or BAT < 25 V;
I(REG33OUT) = 2 mA
Line regulation
3
10
mV
0.2 mA ≤ I(REG33OUT) ≤ 2 mA
7
17
100
145
65
ΔV(REG33LOAD)
Load regulation
Current limit
mV
mA
0.2 mA ≤ I(REG33OUT) ≤ 25 mA
drawing current until REG33 = 3 V
short REG33 to VSS, REG33 = 0 V
40
25
12
100
I(REG33MAX)
THERMISTOR DRIVE
V(TOUT) Output voltage
I(TOUT) = 0 mA; TA = 25°C
V(REG25)
50
V
TOUT pass element
resistance
I(TOUT) = 1 mA; RDS(on) = (V(REG25) - V(TOUT) )/ 1 mA; TA
= –40°C to 100°C
RDS(on)
100
0.4
Ω
LED OUTPUTS
VOL
Output low voltage
LED1, LED2, LED3, LED4, LED5
V
VCELL+ HIGH VOLTAGE TRANSLATION
VC(n) - VC(n+1) = 0 V;
TA = –40°C to 100°C
0.950
0.275
0.965
0.975
0.3
1
V(VCELL+OUT)
VC(n) - VC(n+1) = 4.5 V;
TA = –40°C to 100°C
0.375
0.985
internal AFE reference voltage ;
TA = –40°C to 100°C
V(VCELL+REF)
V(VCELL+PACK)
Translation output
0.975
V
Voltage at PACK pin;
TA = –40°C to 100°C
0.98 ×
V(PACK)/18
1.02 ×
V(PACK)/18
V(PACK)/18
V(BAT)/18
Voltage at BAT pin;
TA = –40°C to 100°C
0.98 ×
V(BAT)/18
1.02 ×
V(BAT)/18
V(VCELL+BAT)
CMMR
Common mode rejection ratio VCELL+
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) - VCELL+
40
dB
0.147
0.150
0.150
18
0.153
0.153
output (VC5=0 V; VC4=0 V)}/4.5
K
Cell scale factor
K= {VCELL+ output (VC2=13.5 V; VC1=18 V) - VCELL+
output
(VC5=13.5 V; VC1=13.5 V)}/4.5
0.147
12
Drive Current to VCELL+
capacitor
VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;
TA = –40°C to 100°C
I(VCELL+OUT)
μA
CELL output (VC2 = VC1 = 18 V) - CELL output (VC2 =
VC1 = 0 V)
V(VCELL+O)
IVCnL
CELL offset error
-18
-1
-1
18
1
mV
VC(n) pin leakage current
VC1, VC2, VC3, VC4, VC5 = 3 V
0.01
μA
CELL BALANCING
internal cell balancing FET
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
RBAL
200
400
600
Ω
resistance
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
VOL = 25 mV (min)
15
90
25
35
OL detection threshold
voltage accuracy
V(OL)
VOL = 100 mV; RSNS = 0, 1
VOL = 205 mV (max)
100
205
110
225
mV
185
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ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(SCC) = 50 mV (min)
30
50
70
SCC detection threshold
voltage accuracy
V(SCC)
V(SCC) = 200 mV; RSNS = 0, 1
V(SCC) = 475 mV (max)
180
428
200
475
220
523
mV
V(SCD) = –50 mV (min)
–30
–50
–70
SCD detection threshold
voltage accuracy
V(SCD)
V(SCD) = –200 mV; RSNS = 0, 1
V(SCD) = –475 mV (max)
–180
–428
–200
–475
±15.25
–220
–523
mV
tda
tpd
Delay time accuracy
μs
μs
Protection circuit propagation
delay
50
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON) = V(DSG) - V(PACK)
;
V(DSGON)
DSG pin output on voltage
CHG pin output on voltage
V(GS) connected to 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8
8
12
12
16
16
V
V
V(CHGON) = V(CHG) - V(BAT)
;
V(CHGON)
V(GS) = 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
V(DSGOFF)
V(CHGOFF)
DSG pin output off voltage
CHG pin output off voltage
V(DSGOFF) = V(DSG) - V(PACK)
V(CHGOFF) = V(CHG) - V(BAT)
0.2
0.2
V
V
V(CHG): V(PACK) ≥ V(PACK) + 4V
400
400
1000
1000
tr
Rise time
CL= 4700 pF
μs
V(DSG): V(BAT) ≥V(BAT) + 4V
V(CHG): V(PACK) + V(CHGON) ≥ V(PACK)
1V
+
40
200
tf
Fall time
CL= 4700 pF
BAT = 4.5 V
μs
V(DSG): VC1 + V(DSGON) ≥ VC1 + 1 V
40
200
3.7
V(ZVCHG)
ZVCHG clamp voltage
3.3
3.5
V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
ALERT
60
1
100
3
200
6
R(PULLUP)
Internal pullup resistance
kΩ
RESET
ALERT
0.2
0.4
0.6
VOL
Logic low output voltage level RESET; V(BAT) = 7 V; V(REG25) = 1.5 V; I (RESET) = 200 μA
GPOD; I(GPOD) = 50 μA
V
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT, DISP
VIH
VIL
High-level input voltage
Low-level input voltage
2.0
V
V
0.8
0.4
V
REG25–0.
5
VOH
Output voltage high(1)
IL = –0.5 mA
V
VOL
Low-level output voltage
Input capacitance
PRES, PFIN, ALERT, DISP; IL = 7 mA;
V
CI
5
pF
mA
µA
µA
I(SAFE)
Ilkg(SAFE)
Ilkg
SAFE source currents
SAFE leakage current
Input leakage current
SAFE active, SAFE = V(REG25) –0.6 V
–3
SAFE inactive
–0.2
0.2
1
ADC(2)
Input voltage range
Conversion time
TS1, TS2, using Internal Vref
–0.2
1
V
31.5
15
ms
Resolution (no missing
codes)
16
14
bits
Effective resolution
Integral nonlinearity
Offset error(4)
bits
%FSR(3)
µV
±0.03
250
18
140
2.5
Offset error drift(4)
TA = 25°C to 85°C
μV/°C
(1) RC[0:7] bus
(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes.
(3) Full-scale reference
(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference.
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ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full-scale error(5)
±0.1%
±0.7%
Full-scale error drift
Effective input resistance(6)
50
PPM/°C
MΩ
8
COULOMB COUNTER
Input voltage range
Conversion time
–0.20
0.20
±0.034
0.7
V
Single conversion
Single conversion
–0.1 V to 0.20 V
–0.20 V to –0.1 V
TA = 25°C to 85°C
250
ms
bits
Effective resolution
15
±0.007
±0.007
10
Integral nonlinearity
%FSR
(7)
Offset error
µV
Offset error drift
0.4
µV/°C
(9)
Full-scale error(8)
±0.35%
150
Full-scale error drift
Effective input resistance(10)
PPM/°C
MΩ
TA = 25°C to 85°C
2.5
INTERNAL TEMPERATURE SENSOR
Temperature sensor
V(TEMP)
–2.0
mV/°C
voltage(11)
VOLTAGE REFERENCE
Output voltage
1.215
1.225
65
1.230
V
Output voltage drift
PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency
4.194
0.25%
0.25%
2.5
MHz
–3%
–2%
3%
2%
5
(12) (13)
f(EIO)
Frequency error
Start-up time(14)
TA = 20°C to 70°C
t(SXO)
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
f(LEIO)
t(LSXO)
Operating frequency
32.768
0.25%
0.25%
kHz
–2.5%
–1.5%
2.5%
1.5%
500
Frequency error(13)
Start-up time(14)
(15)
TA = 20°C to 70°C
µs
(5) Uncalibrated performance. This gain error can be eliminated with external calibration.
(6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(7) Post-calibration performance
(8) Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
(9) Uncalibrated performance. This gain error can be eliminated with external calibration.
(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(11) –53.7 LSB/°C
(12) The frequency error is measured from 4.194 MHz.
(13) The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5 V, TA = 25°C.
(14) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
(15) The frequency error is measured from 32.768 kHz.
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POWER-ON RESET
Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.7
5
TYP
1.8
MAX
1.9
UNIT
V
VIT-
Negative-going voltage input
Power-on reset hysteresis
VHYS
125
200
mV
Active low time after power up or watchdog
reset
tRST
RESET active low time
100
250
560
µs
POWER ON RESET BEHAVIOR
VS
FREE-AIR TEMPERATURE
1.81
1.8
1.79
1.78
1.77
1.76
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - °C
DATA FLASH CHARACTERISTICS OVER RECOMMENDED OPERATING TEMPERATURE AND
SUPPLY VOLTAGE
Typical values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
Data retention
Flash programming write-cycles
t(ROWPROG) Row programming time
TEST CONDITIONS
MIN TYP MAX
UNIT
Years
Cycles
ms
10
20k
2
(1)
See
t(MASSERASE) Mass-erase time
t(PAGEERASE) Page-erase time
200
20
ms
ms
I(DDPROG)
I(DDERASE)
RAM/REGISTER BACKUP
Flash-write supply current
5
5
10
10
mA
Flash-erase supply current
mA
V
(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 85°C
(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 25°C
1000 2500
I(RB)
RB data-retention input current
RB data-retention input voltage(1)
nA
V
V
90
220
V(RB)
1.7
(1) Specified by design. Not production tested.
SMBus TIMING CHARACTERISTICS
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(SMB)
SMBus operating frequency
Slave mode, SMBC 50% duty cycle
10
100
kHz
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SMBus TIMING CHARACTERISTICS (continued)
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(MAS)
SMBus master clock frequency
Master mode, No clock low slave
extend
51.2
kHz
Bus free time between start and stop
(see Figure 3)
t(BUF)
4.7
µs
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
Hold time after (repeated) start (see Figure 3)
Repeated start setup time (see Figure 3)
Stop setup time (see Figure 3)
4
4.7
4
µs
µs
µs
ns
Receive mode
Transmit mode
0
Data hold time (see Figure 3)
300
250
25
4.7
4
t(SU:DAT)
t(TIMEOUT)
t(LOW)
Data setup time (see Figure 3)
Error signal/detect (see Figure 3)
Clock low period (see Figure 3)
Clock high period (see Figure 3)
ns
µs
µs
µs
ms
(1)
See
35
(2)
t(HIGH)
See
50
25
(3)
t(LOW:SEXT) Cumulative clock low slave extend time
See
Cumulative clock low master extend time
(see Figure 3)
(4)
t(LOW:MEXT)
See
10
ms
(5)
tf
tr
Clock/data fall time
Clock/data rise time
See
300
ns
ns
(6)
See
1000
(1) The bq20z655-R1 times out when any clock low exceeds t(TIMEOUT)
.
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z655-R1 that
is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tf = 0.9 VDD to (VILMAX – 0.15)
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tR
tF
tF
tR
tSU(STO)
tHD(STA)
tBUF
tHIGH
SMBC
SMBC
SMBD
tLOW
SMBD
P
S
tHD(DAT)
tSU(DAT)
Start and Stop condition
Wait and Hold condition
tSU(STA)
tTIMEOUT
SMBC
SMBD
SMBC
SMBD
S
Timeout condition
Repeated Start condition
A. SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 3. SMBus Timing Diagram
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FEATURE SET
Primary (1st Level) Safety Features
The bq20z655-R1 supports a wide range of battery and system protection features that can easily be configured.
The primary safety features include:
•
•
•
•
•
Cell over/undervoltage protection
Charge and discharge overcurrent
Short Circuit protection
Charge and discharge overtemperature with independent alarms and thresholds for each thermistor
AFE Watchdog
Secondary (2nd Level) Safety Features
The secondary safety features of the bq20z655-R1 can be used to indicate more serious faults via the SAFE pin.
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
•
•
•
•
•
•
•
•
•
•
•
Safety overvoltage
Safety undervoltage
2nd level protection IC input
Safety overcurrent in charge and discharge
Safety over-temperature in charge and discharge with independent alarms and thresholds for each thermistor
Charge FET and zero-volt charge FET fault
Discharge FET fault
Cell imbalance detection (active and at rest)
Open thermistor detection
Fuse blow detection
AFE communication fault
Charge Control Features
The bq20z655-R1 charge control features include:
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range.
Handles more complex charging profiles. Allows for splitting the standard temperature range into two
sub-ranges and allows for varying the charging current according to the cell voltage.
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
Determines the chemical state of charge of each battery cell using Impedance Track™ and can reduce the
charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing
algorithm during charging. This prevents fully charged cells from overcharging and causing excessive
degradation and also increases the usable pack energy by preventing premature charge termination
•
•
•
Supports pre-charging/zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status via charge and discharge alarms.
Gas Gauging
The bq20z655-R1 uses the Impedance Track™ Technology to measure and calculate the available charge in
battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full
charge discharge learning cycle required.
See the Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note
(SLUA364) for further details.
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Lifetime Data Logging Features
The bq20z655-R1 offers lifetime data logging, where important measurements are stored for warranty and
analysis purposes. The data monitored include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Lifetime maximum temperature
Lifetime maximum temperature count
Lifetime maximum temperature duration
Lifetime minimum temperature
Lifetime maximum battery cell voltage
Lifetime maximum battery cell voltage count
Lifetime maximum battery cell voltage duration
Lifetime minimum battery cell voltage
Lifetime maximum battery pack voltage
Lifetime minimum battery pack voltage
Lifetime maximum charge current
Lifetime maximum discharge current
Lifetime maximum charge power
Lifetime maximum discharge power
Lifetime maximum average discharge current
Lifetime maximum average discharge power
Lifetime average temperature
Authentication
The bq20z655-R1 supports authentication by the host using SHA-1.
Power Modes
The bq20z655-R1 supports three different power modes to reduce power consumption:
•
In Normal Mode, the bq20z655-R1 performs measurements, calculations, protection decisions and data
updates in 1 second intervals. Between these intervals, the bq20z655-R1 is in a reduced power stage.
•
In Sleep Mode, the bq20z655-R1 performs measurements, calculations, protection decisions and data update
in adjustable time intervals. Between these intervals, the bq20z655-R1 is in a reduced power stage. The
bq20z655-R1 has a wake function that enables exit from Sleep mode, when current flow or failure is detected.
•
In Shutdown Mode, the bq20z655-R1 is completely disabled.
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CONFIGURATION
Oscillator Function
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The bq20z655-R1 fully integrates the system oscillators therefore, no external components are required for this
feature.
System Present Operation
The bq20z655-R1 periodically verifies the PRES pin and detects that the battery is present in the system via a
low state on a PRES input. When this occurs, the bq20z655-R1 enters normal operating mode. When the pack is
removed from the system and the PRES input is high, the bq20z655-R1 enters the battery-removed state,
disabling the charge, discharge, and ZVCHG FETs. The PRES input is ignored and can be left floating when
non-removal mode is set in the data flash.
BATTERY PARAMETER MEASUREMENTS
The bq20z655-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement,
and a second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from -0.25 V to 0.25 V. The bq20z655-R1 detects charge activity when VSR = V(SRP)-V(SRN)is positive and
discharge activity when VSR = V(SRP) - V(SRN) is negative. The bq20z655-R1 continuously integrates the signal
over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq20z655-R1 updates the individual series cell voltages at one second intervals. The internal ADC of the
bq20z655-R1 measures the voltage, scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track™ gas-gauging.
Current
The bq20z655-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 5–mΩ to 20–mΩ typ. sense resistor.
Wake Function
The bq20z655-R1 can exit sleep mode, if enabled, by the presence of a programmable level of current signal
across SRP and SRN.
Auto Calibration
The bq20z655-R1 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq20z655-R1 performs auto-calibration when the SMBus lines
stay low continuously for a minimum of a programmable amount of time.
Temperature
The bq20z655-R1 has an internal temperature sensor and 2 external temperature sensor inputs, TS1 and TS2,
used in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery
environmental temperature. The bq20z655-R1 can be configured to use the internal temperature sensor or up to
2 external temperature sensors.
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COMMUNICATIONS
The bq20z655-R1 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq20z655-R1 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing
this state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
SBS Commands
Table 2. SBS COMMANDS
SBS
CMD
SIZE IN
BYTES
MIN
VALUE
MAX
VALUE
DEFAULT
VALUE
MODE
NAME
FORMAT
UNIT
0x00
0x01
0x02
R/W
R/W
R/W
ManufacturerAccess
RemainingCapacityAlarm
RemainingTimeAlarm
Hex
2
2
2
0x0000
0xffff
700 or 1000
30
—
300 or 432
10
—
mAh or 10 mWh
min
Integer
0
0
Unsigned
integer
0x03
0x04
0x05
R/W
R/W
R
BatteryMode
AtRate
Hex
2
2
2
0x0000
–32,768
0
0xffff
—
—
—
—
mA or 10 mW
min
Integer
32,767
65,535
AtRateTimeToFull
Unsigned
integer
0x06
0x07
0x08
0x09
R
R
R
R
AtRateTimeToEmpty
AtRateOK
Unsigned
integer
2
2
2
2
0
0
0
0
65,535
65,535
65,535
20,000
—
—
—
—
min
—
Unsigned
integer
Temperature
Voltage
Unsigned
integer
0.1°K
mV
Unsigned
integer
0x0a
0x0b
0x0c
R
R
R
Current
AverageCurrent
MaxError
Integer
Integer
2
2
1
–32,768
–32,768
0
32767
32,767
100
—
—
—
mA
mA
%
Unsigned
integer
0x0d
0x0e
0x0f
R
R
RelativeStateOfCharge
AbsoluteStateOfCharge
RemainingCapacity
FullChargeCapacity
RunTimeToEmpty
Unsigned
integer
1
1
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
100
—
—
—
—
—
—
—
—
—
%
Unsigned
integer
100+
%
R/W
R
Unsigned
integer
65,535
65,535
65,534
65,534
65,534
65,534
65,534
mAh or 10 mWh
0x10
0x11
0x12
0x13
0x14
0x15
Unsigned
integer
mAh or 10 mWh
R
Unsigned
integer
min
min
min
mA
mV
R
AverageTimeToEmpty
AverageTimeToFull
ChargingCurrent
Unsigned
integer
R
Unsigned
integer
R
Unsigned
integer
R
ChargingVoltage
Unsigned
integer
0x16
0x17
R
BatteryStatus
CycleCount
Hex
2
2
0x0000
0
0xdbff
—
—
—
R/W
Unsigned
integer
65,535
0
0x18
0x19
R/W
R/W
DesignCapacity
DesignVoltage
Integer
Integer
2
2
0
32,767
18,000
4400 or 6336 mAh or 10 mWh
14,400 mV
7000
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UNIT
Table 2. SBS COMMANDS (continued)
SBS
SIZE IN
BYTES
MIN
VALUE
MAX
VALUE
DEFAULT
VALUE
MODE
CMD
NAME
FORMAT
0x1a
0x1b
R/W
R/W
SpecificationInfo
ManufactureDate
Hex
2
2
0x0000
0
0xffff
0x0031
0
—
—
Unsigned
integer
65,535
0x1c
0x20
R/W
R/W
SerialNumber
Hex
2
0x0000
0xffff
0x0000
—
—
ManufacturerName
String
20+1
—
—
Texas
Instruments
0x21
0x22
0x23
0x2f
R/W
R/W
R
DeviceName
DeviceChemistry
ManufacturerData
Authenticate
String
String
String
String
20+1
4+1
14+1
20+1
2
—
—
—
—
0
—
—
bq20z655-R1
—
—
LION
—
—
—
R/W
R
—
—
—
0x3c
CellVoltage4
Unsigned
integer
65,535
—
mV
0x3d
0x3e
0x3f
R
R
R
CellVoltage3
CellVoltage2
CellVoltage1
Unsigned
integer
2
2
2
0
0
0
65,535
65,535
65,535
—
—
—
mV
mV
mV
Unsigned
integer
Unsigned
integer
Table 3. EXTENDED SBS COMMANDS
SBS
CMD
SIZE IN
BYTES
MIN
VALUE
MAX
VALUE
DEFAULT
VALUE
MODE
NAME
FORMAT
UNIT
0x45
0x46
0x4f
R
R/W
R
AFEData
FETControl
StateOfHealth
SafetyStatus
PFAlert
String
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
11+1
—
—
0xff
—
—
—
—
—
—
—
—
—
—
—
—
%
2
2
2
2
2
2
2
2
2
0x00
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0
0xffff
0xffff
0xffff
0xffff
0xffff
0xffff
0xffff
65,535
0x51
0x52
0x53
0x54
0x55
0x57
0x58
R
—
—
—
—
—
—
—
R
R
PFStatus
R
OperationStatus
ChargingStatus
ResetData
R
R
R
WDResetData
Unsigned
integer
0x5a
0x5d
R
R
PackVoltage
Unsigned
integer
2
2
0
0
65,535
65,535
—
—
mV
mV
AverageVoltage
Unsigned
integer
0x5e
0x5f
R
R
TS1Temperature
TS2Temperature
UnSealKey
Integer
Integer
Hex
2
2
4
4
4
4
4
4
4
2
2
2
2
-400
1200
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1°C
0.1°C
—
-400
1200
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x68
0x69
0x6a
0x6b
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x000f
0x000f
0x000f
0x000f
FullAccessKey
PFKey
Hex
—
Hex
—
AuthenKey3
AuthenKey2
AuthenKey1
AuthenKey0
SafetyAlert2
SafetyStatus2
PFAlert2
Hex
—
Hex
—
Hex
—
Hex
—
Hex
—
R
Hex
0x0000
—
R
Hex
0x0000
—
R
PFStatus2
Hex
0x0000
—
18
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq20z655-R1
bq20z655-R1
www.ti.com
SBS
CMD
0x6c
0x6d
0x6e
0x6f
SLUSAN9 –AUGUST 2011
Table 3. EXTENDED SBS COMMANDS (continued)
SIZE IN
BYTES
MIN
VALUE
MAX
VALUE
DEFAULT
VALUE
MODE
NAME
FORMAT
UNIT
R
R
ManufBlock1
ManufBlock2
ManufBlock3
ManufBlock4
ManufacturerInfo
SenseResistor
String
String
String
String
String
20
20
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
μΩ
R
20
—
R
20
—
0x70
0x71
R/W
R/W
31+1
2
—
Unsigned
integer
65,535
0x72
0x73
0x74
0x77
0x78
0x79
0x7a
0x7b
0x7c
0x7d
0x7e
0x7f
R
TempRange
Hex
String
String
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
Hex
2
32+1
8+1
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R
LifetimeData1
R
LifetimeData2
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DataFlashSubClassID
DataFlashSubClassPage1
DataFlashSubClassPage2
DataFlashSubClassPage3
DataFlashSubClassPage4
DataFlashSubClassPage5
DataFlashSubClassPage6
DataFlashSubClassPage7
DataFlashSubClassPage8
0x0000
—
0xffff
—
32
32
—
—
32
—
—
32
—
—
32
—
—
32
—
—
32
—
—
32
—
—
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s): bq20z655-R1
bq20z655-R1
SLUSAN9 –AUGUST 2011
www.ti.com
APPLICATION SCHEMATIC
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Product Folder Link(s): bq20z655-R1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
BQ20Z655DBT-R1
BQ20Z655DBTR-R1
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
DBT
44
44
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-250C-1 YEAR
BQ20Z655
BQ20Z655
ACTIVE
DBT
2000
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ20Z655DBTR-R1
TSSOP
DBT
44
2000
330.0
24.4
6.8
11.7
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DBT 44
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
BQ20Z655DBTR-R1
2000
Pack Materials-Page 2
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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