BQ20Z95DBT [TI]
SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION ENABLED WITH IMPEDANCE TRACK⑩; SBS 1.1的电量监测计和保护已启用采用Impedance Track ™
| 型号： | BQ20Z95DBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION ENABLED WITH IMPEDANCE TRACK⑩ |
| 文件： | 总20页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq20z95
www.ti.com
SLUS757–JULY 2007
SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION ENABLED WITH IMPEDANCE
TRACK™
1
FEATURES
DESCRIPTION
2
•
Next Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
The bq20z95 SBS-compliant gas gauge and
protection IC is a single IC solution designed for
battery-pack or in-system installation. The bq20z95
measures and maintains an accurate record of
available charge in Li-ion or Li-polymer batteries
using its integrated high-performance analog
peripherals, monitors capacity change, battery
impedance, open-circuit voltage, and other critical
parameters of the battery pack as well and reports
the information to the system host controller over a
serial-communication bus. Together with the
integrated analog front-end (AFE) short-circuit and
overload protection, the bq20z95 maximizes
functionality and safety while minimizing external
component count, cost, and size in smart battery
circuits.
–
Better Than 1% Error Over Lifetime of the
Battery
•
•
•
•
Supports the Smart Battery Specification
SBS V1.1
Flexible Configuration for 2 to 4 Series Li-Ion
and Li-Polymer Cells
Powerful 8-Bit RISC CPU With Ultra-Low
Power Modes
Full Array of Programmable Protection
Features
–
Voltage, Current, and Temperature
•
•
Supports SHA-1 Authentication
The implemented Impedance Track™ gas gauging
technology continuously analyzes the battery
impedance, resulting in superior gas-gauging
accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
aging all accounted for during each stage of every
cycle with high accuracy.
Complete Battery Protection and Gas Gauge
Solution in one Package
•
Small 44-Pin TSSOP (DBT) package
APPLICATIONS
•
•
•
Notebook PCs
Medical and Test Equipment
Portable Instrumentation
AVAILABLE OPTIONS
PACKAGE(1)
TA
44-PIN TSSOP (DBT) Tube
44-PIN TSSOP (DBT) Tape and Reel
–40°C to 85°C
bq20z95DBT(2)
bq20z95DBTR(3)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
bq20z95
www.ti.com
SLUS757–JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SYSTEM PARTITIONING DIAGRAM
Pack +
RBI
D¯¯IS¯P¯
Fuse Blow
Detection and
Logic
Power Mode
Control
Pre Charge FET
& PGOD Drive
N-Channel FET
Drive
LED Display
Oscillator
M¯¯S¯R¯¯T
SMBD
SMBC
R¯¯E¯S¯E¯T¯
¯A¯L¯E¯R¯T¯
SMBD
SMBC
SMB 1.1
System Control
AFE HW Control
Watchdog
VCELL+
Data Flash
Memory
Voltage
Cell Voltage
Multiplexer
Measurement
VC1
VC2
VC3
VC4
VC5
VC1
VC2
VC3
VC4
VDD
OUT
CD
Over
Temperature
Protection
Over- & Under-
Voltage
Impedance
Track™
GND
Charging
Algorithm
Cell Balancing
Protection
Gas Gauging
bq294xx
REG33
REG25
HW Over
Current &
SHA-1
Temperature
Measurement
Over Current
Protection
Coloumb
Counter
Regulators
Authentication
Short Circuit
Protection
bq20z95
Pack -
RSNS
5mΩ – 20mΩ typ.
bq20z95
DBT Package
(TOP VIEW)
DSG
PACK
VCC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CHG
BAT
VC1
2
3
ZVCHG
GPOD
PMS
4
VC2
VC3
5
6
VC4
VC5
VSS
7
REG33
TOUT
VCELL+
8
ASRP
ASRN
¯R¯E¯S¯E¯T¯
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
¯¯¯¯¯¯
ALERT
NC
TS1
TS2
RBI
REG25
VSS
P¯¯R¯E¯S¯
M¯¯R¯S¯¯T
GSRN
GSRP
LED5
LED4
LED3
LED2
LED1
P¯¯F¯IN¯
SAFE
SMBD
NC
SMBC
D¯I¯S¯P¯
VSS
2
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SLUS757–JULY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O(1)
DESCRIPTION
NO.
NAME
1
DSG
O
High side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in shutdown
mode.
2
PACK
IA, P
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input
3
4
5
VCC
P
O
ZVCHG
GPOD
P-chan pre-charge FET gate drive
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition
OD
Pre-charge mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0V pre-charge using charge FET connected at
CHG pin.
6
PMS
I
7
8
VSS
REG33
TOUT
P
P
P
-
Negative device power supply input. Connect all VSS pins together for operation of device
3.3V regulator output. Connect at least a 2.2µF capacitor to REG33 and VSS
Thermistor bias supply output
9
10
VCELL+
Internal cell voltage multiplexer and amplifier output. Connect a 0.1µF capacitor to VCELL+ and VSS
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
11
ALERT
I/OD
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
TS1
-
Not connected
IA
Temperature sensor 1 input
TS2
IA
Temperature sensor 2 input
PRES
PFIN
SAFE
SMBD
NC
I/OD
System / Host present input. Pull up to TOUT
I/OD
Fuse blow detection input
I/OD
blow fuse signal output
I/OD
SMBus data line
-
Not connected
SMBC
DISP
VSS
I/OD
SMBus clock line
I/OD
Display enable input
P
I
Negative device power supply input. Connect all VSS pins together for operation of device
LED 1 current sink input
LED1
LED2
LED3
LED4
LED5
GSRP
GSRN
MRST
VSS
I
LED 2 current sink input
I
LED 3 current sink input
I
LED 4 current sink input
I
LED 5 current sink input
IA
IA
I
Coulomb counter differential input. Connect to one side of the sense resistor
Coulomb counter differential input. Connect to one side of the sense resistor
Reset input for internal CPU core. connect to RESET for correct operation of device
Negative device power supply input. Connect all VSS pins together for operation of device
2.5V regulator output. Connect at least a 1µF capacitor to REG25 and VSS
P
P
REG25
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
short circuit condition
33
RBI
P
34
35
36
37
VSS
RESET
ASRN
ASRP
P
O
Negative device power supply input. Connect all VSS pins together for operation of device
Reset output. Connect to MSRT.
IA
IA
Short circuit and overload detection differential input. Connect to sense resistor
Short circuit and overload detection differential input. Connect to sense resistor
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
stack.
38
39
VC5
VC4
IA, P
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in cell stack.
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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SLUS757–JULY 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O(1)
DESCRIPTION
NO.
NAME
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
cell stack and the negative voltage of the second highest cell in 4 cell applications.
40
VC3
VC2
VC1
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
IA, P and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack
applications
41
42
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4 cell applications. Connect to VC2 in 3 or 2 cell stack applications
IA, P
43
44
BAT
I, P
O
Battery stack voltage sense input
CHG
High side N-chan charge FET gate drive
Absolute Maximum Ratings
Over Operating Free-Air Temperature (unless otherwise noted)
(1)
DESCRIPTION
PIN
UNIT
VBAT, VCC
–0.3 V to 34 V
–0.3 V to 34 V
–0.3 V to 8.5 V
–0.3 V to 34 V
–0.3 V to 1 V
PACK, PMS
VSS
Supply voltage range
VC(n)-VC(n+1); n = 1, 2, 3, 4
VC1, VC2, VC3, VC4
VC5
PFIN, SMBD, SMBC, LED1, LED2,
LED3, LED4, LED5, DISP
–0.3 V to 6 V
TS1, TS2, SAFE, VCELL+, PRES;
ALERT
–0.3 V to V(REG25) + 0.3 V
VIN
Input voltage range
MRST, GSRN, GSRP, RBI
ASRN, ASRP
–0.3 V to V(REG25) + 0.3 V
–1 V to 1 V
DSG, CHG, GPOD
ZVCHG
–0.3 V to 34 V
–0.3 V to V (BAT)
–0.3 V to 6 V
VOUT
Output voltage range
TOUT, ALERT, REG33
RESET
–0.3 V to 7 V
REG25
–0.3 V to 2.75 V
PRES, PFIN, SMBD, SMBC, LED5,
LED4, LED3, LED2, LED1
ISS
Maximum combined sink current for input pins
50 mA
TA
Operating free-air temperature range
Functional temperature
–40°C to 85°C
–40°C to 100°C
–65°C to 150°C
TF
Tstg
Storage temperature range
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
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SLUS757–JULY 2007
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VSS
PIN
MIN
4.5
5.5
0
NOM
MAX
UNIT
V
Supply voltage
VCC, VBAT
VCC, BAT, PACK
VC(n)-VC(n+1); n = 1,2,3,4
VC1, VC2, VC3, VC4
VC5
25
V(STARTUP)
Minimum startup voltage
V
5
VSUP
0.5
0.5
25
V
0
V
VIN
Input Voltage Range
0
V
ASRN, ASRP
PACK, PMS
GPOD
–0.5
0
V
V
V(GPOD)
A(GPOD)
C(REG25)
C(REG33)
C(VCELL+)
C(PACK)
Output Voltage Range
Drain Current(1)
0
25
V
GPOD
1
mA
µF
µF
µF
kΩ
2.5V LDO Capacitor
REG25
1
2.2
0.1
1
3.3V LDO Capacitor
REG33
Cell Voltage Output Capacitor
PACK input block resistor(2)
VCELL+
PACK
(1) Use an external resistor to limit the current to GPOD to 1mA in high voltage application.
(2) Use an external resistor to limit the inrush current PACK pin required.
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT)
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(NORMAL)
I(SLEEP)
Firmware running
Sleep Mode
550
124
90
µA
µA
µA
µA
µA
CHG FET on; DSG FET on
CHG FET off; DSG FET on
CHG FET off; DSG FET off
52
I(SHUTDOWN)
Shutdown Mode
0.1
1
1
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
I(PACK) Shutdown exit at VSTARTUP threshold
µA
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
Positive or negative wake threshold
V(WAKE)
with 1.00 mV, 2.25 mV, 4.5 mV and 9
mV programmable options
1.25
-0.7
-0.8
10
0.7
0.8
mV
V(WAKE) = 1 mV;
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1;
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
V(WAKE_ACR)
Accuracy of V(WAKE)
mV
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
-1.0
-1.4
1.0
1.4
V(WAKE) = 9 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
V(WAKE_TCO)
t(WAKE)
Temperature drift of V(WAKE) accuracy
0.5
1
%/°C
Time from application of current and
wake of bq8040
10
ms
POWER-ON RESET
VIT–
Vhys
Negative-going voltage input
Voltage at REG25 pin
VIT+ – VIT-
1.70
50
1.80
150
1.90
250
V
Hysteresis
mV
active low time after power up or
watchdog reset
tRST
RESET active low time
100
250
560
µs
WATCHDOG TIMER
tWDTINT
Watchdog start up detect time
250
500
1000
ms
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SLUS757–JULY 2007
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT)
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tWDWT
Watchdog detect time
50
100
150
µs
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
I(REG25OUT) ≤ 16 mA;
V(REG25)
Regulator output voltage
2.41
2.5
2.59
V
TA = –40°C to 100°C
Regulator output change with
temperature
I(REG25OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG25TEMP)
ΔV(REG25LINE)
±0.2
3
%
5.4 < VCC or BAT < 25 V;
I(REG25OUT) = 2 mA
Line regulation
Load Regulation
Current Limit
10
mV
0.2 mA ≤ I(REG25OUT) ≤ 2 mA
0.2 mA ≤ I(REG25OUT) ≤ 16 mA
7
25
50
ΔV(REG25LOAD)
mV
mA
25
drawing current until
REG25 = 2 V to 0 V
I(REG25MAX)
5
3
40
75
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
4.5 < VCC or BAT < 25 V;
V(REG33)
Regulator output voltage
I(REG33OUT) ≤ 25 mA;
3.3
3.6
V
TA = –40°C to 100°C
Regulator output change with
temperature
I(REG33OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG33TEMP)
ΔV(REG33LINE)
±0.2
3
%
5.4 < VCC or BAT < 25 V;
I(REG33OUT) = 2 mA
Line regulation
10
mV
0.2 mA ≤ I(REG33OUT) ≤ 2 mA
7
40
17
100
145
65
ΔV(REG33LOAD)
Load Regulation
mV
mA
0.2mA ≤ I(REG33OUT) ≤ 25 mA
drawing current until REG33 = 3 V
short REG33 to VSS, REG33 = 0 V
25
12
100
I(REG33MAX)
Current Limit
THERMISTOR DRIVE
V(TOUT) Output voltage
I(TOUT) = 0 mA; TA = 25°C
V(REG25)
50
V
I(TOUT) = 1 mA; RDS(on) = (V(REG25)
V(TOUT) )/ 1 mA; TA = –40°C to 100°C
-
RDS(on)
TOUT pass element resistance
100
Ω
VCELL+ HIGH VOLTAGE TRANSLATION
VC(n) - VC(n+1) = 0 V;
TA = –40°C to 100°C
0.950
0.275
0.965
0.975
0.3
1
0.375
0.985
V(VCELL+OUT)
VC(n) - VC(n+1) = 4.5 V;
TA = –40°C to 100°C
internal AFE reference voltage ;
TA = –40°C to 100°C
V(VCELL+REF)
V(VCELL+PACK)
Translation output
0.975
V
Voltage at PACK pin;
TA = –40°C to 100°C
0.98 ×
V(PACK)/18
1.02 ×
V(PACK)/18
V(PACK)/18
V(BAT)/18
Voltage at BAT pin;
TA = –40°C to 100°C
0.98 ×
V(BAT)/18
1.02 ×
V(BAT)/18
V(VCELL+BAT)
CMMR
Common mode rejection ratio
Cell scale factor
VCELL+
40
dB
K= {VCELL+ output (VC5=0V;
VC4=4.5V) - VCELL+ output (VC5=0V;
VC4=0V)}/4.5
0.147
0.150
0.153
0.153
K
K= {VCELL+ output (VC2=13.5V;
VC1=18V) - VCELL+ output
(VC5=13.5V; VC1=13.5V)}/4.5
0.147
12
0.150
18
VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;
TA = –40°C to 100°C
I(VCELL+OUT)
Drive Current to VCELL+ capacitor
µA
CELL output (VC2 = VC1 = 18 V) -
CELL output (VC2 = VC1 = 0 V)
V(VCELL+O)
IVCnL
CELL offset error
-18
-1
-1
18
1
mV
VC(n) pin leakage current
VC1, VC2, VC3, VC4, VC5 = 3 V
0.01
µA
CELL BALANCING
RBAL internal cell balancing FET resistance
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
200
400
600
Ω
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
6
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SLUS757–JULY 2007
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT)
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
VOL = 25 mV (min)
MIN
15
TYP
25
MAX
35
UNIT
OL detection threshold voltage
accuracy
V(OL)
VOL = 100 mV; RSNS = 0, 1
VOL = 205 mV (max)
90
100
110
225
70
mV
mV
mV
185
30
205
V(SCC) = 50 mV (min)
50
SCC detection threshold voltage
accuracy
V(SCC)
V(SCC) = 200 mV; RSNS = 0, 1
V(SCC) = 475 mV (max)
V(SCD) = –50 mV (min)
180
428
–30
–180
–428
200
220
523
–70
–220
–523
475
–50
SCD detection threshold voltage
accuracy
V(SCD)
V(SCD) = –200 mV; RSNS = 0, 1
V(SCD) = –475 mV (max)
–200
–475
±15.25
50
tda
tpd
Delay time accuracy
µs
µs
Protection circuit propagation delay
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON) = V(DSG) - V(PACK); V(GS) = 10
MΩ; DSG and CHG on;
TA = –40°C to 100°C
V(DSGON)
DSG pin output on voltage
CHG pin output on voltage
8
8
12
12
16
16
V
V
V(CHGON) = V(CHG) - V(BAT); V(GS) = 10
MΩ; DSG and CHG on;
V(CHGON)
TA = –40°C to 100°C
V(DSGOFF)
V(CHGOFF)
DSG pin output off voltage
CHG pin output off voltage
V(DSGOFF) = V(DSG) - V(PACK)
V(CHGOFF) = V(CHG) - V(BAT)
0.2
0.2
V
V
CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK)
4V
+
400
400
40
1000
1000
200
tr
Rise time
µs
CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT)
+
4V
CL= 4700pF; V(PACK) + V(DSGON) ≤ DSG
≤ V(PACK) + 1V
tf
Fall time
µs
CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG
≤ V(BAT) + 1V
40
200
3.7
V(ZVCHG)
ZVCHG clamp voltage
BAT = 4.5 V
3.3
3.5
V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
ALERT
RESET
ALERT
60
1
100
3
200
6
R(PULLUP)
Internal pullup resistance
kΩ
0.2
RESET; V(BAT) = 7V; V(REG25) = 1.5 V;
I(RESET) = 200 µA
VOL
Logic low output voltage level
0.4
0.6
V
GPOD; I(GPOD) = 50 µA
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT
VIH
High-level input voltage
Low-level input voltage
Output voltage high(1)
Low-level output voltage
Input capacitance
2.0
V
V
VIL
0.8
0.4
VOH
IL = –0.5 mA
VREG25–0.5
V
VOL
PRES, PFIN, ALERT, IL = 7 mA;
V
CI
5
pF
mA
µA
µA
I(SAFE)
Ilkg(SAFE)
Ilkg
SAFE source currents
SAFE leakage current
Input leakage current
SAFE active, SAFE = V(REG25) –0.6 V
SAFE inactive
–3
–0.2
0.2
1
ADC(2)
Input voltage range
Conversion time
TS1, TS2, using Internal Vref
–0.2
1
V
31.5
15
ms
bits
bits
Resolution (no missing codes)
Effective resolution
16
14
(1) RC[0:7] bus
(2) Unless otherwise specified, the specification limits are valid at all measurement speed modes
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT)
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
=
PARAMETER
Integral nonlinearity
Offset error(4)
Offset error drift(4)
Full-scale error(5)
TEST CONDITIONS
MIN
TYP
MAX
±0.03 %FSR(3)
UNIT
140
2.5
250
18
µV
TA = 25°C to 85°C
µV/°C
±0.1%
50
±0.7%
Full-scale error drift
Effective input resistance(6)
PPM/°C
MΩ
8
–0.20
15
COULOMB COUNTER
Input voltage range
Conversion time
0.20
±0.034
0.7
V
Single conversion
Single conversion
–0.1 V to 0.20 V
–0.20 V to –0.1 V
TA = 25°C to 85°C
250
ms
bits
Effective resolution
±0.007
±0.007
10
Integral nonlinearity
%FSR
(7)
Offset error
µV
Offset error drift
Full-scale error(8)(9)
0.4
µV/°C
±0.35%
150
Full-scale error drift
Effective input resistance(10)
PPM/°C
MΩ
TA = 25°C to 85°C
2.5
INTERNAL TEMPERATURE SENSOR
V(TEMP)
VOLTAGE REFERENCE
Output voltage
Temperature sensor voltage(11)
-2.0
mV/°C
1.215
1.225
65
1.230
V
Output voltage drift
PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency
4.194
0.25%
0.25%
2.5
MHz
–3%
–2%
3%
2%
5
(12)(13)
f(EIO)
Frequency error
Start-up time(14)
TA = 20°C to 70°C
t(SXO)
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
f(LEIO)
t(LSXO)
Operating frequency
Frequency error(13)(15)
Start-up time(14)
32.768
0.25%
0.25%
kHz
–2.5%
–1.5%
2.5%
1.5%
500
TA = 20°C to 70°C
µs
(3) Full-scale reference
(4) Post-calibration performance and no I/O changes during conversion with SRN as the ground reference
(5) Uncalibrated performance. This gain error can be eliminated with external calibration.
(6) The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(7) Post-calibration performance
(8) Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
(9) Uncalibrated performance. This gain error can be eliminated with external calibration.
(10) The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
(11) –53.7 LSB/°C
(12) The frequency error is measured from 4.194 MHz.
(13) The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5V, TA = 25°C
(14) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%
(15) The frequency error is measured from 32.768 kHz.
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Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITIONS
MIN
10
TYP
MAX
UNIT
Years
Cycles
ms
Flash programming write-cycles
Row programming time
20k
(1)
t(ROWPROG)
See
2
200
20
t(MASSERASE) Mass-erase time
t(PAGEERASE) Page-erase time
ms
ms
I(DDPROG)
I(DDERASE)
RAM BACKUP
Flash-write supply current
5
5
10
mA
Flash-erase supply current
10
mA
V(RBI) > V(RBI)MIN , VREG25 < VIT–
TA = 85°C
,
1000
90
2500
220
I(RB)
RB data-retention input current
nA
V
V(RBI) > V(RBI)MIN , VREG25 < VIT–
,
TA = 25°C
V(RB)
RB data-retention input voltage(1)
1.7
(1) Specified by design. Not production tested.
SMBus Timing Characteristics
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
SMBus operating frequency
SMBus master clock frequency
TEST CONDITIONS
MIN
TYP
MAX
100
UNIT
kHz
f(SMB)
f(MAS)
Slave mode, SMBC 50% duty cycle
10
Master mode, No clock low slave
extend
51.2
kHz
Bus free time between start and stop
(see Figure 1)
t(BUF)
4.7
µs
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
Hold time after (repeated) start (see Figure 1)
Repeated start setup time (see Figure 1)
Stop setup time (see Figure 1)
4
4.7
4
µs
µs
µs
ns
Receive mode
Transmit mode
0
Data hold time (see Figure 1)
300
250
25
4.7
4
t(SU:DAT)
t(TIMEOUT)
t(LOW)
Data setup time (see Figure 1)
Error signal/detect (see Figure 1)
Clock low period (see Figure 1)
Clock high period (see Figure 1)
ns
µs
µs
µs
µs
(1)
See
35
(2)
t(HIGH)
See
50
25
(3)
t(LOW:SEXT) Cumulative clock low slave extend time
See
Cumulative clock low master extend time
(see Figure 1)
(4)
t(LOW:MEXT)
See
10
µs
(5)
tf
tr
Clock/data fall time
Clock/data rise time
See
300
ns
ns
(6)
See
1000
(1) The bq8040 times out when any clock low exceeds t(TIMEOUT)
.
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq8040 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tf = 0.9VDD to (VILMAX – 0.15)
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T
LOW
T
R
T
F
T
HD:STA
SCLK
T
T
T
HIGH
T
SU:STO
SU:STA
HD:STA
T
SU:DAT
T
HD:DAT
SDATA
T
BUF
P
S
S
P
Start
Stop
T
LOW:SEXT
†
†
SCLK
SCLK
ACK
ACK
T
T
T
LOW:MEXT
LOW:MEXT
LOW:MEXT
SCLK
SDATA
A. SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
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FEATURE SET
Primary (1st Level) Safety Features
The bq20z95 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
•
•
•
•
•
Cell over/under voltage protection
Charge and Discharge over current
Short Circuit
Charge and Discharge Over temperature
AFE Watchdog
Secondary (2nd Level) Safety Features
The secondary safety features of the bq20z95 can be used to indicate more serious faults via the SAFE (pin 7).
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
•
•
•
•
•
•
Safety over voltage
Safety over current in Charge and Discharge
Safety over temperature in Charge and Discharge
Charge FET and 0 Volt Charge FET fault
Discharge FET fault
AFE communication fault
Charge Control Features
The bq20z95 charge control features include:
•
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
•
Determines the chemical state of charge of each battery cell using Impedance Track™ and can reduce the
charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing
algorithm during charging. This prevents fully charged cells from overcharging and causing excessive
degradation and also increases the usable pack energy by preventing premature charge termination
•
•
•
•
Supports pre-charging/zero-volt charging
Support fast charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status via charge and discharge alarms.
Gas Gauging
The bq20z95 uses the Impedance Track™ Technology to measure and calculate the available charge in battery
cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge
discharge learning cycle required.
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364)
for further details.
Authentication
The bq20z95 supports authentication by the host using SHA-1.
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Power Modes
The bq20z95 supports 3 different power modes to reduce power consumption:
•
In Normal Mode, the bq20z95 performs measurements, calculations, protection decisions and data updates in
1 second intervals. Between these intervals, the bq20z95 is in a reduced power stage.
•
In Sleep Mode, the bq20z95 performs measurements, calculations, protection decisions and data update in
adjustable time intervals. Between these intervals, the bq20z95 is in a reduced power stage. The bq20z95
has a wake function that enables exit from Sleep mode, when current flow or failure is detected.
•
In Shutdown Mode the bq20z95 is completely disabled.
CONFIGURATION
Oscillator Function
The bq20z95 fully integrates the system oscillators. Therefore the bq20z95 requires no external components for
this feature.
System Present Operation
The bq20z95 checks the PRES pin periodically (1s). If PRES input is pulled to ground by external system, the
bq20z95 detects this as system present.
BATTERY PARAMETER MEASUREMENTS
The bq20z95 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage, and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from -0.25 V to 0.25 V. The bq20z95 detects charge activity when VSR = V(SRP)-V(SRN)is positive and
discharge activity when VSR = V(SRP) - V(SRN) is negative. The bq20z95 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq20z95 updates the individual series cell voltages at one second intervals. The internal ADC of the
bq20z95 measures the voltage, scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track™ gas-gauging.
Current
The bq20z95 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5 mΩ to 20 mΩ typ. sense resistor.
Auto Calibration
The bq20z95 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq20z95 performs auto-calibration when the SMBus lines stay
low continuously for a minimum of 5 s.
Temperature
The bq20z95 has an internal temperature sensor and 2 external temperature sensor inputs TS1 and TS2 used in
conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery environmental
temperature. The bq20z95 can be configured to use internal or up to 2 external temperature sensors.
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COMMUNICATIONS
The bq20z95 uses SMBus v1.1 with Master Mode and package error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq20z95 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
SBS Commands
Table 1. SBS COMMANDS
SBS
Cmd
Mode Name
Format
Size in Min
Max
Value
Default
Value
Unit
Bytes
Value
0x00
0x01
R/W
R/W
ManufacturerAccess
hex
2
2
0x0000
0
0xffff
—
—
RemainingCapacityAlarm
unsigned int
65535
mAh or
10mWh
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
R/W
R/W
R/W
R
RemainingTimeAlarm
BatteryMode
unsigned int
hex
2
2
2
2
2
2
2
2
2
2
1
1
1
2
0
65535
0xffff
—
—
—
—
—
—
—
—
—
—
—
—
—
—
min
0x0000
AtRate
signed int
-32768
32767
65535
65535
65535
65535
20000
32767
32767
100
mA or 10mW
AtRateTimeToFull
AtRateTimeToEmpty
AtRateOK
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
signed int
0
min
min
R
0
R
0
R
Temperature
0
0.1°K
mV
mA
mA
%
R
Voltage
0
R
Current
-32768
R
AverageCurrent
MaxError
signed int
-32768
R
unsigned int
unsigned int
unsigned int
unsigned int
0
0
0
0
R
RelativeStateOfCharge
AbsoluteStateOfCharge
RemainingCapacity
100
%
R
100
%
R/W
65535
mAh or
10mWh
0x10
R
FullChargeCapacity
unsigned int
2
0
65535
—
mAh or
10mWh
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
R
RunTimeToEmpty
AverageTimeToEmpty
AverageTimeToFull
ChargingCurrent
ChargingVoltage
BatteryStatus
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
unsigned int
2
2
2
2
2
2
2
2
0
65535
65535
65535
65535
65535
0xffff
—
—
—
—
—
—
—
—
min
min
min
mA
mV
R
0
R
0
R
0
R
0
R
0x0000
R/W
R/W
CycleCount
0
0
65535
65535
DesignCapacity
mAh or
10mWh
0x19
0x1a
0x1b
0x1c
0x20
R/W
R/W
R/W
R/W
R/W
DesignVoltage
unsigned int
unsigned int
unsigned int
hex
2
7000
0x0000
0
16000
0xffff
65535
0xffff
—
14400
0x0031
0
mV
SpecificationInfo
ManufactureDate
SerialNumber
2
2
2
0x0000
—
0x0001
ManufacturerName
String
11+1
Texas
ASCII
Instruments
0x21
0x22
0x23
0x2f
R/W
R/W
R
DeviceName
String
String
String
String
7+1
—
—
—
—
—
—
—
—
bq20z95
LION
—
ASCII
ASCII
ASCII
ASCII
DeviceChemistry
ManufacturerData
Authenticate
4+1
14+1
20+1
R/W
—
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Table 1. SBS COMMANDS (continued)
SBS
Cmd
Mode Name
Format
Size in Min
Max
Value
Default
Value
Unit
Bytes
Value
0x3c
0x3d
0x3e
0x3f
R
R
R
R
CellVoltage4
CellVoltage3
CellVoltage2
CellVoltage1
unsigned int
unsigned int
unsigned int
unsigned int
2
2
2
2
0
0
0
0
65535
65535
65535
65535
—
—
—
—
mV
mV
mV
mV
Table 2. EXTENDED SBS COMMANDS
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default
Unit
Value
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x45
0x46
0x4f
R
AFEData
String
hex
11+1
1
—
—
ASCII
R/W
R
FETControl
0x00
0xff
StateOfHealth
unsigned int
hex
1
0
100
%
0x51
0x53
0x54
0x55
0x57
0x5a
0x5d
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x70
0x71
0x77
0x78
0x79
0x7a
0x7b
0x7c
0x7d
0x7e
0x7f
R
SafetyStatus
2
0x0000
0xffff
0xffff
0xffff
0xffff
0xffff
65535
65535
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
—
R
PFStatus
hex
2
0x0000
R
OperationStatus
ChargingStatus
ResetData
hex
2
0x0000
R
hex
2
0x0000
R
hex
2
0x0000
R
PackVoltage
unsigned int
unsigned int
hex
2
0
mV
mV
R
AverageVoltage
UnSealKey
2
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4
0x00000000
FullAccessKey
hex
4
0x00000000
PFKey
hex
4
0x00000000
AuthenKey3
hex
4
0x00000000
AuthenKey2
hex
4
0x00000000
AuthenKey1
hex
4
0x00000000
AuthenKey0
hex
4
0x00000000
ManufacturerInfo
SenseResistor
String
unsigned int
hex
8+1
2
—
0
65535
0xffff
—
µΩ
DataFlashSubClassID
DataFlashSubClassPage1
DataFlashSubClassPage2
DataFlashSubClassPage3
DataFlashSubClassPage4
DataFlashSubClassPage5
DataFlashSubClassPage6
DataFlashSubClassPage7
DataFlashSubClassPage8
2
0x0000
—
hex
32
32
32
32
32
32
32
32
hex
—
—
hex
—
—
hex
—
—
hex
—
—
hex
—
—
hex
—
—
hex
—
—
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Application Schematic
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Oct-2007
PACKAGING INFORMATION
Orderable Device
BQ20Z95DBT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SM8
DBT
44
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BQ20Z95DBTR
SM8
DBT
44
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
BQ20Z95DBTR
DBT
44
SITE 60
330
24
6.8
11.7
1.6
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
BQ20Z95DBTR
DBT
44
SITE 60
367.0
367.0
45.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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Copyright © 2007, Texas Instruments Incorporated
相关型号：
BQ20ZDBT-V102G4
SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK TM TECHNOLOGY FOR USE WITH THE BQ29312A
TI
BQ20ZDBTR-V102G4
SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK TM TECHNOLOGY FOR USE WITH THE BQ29312A
TI
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