BQ24002PWPR [TI]

SINGLE-CELL LI-ION CHARGE MANAGEMENT ICFOR PDAS; 单节锂离子电池充电管理ICFOR PDAS
BQ24002PWPR
型号: BQ24002PWPR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

SINGLE-CELL LI-ION CHARGE MANAGEMENT ICFOR PDAS
单节锂离子电池充电管理ICFOR PDAS

电源电路 电池 电源管理电路 光电二极管 监视器 输入元件
文件: 总31页 (文件大小:881K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
www.ti.com  
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
ꢇꢈꢉ ꢊ ꢋ ꢌꢍ ꢎ ꢌꢋ ꢋ ꢋ ꢏꢍ ꢈꢐ ꢉ ꢎꢑ ꢒ ꢓꢊ ꢌ ꢔ ꢒꢉ ꢒꢊ ꢌꢔ ꢌ ꢉꢕ ꢈ ꢎ ꢖꢐ ꢓ ꢗ ꢘꢒꢙ  
ꢒ ꢉ ꢘ ꢈꢉ ꢕꢌꢓ ꢉ ꢌꢕ ꢒꢗ ꢗ ꢋꢈꢒ ꢉꢎ ꢌꢇ  
FEATURES  
DESCRIPTION  
D
Highly Integrated Solution With FET Pass  
Transistor and Reverse-Blocking Schottky  
and Thermal Protection  
The bq2400x series ICs are advanced Li-Ion linear  
charge management devices for highly integrated and  
space-limited applications. They combine high-  
accuracy current and voltage regulation; FET pass-  
transistor and reverse-blocking Schottky; battery  
conditioning, temperature, or input-power monitoring;  
charge termination; charge-status indication; and  
charge timer in a small package.  
D
D
D
Integrated Voltage and Current Regulation  
With Programmable Charge Current  
High-Accuracy Voltage Regulation ( 1%)  
Ideal for Low-Dropout Linear Charger  
Designs for Single-Cell Li-Ion Packs With  
Coke or Graphite Anodes  
The bq2400x measures battery temperature using an  
external thermistor. For safety reasons, the bq2400x  
inhibits charge until the battery temperature is within the  
user-defined thresholds. Alternatively, the user can  
monitor the input voltage to qualify charge. The  
bq2400x series then charge the battery in three phases:  
preconditioning, constant current, and constant  
voltage. If the battery voltage is below the internal  
low-voltage threshold, the bq2400x uses low-current  
precharge to condition the battery. A preconditioning  
timer is provided for additional safety. Following pre-  
conditioning, the bq2400x applies a constant-charge  
current to the battery. An external sense-resistor sets  
the magnitude of the current. The constant-current  
phase is maintained until the battery reaches the  
charge-regulation voltage. The bq2400x then  
transitions to the constant voltage phase. The user can  
configure the device for cells with either coke or  
graphite anodes. The accuracy of the voltage regulation  
is better than 1% over the operating junction  
temperature and supply voltage range.  
D
D
D
Up to 1.2-A Continuous Charge Current  
Safety-Charge Timer During Preconditioning  
and Fast Charge  
Integrated Cell Conditioning for Reviving  
Deeply Discharged Cells and Minimizing Heat  
Dissipation During Initial Stage of Charge  
D
D
Optional Temperature or Input-Power  
Monitoring Before and During Charge  
Various Charge-Status Output Options for  
Driving Single, Double, or Bicolor LEDs or  
Host-Processor Interface  
D
Charge Termination by Minimum Current and  
Time  
D
Low-Power Sleep Mode  
D
Packaging: 5 mm × 5 mm MLP or 20-Lead  
TSSOP PowerPAD  
APPLICATIONS  
Charge is terminated by maximum time or minimum  
taper current detection  
D
D
D
D
PDAs  
Internet Appliances  
MP3 Players  
Digital Cameras  
The bq2400x automatically restarts the charge if the  
battery voltage falls below an internal recharge  
threshold.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
ꢗꢓ ꢐ ꢘꢚ ꢎ ꢕꢈ ꢐꢉ ꢘ ꢒꢕꢒ ꢏꢛ ꢜꢝ ꢞ ꢟꢠ ꢡꢏꢝꢛ ꢏꢙ ꢢꢣ ꢞ ꢞ ꢤꢛꢡ ꢠꢙ ꢝꢜ ꢥꢣꢀ ꢦꢏꢢ ꢠꢡꢏ ꢝꢛ ꢧꢠ ꢡꢤꢨ ꢗꢞ ꢝꢧꢣ ꢢꢡꢙ  
ꢢ ꢝꢛ ꢜꢝꢞ ꢟ ꢡꢝ ꢙ ꢥꢤ ꢢ ꢏ ꢜꢏ ꢢ ꢠ ꢡꢏ ꢝꢛꢙ ꢥ ꢤꢞ ꢡꢩꢤ ꢡꢤ ꢞ ꢟꢙ ꢝꢜ ꢕꢤꢪ ꢠꢙ ꢈꢛꢙ ꢡꢞ ꢣꢟ ꢤꢛꢡ ꢙ ꢙꢡ ꢠꢛꢧ ꢠꢞ ꢧ ꢫ ꢠꢞ ꢞ ꢠ ꢛꢡꢬꢨ  
ꢗꢞ ꢝ ꢧꢣꢢ ꢡ ꢏꢝ ꢛ ꢥꢞ ꢝ ꢢ ꢤ ꢙ ꢙ ꢏꢛ ꢭ ꢧꢝ ꢤ ꢙ ꢛꢝꢡ ꢛꢤ ꢢꢤ ꢙꢙ ꢠꢞ ꢏꢦ ꢬ ꢏꢛꢢ ꢦꢣꢧ ꢤ ꢡꢤ ꢙꢡꢏ ꢛꢭ ꢝꢜ ꢠꢦ ꢦ ꢥꢠ ꢞ ꢠꢟ ꢤꢡꢤ ꢞ ꢙꢨ  
Copyright 2002 − 2004, Texas Instruments Incorporated  
ꢄꢄ  
ꢄꢄ  
ꢄꢄ  
www.ti.com  
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during  
storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
PACKAGE  
CHARGE STATUS  
CONFIGURATION  
T
J
20-LEAD HTTSOP PowerPAD20-LEAD 5 mm × 5 mm MLP  
(1)  
(2)  
(PWP) (RGW)  
bq24001PWP  
bq24002PWP  
bq24003PWP  
bq24001RGW  
bq24002RGW  
bq24003RGW  
Single LED  
2 LEDs  
−40°C to 125°C  
Single bicolor LED  
(1)  
(2)  
The PWP package is available taped and reeled. Add R suffix to device type (e.g. bq24001PWPR) to order. Quantities 2500 devices per reel.  
The RGW package is available taped and reeled. Add R suffix to device type (e.g. bq24001RGWR) to order. Quantities 3000 devices per reel.  
PACKAGE DISSIPATION RATINGS  
T
25°C  
DERATING FACTOR  
A
PACKAGE  
Θ
JA  
Θ
JC  
POWER RATING  
ABOVE T = 25°C  
A
(1)  
PWP  
30.88°C/W  
31.41°C/W  
1.19°C/W  
1.25°C/W  
3.238 W  
0.0324W/°C  
0.0318W/°C  
(2)  
RGW  
3.183 W  
(1)  
(2)  
This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (6.5 × 3.4 mm), internal 1 oz power and  
ground planes, 8 thermal via underneath the die connecting to ground plane.  
This data is based on using the JEDEC high-K board and topside traces, top and bottom thermal pad (3.25 × 3.25 mm), internal 1 oz power  
and ground planes, 9 thermal via underneath the die connecting to ground plane.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted  
(1)  
bq24001  
bq24002  
bq24003  
Supply voltage (Vcc with respect to GND)  
13.5 V  
13.5 V  
Input voltage (IN, ISNS, EN, APG/THERM/CR/STAT1/STAT2, VSENSE, TMR SEL, VSEL) (all with respect to GND)  
Output current (OUT pins)  
2 A  
Output sink/source current (STAT1 and STAT2)  
10 mA  
Operating free-air temperature range, T  
−40°C to 70°C  
−65°C to 150°C  
−40°C to 125°C  
300°C  
A
Storage temperature range, T  
stg  
Junction temperature range, T  
J
Lead temperature (Soldering, 10 sec)  
(1)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN MAX  
UNIT  
V
Supply voltage, V  
CC  
4.5  
4.5  
10  
10  
Input voltage, VIN  
V
Continuous output current  
Operating junction temperature range, T  
1.2  
125  
A
−40  
°C  
J
2
www.ti.com  
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating junction temperature supply and input voltages, and V (V ) V (IN) ( unless otherwise noted)  
I
CC  
I
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
mA  
µA  
V
V
current  
V
> V _UVLO,  
CC  
EN V  
IH(EN)  
1
CC  
CC  
current, standby mode  
EN V  
EN V  
1
CC  
IL(EN)  
IN current, standby mode  
10  
4
µA  
IL(EN)  
V
CC  
< V _UVLO,  
CC  
V
= 4.3 V, VSENSE = 4.3V  
= 4.3 V, VSENSE = 4.3 V  
2
2
Standby current (sum of currents into OUT  
and VSENSE pins)  
OUT  
µA  
EN <= Vil  
EN,  
V
OUT  
4
VOLTAGE REGULATION, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
0 < I 1.2 A  
MIN  
4.059  
4.158  
TYP  
MAX  
UNIT  
V
VSEL = V  
,
4.10 4.141  
4.20 4.242  
SS  
O
Output voltage  
VSEL = V  
,
0 < I 1.2 A  
V
CC  
O
1 mA I 1.2 A,  
V
= 5 V,  
O
I(IN)  
Load regulation  
Line regulation  
1
mV  
V
CC  
=5 V,  
T = 25°C  
J
V +V +V  
OUT DO ilim(MAX)  
< V  
< 10 V, T = 25°C  
0.01  
0.7  
%/V  
V
I(VCC)  
J
I
O
I
O
= 1.0 A,  
4.9 V <V  
< 10 V  
I(Vcc)  
<V  
Dropout voltage = VI(IN)-Vout  
= 1.2 A,  
V
+V +V  
< 10 V  
0.8  
V
OUT DO ilimMAX I(VCC)  
CURRENT REGULATION, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Current regulation threshold, V  
VSENSE < V  
O(VSEL-LOW/HIGH)  
0.095  
0.1 0.105  
V
I(limit)  
VSENSE pulsed above VVLOWV to I = 10% of  
regulated value  
O
Delay time  
1
ms  
ms  
(1)  
I
R
increasing from 10% to 90% of regulated value.  
(1)  
O
SNS  
Rise time  
0.1  
1
0.2 Ω,  
(1)  
Specified by design, not production tested.  
CURRENT SENSE RESISTOR, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
100 mA Ilim 1.2 A  
MIN  
TYP  
MAX  
UNIT  
External current sense resistor range (R  
)
0.083  
1
SNS  
PRECHARGE CURRENT REGULATION, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Precharge current regulation  
V
<V  
0.083 R 1.0 Ω  
40  
60  
80  
mA  
SENSE LOWV,  
SNS  
V
UVLO COMPARATOR, 0°C T 125°C  
J
CC  
PARAMETER  
TEST CONDITIONS  
TEST CONDITIONS  
TEST CONDITIONS  
MIN  
4.35  
4.25  
50  
TYP  
4.43  
4.33  
MAX  
4.50  
4.40  
UNIT  
V
Start threshold  
Stop threshold  
Hysteresis  
V
mV  
APG/THERM COMPARATOR, 0°C T 125°C  
J
PARAMETER  
Upper trip threshold  
Lower trip threshold  
Input bias current  
MIN  
TYP  
MAX  
UNIT  
V
1.480 1.498 1.515  
0.545 0.558 0.570  
1
V
µA  
LOWV COMPARATOR, 0°C T 125°C  
J
PARAMETER  
Start threshold  
MIN  
2.80  
3.00  
100  
TYP  
2.90  
3.10  
MAX  
3.00  
3.20  
UNIT  
V
Stop threshold  
V
Hysteresis  
mV  
3
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS CONTINUED  
over recommended operating junction temperature supply and input voltages, and V (V ) V (IN) ( unless otherwise noted)  
I
CC  
I
HIGHV (RECHARGE) COMPARATOR, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Start threshold  
3.80  
3.90  
4.00  
V
OVERV COMPARATOR, 0°C T 125°C  
J
PARAMETER  
Start threshold  
TEST CONDITIONS  
MIN  
4.35  
4.25  
50  
TYP  
4.45  
4.30  
MAX  
4.55  
4.35  
UNIT  
V
Stop threshold  
V
Hysteresis  
mV  
TAPERDET COMPARATOR, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Trip threshold  
12  
18.5  
25  
mV  
EN LOGIC INPUT, 0°C T 125°C  
J
PARAMETER  
High-level input voltage  
MIN  
TYP  
TYP  
MAX  
UNIT  
V
2.25  
Low-level input voltage  
0.8  
V
Input pulldown resistance  
100  
200  
kΩ  
VSEL LOGIC INPUT, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
V
High-level input voltage  
2.25  
Low-level input voltage  
0.8  
V
Input pulldown resistance  
100  
200  
kΩ  
TMR SEL INPUT 0°C T 125°C  
J
PARAMETER  
High-level input voltage  
Low-level input voltage  
Input bias current  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
2.7  
0.6  
15  
V
V
5V  
µA  
I(TMR SEL)  
STAT1, STAT2 (bq24001, bq24003), 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.5  
UNIT  
V
Output (low) saturation voltage  
Output (low) saturation voltage  
Output (high) saturation voltage  
Output (high) saturation voltage  
Output turn on/off time  
I
O
I
O
I
O
I
O
I
O
= 10 mA  
= 4 mA  
0.6  
V
= −10 mA  
= −4 mA  
V
CC  
V
CC  
−1.5  
−0.5  
V
V
(1)  
=
10 mA, C = 100 p  
100  
µs  
(1) Assured by design, not production tested.  
POWER-ON RESET (POR), 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
1.2  
25  
TYP  
MAX  
3
UNIT  
ms  
POR delay  
See Note 1  
See Note 1  
POR falling-edge deglitch  
75  
µs  
(1) Assured by design, not production tested.  
4
www.ti.com  
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
ELECTRICAL CHARACTERISTICS CONTINUED  
over recommended operating junction temperature supply and input voltages, and V (V ) V (IN) ( unless otherwise noted)  
I
CC  
I
APG/THERM DELAY, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
APG/THERM falling-edge deglitch  
See Note 1  
25  
75  
µs  
(1) Assured by design, not production tested.  
TIMERS, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
MIN  
−15%  
−20%  
TYP  
MAX  
15%  
20%  
UNIT  
T
A
= 25°C  
User-selectable timer accuracy  
Precharge and taper timer  
22.5  
minute  
THERMAL SHUTDOWN, 0°C T 125°C  
J
PARAMETER  
Thermal trip  
TEST CONDITIONS  
MIN  
TYP  
165  
10  
MAX  
UNIT  
°C  
See Note 1  
See Note 1  
Thermal hysteresis  
°C  
(1) Assured by design, not production tested.  
CR PIN, 0°C T 125°C  
J
PARAMETER  
TEST CONDITIONS  
< 100 µA  
MIN  
TYP  
MAX  
UNIT  
Output voltage  
0 < I  
O(CR)  
2,816  
2.85  
2.88  
V
PIN ASSIGNMENTS  
bq24002, bq24003  
PWP PACKAGE  
(TOP VIEW)  
bq24001  
PWP PACKAGE  
(TOP VIEW)  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
N/C  
IN  
IN  
N/C  
OUT  
OUT  
VSENSE  
AGND  
STAT2  
STAT1  
TMR SEL  
CR  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
N/C  
IN  
IN  
N/C  
OUT  
OUT  
VSENSE  
AGND  
N/C  
STAT1  
TMR SEL  
CR  
2
3
4
V
CC  
V
CC  
5
ISNS  
N/C  
APG/THERM  
EN  
ISNS  
6
N/C  
APG/THERM  
EN  
7
8
9
VSEL  
GND/HEATSINK  
VSEL  
GND/HEATSINK  
10  
N/C  
10  
N/C  
N/C − Do not connect  
5
ꢄꢄ  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
bq24001  
RGW PACKAGE  
(TOP VIEW)  
bq24002, bq24003  
RGW PACKAGE  
(TOP VIEW)  
EN 6  
VSEL 7  
GND 8  
CR 9  
20 N/C  
EN 6  
VSEL 7  
GND 8  
CR 9  
20 N/C  
19 N/C  
18 N/C  
17 OUT  
19 N/C  
18 N/C  
17 OUT  
N/C  
OUT  
N/C  
OUT  
16  
10  
16  
10  
N/C − Do Not Connect  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
AGND  
NO.  
NO.  
14  
5
16  
7
Ground pin; connect close to the negative battery terminal.  
Adapter power good input/thermistor sense input  
Internal regulator bypass capacitor  
APG/THERM  
I
I
I
CR  
EN  
12  
8
9
6
Charge-enableinput. Active-high enable input with internal pull down. Low-current stand-by mode  
active when EN is low.  
GND/HEATSINK  
10  
2, 3  
5
8
1, 2  
4
Ground pin; connect to PowerPAD heat-sink layout pattern.  
Input voltage. This input provides the charging voltage for the battery.  
Current sense input  
IN  
I
I
ISNS  
N/C  
1, 6, 11, 10, 13,  
No connect. These pins must be left floating. Pin 15 is N/C on bq24001PWP only. Pin 13 is N/C on  
bq24001RGWonly.  
15, 20  
18, 19  
14  
18−20  
16, 17  
12  
OUT  
O
O
O
I
Charge current output  
STAT1  
STAT2  
TMR SEL  
Status display output 1  
15  
13  
Status display output 2 (for bq24002 and bq24003 only)  
Charge timer selection input  
13  
11  
V
CC  
4
3
I
Supply voltage  
VSEL  
9
7
I
4.1 V or 4.2 V charge regulation selection input  
Battery voltage sense input  
VSENSE  
17  
15  
I
6
www.ti.com  
SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
FUNCTIONAL BLOCK DIAGRAM  
OUT  
IN  
+
VSENSE  
TaperDet  
0.2*V  
ilim  
+
+
ISNS  
V
ilim  
V
CC  
V
ref  
AGND  
+
ChargeOK  
LowV  
UVS  
Precharge  
GND/  
HEATSINK  
V
uvlo  
+
OverV  
HighV  
LowV  
ChipEN  
EN  
+
H: V  
L: V  
= 4.2 V/Cell  
= 4.1 V/Cell  
Bias and  
Ref  
Generator  
reg  
reg  
VSEL  
R9  
R8  
+
Power On  
Delay  
V
V
uvlo  
ref  
V
ref  
+
APG/  
THERM  
CLRFLT  
+
PWRDWN  
Thermal  
Shutdown  
UVS  
V
V
CC  
TaperDet  
STAT1  
STAT2  
PWRDWN  
PWRDWN  
OSC  
CC  
Charge Control, Charge Timer  
and  
Display Logic  
TMR SEL  
REG  
CR  
Two Open  
Drain  
Outputs  
for  
ChargeOK  
bq24002  
7
ꢄꢄ  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
TYPICAL CHARACTERISTICS  
OUTPUT VOLTAGE  
vs  
OUTPUT VOLTAGE  
vs  
OUTPUT CURRENT  
JUNCTION TEMPERATURE  
4.24  
4.22  
4.20  
4.18  
4.16  
4.14  
4.12  
4.10  
4.08  
4.06  
4.24  
4.22  
4.20  
4.18  
4.16  
4.14  
4.12  
4.10  
4.08  
4.06  
V
IN  
= 5 V  
V
T
= 5 V  
= 25°C  
IN  
A
V
SEL  
= V  
CC  
V
= V  
CC  
SEL  
V
SEL  
= V  
SS  
V
= V  
SS  
SEL  
−50  
0
50  
100  
150  
0
200  
400  
600  
800  
1000  
1200  
T
J
− Junction Temperature − °C  
I
O
− Output Current − mA  
Figure 1  
Figure 2  
OUTPUT VOLTAGE  
vs  
CURRENT SENSE VOLTAGE  
vs  
INPUT VOLTAGE  
INPUT VOLTAGE  
4.24  
4.22  
4.20  
4.18  
4.16  
4.14  
4.12  
4.10  
4.08  
4.06  
103  
102  
101  
100  
99  
I
T
= 100 mA  
= 25°C  
I
T
= 100 mA  
= 25°C  
O
A
O
A
V
= V  
CC  
SEL  
V
= V  
SS  
SEL  
98  
97  
5
6
7
8
9
10  
5
6
7
8
9
10  
V − Input Voltage − V  
I
V − Input Voltage − V  
I
Figure 3  
Figure 4  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
TYPICAL CHARACTERISTICS  
CURRENT SENSE VOLTAGE  
vs  
QUIESCENT CURRENT  
vs  
JUNCTION TEMPERATURE  
INPUT VOLTAGE  
103  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
I
T
= 100 mA  
= 25°C  
T
A
= 25°C  
O
A
102  
101  
100  
99  
V
V
= 10 V  
CC  
= 5 V  
CC  
98  
−50  
0
50  
100  
150  
5
6
7
8
9
10  
T
J
− Junction Temperature − °C  
V − Input Voltage − V  
I
Figure 5  
Figure 6  
QUIESCENT CURRENT  
(POWER DOWN)  
vs  
DROPOUT VOLTAGE  
vs  
INPUT VOLTAGE  
INPUT VOLTAGE  
600  
30  
25  
20  
15  
10  
5
T
A
= 25°C  
T
A
= 25°C  
500  
400  
300  
200  
100  
0
1200 mA  
800 mA  
400 mA  
100 mA  
0
4.5  
5.5  
6.5  
7.5  
8.5  
9.5  
5
6
7
8
9
10  
V − Input Voltage − V  
I
V − Input Voltage − V  
I
Figure 7  
Figure 8  
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TYPICAL CHARACTERISTICS  
DROPOUT VOLTAGE  
vs  
DROPOUT VOLTAGE  
vs  
OUTPUT CURRENT  
JUNCTION TEMPERATURE  
600  
500  
400  
300  
200  
100  
0
800  
700  
600  
500  
400  
300  
200  
100  
I
O
= 1.2 A  
T
A
= 25°C  
V
= 5 V  
IN  
V
= 5 V  
CC  
V
= 10 V  
IN  
V
CC  
= 10 V  
0
200  
400  
600  
800  
1000  
1200  
−50  
0
50  
100  
150  
I
O
− Output Current − mA  
T
J
− Junction Temperature − °C  
Figure 9  
Figure 10  
REVERSE CURRENT  
vs  
REVERSE CURRENT LEAKAGE  
vs  
JUNCTION TEMPERATURE  
VOLTAGE ON OUT PIN  
6
5
4
3
2
1
0
4.0  
V
OUT  
= 4.3 V  
T
A
= 25°C  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
−50  
0
50  
100  
150  
5
6
7
8
9
10  
T
J
− Junction Temperature − °C  
V
O
− Voltage on Out Pin − V  
Figure 11  
Figure 12  
10  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
APPLICATION INFORMATION  
U1  
V
CC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
R1  
0.1 Ω  
N/C  
IN  
N/C  
OUT  
OUT  
DC+  
DC−  
PACK+  
PACK−  
TEMP  
C1  
10 µF  
V
CC  
3
+
IN  
+
4
V
CC  
VSENSE  
AGND  
5
ISNS  
N/C  
6
STAT2  
C4  
1 µF  
C2  
0.1 µF  
7
APG/THM STAT1  
8
EN  
TMR SEL  
CR  
9
Battery  
Pack  
VSEL  
GND  
V
CC  
C3  
0.22 µF  
10  
N/C  
R4  
bq24002PWP  
500 Ω  
D1  
D2  
R5  
500 Ω  
R2  
18.7 kΩ  
R3  
95.3 kΩ  
Figure 13. Li-Ion/Li-Pol Charger  
D
D
If the TMR SEL pin is left floating (3 HR time), a 10-pF capacitor should be installed between TMR SEL and CR.  
If a micro process is monitoring the STAT pins, it may be necessary to add some hysteresis into the feedback  
to prevent the STAT pins from cycling while crossing the taper detect threshold (usually less than one half  
second). See SLUU083 EVM or SLUU113 EVM for additional resistors used for the STAT pins.  
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APPLICATION INFORMATION  
FUNCTIONAL DESCRIPTION  
The bq2400x supports a precision current- and voltage-regulated Li-Ion charging system suitable for cells with either coke  
or graphite anodes. See Figure 14 for a typical charge profile and Figure 15 for an operational flowchart.  
Current Regulation  
Phase  
Voltage Regulation and  
Charge TerminationPhase  
Preconditioning  
Phase  
Regulation Voltage  
(V  
)
OUT  
Regulation Current  
(I  
)
lim  
Charge Voltage  
Minimum Charge  
Voltage (LowV)  
Preconditioning  
Current (I  
PRECHG  
)
Charge Current  
Taper Detect  
22.5 Minutes  
Charge Timer (3, 4.5 or 6 Hours)  
22.5 Minutes  
Figure 14. Typical Charge Profile  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
POR  
Regulate  
(PRECHG)  
I
Yes  
Reset and Start  
22.5 min Timer  
V
< V ?  
(LOWV)  
I(VSENSE)  
Indicate Pre−  
Charge  
No  
Reset All Timers,  
Start Charge Timer  
(TMR SEL input )  
Yes  
V
> V ?  
(OVERV)  
I(VSENSE)  
No  
Regulate Current  
or Voltage  
Indicate Charge  
No  
V
< V ?  
(LOWV)  
I(VSENSE)  
Yes  
Yes  
V
> V ?  
(OVERV)  
I(VSENSE)  
No  
22.5min Timer  
Expired?  
No  
Yes  
Yes  
Charge timer  
Expired?  
No  
Fault Condition  
Indicate Fault  
Yes  
V
< V ?  
(LOWV)  
I(VSENSE)  
No  
POR?  
or  
APG/THERM toggle?  
No  
Start 22.5 minute  
Timer  
or  
Yes  
Taper  
Detected?  
EN toggle?  
Indicate DONE  
Yes  
No  
22.5min Timer  
Expired?  
Yes  
Turn Off Charge  
Indicate DONE  
V
< V  
?
(HIGHV)  
I(VSENSE)  
or  
No  
POR?  
or  
APG/THERM Toggle?  
or  
EN Toggle?  
Yes  
Figure 15. Operational Flow Chart  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
either the adapter power or the battery temperature using  
a thermistor. The bq2400x suspends charge if this input is  
outside the limits set by the user. Please refer to the  
APG/THERM input section for additional details.  
Charge Qualification and Preconditioning  
The bq2400x starts a charge cycle when power is applied  
while a battery is present. Charge qualification is based on  
battery voltage and the APG/THERM input.  
APG/THERM Input  
The bq400x continuously monitors temperature or system  
input voltage by measuring the voltage between the  
APG/THERM (adapter power good/thermistor) and GND.  
For temperature, a negative- or a positive- temperature  
coefficient thermistor (NTC, PTC) and an external voltage  
divider typically develop this voltage (see Figure 16). The  
As shown in the block diagram, the internal LowV  
comparator output prevents fast-charging a deeply  
depleted battery. When set, charging current is provided  
by a dedicated precharge current source. The precharge  
timer limits the precharge duration. The precharge current  
also minimizes heat dissipation in the pass element during  
the initial stage of charge.  
bq2400x compares this voltage against its internal V  
TP1  
and V  
thresholds to determine if charging is allowed.  
TP2  
The APG/THERM input can also be configured to monitor  
(See Figure 17.)  
U1  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
N/C  
IN  
N/C  
OUT  
PACK+  
PACK−  
TEMP  
3
IN  
OUT  
+
4
V
CC  
VSENSE  
AGND  
STAT2  
5
ISNS  
N/C  
6
NTC Thermistor  
Battery Pack  
7
APG/THM STAT1  
8
EN  
TMR SEL  
CR  
9
VSEL  
GND  
C3  
0.22 µF  
10  
N/C  
bq24002PWP  
RT1  
RT2  
Figure 16. Temperature Sensing Circuit  
14  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
If the charger designs incorporate a thermistor, the resistor  
divider RT1 and RT2 is calculated by using the following  
two equations.  
Where:  
VB = VCR (bias voltage)  
First, calculate RT2.  
RH = Resistance of the thermistor at the desired hot trip  
threshold  
1
1
ƪ ƫ  
V R R  
*
V
V
B
H
C
C
H
RC = Resistance of the thermistor at the desired cold trip  
threshold  
RT2 +  
V
V
V
B
H
B
ǒ
* 1Ǔ* R  
ǒ Ǔ  
R
* 1  
V
C
H
C
VH = VP2 or the lower APG trip threshold  
VC = VP2 or the upper APG trip threshold  
RT1 = Top resistor in the divider string  
RT2 = Bottom resistor in the divider string  
then use the resistor value to find RT1.  
V
B
* 1  
V
C
RT1 +  
1
1
)
RT2  
R
C
U1  
V
CC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
N/C  
IN  
N/C  
OUT  
DC+  
3
Vcc  
IN  
OUT  
4
V
CC  
VSENSE  
AGND  
STAT2  
Temp Fault  
5
ISNS  
N/C  
6
R1  
R2  
VTP1  
7
APG/THM STAT1  
Normal Temp Range  
Temp Fault  
8
VTP2  
EN  
TMR SEL  
CR  
9
VSEL  
GND  
10  
DC−  
N/C  
GND  
bq24002PWP  
Figure 17. Temperature Threshold  
Figure 18. APG Sensing Circuit  
Values of resistors R1 and R2 can be calculated using the following equation:  
R2  
V
+ V  
CC  
APG  
(R1 ) R2)  
where V  
is the voltage at the APG/THM pin.  
APG  
Current Regulation  
The bq2400x provides current regulation while the battery-pack voltage is less than the regulation voltage. The current  
regulation loop effectively amplifies the error between a reference signal, Vilim, and the drop across the external sense  
resistor, R  
.
SNS  
15  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
U1  
V
CC  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
N/C  
IN  
N/C  
OUT  
OUT  
R
SNS  
DC+  
DC−  
C1  
10 µF  
V
CC  
3
+
IN  
4
V
CC  
VSENSE  
AGND  
5
ISNS  
N/C  
6
STAT2  
C2  
0.1 µF  
7
APG/THM STAT1  
8
EN  
TMR SEL  
CR  
9
VSEL  
GND  
10  
N/C  
bq24002PWP  
Figure 19. Current Sensing Circuit  
Charge current feedback, applied through pin ISNS,  
maintains regulation around a threshold of Vilim. The  
following formula calculates the value of the sense  
resistor:  
that in the case of a fault condition, such as an out-of-range  
signal on the APG/THERM input or a thermal shutdown,  
the bq2400x suspends the timer.  
TMRSEL STATE  
(1)  
CHARGE TIME  
3 hours  
Vilim  
Floating  
R
+
SNS  
I
REG  
Low  
6 hours  
High  
4.5 hours  
where I  
is the desired charging current.  
REG  
(1)  
To improve noise immunity, it is recommended that a minimum of  
10 pF capacitor be tied to Vss on a floating pin.  
Voltage Monitoring and Regulation  
Minimum Current: The bq2400x monitors the charging  
current during the voltage regulation phase. The bq2400x  
initiates a 22-minute timer once the current falls below the  
taperdet trip threshold. Fast charge is terminated once the  
22-minute timer expires.  
Voltage regulation feedback is through pin VSENSE. This  
input is tied directly to the positive side of the battery pack.  
The bq2400x supports cells with either coke (4.1 V) or  
graphite (4.2 V) anode. Pin VSEL selects the charge  
regulation voltage.  
Charge Status Display  
VSEL State  
(see Note)  
CHARGE REGULATION  
VOLTAGE  
The three available options allow the user to configure the  
charge status display for single LED (bq24001), two  
individual LEDs (bq24002) or a bicolor LED (bq24003).  
The output stage is totem pole for the bq24001 and  
bq24003 and open-drain for the bq24002. The following  
tables summarize the operation of the three options:  
Low  
4.1 V  
4.2 V  
High  
NOTE: VSEL should not be left floating.  
Table 1. bq24001 (Single LED)  
Charge Termination  
CHARGE STATE  
Precharge  
STAT1  
ON (LOW)  
The bq2400x continues with the charge cycle until  
termination by one of the two possible termination  
conditions:  
Fast charge  
ON (LOW)  
FAULT  
Flashing (1 Hz, 50% duty cycle)  
OFF (HIGH)  
Maximum Charge Time: The bq2400x sets the maximum  
charge time through pin TMRSEL. The TMR SEL pin  
allows the user to select between three different total  
charge-time timers (3, 4, 5, or 6 hours). The charge timer  
is initiated after the preconditioning phase of the charge  
and is reset at the beginning of a new charge cycle. Note  
Done (>90%)  
Sleep-mode  
OFF (HIGH)  
APG/Therm invalid  
Thermal shutdown  
Battery absent  
OFF (HIGH)  
OFF (HIGH)  
OFF (HIGH)  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
Table 2. bq24002 (2 Individual LEDs)  
Table 3. bq24003 (Single Bicolor LED)  
LED2  
(GREEN)  
APPARENT  
COLOR  
CHARGE STATE LED1 (RED)  
STAT2  
(GREEN)  
CHARGE STATE  
STAT1 (RED)  
Precharge  
Fast charge  
FAULT  
ON (LOW)  
ON (LOW)  
ON (LOW)  
OFF (HIGH)  
OFF (HIGH)  
OFF (HIGH)  
OFF (HIGH)  
ON (LOW)  
ON (LOW)  
OFF (HIGH)  
RED  
RED  
Precharge  
ON (LOW)  
ON (LOW)  
OFF  
OFF  
Fast charge  
YELLOW  
GREEN  
OFF  
Flashing (1 Hz,  
50% duty cycle)  
FAULT  
OFF  
Done (>90%)  
Sleep-mode  
Done (>90%)  
OFF  
OFF  
OFF  
OFF  
OFF  
ON (LOW)  
OFF  
APG/Therm  
invalid  
Sleep-mode  
OFF (HIGH)  
OFF (HIGH)  
OFF (HIGH)  
OFF (HIGH)  
OFF  
OFF  
APG/Therm invalid  
Thermal shutdown  
Battery absent  
OFF  
Thermal  
shutdown  
OFF  
(1)  
OFF  
(1)  
OFF (HIGH) OFF (HIGH)  
(1)  
OFF  
Battery absent  
(1) If thermistor is used, then the Green LED is off.  
(1) If thermistor is used, then the Green LED is off.  
Thermal Shutdown  
The bq2400x monitors the junction temperature T of the DIE and suspends charging if T exceeds 165°C. Charging  
J
J
resumes when T falls below 155°C.  
J
DETAILED DESCRIPTION  
POWER FET  
VOLTAGE SENSE  
The integrated transistor is a P-channel MOSFET. The  
power FET features a reverse-blocking Schottky diode,  
which prevents current flow from OUT to IN.  
To achieve maximum voltage regulation accuracy, the  
bq2400x uses the feedback on the VSENSE pin.  
Externally, this pin should be connected as close to the  
battery cell terminals as possible. For additional safety, a  
10kinternal pullup resistor is connected between the  
VSENSE and OUT pins.  
An internal thermal-sense circuit shuts off the power FET  
when the junction temperature rises to approximately  
165°C. Hysteresis is built into the thermal sense circuit.  
After the device has cooled approximately 10°C, the  
power FET turns back on. The power FET continues to  
cycle off and on until the fault is removed.  
ENABLE (EN)  
The logic EN input is used to enable or disable the IC. A  
high-level signal on this pin enables the bq2400x. A  
low-level signal disables the IC and places the device in a  
low-power standby mode.  
CURRENT SENSE  
The bq2400x regulates current by sensing, on the ISNS  
pin, the voltage drop developed across an external sense  
resistor. The sense resistor must be placed between the  
supply voltage (Vcc) and the input of the IC (IN pins).  
17  
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THERMAL INFORMATION  
THERMALLY ENHANCED TSSOP-20  
DIE  
The thermally enhanced PWP package is based on the  
20-pin TSSOP, but includes a thermal pad (see  
Figure 20) to provide an effective thermal contact between  
the IC and the PWB.  
Side View (a)  
DIE  
Traditionally, surface mount and power have been  
mutually exclusive terms. A variety of scaled-down  
TO220-type packages have leads formed as gull wings to  
make them applicable for surface-mount applications.  
These packages, however, suffer from several  
shortcomings: they do not address the very low profile  
requirements (<2 mm) of many of today’s advanced  
systems, and they do not offer a pin-count high enough to  
accommodate increasing integration. On the other hand,  
traditional low-power surface-mount packages require  
power-dissipation derating that severely limits the usable  
range of many high-performance analog circuits.  
End View (b)  
Thermal  
Pad  
The PWP package (thermally enhanced TSSOP)  
combines fine-pitch surface-mount technology with  
thermal performance comparable to much larger power  
packages.  
Bottom View (c)  
The PWP package is designed to optimize the heat  
transfer to the PWB. Because of the very small size and  
limited mass of a TSSOP package, thermal enhancement  
is achieved by improving the thermal conduction paths that  
remove heat from the component. The thermal pad is  
formed using a lead-frame design (patent pending) and  
manufacturing technique to provide the user with direct  
connection to the heat-generating IC. When this pad is  
soldered or otherwise coupled to an external heat  
dissipator, high power dissipation in the ultrathin,  
fine-pitch, surface-mount package can be reliably  
achieved.  
Figure 20. Views of Thermally Enhanced  
PWP Package  
Because the conduction path has been enhanced,  
power-dissipation capability is determined by the thermal  
considerations in the PWB design. For example, simply  
adding a localized copper plane (heat-sink surface), which  
is coupled to the thermal pad, enables the PWP package  
to dissipate 2.5 W in free air. (Reference Figure 22(a), 8  
2
cm of copper heat sink and natural convection.)  
Increasing the heat-sink size increases the power  
dissipation range for the component. The power  
dissipation limit can be further improved by adding airflow  
to a PWB/IC assembly (see Figure 22(b) and 22(c)). The  
2
line drawn at 0.3 cm in Figures 21 and 22 indicates  
performance at the minimum recommended heat-sink  
size.  
18  
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SLUS462E − SEPTEMBER 2000 − REVISED NOVEMBER 2004  
THERMAL INFORMATION  
THERMAL RESISTANCE  
vs  
COPPER HEAT-SINK AREA  
150  
125  
100  
Natural Convection  
50 ft/min  
100 ft/min  
150 ft/min  
200 ft/min  
75  
50  
25  
250 ft/min  
300 ft/min  
0 0.3  
1
2
3
4
5
6
7
8
2
Copper Heat-Sink Area − cm  
Figure 21  
19  
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THERMAL INFORMATION  
3.5  
3.5  
T
A
= 25°C  
T
A
= 55°C  
300 ft/min  
3
2.5  
2
3
2.5  
2
150 ft/min  
300 ft/min  
150 ft/min  
Natural Convection  
1.5  
1.5  
Natural Convection  
1
0.5  
0
1
0.5  
0
0
2
4
6
8
0
2
4
6
8
0.3  
0.3  
2
2
Copper Heat-Sink Size − cm  
Copper Heat-Sink Size − cm  
(a)  
(b)  
3.5  
T
A
= 105°C  
3
2.5  
2
1.5  
1
150 ft/min  
300 ft/min  
Natural Convection  
0.5  
0
0
0.3  
2
4
6
8
2
Copper Heat-Sink Size − cm  
(c)  
Figure 22. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C  
20  
PACKAGE OPTION ADDENDUM  
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8-Dec-2009  
PACKAGING INFORMATION  
Orderable Device  
BQ24001PWP  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
HTSSOP  
PWP  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
BQ24001PWPG4  
BQ24001PWPR  
BQ24001PWPRG4  
BQ24001RGWR  
BQ24001RGWRG4  
BQ24002PWP  
HTSSOP  
HTSSOP  
HTSSOP  
VQFN  
PWP  
PWP  
PWP  
RGW  
RGW  
PWP  
PWP  
PWP  
PWP  
RGW  
RGW  
PWP  
PWP  
PWP  
PWP  
RGW  
RGW  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
VQFN  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
BQ24002PWPG4  
BQ24002PWPR  
BQ24002PWPRG4  
BQ24002RGWR  
BQ24002RGWRG4  
BQ24003PWP  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
HTSSOP  
HTSSOP  
HTSSOP  
HTSSOP  
VQFN  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
BQ24003PWPG4  
BQ24003PWPR  
BQ24003PWPRG4  
BQ24003RGWR  
BQ24003RGWRG4  
70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
VQFN  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Dec-2009  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
BQ24001PWPR  
BQ24001RGWR  
BQ24002PWPR  
BQ24002RGWR  
BQ24003PWPR  
BQ24003RGWR  
HTSSOP PWP  
VQFN RGW  
HTSSOP PWP  
VQFN RGW  
HTSSOP PWP  
VQFN RGW  
20  
20  
20  
20  
20  
20  
2000  
3000  
2000  
3000  
2000  
3000  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
12.4  
16.4  
12.4  
16.4  
12.4  
6.95  
5.3  
7.1  
5.3  
7.1  
5.3  
7.1  
5.3  
1.6  
1.5  
1.6  
1.5  
1.6  
1.5  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
16.0  
12.0  
16.0  
12.0  
16.0  
12.0  
Q1  
Q2  
Q1  
Q2  
Q1  
Q2  
6.95  
5.3  
6.95  
5.3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
BQ24001PWPR  
BQ24001RGWR  
BQ24002PWPR  
BQ24002RGWR  
BQ24003PWPR  
BQ24003RGWR  
HTSSOP  
VQFN  
PWP  
RGW  
PWP  
RGW  
PWP  
RGW  
20  
20  
20  
20  
20  
20  
2000  
3000  
2000  
3000  
2000  
3000  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
35.0  
38.0  
35.0  
38.0  
35.0  
HTSSOP  
VQFN  
HTSSOP  
VQFN  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All  
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time  
of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
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documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
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Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
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Copyright © 2012, Texas Instruments Incorporated  

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