BQ24140YFFR_技术文档

bq24140

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SLUSAO5 –OCTOBER 2011

Fully Integrated Dual-Input Switch-Mode One-Cell Li-Ion Charger with Full USB

Compliance and USB-OTG Support

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1

FEATURES

•

Programmable Charge Parameters Through

I²C Interface (up to 3.4 Mbps):

•

High-Efficiency Mini-USB/AC Battery Charger

for Single-Cell Li-Ion and Li-Polymer Battery

Packs

–

Input Current

Fast-Charge/Termination Current

Charge Voltage (3.5-4.44V)

Safety Timer with Reset Control

Termination Enable

•

Charge Battery and Provide USB-OTG Support

at the Same Time

High-Accuracy Voltage and Current Regulation

–

Input Current Regulation Accuracy: ±5%

(100mA, 500mA)

•

Synchronous Fixed-Frequency PWM

Controller Operating at 3 MHz With 0% to

99.5% Duty Cycle

Charge Voltage Regulation Accuracy:

±0.5% (25°C), ±1% (0-125°C)

Charge Current Regulation Accuracy: ±5%

•

Automatic High Impedance Mode for Low

Power Consumption

•

Boost Mode Operation for USB OTG:

–

Input Voltage Range (from Battery): 2.3V to

4.5V

Robust Protection

–

Reverse Leakage Protection Prevents

Battery Drainage

–

Output for VBUS: 5.05V/500 mA

Input Voltage Based Dynamic Power

Management Provides Protection Against

Current Limited Adapters

–

Thermal Regulation and Protection

Input/Output Over Voltage Protection

•

Status Output for Charging and Faults

USB Friendly Boot-Up Sequence

•

Bad Adaptor Detection and Rejection

Safety Limit Register for Added Security by

Limiting Maximum Charge Voltage and

Maximum Charge Current

2.35 × 2.65 mm 30-pin WCSP Package

APPLICATIONS

•

20-V Absolute Maximum Input Voltage Rating

9.0-V Maximum Operating Input Voltage

Charge Faster than Linear Chargers

•

Mobile Phones and Smart Phones

MP3 Players

Handheld Devices

Built-in Input Current Sensing and Limiting

Integrated Power FETs for up to 1.5-A Charge

Rate

4.7 mF

PMID1

PMID2

1 mH

68 mW

AC Adapter or

SW1

VIN

10 µF

47 µF

Wireless Power

100 nF

1 mF

PACK+

PACK-

BOOT1

SW2

+

1 mH

VBUS

USB Adapter

4.7 mF

100 nF

BOOT2

10 kW

CSIN

VBAT

SCL

SDA

STAT

OTG

SLRST

DIS

10 kW

VREF

GND

1 mF

VREG

LED

HOST

0.1 mF

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24140

SLUSAO5 –OCTOBER 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The bq24140 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for

single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters

can be programmed through an I²C interface. The IC integrates two synchronous PWM chargers, power

MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a

small WCSP package.

The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input

current is automatically limited to the value set by the host. Charge is terminated based on user-selectable

minimum current level. A safety timer with reset control provides a safety backup for I²C interface. During normal

operation, the IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold

and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge

status can be reported to the host using the I²C interface. During the charging process, the IC monitors its

junction temperature (T_J) and reduces the charge current once T_Jincreases to 125°C typical. To support USB

OTG device, the IC can provide VBUS (5.05V typical) by boosting the battery voltage. The IC is available in

30-pin WCSP package.

DEVICE INFORMATION

PIN OUT (TOP VIEW)

1

2

3

4

5

A

B

C

D

E

F

BOOT

VREF

VREG

SDA

BOOT1

VIN

PMID2

SW2

GND

LED

VIN

PMID2

SW2

SCL

SLRST

DIS

VBUS

PMID1

SW1

VBUS

PMID1

SW1

GND

OTG

GND

CSIN

GND

VBAT

STAT

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

NO.

Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 100nF ceramic capacitor (voltage

rating above 10V) from BOOT pin to SW2 pin.

BOOT

A1

O

VREF

VREG

SDA

A2

A3

A4

O

Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND.

Voltage regulator. 2.5V with 10mA current capability. Connect a 0.1μF ceramic capacitor to ground

I/O I2C interface data. Connect a 10-kΩ pull-up resistor to 1.8V rail.

Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 100nF ceramic capacitor (voltage

rating above 10V) from BOOT1 pin to SW1 pin.

BOOT1

A5

O

VIN

B1 – B2

I

Charger input voltage. Bypass it with a 1μF ceramic capacitor from VIN to GND.

I²C interface clock. Connect a 10-kΩ pull-up resistor to 1.8V rail.

SCL

B3

Charger input voltage. Bypass it with a 4.7μF ceramic capacitor from VBUS to GND. This pin also provides the

output of the boost converter when in Boost Mode.

VBUS

B4 – B5 I/O

Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of

3.3μF capacitor from PMID2 to GND.

PMID2

C1 – C2

O

2

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PIN FUNCTIONS (continued)

I/O

DESCRIPTION

NAME

NO.

Safety limit register control. When SLRST = 0, all the safety limit values are reset to default values, regardless

of the write actions to the safety limits registers. When SLRST = 1, the host can program the safety limits

register until any write action to other registers locks the programmed safety limits.

SLRST

C3

I

Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of

3.3μF capacitor from PMID1 to GND.

PMID1

SW2

C4 – C5

D1 – D2

O

Internal switch to output inductor connection.

Charge disable control pin. DIS=0, charge is enabled. DIS=1, charge is disabled. VIN and VBUS pins are high

impedance to PGND. In 15min mode, DIS=1 will reset the 15min timer; while in 32s mode, DIS=1 will NOT

reset the 32-second timer.

DIS

D3

I

SW1

GND

LED

D4 – D5

E1 – E5

F1

O

Internal switch to output inductor connection.

Ground pins.

O

I

High side LED driver. Current, on and off times can be programmed through I2C to select different modes.

Boost mode enable control and VBUS input current limiting selection pin. When OTG is in active status per the

control register, VBUS converter will be forced to operate in boost mode. It has higher priority over I²C control

and can be disabled through control register. The polarity of OTG active status can also be controlled.

OTG

F2

At POR, the OTG control register is ignored and the OTG pin is used as the input current limiting selection pin

for VBUS converter. When OTG=High, IIN_LIMIT=500mA and when OTG=Low, IIN_LIMIT=100mA.

Charge current-sense input. Battery current is sensed via the voltage drop across an external sense resistor. A

0.1μF ceramic capacitor to GND is required.

CSIN

VBAT

F3

F4

I

Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1µF) to GND if there

are long inductive leads to battery.

Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128µS

pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive

a LED or communicate with a host processor.

STAT

F5

O

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

Supply voltage range (with respect

VBUS, VIN

to GND)

–2

20

V

Input voltage range (with respect

to and GND)

SCL, SDA, OTG, CSIN, VREG, VBAT, SLRST, DIS, LED

–0.3

7

PMID1, PMID2, STAT

VREF

20

6.5

Output voltage range (with respect

to and GND)

V

BOOT, BOOT1

SW1, SW2

–0.7

20

12

Voltage difference between CSIN and VBAT inputs (VCSIN -VBAT)

±7

V

mA

A

Output sink

STAT

10

Output current (average)

SW1, SW2

1.5⁽²⁾

+85

+125

+150

T_AOperating free-air temperature range

–30

–40

–45

°C

T_J

Junction temperature range

T_stgStorage temperature

Human body model at all pins

Machine model

±2000

±100

±500

ESD

V

Rating⁽³⁾

Charge device model

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Duty cycle for output current should be less than 50% for 10- year life time when output current is above 1.25A

(3) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

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UNITS

THERMAL INFORMATION

bq24140

THERMAL METRIC⁽¹⁾

WCSP PACKAGE

30 PINS

79.5

0.3

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

θ_JCtop

θ_JB

Junction-to-board thermal resistance

44.4

0.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

44.4

n/a

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

VBUS

VIN

T_J

Supply voltage

4.0

6⁽¹⁾

9⁽¹⁾

V

Supply voltage

Operating junction temperature range

–40

125 °C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight

layout minimizes switching noise.

ELECTRICAL CHARACTERISTICS

Circuit of Figure 1, V_BUS= 5V, HZ_MODE=0, OPA_MODE=0, CD=0, T_J= –40°C–125°C and T_J= 25°C for typical values

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

INPUT CURRENTS

VBUS > V_MIN, PWM switching

10

mA

μA

I_VBUS

VBUS supply current for control

VIN supply current for control

VBUS > V_MIN, PWM NOT switching

0°C < T_J< 85°C, CD = 1 or HZ_MODE = 1

VIN > V_MIN, PWM switching

5

33

10

80

mA

VIN > V_MIN, PWM NOT switching

5

I_VIN

0°C < T_J< 85°C, CD = 1 or HZ_MODE = 1, No load on

VREG

150

μA

Leakage current from battery to VBUS pin

and / or VIN

I_{IN_LEAK}

0°C < T_J< 85°C, V_VBAT= 4.2 V, High Impedance mode

5

Battery discharge current in high

impedance mode, (CSIN, VBAT, SW

pins)

0°C < T_J< 85°C, V_VBAT= 4.2 V, High Impedance mode,

SCL,SDA,OTG=0V or 1.8V

23

μA

VOLTAGE REGULATION

V_OREGOutput charge voltage

Operating in voltage regulation, programmable

3.5

4.44

V

T_A= 25°C

–0.5%

0.5%

0.75

%

Over recommended operating temperature

–0.75%

–0.6%

Voltage regulation accuracy

4.1 V – 4.35 V range, over recommended operating

temperature

0.4%

CURRENT REGULATION -FAST CHARGE

VIN, V_LOWV≤ V_VBAT< V_OREG, VIN > VSLP,

RSNS = 68 mΩ, LOW_CHG=0, Programmable

550

1550

1250

350

VBUS, V_LOWV≤ V_VBAT< V_OREG, VBUS > VSLP,

RSNS = 68 mΩ LOW_CHG = 0, Programmable

I_OCHARGE

Output charge current

mA

V_LOWV≤ V_VBAT< V_OREG, VBUS > VSLP,

325

RSNS=68 mΩ LOW_CHG=1

Regulation accuracy for charge current

across RSNS, V_IREG= I_OCHARGE× R_SNS

37.4 mV ≤ V_IREG

-3%

3%

WEAK BATTERY DETECTION

V_LOWVWeak battery voltage threshold

Programmable

3.4

3.7

5%

V

Weak battery voltage accuracy

–5%

4

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ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, V_BUS= 5V, HZ_MODE=0, OPA_MODE=0, CD=0, T_J= –40°C–125°C and T_J= 25°C for typical values

PARAMETER

TEST CONDITIONS

Rising voltage, 2-mV over drive, t_RISE= 100 ns

Battery voltage falling

MIN

TYP MAX

UNIT

Deglitch time for weak battery threshold

Hysteresis for V_LOWV

30

ms

100

mV

DIS, SLRST and OTG PIN LOGIC LEVEL

V_IL

V_IH

Input low threshold level

Input high threshold level

0.4

V

1.3

50

CHARGE TERMINATION DETECTION

V

_VBAT> V_OREG-V_RCH, V_BUS> V_SLP, R_SNS= 68 mΩ,

I_TERM

Termination charge current

400

mA

ms

Programmable

Deglitch time for charge termination

Both rising and falling, 2-mV overdrive, t_RISE, t_FALL= 100 ns

3.4 mV ≤ V_{IREG_TERM}≤ 6.8mV

30

-35%

–12.5%

–6%

35%

Regulation accuracy for termination

current across R_SNSV_{IREG_TERM}= I_OTERM

× R_SNS

12.5

%

6.8 mV < V_{IREG_TERM}≤ 13.6 mV

13.6mV < V_{IREG_TERM}≤ 30 mV

6%

BAD ADAPTOR DETECTION

V_IN(MIN)

Input voltage lower limit

Bad adaptor detection

3.7

3.8

30

4.0

V

Deglitch time for VBUS rising above

V_IN(MIN)

Rising voltage, 2-mV overdrive, t_RISE= 100 ns

ms

Hysteresis for V_IN(MIN)

Current source to GND

Detection interval

Input voltage rising

100

20

200

40

mV

mA

S

I_SHORT

T_INT

During bad adaptor detection

Input power source detection

30

2

INPUT BASED DYNAMIC POWER MANAGEMENT

The threshold when input based DPM

loop kicks in

V_{IN_LOW}

Charge mode, programmable

4.2

4.76

+2%

V

DPM loop kick-in threshold tolerance

–2%

INPUT CURRENT LIMITING

T_J= 0°C–125ºC

88

86

93

98

I_IN= 100mA

mA

T_J= –40ºC–125ºC

I_{IN_LIMIT}

Input current limit

T_J= 0ºC–125ºC

450

440

475

500

I_IN= 500mA

T_J= –40ºC–125ºC

VREF BIAS REGULATOR

V_REFInternal bias regulator voltage

V_REFoutput short current limit

BATTERY RECHARGE THRESHOLD

V

_IN> V_REF, I_VREF= 1 mA, C_VREF= 1 μF

5.5

90

6.5

V

30

mA

V_RCH

Recharge threshold voltage

Deglitch time

Below V_OREG

120

130

160

mV

ms

V_VBATdecreasing below threshold, t_FALL= 100 ns, 10-mV

overdrive

STAT OUTPUT

Low-level output saturation voltage,

STAT pin

V_OL

I_O= 10 mA, sink current

0.55

1

V

High-level leakage current for STAT

Voltage on STAT pin is 5V

μA

LED OUTPUT

V_{LED_MIN}

Minimum LED operating voltage

LED current, programmable

2.5

V

ILED1 = L, ILED0 = L

ILED1 = L, ILED0 = H

ILED1 = H, ILED0 = L

ILED1 = H, ILED0 = H

0

1.35

2.7

I_LED

mA

5.4

LED current accuracy

–20%

+20%

200

V_DO

T_ON

Drop-out voltage of LED

VBAT = 2.5 V

100

mV

Turn on time for current source

(10%–90%)

μs

Turn off time for current source

(90%–10%)

T_OFF

100

μs

I²C BUS LOGIC LEVELS AND TIMING CHARTERISTICS

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ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, V_BUS= 5V, HZ_MODE=0, OPA_MODE=0, CD=0, T_J= –40°C–125°C and T_J= 25°C for typical values

PARAMETER

Output low threshold level

Input low threshold level

Input high threshold level

Input bias current

TEST CONDITIONS

MIN

TYP MAX

UNIT

V_OL

V_IL

I_O= 10 mA, sink current

0.4

V

V_(pull-up)= 1.8 V, SDA and SCL

V

V_IH

1.2

V

I_(bias)

f_SCL

1

μA

MHz

SCL clock frequency

3.4

BATTERY DETECTION

Battery detection current before charge

I_DETECT

t_DETECT

t_DETECT2

Begins after termination detected

-0.5

262

mA

ms

done (sink current)⁽¹⁾

Battery detection time

Battery detection time after linear charge

is complete and PWM starts

SLEEP COMPARATOR

Sleep-mode entry threshold, V_BUS-V_VBAT

or V_IN– V_VBAT

V_SLP

2.3 V ≤ V_VBAT≤ V_OREG, V_BUSor V_INfalling

2.3 V ≤ V_VBAT≤ V_OREG

0

40

110

30

100

200

mV

ms

V_SLP-EXIT

Sleep-mode exit hysteresis

70

Deglitch time for V_BUSor V_INrising above

V_SLP+V_{SLP_EXIT}

Rising voltage, 2-mV over drive, t_RISE= 100 ns

UNDER-VOLTAGE LOCKOUT (UVLO)

V_UVLO

V_{UV_HYS}

PWM

IC active threshold voltage

IC active hysteresis

V_BUSor V_INrising

3.05

90

3.3

3.65

V

V_BUSor V_INfalling from above V_UVLO

100

mV

Voltage from BOOT1 pin to SW1 pin, or

Voltage from BOOT2

V_BOOT

6.5

V

pin to SW2 pin

Internal top reverse blocking MOSFET

on-resistance

R_{ON_Q1}

R_{ON_Q2}

R_{ON_Q3}

R_{ON_Q4}

R_{ON_Q5}

I_{IN_LIMIT}= 500 mA, Measured from V_INto PMID2

Measured from PMID2 to SW2, V_BOOT2– V_SW2= 4 V

Measured from SW2 to GND

100

120

110

100

120

150

200

150

200

mΩ

Internal top N-channel Switching

MOSFET on-resistance

Internal bottom N-channel MOSFET

on-resistance

Internal top reverse blocking MOSFET

on-resistance

I_{IN_LIMIT}= 500 mA, Measured from V_BUSto PMID1

Measured from PMID1 to SW1, V_BOOT1– V_SW1= 4 V

Measured from SW1 to GND

Internal top N-channel Switching

MOSFET on-resistance

Internal bottom N-channel MOSFET

on-resistance

R_{ON_Q6}

f_OSC

110

3.0

mΩ

Oscillator frequency

Frequency accuracy

Maximum duty cycle

Minimum duty cycle

MHz

–10%

10%

D_MAX

D_MIN

99.5%

100

0

Synchronous mode to non-synchronous

mode transition current threshold⁽²⁾

Low-side MOSFET cycle-by-cycle current sensing

mA

CHARGE MODE PROTECTION

V_OVP-VIN

V_OVP-VBUS

V_OVP

Input OVP for VIN

Rising edge

9.6

6.3

9.8

140

6.5

170

117

11

10.0

6.7

V

mV

V

V_{OVP VIN}hysteresis

Input OVP for VBUS

VOVP VBUS hysteresis

Output OVP threshold voltage

VOVP hysteresis

mV

V_VBATthreshold over V_OREGto turn off charger during charge

Lower limit for V_VBATfalling from above V_OVP

Charge mode operation

110

121 %V_OREG

%V_OREG

I_LIMIT

Cycle-by-cycle current limit for charge

Trickle to fast charge threshold

V_SHORThysteresis

1.8

2.0

2.4

2.1

100

30

3.0

2.2

A

V

V_SHORT

V_VBATrising

mV

mA

I_SHORT

Trickle charge charging current

V_VBAT≤ V_SHORT

20

40

(1) Negative charge current means the charge current flows from the battery to charger (discharging battery).

(2) Bottom N-channel MOSFET always turns on for ~60 ns and then turns off if current is too low.

6

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ELECTRICAL CHARACTERISTICS (continued)

Circuit of Figure 1, V_BUS= 5V, HZ_MODE=0, OPA_MODE=0, CD=0, T_J= –40°C–125°C and T_J= 25°C for typical values

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

BOOST MODE OPERATION FOR V_BUS(OPA_MODE=1, HZ_MODE=0, VBUS input only)

V_{BUS_BOOST}

Boost output voltage (to VBUS pin)

Boost output voltage accuracy

2.5 V < V_VBAT< 4.5 V

5.05

+3%

V

Including line and load regulation

V_BUS= 5.05 V, 2.5 V < V_VBAT< 4.5 V

-3%

650

I_BOOST

I_BLIMIT

Maximum output current for boost

Cycle by cycle current limit for boost

mA

A

1.0

Over voltage protection threshold for

boost (VBUS pin)

V_BUSOVP

Threshold over V_BUSto turn off converter during boost

V_BUSfalling from above V_BUSOVP

5.8

6.0

162

6.2

V

mV

V

V_BUSOVPhysteresis

Maximum battery voltage for boost (VBAT

pin)

V_BATMAX

V_VBATrising edge during boost

4.65

4.75

4.85

V_BATMAXhysteresis

V_VBATfalling from above V_BATMAX

During boosting

70

2.3

2.8

mV

Minimum battery voltage for boost (VBAT

pin)

V_BATMIN

V

Before boost starts

2.97

Boost output resistance at

high-impedance mode (From VBUS to

PGND)

CD = 1 or HZ_MODE = 1

500

kΩ

µA

ICC_BOOS Operation quiescent current in boost

No load at VBUS, power save mode, V_VBAT= 4 V, boosting

650

T

mode

PROTECTION

T_SHTDWN

Thermal trip

165

10

°C

S

Thermal hysteresis

T_CF

Thermal regulation threshold

Time constant for the 32-second timer

Time constant for the 15-minute timer

Charge current begins to taper down

32 second mode

120

32

T_32S

15

12

T_15M

15 minute mode

15 Minute

VREG

V_REG

I_{LIM VREG}

VREG Regulator

I_LOAD= 1mA, CREG = 0.1µF, VIN > V_UVLO

2.34

10

2.6

2.86

V

Current limit VREG

VREG = 0V

mA

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TYPICAL APPLICATION CIRCUITS

V_IN=5V or V_BUS=5V, I_CHARGE= 1550mA, V_BAT= 3.5--4.44V (Adjustable), Safety Timer = 15 minutes or 32 seconds

4.7 mF

PMID2

SW1

PMID1

1 mH

68 mW

AC Adapter or

VIN

10 µF

47 µF

Wireless Power

1 mF

100 nF

PACK+

BOOT1

SW2

1 mH

+

VBUS

USB Adapter

PACK-

4.7 mF

100 nF

BOOT2

10 kW

CSIN

VBAT

SCL

SDA

STAT

OTG

SLRST

DIS

10 kW

VREF

GND

10 kW

1 mF

LED

VREG

HOST

0.1 mF

Figure 1. I²C Controlled 1-Cell USB and AC or Wireless Power Charger Application Circuit

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V_IN=5V or V_BUS=5V, I_CHARGE= 1550mA, V_BAT= 3.5--4.44V (Adjustable), Safety Timer = 15 minutes or 32 seconds

BLOCK DIAGRAM

PMID2

Q1

Q2

SW2

VIN

CBC Current

Limit

OSC

Charge

Pump

VREF

+

PWM Controller

Q3

V_{IN_DPM}

-

+

-

I_{IN_LIM}

CBC Current

Limit

PMID1

VBUS

Q5

Q4

SW1

PMID2

Charge

Pump

VREF

2.5V, 10mA (back

to back switches)

VREG

+

Q6

V_{BUS_DPM}

-

CSIN

VBAT

+

-

+

T_REG

I_CHG

+

-

I_{BUS_LIM}

-

T_J

+

-

V_BUS

+

PWM Charge

V_BUSUVLO

V_OREG

V_{BUS UVLO}

-

VREF

V_IN

V_{IN UVLO}

V_BUS

I_SHORT

+

-

V_INUVLO

Linear Chg

+

-

V_BUS

+

-

V_BUSPoor

Source

V_BUSOVP

BOOT

VREF

V_{BUS MIN}

V_{BUS OVP}

+

-

V_IN

Ref & Bias

V_IN

V_INPoor

Source

+

-

V_INOVP

TSHUT

V_{IN MIN}

V_{IN OVP}

PMID1

V_BAT

BOOT1

LED

+

-

T_J

+

-

PWM Charge

PMID2

Charge Control,

Timer and Display

Logic

V_SHORT

T_SHTDWN

VBAT

LED

V_BAT

+

-

BAT OVP

V_{BAT OVP}

V_BAT

+

-

STAT

Recharge

V_OREG- V_RCH

V_BUS

V_BAT

+

-

Sleep V_BUS

DIS

SLRST

OTG

V_IN

+

-

Sleep V_IN

V_BAT

SDA

SCL

Recharge

GND

I2C Control

V_CSIN

Termination

+

V_BAT

-

I_TERM

Figure 2. bq24140 Block Diagram

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. VBUS to VIN Charging – Default Mode C1:VIN, CH2: IVBUS, CH3: IVIN, CH4: VBUS

Figure 4. VIN Charging and removed, switch to VBUS – Default Mode C1:VIN, CH2: IVBUS, CH3: IVIN,

CH4: VBUS

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Figure 5. VBUS Dynamic Power Management (DPM) – C1:VIN, CH2: IVBUS, CH3: VBUS, CH4: STAT

Figure 6. VBUS Dynamic Power Management (DPM) – CH1:VIN, CH2: STAT, CH3: VBAT, CH4: IVIN

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0.95

0.93

Efficiency 325

Efficiency 550

Efficiency 950

0.91

0.89

0.87

0.85

0.83

0.81

0.79

0.77

0.75

Efficiency 1250

2

2.5

3

3.5

4

4.5

VBAT - Battery Voltage - V

Figure 7. VBUS Efficiency versus Battery Voltage

0.95

0.93

VBAT at 4.2 V

VBAT at 4 V

VBAT at 3.6 V

0.91

0.89

0.87

0.85

0.83

0.81

0.79

0.77

0.75

VBAT at 3 V

VBAT at 2.5 V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

ICHG - Charge Current - A

Figure 8. VBUS Efficiency versus Charge Current

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0.95

0.93

Efficiency 325

Efficiency 550

Efficiency 950

0.91

0.89

0.87

0.85

0.83

0.81

0.79

0.77

0.75

Efficiency 1.55

2

2.5

3

3.5

4

4.5

5

VBAT - Battery Voltage - V

Figure 9. VIN Efficiency versus Battery Voltage

0.95

0.93

VBAT at 4.2 V

VBAT at 4 V

VBAT at 3.6 V

0.91

0.89

0.87

0.85

0.83

0.81

0.79

0.77

0.75

VBAT at 3 V

VBAT at 2.5 V

0

0.2

0.4

0.6

0.8

1

ICHG - Charge Current - A

1.2

1.4

1.6

Figure 10. VIN Efficiency versus Charge Current

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Figure 11. Charge Current Response – 550mA to 1.55A

CH1: VIN, CH2: VBAT, CH3: IBAT, CH4: IVIN

Figure 12. Input Current Regulation Response – 100mA to No Limit

CH1: VIN, CH2: VBAT, CH3: IBAT, CH4: IVIN

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2 %

1 %

0 %

-1 %

VIN = 5 V, VBAT = 3.6 V

VIN = 5 V, VBAT = 3 V

VIN = 5 V, VBAT = 4 V

-2 %

-3 %

VBUS = 5 V, VBAT = 3.6 V

VBUS = 5 V, VBAT = 4 V

-4 %

-5 %

-6 %

VBUS = 5 V, VBAT = 3 V

0

20

40

60

80

100

120

Figure 13. Typical Charge Current Accuracy

Figure 14. VBUS OTG in PFM Mode

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92

91

90

89

88

87

86

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

Boost Output current (A)

Figure 15. VBUS OTG Efficiency

DETAILED FUNCTIONAL DESCRIPTION

The bq24140 is a highly integrated dual input switch-mode battery charger with USB-OTG support. Due to the

switch-mode architecture, it provides the capability of charging the battery faster than traditional linear chargers

in the event that the power source is current limited, such as USB ports. In addition to the reduced charge time,

higher efficiencies reduce the power losses through the charger and allows for better thermal management of the

end product.

The bq24140 integrates a dual input 3MHz synchronous switching charger that targets space limited portable

applications powered by a single cell Li based battery pack. In addition to charge the battery, the bq24140

provides support for simultaneously boosting the battery voltage back to the USB input for USB-OTG support.

The bq24140 has two operation modes: default mode and host-control mode. In default mode, the charger will

start a charge cycle with the default parameters and wait for an I2C write to the IC before entering host-mode. In

host-control mode, the charger will switch to a 32s watchdog timer and the charge paramters will follow the

information set on the registers.

The bq24140 provides three ways of configuring the charger, charge mode, boost mode and high impedance

mode. These 3 configuration allows for multiple possible settings of the charge systems, including charging the

battery and providing power to an accessory. The high impedance mode reduces the quiescent current from the

device, effectively reducing the power consumption when the portable device is in standby mode. Integrated

control loops ensure smooth transitions between the different operating modes.

PWM Buck Charger

The IC provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate charge current or

voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation

network used for both continuous and discontinuous current conduction operation. The voltage and current loops

are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable

operation, allowing the use of small ceramic capacitors with very low ESR. The device operates between 0% to

99.5% duty cycles.

The IC has back to back common-drain N-channel FETs at the high side and one N-channel FET at low side for

both VIN and VBUS inputs. The input N-FETs (Q1, Q4) prevents battery discharge when VIN and/or VBUS is

lower than VBAT. The second high-side N-FET (Q2, Q5) are the switching FETs. A charge pump circuit is used

to provide gate drive for Q1 and Q4, while a bootstrap circuit with an external bootstrap capacitor is used to

supply the gate drive voltage for Q2 and Q5.

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Cycle-by-cycle current limit is sensed through FETs Q4 and Q5 for the high side current limit and through Q3 and

Q6 for the low side current limit. The high side current limit threshold is set to a nominal 2.4-A peak current. The

low-side current limit decides if the PWM Controller will operate in synchronous or non-synchronous mode. This

threshold is set to 100mA and it turns off the low-side N-channel FETs (Q3 and/or Q6) before the current

reverses, preventing the battery from discharging. Synchronous operation is used when the current of the

low-side FET is greater than 100mA to minimize power losses.

If the battery voltage is below the V(_SHORT) threshold, the bq24140 applies the short circuit current, I(_SHORT), to

the battery. The purpose of this current is to close an open protector on the battery pack. Once the battery

voltage rises above V_SHORT, the bq24140 ramps us the charge current to the programmed I_CHARGEvalue. If the

programmed charge current requires an input current that is higher than the programmed I_{IN_LIMIT}value, then the

bq24140 will regulate the input current and the charge current will be limited by the input current loop. The slew

rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. Both the

input current limit, I_{IN_LIMIT}, and fast charge current, I_CHARGE, can be set by the host. Once the battery voltage

reaches the programmed regulation voltage, V_OREG, the charge current is tapered down. (See Figure 16 and

Figure 17.

Fastcharge Phase

(PWM Charge)

Precharge Phase

(Linear Charge)

Voltage Regulation Phase

(PWM Charge)

V

OREG

I

CHARGE

Charge Voltage

V

SHORT

Charge Current

Termination

I

SHORT

Figure 16. Typical Charging Profile for No Input Current Limit

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Voltage Regulation Phase

(PWM Charge)

Fastcharge Phase

(PWM Charge)

Precharge Phase

(Linear Charge)

V

OREG

Charge Voltage

V

SHORT

Charge Current

Termination

I

SHORT

Figure 17. Typical Charging Profile With Input Current Limit

The voltage regulation feedback occurs by monitoring the battery-pack voltage between the VBAT and GND

pins. The regulation voltage is adjustable (3.5V to 4.44V) and is programmed through I²C interface. The IC

monitors the charging current during the voltage regulation phase. When the termination is enabled, once the

termination threshold, I_TERM, is detected and the battery voltage is above the recharge threshold, the IC

terminates charge. The termination current level is programmable. To disable the charge current termination, the

host can set the charge termination bit (TE) of charge control register to 0, refer to I²C section for detail.

A new charge cycle is initiated when one of the following conditions is detected:

•

The battery voltage falls below the V_(OREG)– V_(RCH)threshold.

VBUS or VIN Power-on reset (POR), if battery voltage is below the V_(LOWV)threshold.

CE bit toggle or RESET bit is set (Host controlled)

Figure 18 shows an operational flow chart of the bq24140 in charge mode.

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IC unpowered

Attach V

IN

and/or V_BUS

DEFAULT mode

CD Pin Low?

Yes

Hi-Z mode

No

Good input

power?

Attach

battery

Yes

No

Battery

Inserted?

Hi-Z mode

Yes

Battery need

charge?

Charge Disable

DEFAULT mode

Charge at

I_CHRG=325mA up

to V_BAT=3.54V

HOST mode

controlled

I2C

communication

?

charging at I

up to V

CHRG

OREG

No

Watchdog

timer expired?

15-min timer

expired?

Yes

No

V_BAT>V_RCHG,Term

Enabled and I_TERM

reached?

Hi-Z mode

Yes

No

Input Power

POR?

Hi-Z mode

Figure 18. Operational Flowchart

POWER UP

When a power source is first connected to the bq24140, the IC will go to default mode for 15 minutes. In default

mode, the bq24140 is configured with safe charging parameters for charge current, charge voltage and input

current. Once a write event is done to the bq24140 through I²C, the device enters host mode and the device will

then follow the parameters as they are written by the host.

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During initial power up in default mode, the device will look at the battery voltage. If the battery voltage is less

than the V_LOWV, the device will charge the battery with a default charge current of 325mA and a default battery

charge voltage of 3.54V. The input current limit value depends on which power source was used. In the case the

bq24140 is powered up from the VIN source, the input current limit is set to 500mA. If the device is powered up

from the VBUS source, the input current limit depends on the status of the OTG pin. If the OTG pin is low, the

input current limit is set to 100mA. If the OTG pin is high, the input current limit is set to 500mA.

INPUT POWER SOURCE PRIORITY

When two power supplies are detected in default mode, the bq24140 will default to VIN operation and the VBUS

input will go to high impedance. There is a blanking time between switching from one power source to the other

power source of 10ms (t_HANDOFF). The state diagram below describes the operation (Figure 19).

Input Power Source Switch Over State Diagram

VBUS Charging Active

No

VIN > V_UVLO

?

Yes

Bad Adaptor Detection

for VIN

No

VIN Adaptor

Good?

Yes

Set /CE bit (B2, Register 1,

0x6b) high

Delay T_HANDOFF

10 ms

Start VIN Charging

Figure 19. Input power source selection in default mode

In the case where the bq24140 is in host mode, power priority will be dictated by the Host by setting one input to

high impedance and activating the other input using the HZ_MODE bit of the control register.

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BAD ADAPTOR DETECTION

At POR of VBUS or VIN, the IC performs the bad adaptor detection by applying a current sink of 30mA to the

valid power pin. If the power pin is higher than VIN(MIN) for 30ms, the adaptor is good and the charge process

begins. Otherwise, if the power pin drops below VIN(MIN), a bad adaptor is detected. Once a bad adaptor is

detected, the IC disables the current sink, sends a send fault pulse in FAULT pin and sets the bad adaptor flag

(B2-B0=011 for Register 0x00). After a delay of T_INT, the IC repeats the adaptor detection process, as shown in

the flowchart below:

VIN or VBUS POR

Delay 1ms

Enable Adaptor Detection

Start 30ms timer

Enable 30mA current source

No

VIN or VBUS

>

30ms Timer

expired?

Yes

V_{IN MIN}

?

No

Good Adaptor Detected

Disable Adaptor Detection

Start Charge

Bad Adaptor Detected

Pulse STAT pin

Set Bad Adaptor Flag

Enable V_{IN DPM}

Delay T_INT

2s

Figure 20. Bad Adaptor Detection

BATTERY DETECTION

Battery detection during charging

During normal charging process with host control, once the voltage at the VBAT pin is above the battery

recharge threshold, V_OREG–V_RCH, and the termination charge current is detected, the IC turns off the PWM

charge and enables a discharge current, I_DETECT, for a period of t_DETECT, then checks the battery voltage. If the

battery voltage is still above recharge threshold, the IC concludes that the battery is present and charge is

completed. On the other hand, if the battery voltage is below battery recharge threshold, the IC concludes that

the battery was removed. Under this condition, the charge parameters (such as input current limit) are reset to

the default values and charge resumes after a delay of t_INT. This function ensures that the charge parameters are

reset whenever the battery is replaced.

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Battery detection during power-up

The bq24140 also has a unique battery detection scheme during the start up of the charger. At power up, if the

timer is in 15-minute mode, bq24140 will start a 262ms timer when exiting from short circuit mode to PWM

charge mode. If the battery voltage is charged to recharge threshold (V_OREG–V_RCH) and the 262ms timer has not

expired yet, or battery voltage is above output OVP threshold during short-circuit mode, bq24140 will consider

the battery is not present; then stop charging and go to high impedance mode immediately. However, if the

262ms timer has expired before the recharge threshold is reached, the charging process will continue as normal.

HIGH-SIDE LED DRIVER

The LED pin is a high-side LED driver. This LED function needs to run from the battery and the expected output

current can be programmed through I²C. There are 2 bits for programming the output current from the LED pin.

In addition, there is extra programmability for the LED function. Since there is only one LED driver used by both

the VIN and VBUS charger cores, there is only one LED register that can be accessed through the addresses

6AH and 6BH. When one of the two addresses is written, the settings for both cores will be set. Refer to the

Register Description Section for details on the LED programmable timings and current options.

BOOST CONVERTER OPERATION

The bq24140 support USB-OTG for the VBUS pin when OTG mode is enabled. In this configuration, the battery

voltage is boosted to 5.05V (±3%). The maximum output current for the boost converted is increased to 650mA

minimum current.

Boost Start Up

To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start

up.

PFM Mode at Light Load

In boost mode, the IC operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the

converter efficiency at light load condition. During boosting, the PWM converter is turned off if the inductor

current falls below than 200mA. The PWM is turned back on only when the voltage at PMID pin drops to 99.5%

of the typical rated output voltage. A unique pre-set circuit is used to make the smooth transition between PWM

and PFM mode.

Safety Timer in Boost Mode

At the beginning of boost operation, the IC starts a 32-second timer that is reset by the host using the I²C

interface. Writing “1” to reset bit of TMR_RST in control register will reset the 32-second timer and TMR_RST is

automatically set to “0” after the 32-second timer is reset. Once the 32-second timer expires, the IC turns off the

boost converter, enunciates the fault pulse from the STAT pin and sets fault status bits in the status register. The

fault condition is cleared by POR or host control.

Charge Status Output, STAT Pin

The STAT pin is used to indicate operation conditions for bq24140. STAT is pulled low during charging when

EN_STAT bit in control register (00H) is set to “1”. Under other conditions, STAT pin behaves as a high

impedance (open-drain) output. Under fault conditions, a 128-μs pulse will be sent out to notify the host. The

status of STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive

an LED or communicate to the host processor.

Table 1. STAT Pin Summary

CHARGE STATE

Charge in progress and EN_STAT = 1

STAT

Low

Other normal conditions

Open-Drain

Charge mode faults and input not in HiZ

128 µs pulse, then open-drain

128 µs pulse, then normal per above cases

Boost mode faults and input not in HiZ

VIN Present bit change (H→L or L→H) regardless of HiZ status

VBUS Present bit change (H→L or L→H) regardless of HiZ status

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Safety Limit Registers

The bq24140 includes safety limit registers which are used as an extra level of security for devices that allow

applications to be developed by third party vendors (i.e. Android OS). The purpose of the safety limit registers is

to program the maximum allowable battery regulation voltage and charge current. These two registers need to be

written before any other write actions are sent to the bq24140. Once a write action to a register other than the

safety limit registers, the values on the safety limit registers will be locked.

SLRST Pin

When SLRST=0, the bq24140 will reset all the safety limits to default values, regardless of the write actions to

safety limits registers (06H). When SLRST=1, the bq24140 can program the safety limit register until any write

action to other registers locks the programmed safety limits.

VREG LDO

The bq24140 includes a 2.6V LDO that can be used as an indication of the VIN input being connected. This LDO

is active all the time when there is a power source connected to the VIN input. The current limit on the LDO

guarantees up to 10mA.

SERIAL INTERFACE DESCRIPTION

I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the

bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I2C bus

through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The IC works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write

mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements. Register contents remain intact as long as

supply voltage remains above 2.2 V (typical). I²C is asynchronous, which means that it runs off of SCL. The

device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that

SDA changes while SCL is LOW.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as

F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to

as HS-mode. The IC supports 7-bit addressing only. The device has two 7-bit addresses, defined as

‘1101011’ (6BH) for USB portion and, and ‘1101010’ (6AH) for AC portion.

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REGISTER DESCRIPTION

For I2C address 6BH (USB Charger)

Status/Control Register (READ/WRITE)

Memory location: 00, Reset state: x1xx 0xxx

BIT

NAME

Read/Write

FUNCTION

B7(MSB) TMR_RST/OTG

Read/Write

Write: TMR_RST function, write “1” to reset the safety timer (auto clear)

Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level;

B6

B5

EN_STAT

STAT2

Read/Write

Read only

0-Disable STAT pin function, 1-Enable STAT pin function (default 1)

00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault

B4

STAT1

B3

BOOST

Boost mode, 0—Not in boost mode.

B2

FAULT_3

FAULT_2

FAULT_1

Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or

VBUS<VUVLO, 100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No battery

B1

B0(LSB)

Boost mode: 000-Normal, 001-V_BUSOVP, 010-Over load, 011-Battery voltage is too low,

100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA

Control Register (READ/WRITE)

Memory location: 01, Reset state: 0011 0000

BIT

NAME

Read/Write

FUNCTION

B7(MSB) Iin_Limit_2

Read/Write

00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB

host/charger with 800-mA current limit, 11-No input current limit (default 00)

B6

B5

Iin_Limit_1

VLOWV_2⁽¹⁾

VLOWV_1⁽¹⁾

TE

200 mV weak battery voltage threshold (default 1)

B4

100 mV weak battery voltage threshold (default 1)

B3

1-Enable charge current termination, 0-Disable charge current termination (default 0)

1-Charger is disabled, 0-Charger enabled (default 0)

1-High impedance mode, 0-Not high impedance mode (default 0)

1-Boost mode, 0-Charger mode (default 0)

B2

CE

B1

HZ_MODE

OPA_MODE

B0(LSB)

(1) The range of weak battery voltage threshold (VLOWV) is 3.4V–3.7V with the offset of 3.4V and step of 100mV (default 3.7V).

Control/Battery Voltage Register (READ/WRITE)

Memory location: 02, Reset state: 0000 1010

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

V_OREG5

V_OREG4

V_OREG3

V_OREG2

V_OREG1

V_OREG0

OTG_PL

OTG_EN

Battery Regulation Voltage: 640 mV (default 0)

Battery Regulation Voltage: 320 mV (default 0)

Battery Regulation Voltage: 160 mV (default 0)

Battery Regulation Voltage: 80 mV (default 0)

Battery Regulation Voltage: 40 mV (default 1)

Battery Regulation Voltage: 20 mV (default 0)

Active at High level, 0-Active at Low level (default 1)

Enable OTG Pin, 0-Disable OTG pin (default 0)

B5

B4

B3

B2

B1

B0(LSB)

•

Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.54V).

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Vender/Part/Revision Register (READ only)

Memory location: 03, Reset state: 0101 0000

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

Vender2

Vender1

Vender0

PN1

Read only

Vender Code: bit 2 (default 0)

Vender Code: bit 1 (default 1)

Vender Code: bit 0 (default 0)

10

B5

B4

B3

PN0

B2

Revision2

Revision1

Revision0

000: Revision 1.0

B1

B0(LSB)

Battery Termination/Fast Charge Current Register (READ/WRITE)

Memory location: 04, Reset state: 0000 0001

BIT

NAME

Read/Write

FUNCTION

B7(MSB)

Reset

Write only

Write: 1-Charger in reset mode, 0-No effect

Read: always get “0”

B6

B5

V_ICHRG3

V_ICHRG2

V_ICHRG1

V_ICHRG0

V_ITERM2

V_ITERM1

V_ITERM0

Read/Write

Charge current sense voltage: 27.2mV

Charge current sense voltage: 13.6mV

B4

Charge current sense voltage: 6.8mV

B3

Charge current sense voltage: NA

B2

Termination current sense voltage: 13.6mV (default 0)

Termination current sense voltage: 6.8mV (default 0)

Termination current sense voltage: 3.4mV (default 1)

B1

B0(LSB)

•

Charge current sense voltage offset is 37.4mV and default charge current is 550mA, if 68-mΩ sensing

resistor is used and LOW_CHG=0.

The maximum charge current is 1.25A (Rsns=68mΩ) when charging from VBUS. If a higher value is

programmed, the 1.25A or maximum safety limit charge current is selected

Special Charger Voltage/Enable Pin Status Register

Memory location: 05, Reset state: 001X X100

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

NA

Read/Write

NA

VBUS_PRESENT Read Only

0—VBUS not connected, 1—VBUS present

B5

LOW_CHG

Read/Write

0—Normal charge current sense voltage at 04H,

1—Low charge current sense voltage of 22.1mV (default 1)

B4

B3

DPM_STATUS

VIN_PRESENT

V_SREG2

Read Only

Read/Write

0—DPM mode is not active, 1—DPM mode is active

0—VIN not connected, 1—Vin present

B2

Special charger voltage: 320 mV (default 1)

Special charger voltage: 160 mV (default 0)

Special charger voltage: 80 mV (default 0)

B1

V_SREG1

B0(LSB)

V_SREG0

•

Special charger voltage offset is 4.2V and default special charger voltage is 4.52V.

Default charge current will be 325mA, if 68-mΩ sensing resistor is used, since default LOW_CHG=1.

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Safety Limit Register (READ/WRITE, Write only once after reset!)

Memory location: 06, Reset state: 01000000

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

V_MCHRG3

V_MCHRG2

V_MCHRG1

V_MCHRG0

V_MREG3

V_MREG2

V_MREG1

V_MREG0

Maximum charge current sense voltage: 54.4 mV (default 0)

Maximum charge current sense voltage: 27.2 mV (default 1)

Maximum charge current sense voltage: 13.6 mV (default 0)

Maximum charge current sense voltage: 6.8 mV (default 0)

Maximum battery regulation voltage: 160 mV (default 0)

Maximum battery regulation voltage: 80 mV (default 0)

Maximum battery regulation voltage: 40 mV (default 0)

Maximum battery regulation voltage: 20 mV (default 0)

B5

B4

B3

B2

B1

B0(LSB)

•

Maximum charge current sense voltage offset is 550mA (default at 950mA) and the maximum charge current

option is 1.55A, if 68-mΩ sensing resistor is used.

Maximum battery regulation voltage offset is 4.2V (default at 4.2V) and maximum battery regulation voltage

option is 4.44V.

LED Configuration Register

Memory location: 07, Reset state: 10000010

BIT

B7(MSB)

B6

NAME

ILED1

ILED0

Read/Write

FUNCTION

00 – LED Off

01 – LED current 1.25mA

10 – LED current 2.5mA (default)

11 – LED current 5mA

B5

B4

NA

Read Only

Read/Write

Returns 0

LED_CTRL

0 – LED On when charging is Active (default)

1 – LED On regardless of charging status

B3

B2

t_LEDON1

t_LEDON0

Read/Write

00 – LED On time 130ms (default)

01 – LED On time 260ms

10 – LED On time 520ms

11 – LED Constant On

B1

t_LEDOFF1

t_LEDOFF0

Read/Write

00 – LED Off time 390ms

01 – LED Off time 780ms

10 – LED Off time 1560ms (default)

11 – LED Off time 3120ms

B0(LSB)

26

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For I2C address 6AH (AC Charger)

Status/Control Register (READ/WRITE)

Memory location: 00, Reset state: x1xx 0xxx

BIT

NAME

Read/Write

FUNCTION

B7(MSB)

TMR_RST/OTG Read/Write

Write: TMR_RST function, write “1” to reset the safety timer (auto clear)

Read: SLRST pin status, 0-SLRST pin at LOW level, 1-SLRST pin at HIGH level.

B6

B5

EN_STAT

STAT2

Read/Write

Read only

0-Disable STAT pin function, 1-Enable STAT pin function (default 1)

00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault

B4

STAT1

B3

NA

B2

FAULT_3

FAULT_2

FAULT_1

Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Bad Adaptor or

VBUS<VUVLO, 100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No

battery

B1

B0(LSB)

Control Register (READ/WRITE)

Memory location: 01, Reset state: 0111 0000

BIT

NAME

Read/Write

FUNCTION

B7(MSB)

Iin_Limit_2

Read/Write

00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit, 10-USB

host/charger with 800-mA current limit, 11-No input current limit (default 01)

B6

Iin_Limit_1

VLOWV_2⁽¹⁾

VLOWV_1⁽¹⁾

TE

Read/Write

B5

200mV weak battery voltage threshold (default 1)

100mV weak battery voltage threshold (default 1)

1-Enable charge current termination, 0-Disable charge current termination (default 0)

1-Charger is disabled, 0-Charger enabled (default 0)

1-High impedance mode, 0-Not high impedance mode (default 0)

NA

B4

B3

B2

/CE

B1

HZ_MODE

NA

B0(LSB)

(1) The range of weak battery voltage threshold (VLOWV) is 3.4V–3.7V with the offset of 3.4V and step of 100mV (default 3.7V).

Control/Battery Voltage Register (READ/WRITE)

Memory location: 02, Reset state: 0000 1010

BIT

B7(MSB)

B6

NAME

V_OREG5

V_OREG4

V_OREG3

V_OREG2

V_OREG1

V_OREG0

NA

Read/Write

FUNCTION

Battery Regulation Voltage: 640 mV (default 0)

Battery Regulation Voltage: 320 mV (default 0)

Battery Regulation Voltage: 160 mV (default 0)

Battery Regulation Voltage: 80 mV (default 0)

Battery Regulation Voltage: 40 mV (default 1)

Battery Regulation Voltage: 20 mV (default 0)

NA

B5

B4

B3

B2

B1

B0(LSB)

NA

•

Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.54V).

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Vender/Part/Revision Register (READ only)

Memory location: 03, Reset state: 0100 0000

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

Vender2

Vender1

Vender0

PN1

Read only

Vender Code: bit 2 (default 0)

Vender Code: bit 1 (default 1)

Vender Code: bit 0 (default 0)

00

B5

B4

B3

PN0

B2

Revision2

Revision1

Revision0

000: Revision 1.0

B1

B0(LSB)

Battery Termination/Fast Charge Current Register (READ/WRITE)

Memory location: 04, Reset state: 0000 0001

BIT

NAME

Reset

Read/Write

Write only

FUNCTION

B7(MSB)

Write: 1-Charger in reset mode, 0-No effect

Read: always get “0”

B6

VICHRG3

VICHRG2

VICHRG1

VICHRG0

VITERM2

VITERM1

VITERM0

Read/Write

Charge current sense voltage: 54.4 mV (default 0)

Charge current sense voltage: 27.2 mV (default 0)

Charge current sense voltage: 13.6 mV (default 0)

Charge current sense voltage: 6.8 mV (default 0)

Termination current sense voltage: 13.6 mV (default 0)

Termination current sense voltage: 6.8 mV (default 0)

Termination current sense voltage: 3.4 mV (default 1)

B5

B4

B3

B2

B1

B0(LSB)

•

Charge current sense voltage offset is 37.4mV and default charge current is 550mA, if 68-mΩ sensing

resistor is used and LOW_CHG=0.

•

The maximum charge current is 1.55A when charging from VIN. If a higher value is programmed, the 1.55A

or maximum safety limit charge current is selected.

Special Charger Voltage/Enable Pin Status Register

Memory location: 05, Reset state: 001X X100

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

NA

Read/Write

NA

VIN_PRESEN Read Only

T

0—VIN not connected, 1—Vin present

B5

LOW_CHG

Read/Write

0—Normal charge current sense voltage at 04H, 1—Low charge current sense voltage

of 22.1mV (default 1)

B4

B3

DPM_STATUS Read Only

0—DPM mode is not active, 1—DPM mode is active

0—CD pin at LOW level, 1—CD pin at HIGH level

Special charger voltage: 320mV (default 1)

Special charger voltage: 160mV (default 0)

Special charger voltage: 80mV (default 0)

CD_STATUS

V_SREG2

Read Only

Read/Write

B2

B1

V_SREG1

B0(LSB)

V_SREG0

•

Special charger voltage offset is 4.2V and default special charger voltage is 4.52V.

Default charge current will be 325mA, if 68-mΩ sensing resistor is used, since default LOW_CHG=1.

28

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Safety Limit Register (READ/WRITE, Write only once after reset!)

Memory location: 06, Reset state: 01000000

BIT

B7(MSB)

B6

NAME

Read/Write

FUNCTION

V_MCHRG3

V_MCHRG2

V_MCHRG1

V_MCHRG0

V_MREG3

V_MREG2

V_MREG1

V_MREG0

Maximum charge current sense voltage: 54.4 mV (default 0)

Maximum charge current sense voltage: 27.2 mV (default 1)

Maximum charge current sense voltage: 13.6 mV (default 0)

Maximum charge current sense voltage: 6.8 mV (default 0)

Maximum battery regulation voltage: 160 mV (default 0)

Maximum battery regulation voltage: 80 mV (default 0)

Maximum battery regulation voltage: 40 mV (default 0)

Maximum battery regulation voltage: 20 mV (default 0)

B5

B4

B3

B2

B1

B0(LSB)

•

Maximum charge current sense voltage offset is 550mA (default at 950mA) and the maximum charge current

option is 1.55A, if 68-mΩ sensing resistor is used.

Maximum battery regulation voltage offset is 4.2V (default at 4.2V) and maximum battery regulation voltage

option is 4.44V.

Memory location 06 resets only when VBAT voltage drops below V_SHORTthreshold (typ.2.05V) or SLRST (pin

C3) goes to logic ‘0’. After reset, the maximum values for battery regulation voltage and charge current can

be programmed many times until any writing to other register locks the safety limits. Programmed values

exclude higher values from memory locations 02 (battery regulation voltage), and from memory location 04

(Fast charge current).

If host accesses (write command) to some other register before safety limit register, the default values hold!

LED Configuration Register

Memory location: 07, Reset state: 10000010

BIT

B7(MSB)

B6

NAME

ILED1

ILED0

Read/Write

FUNCTION

00 – LED Off

01 – LED current 1.25 mA

10 – LED current 2.5 mA (default)

11 – LED current mA

B5

B4

NA

Read Only

Read/Write

Returns 0

LED_CTRL

0 – LED On when charging is Active (default)

1 – LED On regardless of charging status

B3

B2

t_LED_ON

1

0

Read/Write

00 – LED On time 13 ms (default)

01 – LED On time 260 ms

10 – LED On time 520 ms

11 – LED Constant On

t_LED_ON

B1

t_LED_OFF

1

0

Read/Write

00 – LED Off time 390 ms

01 – LED Off time 780 ms

10 – LED Off time 1560 ms (default)

11 – LED Off time 3120 ms

B0(LSB)

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APPLICATION SECTION

Charge Current Sensing Resistor Selection Guidelines

Both the termination current range and charge current range depend on the sensing resistor (R_SNS). The

termination current step (I_{OTERM_STEP}) can be calculated using Equation 1:

V

I(TERM0)

I

=

O(TERM_STEP)

R

(SNS)

(1)

Table 2 shows the termination current settings for three sensing resistors.

Table 2. Termination Current Settings for 55-mΩ, 68-mΩ, 100-mΩ Sense Resistors

I_(TERM)(mA)

R_(SNS)= 55mΩ

I_(TERM)(mA)

R_(SNS)= 68mΩ

I_(TERM)(mA)

R_(SNS)= 100mΩ

BIT

V_I(TERM)(mV)

V_I(TERM2)

V_I(TERM1)

V_I(TERM0)

Offset

13.6

6.8

3.4

247

124

62

200

100

50

136

68

34

62

50

34

The charge current step (I_{O(CHARGE_STEP)}) is calculated using Equation 2:

V

I(CHRG0)

I

=

O(CHARGE_STEP)

R

(SNS)

(2)

Table 3 shows the charge current settings for three sensing resistors.

Table 3. Charge Current Settings for 55-mΩ, 68-mΩ and 100-mΩ Sense Resistors

I_O(CHARGE)(mA)

R_(SNS)= 55mΩ

I_O(CHARGE)(mA)

R_(SNS)= 68mΩ

I_O(CHARGE)(mA)

R_(SNS)= 100mΩ

BIT

V_I(REG)(mV)

V_I(CHRG3)

V_I(CHRG2)

V_I(CHRG1)

V_I(CHRG0)

Offset

54.4

27.2

13.6

6.8

989

495

247

124

680

800

400

200

100

550

544

272

136

68

37.4

374

Output Inductor and Capacitance Selection Guidelines

The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs

when the LC resonant frequency, f_o, is approximately 40 kHz (20 kHz to 80 kHz). Equation 3 can be used to

calculate the value of the output inductor, L_OUT, and output capacitor, C_OUT

.

1

f

=

o

2p ´

L

´ C

OUT

(3)

To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 μF and 47 μF is

recommended for C_OUT, see the application section for components selection.

30

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SLUSAO5 –OCTOBER 2011

POWER TOPOLOGIES

System Load After Sensing Resistor

One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as

shown in Figure 21. The input voltage has been converted to a usable system voltage with good efficiency from

the input. When the input power is on, it supplies the system load and charges the battery pack at the same time.

When the input power is off, the battery pack powers the system directly.

SW

VBUS

Isns

Isys

Ichg

L1

Rsns

V_IN

+

-

bq2414x

System

Load

+

C3

C4

BAT

C1

PMID

C2

PGND

Figure 21. System Load After Sensing Resistor

The advantages:

1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power

dissipation. Consequently, the time that the system runs on the battery pack can be maximized.

2. It reduces the number of external path selection components and offers a low-cost solution.

3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current

can be limited to a desired value by setting the charge current value. When the system current increases, the

charge current drops by the same amount. As a result, no potential over-current or over-heating issues are

caused by excessive system load demand.

4. The total input current can be limited to a desired value by setting the input current limit value. USB

specifications can be met easily.

5. The supply voltage variation range for the system can be minimized.

6. The input current soft-start can be achieved by the generic soft-start feature of the IC.

Design considerations and potential issues:

1. If the system always demands a high current (but lower than the regulation current), the battery charging

never terminates. Thus, the battery is always charged, and its lifetime may be reduced.

2. Because the total current regulation threshold is fixed and the system always demands some current, the

battery may not be charged with a full-charge rate and thus may lead to a longer charge time.

3. If the system load current is large after the charger has been terminated, the IR drop across the battery

impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle.

The charger would then terminate due to low charge current. Therefore, the charger would cycle between

charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,

resulting in a much slower cycling.

4. In a charger system, the charge current is typically limited to about 30mA, if the sensed battery voltage is

below 2V short circuit protection threshold. This results in low power availability at the system bus. If an

external supply is connected and the battery is deeply discharged, below the short circuit protection

threshold, the charge current is clamped to the short circuit current limit. This then is the current available to

the system during the power-up phase. Most systems cannot function with such limited supply current, and

the battery supplements the additional power required by the system. Note that the battery pack is already at

the depleted condition, and it discharges further until the battery protector opens, resulting in a system

shutdown.

5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the

short circuit current limit, the end-equipment will be operational, but the charging process can be affected

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depending on the current left to charge the battery pack. Under extreme conditions, the system current is

close to the short circuit current levels and the battery may not reach the fast-charge region in a timely

manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.

Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the

application possible.

6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is

clamped by the battery and it cannot operate even if the input power is on.

System Load Before Sensing Resistor

The second circuit is similar to first one; the difference is that the system load is connected before the sense

resistor, as shown in Figure 22.

Isys

SW

VBUS

Isns

L1

Rsns

Ichg

V_IN

+

bq2414x

System

Load

+

-

C3

C4

BAT

C1

PMID

C2

PGND

Figure 22. System Load Before Sensing Resistor

The advantages of system load before sensing resistor to system load after sensing resistor:

1. The charger controller is based only on the current going through the current-sense resistor. So, the constant

current fast charge and termination functions operate without being affected by the system load. This is the

major advantage of having the system load connected before the sense resistor.

2. A depleted battery pack can be connected to the charger without the risk of the safety timer expiration

caused by high system load.

3. The charger can disable termination and keep the converter running to keep battery fully charged; or let the

switcher terminate when the battery is full and then allow the system to run off of the battery through the

sense resistor.

Design considerations and potential issues:

1. The total current is limited by the IC input current limit, or peak current protection, but not the charge current

setting. The charge current does not drop when the system current load increases until the input current limit

is reached. This solution is not recommended if the system requires a high current.

2. Efficiency declines when discharging through the sense resistor to the system.

3. No thermal regulation. Therefore, the system design should ensure the maximum junction temperature of the

IC is below 125°C during normal operation.

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DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUIT

Systems Design Specifications:

•

VBUS = 5 V

V_BAT= 4.2 V (1-Cell)

I_(charge)= 1.25 A

Inductor ripple current = 30% of fast charge current

1. Determine the inductor value (L_OUT) for the specified charge current ripple:

VBAT ´ (VBUS - VBAT)

L

=

OUT

VBUS ´ f ´ DI

L

, the worst case is when battery voltage is as close as to half of the input

voltage.

2.5 ´ (5 - 2.5)

L

=

OUT

6

5 ´ (3 ´ 10 ) ´ 1.25 ´ 0.3

(4)

L_OUT= 1.11 μH

Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:

VBAT ´ (VBUS - VBAT)

DI =

L

VBUS ´ f ´ L

OUT

(5)

(6)

2.5 ´ (5 - 2.5)

DI =

L

6

-6

5 ´ (3 ´ 10 ) ´ (1 ´ 10

)

ΔI_L= 0.42 A

Calculate the maximum output current:

DI

L

I

= I +

OUT

LPK

2

0.42

2

(7)

(8)

I

= 1.25 +

LPK

I_LPK= 1.46 A

Select 2.5mm by 2mm 1-μH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbers

are shown as following.

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Table 4. Inductor Part Numbers

PART NUMBER

LQM2HPN1R0MJ0

MIPS2520D1R0

MDT2520-CN1R0M

CP1008

INDUCTANCE

SIZE

MANUFACTURER

1 μH

2.5 x 2.0 mm

Murata

FDK

TOKO

Inter-Technical

2. Determine the output capacitor value (C_OUT) using 40 kHz as the resonant frequency:

1

f

=

o

2p ´

L

´ C

OUT

(9)

(10)

(11)

1

C

=

OUT

2

4p²´ f

´ L

0

OUT

1

C

=

OUT

2

3 2

-6

4p ´ (40 ´ 10 ) ´ (1 ´ 10 )

C_OUT= 15.8 μF

Select two 0603 X5R 6.3V 10-μF ceramic capacitors in parallel i.e., Murata GRM188R60J106M.

3. Determine the sense resistor using the following equation:

V

(RSNS)

R

=

(SNS)

I

(CHARGE)

(12)

The maximum sense voltage across the sense resistor is 85 mV. In order to get a better current regulation

accuracy, V_(RSNS)should equal 85mV, and calculate the value for the sense resistor.

85mV

R

=

(SNS)

1.25A

(13)

R_(SNS)= 68 mΩ

This is a standard value. If it is not a standard value, then choose the next close value and calculate the real

charge current. Calculate the power dissipation on the sense resistor:

P_(RSNS)= I_(CHARGE)²× R_(SNS)

P_(RSNS)= 1.25²× 0.068

P_(RSNS)= 0.106 W

Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.

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PACKAGE MATERIALS INFORMATION

www.ti.com

26-Apr-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24140YFFR

BQ24140YFFT

DSBGA

YFF

30

3000

250

180.0

8.4

2.4

2.7

0.69

4.0

8.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Apr-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24140YFFR

BQ24140YFFT

DSBGA

YFF

30

3000

250

210.0

185.0

35.0

Pack Materials-Page 2

X: Max = 2.645 mm, Min =2.545 mm

Y: Max = 2.345 mm, Min =2.245 mm

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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型号：	BQ24140YFFR
厂家：	TEXAS INSTRUMENTS
描述：	Fully Integrated Dual-Input Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support 完全集成的双输入开关模式单节锂离子电池充电器与USB完全遵守和USB -OTG支持电源电路电池开关电源管理电路
文件：	总39页 (文件大小：1666K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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