BQ24157SYFFT [TI]
具有 OTG 的 I2C 单节 1.25A 降压电池充电器 | YFF | 20 | -40 to 125;
| 型号： | BQ24157SYFFT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 OTG 的 I2C 单节 1.25A 降压电池充电器 | YFF | 20 | -40 to 125 电池 |
| 文件： | 总43页 (文件大小：3102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq24157S
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
bq24157S 1.55A 完全集成开关模式单节锂离子充电器
具有完全 USB 兼容且支持 USB-OTG
Not Recommended for New Designs
1 特性
–
输入电压范围（电池供电）：
3.2 至 4.5V
1
•
集成功率场效应晶体管 (FET)，以支持高达 1.55A
的充电率
–
针对 VBUS 的输出：5.05V，350mA
•
•
2.1 × 2.0mm 20 引脚 DSBGA 封装
•
•
展频频率控制，以提高电磁干扰 (EMI) 性能
高精度电压和电流调节
与 bq24157 和 bq24158 引脚到引脚兼容
–
–
–
输入电流调节精度：
±5%（100mA 和 500mA)
2 应用范围
•
•
•
手机和智能电话
MP3 播放器
手持设备
充电电压调节精度：
±0.5% (25°C)，±1%（0°C 至 125°C）
充电电流调节精度：±5%
•
•
•
•
•
在无电池情况下，针对 GSM 校准的厂家测试模式
基于动态电源管理的输入电压 (VIN DPM)
故障适配器检测和抑制
3 说明
bq24157S 是一款紧凑、灵活、高效的 USB 适用型开
关模式充电管理器件，适用于各种便携式 应用中使用
的单节锂离子和锂聚合物电池。可通过一个 I2C 接口对
充电参数进行编程。IC 将同步 PWM 控制器，功率金
属氧化物半导体场效应晶体管 (MOSFET)，输入电流
感测，高精度电流和电压调节以及充电终止功能集成到
小型 DSBGA 封装中。
用于最大充电电压和电流限制的安全限制寄存器
用于单节锂离子和锂聚合物电池组的高效微型 USB
/ 交流电池充电器
•
•
•
20V 额定最大绝对输入电压
6.5V 最大运行输入电压
通过 I2C 兼容接口的可编程充电参数（高达
3.4Mbps）：
IC 分三个阶段对电池进行充电：调节、恒定电流和恒
定电压。输入电流被自动限制在主机设定的值上。
–
–
–
–
–
–
输入电流限制
VIN DPM 阈值
器件信息(1)
快速充电/终止电流
充电稳压电压（3.5 至 4.44V）
低充电电流模式启用/禁用
终止使能/禁用
器件型号
bq24157S
封装
封装尺寸（标称值）
DSBGA (20)
2.10mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
同步固定频率脉宽调制 (PWM) 控制器，运行在
3MHz 上时，占空比 0% 至 99.5%
典型应用电路
LO 1 mH
RSNS
•
•
针对低功耗的自动高阻抗模式
稳健耐用的保护
VBAT
VBUS
VBUS
PMID
SW
CO1
CIN
CO2
33 mF
U1
bq24157S
CBOOT
33 nF
1 mF
22 mF
BOOT
PGND
–
–
–
反向漏电保护防止电池亏电
热调节和保护
CIN
PACK+
4.7 mF
CCSIN
+
VAUX
10 kW
0.1 mF
CSIN
10 kW
2
I
C BUS
10 kW
PACK–
CSOUT
SCL
SCL
输入/输出过压保护
SDA
SDA
CCSOUT
0.1 mF
STAT
STAT
VREF
•
•
•
•
•
针对充电和故障的状态输出
支持 USB 的引导序列
自动充电
OTG
OTG
CD
CVREF
CD
10 kW
1 mF
10 kW
HOST
A. 使用 RSNS = 68mΩ 来设定高达 1.25A 的充
电电流，使用 RSNS = 55mΩ 来设定高达
1.55A 充电电流。要获得详细操作指南，请
参考 Detailed Design Procedure。
无电池的加电系统
针对 USB OTG 的升压模式操作：
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSB76
Not Recommended for New Designs
bq24157S
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 24
8.5 Register Maps......................................................... 26
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application .................................................. 29
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Performance Characteristics ........................ 8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 12
8.3 Feature Description................................................. 15
9
10 Power Supply Recommendations ..................... 34
10.1 System Load After Sensing Resistor .................... 34
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 36
12 器件和文档支持 ..................................................... 38
12.1 器件支持................................................................ 38
12.2 文档支持................................................................ 38
12.3 商标....................................................................... 38
12.4 静电放电警告......................................................... 38
12.5 Glossary................................................................ 38
13 机械、封装和可订购信息....................................... 39
13.1 封装概要................................................................ 39
8
4 修订历史记录
Changes from Revision A (June 2014) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
从特性删除了“具有重置控制功能的安全计时器” ..................................................................................................................... 1
已更改 封装特性：从 2.25 x 2.65mm 更改为 2.1 x 2.0mm .................................................................................................... 1
已更改 器件信息 表中的封装尺寸值........................................................................................................................................ 1
(2)
Moved Tstg Storage Temperature From: ESD Ratings To: Absolute Maximum Ratings(1)
............................................... 4
Changed the title of Figure 3 From Battery Detection at Power Up To: Power Up in DEFAULT Mode ................................ 8
Changed "32S Mode" To: "HOST Mode" and 15 Minute Mode To: DEFAULT Mode in Figure 5......................................... 8
Changed 32-second mode To: HOST mode in the Overview section ................................................................................. 11
Changed 15-minute operation To: default mode in the Overview section ........................................................................... 11
Changed 100-ms power-up delay From: No To: Yes in Table 1.......................................................................................... 11
Changed Figure 19 .............................................................................................................................................................. 14
Changed text From: "During the normal charging process with HOST control..." To: "During the normal charging
process with HOST control and termination enabled.." ....................................................................................................... 17
•
•
•
Changed Title From: 15-Minute Safety Timer To: DEFAULT Mode ................................................................................... 17
Changed 32-second mode To: HOST mode in USB Friendly Power Up ............................................................................ 17
Changed 15-minute mode To: DEFAULT mode and 32-s mode To: HOST mode in Input Current Limiting at Power
Up ........................................................................................................................................................................................ 17
•
•
•
•
Added a NOTE to the Application and Implementation section ........................................................................................... 29
Changed Figure 30 .............................................................................................................................................................. 33
Changed Figure 31 .............................................................................................................................................................. 33
Added Figure 30 .................................................................................................................................................................. 33
Changes from Original (February 2013) to Revision A
Page
•
添加了处理额定值 表、详细的 说明 部分、特性 说明 部分、器件功能模式 部分、寄存器映射 部分、应用和实施 部
分、电源推荐 部分、PCB 布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 .......................................... 1
2
Copyright © 2013–2015, Texas Instruments Incorporated
Not Recommended for New Designs
bq24157S
www.ti.com.cn
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
5 说明 （续）
此器件根据电池电压和用户可选的最小电流水平来确定是否终止充电。正常运行期间，如果电池电压下降到低于一
个内部阈值，IC 自动重新启动充电周期并在输入电源被移除后，自动进入睡眠模式或者高阻抗模式。充电状态可通
过 I2C 接口报告给主机。充电过程中，IC 监视其结温 (TJ) 并且在 TJ 增加到大约 125°C 时减少充电电流。为了支
持 USB OTG 器件，通过提升电池电压，bq24157S 能够提供 VBUS (5.05V)。此 IC 采用 20 引脚 DSBGA 封装。
6 Pin Configuration and Functions
20-Bump DSBGA Package
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
B2
B3
B4
PMID
PMID
PMID
SDA
C1
SW
C2
SW
C3
SW
C4
STAT
D1
D2
D3
D4
PGND
PGND
PGND
OTG
E1
E2
CD
E3
E4
CSOUT
CSIN
VREF
Pin Functions
PIN
NUMBER
I/O
DESCRIPTION
NAME
BOOT
CD
Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥10 V)
A3
E2
E1
I/O
from BOOT pin to SW pin.
I
I
Charge disable control pin. CD = 0, charge is enabled. CD = 1, charge is disabled and VBUS pin is high impedance to GND.
Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1-μF ceramic capacitor to PGND
CSIN
is required.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are long
inductive leads to battery.
CSOUT
OTG
E4
D4
I
I
Boost mode enable control or input current limiting selection pin. When OTG is in active status, the device is forced to
operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR while in
DEFAULT mode, the OTG pin is the default to be used as the input current limiting selection pin. The I2C register is ignored
at startup. When OTG = High, IIN_LIMIT = 500 mA and when OTG = Low, IIN_LIMIT = 100 mA.
PGND
PMID
D1, D2, D3
B1, B2, B3
Power ground
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3-μF capacitor
from PMID to PGND.
I/O
I2C interface clock. Connect a 10-kΩ pullup resistor to 1.8-V rail (VAUX= VCC_HOST
I2C interface data. Connect a 10-kΩ pullup resistor to 1.8-V rail (VAUX= VCC_HOST
)
SCL
SDA
A4
B4
I
I/O
)
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128-μs pulse is sent
out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with
a host processor.
STAT
C4
O
SW
C1, C2, C3
A1, A2
O
Internal switch to output inductor connection
Charger input voltage. Bypass it with a 1-μF ceramic capacitor from VBUS to PGND. It also provides power to the load during
boost mode.
VBUS
I/O
Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. TI does not recommend an
external load on VREF.
VREF
E3
O
Copyright © 2013–2015, Texas Instruments Incorporated
3
Not Recommended for New Designs
bq24157S
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1) (2)
over operating free-air temperature (unless otherwise noted)
MIN
–2
MAX UNIT
Supply voltage (with respect to PGND(3)
)
VBUS; VPMID ≥ VBUS – 0.3 V
20
7
V
V
V
V
V
V
V
V
V
Input voltage (with respect to PGND(3)
)
SCL, SDA, OTG, SLRST, CSIN, CSOUT, CD
–0.3
–0.3
-0.3
–0.7
PMID, STAT
VREF
20
7
Output voltage (with respect to PGND(3)
)
SW, BOOT
20
±7
7
Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT)
Voltage difference between BOOT and SW inputs (V(BOOT) – V(SW)
Voltage difference between VBUS and PMID inputs (V(VBUS) – V(PMID)
Voltage difference between PMID and SW inputs (V(PMID) – V(SW)
)
)
–0.3
–7
)
0.7
20
)
–0.7
10
Output sink
STAT
SW
10 mA
Output current (average)
Operating free-air temperature range
Storage temperature range
Junction temperature
1.55(2)
A
TA
–30
–45
–40
85
150
125
°C
°C
°C
Tstg
TJ
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) Duty cycle for output current should be less than 50% for 10-year lifetime when output current is above 1.5 A.
(3) All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified terminal, if not specified.
For thermal limitations and considerations of packages, see Thermal Information .
7.2 ESD Ratings
MIN
0
MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
2000
V
Electrostatic
discharge
V(ESD)
0
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
4
NOM
MAX
6(1)
UNIT
V
VBUS
TJ
Supply voltage, bq24157S
Operating junction temperature range
–40
125
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight
layout minimizes switching noise.
7.4 Thermal Information
bq24157S
THERMAL METRIC(1)
UNIT
YFF (20 PINS)
RθJA
Junction-to-ambient thermal resistance
85
25
55
4
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
50
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2013–2015, Texas Instruments Incorporated
Not Recommended for New Designs
bq24157S
www.ti.com.cn
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
7.5 Electrical Characteristics
Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical
values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VBUS > VBUS(min), PWM switching
VBUS > VBUS(min), PWM not switching
0°C < TJ < 85°C, CD = 1 or HZ_MODE = 1
10
mA
I(VBUS)
VBUS supply current control
5
15
23
μA
μA
0°C < TJ < 85°C, V(CSOUT) = 4.2 V, high impedance
mode, VBUS = 0 V
Ilgk
Leakage current from battery to VBUS pin
5
Battery discharge current in high impedance
mode, (CSIN, CSOUT, SW pins)
0°C < TJ < 85°C, V(CSOUT) = 4.2 V, high impedance
mode, V = 0 V, SCL, SDA, OTG = 0 V or 1.8 V
23
μA
VOLTAGE REGULATION
V(OREG) Output regulation voltage programable range
Operating in voltage regulation, programmable
TA = 25°C
3.5
–0.5%
–1%
4.44
0.5%
1%
V
Voltage regulation accuracy
CURRENT REGULATION (FAST CHARGE)
IO(CHARGE) Output charge current programmable range
TA = -40°C to 125°C
V(LOWV) ≤ V(CSOUT) < V(OREG),
VBUS > V(SLP), R(SNS) = 68 mΩ, LOW_CHG = 0,
Programmable
550
1250
mA
mA
V
LOWV ≤ VCSOUT < VOREG, VBUS > VSLP
,
325
550
350
569
RSNS= 68 mΩ, LOW_CHG = 1, OTG = High
Low charge current (default after POR in 15
min mode)
VLOWV ≤ VCSOUT < VOREG, VBUS > VSLP,
RSNS= 68 mΩ, LOW_CHG = 0, OTG = High
37.4 mV ≤ V(IREG)< 44.2 mV
44.2 mV ≤ V(IREG)
Regulation accuracy of the voltage across
R(SNS) (for charge current regulation)
V(IREG) = IO(CHARGE) × R(SNS)
–3.5%
–3%
3.5%
3%
WEAK BATTERY DETECTION
V(LOWV) Weak battery voltage threshold programmable
Adjustable using I2C control
3.4
3.7
5%
V
(1)
range2
Weak battery voltage accuracy
Hysteresis for V(LOWV)
–5%
Battery voltage falling
100
30
mV
ms
Deglitch time for weak battery threshold
Rising voltage, 2-mV overdrive, tRISE = 100 ns
CD, OTG, AND SLRST PIN LOGIC LEVEL
VIL
Input low threshold level
Input high threshold level
Input bias current
0.4
1.0
V
V
VIH
1.3
50
I(bias)
Voltage on control pin is 5 V
µA
CHARGE TERMINATION DETECTION
Termination charge current programmable
range
V(CSOUT) > V(OREG) – V(RCH)
,
I(TERM)
400
mA
ms
VBUS > V(SLP), R(SNS) = 68 mΩ, programmable
Deglitch time for charge termination
Both rising and falling, 2-mV overdrive,
tRISE, tFALL = 100 ns
30
3.4 mV ≤ V(IREG_TERM) ≤ 6.8 mV
6.8 mV < V(IREG_TERM) ≤ 17 mV
17 mV < V(IREG_TERM) ≤ 27.2 mV
–15%
–10%
–5.5%
15%
10%
5.5%
Regulation accuracy for termination current
across R(SNS)
V(IREG_TERM) = IO(TERM) × R(SNS)
BAD ADAPTOR DETECTION
VIN(min)
Input voltage lower limit
Bad adaptor detection
3.6
3.8
30
4.0
V
ms
mV
mA
s
Deglitch time for VBUS rising above VIN(min)
Hysteresis for VIN(min)
Rising voltage, 2-mV overdrive, tRISE = 100 ns
Input voltage rising
100
20
200
40
ISHORT
tINT
Current source to GND
During bad adaptor detection
Input power source detection
30
2
Detection Interval
INPUT BASED DYNAMIC POWER MANAGEMENT
Input Voltage DPM threshold programmable
VIN_DPM
range
4.2
4.76
1%
V
VIN DPM threshold accuracy
–3%
(1) While in DEFAULT mode, if a battery that is charged to a voltage higher than this voltage is inserted, the charger enters Hi-Z mode and
awaits I2C commands.
Copyright © 2013–2015, Texas Instruments Incorporated
5
Not Recommended for New Designs
bq24157S
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
www.ti.com.cn
Electrical Characteristics (continued)
Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical
values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT LIMITING
TJ = 0°C to 125°C
TJ = –40°C to 125°C
TJ = 0°C to 125°C
TJ = –40°C to 125°C
88
86
93
93
98
98
IIN = 100 mA
IIN = 500 mA
mA
mA
IIN_LIMIT
Input current limiting threshold
450
440
475
475
500
500
VREF BIAS REGULATOR
VREF Internal bias regulator voltage
VBUS > VIN(min) or V(CSOUT) > VBUS(min),
I(VREF) = 1 mA, C(VREF) = 1 μF
2
6.5
V
VREF output short current limit
BATTERY RECHARGE THRESHOLD
30
mA
V(RCH)
Recharge threshold voltage
Deglitch time
Below V(OREG)
100
120
130
150
mV
ms
V(SCOUT) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
STAT OUTPUTS
Low-level output saturation voltage, STAT pin
High-level leakage current for STAT
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
IO = 10 mA, sink current
0.55
1
V
VOL(STAT)
Voltage on STAT pin is 5 V
μA
VOL
VIL
Output low threshold level
Input low threshold level
Input high threshold level
Input bias current
IO = 10 mA, sink current
0.4
0.4
V
V
V(pullup) = 1.8 V, SDA and SCL
V(pullup) = 1.8 V, SDA and SCL
V(pullup) = 1.8 V, SDA and SCL
VIH
1.2
V
I(BIAS)
f(SCL)
1
μA
MHz
SCL clock frequency
3.4
BATTERY DETECTION
Battery detection current before charge done
Begins after termination detected,
V(CSOUT) ≤ V(OREG)
I(DETECT)
–0.5
262
mA
ms
(2)
(sink current)
Battery detection time
SLEEP COMPARATOR
tDETECT
Sleep-mode entry threshold,
VBUS – VCSOUT
V(SLP)
2.3 V ≤ V(CSOUT) ≤ V(OREG), VBUS falling
2.3 V ≤ V(CSOUT) ≤ V(OREG)
0
40
200
30
100
260
mV
mV
ms
V(SLP_EXIT)
Sleep-mode exit hysteresis
140
Deglitch time for VBUS rising above V(SLP)
V(SLP_EXIT)
+
Rising voltage, 2-mV overdrive, tRISE = 100 ns
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO
IC active threshold voltage
IC active hysteresis
Power up delay
VBUS rising – exits UVLO
3.05
120
3.3
150
140
3.55
V
UVLO(HYS)
VBUS falling below UVLO – enters UVLO
mV
ms
PWM
Voltage from BOOT pin to SW pin
During charge or boost operation
6.5
V
Internal top reverse blocking MOSFET on-
resistance
IIN(LIMIT) = 500 mA, measured from VBUS to PMID
180
120
250
Internal top N-channel switching MOSFET on-
resistance
Measured from PMID to SW,
VBOOT – VSW= 4 V
250
210
mΩ
MHz
Internal bottom N-channel MOSFET on-
resistance
Measured from SW to PGND
110
3.0
f(OSC)
Oscillator frequency
Frequency accuracy
Maximum duty cycle
Minimum duty cycle
–10%
0
10%
D(MAX)
D(MIN)
99.5%
100
Synchronous mode to non-synchronous mode
transition current threshold(2)
Low-side MOSFET cycle-by-cycle current sensing
mA
(2) Bottom N-channel FET always turns on for approximately 30 ns, and then turns off if current is too low.
6
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Electrical Characteristics (continued)
Circuit of Figure 28, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (CD = 0), TJ = –40°C to 125°C, TJ = 25°C for typical
values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE MODE PROTECTION
VOVP_IN_USB
Input VBUS OVP threshold voltage
Output OVP threshold voltage
VBUS threshold to turn off converter during charge
6.3
6.5
6.7
V
V(CSOUT) threshold over V(OREG) to turn off charger
during charge
110
117
121
VOVP
%VOREG
V(OVP) hysteresis
Lower limit for V(CSOUT) falling from above V(OVP)
Charge mode operation
11
2.4
2.1
100
30
ILIMIT
Cycle-by-cycle current limit for charge
Trickle to fast charge threshold
VSHORT hysteresis
1.8
2.0
3.0
2.2
A
V
V(CSOUT) rising
VSHORT
ISHORT
V(CSOUT) falling below VSHORT
mV
mA
Trickle charge charging current
V(CSOUT) ≤ VSHORT)
20
40
BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)
VBUS_B
Boost output voltage (to VBUS pin)
Boost output voltage accuracy
2.5 V < V(CSOUT) < 4.5 V
5.05
V
Including line and load regulation
–3%
350
3%
VBUS_B = 5.05 V, 3.3 V < V(CSOUT) < 4.5 V,
TJ= 0°C – 125°C
IBO
Maximum output current for boost
Cycle by cycle current limit for boost
mA
A
IBLIMIT
VBUS_B = 5.05 V, 2.5 V < V(CSOUT) < 4.5 V
1.0
6.0
Overvoltage protection threshold for boost
(VBUS pin)
Threshold over VBUS to turn off converter during
boost
5.8
6.2
V
VBUSOVP
VBUSOVP hysteresis
VBUS falling from above VBUSOVP
V(CSOUT) rising edge during boost
162
4.9
mV
V
Maximum battery voltage for boost
(CSOUT pin)
4.75
5.05
VBATMAX
VBATMAX hysteresis
V(CSOUT) falling from above VBATMAX
During boosting
200
2.5
2.9
mV
V
Minimum battery voltage for boost
(CSOUT pin)
VBATMIN
Before boost starts
3.05
V
Boost output resistance at high-impedance
mode (from VBUS to PGND)
CD = 1 or HZ_MODE = 1
217
kΩ
PROTECTION
TSHTDWN)
Thermal trip
165
10
Thermal hysteresis
Thermal regulation threshold
°C
TCF
Charge current begins to reduce
120
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7.6 Typical Performance Characteristics
Using circuit shown in Figure 28, TA = 25°C, unless otherwise specified.
VSW
VSW
VSW
5 V/div
VSW
5 V/div
IBAT
I Inductor
500 mA/div
IND
IBAT
200 mA/div
2 μs/div
200 μs/div
VBUS = 5 V
VBAT = 3.5 V
VIN = 5 V
VBAT = 3.2 V
ICHG = 950 mA
Figure 1. Cycle by Cycle Current Limiting In Charge Mode
Overload Operation
Figure 2. Charge Current Ramp Up
No Input Current Limit
VBUS
4 V/div
VBUS
2 V/div
VBAT
2 V/div
VSW
2 V/div
VSW
5 V/div
IBUS
20 mA/div
IBUS
100 mA/div
100 ms/div
10 ms/div
VBUS = 5 V
No Battery Connected
Termination Disabled
VBUS = 5 V at 8 mA
ICHG = 550 mA
VBAT = 3.2 V
IIN_limit = 100 mA
Figure 3. Power Up in DEFAULT Mode
Figure 4. Poor Source Detection
VBUS
IBUS
VBUS
1 V/div
OTG
2 V/div
OTG
DEFAULT Mode
HOST Mode
IBAT
200 mA/div
IBAT
IBUS
200 mA/div
Write Command
1 s/div
500 μs/div
OTG Control, DEFAULT Mode: VBUS = 5 V, VBAT = 3.1 V,
IIN_limit = 100 and 500 mA
I2C Control, HOST Mode: IIN_limit = 100 mA
VBUS = 5 V at 500 mA
VIN_DPM = 4.52 V
VBAT = 3.5 V
ICHG = 1550 mA
Figure 5. Input Current Control
Figure 6. VIN Based DPM
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Typical Performance Characteristics (continued)
Using circuit shown in Figure 28, TA = 25°C, unless otherwise specified.
94
VBUS
VBAT
VSW
AC Coupled
VBUS
100 mV/div
93
92
91
90
89
88
87
86
85
84
83
82
81
80
AC Coupled
VBAT
100 mV/div
AC Coupled
VSW 2 V/div
VBAT = 3.0 V
VBAT = 3.6 V
VBAT = 4.2 V
I Inductor
0.2 A/div
IND
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Charge Current (A)
5 μs/div
VBUS = 5.05 V
VBAT = 3.5 V
IBUS = 42 mA
Figure 8. Boost Waveform (PFM Mode)
Figure 7. Charger Efficiency
VBUS
200 mV/div,
5.05 V Offset
VBUS
VBUS
5 V/div
VPMID
VPMID
2 V/div
VBAT
200 mV/div,
3.5 V Offset
VSW
VSW
5 V/div
VSW
5 V/div
IBUS
IBUS
0.5 A/div
IBAT
500 mV/div
5 ms/div
100 μs/div
VBUS = 5.05 V
VBAT = 3.5 V
VBUS = 5.05 V
VBAT = 3.5 V
IBUS = 0 to 360 mA
ILOAD (at VBUS) = 5 to 450 mA
Figure 9. VBUS Overload Waveforms (Boost Mode)
Figure 10. Load Step Up Response (Boost Mode)
VBUS
VBUS
100 mV/div
5.05 V Offset
VBUS
2 V/div
VBAT
0.2 V/div
3.5 V Offset
OTG
OTG
VSW
5 V/div
VSW
5 V/div
VSW
5 V/div
IBUS
IBUS
IBAT
0.5 A/div
0.1 A/div
100 μs/div
10 ms/div
VBUS = 4.5 V (Charge Mode)
VBUS = 5.1 V (Boost Mode)
VBUS = 5.05 V
VBAT = 3.5 V
IBUS = 0 to 217 mA
VBAT = 3.5 V, IIN_LIM = 500 mA, (HOST Mode)
Figure 12. Boost to Charge Mode Transition (OTG Control)
Figure 11. Load Step Up Response (Boost Mode)
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Typical Performance Characteristics (continued)
Using circuit shown in Figure 28, TA = 25°C, unless otherwise specified.
95
90
85
80
75
70
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
IBUS = 50 mA
VBAT = 2.7 V
VBAT = 3.6 V
VBAT = 4.2 V
IBUS = 100 mA
IBUS = 200 mA
IBUS = 375 mA
0
50
100
150
200
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
Load Current at VBUS (mA)
VBAT (V)
Figure 13. Boost Efficiency
Figure 14. Line Regulation For Boost
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5
VOUT
AC Coupled
10 mV/div
INDUCTOR
AC Coupled
50 mA/div
VBAT = 2.7 V
VBAT = 3.6 V
VBAT = 4.2 V
IBAT
AC Coupled
10 mA/div
0
50
100
150
200
200 ns/div
Load Current at VBUS (mA)
ICHG = 1.2 A
Figure 16. Output Ripple for Voltage and Current
Figure 15. Load Regulation for Boost
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8 Detailed Description
8.1 Overview
For a current-restricted power source, such as a USB host or hub, a high-efficiency converter is critical to fully
use the input power capacity for quickly charging the battery. Due to the high efficiency for a wide range of input
voltages and battery voltages, the switch mode charger is a good choice for high speed charging with less power
loss and better thermal management than a linear charger.
The bq24157S includes highly integrated synchronous switch-mode chargers, featuring integrated FETs and
small external components, targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or
Li-polymer battery pack. Furthermore, the device has bidirectional operation to achieve boost function for USB-
OTG support.
The bq24157S has three operation modes: charge mode, boost mode, and high impedance mode. In charge
mode, the IC supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost
mode, the IC boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode,
the IC stops charging or boosting and operates in a mode with very-low current from VBUS or battery, to
effectively reduce the power consumption when the portable device is in standby mode. Through I2C
communication with a host (referred to as HOST mode), the IC achieves smooth transition among the different
operation modes. During DEFAULT operation, the charger will still charge the battery but uses each register's
default values.
Table 1. Device Features
Features
bq24157S
6.5
VOVP (V)
D4 pin definition
OTG
ICHARGE(MAX) at POR in DEFAULT mode with R(SNS) = 68 mΩ and OTG = High
ICHARGE(MAX) in HOST mode with R(SNS) = 68 mΩ and safety limit register increased from default (A)
Output regulation voltage at POR (V)
550 mA
1.5
3.54
Boost function
Yes
100 mA (OTG = Low);
500 mA (OTG = High)
Input current limit in DEFAULT mode
Battery detection at power up
I2C address
No
6AH
1
PN1 (bit4 of 03H)
PN0 (bit3 of 03H)
0
Safety timer and WD timer
100-ms power-up delay
Spread Spectrum
Disabled
Yes
Yes
Yes
Factory test mode
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8.2 Functional Block Diagrams
PMID
PMID
PMID
bq24157S
V
PMID
NMOS
NMOS
VBUS
VBUS
SW
V
BUS
SW
SW
Q2
CBC
Q 3
Q 1
Current
Limiting
I
LIMIT
NMOS
PWM
VREF
1
OSC
Charge
Pump
Controller
V
OUT
-
+
+
-
CSOUT
CSIN
-
IIN
_ LIMIT
V
OREG
+
-
-
V CSIN
+
V IN
_ DPM
-
I
OCHARGE
TCF
TJ
+
-
VREF
I
SHORT
PWM _ CHG
V
BUS
+
-
VBUS UVLO
V
UVLO
_CHG
VREF
LINEAR
V
BUS
+
-
Poor Input
Source
VREF
BOOT
V
IN(MIN)
REFERNCES
and BIAS
V
+
-
BUS
VBUS OVP
V
OVP_IN
CHARGE CONTROL
TIMER and DISPLAY
LOGIC
VREF 1
T
J
V
+
-
Thermal
Shutdown
PMID
T
SHTDWN
VOUT
V
OUT
Battery OVP
+
-
*
V
OVP
STAT
CD
V
BAT
+
Sleep
*
V
-
BUS
V
- V
OREG
RCH
+
-
Recharge
*
V
OTG (bq24153 /8)
SLRST(bq24156)
OUT
V
OUT
Termination
-
+
-
PGND
PGND
PGND
V
CSIN
*
( I2 C Control )
Decoder
DAC
I
SCL
SDA
TERM
V
+
-
BAT
PWM Charge
Mode
*
V
SHORT
*
Signal Deglitched
Figure 17. Function Block Diagram of bq24157S in Charge Mode
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Functional Block Diagrams (continued)
PMID
bq24157S
PMID
VPMID
PMID
NMOS
NMOS
VBUS
VBUS
SW
SW
SW
V
BUS
CBC
Current
Limiting
Q2
Q1
I
BLIMIT
PWM
Controller
VREF
1
Charge
Pump
OSC
Q3
NMOS
PFM Mode
-
75 mA
+
-
+
V
+
-
BUS_B
VREF
VREF
I
BO
V
REFERNCES
BOOT
PWM _BOOST
and BIAS
BUS
+
-
VBUS OVP
VREF 1
V
BUSOVP
V
PMID
CSIN
T
J
+
-
Thermal
Shutdown
T
VOUT
SHTDWN
CSOUT
STAT
V
CHARGE CONTROL,
TIMER and DISPLAY
LOGIC
Battery OVP
Low Battery
OUT
+
-
*
V
BATMAX
CD
V
BAT
+
-
*
OTG
V
BATMIN
PGND
PGND
PGND
(I2C Control)
Decoder
DAC
SCL
SDA
*
Signal Deglitched
Figure 18. Function Block Diagram of bq24157S in Boost Mode
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Functional Block Diagrams (continued)
High Impedance Mode or Host
Controlled Operation Mode
Power Up
V CSOUT < VLOWV
No
VBUS > VUVLO
POR
Load I2 C Registers
with Default Value
Yes
Disable Charge
/CE = LOW
/CE = HIGH
Any Charge State
Charge Configure
Mode
Disable Charge
Wait Mode
Indicate Power
not Good
Delay T
INT
Yes
No
Enable ISHORT
VCSOPUT <V SHORT
?
Yes
VBUS < VIN ( MIN
?
No
)
Indicate Short
Circuit condition
No
Regulate
Input Current, Charge
Current or Voltage
Indicate Charge-In -
Progress
Yes
VBUS < VIN ( MIN ) ?
Yes
Turn Off Charge
No
Enable IDETECT for
tDETECT
No
Battery Removed
VCSOUT
<
VOREG
?
-
Wait Mode
Delay TINT
Yes
Reset Charge
Parameters
VRCH
Yes
No
VCSOUT < VSHORT ?
Charge Complete
Indicate DONE
No
No
Yes
Termination Enabled
ITERM detected
VCSOUT < V OREG
VRCH
-
and VCSOUT >V OREG -VRCH
?
?
Yes
Figure 19. Operational Flow Chart of bq24157S in Charge Mode
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8.3 Feature Description
8.3.1 Input Voltage Protection
8.3.1.1 Input Overvoltage Protection
The IC provides built-in input overvoltage protection to protect the device and other components against damage
if the input voltage (voltage from VBUS to PGND) goes too high. When an input overvoltage condition is
detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT
pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and the charge process
resumes.
8.3.1.2 Bad Adaptor Detection/Rejection
Although not shown in Figure 20, at power-on-reset (POR) of VBUS, the IC performs the bad adaptor detection
by applying a current sink to VBUS. If the VBUS is higher than VIN(MIN) for 30 ms, the adaptor is good and the
charge process begins. If the VBUS drops below VIN(MIN), a bad adaptor is detected. Then, the IC disables the
current sink, sends a send fault pulse in FAULT pin, and sets the bad adaptor flag (B2 – B0 = 011 for register
00H). After a delay of TINT, the IC repeats the adaptor detection process, as shown in Figure 20 and Figure 21.
Adpator
V
VBUS
BUS
I
SHORT
(30 mA)
Adaptor Detection Control
V
IN_GOOD
Deglitch
30ms
PGND
START
Delay
GND
V
IN
T
V
INT
IN(MIN)
V
IN_POOR
Figure 20. Bad Adaptor Detection Circuit
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Feature Description (continued)
Charge Command
(Host Control or VBUS
Ramps Up)
Delay 10mS
Enable Adaptor Detection
Start 30ms Timer
Enable Input Current Sink
(30mA, to GND)
No
30ms Timer
Expired?
VBUS>VIN(MIN)
?
Yes
Yes
No
Good Adaptor Detected
Bad Adaptor Detected
Disable Adaptor Detection
Charge Start
Enable VIN Based DPM
Pulsing STAT Pin
Set Bad Adaptor Flag
Delay TINT
(2 Seconds)
Figure 21. Bad Adaptor Detection Scheme Flow Chart
8.3.1.3 Sleep Mode
The IC enters the low-power sleep mode if the VBUS pin voltage falls below the sleep-mode entry threshold,
VCSOUT + VSLP, and VBUS is higher than the bad adaptor detection threshold, VIN(MIN). This feature prevents
draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switch Q1 and
PWM are turned off.
8.3.1.4 Input Voltage Based DPM (Special Charger Voltage Threshold)
During the charging process, if the input power source is not able to support the programmed or default charging
current, the VBUS voltage will decrease. After the VBUS drops to VIN_DPM (default 4.52 V), the charge current
begins to taper down to prevent any further drop of VBUS. When the IC enters this mode, the charge current is
lower than the set value and the special charger bit is set (B4 in register 05H). This feature makes the IC
compatible with adapters having different current capabilities.
8.3.2 Battery Protection
8.3.2.1 Output Overvoltage Protection
The IC provides a built-in overvoltage protection to protect the device and other components against damage if
the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is
detected, the IC turns off the PWM converter, sets fault status bits, and sends out a fault pulse from the STAT
pin. When V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and the charge process
resumes.
16
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Feature Description (continued)
8.3.2.2 Battery Short Protection
During the normal charging process, if the battery voltage is lower than the short-circuit threshold, VSHORT, the
charger operates in short circuit mode with a lower charge rate of ISHORT
.
8.3.2.3 Battery Detection in HOST Mode
For applications with removable battery packs, the IC provides a battery absent detection scheme to reliably
detect insertion or removal of battery packs.
During the normal charging process with HOST control and termination enabled, when the voltage at the CSOUT
pin is above the battery recharge threshold, VOREG – VRCH, and the termination charge current is detected, the IC
turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT, (262-ms typical), then
checks the battery voltage. If the battery voltage is still above the recharge threshold after tDETECT, the battery is
present. On the other hand, if the battery voltage is below the battery recharge threshold, the battery is absent.
Under this condition, the charge parameters (such as input current limit) are reset to the default values and
charge resumes after a delay of tINT. This function ensures that the charge parameters are reset whenever the
battery is replaced.
8.3.3 DEFAULT Mode
After the battery and input bus voltages are removed from the IC and replaced, the bq24157S enters DEFAULT
mode until I2C communication begins.
8.3.4 USB Friendly Power Up
Prior to POR, if the host continues to write the TMR_RST bit to 1, to stay in HOST mode, then at POR, the
charger enters normal charge mode (using the desired control bits). If not in HOST mode at POR, the charge will
operate with default bit values, until the host updates the control registers.
The default control bits set the charging current and regulation voltage low as a safety feature to avoid violating
USB specifications and overcharging any of the Li-Ion chemistries, while the host has lost communication. The
input current limiting is described in the following sections.
8.3.5 Input Current Limiting at Power Up
The input current sensing circuit and control loop are integrated into the IC. When operating in DEFAULT mode,
the OTG pin logic level sets the input current limit to 100 mA for a logic low and 500 mA for a logic high. In
HOST mode, the input current limit is set by the programmed control bits in register 01H.
8.3.6 Factory Mode
The factory mode can be enabled only when the battery is removed. This can be done through an I2C register 05
bit 6 (see Table 9). The purpose of the mode is to operate the phone in a GSM phone call with no-battery
connected and do a calibration of the system. Setting the factory mode bit enables the following changes:
•
•
•
20X ICHG amp is disabled – that is, output current limit is disabled
Cycle-by-cycle HS current limit threshold is doubled (current typical is 2.4 A, shifts to 4.8 A)
CCM mode is always enabled (because the current could go from 0 to full GSM pulse)
8.3.7 Spread Spectrum Mode
The purpose of the spread spectrum clock modulation is to reduce EMI. In the spread spectrum mode, the
switching frequency is not fixed to 3 MHz. It is instead shifted by ±10% from the fixed 3-MHz switching
frequency. The shift is happening in eight steps, four steps in the upper range and four steps in the lower range
every 170 µs. By modulating the clock frequency, the energy of the switching converter’s EMI is distributed over
a wider range of frequencies thereby lowering the magnitude of EMI at 3 MHz ±10% as well as harmonic
frequencies.
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Feature Description (continued)
8.3.8 PWM Controller in Charge Mode
The IC provides an integrated, fixed 3-MHz frequency voltage-mode controller to regulate charge current or
voltage. This type of controller is used to improve line transient response, thereby, simplifying the compensation
network used for both continuous and discontinuous current conduction operation. The voltage and current loops
are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable
operation, allowing the use of small ceramic capacitors with a low ESR. The device operates between 0% to
99.5% duty cycles.
The IC has back-to-back common-drain N-channel FETs at the high side and one N-channel FET at the low side.
The input N-FET (Q1) prevents battery discharge when VBUS is lower than VCSOUT. The second high-side N-FET
(Q2) is the switching control switch. A charge pump circuit is used to provide gate drive for Q1, while a bootstrap
circuit with an external bootstrap capacitor is used to supply the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the FETs Q2 and Q3. The threshold for Q2 is set to a nominal 2.4-
A peak current. The low-side FET (Q3) also has a current limit that decides if the PWM controller will operate in
synchronous or non-synchronous mode. This threshold is set to 100 mA and it turns off the low-side N-channel
FET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used
when the current of the low-side FET is greater than 100 mA to minimize power losses.
8.3.9 Battery Charging Process
At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the IC applies a short-circuit
current, I(SHORT), to the battery. When the battery voltage is above VSHORT and below VOREG, the charge current
ramps up to fast charge current, IOCHARGE, or a charge current that corresponds to the input current of IIN_LIMIT
.
The slew rate for fast charge current is controlled to minimize the current and voltage overshoot during transient.
Both the input current limit, IIN_LIMIT, and fast charge current, IOCHARGE, can be set by the host. When the battery
voltage reaches the regulation voltage, VOREG, the charge current is tapered down, as shown in Figure 27. The
voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins.
In HOST mode, the regulation voltage is adjustable (3.5 to 4.44 V) and is programmed through I2C interface. In
DEFAULT mode, the regulation voltage is fixed at 3.54 V.
The IC monitors the charging current during the voltage regulation phase. If termination is enabled, during the
normal charging process with HOST control, after the voltage at the CSOUT pin is above the battery recharge
threshold, VOREG – VRCH for the 32-ms (typical) deglitch period, and the termination charge current ITERM is
detected, the IC turns off the PWM charge and enables a discharge current, IDETECT, for a period of tDETECT (262-
ms typical), then checks the battery voltage. If the battery voltage is still above the recharge threshold after
tDETECT, the battery charging is complete. The battery detection routine is used to ensure termination did not
occur because the battery was removed. After 40 ms (typical) for synchronization purposes of the EOC state and
the counter, the status bit and pin are updated to indicate charging has completed. The termination current level
is programmable. To disable the charge current termination, the host can set the charge termination bit (TE) of
charge control register to 0, refer to I2C Update Sequence for details.
A new charge cycle is initiated when one of the following conditions is detected:
•
•
•
The battery voltage falls below the V(OREG) – V(RCH) threshold.
VBUS POR, if battery voltage is below the V(LOWV) threshold.
CE bit toggle or RESET bit is set (host controlled)
8.3.10 Thermal Regulation and Protection
To prevent overheating of the chip during the charging process, the IC monitors the junction temperature, TJ, of
the die and begins to taper down the charge current after TJ reaches the thermal regulation threshold, TCF. The
charge current is reduced to 0 when the junction temperature increases approximately 10°C above TCF. In any
state, if TJ exceeds TSHTDWN, the IC suspends charging. In thermal shutdown mode, PWM is turned off and all
timers are frozen. Charging resumes when TJ falls below TSHTDWN by approximately 10°C.
18
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Feature Description (continued)
8.3.11 Charge Status Output, STAT Pin
The STAT pin is used to indicate operation conditions. STAT is pulled low during charging when EN_STAT bit in
control register (00H) is set to 1. Under other conditions, STAT pin behaves as a high impedance (open-drain)
output. Under fault conditions, a 128-µs pulse will be sent out to notify the host. The status of STAT pin at
different operation conditions is summarized in Table 2. The STAT pin can be used to drive an LED or
communicate to the host processor.
Table 2. STAT Pin Summary
Charge State
Stat
Charge in progress and EN_STAT = 1
Other normal conditions
Low
Open-drain
Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source, VBUS
UVLO, no battery, thermal shutdown
128-μs pulse, then open-drain
Boost mode faults: Timer fault, over load, VBUS or battery overvoltage, low battery voltage, thermal
shutdown
128-μs pulse, then open-drain
8.3.12 Control Bits in Charge Mode
8.3.12.1 CE Bit (Charge Mode)
The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit
enables the charge and a high logic level (1) disables the charge.
8.3.12.2 RESET Bit
The RESET bit in the Battery Termination/Fast Charge Current register is used to reset all the charge
parameters. Writing 1 to the RESET bit will reset all the charge parameters to default values except the safety
limit register, and RESET bit is automatically cleared to 0 when the charge parameters are reset. It is designed
for charge parameter reset before charge starts and TI does not recommended to set the RESET bit while
charging or boosting are in progress.
8.3.12.3 OPA_MODE Bit
OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger; if
HZ_MODE is set to 0, refer to Table 3 for details. When OPA_MODE = 1 and HZ_MODE = 0, the IC operates in
boost mode.
Table 3. Operation Mode Summary
OPA_MODE
HZ_MODE
Operation Mode
Charge (no fault)
0
0
Charge configure (fault, Vbus > UVLO)
High impedance (Vbus < UVLO)
Boost (no faults)
Any fault go to charge configure mode
1
0
1
X
High impedance
8.3.13 Control Pins in Charge Mode
8.3.13.1 CD Pin (Charge Disable)
The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD
pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.
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8.3.14 Boost Mode Operation
In HOST mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the
operation mode bit (OPA_MODE) is set to 1, the device operates in boost mode and delivers the power to VBUS
from the battery. In normal boost mode, the device converts the battery voltage to VBUS-B (about 5.05 V) and
delivers a current as much as IBO (about 375 mA for bq24157S) to support other USB OTG devices connected to
the USB connector.
8.3.14.1 PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode, the IC provides an integrated, fixed 3-MHz frequency voltage-
mode controller to regulate output voltage at PMID pin (VPMID). The voltage control loop is internally
compensated using a Type-III compensation scheme that provides enough phase margin for stable operation
with a wide load range and battery voltage range.
In boost mode, the input N-FET (Q1) prevents battery discharge when VBUS pin is over loaded. Cycle-by-cycle
current limit is sensed through the internal sense FET for Q3. The cycle-by-cycle current limit threshold for Q3 is
set to a nominal 1.0-A peak current. Synchronous operation is used in PWM mode to minimize power losses.
8.3.14.2 Boost Start Up
To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start
up.
8.3.14.3 PFM Mode at Light Load
In boost mode, under light load conditions, the IC operates in pulse skipping mode (PFM mode) to reduce the
power loss and improve the converter efficiency. During boosting, the PWM converter is turned off when the
inductor current is less than 75 mA, and the PWM is turned back on only when the voltage at PMID pin drops to
about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition between
PWM and PFM mode.
8.3.14.4 Protection in Boost Mode
8.3.14.4.1 Output Overvoltage Protection
The IC provides built-in overvoltage protection to protect the device and other components against damage if the
VBUS voltage goes too high. When an overvoltage condition is detected, the IC turns off the PWM converter,
resets OPA_MODE bit to 0, sets fault status bits, and sends out a fault pulse from the STAT pin. When VBUS
drops to the normal level, the boost starts after host sets OPA_MODE to 1 or OTG pin stays in active status.
8.3.14.4.2 Output Overload Protection
The IC provides built-in overload protection to prevent the device and battery from damage when VBUS is
overloaded. After the overload condition is detected, Q1 operates in linear mode to limit the output current. If the
overload condition lasts for more than 30 ms, the overload fault is detected. When an overload condition is
detected, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets fault status bits, and sends out
fault pulse in STAT pin. The boost will not start until the host clears the fault register.
8.3.14.4.3 Battery Overvoltage Protection
During boosting, when the battery voltage is above the battery overvoltage threshold, VBATMAX, or below the
minimum battery voltage threshold, VBATMIN, the IC turns off the PWM converter, resets OPA_MODE bit to 0, sets
fault status bits, and sends out fault pulse in STAT pin. After the battery voltage goes above VBATMIN, the boost
will start after the host sets OPA_MODE to 1 or OTG pin stays in active status.
8.3.14.5 STAT Pin in Boost Mode
During normal boosting operation, the STAT pin behaves as a high impedance (open-drain) output. Under fault
conditions, a 128-μs pulse is sent out to notify the host.
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8.3.15 High Impedance (Hi-Z) Mode
In Hi-Z mode, the charger stops charging and enters a low quiescent current state to conserve power. Taking the
CD pin high causes the charger to enter Hi-Z mode. When in DEFAULT mode and the CD pin is low, the charger
automatically enters Hi-Z mode if either:
•
•
VBUS > UVLO and a battery with VBAT > VLOWV is inserted, or
VBUS falls below UVLO.
When in HOST mode and the CD is low, the charger can be placed into Hi-Z mode if the HZ-MODE control bit is
set to 1 and OTG pin is not in active status.
To exit Hi-Z mode, the CD pin must be low, VBUS must be higher than UVLO, and the HOST must write a 0 to
the HZ-MODE control bit.
8.3.16 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, TI recommends that
SDA changes while SCL is low.
The data transfer protocol for standard and fast modes is the same; therefore, they are referred to as F/S-mode
in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-
mode. The bq24157S device supports 7-bit addressing only. The device 7-bit address is defined as 1101010
(6AH).
8.3.16.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 22. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 22. Start and Stop Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the Read or Write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 23). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device
with a matching address generates an acknowledge (see Figure 23) by pulling the SDA line low during the entire
high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link
with a slave has been established.
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DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 23. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 25). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from getting stuck in a bad state. Attempting to read data from register addresses not
listed in this section will result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
9
8
1
2
Clock Pulse for
Acknowledgement
START
Condition
Figure 24. Acknowledge on the I2C Bus
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Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
Sr
S
ACK
ACK
or
P
or
Sr
Clock Line Held Low While
Interrupts are Serviced
Figure 25. Bus Protocol
8.3.16.2 HS Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a START condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
The master then generates a repeated START condition (a repeated START condition has the same timing as
the start condition). After this repeated START condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A STOP condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a STOP condition, repeated
START conditions should be used to secure the bus in HS-mode. If a transaction is terminated prematurely, the
master needs to send a STOP condition to prevent the slave I2C logic from getting stuck in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
8.3.16.3 I2C Update Sequence
The IC requires a start condition, a valid I2C address, a register address byte, and a data byte for a single
update. After the receipt of each byte, the IC acknowledges by pulling the SDA line low during the high period of
a single clock pulse. A valid I2C address selects the IC. The IC performs an update on the falling edge of the
acknowledge signal that follows the LSB byte.
For the first update, the IC requires a START condition, a valid I2C address, a register address byte, and a data
byte. For all consecutive updates, the IC needs a register address byte and a data byte. When a STOP condition
is received, the IC releases the I2C bus and awaits new start conditions.
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S
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
Data Transferred
A
DATA
P
A/A
‘0’ (Write)
(n Bytes + Acknowledge)
From master to IC
A
A
= Acknowledge (SDA LOW)
= Not acknowledge (SDA
HIGH)
From IC to master
S
= START condition
Sr = Repeated START condition
= STOP condition
P
(a) F/S-Mode
F/S-Mode
F/S-Mode
HS-Mode
S
HS-MASTER CODE
Sr
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
P
A
A/A
Data Transferred
HS-Mode
‘0’ (write)
(n Bytes + Acknowledge)
Continues
Sr
Slave A.
(b) HS-Mode
Figure 26. Data Transfer Format In F/S Mode And HS Mode
8.3.16.4 Slave Address Byte
The slave address byte is the first byte received following the START condition from the master device.
MSB
LSB
1
X
1
1
0
1
0
1
8.3.16.5 Register Address Byte
Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which
contains the address of the register to be accessed. The IC contains five 8-bit registers accessible through a
bidirectional I2C-bus interface. Among them, four internal registers have read and write access; and one has only
read access.
MSB
0
LSB
D0
0
0
0
0
D2
D1
8.4 Device Functional Modes
8.4.1 Charge Mode Operation
8.4.1.1 Charge Profile
When a good battery with voltage below the recharge threshold has been inserted and a good adapter is
attached, the bq24157S enters charge mode. In charge mode, the IC has five control loops to regulate input
voltage, input current, charge current, charge voltage, and device junction temperature. During the charging
process, all five loops are enabled and the one that is dominant takes control. The IC supports a precision Li-ion
or Li-polymer charging system for single-cell applications. Figure 27 (a) indicates a typical charge profile without
input current regulation loop. It is the traditional CC/CV charge curve, while Figure 27 (b) shows a typical charge
profile when input current limiting loop is dominant during the constant current mode. In this case, the charge
current is higher than the input current, so the charge process is faster than the linear chargers. The input
voltage threshold for DPM loop, input current limits, charge current, termination current, and charge voltage are
all programmable using I2C interface.
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Device Functional Modes (continued)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
Voltage
Regulation
Current
Charge Voltage
VSHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
(a)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Voltage
VSHORT
Charge Current
Termination
ISHORT
Fast Charge
Precharge
(Linear Charge)
(PWM Charge)
(b)
Figure 27. Typical Charging Profile:
(a) Without Input Current Limit
(b) With Input Current Limit
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8.5 Register Maps
Table 4. Status/Control Register (Read or Write)
Memory Location: 00, Reset State: x1xx 0xxx
BIT
NAME
Read or Write
FUNCTION
Write: TMR_RST function, write 1 to reset the safety timer (auto clear)
Read: OTG pin status
0 – OTG pin at low level
B7 (MSB) TMR_RST/OTG Read or Write
1 – OTG pin at high level
0 – Disable STAT pin function
1 – Enable STAT pin function (default 1)
B6
B5
EN_STAT
STAT2
Read or Write
Read only
00 – Ready
01 – Charge in progress
10 – Charge done
11 – Fault
B4
STAT1
Read only
B3
B2
B1
BOOST
FAULT_3
FAULT_2
Read only
Read only
Read only
1 – Boost mode, 0 – Not in boost mode
Charge mode:
000 – Normal
001 – VBUS OVP
010 – Sleep mode
011 – Bad Adaptor or VBUS < VUVLO
100 – Output OVP
101 – Thermal shutdown
110 – Timer fault
111 – No battery
Boost mode:
000 – Normal
B0 (LSB)
FAULT_1
Read only
001 – VBUS OVP
010 – Overload
011 – Battery voltage is too low
100 – Battery OVP
101 – Thermal shutdown
110 – Timer fault
111 – N/A
Table 5. Control Register (Read or Write)
Memory Location: 01, Reset State: 0011 0000
BIT
NAME
Read or Write
FUNCTION
B7 (MSB)
Iin_Limit_2
Read or Write
00 – USB host with 100-mA current limit
01 – USB host with 500-mA current limit
10 – USB host/charger with 800-mA current limit
11 – No input current limit
B6
Iin_Limit_1
Read or Write
(1)
B5
B4
V(LOWV_2)
Read or Write
Read or Write
Weak battery voltage threshold: 200-mV step (default 1)
Weak battery voltage threshold: 100-mV step (default 1)
(1)
V(LOWV_1)
1 – Enable charge current termination
0 – Disable charge current termination (default 0)
B3
B2
TE
CE
Read or Write
Read or Write
Read or Write
Read or Write
1 – Charger is disabled
0 – Charger enabled (default 0)
1 – High impedance mode
0 – Not high impedance mode (default 0)
B1
HZ_MODE
1 – Boost mode
0 – Charger mode (default 0)
B0 (LSB)
OPA_MODE
(1) The range of the weak battery voltage threshold (V(LOWV)) is 3.4 to 3.7 V with an offset of 3.4 V and steps of 100 mV (default 3.7 V,
using bits B4 to B5).
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Table 6. Control/Battery Voltage Register (Read or Write)
Memory Location: 02, Reset State: 0000 1010(1)
BIT
B7 (MSB)
B6
NAME
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
FUNCTION
Battery Regulation Voltage: 640-mV step (default 0)
Battery Regulation Voltage: 320-mV step (default 0)
Battery Regulation Voltage: 160-mV step (default 0)
Battery Regulation Voltage: 80-mV step (default 0)
Battery Regulation Voltage: 40-mV step (default 1)
Battery Regulation Voltage: 20-mV step (default 0)
VO(REG5)
VO(REG4)
VO(REG3)
VO(REG2)
VO(REG1)
VO(REG0)
B5
B4
B3
B2
1 – OTG boost enable with high level
B1
OTG_PL
OTG_EN
Read or Write
Read or Write
0 – OTG boost enable with low level (default 1); not applicable to OTG pin control of
current limit at POR in DEFAULT mode
1 – Enable OTG Pin in HOST mode
0 – Disable OTG pin in HOST mode (default 0), not applicable to OTG pin control of
current limit at POR in DEFAULT mode
B0 (LSB)
(1) Charge voltage range is 3.5 to 4.44 V with the offset of 3.5 V and steps of 20 mV (default 3.54 V), using bits B2 to B7.
Table 7. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0101 000x
BIT
B7 (MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
Read or Write
Read only
Read only
Read only
Read only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
B5
B4
For I2C Address 6AH:
01–N/A
10–bq24157S
11–N/A
B3
PN0
Read only
B2
B1
Revision2
Revision1
Revision0
Read only
Read only
Read only
011: Revision 1.0;
001: Revision 1.1;
100 – 111: Future Revisions
B0 (LSB)
Table 8. Battery Termination/Fast Charge Current Register (Read or Write)
Memory Location: 04, Reset State: 0000 0001(1)
BIT
NAME
Read or Write
FUNCTION
Write:
B7 (MSB)
Reset
Read or Write
1 – Charger in reset modes
0 – No effect, Read: always get 0
(2)
(2)
(2)
(2)
(3)
(3)
(3)
B6
B5
VI(CHRG3)
VI(CHRG2)
VI(CHRG1)
VI(CHRG0)
VI(TERM2)
VI(TERM1)
VI(TERM0)
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Charge current sense voltage: 27.2-mV step
Charge current sense voltage: 13.6-mV step
Charge current sense voltage: 6.8-mV step
N/A
B4
B3
B2
Termination current sense voltage: 13.6-mV step (default 0)
Termination current sense voltage: 6.8-mV step (default 0)
Termination current sense voltage: 3.4-mV step (default 1)
B1
B0 (LSB)
(1) Charge current sense voltage offset is 37.4 mV and default charge current is 550 mA, if 68-mΩ sensing resistor is used and
LOW_CHG = 0.
(2) See Table 13
(3) See Table 12
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Table 9. Special Charger Voltage/Enable Pin Status Register
Memory Location: 05, Reset state: 000X X100(1) (2)
BIT
NAME
Read or Write
FUNCTION
B7 (MSB)
NA
Read or Write
NA
0 – Disables factory test mode
1 – Enables the factory test mode
B6
B5
B4
B3
FAC_MODE
LOW_CHG
Read or Write
Read or Write
Read only
0 – Normal charge current sense voltage at 04H,
1 – Low charge current sense voltage of 22.1 mV (default 0)
0 – DPM mode is not active,
1 – DPM mode is active
DPM_STATUS
CD_STATUS
0 – CD pin at LOW level,
1 – CD pin at HIGH level
Read only
B2
B1
VSREG2
VSREG1
VSREG0
Read or Write
Read or Write
Read or Write
Special charger voltage: 320mV step (default 1)
Special charger voltage: 160mV step (default 0)
Special charger voltage: 80mV step (default 0)
B0 (LSB)
(1) Special charger voltage offset is 4.2 V and default special charger voltage is 4.52 V.
(2) Default charge current will be 550 mA, if 68-mΩ sensing resistor is used, since default LOW_CHG = 0.
Table 10. Safety Limit Register (Read or Write, Write Only One Time After Reset)
Memory Location: 06, Reset State: 01000000
BIT
B7 (MSB)
B6
NAME
VMCHRG3
VMCHRG2
VMCHRG1
VMCHRG0
VMREG3
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
FUNCTION
(1)
(1)
(1)
(1)
(2)
Maximum charge current sense voltage: 54.4-mV step (default 0)
Maximum charge current sense voltage: 27.2-mV step (default 1)
Maximum charge current sense voltage: 13.6-mV step (default 0)
Maximum charge current sense voltage: 6.8-mV step (default 0)
Maximum battery regulation voltage: 160-mV step (default 0)
Maximum battery regulation voltage: 80-mV step (default 0)
Maximum battery regulation voltage: 40-mV step (default 0)
Maximum battery regulation voltage: 20-mV step (default 0)
B5
B4
B3
B2
VMREG2
B1
VMREG1
B0 (LSB)
VMREG0
(1) Refer to Table 13
SPACE
•
•
•
Maximum charge current sense voltage offset is 37.4 mV (550 mA), default at 64.6 mV (950 mA) and the
maximum charge current option is 1.55 A (105.4 mV), if 55-mΩ sensing resistor is used.
Maximum battery regulation voltage offset is 4.2 V (default at 4.2 V) and maximum battery regulation voltage
option is 4.44 V.
Memory location 06H resets only when V(CSOUT) drops below either 1) V(SHORT) threshold (typical 2.05 V) if
VBUS>V(UVLO) or 2) the digital reset threshold (typ 2.4V) if VBUS<V(UVLO). After reset, the maximum
values for battery regulation voltage and charge current can be programmed until any writing to other register
locks the safety limits. Programmed values exclude higher values from memory locations 02 (battery
regulation voltage), and from memory location 04 (fast charge current).
•
If host accesses (write command) to some other register before safety limit register, the safety default values
are used.
28
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Not Recommended for New Designs
bq24157S
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq24157S is a compact, flexible, high-efficiency, USB-friendly, switch-mode charge management solution for
single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The bq24157S integrates
a synchronous PWM controller, power MOSFETs, input current sensing, high-accuracy current and voltage
regulation, and charge termination, into a small DSBGA package. The charge parameters can be programmed
through an I2C interface.
9.2 Typical Application
VBUS = 5 V, ICHARGE = 1250 mA, VBAT = 3.5 to 4.44 V (adjustable).
L
1 mH
RSNS
O
VBAT
VBUS
VBUS
SW
CO1
CIN
CO2
33 mF
CBOOT
33 nF
U1
1 mF
22 mF
bq24157S
BOOT
PGND
PMID
CIN
PACK+
4.7 mF
CCSIN
+
VAUX
10 kW
0.1 mF
CSIN
2
I C BUS
10 kW
10 kW
10 kW
PACK–
CSOUT
SCL
SCL
SDA
STAT
SDA
CCSOUT
0.1 mF
STAT
SLRST
VREF
SLRST
CVREF
CD
10 kW
CD
1 mF
10 kW
HOST
Figure 28. I2C Controlled 1-Cell USB Charger Application Circuit With USB-OTG Support
9.2.1 Design Requirements
Use the following typical application design procedure to select external components values for the bq24157S
device.
Specification
Test Condition
MIN
4
TYP
5
MAX
6
UNIT
V
Input DC voltage, VIN
Input current
Input voltage from AC adapter input
Maximum input current from AC adapter input
Battery charge current
0.1
0.325
0
0.1 to 0.5
0.7
1.5
A
Charge current
1.55
4.44
125
A
Output regulation voltage
Voltage applied at VBAT
3 to 4.2
V
Operating junction temperature range, TJ
0
°C
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9.2.2 Detailed Design Procedure
Systems design specifications:
•
•
•
•
VBUS = 5 V
VBAT = 4.2 V (1 cell)
I(charge) = 1.25 A
Inductor ripple current = 30% of fast charge current
SPACE
1. Determine the inductor value (LOUT) for the specified charge current ripple:
VBAT ´ (VBUS - VBAT)
L
=
OUT
VBUS ´ f ´ DI
L
, the worst case is when battery voltage is as close as to half of the input
voltage.
2.5 ´ (5 - 2.5)
L
=
OUT
6
5 ´ (3 ´ 10 ) ´ 1.25 ´ 0.3
(1)
LOUT = 1.11 μH
Select the output inductor to standard 1 μH. Calculate the total ripple current with using the 1-μH inductor:
VBAT ´ (VBUS - VBAT)
DI =
L
VBUS ´ f ´ L
OUT
(2)
(3)
2.5 ´ (5 - 2.5)
DI =
L
6
-6
5 ´ (3 ´ 10 ) ´ (1 ´ 10
)
ΔIL = 0.42 A
Calculate the maximum output current:
DI
L
I
= I +
OUT
LPK
2
0.42
2
(4)
(5)
I
= 1.25 +
LPK
ILPK = 1.46 A
Select 2.5-mm by 2-mm, 1-μH, 1.5-A surface mount multi-layer inductor. The suggested inductor part
numbers are shown in Table 11.
Table 11. Inductor Part Numbers
Part Number
LQM2HPN1R0MJ0
MIPS2520D1R0
MDT2520-CN1R0M
CP1008
Inductance
1 μH
Size
Manufacturer
Murata
2.5 × 2.0 mm
2.5 × 2.0 mm
2.5 × 2.0 mm
2.5 × 2.0 mm
1 μH
FDK
1 μH
TOKO
1 μH
Inter-Technical
2. Determine the output capacitor value (COUT) using 40 kHz as the resonant frequency:
1
f
=
o
2p ´
L
´ C
OUT
OUT
(6)
(7)
1
C
=
OUT
2
4p ´ f
2
´ L
0
OUT
1
C
=
OUT
2
3 2
-6
4p ´ (40 ´ 10 ) ´ (1 ´ 10 )
(8)
30
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
COUT = 15.8 μF
Select two 0603 X5R 6.3-V 10-μF ceramic capacitors in parallel, that is, Murata GRM188R60J106M.
3. Determine the sense resistor using Equation 9:
V
(RSNS)
R
=
(SNS)
I
(CHARGE)
(9)
The maximum sense voltage across the sense resistor is 85 mV. To get a better current regulation accuracy,
V(RSNS) should equal 85 mV, and calculate the value for the sense resistor.
85mV
R
=
(SNS)
1.25A
(10)
R(SNS) = 68 mΩ
This is a standard value. If it is not a standard value, then choose the next close value and calculate the real
charge current. Calculate the power dissipation on the sense resistor:
P(RSNS) = I(CHARGE) 2 × R(SNS)
P(RSNS) = 1.252 × 0.068
P(RSNS) = 0.106 W
Select 0402 0.125-W 68-mΩ 2% sense resistor, that is, Panasonic ERJ2BWGR068.
For 1.5A application, R(SNS)= 85mV/1.55A = 55 mΩ
4. Measured efficiency and total power loss with different inductors are shown in Figure 29. SW node and
inductor current waveform are shown in Figure 37.
Battery Charge Efficiency
Battery Charge Loss
90
89
88
87
86
85
84
83
82
800
700
600
500
400
300
200
100
TA = 25°C
TA = 25°C
VBUS = 5 V
VBAT = 3 V
VBUS = 5 V
VBAT = 3 V
FDK
FDK
TOKO
TOKO
Inter-Technical
muRata
Inter-Technical
muRata
500
600
700
800
900 1000 1100 1200 1300
500
600
700
800
900 1000 1100 1200 1300
Charge Current (mA)
Charge Current (mA)
Figure 29. Measured Efficiency and Power Loss
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9.2.2.1 Charge Current Sensing Resistor Selection Guidelines
Both the termination current range and charge current range depend on the sensing resistor (RSNS). The
termination current step (IOTERM_STEP) can be calculated using Equation 11.
V
I(TERM0)
I
=
O(TERM_STEP)
R
(SNS)
(11)
Table 12 shows the termination current settings for three sensing resistors.
Table 12. Termination Current Settings for 55-mΩ, 68-mΩ, and 100-mΩ Sense Resistors
I(TERM) (mA)
R(SNS) = 55 mΩ
I(TERM) (mA)
R(SNS) = 68 mΩ
I(TERM) (mA)
R(SNS) = 100 mΩ
BIT
VI(TERM) (mV)
VI(TERM2)
VI(TERM1)
VI(TERM0)
Offset
13.6
6.8
247
124
62
200
100
50
136
68
3.4
34
3.4
62
50
34
For example, with a 68-mΩ sense resistor, V(ITERM2) = 1, V(ITERM1) = 0, and V(ITERM0) = 1, ITERM = [(13.6 mV × 1) +
(6.8 mV × 0) + (3.4 mV × 1) + 3.4 mV] / 68 mΩ = 200 mA + 0 + 50 mA + 50 mA = 300 mA.
The charge current step (IO(CHARGE_STEP)) is calculated using Equation 12.
V
I(CHRG0)
I
=
O(CHARGE_STEP)
R
(SNS)
(12)
Table 13 shows the charge current settings for three sensing resistors.
Table 13. Charge Current Settings for 55-mΩ, 68-mΩ, and 100-mΩ Sense Resistors
IO(CHARGE) (mA)
R(SNS) = 55 mΩ
IO(CHARGE) (mA)
R(SNS) = 68 mΩ
IO(CHARGE) (mA)
R(SNS) = 100 mΩ
BIT
VI(REG) (mV)
VI(CHRG3)
VI(CHRG2)
VI(CHRG1)
VI(CHRG0)
Offset
54.4
27.2
13.6
6.8
989
495
247
124
680
800
400
200
100
550
544
272
136
68
37.4
374
For example, with a 68-mΩ sense resistor, V(CHRG3) = 1, V(CHRG2) = 0, V(ICHRG1) = 0, and V(ICHRG0) = 1, ITERM
=
[(54.4 mV × 1) + (27.2 mV × 0) + (13.6 mV × 0) + (6.8 mV × 1) + 37.4 mV] / 68 mΩ = 800 mA + 0 + 0 + 100 mA
= 900 mA.
9.2.2.2 Output Inductor and Capacitance Selection Guidelines
The IC provides internal loop compensation. With the internal loop compensation, the highest stability occurs
when the LC resonant frequency, ƒo, is approximately 40 kHz (20 to 80 kHz). Equation 13 can be used to
calculate the value of the output inductor, LOUT, and output capacitor, COUT
.
1
f
=
o
2p ´
L
´ C
OUT
OUT
(13)
To reduce the output voltage ripple, TI recommends a ceramic capacitor with the capacitance between 4.7 to 47
μF for COUT. See previous sections in the Detailed Design Procedure for components selection.
32
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
9.2.3 Application Curves
V(VBUS)
V(VBUS)
V(VBUS)
2 V/div
V(VBUS)
2 V/div
V(BAT)
V(BAT)
V(BAT)
V(BAT)
V(SW)
2 V/div
2 V/div
V(SW)
V(SW)
2 V/div
V(SW)
2 V/div
I(BAT)
I(BAT)
I(BAT)
500 mA/div
I(BAT)
500 mA/div
100 ms/div
1 s/div
VBUS = 0 to 5 V
VBAT = 3.5 V
IIN_limit = 500 mA
VBATREG = 4.2 V
VBUS = 5 V
VBAT = 3.5 V
IIN_limit = 500 mA
ICHG = 550 mA
VBATREG = 4.2 V
ICHG = 550 mA
Termination Enabled
Figure 30. Adapter Insertion (HOST Mode)
Figure 31. Battery Insertion/Removal Termination Enabled
(HOST Mode)
VSW
V(VBUS)
2 V/div
V(VBUS)
VSW
2 V/div
V(BAT)
V(SW)
V(BAT)
2 V/div
V(SW)
IND
2 V/div
I Inductor
500 ms/div
I(BAT)
I(BAT)
500 mA/div
1 s/div
200 ns/div
VBUS = 5 V
VBAT = 3.5 V
IIN_limit = 500 mA
VBUS = 5 V
VBAT = 2.6 V
VOREG = 4.2 V
VBATREG = 4.2 V
ICHG = 550 mA
Termination
Enabled
ICHG = 950 mA
Figure 33. PWM Charging Waveforms
Figure 32. Battery Insertion/Removal Termination Disabled
(HOST Mode)
VBUS
AC Coupled
VBUS
100 mV/div
VBAT
VBAT
2 V/div
VBAT
AC Coupled
VBAT
100 mV/div
IBAT
VSW
2 V/div
VSW
IBAT
1 A/div
I Inductor
200 mA/div
IND
100 ns/div
200 μs/div
VBUS = 5.05 V
VBAT = 3.5 V
IBUS = 217 mA
5.5-V input voltage
Figure 34. Boost Waveform (PWM Mode)
Figure 35. Step Load from 0 to 2 A During Factory Mode
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
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10 Power Supply Recommendations
10.1 System Load After Sensing Resistor
One of the simpler high-efficiency topologies connects the system load directly across the battery pack, as
shown in Figure 36. The input voltage has been converted to a usable system voltage with good efficiency from
the input. When the input power is on, it supplies the system load and charges the battery pack at the same time.
When the input power is off, the battery pack powers the system directly.
SW
VBUS
Isns
Isys
Ichg
L1
Rsns
VIN
+
-
bq2415x
System
Load
+
C3
C4
BAT
C1
PMID
C2
PGND
Figure 36. System Load After Sensing Resistor
The advantages:
1. When the AC adapter is disconnected, the battery pack powers the system load with minimum power
dissipation. Consequently, the time that the system runs on the battery pack can be maximized.
2. It reduces the number of external path selection components and offers a low-cost solution.
3. Dynamic power management (DPM) can be achieved. The total of the charge current and the system current
can be limited to a desired value by setting the charge current value. When the system current increases, the
charge current drops by the same amount. As a result, no potential overcurrent or overheating issues are
caused by excessive system load demand.
4. The total input current can be limited to a desired value by setting the input current limit value. USB
specifications can be met easily.
5. The supply voltage variation range for the system can be minimized.
6. The input current soft-start can be achieved by the generic soft-start feature of the IC.
Design considerations and potential issues:
1. If the system always demands a high current (but lower than the regulation current), the battery charging
never terminates. Thus, the battery is always charged, and its lifetime may be reduced.
2. Because the total current regulation threshold is fixed and the system always demands some current, the
battery may not be charged with a full-charge rate and thus may lead to a longer charge time.
3. If the system load current is large after the charger has been terminated, the IR drop across the battery
impedance may cause the battery voltage to drop below the refresh threshold and start a new charge cycle.
The charger would then terminate due to low charge current. Therefore, the charger would cycle between
charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,
resulting in a much slower cycling.
4. In a charger system, the charge current is typically limited to about 30 mA, if the sensed battery voltage is
below the 2-V short circuit protection threshold. This results in low power availability at the system bus. If an
external supply is connected and the battery is deeply discharged below the short circuit protection threshold,
the charge current is clamped to the short circuit current limit. This then is the current available to the system
during the power-up phase. Most systems cannot function with such limited supply current, and the battery
supplements the additional power required by the system. Note that the battery pack is already at the
depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown.
5. If the battery is below the short circuit threshold and the system requires a bias current budget lower than the
short circuit current limit, the end-equipment will be operational, but the charging process can be affected
34
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Not Recommended for New Designs
bq24157S
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
System Load After Sensing Resistor (continued)
depending on the current left to charge the battery pack. Under extreme conditions, the system current is
close to the short circuit current levels and the battery may not reach the fast-charge region in a timely
manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.
Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the
application possible.
6. If the battery pack voltage is too low, highly depleted, totally dead or even shorted, the system voltage is
clamped by the battery and it cannot operate even if the input power is on.
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11 Layout
11.1 Layout Guidelines
Give special attention to the PCB layout. The following list provides guidelines:
•
To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the pin. The output inductor should be placed close to the IC and the output capacitor
connected between the inductor and PGND of the IC. The intent is to minimize the current path loop area
from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical (see Figure 37). The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other
on adjacent layers (do not route the sense leads through a high-current path, see Figure 38).
•
•
Place all decoupling capacitors close to their respective IC pins and close to PGND (do not place components
such that routing interrupts power stage currents). All small control signals should be routed away from the
high current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, and one via per capacitor for
small-signal components). A star ground design approach is typically used to keep circuit block currents
isolated (high-power/low-power small-signal), which reduces noise-coupling and ground-bounce issues. A
single ground plane for this design gives good results. With this small layout and a single ground plane, there
is no ground-bounce issue, and having the components segregated minimizes coupling between signals.
•
•
The high-current charge paths into VBUS, PMID, and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
Place 4.7-μF input capacitor as close to PMID pin and PGND pin as possible to make the high frequency
current loop area as small as possible. Place 1-μF input capacitor as close to VBUS pin and PGND pin as
possible to make high frequency current loop area as small as possible (see Figure 39).
11.2 Layout Example
L1
R1
V
VBUS
BAT
SW
High
Frequency
BAT
V
IN
Current
Path
PMID
C2
PGND
C3
C1
Figure 37. High Frequency Current Path
36
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
Layout Example (接下页)
Charge Current Direction
R
SNS
To Inductor
To Capacitor and battery
Current Sensing Direction
To CSIN and CSOUT pin
Figure 38. Sensing Resistor PCB Layout
VBUS
PMID
Vin+
1µF
SW
Vin–
4.7µF
PGND
Figure 39. Input Capacitor Position and PCB Layout Example
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37
Not Recommended for New Designs
bq24157S
ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 文档支持
12.2.1 相关文档
《bq24157S 用户指南》(SLUU453)
12.3 商标
NanoFree is a trademark of Texas Instruments.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
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ZHCSCJ9B –FEBRUARY 2013–REVISED MAY 2015
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
13.1 封装概要
DSBGA Package
(Top View)
Chip Scale Package
(Top Side Symbol)
A1
B1
C1
A2
B2
A3
B3
C3
A4
B4
TIYMLLLLS
bq24157S
C2
C4
D
D1
E1
D2
E2
D3
E3
D4
E4
E
0 引脚 A1 标记，TI-TI 字符，YM = 年月日日期代码，LLL = 批次追踪代码，S = 组装地点代码
13.1.1 芯片尺寸级封装尺寸
bq24157S 器件采用 20 焊锡凸块芯片尺寸封装 (DSBGA， NanoFree™)。
封装尺寸为：
D
E
最大值 = 2.17mm
最小值 = 2.11mm
最大值 = 2.03mm
最小值 = 1.97mm
版权 © 2013–2015, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ24157SYFFR
BQ24157SYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
20
20
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
BQ24157S
BQ24157S
Samples
Samples
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2022
Addendum-Page 2
D: Max = 2.172 mm, Min =2.112 mm
E: Max = 2.03 mm, Min = 1.97 mm
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