BQ24160ARGER [TI]

具有双输入、电源路径且无 WD 的 I2C 单节 2.5A 降压电池充电器 | RGE | 24 | 0 to 125;


型号：	BQ24160ARGER
厂家：	TEXAS INSTRUMENTS
描述：	具有双输入、电源路径且无 WD 的 I2C 单节 2.5A 降压电池充电器 \| RGE \| 24 \| 0 to 125 电池
文件：	总54页 (文件大小：4022K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

BQ2416xx 具有电源路径管理功能和I²C 接口的2.5A、双输出、单芯开关模式

锂离子电池充电器

1 特性

3 说明

• 具有独立电源路径控制的高效开关模式充电器

– 从深度放电电池或者在无电池的情况下快速启动

系统

• 与BQ27530 搭配使用时可与MaxLife™ 技术兼

容，从而实现更快的充电速度

BQ24160 、BQ24160A 、BQ24161 、BQ24161B 、

BQ24163 和 BQ24168 是高度集成的单芯锂离子电池

充电器和系统电源路径管理器件，旨在用于空间有限且

具有高容量电池的便携式应用。此单芯充电器具有双输

入，可由 USB 端口或更高功率的输入电源（即交流适

配器或无线充电输入）供电，适用于多用途解决方案。

这两个输入彼此完全隔离，并可以使用I²C 接口方便地

进行选择。

• 双输入、集成式FET 充电器，充电电流高达2.5A

– 20V 输入额定值，具有过压保护(OVP)

• USB 输入为6.5V，电流高达1.5A

• IN 输入为10.5V，电流高达2.5A

（BQ24160、BQ24160A、BQ24161、

BQ24163）

凭借电源路径管理功能，BQ2416xx 能够在对电池进行

独立充电的同时通过一个高效的直流/直流转换器为系

统供电。电源路径管理架构使该系统能够在电池包有缺

陷或缺失的情况下运行，并且即使在电池完全放电或者

无电池的情况下也可实现即时系统启动。

• IN 输入为6.5V，电流高达2.5A (BQ24168)

• 安全且准确的电池管理功能

– 电池调节精度为1%

– 充电电流精度为10%

• 可使用I²C 接口对充电参数编程

• 基于电压的NTC 监控输入

器件信息

封装⁽¹⁾

封装尺寸（标称值）

4.00mm × 4.00mm

2.80mm × 2.80mm

器件型号

BQ2416xx

VQFN (24)

DSBGA (49)

– 符合JEITA 标准（BQ24160、BQ24160A、

BQ24161B、BQ24163、BQ24168）

• 采用小型2.8mm × 2.8mm 49 焊球WCSP 或4mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

× 4mm VQFN-24 封装

2 应用

• 手持产品

• 便携式媒体播放器

• 便携式设备

• 上网本和便携式互联网设备

应用原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSAO0

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

Table of Contents

8.5 Programming............................................................ 27

8.6 Register Maps...........................................................29

9 Application and Implementation..................................34

9.1 Application Information............................................. 34

9.2 Typical Application.................................................... 34

10 Power Supply Recommendations..............................38

10.1 Requirements for SYS Output................................ 38

10.2 Requirements for Charging.....................................38

11 Layout...........................................................................39

11.1 Layout Guidelines................................................... 39

11.2 Layout Example...................................................... 40

12 Device and Documentation Support..........................41

12.1 Device Support....................................................... 41

12.2 接收文档更新通知................................................... 41

12.3 支持资源..................................................................41

12.4 Trademarks.............................................................41

12.5 Electrostatic Discharge Caution..............................41

12.6 术语表..................................................................... 41

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 Handling Ratings.........................................................7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Electrical Characteristics.............................................8

7.6 Typical Characteristics.............................................. 11

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision G (November 2015) to Revision H (July 2022)

Page

• Changed I_TERMspecification...............................................................................................................................8

Changes from Revision F (July 2014) to Revision G (November 2015)

Page

• Deleted hyperlink to unpublished application note SLUA727...........................................................................26

Changes from Revision E (November 2013) to Revision F (January 2014)

Page

• 添加了处理额定值表、特性说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器

件和文档支持部分以及机械、封装和可订购信息部分.......................................................................................1

• Changed the Ordering Information table to the Device Comparison Table........................................................ 4

• Changed to V_{BAD_SOURCE}include values for "During Bad Source Detection"....................................................8

• Changed the Functional Block Diagram. Changed the device numbers above D+/D- and PSEL....................14

• Changed the PWM Controller in Charge Mode section to include the soft-start function.................................15

• Changed the Battery Charging Process section. New text added starting with "The BQ2416xx monitors the

charging current..".............................................................................................................................................16

• Changed the Input Source Connected section.................................................................................................17

• Changed the Input Source Connected section.................................................................................................19

• Added the Reverse Boost (Boost Back) Prevention Circuit section................................................................. 25

Changes from Revision D (November 2012) to Revision E (November 2013)

Page

• 添加了特性：与BQ27530 搭配使用时可与MaxLife 技术兼容，从而实现更快的充电速度................................ 1

• 在整个数据表中将QFN-24 封装更改为VQFN-24 封装......................................................................................1

Changes from Revision C (October 2012) to Revision D (November 2012)

Page

• Changed the Ordering Information table to include the WSCP package for BQ24161BRGR and

BQ24161BYFF................................................................................................................................................... 4

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

Changes from Revision B (September 2012) to Revision C (October 2012)

Page

• Changed the Ordering Information table to include BQ24160A......................................................................... 4

Changes from Revision A (March 2012) to Revision B (September 2012)

Page

• Changed the Ordering Information table to include BQ24161B......................................................................... 4

• Changed text From: "battery FET (Q6)" To: "battery FET (Q4)" in the Battery Only Connected section..........18

• Changed From: V_WARM< V_TS< V_HOTTo: V_WARM> V_TS> V_HOT, and Changed From: V_COLD< V_TS< V_COOLTo:

V_COLD> V_TS> V_COOLin the External NTC Monitoring (TS) section................................................................. 21

• Changed 图11-1 ..............................................................................................................................................40

Changes from Revision * (November 2011) to Revision A (March 2012)

Page

• Changed the USB Pin numbers in the YFF pachkage for bq24160/3 From: A5-A6 To: A5-A7..........................4

• Changed V_BATREG- Voltage regulation accuracy ...............................................................................................8

• Changed 图9-1 ............................................................................................................................................... 34

• Changed 图9-2 ............................................................................................................................................... 34

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

5 Device Comparison Table

TIMERS

(Safety and

Watchdog)

NTC

MONITORING

V_BATSHRT/

I_BATSHRT

PART NUMBER^{(1) (2)}

USB OVP

IN OVP

USB DETECTION

V_MINSYS

3.0V

50mA

BQ24160

6.5V

10.5V

6.5V

Yes

JEITA

3.5V

3.2V

3.5V

D+/D–

3.0V

50mA

BQ24160A

BQ24161

BQ24161B

BQ24163

BQ24168

PSEL (0=1.5A,

1=100mA)

2.0V

50mA

Yes

Standard

JEITA

PSEL (0=1.5A,

1=500mA)

3.0V

50mA

2.0V

50mA

JEITA

D+/D–

PSEL (0=1.5A,

1=100mA)

2.0V

50mA

JEITA

(1) Each of the above are available in as YFF and RGE packages with the following options:

R - tabed and reeled in quantities of 3,000 devices per reel.

T - taped and reeled in quantities of 250 devices per reel.

(2) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for

use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including

bromine (Br) or antimony (Sb) above 0.1% of total product weight.

6 Pin Configuration and Functions

18 SW

D-

N.C.

18 SW

PGND

SGND

D+

PSEL

SCL

PGND

SGND

PGND

SYS

SCL

BQ24161

BQ24161B

BQ241618

BQ24160

BQ24163

PGND

SDA

PGND

DRV

SDA

GND

DRV

14 SYS

SYS

图6-1. RGE Package VQFN 24 Pins Top View

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

BQ24161

BQ24161B

BQ24168

BQ24160

BQ24163

(Top View)

PMIDI

USB

PMIDI

PMIDU

PMIDI

PMIDU

PGND

BOOT

PGND

BOOT

PGND

PSEL

N.C.

PGND

D+

D-

SDA

SCL

SDA

SCL

SYS

BAT

SYS

BAT

SYS

BAT

BGATE

INT

DRV

SYS

BAT

SYS

BAT

SYS

BAT

SYS

BAT

BGATE

INT

DRV

BAT

STAT

PGND

STAT

PGND

图6-2. YFF Package WCSP 49 Pins Top View

表6-1. Pin Functions

NO.

BQ24160, 3

NO.

I/O

DESCRIPTION

BQ24161, 1B, 8

NAME

YFF RGE

YFF

RGE

BAT

G1-G4

11, 12

G1-G4

11, 12

I/O

Battery Connection –Connect to the positive terminal of the battery. Additionally, bypass BAT

to GND with at least a 1-μF capacitor.

BGATE

External Discharge MOSFET Gate Connection –BGATE drives an external P-Channel

MOSFET to provide a very low-resistance discharge path. Connect BGATE to the gate of the

external MOSFET. BGATE is low during high impedance mode and when no input is connected.

BOOT

High Side MOSFET Gate Driver Supply –Connect a 0.01-µF ceramic capacitor (voltage

rating > 10 V) from BOOT to SW to supply the gate drive for the high side MOSFETs.

IC Hardware Chip Disable Input –Drive CD high to place the BQ2416xx in high-z mode.

Drive CD low for normal operation. Do not leave CD unconnected.

D+

—

D+ and D–Connections for USB Input Adapter Detection –When a charge cycle is

initiated by the USB input, and a short is detected between D+ and D–, the USB input current

limit is set to 1.5 A. If a short is not detected, the USB100 mode is selected. The D+/D–

detection has no effect on the IN input.

D–

DRV

Gate Drive Supply –DRV is the bias supply for the gate drive of the internal MOSFETs.

Bypass DRV to PGND with a 1-μF ceramic capacitor. DRV may be used to drive external loads

up to 10 mA. DRV is active whenever the input is connected and V_SUPPLY> V_UVLOand V_SUPPLY

> (V_BAT+ V_SLP

)

A1- A4

Input power supply –IN is connected to the external DC supply (AC adapter or alternate

power source). Bypass IN to PGND with at least a 1-μF ceramic capacitor.

INT

Status Output –INT is an open-drain output that signals charging status and fault interrupts.

INT pulls low during charging. INT is high impedance when charging is complete or the charger

is disabled. When a fault occurs, a 128-μs pulse is sent out as an interrupt for the host. INT is

enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail

through a 100-kΩresistor to communicate with the host processor.

PGND

D1-D7,

E1, G7

5, 15,

16, 17

D1-D7,

E1, G7

5, 15,

16, 17

—

Ground terminal –Connect to the thermal pad (for VQFN only) and the ground plane of the

circuit.

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

表6-1. Pin Functions (continued)

NO.

BQ24160, 3

NO.

I/O

DESCRIPTION

BQ24161, 1B, 8

NAME

YFF

RGE

YFF

RGE

PMIDI

B1-B4

Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power

Input –Bypass PMIDI to GND with at least a 4.7-μF ceramic capacitor. Use caution when

connecting an external load to PMIDI. The PMIDI output is not current limited. Any short on

PMIDI will damage the IC.

PMIDU

PSEL

B5-B7

Reverse Blocking MOSFET and High Side MOSFET Connection Point for USB Input –

Bypass PMIDU to GND with at least a 4.7-μF ceramic capacitor. Use caution when connecting

an external load to PMIDU. The PMIDU output is not current limited. Any short on PMIDU will

damage the IC.

—

USB Source Detection Input –Drive PSEL high to indicate that a USB source is connected to

the USB input. When PSEL is high, the IC starts up with a 100 mA (BQ24161/8) or 500 mA

(BQ24161B) input current limit for USB. Drive PSEL low to indicate that an AC Adapter is

connected to the USB input. When PSEL is low, the IC starts up with a 1.5 A input current limit

for USB. PSEL has no effect on the IN input. Do not leave PSEL unconnected.

I²C Interface Clock –Connect SCL to the logic rail through a 10-kΩresistor.

I²C Interface Data –Connect SDA to the logic rail through a 10-kΩresistor.

SCL

SDA

STAT

I/O

Status Output –STAT is an open-drain output that signals charging status and fault interrupts.

STAT pulls low during charging. STAT is high impedance when charging is complete or the

charger is disabled. When a fault occurs, a 128-μs pulse is sent out as an interrupt for the host.

STAT is enabled /disabled using the EN_STAT bit in the control register. Pull STAT up to a logic

rail thruogh an LED for visual indication or through a 10-kΩresistor to communicate with the

host processor.

C1-C7

F1-F4

C1-C7

F1-F4

Inductor Connection –Connect to the switched side of the external inductor.

SYS

13, 14

13,14

System Voltage Sense and Charger FET Connection –Connect SYS to the system output

at the output bulk capacitors. Bypass SYS locally with at least 10 μF. A 47-μF bypass

capacitor is recommended for optimal transient response.

Battery Pack NTC Monitor –Connect TS to the center tap of a resistor divider from DRV to

GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA

compatibility (160, 161B, 163, 168 only). TS faults are reported by the I²C interface. See the

NTC Monitor section for more details on operation and selecting the resistor values. Connect TS

to DRV to disable the TS function.

USB

A5-A7

USB Input Power Supply –USB is connected to the external DC supply (AC adapter or USB

port). Bypass USB to PGND with at least a 1-μF ceramic capacitor.

Thermal

Pad

There is an internal electrical connection between the exposed thermal pad and the PGND pin

of the device. The thermal pad must be connected to the same potential as the PGND pin on

the printed circuit board. Do not use the thermal pad as the primary ground input for the device.

PGND pin must be connected to ground at all times.

—

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–2

MAX

UNIT

IN, USB

PMIDI, PMIDU, BOOT

Pin voltage range (with

–0.3

–0.7

–0.3

4.5

respect to VSS)

SDA, SCL, SYS, BAT, STAT, BGATE, DRV, TS, D+, D–, INT, PSEL, CD

BOOT to SW

Output current (continuous)

SYS, BAT

3.5

2.75

1.75

Input current (continuous)

Output sink current

USB

STAT

INT

°C

° C

Operating free-air temperature range

Junction temperature, T_J

–40

300

125

Lead temperature (soldering, 10 s)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

7.2 Handling Ratings

MIN

MAX

150

UNIT

°C

T_stg

Storage temperature range

–65

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

IN voltage range

4.2

V_IN

IN operating voltage range (BQ24160/1/3)

IN operating voltage range (BQ24168)

USB voltage range

V_USB

USB operating range

I_IN

Input current, IN input

2.5

1.5

I_USBInput current USB input

I_SYSOutput Current from SW, DC

Charging

2.5

125

I_BAT

Discharging, using internal battery FET

T_J

Operating junction temperature range

°C

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

UNIT

7.4 Thermal Information

BQ2416xx

24 PINS (RGE)

THERMAL METRIC⁽¹⁾

49 PINS (YFF)

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

49.8

0.2

1.1

6.6

n/a

32.6

30.5

3.3

°C/W

θ_JA

θ_JCtop

θ_JB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JT

9.3

ψ_JB

2.6

θ_JCbot

(1) For more information about traditional and new thermal metrics, see The IC Package Thermal Metrics Application Report.

7.5 Electrical Characteristics

Circuit of 图9-1, V_SUPPLY= V_USBor V_IN(whichever is supplying the IC), V_UVLO< V_SUPPLY< V_OVPand V_SUPPLY> V_BAT+V_SLP

T_J= -40°C –125°C and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

PWM switching

V_UVLO< V_SUPPLY< V_OVPand

V_SUPPLY> V_BAT+V_SLP

PWM NOT switching

175

I_SUPPLY

Supply current for control (V_INor V_USB)

0°C < T_J< 85°C, High-Z Mode

μA

I_BATLEAK

I_{BAT_HIZ}

Leakage current from BAT to the Supply

0°C < T_J< 85°C, V_BAT= 4.2V, V_USB= V_IN= 0V

Battery discharge current in High Impedance mode,

(BAT, SW, SYS)

0°C< T_J< 85°C, V_BAT= 4.2V, V_SUPPLY= 5V or 0V,

SCL, SDA = 0 V or 1.8V, High-Z Mode

μA

POWER-PATH MANAGEMENT

BQ24160, 1, 1B, 8

BQ24163

3.60

3.3

3.7

3.4

3.82

3.5

Charge Enabled, V_BAT< V_MINSYS

V_SYS(REG)

System regulation voltage

Battery FET turned off (Charge Disabled, TS Fault or

Charging Terminated)

V_BATREG

+ 1.5%

V_BATREG

+ 3.0%

V_BATREG

+ 4.17%

BQ24160, 1, 1B, 8

3.4

3.1

3.5

3.2

3.62

3.3

Charge enabled, V_BAT< V_MINSYS

Input current limit or V_INDPMactive

V_MINSYS

Minimum system regulation voltage

BQ24163

V_BAT

–30mV

V_BSUP1

Enter supplement mode threshold

Exit supplement mode threshold

V_BAT> 2.5V

V_BAT

–10mV

V_BSUP2

V_BAT> 2.5V

I_{LIM(discharge)}Current limit, discharge or supplement mode

Current monitored in internal FET only.

Deglitch time, SYS short circuit during discharge or

supplement mode

Measured from (V_BAT–V_SYS) = 300mV to BAT high-

impedance

t_DGL(SC1)

250

μs

Recovery time, SYS short circuit during discharge or

supplement mode

t_REC(SC1)

Battery range for BGATE and supplement mode

operation

2.5

4.5

BATTERY CHARGER

YFF pkg

Measured from BAT to SYS,

V_BAT= 4.2V

R_ON(BAT-SYS)Internal battery charger MOSFET on-resistance

mΩ

RGE pkg

Charge Voltage

V_BATREG

Operating in voltage regulation, Programmable range

3.5

–1%

550

4.44

Voltage regulation accuracy

Fast charge current range

I_CHARGE

2500

+10%

2.1

_BATSHRT≤V_BAT< V_BAT(REG)programmable range

Fast charge current accuracy

0°C to 125°C

–10%

1.9

BQ24161, 3, 8

BQ24160, 1B

2.0

3.0

V_BATSHRT

Battery short circuit threshold

Battery short circuit current

100mV Hysteresis

V_BAT< V_BATSHRT

2.9

3.1

I_BATSHRT

Deglitch time for battery short circuit to fastcharge

transition

t_DGL(BATSHRT)

I_TERM= 50mA

I_TERM= 100mA

+40%

+20%

+15%

–40%

–20%

–15%

I_TERM

Termination charge current accuracy

_TERM≥150mA

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7.5 Electrical Characteristics (continued)

Circuit of 图9-1, V_SUPPLY= V_USBor V_IN(whichever is supplying the IC), V_UVLO< V_SUPPLY< V_OVPand V_SUPPLY> V_BAT+V_SLP

T_J= -40°C –125°C and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

Deglitch time for charge termination

Recharge threshold voltage

Deglitch time

TEST CONDITIONS

Both rising and falling, 2mV overdrive, t_RISE,t_FALL= 100ns

Below V_BATREG

MIN

TYP

MAX

UNIT

t_DGL(TERM)

V_RCH

t_DGL(RCH)

V_DETECT

120

VBAT falling below VRCH, tFALL=100ns

During battery detection source cycle

During battery detection sink cycle

Termination enabled (EN_TERM = 1)

Battery detection threshold

3.3

3.0

2.5

I_DETECT

Battery detection current before charge done (sink

current)

t_DETECT

V_IH

Battery detection time

Termination enabled (EN_TERM = 1)

250

PSEL, CD Input high logic level

PSEL, CD Input low logic level

1.3

V_IL

0.4

INPUT CURRENT LIMITING

I_USBLIM= USB100

I_USBLIM= USB500

450

135

800

700

1250

1.35

2.3

475

100

500

I_USBLIM= USB150

142.5

850

150

USB charge mode, V_USB= 5V,

DC Current pulled from SW

I_{IN_USB}

Input current limit threshold (USB input)

I_USBLIM= USB900

900

I_USBLIM= USB800

I_USBLIM= 1.5A

750

800

1400

1.5

1500

1.65

2.8

IN charge mode, V_IN= 5V,

DC Current pulled from SW

I_INLIM= 1.5A

I_INLIM= 2.5A

I_{IN_IN}

Input current limit threshold (IN input)

2.5

V_{IN_DPM}

Input based DPM threshold range

V_{IN_DPM}threshold accuracy

Charge mode, programmable via I²C, both inputs

4.2

4.76

+2%

–2

VDRV BIAS REGULATOR

V_DRV

Internal bias regulator voltage

V_SUPPLY> 5.45V

5.2

5.45

450

I_DRV

DRV output current

V_{DO_DRV}

I_SUPPLY= 1A, V_SUPPLY= 5V, I_DRV= 10mA

DRV Dropout voltage (V_SUPPLY–V_DRV

)

STATUS OUTPUT ( STAT, INT)

V_OL

Low-level output saturation voltage

I_O= 10mA, sink current

V_STAT= V_INT= 5V

0.4

I_IH

High-level leakage current

µA

PROTECTION

V_UVLO

IC active threshold voltage

IC active hysteresis

V_INrising

3.6

120

3.8

150

V_{UVLO_HYS}

V_SLP

V_INfalling from above V_UVLO

2.0V ≤V_BAT≤V_BATREG, V_INfalling

2.0V ≤V_BAT≤V_BATREG

Sleep-mode entry threshold, V_SUPPLY-V_BAT

Sleep-mode exit hysteresis

100

175

V_{SLP_EXIT}

100

Deglitch time for supply rising above V_SLP+V_{SLP_EXIT}

Rising voltage, 2mV over drive, t_RISE= 100ns

After Bad Source Detection completes

V_{IN_DPM}

–80 mV

V_{BAD_SOURCE}Bad source detection threshold

During Bad Source Detection

V_{IN_DPM}

+ 80 mV

t_DGL(BSD)

Deglitch on bad source detection

Input supply OVP threshold voltage

6.5

USB, V_USBRising

6.3

10.3

6.3

6.7

10.7

6.7

V_OVP

IN, V_INRising (BQ24160/1/1B/3)

IN, V_INRising (BQ24168)

Supply falling from V_OVP

10.5

6.5

V_OVP(HYS)

V_BOVP

V_OVPhysteresis

100

1.025 ×

V_BATREG

1.05 ×

V_BATREG

1.075 ×

V_BATREG

Battery OVP threshold voltage

V_BATthreshold over V_OREGto turn off charger during charge

% of

V_BATREG

V_BOVPhysteresis

Lower limit for V_BATfalling from above V_BOVP

t_DGL(BOVP)

Battery OVP deglitch

BOVP fault shown in register once t_DGL(BOVP)expires.

Buck converter shut down immediately when V_BAT

V_BATOVP

V_BATUVLO

I_LIMIT

Battery undervoltage lockout threshold

Cycle-by-cycle current limit

Thermal trip

V_BATrising, 100mV hysteresis

V_SYSshorted

2.5

4.9

165

4.1

5.6

T_SHTDWN

°C

Thermal hysteresis

T_REG

Thermal regulation threshold

Charge current begins to cut off

120

°C

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7.5 Electrical Characteristics (continued)

Circuit of 图9-1, V_SUPPLY= V_USBor V_IN(whichever is supplying the IC), V_UVLO< V_SUPPLY< V_OVPand V_SUPPLY> V_BAT+V_SLP

T_J= -40°C –125°C and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Safety timer accuracy

(BQ24160/1/1B/3 Only)

20%

–20%

PWM

I_{IN_LIMIT}= 500mA, Measured from USB to PMIDU

I_{IN_LIMIT}= 500mA, Measured from IN to PMIDI

Measured from PMIDU to SW

175

Internal top reverse blocking MOSFET on-resistance

mΩ

100

175

110

115

1.65

Internal top N-channel Switching MOSFET on-

resistance

Measured from PMIDI to SW

Internal bottom N-channel MOSFET on-resistance

Oscillator frequency

Measured from SW to PGND

mΩ

f_OSC

1.35

1.50

95%

MHz

D_MAX

D_MIN

Maximum duty cycle

Minimum duty cycle

BATTERY-PACK NTC MONITOR

V_HOT

High temperature threshold

V_TSfalling

29.7

37.9

30.5

39.6

56.9

60.4

%V_DRV

V_HYS(HOT)

V_WARM

V_HYS(WARM)

V_COOL

V_HYS(COOL)

V_COLD

Hysteresis on high threshold

High temperature threshold

Hysteresis on high threshold

Low temperature threshold

Hysteresis on low threshold

Low temperature threshold

Hysteresis on low threshold

TS Disable threshold

V_TSrising

V_TSfalling

38.3

V_TSrising

V_TSfalling

56.5

V_TSrising

V_TSfalling

59.5

V_HYS(COLD)

TSOFF

V_TSrising

V_TSrising, 2%V_DRVhysteresis

%V_DRV

t_DGL(TS)

Deglitch time on TS change

0.6

D+/D–DETECTION (bq24160)

V_{D+_SRC}

I_{D+_SRC}

I_{D-_SINK}

I_{D_LKG}

D+ Voltage Source

0.5

0.7

150

D+ Connection Check Current Source

D- Current Sink

µA

100

D–, switch open

–1

0.8

Leakage Current into D+/D-

D+, switch open

V_{D+_LOW}

D+ Low Comparator Threshold

V_{D-_LOWdatref}D- Low Comparator Threshold

R_{D-_DWN}D- Pulldown for Connection Check

BATGD OPERATION

V_BATGDGood Battery threshold

Deglitch for good battery threshold

I²C COMPATIBLE INTERFACE

250

14.25

400

kΩ

24.8

3.6

1.3

3.8

3.9

V_BATrising to HIGH-Z mode, DEFAULT Mode Only

V_IH

Input low threshold level

V_PULL-UP= 1.8V, SDA and SCL

I_L= 10mA, sink current

V_IL

Input low threshold level

Output low threshold level

High-Level leakage current

Watchdog timer timeout

0.4

V_OL

I_BIAS

V_PULL-UP= 1.8V, SDA and SCL

(BQ24160/1/3 Only)

μA

t_WATCHDOG

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7.6 Typical Characteristics

100

V_IN= 5 V

V_IN= 7 V

V_IN= 9 V

V_USB= 5 V

V_USB= 6 V

0.1

System Current (A)

G001

G002

Charge Disabled

IN2500 ILIM

SYS loaded

V_BATREG= 3.6 V

Charge Disabled

USB1500 ILIM

SYS loaded

V_BATREG= 3.6 V

图7-1. IN Efficiency

图7-2. USB Efficiency

3.9

4.21

4.208

4.206

4.204

4.202

4.2

SYSREG Regulation

MINSYS Regulation

3.85

3.8

3.75

3.7

3.65

3.6

4.198

4.196

4.194

4.192

4.19

3.55

3.5

3.45

3.4

−50

Temperature (°C)

100

150

50 75

Temperature (°C)

100

125

G003

G004

V_BAT= 3 V

V_BATREG= 4.2 V

No load

Termination Disabled

图7-3. SYSREG and MINSYS Regulation vs Temperature

图7-4. Battery Regulation vs Temperature

700

6.7

6.6

6.5

6.4

6.3

6.2

6.1

USB100 Current Limit

USB500 Current Limit

Falling Edge

Rising Edge

600

500

400

300

200

100

−50

Temperature (°C)

100

150

−50

Temperature (°C)

100

150

G005

G006

USB100 and USB500 current limit V_USB= 5 V V_BAT= 3.6 V

USB input and IN input (BQ24168)

图7-6. 6.5-V OVP Threshold vs Temperature

图7-5. USB Input Current Limit vs Temperature

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7.6 Typical Characteristics (continued)

10.7

2.1

2.09

2.08

2.07

2.06

2.05

2.04

2.03

2.02

2.01

Falling Edge

Rising Edge

10.6

10.5

10.4

10.3

10.2

10.1

−50

Temperature (°C)

100

150

2.5

3 3.5

Battery Voltage (V)

4.5

G007

G008

图7-7. 10.5-V OVP Threshold vs Temperature

I_CHARGE= 2 A

V_IN= 5 V

V_BATREG= 4.44 V

图7-8. Charge Current vs Battery Voltage

0.055

0.054

0.053

0.052

0.051

0.05

0.5

1.5

Battery Voltage (V)

2.5

G009

图7-9. I_BATSHRTvs Battery Voltage

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8 Detailed Description

8.1 Overview

The BQ24160/BQ24160A/BQ24161/BQ24161B/BQ24163/BQ24168 devices are highly integrated single-cell Li-

Ion battery chargers and system power path management devices targeted for space-limited, portable

applications with high-capacity batteries. The dual-input, single-cell charger operates from either a USB port or

alternate power source (that is, wall adapter or wireless power input) for a versatile solution.

The power path management feature allows the BQ2416xx to power the system from a high-efficiency DC-DC

converter while simultaneously and independently charging the battery. The charger monitors the battery current

at all times and reduces the charge current when the system load requires current above the input current limit.

This allows proper charge termination and enables the system to run with a defective or absent battery pack.

Additionally, this enables instant system turnon even with a totally discharged battery or no battery. The power-

path management architecture also permits the battery to supplement the system current requirements when the

adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The 2.5-A current

capability allows for GSM phone calls as soon as the adapter is plugged in regardless of the battery voltage. The

charge parameters are programmable using the I²C interface.

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8.2 Functional Block Diagram

PMIDU

PMIDI

5.2-V Reference

DRV

USB

BOOT

CbC Current

Limit

IN I_INLIM

USB I_USBLIM

IN V_INDPM

DC-DC CONVERTER

PWM LOGIC,

COMPENSATION

AND

BATTERY FET CONTROL

USB V_INDPM

V_SYS(REG)

I_BAT(REG)

V_BAT(REG)

DIE Temp

Regulation

PGND

SYS

V_SUPPLY

SUPPLY_SEL

Termination

References

V_USB

Reference

V_USBOVP

I_BAT

OVP Comparators

Termination Comparator

V_IN

BAT

V_INOVP

Recharge Comparator

V_BATREG– 0.12V

Start Recharge

Cycle

V_BAT

V_USB

V_SYSREGComparator

V_BAT+ V_SLP

V_SYS

Enable Linear

Charge

Sleep Comparators

V_MINSYS

V_IN

V_BAT

Good Battery

Circuit

V_BAT+ V_SLP

Hi-Z Mode

BGATE

V_BATGD

V_BATSCComparator

Hi-Z Mode

Enable

V_BAT

V_BATSHRT

I_BATSHRT

SDA

I²C

Interface

Supplement Comparator

V_SYS

SCL

V_BAT

V_BSUP

VDRV

BQ24160, 60A, 3

V_BOVPComparator

USB

V_BAT

D+

D–

Adapter

Detection

Circuitry

1.5A/USB100

V_BATOVP

DISABLE

1C/0.5C

TS COLD

TS COOL

BQ24161, 1B, 8

PSEL

BQ24160/2/3

V_BATREG– 0.14V

DISABLE

STAT

INT

TS WARM

TS HOT

CHARGE

CONTROLLER

with Timers (160/1/3)

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8.3 Feature Description

8.3.1 Charge Mode Operation

8.3.1.1 Charge Profile

The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS voltage, the

internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the battery.

When battery is less than MINSYS, the SYS is regulated to V_SYS(REG)and battery is charged using the battery

FET to regulate the charge current. There are 5 loops that influence the charge current:

• Constant current loop (CC)

• Constant voltage loop (CV)

• Thermal-regulation loop

• Minimum system-voltage loop (MINSYS)

• Input-voltage dynamic power-management loop (V_IN-DPM)

During the charging process, all five loops are enabled and the one that is dominant takes control. The

BQ2416xx supports a precision Li-ion or Li-polymer charging system for single-cell applications. The Dynamic

Power Path Management (DPPM) feature regulates the system voltage to a minimum of V_MINSYS, so that startup

is enabled even for a missing or deeply discharged battery. 图 8-1 shows a typical charge profile including the

minimum system output voltage feature.

Voltage Regulation

Phase

Precharge

Phase

Current Regulation

Phase

Regulation

voltage

Charge Current

Regulation

Threshold

System Voltage

SYS

BATSHORT

Battery

Voltage

Charge Current

Termination

Current

Threshold

BATSHORT

Linear Charge

to Maintain

Battery

FET

is OFF

50mA Precharge to

Close Pack Protector

Battery FET is ON

Minimum

System

Voltage

图8-1. Typical BQ2416xx Charging Profile

8.3.1.2 PWM Controller in Charge Mode

The BQ2416xx provides an integrated, fixed-frequency 1.5-MHz voltage-mode controller to power the system

and supply the charge current. The voltage loop is internally compensated and provides enough phase margin

for stable operation, allowing the use of small ceramic capacitors with low ESR. When starting up, the BQ2416xx

uses a "soft-start" function to help limit inrush current. When coming out of High Impedance mode, the

BQ2416xx starts up with the input current limit set to 40% of the value programmed in the I²C register. After 80

ms, the input current limit threshold steps up in 256-µs steps. The steps are 40% to 50%, then 50% to 60%, then

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60% to 70%, then 70% to 80%, and finally 80% to 100%. After the final step, soft start is complete and will not

be restarted until the BQ2416xx enters High Impedance mode.

The input scheme for the BQ2416xx prevents battery discharge when the supply voltages are lower than VBAT

and also isolates the two inputs from each other. The high-side N-MOSFET (Q1/Q2) switches to control the

power delivered to the output. The DRV LDO provides a supply for the gate drive for the low side MOSFET,

while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up the gate drive voltage for

Q1 and Q2.

Both inputs are protected by a cycle-by-cycle current limit that is sensed through the high-side MOSFETs for Q1

and Q2. The threshold for the current limit is set to a nominal 5-A peak current. The inputs also utilize an input

current limit that limits the current from the power source.

8.3.2 Battery Charging Process

Assuming a vaild input source is attached to IN or USB, as soon as a deeply discharged or shorted battery is

attached to the BAT pin, (V_BAT< V_BATSHRT), the BQ2416xx applies I_BATSHRTto close the pack protector switch

and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly

regulated and the system output is regulated to V_SYS(REG). Once the battery rises above V_BATSHRT, the charge

current is regulated to the value set in the I²C register. The battery FET is linearly regulated to maintain the

system voltage at V_SYS(REG). Under normal conditions, the time spent in this region is a very short percentage of

the total charging time, so the linear regulation of the charge current does not affect the overall charging

efficiency for very long. If the die temperature does rise, the thermal regulation circuit reduces the charge current

to maintain a die temperature less than 120°C. If the current limit for the SYS output is reached (limited by the

input current limit, or V_{IN_DPM}), the SYS output drops to the V_MINSYSoutput voltage. When this happens, the

charge current is reduced to provide the system with all the current that is needed while maintaining the

minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the

output to fall to the battery voltage and enter supplement mode. (See the Dynamic Power Path Management

section for more details.)

Once the battery is charged enough so that the system voltage begins to rise above V_SYS(REG), the battery FET

is turned on fully and the battery is charged with the full programmed charge current set by the I²C interface,

I_CHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during

transients. The charge current is regulated to I_CHARGEuntil the battery is charged to the regulation voltage. As

the battery voltage rises above VRCH, the battery regulation loop is activated. This may result in a small step

down in the charge current as the loops transition between the charge current and charge voltage loops. As the

battery voltage charges up to the regulation voltage, V_BATREG, the charge current is tapered down as shown in 图

8-1 while the SYS output remains connected to the battery. The voltage between the BAT and PGND pins is

regulated to V_BATREG. The BQ2416xx is a fixed single-cell voltage version, with adjustable regulation voltage (3.5

V to 4.44 V), programmed using the I²C interface.

The BQ2416xx monitors the charging current during the voltage-regulation phase. If the battery voltage is above

the recharge threshold and the charge current has naturally tapered down to and remains below termination

threshold, I_TERM, (without disturbance from events like supplement mode) for 32 ms, the charger terminates

charge, turns off the battery charging FET and enters battery detection. Termination is disabled when the charge

current is reduced by a loop other than the voltage regulation loop or the input current limit is set to 100 mA. For

example, when the BQ2416xx is in half charge due to TS function, reverse boost protection is active, LOW_CHG

bit is set, or the thermal regulation, V_INDPMor input current loops are active, termination will not occur. This

prevents false termination events. During termination, the system output is regulated to the V_SYS(REG)and

supports the full current available from the input and the battery supplement mode is available. (See the

Dynamic Power Path Management section for more details.) The termination current level is programmable.

When setting the termination threshold less than 150mA, the reverse boost protection may trip falsely with load

transients and very fully charged batteries. This will prevent termination while in the reverse boost protection and

may extend charge time. To disable the charge current termination, the host sets the charge termination bit (TE)

of charge control register to 0, refer to I²C section for details.

A new charge cycle is initiated if CD is low when either

1. V_SUPPLYrises above UVLO while a battery with V_BAT< V_BATREG- V_RCHis attached or

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2. a battery with V_BAT< V_BATREG- V_RCHis attached while V_SUPPLYis above UVLO.

With V_SUPPLYabove UVLO and V(BAT) < V_BOVP, a recharge cycle is initiated when one of the following

conditions is detected:

1. The battery voltage falls below the V_BAT(REG)-V_RCHthreshold.

2. CE bit toggle or RESET bit toggle

3. Supplement mode event occurs

4. CD pin or HI-Z bit toggle

V_BAT(REG)should never be programmed less than V_BAT. If the battery is ever 5% above the regulation threshold,

the battery OVP circuit shuts the PWM converter off immediately and the battery FET is turned on to discharge

the battery to safe operating levels. If the battery OVP condition exists for the 1ms deglitch, a battery OVP fault

is reported in the I²C status registers. The battery OVP fault is cleared when the battery voltage discharges

below V_RCHor if the IC enters hi-impedance mode (HZ_MODE=1 or CD=1). Always write BQ2416xx to high

impedance mode before changing V_BATREGto clear BOVP condition to ensure proper operation.

If the battery voltage is ever greater than VBATREG (for example, when an almost fully charged battery enters

the JEITA WARM state due to the TS pin) but less than V_BOVP, the reverse boost protection circuitry may

activate as explained later in this data sheet. If the battery is ever above V_BOVP, the buck converter turns off and

the internal battery FET is turned on. This prevents further overcharging of the battery and allows the battery to

discharge to safe operating levels. The battery OVP event does not clear until the battery voltage falls below

V_RCH

8.3.3 Battery Detection

When termination conditions are met, a battery detection cycle is started. During battery detection, I_DETECTis

pulled from V_BATfor t_DETECTto verify there is a battery. If the battery voltage remains above V_DETECTfor the full

duration of t_DETECT, a battery is determined to present and the IC enters “Charge Done”. If V_BATfalls below

V_DETECT, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of battery

detection, the BQ2416xx turns on I_BATSHORTfor t_DETECT. If V_BATrises to V_DETECT, the current source is turned

offand after t_DETECT, the battery detection continues through another current sink cycle. Battery detection

continues until charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and

a new charge cycle begins. Battery detection is not run when termination is disabled.

8.3.4 Dynamic Power Path Management (DPPM)

The BQ2416xx features a SYS output that powers the external system load connected to the battery. This output

is active whenever a source is connected to IN, USB or BAT. The following sections discuss the behavior of SYS

with a source connected to the supply or a battery source only.

8.3.5 Input Source Connected

When a valid input source is connected to IN or USB and the BQ2416xx is NOT in High Impedance mode, the

buck converter enters soft-start and turns on to power the load on SYS. The STAT/INT pin outputs a 128-µs

interrupt pulse to alert the host that an input has been connected. The FAULT bits indicate a normal condition,

and the Supply Status register indicates that a new supply is connected. The CE bit (bit 1) in the control register

(0x02) indicates whether a charge cycle is initiated. By default, the BQ2416xx ( CE = 0) enables a charge cycle

when a valid input source is connected. When the CE bit is '1' and a valid input source is connected, the battery

FET is turned off and the SYS output is regulated to the V_SYS(REG)programmed by the V_BATREGthreshold in the

I²C register. A charge cycle is initiated when the CE bit is written to a 0 value (cleared).

When the CE bit is a 0 and a valid source is connected to IN or USB, the buck converter starts up using soft-

start. A charge cycle is initiated 64 ms after the buck converter iniates startup. When V_BATis high enough that

V_SYS> V_SYS(REG), the battery FET is turned on and the SYS output is connected to BAT. If the SYS voltage falls

to V_SYS(REG), it is regulated to that point to maintain the system output even with a deeply discharged or absent

battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET linearly

regulates the charge current into the battery. The current from the supply is shared between charging the battery

and powering the system load at SYS. The dynamic power-path management (DPPM) circuitry of the BQ2416xx

monitors the current limits continuously, and if the SYS voltage falls to the V_MINSYSvoltage, it adjusts charge

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current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to

zero and the load increases further, the BQ2416xx enters battery-supplement mode. During supplement mode,

the battery FET is turned on and the battery supplements the system load.

When an input is connected with no battery attached and termination enabled, the startup process proceeds as

normal until the termination deglitch times out. After this, the BQ2416xx enters battery detection and waits for a

battery to be connected. Once a battery is connected and passes battery detection, a new charge cycle begins.

Once the battery is applied, the HZMODE bit or CD pin must be toggled before writing the BATREG to a higher

voltage and beginning a new charge cycle. Failure to do this can result in SYS unexpectedly regulating to 15%

above V_BATREG

2000 mA

1800 mA

I_SYS

800 mA

1500 mA

~850 mA

I_IN

0mA

I_BAT

0mA

-200 mA

V_SYS(REG)

V_MINSYS

DPPM loop active

V_OUT

~3.1V

Supplement

Mode

图8-2. Example DPPM Response (V_Supply= 5 V, V_BAT= 3.1 V, 1.5 A Input Current Limit)

8.3.6 Battery Only Connected

When a battery with voltage greater than V_BATUVLOis connected with no input source, the battery FET is turned

on similar to supplement mode. In this mode, the current is not regulated; however, there is a short circuit current

limit. If the short circuit limit is reached, the battery FET is turned off for the deglitch time (t_DGL(SC1)). After the

recovery time (t_REC(SC1)), the battery FET is turned on to test and see if the short has been removed. If it has not,

the FET turns off and the process repeats until the short is removed. This process is to protect the internal FET

from over current. If an external FET is used for discharge, the external FET's body diode prevents the load on

SYS from being disconnected from the battery. If the battery voltage is less than V_BATUVLO, the internal battery

FET (Q4) remains off and BAT is high-impedance. This prevents further discharging of deeply-discharged

batteries.

8.3.7 Battery Discharge FET (BGATE)

The BQ2416xx contains a MOSFET driver to drive the gate of an external discharge FET between the battery

and the system output. This external FET provides a low impedance path when supplying the system from the

battery. Connect BGATE to the gate of the external discharge MOSFET. BGATE is on under the following

conditions:

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1. No input supply connected.

2. HZ_MODE bit = 1

3. CD pin = 1

8.3.8 DEFAULT Mode

DEFAULT mode is used when I²C communication is not available. DEFAULT mode is entered in the following

situations:

1. When the charger is enabled and V_BAT< V_BATGDbefore I²C communication is established

2. When the watchdog timer expires without a reset from the I²C interface and the safety timer has not expired.

3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I²C

communication is established

In DEFAULT mode, the I²C registers are reset to the default values. The 27-minute safety timer (no timer for

BQ24168) is reset and starts when DEFAULT mode is entered. The default value for VBATREG is 3.6 V, and the

default value for I_CHARGEis 1 A. The input current limit for the IN input is set to 1.5 A. The input current limit for

the USB input is determined by the D+/D– detection (BQ24160/3) or PSEL (BQ24161/1B/8). PSEL and D+/D–

detection have no effect on the IN input. Default mode is exited by programming the I²C interface. Once I²C

communication is established, PSEL has no effect on the USB input. Note that if termination is enabled and

charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.

8.3.9 Safety Timer and Watchdog Timer (BQ24160/BQ24161/BQ24161B/BQ24163 only)

At the beginning of charging process, the BQ24160/1/1B/3 starts the safety timer. This timer is active during the

entire charging process. If charging has not terminated before the safety timer expires, charging is disabled, the

charge parameters are reset to the default values and the CE bit is written to a “1”. The length of the safety

timer is selectable using the I²C interface. A single 128-μs pulse is sent on the STAT and INT outputs and the

STATx bits of the status registers are updated in the I²C. In DEFAULT mode, the safety timer can be reset and a

new charge cycle initiated by input supply power on reset, removing/inserting battery or toggling the CD pin. In

HOST mode, the CE bit is set to a '1' when the safety timer expires. The CE bit must be cleared to a '0' in order

to resume charging and clear the safety timer fault. The safety timer duration is selectable using the TMR_X bits

in the Safety Timer Register/ NTC Monitor register. Changing the safety timer duration resets the safety timer.

This function prevents continuous charging of a defective battery. During the fast charge (CC) phase, several

events increase the timer duration by 2× if the EN_2X_TMR bit is set in the register.

1. The system load current reduces the available charging current.

2. The input current needed for the fast charge current is limited by the input current loop.

3. The input current is reduced because the VINDPM loop is preventing the supply from crashing.

4. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG).

5. The LOW_CHG bit is set.

6. The battery voltage is less than VBATSHORT.

7. The battery has entered the JEITA WARM or COLD state via the TS pin

During these events, the timer is slowed by half to extend the timer and prevent any false timer faults. Starting a

new charge cycle by VSUPPLY POR or removing/replacing the battery or resuming a charge by toggling the CE

or HZ_MODE bits, resets the safety timer. Additionally, thermal shutdown events cause the safety timer to reset.

In addition to the safety timer, the BQ24160/1/1B/3 contain a watchdog timer that monitors the host through the

I²C interface. Once a read/write is performed on the I²C interface, a 30-second timer (t_WATCHDOG) is started. The

30-second timer is reset by the host using the I²C interface. This is done by writing a “1” to the reset bit

(TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is

reset. This process continues until the battery is fully charged or the safety timer expires. If the 30-second timer

expires, the IC enters DEFAULT mode where the default register values are loaded, the safety timer restarts at

27 minutes and charging continues. The I²C may be accessed again to reinitialize the desired values and restart

the watchdog timer. The watchdog timer flow chart is shown in 图8-3.

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Start Safety Timer

Yes

Safety timer

fault

Safety timer expired?

Charging suspended

Enter suspended

mode

STAT = Hi

Update STAT

bits

Yes

Charge Done?

I_CHG< I_TERM

Fault indicated in

STAT registers

I2C Read/Write

performed?

Yes

Start 30 second

watchdog timer

Reset 30 second

watchdog timer

STAT = Hi

Update STAT

bits

Yes

Charge Done?

I_CHG< I_TERM

Yes

Safety timer

fault

Safety timer expired?

Charging suspended

Fault indicated in

STAT registers

Yes

Received SW watchdog

RESET?

30s timer expired?

Yes

Reset to default

values in I2C

Restart 27min

safety timer

图8-3. The Watchdog Timer Flow Chart for BQ2416xx

8.3.10 D+, D–Based Adapter Detection for the USB Input (D+, D–, BQ24160/0A/3)

The BQ24160/0A/3 contain a D+, D– based adapter detection circuit that is used to program the input current

limit for the USB input during DEFAULT mode. D+, D– detection is only performed in DEFAULT mode unless

forced by the D+, D–_EN bit in host mode. Writing to register 2 during detection stops the detection routine.

By default the USB input current limit is set to 100 mA. When a voltage higher than UVLO is applied to the USB

input, the BQ24160/0A/3 performs a charger source identification to determine if it is connected to an SDP (USB

port) or CDP/DCP (dedicated charger). The first step is D+, D- line connection detection as described in BC1.2.

Primary detection begins 10 ms after the connection detection complete. The primary detection complies with

the method described in BC1.2. During primary detection, the D+, D- lines are tested to determine if the port is

an SDP or CDP/DCP. If a CDP/DCP is detected the input current limit is increased to 1.5 A, if an SDP is

detected the current limit remains at 100 mA, until changed via the I²C interface. These two steps require at

least 90 ms to complete but if they have not completed within 500 ms, the D+, D- detection routine selects 100

mA for the unknown input source. Secondary detection as described in BC1.2 is not performed.

Automatic detection is performed only if V_D+and V_D–are less than 0.6 V to avoid interfering with the USB

transceiver which may also perform D+, D– detection when the system is running normally. However, D+, D–

can be initiated at any time by the host by setting the D+, D–EN bit in the Control/Battery Voltage Register to 1.

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After detection is complete the D+, D– EN bit is automatically reset to 0 and the detection circuitry is

disconnected from the D+, D–pins to avoid interference with USB data transfer.

When a command is written to change the input current limit in the I²C, this overrides the current limit selected

by D+/D–detection. D+, D–detection has no effect on the IN input.

8.3.11 USB Input Current Limit Selector Input (PSEL, BQ24161/161B/168 only)

The BQ24161, BQ24161B, and BQ24168 contain a PSEL input that is used to program the input current limit for

USB during DEFAULT mode. Drive PSEL high to indicate that a USB source is connected to the USB input and

program the 100 mA (BQ24161/8) or 500 mA (BQ24161B) current limit for USB. Drive PSEL low to indicate that

an AC adapter is connected to the USB input. When PSEL is low, the IC starts up with a 1.5-A current limit for

USB. PSEL has no effect on the IN input. Once an I²C write is done, the PSEL has no effect on the input current

limit until the watchdog timer expires.

8.3.12 Hardware Chip Disable Input (CD)

The BQ2416xx contains a CD input that is used to disable the IC and place the BQ2416xx into high-impedance

mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the

BQ2416xx into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving

CD high during HOST mode resets the safety timer and places the BQ2416xx into high impedance mode. The

CD pin has precedence over the I²C control.

8.3.13 LDO Output (DRV)

The BQ2416xx contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other

circuitry. Additionally, DRV supplies up to 10-mA external loads to power the STAT LED or the USB transceiver

circuitry. The maximum value of the DRV output is 5.45 V; ideal for protecting voltage sensitive USB circuits from

high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the IN or USB inputs of

the BQ2416xx. The DRV is disabled under the following conditions:

1. V_SUPPLY< UVLO

2. V_SUPPLY< V_SLP

3. Thermal Shutdown

8.3.14 External NTC Monitoring (TS)

The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack

thermistor is monitored by the host. Additionally, the BQ2416xx provides a flexible, voltage based TS input for

monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a

safe temperature during charging. The BQ24160, BQ24160A, BQ24161B, BQ24163, and BQ24168 enable the

user to easily implement the JEITA standard for charging temperature while the BQ24161 only monitors the hot

and cold cutoff temperatures and leaves the JEITA control to the host. The JEITA specification is shown in.

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1°C

0.5°C

Portion of spec not covered by TS

Implementation on BQ24160

4.25 V

4.15 V

4.1 V

(0°C)

(10°C)

T3 T4

(45°C) (50°C)

(60°C)

图8-4. Charge Current During TS Conditions

To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (T_NTC

0°C), the cool battery threshold (0°C < T_NTC< 10°C), the warm battery threshold (45°C < T_NTC≤ 60°C) and the

hot battery threshold (T_NTC> 60°C). These temperatures correspond to the V_COLD, V_COOL, V_WARM, and V_HOT

thresholds. Charging is suspended and timers are suspended when V_TS< V_HOTor V_TS> V_COLD. When V_WARM

V_TS> V_HOT, the battery regulation voltage is reduced by 140 mV from the programmed regulation threshold.

When V_COLD> V_TS> V_COOL, the charging current is reduced to half of the programmed charge current.

The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS

connected to the center tap to set the threshold. The connections are shown in 图 8-11. The resistor values are

calculated using the following equations:

V_DRV´ RCOLD ´ RHOT ´

V_COLD

^HOTû

RLO =

V_DRV

RHOT ´

-1 -RCOLD ´

-1

V_HOT

V_COLD

(1)

(2)

V_DRV

-1

V_COLD

RHI =

RLO RCOLD

Where:

V_COLD= 0.60 × V_DRV

V_HOT= 0.30 × V_DRV

Where R_HOTis the NTC resistance at the hot temperature and R_COLDis the NTC resistance at cold temperature.

For the BQ24160, BQ24161B, BQ24163, and BQ24168, the WARM and COOL thresholds are not independently

programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using the

following equations:

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RLO ´ 0.564 ´ RHI

RCOOL =

RLO - RLO ´ 0.564 - RHI ´ 0.564

(3)

RLO ´ 0.383 ´ RHI

RWARM =

RLO - RLO ´ 0.383 - RHI ´0.383

(4)

1 x Charge/

V_BAT(REG)

V_DRV

0.5 x Charge

TS COLD

DISABLE

-140 mV

TS COOL

TS WARM

V_DRV

TS HOT

RHI

PACK+

TEMP

BQ2416x

RLO

PACK-

图8-5. TS Circuit

8.3.15 Thermal Regulation and Protection

During the charging process, to prevent chip overheating, the BQ2416xx monitors the junction temperature, T_J,

of the die and begins to taper down the charge current once T_Jreaches the thermal regulation threshold, T_REG

The charge current is reduced to zero when the junction temperature increases about 10°C above T_REG. Once

the charge current is reduced, the system current is reduced while the battery supplements the load to supply

the system. This may cause a thermal shutdown of the BQ2416xx if the die temperature rises too high. At any

state, if T_Jexceeds T_SHTDWN, the BQ2416xx suspends charging and disables the buck converter. During thermal

shutdown mode, the buck converter is turned off, all timers are suspended, and a single 128-μs pulse is sent on

the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I²C. A new

charging cycle begins when T_Jfalls below T_SHTDWNby approximately 10°C.

8.3.16 Input Voltage Protection in Charge Mode

8.3.16.1 Sleep Mode

The BQ2416xx enters the low-power sleep mode if the voltage on V_SUPPLYfalls below the sleep-mode entry

threshold, V_BAT+V_SLP, and V_SUPPLYis higher than the undervoltage lockout threshold, V_UVLO. This feature

prevents draining the battery during the absence of V_SUPPLY. When V_SUPPLY< V_BAT+ V_SLP, the BQ2416xx turns

off the PWM converter, turns the battery FET on and drives BGATE to GND, sends a single 128-μs pulse on the

STAT and INT outputs and updates the STATx and FAULT_x bits in the status registers. Once V_SUPPLY> V_BAT

V_SLP, the STATx and FAULT_x bits are cleared and the device initiates a new charge cycle.

8.3.16.2 Input Voltage Based DPM

During normal charging process, if the input power source is not able to support the programmed or default

charging current, the supply voltage decreases. Once the supply drops to V_{IN_DPM}(default 4.2 V for both inputs),

the input current limit is reduced to prevent further supply droop. When the IC enters this mode, the charge

current is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature provides

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IC compatibility with adapters with different current capabilities without a hardware change. 图 8-6 shows the

V_IN–DPM behavior to a current-limited source. In this figure the input source has a 750-mA current limit and the

charging is set to 750 mA. The SYS load is then increased to 1.2 A.

Adapter Voltage Falls due

5 V Adapter

rated for 750 mA

to Adapter Current Limit

Input Current Reduced by V_INDPMfunction

to Prevent Adapter from Crashing

SYS

750 mA Charging

BAT

Supplement Mode

1.2 A Load Step

SYS

图8-6. BQ24160 V_IN-DPM

8.3.16.3 Bad Source Detection

When a source is connected to IN or USB, the BQ2416xx runs a Bad Source Detection procedure to determine if

the source is strong enough to provide some current to charge the battery. A current sink is turned on (30 mA for

USB input, 75 mA for the IN input) for 32 ms. If the source is valid after the 32 ms (V_BADSOURCE< V_SUPPLY

V_OVP), the buck converter starts up and normal operation continues. If the supply voltage falls below

V_{BAD_SOURCE}during the detection, the current sink shuts off for two seconds and then retries, a single 128-μs

pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the

battery/supply status registers are updated. The detection circuits retry continuously until either a new source is

connected to the other input or a valid source is detected after the detection time. If during normal operation the

source falls to V_{BAD_SOURCE}, the BQ2416xx turns off the PWM converter, turns the battery FET on, sends a

single 128-μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status

registers, and the battery/supply status registers are updated. Once a good source is detected, the STATx and

FAULT_x bits are cleared and the device returns to normal operation.

If two supplies are connected, the supply with precedence is checked first. If the supply detection fails once, the

device switches to the other supply for two seconds and then retries. This allows the priority supply to settle if the

connection was jittery or the supply ramp was too slow to pass detection. If the priority supply fails the detection

a second time, it is locked out and lower priority supply is used. Once the bad supply is locked out, it remains

locked out until the supply voltage falls below UVLO. This prevents continuously switching between a weak

supply and a good supply.

8.3.16.4 Input Overvoltage Protection

The built-in input overvoltage protection to protect the device and other downstream components against

damage from overvoltage on the input supply (voltage from V_USBor V_INto PGND). During normal operation, if

V_SUPPLY> V_OVP, the BQ2416xx turns off the PWM converter, turns the battery FET and BGATE on, sends a

single 128-μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status

registers and the battery/supply status registers are updated. Once the OVP fault is removed, the STATx and

FAULT_x bits are cleared and the device returns to normal operation.

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To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.

This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If

the adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The

OVP circuit is active during normal operation, so if the system standby current plus the charge current is not

enough to pull down the source, operation is suspended.

8.3.16.5 Reverse Boost (Boost Back) Prevention Circuit

A buck converter has two operating modes, continuous conduction mode (CCM) and discontinuous conduction

mode (DCM). In DCM, the inductor current ramps down to zero during the switching cycle while in CCM the

inductor maintains a DC level of current. Transitioning from DCM to CCM during load transients, slows down the

converter's transient response for those load steps, which can result in the SYS rail drooping. To achieve the

fastest possible transient reponse for this charger, this charger's synchronous buck converter is forced to run in

CCM even at light loads when the buck converter would typically revert to DCM. The challenge that presents

itself when forcing CCM with a charger is that the output of the buck converter now has a power source. Thus, if

the battery voltage, V(BAT), is ever greater than V_BATREG, the inductor current goes fully negative and pushes

current back to the input supply. This effect causes the input source voltage to rise if the input source cannot sink

current. The input over-voltage protection circuit protects the IC from damage however some input sources may

be damaged if the voltage rises. To prevent this, this charger has implemented a reverse boost prevention

circuit. When reverse current is sensed that is not a result of the supplement comparator tripping, this circuit

disables the internal battery FET and changes the feedback point to V_SYSREGfor 1 ms. After the 1-ms timeout,

the BATFET is turned on again and the battery is tested to see if it is higher than V_BATREG(negative current). The

reverse current protection is only active when V_BOVP> V_BAT> V_BATREG- V_RCH. Having V_BOVP> V_BAT> V_BATREG

V_RCHresults in an approximately 100-mV, 1000-Hz ripple on SYS as seen in 图 8-7. The most common trigger

for reverse boost prevention is a load transient on SYS that requires the charger to enter battery supplement

mode. When the IC enters reverse boost prevention, the IC stops charging or exits charge done which may

result in the battery never reaching full charge. With termination enabled and ITERM > 150 mA or with a high

line impedance to the battery, the likelihood of activating the reverse boost prevention circuit is small and even

when activated, the charger typically exits reverse boost prevention as the battery relaxes. With termination

enabled and ITERM < 150 mA or with a low impedance battery, the likelihood of activating the reverse boost

prevention circuit by a load transient or even the inductor ripple current is higher. In either case, the IC resumes

charging until VBAT drops below VBATREG - VRCH, resulting in the battery always charging to at least 0.97 of

full charge. If full charge is required with ITERM < 150 mA then the recommended solution to ensure full charge

is as follows

SET the charger’s enable no battery operation bit ( EN_NOBATOP) = 1 to disable the reverse boost

prevention circuits. Brief, low-amplitude voltage pulses on IN may be observed as the IC enters boost back to

resolve instances where VBAT is greater than the VBATREG, for example when exiting supplement mode. The

I²C communication software must ensure that VBATREG is never written below VBAT. The IC automatically

rewrites the VBATREG register to the default value of 3.6 V when existing HOST mode. For JEITA enabled ICs,

the IC automatically lowers the voltage reference to 0.98 of the VBATREG value. The software must account

for these instances as well.

Disable the charger’s termination function and TS functions and use a gas gauge to control termination

and TS through its independent voltage and current measurements.

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图8-7. V(SYS) When Reverse Boost Prevention Circuit is Active

8.3.17 Charge Status Outputs (STAT, INT)

The STAT output is used to indicate operation conditions for BQ2416xx. STAT is pulled low during charging

when EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is

high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT

during different operation conditions is summarized in 表 8-1. STAT drives an LED for visual indication or can be

connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to

enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be

shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.

表8-1. STAT Pin Summary

CHARGE STATE

Charge in progress and EN_STAT=1

STAT AND INT BEHAVIOR

Low

Other normal conditions

High-Impedance

Status Changes: Supply Status Change (plug in or removal), safety timer fault,

watchdog expiration, sleep mode, battery temperature fault (TS), battery fault

(OVP or absent), thermal shutdown

128-µs pulse, then High Impedance

8.3.18 Good Battery Monitor

The BQ2416xx contains a good battery monitor circuit that places the BQ2416xx into high-z mode if the battery

voltage is above the BATGD threshold while in DEFAULT mode. This function is used to enable compliance to

the battery charging standard that prevents charging from an un-enumerated USB host while the battery is

above the good battery threshold. If the BQ2416xx is in HOST mode, it is assumed that USB host has been

enumerated and the good battery circuit has no effect on charging.

8.4 Device Functional Modes

The state machine of the BQ2416x automatically changes primary states (Off, sleep, HiZ, charge disabled,

charging, charge done, battery OVP, fault) based on data in the I²C registers, IN and USB pin voltages, BAT pin

voltage and current flow, TS pin voltage, CD pin voltage and status of the safety timer. The BAT and TS pin

voltages as well as current flow into the IN and USB pins, out of SYS pin and into/out of the BAT pin determine

the charging sub-states, including conditioning, constant current (CC), CC with reduced charge current, constant

voltage (CV) with reduced charge current.

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8.5 Programming

8.5.1 Serial Interface Description

The BQ2416xx uses an I²C-compatible interface to program charge parameters. I²C is a 2-wire serial interface

developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1, January 2000). The bus consists of

a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines

are pulled high. All I²C-compatible devices connect to the I²C bus through open drain I/O pins, SDA and SCL. A

host device, usually a microcontroller or a digital signal processor, controls the bus. The host is responsible for

generating the SCL signal and device addresses. The host also generates specific conditions that indicate the

START and STOP of data transfer. A target device receives and/or transmits data on the bus under control of the

host device.

The BQ2416xx device works as a target and supports the following data transfer modes, as defined in the I²C

Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the

battery charging solution, enabling most functions to be programmed to new values depending on the

instantaneous application requirements. Register contents remain intact as long as battery voltage remains

above 2.5 V (typical). The I²C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is

not connected, the I²C circuitry is powered from the battery through BAT. The battery voltage must stay above

2.5 V with no input connected in order to maintain proper operation.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The BQ2416xx devices only support 7-bit addressing. The device 7-bit address is

defined as ‘1101011’(6Bh).

8.5.1.1 F/S Mode Protocol

The host initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in 图 8-8. All I²C-compatible devices should

recognize a start condition.

DATA

CLK

START Condition

STOP Condition

图8-8. START and STOP Condition

The host then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on

the SDA line. During all transmissions, the host ensures that data is valid. A valid data condition requires the

SDA line to be stable during the entire high period of the clock pulse (see 图 8-9). All devices recognize the

address sent by the host and compare it to their internal fixed addresses. Only the target device with a matching

address generates an acknowledge (see 图 8-10) by pulling the SDA line low during the entire high period of the

ninth SCL cycle. Upon detecting this acknowledge, the host knows that communication link with a target has

been established.

DATA

CLK

Chang

of Data

Allowed

Data Line

Stable

Data Valid

图8-9. Bit Transfer on the Serial Interface

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The host generates further SCL cycles to either transmit data to the target (R/W bit 1) or receive data from the

target (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the host or by the target, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the host generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see 图8-11). This releases the bus and stops the communication link

with the addressed target. All I²C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching

address. If a transaction is terminated prematurely, the host needs sending a STOP condition to prevent the

target I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in

this section result in FFh being read out.

Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

SCL From

Host

Clock Pulse for

Acknowledgement

START

Condition

图8-10. Acknowledge on the I²C Bus

Recognize START or

REPRATED START

Condition

Recognize STOP or

REPRATED START

Condition

Generate ACKNOWLEDGE

Signal

SDA

Acknowledgment

Signal From Target

MSB

Address

R/W

SCL

ACK

Clock Line Held Low While

Interrupts are Serviced

图8-11. Bus Protocol

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8.6 Register Maps

8.6.1 Status/Control Register (READ/WRITE)

Memory location: 00, Reset state: 0xxx 0xxx

BIT

NAME

READ/WRITE

FUNCTION

B7 (MSB)

TMR_RST

Read/Write

Write: TMR_RST function, write “1”to reset the watchdog timer (auto clear)

Read: Always 0

(BQ24160/1/3 only)

STAT_2

STAT_1

STAT_0

Read only

000- No Valid Source Detected

001- IN Ready (shows preferred source when both connected)

010- USB Ready (shows preferred source when both connected)

011- Charging from IN

100- Charging from USB

101- Charge Done

110- NA

111- Fault

SUPPLY_SEL

Read/Write

0-IN has precedence when both supplies are connected

1-USB has precedence when both supplies are connected (default 0)

FAULT_2

FAULT_1

FAULT_0

Read only

000-Normal

001- Thermal Shutdown

010- Battery Temperature Fault

011- Watchdog Timer Expired (BQ24160/1/1B/3 only)

100- Safety Timer Expired (BQ24160/1/1B/3 only)

101- IN Supply Fault

B0 (LSB)

110- USB Supply Fault

111- Battery Fault

SUPPLY_SEL Bit (Supply Precedence Selector)

The SUPPLY_SEL bit selects which supply has precedence when both supplies are present. In cases where both supplies are

connected, they must remain isolated from each other which means only one is allowed to charge the battery. Write a 1 to

SUPPLY_SEL to select the USB input to have precedence. Write a 0 to select the IN input.Note the following behavior when

switching the SUPPLY_SEL bit with both supplies attached:

•

The BQ2416xx returns to high impedance mode

The input supply is switched

The BQ2416xx begins a full startup cycle starting with bad adapter detection then proceeding to soft-start

Similarly, if charging from the non-preferred supply when the preferred supply is attached, the BQ2416xx follows the same

procedure.

STAT_x and FAULT_x Bits

The STAT_x show the current status of the device and are updated dynamically as the IC changes state. The FAULT_x bits show

faults that have occurred and are only cleared by reading the bits, assuming the fault no longer exists. If multiple faults occur, the

first one is the one that is shown.

8.6.2 Battery/ Supply Status Register (READ/WRITE)

Memory location: 01, Reset state: xxxx 0xxx

BIT

B7 (MSB)

NAME

INSTAT1

INSTAT0

READ/WRITE

Read Only

FUNCTION

00-Normal

01-Supply OVP

10-Weak Source Connected (No Charging)

11- V_IN<V_UVLO

Read Only

USBSTAT1

USBSTAT0

Read Only

00-Normal

01-Supply OVP

01-Weak Source Connected (No Charging)

11- V_USB<V_UVLO

OTG_LOCK

Read/Write

0 –No OTG supply present. Use USB input as normal.

1 –OTG supply present. Lockout USB input for charging.

(default 0)

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BIT

NAME

READ/WRITE

Read Only

FUNCTION

BATSTAT1

BATSTAT0

00-Battery Present and Normal

01-Battery OVP

10-Battery Not Present

11- NA

Read Only

B0 (LSB) EN_NOBATOP

Read/ Write

0-Normal Operation

1-Enables No Battery Operation when termination is disabled (default 0)

OTG_LOCK Bit (USB Lockout)

The OTG_LOCK bit is used to prevent any charging from USB input regardless of the SUPPLY_SEL bit and IN supply status.

For systems using OTG supplies, it is not desirable to charge from an OTG source. Doing so would mean draining the battery by

allowing it to effectively charge itself. Write a “1”to OTG_LOCK to lock out the USB input. Write a “0”to OTG_LOCK to

return to normal operation. During OTG lock, the USB input is ignored and DRV does not come up. The watchdog timer must be

reset while in USB_LOCK to maintain the USB lockout state. This prevents the USB input from being permanently locked out for

cases where the host loses I²C communication with OTG_LOCK set (for example, discharged battery from OTG operation). See

the Safety Timer and Watchdog Timer section for more details.

EN_NOBATOP (No Battery Operation)

The EN_NOBATOP bit enables no battery operation. When using the BQ2416x without a battery attached, it is recommended to

first disable charging, then disable charge termination and finally set this bit to 1. Setting this bit to 1 also disables the reverse

boost prevention circuit and the BATOVP circuit. With a battery attached, setting this bit to 1 may be helpful to ensure full battery

charging as explained in the reverse battery prevention circuit section. In the event of battery overvoltage (for example, recovery

from large SYS load transient requiring supplement), the BATOVP protection circuit turns off the buck converter to allow the

battery to discharge through SYS.

8.6.3 Control Register (READ/WRITE)

Memory location: 02, Reset state: 1000 1100

BIT

NAME

READ/WRITE FUNCTION

B7 (MSB)

RESET

Write only

Write: 1 –Reset all registers to default values

0 –No effect

Read: always get 1

IUSB_LIMIT_2

IUSB_LIMIT_1

IUSB_LIMIT _0

Read/Write

000 –USB2.0 host with 100-mA current limit

001 –USB3.0 host with 150-mA current limit

010 –USB2.0 host with 500-mA current limit

011 –USB host/charger with 800-mA current limit

100 –USB3.0 host with 900-mA current limit

101 –USB host/charger with 1500-mA current limit

110–111 –NA (default 000⁽¹⁾

)

EN_STAT

Read/Write

1 –Enable STAT output to show charge status,

0-Disable STAT output for charge status. Fault interrupts are still show even when

EN_STAT = 0. (default 1)

Read/Write

1 –Enable charge current termination,

0-Disable charge current termination (default 1)

1 –Charging is disabled

0 –Charging enabled (default 0 BQ24160/1/1B/3/8)

B0 (LSB)

HZ_MODE

1 –High impedance mode

0 –Not high impedance mode (default 0)

(1) When in DEFAULT mode, the D+/D–(BQ24160) or PSEL (BQ24161/8) inputs determine the input current limit for the USB input.

RESET Bit

The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write 1 to RESET bit to reset all the

registers to default values and place the BQ2416xx into DEFAULT mode and turn off the watchdog timer. The RESET bit is

automatically cleared to zero once the BQ2416xx enters DEFAULT mode.

CE Bit (Charge Enable)

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The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic level (0) on this bit enables

the charge and a high logic level (1) disables the charge. When charge is disabled, the SYS output regulates to VSYS(REG) and

battery is disconnected from the SYS. Supplement mode is still available if the system load demands cannot be met by the

supply.

HZ_MODE Bit (High Impedance Mode Enable)

The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance mode. A low logic level (0) on

this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state called high impedance mode. When

in high impedance mode, the converter is off and the battery FET and BGATE are on. The load on SYS is supplied by the

battery.

8.6.4 Control/Battery Voltage Register (READ/WRITE)

Memory location: 03, Reset state: 0001 0100

BIT

B7 (MSB)

NAME

V_BREG5

V_BREG4

V_BREG3

V_BREG2

V_BREG1

V_BREG0

I_INLIMIT

READ/WRITE FUNCTION

Read/Write

Battery Regulation Voltage: 640 mV (default 0)

Battery Regulation Voltage: 320 mV (default 0)

Battery Regulation Voltage: 160 mV (default 0)

Battery Regulation Voltage: 80 mV (default 1)

Battery Regulation Voltage: 40 mV (default 0)

Battery Regulation Voltage: 20 mV (default 1)

Input Limit for IN input-

0 –1.5 A

1 –2.5 A (default 0)

B0 (LSB)

Read/Write

D+/D–_EN

0 –Normal state, D+/D- Detection done

1 –Force D+/D–Detection. Returns to 0 after detection is done. (default 0)

• Charge voltage range is 3.5 V –4.44 V with the offset of 3.5 V and step of 20 mV (default 3.6 V).

• Before writing to increase VBATREG register following a BATOVP event (for example, IN or USB voltage is

applied, IC remains in DEFAULT mode and then VBAT > 3.6 V is attached), toggle the HiZ bit or CD pin to

clear the BATOVP fault.

8.6.5 Vender/Part/Revision Register (READ only)

Memory location: 04, Reset state: 0100 0000

BIT

B7 (MSB)

NAME

Vender2

Vender1

Vender0

PN1

READ/WRITE FUNCTION

Read only

Vender Code: bit 2 (default 0)

Vender Code: bit 1 (default 1)

Vender Code: bit 0 (default 0)

For I²C Address 6Bh:

00: BQ2416xx

01–11: Future product spins

PN0

Revision2

Revision1

Revision0

Read only

000: Revision 1.0

001: Revision 1.1

010: Revision 2.0

011: Revision 2.1

100: Revision 2.2

101: Revision 2.3

110-111: Future Revisions

B0 (LSB)

8.6.6 Battery Termination/Fast Charge Current Register (READ/WRITE)

Memory location: 05, Reset state: 0011 0010

BIT

B7 (MSB)

NAME

I_CHRG4

I_CHRG3

READ/WRITE FUNCTION

Read/Write

Charge current: 1200 mA –(default 0)

Charge current: 600 mA –(default 0)

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BIT

NAME

I_CHRG2

I_CHRG1

I_CHRG0

I_TERM2

I_TERM1

I_TERM0

READ/WRITE FUNCTION

Read/Write

Charge current: 300 mA –(default 1)

Charge current: 150 mA –(default 1)

Charge current: 75 mA (default 0)

Termination current sense voltage: 200 mA (default 0)

Termination current sense voltage: 100 mA (default 1)

Termination current sense voltage: 50 mA (default 0)

B0 (LSB)

• Charge current sense offset is 550 mA and default charge current is 1000 mA.

• Termination threshold offset is 50 mA and default termination current is 150 mA

8.6.7 V_IN-DPMVoltage/ DPPM Status Register

Memory location: 06, Reset state: xx00 0000

BIT

NAME

READ/WRITE

FUNCTION

B7(MSB)

MINSYS_STATUS

Read Only

1 –Minimum System Voltage mode is active (V_BAT<V_MINSYS

0 –Minimum System Voltage mode is not active

)

DPM_STATUS

Read Only

1 –V_IN-DPM mode is active

0 –V_IN-DPM mode is not active

V_INDPM2(USB)

V_INDPM1(USB)

V_INDPM0(USB)

V_INDPM2(IN)

V_INDPM1(IN)

V_INDPM0(IN)

Read/Write

USB input V_IN-DPMvoltage: 320 mV (default 0)

USB input V_IN-DPMvoltage: 160 mV (default 0)

USB input V_IN-DPMvoltage: 80 mV (default 0)

IN input V_IN-DPMvoltage: 320 mV (default 0)

IN input V_IN-DPMvoltage: 160 mV (default 0)

IN input V_IN-DPMvoltage: 80 mV (default 0)

B0(LSB)

• V_IN-DPMvoltage offset is 4.20 V and default V_IN-DPMthreshold is 4.20 V.

8.6.8 Safety Timer/ NTC Monitor Register (READ/WRITE)

Memory location: 07, Reset state: 1001 1xxx

BIT

NAME

READ/WRITE FUNCTION

B7 (MSB)

2XTMR_EN

Read/Write

1 –Timer slowed by 2x when in thermal regulation, input current limit, V_{IN_DPM}or

DPPM

0 –Timer not slowed at any time (default 0) (BQ24160/1 only)

TMR_1

TMR_2

Read/Write

Safety Timer Time Limit –

00 –27 minute fast charge

01 –6 hour fast charge

10 –9 hour fast charge

11 –Disable safety timers (default 00) (BQ24160/1 only)

Read/Write

TS_EN

0 –TS function disabled

1 –TS function enabled (default 1)

TS_FAULT1

TS_FAULT0

Read only

TS Fault Mode:

00 –Normal, No TS fault

01 –TS temp < T_COLDor TS temp > T_HOT(Charging suspended)

10 –T_COOL> TS temp > T_COLD(Charge current reduced by half, BQ24160 only)

11 –T_WARM< TS temp < T_HOT(Charge voltage reduced by 140 mV, BQ24160 only)

B0 (LSB)

LOW_CHG

Read/ Write

0 –Charge current as programmed in Register 0x05

1 –Charge current is half programmed value in Register 0x05

(default 0)

2xTMR_EN Bit (2x Timer Enable)

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The 2xTMR_EN bit is used to slow down the timer when charge current is reduced by the system load. When 2xTMR_EN is a 1,

the safety timer is slowed to half speed effectively doubling the timer time. The conditions that activate the 2x timer are: Input

Current Limit, V_INDPM, Thermal Regulation, LOW_CHG, BATSHRT and TS Cool. When 2xTMR_EN is a 0, the timer operates at

normal speed in all conditions.

LOW_CHG Bit (Low Charge Mode Enable)

The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is used by systems where

battery NTC is monitored by the host and requires a reduced charge current setting or by systems that need a

“preconditioning”current for low battery voltages. Write a 1 to this bit to charge at half of the programmed charge current

(BQ24160/1/3/8). Write a 0 to this bit to charge at the programmed charge current.

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9 Application and Implementation

9.1 Application Information

A typical application circuit using the BQ24160 with a smartphone's GSM power amplifier (PA) powered directly

from the battery is shown in 图9-1. A typical application circuit using the BQ24161 with a smartphone's GSM PA

powered from the SYS rail, to allow for calls even with a deeply discharged battery, is shown in 图 9-2. Each

circuit shows the minimum capacitance requirements for each pin and typical recommended inductance value of

1.5 µH. The TS resistor divider for configuring the TS function for the battery's specific thermistor can be

computed from equations 方程式 1 and 方程式 2. The resistor on STAT is sized per the LED current

requirements. All other configuration settings for VINDPM, input current limit, charge current and charge voltage

are made in EEPROM registers using I²C commands. Options for sizing the inductor outside the 1.5 µH

recommended value and additional SYS pin capacitance are explained in the next section.

9.2 Typical Application

ADAPTER

1.5 mH

PMIDI

System

Load

0.01 mF

1 mF

4.7 mF

BOOT

SYS

USB

VBUS

D+

D-

10 mF

PMIDU

PGND

GND

1 mF

4.7 mF

BGATE

DRV

BAT

VDRV

1 mF

GSM

PACK+

STAT

TEMP

V_SYS

(1.8V)

D+

D-

PACK-

HOST

BQ24160

GPIO1

INT

SDA

SCL

SDA

SCL

图9-1. BQ24160, Shown with no External Discharge FET, PA Connected to Battery

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ADAPTER

1.5 mH

PMIDI

System

Load

0.01 mF

1 mF

4.7 mF

BOOT

USB

SYS

VBUS

D+

10 mF

PMIDU

D-

PGND

GND

1 mF

4.7 mF

BGATE

GSM

DRV

BAT

VDRV

1 mF

PACK+

STAT

PSEL

TEMP

V_SYS

(1.8V)

USB PHY

PACK-

HOST

BQ24161

GPIO1

INT

SDA

SCL

SDA

SCL

图9-2. BQ24161, Shown with External Discharge FET, PA Connected to System for GSM Call Support

with a Deeply Discharged or No Battery

9.2.1 Design Requirements

MIN

4.2

3.3

TYP

MAX

UNIT

Supply voltage, V_IN

USB voltage, V_USB

System voltage, V_SYS

Input voltage from ac adapter

Input voltage from USB or equivalent supply

Voltage output at SYS terminal (depends on VBAT voltage and

VBATRE

G+4.17%

status of V_INDPM

)

Battery voltage, V_BAT

Supply current, I_IN(MAX)

Supply current, I_USB(MAX)

Voltage output at VBAT terminal (registers set via I²C

communication)

1.5

4.2

0.5

4.44

Maximum input current from ac adapter input (registers set via

I²C communication)

2.5

Maximum input current from USB input (registers set via I²C

communication)

0.1

1.5

Fast charge current,

I_CHRG(MAX)

Battery charge current (registers set via I²C communication)

0.550

-40

2.5

Operating junction temperature range, T_J

125

°C

9.2.2 Detailed Design Procedure

9.2.2.1 Output Inductor and Capacitor Selection Guidelines

When selecting an inductor, several attributes must be examined to find the right part for the application. First,

the inductance value should be selected. The BQ2416xx is designed to work with 1.5-µH to 2.2-µH inductors.

The chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some

efficiency gain is reached using the 2.2-µH inductor, however, due to the physical size of the inductor, this may

not be a viable option. The 1.5-µH inductor provides a good tradeoff between size and efficiency.

Once the inductance has been selected, the peak current must be calculated in order to choose the current

rating of the inductor. Use 方程式5 to calculate the peak current.

RIPPPLE

I_PEAK= I_LOAD(MAX)

(5)

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The inductor selected must have a saturation current rating greater than or equal to the calculated I_PEAK. Due to

the high currents possible with the BQ2416xx, a thermal analysis must also be done for the inductor. Many

inductors have a 40°C temperature-rise rating. The DC component of the current can cause a 40°C temperature

rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used

adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5-A DC load with

peaks at 2.5 A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7 A:

I_TEMPRISE= I_LOAD+ D ´

(

- I_LOAD= 1.5A + 0.2 × 2.5A -1 .5A = 1.7A

(

)

PEAK

(6)

The BQ2416xx provides internal loop compensation. Using this scheme, the BQ2416xx is stable with 10 µF to

200 µF of local capacitance on the SYS output. The capacitance on the SYS rail can be higher if distributed

amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10 µF

and 47 µF is recommended for local bypass to SYS. A 47-µF bypass capacitor is recommended for optimal

transient response.

9.2.3 Application Curves

USB500

925-mA Charge Setting

1500-mA ILIM

1300-mA Charge Setting

图9-3. USB Plug-In with Battery Connected

图9-4. IN Plug-in with Battery Connected

Termination Enabled

图9-5. Adapter Detection USB

图9-6. Battery Insert During Battery Detection

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

Termination Enabled

MINSYS Operation USB1500

200-mA to 1400-mA Load Step on SYS

图9-7. Battery Pull During Charging

图9-8. Load Transient into DPPM

V_USB

5 V/div

V_SYS

V_BAT

5 V/div

V_STAT/INT

1 V/div

5 V/div

V_SW

I_USB

500 mA/div

1 A/div

I_BAT

500 mA/div

10 ms/div

4 ms/div

MINSYS Operation USB500

200-mA to 1400-mA Load Step on SYS

图9-10. OVP Fault USB Input

图9-9. Load Transient into Supplement Mode

100

V_IN= 5 V

V_IN= 7 V

V_IN= 9 V

V_USB= 5 V

V_USB= 6 V

0.1

System Current (A)

G001

G002

Charge Disabled

IN2500 ILIM

SYS loaded

V_BATREG= 3.6 V

Charge Disabled

USB1500 ILIM

SYS loaded

V_BATREG= 3.6 V

图9-11. IN Efficiency

图9-12. USB Efficiency

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

10 Power Supply Recommendations

10.1 Requirements for SYS Output

In order to provide an output voltage on SYS, the BQ2416xx requires either a power supply between 4.2 V and

6.0 V for USB input on all versions, 4.2 V and 6.0 V for IN input on BQ24168 and 4.2 V and 10.0 V on the

remaining versions with at least 100-mA current rating connected to IN or USB or a single-cell LiIon battery with

voltage > V_BATUVLOconnected to BAT. The source current rating needs to be at least 2.5 A in order for the

charger's buck converter to provide maximum output power to SYS.

10.2 Requirements for Charging

In order for charging to occur, the source voltage as measured at the IC's USB or IN pins (factoring in cable/

trace losses from the source) must be greater than the VINDPM threshold (but less than the maximum values

above) and the source's current rating must be higher than the buck converter needs to provide the load on

SYS. For charging at a desired charge current of I_CHRG, V_USBorINx I_USBorINx η > V_SYSx (I_SYS+ I_CHRG) where η

is the efficiency estimate from 图7-1 or 图7-2 and V_SYS= V_BATwhen V_BATcharges above V_MINSYS. The charger

limits I_USBorINto that input's current limit setting. With I_SYS= 0 A, the charger consumes maximum power at the

end of CC mode, when the voltage at the BAT pin is near V_BATREGbut I_CHRGhas not started to taper off toward

I_TERM

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

11 Layout

11.1 Layout Guidelines

It is important to pay special attention to the PCB layout. 图 11-1 provides a sample layout for the high current

paths of the BQ2416xx. A list of layout guidelines follows.

• To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be

placed as close as possible to the BQ2416xx

• Minimize the amount of inductance between BAT and the postive connection of the battery terminal. If a large

parasitic board inductance on BAT is expected, increase the bypass capacitance on BAT.

• Place 4.7-µF input capacitor as close to PMID_ pin and PGND pin as possible to make high frequency

current loop area as small as possible. Place 1-µF input capacitor GNDs as close to the respective PMID cap

GND and PGND pins as possible to minimize the ground difference between the input and PMID_.

• The traces from the input connector to the inputs of the BQ2416xx should be as wide as possible to minimize

the impedance in the line. Although the VINDPM feature will allow operation from input sources having high

resistances(impedances), the BQ2416xx input pins (IN and USB) have been optimized to connect to input

sources with no more than 350 mΩ of input resistance, including cables and PCB traces

• The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the

IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the

PGND pin.

• Place all decoupling capacitors close to their respective IC pins and as close as to PGND (do not place

components such that routing interrupts power stage currents). All small control signals should be routed

away from the high-current paths.

• The PCB should have a ground plane (return) connected directly to the return of all components through vias

(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is

also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is

typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces

noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this

small layout and a single ground plane, there is no ground-bounce issue, and having the components

segregated minimizes coupling between signals.

• The high-current charge paths into IN, USB, BAT, SYS and from the SW pins must be sized appropriately for

the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be

connected to the ground plane to return current through the internal low-side FET.

• For high-current applications, the balls for the power paths should be connected to as much copper in the

board as possible. This allows better thermal performance because the board conducts heat away from the

IC.

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BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

www.ti.com.cn

11.2 Layout Example

WCSP

VQFN

图11-1. Recommended BQ2416xx PCB Layout

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

BQ24160, BQ24160A, BQ24161, BQ24161B, BQ24163, BQ24168

www.ti.com.cn

ZHCS384H –NOVEMBER 2011 –REVISED JULY 2022

12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: BQ24160 BQ24160A BQ24161 BQ24161B BQ24163 BQ24168

PACKAGE OPTION ADDENDUM

www.ti.com

28-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ24160ARGER

BQ24160ARGET

BQ24160RGER

BQ24160RGET

ACTIVE

VQFN

RGE

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

0 to 125

-40 to 85

24160A

Samples

ACTIVE

RGE

NIPDAU

24160A

RGE

24160

RGE

24160

BQ24160YFFR

BQ24160YFFT

BQ24161BRGER

ACTIVE

DSBGA

VQFN

YFF

RGE

SNAGCU

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 85

BQ24160

Samples

BQ24160

24161B

BQ24161BRGET

ACTIVE

VQFN

RGE

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

24161B

Samples

BQ24161BYFFR

BQ24161RGER

ACTIVE

DSBGA

VQFN

YFF

3000 RoHS & Green

SNAGCU

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

BQ24161B

Samples

RGE

-40 to 85

24161

BQ24161RGET

ACTIVE

VQFN

RGE

250

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

24161

Samples

BQ24161YFFR

BQ24161YFFT

BQ24163RGER

ACTIVE

DSBGA

VQFN

YFF

RGE

SNAGCU

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 85

BQ24161

Samples

BQ24161

24163

BQ24163RGET

ACTIVE

VQFN

RGE

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

24163

Samples

BQ24163YFFR

BQ24163YFFT

BQ24168RGER

ACTIVE

DSBGA

VQFN

YFF

RGE

SNAGCU

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 85

BQ24163

Samples

BQ24163

24168

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Jul-2022

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ24168RGET

ACTIVE

VQFN

RGE

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

24168

Samples

BQ24168YFFR

BQ24168YFFT

ACTIVE

DSBGA

YFF

3000 RoHS & Green

250 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 85

BQ24168

Samples

BQ24168

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

28-Jul-2022

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24160ARGER

BQ24160ARGET

BQ24160RGER

BQ24160RGET

BQ24160YFFR

BQ24160YFFT

BQ24161BRGER

BQ24161BRGET

BQ24161BYFFR

BQ24161RGER

BQ24161RGET

BQ24161YFFR

BQ24161YFFT

BQ24163RGER

BQ24163RGET

BQ24163YFFR

VQFN

RGE

YFF

RGE

YFF

RGE

YFF

RGE

YFF

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

330.0

180.0

12.4

8.4

4.25

2.93

4.25

2.93

4.25

2.93

4.25

2.93

4.25

2.93

4.25

2.93

4.25

2.93

4.25

2.93

1.15

0.81

1.15

0.81

1.15

0.81

1.15

0.81

8.0

4.0

8.0

4.0

8.0

4.0

8.0

4.0

12.0

8.0

VQFN

3000

250

VQFN

DSBGA

VQFN

3000

250

8.4

8.0

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

VQFN

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

VQFN

3000

250

8.4

8.0

3000

250

12.4

8.4

12.0

8.0

VQFN

DSBGA

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24163YFFT

BQ24168RGER

BQ24168RGET

BQ24168YFFR

BQ24168YFFT

DSBGA

VQFN

YFF

RGE

YFF

250

3000

250

180.0

330.0

180.0

8.4

12.4

8.4

2.93

4.25

2.93

4.25

2.93

0.81

1.15

0.81

4.0

8.0

4.0

8.0

12.0

8.0

VQFN

DSBGA

3000

250

8.4

8.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24160ARGER

BQ24160ARGET

BQ24160RGER

BQ24160RGET

BQ24160YFFR

BQ24160YFFT

BQ24161BRGER

BQ24161BRGET

BQ24161BYFFR

BQ24161RGER

BQ24161RGET

BQ24161YFFR

BQ24161YFFT

BQ24163RGER

BQ24163RGET

BQ24163YFFR

BQ24163YFFT

BQ24168RGER

VQFN

RGE

YFF

RGE

YFF

RGE

YFF

RGE

YFF

RGE

3000

250

346.0

210.0

346.0

210.0

182.0

346.0

210.0

182.0

346.0

210.0

182.0

346.0

210.0

182.0

346.0

185.0

346.0

185.0

182.0

346.0

185.0

182.0

346.0

185.0

182.0

346.0

185.0

182.0

346.0

33.0

35.0

33.0

35.0

20.0

33.0

35.0

20.0

33.0

35.0

20.0

33.0

35.0

20.0

33.0

VQFN

3000

250

VQFN

DSBGA

VQFN

3000

250

3000

250

VQFN

DSBGA

VQFN

3000

250

VQFN

DSBGA

VQFN

3000

250

3000

250

VQFN

DSBGA

VQFN

3000

250

3000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24168RGET

BQ24168YFFR

BQ24168YFFT

VQFN

DSBGA

RGE

YFF

250

3000

250

210.0

182.0

185.0

182.0

35.0

20.0

Pack Materials-Page 4

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ

(0.2) TYP

2X 2.5

20X 0.5

SYMM

2.5

0.30

PIN 1 ID

(OPTIONAL)

24X

0.18

0.1

0.05

C A B

SYMM

0.48

0.28

24X

4219016 / A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

2.7)

(

24X (0.58)

24X (0.24)

20X (0.5)

SYMM

(3.825)

(1.1)

ꢆꢄꢂꢁꢇꢀ9,$

TYP

(R0.05)

2X(1.1)

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)

24X (0.58)

24X (0.24)

20X (0.5)

SYMM

(3.825)

(0.694)

TYP

(R0.05) TYP

METAL

TYP

(0.694)

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

D: Max = 2.771 mm, Min = 2.71 mm

E: Max = 2.771 mm, Min = 2.71 mm

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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