BQ24273RGET [TI]
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Integrated Current Sense; 2.5A ，单输入，单节开关模式锂离子电池充电器，带有集成电流检测
| 型号： | BQ24273RGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Integrated Current Sense |
| 文件： | 总27页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24273
www.ti.com
SLUSB08 –JUNE 2012
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with
Integrated Current Sense
Check for Samples: bq24273
1
FEATURES
APPLICATIONS
•
High-Efficiency Switch Mode Charger with
Integrated Current Sense Element
•
•
•
•
Handheld Prducts
Portable Media Players
Portable Equipment
•
Single Input Charger
–
20V input rating, with 10.5V Over-Voltage
Protection (OVP)
Tablets and Portable Internet Devices
APPLICATION SCHEMATIC
–
Integrated FETs for Up to 2.5A Charge Rate
•
•
Integrated Charge Current Sense Element for
Reduced BOM Count and Board Space
Savings
IN
SW
PMID
BOOT
CS+
Safe and accurate Battery Management
Functions
–
–
0.5% Battery Regulation Accuracy
10% Charge Current Accuracy
`
SDA
SCL
•
•
Voltage-based, NTC Monitoring Input (TS)
JEITA Compatible
CD
BAT
–
INT
HOST
System
Load
Thermal Regulation Protection for Output
Current Control
PACK+
TEMP
BYP
TS
•
•
•
•
BAT Short-Circuit Protection
STAT
DRV
PGND
PACK-
Soft-Start Feature to Reduce Inrush Current
Thermal Shutdown and Protection
Available in Small 49-ball WCSP or QFN-24
Packages
DESCRIPTION
The bq24273 is a highly integrated single cell Li-Ion battery charger with integrated charge current sense
element device targeted for space-limited, portable applications with high capacity batteries. The single cell
charger operates from a dedicated power source such as a wall adapter or wireless power supply for a versatile
solution. The integrated sense element eliminates the need for an external sense resistor reducing the total
solution size and external component count.
The battery is charged in three phases: precharge, fast charge constant current and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Charge is terminated based on user-selectable minimum current
level. A software watchdog provides a safety backup for I2C interface while a safety timer prevents continuously
charging a damaged battery. During normal operation, bq24273 automatically restarts the charge cycle if the
battery voltage falls below an internal threshold and automatically enters sleep mode or high impedance mode
when the input supply is removed. The charge status is reported to the host using the I2C interface. Additionally,
a voltage-based battery pack thermistor monitoring input (TS) is included that monitors battery temperature for
safe charging. The TS function for bq24273 JEITA compatible.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24273
SLUSB08 –JUNE 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
NTC MONITORING
PART NUMBER
OVP
JEITA COMPATIBLE
PACKAGE
(TS)
Yes
Yes
bq24273YFFR
bq24273YFFT
10.5 V
10.5 V
Yes
Yes
WCSP
WCSP
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
20
UNIT
V
IN
BYP, PMID, BOOT
SW
–0.3
–0.7
–0.3
–0.3
20
V
Pin voltage range (with
respect to VSS)
12
V
CS+, BAT, BGATE, DRV, STAT, INT, SDA, SCL, CD,TS
7
V
BOOT to SW
7
V
Output Current (Continuous)
Input Current (Continuous)
Output Sink Current
SW
4.5
2.75
10
A
IN
A
STAT, INT
mA
°C
°C
°C
°C
Operating free-air temperature range
Junction temperature, TJ
–40
–40
–65
85
125
150
300
Storage temperature, TSTG
Lead temperature (soldering, 10 s)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
bq24273
THERMAL METRIC(1)
UNITS
49 PINS (YFF)
θJA
Junction-to-ambient thermal resistance
49.8
0.2
1.1
1.1
6.6
n/a
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
spacer
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNITS
IN voltage range
VIN
4.2
4.2
18(1)
V
IN operating range
10
IIN
Input current IN input
Charging
2.5
A
A
IBAT
TJ
2.5
Operating junction temperature range
0
125
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP
PWM switching
,
15
mA
IIN
Input quiescent current
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP
PWM NOT switching
,
5
0°C< TJ < 85°C, High-Z Mode
175
5
μA
μA
IBATLEAK
IBAT_HIZ
Leakage current from BAT to the supply
0°C< TJ < 85°C, VBAT = 4.2V, VIN = 0V
Battery discharge current in high impedance mode,
(BAT, SW)
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0 V or 5 V, High-Z
mode
55
μA
BATTERY CHARGER
RON(BAT-CS+) Internal battery charger MOSFET on-resistance
YFF pkg
RGE pkg
37
50
57
70
Measured from BAT to CS+,
VBAT = 4.2V
mΩ
Battery regulation voltage
3.5
–0.5%
–1%
4.44
0.5%
1%
V
VBATREG
TA = 25°C
Battery regulation voltage accuracy
Over temperature
VBATSHRT < VBAT < VBATREG
0°C to 125°C
Charge current programmable range
Fast charge current accuracy
550
2500
10%
3.1
mA
ICHARGE
–10%
2.9
VBATSHRT
IBATSHRT
tDGL(BATSHRT)
ITERM
Battery short threshold
VBAT Rising, 100 mV Hysteresis
VBAT < VBATSHRT
3.0
50.0
32
V
Battery short current
mA
ms
Deglitch time for battery short to fast charge transition
Termination charge current accuracy
ICHARGE = 50 mA
ICHARGE > 50 mA
–35%
–15%
35%
15%
Both rising and falling, 2-mV over-drive,
tRISE, tFALL = 100 ns
tDGL(TERM)
Deglitch time for charge termination
32
ms
VRCH
Recharge threshold voltage
Deglitch time
Below VBATREG
120
32
mV
ms
tDGL(RCH)
VBAT falling below VRCH, tFALL = 100ns
During battery detection source cycle
During battery detection sink cycle
3.3
3.0
VDETECT
Battery detection voltage threshold
V
Battery detection current before charge done (sink
current)
IDETECT
2.5
mA
tDETECT
VIH(CD)
VIL(CD)
Battery detection time
CD input high logic level
CD input low logic level
250
ms
V
1.3
0.4
V
INPUT PROTECTION
IINLIM = 1.5 A
IINLIM = 2.5 A
1.35
2.3
4.2
–2%
5
1.5
2.5
1.65
2.8
IINLIM
Input current limit
VIN=5V, DC current pulled from SW
A
V
Input DPM threshold
4.76
2%
VIN_DPM
Input DPM accuracy
VDRV
Internal bias regulator voltage
DRV Output current
5.2
5.45
V
IDRV
10
mA
mV
V
VDO_DRV
VUVLO
VSLP
DRV Dropout voltage (VIN – VDRV
)
IIN = 1A, VIN = 5V, IDRV = 10mA
VIN rising, 150 mV hysteresis
2.0 V ≤ VBAT ≤ VOREG, VIN falling
2.0 V ≤ VBAT ≤ VOREG
450
4.0
IC active threshold voltage
3.6
0
3.8
40
Sleep-mode entry threshold, VIN-VBAT
Sleep-mode exit hysteresis
100
160
mV
mV
VSLP_EXIT
40
100
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
Rising voltage, 2-mV over drive, tRISE=100ns
IN, VIN Rising, 100 mV hysteresis
MIN
TYP
MAX
UNITS
Deglitch time for supply rising above
VSLP+VSLP_EXIT
30
ms
V
VOVP
Input supply OVP threshold voltage
Battery OVP threshold voltage
10.3
10.5
10.7
1.025 ×
VBATREG
1.05 ×
VBATREG
1.075 ×
VBATREG
VBOVP
VBAT threshold over VOREG to turn off charger during charge
V
% of
VBATREG
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
1
VBATUVLO
Battery UVLO threshold voltage
Bad source detection threshold
2.5
V
V
VIN_DPM
–
VBAT_SOURCE
80mV
Bad source detection deglitch
Cycle by cycle current limit
Thermal shutdown
32
ms
A
ILIMIT
4.1
4.9
5.6
TSHUTDWN
TREG
10°C Hysteresis
165
120
C
Thermal regulation threshold
Safety timer accuracy
C
–20%
20%
STAT, INT
IIH
High-level leakage current
V/CHG = V/PG = 5 V
1
µA
V
VOL
Low-level output saturation voltage
IO = 10 mA, sink current
0.4
PWM CONVERTER
Internal top reverse blocking MOSFET on-resistance
IIN_LIMIT = 1.5 A, Measured from VIN to PMIDU
Measured from PMID to SW
45
65
80
mΩ
mΩ
Internal top N-channel Switching MOSFET on-
resistance
110
Internal bottom N-channel MOSFET on-resistance
Oscillator frequency
Measured from SW to PGND
65
1.50
95%
115
mΩ
fOSC
1.35
0
1.65
MHz
DMAX
DMIN
Maximum duty cycle
Minimum duty cycle
BATTERY-PACK NTC MONITOR
VHOT
29.7
37.9
56.0
59.5
70
30
38.3
56.5
60
30.5
39.6
56.9
60.4
73
%VDRV
High temperature threshold
VTS falling, 1%VDRV Hysteresis
VWARM
VCOOL
VCOLD
VTSOFF
tDGL(TS)
VIH
%VDRV
%VDRV
Low temperature threshold
VTS rising, 1%VDRV Hysteresis
VTS rising, 2%VDRV Hysteresis
%VDRV
TS Disable threshold
Deglitch time on TS change
Input high threshold
%VDRV
50
ms
V
VPULLUP = 1.8 V, SDA and SCL
VPULLUP = 1.8 V, SDA and SCL
ISDA = 10 mA, sink current
1.3
VIL
Input low threshold
0.4
0.4
V
VOL
Output low threshold
Input high leakage current
Watchdog timer timeout
V
IIH
VPULLUP = 1.8 V, SDA and SCL
1
µA
s
tWATCHDOG
30
4
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SLUSB08 –JUNE 2012
BLOCK DIAGRAM
PMID
BYP
5.2V
Reference
DRV
IN
5A
BOOT
CbC Current
Limit
IN IINLIM
Q1
DC-DC CONVERTER PWM LOGIC,
COMPENSATION AND BATTERY
FET CONTROL
IN VINDPM
VSYS(REG)
IBAT(REG)
VBAT(REG)
SW
DIE Temp
Regulation
Q2
PGND
CS+
BAT
References
VSUPPLY
VIN
10% of
ICHARGE
+
VINOVP
+
OVP
Comparator
IBAT
Termination
Comparator
Recharge Comparator
+
Start Recharge
Cycle
VBATREG – 0.12V
VIN
+
VBAT
VBAT+VSLP
Sleep
Comparator
VSYSREG Comparator
+
VSYS
Enable Linear
Charge
VMINSYS
VBATSC Comparator
+
Enable
IBATSHRT
SDA
SCL
VBAT
I2C
Interface
VBATSHRT
TS
Supplement COMPARATOR
+
VSYS
VBSUP
VBAT
VDRV
VBOVP Comparator
+
VBAT
VBATOVP
+
CD
DISABLE
TS COLD
+
+
1C/
0.5C
TS COOL
4.2V/4.06V
STAT
INT
TS WARM
+
DISABLE
TS HOT
CHARGE
CONTROLLER
w/ Timer
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PIN CONFIGURATION
49-Ball WCSP (Top View)
1
2
3
4
5
6
7
IN
IN
IN
IN
GND
GND
GND
A
B
C
D
E
PMIDI
PMIDI
PMIDI
PMIDI
BYP
SW
BYP
SW
BYP
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
BOOT
PGND
PGND
PGND
N.C.
N.C.
CD
SDA
SCL
CS+
BAT
CS+
BAT
CS+
BAT
CS+
BAT
N.C.
INT
DRV
F
TS
STAT
PGND
G
PIN FUNCTIONS
PIN
NAME
IN
bq24273 (YFF)
I/O
DESCRIPTION
Input Power Supply. IN is connected to the external DC supply (AC adapter). Bypass IN to PGND
with at least a 1μF ceramic capacitor.
A1-A4
I
I
GND
A5-A7
Ground. Connect to ground plane.
Reverse Blocking MOSFET and High Side MOSFET Connection Point for the input. Bypass PMID
to GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to
PMID. The PMID output is not current limited. Any short on PMID will result in damage to the IC.
PMID
B1-B4
O
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not
connect any external load to BYP.
BYP
B5-B7
O
SW
C1-C7
O
--
Inductor Connection. Connect to the switched side of the external inductor.
Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
No Connection. Leave N.C. unconnected.
PGND
N.C.
D1-D7, E1, G7
E2-E3, F5
IC Hardware Disable Input – Drive CD high to place the bq24273 in high-z mode. Drive CD low for
normal operation. Do not leave CD unconnected.
CD
E4
SDA
SCL
E5
E6
I2C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
I2C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
High Side MOSFET Gate Driver Supply. Connect a 0.01μF ceramic capacitor (voltage rating >
10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
BOOT
CS+
E7
I
I
Current Sense Input. High side connection to internal current sense element. Bypass CS+ locally
with at least 10µF of ceramic capacitance for stability.
F1-F4
Status Output – INT is an open-drain output that signals charging status and fault interrupts. INT
pulls low during charging. INT is high impedance when charging is complete or the charger is
disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail through
a 100kΩ resistor to communicate with the host processor
INT
F6
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. bypass
DRV
BAT
F7
O
DRV to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to
10mA. DRV is active whenever the input is connected and VIN > VUVLO and VIN > (VBAT + VSLP
)
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to
GND with a 1μF capacitor.
G1-G4
I/O
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PIN FUNCTIONS (continued)
PIN
bq24273 (YFF)
NAME
I/O
DESCRIPTION
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND.
The NTC is connected from TS to GND. The TS function in the bq24276 provides 2 thresholds for
Hot/ Cold shutoff, while the bq24277 has 2 additional thresholds for JEITA compliance. See the
NTC Monitor section for more details on operation and selecting the resistor values.
TS
G5
G6
–
Status Output – STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete or the
charger is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host.
STAT is enabled/ disabled using the EN_STAT bit in the control register. Pull STAT up to a logic
rail through an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
STAT
There is an internal electrical connection between the exposed thermal pad and the VSS pin of
the device. The thermal pad must be connected to the same potential as the VSS pin on the
printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS
pin must be connected to ground at all times.
Thermal
Pad
–
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TYPICAL APPLICATION CIRCUIT
IN
SW
PMID
BOOT
CS+
`
SDA
SCL
CD
BAT
INT
HOST
System
Load
PACK+
TEMP
BYP
TS
STAT
DRV
PGND
PACK-
Figure 1. bq24273 Application Circuit
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DETAILED DESCRIPTION
The bq24273 is a highly integrated synchronous switch-mode charger featuring integrated MOSFETs and current
sense element reducing the count of external components. It is targeted at portable applications with higher
capacity batterires powered by 1-cell Li-Ion, LiFePO4 or Li-polymer battery pack. Due to the high efficiency in a
wide range of the input voltage and battery voltage, the switching mode charger is a good choice for high speed
charging with less power loss and better thermal management.
The bq24273 has two operation states: charge state and high impedance state. In the charge state, the bq24273
supports a precision Li-ion, LiFePO4 or Li-polymer charging system for single-cell applications. In the high
impedance state, the bq24273 stops charging and operates in a mode with very low current from IN and battery,
to effectively reduce the power consumption when the portable device is in standby mode.
The bq24273 includes an integrated 35mΩ sense resistor that is used to measure the charge current into the
battery. As resistors are expected to have a temperature coefficient, the bq24273 includes a compensation
mechanism that maintains the accuracy of the charge current as the temperature changes. This allows for a
smaller BOM solution allowing the removal of an external high accuracy sense resistor that are typically needed
for non-power path charger solutions.
Charge Mode Operation
Charge Profile
There are 5 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV),
thermal regulation loop, input current sense loop and input voltage dynamic power management loop (VIN-DPM).
During the charging process, all five loops are enabled and the one that is dominate takes control. The bq24273
supports a precision LiFePO4, Li-Ion or Li-Polymer charging systems for single-cell applications. Figure 2 shows
a typical charge profile.
Current Regulation
Phase
Voltage Regulation
Phase
Precharge
Phase
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
Voltage
Regulation
Voltage
Regulation
Current
Charge Voltage
Charge Voltage
V
V
SHORT
SHORT
Charge Current
Charge Current
Termination
Termination
I
SHORT
I
SHORT
Fast Charge
(PWM Charge)
Fast Charge
(PWM Charge)
Precharge
(Linear Charge)
Precharge
(Linear Charge)
(a) Not input current limited
(b) Input current limited
Figure 2. Typical Charging Profile of bq24273
PWM Controller in Charge Mode
The bq24273 provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to supply the charge
current. The voltage loop is internally compensated and provides enough phase margin for stable operation,
allowing the use of small ceramic capacitors with very low ESR.
The input is protected from short circuit by a cycle-by-cycle current limit that is sensed through the high-side
MOSFET. The threshold is set to a nominal 5-A peak current. The input also utilizes an input current limit that
limits the current from the power source.
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Battery Charging Process
When the battery is deeply discharged or shorted (VBAT<VBATSHRT), the bq24273 applies a 50mA current to close
the pack protector switch and bring the battery voltage up to acceptable charging levels. Once the battery rises
above VBATSHRT, the charge current is regulated to the value set in the I2C register. If the die temperature does
heat up, the thermal regulation circuit reduces the charge current to maintain a die temperature less than 125°C.
The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient.
The charge current is regulated to IOCHARGE until the battery is charged to the regulation voltage. Once the
battery voltage is close to the regulation voltage, VBATREG, the charge current is tapered down as shown in
Figure 2. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the BAT and
PGND pins. The bq24273 is a fixed single-cell voltage version, with adjustable regulation voltage (3.5V to 4.44V)
programmed using the I2C interface.
The bq24273 monitors the charging current during the voltage regulation phase. Once the termination threshold,
ITERM, is detected and the battery voltage is above the recharge threshold, the bq24273 terminates the charge
cycle and enters battery detection. The termination current level is programmable. To disable the charge current
termination, the host sets the charge termination bit (TE) of charge control register to 0, refer to I2C section for
details.
A new charge cycle is initiated when one of the following conditions is detected:
1. The battery voltage falls below the VBATREG-VRCH threshold.
2. CE bit toggle or RESET bit is set
3. HI-Z bit toggle
Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is
pulled from VBAT for tDETECT to verify there is a battery. If the battery voltage remains above VDETECT for the full
duration of tDETECT, a battery is determined to present and the IC enters “Charge Done”. If VBAT falls below
VDETECT, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of battery
detection, the bq2427x turns on IBATSHORT for tDETECT. If VBAT rises to VDETECT, the current source is turned off and
after tDETECT, the battery detection continues through another current sink cycle. Battery detection continues until
charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and a new charge
cycle begins. Battery detection is not run when termination is disabled.
DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT<3.6V before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In default mode, the I2C registers are reset to the default values. The 27 min safety timer is reset and starts when
DEFAULT mode is entered. The default value for VBATREG is 3.6V, and the default value for ICHARGE is 1A. The
input current limit for the IN input is set to 1.5A. Default mode is exited by programming the I2C interface. Note
that if termination is enabled and charging has terminated, a new charge cycle is NOT initiated when entering
DEFAULT mode.
Safety Timer and Watchdog Timer
At the beginning of charging process, the bq24273 starts the safety timer. This timer is active during the entire
charging process. If charging has not terminated before the safety timer expires, charging is halted and the CE
bit is written to a “1”. The length of the safety timer is selectable using the I2C interface. A single 128μs pulse is
sent on the STAT and INT outputs and the STATx bits of the status registers are updated in the I2C. The /CE bit
must be toggled in order to clear the safety timer fault. The safety timer duration is selectable using the TMR_X
bits in the Safety Timer Register/ NTC Monitor register. Changing the safety timer duration resets the safety
timer. If the safety timer expires, charging is disabled (CE changed to a “1”). This function prevents continuous
charging of a defective battery if the host fails to reset the safety timer.
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In addition to the safety timer, the bq24273 contains a watchdog timer that monitors the host through the I2C
interface. Once a read/write is performed on the I2C interface, a 30-second timer (tWATCHDOG) is started. The 30-
second timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit (TMR_RST)
in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is reset. This
process continues until battery is fully charged or the safety timer expires. If the 30-second timer expires, the IC
enters DEFAULT mode where the default register values are loaded, the safety timer restarts at 27minutes and
charging continues. The I2C may be accessed again to reinitialize the desired values and restart the watchdog
timer as long as the 27 minute safety timer has not expired. The watchdog timer flow chart is shown in Figure 3.
Start Safety Timer
Yes
Safety timer expired?
fault
Safety timer
No
Charging suspended
Enter suspended
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG < ITERM
mode
Fault indicated in
STAT registers
No
No
I2C Read/Write
performed?
Yes
Start 30 second
watchdog timer
Reset 30 second
watchdog timer
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG < ITERM
No
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Fault indicated in
STAT registers
No
Yes
No
30s timer expired?
Yes
Received SW watchdog
RESET?
Reset to default
values in I2C
register
Restart 27min
safety timer
Figure 3. The Watchdog Timer Flow Chart for bq24273
Hardware Chip Disable Input (CD)
The bq24273 contains a CD input that is used to disable the IC and place the bq24273 into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
bq24273 into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving CD
high during HOST mode resets the safety timer.
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LDO Output (DRV)
The bq24273 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT. The maximum value of the
DRV output is 5.45V. The LDO is on whenever a supply is connected to the IN input of the bq24273. The DRV is
disabled under the following conditions:
1. VSUPPLY < UVLO
2. VSUPPLY < VSLP
3. Thermal Shutdown
External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the bq24273 provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The bq24273 enable the user to easily implement the JEITA standard for
charging temperature. The JEITA specification is shown in Figure 4.
1.0C
0.5C
Portion of spec not covered by TS
4.25V
Implementation on bq24273
4.15V
4.1V
T1
(0ºC)
T2
(10ºC)
T3 T4
(45ºC) (50ºC)
T5
(60ºC)
Figure 4. Charge Current During TS Conditions
To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC
<
0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC < 60°C) and the
hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VHOT
<
VTS < VWARM, the battery regulation voltage is reduced by 140mV from the programmed regulation threshold.
When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current.
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 5. The resistor values are
calculated using the following equations:
é
ê
ë
ù
ú
1
1
VDRV ´RCOLD ´ RHOT´
-
VCOLD VHOT û
RLO =
é
ê
ë
ù
ú
û
é
ê
ë
ù
VDRV
VDRV
RHOT ´
- 1 -RCOLD ´
-1
ú
VHOT
VCOLD
û
(1)
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V
DRV
- 1
V
COLD
RHI =
1
1
+
RLO RCOLD
(2)
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.30 × VDRV
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC
resistances for a selected resistor divider are calculated using the following equations:
RLO´ 0.564´ RHI
RCOOL =
RLO - RLO´ 0.564 - RHI´ 0.564
RLO´ 0.383´ RHI
(3)
(4)
RWARM =
RLO - RLO´ 0.383 -RHI´ 0.383
V
1 x Charge/
0.5 x Charge
BAT(REG)
– 140mV
VDRV
DISABLE
TS COLD
+
TS COOL
TS WARM
+
+
VDRV
TS HOT
+
RHI
TS
PACK+
TEMP
bq242702
RLW
PACK-
Figure 5. TS Circuit
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, bq24273 monitors the junction temperature, TJ, of the
die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq24273 if the die temperature rises too high. At any state, if
TJ exceeds TSHTDWN, bq24273 suspends charging and disables the buck converter. During thermal shutdown
mode, the PWM is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new charging cycle
begins when TJ falls below TSHTDWN by approximately 10°C.
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Input Voltage Protection in Charge Mode
Sleep Mode
The bq24273 enters the low-power sleep mode if the voltage on VSUPPLY falls below sleep-mode entry threshold,
VBAT+VSLP, and VVBUS is higher than the undervoltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the bq24273 turns off the PWM
converter and sends a single 128μs pulse on the STAT and INT outputs and updates the STATx and FAULT_x
bits in the status registers. Once VSUPPLY > VBAT+ VSLP, the STATx and FAULT_x bits are cleared and the device
initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage will decease. Once the supply drops to VIN_DPM (default 4.76V), the input
current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current
is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature ensures IC
compatibility with adapters with different current capabilities without a hardware change.
Bad Source Detection
When a source is connected to IN, the bq24273 runs a Bad Source Detection procedure to determine if the
source is strong enough to provide some current to charge the battery. A current sink is turned on (75mA) for
32ms. If the source is valid after the 32ms (VBADSOURCE < VSUPPLY < VOVP), the buck converter starts up and
normal operation continues. If the supply voltage falls below VBAD_SOURCE during the detection, the current sink
shuts off for 2s and then retries, a single 128μs pulse is sent on the STAT and INT outputs and the STATx and
FAULT_x bits of the status registers and the battery/supply status registers are updated in the I2C. The detection
circuits retries continuously until a valid source is detected after the detection time. If during normal operation the
source falls to VBAD_SOURCE, the bq24273 turns off the PWM converter and sends a single 128μs pulse is sent on
the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status
registers are updated in the I2C. Once a good source is detected, the STATx and FAULT_x bits are cleared and
the device returns to normal operation.
Input Over-Voltage Protection
The bq24273 provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). During normal operation, if VSUPPLY > VOVP, the bq24273 turns off the
PWM converter and sends a single 128μs pulse is sent on the STAT and INT outputs and the STATx and
FAULT_x bits of the status registers and the battery/supply status registers are updated in the I2C. Once the
OVP fault is removed, the STATx and FAULT_x bits are cleared and the device returns to normal operation.
To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.
This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If the
adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The OVP
circuit is active during normal operation, so if the system standby current plus the charge current is not enough to
pull down the source, operation is suspended.
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq24273. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
Table 1. STAT Pin Summary
Charge State
STAT and INT behavior
Low
Charge in progress and EN_STAT=1
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault,
watchdog expiration, sleep mode, battery temperature fault (TS), battery fault (OVP or
absent), thermal shutdown
128-µs pulse, then High Impedance
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SERIAL INTERFACE DESCRIPTION
The bq24273 uses an I2C compatible interface to program charge parameters. I2C™ is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device.
The bq24273 device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charging solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as battery voltage remains
above 2.5 V (typical). The I2C circuitry is powered from IN when a supply is connected. If the IN supply is not
connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V
with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24273 devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 6. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
P
S
START Condition
STOP Condition
Figure 6. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 7). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 7. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high ( see Figure 9). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data output
by Transmitter
Not Acknowledge
Data output
by Receiver
Acknowledge
9
1
2
8
SCL From
Master
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 8. Acknowledge on the I2C Bus
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
1
8
9
7
1
2
2
9
3 - 8
Sr
or
P
S
ACK
ACK
or
Sr
Clock Line Held Low While
Interrupts are Serviced
Figure 9. Bus Protocol
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REGISTER DESCRIPTION
Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
B6
B5
B4
STAT_2
STAT_1
STAT_0
Read only
Read only
Read only
000- No Valid Source Detected
001- IN Ready
010- NA
011- Charging
100- NA
101- Charge Done
110- NA
111- Fault
B3
NA
Read/Write
Read only
Read only
Read only
0-Set always to 0
B2
FAULT_2
FAULT_1
FAULT_0
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired
100- Safety Timer Expired
101- Supply Fault
B1
B0(LSB)
110- NA
111- Battery Fault
Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
Read/Write
Read Only
Read Only
FUNCTION
B7(MSB)
B6
INSTAT1
INSTAT0
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN<VUVLO
B5
B4
B3
B2
B1
NA
Read Only
Read Only
Read/Write
Read Only
Read Only
NA
NA
NA
NA
NA
BATSTAT1
BATSTAT0
00-Battery Present and Normal
01-Battery OVP
10-Battery Not Present
11- NA
B0 (LSB)
EN_NOBATO Read/ Write
P
0-Normal Operation
1-Enables No Battery Operation when termination is disabled
(default 0)
EN_NOBATOP (No Battery Operation with Termination Disabled)
The EN_NOBATOP bit is used to enable operation when termination is disabled and no battery is connected.
This is useful for factory mode cases where it is desired to do a GSM calibration in the factory. For this
application, the TE bit (Bit 2 in Register 0x02h) should be set to a “0” to disable termination and the
EN_NOBATOP should be set to a “1”. This feature should not be used during normal operation as it disables the
BATOVP and the reverse boost protection circuits.
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Control Register (READ/WRITE)
Memory location: 02, Reset state: 1000 1100
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
RESET
Write Only
Write: 1-Reset all registers to default values
0-No effect
Read: always get “1”
B6
B5
B4
B3
NA
Read/Write
Read/Write
Read/Write
Read/Write
NA
NA
NA
NA
NA
EN_STAT
1-Enable STAT output to show charge status,
0-Disable STAT output for charge status. Fault interrupts are still show even when EN_STAT
= 0. (default 1)
B2
TE
CE
Read/Write
Read/Write
1-Enable charge current termination,
0-Disable charge current termination (default 1)
B1
1-Charger is disabled
0-Charger enabled (default 0)
B0 (LSB)
HZ_MODE Read/Write
1-High impedance mode
0-Not high impedance mode (default 0)
RESET Bit
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write “1” to RESET bit
to reset all the registers to default values and place the bq24273 into DEFAULT mode and turn off the watchdog
timer. The RESET bit is automatically cleared to zero once the bq24273 enters DEFAULT mode.
CE Bit (Charge Enable)
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic level (0) on
this bit enables the charge and a high logic level (1) disables the charge. When charge is disabled, the battery is
disconnected from the CS+.
HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance mode. A low
logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state
called high impedance mode.
Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
BIT
B7(MSB)
B6
NAME
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
VBREG5
VBREG4
VBREG3
VBREG2
VBREG1
VBREG0
IINLIMIT_IN
Battery Regulation Voltage: 640mV (default 0)
Battery Regulation Voltage: 320mV (default 0)
Battery Regulation Voltage: 160mV (default 0)
Battery Regulation Voltage: 80mV (default 1)
Battery Regulation Voltage: 40mV (default 0)
Battery Regulation Voltage: 20mV (default 1)
B5
B4
B3
B2
B1
Input Limit for IN input
0 – 1.5A
1 – 2.5A (default 0)
B0(LSB)
NA
Read/Write
NA
•
Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
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Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
BIT
B7(MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
Read/Write
Read only
Read only
Read only
Read only
Read only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
B5
B4
For I2C Address 6Bh:
00: bq24273
01 – 11: Future product spins
B3
PN0
B2
Revision2
Revision1
Revision0
Read only
Read only
Read only
000: Revision 1.0
001:Revision 1.1
010: Revision 2.0
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
B1
B0(LSB)
Battery Termination/Fast Charge Current Register (READ/WRITE)
Memory location: 05, Reset state: 0011 1110
BIT
NAME
ICHRG4
ICHRG3
ICHRG2
ICHRG1
ICHRG0
ITERM2
ITERM1
ITERM0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
B7(MSB)
B6
Charge current: 1200 mA – (default 0)
Charge current: 600 mA— (default 0)
Charge current: 300 mA—(default 1)
Charge current: 150 mA— (default 1)
Charge current: 75 mA (default 0)
B5
B4
B3
B2
Termination current sense voltage: 200 mA (default 0)
Termination current sense voltage: 100 mA (default 1)
Termination current sense voltage: 50 mA (default 0)
B1
B0(LSB)
•
•
Charge current sense offset is 550mA and default charge current is 1000mA
Termination threshold offset is 50mA and default termination current is 150mA
VIN-DPM Voltage/ DPPM Status Register
Memory location: 06, Reset state: xx00 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB) NA
Read Only
NA
B6
DPM_STATUS Read Only
1 – VIN-DPM mode is active
0 – VIN-DPM mode is not active
B5
B4
B3
B2
B1
NA
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
NA
NA
NA
NA
NA
VINDPM2(IN)
VINDPM1(IN)
IN input VIN-DPM voltage: 320 mV (default 0)
IN input VIN-DPM voltage: 160 mV (default 0)
IN input VIN-DPM voltage: 80 mV (default 0)
B0(LSB) VINDPM0(IN)
•
VIN-DPM voltage offset is 4.20 V and default VIN-DPM threshold is 4.20 V.
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Safety Timer/ NTC Monitor Register (READ/WRITE)
Memory location: 07, Reset state: 1001 1xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB) 2XTMR_EN
Read/Write
1 – Timer slowed by 2x when in thermal regulation, input current limit, VIN_DPM or DPPM
0 – Timer not slowed at any time (default 0)
B6
B5
TMR_1
TMR_2
Read/Write
Read/Write
Safety Timer Time Limit
00 – 27 minute fast charge
01 – 6 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers (default 00)
B4
B3
NA
Read/Write
Read/Write
NA
TS_EN
0 – TS function disabled
1 – TS function enabled (default 1)
B2
B1
TS_FAULT1
TS_FAULT0
Read Only
Read Only
TS Fault Mode:
00— Normal, No TS fault
01— TS temp < TCOLD or TS temp > THOT(Charging suspended)
10— TCOOL > TS temp > TCOLD (Charge current reduced by half, bq24273 only)
11— TWARM < TS temp < THOT (Charge voltage reduced by 140mV, bq24273 only)
B0(LSB) LOW_CHG
Read/Write
0 – Charge current as programmed in Register 0x05
1 – Charge current half programmed value in Register 0x05 (default 0)
LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current to half of the programmed value. This feature is used by
systems where battery NTC is monitored by the host and requires a reduced charge current setting or by
systems that need a “preconditioning” current for low battery voltages. Write a “1” to this bit to charge at half of
the programmed charge current. Write a “0” to this bit to charge at the programmed charge current.
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s) :bq24273
bq24273
www.ti.com
SLUSB08 –JUNE 2012
APPLICATION INFORMATION
OUTPUT INDUCTOR AND CAPACITOR SELECTION GUIDELINES
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24273 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use equation 2 to calculate the peak current.
%
æ
ö
RIPPPLE
IPEAK = ILOAD(MAX ) ´ 1+
ç
÷
2
è
ø
(5)
The inductor selected must have a saturation current rating less than or equal to the calculated IPEAK. Due to the
high currents possible with the bq24273, a thermal analysis must also be done for the inductor. Many inductors
have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the
ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty
cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of
the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE =ILOAD +D ´I PEAK -ILOAD = 1.5A + 0.2´ 2.5A -1.5A = 1.7A
(
)
(
)
(6)
The bq24273 provides internal loop compensation. Using this scheme, the bq24273 is stable with 10µF to 200µF
of local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. To reduce the
output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for
local bypass to CS+.
PCB LAYOUT GUIDELINES
It is important to pay special attention to the PCB layout. The following provides some guidelines:
•
To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24273
•
Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
•
•
•
The local bypass capacitor from CS+ to GND should be connected between the CS+ pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
•
•
The high-current charge paths into IN, BAT, CS+ and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
Copyright © 2012, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s) :bq24273
bq24273
SLUSB08 –JUNE 2012
www.ti.com
Sample Layout
PMID
SW
GND
IN
SW
PGND
BOOT
ILIM
BAT
SYS
ISET
PGND
SW
SYS
(YFF Package)
Figure 10. PCB Layout Example
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s) :bq24273
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ24273RGER
BQ24273RGET
PREVIEW
PREVIEW
VQFN
VQFN
RGE
RGE
24
24
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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