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bq24296, bq24297

SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

bq2429x I²C Controlled 3-A Single Cell USB Charger With Narrow VDC

Power Path Management and Adjustable Voltage USB OTG

1

1 Features

•

90% High Efficiency Switch Mode 3-A Charger

•

Safety

•

3.9-V to 6.2-V Single Input USB-Compliant

Charger with 6.4-V Over-Voltage Protection

–

Battery Temperature Sensing for Charging and

Discharging in OTG Mode

–

USB Host or Charging Port D+/D- Detection

Compatible to USB Battery Charger Spec

(BC1.2)

–

Battery Charging Safety Timer

Thermal Regulation and Thermal Shutdown

Input and System Over-Voltage Protection

MOSFET Over-Current Protection

–

Supports Nonstandard 2-A/1-A Adapters

Detection (bq24297)

•

Charge Status Outputs for LED or Host Processor

Input Voltage and Current Limit Supports USB

2.0 and USB 3.0

Maximum Power Tracking Capability by Input

Voltage Regulation

Input Current Limit: 100 mA, 150 mA, 500 mA,

900 mA, 1 A, 1.5 A, 2 A, and 3 A

•

20-µA Low Battery Leakage Current and Support

Shipping Mode

•

USB OTG with Adjustable Output 4.55 V to 5.5 V

at 1 A or 1.5 A

4.00-mm x 4.00-mm VQFN-24 Package

–

Fast OTG Startup (22 ms Typ)

90% 5-V Boost Mode Efficiency

2 Applications

•

Tablet PC, Smart Phone, Internet Devices

Portable Audio Speaker

Accurate ±15% Hiccup Mode Over-Current

Protection

Handheld Computers, PDA, and POS

Narrow VDC (NVDC) Power Path Management

–

Instant System On with No Battery or Deeply

Discharged Battery

3 Description

The bq24296/bq24297 are highly-integrated switch-

mode battery charge management and system power

path management devices for 1 cell Li-Ion and Li-

polymer batteries in a wide range of smart phone and

tablet applications.

–

Ideal Diode Operation in Battery Supplement

Mode

•

1.5-MHz Switching Frequency for Low Profile 1.2-

mm Inductor

I²C Port for Optimal System Performance and

Status Reporting

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

Autonomous Battery Charging With or Without

Host Management

bq24296/7

VQFN (24)

4.00 mm x 4.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

–

Battery Charge Enable and Preconditioning

Charge Termination and Recharge

1mH

5V USB

SDP/DCP

VBUS

PMID

SW

BTST

REGN

SYSTEM

•

High Accuracy

47nF

20mF

1mF

–

±0.5% Charge Voltage Regulation

±7% Charge Current Regulation

±7.5% Input Current Regulation

8.2mH

4.7mF

STAT

SYS

VREF

PGND

SYS

SDA

SCL

INT

Battery

±3% Output Voltage Regulation in USB OTG

Boost Mode

BAT

Host

10mF

OTG

QON

Optional

CE

High Integration

TS

+

D+/PSEL

D-/PG

USB

PHY

ILIM

–

Power Path Management

Synchronous Switching MOSFETs

Integrated Current Sensing

Bootstrap Diode

-

bq24296/297

Internal Loop Compensation

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

bq24296, bq24297

SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

www.ti.com

Table of Contents

9.3 Feature Description................................................. 16

9.4 Device Functional Modes........................................ 28

9.5 Programming........................................................... 29

9.6 Register Map........................................................... 33

10 Application and Implementation........................ 40

10.1 Application Information.......................................... 40

10.2 Typical Application ................................................ 40

11 Power Supply Recommendations ..................... 45

12 Layout................................................................... 45

12.1 Layout Guidelines ................................................. 45

12.2 Layout Example .................................................... 46

13 Device and Documentation Support ................. 47

13.1 Documentation Support ....................................... 47

13.2 Related Links ........................................................ 47

13.3 Trademarks........................................................... 47

13.4 Electrostatic Discharge Caution............................ 47

13.5 Glossary................................................................ 47

1

2

3

4

5

6

7

8

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (Continued)........................................ 3

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings ............................................................ 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Electrical Characteristics........................................... 7

8.6 Timing Requirements.............................................. 11

8.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 14

9.1 Overview ................................................................. 14

9.2 Functional Block Diagram ....................................... 15

9

14 Mechanical, Packaging, and Orderable

Information ........................................................... 47

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2013) to Revision B

Page

•

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1

Changed front page schematic............................................................................................................................................... 1

Changed REG01[4] = 1 to REG01[5] = 1 in OTG description................................................................................................ 4

Added (10kΩ NTC thermister only) to QON description ........................................................................................................ 5

Added ESD information to Handling Ratings ........................................................................................................................ 6

Changed I_CHG= 1792 mA in I_{ICHG_REG_ACC}test conditions...................................................................................................... 8

Changed falling to rising in V_HTF............................................................................................................................................. 9

Changed V_HTFTYP to 47.2% ................................................................................................................................................. 9

Changed Input high threshold (OTG) MIN to 1.1 V.............................................................................................................. 10

Changed Table 3 ................................................................................................................................................................. 19

Changed Figure 15 .............................................................................................................................................................. 22

Changed RT1 = 5.25 kΩ ..................................................................................................................................................... 25

Deleted and LSFET from Voltage and Current Monitoring in Buck Mode description......................................................... 27

Deleted HSFET and from Voltage and Current Monitoring in Boost Mode description ....................................................... 28

Changed text in Over-Current Protection ............................................................................................................................ 28

Changed REG09[5] to REG09[3] in Battery Over-Voltage Protection (BATOVP) section................................................... 28

Changed REG09 Bit 3 description 1 – Battery OVP ........................................................................................................... 39

•

Changes from Original (September 2013) to Revision A

Page

•

Deleted H from bq24297 PART NUMBER ............................................................................................................................. 1

2

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

5 Description (Continued)

Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charge time and

extends battery life during discharging phase. The I²C serial interface with charging and system settings makes

the device a truly flexible solution.

The device supports 3.9-V to 6.2-V USB input sources, including standard USB host port and USB charging port

with 6.4-V over-voltage protection. The device is compliant with USB 2.0 and USB 3.0 power specifications with

input current and voltage regulation. To set the default input current limit, the bq24296 takes the result from the

detection circuit in the system, such as USB PHY device and the bq24297 detects the input source through

D+/D- detection following the USB battery charging spec 1.2. In addition, the bq24297 detects non-standard 2-

A/1-A adapters. The device also supports USB On-the-Go operation by providing fast startup and supplying

adjustable voltage 4.55-V to 5.5-V (default 5 V) on the VBUS with an accurate current limit up to 1.5 A.

The power path management regulates the system slightly above battery voltage but does not drop below 3.5-V

minimum system voltage (programmable). With this feature, the system keeps operating even when the battery

is completely depleted or removed. When the input source current or voltage limit is reached, the power path

management automatically reduces the charge current to zero and then starts discharges the battery until the

system power requirement is met. This supplement mode operation keeps the input source from getting

overloaded.

The device initiates and completes a charging cycle when host control is not available. It automatically charges

the battery in three phases: pre-conditioning, constant current, and constant voltage. In the end, the charger

automatically terminates when the charge current is below a preset limit in the constant voltage phase. Later on,

when the battery voltage falls below the recharge threshold, the charger automatically starts another charging

cycle.

The charge device provides various safety features for battery charging and system operation, including negative

thermistor monitoring, charging safety timer, and over-voltage/over-current protections. The thermal regulation

reduces charge current when the junction temperature exceeds 120°C (programmable).

The STAT output reports the charging status and any fault conditions. The INT immediately notifies the host

when a fault occurs.

The bq24296 and bq24297 are available in a 24-pin, 4.00 x 4.00 mm²thin VQFN package.

6

Device Comparison Table

bq24296

bq24297

I²C Address

USB OTG

6BH

Yes

Adjustable 4.5 V to 5.5 V at 1.5 A (max)

USB Detection

PSEL

4.208 V

D+/D–

4.208 V

Default Battery Voltage

Default Charge Current

Default Adapter Current Limit

2.048 A

3 A

Default Pre-Charge Current / Max Pre-

Charge Current

256 mA / 2.048 A

Default Termination Current

Charging Temperature Profile

Status Output

256 mA

Cold/Hot

STAT, PG

Blinking at 1 Hz

12 hr

256 mA

Cold/Hot

STAT

STAT During Fault

Blinking at 1 Hz

12 hr

Default Safety Timer

Default VINDPM

4.36 V

Default Pre-charge Timer

4 hr

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

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7 Pin Configuration and Functions

24-Pin VQFN

RGE Package

(Top View)

24-Pin VQFN

RGE Package

(Top View)

24

23

22

21

20

19

23

22

20

19

24

21

1

2

3

4

5

6

18

17

16

15

14

13

VBUS

PSEL

PG

PGND

SYS

VBUS

D+

1

2

3

4

5

6

18

PGND

SYS

17

16

15

D–

STAT

SCL

bq24296

bq24297

STAT

SCL

SYS

BAT

14

BAT

SDA

BAT

13

SDA

7

8

9

10

11

12

8

9

10

11

12

7

Pin Functions

NUMBER

TYPE

DESCRIPTION

bq24296

bq24297

VBUS

1,24

P

Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between

VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place

it as close as possible to IC.

PSEL

–

PSEL

D+

2

I

Power source selection input. High indicates a USB host source and Low indicates an adapter source.

Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection

includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters.

Analo

g

PG

–

3

O

Open drain active low power good indicator. Connect to the pull up rail via 10-kΩ resistor. LOW

indicates a good input source if the input voltage is between UVLO and ACOV, above SLEEP mode

threshold, and current limit is above 30 mA.

D–

I

Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection

includes data contact detection (DCD), primary detection in bc1.2, and non-standard adapters.

Analo

g

STAT

4

O

Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-

kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled.

When any fault condition occurs, STAT pin in the charge blinks at 1 Hz.

I²C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.

I²C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.

SCL

SDA

INT

SCL

SDA

INT

5

6

7

I

I/O

O

Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active

low, 256-µs pulse to host to report charger device status and fault.

OTG

8

I

USB current limit selection pin during buck mode, and active high enable pin during boost mode.

Digital

For bq24296, when in buck mode with USB host (PSEL = High), when OTG = High, IIN limit = 500 mA

and when OTG = Low, IIN limit = 100 mA.

For bq24297, when in buck mode with USB host, when OTG = High, IIN limit = 500 mA and when OTG

= Low, IIN limit = 100 mA.

The boost mode is activated when the REG01[5] = 1 and OTG pin is High.

CE

9

I

Active low Charge Enable pin. Battery charging is enabled when REG01[5:4] = 01 and CE pin = Low.

CE pin must be pulled high or low.

4

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

Pin Functions (continued)

NUMBER

TYPE

DESCRIPTION

bq24296

bq24297

ILIM

10

I

ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is

connected from ILIM pin to ground to set the maximum limit as I_INMAX= (1V/R_ILIM) × K_ILIM. The actual

input current limit is the lower one set by ILIM and by I²C REG00[2:0]. The minimum input current

programmed on ILIM pin is 500 mA.

TS

11

12

I

Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program

temperature window with a resistor divider from REGN to TS to GND. Charge suspends or Boost

disable when TS pin is out of range. A 103AT-2 thermistor is recommended.

Analo

g

QON

I

BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2-ms

high level turns on BATFET to exit shipping mode. It has internal 1-MΩ (Typ) pull down. For backward

compatibility, when BATFET enable control function is not used, the pin can be no connect or tied to TS

pin (10-kΩ NTC thermister only). (Refer to Shipping Mode for detail description).

BAT

SYS

BAT

SYS

13,14

15,16

P

I

Battery connection point to the positive pin of the battery pack. The internal BATFET is connected

between BAT and SYS. Connect a 10 µF closely to the BAT pin.

System connection point. The internal BATFET is connected between BAT and SYS. When the battery

falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system

voltage.

PGND

SW

PGND

SW

17,18

19,20

P

Power ground connection for high-current power converter node. Internally, PGND is connected to the

source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and

output capacitors of the charger. A single point connection is recommended between power PGND and

the analog GND near the IC PGND pin.

O

Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel

HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to

BTST.

BTST

21

22

P

PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap

diode. Connect the 0.047-µF bootstrap capacitor from SW to BTST.

REGN

PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-

strap diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The

capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.

PMID

23

–

O

P

Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input

capacitance, connect a 1-µF capacitor on VBUS to PGND, and the recommended 8.2 µF or more on

PMID to PGND.

Thermal Pad

Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias

on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter.

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

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8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

MIN

–2

MAX

15⁽²⁾

12

UNIT

VBUS (converter not switching)

V

PMID (converter not switching)

–0.3

–2

STAT, PG

BTST

12

SW

7

8 (Peak

for 20ns

duration)

Voltage

(with respect to GND)

BAT, SYS (converter not switching)

–0.3

6

7

V

SDA, SCL, INT, OTG, ILIM, REGN, TS, QON, CE , D+, D–,

PSEL

BTST TO SW

PGND to GND

INT, STAT, PG

–0.3

7

0.3

6

V

Output sink current

mA

°C

Junction temperature

–40

–65

150

Storage temperature range, T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground pin unless otherwise noted.

(2) VBUS is specified up to 16 V for a maximum of 24 hours under no load conditions.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

1000

V

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

MIN

MAX

6.2⁽¹⁾

3

UNIT

V

V_IN

Input voltage

3.9

I_IN

Input current (VBUS)

A

I_SYS

V_BAT

Output current (SYS)

3.5

4.4

3

A

Battery voltage

V

Fast charging current

A

I_BAT

T_A

Discharging current with internal MOSFET

Operating free-air temperature range

5.5

85

A

–40

°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight

layout minimizes switching noise.

6

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

8.4 Thermal Information

bq24296,

bq24297

THERMAL METRIC⁽¹⁾

UNIT

RGE (24 PIN)

32.2

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

R_θJCtop

R_θJB

29.8

Junction-to-board thermal resistance

9.1

°C/W

0.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

9.1

2.2

R_θJCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values unless other

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

QUIESCENT CURRENTS

V_VBUS< V_UVLO, VBAT = 4.2 V, leakage between BAT and

VBUS

5

16

32

µA

High-Z Mode, or no VBUS, BATFET disabled (REG07[5] =

1), –40°C – 85°C

I_BAT

Battery discharge current (BAT, SW, SYS)

20

55

µA

High-Z Mode, or no VBUS, BATFET enabled (REG07[5] =

0), –40°C – 85°C

V_VBUS= 5 V, High-Z mode, No battery

15

30

3

µA

V_VBUS> V_UVLO, V_VBUS> V_BAT, converter not switching

1.5

mA

V_VBUS> V_UVLO, V_VBUS> V_BAT, converter switching, V_BAT

3.2 V, I_SYS= 0 A

=

I_VBUS

Input supply current (VBUS)

4

3.5

mA

V_VBUS> V_UVLO, V_VBUS> V_BAT, converter switching, charge

disable, V_BAT= 3.8 V, I_SYS= 100 µA

VBAT = 4.2 V, Boost mode, I_VBUS= 0 A, converter

switching

I_BOOST

Battery discharge current in boost mode

VBUS/BAT POWER UP

V_{VBUS_OP}

V_{VBUS_UVLOZ}

V_SLEEP

VBUS operating voltage

3.9

3.6

35

6.2

V

VBUS for active I²C, no battery

Sleep mode falling threshold

V_VBUSrising

V_VBUSfalling, V_VBUS-VBAT

V_VBUSrising, V_VBUS-VBAT

V_VBUSrising

80

250

6.4

120 mV

350 mV

V_SLEEPZ

Sleep mode rising threshold

170

6.2

V_ACOV

VBUS over-voltage rising threshold

VBUS over-voltage falling hysteresis

Battery for active I²C, no VBUS

Battery depletion threshold

6.6

V

mV

V

V_{ACOV_HYST}

V_{BAT_UVLOZ}

V_{BAT_DPL}

V_{BAT_DPL_HY}

V_VBUSMIN

I_BADSRC

V_VBUSfalling

250

V_BATrising

2.3

V_BATfalling

2.4

200

3.8

30

2.6

V

Battery depletion rising hysteresis

Bad adapter detection threshold

Bad adapter detection current source

V_BATrising

mV

V

V_VBUSfalling

mA

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values unless other

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER PATH MANAGEMENT

Isys = 0 A, BATFET (Q4) off, V_BATup to 4.2 V,

REG01[3:1] = 101, V_SYSMIN= 3.5 V

V_{SYS_MAX}

V_{SYS_MIN}

R_ON(RBFET)

Typical system regulation voltage

System voltage outpu

3.5

4.35

V

REG01[3:1] = 101, V_SYSMIN= 3.5 V

3.65

28

Top reverse blocking MOSFET on-

resistance between VBUS and PMIID

41 mΩ

T_J= –40°C – 85°C

T_J= -40°C – 125°C

T_J= –40°C – 85°C

T_J= -40°C – 125°C

39

61

51

Internal top switching MOSFET on-

resistance between PMID and SW

R_ON(HSFET)

mΩ

58

82

mΩ

90

Internal bottom switching MOSFET on-

resistance between SW and PGND

R_ON(LSFET)

BATFET forward voltage in supplement

mode

V_FWD

BAT discharge current 10mA

30

mV

V_{SYS_BAT}

V_BATGD

SYS/BAT comparator

V_SYSfalling

V_BATrising

V_BATfalling

70

3.55

100

mV

V

Battery good comparator rising threshold

Battery good comparator falling threshold

V_{BATGD_HYST}

mV

BATTERY CHARGER

V_{BAT_REG_ACC}Charge voltage regulation accuracy

V_BAT= 4.112 V and 4.208 V

–0.5%

-4%

0.5%

V_BAT= 3.8 V, I_CHG= 1024 mA, T_J= 25°C

V_BAT= 3.8 V, I_CHG= 1024 mA, T_J= -20°C – 125°C

V_BAT= 3.8 V, I_CHG= 1792 mA, T_J= -20°C – 125°C

4%

7%

I_{ICHG_REG_ACC}

Fast charge current regulation accuracy

-7%

–10%

10%

V_BAT= 3.1 V, I_CHG= 104 mA, REG02 = 03 and REG02[0]

= 1

I_{CHG_20pct}

Charge current with 20% option on

Battery LOWV falling threshold

Battery LOWV rising threshold

75

2.6

175 mA

V_BATLOWV

Fast charge to precharge, REG04[1] = 1

2.8

3.0

2.9

3.1

V

Precharge to fast charge, REG04[1] = 1

(Typical 200-mV hysteresis)

V_{BATLOWV_HYST}

2.8

I_{PRECHG_ACC}

I_{TYP_TERM_ACC}

I_{TERM_ACC}

V_SHORT

Precharge current regulation accuracy

Typical termination current

Termination current accuracy

Battery short voltage

VBAT = 2.6 V, I_CHG= 256 mA

I_TERM= 256 mA, I_CHG= 2048 mA

VBAT falling

–20%

20%

265

mA

–22.5%

22.5%

2.0

200

100

20

V

V_{SHORT_HYST}

I_SHORT

Battery Short Voltage hysteresis

Battery short current

VBAT rising

mV

mA

mV

ms

VBAT < 2.2 V

V_RECHG

Recharge threshold below VBAT_REG

Recharge deglitch time

VBAT falling, REG04[0] = 0

T_J= 25°C

t_RECHG

24

28

35

R_{ON_BATFET}

SYS-BAT MOSFET on-resistance

mΩ

T_J= –40°C – 125°C

24

INPUT VOLTAGE/CURRENT REGULATION

V_{INDPM_REG_ACC}

Input voltage regulation accuracy

-2%

85

2%

USB100

100 mA

150 mA

500 mA

900 mA

USB150

125

440

750

1.3

USB Input current regulation limit, VBUS =

5V, current pulled from SW

I_{USB_DPM}

USB500

USB900

I_{ADPT_DPM}

I_{IN_START}

K_ILIM

Input current regulation accuracy

Input current limit during system start up

I_IN= K_ILIM/R_ILIM

IADP = 1.5 A, REG00[2:0] = 101

VSYS < 2.2 V

IINDPM = 1.5 A

1.5

A

100

435

mA

395

475 A x Ω

D+/D- DETECTION (bq24297)

V_{D+_SRC}

I_{D+_SRC}

I_{D–_SINK}

D+ voltage source

0.5

7

0.7

14

150

1

V

D+ connection check current source

D– current sink

µA

V

50

–1

100

D–, switch open

D+, switch open

I_{D_LKG}

Leakage current into D+/D–

D+ low comparator threshold

1

V_{D+_LOW}

0.8

8

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values unless other

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{D–_LOWdatref}

R_{D–_DWN}

D– low comparator threshold

D– pulldown for connection check

250

400 mV

14.25

24.8

kΩ

Charging timer with 100mA USB host in

default mode

t_{SDP_DEFAULT}

V_{adpt1_lo}

V_{adpt1_hi}

V_{adpt2_lo}

V_{adpt2_hi}

V_{adpt3_lo}

V_{adpt3_hi}

45 mins

D+ low comparator threshold for non-

standard adapter Divider-1

As percentage of REGN, 0°C – 85°C⁽¹⁾

46.5%

58.5%

15.5%

28.5%

46.5%

58.5%

48% 49.5%

60% 61.5%

17% 18.5%

30% 31.5%

48% 49.5%

60% 61.5%

D+ low comparator threshold for non-

standard adapter divider-1

D+ low comparator threshold for non-

standard adapter divider-2

D+ low comparator threshold for Non-

standard adapter divider-2

D- low comparator threshold for non-

standard adapter divider-3

D- high comparator threshold for non-

standard adapter divider-3

BAT OVER-VOLTAGE PROTECTION

V_BATOVP

Battery over-voltage threshold

V_BATrising, as percentage of V_{BAT_REG}

V_BATfalling, as percentage of V_{BAT_REG}

104%

2%

V_{BATOVP_HYST}

Battery over-voltage hysteresis

Battery over-voltage deglitch time to

disable charge

t_BATOVP

1

µs

THERMAL REGULATION AND THERMAL SHUTDOWN

T_{Junction_REG}

T_SHUT

Junction temperature regulation accuracy

Thermal shutdown rising temperature

Thermal shutdown hysteresis

REG06[1:0] = 11

120

160

30

1

°C

ms

Temperature increasing

T_{SHUT_HYS}

Thermal shutdown rising deglitch

Thermal shutdown falling deglitch

Temperature increasing delay

Temperature decreasing delay

1

COLD/HOT THERMISTER COMPARATOR

Cold temperature threshold, TS pin

voltage rising threshold

V_LTF

Charger suspends charge. as percentage to V_REGN

As percentage to V_REGN

73% 73.5%

0.4%

74%

Cold temperature hysteresis, TS pin

voltage falling

V_{LTF_HYS}

V_HTF

Hot temperature TS pin voltage rising

threshold

As percentage to V_REGN

46.6% 47.2% 48.8%

44.2% 44.7% 45.2%

10

Cut-off temperature TS pin voltage falling

threshold

V_TCO

As percentage to V_REGN

Deglitch time for temperature out of range

detection

V_TS> V_LTF, or V_TS< V_TCO, or V_TS< V_HTF

ms

Cold temperature threshold, TS pin

voltage rising threshold

As percentage to V_REGNREG02[1] = 0

(Approx. -10°C w/ 103AT)

VBCOLD0

75.5%

78.5%

35.5%

32.5%

76% 76.5%

1%

As percentage to V_REGNREG02[1] = 0

(Approx. 1°C w/ 103AT)

VBCOLD0_HYS

VBCOLD1

Cold temperature threshold 1, TS pin

voltage rising threshold

As percentage to V_REGNREG02[1] = 1

(Approx. -20°C w/ 103AT)

79% 79.5%

1%

As percentage to V_REGNREG02[1] = 1

(Approx. 1°C w/ 103AT)

VBCOLD1_HYS

VBHOT0

Hot temperature threshold, TS pin voltage As percentage to V_REGNREG06[3:2] = 01

falling threshold

36% 36.5%

3%

(Approx. 55°C w/ 103AT)

As percentage to V_REGNREG06[3:2] = 01

(Approx. 3°C w/ 103AT)

VBHOT0_HYS

VBHOT1

Hot temperature threshold 1, TS pin

voltage falling threshold

As percentage to V_REGNREG06[3:2] = 00

(Approx. 60°C w/ 103AT)

33% 33.5%

3%

As percentage to V_REGNREG06[3:2] = 00

(Approx. 3°C w/ 103AT)

VBHOT1_HYS

(1) REGN LDO is configured in drop-out mode. VBUS is close to REGN when I_REGN= 0 mA.

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values unless other

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Hot temperature threshold 2, TS pin

voltage falling threshold

As percentage to V_REGNREG06[3:2] = 10

(Approx. 65°C w/ 103AT)

VBHOT2

29.5%

30% 30.5%

3%

As percentage to V_REGNREG06[3:2] = 10

(Approx. 3°C w/ 103AT)

VBHOT2_HYS

CHARGE OVER-CURRENT COMPARATOR

HSFET cycle by cycle over-current

I_{HSFET_OCP}

threshold

5.3

5.5

7.5

6.6

A

I_{BATFET_OCP}

V_{LSFET_UCP}

System over load threshold

LSFET charge under-current falling

threshold

From sync mode to non-sync mode

100

mA

PWM Switching frequency, and digital

clock

F_SW

1300

1500

97%

3.6

1700 kHz

D_MAX

Maximum PWM duty cycle

VBTST-VSW when LSFET refresh pulse is requested,

VBUS = 5 V

V_{BTST_REFRESH}

Bootstrap refresh comparator threshold

V

BOOST MODE OPERATION

V_{OTG_REG_ACC}

V_{OTG_BAT}

OTG output voltage

I(VBUS) = 0, REG06[7:4] = 0111 (4.998 V)

BAT falling, REG04[1] = 1

REG01[0] = 0

5

V

OTG output voltage accuracy

-3%

2.9

1

3%

V

Battery voltage exiting OTG mode

A

I_OTG

OTG mode output current

REG01[0] = 1

1.5

5.8

A

V_{OTG_OVP}

OTG over-voltage threshold

Rising threshold

6

V

V_{OTG_OVP_HYS}

I_{OTG_LSOCP}

I_{OTG_HSZCP}

OTG over-voltage threshold hysteresis

LSFET cycle by cycle current limit

HSFET under current falling threshold

Falling threshold

300

mV

A

5

100

1.15

1.70

mA

REG01[0] = 0

REG01[0] = 1

1.00

1.50

1.30

A

I_{RBFET_OCP}

REGN LDO

V_REGN

RBFET over-current threshold

1.90

V_VBUS= 6 V, I_REGN= 40 mA

V_VBUS= 5 V, I_REGN= 20 mA

V_VBUS= 5 V, V_REGN= 3.8 V

4.8

4.7

50

5

5.5

V

REGN LDO output voltage

REGN LDO current limit

4.8

I_REGN

mA

LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)

V_ILO

V_IH

Input low threshold

0.4

V

Input high threshold (CE, STAT, QON,

PSEL, PG)

1.3

1.1

V_{IH_OTG}

V_{OUT_LO}

Input high threshold (OTG)

Output low saturation voltage

V

Sink current = 5 mA

Pull-up rail 1.8 V

Pull-up rail 3.6 V

0.4

1

High level leakage current (OTG, CE,

STAT , PSEL, PG)

I_BIAS

µA

High level leakage current (QON)

8

I²C INTERFACE (SDA, SCL, INT)

V_IH

Input high threshold level

VPULL-UP = 1.8 V, SDA and SCL

Sink current = 5 mA

1.3

V

V_IL

Input low threshold level

Output low threshold level

High-level leakage current

SCL clock frequency

0.4

1

V_OL

I_BIAS

f_SCL

V

VPULL-UP = 1.8 V, SDA and SCL

µA

400 kHz

DIGITAL CLOCK AND WATCHDOG TIMER

f_HIZ

f_DIG

Digital crude clock

Digital clock

REGN LDO disabled

REGN LDO enabled

15

35

50 kHz

1300

1500

1700 kHz

10

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8.6 Timing Requirements

MIN

TYP

MAX UNIT

VBUS/BAT POWER UP

t_BADSRC

Bad source detection duration

30

ms

BOOST MODE OPERATION

t_{OTG_OCP_OFF}

t_{OTG_OCP_ON}

QON TIMING

t_QON

OTG mode over-current protection off cycle time

32

ms

µs

OTG mode over-current protection on cycle time

260

QON pin high time to turn on BATFET

2

ms

DIGITAL CLOCK AND WATCHDOG TIMER

REGN LDO disabled

REGN LDO enabled

112

136

160

t_WDTREG05[5:4] = 11

sec

Figure 1. I²C-Compatible Interface Timing Diagram

8.7 Typical Characteristics

Table 1. Table of Figures

FIGURE

Charging Efficiency vs Charging Current (DCR = 10 mΩ)

System Efficiency vs System Load Current (DCR = 10 mΩ)

Boost Mode Efficiency vs VBUS Load Current (DCR = 10 mΩ)

SYS Voltage Regulation vs System Load Current

Boost Mode VBUS Voltage Regulation (Typical Output = 4.998 V, REG06[7:4] = 0111) vs VBUS Load Current

SYS Voltage vs Temperature

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

BAT Voltage vs Temperature

Input Current Limit vs Temperature

Charge Current vs Package Temperature

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95

90

85

80

75

70

95

90

85

80

75

70

VBUS = 5V

2.5

65

0

0.5

1

1.5

2

2.5

3

3.5

1.5

0

0.5

1

1.5

2

3

Charge Current (A)

Load Current (A)

Figure 2. Charge Efficiency vs Charge Current

Figure 3. System Efficiency

vs System Load Current

100

95

90

85

80

75

70

65

60

4

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

SYSMIN = 3.5

SYSMIN = 3.2

SYSMIN = 3.7

VBAT = 3.2V

VBAT = 3.5V

VBAT = 3.8V

0

0.5

1

0

0.5

1

1.5

2

2.5

3

3.5

VBUS Load Current (A)

System Load Current (A)

Figure 4. Boost Mode Efficiency

vs VBUS Load Current

Figure 5. SYS Voltage Regulation

vs System Load Current

5.1

5

3.7

3.65

3.6

4.9

4.8

4.7

4.6

4.5

3.55

3.5

VBAT = 3.2V

VBAT = 3.5V

VBAT = 3.8V

SYSMIN = 3.5V

100 125 150

0

0.5

1

-50

-25

0

25

50

75

VBUS Load Current (A)

Temperature (^oC)

Typical Output = 4.998 V, REG06[7:4] = 0111

Figure 6. Boost Mode VBUS Voltage Regulation

vs VBUS Load Current

Figure 7. SYS Voltage vs Temperature

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4.4

2.5

2

4.35

4.3

1.5

1

4.25

4.2

IIN = 500mA

IIN = 1.5A

IIN = 2A

0.5

0

VREG = 4.208V

VREG = 4.35V

4.15

4.1

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (^oC)

Temperature ^(oC)

Figure 8. BAT Voltage vs Temperature

Figure 9. Input Current Limit vs Temperature

2.5

TREG = 120C

TREG = 80C

2

1.5

1

0.5

0

60

80

100

120

140

160

Package Temperature (^oC)

Figure 10. Charge Current vs Package Temperature

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9 Detailed Description

9.1 Overview

The bq24296, bq24297 is an I²C controlled power path management device and a single cell Li-Ion battery

charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-

side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also

integrates the bootstrap diode for the high-side gate drive.

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9.2 Functional Block Diagram

VBUS

PMID

RBFET (Q1)

V_{VBUS_UVLOZ}

UVLO

Q1 Gate

Control

REGN

V_BATZ+V_SLEEP

SLEEP

REGN

LDO

EN_HIZ

ACOV

V_ACOV

BTST

FBO

VBUS

VBUS_OVP_BOOST

Q2_UCP_BOOST

V_{OTG_OVP}

I(Q2)

V_INDPM

I_{OTG_HSZCP}

SW

I(Q3)

I_{OTG_LSOCP}

Q3_OCP_BOOST

HSFET (Q2)

CONVERTER

CONTROL

REGN

I_INDPM

BAT

BATOVP

IC T_J

T_REG

104%xV_{BAT_REG}

BAT

LSFET (Q3)

PGND

I(Q2)

I_{LSFET_UCP}

V_{BAT_REG}

UCP

Q2_OCP

I(Q3)

SYS

I_{HSFET_OCP}

V_SYSMIN

EN_HIZ

EN_CHARGE

EN_BOOST

V_BTST-SW

I_{CHG_REG}

REFRESH

V_{BTST_REFRESH}

SYS

I_CHG

V_{BAT_REG}

Q4 Gate

Control

I_{CHG_REG}

REF

DAC

BATFET (Q4)

I_BADSRC

BAD_SRC

I_DC

CONVERTER

CONTROL

STATE

BAT

ILIM

IC T_J

T_SHUT

TSHUT

D+ (bq24297)

USB Host

Adapter

MACHINE

D– (bq24297)

PSEL(bq24296)

OTG

BAT

QON

Detection

BAT_GD

RECHRG

USB

Adapter

V_BATGD

V_{BAT_REG}- V_RECHG

bq24296/297

BAT

I_CHG

INT

TERMINATION

CHARGE

CONTROL

STATE

I_TERM

BATTERY

THERMISTER

SENSING

SUSPEND

BATLOWV

STAT

TS

V_BATLOWV

BAT

MACHINE

I2C

Interface

PG(bq24296)

V_SHORT

BAT

BATSHORT

CE

SCL SDA

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9.3 Feature Description

9.3.1 Device Power Up

9.3.1.1 Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises

above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I²C interface

is ready for communication and all the registers are reset to default value. The host can access all the registers

after POR.

9.3.1.2 Power Up from Battery without DC Source

If only battery is present and the voltage is above depletion threshold (V_{BAT_DEPL}), the BATFET turns on and

connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low R_DSONin

BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

During both boost and charge mode, the device always monitors the discharge current through BATFET. When

the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the

input source plugs in again.

9.3.1.2.1 BATFET Turn Off

The BATFET can be forced off by the host through I²C REG07[5]. This bit allows the user to independently turn

off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no

path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by

setting REG07[5] to 1 to disable charging and supplement mode.

9.3.1.2.2 Shipping Mode

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,

the device can turn off BATFET so that the system voltage is zero to minimize the leakage. The BATFET can be

turned off by setting REG07[5] (BATFET_DISABLE) bit.

In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] =

00) and disable BATFET (REG07[5] = 1) at the same time. Once the BATFET is disabled, one of the following

events can turn on BATFET and clear REG07[5] (BATFET_DISABLE) bit.

1. Plug in adapter

2. Write REG07[5] = 0

3. watchdog timer expiration

4. Register reset (REG01[7] = 1)

5. A logic low to high transition on QON pin (refer to Figure 11 for detail timing)

Min. 2ms

QON

BATFET Status

Turn off by i2c command

Turn on by QON

REG07[5]=0

REG07[5]=1

Figure 11. QON Timing

9.3.1.3 Power Up from DC Source

When the DC source plugs in, the charger device checks the input source voltage to turn on REGN LDO and all

the bias circuits. It also checks the input current limit before starts the buck converter.

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Feature Description (continued)

9.3.1.3.1 REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also

provides bias rail to TS external resistors. The pull-up rail of STAT and PG (bq24296) can be connected to

REGN as well.

The REGN is enabled when all the conditions are valid.

1. VBUS above V_{VBUS_UVLOZ}

2. VBUS above V_BAT+ V_SLEEPZin buck mode or VBUS below V_BAT+ V_SLEEPin boost mode

3. After typical 220-ms delay (100 ms minimum) is complete

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The

device draws less than I_VBUS(15 µA typical) from VBUS during HIZ state. The battery powers up the system

when the device is in HIZ.

9.3.1.3.2 Input Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has

to meet the following requirements to start the buck converter.

1. VBUS voltage below V_ACOV(not in VBUS over-voltage)

2. VBUS voltage above V_BADSRC(3.8 V typical) when pulling I_BADSRC(30 mA typical) (poor source detection)

Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin

(bq24296) goes low. An INT is asserted to the host.

If the device fails the poor source detection, it will repeat the detection every 2 seconds.

9.3.1.3.3 Input Current Limit Detection

The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable

device is attached to a USB host, the USB specification requires the portable device to draw limited current (100

mA/500 mA in USB 2.0, and 150 mA/900 mA in USB 3.0). If the portable device is attached to a charging port, it

is allowed to draw up to 3 A.

After the PG is LOW (bq24296) or REG08[2] goes HIGH, the charger device always runs input current limit

detection when a DC source plugs in unless the charger is in HIZ during host mode.

The bq24297 follows Battery Charging Specification 1.2 (BC1.2) to detect input source through USB D+/D- lines.

The bq24296 sets input current limit through PSEL and OTG pins. After the input current limit detection is done,

the detection result is reported in VBUS_STAT registers (REG08[7:6]) and input current limit is updated in IINLIM

register (REG00[2:0]). In additon, host can write to REG00[2:0] to change the input current limit.

9.3.1.3.4 D+/D– Detection Sets Input Current Limit (bq24297)

The bq24297 contains a D+/D– based input source detection to program the input current limit. The D+/D-

detection has three steps: data contact detect (DCD), primary detection, and non-standard adapter detection.

When the charging source passes data contact detect, the device would proceed to run primary detection.

Otherwise the charger would proceed to run non-standard adapter detection.

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Feature Description (continued)

D+

VDP_SRC

VLGC_HI

IDP_SRC

CHG_DET

VDAC_REF

IDM_SINK

D-

RDM_DWN

Figure 12. USB D+/D- Detection

DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during

an attach event. The protocol for data contact detect is as follows:

•

Detect VBUS present and REG08[2] = 1 (power good)

Turn on D+ I_{DP_SRC}and the D– pull-down resistor R_{DM_DWN}for 40 ms

If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec.

Turn off I_{DP_SRC}and disconnect R_{DM_DWN}

The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and

different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP).

The protocol for primary detection is as follows:

•

Turn on V_{DP_SRC}on D+ and I_{DM_SINK}on D– for 40 ms

If PD is attached to a USB host (SDP), the D– is low. If PD is attached to a charging port (CDP or DCP), the

D– is high

•

Turn off V_{DP_SRC}and I_{DM_SINK}

Table 2 shows the input current limit setting after D+/D– detection.

Table 2. bq24297 USB D+/D– Detection

D+/D– DETECTION

OTG

INPUT CURRENT LIMIT

REG08[7:6]

0.5 sec timer expired in DCD

(D+/D- floating)

—

Proceed to non-standard

adapter detection

00

USB host

LOW

HIGH

—

100 mA

500 mA

3 A

01

10

Charging port

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When DCD 0.5 sec timer expires, the non-standard adapter detection is used to distinguish three different divider

bias conditions on D+/D- pins. When non-standard adapter is detected, the input current limit (REG0[2:0]) is set

based on the table shown below and REG08[7:6] is set to 10 (Adapter port). If non-standard adapter is not

detected, REG08[7:6] is set to 00 (Unknown) and the input current limit is set in REG0[2:0] to 500 mA by default.

Table 3. bq24297 Non-Standard Adapter Detection

NON-

STANDARD

ADAPTER

INPUT

CURRENT

LIMIT

D+ THRESHOLD

D- THRESHOLD

Divider 1

V_{adpt1_lo}< V_D+< V_{adpt1_hi}

For VBUS = 5 V, typical range 2.4 V < V_D+< 3.1 V

V_D-< V_{adpt1_lo}or V_D-> V_{adpt1_hi}

For VBUS = 5 V, typical range V_D-< 2.4 V or V_D-

3.1 V

2.0A

>

Divider 2

Divider 3

V_{adpt2_lo}< V_D+< V_{adpt2_hi}

For VBUS = 5 V, typical range 0.85 V < V_D+< 1.5 V

NA

2.0A

1A

V_D+< V_{adpt3_lo}or V_D+> V_{adpt3_hi}

V_{adpt3_lo}< V_D-< V_{adpt3_hi}

For VBUS = 5 V, typical range V_D+< 2.4 V or V_D+

3.1 V

>

For VBUS = 5 V, typical range 2.4 V < V_D-< 3.1 V

After D+/D- detection is completed with an input source already plugged in, the input current limit is not changed

unless DPDM_EN (REG07[7]) bit is set to force detection.

9.3.1.3.5 PSEL/OTG Pins Set Input Current Limit

The bq24296 has PSEL instead of D+/D-. It directly takes the USB PHY device output to decide whether the

input is USB host or charging port.

Table 4. bq24296 Input Current Limit Detection

PSEL

HIGH

LOW

OTG

LOW

HIGH

—

INPUT CURRENT LIMIT

REG08[7:6]

100 mA

500 mA

3 A

01

10

9.3.1.3.6 HIZ State with 100mA USB Host

In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the

portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good

threshold (V_BATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state,

the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets

REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 µA. The system is supplied by the

battery.

Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When

the processor host wakes up, it is recommended to first check if the charger is in HIZ state.

In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another

source plugs in, the charger IC will run detection again, and update the input current limit.

9.3.1.3.7 Force Input Current Limit Detection

While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting

REG07[7] = 1 or when watchdog timeout. During the forced detection, the input current limit is set to 100 mA.

After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on

D+/D- (bq24297) or PSEL/OTG (bq24296).

9.3.1.4 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery

charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input

current limit is forced to 100mA. After the system rises above 2.2 V, the charger device sets the input current

limit set by the lower value between register and ILIM pin.

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As a battery charger, the charger deploys a 1.5-MHz step-down switching regulator. The fixed frequency

oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,

charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-

tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp

height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below

minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is

set by the ratio of SYS and VBUS.

9.3.1.5 Boost Mode Operation from Battery

The device supports boost converter operation to deliver power from the battery to other portable devices

through USB port. The boost mode output current rating meets the USB On-The-Go 1-A output requirement. The

maximum output current is 1.5 A. The boost operation can be enabled if the following conditions are valid:

1. BAT above BATLOWV threshold (V_BATLOWVset by REG04[1])

2. VBUS less than V_BAT+ V_SLEEP(in sleep mode)

3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10)

4. Thermistor Temperature is within boost mode temperature monitor threshold unless BHOT[1:0] is set to 11

(REG06[1:0]) to disable this monitor function

5. After 30ms delay from boost mode enable

In boost mode, the device employs a 1.5-MHz step-up switching regulator. Similar to buck operation, the device

switches from PWM operation to PFM operation at light load to improve efficiency.

During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5 V and the output current

can reach up to 1 A or 1.5 A, selected via I²C (REG01[0]). In addition, the device provides adjustable boost

voltage from 4.55 V to 5.5 V by changing BOOSTV bits in REG06[7:4]

Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to

1 and an INT is asserted.

9.3.2 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device

provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or

both.

9.3.2.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above

the minimum system voltage (default 3.5 V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the

minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the

V_DSof BATFET.

When the battery charging is disabled or terminated, the system is always regulated at 150 mV above the

minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system

voltage regulation.

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4.5

4.3

4.1

Charge Enabled

Charge Disabled

SYS

(V)

3.9

3.7

3.5

Minimum System Voltage

3.3

3.1

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3

BAT (V)

Figure 13. V(SYS) vs V(BAT)

9.3.2.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic

Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage

falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current

falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement

mode where the BATFET turns on and battery starts discharging so that the system is supported from both the

input source and battery.

During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.

Figure 14 shows the DPM response with 5-V/1.2-A adapter, 3.2-V battery, 2.0-A charge current and 3.4-V

minimum system voltage setting.

Voltage

VBUS

5V

SYS

BAT

3.6V

3.4V

3.2V

3.18V

Current

3A

ICHG

2.3A

2.0A

ISYS

1.5A

1.0A

IIN

0.5A

-0.7A

DPM

Supplement

Figure 14. DPM Response

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9.3.2.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is

regulated the gate drive of BATFET so that the minimum BATFET V_DSstays at 30 mV when the current is low.

This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the

BATFET gate is regulated with a higher voltage to reduce R_DSONuntil the BATFET is in full conduction. At this

point onwards, the BATFET V_DSlinearly increases with discharge current. shows the V-I curve of the BATFET

gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion

threshold.

3.0

2.5

2.0

1.5

1.0

0.5

0

10 20 30 40 50 60 70 80

V(BAT-SYS) (mV)

Figure 15. BATFET V-I Curve

9.3.3 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3-A charge current for high capacity tablet battery. The 24-mΩ

BATFET improves charging efficiency and minimizes the voltage drop during discharging.

9.3.3.1 Autonomous Charging Cycle

With battery charging enabled at POR (REG01[5:4] = 01), the charger device complete a charging cycle without

host involvement. The device default charging parameters are listed in the following table.

Table 5. Charging Parameter Default Setting

DEFAULT MODE

Charging voltage

Charging current

Pre-charge current

Termination current

Temperature profile

Safety timer

bq24296 / bq24297

4.208 V

2.048 A

256 mA

Hot/Cold

12 hours⁽¹⁾

(1) See Charging Safety Timer for more information.

A new charge cycle starts when the following conditions are valid:

•

Converter starts

Battery charging is enabled by I²C register bit (REG01[5:4]) = 01 and CE is low

No thermistor fault on TS

No safety timer fault

BATFET is not forced to turn off (REG07[5])

The charger device automatically terminates the charging cycle when the charging current is below termination

threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below

recharge threshold (REG04[0]), the device automatically starts another charging cycle. After the charge done,

either toggle /CE pin or REG01[5:4] will initiate a new charging cycle.

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The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)

or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging

disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a

charging cycle is complete, an INT is asserted to notify the host.

The host can always control the charging operation and optimize the charging parameters by writing to the

registers through I²C.

9.3.3.2 Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the

beginning of a charging cycle, the device checks the battery voltage and applies current.

Table 6. Charging Current Setting

VBAT

CHARGING CURRENT

REG DEFAULT SETTING

REG08[5:4]

V_BAT< V_SHORT

(Typical 2 V)

100 mA

–

01

V_SHORT≤ V_BAT< V_BATLOWV

(Typical 2 V ≤ V_BAT< 3 V)

REG03[7:4]

REG02[7:2]

256 mA

01

10

V_BAT≥ V_BATLOWV

2048 mA

(Typical V_BAT≥ 3 V)

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will

be less than the programmed value. In this case, termination is temporarily disabled and the charging safety

timer is counted at half the clock rate.

Regulation Voltage

(3.5V – 4.4V)

Battery Voltage

Fast Charge Current

(500mA-3008mA)

Charge Current

V

BAT_LOWV (2.8V/3V)

V

BAT_SHORT (2V)

I

PRECHARGE (128mA-2048mA)

TERMINATION (128mA-2048mA)

BATSHORT (100mA)

I

Fast Charge and Voltage Regulation

Trickle Charge Pre-charge

Safety Timer

Expiration

Figure 16. Battery Charging Profile

9.3.3.3 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

9.3.3.3.1 Cold/Hot Temperature Window

The device continuously monitors battery temperature by measuring the voltage between the TS pin and ground,

typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device

compares this voltage against its internal thresholds to determine if charge or boost is allowed.

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To initiate a charge cycle, the battery temperature must be within the V_LTFto V_HTFthresholds. During the charge

cycle the battery temperature must be within the V_LTFto V_TCOthresholds, else the device suspends charging and

waits until the battery temperature is within the V_LTFto V_HTFrange.

For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx

to VBHOTx thresholds unless boost mode temperature is disabled by setting BHOT bits (REG06[3:2]) to 11.

When temperature is outside of the temperature thresholds, the boost mode is suspended and REG08[7:6] bits

(VBUS_STAT) are set to 00. Once temperature returns within thresholds, the boost mode is recovered.

REGN

bq24296

bq24297

RT1

TS

RTH

RT2

103AT

Figure 17. TS Resistor Network

When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT

is asserted to the host. The STAT pin indicates the fault when charging is suspended.

TEMPERATURE RANGE

TEMPERATURE RANGE TO

INITIATE CHARGE

DURING A CHARGE CYCLE

VREF

CHARGE SUSPENDED

V_LTF

V_LTFH

CHARGE at full C

V_HTF

V_TCO

CHARGE SUSPENDED

AGND

Figure 18. TS Pin Thermistor Sense Thresholds in Charge Mode

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Temperature Range to

Boost

VREF

Boost Disable

V

BCOLDx

(-10ºC / -20ºC)

Boost Enable

V

BHOTx

(55ºC / 60ºC / 65ºC)

Boost Disable

AGND

Figure 19. TS Pin Thermistor Sense Thresholds in Boost Mode

Assuming a 103AT NTC thermistor is used on the battery pack Figure 18, the value RT1 and RT2 can be

determined by using the following equation:

æ

ç

è

ö

÷

ø

1

V_VREF´RTH_COLD´RTH_HOT

´

-

V_LTFV_TCO

RT2 =

æ

ç

è

ö

æ

ç

è

ö

V_VREF

RTH_HOT

´

-1 - RTH

´

-1

÷

COLD

V_TCO

V_LTF

ø

V_VREF

-1

V_LTF

RT1=

1

+

RT2 RTH_COLD

(1)

Select 0°C to 45°C range for Li-ion or Li-polymer battery,

RTH_COLD= 27.28 kΩ

RTH_HOT= 4.911 kΩ

RT1 = 5.25 kΩ

RT2 = 31.23 kΩ

9.3.3.4 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is

below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps

running to power the system, and BATFET can turn back on to engage supplement mode.

When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is

temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination

can be disabled by writing 0 to REG05[7].

9.3.3.4.1 Termination When REG02[0] = 1

When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the

termination current. The charger device termination function should be disabled. When the battery is charged to

fully capacity, the host disables charging through CE pin or REG01[5:4].

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9.3.3.5 Charging Safety Timer

The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety

timer is 4 hours when the battery is below batlowv threshold. The user can program fast charge safety timer

(default 12 hours) through I²C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11

and an INT is asserted to the host. The safety timer feature can be disabled via I²C (REG05[3]).

The following actions restart the safety timer after safety timer expires:

•

Toggle the CE pin HIGH to LOW to HIGH (charge enable)

Write REG01[5:4] from 00 to 01 (charge enable)

Write REG05[3] from 0 to 1 (safety timer enable)

During input voltage/current regulation, thermal regulation, or FORCE_20PCT bit (REG02[0]) is set , the safety

timer counting at half clock rate since the actual charge current is likely to be below the register setting. For

example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the

safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to

REG07[6].

9.3.3.5.1 Safety Timer Configuration Change

When safety timer value needs to be changed, it is recommended that the timer is disabled first before new

configuration is written to REG05[2:1]. The safety timer can be disable by writing 1 to REG05[3]. This ensures

the safety timer restart counting after new value is configured.

9.3.3.6 USB Timer When Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of

the timer, the device stops the converter and goes to HIZ.

9.3.4 Status Outputs (PG, STAT, and INT)

9.3.4.1 Power Good Indicator (PG) (bq24296)

In bq24296, PG goes LOW to indicate a good input source when:

1. VBUS above V_{BUS_UVLO}

2. VBUS above battery (not in sleep)

3. VBUS below V_ACOVthreshold

4. VBUS above V_{BUS_MIN}when I_BADSRCcurrent is applied (not a poor source)

9.3.4.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application

diagram shows.

Table 7. STAT Pin State

CHARGING STATE

Charging in progress (including recharge)

Charging complete

STAT

LOW

HIGH

Sleep mode, charge disable

HIGH

Charge suspend (Input over-voltage, TS fault, timer fault, input

or system over-voltage)

blinking at 1Hz

9.3.4.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the

device operation. The following events will generate a 256-µs INT pulse.

1. USB/adapter source identified (through PSEL or DPDM detection, and OTG pin)

2. Good input source detected

–

not in sleep

VBUS below V_ACOVthreshold

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–

current limit above I_BADSRC

3. Input removed or VBUS above V_ACOVthreshold

4. Charge Complete

5. Any FAULT event in REG09

For the first four events, INT pulse is always generated. For the last event, when a fault occurs, the charger

device sends out INT and latches the fault state in REG09 until the host reads the fault register. If a prior fault

exists, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC

fault is not latched and always reports the current thermistor conditions. In order to read the current fault status,

the host has to read REG09 two times consecutively. The 1^streads fault register status from the last read and

the 2^ndreads the current fault register status.

9.3.5 Protections

9.3.5.1 Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.

The input maximum current is set by a resistor from ILIM pin to ground as:

1V

I

=

´K_LIM

INMAX

R_ILIM

(2)

The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For

example, if the register setting is 111 for 3 A, and ILIM has a 316-Ω resistor to ground for 1.5 A, the input current

limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings.

The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation

(Refer to Dynamic Power Path Management section).

The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current

following Equation 3:

V

ILIM

I

=

´I

INMAX

IN

1V

(3)

For example, if ILIM pin sets 2 A, and the ILIM voltage is 0.75 V, the actual input current 1.5 A. If ILIM pin is

open, the input current is limited to zero since ILIM voltage floats above 1 V. If ILIM pin is short, the input current

limit is set by the register.

9.3.5.2 Thermal Regulation and Thermal Shutdown

During charge operation, the device monitors the internal junction temperature T_Jto avoid overheat the chip and

limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]),

the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the

user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current.

Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1]

goes high.

Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and

an INT is asserted to the host.

9.3.5.3 Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode

operation.

9.3.5.3.1 Input Over-Voltage (ACOV)

The maximum input voltage for buck mode operation is V_{VBUS_OP}. If VBUS voltage exceeds V_ACOV, the device

stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An

INT is asserted to the host.

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9.3.5.3.2 System Over-Voltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system

would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to

clamp the overshoot.

9.3.5.4 Voltage and Current Monitoring in Boost Mode

The charger device closely monitors the VBUS voltage, as well as LSFET current to ensure safe boost mode

operation.

9.3.5.4.1 Over-Current Protection

The charger device closely monitors the RBFET (Q1) and LSFET (Q3) current to ensure safe boost mode

operation. During over-current condition, the device will operate in hiccup mode for protection. While in hiccup

mode cycle, the device turns off RBFET for t_{OTG_OCP_OFF}(32 ms typical) and turns on RBFET for t_{OTG_OCP_ON}

(260 us typical) in an attempt to restart. If the over-current condition is removed, the boost converter will maintain

the RBFET on state and the VBUS OTG output will operate normally. When over-current condition continues to

exist, the device will repeat the hiccup cycle until over-current condition is removed. When over-current condition

is detected, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An

INT is asserted to the host.

9.3.5.4.2 VBUS Over-Voltage Protection

When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the

VBUS voltage exceeds V_{OTG_OVP}, the device stops switching and the device exits boost mode. During the over-

voltage, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is

asserted to the host.

9.3.5.5 Battery Protection

9.3.5.5.1 Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at V_{BAT_OVP}(4% nominal) above the battery regulation voltage. When

battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[3] goes

high and an INT is asserted to the host.

9.3.5.5.2 Battery Short Protection

If the battery voltage falls below V_short(2V typical), the device immediately turns off BATFET to disable the

battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100-mA

current. The device does not turn on BATFET to discharge a battery that is below 2.5 V.

9.3.5.5.3 System Over-Current Protection

If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on

VBUS is required to reset the latch-off condition and turn on BATFET.

9.4 Device Functional Modes

9.4.1 Host Mode and Default Mode

The device is a host controlled device, but it can operate in default mode without host management. In default

mode, the device can be used as an autonomous charger with no host or with host in sleep.

When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW.

After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in

the default settings. The device keeps charging the battery by default with 12-hour fast charging safety timer. At

the end of the 12 hours, the charging is stopped and the buck converter continues to operate to supply system

load.

Any write command to device transitions the device from default mode to host mode. All the device parameters

can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by

writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting

REG05[5:4] = 00.

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Device Functional Modes (continued)

When the host changes watchdog timer configuration (REG05[5:4]), it is recommended to first disable watchdog

by writing 00 to REG05[5:4] and then change the watchdog to new timer values. This ensures the watchdog

timer is restarted after new value is written.

POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Start watchdog timer

Host programs registers

Y

I2C Write?

N

Default Mode

Reset watchdog timer

Reset registers

Y

N

Reset REG01

bit[6]?

N

Y

N

I2C Write?

Y

Watchdog Timer

Expired?

Figure 20. Watchdog Timer Flow Chart

9.4.1.1 Plug in USB100mA Source with Good Battery

When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold

(V_BATGD), the charger device enters HIZ state to meet the battery charging spec requirement.

If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and

the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It

is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The

host can write REG00[7] to 0 to exit HIZ state.

If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state

automatically. When the input source plugs in again, the charger IC runs detection on the input source and

update the input current limit.

9.4.1.2 USB Timer When Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of

the timer, the device stops the converter and goes to HIZ.

9.5 Programming

9.5.1 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP

Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices

can be considered as masters or slaves when performing data transfers. A master is the device which initiates a

data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device

addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like

micro controller or a digital signal processor. The I²C interface supports both standard mode (up to 100 kbits),

and fast mode (up to 400 kbits).

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Programming (continued)

Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-

up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

9.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Change

of data

allowed

Data line stable;

Data valid

Figure 21. Bit Transfer on the I²C Bus

9.5.1.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

START (S)

Figure 22. START and STOP Conditions

9.5.1.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

30

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

Programming (continued)

Acknowledgement

signal from receiver

Acknowledgement

signal from slave

MSB

SDA

S or Sr

1

2

7

8

9

1

2

8

9

P or Sr

SCL

ACK

START or

Repeated

STOP or

Repeated

START

Figure 23. Data Transfer on the I²C Bus

9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9^thclock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

9.5.1.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

S

8

9

8

9

8

9

P

SCL

1-7

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

START

Figure 24. Complete Data Transfer

9.5.1.5.1 Single Read and Write

1

8

1

7

1

0

1

8

Slave Address

ACK

Reg Addr

ACK

P

S

ACK

Data Addr

Figure 25. Single Write

1

8

1

7

1

0

1

7

Slave Address

ACK

Reg Addr

ACK

S

ACK

Slave Address

1

8

P

Data

NCK

Figure 26. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

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Programming (continued)

9.5.1.5.2 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG08.

1

8

7

1

0

1

Slave Address

ACK

Reg Addr

ACK

S

1

8

1

8

1

8

1

Slave Address

ACK

Data to Addr+1

ACK

Data to Addr+1

ACK

P

Figure 27. Multi-Write

1

8

1

7

1

0

1

7

1

Slave Address

ACK

Reg Addr

ACK

1

ACK

S

8

1

8

1

8

1

Data @ Addr

ACK

Data @ Addr+1

ACK

Data @ Addr+1

ACK

P

Figure 28. Multi-Read

The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if

Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it

is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault

register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not

support multi-read or multi-write.

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For

example, if there is a TS fault but gets recovered immediately, the host still sees TS fault during the first read. In

order to get the fault information at present, the host has to read REG09 for the second time. REG09 does not

support multi-read and multi-write.

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

9.6 Register Map

9.6.1 I²C Registers

Address: 6BH. REG00-07 support Read and Write. REG08-0A are Read only.

9.6.1.1 Input Source Control Register REG00 [reset = 00110xxx, or 3x]

Figure 29. Input Source Control Register REG00 Format

7

6

5

4

3

2

1

0

EN_HIZ

R/W

VINDPM[3]

R/W

VINDPM[2]

R/W

VINDPM[1]

R/W

VINDPM[0]

R/W

IINLIM[2]

R/W

IINLIM[1]

R/W

IINLIM[0]

R/W

LEGEND: R/W = Read/Write

Table 8. Input Source Control Register REG00 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Bit 7

EN_HIZ

R/W

0

0 – Disable, 1 – Enable

Default: Disable (0)

Input Voltage Limit

Bit 6

Bit 5

Bit 4

Bit 3

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

R/W

0

1

0

640 mV

320 mV

160 mV

80 mV

Offset 3.88 V, Range: 3.88 V – 5.08 V

Default: 4.36 V (0110)

Input Current Limit (Actual input current limit is the lower of I²C and ILIM)

Bit 2

Bit 1

Bit 0

IINLIM[2]

IINLIM[1]

IINLIM[0]

R/W

x

000 – 100 mA, 001 – 150 mA,

010 – 500 mA, 011 – 900 mA, 100 – 1 A,

101 – 1.5 A,

bq24296

PSEL = Lo : 3 A (111)

PSEL = Hi : 100 mA (000) (OTG pin = Lo) or

500 mA (OTG pin = Hi)

bq24297

110 – 2 A, 111 – 3A

Default SDP : 100 mA (000) (OTG pin = Lo)

or 500 mA (OTG pin = Hi)

Default DCP/CDP: 3 A (111)

Default Divider 1 and 2 : 2 A (110)

Default Divider 3 : 1 A (100)

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9.6.1.2 Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]

Figure 30. Power-On Configuration Register REG01 Format

7

6

5

4

3

2

1

0

I²C Watchdog

Timer Reset

Register Reset

R/W

OTG_CONFIG CHG_CONFIG

R/W R/W

SYS_MIN[2]

R/W

SYS_MIN[1]

R/W

SYS_MIN[0]

R/W

BOOST_LIM

R/W

LEGEND: R/W = Read/Write

Table 9. Power-On Configuration Register REG01 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Bit 7

Register Reset R/W

0

0 – Keep current register setting,

1 – Reset to default

Default: Keep current register setting (0)

Note: Register Reset bit does not reset

device to default mode

Bit 6

I²C Watchdog R/W

Timer Reset

0

0 – Normal ; 1 – Reset

Default: Normal (0)

Note: Consecutive I²C watchdog timer

reset requires minimum 20-µs delay

Charger Configuration

Bit 5

OTG_CONFIG R/W

0

1

0 – OTG Disable; 1 – OTG Enable⁽¹⁾

0- Charge Disable; 1- Charge Enable⁽¹⁾

Default: OTG disable (0)

Note: OTG_CONFIG would over-ride

Charge Enable Function in

CHG_CONFIG

Bit 4

CHG_CONFIG R/W

Default: Charge Battery (1)

Minimum System Voltage Limit

Bit 3

Bit 2

Bit 1

SYS_MIN[2]

SYS_MIN[1]

SYS_MIN[0]

R/W

1

0

1

0.4 V

0.2 V

0.1 V

Offset: 3.0 V, Range 3.0 V – 3.7 V

Default: 3.5 V (101)

Boost Mode Current Limit

Bit 0 BOOST_LIM R/W

1

0 – 1 A, 1 – 1.5 A

Default: 1.5 A (1)

(1) The CHG_CONFIG and OTG_CONFIG bits cannot be set at the same time.

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

9.6.1.3 Charge Current Control Register REG02 [reset = 01100000, or 60]

Figure 31. Charge Current Control Register REG02 Format

7

6

5

4

3

2

1

0

ICHG[5]

R/W

ICHG[4]

R/W

ICHG[3]

R/W

ICHG[2]

R/W

ICHG[1]

R/W

ICHG[0]

R/W

BCOLD

R/W

FORCE_20PCT

R/W

LEGEND: R/W = Read/Write

Table 10. Charge Current Control Register REG02 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Fast Charge Current Limit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

BCOLD

R/W

0

1

0

2048 mA

1024 mA

512 mA

256 mA

128 mA

64 mA

Offset: 512 mA

Range: 512 – 3008 mA (000000 –

100111)

Default: 2048 mA (011000)

Note: ICHG higher than 3008mA is

not supported

Set Boost Mode temperature monitor

threshold voltage to disable boost mode

0 – V_bcold0(Typ. 76% of REGN or -10°C

w/ 103AT thermistor )

Default: V_bcold0(0)

1 – V_bcold1(Typ. 79% of REGN or -20°C

w/ 103AT thermistor)

Bit 0

FORCE_20PCT R/W

0

0 – ICHG as Fast Charge Current

(REG02[7:2]) and IPRECH as Pre-

Charge Current (REG03[7:4])

programmed

Default: ICHG as Fast Charge

Current (REG02[7:2]) and IPRECH

as Pre-Charge Current (REG03[7:4])

programmed (0)

1 – ICHG as 20% Fast Charge Current

(REG02[7:2]) and IPRECH as 50% Pre-

Charge Current (REG03[7:4])

programmed

9.6.1.4 Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]

Figure 32. Pre-Charge/Termination Current Control Register REG03 Format

7

6

5

4

3

2

1

0

IPRECHG[3]

R/W

IPRECHG[2]

R/W

IPRECHG[1]

R/W

IPRECHG[0]

R/W

ITERM[3]

R/W

ITERM[2]

R/W

ITERM[1]

R/W

ITERM[0]

R/W

LEGEND: R/W = Read/Write

Table 11. Pre-Charge/Termination Current Control Register REG03 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Pre-Charge Current Limit

Bit 7

Bit 6

Bit 5

Bit 4

IPRECHG[3]

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

R/W

0

1

1024 mA

512 mA

256 mA

128 mA

Offset: 128 mA,

Range: 128 mA – 2048 mA

Default: 256 mA (0001)

Termination Current Limit

Bit 3

Bit 2

Bit 1

Bit 0

ITERM[3]

ITERM[2]

ITERM[1]

ITERM[0]

R/W

0

1

1024 mA

512 mA

256 mA

128 mA

Offset: 128 mA

Range: 128 mA – 2048 mA

Default: 256 mA (0001)

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9.6.1.5 Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]

Figure 33. Charge Voltage Control Register REG04 Format

7

6

5

4

3

2

1

0

VREG[5]

R/W

VREG[4]

R/W

VREG[3]

R/W

VREG[2]

R/W

VREG[1]

R/W

VREG[0]

R/W

BATLOWV

R/W

VRECHG

R/W

LEGEND: R/W = Read/Write

Table 12. Charge Voltage Control Register REG04 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Charge Voltage Limit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

VREG[5]

VREG[4]

VREG[3]

VREG[2]

VREG[1]

VREG[0]

BATLOWV

R/W

1

0

1

512 mV

Offset: 3.504 V

Range: 3.504 V – 4.400 V

Default: 4.208 V

256 mV

128 mV

64 mV

32 mV

16 mV

0 – 2.8 V, 1 – 3.0 V

Default: 3.0 V (1) (pre-charge to fast charge)

Default: 100 mV (0)

Battery Recharge Threshold (below battery regulation voltage)

Bit 0 VRECHG R/W 0 – 100 mV, 1 – 300 mV

0

9.6.1.6 Charge Termination/Timer Control Register REG05 [reset = 10011010, or 0x9A]

Figure 34. Charge Termination/Timer Control Register REG05 Format

7

6

5

4

3

2

1

0

EN_TERM

R/W

Reserved

R/W

WATCHDOG[1] WATCHDOG[0]

R/W R/W

EN_TIMER

R/W

CHG_TIMER[1] CHG_TIMER[0]

R/W R/W

Reserved

R/W

LEGEND: R/W = Read/Write

Table 13. Charge Termination/Timer Control Register REG05 Field Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

NOTE

Charging Termination Enable

Bit 7

Bit 6

EN_TERM

Reserved

R/W

1

0

0 – Disable, 1 – Enable

0 - Reserved

Default: Enable termination (1)

I2C Watchdog Timer Setting

Bit 5

Bit 4

WATCHDOG[1] R/W

WATCHDOG[0] R/W

0

1

00 – Disable timer, 01 – 40 s, 10 –

80 s, 11 – 160 s

Default: 40 s (01)

Default: Enable (1)

Charging Safety Timer Enable

Bit 3 EN_TIMER R/W

Fast Charge Timer Setting

1

0 – Disable, 1 – Enable

Bit 2

Bit 1

Bit 0

CHG_TIMER[1] R/W

CHG_TIMER[0] R/W

0

1

0

00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, Default: 12 hrs (10)

11 – 20 hrs

(See Charging Safety Timer for details)

Reserved

R/W

0 - Reserved

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9.6.1.7 Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]

Figure 35. Boost Voltage/Thermal Regulation Control Register REG06 Format

7

6

5

4

3

2

1

0

BOOSTV[3]

R/W

BOOSTV[2]

R/W

BOOSTV[1]

R/W

BOOSTV[0]

R/W

BHOT[1]

R/W

BHOT[0]

R/W

TREG[1]

R/W

TREG[0]

R/W

LEGEND: R/W = Read/Write

Table 14. Boost Voltage/Thermal Regulation Control Register REG06 Field Description

BIT

FIELD

TYPE

R/W

RESET

DESCRIPTION

512 mV

NOTE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

BOOSTV[3]

BOOSTV[2]

BOOSTV[1]

BOOSTV[0]

BHOT[1]

0

1

0

Offset: 4.55 V

Range: 4.55 V – 5.51 V

Default:4.998 V (0111)

256 mV

128 mV

64 mV

Set Boost Mode temperature monitor Default: V_bhot1(00)

threshold voltage to disable boost

mode

Voltage to disable boost mode

00 – V_bhot1(33% of REGN or 55°C

w/ 103AT thermistor)

Note: For BHOT[1:0] = 11, boost mode

operates without temperature monitor

and the NTC_FAULT is generated based

on V_bhot1threshold

BHOT[0]

01 – V_bhot0(36% of REGN or 60°C

w/ 103AT thermistor)

10 – V_bhot2(30% of REGN or 65°C

w/ 103AT thermistor)

11 – Disable boost mode thermal

protection.

Thermal Regulation Threshold

Bit 1

Bit 0

TREG[1]

TREG[0]

R/W

1

00 – 60°C, 01 – 80°C, 10 – 100°C,

11 – 120°C

Default: 120°C (11)

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9.6.1.8 Misc Operation Control Register REG07 [reset = 01001011, or 4B]

Figure 36. Misc Operation Control Register REG07 Format

7

6

5

4

3

2

1

0

DPDM_EN

R/W

TMR2X_EN

R/W

BATFET_Disable

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

INT_MASK[1]

R/W

INT_MASK[0]

R/W

LEGEND: R/W = Read/Write

Table 15. Misc Operation Control Register REG07 Field Description

BIT

Force DPDM detection

Bit 7 DPDM_EN

FIELD

TYPE

RESET

DESCRIPTION

NOTE

R/W

0

0 – Not in D+/D– detection;

1 – Force D+/D– detection when

VBUS power is presence

Default: Not in D+/D– detection (0), Back to 0

after detection complete

Safety Timer Setting during Input DPM and Thermal Regulation

Bit 6

TMR2X_EN

R/W

1

0 – Safety timer not slowed by 2X

during input DPM or thermal

regulation,

Default: Safety timer slowed by 2X (1)

1 – Safety timer slowed by 2X

during input DPM or thermal

regulation

Force BATFET Off

Bit 5

BATFET_Disable R/W

0

0 – Allow BATFET (Q4) turn on,

1 – Turn off BATFET (Q4)

Default: Allow BATFET (Q4) turn on(0)

Bit 4

Bit 3

Bit 2

Bit 1

Reserved

R/W

0

1

0

1

0 - Reserved

1 - Reserved

0 - Reserved

Reserved

INT_MASK[1]

0 – No INT during CHRG_FAULT, Default: INT on CHRG_FAULT (1)

1 – INT on CHRG_FAULT

Bit 0

INT_MASK[0]

R/W

1

0 – No INT during BAT_FAULT,

1 – INT on BAT_FAULT

Default: INT on BAT_FAULT (1)

9.6.1.9 System Status Register REG08

Figure 37. System Status Register REG08 Format

7

6

5

4

3

DPM_STAT

R

2

PG_STAT

R

1

0

VSYS_STAT

R

VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0]

THERM_STAT

R

LEGEND: R = Read only

Table 16. System Status Register REG08 Field Description

BIT

FIELD

TYPE

DESCRIPTION

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VBUS_STAT[1]

VBUS_STAT[0]

CHRG_STAT[1]

CHRG_STAT[0]

DPM_STAT

R

00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 –

OTG

00 – Not Charging, 01 – Pre-charge (<V_BATLOWV), 10 – Fast Charging, 11 – Charge Termination

Done

0 – Not DPM, 1 – VINDPM or IINDPM

0 – Not Power Good, 1 – Power Good

0 – Normal, 1 – In Thermal Regulation

PG_STAT

THERM_STAT

VSYS_STAT

0 – Not in VSYSMIN regulation (BAT > VSYSMIN), 1 – In VSYSMIN regulation (BAT <

VSYSMIN)

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9.6.1.10 New Fault Register REG09

Figure 38. New Fault Register REG09 Format

7

6

5

4

3

2

Reserved

R

1

0

WATCHDOG

_FAULT

OTG_FAULT CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT

NTC_FAULT[1]

R

NTC_FAULT[0]

R

LEGEND: R = Read only

Table 17. New Fault Register REG09 Field Description^(1)(2)(3)

BIT

FIELD

TYPE

DESCRIPTION

Bit 7

Bit 6

WATCHDOG_FAULT

OTG_FAULT

R

0 – Normal, 1- Watchdog timer expiration

0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any

conditions that cannot start boost function)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

CHRG_FAULT[1]

CHRG_FAULT[0]

BAT_FAULT

R

00 – Normal, 01 – Input fault (OVP or bad source), 10 - Thermal shutdown,

11 – Charge Timer Expiration

0 – Normal, 1 – Battery OVP

Reserved – 0

Reserved

NTC_FAULT[1]

0-Normal 1–Cold Note: Cold temperature threshold is different based on device operates in

buck or boost mode

Bit 0

NTC_FAULT[0]

R

0-Normal 1–Hot Note: Hot temperature threshold is different based on device operates in

buck or boost mode

(1) REG09 only supports single byte I²C read.

(2) All register bits in REG09 are latched fault. First time read of REG09 clears the previous fault and second read updates fault register to

any fault that still presents.

(3) When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] is set to 01 once.

9.6.1.11 Vender / Part / Revision Status Register REG0A

Figure 39. Vender / Part / Revision Status Register REG0A Format

7

PN[2]

R

6

PN[1]

R

5

PN[0]

R

4

Reserved

R

3

Reserved

R

2

Rev[2]

R

1

Rev[1]

R

0

Rev[0]

R

LEGEND: R = Read only

Table 18. Vender / Part / Revision Status Register REG0A Field Description

BIT

FIELD

PN[2]

TYPE

R

DESCRIPTION

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

001 (bq24296)

011 (bq24297)

PN[1]

R

PN[0]

R

Reserved

Rev[2]

Rev[1]

Rev[0]

R

0 – Reserved

000

R

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The bq24296 and bq24297 evaluation module (EVM) PWR021 is a complete charger module for evaluating the

bq24296 and bq24297. The application curves were taken using the bq24296/297 VM-021. Refer to the Related

Links section.

10.2 Typical Application

bq24296

1μH

SYS: 3.5V-4.35V

5V USB

SDP/DCP

SW

VBUS

10μF

1μF

PMID

47nF

μF

8.2

BOOT

REGN

317W (1.5A max)

4.7μF

ILIM

SYS

PGND

2.2kW

SYS

BAT

PG

STAT

VREF

10μF

10kW

4.2V

Optional

QON

SDA

SCL

INT

Host

PHY

REGN

5.25kW

OTG

CE

TS

31.23kW

10kW

Charge Enable (0°C - 45°C)

PSEL

Power Pad

Figure 40. bq24296 with PSEL from PHY, Charging from SDP/DCP, and Optional BATFET Enable

Interface

40

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Typical Application (continued)

bq24297

1μH

SYS: 3.5V-4.35V

5V USB SDP/DCP

SW

VBUS

10μF

1μF

PMID

47nF

8.2μF

BTST

USB

D+

REGN

4.7μF

D–

SYS

PGND

2.2kW

SYS

BAT

STAT

ILIM

(1.5A max)

317W

10kW

10μF

VREF

4.2V

QON

Optional

10kW

REGN

5.25kW

SDA

SCL

INT

Host

TS

OTG

CE

31.23kW

10kW

Charge Enable (0°C - 45°C)

Power Pad

Figure 41. bq24297 with USB D+/D- Detection, USB On-The-Go (OTG) and Optional BATFET Enable

Interface

10.2.1 Design Requirements

Table 19. Design Requirements

DESIGN PARAMATER

Input voltage range

EXAMPLE VALUE

3.9 V to 6.2 V

3000 mA

Input current limit

Fast charge current

3000 mA

Boost mode output current

1.5 A

10.2.2 Detailed Design Procedure

10.2.2.1 Inductor Selection

The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The

Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I_SAT³ I_CHG

+ 1/ 2 I

( )

RIPPLE

(4)

The inductor ripple current depends on input voltage (VBUS), duty cycle (D = V_BAT/V_VBUS), switching frequency

(fs) and inductance (L):

V ´D´(1- D)

IN

I_RIPPLE

=

¦s´L

(5)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in

the range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a

practical design.

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10.2.2.2 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at

50% duty cycle, then the worst case capacitor RMS current I_CINoccurs where the duty cycle is closest to 50%

and can be estimated by the following equation:

I_CIN= I_CHG´ D´(1- D)

(6)

For best performance, VBUS should be decouple to PGND with 1-μF capacitance. The remaining input capacitor

should be place on PMID.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25-V rating or higher capacitor is preferred

for 15-V input voltage. 22-μF capacitance is suggested for typical of 3-A to 4-A charging current.

10.2.2.3 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current I_COUTis given:

I_RIPPLE

I_COUT

=

» 0.29´I_RIPPLE

2´ 3

(7)

The output capacitor voltage ripple can be calculated as follows:

æ

ç

ö

÷

V_OUT

DV_O

=

1-

8LC¦s²

ç

÷

V

IN

è

ø

(8)

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC.

The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the

output inductor and output capacitor should be designed between 15 kHz and 25 kHz. The preferred ceramic

capacitor is 6 V or higher rating, X7R or X5R.

42

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

10.2.3 Application Performance Plots

VBUS

5V/div

VBUS

5V/div

REGN

5V/div

REGN

5V/div

SYS

2V/div

SYS

2V/div

IVBUS

100mA/div

IBAT

2A/div

100ms/div

VBAT = 3.2 V

Figure 42. bq24296 Power Up with Charge Enabled

Figure 43. bq24297 Power Up with Charge Enabled

STAT

VBUS

5V/div

2V/div

CE

REGN

5V/div

2V/div

SW

5V/div

SYS

2V/div

IBAT

1A/div

2A/div

200ms/div

100ms/div

VBAT = 3.2 V

VBAT = 5 V

Figure 44. bq24297 Power Up with Charge Disabled

Figure 45. Charge Enable

STAT

2V/div

CE

5V/div

IL

1A/div

SW

5V/div

SW

IBAT

2V/div

1A/div

4ms/div

400ns/div

VBUS = 5 V, No Battery, ISYS = 40 mA, Charge Disable

Figure 47. PWM Switching in Buck Mode

Figure 46. Charge Disable

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SYS3p5

500mV/div

SYS3p7

100mV/div

ISYS

2A/div

SW

2V/div

IL

1A/div

IVBUS

2A/div

4ms/div

2ms/div

VBUS = 5 V, IIN = 3 A, No Battery, Charge Disable

VBUS = 5 V, VBAT = 3.6 V, ICHG = 2.5 A

Figure 49. Input Current DPM Response without Battery

Figure 48. PFM Switching in Buck Mode

SYS3p8

500mV/div

ISYS

2A/div

SW

2V/div

IBAT

2A/div

IVBUS

2A/div

IL

1A/div

20ms/div

400ns/div

VBUS = 5 V, IIN = 1.5 A, VBAT = 3.8 V

VBAT = 3.8 V, ILOAD = 1 A

Figure 50. Load Transient During Supplement Mode

Figure 51. Boost Mode Switching

VBUS

200mV/div

IBAT

1A/div

IVBUS

1A/div

4ms/div

VBAT = 3.8 V

Figure 52. Boost Mode Load Transient

44

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SLUSBP6B –SEPTEMBER 2013–REVISED NOVEMBER 2014

11 Power Supply Recommendations

In order to provide an output voltage on SYS, the bq24296/297 require a power supply between 3.9 V and 6.2 V

input with at least 100-mA current rating connected to V_BUS; or, a single-cell Li-Ion battery with voltage >

V_BATUVLOconnected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of

the charger to provide maximum output power to SYS.

12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Figure 53) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper

layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper

trace connection or GND plane.

2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not

use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other

trace or plane.

3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground

with a short copper trace connection or GND plane.

4. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using thermal pad as the single ground

connection point. Or using a 0Ω resistor to tie analog ground to power ground.

5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.

Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the VQFN

information, refer to SCBA017 and SLUA271.

Figure 53. High Frequency Current Path

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12.2 Layout Example

C_REGN

C_BTST

R_BTST

C_PMID

PGND

Top layer

PGND

VBUS

L

2^ndlayer (PGND)

via

PGND

C_SYS

PIN1

VSYS

VBAT

PGND

PGND on

Top layer

PGND

C_BAT

PGND

Figure 54. Layout Example

46

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

bq24296/7 EVM (PWR021) User’s Guide (SLUUAQ1)

Quad Flatpack No-Lead Logic Packages Application Report (SCBA017)

QFN/SON PCB Attachment Application Report (SLUA271)

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 20. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

bq24296

bq24297

Click here

13.3 Trademarks

All trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24296RGER

BQ24296RGET

BQ24297RGER

BQ24297RGET

VQFN

RGE

24

3000

250

330.0

180.0

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24296RGER

BQ24296RGET

BQ24297RGER

BQ24297RGET

VQFN

RGE

24

3000

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

35.0

3000

250

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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型号：	BQ24297_15
厂家：	TEXAS INSTRUMENTS
描述：	bq2429x I2C Controlled 3-A Single Cell USB Charger With Narrow VDC Power Path Management and Adjustable Voltage USB OTG
文件：	总55页 (文件大小：1554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24297_15 [TI]

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