BQ24350DSGR [TI]
Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET; 过压和过流充电器前端保护IC，具有集成FET充电
| 型号： | BQ24350DSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET |
| 文件： | 总17页 (文件大小：1496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24350
bq24352
www.ti.com ............................................................................................................................................................... SLUS943A–MAY 2009–REVISED JUNE 2009
Over-Voltage and Over-Current Charger Front-end
Protection IC With Integrated Charging FET
1
FEATURES
•
•
•
•
•
Soft-Start to Prevent Inrush Currents
Soft-Stop to Prevent Voltage Spikes
30V Maximum Input Voltage
2
•
Robust Protection
–
–
–
–
–
Input Over-Voltage Protection
Input Over-Current Protection
Accurate Battery Over-Voltage Protection
Thermal Shutdown
Supports Up to 1A Load Current
Small 2mm × 2mm 8pin SON Package
APPLICATIONS
•
•
Output Short-Circuit Protection
Mobile Phones
Low-Power Handheld Devices
•
•
•
Integrated Charging FET
LDO Mode Operation
Current Limited Power Supply for Host
Controller
DESCRIPTION
The bq24350/2 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the
charging circuit. The IC continuously monitors the input voltage and the battery voltage. In case of an input
over-voltage condition, the IC will turn off the internal power FET after a blanking time. If the battery voltage rises
to unsafe levels during charging process, power is removed from the system. If the input current exceeds the
over current threshold for a limited time, the IC will turn off the output power. The integrated charging FET can
regulate the charge voltage and current according to the control from the host. The device can also provide a
voltage source with over voltage and over current protection for host controller.
WHITE SPACE
WHITE SPACE
WHITE SPACE
TYPICAL APPLICATION CIRCUIT
PIN ASSIGNMENT
WHITE SPACE
WHITE SPACE
bq24350/2
CHGIN
BB
1
2
8
7
OUT
OUT
ACIN
ACIN
GND
VBAT
ACIN
AC
CHGIN
C
C
CHGIN
ACIN
Q1
1 mF
1 mF
3
4
6
5
CHGIN
GATDRV
OUT
Q2
GATDRV
ISENS
GATDRV
0 .2 W
R
GND
BAT
VBAT
VBAT
200 kW
PACK+
PACK-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq24350
bq24352
SLUS943A–MAY 2009–REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED FUNCTION BLOCK DIAGRAM
Q 2
Q 1
V
V
OUT
ACIN
ACIN
OUT
IIN
Protection &
+
-
Gate Control
IO(OCP)
INPUT UVLO
tBLK ( CHGIN)
V
+
-
ACIN
V
UVLO
V
CHGIN
+
-
INPUT OVP
tDGL(OVP )
GND
CHGIN
V
+
-
ACIN
V
OREG
500 W
Control
L ogic
V
OVP
CHGIN Discharge
V
+
-
ACIN
SLEEP
VOUT
Battery OVP
tDGL (BOVP )
Protection
Control
VBAT
+
-
BV
OVP
GATDRV
VBAT
Thermal
Shutdown
V
BAT
PIN FUNCTIONS
PIN
NAME
NUMBER
I/O DESCRIPTION
ACIN
1,2
I
Power Supply Input, connect to an external DC supply. Connect an external 1µF ceramic capacitor
(minimum) to GND.
OUT
7,8
4
O
I
Output terminal to the charging system.
VBAT
Battery voltage sense input. Connected to pack positive terminal through a resistor. Connected to
ground if battery OVP function is not used.
GATDRV
CHGIN
5
6
I
P-FET gate drive input , connected to gate drive pin of the host charger controller
O
Output power pin for power input of host charger controller. Connect an external ceramic bypass
capacitor (1.0µF minimum) to GND.
GND
3
–
Ground terminal
Thermal PAD
There is an internal electrical connection between the exposed thermal pad and the GND pin of the
device. The thermal pad must be connected to the same potential as the GND pin on the printed circuit
board. Do not use the thermal pad as the primary ground input for the device. GND pin must be
connected to ground at all times.
ORDERING INFORMATION
INPUT OVP
THRESHOLD
PART NUMBER
MARKING
MEDIUM
QUANTITY
PACKAGE
bq24350DSGR
bq24350DSGT
bq24352DSGR
bq24352DSGT
OAJ
OAJ
OCY
OCY
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
3000
250
2mm × 2mm SON
2mm × 2mm SON
2mm × 2mm SON
2mm × 2mm SON
6.17 V
6.17 V
3000
250
7.1 V
7.1 V
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
www.ti.com ............................................................................................................................................................... SLUS943A–MAY 2009–REVISED JUNE 2009
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
Input voltage
Output voltage
Input voltage
Input current
ACIN (with respect to GND)
OUT, CHGIN (with respect to GND)
VBAT, GATDRV (with respect to GND)
ACIN
–0.3 V to 30 V
–0.3 V to 7V
–0.3 V to 7 V
–1.8 A(2) to 1.4 A
–40°C to 150°C
–65°C to 150°C
Junction temperature, TJ
Storage temperature, TSTG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) Reverse current is specified for a maximum of 50 hours at TJ < 150°C.
PACKAGE DISSIPATION RATINGS
PACKAGE
PACKAGE DRAWING
RθJC
RθJA
SON-8
DSG
5°C/W
75°C/W
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNITS
VACIN
IACIN
TJ
ACIN voltage range
Current, ACIN pin
4.4
15
V
A
1
Junction Temperature
–40
125
°C
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
SLUS943A–MAY 2009–REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
Refer to the typical application circuit shown in Figure 1 . These specifications apply over ACIN=5V, TJ = -40~125°C, unless
otherwise specified. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
ACIN
ACIN: 3V → 2V, ACIN falling
ACIN: 2V → 3V, ACIN rising
VACIN rising to CHGIN rising
No load on OUT and CHGIN pin
1.8 1.95
2.1
V
VUVLO
Under-voltage lock-out threshold
2.5
10
tBLK(CHGIN) Input power on blanking time
IDD Operating current
ms
500
µA
INPUT TO OUTPUT CHARACTERISTICS
On resistance from ACIN to OUT
IOUT = 1.0A, ACIN=5V, GATDRV=0V
ICHGIN = 1.0A, ACIN=5V, IOUT=0A
415
250
685
495
mΩ
mΩ
On resistance from ACIN to CHGIN
INPUT OVER-VOLTAGE PROTECTION (OVP)
ACIN=5.9V, GATDRV=CHGIN, ICHGIN=0 to
1A.
VOREG
VOVP
CHGIN voltage in LDO mode
5.33
5.5
5.66
V
V
Input OVP threshold, bq24350
Input OVP threshold, bq24352
Input OVP recovery hysteresis, bq24350
Input OVP recovery hysteresis, bq24352
Input OVP deglitch time
6
6.17
7.1
6.35
7.3
VACIN rising
6.9
250 300
100 150
256
350
200
VHYS-OVP
VACIN: 7.5V → 5V
mV
tDGL(OVP)
tREC(OVP)
VACIN rising to CHGIN falling
µS
Input OVP recovery time
VACIN falling below VOVP to CHGIN rising
8.2
ms
INPUT OVER CURRENT LIMITING AND PROTECTION (OCP)
IO(OCP)
OCP threshold
1.02
1.2
8.2
1.38
A
tDGL(OCP)
tREC(OCP)
OCP blanking time
OCP recovery time
ms
ms
131
BATTERY OVER-VOLTAGE PROTECTION
BVOVP Battery OVP threshold
VHYS-BOVP Battery OVP hysteresis
VBAT rising
VBAT falling
4.3 4.35
200 250
4.4
V
300
mV
VBAT=4.25V, series connection of a 200kΩ
resistor, TJ = 25°C
IVBAT
VBAT pin leakage current
10
nA
tDGL(BOVP) Battery OVP deglitch time
tREC(BOVP) Battery OVP recovery time
CHGIN
VBAT rising to CHGIN falling
8.2
ms
ms
VBAT falling below BVOVP to CHGIN rising
131
Sleep mode exit threshold and CHGIN turn
on threshold, ACIN-VOUT
VSEXIT
ACIN rising, VOUT = 4.2 V
ACIN falling, VOUT = 4.2 V
24
10
90
55
160
105
10
mV
mV
Sleep mode entry threshold and CHGIN turn
off threshold, ACIN-VOUT
VSENTRY
OUT = 4.2 V, GATDRV = 4.2 V,
ACIN = VSS
IDDSLP
RDIS
Sleep Mode supply current
µA
Ω
CHGIN discharge resistor
500
OUT = 4.2 V, GATDRV = 4.2 V, CHGIN = 0
V, ACIN = 0 V, TJ = 85°C
Leakage current from OUT to CHGIN
1
µA
INTEGRATED P-FET PARAMETERS
Vt
Threshold Voltage, CHGIN-GATDRV.
CHGIN=5V, OUT=3.6V, IOUT=10mA
500 680
800
1
mV
µA
µA
Ig
GATDRV pin leakage current
0.1
1
Ioff
Off state leakage current at OUT pin.
ACIN=5V, GATDRV=CHGIN, OUT=0V
IOUT = 1.0A, ACIN=5V, GATDRV=0V
On Resistance of P-FET (from CHGIN to
OUT)
Ronp
165
225
mΩ
Gm
Cg
Forward Transconductance
ACIN=5V, IOUT=5mA, GATDRV=3.5V
CHGIN=GATDRV=5V
27
mA/V
pF
Input capacitance at the GATDRV pin
104
THERMAL PROTECTION
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
www.ti.com ............................................................................................................................................................... SLUS943A–MAY 2009–REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS (continued)
Refer to the typical application circuit shown in Figure 1 . These specifications apply over ACIN=5V, TJ = -40~125°C, unless
otherwise specified. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
Junction temperature rising
Junction temperature falling
MIN TYP
140 150
20
MAX UNIT
TJ(OFF)
Thermal shutdown threshold
160
°C
°C
TJ(OFF-HYS) Thermal shutdown hysteresis
TYPICAL APPLICATION CIRCUIT
ACIN=5V, ICHARGE=1A, VBAT=4.2V
bq24350/2
BB
ACIN
CHGIN
AC
CHGIN
C
C
ACIN
Q1
CHGIN
1 mF
1 mF
GATDRV
OUT
Q2
GATDRV
ISENS
0.2 W
R
GND
BAT
VBAT
VBAT
200 kW
PACK+
PACK-
Figure 1. Host Controlled One-Cell Charger Application Circuit
TYPICAL PERFORMANCE CHARACTERISTICS
Using circuit shown in typical application circuit Figure 1, TA = 25°C, unless otherwise specified.
ACIN RAMP UP
ACIN RAMP DOWN
GATDRV 2 V/div
ACIN 2 V/div
CHGIN Pull Down
CHGIN 2 V/div
ACIN 2 V/div
Soft-Start
Soft-Stop
VACIN = 5.2 V, CHGIN = 4.5 V, ICHG = 0.6 A,
VGATDRV = 3.5 V, VBAT = 3.4 V
CHGIN 2 V/div
I
0.5 A/div
ACIN
I
0.5 A/div
ACIN
VACIN = 5.2 V, CHGIN = 4.5 V, ICHG = 0.6 A,
VGATDRV = 3.5 V, VBAT = 3.4 V
Time: 2 mS/div
Time: 1 mS/div
Figure 2.
Figure 3.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
SLUS943A–MAY 2009–REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
ACIN OVP (BLANKING TIME)
ACIN OVP
16 V
16 V
ACIN 5 V/div
5 V
ACIN 5 V/div
5 V
CHGIN 1 V/div
CHGIN 1 V/div
6 V
5.5 V
VACIN = 5-16 V, Rising Time 0.5 ms
VACIN = 5-16 V, Rising Time 0.5 ms
I
0.1 A/div
I
0.1 A/div
CHGIN
CHGIN
Time: 1 ms/div
Figure 5.
Time: 100 ms/div
Figure 4.
ACIN OVP
CHGIN OCP
ACIN 5 V/div
VACIN = 5 V, ICHGIN = 0 to 1.3 A
VACIN = 5-16 V, Rising Time
0.5 ms, ICHGIN 2V/div
CHGIN 2 V/div
CHGIN 2 V/div
1.3 A
I
0.5 A/div
I
0.1 A/div
CHGIN
CHGIN
Time: 20 mS/div
Figure 6.
Time: 100 mS/div
Figure 7.
CHGIN OCP
BATTERY OVP
VBAT 2 V/div
Connect 3 W Load
CHGIN 2 V/div
VACIN = 5 V, ICHGIN = 0 to1.3 A
VACIN = 5 V, VBAT = 3.4 V to 5 V
ICHGIN 0.5 A/div
CHGIN 2 V/div
ICHGIN 0.1 A/div
Time: 2 mS/div
Time: 50 mS/div
Figure 8.
Figure 9.
6
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
www.ti.com ............................................................................................................................................................... SLUS943A–MAY 2009–REVISED JUNE 2009
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
BATTERY OVP
VBAT 2 V/div
Rdson vs Vgs
10000
1000
VACIN = 5 V, VBAT = 3.4 V to 5 V
CHGIN 2 V/div
VCHGIN = 5 V,
V
100
10
1
-V = 200 mV
OUT
CHGIN
IACIN 0.5 A/div
Q2
Time: 2 mS/div
0.1
0
1000
2000
3000
4000
5000
Vgs - Vchgin-Vgatdrv - mV
Figure 10.
Figure 11.
FET ON RESISTANCE vs TEMPERATURE
600
550
500
450
Q1 +Q2
400
350
300
Q1
Q2
250
200
150
100
-50
0
50
100
150
T
- Junction Temperature - °C
J
Figure 12.
BACKGROUND
During the charging process for portable devices, input voltage spikes usually happen when the AC/DC adaptor
is plugged in, or charge current is cut off quickly under fault conditions, such as input OVP, OCP or battery OVP
and so on. The over voltage stress may damage the analog baseband chip which has lower voltage rating due to
its increased complexity. Therefore, over voltage protection is needed for the safe operation of portable devices.
Another challenge arises from the charge circuit that uses external charging FET in series with a reverse
blocking diode as the charging device. The battery may not be fully charged when input voltage is low due to the
additional diode voltage drop. bq24350/2 will provide the solution for above problems since it has input OVP,
OCP, battery OVP function, together with integrated charging FET which will eliminate the reverse blocking diode
in the previously mentioned charge circuit, as shown in Figure 1.
DETAILED FUNCTIONAL DESCRIPTION
The bq24350/2 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the
charging circuit. The IC continuously monitors the input voltage and the battery voltage. In case of an input
over-voltage condition, the IC will turn off the internal power FET after a blanking time. If the battery voltage rises
to unsafe levels during charging process, power is removed from the system. If the input current exceeds the
over current threshold for a limited time, the IC will turn off the output power. The integrated charging FET can
regulate the charge voltage and current according to the control from the host. The device can also provide a
voltage source with over voltage and over current protection for host controller.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
SLUS943A–MAY 2009–REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
POWER DOWN
The device remains in power down mode when the input voltage at the ACIN pin is below the under-voltage
threshold VUVLO. The FET Q1 and Q2 connected between ACIN and OUT pins are off.
POWER-ON RESET
The device resets when the input voltage at the ACIN pin exceeds the UVLO threshold. All internal counters and
other circuit blocks are reset. The IC then waits for duration tBLK(CHGIN) for the input voltage to stabilize. If, after
tBLK(CHGIN), the input voltage and battery voltage are in normal range, FET Q1 is turned ON. The IC has a
soft-start feature to control the inrush current. The soft-start minimizes the ringing at the input, where the ringing
occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant
circuit. Once the soft-start sequence starts, the IC monitors the load current. If the load current is larger than
IO(OCP) for more than tDGL(OCP), FET Q1 and Q2 are switched off. The IC then repeats the power-on sequence
after tREC(OCP)
.
When a short-circuit is detected at power-on and Q1 is switched off, to prevent the input voltage from spiking up
due to resonance between the inductance of the input cable and the input capacitor, Q1 is turned off slowly by
reducing its gate-drive gradually, resulting in a “soft-stop”.
SLEEP MODE
When ACIN falls to below sleep mode entry threshold (VSENTRY), the device operates in sleep mode and turns off
Q1 and Q2 by internal circuit regardless of the gate drive signal from GARDRV pin. The device exits sleep mode
when ACIN rising to above sleep mode exit threshold (VSEXIT). In this way, the device behaves like a diode and
no external reverse blocking diode is needed in the application circuit.
OPERATING
The device continuously monitors the input voltage, the input current and the battery voltage as described in
detail below:
Input Over-Voltage Protection and LDO Mode Operation
The CHGIN output of the IC operates similar to a linear regulator. Figure 13 shows the typical input OVP
performance. When the ACIN input voltage is less than VO(REG), and above the VUVLO, the CHGIN output voltage
tracks the input voltage with a voltage drop caused by RDS(on) of the protection FET Q1. When the ACIN input
voltage is greater than VO(REG) plus the RDS(on) drop of Q1, and less than VOVP, the CHGIN output voltage is
regulated to VO(REG), and this is also referred as LDO mode operation. If the input voltage rises above VOVP, the
internal FET Q1 and Q2 are turned off after a blanking time of tDGL(OVP), removing power from the circuit. When
the input voltage drops below VOVP – VHYS-OVP, and is still above VUVLO, the FET Q1 and Q2 are turned on again
after a deglitch time of tREC(OVP) , which ensures that the input supply is stabilized when the IC starts up again.
V
>V
IN OREG
V
<V
IN OREG
V
OVP
V
POR
ACIN
V
O(REG)
CHGIN
t
t
DGL(OVP)
t
REC(OVP)
BLK(CHGIN)
ACIN OVP
Figure 13. Input OVP Timing Diagram
Over Current Limiting and Protection
The device includes a low drop out linear current regulator. This current regulator uses Q1 as the controlling
8
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
www.ti.com ............................................................................................................................................................... SLUS943A–MAY 2009–REVISED JUNE 2009
power device. Once the soft start sequence starts, the input current is limited to the Over Current Protection
(OCP) threshold, IO(OCP). If the input current through the IC attempts to exceed the OCP threshold, the switch Q1
is opened only enough to maintain the current at the OCP level. If the current limiting condition is maintained
longer than the deglitch time, tDGL(OCP), both the switch Q1 and Q2 are opened completely, as shown in
Figure 14. In this fault case, the switch Q1 is turned off slowly, typically taking 100µS.
Once the OCP feature has been activated, the switch Q1 and Q2 will remain off for the OCP recovery time,
tREC(OCP). Following this time the switch will turn on, using soft start sequence. If the current through the IC
remains below the OCP threshold, the switch will remain closed and normal operation resumes. If the current
through the IC attempts to exceed the OCP threshold again, the operation described above repeats.
IACIN
OCP
Threshold
CHGIN
t
t
REC(OCP)
REC(OCP)
t
t
DGL(OCP)
DGL(OCP)
Figure 14. Charge Current OCP Timing Diagram
Battery Over-Voltage Protection
The battery over-voltage threshold, BVOVP, is internally set to 4.35V. If the battery voltage exceeds the BVOVP
threshold, the FET Q1 and Q2 are turned off after a deglitch time of tDGL(BOVP). The FET is turned on once the
battery voltage drops to BVOVP – VHYS-BOVP and remains below this threshold for tREC(BOVP), as shown in
Figure 15. In this battery over-voltage fault case, Q1 is switched OFF gradually for a smooth transient response.
V
BAT
VBAT
OVP
CHGIN
t
REC(BOVP)
t
t
t
DGL(BOVP)
REC(BOVP)
DGL(BOVP)
Figure 15. Battery OVP Timing Diagram
Thermal Protection
If the junction temperature of the device exceeds TJ(OFF), the FET Q1 and Q2 are turned off. The FET is turned
back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS)
.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): bq24350 bq24352
bq24350
bq24352
SLUS943A–MAY 2009–REVISED JUNE 2009 ............................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
Selection of RBAT
It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some
failure modes of the IC, the voltage at the ACIN pin may appear on the VBAT pin. This voltage can be as high as
30V, and applying 30V to the battery in case of the failure of the device can be hazardous. Connecting the VBAT
pin through RBAT prevents a large current from flowing into the battery in case of failure of the IC. In the interests
of safety, RBAT should have a very high value. The problem with a large RBAT is that the voltage drop across this
resistor because of the VBAT bias current IVBAT causes an error in the BVOVP threshold. This error is over and
above the tolerance on the nominal 4.35V BVOVP threshold.
Choosing RBAT in the range 100kΩ to 470kΩ is a good compromise. In the case of IC failure, with RBAT equal to
100kΩ, the maximum current flowing into the battery would be (30V – 3V) ÷ 100kΩ = 270µA, which is low
enough to be absorbed by the bias currents of the system components. RBAT equal to 100kΩ would result in a
worst-case voltage drop of RBAT × IVBAT ≈ 1mV. This is negligible compared to the internal tolerance of 50mV on
the BVOVP threshold.
If the Battery OVP function is not required, the VBAT pin should be connected to GND.
Selection of Input and Output Bypass Capacitors
The input capacitor CACIN is for decoupling, and serves an important purpose. Whenever there is a step change
downwards in the system load current, the inductance of the input cable causes the input voltage to spike up.
CACIN prevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a
ceramic capacitor of at least 1µF be used at the input of the device. It should be located in close proximity to the
ACIN pin.
CCHGIN should also be a ceramic capacitor of at least 1µF, located close to the CHGIN pin. CCHGIN also serves as
the input decoupling capacitor for the charging circuit downstream of the protection IC.
PCB Layout Guidelines
1. This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages.
Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of
PCB traces satisfy the design rules for the maximum voltages expected to be seen in the system.
2. The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should
be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly
under the IC. This copper pad should be connected to the ground plane with an array of thermal vias.
3. CACIN and CCHGIN should be located close to the IC. Other components like RBAT should also be located close
to the IC.
10
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24350 bq24352
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2009
PACKAGING INFORMATION
Orderable Device
BQ24350DSGR
BQ24350DSGT
BQ24352DSGR
BQ24352DSGT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DSG
8
8
8
8
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
SON
SON
DSG
DSG
DSG
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
BQ24350DSGR
BQ24350DSGT
BQ24352DSGR
BQ24352DSGT
SON
SON
SON
SON
DSG
DSG
DSG
DSG
8
8
8
8
3000
250
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24350DSGR
BQ24350DSGT
BQ24352DSGR
BQ24352DSGT
SON
SON
SON
SON
DSG
DSG
DSG
DSG
8
8
8
8
3000
250
195.0
195.0
195.0
195.0
200.0
200.0
200.0
200.0
45.0
45.0
45.0
45.0
3000
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
相关型号：
BQ24350DSGT
Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET
TI
BQ24352
Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET
TI
BQ24352DSGR
Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET
TI
BQ24352DSGT
Over-Voltage and Over-Current Charger Front-end Protection IC With Integrated Charging FET
TI
BQ24380
Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC With LDO Mode
TI
BQ24380DSGR
Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC With LDO Mode
TI
BQ24380DSGRG4
Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC With LDO Mode
TI
BQ24380DSGT
Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC With LDO Mode
TI
BQ24380DSGTG4
Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC With LDO Mode
TI
©2020 ICPDF网 联系我们和版权申明