BQ24620_技术文档

bq24620

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SLUS893 –MARCH 2010

Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with Low I_q

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1

FEATURES

APPLICATIONS

•

Power Tool and Portable Equipment

Personal Digital Assistants

Handheld Terminals

Industrial and Medical Equipment

Netbook, Mobile Internet Device and

Ultra-Mobile PC

•

300 kHz NMOS-NMOS Synchronous Buck

Converter

Stand-alone Charger Designed Specifically for

Lithium Phosphate

5V–28V VCC Operating Range, Support 1-7

Battery Cells

High-Accuracy Voltage and Current Regulation

DESCRIPTION

–

±0.5% Charge Voltage Accuracy

±3% Charge Current Accuracy

The bq24620 is highly integrated switch-mode battery

charge controller designed specifically for Lithium

Phosphate battery. It offers a constant-frequency

synchronous PWM controller with high accuracy

•

Integration

–

Internal Loop Compensation

Internal Soft Start

current

and

voltage

regulation,

charge

preconditioning, termination, and charge status

monitoring.

Safety

–

Input Over-Voltage Protection

The bq24620 charges the battery in three phases:

preconditioning, constant current, and constant

voltage. Charge is terminated when the current

reaches a minimum level. An internal charge timer

provides a safety backup. The bq24620 automatically

restarts the charge cycle if the battery voltage falls

below an internal threshold, and enters

low-quiescent current sleep mode when the input

voltage falls below the battery voltage.

Battery Thermistor Sense Suspend Charge

at Hot/Cold Charge Suspend and

Automatically I_CHARGE/8 at WARM/COOL

–

Battery Detection

Built-in Safety Timer

a

Charge Over-Current Protection

Battery Short Protection

Battery Over-Voltage Protection

Thermal Shutdown

PACKAGE

•

Status Outputs

–

Adapter Present

16

15

14

13

Charger Operation Status

•

Charge Enable Pin

12

11

10

1

2

3

REGN

GND

SRP

VCC

6V Gate Drive for Synchronous Buck

Converter

OAR

(bq24620)

•

30ns Driver Dead-time and 99.95% Max

Effective Duty Cycle

CE

QFN-16

TOP VIEW

STAT

•

16-Pin 3.5×3.5-mm QFN Package

Energy Star Low Iq

–

< 15 mA Off-State Battery Discharge Current

4

9

TS

SRN

< 1.5 mA Off-State Input Quiescent Current

5

6

7

8

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24620

SLUS893 –MARCH 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TYPICAL APPLICATION

ADAPTER +

ADAPTER -

R11

2 W

C9

10 µF

C8

10 µF

D2

R6

10 W

MBRS540T3

C2

2.2 µF

Q4

SiR426

VREF

HIDRV

VCC

N

C7

1 µF

R7

100 kW

RSR

PH

L1

0.010 Ω

VBAT

PACK+

PACK-

BTST

ISET

VREF

CE

C6

0.1 µF

8.2 µH*

D1

R8

22.1 kW

BAT54

REGN

C5

C13

10 µF*

C12

10 µF*

C4

1 µF

Q5

SiR426

1 µF

LODRV

GND

bq24620

N

R13 10 kW

R2

900 kW

Cff

D3

D4

STAT

PG

ADAPTER +

22 pF

C10

0.1 µF

C11

0.1 µF

R14 10 kW

SRP

SRN

R1

100 kW

VREF

R5

R9

9.31 kW

Pack

Thermistor

Sense

100 W

TS

VFB

PwrPad

0.1 μF

R10

430 kW

NOTE: VIN=28V, BAT=5-cell Li-Phosphate, I_charge=3A, I_pre-charge=0.125A, I_term=0.3A

Figure 1. Typical System Schematic

ORDERING INFORMATION

PART NUMBER

PACKAGE

ORDERING NUMBER

(Tape and Reel)

QUANTITY

IC MARKING

bq24620

16-Pin 3.5×3.5 mm QFN

bq24620RVAR

bq24620RVAT

3000

250

OAR

PACKAGE THERMAL DATA⁽¹⁾

PACKAGE

q_JP

q_JA

T_A= 25°C

POWER RATING

DERATING FACTOR

ABOVE T_A= 25°C

(2)

QFN – RVA

4.0°C/W

43.8°C/W

2.28W

0.0228 W/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×2 via matrix. q_JAhas 5% improvement by 3x3 via matrix.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

2

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ABSOLUTE MAXIMUM RATINGS^{(1) (2) (3)}

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

VCC, SRP, SRN, CE, STAT, PG

PH

–0.3 to 33

–2 to 36

V

VFB

Voltage range

–0.3 to 16

–0.3 to 7

V

REGN, LODRV, TS

V

BTST, HIDRV with respect to GND

VREF, ISET

–0.3 to 39

–0.3 to 3.6

–0.5 to 0.5

–40 to 155

–55 to 155

V

Maximum difference voltage

Junction temperature range, T_J

Storage temperature range, T_stg

SRP–SRN

V

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

(3) Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16V. Usually the resistor

divider top resistor will take care of this.

RECOMMENDED OPERATING CONDITIONS

VALUE

–0.3 to 28

–2 to 30

UNIT

V

VCC, SRP, SRN, CE, STAT, PG

PH

V

VFB

–0.3 to 14

–0.3 to 6.5

–0.3 to 34

–0.3 to 3.3

3.3

V

Voltage range

REGN, LODRV, TS

V

BTST, HIDRV with respect to GND

V

ISET

V

VREF

V

Maximum difference voltage SRP–SRN

Junction temperature range

–0.2 to 0.2

0 to 125

V

T_J

°C

T_stg

Storage temperature range

–55 to 155

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ELECTRICAL CHARACTERISTICS

5.0V ≤ V(VCC) ≤ 28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

OPERATING CONDITIONS

V_{VCC_OP}VCC Input voltage operating range

QUIESCENT CURRENTS

Total battery discharge current (sum of

TEST CONDITIONS

MIN

TYP

MAX

UNIT

5.0

28.0

15

V

I_BAT

currents into VCC, BTST, PH, SRP,

V_VCC< V_SRN, V_VCC> V_UVLO(SLEEP)

mA

SRN, VFB), VFB ≤2.1 V

V_VCC> V_SRN, V_VCC> V_UVLOCE = LOW (IC quiescent

current)

1

2

1.5

5

Adapter supply current (current into

VCC pin)

V_VCC> V_SRN, V_VCC>V_VCCLOW, CE = HIGH, charge

done

I_AC

mA

V_VCC> V_SRN, V_VCC>V_VCCLOW, CE = HIGH, Charging,

Qg_total = 20 nC, V_VCC=20V

12

CHARGE VOLTAGE REGULATION

V_FBFeedback regulation voltage

1.8

V

T_J= 0°C to 85°C

T_J= –40°C to 125°C

VFB = 1.8 V

–0.5%

–0.7%

0.5%

0.7%

100

Charge voltage regulation accuracy

I_VFB

Input leakage current into VFB pin

nA

CURRENT REGULATION – FAST CHARGE

V_ISET

ISET voltage range

0

2

V

V_{IREG_CHG}

SRP–SRN current sense voltage range V_{IREG_CHG}= V_SRP– V_SRN

100

mV

Charger current set factor amps of

R_SENSE= 10 mΩ

K_ISET

5

A/V

charge current per volt on ISET pin)

V_{IREG_CHG}= 40 mV

–3%

–4%

3%

4%

V_{IREG_CHG}= 20 mV

Charge current regulation accuracy

V_{IREG_CHG}= 5 mV

–25%

–40%

25%

40%

100

V_{IREG_CHG}= 1.5 mV (V_SRN> 3.1V)

V_ISET= 2 V

I_ISET

Leakage current in to ISET Pin

nA

CURRENT REGULATION – PRECHARGE

Precharge current

R_SENSE= 10 mΩ, VFB < V_LOWV

R_SENSE= 10 mΩ

50

125

200

mA

CHARGE TERMINATION

Termination current range

I_CHARGE/10

0.5

A

Termination current set factor (amps of

termination current per volt on ISET pin)

K_TERM

A/V

V_ITERM= 10 mV

V_ITERM= 5 mV

V_ITERM= 1.5 mV

–10%

–25%

–45%

10%

25%

45%

Termination current accuracy

Deglitch time for termination (both

edge)

100

ms

t_QUAL

I_QUAL

Termination qualification time

V_BAT> V_RECHand I_CHARGE< I_TERM

250

2

ms

Discharge current once termination is detected

mA

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)

V_UVLO

AC under-voltage rising threshold

AC under-voltage hysteresis, falling

Measure on VCC

3.65

3.85

350

4

V

V_{UVLO_HYS}

mV

VCC LOWV COMPARATOR

Falling threshold, disable charge

Rising threshold, resume charge

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)

4.1

V

4.35

4.5

V_{SLEEP _FALL}

V_{SLEEP_HYS}

SLEEP falling threshold

SLEEP hysteresis

V_VCC– V_SRNto enter SLEEP

40

100

500

1

150

mV

µs

SLEEP rising delay

VCC falling below SRN, delay to pull up PG

VCC rising above SRN, delay to pull down PG

VCC falling below SRN, Delay to enter SLEEP mode

SLEEP falling delay

30

ms

SLEEP rising shutdown deglitch

100

4

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤ 28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC rising above SRN, Delay to come out of SLEEP

mode

SLEEP falling powerup deglitch

30

ms

BAT LOWV COMPARATOR

LOWV rising threshold (Precharge to

Fast Charge)

V_LOWV

Measured on VFB pin

0.333

0.35

0.367

V

V_{LOWV_HYS}

LOWV hysteresis

100

25

mV

ms

LOWV rising deglitch

LOWV falling deglitch

VFB falling below V_LOWV

VFB rising above V_LOWV+ V_{LOWV_HYS}

25

RECHARGE COMPARATOR

Recharge threshold (with respect to

V_RECHG

Measured on VFB pin

110

125

140

mV

V_REG

)

Recharge rising deglitch

Recharge falling deglitch

VFB decreasing below V_RECHG

VFB increasing above V_RECHG

10

ms

BAT OVER-VOLTAGE COMPARATOR

V_{OV_RISE}

V_{OV_FALL}

Over-voltage rising threshold

Over-voltage falling threshold

As percentage of V_FB

108%

105%

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

AC over-voltage rising threshold on

VCC

V_ACOV

V_{ACOV_HYS}

31.04

32

32.96

V

AC over-voltage falling hysteresis

AC Over-Voltage Rising Deglitch

AC Over-Voltage Falling Deglitch

1000

mV

ms

Delay to changing the STAT pins

1

THERMAL SHUTDOWN COMPARATOR

T_SHUT

Thermal shutdown rising temperature

Temperature increasing

145

15

°C

ms

Thermal shutdown hysteresis

Thermal shutdown rising deglitch

Thermal shutdown falling deglitch

T_{SHUT_HYS}

Temperature increasing

Temperature decreasing

100

10

ms

THERMISTOR COMPARATOR

V_LTF

Cold temperature rising threshold

Charger suspended below this temperature

72.5%

0.2%

73.5%

0.4%

74.5%

0.6%

V_{LTF_HYS}

Cold temperature hysteresis

Charger enabled, cuts back to I_CHARGE/8 below this

temperature

V_COOL

Cool Temperature rising threshold

Cool temperature hysteresis

70.2%

0.2%

70.7%

0.6%

48%

71.2%

1.0%

V_{COOL_HYS}

V_WARM

V_{WARM_HYS}

V_HTF

Charger cuts back to I_CHARGE/8 above this

temperature

Warm temperature rising threshold

Warm temperature hysteresis

Hot temperature rising threshold

47.5%

1.0%

48.5%

1.4%

1.2%

37%

Charger suspended above this temperature before

initiating charge

36.2%

37.8%

Charger suspended above this temperature during

initiating charge

V_TCO

Cut-off temperature rising threshold

33.7%

34.4%

400

35.1%

Deglitch time for Temperature Out of

Range Detection

V_TS> V_LTF, or V_TS< V_TCO, or V_TS< V_HTF

ms

Deglitch time for Temperature in Valid

Range Detection

V_TS< V_LTF– V_{LTF_HYS}or V_TS>V_TCO, or V_TS> V_HTF

20

Deglitch time for current reduction to

I_CHARGE/8 due to warm or cool

temperature

V_TS> V_COOL, or V_TS< V_WARM

25

ms

Deglitch time to charge at I_CHARGEfrom

I_CHARGE/8 when resuming from warm or

cool temperatures

V_TS< V_COOL- V_{COOL_HYS}, or V_TS> V_WARM

V_{WARM_HYS}

-

25

Charge current due to warm or cool

temperatures

V_COOL< V_TS< V_LTF, or V_WARM< V_TS< V_HTF, or

V_WARM< V_TS< V_TCO

I_CHARGE/8

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤ 28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

Current rising, in non-synchronous mode, measure

on V_(SRP-SRN), V_SRP< 2 V

45.5

160%

50

mV

Charge over-current falling threshold

Current rising, as percentage of V_{(IREG_CHG)}, in

synchronous mode, V_SRP> 2.2V

V_OC

Minimum OCP threshold in synchronous mode,

measure on V_(SRP-SRN), V_SRP> 2.2V

Charge over-current threshold floor

Charge over-current threshold ceiling

mV

Maximum OCP threshold in synchronous mode,

measure on V_(SRP-SRN), V_SRP> 2.2V

180

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

V_ISYNSETCharge under-current falling threshold

Switch from STNCH to NON-SYNCH, V_SSP> 2.2 V

V_SRPfalling

1

5

2

9

mV

V

BATTERY SHORTED COMPARATOR (BATSHORT)

BAT Short falling threshold, forced

non-syn mode

V_BATSHT

V_{BATSHT_HYS}

V_{BATSHT_DEG}

BAT short rising hysteresis

Deglitch on both edge

200

1

mV

ms

LOW CHARGE CURRENT COMPARATOR

Average low charge current falling

threshold

Measure on V_(SRP-SRN), forced into non-synchronous

mode

V_LC

1.25

mV

V_{LC_HYS}

V_{LC_DEG}

Low charge current rising hysteresis

Deglitch on both edge

1.25

1

mV

ms

VREF REGULATOR

V_{VREF_REG}VREF regulator voltage

I_{VREF_LIM}

V_VCC> V_UVLO(0 – 35 mA Load)

V_VREF= 0 V, V_VCC> V_UVLO

REGN REGULATOR

3.267

35

3.3

6.0

3.333

6.3

V

VREF current limit

mA

V_{REGN_REG}

I_{REGN_LIM}

REGN regulator voltage

REGN current limit

V_VCC> 10 V, CE = HIGH (0 – 40 mA Load)

V_REGN= 0 V, V_VCC> V_UVLO

SAFETY TIMER

5.7

40

V

mA

T_PRECHG

T_CHARGE

Precharge safety timer range⁽¹⁾

Internal fast charge safety timer⁽¹⁾

Precharge time before fault occurs

1440

4.25

1800

5

2160

5.75

sec

Hr

BATTERY DETECTION

t_WAKE

Wake timer

Max time charge is enabled

R_SENSE= 10 mΩ

500

125

1

ms

mA

sec

mA

I_WAKE

Wake Current

50

200

t_DISCHARGE

I_DISCHARGE

I_FAULT

Discharge timer

Max time discharge current is applied

Discharge current

8

Fault current after a timeout fault

2

Voltage on VFB to detect battery absent during

Wake

V_WAKE

V_DISCH

Wake threshold ( w.r.t. V_REG

Discharge threshold

)

125

mV

V

Voltage on VFB to detect battery absent during

Discharge

0.35

PWM HIGH SIDE DRIVER (HIDRV)

High Side driver (HSD) turn-on

resistance

R_{DS_HI_ON}

V_BTST– V_PH= 5.5 V

3.3

1

6

Ω

V

R_{DS_HI_OFF}

V_{BTST_REFRESH}

High Side driver turn-off resistance

1.3

Bootstrap refresh comparator threshold V_BTST– V_PHwhen low side refresh pulse is

4

4.2

voltage

PWM LOW SIDE DRIVER (LODRV)

Low side driver (LSD) turn-on

requested

R_{DS_LO_ON}

4.1

1

7

Ω

resistance

R_{DS_LO_OFF}

Low side driver turn-off resistance

1.4

PWM DRIVERS TIMING

Driver dead time

Dead time when switching between LSD and HSD,

no load at LSD and HSD

30

ns

(1) Verified by design

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤ 28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM OSCILLATOR

V_{RAMP_HEIGHT}PWM ramp height

PWM switching frequency⁽²⁾

As percentage of VCC

7%

255

300

345

kHz

INTERNAL SOFT START (8 steps to regulation current I_CHARGE

)

Soft start steps

8

step

ms

Soft start step time

1.6

CHARGER SECTION POWER-UP SEQUENCING

Charge-enable delay after power-up

Delay from when CE = 1 to when the charger is

allowed to turn on

1.5

s

LOGIC IO PIN CHARACTERISTICS

V_{IN_LO}

CE input low threshold voltage

CE input high threshold voltage

CE input bias current

0.8

V

V_{IN_HI}

2.1

V_{BIAS_CE}

V_{OUT_LO}

I_{OUT_HI}

V = 3.3 V (CE has internal 1MΩ pulldown resistor)

6

0.5

1.2

mA

V

STAT, PG output low saturation voltage Sink current = 5 mA

Leakage Current V = 32V

µA

(2) Verified by design

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TYPICAL CHARACTERISTICS

Table 1. Table of Graphs

Figure

REF REGN and PG Power Up (CE=1)

Charge Enable

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Current Soft-Start (CE=1)

Charge Disable

Continuous Conduction Mode Switching Waveforms

Cycle-by-Cycle Synchronous to Nonsynchronous

Battery Insertion

Battery to Ground Short Protection

Efficiency vs Output Current

PH

VCC

/PG

LODRV

VREF

REGN

IBAT

CE

t − Time = 4 ms/div

t − Time = 200 ms/div

Figure 2. REF REGN and PG Power Up (CE=1)

Figure 3. Charge Enable

PH

LDRV

LODRV

IBAT

IL

CE

t − Time = 4 μs/div

t − Time = 4 ms/div

Figure 4. Current Soft-Start (CE=1)

Figure 5. Charge Disable

8

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PH

HIDRV

PH

LODRV

IL

t – Time = 200 ns/div

t − Time = 200 ns/div

Figure 6. Continuous Conduction Mode Switching Waveform

Figure 7. Cycle-by-Cycle Synchronous to Nonsynchronous

PH

LDRV

IL

VBAT

t – Time = 4 ms/div

t – Time = 200 ms/div

Figure 8. Battery Insertion

Figure 9. Battery to GND Short Protection

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98

96

94

92

90

88

86

84

82

80

24 Vin, 6 cell

24 Vin, 5 cell

12 Vin, 2 cell

12 Vin, 1 cell

0

1

2

3

4

5

6

7

8

IBAT - Output Current - A

Figure 10. Efficiency vs Output Current

10

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PIN FUNCTIONS

FUNCTION DESCRIPTION

NO. NAME

1

VCC

IC power positive supply. Connect, through a 10 Ω resistor to the common-source (diode-OR) point: source of

high-side P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10 Ω

resistor to the cathode of the input diode. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.

2

CE

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down

resistor.

3

4

STAT

TS

Open-drain charge status pin to indicate various charger operation (See Table 3)

Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot

and cold temperature window with a resistor divider from VREF to TS to GND.

5

PG

Open-drain power-good status output. The transistor turns on when a valid VCC is detected. It is turned off in the

sleep mode. PG can be used to drive a LED or communicate with a host processor. It can be used to drive ACFET

and BATFET.

6

7

8

9

VREF

ISET

VFB

3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage

could be used for programming of voltage and current regulation and for programming the TS threshold.

Charge current set input. The voltage of ISET pin programs the charge current regulation, pre-charge current and

termination current set-point.

Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery

terminals to this node to adjust the output battery regulation voltage.

SRN

Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode

filtering.

10 SRP

Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.

11 GND

Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.

12 REGN

PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to PGND pin, close to

the IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from

REGN to BTST.

13 LODRV

14 PH

PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1mF bootstrap capacitor from PH to

BTST.

15 HIDRV

16 BTST

PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1mF bootstrap capacitor from SW to

BTST

PowerPad

Exposed pad beneath the IC. Always solder PowerPad to the board, and have vias on the PowerPad plane

star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to

dissipate the heat.

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BLOCK DIAGRAM

VREF

bq24620

VOLTAGE

REFERENCE

-

VCC

SLEEP

UVLO

+

SRN +100 mV

-

VCC

SLEEP

UVLO

V

+

UVLO

3.3 V

VCC

VREF

LDO

VCC

CE

1M

COMP

ERROR

BTST

AMPLIFIER

CE

-

+

PWM

+

-

1V

+

-

LEVEL

SHIFTER

VFB

SRP

SRN

HIDRV

PH

1.8 V

BAT _OVP

SYNCH

20 mA

+

-

SRP-SRN

5 mV

+

-

PWM

CONTROL

LOGIC

VCC

+

20X

-

20XV(SRP-SRN)

+

-

IBAT_ REG

REGN

LODRV

6V LDO

REFRESH

-

BTST

_

20 mA

PH

+

ENA _BIAS

4.2 V

FAULT

V(SRP -SRN )

-

CHG _OCP

2 mA

+

160 % X IBAT _REG

GND

8 mA

FAULT

5HR Safety

Timer

STAT

IC Tj

TSHUT

+

-

CHARGE

STAT

30 minute

Precharge

Timer

CHARGE

145 degC

DISCHARGE

PG

+

-

BAT

BAT _OVP

VREF

STATE

ISET

8

108 % X VBAT _REG

DISCHARGE

LTF

MACHINE

LOGIC

ISET

IBAT _ REG

-

PG

+

1.25 mV

LOWV

BATTERY

DETECTION

LOGIC

-

COOL

VFB

-

LOWV

+

0.35V

-

+

-

WARM

COOL

WARM

+

VCC

ACOV

TS

-

SUSPEND

VFB

-

+

-

V

ACOV

RCHRG

+

-

HTF

TCO

+

-

1.675 V

+

-

RCHRG

TERM

TERMINATE CHARGE

-

20XV(SRP-SRN)

TERM

+

ISET

10

bq24620

12

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OPERATIONAL FLOWCHART

POR

SLEEP MODE

VCC > SRN

No

Indicate SLEEP

Yes

Enable VREF LDO &

Chip Bias

Initiate battery

detect algorithm

Battery

present?

Indicate battery

absent

No

Yes

See Enabling and

Disabling Charge Section

Indicate NOT

CHARGING,

Suspend timers

Conditions met

for charge?

Conditions met

for charge?

No

Yes

Regulate

precharge current

Precharge

timer expired?

Start 30 minute

precharge timer

VFB< VLOWV

Yes

VFB < VLOWV

Yes

Indicate Charge-

In-Progress

Start Fastcharge

timer

No

Regulate

fastcharge current

Yes

Indicate NOT

,

CHARGING

Suspend timers

Conditions met

for charge?

No

Yes

Indicate Charge-

In-Progress

No

Turn off charge ,

Enable I_DISCHGfor1

second

FAULT

Enable I

FAULT

VFB> VRECH

&

ICHG < ITERM

Fastcharge

Timer Expired ?

Yes

No

Yes

Indicate Charge In

Progress

Indicate FAULT

Charge Complete

Indicate DONE

Yes

No

VFB > VRECH

VFB < VRECH

No

Battery Removed

Yes

Indicate BATTERY

ABSENT

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DETAILED DESCRIPTION

Precharge

Current

Fastcharge Current

Regulation Phase

Fastcharge Voltage

Regulation Phase

Termination

Regulation

Phase

Regulation Voltage

V

RECH

Regulation Current

Charge

Current

Charge

Voltage

V

LOWV

I

& I

TERM

PRECH

Precharge

Time

Fastcharge Safety Time

Figure 11. Typical Charging Profile

BATTERY VOLTAGE REGULATION

The bq24620 uses a high accuracy voltage bandgap and regulator for the charging voltage. The charge voltage

is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The

voltage at the VFB pin is regulated to 1.8V, giving Equation 1 for the regulation voltage:

R2

é

ù

V

= 1.8 V ´ 1+

BAT

ê

ú

R1

ë

û

(1)

where R2 is connected from VFB to the battery and R1 is connected from VFB to GND

BATTERY CURRENT REGULATION

The ISET1 input sets the maximum charging current. Battery current is sensed by resistor R_SRconnected

between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100mV. Thus, for a 10mΩ

sense resistor, the maximum charging current is 10A. Equation 2 is for charge current

V

ISET

I

=

CHARGE

20 ´ R

SR

(2)

V_ISET, The input voltage range of ISET is between 0 and 2V. The SRP and SRN pins are used to sense voltage

across R_SRwith default value of 10mΩ. However, resistors of other values can also be used. A larger sense

resistor will give a larger sense voltage, a higher regulation accuracy; but, at the expense of higher conduction

loss.

14

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PRECHARGE

On power-up, if the battery voltage is below the V_LOWVthreshold, the bq24620 applies 125mA to the battery⁽¹⁾

The precharge feature is intended to revive deeply discharged cells. If the V_LOWVthreshold is not reached within

30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.

CHARGE TERMINATION, RECHARGE, AND SAFETY TIMER

The bq24620 monitors the charging current during the voltage regulation phase. Termination is detected while

the voltage on the VFB pin is higher than the V_RECHthreshold AND the charge current is less than the I_TERM

threshold, which is 1/10^thof programmed charge current, as calculated in Equation 3:

V

ISET

I

=

TERM

200 ´ R

SR

(3)

As a safety backup, the bq24620 also provides an internal 5 hour charge timer for fast charge.

A new charge cycle is initiated when one of the following conditions occur:

•

The battery voltage falls below the recharge threshold.

A power-on-reset (POR) event occurs.

CE is toggled.

POWER UP

The bq24620 uses a SLEEP comparator to determine the source of power on the VCC pin, since VCC can be

supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24620 will

enable the ACFET and disable BATFET. If all other conditions are met for charging, bq24620 will then attempt to

charge the battery (See Enabling and Disabling Charging). If the SRN voltage is greater than VCC, indicating

that the battery is the power source, bq24620 enters a low quiescent current (<15mA) SLEEP mode to minimize

current drain from the battery.

If VCC is below the UVLO threshold, the device is disabled.

ENABLE AND DISABLE CHARGING

The following conditions have to be valid before charge is enabled:

•

CE is HIGH.

The device is not in VCCLOWV mode.

The device is not in SLEEP mode (i.e., VCC > SRN) .

The VCC voltage is lower than the AC over-voltage threshold (VCC < V_ACOV).

30 ms delay is complete after initial power-up.

The REGN LDO and VREF LDO voltages are at the correct levels.

Thermal Shut (TSHUT) is not valid.

TS fault is not detected.

One of the following conditions will stop on-going charging

•

CE is LOW.

Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode.

Adapter voltage is less than 100mV above battery.

Adapter is over voltage.

The REGN or VREF LDOs are overloaded.

TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis).

TS voltage goes out of range indicating the battery temperature is too hot or too cold.

Safety timer times out.

(1) 125mA (assuming a 10mΩ sense resistor. 1.25mV will be regulated across SRP-SRN, regardless of the value of the sense resistor.)

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AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT

The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge

to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists

of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.

Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this

function.

CONVERTER OPERATION

The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A

type III compensation network allows using ceramic capacitors at the output of the converter. The compensation

input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The

feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output

(EAO). The LC output filter is selected to give a resonant frequency of 10 kHz – 15 kHz for bq24620, where

resonant frequency, f_o, is given by:

1

f_o

=

2p L_oC_o

(4)

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the

converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input

adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop

compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is

below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%

duty-cycle PWM request. Internal gate drive logic allows achieving 99.95% duty-cycle while ensuring the

N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below

4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side

n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the

high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again

due to leakage current discharging the BTST capacitor below the 4.2 V, and the reset pulse is reissued.

The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,

battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible

noise region. Also see Application Information for how to select Inductor, capacitor and MOSFET.

SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION

The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for

a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is

break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where

both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the

low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During

synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode

(CCM), creating a fixed two-pole system.

The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor

current for a 10mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is

lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.

During non-synchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor

current after the high-side n-channel power MOSFET turns off. When the load current decreases and the

inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become

discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel

power MOSFET will turn-on for around 80ns when the bootstrap capacitor voltage drops below 4.2V, then the

low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power

MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is

always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for

battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can

both source and sink current. The 80ns low-side pulse pulls the PH node (connection between high and low-side

MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80ns, the

low-side MOSFET is kept off to prevent negative inductor current from occurring.

16

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At very low currents during non-synchronous operation, there may be a small amount of negative inductor

current during the 80ns recharge pulse. The charge should be low enough to be absorbed by the input

capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on,

and the low-side MOSFET does not turn on (only 80ns recharge pulse) either, and there is almost no discharge

from the battery.

During the DCM mode the loop response automatically changes and has a single pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means at very low currents the loop response is slower, as there is less sinking current

available to discharge the output voltage.

CYCLE-BY-CYCLE CHARGE UNDER CURRENT

If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the

average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the

switching cycle to prevent negative inductor current. During DCM, the low-side FET will only turn on for at around

80ns when the bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap

capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input

voltage increases as power is transferred from the battery to the input capacitors and lead to an over-voltage

stress on the VCC node and potentially cause damage to the system.

INPUT OVER VOLTAGE PROTECTION (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage

reaches the ACOV threshold, charge is disabled and the battery is switched to system instead of adapter.

INPUT UNDER VOLTAGE LOCK OUT (UVLO)

The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from

either input adapter or battery, if a conduction path exists from the battery to VCC through the high side NMOS

body diode. When VCC is below the UVLO threshold, all circuits in the IC are disabled.

BATTERY OVER-VOLTAGE PROTECTION

The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 105% of the regulation

voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed

or the battery is disconnected. An 8mA current sink from SRP/SRN to PGND is on only during charge and allows

discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP will also

suspend the safety timer.

CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION

The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents

the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the

over-current is detected, and automatically resumes when the current falls below the over-current threshold.

THERMAL SHUTDOWN PROTECTION

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the

ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and

self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off

until the junction temperature falls below 130°C. Then the charger will soft-start again if all other enable charge

conditions are valid. Thermal shutdown will also suspend the safety timer.

TEMPERATURE QUALIFICATION

The controller continuously monitors battery temperature by measuring the voltage between the TS pin and

GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this

voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.

To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery

temperature is outside of this range, the controller suspends charge and the safety timer and waits until the

battery temperature is within the V(LTF) to V(HTF) range. During the charge cycle the battery temperature must

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be within the V(LTF) to V(TCO) thresholds. If battery temperature is outside of this range, the controller suspends

charge and safety timer and waits until the battery temperature is within the V(LTF) to V(HTF) range. If the

battery temperature is between the V(LTF) and the V(COOL) thresholds or between the V(HTF) and V(WARM)

thresholds, charge is automatically reduced to I_CHARGE/8. To avoid early termination during COOL/WARM

condition, set I_TERM≤ I_CHARGE/10. The controller suspends charge by turning off the PWM charge FETs. Figure 12

and Figure 13 summarizes the operation.

TEMPERATURE RANGE TO

INITIATE CHARGE

TEMPERATURE RANGE

DURING A CHARGE CYCLE

VREF

CHARGE SUSPENDED

CHARGE at I_CHARGE/8

CHARGE at I_CHARGE

CHARGE SUSPENDED

V

LTF

LTF_HYS

V

LTF

CHARGE at I_CHARGE/8

V

COOL

V

COOL_HYS

CHARGE at I_CHARGE

V

WARM

V

WARM_HYS

CHARGE at I_CHARGE/8

CHARGE SUSPENDED

CHARGE at I_CHARGE/8

CHARGE SUSPENDED

V

HTF

V

TCO

GND

Figure 12. TS, Thermistor Sense Thresholds

Charge

Current

Charge

Suspended

Charge

Suspended

Charge at I_CHG

Programmed

Charge Current

(I_CHARGE

)

1/8 x Programmed

Charge Current

(I_CHARGE/8)

Temperature

/V_TCO

V

HTF

WARM

LTF

COOL

Figure 13. Typical Charge Current vs Temperature Profile

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Assuming a 103AT NTC thermistor on the battery pack as shown in the Typical System Schematic, the value

RT1 and RT2 can be determined by using Equation 5 and Equation 6:

æ

ç

è

ö

÷

ø

1

V_VREF´ RTH_COOL´ RTH_WARM

´

-

V_COOL

V_WARM

RT2 =

æ

ç

è

ö

æ

ö

÷

ø

V_VREF

RTH_WARM

´

-1 - RTH

´

-1

÷

ç

COOL

V_WARM

V_COOL

ø

è

(5)

(6)

V_VREF

-1

V_COOL

RT1 =

1

+

RT2

RTH_COOL

VREF

RT1

RT2

bq24620

TS

RTH

103AT

Figure 14. TS Resistor Network

For example, 103AT NTC thermistor is used to monitor the battery pack temperature. Select T_COOL= 0ºC, T_WARM

= 60ºC. From the calculation and select standard 5% resistor value. We can get R_T1= 2.2kΩ, R_T2= 6.8kΩ, and

T_COLDis -17ºC (target -20ºC); T_HOTis 77ºC (target 75ºC), and T_CUT-OFFis 86ºC (target 80ºC). A small RC filter is

suggested to protect TS pin from system-level ESD.

Timer Fault Recovery

The bq24620 provides a recovery method to deal with timer fault conditions. The following summarizes this

method:

Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.

Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and

battery detection will begin. Taking CE low or a POR condition will also clear the fault.

Condition 2: The battery voltage is below the RECHARGE threshold and a timeout fault occurs.

Recovery Method: Under this scenario, the bq24620 applies the IFAULT current to the battery. This small

current is used to detect a battery removal condition and remains on as long as the battery voltage stays below

the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24620 disables the fault

current and executes the recovery method described in Condition 1. Taking CE low or a POR condition will also

clear the fault.

PG Output

The open drain PG(power good) indicates whether the VCC voltage is valid or not. The open drain FET turns on

whenever bq24620 has a valid VCC input ( not in UVLO or ACOV or SLEEP mode). The PGpin can be used to

drive an LED or communicate to the host processor.

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CE (Charge Enable)

The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables

charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high to low

transition on this pin also resets all timers and fault conditions. There is an internal 1 MΩ pulldown resistor on the

CE pin, so if CE is floated the charge will not turn on.

INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES

The bq24620 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant

frequency, f_o, is approximately 10kHz – 15kHz per Equation 7:

1

f_o

=

2p L_oC_o

(7)

Table 2 provides a summary of typical LC components for various charge currents

Table 2. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current

CHARGE CURRENT

Output Inductor Lo

Output Capacitor Co

Sense Resistor

2A

4A

6A

8A

10A

8.2 mH

20 mF

10 mΩ

8.2 mH

20 mF

10 mΩ

5.6 mH

20 mF

10 mΩ

4.7 mH

40 mF

10 mΩ

4.7 mH

40 mF

10 mΩ

CHARGE STATUS OUTPUTS

The open-drain STAT outputs indicate various charger operations as shown in Table 3. These status pins can be

used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain

transistor is turned off.

Table 3. STAT Pin Definition for bq24620

CHARGE STATE

STAT

ON

Charge in progress

Charge complete (PG=LOW)

Sleep mode (PG=HIGH)

OFF

Charge suspend, timer fault, ACOV, battery absent

BLINK (0.5 Hz)

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BATTERY DETECTION

For applications with removable battery packs, bq24620 provides a battery absent detection scheme to reliably

detect insertion or removal of battery packs. CE needs to be HIGH to enable battery detection function.

POR or RECHARGE

The battery detection routine runs on

power up, or if VFB falls below VRECH

due to removing a battery or

discharging a battery

Apply 8mA discharge

current, start 1s timer

1s timer

expired

No

VFB < V_LOWV

No

Yes

Battery Present,

Begin Charge

Disable 8mA

discharge current

Enable 125 mA Charge,

Start 0.5s timer

0.5s timer

expired

No

VFB > V_RECH

No

Yes

Battery Present,

Begin Charge

Disable 125mA

Charge

Battery Absent

Figure 15. Battery Detection Flowchart

Once the device has powered up, an 8mA discharge current will be applied to the SRN terminal. If the battery

voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is

turned on at low charge current (125mA). If the battery voltage gets up above the recharge threshold within

500ms, there is no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before

the respective thresholds are hit, a battery is detected and a charge cycle is initiated.

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Battery not Detected

V

REG

V

RECH

Battery

Inserted

V

LOWV

Battery Detected

t

WAKE

t

RECH DEG

_

LOWV DEG

_

Figure 16. Battery Detect Timing Diagram

Care must be taken that the total output capacitance at the battery node is not so large that the discharge current

source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum

output capacitance can be calculated as seen in Equation 8:

I_DISCH´ t_DISCH

C_MAX

=

é

ù

R

ê

²ú

1.425 ´ 1+

R₁

ë

û

(8)

Where C_MAXis the maximum output capacitance, I_DISCHis the discharge current, t_DISCHis the discharge time, and

R₂and R₁are the voltage feedback resistors from the battery to the VFB pin. The 1.425 factor is the difference

between the RECHARGE and the LOWV thresholds at the VFB pin.

EXAMPLE

For a 3-cell Li+ charger, with R2 = 500k, R1 = 100k (giving 10.8V for voltage regulation), I_DISCH= 8mA, t_DISCH= 1

second,

8mA ´ 1sec

C_MAX

=

= 930 mF

500k

é

ù

1.425 ´ 1+

ê

ú

100k

ë

û

(9)

Based on these calculations, no more than 930 mF should be allowed on the battery node for proper operation of

the battery detection circuit.

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Component List for Typical System Circuit of Figure 1

PART DESIGNATOR

QTY

2

DESCRIPTION

N-channel MOSFET, 40 V, 30 A, PowerPAK SO-8, Vishay-Siliconix, SiR426DN

Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C

Schottky Diode, 40V, 5A, SMC, ON Semiconductor, MBRS540T3

Sense Resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F

Inductor, 6.8 mH, 5.5 A, Vishay-Dale, IHLP2525CZ

Capacitor, Ceramic, 10 mF, 35 V, 10%, X7R

Capacitor, Ceramic, 2.2µF, 50 V, 10%, X7R

Capacitor, Ceramic, 1 mF, 16V, 10%, X7R

Q4, Q5

D1

1

D2

1

R_SR

2

L1

1

C8, C9, C12, C13

4

C2

1

C4, C5

C7

2

1

Capacitor, Ceramic, 1µF, 50 V, 10%, X7R

C1, C6, C11

C_ff

4

Capacitor, Ceramic, 0.1 mF, 16 V, 10%, X7R

Capacitor, Ceramic, 22 pF, 35 V, 10%, X7R

Capacitor, Ceramic, 0.1 mF, 50V, 10%

1

C10

1

R1, R7

R2

2

Resistor, Chip, 100 kΩ, 1/16W, 0.5%

1

Resistor, Chip, 900 kΩ, 1/16W, 0.5%

R8

1

Resistor, Chip, 22.1 kΩ, 1/16W, 0.5%

R9

1

Resistor, Chip, 9.31 kΩ, 1/16W, 1%

R10

1

Resistor, Chip, 430 kΩ, 1/16W, 1%

R11

1

Resistor, Chip, 2Ω, 1W, 5%

R13, R14

R5

2

Resistor, Chip, 10 kΩ, 1/16W, 5%

1

Resistor, Chip, 100 Ω, 1/16W, 0.5%

R6

1

Resistor, Chip, 10 Ω, 1W, 5%

D3, D4

2

LED Diode, Green, 2.1V, 10mΩ, Vishay-Dale, WSL2010R0100F

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23

Product Folder Link(s): bq24620

bq24620

SLUS893 –MARCH 2010

www.ti.com

APPLICATION INFORMATION

Inductor Selection

The bq24620 has 300kHz switching frequency to allow the use of small inductor and capacitor values. Inductor

saturation current should be higher than the charging current (I_CHARGE) plus half the ripple current (I_RIPPLE):

I

³ I

+ (1/2) I

SAT

CHG RIPPLE

(10)

The inductor ripple current depends on input voltage (V_IN), duty cycle (D=V_OUT/V_IN), switching frequency (f_s) and

inductance (L):

V

´ D ´ (1 - D)

IN

I_RIPPLE

=

f_S´ L

(11)

The maximum inductor ripple current happens with D = 0.5. For example, the battery charging voltage range is

from 2.8V to 14.4V for 4-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum

inductor ripple current.

Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between

inductor size and efficiency for a practical design.

The bq24620 has cycle-by-cycle charge under current protection (UCP) by monitoring charging current sensing

resistor to prevent negative inductor current. The Typical UCP threshold is 5mV falling edge corresponding to

0.5A falling edge for a 10mΩ charging current sensing resistor.

Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at

50% duty cycle, then the worst case capacitor RMS current I_CINoccurs where the duty cycle is closest to 50%

and can be estimated by the following equation:

I_CIN= I_CHG

´

D ´ (1-D)

(12)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred

for 20V input voltage. 20µF capacitance is suggested for typical of 3-4A charging current.

Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current I_COUTis given:

I

RIPPLE

I

=

» 0.29 ´ I

RIPPLE

COUT

2 ´

3

(13)

The output capacitor voltage ripple can be calculated as follows:

æ

ç

è

ö

÷

ø

V_OUT

DV_o=

1-

2

V

8LCf_s

IN

(14)

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC.

The bq24620 has internal loop compensator. To get good loop stability, the resonant frequency of the output

inductor and output capacitor should be designed between 10 kHz and 15 kHz. The preferred ceramic capacitor

is 25V, X7R or X5R for 4-cell application.

Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are

internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are

preferred for 20V input voltage and 40V MOSFETs are preferred for 20-28V input voltage.

24

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bq24620

www.ti.com

SLUS893 –MARCH 2010

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction

loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,

R_DS(ON), and the gate-to-drain charge, Q_GD. For bottom side MOSFET, FOM is defined as the product of the

MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

FOM_top= R_DS(on)´ Q_GD

FOM_bottom= R_DS(on)´ Q_G

(15)

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON)has higher cost with the same

package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle

(D=V_OUT/V_IN), charging current (I_CHARGE), MOSFET's on-resistance R_DS(ON)), input voltage (V_IN), switching

frequency (F), turn on time (t_on) and turn off time (t_toff):

1

2

= D ´ I_CHG´ R_DS(on)

P

+

´ V ´ I_CHG

´

t_on+ t_off´ f

S

(

)

top

IN

2

(16)

The first item represents the conduction loss. Usually MOSFET R_DS(ON)increases by 50% with 100ºC junction

temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are

given by:

Q

SW

t

=

, t

=

off

on

I

on

off

(17)

where Q_swis the switching charge, I_onis the turn-on gate driving current and Ioff is the turn-off gate driving

current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge

(Q_GD) and gate-to-source charge (Q_GS):

1

Q

= Q

+

´ Q

GS

SW

GD

2

(18)

Gate driving current total can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total

turn-on gate resistance (Ron) and turn-off gate resistance R_off) of the gate driver:

V_REGN- V_plt

V_plt

I_on

=

, I_off=

R_on

R_off

(19)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in

synchronous continuous conduction mode:

2

= (1 - D) ´ I_CHG´ R_DS(on)

P

bottom

(20)

If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the

average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the

switching cycle to prevent negative inductor current.

As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum

charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing

resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body

diode capable of carrying the maximum non-synchronous mode charging current.

MOSFET gate driver power loss contributes to the dominant losses on controller IC, when the buck converter is

switching. Choosing the MOSFET with a small Q_{g_total}will reduce the IC power loss to avoid thermal shut down.

P

= V ×Q_{g_total}×f_s

IN

ICLoss_driver

(21)

Where Q_{g_total}is the total gate charge for both upper and lower MOSFET at 6V V_REGN.

The VREF load current is another component on VCC input current (Do not overload VREF) where total IC loss

can be described by following equations:

P_VREF= (V_IN- V_VREF)×I_VREF

P

= P

+ P_VREF+ P_Quiescent

ICLOSS

ICLOSS _ driver

(22)

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25

Product Folder Link(s): bq24620

bq24620

SLUS893 –MARCH 2010

www.ti.com

Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second

order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The

input filter must be carefully designed and tested to prevent over voltage event on VCC pin.

There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic

capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin

voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.

However these two solutions may not have low cost or small size.

A cost effective and small size solution is shown in Figure 17. The R1 and C1 are composed of a damping RC

network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used

for reverse voltage protection for VCC pin ( it can be the input schottky diode or the body diode of input ACFET).

C2 is VCC pin decoupling capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form

a damping RC network to further protect the IC from high dv/dt and high voltage spike. C2 value should be less

than C1 value so R1 can dominant the equivalent ESR value to get enough damping effect for hot plug-in. R1

and R2 package must be sized enough to handle inrush current power loss according to resistor manufacturer’s

datasheet. The filter components value always need to be verified with real application and minor adjustments

may need to fit in the real application circuit.

D1

(1206)

R2

4.7-30W

R1

2 W

(2010)

Adapter

connector

VCC pin

C1

2.2 mF

C2

0.1-1 mF

Figure 17. Input Filter

PCB Layout

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Figure 18) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper

layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use

shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on

different layers and using vias to make this connection.

2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal

traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching

MOSFETs.

3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to

carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop

area) and do not route the sense leads through a high-current path (see Figure 19 for Kelvin connection for

best current accuracy). Place decoupling capacitor on these traces next to the IC.

5. Place output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor

ground before connecting to system ground.

7. Route analog ground separately from power ground and use single ground connection to tie charger power

ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins

to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground

and power ground together using PowerPAD as the single ground connection point. Or using a 0Ω resistor to

tie analog ground to power ground (PowerPAD should tie to analog ground in this case). A star-connection

26

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bq24620

www.ti.com

SLUS893 –MARCH 2010

under PowerPAD is highly recommended.

8. It is critical that the exposed PowerPAD on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

10. All via size and number should be enough for a given current path.

L1

R1

V

BAT

SW

High

Frequency

Current

Path

V

BAT

IN

C2

C3

C1

PGND

Figure 18. High Frequency Current Path

Current Direction

R

SNS

Current Sensing Direction

To SRP - SRN pin

Figure 19. Sensing Resistor PCB Layout

Refer to the EVM design (SLUU410) for the recommended component placement with trace and via locations.

For the QFN information, refer to SCBA017 and SLUA271.

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27

Product Folder Link(s): bq24620

PACKAGE OPTION ADDENDUM

www.ti.com

24-Mar-2010

PACKAGING INFORMATION

Orderable Device

BQ24620RVAR

BQ24620RVAT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RVA

16

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

VQFN

RVA

16

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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型号：	BQ24620
厂家：	TEXAS INSTRUMENTS
描述：	Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with Low Iq 独立同步开关模式磷酸锂电池充电器低智商电池开关
文件：	总30页 (文件大小：1420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24620 [TI]

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