BQ24742RHDT_技术文档

bq24741, bq24742

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Li-Ion or Li-Polymer Battery Charger with Low I_qand Accurate Trickle Charge

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1

FEATURES

APPLICATIONS

•

Notebook and Ultra-Mobile PC

Portable Data Capture Terminals

Portable Printers

Medical Diagnostics Equipment

Battery Bay Chargers

•

NMOS-NMOS Synchronous Buck Converter

•

Resistor-Programmable Switching Frequency

between 300 kHz and 800 kHz

•

9 V-24 V Input Voltage Operation Range

Support Two to Four Cells

Battery Back-up Systems

Analog Inputs with Ratiometric Programming

via Resistors or DAC/GPIO

DESCRIPTION

–

Charge Voltage (4-4.512 V/cell)

Charge Current (up to 10 A)

Adapter Current Limit for DPM

The bq24741/2 is a high-efficiency, synchronous

battery charger with integrated compensation,

offering low component count for space-constrained

Li-ion or Li-polymer battery charging applications.

Ratiometric charge current and voltage programming

allows high regulation accuracies, and can be either

hardwired with resistors or programmed by the

system power-management microcontroller using a

DAC or GPIOs.

•

High-Accuracy Voltage and Current Regulation

–

±0.5% Charge Voltage Accuracy

±3% Charge Current Accuracy

±3% Adapter Current Accuracy

±2% Input Current Sense Amp Accuracy

•

150 mA Trickle-charge Current with ±33%

Accuracy Down to Zero Battery Voltage

The bq24741/2 charges two, three, or four series Li+

cells, supporting up to 10 A of charge current, and is

available in a 28-pin, 5x5-mm²thin QFN package.

Safety Protection

Text for space

–

Input Overvoltage Protection

Battery Overvoltage Protection

Charger Overcurrent Protection

Thermal Shutdown Protection

FET/Inductor/Battery Short Protection

28 27

26 25

24 23

22

•

Status and Monitoring Outputs

–

Adapter Present Indicator

21

20

1

2

CE

ACN

DPMDET

CELLS

Programmable Input Power Detect with

Adjustable Threshold

19

18

3

4

5

6

CSP

CSN

ACP

bq24741/2

QFN-28

TOP VIEW

–

Dynamic Power Management (DPM) with

Status Indicator

LPMOD

ACDET

ACSET

17

BAT

–

Current Drawn from Input Source

16

15

•

Charge Enable Pin

ISET

Internal Soft-Start and Loop Compensation

7

IADAPT

LPREF

25 ns Minimum Driver Dead-Time and 99.5%

Maximum Effective Duty Cycle

8

9

10

11

12

13 14

•

28-pin, 5x5-mm²QFN package

Energy Star Low Quiescent Current I_q

–

< 10 μA Off-State Battery Discharge Current

< 1.5 mA Off-State Input Quiescent Current

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The bq24741/2 features resistor-programmable PWM switching frequency and accurate 150mA trickle charge

(with 20 mΩ sensing resistor), which can be enabled via the TRICKLE pin. The bq24741/2 also features Dynamic

Power Management (DPM) and input power limiting. These features reduce battery charge current when the

input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger

simultaneously. A high-accuracy current sense amplifier enables accurate measurement of input current from the

AC adapter, allowing monitoring the overall system power. If the adapter current is above the programmed

low-power threshold, a signal is sent to host so that the system optimizes its power performance according to

what is available from the adapter.

Text for space

R16

10 Ω

SYSTEM

ADAPTER +

ADAPTER -

R

R11

2 Ω

C7

AC

0.010 Ω

C6

P

10 µF

Q1 (ACFET) Q2 (ACFET)

SI4435 SI4435

Controlled by

HOST

D2

BAT54

C1

2.2 µF

C3

C2

ACN

ACP

PVCC

R1

0.1 µF

432 kΩ

1%

Q3(BATFET)

SI4435

C8

0.1 µF

Controlled by

HOST

ACDET

AGND

R2

P

Q4_A

FDS8978

66.5 kΩ

1%

HIDRV

VREF

R3

10kΩ

N

R^SR

0.020 Ω

SW

EXTPWR

VREF

EXTPWR

L1

C9

BTST

PACK+

PACK-

10µH

D1

BAT54

C12

10 µF

0.1 µF

R4

10 kΩ

R5

C4

1 µF

REGN

C11

10 µF

bq24741/2

10kΩ

C10

TRICKLE

DPMDET

1 µF

C13

0.1 µF

LODRV

PGND

GPIO

C14

0.1 µF

N

LPMOD

CELLS

CE

Q4_B

FDS8978

R15

CSP

CSN

HOST

10 kΩ

VDAC

ISET

120 kΩ

BAT

ISET_PWM

(D = 0.72, V_peak= VDAC)

VREF

R14

C13

100nF

C15

0.1 µF

R7

73.2 kΩ

1%

LPREF

ADC

IADAPT

VADJ

VREF

C5

100pF

R9

60.4 kΩ

1%

R8

26.7 kΩ

1%

ACSET

FSET

R12

102 kΩ

1%

PowerPad

R10

40.2 kΩ

1%

R6

97.6 kΩ

R13

64.9 kΩ

1%

Text for space

F_S= 400 kHz, 90 W Adapter, V_ADAPTER= 19 V, V_BAT= 3-cell Li-Ion (4.2V/cell), I_charge= 3.6 A, I_{adapter_limit}= 4.0 A

Figure 1. Typical System Schematic, Voltage, and Current Programmed by Resistor

Text for space

2

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Text for space

R16

10 Ω

SYSTEM

ADAPTER +

R11

2 Ω

C7

C6

R_AC

0.010 Ω

P

10 µF

ADAPTER -

D2

BAT54

Q1 (ACFET) Q2 (ACFET)

SI4435 SI4435

Controlled by

HOST

C1

2.2 µF

C3

C2

R1

ACN

ACP

PVCC

0.1 µF

432 kΩ

1%

Q3 (BATFET)

SI4435

C8

0.1 µF

Controlled by

HOST

ACDET

AGND

bq24741/2

R2

66.5 kΩ

1%

P

Q4_A

FDS8978

HIDRV

VREF

R3

10 kΩ

N

R^SR

0.020 Ω

SW

EXTPWR

VREF

L1

C9

BTST

PACK+

PACK-

4.7 µH

D1

BAT54

C12

10 µF

0.1 µF

R4

10 kΩ

R5

C4

1 µF

REGN

C11

10 µF

10kΩ

C10

TRICKLE

DPMDET

1 µF

C13

0.1 µF

LODRV

PGND

GPIO

C14

0.1 µF

N

LPMOD

CELLS

CE

Q4_B

FDS8978

R15

CSP

CSN

10 kΩ

HOST

VDAC

ISET

120 kΩ

BAT

ISET_PWM

VREF

R14

C13

100nF

C15

0.1 µF

(D = 0.72, V_peak= VDAC)

R7

73.2 kΩ

1%

LPREF

ACSET

VADJ

R8

26.7 kΩ

1%

DAC

ADC

FSET

IADAPT PowerPad

R6

56.2 kΩ

C5

100 pF

Text for space

(1) Pull-up rail could be either VREF or other system rail.

(2) SRSET/ACSET could come from either DAC or resistor dividers.

F_S= 650 kHz, 90 W Adapter, V_ADAPTER= 19 V, V_BAT= 3-cell Li-Ion (4.2V/cell), I_charge= 3.6 A, I_{adapter_limit}= 4.0 A

Figure 2. Typical System Schematic, Voltage and Current Programmed by DAC

ORDERING INFORMATION

Part number

Package

Ordering Number

(Tape and Reel)

Quantity

bq24741RHDR

bq24741RHDT

bq24742RHDR

bq24742RHDT

3000

250

bq24741

bq24742

28-PIN 5 x 5 mm²QFN

3000

250

PACKAGE THERMAL DATA

PACKAGE

θ_JA

T_A= 25°C POWER RATING

2.36 W

DERATING FACTOR ABOVE T_A= 25°C

QFN – RHD^{(1) (2)}

39°C/W

0.028 W/°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2x3 via matrix.

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

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Table 1. Pin Functions – 28-Pin QFN

DESCRIPTION

NAME

NO.

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1 MΩ pull-down

resistor. A 10 KΩ external resistor is required to connect the CE pin to the external pull-up rail other than VREF.

CE

1

Adapter current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from ACN pin to AGND for common-mode

filtering.

ACN

ACP

2

3

4

Adapter current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. A 0.1 μF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

Low-power-mode-detect active-LOW open-drain logic output. Place a 10kohm pull-up resistor from LPMOD pin to the

pull-up voltage rail. The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LOW

when IADAPT pin voltage is higher than LPREF pin voltage. Internal 6% hysteresis.

LPMOD

ACDET

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter

input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET pin voltage is greater than 2.4 V. IADAPT

current sense amplifier is active when ACDET pin voltage is greater than 0.6V and PVCC > VUVLO. ACOV is input

over-voltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes

when ACDET < 3.1 V.

5

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to

ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the

VDAC pin.

ACSET

LPREF

6

7

Low power voltage set input. Connect a resistor divider from VREF to LPREF, and AGND to program the reference for

the LOPWR comparator. The LPREF pin voltage is compared to the IADAPT pin voltage and the logic output is given

on the LPMOD open-drain pin. Connect LPREF to ACSET through a resistor divider to track the adapter power.

Trickle current enable logic input. When CE is HIGH, a HIGH level on this pin enables accurate 150 mA trickle charge

with 20 mΩ sense resistor. A LOW level on this pin enables the ISET pin to program the charge current. It has an

internal 1MΩ pull-down resistor.

TRICKLE

AGND

8

9

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3 V regulated voltage output. Place a 1 μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

could be used for ratio-metric programming of voltage and current regulation and for programming the LPREF

threshold. VREF is also the voltage source for the internal circuit.

VREF

10

Charge voltage set reference input. Connect the VREF or external DAC voltage source to VDAC pin. Battery voltage,

charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the voltage on VADJ, and

ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, ISET, and ACSET pins to AGND for

programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, ISET,

or ACSET.

VDAC

11

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage

regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the

output of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.

VADJ

12

13

Valid adapter active-low detect logic open-drain output. Pulled LO when Input voltage is above ACDET programmed

threshold OR input current is greater than 1.25 A with 10 mΩ sense resistor. Connect a 10 kΩ pull-up resistor from

EXTPWR pin to pull-up supply rail.

EXTPWR

FSET

14

15

PWM switching frequency (F_s) program pin. Program the switching frequency by placing a resistor to AGND on this pin.

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a

100pF (max) or less ceramic decoupling capacitor from IADAPT to AGND.

IADAPT

Charge current set input. The voltage ratio of ISET voltage versus VDAC voltage programs the charge current

regulation set-point. Program by connecting a resistor divider from VDAC to ISET, to AGND; or, by connecting the

output of an external DAC to ISET pin and connect the DAC supply to VDAC pin.

ISET

BAT

CSN

16

17

18

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT

pin to accurately sense the battery pack voltage. Place a 0.1 μF capacitor from BAT to AGND close to the IC to filter

high frequency noise.

Charge current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide

differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from CSN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide

differential-mode filtering. A 0.1 μF ceramic capacitor is placed from CSP pin to AGND for common-mode filtering.

CSP

19

20

CELLS

2, 3 or 4 cells selection logic input. Logic Lo programs 3–cell. Logic HI programs 4-cell. Floating programs 2–cell.

4

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Table 1. Pin Functions – 28-Pin QFN (continued)

DESCRIPTION

NAME

NO.

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input

current is being limited by reducing the charge current. Connect 10-kohm pull-up resistor from DPMDET pin to VREF or

a different pull-up supply rail.

DPMDET

21

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of

low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND

through the PowerPad underneath the IC.

PGND

LODRV

REGN

22

23

24

PWM low side driver output. Connect to the gate of the low–side power MOSFET with a short and wide trace.

PWM low side driver positive supply output. Connect a 1 μF ceramic capacitor from REGN to PGND pin, close to the

IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from

REGN to BTST. REGN is disabled when CE is LOW.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET

SW

25

26

drain, high-side power MOSFET source, and output inductor). Connect the 0.1 μF bootstrap capacitor from SW to

BTST.

HIDRV

PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect a 0.1 μF bootstrap ceramic capacitor from BTST to SW. Connect a

bootstrap Schottky diode from REGN to BTST. A optional 2.0Ω - 5.1Ω bootstrap resistor can be inserted between the

BTST pin and the common point of the bootstrap capacitor and bootstrap diode, thus dampening the SW node voltage

ring and spike.

BTST

27

28

IC power positive supply. Connect to the adapter input through a schottky diode. Place a 0.1 uF ceramic capacitor from

PVCC to PGND pin close to the IC.

PVCC

Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad

to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a thermal

pad to dissipate the heat.

PowerPad

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

VALUE

–0.3 to 30

–1 to 30

–0.3 to 7

UNIT

PVCC, ACP, ACN, CSP, CSN, BAT

SW

REGN, LODRV, VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD,

LPREF, CE, CELLS, EXTPWR, DPMDET, TRICKLE

Voltage range

V

VDAC, VREF

–0.3 to 3.6

–0.3 to 36

–1 to 1

BTST, HIDRV with respect to AGND and PGND

AGND, PGND

Maximum difference voltage ACP–ACN, CSP–CSN

Junction temperature range

-0.5 to 0.5

–40 to 155

–55 to 155

°C

Storage temperature range

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

–0.8

0

NOM

MAX

24

UNIT

V

SW

PVCC, ACP, ACN, CSP, CSN, BAT

24

V

REGN, LODRV

VREF

0

6.5

V

3.3

3.6

V

Voltage range

VDAC

V

VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD, LPREF, CE, CELLS,

EXTPWR, DPMDET, TRICKLE

0

5.5

V

BTST, HIDRV with respect to AGND and PGND

AGND, PGND

0

–0.3

–40

30

0.3

V

Maximum difference voltage: ACP–ACN, CSP–CSN

Junction temperature range

0.3

V

125

150

°C

Storage temperature range

–55

ELECTRICAL CHARACTERISTICS

9.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

(1) (2) (3)

otherwise noted)

PARAMETER

OPERATING CONDITIONS

V_{PVCC_OP}PVCC input voltage operating range

CHARGE VOLTAGE REGULATION

V_{BAT_REG_RNG}BAT voltage regulation range

V_{VDAC_OP}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

9

24

V

4-4.512 V per cell, times 2,3,4 cells

8

2.6

18.048

3.6

V

VDAC reference voltage range

VADJ voltage range

V_{VADJ_OP}

0

VDAC

0.5

8 V, 8.4 V, 9.024 V

–0.5

Charge voltage regulation accuracy

12 V, 12.6 V, 13.536 V

16 V, 16.8 V, 18.048 V

0.5

%

0.5

CHARGE CURRENT REGULATION (ENABLE CE & DISABLE TRICKLE)

V_{IREG_CHG}

Charge current regulation differential

voltage range

V_{IREG_CHG}= V_CSP– V_CSN

0

100

mV

V

V_{ISET_OP}

SRSET voltage range

0

–3%

VDAC

3%

V_{IREG_CHG}= 40 mV

V_{IREG_CHG}= 20 mV

–5%

5%

Charge current regulation accuracy

V_{IREG_CHG}= 5 mV

–25%

–33%

–50%

–1.0

25%

33%

50%

1.0

V_{IREG_CHG}= 3 mV (V_BAT≥ 4 V)

V_{IREG_CHG}= 3 mV (V_BAT< 4 V)

V_BAT≥ 4 V

Off-set Voltage of Amplifier

mV

V_BAT< 4 V

–1.5

1.5

TRICKLE CHARGE CURRENT REGULATION (ENABLE CE & TRICKLE)

Charge Current Regulation Accuracy

Off-set Voltage of Amplifier

V_{IREG_CHG}= 3 mV

–33%

–1.0

33%

1.0

(1) Verified by design

(2) Deglitch time and delay are proportional to the period of oscillator, unless specified.

(3) When CE=HIGH, the internal oscillator frequency is equal to external setting F_s; when CE=LOW, the internal oscillator frequency is fixed

internal setting 700 kHz.

6

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

(1) (2) (3)

otherwise noted)

PARAMETER

INPUT CURRENT REGULATION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{IREG_DPM}

Adapter current regulation differential

voltage range

V_{IREG_DPM}= V_ACP– V_ACN

0

100

mV

V

V_{ACSET_OP}

ACSET voltage range

0

–3%

VDAC

3%

V_{IREG_DPM}= 40 mV

V_{IREG_DPM}= 20 mV

V_{IREG_DPM}= 5 mV

V_{IREG_DPM}= 1.5 mV

–5%

5%

Input current regulation accuracy

Off-set Voltage of Amplifier

–25%

–33%

-500

25%

33%

500

μV

VREF REGULATOR

V_{VREF_REG}

VREF regulator voltage

VREF short current limit

V_ACDET> 0.6 V, 0-30 mA

3.267

35

3.3

5.9

3.333

80

V

I_{VREF_LIM}

V_VREF= 0 V, V_ACDET> 0.6 V

mA

REGN REGULATOR

V_{REGN_REG}

REGN regulator voltage

REGN short current limit

V_ACDET> 0.6 V, 0-75 mA, PVCC > 10 V

V_REGN= 0 V, V_ACDET> 0.6 V

5.6

90

6.2

V

I_{REGN_LIM}

145

mA

ADAPTER CURRENT SENSE AMPLIFIER

V_{ACP/N_OP}

V_IADAPT

I_IADAPT

Input common mode range

IADAPT output voltage range

IADAPT output current

Voltage on ACP/ACN

0

24

2

V

1

mA

V/V

A_IADAPT

Current sense amplifier voltage gain

A_IADAPT= V_IADAPT/ V_{IREG_DPM}

V_{IREG_DPM}= 40 mV

20

–2%

–4%

–25%

–33%

1

2%

4%

V_{IREG_DPM}= 20 mV

Adapter current sense accuracy

V_{IREG_DPM}= 5 mV

25%

33%

V_{IREG_DPM}= 1.5 mV

I_{IADAPT_LIM}

Output short current limit

V_IADAPT= 0 V

mA

pF

C_{IADAPT_MAX}

Maximum output load capacitance

For stability with 0 mA to 1 mA load

100

ACDET COMPARATOR (INPUT UNDER_VOLTAGE, ACVGOOD)

V_{ACDET_CHG}

ACDET adapter-detect rising threshold

ACDET falling hysteresis

Min voltage to enable charging, V_ACDETrising

V_ACDETfalling, PVCC>8V

2.376

2.40

40

2.424

V

V_{ACDET_CHG_HYS}

mV

ms

ACDET rising deglitch to turn on EXTPWR V_ACDETrising, PVCC>8V

FET⁽⁴⁾

1.2

(4)

ACDET rising deglitch to enable charge

V_ACDETrising, PVCC>8V, CE=HIGH

333

80

ms

ACDET falling deglitch to turn off EXTPWR V_ACDETfalling, PVCC>8V

FET⁽⁴⁾

μs

ACDET falling deglitch to disable charge⁽⁴⁾V_ACDETfalling, PVCC>8V

80

μs

T_{ACDET_EXTPWR}

Power-up delay from V_ACDET>2.4V to

EXTPWR FET turn-on⁽⁴⁾

First time power up, F_s= 300 kHz – 800 kHz

2

ms

AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT, ACIGOOD)

V_ACIDET

Adapter current detect falling threshold

Adapter current detect hysteresis

V_ACI= 20 X I_ACx R_AC, falling edge

Rising edge

200

250

50

300

mV

μs

V_{ACIDE_HYS}

IADAPT rising

10

Adapter current detect deglitch

IADAPT falling

10

μs

(4) Verified by design

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ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

(1) (2) (3)

otherwise noted)

PARAMETER

PVCC / BAT COMPARATOR

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{PVCC_BAT_OP}

V_{PVCC-BAT_FALL}

V_{PVCC-BAT__HYS}

Differential Voltage from PVCC to BAT

PVCC to BAT falling threshold

PVCC to BAT hysteresis

-20

850

200

24

950

250

V

V_PVCC– V_BATto disable charge

900

225

4.5

10

mV

ms

μs

PVCC to BAT rising deglitch

PVCC to BAT falling deglitch

V_PVCC– V_BAT> V_{PVCC-BAT_RISE}

V_PVCC– V_BAT< V_{PVCC-BAT_FALL}

BAT OVERVOLTAGE COMPARATOR

V_{OV_RISE}

Overvoltage rising threshold⁽⁵⁾

V_{OV_FALL}

Overvoltage falling threshold⁽⁵⁾

BATSHORT COMPARATOR

V_{BATSHORT_RISE}Battery rising voltage for BATSHORT exit

V_{BATSHORT_FALL}

As percentage of V_{BAT_REG}

104%

102%

2

V/Cell

Battery falling voltage for BATSHORT

entry

1.7

CHARGE OVERCURRENT COMPARATOR

V_{OC_peak}

Peak charge over-current threshold

V_{(CSP- CSN)}, when V_ISET/ VDAC < 0.8

90

110

125

130

150

mV

V_{(CSP- CSN)}, when V_ISET/ V_DAC≥ 0.8

100

MOSFET SHORT PROTECTION COMPARATOR

V_HS

V_LS

High-side Threshold (bq24741)

High-side Threshold (bq24742)

Low-side Threshold

Measured on ACP-SW

Measured on SW-AGND

120

475

90

250

750

160

455

1065

320

mV

CHARGE UNDERCURRENT PROTECTION COMPARATOR (UCP)

V_UCP

Charge under-current threshold, falling

edge

V_{(CSP- CSN)}from synchronous to non-synchronous

operation

25

35

30

40

35

45

mV

Charge under-current threshold, rising

edge

V_(CSP-CSN)from non-synchronous to synchronous

operation

Charge under-current rising deglitch

Charge under-current falling deglitch

10

μs

320

INPUT OVERVOLTAGE COMPARATOR (ACOV)

V_ACOV

AC over-voltage rising threshold on

ACDET

Measure on ACDET pin

Measured on PVCC pin

3.007

3.1

3.193

V

V_{ACOV_HYS}

AC over-voltage deglitch (rising edge)

AC over-voltage deglitch (falling edge)

650

μs

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

V_UVLO

AC under-voltage rising threshold

AC under-voltage hysteresis

7

8

9

V

V_{UVLO_HYS}

260

mV

INPUT LOW POWER MODE COMPARATOR (LPMOD)

V_{ACLP_HYS}

AC low power mode comparator internal

hysteresis

5%

7%

V_{ACLP_OFFSET}

AC low power mode comparator offset

voltage

1

mV

THERMAL SHUTDOWN COMPARATOR

T_SHUT

Thermal shutdown rising temperature

Thermal shutdown hysteresis, falling

Temperature Increasing

155

20

°C

T_{SHUT_HYS}

PWM HIGH SIDE DRIVER (HIDRV)

R_{DS_HI_ON}

High side driver turn-on resistance

V_BTST– V_SW= 5.5 V, tested at 100 mA

6

Ω

R_{DS_HI_OFF}

V_{BTST_REFRESH}

High side driver turn-off resistance

1.4

Bootstrap refresh comparator threshold

voltage

V_BTST– V_SWwhen low side refresh pulse is

requested

4

V

I_{BTST_LEAK}

BTST leakage current

High side is on; charge enabled

200

μA

(5) Verified by design

8

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ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, F_s=600 kHz, typical values are at T_A= 25°C, with respect to AGND (unless

(1) (2) (3)

otherwise noted)

PARAMETER

PWM LOW SIDE DRIVER (LODRV)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_{DS_LO_ON}

R_{DS_LO_OFF}

PWM DRIVERS TIMING

Driver Dead Time between HIDRV and

Low side driver turn-on resistance

REGN = 6 V, tested at 100 mA

6

Ω

Low side driver turn-off resistance

REGN = 6 V, tested at 100 mA

1.2

25

ns

LODRV

PWM OSCILLATOR

F_S

Programmable PWM switching frequency

range

R_FSET=130 kΩ - 45 kΩ

300

800

kHz

PWM switching frequency accuracy

RAMP amplitude

-20%

20%

1.33

300

V

DC offset of RAMP

mV

QUIESCENT CURRENT

Total off-state quiescent current into pins:

V_BAT= 16.8 V, V_ACDET< 0.6 V,

I_{OFF_STATE}

CSP, CSN, BAT, BTST, SW, PVCC, ACP, V_PVCC> 8 V, T_J= 0 to 125°C

ACN

7

11

1

μA

Total off-state battery current from ACP,

ACN

V_BAT= 16.8 V, V_ACDET< 0.6 V,

V_PVCC> 8 V, T_J= 0 to 125°C

μA

Battery on-state quiescent current

V_BAT= 16.8 , 0.6 V < V_ACDET< 2.4 V,

V_PVCC> 8V

I_{BAT_ON}

I_{BATQ_CD}

I_AC

1

mA

Total quiescent current into CSP, CSN,

BAT, PVCC, BTST, SW

Adapter present, V_ACDET> 2.4 V, charge disabled

100

1

200

1.5

μA

Adapter quiescent current

V_PVCC= 20 V, charge disabled

mA

INTERNAL SOFT START (8 steps to regulation current)

Soft start steps

8

step

Soft start time of each step (512 PWM

cycles)

853

μs

LOGIC INPUT PIN CHARACTERISTICS (CE, TRICKLE)

V_{IN_LO}

Input low threshold voltage

0.8

V

V_{IN_HI}

Input high threshold voltage

2.1

0.8

R_PULLDOWN

T_{CE_ENCHARGE}

PIN pull down resistance inside IC

Delay from CE=HIGH to charge enable⁽⁶⁾

V = 0 to V_REGN

1

2

MΩ

F_s=300 kHz - 800 kHz

ms

LOGIC INPUT PIN CHARACTERISTICS (CELLS)

V_{IN_LO}

Input low threshold voltage, 3 cells

Input float threshold voltage, 2 cells

CELLS voltage falling edge

0.5

1.8

CELLS voltage rising for MIN,

CELLS voltage falling for MAX

V_{IN_FLOAT}

V

V_{IN_HI}

Input high threshold voltage, 4 cells

CELLS voltage rising

VCE = 0 to VREGN

2.5

–1

I_{BIAS_FLOAT}

Input bias float current for 2 cell selection

1

μA

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR, DPMDET, LPMOD)

V_{OUT_LO}

Output low saturation voltage

Leakage current

Sink Current = 5 mA

Pull up to 3.3 v

0.5

1

V

μA

ms

DPMDET delay, both edge

5

(6) Verified by design

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TYPICAL CHARACTERISTICS

Table 2. Table of Graphs⁽¹⁾F_s=400 kHz, Ta = 25 °C

Y

X

Figure

VREF Load and Line Regulation

REGN Load and Line Regulation

BAT Voltage

vs Load Current

Figure 3

vs Load Current

Figure 4

vs VADJ/VDAC Ratio

vs Setpoint

Figure 5

BAT Voltage Regulation Accuracy

Charge Current

Figure 6

vs ISET/VDAC Ratio

vs V(CSP-CSN) Setpoint

vs ACSET/VDAC Radio

vs V(ACP-ACN) Setpoint

vs Charge Current

vs V(ACP-ACN) Voltage

vs BAT Voltage

Figure 7

Charge Current Regulation Accuracy

Input Current

Figure 8

Figure 9

DPM Accuracy

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

BAT Voltage Regulation Accuracy

V_IADAPT Accuracy

Trickle Charge Current

DPM and Charge Current

vs System Current

REF, REGN, and EXTPWR Startup (CE=HIGH)

Transient System Load (DPM) Response Transition

Transient Response of IADAPT and LPMOD

Battery Overcurrent Protection (OCP)

Battery to Ground Short Transition

Battery to Ground Short Protection

Charge Enable and Current Soft-Start

Charge Disable

Trickle Disable and Current Soft-Start

Synchronous to Non-synchronous Transition

Non-synchronous to Synchronous Transition

Continuous Conduction Mode Switching Waveforms

Near 100% Duty Cycle Bootstrap Recharge Pulse

Efficiency

vs Battery Charge Current

vs Setting Resistor

Switch Frequency

(1) Test results based on Figure 2 application schematic. V_IN= 20 V, V_BAT= 3-cell Li-Ion, I_CHG= 3 A, I_{ADAPTER_LIMIT}= 4 A, T_A= 25°C,

unless otherwise specified.

10

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VREF LOAD AND LINE REGULATION

REGN LOAD AND LINE REGULATION

vs

Load Current

LOAD CURRENT

0

0.50

0.40

-0.50

-1

0.30

0.20

0.10

PVCC = 10 V

-1.50

-2

PVCC = 10 V

0

PVCC = 20 V

-2.50

-3

-0.10

PVCC = 20 V

40 50

-0.20

0

10

20

30

40

50

0

10

20

30

60

70

80

VREF - Load Current - mA

REGN - Load Current - mA

Figure 3.

Figure 4.

BAT VOLTAGE

vs

BAT VOLTAGE REGULATION ACCURACY

vs

VADJ/VDAC RATIO

SETPOINT

0.06

13.6

0.05

0.04

3-Cell

13.4

13.2

13

0.03

0.02

0.01

12.8

12.6

0

12.4

12.2

12

-0.01

-0.02

12

12.2

12.4

12.6

12.8

13

13.2

13.4

13.6

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VADJ/VDAC Ratio

1

VBAT_reg Setpoint (V)

Figure 5.

Figure 6.

CHARGE CURRENT

vs

CHARGE CURRENT REGULATION ACCURACY

vs

ISET/VDAC

V(CSP-CSN) SETPOINT

5

25

4.5

3-Cell

4

3.5

3

20

15

10

5

2.5

2

1.5

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

10

20

30

40

50

60

70

80

90

100

ACSET/VDAC Ratio

ICHG_reg Setpoint (mV)

Figure 7.

Figure 8.

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INPUT CURRENT

vs

DPM ACCURACY

vs

ACSET/VDAC RATIO

V(ACP-ACN) SETPOINT

2

10

9

3-Cell

0

8

7

6

5

4

3

2

1

0

-2

-4

-6

-8

-10

0

10

20

30

40

50

60

70

80

90

100

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

IIN_reg Setpoint (mV)

VACSET/VDAC

Figure 9.

Figure 10.

BAT VOLTAGE REGULATION ACCURACY

V_IADAPT ACCURACY

vs

CHARGE CURRENT

V(ACP-ACN) VOLTAGE

0.030

0.025

0.020

0.015

0.010

0.005

0.00%

-0.50%

-1.00%

-1.50%

-2.00%

-2.50%

-3.00%

-3.50%

-4.00%

-4.50%

-5.00%

0.000

0

10

20

30

40

50

60

70

80

90

100

0

0.5

1

1.5

2

2.5

3

3.5

4

Charge Current (A)

V(ACP-ACN) (mV)

Figure 11.

Figure 12.

TRICKLE CHARGE CURRENT

DPM and CHARGE CURRENT

vs

BAT VOLTAGE

SYSTEM CURRENT

4.5

0.165

4

VBAT 0 V to 12.6 V

3.5

0.16

Input Current

3

2.5

0.155

2

1.5

1

Charge Current

0.15

VBAT 12.6 V to 0 V

0.5

0.145

0

2

4

6

8

10

12

14

0.5

1

1.5

2

2.5

3

3.5

4

BAT Voltage (V)

System Current (A)

Figure 13.

Figure 14.

12

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REF, REGN, and EXTPWR

STARTUP (CE=HIGH)

TRANSIENT SYSTEM LOAD

(DPM) RESPONSE TRANSITION

Isys

EXTPWR

I_IN

Ibat

Time = 200 μs/div

Time =400 μs/div

Figure 15.

Figure 16.

TRANSIENT RESPONSE

of

IADAPT and LPMOD

BATTERY OVERCURRENT PROTECTION

(OCP)

VBAT

ISYS

I_L

Iadapt

SW

LPMOD

LODRV

Time = 20 μs/div

Time = 100 μs/div

Figure 17.

Figure 18.

BATTERY TO GROUND

SHORT TRANSITION

BATTERY TO GROUND

SHORT PROTECTION

I_L

VBAT

Vbat

SW

LODRV

Time = 10 μs/div

Time = 2 ms/div

Figure 19.

Figure 20.

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CHARGE ENABLE

and

CURRENT SOFT-START

CHARGE DISABLE

CE

I_L

SW

LODRV

Time = 4 μs/div

Time = 2 ms/div

Figure 21.

Figure 22.

TRICKLE DISABLE

and

SYNCHRONOUS

to

CURRENT SOFT-START

NON-SYNCHRONOUS TRANSITION

TRICKLE

SW

LODRV

I_L

Time = 2 ms/div

Time = 2 μs/div

Figure 23.

Figure 24.

NON-SYNCHRONOUS

to

SYNCHRONOUS TRANSITION

CONTINUOUS CONDUCTION MODE

SWITCHING WAVEFORMS

SW

HIDRV

LODRV

SW

LODRV

I_L

Time = 200 ns/div

Time = 2 μs/div

Figure 25.

Figure 26.

14

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EFFICIENCY

vs

NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE PULSE

BATTERY CHARGE CURRENT

100

V

PH

4-Cell 16.8 V

95

90

85

80

V

HIDRV

3-Cell 12.6 V

V

LODRV

I

L

0

0.5

1

1.5

2

2.5

3

3.5

4

Time = 4 ms/div

Charge Current (A)

Figure 27.

Figure 28.

SWITCH FREQUENCY

vs

SETTING RESISTOR

1200

Measurment

Calculation

1000

800

600

400

200

0

50

100

150

200

250

300

R_FET (kOhm)

Figure 29.

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FUNCTIONAL BLOCK DIAGRAM

ENA_BIAS_CMP

-

0.6V

AC_VGOOD

AC_IGOOD

EXTPWR

-

2.4V

+

ACGOOD

+

ACDET

VREF

+

-

VAC20X

250mV

3.3V

LDO

ENA_BIAS

PVCC

VREFGOOD

+

-

UVLO

PVCC

+

EAI

BAT

PVCC-BAT

-

ACP

ACN

FBO

EAO

900mV

+

VAC20X

IIN_REG

IIN_ER

20X

+

-

CE

-

COMP

ERROR

AMPLIFIER

1 MΩ

BTST

CE

-

+

-

BAT_ER

ICH_ER

BAT

CSP

1V

VBAT_REG

VSR20X

LEVEL

SHIFTER

HIDRV

SW

3.5 mA

20 µA

DC-DC

CONVERTER

PWM LOGIC

+

20X

-

+

-

BAT_SHORT

CSN

PVCC-BAT

SYNCH

3.5 mA

20 µA

PVCC

AC_VGOOD

CLK

REGN

LODRV

PGND

IADAPT

CHRG_ON

6V LDO

IBAT_ REG

60mV

VREFGOOD

CE

REFRESH

TRICKLE

FSET

-

BTST

4V

CBTST

+

1 MΩ

+

_

OSC

CLK

SW

ACSET

SRSET

IC Tj

TSHUT

+

-

155 °C

+

-

VAC20X

V(IADAPT)

VBATSET

IBATSET

IINSET

VBAT_REG

IBAT_REG

IIN_REG

-

104% X VBAT_REG

BAT

BAT_OVP

+

VADJ

RATIO

PROGRAM

DPMDET

DPM_LOOP_ON

-

2.08 V / 2.5 V

VSR20X

CHG_OCP

ACOV

+

VDAC

+

-

VSR20X

30mV

SYNCH

ACDET

+

-

CELLS

+

-

3.1V

VAC20X

+

-

+

-

1.7 V

BAT

BAT_SHORT

LPREF

PVCC

-

AGND

PGND

UVLO

+

LPMOD

+

8V

-

bq24741/2

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DETAILED DESCRIPTION

Converter Operation

The synchronous buck PWM converter uses a programmable-frequency (300 kHz to 800 kHz) voltage mode

control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter.

The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier

input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error

amplifier output (EAO). The LC output filter should be selected to give a nominal resonant frequency within 8 kHz

to 12.5 kHz to have good loop compensation.

Where resonant frequency, f_o, is give by:

1

f_o=

2p L_oC_o

(1)

Where L_o, C_oare the total output filter inductance and capacitance

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the

converter. The ramp height is fixed 1.33 V. The ramp is offset by 300 mV in order to allow zero percent

duty-cycle, when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth

ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98%

duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin

to SW pin voltage falls below 4 V, then the high-side n-channel power MOSFET is turned off and the low-side

n-channel power MOSFET is turned on to pull the SW node down and recharge the BTST capacitor. Then the

high-side driver returns to 100% duty-cycle operation until the (BTST-SW) voltage is detected to fall low again

due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.

The oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,

charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.

The charge current sense resistor RSR should be placed with at least half or more of the total output capacitance

placed before the sense resistor contacting both sense resistor and the output inductor; and the other half or

remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed

onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives the best performance; but the

node in which the output inductor and sense resistor connect should have a minimum of 50% of the total

capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current

sense accuracy. The type III compensation provides Phase boost near the cross-over frequency, giving sufficient

Phase margin.

Synchronous and Non-Synchronous Operation

The charger operates in non-synchronous mode when the sensed charge current is below the charge

under-current comparator threshold (30 mV). Otherwise, the charger operates in synchronous mode. This part is

designed for 20 mΩ charge current sense resistor and the SYNC/NON-SYNC threshold is 1.5 A. If 10 mΩ is

used, the SYNC/NON-SYNC threshold will be 3 A.

During synchronous mode, the low-side n-channel power MOSFET is on, when the high-side n-channel power

MOSFET is off. The internal gate drive logic ensures there is break-before-make switching to prevent

shoot-through currents. During the 25 ns dead time where both FETs are off, the back-diode of the low-side

power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low,

and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and

operates in Continuous Conduction Mode (CCM), creating a fixed two-pole system.

During non-synchronous operation, the low side MOSFET will stay off during the off-time unless the voltage on

the bootstrap capacitor drops below 4 V. If this occurs, the high side FET will be turned off and the 80ns low-side

MOSFET recharge pulse will be initiated. The 80 ns pulse pulls the SW node (connection between high and

low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80

ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The inductor current is

blocked by the off low-side MOSFET, and the inductor current will become discontinuous. This mode is called

Discontinuous Conduction Mode (DCM).

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During the DCM mode the loop response automatically changes and has a single pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means at very low currents the loop response is slower, as there is less sinking current

available to discharge the output voltage. At very low currents during non-synchronous operation, there may be a

small amount of negative inductor current during the 80ns recharge pulse. The charge should be low enough to

be absorbed by the input capacitance.

Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the

low-side MOSFET does not turn on (no 80ns recharge pulse) either, and there is no discharge from the battery.

Battery Voltage Regulation

The bq24741/2 uses a high-accuracy voltage regulator for charging voltage. The regulation voltage is ratio-metric

with respect to VDAC. The ratio of VADJ and VDAC provides extra 12.5% adjust range on V_BATTregulation

voltage. By limiting the adjust range to 12.5% of the regulation voltage, the external resistor mismatch error is

reduced from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, while using

1% mis-match resistors. Ratio-metric conversion also allows compatibility with D/As or microcontrollers (μC). The

battery voltage is programmed through VADJ and VDAC using the following equation:

é

ù

ú

û

æ

ö

÷

ø

V_VADJ

V_BATT= cell count ´ 4 V + 0.512´

ê

ç

V_VDAC

ê

ë

è

(2)

The input voltage range of VDAC is between 2.6V and 3.6V. VADJ is set between 0 and VDAC.

CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2, 3, or 4 Li+ cells. When

charging other cell chemistries, use CELLS to select an output voltage range for the charger.

Table 3. Cell-Count Selection

CELLS

Float

CELL COUNT

2

3

4

AGND

VREF

The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to

determine this voltage.

The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the

battery as possible, or directly on the output capacitor. A 0.1μF ceramic capacitor from BAT to AGND is

recommended to be as close to the BAT pin as possible to decouple high frequency noise.

Battery Current Regulation

The ISET input sets the maximum charging current. Battery current is sensed by resistor RSR connected

between CSP and CSN. The full-scale differential voltage between CSP and CSN is 100 mV. Thus, for a 0.020 Ω

sense resistor, the maximum charging current is 5 A. ISET is ratio-metric with respect to VDAC using the

following equation:

V

0.10

ISET

´

I_CHARGE

=

V_VDACR_SR

(3)

The input voltage range of ISET is between 0 and VDAC, up to 3.6 V.

The CSP and CSN pins are used to sense across R_SRwith default value of 20 mΩ. However, resistors of other

values can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation

accuracy; but, at the expense of higher conduction loss.

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Trickle Charge Current Regulation

The TRICKLE pin is provided to allow accurate current regulation at very low charge current. When CE is set to

HIGH, a logic HIGH level is applied to the TRICKLE pin, the charger will regulate 3 mV from CSP to CSN (150

mA with a 20 mΩ sense resistor), regardless of the voltage applied to the ISET pin. When TRICKLE is LOW,

ISET is used to program the charge current.

Input Adapter Current Regulation

The total input current from an AC adapter or other DC sources is a function of the system supply current and

the battery charging current. System current normally fluctuates as portions of the systems are powered up or

down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system

current and the maximum charger input current simultaneously. By using DPM, the input current regulator

reduces the charging current when the input current exceeds the input current limit set by ACSET. The current

capacity of the AC adapter can be lowered, reducing system cost.

Similar to setting battery-regulation current, adapter current is sensed by resistor R_ACconnected between ACP

and ACN. Its maximum value is set by ACSET, which is ratiometric with respect to VDAC, using Equation 4.

V_ACSET

´

0.10

I_ADAPTER

=

V_VDACR_AC

(4)

The input voltage range of ACSET is between 0 and V_DAC, up to 3.6 V.

The ACP and ACN pins are used to sense R_ACwith a default value of 10 mΩ. However, resistors of other values

can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.

However, this is at the expense of a higher conduction loss.

Adapter Detect and Power Up

An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter detect

threshold should typically be programmed to a value greater than the maximum battery voltage and lower than

the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense

the true adapter input voltage whether the ACFET is on or off.

If ACDET is below 0.6 V but PVCC is above 8 V, part of the bias is enabled, including a crude bandgap

reference, IADAPT is disabled and pulled down to GND. The total quiescent current is less than 10 μA.

Once ACDET rises above 0.6 V and PVCC is above 8 V, all the bias circuits are enabled and VREF goes to 3.3

V; and REGN output goes to 6 V if CE is HIGH. IADAPT becomes valid to proportionally reflect the adapter

current.

When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 8 ms later, charge is allowed to turn

on.

Programming the PWM Switching Frequency

To program the PWM switching frequency, place a resistor from the FSET pin to ground, according to the

following formula:

41´10³

R_FSET

=

- 6.25 (kW)

F_s

(5)

Where R_FSET(kΩ) is the resistor from the FSET pin to ground, and F_s(kHz) is the desired switching frequency.

The switching frequency should be programmed between 300 kHz and 800 kHz.

Enable and Disable Charging

The following conditions must be valid before the charge function is enabled:

•

CE is HIGH

Adapter is detected

Adapter voltage is higher than PVCC-BAT threshold

Adapter is not over voltage

The VREF and REGEN regulators are above 90% of the final values

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•

Thermal Shut (TSHUT) is not active

The PWM frequency is programmed inside the allowable range

There’s a 2ms charge enable delay from when adapter is detected to when the charger is allowed to turn on.

One of the following conditions will stop on-going charging:

•

CE is LOW

Adapter is removed

Adapter Voltage is lower than PVCC-BAT threshold

Adapter is over voltage

Adapter is over current

TSHUT IC temperature threshold is reached (155 °C on rising-edge with 20 °C hysteresis).

Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure

there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of

stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each

step lasts around 1ms, for a typical rise time of 8ms. No external components are needed for this function.

High Accuracy IADAPT Using Current Sense Amplifier (CSA)

An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the

host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input

sensed voltage of ACP–ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times

the input differential voltage. Once PVCC is above 8 V and ACDET is above 0.6 V, IADAPT no longer stays at

ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT to

AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.

Input Overvoltage Protection (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage is 30%

above adapter detect voltage, (ACDET pin voltage is 30% above 2.4 V (2.4 V X 130% = 3.1 V), charge is

disabled. ACOV does not latch, and normal operation resumes when ACDET < 3.1 V.

Input Undervoltage Lock Out (UVLO)

The system must have a typical 8 V PVCC voltage to allow proper operation. This PVCC voltage could come

from an input adapter . When the PVCC voltage is below 8 V the bias circuits REGN and VREF stay inactive,

even with ACDET above 0.6 V.

Battery Overvoltage Protection

The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 102% of the regulation

voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed

or the battery is disconnected.

Charge Overcurrent Protection

The charger has a secondary over-current protection. It monitors the charge current, and prevents the current

from exceeding 6.25A peak value with a 20 mΩ sensing resistor. The high-side gate drive turns off when the

over-current is detected, and automatically resumes at the next switching cycle that occurs after the current falls

below the OCP threshold. When the BAT-GND short is detected, the charger will be automatically shut down

immediately and then restarts again 100 μs later.

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Short-Circuit Protection

The charger has a secondary short-circuit protection. It monitors the voltage-drop (detect ACP-SW for protecting

high-side MOSFET and detect SW-AGND for protecting low-side MOSFET) to prevents the short-circuit current

from exceeding a certain value to damage the charger. It will be monitored after typical blanking time of 100ns.

The MOSFET gate driver signal turns off when the short-circuit current is detected in every switching cycle. The

charger will shut-down and latch off after this occurs 7 times. POR or toggling CE pin can resume normal charge

function.

Thermal Shutdown Protection

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the

ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and

self-protects whenever the junction temperature exceeds the TSHUT threshold of 155 °C. The charger stays off

until the junction temperature falls below 135 °C, then the charger will soft-start again if all other enable charge

conditions are valid.

Input Low Power Detection

In order to optimize the system performance, the HOST keeps an eye on the adapter current. Once the adapter

current is above a threshold set via LPREF, the LPMOD pin sends a signal to the HOST. The signal alarms the

host that input power has exceeded the programmed limit. The LPMOD pin is an open-drain output. Connect a

pull-up resistor to LPMOD. The LPMOD output is logic LOW when the 20X current sense voltage (20 x

V_(ACP-ACN)) is higher than the LPREF input voltage. The LPREF threshold may be set by an external resistor

divider using VREF, or may be programmed from a resistor divider off of ACSET to maintain an LPREF voltage

proportional to the adapter current. The LPMOD comparator has an internal 6% hysteresis built in.

ACDET

AC_VGOOD

+

-

2.4 V

ACVDET

Comparator

EXTPWR

ACP

ACN

Adaptor

Current Sense

Amplifier

1 kΩ

+

-

ACIDET

Comparator

250 mV

(1.25 A)

-

AC_IGOOD

+

IADAPT Error

Amplifier

Disable

20 kΩ

20xV(ACP-ACN)

-

IADAPT

+

IADAPT

Disable

IADAPT

OUTPUT

BUFFER

LPMOD

Comparator

LPMOD

+

-

LOPWR_DET

LPREF

Hysteresis = 6%

Figure 30. EXTPWR , LPREF, and LPMOD Logic

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Status Outputs ( EXTPWR , LPMOD , DPMDET Pin)

Three status outputs are available, and they all require external pull up resistors to pull the pins to system digital

rail for a high level.

EXTPWR open-drain output goes low under each of the three conditions:

1. ACDET is above 2.4 V

2. Adapter current is above 1.25 A using a 10mohm sense resistor (IADAPT voltage above 250 mV)

Internally, the AC current detect comparator looks between the output of the 20x adapter current amplifier and an

internal 250mV threshold. EXTPWR indicates a good adapter is connected because of valid voltage or current.

LPMOD output goes low when the input current is higher than the programmed threshold via LPREF pin.

Hysteresis is internally set to 6% of the programmed LPMOD threshold.

DPMDET open-drain output goes low when the DPM loop is active to reduce the battery charge current.

Table 4. Component List for Typical System Circuit of Figure 1

PART DESIGNATOR

QTY

3

DESCRIPTION

Q1, Q2, Q3

P-channel MOSFET, -30V,-6A, SO-8, Vishay-Siliconix, Si4435

N-channel Dual-MOSFET, 30V, 7.5A, SO-8, Fairchild, FDS8978

Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C

Sense Resistor, 10mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0100F

Sense Resistor, 20mΩ, 1%, 1W, 2010, Vishay-Dale, WSL2010R0200F

Inductor, 10μH, 24.8mΩ Vishay-Dale, IHLP5050CE-01

Capacitor, Ceramic, 2.2μF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E225M

Capacitor, Ceramic, 10μF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M

Capacitor, Ceramic, 1μF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K

Capacitor, Ceramic, 100nF, 25V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU

Capacitor, Ceramic, 0.1μF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU

Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0805, Kemet, C0805C101K5RACTU

Resistor, Chip, 464kΩ, 1/16W, 1%, 0402

Q4

1

D1, D2

2

R_AC

1

R_SR

1

L1

1

C1

1

C6, C7, C11, C12

4

C4, C10

2

C13

1

C2, C3, C8, C9, C13, C14, C15, C16

6

C5

1

R1

1

R2

1

Resistor, Chip, 66.5kΩ, 1/16W, 1%, 0402

R3, R4, R5, R15

4

Resistor, Chip, 10kΩ, 1/16W, 5%, 0402

R6

1

Resistor, Chip, 97.6kΩ, 1/16W, 1%, 0402

R7

1

Resistor, Chip, 73.2kΩ, 1/16W, 1%, 0402

R8

1

Resistor, Chip, 26.7kΩ, 1/16W, 1%, 0402

R9

1

Resistor, Chip, 60.4kΩ, 1/16W, 1%, 0402

R10

R11

R12

R13

R14

1

Resistor, Chip, 40.2kΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 2Ω, 1W, 5%, 2012

1

Resistor, Chip, 102kΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 64.9kΩ, 1/16W, 1%, 0402

1

Resistor, Chip, 120kΩ, 1/16W, 1%, 0402

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APPLICATION INFORMATION

Inductor Selection

The bq24741/2 can program the switching frequency between 300k and 800kHz for different applications. Higher

switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should

be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I

³ I

+ (1/2) I

SAT

CHG RIPPLE

(6)

The inductor ripple current depends on input voltage (V_IN), duty cycle (D=V_OUT/V_IN), switching frequency (f_s) and

inductance (L):

V

´ D ´ (1 - D)

IN

I_RIPPLE

=

f_S´ L

(7)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging

voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the

maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to

16.8V, and 12V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between

inductor size and efficiency for a practical design.

The bq24741/2 has charge under current protection (UCP) by monitoring charging current sensing resistor. The

Typical UCP threshold is 30mV falling edge and 40mV rising edge corresponding to 1.5A falling edge and 2A

rising edge for a 20mΩ charging current sensing resistor. To prevent negative inductor current, the inductance

must be high enough so that peak to peak ripple current is less than 3A (for a 20mΩ charging current sensing

resistor) when charging current tapers down. Considering UCP threshold tolerance for worst case, peak to peak

ripple current less than 2.5A for a 20mΩ charging current sensing resistor is preferred.

Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at

50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and

can be estimated by the following equation:

I_CIN= I_CHG

´

D ´ (1-D)

(8)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred

for 19-20V input voltage. 10-20µF capacitance is suggested for typical of 3-4A charging current.

Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current is given:

I

RIPPLE

I

=

» 0.29 ´ I

RIPPLE

COUT

2 ´

3

(9)

The bq24741/2 has internal loop compensator. To get good loop stability, the resonant frequency of the output

inductor and output capacitor should be designed between 8 kHz and 12.5 kHz.

The preferred ceramic capacitor is 25V, X7R or X5R for output capacitor. 10-20µF capacitance is suggested for

practical application. Two capacitors, one capacitor is located before and another one after charging current

sensing resistor to get the best average charge current regulation accuracy.

Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are

internally integrated into the IC with 5.9V of gate drive voltage. 30V or higher voltage rating MOSFETs are

preferred for 19-20V input voltage.

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Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction

loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,

R_DS(ON), and the gate-to-drain charge, Q_GD. For bottom side MOSFET, FOM is defined as the product of the

MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

FOM_top= R_DS(on)´ Q_GD

FOM_bottom= R_DS(on)´ Q_G

(10)

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON)has higher cost with the same

package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle

(D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance ®_DS(ON)), input voltage (V_IN), switching frequency

(F), turn on time (t_on) and turn off time (t_toff):

1

2

= D ´ I_CHG´ R_DS(on)

P

+

´ V ´ I_CHG

´

t_on+ t_off´ f

S

(

)

top

IN

2

(11)

The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100ºC junction

temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are

given by:

Q

SW

t

=

, t

=

off

on

I

on

off

(12)

where Q_swis the switching charge, I_onis the turn-on gate driving current and Ioff is the turn-off gate driving

current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge

(Q_GD) and gate-to-source charge (Q_GS):

1

Q

= Q

+

´ Q

GS

SW

GD

2

(13)

Gate driving current total can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total

turn-on gate resistance (Ron) and turn-off gate resistance ®_off) of the gate driver:

V_REGN- V_plt

V_plt

I_on

=

, I_off=

R_on

R_off

(14)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in

synchronous continuous conduction mode:

2

= (1 - D) ´ I_CHG´ R_DS(on)

P

bottom

(15)

When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the

freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss

depends on its forward voltage drop (V_F), non-synchronous mode charging current (I_NONSYNC), and duty cycle (D).

P = V_F´ I_NONSYNC´ (1 - D)

D

(16)

The maximum charging current in non-synchronous mode can be up to 2.25A for a 20mΩ charging current

sensing resistor considering IC UCP threshold tolerance. The minimum duty cycle happens at lowest battery

voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the

maximum non-synchronous mode charging current.

Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second

order system. The voltage spike at PVCC pin maybe beyond IC maximum voltage rating and damage IC. The

input filter must be carefully designed and tested to prevent over voltage event on PVCC pin.

There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic

capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin

voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.

However these two solutions may not have low cost or small size.

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A cost effective and small size solution is shown in Figure 31. The R1 and C1 is composed of a damping RC

network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used

for reverse voltage protection for PVCC pin. C2 is PVCC pin decoupling capacitor and it should be place to

PVCC pin as close as possible. C2 value should be much less than C1 value so R1 can dominant the equivalent

ESR value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage

when adapter hot plug-in. R1 has high inrush current. R1 package must be sized enough to handle inrush

current power loss according to resistor manufacturer’s datasheet. The filter components value always need to

be verified with real application and minor adjustments may need to fit in the real application circuit.

D1

(1206)

R2

4.7-30W

R1

2 W

(2010)

Adapter

connector

PVCC pin

C1

2.2 mF

C2

0.1-1 mF

Figure 31. Input Filter

bq24741/2 Design Guideline

The bq24741/2 has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is

achieved through monitoring the voltage drop across Rdson of the MOSFETs after a certain amount of blanking

time. In case of MOSFET short or inductor short circuit, the over current condition is sensed by two comparators

and two counters will be triggered. After seven times of short circuit events, the charger will be latched off. The

way to reset the charger from latch-off status is to toggle the CE pin or IC power on reset. Figure 32 shows the

bq24741/2 short circuit protection block diagram.

Adapter

ACN

R

BTST

ACP

PCB

AC

High-Side

MOSFET

SCP1

L

R

SR

SW

REGN

Battery

Low-Side

MOSFET

COMP1

SCP2

COMP2

Count to 7

CLR

Latch off

Charger

Charge

Enable

Function

Figure 32. Block Diagram of bq24741/2 Short Circuit Protection

In normal operation, low side MOSFET current is from source to drain which generates negative voltage drop

when it turns on, as a result the over current comparator can not be triggered. When high side switch short circuit

or inductor short circuit happens, the large current of low side MOSFET is from drain to source and can trig low

side switch over current comparator. the bq24741/2 senses low side switch voltage drop by SW pin and AGND

pin.

The high-side FET short is detected by monitoring the voltage drop between ACP and SW. As a result, it not only

monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and PCB trace

voltage drop from ACN terminal of R_ACto charger high side switch drain. Usually, there is a long trance between

input sensing resistor and charger converting input, a careful layout will minimize the trace effect.

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To prevent unintentional charger shut down in normal operation, MOSFET R_DS(on)selection and PCB layout is

very important. Figure 33 shows a need improve PCB layout example and its equivalent circuit. In this layout,

system current path and charger input current path is not separated, as a result, the system current causes

voltage drop in the PCB copper and is sensed by IC. The worst layout is when a system current pull point is after

charger input; as a result all system current voltage drops are counted into over current protection comparator.

The worst case for IC is the total system current and charger input current sum equals DPM current. When

system pull more current, the charger IC tries to regulate R_ACcurrent as a constant current by reducing charging

current.

I

DPM

R

System Path PCB Trace

AC

System current

I

SYS

R

AC

PCB

I

CHRGIN

Charger input current

Charger Input PCB Trace

ACP

ACN

Charger

I

BAT

To ACP

To ACN

(a) PCB Layout

(b) Equivalent Circuit

Figure 33. Need Improve PCB Layout Example

Figure 34 shows the optimized PCB layout example. The system current path and charge input current path is

separated, as a result the IC only senses charger input current caused PCB voltage drop and minimized the

possibility of unintentional charger shut down in normal operation. This also makes PCB layout easier for high

system current application.

R

AC

System Path PCB Trace

I

DPM

I

SYS

System current

Single point connection at R

Charger input current

AC

R

PCB

AC

I

CHRGIN

ACP

ACN

I

Charger

BAT

To ACN

Charger Input PCB Trace

To ACP

(a) PCB Layout

(b) Equivalent Circuit

Figure 34. Optimized PCB Layout Example

The total voltage drop sensed by IC can be express as the following equation.

= R ´ I + R + I - I ´ k + R

V

´

I

(

´ I

DS(on) PEAK

(

)

top

AC

DPM

PCB

CHRGIN

DPM

CHRGIN

(17)

where the R_ACis the AC adapter current sensing resistance, I_DPMis the DPM current set point, R_PCBis the PCB

trace equivalent resistance, I_CHRGINis the charger input current, k is the PCB factor, R_DS(on)is the high side

MOSFET turn on resistance and I_PEAKis the peak current of inductor. Here the PCB factor k equals 0 means the

best layout shown in Figure 34 where the PCB trace only goes through charger input current while k equals 1

means the worst layout shown in Figure 33 where the PCB trace goes through all the DPM current. The total

voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut

down in normal operation.

PCB Layout

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Figure 35) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper

layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use

shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on

different layers and using vias to make this connection.

2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal

traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching

26

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

MOSFETs.

3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to

carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop

area) and do not route the sense leads through a high-current path (see Figure 36 for Kelvin connection for

best current accuracy). Place decoupling capacitor on these traces next to the IC.

5. Place output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor

ground before connecting to system ground.

7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC

use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

8. Route analog ground separately from power ground. Connect analog ground to AGND and connect power

ground to PGND separately. Connect analog ground and power ground together using power pad as the

single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground (power pad

should tie to analog ground in this case).

9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

11. The via size and number should be enough for a given current path.

L1

R1

V

BAT

SW

High

Frequency

Current

Path

V

BAT

IN

C2

C3

C1

PGND

Figure 35. High Frequency Current Path

Charge Current Direction

R

SNS

To Inductor

To Capacitor and battery

Current Sensing Direction

To CSP - CSN pin or ACP - ACN pin

Figure 36. Sensing Resistor PCB Layout

Refer to the EVM design (SLUU284) for the recommended component placement with trace and via locations.

For the QFN information, refer to SCBA017 and SLUA271.

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

www.ti.com

REVISION HISTORY

Changes from Revision A (March 2009) to Revision B

Page

•

Changed 8 V to 9 V .............................................................................................................................................................. 1

Changed "Cells pin support two to for Li-Ion cells up to 18 V battery voltage" to Support two to four cells ........................ 1

Added "FET/Inductor/Battery Short Protection" .................................................................................................................... 1

Added "Loop Compensation" ................................................................................................................................................ 1

Deleted "Internal Loop Compensation" bullet ....................................................................................................................... 1

Added "Quiescent Current" ................................................................................................................................................... 1

Added 10Ω R16 to top of schematic ..................................................................................................................................... 2

Added 10Ω R16 to top of schematic ..................................................................................................................................... 3

Changed bq24742RHDR to bq24742RHDT ......................................................................................................................... 3

Changed 8.0 V to 9.0 V in condition values ......................................................................................................................... 6

Changed min voltage from 8 to 9 for V_{PVCC_OP}parameter .................................................................................................... 6

Deleted VBAT_OP parameter from this section ................................................................................................................... 6

Changed 8.0 V to 9.0 V in condition values ......................................................................................................................... 7

Changed 8.0 V to 9.0 V in condition values ......................................................................................................................... 8

Changed "Short Circuit" to "MOSFET short" ........................................................................................................................ 8

Changed VLS max value from 280 to 320 ........................................................................................................................... 8

Changed all instances of V_PHto V_SWin following section ..................................................................................................... 8

Changed 8.0 V to 9.0 V in condition values ......................................................................................................................... 9

Deleted VCC pin ................................................................................................................................................................... 9

Added graph: "Near 100% Duty Cycle.." ............................................................................................................................ 15

Changed polarity of IIN_ER, BAT_ER, and ICH_ER op amps ........................................................................................... 16

Added text note under equation .......................................................................................................................................... 17

Changed 8ms to 2ms .......................................................................................................................................................... 20

Changed "This PVCC voltage could come from either input adapter or battery, using a diode-OR input." ....................... 20

Added then the charger will soft-start again if all other enable change conditions are valid. ............................................. 21

Added added text, equations and illustrations from Inductor Selection to PCB Layout ..................................................... 23

28

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PACKAGE OPTION ADDENDUM

www.ti.com

8-Dec-2009

PACKAGING INFORMATION

Orderable Device

BQ24741RHDR

BQ24741RHDT

BQ24742RHDR

BQ24742RHDT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RHD

28

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

VQFN

RHD

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Dec-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24741RHDR

BQ24741RHDT

BQ24742RHDR

BQ24742RHDT

VQFN

RHD

28

3000

250

330.0

180.0

330.0

180.0

12.4

5.3

1.5

8.0

12.0

Q2

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Dec-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24741RHDR

BQ24741RHDT

BQ24742RHDR

BQ24742RHDT

VQFN

RHD

28

3000

250

346.0

210.0

346.0

210.0

346.0

185.0

346.0

185.0

29.0

35.0

29.0

35.0

250

3000

250

Pack Materials-Page 2

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型号：	BQ24742RHDT
厂家：	TEXAS INSTRUMENTS
描述：	1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28, 5 X 5 MM, GREEN, PLASTIC, QFN-28
文件：	总35页 (文件大小：1535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24742RHDT [TI]

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