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bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

bq25120A 适用于可穿戴设备和物联网的低 I_Q高度集成式电池充电管理解

决方案

1 特性

3 说明

1

•

延长了系统在充电之后的运行时间

bq25120A 是一款高度集成的电池充电管理 IC，集成

了可穿戴设备的最常用功能：线性充电器、稳压输出、

负载开关、通过计时器手动复位以及电池电压监测。该

集成降压转换器是一款具有低 I_Q的高效率开关，其采

用 DCS 控制技术，可进一步提升轻载效率，负载电流

可低至 10µA。运行和关断期间的低静态电流有助于延

长电池寿命。该器件支持 5mA 至 300mA 的充电电

流。输入电流限制、充电电流、降压转换器输出电压、

LDO 输出电压等参数均可通过 I²C 接口进行编程。

–

可配置的 300mA 降压稳压器

（默认电压为 1.8V）

使能降压稳压器（无负载）时的 Iq 为 700nA

（典型值）

可配置的负载开关或 100mA 低压降 (LDO) 输

出（默认采用负载开关）

–

快速充电电流高达 300mA

电池稳压精度为 0.5%（可配置电压范围为 3.6V

至 4.65V，阶跃为 10mV）

器件信息⁽¹⁾

–

可配置的终止电流低至

500µA

器件型号

BQ25120A

封装

封装尺寸（标称值）

DSBGA (25)

2.50mm x 2.50mm

基于电压的简单电池监视器

•

采用小型封装的高度集成解决方案

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

–

2.5mm x 2.5mm WCSP 封装，采用 6 个外部组

件以实现最小尺寸的解决方案

简化原理图

–

通过可调节计时器实现按钮唤醒和复位

电源路径管理可用于系统供电和电池充电

PG

IN

PMID

Unregulated

Load

电源路径管理功能可实现低于 50nA 的运输模式

电池静态电流，以最大程度延长货架存放期

–

电池充电器的工作电压为 3.4V – 5.5 V_IN（5.5V

过压保护 (OVP)/20V 耐压）

VINLS

BQ2512x

GND

SYS

SW

提供专用于输入电流限制、充电电流、终止电流

和状态输出的引脚

MCU /

SYSTEM

CD

HOST

SDA

SCL

INT

•

I²C 通信控制

LS / LDO

BAT

–

充电电压和电流

<100mA

Load

终止阈值

RESET

LSCTRL

输入电流限制

VINDPM 阈值

定时器选项

MR

IPRETERM

ISET

TS

IN

NTC

ILIM

负载开关控制

控制故障中断和状态

系统输出电压调节

LDO 输出电压调节

2 应用

•

智能手表及其他可穿戴设备

健身配件

健康状况监控医疗配件

可再充电玩具

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSD08

bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

9.2 Functional Block Diagram ....................................... 17

9.3 Feature Description................................................. 18

9.4 Device Functional Modes........................................ 31

9.5 Programming .......................................................... 33

9.6 Register Maps ........................................................ 36

10 Application and Implementation........................ 47

10.1 Application Information.......................................... 47

10.2 Typical Application ............................................... 47

11 Power Supply Recommendations ..................... 62

12 Layout................................................................... 63

12.1 Layout Guidelines ................................................. 63

12.2 Layout Example .................................................... 63

13 器件和文档支持 ..................................................... 64

13.1 器件支持................................................................ 64

13.2 商标....................................................................... 64

13.3 静电放电警告......................................................... 64

13.4 Glossary................................................................ 64

14 机械、封装和可订购信息....................................... 64

1

2

3

4

5

6

7

8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Electrical Characteristics........................................... 8

8.6 Timing Requirements ............................................. 12

8.7 Typical Characteristics............................................ 15

Detailed Description ............................................ 17

9.1 Overview ................................................................. 17

9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (May 2017) to Revision A

Page

•

已更改 expression terms in 公式 3 and 公式 4 for clarification. ........................................................................................... 26

2

bq25120A

www.ti.com.cn

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

5 说明（续）

该器件采用标准锂离子充电曲线分三个阶段对电池进行充电：预充电、恒流和恒压该器件包含一个基于电压的

JEITA 兼容电池组热敏电阻监视输入 (TS)，可监视电池温度并自动更改充电参数，从而防止电池在超出其安全温度

范围的温度下充电。该充电器针对 5V USB 输入进行了优化，可承受 20V 线路瞬态电压。降压转换器由输入或电

池供电。当处于仅电池模式时，器件可由电压最高达 4.65V 的电池供电运行。

利用可配置负载开关，器件可断开与不常用器件的连接，从而优化系统。通过定时器手动复位可实现多种优化唤醒

和复位的不同配置选项。

6 Device Comparison Table

DEFAULT

CHARGE

CURRENT

DEFAULT

TERMINATION

CURRENT

DEFAULT SYS DEFAULT LDO

DEFAULT

VBERG

DEFAULT SHIP

MODE

PART NUMBER

VINDPM

OUTPUT

BQ25120A

Enabled

1.8 V

Load Switch

4.2 V

10 mA

2 mA

Off

3

bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

7 Pin Configuration and Functions

YFP Package

25-Pin DSBGA

Top View

1

2

3

4

5

A

IN

GND

PMID

SW

VINLS

/PG

PGND

SYS

B

BAT

ILIM

INT

/CD

C

LS/LDO

GND

ISET

TS

IPRETE

D

RESET

LSCTRL

RM

E

/MR

SDA

SCL

Pin Functions

I/O

DESCRIPTION

NAME

NO.

DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with

at least 1 µF of capacitance using a ceramic capacitor.

IN

A2

I

High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias

derating from PMID to GND as close to the PMID and GND pins as possible. When entering

Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.

PMID

A3, B3

I/O

GND

A1, D5

A5

Ground connection. Connect to the ground plane of the circuit.

Power ground connection. Connect to the ground plane of the circuit. Connect the output

filter cap from the buck converter to this ground as shown in the layout example.

PGND

Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or

enable charging when V_INis valid. Drive CD high for Active Battery mode when battery only

is present, and disable charge when V_INis present. CD is pulled low internally with 900 kΩ.

CD

E2

I

SDA

SCL

E4

E5

I/O

I

I²C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.

I²C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.

Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to

program the input current limit. The input current includes the system load and the battery

charge current. Connect ILIM to GND to set the input current limit to the internal default

threshold. ILIM can also be updated through I²C.

ILIM

C2

E3

I

Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to

disable the LS/LDO output.

LSCTRL

Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program

the fast-charge current level. Connect a resistor from ISET to GND to set the charge current

to the internal default. ISET can also be updated through I²C. While charging, the voltage at

ISET reflects the actual charging current and can be used to monitor charge current if an

ISET resistor is present and the device is not in host mode.

ISET

C1

I

4

bq25120A

www.ti.com.cn

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to

GND to program the termination current between 5% and 20% of the charge current. The

pre-charge current is the same as the termination current setting. Connect IPRETERM to

GND to set the termination current to the internal default threshold. IPRETERM can also be

updated through I²C.

IPRETERM

D1

I

Status Output. INT is an open-drain output that signals charging status and fault interrupts.

INT pulls low during charging. INT is high impedance when charging is complete, disabled,

or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as

an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT

bit in the control register. Connect INT to a logic rail using an LED for visual indication of

charge status or through a 100kΩ resistor to communicate with the host processor.

INT

PG

D2

D4

O

Open-drain Power Good status indication output. PG pulls to GND when V_INis above V_(BAT)

+ V_SLPand less that V_OVP. PG is high-impedance when the input power is not within

specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,

or use with an LED for visual indication. PG can also be configured as a push-button voltage

shifted output (MRS) in the registers, where the output of the PG pin reflects the status of the

MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.

Reset Output. RESET is an open drain active low output that goes low when MR is held low

for longer than t_RESET, which is configurable by the MRRESET registers. RESET is

deasserted after the t_{RESET_D,}typically 400ms.

RESET

MR

D3

E1

O

I

Manual Reset Input. MR is a push-button input that must be held low for greater than t_RESET

to assert the reset output. If MR is pressed for a shorter period, there are two programmable

timer events, t_WAKE1and t_WAKE2, that trigger an interrupt to the host. The MR input can also

be used to bring the device out of Ship mode.

SW

A4

B5

O

I

Inductor Connection. Connect to the switched side of the external inductor.

System Voltage Sense Connection. Connect SYS to the system output at the output bulk

capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.

SYS

Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to

assure stability. Be sure to account for capacitance bias voltage derating when selecting the

capacitor.

LS/LDO

C5

O

Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from

this pin to GND.

VINLS

BAT

B4, C4

B1, B2

I

Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with

at least 1 µF of ceramic capacitance.

I/O

Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to

GND. The NTC is connected from TS to GND. The TS function provides four thresholds for

JEITA compatibility. TS faults are reported by the I²C interface during charge mode.

TS

C3

I

5

bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

UNIT

V

IN

wrt GND

20

PMID, VINLS

7.7

V

Input voltage

CD, SDA, SCL, ILIM, ISET, IPRETERM, LSCTRL,

INT, RESET, TS

wrt GND

–0.3

5.5

V

Output voltage

SYS

3.6

400

10

V

Input current

IN

mA

V

Sink current

INT

Sink/Source Current

Output Voltage Continuos

RESET

SW

10

–0.7

–40

7.7

400

300

150

6.6

125

300

SW

mA

V

Output Current Continuous

SYS, BAT

LS/LDO

VBAT, MR,

Current

BAT Operating Voltage

Junction Temperature

Storage Temperature, T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.4

NOM

MAX

20

UNIT

IN voltage range

5

V_IN

V

IN operating voltage range, recommended

V_(BAT)operating voltage range

VINLS voltage range for Load Switch

VINLS voltage range for LDO

Input Current, IN input

3.4

5.5

V_(BAT)

V_(VINLS)

I_IN

5.5⁽¹⁾

5.5⁽²⁾

5.5

V

0.8

2.2

V

400

300

100

300

125

mA

°C

I_(SW)

Output Current from SW, DC

Output Current from PMID, DC

Output Current from LS/LDO

I_(PMID)

ILS/LDO

I_(BAT), I_(SYS)Charging and discharging using internal battery FET

T_JOperating junction temperature range

(1) Any voltage greater than shown should be a transient event.

(2) These inputs will support 6.6 V for less than 10% of the lifetime at V_(BAT)or VIN, with a reduced current and/or performance.

–40

6

bq25120A

www.ti.com.cn

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

8.4 Thermal Information

bq25120A

THERMAL METRIC⁽¹⁾

YFP (DSBGA)

UNIT

25 PINS

60

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

0.3

12.0

1.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

12.0

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

8.5 Electrical Characteristics

Circuit of 图 1, V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP), T_J= –40°C to 85°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CURRENTS

V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP)PWM

Switching, –40°C < T_J< 85°C

1

mA

Supply Current for

Control

I_IN

V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP)PWM NOT

Switching

3

1.5

1.2

mA

µA

0°C < T_J< 85°C, V_IN= 5 V, Charge Disabled

0°C < T_J< 60°C, V_IN= 0 V, High-Z Mode, PWM Not

Switching, V_(BUVLO)< V_(BAT)< 4.65 V

0.7

0.9

0°C < T_J< 60°C, V_IN= 0 V, High-Z Mode, PWM Not

Switching, V_(BUVLO)< V_(BAT)< 6.6 V

1.5

3.5

µA

Battery discharge current

in High Impedance Mode

I_{(BAT_HIZ)}

0°C < T_J< 60°C, V_IN= 0 V or floating, High-Z Mode, PWM

Switching, No Load

0.75

1.35

0°C < T_J< 85°C, V_IN= 0 V, High-Z Mode, PWM Switching,

LSLDO enabled

4.25

0°C < T_J< 85°C, V_IN= 0 V, Active Battery Mode, PWM

Switching, LSLDO enabled, I2C Enabled, V_(BUVLO)< V_(BAT)

4.65 V

<

6.8

12

µA

Battery discharge current

in Active Battery Mode

I_{(BAT_ACTIVE)}

0°C < T_J< 85°C, 0 < V_IN< V_IN(UVLO), Active Battery Mode,

PWM Switching, LSLDO disabled, I2C Enabled, CD = Low,

V_(BUVLO)< V_(BAT)< 4.65 V

6.2

2

11

µA

nA

Battery discharge current

in Ship Mode

I_{(BAT_SHIP)}

0°C < T_J< 85°C, V_IN= 0 V, Ship Mode

150

POWER-PATH MANAGEMENT and INPUT CURRENT LIMIT

V_DO(IN-PMID)

V_IN– V_(PMID)

V_IN= 5 V, I_IN= 300 mA

125

120

170

160

mV

V_DO(BAT-PMID)

V_(BAT)– V_(PMID)

V_IN= 0 V, V_(BAT)> 3 V, I_ff= 400 mA

V_(PMID)

<

V_(BAT)– 25

mV

Enter supplement mode

threshold

V_(BSUP1)

V_(BAT)> V_(BUVLO)

V

V_(PMID)

V_(BAT)

<

–

Exit supplement mode

threshold

V_(BSUP2)

V_(BAT)> V_(BUVLO)

5mV

Current Limit, Discharge

Mode

I_{(BAT_OCP)}

V_(BAT)> V_(BUVLO)

0.85

50

1.15

1.35

400

A

Input Current Limit

Programmable Range, 50-mA steps

mA

Maximum Input Current

using ILIM

K_(ILIM)

R_(ILIM)

/

I_(ILIM)

50 mA to 100 mA

–12%

–5%

175

12%

5%

I_ILIMaccuracy I_ILIM

accuracy

100 mA to 400 mA

I_(ILIM)= 50 mA to 100 mA

I_(ILIM)= 100 mA to 400 mA

200

225

210

AΩ

Maximum input current

factor

K_(ILIM)

190

Input voltage threshold

when input current is

reduced

Programmable Range using V_IN(DPM)Registers. Can be

disabled using V_{IN(DPM_ON)}

4.2

4.9

3%

V

V_IN(DPM)

V_{IN_DPM}threshold

accuracy

–3%

BATTERY CHARGER

PMID voltage threshold

V_D(PPM)

when charge current is

reduced

Above V_(BATREG)

0.2

V

Internal Battery Charger

MOSFET on-resistance

R_ON(BAT-PMID)

Measured from BAT to PMID, V_(BAT)= 4.35 V, High-Z mode

300

400

mΩ

Operating in voltage regulation, Programmable Range, 10-

mV steps

Charge Voltage

3.6

4.65

V

V_(BATREG)

T_J= 25°C

–0.5%

0.5%

Voltage Regulation

Accuracy

T_J= 0°C to 85°C

8

bq25120A

www.ti.com.cn

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

Electrical Characteristics (continued)

Circuit of 图 1, V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP), T_J= –40°C to 85°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETERS

TEST CONDITIONS

V_(BATUVLO)< V_(BAT)< V_(BATREG)

MIN

TYP

MAX

UNIT

Fast Charge Current

Range

5

300

mA

Fast Charge Current

using ISET

K_(ISET)

R_(ISET)

/

I_(CHARGE)

A

Fast Charge Current

Accuracy

–5%

190

0.5

5%

210

37

Fast Charge Current

Factor

K_(ISET)

5 mA > I_(CHARGE)> 300 mA

200

AΩ

Termination charge

current

Termination current programmable range over I²C

mA

I_(CHARGE)< 300 mA, R_(ITERM)= 15 kΩ

I_(CHARGE)< 300 mA, R_(ITERM)= 4.99 kΩ

I_(CHARGE)< 300 mA, R_(ITERM)= 1.65 kΩ

I_(CHARGE)< 300 mA, R_(ITERM)= 549 Ω

I_(TERM) > 4 mA

5

10

15

20

% of I_SET

I_(TERM)

Termination Current using

IPRETERM

Accuracy

–10%

0.5

10%

37

t_DGL(TERM)

TERM deglitch time

Pre-charge current

Both rising and falling, 2-mV over-drive, t_RISE, t_FALL= 100 ns

Pre-charge current programmable range over I²C

64

ms

mA

Pre-charge Current using

I_PRETERM

I_{(PRE_CHARGE)}

I_(TERM)

A

Accuracy

–10%

100

10%

140

Recharge threshold

voltage

V_(RCH)

Below V_(BATREG)

120

32

mV

ms

Recharge threshold

deglitch time

t_DGL(RCHG)

t_FALL= 100 ns typ, V_(RCH)falling

SYS OUTPUT

R_{DS(ON_HS)}

PMID = 3.6 V, I_(SYS)= 150 mA

675

300

850

475

mΩ

R_{DS(ON_LS)}

MOSFET on-resistance

for SYS discharge

R_{DS(CH_SYS)}

V_IN = 3.6 V, I_OUT= –10 mA into V_OUTpin

22

40

Ω

SW Current limit HS

SW Current limit LS

2.2 V < V_(PMID)< 5.5 V

450

600

700

675

850

mA

I_(LIMF)

PMOS switch current limit

during softstart

I_{(LIM_SS)}

Current limit is reduced during softstart

Programmable range, 100 mV Steps

80

130

200

mA

V

SYS Output Voltage

Range

1.1

3.3

Output Voltage Accuracy V_IN= 5 V, PFM mode, I_OUT= 10 mA, V_(SYS)= 1.8 V

–2.5%

0

2.5%

V_SYS

DC Output Voltage Load

V_OUT= 2 V, over load range

Regulation in PWM mode

0.01

%/mA

%/V

DC Output Voltage Line

V_OUT= 2 V, I_OUT= 100 mA, over V_INrange

Regulation in PWM mode

0.01

LS/LDO OUTPUT

Input voltage range for

Load Switch Mode

LS/LDO

0.8

2.2

6.6

V

V_IN(LS)

Input voltage range for

LDO Mode

LS/LDO

T_J= 25°C

DC output accuracy

–2%

–3%

0.8

±1%

±2%

2%

3%

3.3

1%

60

V_OUT

Over V_IN, I_OUT, temperature

V_LDO

Output range for LS/LDO Programmable Range, 0.1 V steps

V

DC Line regulation

DC Load regulation

Load Transient

FET Rdson

V_OUT(NOM)+ 0.5 V < V_IN< 6.6 V, I_OUT= 5 mA

0 mA < I_OUT< 100 mA

–1%

–120

ΔV_OUT/ Δ V_IN

2 µA to 100 mA, VOUT = 1. 8 V

V_(VINLS)= 3.6 V

mV

R_{DS(ON_LDO)}

460

20

600

mΩ

MOSFET on-resistance

for LS/LDO discharge

R_{(DSCH_LSLDO)}

1.7 V < V_(VINLS)< 6.6 V, I_LOAD= –10 mA

Ω

9

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Electrical Characteristics (continued)

Circuit of 图 1, V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP), T_J= –40°C to 85°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output Current Limit –

LDO

I_{(OCL_LDO)}

V_LS/LDO

=

275

365

475

mA

V_(VINLS)= 3.6 V, V_LSLDO= 3.3 V

V_(VINLS)= 3.3 V, V_LSLDO= 0.8 V

V_(VINLS)= 2.2 V, V_LSLDO= 0.8 V

100

10

mA

I_(LS/LDO)

Output Current

Quiescent current for

VINLS in LDO mode

0.9

µA

V

I_IN(LDO)

OFF-state supply current

0.25

High-level input voltage

for LSCTRL

0.75 x

V_(SYS)

V_IH(LSCTRL)

V_IL(LSCTRL)

1.15 V > V_(VINLS)> 6.6 V

6.6

Low-level input voltage

for LSCTRL

0.25 x

V_(SYS)

V

PUSHBUTTON TIMER (MR)

V_IL

Low-level input voltage

V_BAT> V_BUVLO

0.3

V

R_PU

Internal pull-up resistance

120

kΩ

VBAT MONITOR

Battery Voltage Monitor

Accuracy

V_BMON

V_(BAT)Falling - Including 2% increment

–3.5

3.5 %V_(BATREG)

BATTERY-PACK NTC MONITOR

High temperature

threshold

V_HOT

V_TSfalling, 1% V_INHysteresis

V_TSrising, 1% V_INHysteresis

14.5

20.1

35.4

15

20.5

36

15.2

%V_IN

Warm temperature

threshold

V_WARM

20.8

36.4

Cool temperature

threshold

V_COOL

Low temperature

threshold

V_COLD

V_TSrising, 1% V_INHysteresis

V_TSrising, 2% V_INHysteresis

39.3

55

39.8

40.2

60

%V_IN

TS_OFF

TS Disable threshold

PROTECTION

IC active threshold

voltage

V_(UVLO)

V_INrising

3.4

3.6

3.8

V

mV

V

V_UVLO(HYS)

IC active hysteresis

Battery Undervoltage

V_INfalling from above V_UVLO

150

Programmable Range for V_(BUVLO)VBAT falling, 150 mV

2.2

3.0

Lockout threshold Range Hysteresis

V_(BUVLO)

Default Battery

Undervoltage Lockout

Accuracy

V_(BAT)falling

–2.5%

2.5%

Battery short circuit

threshold

V_(BATSHORT)

Battery voltage falling

2

100

V

V_{(BATSHORT_HYS)}Hysteresis for V_(BATSHORT)

mV

mA

Battery short circuit

I_(BATSHORT)

I_(PRETERM)

charge current

Sleep entry threshold,

V_IN– V_(BAT)

V_(SLP)

2 V < V_BAT< V_(BATREG), V_INfalling

V_INrising above V_(SLP)

65

120

100

mV

V

Sleep-mode exit

V_{(SLP_HYS)}

40

hysteresis

Maximum Input Supply

V_OVP

V_INrising, 100 mV hysteresis

V_INfalling below V_OVP, 1V/us

5.35

5.55

32

5.75

OVP threshold voltage

Deglitch time, VIN OVP

falling

t_{DGL_OVP}

ms

T_SHTDWN

T_HYS

Thermal trip

V_IN> V_UVLO

114

11

°C

Thermal hysteresis

Deglitch time, Thermal

shutdown

t_{DGL_SHTDWN}

T_Jrising above T_SHTDWN

4

µs

10

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ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

Electrical Characteristics (continued)

Circuit of 图 1, V_(UVLO)< V_IN< V_(OVP)and V_IN> V_(BAT)+ V_(SLP), T_J= –40°C to 85°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I2C INTERFACE

I²C Bus Specification

standard and fast mode

frequency support

100

400

kHz

V_IL

Input low threshold level

V_PULLUP= 1.1 V, SDA and SCL

0.275

V

V_IH

V_OL

Input high threshold level V_PULLUP= 1.1 V, SDA and SCL

Input high threshold level V_PULLUP= 3.3 V, SDA and SCL

Output low threshold level IL = 5 mA, sink current, V_PULLUP= 1.1 V

0.825

2.475

0.275

1

High-Level leakage

V_PULLUP= 1.8 V, SDA and SCL

current

I_BIAS

µA

INT, PG, and RESET OUTPUT (Open Drain)

Low level output

threshold

0.25 x

V_(SYS)

V_OL

Sinking current = 5 mA

V

I_IN

Bias current into pin

Pin is high impedance, I_OUT= 0 mA; T_J= –40°C to 60°C

12

nA

Input voltage above

VBAT where PG sends

two 128 µs pulses each

minute to signal the host

of the input voltage status

V_{IN(BAT_DELTA)}

V_UVLO< V_IN< V_OVP

0.825

1

1.15

V

INPUT PIN (CD LSCTRL)

0.25 *

V_SYS

V_{IL(/CD_LSCTRL)}

V_{IH(/CD_LSCTRL)}

R_PULLDOWN/CD

R_(LSCTRL)

Input low threshold

V_(PULLUP)= V_SYS= 3.3 V

V

0.75 *

V_SYS

Input high threshold

Internal pull-down

resistance

900

2

kΩ

MΩ

Internal pull-down

resistance

11

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8.6 Timing Requirements

MIN

TYP

MAX

UNIT

POWER-PATH MANAGEMENT AND INPUT CURRENT LIMIT

Deglitch Time, PMID or SW Short Circuit

during Discharge Mode

t_{DGL_SC}

250

2

µs

s

Recovery time, OUT Short Circuit during

Discharge Mode

t_{REC_SC}

BATTERY CHARGER

Deglitch time transition from ISET short to

I_(CHARGE)disable

t_{DGL_SHORT}

Clear fault by disconnecting VIN

1

ms

BATTERY CHARGING TIMERS

t_MAXCHG

Charge safety timer

Programmable range

2

540

min

t_PRECHG

Precharge safety timer

0.1 x t_MAXCHG

SYS OUTPUT

t_ONMIN

Minimum ON time

Minimum OFF time

V_IN= 3.6 V, V_OUT= 2 V, I_OUT= 0 mA

V_IN= 4.2 V

225

50

ns

t_OFFMIN

V_IN= 5 V, from write on EN_SW_OUT

until output starts to rise

t_{START_SW}

SW start up time

5

25

ms

From insertion of BAT > V_(BUVLO)or V_IN

> V_(UVLO)

t_{START_SYS}

SYS output time to start switching

350

400

µs

t_SOFTSTART

Softstart time with reduced current limit

1200

LS/LDO OUTPUT

t_{ON_LDO}

Turn ON time

Turn OFF time

100-mA load

500

5

µs

t_{OFF_LDO}

PUSHBUTTON TIMER

t_WAKE1

t_RESET

t_{RESET_D}

t_DD

Push button timer wake 1

0.08

5

1

s

Programmable Range for reset

function

Push button timer reset

Reset pulse duration

15

400

6

ms

µs

Detection delay (from MR, input to

RESET)

For 0s condition

BATTERY-PACK NTC MONITOR

Applies to V_(HOT), V_(WARM), V_(COOL), and

V_(COLD)

t_DGL(TS)

Deglitch time on TS change

50

ms

I2C INTERFACE

t_WATCHDOG

I²C interface reset timer for host

I²C interface inactive reset timer

50

s

t_I2CRESET

700

ms

Transition time required to enable the I²C

interface from HiZ to Active BAT

t_{HIZ_ACTIVEBAT}

1

ms

INPUT PIN

t_{/CD_DGL}

t_QUIET

Deglitch for CD

CD rising/falling

100

µs

Input quiet time for Ship Mode transition

ms

12

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Typical Start-Up Timing and Operation

Remove

Battery

Apply

VIN

Insert

Battery

BAT supplies SYS

when VIN removed

VIN

PMID

VIN > UVLO

PG

SW

After delay of several ms,

switching starts and SYS

starts to rise

SYS

CD

Charging

enabled

Charge

Current

Taper

Charging

disabled

IBAT = I_TERM

No SYS Load

0mA

IBAT

VBAT = V_BATREG

VBAT

rises

VBAT =

V_BATREG- V_RCHG

VBAT>V_BUVLO

IBAT=ICHRG

SYS Load Applied

VBAT

INT

Shows

Charge

Status

<3uA max

<4uA max

VISET

<5uA max

<4uA max

<3uA max

nA of leakage with VIN present

BAT IQ

Conditions: PGB_MRS = 0, TE = 1, SW_LDO = 1, VINDPM_ON = 0, PG and INT pulled up to SYS, EN_INT = 1

图 1. Typical Start-Up Timing and Operation

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Insert Battery <

V_BATSHORT

VBAT=V_BUVLO

VBAT

VBAT=V_BUVLO

IBAT = I_BATSHORT

IBAT

IBAT = ICHG

VIN

Device enters Active Battery

Mode after valid /MR

CD

EN_SHIPMODE

MR_WAKE1 time reached

MR_WAKE2 time reached

MRRESET time reached

MR

User depresses button

t_RESET

RESET

MR_WAKE1

Interrupt

MR_WAKE2

Interrupt

INT

<1uA max

<3uA max

<1uA max

<3uA max

BAT IQ

After delay of several ms,

SYS starts to rise

SYS is pulled down shortly

after VBATUVLO is reached

SYS

Conditions: SW_LDO = 1, MRREC = 1, PG and INT pulled up to SYS, ISYS = 10 µA, EN_INT = 1

图 2. Battery Operation and Sleep Mode

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8.7 Typical Characteristics

12

10

8

2.0

1.5

1.0

0.5

0.0

6

4

2

85èC

60èC

25èC

0èC

85èC

60èC

25èC

0èC

0

3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

BAT (V)

D016

D017

1.8 V System Enabled (No Load)

图 3. Active BAT, I_Q

图 4. Hi-Z BAT, I_Q

700

600

500

400

300

200

100

0

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

85èC

60èC

25èC

0èC

3

3.2

3.4

3.6

3.8

4

4.2

4.4

4.6

-40 -25 -10

5

20 35 50 65 80 95 110 125

BAT (V)

Temperature (èC)

D018

D024

图 5. Ship Mode BAT, I_Q

图 6. Blocking FET R_DS(ON)vs Temperature

400

350

300

250

200

150

100

50

0.5%

0.3%

0.1%

-0.1%

-0.3%

-0.5%

4.35 V_(BATREG)

4.2 V_(BATREG)

4 V_(BATREG)

3.8 V_(BATREG)

3.6 V_(BATREG)

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40

-10

20

50

80

110 125

Temperature (èC)

D025

D019

图 7. Battery Discharge FET R_DS(ON)vs Temperature

图 8. V_(BATREG)Accuracy vs Temperature

15

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Typical Characteristics (接下页)

5%

4%

3%

2%

1%

0

5%

3%

-40èC

0èC

25èC

85èC

125èC

1%

-1%

-2%

-3%

-4%

-5%

-1%

-3%

-5%

-40èC

0èC

25èC

85èC

125èC

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0

50

100

150

200

250

300

Input Current Limit (A)

Charge Current (mA)

D020

D021

图 9. ILIM Accuracy vs Input Current

图 10. Charge Current Accuracy vs Charge Current

10%

1000

900

800

700

600

500

400

300

200

100

0

-40èC

0èC

25èC

85èC

125èC

8%

6%

4%

2%

0

-2%

-4%

-6%

-8%

-10%

0

5

10

15

20

25

30

35

40

-40 -25 -10

5

20 35 50 65 80 95 110 125

Pre-Charge Current (mA)

Temperature (èC)

D022

D0264

V_IN= 5 V

图 11. Pre-Charge Accuracy vs Pre-Charge Current

图 12. R_DS(ON)of High Side MOSFET vs Temperature

400

350

300

250

200

150

100

50

160

140

120

100

80

Noise Floor

1 mA

10 mA

50 mA

100 mA

60

40

20

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

10 20 50 100

1000

10000

100000

1000000

Temperature (èC)

Frequency (Hz)

D027

D028

V_IN= 5 V

图 13. R_DS(ON)of Low Side MOSFET vs Temperature

图 14. LS/LDO PSRR vs Frequency

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9 Detailed Description

9.1 Overview

The following sections describe in detail the functions provided by the BQ25120A. These include linear charger,

PWM output, configurable LS/LDO output, Push-button input, reset timer, functional modes, battery monitor, I²C

configurability and functions, and safety features.

9.2 Functional Block Diagram

PMID

Q1/Q2

Q3

IN

SW

D

S

G

GND

I_INLIM

Q4

PWM, LDO, and BAT FET

Control

SYS

V_SYSREG

V_{IN_DPM}

VINLS

LDO

Control

S

D

V_BATREG

I_BATREG

Thermal

Shutdown

G

LDO/ Load Switch

Q5

Control

V_SUPPLY

Hi-Z

Mode

LS/LDO

CD

Termination

Reference

VIN

Q7

SDA

SCL

I2C

Interface

I_BAT

+

LDO/ Load Switch

Host Control

LSCTRL

ILIM

Disable

Input Current Limit

Charge Current

TS COLD

+

ISET

1C/

0.5C

TS COOL

TS WARM

BAT

Termination Current

IPRETERM

PG

VBATREG

œ 140mV

+

V_BAT(SC)

+

Disable

Device Control

TS HOT

V_IN

VOVP

INT

V_INOVP

V_BAT

V_BATOVP

BATOVP

+

V_BAT

BATSHRT

Recharge

V_BATSHRT

+

V_BATREGœ 0.12 V

V_BAT

RESET

Reset and

Timer

MR

TS

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9.3 Feature Description

9.3.1 Ship Mode

Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET

until V_IN> V_BAT+ V_SLPor the MR button is depressed for t_WAKE1and released. The following list shows the events

that are active during Ship Mode:

1. VIN_UV Comparator

2. MR Input (No clock or delay in this mode for lowest power consumption)

3. PMID active pull down

9.3.1.1 Ship Mode Entry and Exit

The device may only enter Ship Mode when there is not a valid VIN supply present (V_IN< V_UVLO). Once the IN

supply is removed there are two ways for the device to enter Ship Mode: through I²C command using the

EN_SHIPMODE bit and by doing a long button press when MRREC bit is set to 0. If the EN_SHIPMODE bit is

set while the IN supply is present, the device will enter Ship Mode upon removal of the supply. The

EN_SHIPMODE bit can be cleared using the I²C interface as well while the IN input is valid.

In addition to V_IN< V_UVLO, CD and MR must be high. Once all of these conditions are met the device will begin

the transition to Ship Mode. All three conditions must remain unchanged for a period of t_QUIETto ensure proper

operation. 图 15 and 图 16show the correct sequencing to ensure proper entry into the Ship Mode through I²C

command and MR button press respectively.

t_QUIET

CD

MR

VIN

Shipmode

2

I C

Write

图 15. CD, MR and VIN Sequencing for Ship Mode Entry Through I²C Command

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Feature Description (接下页)

t_QUIET

CD

MR

VIN

t > t_RESET

Shipmode

2

I C

Write

图 16. CD, MR and VIN Sequencing for Ship Mode Entry Through Long MR button press

The end user can enable the device (exit Ship Mode) by connecting an adapter to IN (V_IN> V_BAT+ V_SLP) or by

toggling the MR button. Note that in the case where an adapter is connected while the MR is still held low and

immediately after the RESET timer has expired (MR low for t_RESET), the device will not enter Ship Mode, but may

enter it upon adapter removal (Same behavior as setting the EN_SHIPMODE bit when the adapter is present).

This will not be the case if MR has gone high when the adapter is connected or MR continues to be held low for

a period longer than t_WAKE1after the adapter is connected.

To exit Ship Mode through and MR press the battery voltage must be above the maximum programmable

BUVLO threshold when V_INis not present. Once MR goes low, the device will start to exit Ship Mode, powering

PMID. The device will not complete the transition from Ship Mode until MR has been held low for at least t_WAKE1

.

Only after the transition is complete may the host start I²C communication if the device has not entered High

Impedance Mode.

9.3.2 High Impedance Mode

High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode

the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are

in a low power or sleep state. The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the

LS/LDO output has been enabled through I²C prior to entering Hi-Z mode, it will stay enabled. The CD pin is

used to put the device in a high-impedance mode when battery is present and V_IN< V_UVLO. Drive CD high to

enable the device and enter active battery operation when V_INis not valid. When the HZ_MODE bit is written by

the host, the I²C interface is disabled if only battery is present. To resume I²C, the CD pin must be toggled. If the

supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the /CD pin

to resume I²C communication.. The functionality of the pin is shown in 表 1.

表 1. CD, State Table

CD, State

V_IN< V_UVLO

Hi-Z

V_IN> V_UVLO

L

Charge Enabled

Charge Disabled

H

Active Battery

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9.3.3 Active Battery Only Connected

When the battery above V_BATUVLOis connected with no input source, the battery discharge FET is turned on.

After the battery rises above V_BATUVLOand the deglitch time is reached, the SYS output starts to rise. The current

from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit limit is

reached for the deglitch time (t_{DGL_SC}), the battery discharge FET is turned off for the recovery time (t_{REC_SC}).

After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not, the FET

turns off and the process repeats until the short is removed. This process protects the internal FET from over

current. During this event PMID will likely droop and cause SYS to go out of regulation.

To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When

the voltage drops below the V_BATUVLOthreshold, the battery discharge FET is turned off. Deeper discharge of the

battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable

with a fixed 150-mV hysteresis.

If a valid V_INis connected during active battery mode, V_IN> V_UVLO, the supplement and battery discharge FET is

turned on when the battery voltage is above the minimum V_BATUVLO

.

Drive CD high or write the CE register to disable charge when V_IN> V_UVLOis present. CD is internally pulled

down. When exiting this mode, charging resumes if V_INis present, CD is low and charging is enabled.

All HOST interfaces (CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches

the programmed level.

9.3.4 Voltage Based Battery Monitor

The device implements a simple voltage battery monitor which can be used to determine the depth of discharge.

Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value for

the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a known

load. The register will be updated and can be read 2ms after a read is initiated. The VBMON voltage threshold is

readable with 2% increments with ±1.5% accuracy between 60% and 100% of VBATREG using the VBMON_TH

registers. Reading the value during charge is possible, but for the most accurate battery voltage indication, it is

recommended to disable charge, initiate a read, and then re-enable charge.

A typical discharge profile for a Li-Ion battery is shown in 表 2. The specific battery to be used in the application

should be fully characterized to determine the thresholds that will indicate the appropriate battery status to the

user. Two typical examples are shown below, assuming the VBMON reading is taken with no load on the battery.

This function enables a simple 5-bar status indicator with the following typical performance with different

VBATREG settings:

表 2. Discharge Profile for a Li-Ion Battery

95% to 65%

65% to 35%

35% to 5%

VBATREG

BATTERY FULL

BATTERY EMPTY

REMAINING CAPACITY REMAINING CAPACITY REMAINING CAPACITY

4.35 V

4.2 V

VBMON > 90%

VBMON > 98%

VBMON = 88%

VBMON = 86%

VBMON = 84%

VBMON < 82%

VBMON < 84%

VBMON = 94% or 96%

VBMON = 90% or 92%

VBMON = 86% or 88%

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VREF

S0

-2 % BAT TAP

-4 % BAT TAP

-6 % BAT TAP

-8 % BAT TAP

-10 % BAT TAP

S1

90 % VB

D

E

80 % VB

S2

C

O

D

E

R

S3

70 % VB

60 % VB

VB =0. 8 VBAT

图 17. Voltage Battery Monitor

9.3.5 Sleep Mode

The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and V_IN

is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the connected battery.

This feature prevents draining the battery during the absence of V_IN. When V_IN< V_(BAT)+ V_SLP, the device turns

the battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the register are

update over I²C. Once V_IN> V_(BAT)+ V_SLP, the device initiates a new charge cycle. The FAULT bits are not

cleared until they are read over I²C and the sleep condition no longer exists. It is not recommended to do a

battery connection or plug in when V_UVLO< VIN < V_BAT+ V_SLPas it may cause higher quiescent current to be

drained form the battery.

9.3.6 Input Voltage Based Dynamic Power Management (V_IN(DPM)

)

During the normal charging process, if the input power source is not able to support the programmed or default

charging current and System load, the supply voltage decreases. Once the supply approaches V_IN(DPM), the input

DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the further

drop of the supply. The V_IN(DPM)threshold is programmable through the I²C register from 4.2 V to 4.9 V in 100-

mV steps. It can be disabled completely as well. When the device enters this mode, the charge current may be

lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is extended

while V_IN(DPM)is active. Additionally, termination is disabled. Note that in a condition where the battery is

connected while V_UVLO<V_IN< V_IN(DPM), the VINDPM loop will prevent the battery from being charged and PMID

will be powered from BAT.

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9.3.7 Input Overvoltage Protection and Undervoltage Status Indication

The input overvoltage protection protects the device and downstream components connected to PMID, SYS, and

BAT against damage from overvoltage on the input supply. When V_IN> V_OVPan OVP fault is determined to exist.

During the OVP fault, the device turns the battery discharge FET on, sends a single 128-µs pulse on INT, and

the FAULT bits are updated over I²C. Once the OVP fault is removed, after the deglitch time, t_{DGL_OVP}, STAT and

FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until they are

read in from I²C after the OVP condition no longer exists. The OVP threshold for the device is set to operate from

standard USB sources.

The input under-voltage status indication is used to notify the host or other device when the input voltage falls

below a desired threshold. When V_IN< V_UVLO, after the deglitch time t_{DGL_UVLO}, a UVLO fault is determined to

exist. During the V_INUVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits

are updated over I²C. The FAULT bits are not cleared until they are read in from I²C after the UVLO condition no

longer exists.

9.3.8 Battery Charging Process and Charge Profile

When a valid input source is connected (V_IN> V_UVLOand V_(BAT)+ V_SLP< V_IN< V_OVPand V_IN> V_IN(DPM)), the CE

bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input

source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on

the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input

can be used to enable and disable charge.

The device supports multiple battery chemistries for single-cell applications. Charging is done through the

internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC),

constant voltage loop (CV), input current limit, V_DPPM, and V_IN(DPM). During the charging process, all loops are

enabled and the one that is dominant takes control.

The charge current is regulated to I_CHARGEuntil the voltage between BAT and GND reaches the regulation

voltage. The voltage between BAT and GND is regulated to V_BATREG(CV Mode) while the charge current

naturally tapers down. When termination is enabled, the device monitors the charging current during the CV

mode, and once the charge current tapers down to the termination threshold, I_TERM, and the battery voltage is

above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination

is disabled when any loop is active other than CV.

9.3.9 Dynamic Power Path Management Mode

With a valid input source connected, the power-path management circuitry monitors the input voltage and current

continuously. The current into IN is shared at PMID between charging the battery and powering the system load

at PMID, SYS, and LS/LDO. If the sum of the charging and load currents exceeds the current that the VIN can

support, the input DPM loop(VINDPM) reduces the current going into PMID through the input blocking FETs.

This will cause a drop on the PMID voltage if the system demands more current. If PMID drops below the DPPM

voltage threshold(V_DPPM), the charging current is reduced by the DPPM loop through the BATFET in order to

stabilize PMID. If PMID continues to drop after BATFET charging current is reduced to zero, the part enters

supplement mode when PMID falls below the supplement mode threshold. Battery termination is disabled while

in DPPM mode. In order to charge the battery, the voltage at PMID has to be greater than V_BATREG+ V_DPPM

threshold..

9.3.10 Battery Supplement Mode

While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the

programmed input current limit, the voltage at PMID reduces further. When the PMID voltage drops below the

battery voltage by V_(BSUP1), the battery supplements the system load. The battery stops supplementing the

system load when the voltage on the PMID pin rises above the battery voltage by V_(BSUP2). During supplement

mode, the battery supplement current is not regulated, however, the short-circuit protection circuit is active.

Battery termination is disabled while in supplement mode.

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9.3.11 Default Mode

The default mode is used when there is no host, or I²C communication is not available. If the externally

programmable pins, ILIM, ISET, and ITERM have resistors connected, that is considered the default mode. If any

one of these resistors is tied to GND, the default register settings are used. The default mode can be entered by

connecting a valid power source to V_INor the RESET bit is written. Default mode is exited by writing to the I²C

interface.

9.3.12 Termination and Pre-Charge Current Programming by External Components (IPRETERM)

The termination current threshold is user programmable through an external resistor or through registers over

I²C. Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND. The

termination can be set between 5% and 20% of the programmed output current set by ISET, using 表 3 for

guidance:

表 3. IPRETERM Resistor Settings

RIPRETERM

IPRE_CHARGE and ITERM

KKIPRETERM

TYP

(STANDARD 1%

VALUES)

UNIT

TYP

(% of ISET)

RECOMMENDED

RIPRETERM

MIN

MAX

MIN

MAX

5

180

200

220

15000

4990

1650

549

Ω

10

15

20

Using the I²C register, the termination current can be programmed with a minimum of 500 µA and a maximum of

37 mA.

The pre-charge current is not independently programmable through the external resistor, and is set at the

termination current. The pre-charge and termination currents are programmable using the IPRETERM registers.

If no IPRETERM resistor is connected and the pin is tied to GND, the default values in the IPRETERM registers

are used. The external value can be used in host mode by configuring the IPRETERM registers. If the external

ICHG setting will be used after being in Host mode, the IPRETERM registers should be set to match the desired

external threshold for the highest ICHG accuracy.

Termination is disabled when any loop other than CV is active.

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9.3.13 Input Current Limit Programming by External Components (ILIM)

The input current limit threshold is user programmable through an external resistor or through registers over I²C.

Set the input current limit using the ILIM pin by connecting a resistor from ILIM to GND using 表 4 for guidance. If

no ILIM resistor is connected and the pin is tied to GND, the default ILIM register value is used. The external

value is not valid once the device enters host mode.

表 4. ILIM Resistor Settings

ILIM

TYP

KILIM

TYP

RILIM

(STANDARD 1%

VALUES)

UNIT

MIN

MAX

MIN

MAX

0.048469388

0.09047619

0.146153846

0.19

0.051020408

0.095238095

0.153846154

0.2

0.053571429

0.1

190

200

210

3920

2100

1300

1000

665

Ω

0.161538462

0.21

0.285714286

0.380761523

0.30075188

0.400801603

0.315789474

0.420841683

499

The device has register programmable input current limits from 50 mA to 400 mA in 50-mA steps. The device is

USB-IF compliant for inrush current testing, assuming that the input capacitance to the device is selected to be

small enough to prevent a violation (<10 µF), as this current is not limited.

9.3.14 Charge Current Programming by External Components (ISET)

The fast charge current is user programmable through an external resistor or through registers over I²C. Set the

fast charge current by connecting a resistor from ISET to GND. If no ISET resistor is connected and the pin is

tied to GND, the default ISET register value is used. While charging, if the charge current is using the externally

programmed value, the voltage at ISET reflects the actual charging current and can be used to monitor charge

current. The current out of ISET is 1/100 (±10%) of the charge current. The charge current can be calculated by

using 表 5 for guidance:

表 5. ISET Resistor Settings

ISET

TYP

KISET

TYP

RISET

(STANDARD 1%

VALUES)

UNIT

MIN

MAX

MIN

MAX

0.285714286

0.19

0.30075188

0.2

0.315789474

0.21

190

200

210

665

1000

1500

2000

2940

3920

4990

6040

7320

10000

15000

20000

29400

39200

Ω

0.126666667

0.095

0.133333333

0.1

0.14

0.105

0.06462585

0.048469388

0.038076152

0.031456954

0.025956284

0.019

0.068027211

0.051020408

0.04008016

0.033112583

0.027322404

0.02

0.071428571

0.053571429

0.042084168

0.034768212

0.028688525

0.021

0.012666667

0.0095

0.013333333

0.01

0.014

0.0105

0.006462585

0.004846939

0.006802721

0.005102041

0.007142857

0.005357143

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9.3.15 Safety Timer and Watchdog Timer

At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the

programmed safety time, t_MAXCHG, expires, the device enters idle mode and charging is disabled. The pre-charge

safety time, t_PRECHG, is 10% of t_MAXCHG. When a safety timer fault occurs, a single 128 µs pulse is sent on the INT

pin and the STAT and FAULT bits of the status registers are updated over I²C. The CD pin or power must be

toggled in order to clear the safety timer fault. The safety timer duration is programmable using the TMR bits.

When the safety timer is active, changing the safety timer duration resets the safety timer. The device also

contains a 2X_TIMER bit that enables the 2X timer function to prevent premature safety timer expiration when

the charge current is reduced by a load on PMID, SYS, LS/LDO or a NTC condition. When t_{2X_TIMER}function is

enabled, the timer is allowed to run at half speed when any loop is active other than CC or CV.

In addition to the safety timer, the device contains a 50-second watchdog timer that monitors the host through

the I²C interface. Only after an I²C transaction is performed on the I²C interface, will the watchdog timer start. In

the case where the device is set to operate in High Impedance Mode, the watchdog timer is automatically

disabled and can only be re-started after the device exits the High Impedance Mode and a subsequent I²C

transaction is performed. The watchdog timer is reset by any transaction by the host using the I²C interface. If

the watchdog timer expires without a reset from the I²C interface, all registers except MRRESET_VIN and

MRREC are reset to the default values.

9.3.16 External NTC Monitoring (TS)

The I²C interface allows the user to easily implement the JEITA standard for systems where the battery pack

thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for

monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a

safe temperature during charging.

To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold, the

cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures correspond

to the V_(COLD), V_(COOL), V_(WARM), and V_(HOT)threshold in the Electrical Characteristics. Charging and timers are

suspended when V_(TS)< V_(HOT)or > V_(COLD). When V_(COOL)< V_(TS)< V_(COLD), the charging current is reduced to

half of the programmed charge current. When V_(HOT)< V_(TS)< V_(WARM), the battery regulation voltage is reduced

by 140 mV (minimum V_BATREGunder this condition is 3.6V).

The TS function is voltage based for maximum flexibility. Connect a resistor divider from V_INto GND with TS

connected to the center tap to set the threshold. The connections are shown in 图 18. The resistor values are

calculated using 公式 1 and 公式 2. To disable the TS function, pull TS above TS_OFFthreshold.

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V_BATREG

1 x Charge/

0.5 x Charge

V_DRV

– 140 mV

DISABLE

TS COLD

+

TS COOL

TS WARM

+

V_DRV

TS HOT

RHI

+

TS

PACK+

TEMP

bq2512x

RLO

PACK–

图 18. TS Circuit

æ

ç

è

ö

1

÷

V

x R

(COLD)

x R

x

-

IN

(HOT)

÷

V

(HOT)

(COLD)

ø

R

=

(LO)

æ

ç

è

ö

æ

ç

è

ö

V

IN

V

(COLD)

÷

-1

R

x

-1 - R

x

(HOT)

(COLD)

÷

ø

÷

V

(HOT)

ø

(1)

(2)

æ

ö

V

IN

ç

è

÷

- 1

÷

V

(COLD)

ø

R

=

(HI)

æ

ç

è

ö

÷

ø

1

+

R

(LO)

(COLD)

Where

•

R_(HOT)= the NTC resistance at the hot temperature

R_(COLD)= the NTC resistance at the cold temperature

The warm and cool thresholds are not independently programmable. The cool and warm NTC resistances for a

selected resistor divider are calculated using 公式 3 and 公式 4.

R

x R

(HI)

x V_COOL

%

(LO)

x V_COOL% - R

R

=

(COOL)

R

- R

(LO)

x V_COOL

%

(LO)

(HI)

(3)

(4)

R

x R

x V %

WARM

(LO)

(HI)

R

=

-

R

(

(LO)

x V

% - R

(HI)

x V %

WARM

)

(WARM)

WARM

(LO)

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9.3.17 Thermal Protection

During the charging process, to prevent overheating in the device, the junction temperature of the die, T_J, is

monitored. When T_Jreaches T_(SHUTDOWN)the device stops charging, disables the PMID output, disables the SYS

output, and disables the LS/LDO output. During the time that T_(SHUTDOWN)is exceeded, the safety timer is reset

and the watchdog timer continues to operate if in host mode. The charge cycle resumes when T_Jfalls below

T_(SHUTDOWN)by T_(HYS)

.

To avoid reaching thermal shutdown, ensure that the system power dissipation is under the limits of the device.

The power dissipated by the device can be calculated using 公式 5.

P_DISS= P_(BLOCK)+ P_(SYS)+ P_(LS/LDO)+ P_(BAT)

(5)

Where

•

P_(BLOCK)= (V_IN– V_(PMID)) x I_IN

P_(SYS)= I_SYS²x R_{DS(ON_HS)}

P_(LS/LDO)= (V_(INLS)– V_(LS/LDO)) x I_(LS/LDO)

P_(BAT)= (V_(PMID)– V_(BAT)) x I_(BAT)

9.3.18 Typical Application Power Dissipation

The die junction temperature, T_J, can be estimated based on the expected board performance using 公式 6.

T_J= T_A+ θ_JAx P_DISS

(6)

The θ_JAis largely driven by the board layout. For more information about traditional and new thermal metrics, see

the IC Package Thermal Metrics application report SPRA953. Under typical conditions, the time spent in this

state is short.

9.3.19 Status Indicators (PG and INT)

The device contains two open-drain outputs that signal its status and are valid only after the device has

completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output

signals when a valid input source is connected. PG pulls to GND when V_IN> V_UVLO,V_IN> V_BAT+V_SLPand V_IN

<

V_OVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic

voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.

The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-

impedance when the MR input is not low, and PG pulls to GND when the MR input is below V_{OL(TH_MRS)}. Connect

PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.

The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When

EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is

high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128

µs pulse (interrupt) is sent on INT to notify the host.

9.3.20 Chip Disable (CD)

The device contains a CD input that is used to disable the device and place it into a high impedance mode when

only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge

FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin

can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.

If V_INis present and the CD input is pulled low, charge is enabled and all other functions remain active. If V_INis

present and the CD input is pulled high, charge is disabled.

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9.3.21 Buck (PWM) Output

The device integrates a low quiescent current switching regulator with DCS control allowing high efficiency down

to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The

internally compensated regulation network achieves fast and stable operation with small external components

and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to

2 MHz. If the load current decreases, the converter enters a power save mode to maintain high efficiency down

to light loads. In this mode, the device generates a single switching pulse to ramp up the inductor current and

recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut down to

achieve a low quiescent current. The duration of the sleep period depends on the load current and the inductor

peak current. For optimal operation and maximum power delivery allow V_PMID> V_SYS+ 0.7V.

The output voltage is programmable using the SYS_SEL and SYS_VOUT bits in the SYS VOUT control register.

The SW output is enabled using the EN_SYS_OUT bit in the register. This bit is for testing and debug only and

not intended to be used in the final system. When the device is enabled, the internal reference is powered up

and the device enters softstart, starts switching, and ramps up the output voltage. When SW is disabled, the

output is in shutdown mode in a low quiescent state. The device provides automatic output voltage discharge so

the output voltage will ramp up from zero once the device in enabled again. Once SYS has been disabled, either

V_INneeds to be connected or the MR button must be held low for the t_RESETduration to re-enable SYS.

The output is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. 表 6 shows the

recommended LC output filter combinations.

表 6. Recommended Output Filter

INDUCTOR VALUE (µH)

OUTPUT CAPACITOR VALUE (µF)

4.7

10

22

2.2

Possible

Recommended

Possible

The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point where the part

enters and exits Pulse Frequency Modulation to lower the power consumed at low loads, the output voltage

ripple and the efficiency. The selected inductor must be selected for its DC resistance and saturation current. The

inductor ripple current (ΔI_L) can be estimated according to 公式 7.

ΔI_L= V_SYSx (1-(V_SYS/V_PMID))/(L x f)

(7)

Use 公式 8 to calculate the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current. As the size of the inductor decreases, the

saturation “knee” must be carefully considered to ensure that the inductance does not decrease during higher

load condition or transient. This is recommended because during a heavy load transient the inductor current rises

above the calculated value. A more conservative way is to select the inductor saturation current above the high-

side MOSFET switch current.

I_L(max) = I_SYS(max) + ΔI_L/ 2

(8)

Where

•

F = Switching Frequency

L = Inductor Value

ΔI_L= Peak to Peak inductor ripple current

I_L(max) = Maximum Inductor current

In DC/DC converter applications, the efficiency is affected by the inductor AC resistance and by the inductor

DCR value.

表 7 shows recommended inductor series from different suppliers.

表 7. Inductor Series

DIMENSIONS

(1)

INDUCTANCE (µH)

DCR (Ω)

INDUCTOR TYPE

SUPPLIER

COMMENT

(mm³)

2.2

0.300

0.170

1.6 x 0.8 x 0.8

1 .6 x 0.8 x 0.8

MDT1608CH2R2N

GLFR1608T2R2M

TOKO

TDK

Smallest size, 75mA max

Smallest size, 150mA max

(1) See Third-party Products Disclaimer

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表 7. Inductor Series (接下页)

DIMENSIONS

(1)

INDUCTANCE (µH)

DCR (Ω)

INDUCTOR TYPE

SUPPLIER

COMMENT

(mm³)

2.2

0.245

0.23

2.0 x 1.2 x 1.0

2.0 x 1.6 x 1.0

2.5 x 2.0 x 1.2

3.3 x 3.3 x 1.4

MDT2012CH2R2N

MIPSZ2012 2R2

74438343022

MIPSA2520 2R2

LPS3314

TOKO

TDK

Small size, high efficiency

0.225

0.12

Wurth

TDK

0.145

Coicraft

The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest

output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At

light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the

output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input

current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of

the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The

PMID capacitor can be increased to 22 µF for better input voltage filtering.

表 8 shows the recommended input/output capacitors.

表 8. Capacitors

CAPACITANCE (µF)

SIZE

0603

0402

CAPACITOR TYPE

GRM188R60J106ME84

CL05A106MP5NUNC

SUPPLIER⁽¹⁾

Murata

COMMENT

Recommended

Smallest size

10

Samsung EMA

(1) See Third-party Products Disclaimer

9.3.22 Load Switch / LDO Output and Control

The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can

be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as

there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low

voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to

VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times

larger than the output capacitor on LS/LDO.

The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated

using 公式 9.

LS/LDO = 0.8 V + LS_LDOCODE x 100 mV

(9)

If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -

V_(DROPOUT). 表 9 summarizes the control of the LS/LDO output based on the I²C or LSCTRL pin setting:

表 9. LS/LDO Output Control

I²C LS_LDO_EN

PIN LSCTRL

I²C V_LDO> 3.3

LS/LDO Output

Pulldown

V_LDO

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSW

V_LDO

LSW

V_LDO

LSW

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If the output of the LDO is less than the programmed V_(SYS)voltage, connect VINLS to SYS. If the output of the

LDO is greater than the programmed V_SYSvoltage, connect VINLS to PMID.

The current capability of the LDO depends on the VINLS input voltage and the programmed output voltage. The

full 100-mA output current for 0.8-V output voltage can be achieved when V_(VINLS)> 3.25 V. The full 100-mA

output current for 3.3-V output voltage can be achieved when V_(VINLS)> 3.6 V.

When the LSLDO output is disabled with LSCTRL or through the register, an internal pull-down discharges the

output.

9.3.23 Manual Reset Timer and Reset Output (MR and RESET)

The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is

valid, stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the

IC may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in

order to avoid unwanted shutdown of SYS output rail.The input conditions can be adjusted by using MRWAKE

bits for the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs

pulse is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I²C. The MR_WAKE

bits and RESET FAULT bits are not cleared until the Push-button Control Register is read from I²C.

When a MR reset condition is met, a 128us pulse is sent on INT to notify the host and a RESET signal is

asserted. A reset pulse occurs with duration of t_{RESET_D}only one time after each valid MRRESET condition. The

MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again.

After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending

on MRREC register settings. For details on how to properly enter Ship Mode through MR, see Ship Mode Entry

and Exit .After RESET is asserted with a valid V_INpresent, the device resumes operation prior to the MR button

press. If SYS was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active

Battery.

The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button

press and V_INpresent (V_UVLO+ V_SLP< V_IN< V_OVP).

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9.4 Device Functional Modes

表 10. Modes and Functions

READY (PRIOR

HOST MODE

ACTIVE

BATTERY

FUNCTION

TO I²C) AND

READY (AFTER

CHARGE

SHIP MODE

HIGH_Z

AFTER RESET

I²C)

VOVP

VUVLO

Yes

No

Yes

No

Yes

VBATUVLO

Default or

registers

Default or

registers

VINDPM

SYS

If enabled

No

Default or

registers

Default or

registers

If enabled

Default or

registers

Default or

registers

LS/LDO

BATFET

TS

Yes

No

Yes

No

Yes

No

Yes (VIN Valid)

Default, registers, Default, registers,

or external or external

IPRETERM

ISET

External

No

Default, registers, Default, registers,

or external or external

Default, registers, Default, registers,

ILIM

or external

MR input

LSCTRL input

RESET output

INT output

I²C interface

CD input

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

PG output

Yes

If enabled

Yes

VBMON

Yes

No

表 11. Fault and Status Condition Responses

CHARGER

BEHAVIOR

LS/LDO

BEHAVIOR

FAULT or STATUS

ACTIONS

SYS BEHAVIOR

TS BEHAVIOR

Update VIN_OV status, Update

STAT to fault, interrupt on INT,

PG shown not good

Enabled through

BAT

Enabled through

BAT

VIN_OV

Disabled

Update VIN_UV status, Update

STAT to fault, interrupt on INT,

PG shown not good

Enabled through

BAT

Enabled through

BAT

VIN_UV

Disabled

Update charge in progress

status, interrupt on INT, input

current is limited

Enabled, input

current limited

Enabled (if

enabled)

Enabled (if

enabled)

VIN_ILIM

OVER_TEMP

BAT_UVLO

Enabled

Disabled

Update BAT_UVLO status,

Update STAT to fault, interrupt

on INT

Enabled (if

enabled) and VIN

Valid

Enabled (if

enabled) and VIN

Valid

Enabled if VIN

Valid

Pre-charge

Enabled (if

enabled)

SW_SYS_SHORT

LS_LDO_OCP

TIMER fault

Enabled

Disabled

Current Limit

Enabled

Disabled

Enabled (if

enabled)

Current Limit

Update TIMER, Update STAT

to fault, interrupt on INT

Enabled (if

enabled)

Enabled (if

enabled)

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表 11. Fault and Status Condition Responses (接下页)

CHARGER

BEHAVIOR

LS/LDO

BEHAVIOR

FAULT or STATUS

ACTIONS

SYS BEHAVIOR

TS BEHAVIOR

Update VINDPM_STAT,

Update STAT to fault, interrupt

on INT

Enabled, input

current reduced

Enabled (if

enabled)

Enabled (if

enabled)

VINDPM

Enabled

Update TS_FAULT to COLD

OR HOT, Update STAT to

fault, interrupt on INT

TS_FAULT COLD

or HOT

Enabled (if

enabled)

Enabled (if

enabled)

Disabled

Enabled

Update TS_FAULT to COOL,

TS_FAULT COOL Update STAT to fault, interrupt Reduce ICHG to ½

on INT

Enabled (if

enabled)

Enabled (if

enabled)

Update TS_FAULT to WARM,

TS_FAULT WARM Update STAT to fault, interrupt

Reduce VBATREG

Enabled (if

enabled)

Enabled (if

enabled)

by 140 mV

on INT

Disabled, monitor

for VBAT falling

below VRCHG

Update STAT to Charge Done,

Enabled (if

enabled)

Enabled (if

enabled)

Charge Done

interrupt on INT

yVBAT>VBAT_UVLO

yVIN<VBAT+VSLP

yCD9

/CE

RESET

HZ_MODE

yVIN_OV

yVIN_UV

yOVER_TEMP

yBAT_SHORT

yBAT_OVP

yCD;|_VIN>VUVLO

HIGH_Z

FAULT

READY STATE

After Reset, all default OTP settings

are used in this state.

Lowest quiescent current state. SYS

is powered by BAT, MR input is active,

and the LSCTRL input is active.

A failure occurred. The fault event

must be cleared before going to the

previous state.

!FAULT|_/CE

yTIMER

yVIN_OV

yOVER_TEMP

yTS_FAULT (HOT OR COLD)

HZ_MODE

yCD9

yCD;|_VIN<VUVLO

yBAT_OVP

yVIN_OV

yTS_FAULT (HOT OR COLD)

yVBAT>VBAT_UVLO

yVIN<VBAT+VSLP

!/CE

!FAULT|

!/CE & DONE

/CE

!FAULT|_!/CE

ACTIVE BATTERY

The device is powered from BAT, all

outputs and interfaces are active.

yCHARGING DONE|_TE

CHARGING

The system charges the battery using

the programmed register settings,

default OTP settings, or the externally

programmed settings. Watchdog and

safety timers are active in this state,

unless disabled in OTP or register

settings.

DONE

The termination requirements have

been met. VBAT is monitored and

Charging resumes when conditions

are met.

yVIN>VUVLO

yVIN>VBAT+VSLP

yVBAT;

!TE

Comments about naming convention:

^//9^ }Œ ^HZ_ah59^ -> Register name: event caused by user / configuration

^!^ -> Not

^y^ -> Event caused by external influence

^Event|_condition^ -> describes the event with a specific condition

图 19. State Diagram

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ILIM

VINDPM

TS_FAULT

PRE_CHARGE

2X TIMER MODE

VALID CHARGE INPUTS

RESET

CC MODE

CV MODE

DEFAULT MODE CHARGE

ICHRG+ISW+ILDO>ILIM

ICHRG+ISW+ILDO<ILIM

No HOST or I2C is not available, ILIM,

ISET, and ITERM have resistors

populated .

Default OTP charge settings are used if

no resistors are populated

Register settings used if changed in

I2C

ICHG≤0

PMID<VBAT-V_BSUP1

DYNAMIC POWER PATH MODE

BAT SUPPLEMENT MODE

BAT supplements the load at

SW/OUT and LSLDO

Charging current is reduced to supply

the load to SW/OUT and LSLDO

Battery Termination is disabled

ICHG>0

PMID<VBAT-V_BSUP2

TS_FAULT (COOL)

!TS_FAULT

VBAT>V_BATSHORTVBAT<V_BATUVLO

VBAT>V_BATUVLO+ 150mV

VBAT<V_BATSHORT

PRE-CHARGE MODE

TS_FAULT (WARM)

!TS_FAULT

½ CHARGE MODE

Charging current is reduced to half the

programmed or default current

Charge current is reduced

to the Pre-charge current

level to slowly bring up the

VBAT voltage

VIN>VIN_DPM

VIN ≤ VIN_DPM

BAT-SHORT MODE

Charge current is reduced to

the Bat-Short current level to

slowly bring up the VBAT

voltage

VBATREG œ 140mV MODE

VBATREG is reduced by 140mV from

the programmed or default VBATREG

VINDPM MODE

Charge current is reduced , 2X TIMER

mode is active (if enabled) and

termination is disabled

Comments about naming convention:

^//9^ }Œ ^HZ_ah59^ -> Register name: event caused by user/ configuration

^!^ -> Not

^y^ -> Event caused by external influence

^Event|_condition^ -> describes the event with a specific condition

图 20. Change State Diagram

9.5 Programming

9.5.1 Serial Interface Description

The device uses an I²C compatible interface to program and read many parameters. I²C is a 2-wire serial

interface developed by NXP. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures.

When the bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C

bus through open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal

processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The

master also generates specific conditions that indicate the START and STOP of data transfer. A slave device

receives and/or transmits data on the bus under control of the master device.

The device works as a slave and supports the following data transfer modes, as defined in the I²C BUS

Specification: standard mode (100 kbps) and fast mode (400kbps). The interface adds flexibility to the battery

management solution, enabling most functions to be programmed to new values depending on the instantaneous

application requirements. The I²C circuitry is powered from the battery in active battery mode. The battery

voltage must stay above V_(BATUVLO)when no V_INis present to maintain proper operation. The host must also wait

for SYS to come up before starting communication with the part.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the

F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 6A (8-bit

shifted address is D4).

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Programming (接下页)

To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I²C transactions. If the SDA line is held low longer than

t_I2CRESET, any additional commands are ignored and the I²C engine is reset. The timeout is reset with START and

repeated START conditions and stops when a valid STOP condition is sent.

9.5.2 F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in 图 21. All I²C-compatible devices should

recognize a start condition.

DATA

CLK

S

P

START Condition

STOP Condition

图 21. Start Stop Condition

The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on

the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the

SDA line to be stable during the entire high period of the clock pulse (see 图 22). All devices recognize the

address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates and acknowledge (see 图 23) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a

slave has been established.

DATA

CLK

Data Line

Stable;

Data Valid

Change

of Data

Allowed

图 22. Bit Transfer on the Serial Interface

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Programming (接下页)

Data Output

by Transmitter

Not Acknowledge

Acknowledge

Data Output

by Receiver

SCL From

Master

9

8

1

2

Clock Pulse for

Acknowledgement

START

Condition

图 23. Acknowledge on the I²C Bus

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the

slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An

acknowledge signal can either be generated by the master or by the slave, depending on which on is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see 图 24). This releases the bus and stops the communication link

with the addressed slave. All I²C compatible devices must recognize the STOP condition. Upon the receipt of a

STOP condition, all devices know that the bus is released, and wait for a START condition followed by a

matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to

prevent the slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses

not listed in this section results in 0xFFh being read out.

Recognize START or

REPEATED START

Condition

Recognize STOP or

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

P

SDA

Acknowledgement

Signal From Slave

MSB

Sr

Address

R/W

SCL

S

or

Sr

or

P

ACK

Sr

图 24. Bus Protocol

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9.6 Register Maps

9.6.1 Status and Ship Mode Control Register

Memory location 0x00h, Reset State: xx0x xxx1 (BQ25120A)

图 25. Status and Ship Mode Control Register

7 (MSB)

6

x

5

0

4

x

3

x

2

x

1

x

0 (LSB)

x

1

R

Write Only

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 12. Status and Ship Mode Control Register

Bit

Field

Type

R

Reset

Description

B7 (MSB) STAT_1

x

00 - Ready

01 - Charge in Progress

10 - Charge done

11 - Fault

B6

STAT_0

R

Status is current status only.

B5

B4

B3

B2

B1

EN_SHIPMODE

RESET_FAULT

TIMER

Write

Only

0

x

0 – Normal Operation

1 – Ship Mode Enabled

R

1 – RESET fault. Indicates when the device meets the RESET

conditions, and is cleared after I²C read.

1 – Safety timer fault. Continues to show fault after an I²C read

unless the CD pin or power have been toggled.

VINDPM_STAT

CD_STAT

0 – VIN_DPM is not active

1 – VIN_DPM is active

0 – CD low, IC enabled

1 – CD high, IC disabled

B0 (LSB) SYS_EN_STAT

1 – SW enabled

0 – SW disabled

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9.6.2 Faults and Faults Mask Register

Memory location 0x01h, Reset State: xxxx 0000 (BQ25120A)

图 26. Faults and Faults Mask Register

7 (MSB)

6

x

5

x

4

x

3

0

2

0

1

0

0 (LSB)

0

x

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 13. Faults and Faults Mask Register

Bit

Field

Type

Reset

Description

B7 (MSB) VIN_OV

R

x

1 - V_INovervoltage fault. VIN_OV continues to show fault after

an I²C read as long as OV exists

B6

B5

VIN_UV

R

x

1 - V_INundervoltage fault. VIN_UV is set when the input falls

below V_SLP. VIN_UV fault shows only one time. Once read,

VIN_UV clears until the the UVLO event occurs.

BAT_UVLO

1 – BAT_UVLO fault. BAT_UVLO continues to show fault after

an I²C read as long as BAT_UVLO conditions exist.

B4

B3

B2

B1

BAT_OCP

R

x

0

1 – BAT_OCP fault. BAT_OCP is cleared after I²C read.

VIN_OV_M

VIN_UV_M

BAT_UVLO_M

R/W

1 – Mask V_INovervoltage fault

1 – Mask V_INundervoltage fault

1 – Mask BAT UVLO fault

B0 (LSB) BAT_OCP_M

1 – Mask BAT_OCP fault

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9.6.3 TS Control and Faults Masks Register

Memory location 0x02h, Reset State: 1xxx 1000 (BQ25120A)

图 27. TS Control and Faults Masks Register (02)

7 (MSB)

1

6

x

5

x

4

x

3

1

2

0

1

0

0 (LSB)

0

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 14. TS Control and Faults Masks Register, Memory Location 0010

Bit

Field

Type

Reset

Description

B7 (MSB) TS_EN

R/W

1

0 – TS function disabled

1 – TS function enabled

B6

B5

TS_FAULT1

R

x

TS Fault mode:

00 – Normal, No TS fault

01 – TS temp < T_COLDor TS temp > T_HOT(Charging suspended)

TS_FAULT0

10 – T_COOL> TS temp > T_COLD(Charging current reduced by

half)

11 – T_WARM< TS temp < T_HOT(Charging voltage reduced by

140 mV)

B4

B3

Reserved

EN_INT

R

x

Reserved

R/W

1

0 – Disable INT function (INT only shows faults and does not

show charge status)

1 – Enable INT function (INT shows faults and charge status)

B2

B1

WAKE_M

RESET_M

R/W

0

1 – Mask interrupt from Wake Condition from MR

1 – Mask RESET interrupt from MR . The RESET output is not

masked by this bit.

B0 (LSB) TIMER_M

R/W

0

1 – Mask Timer fault interrupt (safety)

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9.6.4 Fast Charge Control Register

Memory location 0x03h, Reset State: 0001 0100 (BQ25120A)

图 28. Fast Charge Control Register

7 (MSB)

0

6

0

5

0

4

1

3

0

2

1

0

0 (LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 15. Fast Charge Control Register

Bit

Field

Type

Reset

Description

B7 (MSB) ICHRG_RANGE

R/W

0

0 – to select charge range from 5 mA to 35 mA, ICHRG bits are

1-mA steps

1 – to select charge range from 40 mA to 300 mA, ICHRG bits

are 10-mA steps

B6

B5

B4

B3

B2

B1

ICHRG_4

ICHRG_3

ICHRG_2

ICHRG_1

ICHRG_0

CE

R/W

0

1

0

1

0

Charge current 16 mA or 160 mA

Charge current 8 mA or 80 mA

Charge current 4 mA or 40 mA

Charge current 2 mA or 20 mA

Charge current 1 mA or 10 mA

0 – Charger enabled

1 – Charger is disabled

B0 (LSB) HZ_MODE

R/W

0

0 – Not high impedance mode

1 – High impedance mode

ICHRG_RANGE and ICHRG bits are used to set the charge current. The I_CHRGis calculated using the following equation: If

ICHRG_RANGE is 0, then I_CHRG= 5 mA + I_CHRGCODE x 1 mA. If ICHRG_RANGE is 1, then I_CHRG= 40 mA + I_CHRGCODE x 10 mA. If a

value greater than 35 mA (ICHRG_RANGE = 0) or 300 mA (ICHRG_RANGE = 1) is written, the setting goes to 35 mA or 300 mA

respectively except if the ICHRG bits are all 1 (that is, 11111), then the externally programmed value is used. The PRETERM bits must also

be set prior to writing all 1s to ensure the external ISET current is used as well as the proper termination and pre-charge values are used.

For IPRETERM = 5%, set the IPRETERM bits to 000001, for IPRETERM = 10%, set the IPRETERM bits to 000010, for IPRETERM = 15%,

set the IPRETERM bits to 000100, and for IPRETERM = 20%, set the iPRETERM bits to 001000. The default may be overridden by the

external resistor on ISET.

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9.6.5 Termination/Pre-Charge and I²C Address Register

Memory location 0x04h, Reset State: 0000 1110 (BQ25120A)

图 29. Termination/Pre-Charge and I²C Address Register

7 (MSB)

0

6

0

5

0

4

0

3

1

2

1

0 (LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 16. Termination/Pre-Charge and I²C Address Register

Bit

Field

Type

Reset

Description

B7 (MSB) IPRETERM_RANGE

R/W

0

0 – to select termination range from 500 µA to 5 mA,

IPRETERM bits are 500-µA steps

1 – to select charge range from 6 mA to 37 mA, IPRETERM bits

are 1-mA steps

B6

B5

B4

B3

B2

B1

IPRETERM_4

IPRETERM_3

IPRETERM_2

IPRETERM_1

IPRETERM_0

TE

R/W

0

1

Termination current 8 mA or 16 mA

Termination current 4 mA or 8 mA

Termination current 2 mA or 4 mA

Termination current 1 mA or 2 mA

Termination current 500 µA or 1 mA

0 – Disable charge current termination

1 – Enable charge current termination

B0 (LSB)

R/W

0

IPRETERM_RANGE and IPRETERM bits are used to set the termination and pre-charge current. The I_TERMis calculated using the

following equation: If IPRETERM_RANGE is 0, then I_TERM= 500 µA + I_TERMCODE x 500 µA. If IPRETERM_RANGE is 1, then I_TERM= 6

mA + I_TERMCODE x 1 mA. If a value greater than 5 mA (IPRETERM_RANGE = 0) is written, the setting goes to 5 mA. Termination is

disabled if any loop other than CC or DV in control, such as VINDPM, and TS/Cool. The default may be overridden by the external resistor

on IPRETERM.

9.6.6 Battery Voltage Control Register

Memory location 0x05h, Reset State: 0111 1000 (BQ25120A)

图 30. Battery Voltage Control Register

7 (MSB)

0

6

1

5

1

4

1

3

1

2

0

1

0

0 (LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 17. Battery Voltage Control Register

Bit

Field

Type

R/W

Reset

Description

B7 (MSB) VBREG_6

0

1

0

Battery Regulation Voltage: 640 mV

Battery Regulation Voltage: 320 mV

Battery Regulation Voltage: 160 mV

Battery Regulation Voltage: 80 mV

Battery Regulation Voltage: 40 mV

Battery Regulation Voltage: 20 mV

Battery Regulation Voltage: 10 mV

B6

B5

VBREG_5

VBREG_4

VBREG_3

VBREG_2

VBREG_1

VBREG_0

B4

B3

B2

B1

B0 (LSB)

VBREG Bits: Use VBREG bits to set the battery regulation threshold. The V_BATREGis calculated using the following equation: V_BATREG= 3.6

V + V_BREGCODE x 10 mV. The charge voltage range is from 3.6 V to 4.65 V. If a value greater than 4.65 V is written, the setting goes to

4.65 V.

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9.6.7 SYS VOUT Control Register

Memory location 0x06h, Reset State: 1010 1010 (BQ25120A)

图 31. SYS VOUT Control Register

7 (MSB)

1

6

0

5

1

4

0

3

1

2

0

1

0 (LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 18. SYS VOUT Control Register

Bit

Field

Type

Reset

Description

B7 (MSB) EN_SYS_OUT

R/W

1

0 – Disable SW

1 – Enable SW

(When disabled, output is pulled low)

B6

B5

SYS_SEL1

SYS_SEL0

R/W

0

1

00 – 1.1 V and 1.2 V selection

01 – 1.3 V through 2.8 V selection

10 – 1.5V through 2.75 V selection

11 – 1.8 V through 3.3 V selection

B4

B3

SYS_VOUT_3

SYS_VOUT_2

SYS_VOUT_1

SYS_VOUT_0

R/W

0

1

0

1

0

OUT Voltage: 800 mV step if SYS_SEL is 01 or 11

OUT Voltage: 400 mV step if SYS_SEL is 01 or 11

OUT Voltage: 200 mV step if SYS_SEL is 01 or 11

OUT Voltage: 100 mV step if SYS_SEL is 01 or 11

B2

B1

B0 (LSB)

SW_VOUT Bits: Use SYS_SEL and SYS_VOUT bits to set the output on SYS. The SYS voltage is calculated using the following equation:

See table below for all VOUT values that can be programmed through SYS_SEL and SYS_VOUT.

If SYS_SEL = 01, then SYS = 1.30 V + SYS_VOUTCODE x 100 mV.

If SYS_SEL = 11, then SYS = 1.80 V + SYS_VOUTCODE x 100 mV.

表 19. SYS_SEL Codes

SYS_SEL

00

SYS_VOUT

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

TYP

1.1

UNIT

V

00

1.2

V

00

1.25

1.333

1.417

1.5

V

00

V

00

V

00

V

00

1.583

1.667

1.75

1.833

1.917

2

V

00

V

00

V

00

V

00

V

00

V

00

2.083

2.167

2.25

2.333

1.3

V

00

V

00

V

00

V

01

V

01

1.4

V

01

1.5

V

01

1.6

V

01

1.7

V

01

1.8

V

01

1.9

V

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表 19. SYS_SEL Codes (接下页)

SYS_SEL

01

10

11

SYS_VOUT

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

TYP

2

UNIT

V

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

1.5

1.583

1.667

1.75

1.833

1.917

2

2.083

2.167

2.25

2.333

2.417

2.5

2.583

2.667

2.75

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

3.1

3.2

3.3

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9.6.8 Load Switch and LDO Control Register

Memory location 0x07h, Reset State: 0111 110x (BQ25120A)

图 32. Load Switch and LDO Control Register

7 (MSB)

0

6

1

5

1

4

1

3

1

2

1

0

0 (LSB)

x

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 20. Load Switch and LDO Control Register

Bit

Field

Type

Reset

Description

B7 (MSB) EN_LS_LDO

R/W

0

0 – Disable LS/LDO

1 – Enable LS/LDO

B6

B5

B4

B3

B2

B1

LS_LDO_4

LS_LDO_3

LS_LDO_2

LS_LDO_1

LS_LDO_0

R/W

1

0

LS/LDO Voltage: 1600 mV

LS/LDO Voltage: 800 mV

LS/LDO Voltage: 400 mV

LS/LDO Voltage: 200 mV

LS/LDO Voltage: 100 mV

B0 (LSB) MRRESET_VIN

R/W

0 – Reset sent when MR Reset time is met

1 – Reset sent when MR Reset time is met and V_UVLO+ V_SLP

VIN < V_OVP

<

LS_LDO Bits: Use LS_LDO bits to set the LS/LDO output. The LS/LDO voltage is calculated using the following equation: LS/LDO = 0.8 V

+ LS_LDOCODE x 100 mV. If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -

V_DROPOUT. The LS_LDO output can only be changed when the EN_LS_LDO and LSCTRL pin has disabled the output.

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9.6.9 Push-button Control Register

Memory location 0x08h, Reset State: 0110 10xx (BQ25120A)

图 33. Push-button Control Register

7 (MSB)

0

6

1

5

1

4

0

3

1

2

0

1

x

0 (LSB)

x

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 21. Push-button Control Register

Bit

Field

Type

Reset

Description

B7 (MSB) MRWAKE1

R/W

0

MR Timer adjustment for WAKE1:

0 – 80 ms < MR

1 – 600 ms < MR

B6

B5

MRWAKE2

MRREC

R/W

1

MR Timer adjustment for WAKE2:

0 –1000 ms < MR

1 – 1500 ms < MR

0 – After Reset, device enters Ship mode

1 – After Reset, device enters Hi-Z Mode

B4

B3

MRRESET_1

MRRESET_0

R/W

0

1

MR Timer adjustment for reset:

00 – 5 s ± 20%

01 - 9 s ± 20%

10 - 11 s ± 20%

11 - 15 s ± 20%

B2

B1

PGB_MR

WAKE1

R/W

R

0

x

0 – Output functions as PG

1 – Output functions as voltage shifted push-button (MR) input

1 – WAKE1 status. Indicates when the device meets the WAKE1

conditions, and is cleared after I²C read.

B0 (LSB) WAKE2

R

1 – WAKE2 status. Indicates when the device meets the WAKE2

conditions, and is cleared after I²C read.

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9.6.10 ILIM and Battery UVLO Control Register

Memory location 0x09h, Reset State: 0000 1010 (BQ25120A)

图 34. ILIM and Battery UVLO Control Register

7 (MSB)

0

6

0

5

0

4

0

3

1

2

0

1

0 (LSB)

0

Write

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 22. ILIM and Battery UVLO Control Register, Memory Location 1001

Bit

Field

Type

Reset

Description

B7 (MSB) RESET

Write

only

0

Write:

1- Reset all registers to default values

0 – No effect

Read: Always get 0

B6

R/W

0

1

0

1

0

N/A

B5

B4

B3

B2

B1

INLIM_2

INLIM_1

INLIM_0

BUVLO_2

BUVLO_1

Input Current Limit: 200 mA

Input Current Limit: 100 mA

Input Current Limit: 50 mA

000, 001: RESERVED

010: BUVLO = 3.0 V

011: BUVLO = 2.8 V

100: BUVLO = 2.6 V

101: BULVO = 2.4 V

110: BUVLO = 2.2 V

111: BUVLO = 2.2V

B0 (LSB) BUVLO_0

INLIM Bits: Use INLIM bits to set the input current limit. The I_(INLIM)is calculated using the following equation: I_(INLIM)= 50 mA +

I_(INLIM)CODE x 50 mA. The default may be overridden by the external resistor on ILIM.

9.6.11 Voltage Based Battery Monitor Register

Memory location 0x0Ah, Reset State: 0xxx xxxx (BQ25120A)

图 35. Voltage Based Battery Monitor Register

7 (MSB)

0

6

x

5

x

4

x

3

x

2

x

1

x

0 (LSB)

x

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 23. Voltage Based Battery Monitor Register, Memory Location 1010

Bit

Field

Type

R/W

R

Reset

Description

B7 (MSB) VBMON_READ

0

x

Write 1 to initiate a new VBATREG reading. Read always 0.

B6

B5

VBMON_RANGE_1

VBMON_RANGE_0

11 – 90% to 100% of VBATREG

10 – 80% to 90% of VBATREG

01 – 70% to 80% of VBATREG

00 – 60% to 70% of VBATREG

R

B4

B3

B2

VBMON_TH_2

VBMON_TH_1

VBMON_TH_0

R

x

111 – Above 8% of VBMON_RANGE

110 – Above 6% of VBMON_RANGE

011 – Above 4% of VBMON_RANGE

010 – Above 2% of VBMON_RANGE

001 – Above 0% of VBMON_RANGE

B1

R

x

N/A

B0 (LSB)

The VBMON registers are used to determine the battery voltage. Before entering a low power state, the device will determine the voltage

level by starting at VBMON_RANGE 11 (90% to 100%), and if VBMON_TH of 000 is read, then it will move to VBMON_RANGE 10 (80% to

90%) and continue until a non 000 value of VBMON_TH is found. If this does not happen, then VBMON_RANGE and VBMON_TH will be

written with 00 000. The VBMON_READ bit can be used to initiate a new reading by writing a 1 to it. Example: A reading of 10 011

indicated a VBAT voltage of between 84% and 86% of the VBATREG setting.

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9.6.12 VIN_DPM and Timers Register

Memory location 0x0Bh, Reset State: 0100 1010 (BQ25120A)

图 36. VIN_DPM and Timers Register

7 (MSB)

0

6

1

5

0

4

0

3

0

2

0

1

0 (LSB)

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 24. VIN_DPM and Timers Register

Bit

Field

Type

Reset

Description

B7 (MSB) VINDPM_ON

R/W

0

0 - enable VINDPM

1 - disable VINDPM

B6

B5

B4

B3

VINDPM_2

VINDPM_1

VINDPM_0

2XTMR_EN

R/W

1

0

Input V_{(IN_DPM)}voltage: 400 mV

Input V_{(IN_DPM)}voltage: 200 mV

Input V_{(IN_DPM)}voltage: 100 mV

0 – Timer is not slowed at any time

1 – Timer is slowed by 2x when in any control other than CC or

CV

B2

B1

TMR_1

TMR_0

R/W

0

1

Safety Timer Time Limit

00 – 30 minute fast charge

01 – 3 hour fast charge

10 – 9 hour fast charge

11 – Disable safety timers

B0 (LSB)

0

The VINDPM threshold is set using the following equation: VINDPM = 4.2 + VINDPM_CODE x 100 mV

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI's customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

A typical design is shown in 图 37. This design uses the BQ25120A with external resistors for ILIM, IPRETERM,

and ISET. These are not needed if these values are set with a host controller through I²C commands. This

design also shows the TS resistors, which is also optional.

When powering up in default mode the battery voltage is the default for the part (4.2 V), the SYS output is the

default (1.8 V). External resistors set the charge current to 40 mA, the termination current to 10% (4 mA), and

the input current limit to 100 mA. If the I²C interface is used the part goes to the internal default settings until

changed by the host.

10.2 Typical Application

图 37. Typical Application Circuit

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Typical Application (接下页)

10.2.1 Design Requirements

This application is for a low power system that has varying loads from less than 10 mA up to 300 mA. It must

work with a valid adaptor or USB power input. Below are some of the key components that are needed in normal

operation. For this example, the fast charge current is 50 mA, input current limit is 400 mA and the pre-charge

and termination current is 10% of the fast charge current.

•

Supply voltage = 3.4 V to 20 V

Fast charge current is default to 10 mA with ISET pin shorted to ground. To program the fast charge current,

connect an external resistor from ISET to ground.

•

Input current limit is default to 100 mA with ILIM pin shorted to ground. To program the input current limit,

connect an external resistor from ILIM to ground.

Termination current threshold is default to 2 mA with IPRETERM pin shorted to ground. To program the input

current limit, connect an external resistor from IPRETERM to ground.

•

A 2.2-µH inductor is needed between SW pin and SYS pin for PWM output.

TS- Battery temperature sense needs a NTC connected on TS pin.

10.2.2 Detailed Design Procedure

See 图 37 for an example of the application diagram.

10.2.2.1 Default Settings

•

• Connect ISET, ILIM and IPRETERM pins to ground to program fast charge current to 10mA, input current

limit to 100mA and pre-charge/termination current to 2 mA.

•

BAT_UVLO = 3 V.

VSYS = 1.8 V

LS/LDO is LS

VBREG = 4.2 V

VIN_DPM is enabled and VIN_DPM Threshold = 4.6 V.

Safety Timer = 3 hr

If the function is not needed, connect TS to the center tab of the resistor divider between V_INand the ground.

(pull up resistor = 14 kΩ, pull down resistor = 14.3 kΩ)

10.2.2.2 Choose the Correct Inductance and Capacitance

Refer to the Buck (PWM) Output section for the detailed procedure to determine the optimal inductance and

capacitance for the buck output.

10.2.2.3 Calculations

10.2.2.3.1 Program the Fast Charge Current (ISET)

R_ISET= K_ISET/ICHG

(10)

(11)

K_ISET= 200 AΩ from the Specifications table

R_ISET= 200 AΩ / 0.05A = 4 kΩ

Select the closest standard value, which in this case is 4.99 kΩ. Connect this resistor between ISET pin and

GND.

10.2.2.3.2 Program the Input Current Limit (ILIM)

R_ILIM= K_ILIM/I_{I_MAX}

(12)

(13)

K_ILIM= 200 AΩ from the Specifications table

R_ILIM= 200 AΩ / 0.4A = 500 Ω

Select the closest standard value, which in this case is 499 Ω. Connect this resistor between ILIM pin and GND.

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Typical Application (接下页)

10.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)

According to 表 3, the RIPRETERM is 4990 Ω for 10% termination threshold. Therefore, connect a 4.99 kΩ

resistor between IPRETERM pin and GND.

10.2.2.3.4 TS Resistors (TS)

The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. This device

uses JEITA temperature profile which has four temperature thresholds. Refer to Specifications for the detailed

thresholds number.

The TS circuit is shown in 图 18. The resistor values can be calculated using 公式 1 and 公式 2.

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Typical Application (接下页)

10.2.3 Application Performance Curves

10.2.3.1 Charger Curves

Time 100 ms/div

Time 4 ms/div

图 39. Power Supply Connected to V_IN

图 38. Battery Connected to V_(BAT)

Time 4 ms/div

图 41. Exiting DPPM Mode

图 40. Entering DPPM Mode

Time 4 ms/div

图 42. Entering Battery Supplement Mode

图 43. Exiting Battery Supplement Mode

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Typical Application (接下页)

Time 4 ms/div

Time 2 ms/div

图 45. OVP Fault

图 44. Charger On/Off Using CD

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Typical Application (接下页)

10.2.3.2 SYS Output Curves

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

2.7 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

2.7 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

1E-6

1E-5

0.0001

0.001

0.01

0.10.2 0.5

1E-6

1E-5

0.0001

0.001

0.01

0.10.2 0.5

Load Current (A)

D001

D004

T_A= 25°C

V_SYS= 1.2 V

T_A= 25°C

V_SYS= 1.5 V

图 46. 1.2 V_SYSSystem Efficiency

图 47. 1.5 V_SYSSystem Efficiency

100%

90%

80%

70%

60%

50%

40%

100%

90%

80%

70%

60%

50%

40%

2.7 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

1E-6

1E-5

0.0001

0.001

0.01

0.10.2 0.5

1E-6

1E-5

0.0001

0.001

0.01

0.10.2 0.5

Load Current (A)

D007

D010

T_A= 25°C

V_SYS= 1.8 V

T_A= 25°C

V_SYS= 2.5 V

图 48. 1.8 V_SYSSystem Efficiency

图 49. 2.5 V_SYSSystem Efficiency

100%

90%

80%

70%

60%

50%

40%

1.238

1.228

1.218

1.208

1.198

1.188

1.178

1.168

1.158

2.7 V

3 V

3.6 V

3.8 V

4.2 V

3.6 V BAT

3.8 V BAT

4.2 V BAT

1E-6

1E-5

0.0001

0.001

0.01

0.10.2 0.5

1E-6

1E-5

0.0001

0.001

0.01

0.1

0.5

Load Current (A)

D013

D003

T_A= 25°C

V_SYS= 3.3 V

T_A= 25°C

V_SYS= 1.2 V

图 50. 3.3 V_SYSSystem Efficiency

图 51. 1.2 V_SYSLoad Regulation

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Typical Application (接下页)

1.5475

1.857

1.837

1.817

1.797

1.777

1.757

1.737

1.5275

1.5075

1.4875

2.7 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

2.7 V BAT

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

1.4675

1.4475

1E-6

1E-5

0.0001

0.001

0.01

0.1

0.5

1E-6

1E-5

0.0001

0.001

0.01

0.1

0.5

Load Current (A)

D006

D009

T_A= 25°C

V_SYS= 1.5 V

T_A= 25°C

V_SYS= 1.8 V

图 52. 1.5 V_SYSLoad Regulation

图 53. 1.8 V_SYSLoad Regulation

2.5725

3.3845

3.3345

3.2845

3.2345

3.1845

2.5525

2.5325

2.5125

2.4925

2.4725

2.4525

2.4325

2.4125

3.0 V BAT

3.6 V BAT

3.8 V BAT

4.2 V BAT

3.8 V BAT

4.2 V BAT

1E-6

1E-5

0.0001

0.001

0.01

0.1

0.5

1E-6

1E-5

0.0001

0.001

0.01

0.1

0.5

Load Current (A)

D012

D015

T_A= 25°C

V_SYS= 2.5 V

T_A= 25°C

V_SYS= 3.3 V

图 54. 2.5 V_SYSLoad Regulation

图 55. 3.3 V_SYSLoad Regulation

1.238

1.228

1.218

1.208

1.198

1.188

1.178

1.168

1.158

1.5475

1.5275

1.5075

1.4875

1.4675

1.4475

1 PA

10 PA

100 PA

1 mA

10 mA

100 mA

1 PA

10 PA

100 PA

1 mA

10 mA

100 mA

3

3.2

3.4

3.6

3.8

4

4.2

4

3

3.2

3.4

3.6

3.8

4.2

VBAT Voltage (V)

D002

D005

T_A= 25°C

V_SYS= 1.2 V

T_A= 25°C

V_SYS= 1.5 V

图 56. 1.2 V_SYSLine Regulation

图 57. 1.5 V_SYSLine Regulation

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Typical Application (接下页)

1.857

2.5725

2.5525

2.5325

2.5125

2.4925

2.4725

2.4525

2.4325

2.4125

1.837

1.817

1.797

1.777

1.757

1 PA

1 mA

10 mA

100 mA

1 PA

10 PA

100 PA

1 mA

10 mA

100 mA

300ma

10 PA

100 PA

1.737

4

3

3.2

3.4

3.6

3.8

4.2

3

3.2

3.4

3.6

3.8

4

4.2

VBAT Voltage (V)

D008

D011

T_A= 25°C

V_SYS= 1.8 V

T_A= 25°C

V_SYS= 2.1 V

图 58. 1.8 V_SYSLine Regulation

图 59. 2.1 V_SYSLine Regulation

3.3845

3.3345

3.2845

3.2345

3.1845

1400

1200

1000

800

600

400

1 PA

10 PA

100 PA

1 mA

10 mA

100 mA

200

5 V V_BAT

4.2 V V_BAT

3.6 V V_BAT

3 V V_BAT

2.5 V V_BAT

0

50

100

150

200

250

300

3.8

4

4.2

Load Current (mA)

VBAT Voltage (V)

D023

D014

T_A= 25°C

V_SYS= 3.3 V

图 61. 1.8 V_SYSSwitching Frequency vs Load Current

图 60. 3.3 V_SYSLine Regulation

SW

Time 40 ms/div

I_LOAD= 10 µA

图 62. Light Load Operation Showing SW

I_LOAD= 100 mA

图 63. Light Load Operation Showing SW

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Typical Application (接下页)

SW

Time 40 ms/div

Time 2 ms/div

I_LOAD= 1 mA

I_LOAD= 10 mA

图 64. Light Load Operation Showing SW

图 65. Light Load Operation Showing SW

SW

Time 400 ns/div

I_LOAD= 100 mA

I_LOAD= 200 mA

图 66. Light Load Operation Showing SW

图 67. Light Load Operation Showing SW

SW

Time 4 ms/div

Time 400 ns/div

I_LOAD= 300 mA

V_SYS= 1.2 V

图 68. Light Load Operation Showing SW

图 69. 1.2 V_SYSLoad Transient, 0 to 50 mA

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Typical Application (接下页)

SW

Time 4 ms/div

V_SYS= 1.8 V

V_SYS= 2.1 V

图 70. 1.8 V_SYSLoad Transient, 0 to 50 mA

图 71. 2.1 V_SYSLoad Transient, 0 to 50 mA

SW

Time 4 ms/div

V_SYS= 2.5 V

V_SYS= 3.3 V

图 73. 3.3 V_SYSLoad Transient, 0 to 50 mA

图 72. 2.5 V_SYSLoad Transient, 0 to 50 mA

SW

Time 4 ms/div

V_SYS= 1.2 V

图 74. 1.2 V_SYSLoad Transient, 0 to 200 mA

V_SYS= 1.8 V

图 75. 1.8 V_SYSLoad Transient, 0 to 200 mA

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Typical Application (接下页)

SW

Time 4 ms/div

V_SYS= 2.1 V

V_SYS= 2.5 V

图 76. 2.1 V_SYSLoad Transient, 0 to 200 mA

图 77. 2.5 V_SYSLoad Transient, 0 to 200 mA

SW

Time 4 ms/div

Time 1 ms/div

V_SYS= 3.3 V

图 79. Startup Showing SS on SYS in PWM Mode

图 78. 3.3 V_SYSLoad Transient, 0 to 200 mA

Time 20 ms/div

图 80. Short Circuit and Recovery for SYS

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Typical Application (接下页)

10.2.3.3 Load Switch and LDO Curves

Time 20 ms/div

Time 400 ms/div

图 81. Short Circuit and Recovery for LS

图 82. Startup Showing SS on LS/LDO Output

Time 4 ms/div

V_SLSDO= 0.8 V

V_SLSDO= 1.2 V

图 84. 1.2 V_LSLDOLoad Transient, 0 to 10 mA

图 83. 0.8 V_LSLDOLoad Transient, 0 to 10 mA

Time 4 ms/div

V_SLSDO= 1.8 V

V_SLSDO= 2.5 V

图 86. 2.5 V_LSLDOLoad Transient, 0 to 10 mA

图 85. 1.8 V_LSLDOLoad Transient, 0 to 10 mA

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Typical Application (接下页)

Time 4 ms/div

V_SLSDO= 3.3 V

V_SLSDO= 0.8 V

图 88. 0.8 V_LSLDOLoad Transient, 0 to 100 mA

图 87. 3.3 V_LSLDOLoad Transient, 0 to 10 mA

Time 4 ms/div

V_SLSDO= 1.8 V

图 90. 1.8 V_LSLDOLoad Transient, 0 to 100 mA

V_SLSDO= 1.2 V

图 89. 1.2 V_LSLDOLoad Transient, 0 to 100 mA

Time 4 ms/div

V_SLSDO= 2.5 V

图 91. 2.5 V_LSLDOLoad Transient, 0 to 100 mA

V_SLSDO= 3.3 V

图 92. 3.3 V_LSLDOLoad Transient, 0 to 100 mA

59

bq25120A

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

Typical Application (接下页)

10.2.3.4 LS/LDO Output Curves

Time 400 ms/div

Time 20 ms/div

图 94. Short Circuit and Recovery for LDO

图 93. Startup Showing SS on LS/LDO in LDO Mode

60

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ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

Typical Application (接下页)

10.2.3.5 Timing Waveforms Curves

Time 10 ms/div

Time 2 ms/div

图 95. Show PG and INT Timing (VI_NInsertion)

图 96. Show PG and INT Timing (V_INRemoval)

Time 400 ms/div

图 97. PG Functions as Shifted MR Output

图 98. PG Functions as Shifted MR Output

Time 200 ms/div

Wake1 = 500 ms

Wake2 = 1 s

Wake1 = 50 ms

Wake2 = 1.5 s

图 99. Show MR Timing

图 100. Show MR Timing

61

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Typical Application (接下页)

Time 1 s/div

RESET = 4 s

RESET = 8 s

图 101. RESET Timing

图 102. RESET Timing

Time 2 s/div

RESET = 14 s

图 103. RESET Timing

图 104. RESET Timing and Enter Ship Mode

11 Power Supply Recommendations

It is recommended to use a power supply that is capable of delivering 5 V at the input current limit set by the

BQ25120A.

62

bq25120A

www.ti.com.cn

ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

12 Layout

12.1 Layout Guidelines

•

Keep the core components of the system close to each other and the device.

Keep the PMID, IN, and SYS caps as close to their respective pins as possible. Place the bypass caps for

PMID, SYS, and LSLDO close to the pins.

•

Place the GNDs of the PMID and IN caps close to each other.

Don’t route so the power planes are interrupted.

12.2 Layout Example

图 105. BQ25120A Layout

63

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ZHCSHF5A –MAY 2017–REVISED JANUARY 2018

www.ti.com.cn

13 器件和文档支持

13.1 器件支持

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

13.2 商标

All trademarks are the property of their respective owners.

13.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

64

PACKAGE OUTLINE

YFP0025

DSBGA - 0.5 mm max height

SCALE 8.000

DIE SIZE BALL GRID ARRAY

B

E

A

BALL A1

CORNER

D

0.30

0.25

C

0.5 MAX

SEATING PLANE

0.05 C

0.19

0.13

1.6 TYP

SYMM

E

D

C

SYMM

1.6

TYP

D: Max = 2.56 mm, Min = 2.5 mm

E: Max = 2.498 mm, Min =2.438 mm

B

0.4 TYP

A

3

4

5

2

1

0.25

25X

0.21

0.4 TYP

0.015

C A B

4225306/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFP0025

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

25X ( 0.23)

(0.4) TYP

3

4

5

1

2

A

B

C

SYMM

D

E

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 40X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

(

0.23)

METAL

(

0.23)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225306/A 09/2019

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFP0025

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(R0.05) TYP

3

25X ( 0.25)

4

5

1

2

A

(0.4) TYP

B

C

METAL

TYP

SYMM

D

E

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 40X

4225306/A 09/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25120AYFPR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源路径、集成 LDO 和降压转换器 1.8V 默认输出的 300mA 线性电池充电器 \| YFP \| 25 \| -40 to 85 电池转换器
文件：	总72页 (文件大小：2454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25120AYFPR [TI]

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