BQ25303J_技术文档

BQ25303J

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BQ25303J Standalone 1-Cell, 17-V, 3.0-A Battery Charger with JEITA Battery

Temperature Monitoring

1 Features

2 Applications

•

Standalone charger and easy to configure

High-efficiency, 1.2-MHz, synchronous switch-

mode buck charger

– 92.5% charge efficiency at 2A from 5-V input

for 1-cell battery

•

Wireless speaker

Gaming

Cradle charger

Medical

3 Description

– 91.8% charge efficiency at 2A from 9-V input

for 1-cell battery

The BQ25303J is a highly-integrated standalone

switch-mode battery charger for 1-cell Li-ion and Li-

polymer batteries. The BQ25303J supports 4.1-V to

17-V input voltage and 3-A fast charge current. The

integrated current sensing topology of the device

enables high charge efficiency and low BOM cost.

The best-in-class 200-nA low quiescent current of the

device conserves battery energy and maximizes the

shelf time for portable devices. The BQ25303J is

available in a 3x3 WQFN package for easy 2-layer

layout and space limited applications.

•

Single input to support USB input and high voltage

adaptors

– Support 4.1-V - 17-V input voltage range with

28-V absolute maximum input voltage rating

– Input Voltage Dynamic Power Management

(VINDPM) tracking battery voltage

High integration

– Integrated reverse blocking and synchronous

switching MOSFET

– Internal input and charge current sense

– Internal loop compensation

Device Information

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

– Integrated bootstrap diode

BQ25303J

RTE

3.00mm x 3.00mm

•

4.1-V / 4.2-V / 4.35-V / 4.4-V charge voltage

3.0-A maximum fast charge current

200-nA low battery leakage current at 4.5-V V_BAT

4.25-µA VBUS supply current in IC disable mode

Charge current thermal regulation at 120°C

Precharge current: 10% of fast charge current

Termination current: 10% of fast charge current

Charge accuracy

– ±0.5% charge voltage regulation

– ±10% charge current regulation

Safety

– Thermal regulation and thermal shutdown

– Input Under-Voltage Lockout (UVLO) and Over-

Voltage Protection (OVP)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

L

VBUS

SW

VBUS

Q1

Q2

2.2 …F

10 …F

2.2 …F

10 …F

47 nF

BTST

GND

Q3

PMID

•

REGN

BAT

REGN

ICHG

VSET

TS

– Battery overcharge protection

– Safety timer for precharge and fast charge

– Charge disabled if current setting pin ICHG is

open or short

REGN

POL

1 kꢀ

STAT

EN

– JEITA Battery temperature protection

– Fault report on STAT pin

Thermal Pad

•

Available in WQFN 3x3-16 package

Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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BQ25303J

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................5

8 Specifications.................................................................. 7

8.1 Absolute Maximum Ratings........................................ 7

8.2 ESD Ratings .............................................................. 7

8.3 Recommended Operating Conditions ........................7

8.4 Thermal Information ...................................................8

8.5 Electrical Characteristics.............................................8

8.6 Timing Requirements ...............................................10

8.7 Typical Characteristics..............................................12

9 Detailed Description......................................................13

9.1 Overview...................................................................13

9.2 Functional Block Diagram.........................................14

9.3 Feature Description...................................................15

9.4 Device Functional Modes..........................................20

10 Application and Implementation................................21

10.1 Application Information........................................... 21

10.2 Typical Applications................................................ 21

11 Power Supply Recommendations..............................26

12 Layout...........................................................................27

12.1 Layout Guidelines................................................... 27

12.2 Layout Example...................................................... 27

13 Device and Documentation Support..........................29

13.1 Device Support....................................................... 29

13.2 Receiving Notification of Documentation Updates..29

13.3 Support Resources................................................. 29

13.4 Trademarks.............................................................29

13.5 Electrostatic Discharge Caution..............................29

13.6 Glossary..................................................................29

14 Mechanical, Packaging, and Orderable

Information.................................................................... 30

4 Revision History

DATE

REVISION

NOTES

February 2021

*

Initial release.

2

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5 Description (continued)

The BQ25303J supports 4.1-V to 17-V input to charge single cell batteries. The BQ25303J provides up to 3-A

continuous charge current to a single cell 1S battery The device features fast charging for portable devices. Its

input voltage regulation delivers maximum charging power to the battery from input source. The solution is highly

integrated with an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), and low-side

switching FET (LSFET, Q3).

The BQ25303J features lossless integrated current sensing to reduce power loss and BOM cost with minimized

component count. It also integrates a bootstrap diode for the high-side gate drive and battery temperature

monitor to simplify system design. The device initiates and completes a charging cycle without host control. The

BQ25303J charge voltage and charge current are set by external resistors. The BQ25303J detects the charge

voltage setting at startup and charges the battery in four phases: battery short, pre-conditioning, constant

current, and constant voltage. At the end of the charging cycle, the charger automatically terminates if the

charge current is below the termination current threshold and the battery voltage is above the recharge

threshold. When the battery voltage falls below the recharge threshold, the charger will automatically start

another charging cycle. The charger provides various safety features for battery charging and system

operations, including battery temperature monitoring based on negative temperature coefficient (NTC)

thermistor, charge safety timer, input over-voltage and over-current protections, as well as battery over-voltage

protection. Pin open and short protection is also built in to protect against the charge current setting pin ICHG

accidently open or short to GND. The thermal regulation regulates charge current to limit die temperature during

high power operation or high ambient temperature conditions.

The STAT pin output reports charging status and fault conditions. When the input voltage is removed, the device

automatically enters HiZ mode with very low leakage current from battery to the charger device. The BQ25303J

is available in a 3 mm x 3 mm thin WQFN package.

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6 Device Comparison Table

BQ25300

BQ25302

BQ25303J

BQ25306

Battery Cells in Series

Input Operation Voltage

Charge Voltage

1

1, 2

4.1V to 17V

4.1V to 6.2V

4.1V to 17V

3.6V, 4.15V, 4.2V, 4.05V 4.1V, 4.35V, 4.4V, 4.2V 4.1V, 4.35V, 4.4V, 4.2V

programmable from 3.4V to

9.0V

Maximum Fast Charge Current 3.0A

ICHG

2.0A

3.0A

Battery Temperature Protection Cold/Hot

(JEITA or Cold/Hot)

Cold/Hot

JEITA

Cold/Hot

4

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7 Pin Configuration and Functions

VBUS

REGN

STAT

ICHG

1

2

3

4

12

11

10

9

GND

BAT

Thermal

Pad

VSET

5

6

7

8

(Not to scale)

Figure 7-1. RTE Package 16-Pin WQFN Top View

Table 7-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between

VBUS and PMID with VBUS on source. Place a 2.2uF ceramic capacitor from VBUS to GND and place it

as close as possible to IC.

VBUS

1

P

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of high-side MOSFET

(HSFET). Place ceramic 10μF on PMID to GND and place it as close as possible to IC.

PMID

SW

16

13,14

15

P

Switching node. Connected to output inductor. Internally SW is connected to the source of the n-channel

HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST.

High-side FET driver supply. Internally, the BTST is connected to the cathode of the internal boost-strap

diode. Connect the 0.047μF bootstrap capacitor from SW to BTST.

BTST

GND

REGN

BAT

P

Ground. Connected directly to thermal pad on the top layer. A single point connection is recommended

between power ground and analog ground near the IC GND pins.

11,12

2

P

Low-side FET driver positive supply output. Connect a 2.2μF ceramic capacitor from REGN to GND. The

capacitor should be placed close to the IC.

P

Battery voltage sensing input. Connect this pin to the positive terminal of the battery pack and the node of

inductor output terminal. 10-µF capacitor is recommended to connect to this pin.

10

AI

Battery temperature voltage input. Connect a negative temperature coefficient thermistor (NTC). Program

temperature window with a resistor divider from REGN to TS and TS to GND. Charge suspends when TS

pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-

kΩ resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.

TS

7

4

AI

Charge current program input. Connect a 1% resistor RICHG from this pin to ground to program the

charge current as ICHG = K_ICHG/ R_ICHG(K_ICHG= 40,000). No capacitor is allowed to connect at this pin.

When ICHG pin is pulled to ground or left open, the charger stop switching and STAT pin starts blinking.

ICHG

Charge status indication output. This pin is open drain output. Connect this pin to REGN via a current

limiting resistor and LED. The STAT pin indicates charger status as:

•

Charge in progress: STAT pin is pulled LOW

Charge completed, charge disabled by EN: STAT pin is OPEN

Fault conditions: STAT pin blinks.

STAT

3

AO

Charge Voltage Setting Input. VSET pin sets battery charge voltage. Program battery regulation voltage

with a resistor pull-down from VSET to GND:

•

Floating (R > 200kΩ±10%): 4.1V

Shorted to GND (R < 510Ω): 4.2V

R = 51kΩ ± 10%: 4.35V

VSET

POL

9

5

AI

R = 10kΩ ± 10%: 4.4V

The maximum allowed capacitance on this pin is 50pF.

EN pin polarity selection.

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Table 7-1. Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

EN

NO.

6

Device disable input. With POL pin floating, the device is enabled with EN pin floating or pulled low, and

the device is disabled if EN pin is pulled high. With POL pin grounded, the device is enabled with EN pin

pulled high, and the device is disabled with EN pin pulled low or floating.

AI

-

NC

8

No connection. Keep this pin floating or grounded.

Ground reference for the device that is also the thermal pad used to conduct heat from the device. This

connection serves two purposes. The first purpose is to provide an electrical ground connection for the

device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB.

This pad should be tied externally to a ground plane. Ground layer(s) are connected to thermal pad

through vias under thermal pad.

Thermal Pad

17

-

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,

P = Power

6

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8 Specifications

8.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–2

MAX

28

UNIT

V

VBUS (converter not switching)

PMID (converter not switching)

–0.3

28

V

–2(–3 for

10ns)

SW

20

V

Voltage Range (with respect to

BTST

-0.3

–0.3

25.5

11

V

GND)

BAT

REGN

5.5

11

V

VSET

V

ICHG, REGN, TS, STAT, POL, EN

5.5

6

V

Voltage Range

BTST to SW

STAT

V

Output Sink Current

mA

°C

Output Sink Current

REGN

16

Operating junction temperature, T_J

Storage temperature, T_stg

–40

–65

150

(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

4.4

3

UNIT

V

V_BAT

I_VBUS

I_SW

Battery voltage

Input current

A

Output current (SW)

3

A

T_A

Ambient temperature

–40

85

°C

µH

µF

L

Recommended inductance at V_{VBUS_MAX}< 6.2V

Recommended inductance at V_{VBUS_MAX}> 6.2V

Recommended capacitance at VBUS

Recommended capacitance at PMID

Recommended capacitance at BAT

1.0

2.2

10

L

C_VBUS

C_PMID

C_BAT

10

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UNIT

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8.4 Thermal Information

BQ2530x

RTE

16-PINS

45.8

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance (JEDEC⁽¹⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

)

°C/W

R_θJC(top)

R_θJB

48.5

19.0

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

Ψ_JB

19

R_θJC(bot)

7.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}and V_VBUS> V_BAT+ V_SLEEP, L=2.2µH, TJ = -40°C to +125°C, and TJ = 25°C for typical

values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

QUIESCENT CURRENT

V_BUSreverse current from BAT/SW to V_BAT= V_SW= 4.5V, V_BUSis shorted to

VBUS TJ = -40°C - 85°C GND, measure V_BUSreverse current

I_{VBUS_REVS}

I_{Q_VBUS_DIS}

I_{Q_BAT_HIZ}

0.07

3.5

3

µA

V_BUSleakage current in disable mode V_BUS= 5V, V_BAT= 4V, charger is

4.25 µA

TJ = -40°C - 85°C

disabled, /EN is pulled high

BAT and SW pin leakage current in

HiZ mode TJ = -40°C - 65°C

V_BAT= V_SW= 4.5V, V_BUSfloating

0.17

1

µA

VBUS POWER UP

V_{VBUS_OP}

V_BUSoperating range

4.1

3.0

17.0

3.80

V

V_{VBUS_UVLOZ}

V_BUSpower on reset

V_BUSrising

V_{VBUS_UVLOZ_HYS}

V_{VBUS_LOWV}

V_BUSpower on reset hysteresis

A condition to turnon REGN

V_BUSfalling

250

mV

V

V_BUSrising, REGN turns on, V_BAT= 3.2V

3.8

30

3.90

4.00

A condition to turnon REGN,

hysteresis

V_{VBUS_LOWV_HYS}

V_SLEEP

V_BUSfalling, REGN turns off, V_BAT= 3.2V

300

60

mV

V_BUSfalling, V_BUS- V_BAT, V_{VBUS_LOWV}

V_BAT< V_BATREG

<

Enter sleep mode threshold

Exit sleep mode threshold

100 mV

295 mV

V_BUSrising, V_BUS- V_BAT, V_{VBUS_LOWV}

V_BAT< V_BATREG

<

V_SLEEPZ

110

157

V_{VBUS_OVP_RISE}

V_{VBUS_OVP_HYS}

MOSFETS

V_BUSovervoltage rising threshold

V_BUSovervoltage falling hysteresis

V_BUSrising, converter stops switching

17.00

17.40

750

17.80

V

V_BUSfalling, converter stops switching

mV

Top reverse blocking MOSFET on-

R_{DSON_Q1}

R_{DSON_Q2}

R_{DSON_Q3}

resistance between VBUS and PMID V_REGN= 5V

(Q1)

40

50

45

65 mΩ

82 mΩ

72 mΩ

High-side switching MOSFET on-

resistance between PMID and SW

(Q2)

V_REGN= 5V

Low-side switching MOSFET on-

resistance between SW and GND

(Q3)

BATTERY CHARGER

8

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}and V_VBUS> V_BAT+ V_SLEEP, L=2.2µH, TJ = -40°C to +125°C, and TJ = 25°C for typical

values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VSET pin floating, TJ = -40°C to +85°C

4.08

4.100

4.120

4.371

V

Connect VSET pin to 51kΩ resistor, TJ =

-40°C to +85°C

4.328

4.378

4.350

4.400

V_BATREG

Charge voltage regulation

Connect VSET pin to 10kΩ resistor, TJ =

-40°C to +85°C

4.422

V

VSET pin is grounded, TJ = -40°C to +85°C

ICHG set at 1.72A with R_ICHG= 23.2kΩ

ICHG set at 1.0A with R_ICHG= 40.2kΩ

ICHG set at 0.5A with R_ICHG= 78.7kΩ

4.179

1.55

0.90

0.40

4.200

1.72

1.00

0.50

4.221

1.89

1.10

0.60

V

A

I_CHG

Charge current regulation

ICHG = 1.72A, 10% of ICHG, R_ICHG

23.2kΩ

=

138

70

172

100

63

206 mA

130 mA

93 mA

ICHG = 1.0A, 10% of ICHG, R_ICHG

40.2kΩ

=

I_TERM

Termination current regulation

ICHG = 0.5A, ITERM = 63mA, R_ICHG

78.7kΩ

=

33

ICHG = 1.72A, 10% of ICHG, R_ICHG

23.2kΩ

=

115

50

172

100

225 mA

I_PRECHG

Precharge current

ICHG = 1.0A, 10% of ICHG, R_ICHG

40.2kΩ

=

150 mA

98 mA

ICHG = 0.5A, R_ICHG= 78.7kΩ

Short to precharge

28

2.05

1.85

25

63

2.20

2.00

35

V_{BAT_SHORT_RISE}

V_{BAT_SHORT_FALL}

I_{BAT_SHORT}

V_BATshort rising threshold

V_BATshort falling threshold

Battery short current

Rising threshold

2.35

2.15

V

Precharge to short

V_BAT< V_{BAT_SHORT_FALL,}

Precharge to fast charge

Fast charge to precharge

46 mA

V_{BAT_LOWV_RISE}

V_{BAT_LOWV_FALL}

V_{RECHG_HYS}

2.90

2.60

110

3.00

2.70

160

3.10

2.80

V

Falling threshold

Recharge hysteresis below V_BATREGV_BATfalling

216 mV

INPUT VOLTAGE / CURRENT REGULATION

V_{INDPM_MIN}

V_INDPM

Minimum input voltage regulation

Input voltage regulation

V_BAT= 3.5V, measured at PMID pin

4

4.15

3.00

4.07

4.28

3.35

4.2

4.41

3.70

V

A

V_BAT= 4V, measured at PMID pin, V_INDPM

1.044*VBAT+ 0.125V

=

I_{INDPM_3A}

Input current regulation

V_BUS= 5V

BATTERY OVER-VOLTAGE PROTECTION

V_{BAT_OVP_RISE}Battery overvoltage rising threshold

V_{BAT_OVP_FALL}Battery overvoltage falling threshold

CONVERTER PROTECTION

Bootstrap refresh comparator

V_BATrising, as percentage of V_BATREG

V_BATfalling, as percentage of V_BATREG

101.9

100.0

103.5

101.6

105.0

103.1

%

(V_BTST- V_SW) when LSFET refresh pulse is

requested, V_BUS= 5V

V_{BTST_REFRESH}

2.7

5.2

3

3.3

6.7

V

A

threshold

HSFET cycle by cycle over current

limit threshold

I_{HSFET_OCP}

6.2

STAT INDICATION

I_{STAT_SINK}

STAT pin sink current

6

mA

Hz

%

F_BLINK2

STAT pin blink frequency

STAT pin blink duty cycle

1

F_{BLINK_DUTY}

50

THERMAL REGULATION AND THERMAL SHUTDOWN

Junction temperature regulation

accuracy

T_REG

111

120

150

133 °C

°C

T_SHUT

Thermal Shutdown Rising threshold

Temperature increasing

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}and V_VBUS> V_BAT+ V_SLEEP, L=2.2µH, TJ = -40°C to +125°C, and TJ = 25°C for typical

values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Thermal Shutdown Falling threshold Temperature decreasing

BUCK MODE OPERATION

MIN

TYP

MAX UNIT

125

°C

F_SW

PWM switching frequency

SW node frequency

1.02

1.20

97.0

1.38 MHz

%

D_MAX

Maximum PWM Duty Cycle

REGN LDO

V_{REGN_UVLO}

V_REGN

REGN UVLO

V_VBUSrising

3.85

5.0

V

REGN LDO output voltage

V_VBUS= 5V, I_REGN= 0 to 16mA

V_VBUS= 12V, I_REGN= 16mA

4.20

4.50

V_REGN

5.40

ICHG SETTING

V_ICHG

ICHG pin regulated voltage

993

998

1003 mV

kΩ

R_{ICHG_SHORT_FALL}Resistance to disable charge

1.00

R_{ICHG_OPEN_RISE}

R_ICHG

Resistance to disable charge

565 kΩ

250 kΩ

Programmable resistance at ICHG

V_BUS= 5V, resistance decrease

R_ICHG> R_{ICHG_HIGH}

11.70

60.0

ICHG setting resistor threshold to

clamp precharge and termination

current to 63mA

R_{ICHG_HIGH}

65.0

73.5

70.0 kΩ

JEITA THERMISTOR COMPARATORS

T1 (0°C) threshold, charge

V_TSrising, charger suspends charge. As

Percentage to V_REGN

V_T1%

suspended if thermistor temperature

is below T1

72.68

74.35

%

V_T1

V_T2

%

V_TSfalling

As Percentage to V_REGN

70.68

67.7

66.5

71.5

68.5

67.3

72.33

69.5

68.2

%

T2 (10°C) threshold, charge current is

reduced to 20% of ICHG

V_TSrising. As Percentage to V_REGN

As Percentage to V_REGN

V_TSfalling

T3 (45°C) threshold, charge at 50% of

ICHG and VREG = 4.1V above this

temperature

V_T3%

V_TSfalling. As Percentage to V_REGN

46.35

47.25

48.15

%

V_T3

V_T5

%

V_TSRising

As Percentage to V_REGN

47.35

36.95

37.95

48.25

37.75

38.75

49.15

38.55

39.55

%

T5 (60°C) threshold, charge

suspended above this temperature.

V_TSfalling. As Percentage to V_REGN

As Percentage to V_REGN

V_TSRising

COLD/HOT THERMISTOR COMPARATOR

LOGIC I/O PIN CHARACTERESTICS (POL, EN)

V_ILO

V_IH

Input low threshold

Input high threshold

Falling

Rising

0.40

V

1.3

I_BIAS

High-level leakage current at EN pin EN pin is pulled up to 1.8 V

1.0

µA

8.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VBUS/BAT POWER UP

Delay from enable at /EN pin to

charger power on

t_{CHG_ON_EN}

/EN pin voltage rising

245

275

ms

t_{CHG_ON_VBUS}Delay from VBUS to charge start

BATTERY CHARGER

/EN pin is grounded, batttery present

Fast charge safety timer 20 hours

t_{SAFETY_FAST}Charge safety timer

15.0

20.0

24.0

hr

10

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8.6 Timing Requirements (continued)

PARAMETER

TEST CONDITIONS

Precharge safety timer

MIN

NOM

MAX

UNIT

t_{SAFETY_PRE}

Charge safety timer

1.5

2.0

2.5

hr

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8.7 Typical Characteristics

f_SW= 1.2 MHz

Inductance = 1.0 uH

Inductor DCR = 10 mΩ

f_SW= 1.2 MHz

V_BAT= 3.8 V

Inductance = 2.2 uH

V_VBUS= 5.0 V, V_BAT= 3.8 V

Inductor DCR = 20 mΩ

Figure 8-1. 1-Cell Battery Charge Efficiency vs. Charge Current Figure 8-2. 1-Cell Battery Charge Efficiency vs. Charge Current

4.5

4.4

4.3

4.2

4.1

4

4.4

4.3

4.2

4.1

4

VBATREG = 4.1V

VBATREG = 4.2V

VBATREG = 4.35V

VBATREG = 4.4V

VINDPM = 4.1V

VINDPM = 4.3V

3.9

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Junction Temperature (^oC)

Copy

VIND

Figure 8-4. VINDPM vs. Junction Temperature

Figure 8-3. Battery Charge Regulation Voltage vs. Junction

Temperature

Figure 8-5. KICHG vs. Charge Current

Figure 8-6. Charge Current vs. Charge Current Setting

Resistance RICHG

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9 Detailed Description

9.1 Overview

The BQ25303J is a highly integrated standalone switch-mode battery charger for single cell Li-Ion and Li-

polymer batteries with charge voltage and charge current programmable by an external resistor. It includes an

input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET,

Q3), and bootstrap diode for the high-side gate drive as well as current sensing circuitry.

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9.2 Functional Block Diagram

VBUS

PMID

V_{VBUS_LOWV}

RBFET (Q1)

+

UVLO

V_VBUS

V_BAT+ V_SLEEP

œ

I_IN

Q1 Gate

Control

REGN

EN_REGN

+

SLEEP

REGN

LDO

V_VBUS

œ

EN_CHARGE

BTST

FBO

I_CHG

SNS

V_VBUS

VBUS_OV

+

V_{VBUS_OV}

œ

V_PMID

œ

HSFET (Q2)

V_INDPM

SW

+

BAT

I_IN

+

I_INDPM

Converter

Control

+

BATOVP

UCP

REGN

104% × V _{BAT_REG}

œ

I_{LSFET_UCP}

LSFET (Q3)

IC T_J

PGND

+

T_REG

I_Q2

I_Q3

BAT

œ

Q2_OCP

œ

+

I_{HSFET_OCP}

V_{BAT_REG}

œ

V_BTST- V_SW

I_CHG

+

REFRESH

EN_CHARGE

V_{BTST_REFRESH}

I_{CHG_REG}

œ

BAT

Converter

Control State

Machine

IC T_J

+

TSHUT

T_SHUT

œ

ICHG

VSET

EN

V_REG-V_RECHG

+

RECHRG

BAT

I_CHG

œ

+

TERMINATION

BATLOWV

I_TERM

œ

REF/EN

V_{BAT_LOWV}

+

BAT

œ

V_SHORT

Charger

Control State

Machine

+

BATSHORT

SUSPEND

BAT

œ

POL

œ

V_TCOLD

STAT

+

V_TS

œ

V_THOT

SUSPEND

V_TS

TS

+

V_TS

AGND

14

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9.3 Feature Description

9.3.1 Device Power Up

The EN pin enable or disable the device. When the device is disabled, the device draws minimum current from

VBUS pin. The device can be powered up from either VBUS or by enabling the device from EN pin.

9.3.1.1 Power-On-Reset (POR)

The EN pin can enable or disable the device. When the device is disabled, the device is in disable mode and it

draws minimum current at VBUS. When the device is enabled, if VBUS rises above V_{VBUS_UVLOZ}, the device

powers part of internal bias and comparators and starts Power on Reset (POR).

9.3.1.2 REGN Regulator Power Up

The internal bias circuits are powered from the input source. The REGN supplies internal bias circuits as well as

the HSFET and LSFET gate drive. The REGN also provides voltage rail to STAT LED indication. The REGN is

enabled when all the below conditions are valid:

•

Chip is enabled by EN pin

V_VBUSabove V_{VBUS_UVLOZ}

•

V_VBUSabove V_BAT+ V_SLEEPZ

After sleep comparator deglitch time, VSET detection time, and REGN delay time

REGN remains on at fault conditions. REGN is powered by VBUS only and REGN is off when VBUS power is

removed.

9.3.1.3 Charger Power Up

Following REGN power-up, if there is no fault conditions, the charger powers up with soft start. If there is any

fault, the charger will remain off until fault is clear. Any of the fault conditions below gates charger power-up:

•

V_VBUS> V_{VBUS_OVP}

Thermistor cold/hot fault on TS pin

V_BAT> V_{BAT_OVP}

Safety timer fault

ICHG pin is open or short to GND

Die temperature is above TSHUT

9.3.1.4 Charger Enable and Disable by EN Pin

With POL pin floating, the charger can be enabled with EN pin pulled low (or floating) or disabled by EN pin

pulled high. The charger is in disable mode when disabled.

9.3.1.5 Device Unplugged from Input Source

When V_BUSis removed from an adaptor, the device stays in HiZ mode and the leakage current from the battery

to BAT pin and SW pin is less than I_{Q_BAT_HIZ.}

9.3.2 Battery Charging Management

The BQ25303J charges 1-cell Li-Ion battery with up to 3.0-A charge current from 4.1-V to 17-V input with JEITA

battery temperature monitoring.A new charge cycle starts when the charger power-up conditions are met. The

charge voltage is set by external resistor connected at VSET pin and charge current are set by external resistors

at ICHG pin. The charger terminates the charging cycle when the charging current is below termination threshold

I_TERMand charge voltage is above recharge threshold(V_BATREG- V_{RECHG_HYS}), and device is not in IINDPM or

thermal regulation. When a fully charged battery's voltage is discharged below recharge threshold, the device

automatically starts a new charging cycle with safety timer reset. To initiate a recharge cycle, the conditions of

charger power-up must be met. The STAT pin output indicates the charging status of charging (LOW), charging

complete or charge disabled (HIGH) or charging faults (BLINKING).

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9.3.2.1 Battery Charging Profile

The device charges the battery in four phases: battery short, preconditioning, constant current, constant voltage.

The device charges battery based on charge voltage set by VSET pin and charge current set by ICHG pin as

well as actual battery voltage. The battery charging profile is shown in Figure 9-1. The battery short current is

provided by internal linear regulator.

Table 9-1. Charging Current Setting

MODE

BATTERY VOLTAGE V_BAT

CHARGE CURRENT

TYPICAL VALUE

Battery Short

V_BAT< V_{BAT_SHORT}

I_{BAT_SHORT}

35 mA

10% of I_CHG( I_PRE

63mA )

>

Precharge

V_{BAT_SHORT}< V_BAT< V_{BAT_LOWV}

V_{BAT_LOWV}< V_BAT

I_PRECHG

I_CHG

Fast Charge

Set by ICHG resistor

Regulation Voltage VBATREG

Fast Charge Current ICHG

Battery Voltage

Charge Current

V_{BAT_LOWV}

V_{BAT_SHORT}

I_PRECHG

I_TERM

I_{BAT_SHORT}

Time

Trickle Charge

Pre-charge

Fast Charge

Voltage Regulation

Safety Timer Expiration if

Charge is not Terminated

Figure 9-1. Battery Charging Profile

9.3.2.2 Precharge

The device charges the battery at 10% of set fast charge current in precharge mode. When R_ICHG> R_{ICHG_HIGH}

,

the precharge current is clamped at 63mA.

9.3.2.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold and the charge

current is below termination current. After a charging cycle is completed, the converter stops swicthing, charge is

terminated and the system load is powered from battery. Termination is temporarily disabled when the charger

device is in input current regulation or thermal regulation mode and the charging safety timer is counted at half

the clock rate. The charge termination current is 10% of set fast charge current if R_ICHG< R_{ICHG_HIGH}. The

termination current is clamped at 63mA if R_ICHG> R_{ICHG_HIGH}

.

9.3.2.4 Battery Recharge

A charge cycle is completed when battery is fully charged with charge terminated. If the battery voltage

decreases below the recharge threshold (V_BATREG- V_{RECHG_HYS}), the charger is enabled with safety timer reset

and enabled.

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9.3.2.5 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The

safety timer is 20 hours when the battery voltage is above V_{BAT_LOWV}threshold and 2 hours below V_{BAT_LOWV}

threshold. When the safety timer expires, charge is suspended until the safety timer is reset. Safety timer is reset

and charge starts under one of the following conditions:

•

Battery voltage falls below recharge threshold

VBUS voltage is recycled

EN pin is toggled

Battery voltage transits across V_{BAT_SHORT}threshold

Battery voltage transits across V_{BAT_LOWV}threshold

If the safety timer expires and the battery voltage is above recharge threshold, the charger is suspended and the

STAT pin is open. If the safety timer expires and the battery voltage is below the recharge threshold, the charger

is suspended and the STAT pin blinks to indicate a fault. The safety timer fault is cleared with safety timer reset.

During input current regulation, thermal regulation, JEITA COOL and JEITA WARM, the safety timer counts at

half the original clock frequency and the safety timer is doubled. During TS fault, V_{BUS_OVP}, V_{BAT_OVP}, ICHG pin

open and short, and IC thermal shutdown faults, the safety timer is suspended. Once the fault(s) is clear, the

safety timer resumes to count.

9.3.2.6 Thermistor Temperature Monitoring

The charger device provides a single thermistor input TS pin for battery temperature monitor. To improve the

safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline emphasized

the importance of avoiding a high charge current and high charge voltage at certain low and high temperature

ranges. To initiate a charge cycle, the voltage on TS pin must be within the V_T1% to V_T5% thresholds. If TS

voltage is out of T1-T5 temperature range, the charger stops charging and waits until the battery temperature is

within the T1 to T5 range. .

At cool temperature (T1-T2), the charge current is reduced to 20% of the set fast charge if R_ICHG< R_{ICHG_HIGH}. If

R_ICHG> R_{ICHG_HIGH}, the charge current is reduced to 50% of fast charge current in cool charge. At normal

temperature (T2 - T3), the charger charges battery as fast charge and the fast charge current is set by a resister

at ICHG pin. At warm temperature (T3 -T5), the charge voltage is reduced to 4.1 V and 50% of fast charge

current. If the charge voltage is set below 4.1V, the charge voltage will remain unchanged during warm charge.

RT1 and RT2 programs temperatures from T1 to T5. In the equations, R_NTC,T1is NTC thermistor resistance

value at temperature T1 and R_NTC,T5is NTC thermistor resistance values at temperature T5. Select 0°C to 60°C

for battery charge temperature range, then NTC thermistor 103AT-2 thermistor resistance is R_NTC,T1= 27.28 kΩ

( at 0°C) and R_NTC,T5= 3.02 kΩ (at 60°C), from the Equation 1 and Equation 2, RT1 and RT2 are derived as:

• RT1 = 4.32 kΩ

• RT1 = 21 kΩ

REGN

RT1

TS

RTH

103AT

RT2

Figure 9-2. Battery Temperature Sensing Circuit

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%

(1)

%

(2)

(3)

(4)

4.1V

50% of ICHG

20% of ICHG

T1

T5

45 50 55 60

T3

T2

10 15 20

5

25 40

30 35

0

Battery Thermistor Temperature (°C)

Figure 9-3. JEITA Profile

9.3.3 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive a LED that is pulled up

to REGN rail through a current limit resistor.

Table 9-2. STAT Pin State

CHARGING STATE

STAT INDICATOR

LOW

Charging in progress (including recharge)

Charging complete

HIGH

HiZ mode, sleep mode, charge disable

HIGH

Safety timer expiration with battery voltage above recharge threshold

HIGH

Charge faults:

1. VBUS input over voltage

2. TS cold/hot faults

BLINKING at 1 Hz

with 50% duty cycle

3. Battery over voltage

4. IC thermal shutdown

5. Safety timer expiration with battery voltage below recharge threshold

6. ICHG pin open or short

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9.3.4 Protections

9.3.4.1 Voltage and Current Monitoring

The device closely monitors the input voltage and input current for safe operation.

9.3.4.1.1 Input Over-Voltage Protection

This device integrates the functionality of an input over-voltage protection (OVP). The input OVP threshold is

V_{VBUS_OVP_RISE}. During an input over-voltage event, the converter stops switching and safety timer stops

counting as well. The converter resumes switching and the safety timer resumes counting once the VBUS

voltage drops back below (V_{VBUS_OVP_RISE}- V_{VBUS_OVP_HYS}). The REGN LDO remains on during an input over-

voltage event. The STAT pin blinks during an input OVP event.

9.3.4.1.2 Input Voltage Dynamic Power Management (VINDPM)

When the input current of the device exceeds the current capability of the power supply, the charger device

regulates PMID voltage by reducing charge current to avoid crashing the input power supply. VINDPM

dynamically tracks the battery voltage. The actual VINDPM is the higher of V_{INDPM_MIN}and (1.044*VBAT +

125mV).

9.3.4.1.3 Input Current Limit

The device has built-in input current limit. When the input current is over the threshold I_INDPM, the converter duty

cycle is reduced to reduce input current.

9.3.4.1.4 Cycle-by-Cycle Current Limit

High-side (HS) FET current is cycle-by-cycle limited. Once the HSFET peak current hits the limit I_{HSFET_OCP}, the

HSFET shuts down until the current is reduced below a threshold.

9.3.4.2 Thermal Regulation and Thermal Shutdown

The device monitors the junction temperature T_Jto avoid overheating the chip and limit the device surface

temperature. When the internal junction temperature exceeds thermal regulation limit T_REG, the device lowers

down the charge current. During thermal regulation, the average charging current is usually below the

programmed battery charging current. Therefore, termination is disabled and the safety timer runs at half the

clock rate.

Additionally, the device has thermal shutdown built in to turn off the charger when device junction temperature

exceeds T_SHUTrising threshold. The charger is reenabled when the junction temperature is below T_SHUTfalling

threshold. During thermal shutdown, the safety timer stops counting and it resumes when the temperature drops

below the threshold.

9.3.4.3 Battery Protection

9.3.4.3.1 Battery Over-Voltage Protection (V_{BAT_OVP}

)

The battery voltage is clamped at above the battery regulation voltage. When the battery voltage is over

V_{BAT_OVP_RISE}, the converter stops switching until the battery voltage is below the falling threshold. During a

battery over-voltage event, the safety timer stops counting and STAT pin reports the fault and it resumes once

the battery voltage falls below the falling threshold. A 7-mA pull-down current is on the BAT pin once BAT_OVP

is triggered. BAT_OVP may be triggered in charging mode, termination mode, and fault mode.

9.3.4.3.2 Battery Short Circuit Protection

When the battery voltage falls below the V_{BAT_SHORT}threshold, the charge current is reduced to I_{BAT_SHORT}

.

9.3.4.4 ICHG Pin Open and Short Protection

To protect against ICHG pin is short or open, the charger immediately shuts off once ICHG pin is open or short to

GND and STAT pin blinks to report the fault. At powerup, if ICHG pin is detected open or short to GND, the

charge will not power up until the fault is clear.

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9.4 Device Functional Modes

9.4.1 Disable Mode, HiZ Mode, Sleep Mode, Charge Mode, Termination Mode, and Fault Mode

The device operates in different modes depending on VBUS voltage, battery voltage, and EN pin, POL pin, and

ICHG pin connection. The functional modes are listed in the following table.

Table 9-3. Device Functional Modes

MODE

CONDITIONS

REGN LDO

CHARGE ENABLED

STAT PIN

OPEN

Device is disabled, POL floating or

pulled high, and EN pulled high

OFF

NO

Disable Mode

Device is disabled, POL pulled low,

EN pulled low or floating

OFF

OPEN

Device is enabled and

V_VBUS< V_{VBUS_UVLOZ}

HiZ Mode

OFF

NO

OPEN

Device is enabled and

V_VBUS> V_{VBUS_UVLOZ}and

V_VBUS< V_BAT+ V_SLEEPZ

Sleep Mode

Device is enabled, V_VBUS

>

V_{VBUS_LOWV}and V_VBUS> V_BAT

V_SLEEPZ, no faults, charge is not

terminated

+

Charge Mode

ON

YES

SHORT to GND

V_VBUS> V_{VBUS_LOWV}and V_VBUS

V_BAT+ V_SLEEPZand device is enabled,

no faults, charge is terminated

>

Charge Termination

Mode

ON

NO

OPEN

V_{BUS_OVP}, TS cold/hot, V_{BAT_OVP}, IC

thermal shutdown, safety timer fault,

ICHG pin open or short

Fault Mode

BLINKING

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

A typical application consists of a single cell battery charger for Li-Ion, Li-polymer batteries used in a wide range

of portable devices and accessories. It integrates an input reverse-block FET (RBFET, Q1), high-side switching

FET (HSFET, Q2), and low-side switching FET (LSFET, Q3). The Buck converter output is connected to the

battery directly to charge the battery and power system loads. The device also integrates a bootstrap diode for

high-side gate drive.

10.2 Typical Applications

The typical applications in this section include a standalone charger without power path, and a standalone

charger with external power path.

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10.2.1 Typical Application

The typical application in this section includes a standalone charger without power path.

1.0 …H (V_{VBUS_MAX}< 6.2V)

2.2 …H (V_{VBUS_MAX}> 6.2V)

VBUS

SW

VBUS

Q1

Q2

10 …F

2.2 …F

47 nF

BTST

GND

Q3

PMID

10 …F

REGN

1 kꢀ

BAT

STAT

REGN

2.2 …F

TS

ICHG

VSET

POL

EN

Thermal Pad

Figure 10-1. Typical Application Diagram

10.2.1.1 Design Requirements

Table 10-1. Design Requirements

PARAMETER

Input Voltage

VALUE

4.1V to 17V

3.0A

Input Current

Fast Charge Current

Battery Regulation Voltage

3.0A

4.1V/4.2V/4.35V/4.4V

22

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10.2.1.2 Detailed Design Procedure

10.2.1.3 Application Curves

SW

VBUS

V_BAT

REGN

STAT

IBAT

STAT

IBAT

VBUS = 5 V

ICHG = 2 A

VBAT = 1.5V - 4.2V

ICHG = 2A

Device Enabled

VBATREG = 4.2V

Figure 10-2. Power Up from VBUS

Figure 10-3. Charge Cycle

VBUS = 12V -25V -12V

ICHG = 1A

VBAT = 3.8V

VBUS = 5 V

ICHG = 2A

Adaptor Currrent Limit: 1A

VBAT = 3.5V

Figure 10-4. VBUS Over Voltage Protection

Figure 10-5. VBUS startup into VINDPM

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VBUS = 5 V

From ICHG = 2A to ICHG pin short

Figure 10-6. ICHG Pin Short Circuit Protection

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10.2.2 Typical Application with External Power Path

In the case where a system needs to be immediately powered up from VBUS when the battery is overdischarged

or dead, the application circuit shown in Figure 10-7 can be used to provide a power path from VBUS/PMID to

VSYS. PFET Q4 is an external PFET that turns on to supply VSYS from the battery when VBUS is removed;

PFET Q4 turns off when VBUS is plugged in and VSYS is supplied from VBUS/PMID.

VSYS

10 µF

VBUS

PMID

R

Q4

L

VBUS

SW

VBUS

Q1

Q2

10 …F

2.2 …F

47 nF

BTST

GND

REGN

Q3

2.2 …F

REGN

STAT

ICHG

BAT

1 kꢀ

REGN

TS

Thermal Pad

Figure 10-7. Typical Application Diagram with Power Path

10.2.2.1 Design Requirements

For design requirements, see Section 10.2.1.1.

10.2.2.2 Detailed Design Procedure

For detailed design procedure, see Section 10.2.1.2.

10.2.2.3 Application Curves

For application curves, see Section 10.2.1.3.

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11 Power Supply Recommendations

In order to provide an output voltage on the BAT pin, the device requires a power supply between 4.1 V and 17 V

Li-Ion battery with positive terminal connected to BAT. The source current rating needs to be at least 3 A in order

for the buck converter to provide maximum output power to BAT or the system connected to BAT pin.

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12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Figure 12-1) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the

proper layout.

•

Place input capacitor as close as possible to PMID pin and use shortest thick copper trace to connect input

capacitor to PMID pin and GND plane.

•

It is critical that the exposed thermal pad on the backside of the device be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other

layers. Connect the GND pins to thermal pad on the top layer.

•

Put output capacitor near to the inductor output terminal and the charger device. Ground connections need to

be tied to the IC ground with a short copper trace or GND plane

Place inductor input terminal to SW pin as close as possible and limit SW node copper area to lower

electrical and magnetic field radiation. Do not use multiple layers in parallel for this connection. Minimize

parasitic capacitance from this area to any other trace or plane.

•

Route analog ground separately from power ground if possible. Connect analog ground and power ground

together using thermal pad as the single ground connection point under the charger device. It is acceptable to

connect all grounds to a single ground plane if multiple ground planes are not available.

•

Decoupling capacitors should be placed next to the device pins and make trace connection as short as

possible.

For high input voltage and high charge current applications, sufficient copper area on GND should be

budgeted to dissipate heat from power losses.

Ensure that the number and sizes of vias allow enough copper for a given current path

+

œ

Figure 12-1. High Frequency Current Path

12.2 Layout Example

The device pinout and component count are optimized for a 2 layer PCB design. The 2-layer PCB layout

example is shown in Figure 12-2.

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Top layer

GND

Bottom layer

1 µH

Vias

BAT

47 nF

10 µF

2.2 µF

VBUS

2.2 µF

10 µF

VBUS

GND

1

2

3

4

12

11

10

9

REGN

STAT

ICHG

GND

BAT

VSET

5

6

7

8

Figure 12-2. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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Product Folder Links: BQ25303J

BQ25303J

SLUSDT8 – FEBRUARY 2021

www.ti.com

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30

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Product Folder Links: BQ25303J

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25303J
厂家：	TEXAS INSTRUMENTS
描述：	BQ25303J Standalone 1-Cell, 17-V, 3.0-A Battery Charger with JEITA Battery Temperature Monitoring 电池监控
文件：	总32页 (文件大小：1669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25303J [TI]

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