BQ25600D_技术文档

BQ25600, BQ25600D

ZHCSGO5B –JUNE 2017 –REVISED MARCH 2022

BQ25600 and BQ25600D 用于高输入电压和NVDC 电源路径管理的I²C 控制型

单节电池3.0A 降压电池充电器

• 17µA 低电池泄漏电流

• 高精度

1 特性

• 高效1.5 MHz 同步开关模式降压充电器

– 充电电压调节范围为±0.5%

– 1.38A 充电电流调节范围为±6%

– 0.9A 输入电流调节范围为±10%

– 用于快速充电的远程电池感应

– 在2A 电流（5V 输入）下具有92% 的充电效率

– 针对USB 电压输入(5V) 进行了优化

– 用于轻负载运行的可选低功耗脉冲频率调制

(PFM) 模式

2 应用

• 支持USB On-The-Go (OTG)

• 智能手机

• 手机附件

• 医疗设备

– 具有高达1.2A 输出的升压转换器

– 在1A 输出下具有92% 的升压效率

– 精确的恒定电流(CC) 限制

– 高达500µF 容性负载的软启动

– 输出短路保护

– 低功耗PFM 模式，适合轻载运行

• 单个输入，支持USB 输入和高电压适配器

3 说明

BQ25600 and BQ25600D 是高度集成的 3.0A 开关模

式电池充电管理和系统电源路径管理器件，适用于单节

锂离子和锂聚合物电池。其低阻抗电源路径对开关模式

运行效率进行了优化、缩短了电池充电时间并延长了放

电阶段的电池使用寿命。具有充电和系统设置的 I²C 串

行接口使得此器件成为一种真正灵活的解决方案。

– 支持3.9V 至13.5V 输入电压范围，绝对最大输

入电压额定值为22V

– 可编程输入电流限制（100 mA 至3.2A，分辨率

为100 mA），支持USB 2.0、USB 3.0 标准和

高压适配器(IINDPM)

– 通过高达5.4V 的输入电压限制(VINDPM) 进行

最大功率跟踪

– VINDPM 阈值自动跟踪电池电压

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

BQ25600

BQ25600D

WCSP (30)

2.00mm × 2.40mm

– 自动检测USB SDP、DCP 以及非标准适配器

• 高电池放电效率，电池放电MOSFET 为19.5 mΩ

• 窄VDC (NVDC) 电源路径管理

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 无需电池或深度放电的电池即可瞬时启动

– 电池充电模式下实现理想二极管运行

• BATFET 控制，支持运输模式、唤醒和完全系统复

位

• 灵活的自主和I²C 模式，可实现最优系统性能

• 高集成度，包括所有MOSFET、电流感测和环路补

偿

USB

Host

VBUS

SW

I²C Bus

BTST

SYS

BAT

Host Control

I_CHG

REGN

+

QON

Optional

TS

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCJ4

BQ25600, BQ25600D

ZHCSGO5B –JUNE 2017 –REVISED MARCH 2022

www.ti.com.cn

Table of Contents

8.5 Programming............................................................ 33

8.6 Register Maps...........................................................36

9 Application and Implementation..................................47

9.1 Application Information............................................. 47

9.2 Typical Application.................................................... 48

10 Power Supply Recommendations..............................55

11 Layout...........................................................................56

11.1 Layout Guidelines................................................... 56

11.2 Layout Example...................................................... 56

12 Device and Documentation Support..........................57

12.1 Device Support....................................................... 57

12.2 接收文档更新通知................................................... 57

12.3 支持资源..................................................................57

12.4 Trademarks.............................................................57

12.5 Electrostatic Discharge Caution..............................57

12.6 术语表..................................................................... 57

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................4

6 Pin Configuration and Functions...................................5

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................8

7.4 Thermal Information....................................................9

7.5 Electrical Characteristics.............................................9

7.6 Timing Requirements................................................14

7.7 Typical Characteristics..............................................16

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................29

Information.................................................................... 58

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (August 2017) to Revision B (March 2022)

Page

• 删除了整个数据表中的WEBENCH.................................................................................................................... 1

• Deleted V_REGNMAX values in Electrical Characteristics table...........................................................................9

• Added last sentence to 节8.3.3.5 ....................................................................................................................22

• Changed 图8-3 ............................................................................................................................................... 25

• Changed 图8-4 ............................................................................................................................................... 25

• Added 图8-5 ....................................................................................................................................................25

• Changed 图8-6 ............................................................................................................................................... 26

• Added 节8.4 ....................................................................................................................................................29

• Changed 图8-7 ............................................................................................................................................... 29

• Changed description of exiting shipping mode from QON pin .........................................................................31

• Added 节8.5 ....................................................................................................................................................33

• Changed BQ25600 010 to 011 in Description in 表8-15 .................................................................................44

• Deleted PG pin in 图9-2 ..................................................................................................................................48

• Added 表9-1 ....................................................................................................................................................49

Changes from Revision * (June 2017) to Revision A (August 2017)

Page

• 更改了数据表标题...............................................................................................................................................1

• 从节1 中删除了“200 nS 快速关闭”................................................................................................................ 1

• 更改了简化版应用原理图.................................................................................................................................... 1

• Deleted ACDRV pin references from Pin Functions table.................................................................................. 5

• Changed VAC pin description in Pin Functions table......................................................................................... 5

• Changed ACDRV pin references to "NC" in 节6 section................................................................................... 5

• Deleted ACDRV pin references from 节7.1 table...............................................................................................8

• Added Input supply current specification (I_{VACVBUS_HIZ}) in Electrical Characteristics table................................ 9

• Changed 节8.2 ................................................................................................................................................19

• Changed Power Up from Input Source section................................................................................................ 20

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• Deleted Power Up OVPFET section.................................................................................................................20

• Deleted OVPFET Startup Control timing illustration ........................................................................................20

• Added subsection explaining D+/D–detection ...............................................................................................21

• Changed Input Overvoltage (ACOV) section....................................................................................................27

• Changed Power Path Management Application schematic..............................................................................48

• Changed BQ25600D Applications Diagram schematic ................................................................................... 48

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5 说明（续）

BQ25600 and BQ25600D 支持高输入电压和快速充电功能，适用于各类智能手机、平板电脑和便携式设备。其输

入电压和电流调节以及电池远程感应可以为电池提供最大的充电功率。它还集成了一个自举二极管以进行高侧栅

极驱动，从而简化了系统设计。具有充电和系统设置的I²C 串行接口使得此器件成为一个真正灵活的解决方案。

该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口以及兼容USB 的高电压适配器。该器件根据内

置 USB 接口设置默认输入电流限值。为了设置默认输入电流限值，该器件使用内置 USB 接口或者从系统检测电

路（如 USB PHY 器件）中获取结果。该器件符合 USB 2.0 和 USB 3.0 电源规范，具有输入电流和电压调节功

能。该器件还具有高达 1.2 A 的恒定电流限制能力，能够为 VBUS 提供 5.15V 的电压，符合 USB On-the-Go

(OTG) 运行功率额定值规格。

电源路径管理将系统电压调节至稍高于电池电压的水平，但是不会下降至 3.5V 最小系统电压（可编程）以下。借

助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流限值或电压限

值时，电源路径管理技术自动将充电电流减至0。随着系统负载持续增加，电源路径将使电池放电，直到满足系统

电源需求。这种补充模式可防止输入源过载。

此器件无需软件控制即可启动并完成一个充电周期。它可感测电池电压并分三个阶段为电池充电：预充电、恒定

电流和恒定电压。在充电周期结束时，当充电电流低于预设限值并且电池电压高于再充电阈值时，充电器自动终

止。如果充满电的电池降至再充电阈值以下，则充电器自动开启另一个充电周期。

此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性计

时器和过压/过流保护。当结温超过 110°C（可编程）时，热调节会使充电电流减小。STAT 输出报告充电状态和

任何故障状况。其他安全特性包括针对充电和升压模式的电池温度感应、热调节和热关断以及输入 UVLO 和过压

保护。VBUS_GD 位指示电源是否正常。当故障发生时，INT 输出会立即通知主机。

该器件还提供用于BATFET 使能和复位控制的QON 引脚，用以退出低功耗运输模式或完全系统复位功能。

该器件系列采用30 焊球2.0mm × 2.4mm WCSP 封装。

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6 Pin Configuration and Functions

1

2

3

4

5

A

B

C

D

E

F

GND

BAT

SW

PMID

VBUS

VAC

SW

SYS

PMID

BTST

TS

VBUS

REGN

QON

SDA

NC

PSEL

PG

CE

STAT

SCL

BAT

SNS

INT

图6-1. BQ25600 YFF Package 30-Pin WCSP Top View

1

2

3

4

5

A

B

C

D

E

F

GND

SW

PMID

VBUS

VAC

GND

BAT

SW

SYS

PMID

BTST

TS

VBUS

REGN

QON

SDA

NC

D+

D-

CE

STAT

SCL

BAT

SNS

INT

图6-2. BQ25600D YFF Package 30-Pin WCSP Top View

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表6-1. Pin Functions

BQ25600

WCSP

C1

BQ25600D

TYPE⁽¹⁾

DESCRIPTION

NAME

WCSP

C1

Battery connection point to the positive terminal of the battery pack. The internal

current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely

to the BAT pin.

D1

BAT

P

E1

F1

Battery voltage sensing pin for charge current regulation. in order to minimize the

parasitic trace resistance during charging, BATSNS pin is connected to the actual

battery pack as close as possible.

BATSNS

F3

AIO

PWM high side driver positive supply. internally, the BTST is connected to the cathode

of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.

BTST

CE

C3

E3

C3

E3

P

DI

Charge enable pin. When this pin is driven low, battery charging is enabled.

Positive line of the USB data line pair. D+/D–based USB host/charging port detection.

The detection includes data contact detection (DCD), primary and secondary detection

in BC1.2.

D+

C5

D5

AIO

—

Negative line of the USB data line pair. D+/D–based USB host/charging port

detection. The detection includes data contact detection (DCD), primary and secondary

detection in BC1.2.

AIO

P

D–

A1

B1

A1

B1

GND

Ground

Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩresistor.

The INT pin sends active low, 256-µs pulse to host to report charger device status and

fault.

INT

NC

PG

F4

B5

D5

F4

B5

—

DO

No connection. This pin must be floating.

Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ

resistor. LOW indicates a good input source if the input voltage is between UVLO and

ACOV, above SLEEP mode threshold, and current limit is above 30 mA.

DO

DI

A3

B3

A3

B3

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of

HSFET. Given the total input capacitance, put 1 μF on VBUS to GND, and the rest

capacitance on PMID to GND.

PMID

PSEL

Power source selection input. High indicates 500 mA input current limit. Low indicates

2.4A input current limit. Once the device gets into host mode, the host can program

different input current limit to IINDPM register.

C5

D4

C4

—

BATFET enable/reset control input. When BATFET is in ship mode, a logic low of

t_SHIPMODEduration turns on BATFET to exit shipping mode. When VBUS is not

plugged–in, a logic low of t_{QON_RST}(minimum 8 s) duration resets SYS (system

power) by turning BATFET off for t_{BATFET_RST}(minimum 250 ms) and then re-enable

BATFET to provide full system power reset. The pin contains an internal pull-up to

maintain default high logic.

QON

D4

DI

P

PWM low side driver positive supply output. internally, REGN is connected to the

anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from

REGN to analog GND. The capacitor should be placed close to the IC.

REGN

C4

I²C interface clock. Connect SCL to the logic rail through a 10-kΩresistor.

I²C interface data. Connect SDA to the logic rail through a 10-kΩresistor.

SCL

SDA

F5

E4

F5

E4

DI

DIO

Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The

STAT pin indicates charger status.

STAT

SW

E5

DO

P

Charge in progress: LOW

Charge complete or charger in SLEEP mode: HIGH

Charge suspend (fault response): Blink at 1Hz

A2

B2

A2

B2

Switching node connecting to output inductor. Internally SW is connected to the source

of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF

bootstrap capacitor from SW to BTST.

C2

D2

E2

F2

C2

D2

E2

F2

Converter output connection point. The internal current sensing resistor is connected

between SYS and BAT. Connect a 20 µF closely to the SYS pin.

SYS

P

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表6-1. Pin Functions (continued)

BQ25600

BQ25600D

WCSP

TYPE⁽¹⁾

DESCRIPTION

NAME

WCSP

Ground reference for the device that is also the thermal pad used to conduct heat from

the device. This connection serves two purposes. The first purpose is to provide an

electrical ground connection for the device. The second purpose is to provide a low

thermal-impedance path from the device die to the PCB. This pad should be tied

externally to a ground plane.

Thermal Pad

P

—

Temperature qualification voltage input to support JEITA profile. Connect a negative

temperature coefficient thermistor. Program temperature window with a resistor divider

from REGN to TS to GND. Charge suspends when TS pin voltage is out of range.

When TS pin is not used, connect a 10-kΩresistor from REGN to TS and a 10-kΩ

resistor from TS to GND. It is recommended to use a 103AT-2 thermistor.

TS

D3

AI

VAC

A5

A4

A5

A4

AI

P

Input voltage sensing. This pin must be tied to VBUS.

Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is

connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic

capacitor from VBUS to GND and place it as close as possible to IC.

VBUS

B4

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,

P = Power

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Voltage Range (with respect to

GND)

VAC

22

V

–2

Voltage Range (with respect to

VBUS (converter not switching)⁽²⁾

GND)

22

V

–2

Voltage Range (with respect to

BTST, PMID (converter not switching)⁽²⁾

GND)

–0.3

Voltage Range (with respect to

GND)

SW

16

7

V

–2

Voltage Range (with respect to

GND)

BTST to SW

PSEL

–0.3

Voltage Range (with respect to

GND)

7

V

–0.3

Voltage Range (with respect to

GND)

7

V

D+, D–

–0.3

Voltage Range (with respect to

GND)

BATSNS (converter not switching)

Voltage Range (with respect to

GND)

REGN, TS, CE, PG, BAT, SYS (converter not switching)

7

V

–0.3

Output Sink Current

STAT

6

7

mA

V

Voltage Range (with respect to

GND)

SDA, SCL, INT, QON, STAT

–0.3

Voltage Range (with respect to

GND)

PGND to GND (QFN package only)

INT

0.3

V

Output Sink Current

6

mA

°C

Operating junction temperature, T_J

Storage temperature, T_stg

150

–40

–65

°C

(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

NOM

MAX UNIT

V_BUS

I_in

Input voltage

3.9

13.5 ⁽¹⁾

V

A

Input current (VBUS)

Output current (SW)

3.25

I_SWOP

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7.3 Recommended Operating Conditions (continued)

MIN

NOM

MAX UNIT

V_BATOP

I_BATOP

T_A

Battery voltage

4.624

3.0

6

V

A

Fast charging current

Discharging current (continuous)

Operating ambient temperature

A

85

°C

–40

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A

tight layout minimizes switching noise.

7.4 Thermal Information

BQ25600(D)

THERMAL METRIC

YFF (DSBGA)

UNIT

30 Balls

58.8

0.2

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

8.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.4

Ψ_JT

8.3

Ψ_JB

R_θJC(bot)

N/A

7.5 Electrical Characteristics

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QUIESCENT CURRENTS

V_BAT= 4.5 V, V_BUS< V_AC-UVLOZ

leakage between BAT and VBUS,

T_J< 85°C

,

Battery discharge current (BAT, SW,

SYS) in buck mode

I_BAT

5

µA

V_BAT= 4.5 V, HIZ Mode and

OVPFET_DIS = 1 or No VBUS, I2C

disabled, BATFET Disabled. T_J<

85°C

Battery discharge current (BAT) in

buck mode

I_BAT

17

33

µA

V_BAT= 4.5 V, HIZ Mode and

Battery discharge current (BAT, SW, OVPFET_DIS = 1 or No VBUS, I2C

I_BAT

58

24

85

37

µA

SYS)

Disabled, BATFET Enabled. T_J<

85°C

I_{VAC_HIZ}

Input supply current (VAC) in buck

mode

V_VAC= 5 V, HIZ Mode and

OVPFET_DIS = 1, No battery

V_VAC= 12 V, HIZ Mode and

OVPFET_DIS = 1, No battery

41

37

61

50

µA

I_{VACVBUS_HIZ}

Input supply current (VAC and VBUS V_VAC= 5 V, HIZ Mode and

short) in buck mode

OVPFET_DIS = 1, No battery

V_VAC= 12 V, HIZ Mode and

OVPFET_DIS = 1, No battery

68

90

3

µA

V_VBUS= 12 V, V_VBUS> V_VBAT

converter not switching

,

1.5

mA

Input supply current (VBUS) in buck

mode

I_VBUS

V_VBUS> VUVLO, V_VBUS> V_VBAT

converter switching, VBAT = 3.8V,

ISYS = 0A

,

3

mA

Battery discharge current in boost

mode

V_BAT= 4.2 V, boost mode, I_VBUS= 0

A, converter switching

I_BOOST

VBUS, VAC AND BAT PIN POWER-UP

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7.5 Electrical Characteristics (continued)

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

V_VBUSrising

MIN

TYP

MAX

UNIT

V

V_{BUS_OP}

VBUS operating range

3.9

13.5

VAC for active I²C, no battery

Sense VAC pin voltage

V

V_{VAC_UVLOZ}

V_VACrising

3.3

3.7

3.9

V_{VAC_UVLOZ_HYS}I²C active hysteresis

V_ACfalling from above V_{VAC_UVLOZ}

V_VACrising

300

mV

V

V_{VAC_PRESENT}

REGN turn-on threshold

3.65

V_{VAC_PRESENT_H}

mV

V_VACfalling

500

60

YS

(V_VAC–V_VBAT), V_{BUSMIN_FALL}

_BAT≤V_REG, VAC falling

≤

V_SLEEP

Sleep mode falling threshold

Sleep mode rising threshold

15

131

mV

V

(V_VAC–V_VBAT), V_{BUSMIN_FALL}

_BAT≤V_REG, VAC rising

V_SLEEPZ

115

6.1

220

6.42

11

340

6.75

11.5

15

mV

V

VAC 6.5-V Overvoltage rising

threshold

V_{VAC_OV_RISE}

V_{VAC_OV_HYS}

VAC rising; OVP (REG06[7:6]) = '01'

VAC rising, OVP (REG06[7:6]) = '10'

VAC rising, OVP (REG06[7:6]) = '11'

VAC 10.5-V Overvoltage rising

threshold

10.35

13.5

V

VAC 14-V Overvoltage rising

threshold

14.2

130

V

VAC falling, OVP (REG06[7:6]) =

'01'

VAC 6.5-V Overvoltage hysteresis

VAC 10.5-V Overvoltage hysteresis

mV

VAC falling, OVP (REG06[7:6]) =

'10'

250

300

V_{VAC_OV_HYS}

V_{BAT_UVLOZ}

V_{BAT_DPL_FALL}

V_{BAT_DPL_RISE}

VAC 14-V Overvoltage hysteresis

BAT for active I²C, no adapter

Battery Depletion Threshold

VAC falling, OVP (REG06[7:6]) = '11'

V_BATrising

mV

V

2.5

2.18

2.34

V_BATfalling

2.62

2.86

V

V_BATrising

V

V_{BAT_DPL_HYST}Battery Depletion rising hysteresis

V_BATrising

180

3.8

180

30

mV

Bad adapter detection falling

V_{BUSMIN_FALL}

threshold

V_BUSfalling

3.68

3.9

V

V_{BUSMIN_HYST}

I_BADSRC

Bad adapter detection hysteresis

mV

mA

Bad adapter detection current

source

Sink current from VBUS to GND

POWER-PATH

V_{SYS_MIN}

V_VBAT< SYS_MIN[2:0] = 101,

BATFET Disabled (REG07[5] = 1)

System regulation voltage

3.5

4.4

3.68

V

I_SYS= 0 A, V_VBAT> V_SYSMIN, V_VBAT

4.400 V, BATFET disabled

(REG07[5] = 1)

=

V_BAT+ 50

mV

V_SYS

System Regulation Voltage

Maximum DC system voltage output

I_SYS= 0 A, , Q4 off, V_VBAT≤4.400 V,

V_VBAT> V_SYSMIN= 3.5V

V_{SYS_MAX}

4.45

35

4.48

V

Top reverse blocking MOSFET on-

resistance between VBUS and

PMID - Q1

R_ON(RBFET)

-40°C≤T_A≤125°C

mΩ

Top switching MOSFET on-

resistance between PMID and SW -

Q2

R_ON(HSFET)

55

V_REGN= 5 V , -40°C≤T_A≤125°C

mΩ

Bottom switching MOSFET on-

resistance between SW and GND -

Q3

R_ON(LSFET)

60

30

mΩ

BATFET forward voltage in

supplement mode

V_FWD

mV

10

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7.5 Electrical Characteristics (continued)

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QFN package, Measured from BAT

to SYS, V_BAT= 4.2V, T_J= –40 -

125°C

R_ON(BAT-SYS)

SYS-BAT MOSFET on-resistance

19.5

mΩ

BATTERY CHARGER

V_{BATREG_RANGE}Charge voltage program range

3.856

4.624

V

V_{BATREG_STEP}

Charge voltage step

32

mV

VREG (REG04[7:3]) = 4.208 V

(01011), V, –40 ≤T_J≤85°C

4.187

4.330

4.208

4.229

4.374

V

V_BATREG

Charge voltage setting

VREG (REG04[7:3]) = 4.352 V

(01111), V, –40 ≤T_J≤85°C

4.352

V_BAT= 4.208 V or V_BAT= 4.352 V, –

40 ≤T_J≤85°C

V_{BATREG_ACC}

Charge voltage setting accuracy

0.5%

3000

–0.5%

I_{CHG_REG_RANGE}Charge current regulation range

I_{CHG_REG_STEP}Charge current regulation step

0

mA

60

I_CHG= 240 mA, V_VBAT= 3.1V or

V_VBAT= 3.8 V

I_{CHG_REG}

Charge current regulation setting

0.214

0.24

0.26

A

I_CHG= 240 mA, V_VBAT= 3.1 V or

V_VBAT= 3.8 V

I_{CHG_REG_ACC}

I_{CHG_REG}

Charge current regulation accuracy

Charge current regulation setting

9%

–11%

I_CHG= 720 mA, V_VBAT= 3.1 V or

V_VBAT= 3.8 V

0.68

0.720

1.380

0.76

A

I_{CHG_REG}= 720 mA, V_BAT= 3.1 V or

V_BAT= 3.8 V

I_{CHG_REG}

Charge current regulation accuracy

Charge current regulation setting

Charge current regulation accuracy

-6%

1.30

6%

1.45

6%

I_CHG= 1.38 A, V_VBAT= 3.1 V or

V_VBAT= 3.8 V

I_{CHG_REG}

A

I_CHG= 720 mA or I_CHG= 1.38 A,

V_VBAT= 3.1 V or V_VBAT= 3.8 V

I_{CHG_REG_ACC}

–6%

V_{BATLOWV_FALL}Battery LOWV falling threshold

V_{BATLOWV_RISE}Battery LOWV rising threshold

I_CHG= 240 mA

2.7

3

2.8

3.12

170

2.9

3.24

190

V

Pre-charge to fast charge

IPRECHG[3:0] = '0010' = 180 mA

I_PRECHG

I_{PRECHG_ACC}

I_TERM

Precharge current regulation

150

mA

Precharge current regulation

accuracy

IPRECHG[3:0] = '0010' = 180 mA

5

%

–15

Termination current regulation

I_CHG> 780 mA, ITERM[3:0] = '0010'

= 180 mA, V_VBAT= 4.208 V

145

180

60

215

mA

Termination current regulation

accuracy

I_CHG> 780 mA, , ITERM[3:0] =

'0010' = 180 mA, V_VBAT= 4.208 V

I_{TERM_ACC}

I_TERM

-20%

44

20%

75

I

_CHG≤780 mA, , ITERM[3:0] =

Termination current regulation

mA

'0000' = 60 mA, V_VBAT= 4.208 V

Termination current regulation

accuracy

I

_CHG≤780 mA, ,ITERM[3:0] =

I_{TERM_ACC}

-27%

25%

'0000' = 60 mA, V_VBAT= 4.208 V

V_SHORT

V_SHORTZ

I_SHORT

Battery short voltage

Battery short current

V_VBATfalling

1.85

2.15

50

2

2.25

90

2.15

2.35

117

V

V_VBATrising

V_VBAT< V_SHORTZ

mA

Recharge Threshold below

V_{BAT_REG}

V_RECHG

V_BATfalling, REG04[0] = 0

90

120

150

265

mV

Recharge Threshold below

V_{BAT_REG}

V_RECHG

V_BATfalling, REG04[0] = 1

V_SYS= 4.2 V

200

230

30

mV

mA

I_SYSLOAD

System discharge load current

INPUT VOLTAGE AND CURRENT REGULATION

V_INDPMInput voltage regulation limit

V_INDPM(REG06[3:0] = 0000) = 3.9 V

3.78

3.95

4.1

V

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7.5 Electrical Characteristics (continued)

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–4.5%

4.268

–3%

TYP

4.4

MAX

4%

UNIT

V

V_{INDPM_ACC}

V_INDPM

V_{INDPM_ACC}

V_{DPM_VBAT}

Input voltage regulation accuracy

Input voltage regulation limit

Input voltage regulation accuracy

V_INDPM(REG06[3:0] = 0000) = 3.9 V

V_INDPM(REG06[3:0] = 0110) = 4.4 V

4.532

3%

Input voltage regulation limit tracking VINDPM = 3.9V,

VBAT VDPM_VBAT_TRACK = 300mV,

4.17

4.3

4.46

V

VBAT = 4.0V

V_{DPM_VBAT_ACC}Input voltage regulation accuracy

tracking VBAT

VINDPM = 3.9V,

VDPM_VBAT_TRACK = 300mV,

VBAT = 4.0V

4%

–3%

V_VBUS= 5 V, current pulled from SW,

I_INDPM(REG[4:0] = 00100) = 500

mA, –40 ≤T_J≤85°C

450

750

500

900

1.5

mA

V_VBUS= 5 V, current pulled from SW,

IINDPM (REG[4:0] = 01000) = 900

mA, –40 ≤T_J≤85°C

I_INDPM

USB input current regulation limit

V_VBUS= 5 V, current pulled from SW,

IINDPM (REG[4:0] = 01110) = 1.5 A,

–40 ≤T_J≤85°C

1.28

A

Input current limit during system

start-up sequence

I_{IN_START}

200

mA

BAT PIN OVERVOLTAGE PROTECTION

V_{BATOVP_RISE}Battery overvoltage threshold

V_BATrising, as percentage of

V_{BAT_REG}

103

104

2

105

%

V_BATfalling, as percentage of

V_{BAT_REG}

V_{BATOVP_Fall_HYS}Battery overvoltage falling hysteresis

THERMAL REGULATION AND THERMAL SHUTDOWN

Temperature Increasing, TREG

(REG05[1] = 1) = 110℃

Junction Temperature Regulation

T_{JUNCTION_REG}

110

90

°C

Threshold

T_{JUNCTION_REG}Junction Temperature Regulation

Threshold

Temperature Increasing, TREG

(REG05[1] = 0) = 90℃

Thermal Shutdown Rising

Temperature

T_SHUT

Temperature Increasing

160

30

°C

T_{SHUT_HYST}

Thermal Shutdown Hysteresis

JEITA THERMISTOR COMPARATOR (BUCK MODE)

T1 (0°C) threshold, Charge

suspended T1 below this

temperature.

Charger suspends charge. As

Percentage to V_REGN

V_T1

V_T2

V_T3

72.4%

69%

73.3%

71.5%

68%

74.2%

74%

Falling

As Percentage to V_REGN

As percentage of V_REGN

As Percentage to V_REGN

T2 (10°C) threshold, Charge back to

I_CHG/2 and 4.2 V below this

temperature

67.2%

66%

69%

Falling

66.8%

44.7%

67.7%

45.8%

T3 (45°C) threshold, charge back to

ICHG and 4.05V above this

temperature.

Charger suspends charge. As

Percentage to V_REGN

43.8%

V_T3

V_T5

Falling

As Percentage to V_REGN

45.1%

33.7%

34.5%

45.7%

34.2%

35.3%

46.2%

35.1%

36.2%

T5 (60°C) threshold, charge

suspended above this temperature.

Falling

COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)

12

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7.5 Electrical Characteristics (continued)

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

79.5%

78.5%

30.2%

33.8%

TYP

80%

MAX

80.5%

79.5%

32.2%

34.9%

UNIT

As Percentage to V_REGN(Approx.

-20°C w/ 103AT), T_J= –20°C -

125°C

Cold Temperature Threshold, TS pin

Voltage Rising Threshold

V_BCOLD

V_BHOT

Falling

79%

T_J= –20°C - 125°C

As Percentage to V_REGN(Approx.

60°C w/ 103AT), T_J= –20°C -

125°C

Hot Temperature Threshold, TS pin

Voltage falling Threshold

31.2%

34.4%

Rising

T_J= –20°C - 125°C

CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)

I_{BATFET_OCP}

System over load threshold

6.0

A

PWM

Oscillator frequency, buck mode

Oscillator frequency, boost mode

1320

1150

1500

1412

97%

1680

1660

kHz

f_SW

PWM switching frequency

D_MAX

Maximum PWM duty cycle⁽¹⁾

BOOST MODE OPERATION

V_VBAT= 3.8 V, I_(PMID)= 0 A,

BOOSTV[1:0] = '10' = 5.15 V

V_{OTG_REG}

Boost mode regulation voltage

4.972

-3

5.126

5.280

3

V

Boost mode regulation voltage

accuracy

V_VBAT= 3.8 V, I_(PMID)= 0 A,

BOOSTV[1:0] = '10' = 5.15 V

V_{OTG_REG_ACC}

%

V_VBATfalling, MIN_V_BAT_SEL

(REG01[0]) = 0

2.6

2.9

2.8

3.0

2.9

V

V_VBATrising, MIN_V_BAT_SEL

(REG01[0]) = 0

3.15

V_{BATLOWV_OTG}Battery voltage exiting boost mode

V_VBATfalling, MIN_V_BAT_SEL

(REG01[0]) = 1

2.4

2.7

2.5

2.8

1.4

2.6

2.9

V

V_VBATrising, MIN_V_BAT_SEL

(REG01[0]) = 1

I_OTG

OTG mode output current

BOOST_LIM (REG02[7]) = 1

BOOST_LIM = 0.5 A (REG02[7] = 0)

Rising threshold

1.16

0.5

1.6

0.73

6.15

A

Boost mode RBFET over-current

protection accuracy

I_{OTG_OCP_ACC}

V_{OTG_OVP}

I_{OTG_HSZCP}

OTG overvoltage threshold

5.55

5.8

V

HSFET under current falling

threshold

100

mA

REGN LDO

V_REGN

REGN LDO output voltage

V_VBUS= 9V, I_REGN= 40mA

V_VBUS= 5V, I_REGN= 20mA

5.6

6

V

V_REGN

4.58

4.7

LOGIC I/O PIN CHARACTERISTICS ( CE, PSEL, SCL, SDA,, INT)

V_ILO

V_IH

Input low threshold CE

0.4

V

Input high threshold CE

1.3

I_BIAS

V_ILO

V_IH

High-level leakage current CE

Input low threshold PSEL

Input high threshold PSEL

High-level leakage current PSEL

Pull up rail 1.8 V

Pull up rail 1.8V

1

µA

V

0.4

V

I_BIAS

1

µA

LOGIC I/O PIN CHARACTERISTICS ( PG, STAT)

V_OLLow-level output voltage

0.4

V

D+/D–DETECTION

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7.5 Electrical Characteristics (continued)

V_{VAC_UVLOZ}< V_VAC< V_{VAC_OV}and V_VAC> V_BAT+ V_SLEEP, T_J= –40°C to 125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D+ Threshold for Non-standard

adapter (combined V1P2_VTH_LO

and V1P2_VTH_HI)

V_{D+_1P2}

I_{D+_LKG}

1.05

1.35

V

Leakage current into D+

HiZ

-1

500

1

700

150

24.8

µA

mV

µA

V_{D–_600MVSRC}Voltage source (600 mV)

600

100

I_{D–_100UAISNK}

R_{D–_19K}

V_D–= 500 mV,

50

D–current sink (100 µA)

14.25

D–resistor to ground (19 kΩ)

kΩ

D–comparator threshold for

primary detection

V_{D–_0P325}

250

400

mV

D–pin Rising

D–Threshold for non-standard

adapter (combined V2P8_VTH_LO

and V2P8_VTH_HI)

V_{D–_2P8}

2.55

2.85

V

D–Comparator threshold for non-

standard adapter (For non-standard

–same as bq2589x)

V_{D–_2P0}

1.85

2.15

D–Threshold for non-standard

adapter (combined V1P2_VTH_LO

and V1P2_VTH_HI)

V_{D–_1P2}

I_{D–_LKG}

1.05

-1

1.35

1

V

HiZ

µA

Leakage current into D–

(1) Specified by design. Not production tested.

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

VBUS/BAT POWER UP

VAC rising above ACOV threshold to

turn off Q2

t_ACOV

VAC OVP reaction time

200

30

ns

t_BADSRC

Bad adapter detection duration

ms

BATTERY CHARGER

t_{TERM_DGL}

Deglitch time for charge termination

250

ms

t_{RECHG_DGL}

Deglitch time for recharge

System over-current deglitch time to

turn off Q4

t_{SYSOVLD_DGL}

100

1

µs

Battery over-voltage deglitch time to

disable charge

t_BATOVP

t_SAFETY

Typical Charge Safety Timer Range

Typical Top-Off Timer Range

CHG_TIMER = 1

8

10

30

12

36

hr

t_{TOP_OFF}

TOP_OFF_TIMER[1:0] = 10 (30 min)

24

min

QON TIMING

/QON low time to turn on BATFET and

exit ship mode

t_SHIPMODE

t_{QON_RST_2}

t_{BATFET_RST}

t_{SM_DLY}

0.9

8

1.3

12

s

–10℃≤T_J≤60℃

QON low time to reset BATFET

BATFET off time during full system

reset

250

10

400

15

ms

s

Enter ship mode delay

DIGITAL CLOCK AND WATCHDOG TIMER

t_WDT

f_LPDIG

f_DIG

REG05[4]=1

REGN LDO disabled

REGN LDO enabled

40

30

s

Digital Low Power Clock

Digital Clock

kHz

500

14

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MIN

NOM

MAX

UNIT

f_SCL

SCL clock frequency

400

kHz

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7.7 Typical Characteristics

100

97.5

95

100

97.5

95

92.5

90

92.5

90

87.5

85

87.5

85

82.5

80

82.5

80

V_BUS= 5 V

V_BUS= 9 V

V_BUS= 12 V

V_BAT= 3.1 V

V_BAT= 3.8 V

V_BAT= 4.2 V

77.5

75

77.5

75

0

0.5

1

1.5

Charge Current (A)

2

2.5

3

0

0.2

0.4

0.6

OTG Current (A)

0.8

1

1.2

D001

f_SW= 1.5 MHz

V_BAT=3.8V

V_OTG= 5.15 V

inductor DCR = 18 mΩ

图7-2. Efficiency vs. OTG Current

图7-1. Charge Efficiency vs. Charge Current

6

5

4

5

4

3

2

1

0

3

2

1

0

-1

-2

-3

-4

-5

0

0.2

0.4

0.6

Output Current (A)

0.8

1

1.2

1.4

1.6

0

0.5

1

1.5

Charge Current (A)

2

2.5

3

D001

I_OTG= 1.2 A

V_OTG= 5.15 V

图7-4. Charge Current Accuracy

V_VBAT= 3.8 V

图7-3. OTG Output Voltage vs. Output Current

3.85

4.5

4.4

4.3

4.2

4.1

4

V_BATREG= 4.208 V

V_BATREG= 4.352 V

3.8

3.75

3.7

3.65

3.6

3.55

3.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

D001

图7-5. SYSMIN Voltage vs. Junction Temperature

图7-6. BATREG Charge Voltage vs. Junction

Temperature

16

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2.5

2.25

2

1.8

1.6

1.4

1.2

1

IINDPM = 0.5 A

IINDPM = 0.9 A

IINDPM = 1.5 A

I_CHG= 0.24 A

I_CHG= 0.72 A

I_CHG= 1.38 A

1.75

1.5

1.25

1

0.8

0.6

0.4

0.2

0

0.75

0.5

0.25

0

-40

-25

-10

5

20

35

50

Junction Temperature (°C)

65

80

95

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (°C)

D001

图7-7. Input Current Limit vs. Junction

图7-8. Charge Current vs. Junction Temperature

Temperature

2.25

2

1.75

1.5

1.25

1

0.75

0.5

110 °C

90 °C

0.25

0

55

65

75

85

95

105

Junction Temperature (°C)

115

125

135

D001

图7-9. Charge Current vs. Junction Temperature Under Thermal Regulation

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8 Detailed Description

8.1 Overview

The BQ25600 and BQ25600D is a highly integrated 3.0-A switch-mode battery charger for single cell Li-ion and

Li-polymer batteries. It includes an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET,

Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side

gate drive.

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8.2 Functional Block Diagram

VBUS

PMID

V_{VVAC_PRESENT}

RBFET (Q1)

+

UVLO

SLEEP

ACOV

V_VAC

Q1 Gate

Control

œ

I_IN

V_BAT+ V_SLEEP

+

REGN

BTST

EN_REGN

EN_HIZ

V_VAC

REGN

LDO

œ

V_VAC

+

V_{VAC_OV}

œ

FBO

V_VBUS

VBUS_OVP_BOOST

+

VAC

V_{OTG_OVP}

œ

I_Q2

Q2_UCP_BOOST

Q3_OCP_BOOST

+

V_{OTG_HSZCP}

V_VBUS

œ

+

œ

+

œ

+

HSFET (Q2)

LSFET (Q3)

I_Q3

V_INDPM

SW

+

V_{OTG_BAT}

I_IN

CONVERTER

Control

œ

REGN

BAT

I_INDPM

+

BATOVP

UCP

104% × V _{BAT_REG}

IC T_J

T_REG

PGND

œ

I_{LSFET_UCP}

BATSNS

I_Q2

Q2_OCP

+

œ

+

œ

+

I_{HSFET_OCP}

I_Q3

SYS

V_{BAT_REG}

œ

V_SYSMIN

V_BTST- V_SW

I_CHG

EN_HIZ

EN_CHARGE

EN_BOOST

+

REFRESH

V_{BTST_REFRESH}

I_{CHG_REG}

œ

SYS

I_CHG

V_{BAT_REG}

I_{CHG_REG}

BATFET

(Q4)

Q4 Gate

Control

BAT

I_BADSRC

I_DC

BAD_SRC

+

REF

DAC

Converter

Control State

Machine

œ

IC T_J

T_SHUT

+

TSHUT

œ

BATSNS

V_BATGD

BAT_GD

+

D+ (BQ25600D)

V_QON

Input

Source

Detection

œ

DÅ (BQ25600D)

USB

Adapter

PSEL (BQ25600)

V_REG-V_RECHG

BATSNS

I_CHG

+

RECHRG

QON

œ

INT

STAT

+

TERMINATION

BATLOWV

I_TERM

œ

CHARGE

CONTROL

STATE

V_BATLOWV

+

BATSNS

V_SHORT

MACHINE

œ

BQ25600(D)

+

BATSHORT

SUSPEND

PG (BQ25600)

BATSNS

I2C

Interface

œ

Battery

Temperature

Sensing

TS

SCL SDA CE

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8.3 Feature Description

8.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above

V_{VBUS_UVLOZ}or BAT rises above V_{BAT_UVLOZ}, the sleep comparator, battery depletion comparator and BATFET

driver are active. I²C interface is ready for communication and all the registers are reset to default value. The

host can access all the registers after POR.

8.3.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (V_{BAT _DPL_RISE)}, the BATFET turns on and

connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET

and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET (Supplement Mode). When the system is

overloaded or shorted (I_BAT> I_{BATFET_OCP}), the device turns off BATFET immediately and set BATFET_DIS bit to

indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET

Enable (Exit Shipping Mode) is applied to re-enable BATFET.

8.3.3 Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all

the bias circuits. It detects and sets the input current limit before the buck converter is started. The power-up

sequence from input source is as listed:

1. Power up REGN LDO

2. Poor source qualification

3. Input source type detection is based on D+/D–or PSEL to set default input current limit (IINDPM) register

or input source type.

4. Input voltage limit threshold setting (VINDPM threshold)

5. Converter power up

8.3.3.1 Power Up REGN Regulation

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also

provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The

REGN is enabled when all the below conditions are valid:

• V_VACabove V_{VAC_PRESENT}

• V_VACabove V_BAT+ V_SLEEPZin buck mode or VBUS below V_BAT+ V_SLEEPin boost mode

• After 220-ms delay is completed

If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.

The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when

the device is in HIZ.

8.3.3.2 Poor Source Qualification

After REGN LDO powers up, the device confirms the current capability of the input source. The input source

must meet both of the following requirements in order to start the buck converter.

• VAC voltage below V_{VAC_OV}

• VBUS voltage above V_VBUSMINwhen pulling I_BADSRC(typical 30 mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT

pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source

qualification every 2 seconds.

8.3.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the device runs input source detection through

D+/D– lines or the PSEL pin. The BQ25600D follows the USB Battery Charging Specification 1.2 (BC1.2) to

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detect input source (SDP/ DCP) and nonstandard adapter through USB D+/D– lines. The BQ25600 sets input

current limit through PSEL pins.

After input source type detection is completed, an INT pulse is asserted to the host. in addition, the following

registers and pin are changed:

1. Input Current Limit (IINDPM) register is changed to set current limit

2. PG_STAT bit is set

3. VBUS_STAT bit is updated to indicate USB or other input source

The host can overwrite IINDPM register to change the input current limit if needed. The charger input current is

always limited by the IINDPM register.

8.3.3.3.1 D+/D–Detection Sets Input Current Limit in BQ25600D

The BQ25600D contains a D+/D– based input source detection to set the input current limit at VBUS plug-in.

The D+/D–detection includes standard USB BC1.2 and nonstandard adapter. When input source is plugged in,

the device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream

Port (SDP) and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer expires, the

nonstandard adapter detection is applied to set the input current limit. The nonstandard detection is used to

distinguish vendor specific adapters (Apple and Samsung) based on their unique dividers on the D+/D– pins. If

an adapter is detected as DCP, the input current limit is set at 2.4 A. If an adapter is detected as unknown, the

input current limit is set at 500 mA

表8-1. Nonstandard Adapter Detection

NONSTANDARD

D+ THRESHOLD

INPUT CURRENT LIMIT (A)

D–THRESHOLD

ADAPTER

Divider 1

Divider 2

Divider 3

Divider 4

V_D+within V_{D+ _2p8}

V_D+within V_{D+ _1p2}

V_D+within V_{D+ _2p0}

V_D+within V_{D+ _2p8}

V_D–within V_{D–_2p0}

V_D–within V_{D–_1p2}

V_D–within V_{D–_2p8}

2.1

2

1

2.4

表8-2. Input Current Limit Setting from D+/D–Detection

INPUT CURRENT LIMIT (IINLIM)

D+/D–DETECTION

USB SDP (USB500)

USB DCP

500 mA

2.4 A

1 A

Divider 3

Divider 1

2.1 A

2.4 A

2 A

Divider 4

Divider 2

Unknown 5-V adapter

500 mA

8.3.3.3.2 PSEL Pins Sets Input Current Limit in BQ25600

The BQ25600 has PSEL pin for input current limit setting to interface with USB PHY. It directly takes the USB

PHY device output to decide whether the input is USB host or charging port. When the device operates in host-

control mode, the host needs to IINDET_EN bit to read the PSEL value and update the IINDPM register. When

the device is in default mode, PSEL value updates IINDPM in real time.

表8-3. Input Current Limit Setting from PSEL

INPUT CURRENT LIMIT

INPUT DETECTION

PSEL PIN

VBUS_STAT

(ILIM)

500 mA

2.4A

USB SDP

Adapter

High

Low

001

011

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8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V to 5.4 V) for USB. The device VINDPM is set at 4.5

V. The device supports dynamic VINDPM trackingsettings which tracks the battery voltage. This function can be

enabled via the VDPM_BAT_TRACK[1:0] register bits. When enabled, the actual input voltage limit will be the

higher of the VINDPM register and VBAT + VDPM_BAT_TRACK offset.

8.3.3.5 Converter Power Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery

charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft start when system rail is ramped up. When the system rail is below 2.2 V, the input

current is limited to is to the lower of 200 mA or IINDPM register setting. After the system rises above 2.2 V, the

device limits input current to the value set by IINDPM register.

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed

frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery

voltage, charge current and temperature, simplifying output filter design.

The device switches to PFM control at light load or when battery is below minimum system voltage setting or

charging is disabled. The PFM_DIS bit can be used to prevent PFM operation in either buck or boost

configuration. PFM mod is only enabled when IINDPM is set ≥ 500 mA. When IINDPM is set ≤ 400 mA, PFM

mode is disabled.

8.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices

through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA output requirement.

The maximum output current is up to 1.2 A. The boost operation can be enabled if the conditions are valid:

1. BAT above V_{OTG_BAT}

2. VBUS less than BAT+V_SLEEP(in sleep mode)

3. Boost mode operation is enabled (OTG_CONFIG bit = 1)

4. Voltage at TS (thermistor) pin as a percentage of V_REGNis within acceptable range (V_BHOT< V_TS< V_BCOLD

)

5. After 30-ms delay from boost mode enable

During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5.15 V and the output

current can reach up to 1.2 A , selected through I²C (BOOST_LIM bit). The boost output is maintained when

BAT is above V_{OTG_BAT}threshold.

When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot. The

PFM_DIS bit can be used to prevent PFM operation in either buck or boost configuration.

8.3.5 Host Mode and Standalone Power Management

8.3.5.1 Host Mode and Default Mode in BQ25600 and BQ25600D

The BQ25600 and BQ25600D is a host controlled charger, but it can operate in default mode without host

management. in default mode, the device can be used as an autonomous charger with no host or while host is in

sleep mode. When the charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host

mode, WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the

registers are in the default settings. During default mode, any change on PSEL pin will make real time IINDPM

register changes.

In default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end

of the 10-hour, the charging is stopped and the buck converter continues to operate to supply system load.

Writing a 1 to the WD_RST bit transitions the charger from default mode to host mode. All the device parameters

can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by

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writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog

timer by setting WATCHDOG bits = 00.

When the watchdog timer expires (WATCHDOG_FAULT bit = 1), the device returns to default mode and all

registers are reset to default values except IINDPM, VINDPM, BATFET_RST_EN, BATFET_DLY, and

BATFET_DIS bits.

POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Start watchdog timer

Host programs registers

Y

I2C Write?

N

Default Mode

Reset watchdog timer

Reset selective registers

Y

N

WD_RST bit = 1?

N

Y

I2C Write?

Watchdog Timer

Expired?

图8-1. Watchdog Timer Flow Chart

8.3.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device

provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or

both.

8.3.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-

mΩBATFET improves charging efficiency and minimize the voltage drop during discharging.

8.3.7.1 Autonomous Charging Cycle

With battery charging enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously completes

a charging cycle without host involvement. The device default charging parameters are listed in 表 8-4. The host

can always control the charging operations and optimize the charging parameters by writing to the

corresponding registers through I²C.

表8-4. Charging Parameter Default Setting

DEFAULT MODE

Charging voltage

Charging current

Precharge current

Termination current

Temperature profile

Safety timer

BQ25600 and BQ25600D

4.208V

2.048 A

180 mA

JEITA

10 hours

A new charge cycle starts when the following conditions are valid:

• Converter starts

• Battery charging is enabled (CHG_CONFIG bit = 1 and I_CHGregister is not 0 mA and CE is low)

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• No thermistor fault on TS

• No safety timer fault

• BATFET is not forced to turn off (BATFET_DIS bit = 0)

The charger device automatically terminates the charging cycle when the charging current is below termination

threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.

When a fully charged battery is discharged below recharge threshold (selectable through VRECHG bit), the

device automatically starts a new charging cycle. After the charge is done, toggle CE pin or CHG_CONFIG bit

can initiate a new charging cycle.

The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or

charging fault (blinking). The STAT output can be disabled by setting EN_ICHG_MON bits = 11. in addition, the

status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-

fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is

completed, an INT is asserted to notify the host.

8.3.7.2 Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage

and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage

and regulates current and voltage accordingly.

表8-5. Charging Current Setting

REGISTER DEFAULT

V_BAT

CHARGING CURRENT

CHRG_STAT

SETTING

100 mA

180 mA

2.048 A

< 2.2 V

2.2 V to 3 V

> 3 V

I_SHORT

I_PRECHG

I_CHG

01

10

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will

be less than the programmed value. in this case, termination is temporarily disabled and the charging safety

timer is counted at half the clock rate.

Regulation Voltage

VREG[7:3]

Battery Voltage

Charge Current

ICHG[5:0]

Charge Current

V_BATLOWV(3 V)

V_SHORTZ(2.2 V)

IPRECHG[7:4]

ITERM[3:0]

I_SHORT

Fast Charge and Voltage Regulation

Trickle Charge

Pre-charge

Top-off Timer

(optional)

Safety Timer

Expiration

图8-2. Battery Charging Profile

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8.3.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is

below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps

running to power the system, and BATFET can turn on again to engage Supplement Mode.

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.

Termination is temporarily disabled when the charger device is in input current, voltage, or thermal regulation .

Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

At low termination currents, due to the comparator offset, the actual termination current may be 10 mA-20 mA

higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer

can be applied after termination is detected. The termination timer will follow safety timer constraints, such that if

safety timer is suspended, so will the termination timer. Similarly, if safety timer is doubled, so will the termination

timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read CHRG_STAT

and TOPOFF_ACTIVE to find out the termination status.

Top off timer gets reset at one of the following conditions:

1. Charge disable to enable

2. Termination status low to high

3. REG_RST register bit is set

The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer

value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host

when entering top-off timer segment as well as when top-off timer expires.

8.3.7.4 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

8.3.7.5 JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline

emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high

temperature ranges.

To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds

the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5

range.

At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge current

or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V.

The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at

warm temperature (T3-T5) can be VREG or 4.1V (configured by JEITA_VSET). The current setting at cool

temperature (T1-T2) can be further reduced to 20% of fast charge current (JEITA_ISET).

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100

90

VBATREG

4.1V

JEITA_VSET = 1

JEITA_VSET = 0

80

70

60

JEITA_ISET= 0

50

40

30

JEITA_ISET= 1

20

10

0

T1

0

T2

T3

T5

55

60 65

5

10 15 20

25

30 35

40

45 50

œ5

T1

0

T2

T3

T5

Battery Thermistor Temperature (°C)

5

10 15 20

25

30 35

40

45 50

55

60 65

70

œ5

图8-4. JEITA Profile: Charging Voltage

Battery Thermistor Temperature (°C)

图8-3. JEITA Profile: Charging Current

REGN

TS

RT1

RT2

RTH

103AT

图8-5. TS Resistor Network

方程式1 through 方程式2 describe updates to the resistor bias network.

1

æ

ö

V_REGN´ RTH_COLD´ RTH_HOT

´

-

VT1 VT5

ç

÷

è

ø

RT2 =

V

æ

ö

REGN

RTH_HOT

´

- 1 - RTH_COLD

´

ç

- 1

ç

÷

VT5

VT1

è

ø

è

ø

(1)

(2)

æ

ö

V

æ

_REGNö

- 1

ç

è

÷

ç

÷

VT1

è

ø

RT1=

æ

ö

÷

1

æ

ö

+

ç

÷

RT2

RTH_{COLD ø}

è

ø

è

Select 0°C to 60°C range for Li-ion or Li-polymer battery:

• RTH_COLD= 27.28 KΩ

• RTH_HOT= 3.02 KΩ

• RT1 = 5.23 KΩ

• RT2 = 30.9 KΩ

8.3.7.6 Boost Mode Thermistor Monitor During Battery Discharge Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the V_BCOLDto

V_BHOTthresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended. In

additional, VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once temperature returns within

thresholds, the boost mode is recovered and NTC_FAULT is cleared.

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Temperature Range to Boost

Boost Disabled

100%

V

BCOLD

(œ10°C)

Boost Enabled

Boost Disabled

V

BHOT

(65°C)

0%

图8-6. TS Pin Thermistor Sense Threshold in Boost Mode

8.3.7.7 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The

safety timer is two hours when the battery is below V_BATLOWVthreshold and 10 hours when the battery is higher

than V_BATLOWVthreshold.

The user can program fast charge safety timer through I²C (CHG_TIMER bits). When safety timer expires, the

fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be

disabled through I²C by setting EN_TIMER bit.

During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the

actual charge current is likely to be below the register setting. For example, if the charger is in input current

regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to five hours, the

safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

During the fault, timer is suspended. Once the fault goes away, the timer resumes counting. If user stops the

current charging cycle, and start again, timer gets reset (toggle CE pin or CHRG_CONFIG bit).

8.3.8 Protections

8.3.8.1 Voltage and Current Monitoring in Converter Operation

The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and

boost mode operation.

8.3.8.1.1 Voltage and Current Monitoring in Buck Mode

8.3.8.1.1.1 Input Overvoltage (ACOV)

If VBUS voltage exceeds V_{VAC_OV}(programmable via OVP[2:0] bits), the device stops switching immediately.

During input overvoltage event (ACOV), the fault register CHRG_FAULT bits are set to 01. An INT pulse is

asserted to the host. The device will automatically resume normal operation once the input voltage drops back

below the OVP threshold.

8.3.8.1.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system

would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation

voltage when the system is regulate at V_{SYS_MIN}. Upon SYSOVP, converter stops switching immediately to

clamp the overshoot. The charger provides 30-mA discharge current (I_SYSLOAD) to bring down the system

voltage.

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8.3.8.2 Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode

operation.

8.3.8.2.1 VBUS Soft Start

When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.

8.3.8.2.2 VBUS Output Protection

The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage

protection. The boost build in accurate constant current regulation to allow OTG to adapt to various types of

load. If a short circuit is detected on VBUS, boost turns off and retries 7 times. If retries are not successful, OTG

is disabled with OTG_CONFIG bit cleared. In addition, the BOOST_FAULT bit is set and INT pulse is generated.

The BOOST_FAULT bit can be cleared by host by reenabling boost mode

8.3.8.2.3 Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage

protection which stops switching, clears OTG_CONFIG bit and exits boost mode. At Boost overvoltage duration,

the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also asserted to

the host.

8.3.8.3 Thermal Regulation and Thermal Shutdown

8.3.8.3.1 Thermal Protection in Buck Mode

The BQ25600 and BQ25600D monitors the internal junction temperature T_Jto avoid overheat of the chip and

limits the IC surface temperature in buck mode. When the internal junction temperature exceeds thermal

regulation limit (110°C), the device lowers down the charge current. During thermal regulation, the actual

charging current is usually below the programmed battery charging current. Therefore, termination is disabled,

the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface

temperature exceeds T_SHUT(160°C). The fault register CHRG_FAULT is set to 1 and an INT is asserted to the

host. The BATFET and converter is enabled to recover when IC temperature is T_{SHUT_HYS}(30°C) below

T_SHUT(160°C).

8.3.8.3.2 Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC

junction temperature exceeds T_SHUT(160°C), the boost mode is disabled by setting OTG_CONFIG bit low and

BATFET is turned off. When IC junction temperature is below T_SHUT(160°C) - T_{SHUT_HYS}(30°C), the BATFET is

enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

8.3.8.4 Battery Protection

8.3.8.4.1 Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage

occurs, the charger device immediately disables charging. The fault register BAT_FAULT bit goes high and an

INT is asserted to the host.

8.3.8.4.2 Battery Overdischarge Protection

When battery is discharged below V_{BAT_DPL_FALL}, the BATFET is turned off to protect battery from overdischarge.

To recover from overdischarge latch-off, an input source plug-in is required at VBUS. The battery is charged with

I_SHORT(typically 100 mA) current when the V_BAT< V_SHORT, or precharge current as set in IPRECHG register

when the battery voltage is between V_SHORTZand V_{BAT_LOWV}

.

8.3.8.4.3 System Overcurrent Protection

When the system is shorted or significantly overloaded (I_BAT> I_BATOP) and the current exceeds BATFET

overcurrent limit, the BATFET latches off. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off

condition and turn on BATFET.

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8.4 Device Functional Modes

8.4.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated

above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage rises

above the minimum system voltage, BATFET is fully on and the voltage difference between the system and

battery is the V_DSof BATFET.

When the battery charging is disabled and above minimum system voltage setting or charging is terminated, the

system is always regulated at typically 50 mV above battery voltage. The status register VSYS_STAT bit goes

high when the system is in minimum system voltage regulation.

4.4

Minimum System Voltage

SYS (Charge Disabled)

SYS (Charge Enabled)

4.3

4.2

4.1

4

3.9

3.8

3.7

3.6

3.5

3.4

3.3

2.7

2.9

3.1

3.3

3.5

BAT (V)

3.7

3.9

4.1

4.3

D002

图8-7. System Voltage vs Battery Voltage

8.4.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic

Power management (DPM), which continuously monitors the input current and input voltage. When input source

is over-loaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input

voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input

current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement

mode where the BATFET turns on and battery starts discharging so that the system is supported from both the

input source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) or IDPM_STAT (IINDPM) goes high. shows

the DPM response with 9-V/1.2-A adapter, 3.2-V battery, charge current and 3.5-V minimum system voltage

setting.

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Voltage

9V

VBUS

SYS

BAT

3.6V

3.4V

3.2V

3.18V

Current

4A

ICHG

IIN

3.2A

2.8A

ISYS

1.2A

1.0A

0.5A

-0.6A

DPM

Supplement

图8-8. DPM Response

8.4.3 Supplement Mode

When the system voltage falls 180 mV (V_BAT> V_{SYS_MIN}) or 45 mV (V_BAT< V_{SYS_MIN}) below the battery voltage,

the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET

V_DSstays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement

mode.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce R_DSONuntil

the BATFET is in full conduction. At this point onwards, the BATFET V_DSlinearly increases with discharge

current. 图 8-9 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit

supplement mode when the battery is below battery depletion threshold.

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

5

10 15 20 25 30 35 40 45 50 55

V(BAT-SYS) (mV)

D001

Plot1

图8-9. BAFET V-I Curve

8.4.4 Shipping Mode and QON Pin

8.4.4.1 BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,

the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When

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the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by t_{SM_DLY}as configured by

BATFET_DLY bit.

8.4.4.2 BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following

events can enable BATFET to restore system power:

1. Plug in adapter

2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)

4. A logic high to low transition on QON pin with t_SHIPMODEdeglitch time to enable BATFET to exit shipping

mode

8.4.4.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged in. By

changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a

power-on-reset. The QON pin supports push-button interface to reset system power without host by changing

the state of BATFET.

When the QON pin is driven to logic low for t_{QON_RST}while input source is not plugged in and BATFET is

enabled (BATFET_DIS = 0), the BATFET is turned off for t_{BATFET_RST}and then it is re-enabled to reset system

power. This function can be disabled by setting BATFET_RST_EN bit to 0.

8.4.4.4 QON Pin Operations

The QON pin incorporates two functions to control BATFET. QON is pulled up to V_QONby an internal 200-kΩ

pull-up resistor.

1. BATFET Enable: A QON logic transition from high to low with longer than t_SHIPMODEdeglitch turns on

BATFET to exit shipping mode. When exiting shipping mode, HIZ is enabled (EN_HIZ = 1) as well. HIZ can

be disabled (EN_HIZ = 0) by the host after exiting shipping mode. OTG cannot be enabled (OTG_CONFIG =

1) until HIZ is disabled.

2. BATFET Reset: When QON is driven to logic low by at least t_{QON_RST}while adapter is not plugged in (and

BATFET_DIS = 0), the BATFET is turned off for t_{BATFET_RST}. The BATFET is re-enabled after t_{BATFET_RST}

duration. This function allows systems connected to SYS to have power-on-reset. This function can be

disabled by setting BATFET_RST_EN bit to 0.

图8-10 shows the sample external configurations for each.

QON

Press

push button

Press

push button

t

QON_RST

t

SHIPMODE

t

BATFET_RST

Q4 Status

2

Q4

off

Q4 off due to I C or

system overload

Q4 on

Turn on Q4 FET

when BATFET_DIS = 1 or SLEEPZ = 1

Reset Q4 FET

When BATFET_DIS = 0 and SLEEPZ = 0

图8-10. QON Timing

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SYS

Q4

Control

BAT

V_PULL-UP

+

QON

图8-11. QON Circuit

8.4.5 Status Outputs ( PG, STAT, INT)

8.4.5.1 Power Good Indicator ( PG Pin and PG_STAT Bit)

The PG_STAT bit goes HIGH and PG pin goes LOW to indicate a good input source when:

• VBUS above V_{VBUS_UVLO}

• VBUS above battery (not in sleep)

• VBUS below V_{VAC_OV}threshold

• VBUS above V_VBUSMin(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Completed input Source Type Detection

8.4.5.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin

function can be disabled by setting the EN_ICHG_MON bits = 11.

表8-6. STAT Pin State

CHARGING STATE

STAT INDICATOR

LOW

Charging in progress (including recharge)

Charging complete

HIGH

Sleep mode, charge disable

HIGH

Charge suspend (input overvoltage, TS fault, timer fault or system overvoltage)

Boost Mode suspend (due to TS fault)

Blinking at 1 Hz

8.4.5.3 Interrupt to Host ( INT)

In some applications, the host does not always monitor the charger operation. The INT pulse notifies the system

on the device operation. The following events will generate 256-μs INT pulse.

• USB/adapter source identified (through PSEL pin or DPDM detection)

• Good input source detected

– VBUS above battery (not in sleep)

– VBUS below V_{VAC_OV}threshold

– VBUS above V_VBUSMin(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Input removed

• Charge complete

• Any FAULT event in REG09

• VINDPM / IINDPM event detected (maskable)

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When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads

the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send

any INT upon new faults. To read the current fault status, the host has to read REG09 two times consecutively.

The first read reports the pre-existing fault register status and the second read reports the current fault register

status.

8.5 Programming

8.5.1 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP

Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices

can be considered as masters or slaves when performing data transfers. A master is the device which initiates a

data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device

addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like

micro controller or a digital signal processor through REG00-REG0B. Register read beyond REG0B (0x0B)

returns 0xFF. The I²C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).

connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines

are HIGH. The SDA and SCL pins are open drain.

8.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Data line stable;

Data valid

Change of data

allowed

图8-12. Bit Transfer on the I²C Bus

8.5.1.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The

bus is considered busy after the START condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

START (S)

STOP (P)

图8-13. TS START and STOP conditions

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8.5.1.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Acknowledgement

signal from slave

Acknowledgement

signal from receiver

MSB

1

SDA

SCL

2

7

8

9

1

2

8

9

S or Sr

P or Sr

START or

Repeated

START

STOP or

Repeated

START

ACK

图8-14. Data Transfer on the I²C Bus

8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge ninth clock pulse, are generated by the master. The transmitter releases the SDA line during the

acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH

period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.5.1.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

1 - 7

8

9

1-7

8

9

1-7

8

9

S

P

SCL

START

ADDRESS

R / W

ACK

DATA

ACK

DATA

ACK

STOP

图8-15. Complete Data Transfer

8.5.1.6 Single Read and Write

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

1

7

1

0

1

8

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

Data to Addr

ACK

P

图8-16. Single Write

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1

7

1

0

1

8

1

7

1

S

Slave Address

ACK

Reg Addr

ACK

S

Slave Addr

ACK

8

1

Data

NCK

P

图8-17. Single Read

8.5.1.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0B.

1

7

1

0

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

8

1

8

1

8

1

Data to Addr

ACK

Data to Addr + N

ACK

Data to Addr + N

ACK

P

图8-18. Multi-Write

1

7

1

8

1

7

1

S

Slave Address

0

ACK

Reg Addr

ACK

S

Slave Address

ACK

8

1

8

1

8

1

Data @ Addr

ACK

Data @ Addr + 1

ACK

Data @ Addr + N NCK

P

图8-19. Multi-Read

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For

example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the

fault when it is read the first time, but returns to normal when it is read the second time. in order to get the fault

information at present, the host has to read REG09 for the second time. The only exception is NTC_FAULT

which always reports the actual condition on the TS pin. in addition, REG09 does not support multi-read and

multi-write.

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8.6 Register Maps

I²C Slave Address: 6BH

8.6.1 REG00

表8-7. REG00 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

7

Enable HIZ Mode

0 –Disable (default)

1 –Enable

by REG_RST

by Watchdog

EN_HIZ

0

R/W

0 –Disable, 1 –Enable

6

5

EN_ICHG_MON[1]

EN_ICHG_MON[0]

R/W by REG_RST

R/W

00 –Enable STAT pin function

(default)

01 –Reserved

10 –Reserved

0

by REG_RST

11 –Disable STAT pin function

(float pin)

4

3

2

1

IINDPM[4]

IINDPM[3]

IINDPM[2]

IINDPM[1]

1

0

1

R/W by REG_RST 1600 mA

R/W by REG_RST 800 mA

R/W by REG_RST 400 mA

R/W by REG_RST 200 mA

Input Current Limit

Offset: 100 mA

Range: 100 mA (000000) –3.2 A

(11111)

Default: 2400 mA (10111),

maximum input current limit, not

typical.

IINDPM bits are changed

automatically after input source

detection is completed

BQ25600D

USB SDP = 500 mA

USB DCP = 2.4 A

Unknown Adapter = 500 mA

Non-Standard Adapter = 1 A, 2 A,

2.1 A, or 2.4 A

0

IINDPM[0]

1

R/W by REG_RST 100 mA

BQ25600

PSEL = Hi = 500 mA

PSEL = Lo = 2.4 A

Host can over-write IINDPM

register bits after input source

detection is completed.

LEGEND: R/W = Read/Write; R = Read only

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8.6.2 REG01

表8-8. REG01 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

R/W

0 –Enable PFM

1 –Disable PFM

7

6

PFM _DIS

WD_RST

0

by REG_RST

Default: 0 - Enable

by REG_RST I²C Watchdog Timer Reset 0 –

by Watchdog

Default: Normal (0) Back to 0 after

watchdog timer reset

Normal ; 1 –Reset

Default: OTG disable (0)

Note:

1. OTG_CONFIG would over-ride

Charge Enable Function in

CHG_CONFIG

by REG_RST 0 –OTG Disable

by Watchdog

5

4

OTG_CONFIG

CHG_CONFIG

0

1

1 –OTG Enable

R/W

Default: Charge Battery (1)

Note:

1. Charge is enabled when both

CE pin is pulled low AND

CHG_CONFIG bit is 1.

by REG_RST 0 –Charge Disable

by Watchdog

1 –Charge Enable

3

2

SYS_MIN[2]

SYS_MIN[1]

1

0

R/W by REG_RST

R/W

000: 2.6 V

001: 2.8 V

010: 3 V

011: 3.2 V

100: 3.4 V

101: 3.5 V

110: 3.6 V

111: 3.7 V

System Minimum Voltage

1

0

SYS_MIN[0]

1

0

by REG_RST

Default: 3.5 V (101)

R/W

Minimum battery voltage for OTG

mode. Default falling 2.8 V (0);

Rising threshold 3.0 V (0)

0 –2.8 V BAT falling,

1 –2.5 V BAT falling

MIN_V_BAT_SEL

by REG_RST

LEGEND: R/W = Read/Write; R = Read only

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8.6.3 REG02

表8-9. REG02 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

R/W by REG_RST

by Watchdog 0 –0.5 A

1 –1.2 A

Default: 1.2 A (1)

Note:

The current limit options listed are

minimum current limit specs.

7

BOOST_LIM

1

R/W by REG_RST

0 –Use higher Q1 RDSON when

programmed IINDPM < 700mA

(better accuracy)

In boost mode, full FET is always

used and this bit has no effect

6

Q1_FULLON

0

1 –Use lower Q1 RDSON always

(better efficiency)

R/W by REG_RST

by Watchdog

5

4

3

2

1

0

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

1

0

1

0

1920 mA

960 mA

480 mA

240 mA

120 mA

60 mA

R/W by REG_RST

by Watchdog

Fast Charge Current

Default: 2040 mA (100010)

Range: 0 mA (0000000) –3000

mA (110010)

by REG_RST

R/W

by Watchdog

Note:

R/W by REG_RST

by Watchdog

I_CHG= 0 mA disables charge.

I_CHG> 3000 mA (110010 clamped

to register value 3000 mA

(110010))

R/W by REG_RST

by Watchdog

R/W by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

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8.6.4 REG03

表8-10. REG03 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

7

6

5

4

3

2

1

0

IPRECHG[3]

0

1

0

1

0

R/W

by REG_RST

by Watchdog

480 mA

Precharge Current

Default: 180 mA (0010)

Offset: 60 mA

Note: IPRECHG > 780 mA

clamped to 780 mA (1100)

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

ITERM[3]

by REG_RST

by Watchdog

240 mA

120 mA

60 mA

by REG_RST

by Watchdog

by REG_RST

by Watchdog

by REG_RST

by Watchdog

480 mA

240 mA

120 mA

60 mA

Termination Current

Default: 180 mA (0010)

Offset: 60 mA

Note: ITERM > 780 mA clamped to

780 mA(1100)

ITERM[2]

by REG_RST

by Watchdog

ITERM[1]

by REG_RST

by Watchdog

ITERM[0]

by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

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8.6.5 REG04

表8-11. REG04 Field Descriptions

Description

Bit Field

POR Type Reset

Comment

by REG_RST

by Watchdog

7

6

5

4

3

2

1

0

VREG[4]

0

1

0

1

0

R/W

512 mV

256 mV

128 mV

64 mV

Charge Voltage

Offset: 3.856 V

by REG_RST

by Watchdog

VREG[3]

R/W

Range: 3.856 V to 4.624 V (11000)

Default: 4.208 V (01011)

Special Value:

by REG_RST

by Watchdog

VREG[2]

(01111): 4.352 V

by REG_RST

by Watchdog

VREG[1]

Note: Value above 11000 (4.624 V)

is clamped to register value 11000

(4.624 V)

by REG_RST

by Watchdog

VREG[0]

32 mV

by REG_RST

by Watchdog

00 –Disabled (Default)

01 –15 minutes

10 –30 minutes

The extended time following the

termination condition is met. When

disabled, charge terminated when

termination conditions are met

TOPOFF_TIMER[1]

TOPOFF_TIMER[0]

VRECHG

by REG_RST

by Watchdog

11 –45 minutes

by REG_RST

by Watchdog

0 –100 mV

1 –200 mV

Recharge threshold

Default: 100 mV (0)

LEGEND: R/W = Read/Write; R = Read only

40

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8.6.6 REG05

表8-12. REG05 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

by REG_RST 0 –Disable

7

6

EN_TERM

1

0

R/W

Default: Enable termination (1)

by Watchdog

1 –Enable

Default: Enable OVPFET (0)

Note: This bit only takes effect

when EN_HIZ bit is active

by REG_RST 0 –Enable OVPFET

OVPFET_DIS

by Watchdog

1 –Disable OVPFET

by REG_RST

by Watchdog

5

4

WATCHDOG[1]

WATCHDOG[0]

0

1

R/W

00 –Disable timer, 01 –40 s, 10

–80 s,11 –160 s

Default: 40 s (01)

by REG_RST

by Watchdog

0 –Disable

1 –Enable both fast charge and

precharge timer

by REG_RST

by Watchdog

3

2

1

0

EN_TIMER

CHG_TIMER

TREG

1

R/W

Default: Enable (1)

Default: 10 hours (1)

Default: 110°C (1)

Default: 20% (1)

by REG_RST 0 –5 hrs

by Watchdog

1 –10 hrs

Thermal Regulation Threshold:

0 –90°C

1 –110°C

by REG_RST

by Watchdog

JEITA_ISET

(0C-10C)

by REG_RST 0 –50% of ICHG

by Watchdog

1 –20% of ICHG

LEGEND: R/W = Read/Write; R = Read only

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8.6.7 REG06

表8-13. REG06 Field Descriptions

Description

Bit Field

POR Type Reset

Comment

7

6

5

4

OVP[1]

0

1

0

R/W by REG_RST

VAC OVP threshold:

00 - 5.5 V

01 –6.5 V (5-V input)

10 –10.5 V (9-V input)

11 –14 V (12-V input)

Default: 6.5 V (01)

OVP[0]

R/W by REG_RST

BOOSTV[1]

BOOSTV[0]

R/W by REG_RST

Boost Regulation Voltage:

00 –4.85 V

01 –5.00 V

10 –5.15 V

11 –5.30 V

3

2

1

0

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

0

1

0

R/W by REG_RST 800 mV

R/W by REG_RST 400 mV

R/W by REG_RST 200 mV

R/W by REG_RST 100 mV

Absolute VINDPM Threshold

Offset: 3.9 V

Range: 3.9 V (0000) –5.4 V

(1111)

Default: 4.5 V (0110)

LEGEND: R/W = Read/Write; R = Read only

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8.6.8 REG07

表8-14. REG07 Field Descriptions

Bit Field

POR Type Reset

Description

Comment

0 –Not in D+/D–detection (or

PSEL detection);

1 –Force D+/D–detection

Default: Not in DPDM detection (0)

Note: For PSEL part, reads PSEL

pin value

by REG_RST

by Watchdog

7

6

IINDET_EN

0

1

R/W

0 –Disable

by REG_RST

by Watchdog

1 –Safety timer slowed by 2X

during input DPM (both V and I) or

JEITA cool, or thermal regulation

TMR2X_EN

0 –Allow Q4 turn on, 1 –Turn off

Q4 with t_{BATFET_DLY}delay time

(REG07[3])

5

4

BATFET_DIS

0

R/W by REG_RST

Default: Allow Q4 turn on(0)

0 –Set Charge Voltage to 4.1V

( max),

1 –Set Charge Voltage to VREG

JEITA_VSET

(45C-60C)

by REG_RST

R/W

by Watchdog

0 –Turn off BATFET immediately

when BATFET_DIS bit is set

1 –Turn off BATFET after

t_{BATFET_DLY}(typ. 10 s) when

BATFET_DIS bit is set

Default: 1

Turn off BATFET after t_{BATFET_DLY}

(typ. 10 s) when BATFET_DIS bit

is set

3

BATFET_DLY

1

R/W by REG_RST

by REG_RST 0 –Disable BATFET reset function Default: 1

2

1

BATFET_RST_EN

1

0

R/W

by Watchdog

Enable BATFET reset function

1 –Enable BATFET reset function

VDPM_BAT_TRACK[1]

R/W by REG_RST

00 –Disable function (VINDPM

set by register)

01 –VBAT + 200 mV

10 –VBAT + 250 mV

11 –VBAT + 300 mV

Sets VINDPM to track BAT voltage.

Actual VINDPM is higher of

register value and VBAT +

VDPM_BAT_TRACK

0

VDPM_BAT_TRACK[0]

0

LEGEND: R/W = Read/Write; R = Read only

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8.6.9 REG08

表8-15. REG08 Field Descriptions

Bit Field

POR Type

Reset

Description

7

6

VBUS_STAT[2]

x

R

NA

VBUS Status register

BQ25600D

000: No input

VBUS_STAT[1]

NA

001: USB Host SDP

010: USB CDP: (1.5A)

011: USB DCP (2.4 A)

101: Unknown Adapter (500 mA)

110: Non-Standard Adapter (1A/2A/2.1A/2.4A)

111: OTG

5

VBUS_STAT[0]

x

R

NA

BQ25600

000 –No input

001 –USB Host SDP (500 mA) →PSEL HIGH

011 –Adapter 2.4 A →PSEL LOW

111 –OTG

Software current limit is reported in IINDPM register

4

3

CHRG_STAT[1]

CHRG_STAT[0]

x

R

NA

Charging status:

00 –Not Charging

01 –Pre-charge (< V_BATLOWV

10 –Fast Charging

)

11 –Charge Termination

Power Good status:

0 –Power Not Good

1 –Power Good

2

PG_STAT

x

R

NA

0 –Not in thermal regulation

1 –In thermal regulation

1

0

THERM_STAT

VSYS_STAT

x

R

NA

0 –Not in V_{SYS_MIN}regulation (BAT > V_{SYS_MIN}

1 –In V_{SYS_MIN}regulation (BAT < V_{SYS_MIN}

)

LEGEND: R/W = Read/Write

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8.6.10 REG09

表8-16. REG09 Field Descriptions

Bit Field

POR Type Reset

Description

7

6

WATCHDOG_FAULT

x

R

NA

0 –Normal, 1- Watchdog timer expiration

0 –Normal, 1 –VBUS overloaded in OTG, or VBUS OVP, or battery is

too low (any conditions that cannot start boost function)

BOOST_FAULT

5

4

3

2

1

CHRG_FAULT[1]

CHRG_FAULT[0]

BAT_FAULT

x

R

NA

00 –Normal, 01 –input fault (VAC OVP or VBAT < VBUS < 3.8 V), 10

- Thermal shutdown, 11 –Charge Safety Timer Expiration

0 –Normal, 1 –BATOVP

NTC_FAULT[2]

NTC_FAULT[1]

JEITA

000 –Normal, 010 –Warm, 011 –Cool, 101 –Cold, 110 –Hot

(Buck mode)

0

NTC_FAULT[0]

x

R

NA

000 –Normal, 101 –Cold, 110 –Hot (Boost mode)

LEGEND: R/W = Read/Write; R = Read only

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8.6.11 REG0A

表8-17. REG0A Field Descriptions

Bit Field

POR Type Reset

Description

0 –Not VBUS attached,

1 –VBUS Attached

7

VBUS_GD

x

R

NA

6

5

4

VINDPM_STAT

IINDPM_STAT

Reserved

x

R

NA

0 –Not in VINDPM, 1 –in VINDPM

0 –Not in IINDPM, 1 –in IINDPM

0 –Top off timer not counting.

1 –Top off timer counting

3

2

1

0

TOPOFF_ACTIVE

ACOV_STAT

x

0

R

NA

0 –Device is NOT in ACOV

1 –Device is in ACOV

0 –Allow VINDPM INT pulse

1 –Mask VINDPM INT pulse

VINDPM_INT_ MASK

IINDPM_INT_ MASK

R/W by REG_RST

0 –Allow IINDPM INT pulse

1 –Mask IINDPM INT pulse

LEGEND: R/W = Read/Write; R = Read only

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8.6.12 REG0B

表8-18. REG0B Field Descriptions

Bit Field

POR Type Reset

Description

Register reset

0 –Keep current register setting

1 –Reset to default register value and reset safety timer

Note: Bit resets to 0 after register reset is completed

7

REG_RST

0

R/W NA

6

5

4

3

2

1

0

PN[3]

x

R

NA

PN[2]

BQ25600: 0000

BQ25600D: 0001

PN[1]

PN[0]

Reserved

DEV_REV[1]

DEV_REV[0]

LEGEND: R/W = Read/Write; R = Read only

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

A typical application consists of the device configured as an I²C controlled power path management device and

a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of Smartphone and other

portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The

device also integrates a bootstrap diode for the high-side gate drive.

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9.2 Typical Application

SYSTEM

3.5V œ 4.6V

1 ꢀH

VBUS

PMID

SW

1 ꢀF

10 ꢀF

47 nF

BTST

REGN

10 ꢀF

4.7 µF

GND

SYS

VAC

SYS

Opt.

2.2 kꢁ

PG

BAT

BQ25600

STAT

VREF

10 ꢀF

BATSNS

3 x 10 kꢁ

REGN

5.23 kꢁ

SDA

SCL

INT

CE

TS

Host

+

30.1 kꢁ 10 kꢁ

QON

PHY

PSEL

Optional

图9-1. Power Path Management Application

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SYSTEM

3.5V œ 4.6V

1 ꢀH

VBUS

PMID

SW

1 ꢀF

10 ꢀF

47 nF

BTST

REGN

10 ꢀF

4.7 µF

GND

SYS

VAC

SYS

Opt.

BAT

BQ25600D

STAT

VREF

10 ꢀF

BATSNS

3 x 10 kꢁ

REGN

5.23 kꢁ

SDA

SCL

INT

TS

Host

+

30.1 kꢁ 10 kꢁ

CE

QON

D+

D-

USB

Optional

图9-2. BQ25600D Applications Diagram

9.2.1 Design Requirements

表9-1. Design Parameters

PARAMETER

VALUE

4 V to 13.5 V

3.2 A

VBUS voltage range

Input current limit (REG00[4:0])

Fast charge current limit (REG02[5:0])

Minimum system voltage (REG01[3:1])

Battery regulation voltage (REG04[7:3])

2.4 A

3.5 V

4.2 V

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor

saturation current higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I

_SAT≥I_CHG+ (1/2) I_RIPPLE

(3)

The inductor ripple current depends on the input voltage (V_VBUS), the duty cycle (D = V_BAT/V_VBUS), the switching

frequency (f_S) and the inductance (L).

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V_IN´D ´ (1- D)

=

I_RIPPLE

fs ´ L

(4)

The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually

inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off

between inductor size and efficiency for a practical design.

9.2.2.2 Input Capacitor

Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The

worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not

operate at 50% duty cycle, then the worst case capacitor RMS current I_Cinoccurs where the duty cycle is closest

to 50% and can be estimated using 方程式5.

I_CIN= I_CHG´ D ´ (1- D)

(5)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. A rating of 25 V or higher capacitor is

preferred for 15-V input voltage. Capacitance of 22 μF is suggested for typical of 3-A charging current.

9.2.2.3 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.

方程式6 shows the output capacitor RMS current I_COUTcalculation.

I_RIPPLE

I_COUT

=

» 0.29 ´ I_RIPPLE

2 ´

3

(6)

The output capacitor voltage ripple can be calculated as follows:

æ

ç

è

ö

V_OUT

8LCfs²

V_OUT

V

DV_O=

1-

÷

^INø

(7)

At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC.

The charger device has internal loop compensation optimized for >20-μF ceramic output capacitance. The

preferred ceramic capacitor is 10-V rating, X7R or X5R.

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9.2.3 Application Curves

V_VBUS= 5 V

V_VBAT= 3.2 V

V_VBUS= 5 V

I_CHG= 2 A

V_VBAT= 3.2 V

图9-3. Power-Up with Charge Disabled

图9-4. Power-Up with Charge Enabled

V_VBUS= 5 V

V_VBUS= 9 V

I_SYS= 50 mA

Charge Disabled

图9-5. PFM Switching in Buck Mode

图9-6. PFM Switching in Buck Mode

V_VBUS= 12 V

I_SYS= 50 mA

V_VBUS= 5 V

I_CHG= 2 A

V_VBAT= 3.8 V

Charge Disabled

图9-7. PFM Switching in Buck Mode

图9-8. PWM Switching in Buck Mode

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V_VBUS= 12 V

I_CHG= 2 A

V_VBAT= 3.8 V

V_VBUS= 5 V

I_CHG= 2 A

V_VBAT= 3.2 V

图9-9. PWM Switching in Buck mode

图9-10. Charge Enable

V_VBUS= 5 V

I_CHG= 2 A

V_VBAT= 3.2 V

V_VBAT= 4 V

I_LOAD= 50 mA

PFM Enabled

图9-11. Charge Disable

图9-12. OTG Switching

V_VBAT= 4 V

I_LOAD= 1 A

V_VBAT= 4 V

I_LOAD= 0 A

PFM Enabled

PFM Disabled

图9-13. OTG Switching

图9-14. OTG Switching

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V_VBUS= 5 V

I_INDPM= 1 A

I_CHG= 1 A

V_VBUS= 5 V

I_INDPM= 2 A

I_SYSfrom 0 A to 2 A

V_BAT= 3.7 V

I_SYSfrom 0 A to 4 A

V_BAT= 3.7 V

I_CHG= 1 A

图9-15. System Load Transient

图9-16. System Load Transient

V_VBUS= 5 V

I_INDPM= 1 A

I_CHG= 2 A

V_VBUS= 5 V

I_INDPM= 1 A

I_CHG= 2 A

I_SYSfrom 0 A to 2 A

V_BAT= 3.7 V

I_SYSfrom 0 A to 4 A

V_BAT= 3.7 V

图9-17. System Load Transient

图9-18. System Load Transient

V_VBUS= 5 V

I_INDPM= 2 A

I_CHG= 2 A

V_VBUS= 5 V

I_INDPM= 2 A

I_CHG= 2 A

I_SYSfrom 0 A to 2 A

V_BAT= 3.7 V

I_SYSfrom 0 A to 4 A

V_BAT= 3.7 V

图9-19. System Load Transient

图9-20. System Load Transient

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V_BAT= 3.8 V

C_LOAD= 470 µF

Adaptor I_LIM= 1 A

图9-21. OTG Start-Up

图9-22. VINDPM Tracking Battery Voltage

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10 Power Supply Recommendations

In order to provide an output voltage on SYS, the BQ25600 and BQ25600D device requires a power supply

between 3.9-V and 13.5-V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion

battery with voltage > V_BATUVLOconnected to BAT. The source current rating needs to be at least 3 A in order for

the buck converter of the charger to provide maximum output power to SYS.

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11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see 图 11-1) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems.

备注

It is essential to follow this specific layout PCB order.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper

trace connection or GND plane.

2. Put output capacitor near to the inductor and the IC.

3. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

4. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not

use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other

trace or plane.

5. It is OK to connect all grounds together to reduce PCB size and improve thermal dissipation.

6. Try to avoid ground planes in parallel with high frequency traces in other layers.

See the EVM design for the recommended component placement with trace and via locations.

11.2 Layout Example

+

œ

图11-1. High Frequency Current Path

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

YFF0030

DSBGA - 0.625 mm max height

S

C

A

L

E

4

.

5

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

BALL TYP

0.30

0.12

1.6 TYP

SYMM

F

E

D: Max = 2.392 mm, Min =2.332 mm

E: Max = 1.992 mm, Min =1.931 mm

D

C

SYMM

2

TYP

B

A

0.4 TYP

1

2

4

5

3

0.3

30X

0.4 TYP

0.2

0.015

C A B

4219433/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

YFF0030

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

30X ( 0.23)

(0.4) TYP

2

4

5

1

A

B

C

SYMM

D

E

F

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

(

0.23)

(

0.23)

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219433/A 03/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN

YFF0030

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

30X ( 0.25)

(R0.05) TYP

1

3

2

4

5

A

B

(0.4)

TYP

METAL

TYP

C

D

E

F

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4219433/A 03/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	BQ25600D
厂家：	TEXAS INSTRUMENTS
描述：	具有电源路径、USB 检测和 OTG 且采用 WCSP 封装的 I2C 单节 3A 降压电池充电器电池
文件：	总66页 (文件大小：2298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25600D [TI]

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