BQ25618E [TI]
BQ25618E, BQ25619E I2C Controlled 1-Cell 1.5-A Battery Chargers with 20-mA Termination Current;
| 型号： | BQ25618E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BQ25618E, BQ25619E I2C Controlled 1-Cell 1.5-A Battery Chargers with 20-mA Termination Current 电池 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25618E, BQ25619E
SLUSEC9A – OCTOBER 2020 – REVISED MARCH 2021
BQ25618E, BQ25619E I2C Controlled 1-Cell 1.5-A Battery Chargers with 20-mA
Termination Current
1 Features
2 Applications
•
High-efficiency, 1.5-MHz, synchronous Switch
Mode buck charger
– 95.5% charge efficiency at 0.5 A and 94.5%
efficiency at 1 A
– ±0.5% charge voltage regulation (10-mV step)
– I2C programmable JEITA profile of charge
voltage, current and temperature thresholds
– Low termination current with high accuracy 20
mA±10 mA
– Small inductor form factor of 2.5 x 2.0 x 1.0
mm3
Single input supporting USB input, high-voltage
adapter, or wireless power
– Support 4-V to 13.5-V input voltage range with
22-V absolute max input rating
– Programmable input current limit (IINDPM) with
I2C (100 mA to 3.2 A, 100-mA/step)
– Maximum power tracking by input voltage limit
(VINDPM) up to 5.4 V
•
•
•
•
•
Earbuds (True Wireless or TWS) charging case
Consumer wearables, smartwatch
Personal care and fitness
Headsets/headphone
Hearing aids charging case
3 Description
The BQ25618E/619E integrates charge and voltage
protection in a single device. It offers low termination
current for switching chargers to charge wearable
devices to full battery capacity. The BQ25618E/
BQ25619E low quiescent current reduces battery
leakage down to 7 μA in Ship Mode, which conserves
battery energy to extend the shelf life for the device.
The BQ25619E is in a 4 mm x 4 mm QFN package for
easy layout. The BQ25618E is in a 2.0 mm x 2.4 mm
WCSP package for space-limited designs.
•
Device Information
PART NUMBER
BQ25618E
PACKAGE(1)
BODY SIZE (NOM)
2.00 mm x 2.40 mm
4.00 mm × 4.00 mm
DSBGA (30)
WQFN (24)
– VINDPM threshold automatically tracks battery
voltage
BQ25619E
•
Narrow voltage DC (NVDC) power path
management
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– System instant-on with no battery or deeply
discharged battery
•
•
•
Flexible I2C configuration and autonomous
charging for optimal system performance
High integration includes all MOSFETs, current
sensing and loop compensation
Low RDSON 19.5-mΩ BATFET to minimize
charging loss and extend battery run time
– BATFET control for Ship Mode, and full system
reset with and without adapter
Adapter
Or
Wireless RX
4V œ 13.5V
VBUS
SYS 3.5V-4.6V
SW
I2C Bus
Host
SYS
BAT
Host Control
ICHG
REGN
+
QON
Optional
•
•
7-µA low battery leakage current in Ship Mode
9.5-µA low battery leakage current with system
standby
TS
•
High accuracy battery charging profile
– ±6% charge current regulation
– ±7.5% input current regulation
– Remote battery sensing to charge faster
– Programmable top-off timer for full battery
charging
Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25618E, BQ25619E
SLUSEC9A – OCTOBER 2020 – REVISED MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................12
8.7 Typical Characteristics..............................................13
9 Detailed Description......................................................15
9.1 Overview...................................................................15
9.2 Functional Block Diagram.........................................15
9.3 Feature Description...................................................16
9.4 Device Functional Modes..........................................28
9.5 Register Maps...........................................................30
10 Application and Implementation................................44
10.1 Application Information........................................... 44
10.2 Typical Application.................................................. 44
11 Power Supply Recommendations..............................49
12 Layout...........................................................................50
12.1 Layout Guidelines................................................... 50
12.2 Layout Example...................................................... 50
13 Device and Documentation Support..........................52
13.1 Device Support....................................................... 52
13.2 Documentation Support.......................................... 52
13.3 Receiving Notification of Documentation Updates..52
13.4 Support Resources................................................. 52
13.5 Trademarks.............................................................52
13.6 Electrostatic Discharge Caution..............................52
13.7 Glossary..................................................................52
14 Mechanical, Packaging, and Orderable
Information.................................................................... 53
4 Revision History
Changes from Revision * (October 2020) to Revision A (March 2021)
Page
•
Added BQ25618E to data sheet.........................................................................................................................1
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5 Description (continued)
The BQ25618E/619E is a highly integrated 1.5-A switch-mode battery charge management and system power
path management device for Li-ion and Li-polymer battery. It features fast charging with high input voltage
support for a wide range of applications including earbuds (True Wireless or TWS), earphone charging case, and
wearables. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging
time, and extends battery run time during discharging phase. Its input voltage and current regulation, low
termination current, and battery remote sensing deliver maximum charging power to the battery. The solution is
highly integrated with input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side
switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. It also integrates the
bootstrap diode for the high-side gate drive for simplified system design. The I2C serial interface with charging
and system settings makes the device a truly flexible solution.
The device supports a wide range of input sources, including standard USB host port, USB charging port, USB
compliant high voltage adapter and wireless power. It is compliant with USB 2.0 and USB 3.0 power spec with
input current and voltage regulation. The device takes the result from the detection circuit in the system, such as
USB PHY device.
The power path management regulates the system slightly above battery voltage but does not drop below 3.5-V
minimum system voltage (programmable) with adapter applied. With this feature, the system maintains operation
even when the battery is completely depleted or removed. When the input current limit or voltage limit is
reached, the power path management automatically reduces the charge current. As the system load continues
to increase, the battery starts to discharge the battery until the system power requirement is met. This
supplement mode prevents overloading the input source.
The device initiates and completes a charging cycle without software control. It senses the battery voltage and
charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the
charging cycle, the charger automatically terminates when the charge current is below a preset limit and the
battery voltage is higher than the recharge threshold. If the fully charged battery falls below the recharge
threshold, the charger automatically starts another charging cycle.
The charger provides various safety features for battery charging and system operations, including battery
negative temperature coefficient thermistor monitoring, charging safety timer and overvoltage and over-current
protections. Thermal regulation reduces charge current when the junction temperature exceeds 110°C. The
status register reports the charging status and any fault conditions. With I2C, the VBUS_GD bit indicates if a
good power source is present, and the INT output immediately notifies host when a fault occurs.
The device also provides the QON pin for BATFET enable and reset control to exit low power ship mode or full
system reset function.
The BQ25619E device is available in a 24-pin, 4 mm × 4 mm x 0.75 mm thin WQFN package. The BQ25618E is
available in a 30-ball, 2.0 mm x 2.4 mm WCSP package.
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6 Device Comparison Table
BQ25618
BQ25618E
BQ25619
BQ25619E
NC (pin D5). Leave this
pin floating.
Power Good Indicator
PMID_GOOD Pin
PMID_GOOD Pin
PG Pin
4.6 V/4.75 V/5 V/5.15 V
0.5 A/1.2 A
N/A
N/A
4.6 V/4.75 V/5 V/5.15 V
0.5 A/1.2 A
N/A
N/A
OTG V/I Regulation
Package Type
WCSP-30 2.0 mm x 2.4 mm
QFN-24 4 mm x 4 mm
7 Pin Configuration and Functions
1
2
3
4
5
A
B
GND
GND
BAT
BAT
BAT
SW
PMID
VBUS
VAC
SW
SYS
SYS
SYS
PMID
BTST
TS
VBUS
REGN
/QON
SDA
NC
PSEL
NC
C
D
/CE
STAT
E
BATS
NS
BAT
SYS
/INT
SCL
F
Figure 7-1. BQ25618E YFF Package 30-Pin WCSP Top View
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24
23
22
21
20
19
1
2
3
4
5
6
18
VAC
PSEL
/PG
PGND
17 PGND
16 SYS
BQ25619E
STAT
15
14 BAT
13
SYS
SCL
SDA
BAT
7
8
9
10
11
12
Figure 7-2. BQ25619E RTW Package 24-Pin WQFN Top View
Table 7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
BQ25618E NO.
BQ25619E NO.
Battery connection point to the positive terminal of the battery pack. The internal
current sensing resistor is connected between SYS and BAT. Connect a 10 µF
closely to the BAT pin.
BAT
C1, D1, E1, F1
13, 14
P
Battery voltage sensing pin for charge voltage regulation. In order to minimize the
parasitic trace resistance during charging, BATSNS pin is connected to the
positive terminal of battery pack as close as possible.
BATSNS
BTST
F3
C3
10
21
AIO
P
PWM high side driver positive supply. Internally, the BTST is connected to the
cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor from
SW to BTST.
CE
E3
9
DI
P
Charge enable pin. When this pin is driven LOW, battery charging is enabled.
Ground
GND
A1, B1
17, 18
Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ
resistor. The INT pin sends an active low, 256-µs pulse to the host to report
charger device status and fault.
INT
F4
7
8
DO
—
NC
B5, D5
A3, B3
Not connected. Leave this pin floating.
Connected to the drain of the reverse-blocking MOSFET (RBFET) and the drain
of HSFET. Consider the total input capacitance, put 1 μF on VBUS to GND, and
the rest capacitance on PMID to GND (typical 2x4.7 μF plus 1 nF).
PMID
23
DO
Open drain active low power good indicator. Connect to the pull up rail through
10-kΩ resistor. LOW indicates a good input source if the input voltage is between
UVLO and ACOV, above SLEEP mode threshold, and current limit is above 30
mA. PG is only for the BQ25619E, not the BQ25618E.
PG
N/A
C5
3
2
DO
DI
Power source selection input. HIGH indicates 500-mA input current limit. LOW
indicates 2.4-A input current limit. Once the device gets into host mode, the host
can program a different input current limit to the IINDPM register.
PSEL
BATFET enable/reset control input. When the BATFET is in ship mode, a logic
LOW of tSHIPMODE duration turns on BATFET to exit ship mode. When the
BATFET is not in ship mode, a logic LOW of tQON_RST (minimum 8 s) duration
resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250
ms) and then re-enables BATFET to provide full system power reset. The host
chooses the BATFET reset function with VBUS unplug or not through I2C bit
BATFET_RST_WVBUS. The pin is pulled up to VBAT through 200 kΩ to maintain
default HIGH logic during ship mode. It has an internal clamp to 6.5 V.
QON
D4
C4
12
22
DI
P
PWM low side driver positive supply output. Internally, REGN is connected to the
anode of the boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor
from REGN to analog GND. The capacitor should be placed close to the IC.
REGN
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Table 7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
SCL
BQ25618E NO.
BQ25619E NO.
F5
E4
5
6
DI
I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
SDA
DIO
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ
resistor. The STAT pin indicates charger status.
Charge in progress: LOW
STAT
E5
4
DO
Charge complete or charger in SLEEP Mode: HIGH
Charge suspend (fault response): Blink at 1 Hz
Switching node connecting to output inductor. Internally SW is connected to the
source of the n-channel HSFET and the drain of the n-channel LSFET. Connect
the 0.047-μF bootstrap capacitor from SW to BTST.
SW
A2, B2
19, 20
15, 16
P
P
Converter output connection point. The internal current sensing resistor is
connected between SYS and BAT. Connect a 10 µF (min) closely to the SYS pin.
SYS
C2, D2, E2, F2
Battery temperature qualification voltage input. Connect a negative temperature
coefficient thermistor (NTC). Program temperature window with a resistor divider
from REGN to TS to GND. Charge suspended when TS pin voltage is out of
range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and
a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It
is recommended to use a 103AT-2 thermistor.
TS
D3
11
AI
VAC
A5
1
AI
P
Input voltage sensing. This pin must be tied to VBUS.
Charger input voltage. The internal n-channel reverse-blocking MOSFET
(RBFET) is connected between VBUS and PMID with VBUS on source. Place a
1-μF ceramic capacitor from VBUS to GND and place it as close as possible to
IC.
VBUS
A4, B4
24
Ground reference for the device that is also the thermal pad used to conduct heat
from the device. This connection serves two purposes. The first purpose is to
provide an electrical ground connection for the device. The second purpose is to
provide a low thermal-impedance path from the device die to the PCB. This pad
should be tied externally to a ground plane.
Thermal Pad
N/A
—
P
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,
P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
22
22
22
16
17
22
7
UNIT
V
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
Voltage
VAC (converter not switching)
VBUS (converter not switching)
PMID (converter not switching)
SW
-2
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
BAT, SYS (converter not switching)
BTST
V
V
BATSNS (converter not switching)
PSEL, STAT, SCL, SDA, INT, PG, CE, TS, QON
V
7
V
Output Sink
Current
SDA, STAT, INT, PG
6
mA
TJ
Junction temperature
Storage temperature
–40
–55
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
13.5
4.52
3.2
1.8
1.5
5
UNIT
V
VVBUS
VBAT
IVBUS
ISW
Input voltage
4
Battery voltage
V
Input current
A
Output current (SW)
Fast charging current
RMS discharge current
Ambient temperature
Inductance
A
IBAT
A
IBAT
A
TA
–40
85
°C
µH
µF
µF
µF
µF
µF
L
1
1
2.2
CVBUS
CPMID
CSYS
CBAT
CREGN
VBUS capacitance
PMID capacitance
SYS capacitance
BAT capacitance
REGN capacitance
10
10
10
4.7
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8.4 Thermal Information
BQ25618E
YFF (DSBGA)
30 Balls
BQ25619E
RTW (WQFN)
24 Pins
THERMAL METRIC(1)
UNIT
Junction-to-ambient thermal resistance
RθJA
58.8
35.6
°C/W
(JEDEC(1)
)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.2
8.3
1.4
8.3
N/A
22.7
11.9
0.2
°C/W
°C/W
°C/W
°C/W
°C/W
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
12
RθJC(bot)
2.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
VBAT = 4.5V, VBUS floating or VBUS
= 0V - 5V, SCL, SDA = 0V or 1.8V, TJ
< 85 °C, BATFET enabled
Quiescent battery current (BATSNS,
BAT, SYS, SW)
IQ_BAT
9.5
7
15
µA
µA
VBAT = 4.5V, VBUS floating or VBUS
= 0V - 5V, SCL, SDA = 0V or 1.8V, TJ
< 85 °C, BATFET disabled
Shipmode battery current (BATSNS,
BAT, SYS, SW)
ISHIP_BAT
9.5
Input current (VBUS) in buck mode
when converter is switching
VBUS=5V, charge disabled, converter
switching, ISYS = 0A
IVBUS
2.3
37
68
mA
µA
µA
VAC/VBUS = 5V, HIZ mode, no battery
50
90
IHIZ_VBUS
Quiescent input current in HIZ
VAC/VBUS = 12V, HIZ mode, no
battery
VBUS / VBAT SUPPLY
VVBUS_OP
VBUS operating range
VBUS rising for active I2C, no battery VBUS rising
VBUS falling to turnoff I2C, no battery VBUS falling
4
13.5
3.7
3.3
3.9
3.4
V
V
V
V
V
VVBUS_UVLOZ
VVBUS_UVLO
VVBUS_PRESENT
VVBUS_PRESENTZ
3.3
3
VBUS to enable REGN
VBUS to disable REGN
VBUS rising
VBUS falling
3.65
3.15
VBUS falling, VBUS - VBAT, VBAT =
4V
VSLEEP
Enter Sleep mode threshold
Exit Sleep mode threshold
15
60
110
340
mV
mV
VBUS rising, VBUS - VBAT, VBAT =
4V
VSLEEPZ
115
220
VAC rising, OVP[1:0]=00
VAC rising, OVP[1:0]=01
VAC rising, OVP[1:0]=10
VAC rising, OVP[1:0]=11 (default)
VAC falling, OVP[1:0]=00
VAC falling, OVP[1:0]=01
VAC falling, OVP[1:0]=10
VAC falling, OVP[1:0]=11 (default)
VBAT rising
5.45
6.1
5.85
6.4
6.07
6.75
11.55
14.85
5.8
V
V
V
V
V
V
V
V
V
VAC overvoltage rising threshold to
turn off switching
10.45
13.5
5.2
11
14.2
5.6
VACOV
5.8
6.2
6.45
11.1
VAC overvoltage falling threshold to
resume switching
10
10.7
13.9
13
14.5
VBAT_UVLOZ
BAT voltage for active I2C, no VBUS
2.5
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BAT depletion rising threshold to turn
on BATFET
VBAT_DPLZ
VBAT rising
2.35
2.8
V
BAT depletion falling threshold to turn
off BATFET
VBAT_DPL
VBAT falling
VBUS falling
2.18
3.75
2.62
4.0
V
V
VPOORSRC
Bad adapter detection threshold
3.9
POWER-PATH MANAGEMENT
Typical minimum system regulation
voltage
VBAT=3.2V < SYS_MIN = 3.5V, ISYS
= 0A
VSYS_MIN
3.5
3.65
4.7
35
V
VREG = 4.35V, Charge disabled, ISYS
= 0A
VSYS_OVP
RON_RBFET
RON_RBFET
RON_HSFET
RON_HSFET
RON_LSFET
RON_LSFET
System overvoltage threshold
V
Blocking FET on-resistance
(BQ25618E)
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mV
Blocking FET on-resistance
(BQ25619E)
45
High-side switching FET on-resistance
(BQ25618E)
55
High-side switching FET on-resistance
(BQ25619E)
62
Low-side switching FET on-resistance
(BQ25618E)
60
Low-side switching FET on-resistance
(BQ25619E)
71
BATFET forward voltage in
supplement mode
BAT discharge current 10mA,
converter running
VBATFET
_
30
FWD
BATTERY CHARGER
Typical charge voltage regulation
VREG_RANGE
3.5
4.52
V
range
VREG_STEP
Typical charge voltage step
4.3V < VREG < 4.52V
10
4.2
mV
V
VREG = 4.2V, TJ = –40°C - 85°C
VREG = 4.35V, TJ = –40°C - 85°C
VREG = 4.45V, TJ = –40°C - 85°C
4.179
4.329
4.428
4.221
4.371
4.472
VREG_ACC
Charge voltage accuracy
4.35
4.45
V
V
Typical charge current regulation
range
ICHG_RANGE
ICHG_STEP
0
1.5
A
mA
A
Typical charge current regulation step
20
ICHG = 0.24A, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
0.216
0.24
0.264
Fast charge current regulation
accuracy
ICHG = 0.72A, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
ICHG_ACC
0.6768
0.72 0.7632
A
A
ICHG = 1.50A, VBAT = 3.1V or 3.8V,
TJ = –40°C - 85°C
1.41
20
1.5
1.59
260
IPRECHG_RANGE
IPRECHG_STEP
Typical pre-charge current range
Typical pre-charge current step
mA
mA
mA
mA
mA
mA
20
40
VBAT = 2.6V, IPRECHG = 40mA
VBAT = 2.6V, IPRECHG = 120mA
28
84
20
52
156
260
IPRECHG_ACC
Precharge current accuracy
120
ITERM_RANGE
ITERM_STEP
Typical termination current range
Typical termination current step
20
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ITERM=40mA, ICHG>260mA,
VREG=4.35V, TJ = 0°C - 85°C
30
40
50
30
mA
mA
V
ITERM_ACC
Termination current accuracy
ITERM=20mA, ICHG<260mA,
VREG=4.35V, TJ = 0°C - 85°C
10
20
Battery short voltage rising threshold
to start pre-charge
VBAT_SHORTZ
VBAT rising
2.13
2.25
2.35
Battery short voltage falling threshold
to stop pre-charge
VBAT_SHORT
IBAT_SHORT
VBAT falling
1.85
15
3
2
25
2.15
30
V
mA
V
Battery short trickle charging current
VBAT < VBAT_SHORTZ
VBAT rising
Battery LOWV rising threshold to start
fast-charge
3.12
3.24
VBATLOWV
Battery LOWV falling threshold to stop
fast-charge
VBAT falling
2.7
2.8
2.9
V
VRECHG=0, VBAT falling (default)
VRECHG=1, VBAT falling
90
120
210
150
245
mV
mV
VRECHG
Battery recharge threshold
185
System discharge load current during
SYSOVP
ISYS_LOAD
30
mA
TJ = -40°C - 85°C
TJ = -40°C - 125°C
19.5
19.5
26
30
mΩ
mΩ
RON_BATFET
Battery FET on-resistance
BATTERY OVER-VOLTAGE PROTECTION
Battery overvoltage rising threshold
Battery overvoltage falling threshold
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range
VINDPM_STEP
VBAT rising, as percentage of VREG
VBAT falling, as percentage of VREG
103
101
104
102
105
103
%
%
VBAT_OVP
3.9
5.4
V
Typical input voltage regulation step
100
4.5
mV
Typical input voltage regulation
accuracy
VINDPM_ACC
4.365
4.635
V
V
VINDPM threshold to track battery
voltage
VBAT = 4.35V, VINDPM_BAT_TRACK
= VBAT+200mV
VINDPM_TRACK
4.45
0.1
4.55
4.74
3.2
IINDPM_RANGE
IINDPM_STEP
IINDPM_ACC
IINDPM_ACC
IINDPM_ACC
Typical input current regulation range
Typical input current regulation step
Input current regulation accuracy
Input current regulation accuracy
Input current regulation accuracy
A
100
465
mA
mA
mA
mA
IINDPM = 500mA (TJ=-40°C - 85°C)
IINDPM = 900mA (TJ=-40°C-85°C)
IINDPM = 1500mA (TJ=-40°C-85°C)
450
750
500
900
835
1300
1390
1500
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG = 90°C
90
110
150
130
°C
°C
°C
°C
Junction temperature regulation
accuracy
TREG
TREG = 110°C
TSHUT
Thermal Shutdown Rising threshold
Thermal Shutdown Falling threshold
Temperature Increasing
Temperature Decreasing
CHARGE MODE THERMISTOR COMPARATOR
TS pin voltage rising threshold,
VT1_RISE%
As Percentage to REGN (0°C w/
Charge suspended above this voltage. 103AT)
72.4
71.5
73.3
72
74.2
72.5
%
%
TS pin voltage falling threshold.
Charge re-enabled to 20% of ICHG
and VREG below this
VT1_FALL%
As Percentage to REGN
voltage.
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
As Percentage to REGN,
JEITA_T2=5°C w/ 103AT
70.25
70.75
71.25
68.75
65.75
62.75
69.7
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
As Percentage to REGN,
JEITA_T2=10°C w/ 103AT
67.75
64.75
61.75
68.7
68.25
65.25
62.25
69.2
66.95
64.2
61.2
48.25
44.75
40.7
37.7
49.3
45.8
41.8
39
TS pin voltage rising threshold,
Charge back to 20% of ICHG and
VREG above this voltage.
VT2_RISE%
VT2_FALL%
VT3_FALL%
VT3_RISE%
As Percentage to REGN,
JEITA_T2=15°C w/ 103AT
As Percentage to REGN,
JEITA_T2=20°C w/ 103AT
As Percentage to REGN,
JEITA_T2=5°C w/ 103AT
As Percentage to REGN,
JEITA_T2=10°C w/ 103AT
66.45
63.7
67.45
64.7
TS pin voltage falling threshold.
Charge back to ICHG and VREG
below this voltage.
As Percentage to REGN,
JEITA_T2=15°C w/ 103AT
As Percentage to REGN,
JEITA_T2=20°C w/ 103AT
60.7
61.7
As Percentage to REGN,
JEITA_T3=40°C w/ 103AT
47.75
44.25
40.2
48.75
45.25
41.2
As Percentage to REGN,
JEITA_T3=45°C w/ 103AT
TS pin voltage falling threshold.
Charge to ICHG and 4.1V below this
voltage.
As Percentage to REGN,
JEITA_T3=50°C w/ 103AT
As Percentage to REGN,
JEITA_T3=55°C w/ 103AT
37.2
38.2
As Percentage to REGN,
JEITA_T3=40°C w/ 103AT
48.8
49.8
As Percentage to REGN,
JEITA_T3=45°C w/ 103AT
45.3
46.3
TS pin voltage rising threshold.
Charge back to ICHG and VREG
above this voltage.
As Percentage to REGN,
JEITA_T3=50°C w/ 103AT
41.3
42.3
As Percentage to REGN,
JEITA_T3=55°C w/ 103AT
38.5
39.5
TS pin voltage falling threshold,
As Percentage to REGN (60°C w/
charge suspended below this voltage. 103AT)
VT5_FALL%
33.7
34.2
35.1
TS pin voltage rising threshold.
VT5_RISE%
Charge back to ICHG and 4.1V above As Percentage to REGN
this voltage.
35
35.5
36
%
SWITCHING CONVERTER
FSW
PWM switching frequency
Oscillator frequency
1.32
1.5
97
1.68 MHz
%
DMAX
Maximum PWM Duty Cycle
REGN LDO
VVBUS = 5V, IREGN = 20mA
VVBUS = 9V, IREGN = 20mA
VVBUS = 5V, VREGN = 3.8V
4.58
5.6
50
4.7
6
4.8
6.5
V
V
VREGN
REGN LDO output voltage
REGN LDO current limit
IREGN
mA
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA and
SCL
VIH
Pull up rail 1.8V
1.3
V
VIL
Input low threshold level
Output low threshold level
High-level leakage current
Pull up rail 1.8V
Sink current = 5mA
Pull up rail 1.8V
0.4
0.4
1
V
V
VOL
IBIAS
µA
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH_SDA
VIL_SDA
VOL_SDA
IBIAS_SDA
VIH_SCL
VIL_SCL
Input high threshold level, SDA
Input low threshold level
Output low threshold level
High-level leakage current
Input high threshold level, SDA
Input low threshold level
Output low threshold level
High-level leakage current
Pull up rail 1.8V
1.3
V
Pull up rail 1.8V
Sink current = 5mA
Pull up rail 1.8V
Pull up rail 1.8V
Pull up rail 1.8V
Sink current = 5mA
Pull up rail 1.8V
0.4
0.4
1
V
V
µA
V
1.3
1.3
0.4
0.4
1
V
VOL_SCL
IBIAS_SCL
LOGIC INPUT PIN
VIH
V
µA
Input high threshold level (/CE, PSEL)
Input low threshold level (/CE, PSEL)
V
V
VIL
0.4
1
High-level leakage current (/CE,
PSEL)
IIN_BIAS
Pull up rail 1.8V
µA
LOGIC OUTPUT PIN
Output low threshold level (/INT,
STAT, /PG)
VOL
Sink current = 5mA
Pull up rail 1.8V
0.4
1
V
High-level leakage current (/INT,
STAT, /PG)
IOUT_BIAS
µA
8.6 Timing Requirements
MIN
NOM
MAX
UNIT
VBUS / VBAT POWER UP
tVBUS_OV
VBUS OVP Reaction-time
130
30
2
ns
ms
s
tPOORSRC
Bad adapter detection duration
tPOORSRC_RETRY
BATTERY CHARGER
tTERM_DGL
Bad adapter detection retry wait time
Deglitch time for charge termination
Deglitch time for recharge threshold
30
30
30
20
10
ms
ms
min
hr
tRECHG_DGL
tTOP_OFF
Typical top-off timer accuracy TOP_OFF_TIMER[1:0]=10
Charge safety timer accuracy, CHG_TIMER = 20hr
Charge safety timer accuracy, CHG_TIMER = 10hr
tSAFETY
17
8
24
12
tSAFETY
hr
QON Timing
QON low time to turn on BATFET and exit shipmode (–10℃ ≤ TJ ≤
60℃)
tSHIPMODE
0.9
1.3
s
tQON_RST
tBATFET_RST
tBATFET_DLY
I2C INTERFACE
fSCL
QON low time before BATFET full system reset (–10℃ ≤ TJ ≤ 60℃)
BATFET off time during full system reset (–10℃ ≤ TJ ≤ 60℃)
Delay time before BATFET turn off in ship mode (–10℃ ≤ TJ ≤ 60℃)
8
250
10
12
400
15
s
ms
s
SCL clock frequency
Data set-up time
400
kHz
ns
tSU_STA
10
0
tHD_DAT
Data hold time
70
80
80
ns
trDA
Rise time of SDA signal
Fall time of SDA signal
10
10
ns
tfDA
ns
DIGITAL CLOCK AND WATCHDOG
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8.6 Timing Requirements (continued)
MIN
NOM
30
MAX
UNIT
kHz
kHz
s
fLPDIG
fDIG
Digital low-power clock (REGN LDO is disabled)
Digital power clock
500
160
tWDT
Watchdog Reset time (WATCHDOG REG05[5:4] = 160s)
8.7 Typical Characteristics
100
100
95
90
85
80
75
70
65
95
90
85
80
75
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
0
0.2
0.4
0.6
Charge Current (A)
0.8
1
1.2
1.4
1.6
0
0.2
0.4
0.6
Charge Current (A)
0.8
1
1.2
1.4
1.6
Char
Char
BQ25619EVM VBAT = 3.8 V Inductor 2.2 µH, DCR = 40 mΩ
BQ25618EVM VBAT = 3.8 V Inductor 1.0 µH, DCR = 27 mΩ
Figure 8-1. Charge Efficiency
Figure 8-2. Charge Efficiency
10
4.45
VBUS = 5 V
VBUS = 9 V
VBATREG = 4.35 V
9
8
7
6
5
4
3
2
1
0
4.4
4.35
4.3
4.25
0
0.2
0.4
0.6
Charge Current (A)
0.8
1
1.2
1.4
1.6
-40
-15
10
35
60
85
110 125
Junction Temperature (èC)
Char
Char
Figure 8-3. Charge Current Accuracy
Figure 8-4. Battery Charge Voltage vs Junction
Temperature
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1.6
4.6
4.5
4.4
4.3
4.2
4.1
4
ICHG = 500 mA
ICHG = 1000 mA
ICHG = 1380 mA
VINDPM = 4.1 V
VINDPM = 4.3 V
VINDPM = 4.4 V
VINDPM = 4.5 V
1.4
1.2
1
0.8
0.6
0.4
-40
-25
-10
5
20
35
50
65
8085
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (èC)
Junction Temperature (èC)
Char
VIND
Figure 8-5. Charge Current vs Junction
Temperature
Figure 8-6. VINDPM vs Junction Temperature
3.8
1.75
IINDPM = 0.5 A
INDPM = 0.9 A
INDPM = 1.5 A
1.5
1.25
1
3.75
3.7
0.75
0.5
3.65
3.6
0.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (èC)
-40
-25
-10
5
20
35
Junction Temperature (°C)
50
65
8085
VSYS
IIND
Figure 8-7. SYSMIN Voltage vs Junction
Temperature (VSYS set at 3.5 V)
Figure 8-8. Input Current Limit vs Junction
Temperature
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9 Detailed Description
9.1 Overview
The BQ25618E/619E device is a highly integrated 1.5-A switch-mode battery charger for single cell Li-Ion and
Li-polymer battery. It includes the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET,
Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side
gate drive.
9.2 Functional Block Diagram
VBUS
PMID
VVBUS_UVLOZ
RBFET (Q1)
+
UVLO
SLEEP
ACOV
VVBUS
Q1 Gate
Control
œ
IIN
VBAT + VSLEEP
+
REGN
BTST
EN_REGN
EN_HIZ
VAC
VVBUS
REGN
LDO
œ
VVBUS
+
VVAC_OV
œ
FBO
IQ2
+
Q2_OCP
IHSFET_OCP
œ
VVBUS
VBTST - VSW
œ
+
+
œ
+
œ
œ
+
+
HSFET (Q2)
LSFET (Q3)
REFRESH
VINDPM
VBTST_REFRESH
SW
œ
IIN
CONVERTER
Control
REGN
BAT
IINDPM
+
BATOVP
UCP
104% × V BAT_REG
IC TJ
TREG
PGND
œ
ILSFET_UCP
BATSNS
+
œ
+
œ
+
IQ3
SYS
VBAT_REG
œ
VSYSMIN
ICHG
EN_HIZ
EN_CHARGE
ICHG_REG
SYS
ICHG
VBAT_REG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
IBADSRC
IDC
BAT
BAD_SRC
+
REF
DAC
Converter
Control State
Machine
œ
IC TJ
TSHUT
+
TSHUT
œ
BATSNS
BATSNS
VBATGD
BAT_GD
+
VQON
Input
Source
Detection
œ
USB
Adapter
PSEL
VREG -VRECHG
BATSNS
ICHG
+
RECHRG
/QON
œ
/INT
STAT
/PG*
+
TERMINATION
BATLOWV
ITERM
BQ25618E
BQ25619E
œ
CHARGE
CONTROL
STATE
VBATLOWV
+
BATSNS
VSHORT
MACHINE
œ
* /PG pin is only for BQ25619E.
+
BATSHORT
SUSPEND
BATSNS
I2C
Interface
œ
Battery
Sensing
Thermistor
TS
SCL SDA /CE
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9.3 Feature Description
9.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VVBUS rises above
VVBUS_UVLOZ or VBAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
9.3.2 Device Power Up From Battery Without Input Source
If only the battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and
connects the battery to the system. The REGN stays off to minimize the quiescent current. The low RDSON of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET. When the system is overloaded or shorted
(IBAT > ISYS_OCP_Q4), the device turns off BATFET immediately.
With I2C, when the BATFET turns off due to over-current, the device sets the BATFET_DIS bit to indicate the
BATFET is disabled until the input source plugs in again or one of the methods described in Section 9.3.6.2 is
applied to re-enable BATFET.
9.3.3 Power Up From Input Source
When an input source is plugged in, the device checks the input source voltage to turn on the REGN LDO and
all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:
1. Power Up REGN LDO, see Section 9.3.3.1
2. Poor Source Qualification, see Section 9.3.3.2
3. Input Source Type Detection is based on PSEL to set default input current limit (IINDPM threshold), see
Section 9.3.3.3
4. Input Voltage Limit Threshold Setting (VINDPM threshold), see Section 9.3.3.4
5. Power Up Converter, see Section 9.3.3.5
9.3.3.1 Power Up REGN LDO
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. It also provides the
bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN LDO is
enabled when all the below conditions are valid:
•
•
•
VVBUS > VVBUS_UVLOZ
In buck mode, VVBUS > VBAT + VSLEEPZ
After 220-ms delay is completed
During high impedance mode when EN_HIZ bit is 1, REGN LDO turns off. The battery powers up the system.
9.3.3.2 Poor Source Qualification
After the REGN LDO powers up, the device starts to check current capability of the input source. The first step is
poor source detection.
•
VBUS voltage above VPOORSRC when pulling IBADSRC (typical 30 mA)
With I2C, once the input source passes poor source detection, the status register bit VBUS_GD is set to 1 and
the INT pin is pulsed to signal to the host.
If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.
9.3.3.3 Input Source Type Detection (IINDPM Threshold)
After poor source detection, the device runs input source detection through the PSEL pin. The PSEL pin sets
input current limit 0.5 A (HIGH) or 2.4 A (LOW). After input source type detection is completed, the PG pin is
asserted to LOW and PG_STAT bit is set to 1 (BQ25619E only).
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With I2C, after input source type detection is completed, an INT pulse is asserted to the host. in addition, the
following register bits are updated:
1. Input Current Limit (IINDPM) register is updated from detection result
2. VBUS_STAT bit is updated to indicate USB or other input source
3. PG_STAT bit is updated to indicate good adapter plugs in (BQ25619E only)
The host can over-write the IINDPM register to change the input current limit if needed.
9.3.3.3.1 PSEL Pins Sets Input Current Limit
The device with PSEL pin directly takes the USB PHY device output to decide whether the input is USB host or
charging port. When the device operates in host-control mode, the host needs to IINDET_EN bit set to 1 to
update the IINDPM register. When the device is in default mode , PSEL value updates IINDPM in real time.
Table 9-1. Input Current Limit Setting from PSEL
INPUT CURRENT LIMIT
INPUT DETECTION
PSEL PIN
VBUS_STAT
(ILIM)
500 mA
2.4A
USB SDP
Adapter
HIGH
LOW
001
011
9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device has two modes to set the VINDPM threshold.
•
•
Fixed VINDPM threshold. The VINDPM is default set at 4.5 V (programmable from 3.9 V to 5.4 V).
VINDPM threshold tracks the battery voltage to optimize the converter headroom between input and output.
When it is enabled in REG07[1:0], the actual input voltage limit is the higher of the VINDPM setting in register
and VBAT + offset voltage in VINDPM_BAT_TRACK[1:0].
9.3.3.5 Power Up Converter in Buck Mode
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. The
system voltage is powered from the converter instead of the battery. If battery charging is disabled, the BATFET
turns off. Otherwise, the BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramping up. When the system rail is below VBAT_SHORT, the
input current is limited to the lower of 200 mA or IINDPM register setting. The system load shall be appropriately
planned not to exceed the 200-mA IINDPM limit. After the system rises above VBAT_SHORTZ, the device input
current limit is the value set by the IINDPM register.
As a battery charger, the device deploys a highly efficient 1.5-MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature simplifying output filter design.
The converter supports PFM operation by default for fast transient response during system voltage regulation
and better light load efficiency. The PFM_DIS bit disables PFM operation if system voltage is not in regulation.
9.3.3.6 HIZ Mode with Adapter Present
By setting EN_HIZ bit to 1 with adapter, the device enters high impedance state (HIZ). In HIZ mode, the system
is powered from battery even with good adapter present. The device is in the low input quiescent current state
with Q1 RBFET, REGN LDO and the bias circuits off.
9.3.4 Power Path Management
The device accommodates a wide range of input sources such as USB, wall adapter, or car charger. The device
provides automatic power path selection to supply the system (SYS) from the input source (VBUS), battery
(BAT), or both.
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9.3.4.1 Narrow Voltage DC (NVDC) Architecture
The device deploys NVDC architecture with BATFET separating system from battery. The minimum system
voltage is set by the SYS_MIN bits. Even with a fully depleted battery, the system is regulated above the
minimum system voltage.
When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO
mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage
rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system
and battery is the VDS of the BATFET.
When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50 mV above the battery voltage. The status register VSYS_STAT bit
goes to 1 when the system is in minimum system voltage regulation.
4.5
Minimum System Voltage
Charge Disabled
Charge Enabled
4.1
4.3
3.9
3.7
3.5
3.3
3.1
2.7
2.9
3.1
3.3
3.5
BAT (V)
3.7
3.9
4.1
4.3
D002
Figure 9-1. System Voltage vs Battery Voltage
9.3.4.2 Dynamic Power Management
To meet the maximum current limit in the USB specification and avoid overloading the adapter, the device
features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.
When input source is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls
below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls
below the input current limit or the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and the battery starts discharging so that the system is supported from both
the input source and battery.
During DPM mode, the status register bits VINDPM_STAT or IINDPM_STAT go to 1.
9.3.4.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation
from entering and exiting the supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. The BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.
9.3.5 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 1.5-A charge current for high capacity tablet battery. The 19.5-
mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging.
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9.3.5.1 Autonomous Charging Cycle
When battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously
completes a charging cycle without host involvement. The device default charging parameters are listed in Table
9-2. The host configures the power path and charging parameters by writing to the corresponding registers
through I2C.
Table 9-2. Charging Parameter Default Setting
DEFAULT MODE
Charging voltage
Charging current
Pre-charge current
Termination current
Temperature profile
Safety timer
BQ25618E/619E
4.20 V
340 mA
40 mA
60 mA
JEITA
10 hours
A new charge cycle starts when the following conditions are valid:
•
•
•
•
•
Converter starts
Battery charging is enabled (CHG_CONFIG bit = 1 and ICHG register is not 0 mA and CE is low)
No thermistor fault on TS (TS pin can be ignored by setting TS_IGNORE bit to 1)
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0)
The device automatically terminates the charging cycle when the charging current is below the termination
threshold, the battery voltage is above the recharge threshold, and the device is not in DPM mode or thermal
regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG
bit), the device automatically starts a new charging cycle. After the charge is done, toggle CE pin or
CHG_CONFIG bit will initiate a new charging cycle. Adapter removal and replug will also restart a charging
cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (blinking). The status register (CHRG_STAT) indicates the different charging phases: 00-charging
disable, 01-pre-charge, 10-fast charge (CC) and constant voltage (CV), 11-charging done. Once a charging
cycle is completed, an INT pulse is asserted to notify the host.
9.3.5.2 Battery Charging Profile
The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage
and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage
and regulates current and voltage accordingly.
Resistance between charger output and battery cell terminal such as board routing, connector, MOSFETs and
sense resistor can force the charging process to move from constant current to constant voltage too early and
increase charge time. To speed up the charging cycle, the device provides BATSNS pin to extend the constant
current charge time to deliver maximum power to battery. BATSNS pin should be connected directly to battery
cell terminal to remotely sense battery cell voltage. When battery voltage is above VBAT_DPLZ, charger will detect
whether the BATSNS pin is connected to BAT or not.
•
If BATSNS pin is not connected to BAT, BATSNS_DIS = 1, and charger regulates battery voltage through the
BAT pin
•
If BATSNS pin is connected to BAT, BATFET_DIS = 0, and charger regulates battery voltage through the
BATSNS pin
When battery voltage is below VBAT_DPLZ, charger will automatically regulate charge voltage through BAT pin
without BATSNS detection.
•
When battery voltage rises above VBAT_DPLZ, host can set BATSNS_DIS to 0, to initiate BATSNS detection
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Table 9-3. Charging Current Setting
VBAT
< 2.2 V
CHARGING CURRENT
DEFAULT SETTING
CHRG_STAT
IBAT_SHORT
25 mA
01
01
10
2.2 V to 3 V
> 3 V
IPRECHG
40 mA
ICHG
340 mA
Regulation Voltage
Charge Current
Battery Voltage
Charge Current
VBATLOWV (3 V)
VSHORTZ (2.2 V)
IPRECHG
ITERM
ISHORT
Fast Charge and Voltage Regulation
Trickle Charge
Pre-charge
Safety Timer
Expiration
Top-off Timer
Figure 9-2. Battery Charging Profile
9.3.5.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above the recharge threshold, and the current
is below termination current. After the charging cycle is completed, the BATFET turns off. The STAT is asserted
HIGH to indicate charging done. The converter keeps running to power the system, and BATFET can turn on
again to engage Section 9.3.4.3.
If the device is in IINDPM/VINDPM regulation, or thermal regulation, the actual charging current will be less than
the termination value. In this case, termination is temporarily disabled.
When termination occurs, STAT pin goes HIGH. The status register CHRG_STAT is set to 11, and an INT pulse
is asserted to the host. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
The termination current is set in REG03[3:0]. For small capacity battery, the termination current can be set as
low as 20 mA for full charge. Due to the termination current accuracy, the actual termination current may be
higher than the termination target. In order to compensate for termination accuracy, a programmable top-off
timer can be applied after termination is detected . The top-off timer will follow safety timer constraints, such that
if safety timer is suspended, so will the top-off timer. Similarly, if safety timer is doubled, so will the termination
top-off timer. TOPOFF_ACTIVE bit reports whether the top off timer is active or not. The host can read
CHRG_STAT and TOPOFF_ACTIVE to find out the termination status. STAT pin stays HIGH during top-off timer
counting cycle.
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value (01, 10, 11) after termination will have no effect unless a recharge cycle is initiated. The top-off timer will
immediately stop if it is disabled (00). An INT is asserted to the host when entering top-off timer segment as well
as when top-off timer expires.
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9.3.5.4 Thermistor Qualification
The device provides a single thermistor input for battery temperature monitoring.
9.3.5.4.1 JEITA Guideline Compliance During Charging Mode
To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The
guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low
and high temperature ranges.
To initiate a charge cycle, the voltage on TS pin, as a percentage of VREGN, must be within the VT1_FALL% to
VT5_RISE% thresholds. If the TS voltage percentage exceeds the T1-T5 range, the controller suspends charging,
a TS fault is reported and waits until the battery temperature is within the T1 to T5 range.
At cool temperature (T1-T2), the charge current is reduced to a programmable fast charge current (0%, 20%
default, 50%, 100% of ICHG, by JEITA_ISET). At warm temperature (T3-T5), the charge voltage is reduced to 4.1
V or kept at VREG (JEITA_VSET). and the charge current can be reduced to a programmable level (0%, 20%,
50%, 100% default). Battery termination is disabled in T3-T5. The charger provides more flexible settings on T2
and T3 threshold as well to program the temperature profile beyond JEITA. When the T1 is set to 0°C and T5 is
set to 60°C, T2 can be programmed to 5.5°C/10°C(default)/15°C/20°C, and T3 can be programmed to 40°C/
45.5°C(default)/50.5°C/54.5°C.
When charger does not need to monitor the NTC, host sets TS_IGNORE bit to 1 to ignore the TS pin condition
during charging mode. If TS_IGNORE bit is set to 1, TS pin is ignored and the charger ignore TS pin input. In
this case, NTC_FAULT bits are 000 to report normal TS status.
JEITA_WARM_ISET
100% of ICHG
(default)
(0%, 20%, 50%, 100%)
JEITA_VSET
4.1V (default)
(VREG or 4.1V)
JEITA_COOL_ISET
20% of ICHG
(default)
(0%,20%,50%,100%)
T3
T1
0
T2
T5
60
10
5
15 20
30 35
45 50
40
25
Battery Thermistor Temperature (°C)
Figure 9-3. JEITA Profile
Equation 1 through Equation 2 describe how to calculate resistor divider values on TS pin.
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REGN
TS
RT1
RT2
NTC
103AT
Figure 9-4. TS Pin Resistor Network
%
(1)
(2)
%
%
%
%
In the equations above, RNTC, T1 is NTC thermistor resistance value at temperature T1 and RNTC, T5 is NTC
thermistor resistance values at temperature T5. Select 0°C to 60°C range for Li-ion or Li-polymer battery then
•
•
•
•
RNTC,T1 = 27.28 KΩ (0°C)
RNTC,T5 = 3.02 KΩ (60°C)
RT1 = 5.3 KΩ
RT2 = 31.14 KΩ
9.3.5.5 Charging Safety Timer
The device has a built-in safety timer to prevent extended charging cycle due to abnormal battery conditions.
The safety timer is 2 hours when the battery is below VBATLOWV threshold and 10 hours (10/20 hours in
REG05[2] ) when the battery is higher than VBATLOWV threshold. When the safety timer expires, STAT pin is
blinking at 1 Hz to report a safety timer expiration fault.
The user can program the fast charge safety timer through I2C (CHG_TIMER bit REG05[2]). When safety timer
expires, the fault register CHRG_FAULT bits (REG09[5:4]) are set to 11 and an INT is asserted to the host. The
safety timer (both fast charge and pre-charge) can be disabled through I2C by setting EN_TIMER bit.
During IINDPM/VINDPM regulation, thermal regulation, or JEITA cool/warm when fast charge current is
reduced,the safety timer counts at a half clock rate, because the actual charge current is likely below the setting.
For example, if the charger is in input current regulation (IINDPM_STAT = 1) throughout the whole charging
cycle, and the safety time is set to 10 hours, the safety timer will expire in 20 hours. This half clock rate feature
can be disabled by writing 0 to the TMR2X_EN bit.
During faults of BAT_FAULT, NTC_FAULT that lead to charging suspend, safety timer is suspended as well.
Once the fault goes away, timer resumes. If user stops the current charging cycle, and start again, timer gets
reset (toggle CE pin or CHG_CONFIG bit).
9.3.6 Ship Mode and QON Pin
9.3.6.1 BATFET Disable (Enter Ship Mode)
To extend battery life and minimize power when the system is powered off during system idle, shipping, or
storage, the device turns off BATFET so that the system voltage is floating to minimize the battery leakage
current. When the host sets the BATFET_DIS bit, the charger can turn off the BATFET immediately or delay by
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tBATFET_DLY as configured by the BATFET_DLY bit. To set the device into Ship Mode with the adapter present,
the host has to first set BATFET_RST_VBUS to 1 and then BATFET_DIS to 1. The charger will turn off the
BATFET (no charging, no supplement) while the adapter is still attached. When the adapter is removed, the
charger will enter Ship Mode.
9.3.6.2 BATFET Enable (Exit Ship Mode)
When the BATFET is disabled (in Ship Mode) as indicated by setting BATFET_DIS, one of the following events
can enable the BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit Ship Mode.
9.3.6.3 BATFET Full System Reset
The BATFET functions as a load switch between battery and system when input source is not plugged in. When
BATFET_RST_EN = 1 and BATFET_DIS = 0, BATFET full system reset function is enabled. By changing the
state of BATFET from on to off, systems connected to SYS can be effectively forced to have a power-on-reset.
After the reset is complete, device is in POR state, and all the registers are in POR default settings. The QON
pin supports push-button interface to reset system power without host by changing the state of BATFET.
Internally, it is pulled up to the VQON voltage through a 200-kΩ resistor.
When the QON pin is driven to logic low for tQON_RST, BATFET reset process starts. The BATFET is turned off
for tBATFET_RST and then it is re-enabled to reset system power. This function can be disabled by setting
BATFET_RST_EN bit to 0.
BATFET full system reset functions either with or without adapter present. If BATFET_RST_WVBUS = 1, the
system reset function starts after tQON_RST when QON pin is pushed to LOW. Once the reset process starts, the
device first goes into HIZ mode to turn off the converter, and then power cycles BATFET. If
BATFET_RST_WVBUS = 0, the system reset function does not start until tQON_RST after QON pin is pushed to
LOW and adapter is removed.
After BATFET full system reset is complete, the device will power up again if EN_HIZ is not set to 1 before the
system reset.
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Adapter
/QON
SYS
Q4
Control
VQON
/QON
tBATFET_DLY
tSHIPMODE
ON
BATFET Q4
OFF
Enter Shipmode
after BATFET_DIS=1
Exit Shipmode
with /QON
BATFET_RS
T_WVBUS
Adapter
tQON_RST
tQON_RST
tQON_RST
/QON
ON
ON
ON
Q4
OFF
OFF
OFF
tBATFET_RST
tBATFET_RST
tBATFET_RST
Enter HIZ
Enter HIZ
BATFET Reset with
BATFET_RST_WVBUS=0
BATFET Reset with
BATFET_RST_WVBUS=1
Figure 9-5. QON Timing
9.3.7 Status Outputs ( STAT, INT , PG )
9.3.7.1 Power Good Indicator (PG_STAT Bit; BQ25619E only)
The PG_STAT bit goes 1 to indicate a good input source when:
•
•
•
•
•
VVBUS above VVBUS_UVLO
VVBUS above battery (not in sleep)
VVBUS below VACOV threshold
VVBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Completed Section 9.3.3.3
9.3.7.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.
Table 9-4. STAT Pin State
CHARGING STATE
STAT INDICATOR
LOW
Charging in progress (including recharge)
Charging termination (top off timer may be running)
Sleep Mode, charge disable
HIGH
HIGH
Charge suspend (input overvoltage, TS fault, safety timer fault or system overvoltage)
Blinking at 1 Hz
9.3.7.3 Interrupt to Host ( INT)
In some applications, the host does not always monitor the charger operation. The INT pulse notifies the host on
the device operation. The following events will generate a 256-μs INT pulse.
•
Good input source detected
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– VVBUS above battery (not in sleep)
– VVBUS below VACOV threshold
– VVBUS above VPOORSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
Input adapter removed
USB/adapter source identified during Section 9.3.3.3.
Charge complete
Any FAULT event in REG09
VINDPM / IINDPM event detected (REG0A[1:0], maskable)
Top off timer starts and expires
•
•
•
•
•
•
REG09[7:0] and REG0A[6:4] report charger operation faults and status change to the host. When a fault/status
change occurs, the charger sends out an INT pulse and keeps the state in REG09[7:0]/REG0A[6:4] until the host
reads the registers. Before the host reads REG09[7:0]/REG0A[6:4] and all the ones are cleared, the charger
would not send any INT upon new fault/status change. To read the current status, the host has to read REG09/
REG0A two times consecutively. The first read reports the pre-existing register status and the second read
reports the current register status.
9.3.8 Protections
9.3.8.1 Voltage and Current Monitoring in Buck Mode
9.3.8.1.1 Input Overvoltage Protection (ACOV)
The input voltage is sensed via the VAC pin . The default OVP threshold is 14.2-V, and can be programmed at
5.7 V/6.4 V/11 V/14.2 V via OVP[1:0] register bits . ACOV event will immediately stop converter switching. The
device will automatically resume normal operation once the input voltage drops back below the OVP threshold.
During ACOV, REGN LDO is on, and the device does not enter HIZ mode.
During ACOV, the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host.
9.3.8.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during a load transient so that the components connected to the
system are not damaged due to high voltage. VSYS_OVP threshold is about 300-mV above battery regulation
voltage when battery charging is terminated. Upon SYSOVP, converter stops switching immediately to clamp the
overshoot. The charger pulls 30-mA ISYS_LOAD discharge current to bring down the system voltage.
9.3.8.2 Thermal Regulation and Thermal Shutdown
9.3.8.2.1 Thermal Protection in Buck Mode
Besides the battery temperature monitor on TS pin, the device monitors the internal junction temperature TJ to
avoid overheating the chip and limits the IC junction temperature in buck mode. When the internal junction
temperature exceeds thermal regulation limit (110°C), the device lowers down the charge current. During thermal
regulation, the actual charging current is usually below the programmed battery charging current. Therefore,
termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes
high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT 150°C. The BATFET and converter is enabled to recover when IC temperature is
130°C. The fault register CHRG_FAULT is set to 10 during thermal shutdown and an INT is asserted to the host.
9.3.8.3 Battery Protection
9.3.8.3.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery overvoltage
occurs, the charger device immediately stops switching. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
9.3.8.3.2 Battery Overdischarge Protection
When battery is discharged below VBAT_DPL_FALL, the BATFET will latch off to protect battery from over
discharge. To recover from overdischarge latch-off, an input source plug-in is required at VAC/VBUS.
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9.3.8.3.3 System Overcurrent Protection
ISYS_OCP_Q4 sets battery discharge current limit. Once IBAT > ISYS_OCP_Q4, charger will latch off Q4 and put the
device into Ship Mode. All methods to exit Ship mode are valid to bring the part out of Q4 latch off.
9.3.9 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG0C. Register read beyond REG0C returns
0xFF. The I2C interface supports both Standard Mode (up to 100 kbits), and Fast Mode (up to 400 kbits),
connecting to the positive supply voltage via a current source or pullup resistor. When the bus is free, both lines
are HIGH. The SDA and SCL pins are open drain.
9.3.9.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of data
allowed
Figure 9-6. Bit Transfer on the I2C Bus
9.3.9.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The
bus is considered busy after the START condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
START (S)
STOP (P)
Figure 9-7. TS START and STOP conditions
9.3.9.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
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Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
MSB
1
SDA
SCL
2
7
8
9
1
2
8
9
S or Sr
P or Sr
START or
Repeated
START
STOP or
Repeated
START
ACK
ACK
Figure 9-8. Data Transfer on the I2C Bus
9.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the master. The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
9.3.9.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
1 - 7
8
9
1-7
8
9
1-7
8
9
S
P
SCL
START
ADDRESS
R / W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 9-9. Complete Data Transfer
9.3.9.6 Single Read and Write
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
1
7
1
0
1
8
1
8
1
1
S
Slave Address
ACK
Reg Addr
ACK
Data to Addr
ACK
P
Figure 9-10. Single Write
1
7
1
1
8
1
1
7
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
Slave Addr
1
ACK
8
1
1
Data
NCK
P
Figure 9-11. Single Read
9.3.9.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG0C.
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1
7
1
0
1
8
1
S
Slave Address
ACK
Reg Addr
ACK
8
1
8
1
8
1
1
Data to Addr
ACK
Data to Addr + N
ACK
Data to Addr + N
ACK
P
Figure 9-12. Multi-Write
1
7
1
1
8
1
1
7
1
1
1
S
Slave Address
0
ACK
Reg Addr
ACK
S
Slave Address
ACK
8
1
8
1
8
1
1
Data @ Addr
ACK
Data @ Addr + 1
ACK
Data @ Addr + N NCK
P
Figure 9-13. Multi-Read
REG09[7:0]/REG0A[6:4] are fault/status change register. They keep all the fault/status information from last read
until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later,
the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the
second time. In order to get the fault information at present, the host has to read REG09/REG0A for the second
time.
9.4 Device Functional Modes
9.4.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in Default Mode without host management. In Default
Mode, the device can be used an autonomous charger with no host or while host is in Sleep Mode. When the
charger is in Default Mode, WATCHDOG_FAULT bit is HIGH. When the charger is in Host Mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in Default Mode with watchdog timer expired, or Default Mode. All the
registers are in the default settings.
In Default Mode, the device keeps charging the battery with 10-hour fast charging safety timer. At the end of the
10-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write
command to device transitions the charger from Default Mode to Host Mode. All the device parameters can be
programmed by the host. To keep the device in Host Mode, the host has to reset the watchdog timer by writing 1
to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by
setting WATCHDOG bits = 00.
All the device parameters can be programmed by the host. To keep the device in Host Mode, the host has to
reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT
bit is set), or disable watchdog timer by setting WATCHDOG bits = 00.
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POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset selective registers
Y
WD_RST bit = 1?
N
N
Y
Y
N
I2C Write?
Watchdog Timer
Expired?
Figure 9-14. Watchdog Timer Flow Chart
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9.5 Register Maps
I2C Slave Address: 6AH
Default I2C Slave Address: 0x6A (1101 010B + R/ W)
Table 9-5. I2C Registers
Address
00h
Access Type
Acronym
REG00
REG01
REG02
REG03
REG04
REG05
REG06
REG07
REG08
REG09
REG0A
REG0B
REG0C
Register Name
Section
Go
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Input Current Limit
Charger Control 0
Charge Current Limit
Precharge and Termination Current Limit
Battery Voltage Limit
Charger Control 1
Charger Control 2
Charger Control 3
Charger Status 0
01h
Go
02h
Go
03h
Go
04h
Go
05h
Go
06h
Go
07h
Go
08h
Go
09h
R
Charger Status 1
Go
0Ah
0Bh
0Ch
R
Charger Status 2
Go
R
Part Information
Go
R/W
Charger Control 4
Go
Complex bit access types are encoded to fit into small table cells. Table 9-6 shows the codes that are used for
access types in this section.
Table 9-6. I2C Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset Value
-n
Value after reset
Undefined value
-X
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9.5.1 Input Current Limit Register (Address = 00h) [reset = 17h]
Figure 9-15. REG00 Register
7
6
5
4
3
2
1
1
1
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-7. REG00 Field Descriptions
Bit
Field
POR
Type
R/W
R/W
Reset
Description
HIZ mode enable in Buck Mode.
0 – Disable (default)
1 – Enable
by REG_RST
by Watchdog
7
EN_HIZ
0
When charger does not monitor the NTC, host sets this bit to 1 to
ignore the TS pin condition during charging.
6
5
TS_IGNORE
BATSNS_DIS
0
0
by REG_RST 0 – Include TS pin into charge enable conditions. (default)
1 – Ignore TS pin. Always consider TS is good to allow charging.
NTC_FAULT bits are 000 to report normal status.
R/W
This bit describes BATSNS pin detection status.
0 – BATSNS detected, charge voltage is regulated through
BATSNS pin (default)
by REG_RST 1 – BATSNS not detected, charge voltage is regulated through
BAT pin and not BATSNS pin.
When battery voltage rises above VBAT_DPLZ, host can set
BATSNS_DIS = 0 to initiate BATSNS detection
4
3
2
1
IINDPM[4]
IINDPM[3]
IINDPM[2]
IINDPM[1]
1
0
1
1
R/W
R/W
R/W
R/W
by REG_RST 1600 mA
by REG_RST 800 mA
by REG_RST 400 mA
by REG_RST 200 mA
Input current limit setting (maximum limit, not
typical)
Offset: 100 mA
Range: 100 mA (000000) – 3.2 A (11111)
Default: 2400 mA (10111)
IINDPM bits are changed automatically after
Section 9.3.3.3 is completed
PSEL HIGH = 500 mA
0
IINDPM[0]
1
R/W
by REG_RST 100 mA
PSEL LOW = 2.4 A
Host can reprogram IINDPM register bits after
input source detection is completed.
LEGEND: R/W = Read/Write; R = Read only
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9.5.2 Charger Control 0 Register (Address = 01h) [reset = 1Ah]
Figure 9-16. REG01 Register
7
6
5
4
3
2
0
1
1
0
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-8. REG01 Field Descriptions
Bit Field
POR Type Reset
Description
R/W
PFM disable in buck mode.
by REG_RST 0 – PFM enable (default)
1 – PFM disable
7
PFM_DIS
0
R/W
I2C Watchdog timer reset. Back to 0 after watchdog timer reset
0 – Normal (default)
1 – Reset
by REG_RST
by Watchdog
6
5
WD_RST
Reserved
0
0
R/W
R/W
Battery charging buck mode enable. Charging is enabled when CE pin
by REG_RST is pulled low, CHG_CONFIG bit is 1 and charge current is not zero.
by Watchdog 0 – Charge Disable
4
CHG_CONFIG
1
1 – Charge Enable (default)
3
2
SYS_MIN[2]
SYS_MIN[1]
1
0
R/W by REG_RST System minimum voltage setting.
000 – 2.6 V
R/W by REG_RST
001 – 2.8 V
R/W
010 – 3 V
011 – 3.2 V
100 – 3.4 V
101 – 3.5 V (default)
110 – 3.6 V
1
0
SYS_MIN[0]
Reserved
1
0
by REG_RST
111 – 3.7 V
R/W
LEGEND: R/W = Read/Write; R = Read only
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9.5.3 Charge Current Limit Register (Address = 02h) [reset = 91h]
Figure 9-17. REG02 Register
7
6
5
4
3
2
0
1
0
0
1
1
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-9. REG02 Field Descriptions
Bit
Field
POR
Type
R/W
R/W
Reset
Description
7
Reserved
1
In buck mode, charger will fully turn on Q1 RBFET according
to this bit setting when IINDPM is below 700 mA. When
IINDPM is over 700 mA, Q1 is always fully on.
0 – Partially turn on Q1 for better regulation accuracy when
IINDPM is below 700 mA. (default)
6
Q1_FULLON
0
by REG_RST
1 – Fully turn on Q1 for better efficiency when IINDPM is below
700 mA.
R/W
R/W
by REG_RST
by Watchdog
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
0
1
0
0
0
1
640 mA
Fast charge current setting
by REG_RST
by Watchdog
320 mA
160 mA
80 mA
40 mA
20 mA
Default: 340 mA (010001)
Range: 0 mA (0000001) –
1180 mA (111011), 20 mA/
step
111100: 1290 mA
111101: 1360 mA
111100: 1430 mA
111100: 1500 mA
ICHG 0 mA disables charge.
by REG_RST
by Watchdog
R/W
R/W
by REG_RST
by Watchdog
R/W
R/W
by REG_RST
by Watchdog
by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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9.5.4 Precharge and Termination Current Limit Register (Address = 03h) [reset = 12h]
Figure 9-18. REG03 Register
7
6
5
4
3
2
1
1
0
0
0
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-10. REG03 Field Descriptions
Bit Field
POR Type Reset
Description
by REG_RST
by Watchdog
7
6
5
4
3
2
1
0
IPRECHG[3]
0
0
0
1
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
160 mA
Precharge current setting
Default: 40 mA (0001)
Range: 20 mA (0000) – 260 mA
(1100)
Offset: 20 mA
Note: IPRECHG > 260 mA is
clamped to 260 mA (1100)
by REG_RST
by Watchdog
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
80 mA
40 mA
20 mA
160 mA
80 mA
40 mA
20 mA
by REG_RST
by Watchdog
by REG_RST
by Watchdog
by REG_RST
by Watchdog
Termination current setting
Default: 60 mA (0010)
Range: 20 mA – 260 mA (1100)
Offset: 20 mA
Note: ITERM > 260 mA is clamped
to 260 mA (1100)
by REG_RST
by Watchdog
ITERM[2]
by REG_RST
by Watchdog
ITERM[1]
by REG_RST
by Watchdog
ITERM[0]
LEGEND: R/W = Read/Write; R = Read only
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9.5.5 Battery Voltage Limit Register (Address = 04h) [reset = 40h]
Figure 9-19. REG04 Register
7
6
5
4
3
2
0
1
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-11. REG04 Field Descriptions
Bit Field
POR Type Reset
Description
by REG_RST Battery voltage setting, also called VREG
by Watchdog Default: 4.200 V (01000)
.
7
6
5
4
VBATREG[4]
0
1
0
0
R/W
R/W
R/W
R/W
00000 – 3.504 V
00001 – 3.600 V
00010 – 3.696 V
by REG_RST
by Watchdog
VBATREG[3]
VBATREG[2]
VBATREG[1]
by REG_RST
by Watchdog
00011 – 3.800 V
00100 – 3.904 V
00101 – 4.000 V
00110 – 4.100 V
00111 – 4.150 V
01000 – 4.200 V
by REG_RST
by Watchdog
by REG_RST
by Watchdog
3
VBATREG[0]
0
R/W
01001 – 11111 – 4.300 V - 4.520 V, 10 mV/step
01110 4.350 V, 10011 4.400 V, 11000 4.450 V, 11101 4.500 V
by REG_RST Top-off timer setting.
by Watchdog 00 – Disabled (Default)
01 – 15 minutes
2
1
TOPOFF_TIMER[1]
TOPOFF_TIMER[0]
0
0
R/W
R/W
by REG_RST
10 – 30 minutes
by Watchdog
11 – 45 minutes
by REG_RST Battery recharge threshold setting.
0
VRECHG
0
R/W by Watchdog 0 – 120 mV (default)
1 – 210 mV
LEGEND: R/W = Read/Write; R = Read only
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9.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Eh]
Figure 9-20. REG05 Register
7
6
5
4
3
2
1
1
1
0
0
1
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-12. REG05 Field Descriptions
Bit
Field
POR
Type
Reset
Description
Battery charging termination enable.
0 – Disable
1 – Enable (default)
by REG_RST
by Watchdog
7
EN_TERM
1
R/W
by REG_RST
by Watchdog
6
5
Reserved
0
0
R/W
R/W
Reserved
by REG_RST Watchdog timer setting.
by Watchdog 00 – Disable timer
01 – 40 s (default)
by REG_RST
10 – 80 s
by Watchdog
11 – 160 s
WATCHDOG[1]
4
3
WATCHDOG[0]
EN_TIMER
1
1
R/W
R/W
Battery charging safety timer enable, including both fast
charge and precharge timers. Precharge timer is 2 hours.
Fast charge timer is set by REG05[2]
0 – Disable
by REG_RST
by Watchdog
1 – Enable timer (default)
Battery fast charging safety timer setting.
0 – 20 hrs
1 – 10 hrs (default)
by REG_RST
by Watchdog
2
1
CHG_TIMER
TREG
1
1
R/W
R/W
Thermal Regulation Threshold:
0 – 90°C
1 – 110°C (default)
by REG_RST
by Watchdog
Battery voltage setting during JEITA warm (T3 – T5,
by REG_RST typically 45C – 60C)
by Watchdog 0 – Set Charge Voltage to 4.1 V (max) (default)
1 – Set Charge Voltage to VREG
0
JEITA_VSET (45C-60C)
0
R/W
LEGEND: R/W = Read/Write; R = Read only
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9.5.7 Charger Control 2 Register (Address = 06h) [reset = E6h]
Figure 9-21. REG06 Register
7
6
5
4
3
2
1
1
1
0
0
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-13. REG06 Field Descriptions
Bit Field
POR Type Reset
Description
7
OVP[1]
1
R/W by REG_RST VACOV threshold during Buck Mode.
00 – 5.85 V
01 – 6.4 V (5-V input)
10 – 11 V (9-V input)
6
OVP[0]
1
R/W by REG_RST
11 – 14.2 V (12-V input) (default)
R/W
5
4
3
2
1
0
Reserved
1
0
0
1
1
0
Reserved
R/W
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
R/W by REG_RST 800 mV
R/W by REG_RST 400 mV
R/W by REG_RST 200 mV
R/W by REG_RST 100 mV
VINDPM threshold setting
Default: 4.5 V (0110)
Range: 3.9 V (0000) – 5.4 V (1111)
Offset: 3.9 V
LEGEND: R/W = Read/Write; R = Read only
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9.5.8 Charger Control 3 Register (Address = 07h) [reset = 4Ch]
Figure 9-22. REG07 Register
7
6
5
4
3
2
1
1
0
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-14. REG07 Field Descriptions
Bit Field
POR Type Reset
Description
Force input source type detection. After the detection is complete, this
by REG_RST bit returns to 0.
7
6
IINDET_EN
0
1
R/W
R/W
by Watchdog 0 – Not in input current limit detection. (default)
1 – Force input current limit detection when adapter is present.
Safety timer is slowed by 2X during input DPM, JEITA cool/warm or
thermal regulation.
by REG_RST
TMR2X_EN
0 – Disable. Safety timer duration is set by REG05[2].
by Watchdog
1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA
cool/warm (except ICHG=100%), or thermal regulation. (default)
BATFET Q4 ON/OFF control. Set this bit to 1 to enter Ship Mode. To
reset the device with adapter present, the host shall set
5
4
3
BATFET_DIS
0
0
1
R/W by REG_RST BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.
0 – Turn on Q4. (default)
1 – Turn off Q4 after tBATFET_DLY delay time (REG07[3])
Start BATFET full system reset with or without adapter present.
0 – Start BATFET full system reset after adapter is removed from
BATFET_RST_WVBUS
BATFET_DLY
R/W by REG_RST
VBUS. (default)
1 – Start BATFET full system reset when adapter is present on VBUS.
Delay from BATFET_DIS (REG07[5]) set to 1 to BATFET turn off during
Ship Mode.
R/W by REG_RST 0 – Turn off BATFET immediately when BATFET_DIS bit is set.
1 – Turn off BATFET after tBATFET_DLY (typ 10 s) when BATFET_DIS bit
is set. (default)
Enable BATFET full system reset. The time to start of BATFET full
by REG_RST system reset is based on the setting of BATFET_RST_WVBUS bit.
by Watchdog 0 – Disable BATFET reset function
2
1
BATFET_RST_EN
1
0
R/W
1 – Enable BATFET reset function when REG07[5] is also 1. (default)
VINDPM_BAT_TRACK[1]
R/W by REG_RST Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register
value and VBAT + VINDPM_BAT_TRACK.
00 – Disable function (VINDPM set by register) (default)
01 – VBAT + 200 mV
10 – VBAT + 250 mV
11 – VBAT + 300 mV
0
VINDPM_BAT_TRACK[0]
0
R/W by REG_RST
LEGEND: R/W = Read/Write; R = Read only
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9.5.9 Charger Status 0 Register (Address = 08h)
Figure 9-23. REG08
7
x
6
x
5
x
4
3
2
x
1
x
0
x
x
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-15. REG08 Field Descriptions
Bit Field
POR Type
Reset
Description
7
6
VBUS_STAT[2]
x
x
R
R
NA
VBUS Status register
000 – No input
001 – USB Host SDP (500 mA) → PSEL pin HIGH
011 – Adapter 2.4 A → PSEL pin LOW
VBUS_STAT[1]
VBUS_STAT[0]
CHRG_STAT[1]
NA
5
4
x
x
R
R
NA
NA
Software current limit is reported in IINDPM register
Charging status:
00 – Not Charging
01 – Precharge or trickle charge (< VBATLOWV
10 – Fast Charging
11 – Charge Termination
)
3
2
CHRG_STAT[0]
PG_STAT
x
x
R
R
NA
NA
Power Good status (BQ25619E only):
0 – Power Not Good
1 – Power Good
0 – Not in thermal regulation
1 – In thermal regulation
1
0
THERM_STAT
VSYS_STAT
x
x
R
R
NA
NA
0 – Not in SYS_MIN regulation (VBAT > VSYS_MIN
1 – In SYS_MIN regulation (VBAT < VSYS_MIN
)
)
LEGEND: R/W = Read/Write; R = Read only
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9.5.10 Charger Status 1 Register (Address = 09h)
Figure 9-24. REG09 Register
7
1
6
x
5
x
4
3
2
x
1
x
0
x
x
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-16. REG09 Field Descriptions
Bit Field
POR Type Reset
Description
0 – Normal, device is in Host Mode,
1 – Watchdog timer expiration, device is in Default Mode.
7
WATCHDOG_FAULT
1
R
NA
6
5
Reserved
x
x
R
R
NA
NA
CHRG_FAULT[1]
00 – Normal
01 – Input fault
10 – Thermal shutdown
11 – Charge safety timer expiration
4
3
CHRG_FAULT[0]
BAT_FAULT
x
x
R
R
NA
NA
0 – Normal,
1 – Battery overvoltage.
2
1
NTC_FAULT[2]
NTC_FAULT[1]
x
x
R
R
NA
NA
TS fault in Buck Mode
000 – Normal
010 – Warm
011 – Cool
0
NTC_FAULT[0]
x
R
NA
101 – Cold
110 – Hot
LEGEND: R/W = Read/Write; R = Read only
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9.5.11 Charger Status 2 Register (Address = 0Ah)
Figure 9-25. REG0A Register
7
x
6
x
5
x
4
3
2
x
1
0
0
0
x
x
R
R
R
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-17. REG0A Field Descriptions
Bit Field
POR Type Reset
Description
0 – VBUS does not pass poor source detection
1 – VBUS passes poor source detection
7
6
VBUS_GD
x
x
R
R
NA
NA
0 – Not in VINDPM
1 – In VINDPM
VINDPM_STAT
0 – Not in IINDPM
1 – In IINDPM
5
4
3
IINDPM_STAT
Reserved
x
x
x
R
R
R
NA
NA
NA
0 – Top off timer not counting.
1 – Top off timer counting
TOPOFF_ACTIVE
0 – Not in ACOV
1 – In ACOV
2
1
ACOV_STAT
x
R
NA
Allow or block INT pulse assertion to host during VINDPM.
R/W by REG_RST 0 – INT is asserted to host during VINDPM (default)
1 – No INT pulse asserted to host during VINDPM
VINDPM_INT_ MASK
0
Allow or block INT pulse assertion to host during IINDPM
R/W by REG_RST 0 – INT is asserted to host during IINDPM (default)
1 – No INT pulse asserted to host during IINDPM
0
IINDPM_INT_ MASK
0
LEGEND: R/W = Read/Write; R = Read only
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9.5.12 Part Information Register (Address = 0Bh)
Figure 9-26. REG0B Register
7
0
6
0
5
1
4
3
2
1
1
0
0
0
0
1
R/W
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-18. REG0B Field Descriptions
Bit Field
POR Type Reset
Description
Register reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer. This bit returns
to 0 after register reset is completed.
7
REG_RST
0
R/W NA
6
5
4
3
2
PN[3]
1
0
0
0
1
R
R
R
R
R
NA
NA
NA
NA
NA
PN[2]
DEVICE_ID
PN[1]
PN[0]
Reserved
Reserved
Reserved
1
0
0
0
R
R
NA
NA
Reserved
Reserved
LEGEND: R/W = Read/Write; R = Read only
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9.5.13 Charger Control 4 Register (Address = 0Ch) [reset = 75h]
Figure 9-27. REG0C
7
6
5
4
3
2
1
1
0
0
1
0
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-19. REG0C Field Descriptions
Bit Field
POR Type Reset
Description
by REG_RST Fast charge current setting during cool temperature range (T1 - T2), as
by Watchdog percentage of ICHG in REG02[5:0].
00 – No Charge
7
6
5
4
JEITA_COOL_ISET [1]
0
1
1
1
R/W
R/W
R/W
R/W
01 – 20% of ICHG (default)
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X)
by REG_RST
by Watchdog
JEITA_COOL_ISET [0]
JEITA_WARM_ISET [1]
JEITA_WARM_ISET [0]
by REG_RST Fast charge current setting during warm temperature range (T3 – T5),
by Watchdog as percentage of ICHG in REG02[5:0].
00 – No Charge
01 – 20% of ICHG
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X) (default)
by REG_RST
by Watchdog
by REG_RST
by Watchdog
00 – VT2% = 70.75% (5.5°C)
01 – VT2% = 68.25% (10°C) (default)
10 – VT2% = 65.25% (15°C)
11 – VT2% = 62.25% (20°C)
3
2
1
0
JEITA_VT2 [1]
JEITA_VT2 [0]
JEITA_VT3 [1]
JEITA_VT3 [0]
0
1
0
1
R/W
R/W
R/W
R/W
by REG_RST
by Watchdog
by REG_RST
by Watchdog
00 – VT3% = 48.25% (40°C)
01 – VT3% = 44.75% (44.5°C) (default)
10 – VT3% = 40.75% (50.5°C)
11 – VT3% = 37.75% (54.5°C)
by REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and
a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET,
Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
10.2 Typical Application
INPUT
4 Vœ 13.5 V
Max 22 V
SYSTEM
3.5 V - 4.52 V
VAC
1µH
VBUS
SW
1 µF
Q1
Q2
10 µF
BTST
47 nF
Q3
REGN
PMID
4.7 µF
10 µF
SYS
PGND
SYS
Q4
STAT
VREF
BAT
10 µF
BATSNS
SDA
SCL
/INT
/CE
REGN
Host
TS
+
Optional if
TS_IGNORE=1
/QON
USB
PHY
PSEL
BQ25618E
Optional
Figure 10-1. BQ25618E Application Diagram
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INPUT
4 Vœ 13.5 V
Max 22 V
SYSTEM
3.5 V - 4.52 V
VAC
1µH
VBUS
SW
1 µF
Q1
Q2
10 µF
BTST
47 nF
Q3
REGN
PMID
4.7 µF
10 µF
SYS
PGND
SYS
REGN
Q4
STAT
/PG
VREF
BAT
10 µF
BATSNS
SDA
SCL
/INT
/CE
REGN
Host
TS
+
Optional if
TS_IGNORE=1
/QON
USB
PHY
PSEL
BQ25619E
Optional
Figure 10-2. BQ25619E Application Diagram
See the BQ25618 BMS024 Evaluation Module EVM User's Guide and BQ25619 BMS025 Evaluation Module
EVM User's Guide for complete schematic and component placement with trace and via locations.
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10.2.1 Design Requirements
For this design example, use the parameters shown in the table below.
Table 10-1. Design Parameters
PARAMETER
VALUE
4 V to 13.5 V
2.4 A
VVBUS voltage range
Input current limit (REG00[4:0])
Fast charge current limit (REG02[5:0])
Minimum system voltage (REG01[3:1])
Battery regulation voltage (REG04[7:3] )
1.024 A
3.5 V
4.2 V
10.2.2 Detailed Design Procedure
10.2.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ≥ ICHG + (1/2) IRIPPLE
(3)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(4)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually
inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
10.2.2.2 Input Capacitor and Resistor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest
to 50% and can be estimated using Equation 5.
ICIN = ICHG ´ D ´ (1- D)
(5)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher capacitor is
preferred for 12-V input voltage. Capacitance of minimum 10 μF is suggested for typical of 1.5-A charging
current.
10.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
Equation 6 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(6)
The output capacitor voltage ripple can be calculated as follows:
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æ
ç
è
ö
VOUT
8LCfs2
VOUT
V
DVO =
1-
÷
IN ø
(7)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for >10-μF ceramic output capacitance. The
preferred ceramic capacitor is 10-V rating, X7R or X5R.
10.2.3 Application Curves
VVBUS = 5 V
VBAT = 3.2 V
ICHG = 1.5 A
VVBUS = 5 V
VBAT = 3.2 V
Figure 10-3. Power Up with Charge Disabled
Figure 10-4. Power Up with Charge Enabled
ISYS = 0 - 2 A
ICHG = 1.5 A
VVBUS = 5 V
VBAT = 3.7 V
IINDPM = 1 A
ISYS = 0 – 2 A
ICHG = 1 A
VVBUS = 5 V
VBAT = 3.7 V
IINDPM = 2 A
Figure 10-5. System Load Transient Response
Figure 10-6. System Load Transient Respose
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ISYS = 0 – 4 A
ICHG = 1.5 A
VVBUS = 5 V
VBAT = 3.7 V
IINDPM = 1 A
ISYS = 0 – 4 A VVBUS
=
IINDPM
= 2 A
5 V
ICHG = 1.5 A VBAT
=
3.7 V
Figure 10-7. System Load Transient Response
Figure 10-8. System Load Transient Response
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11 Power Supply Recommendations
In order to provide an output voltage on SYS, the battery charger requires a power supply between 4-V and
13.5-V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with battery
voltage greater than VBAT_UVLOZ connected to BAT. The source current rating needs to be at least 3 A in order for
the buck converter of the charger to provide maximum output power to SYS.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane. Add 1-nF small size (such as 0402 or 0201) decoupling cap for high
frequency noise filter and EMI improvement.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC ground
with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
See the BQ25618 BMS024 Evaluation Module EVM User's Guide and BQ25619 BMS025 Evaluation Module
EVM User's Guide for the recommended component placement with trace and via locations. For the VQFN
information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB
Attachment Application Report.
12.2 Layout Example
+
+
œ
Figure 12-1. High Frequency Current Path
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Figure 12-2. Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
BQ25619 BMS025 Evaluation Module User's Guide
BQ25618 BMS024 Evaluation Module User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25618EYFFR
BQ25619ERTWR
ACTIVE
ACTIVE
DSBGA
WQFN
YFF
30
24
3000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ25618E
RTW
NIPDAU
BQ
25619E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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2-Apr-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25618EYFFR
BQ25619ERTWR
DSBGA
WQFN
YFF
30
24
3000
3000
180.0
330.0
8.4
2.09
4.25
2.59
4.25
0.78
1.15
4.0
8.0
8.0
Q1
Q2
RTW
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25618EYFFR
BQ25619ERTWR
DSBGA
WQFN
YFF
30
24
3000
3000
182.0
367.0
182.0
367.0
20.0
35.0
RTW
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0030
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
F
E
D: Max = 2.392 mm, Min =2.332 mm
E: Max = 1.992 mm, Min =1.931 mm
D
C
SYMM
2
TYP
B
A
0.4 TYP
1
2
4
5
3
0.3
30X
0.4 TYP
0.2
0.015
C A B
4219433/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
30X ( 0.23)
(0.4) TYP
2
4
5
1
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219433/A 03/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
30X ( 0.25)
(R0.05) TYP
1
3
2
4
5
A
B
(0.4)
TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219433/A 03/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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