BQ25622 [TI]
具有 18V 最大输入、电流限制、ADC 和 OTG 的 I²C 控制型单节 3.5A 降压电池充电器;
| 型号： | BQ25622 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 18V 最大输入、电流限制、ADC 和 OTG 的 I²C 控制型单节 3.5A 降压电池充电器 电池 |
| 文件： | 总84页 (文件大小：3764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25620, BQ25622
SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
BQ25620/BQ25622 I2C Controlled, 3.5-A, Maximum 18-V Input, Charger with NVDC
Power Path Management and OTG Output
•
•
IP Camera, EPOS
Portable Medical Equipment
1 Features
•
High-efficiency, 1.5-MHz, synchronous switching
mode buck charger for single cell battery
– >90% efficiency down to 25-mA output current
from 5-V input
– Charge termination from 10 mA to 620 mA, 10-
mA steps
– Flexible JEITA profile for safe charging over
temperature
BATFET control to support shutdown, ship mode
and full system reset
– 1.5-μA quiescent current in battery only mode
– 0.15-μA battery leakage current in ship mode
– 0.1-μA battery leakage current in shutdown
Supports USB On-The-Go (OTG)
– Boost mode operation supporting 3.84-V to 9.6-
V output
– >90% boost efficiency down to 100-mA OTG
current for 5-V VBUS
Supports a wide range of input sources
3 Description
The BQ25620 and BQ25622 are highly-integrated
3.5-A switch-mode battery charge management and
system power path management devices for single
cell Li-Ion and Li-polymer batteries. The solution is
highly integrated with built-in current sensing, loop
compensation, input reverse-blocking FET (RBFET,
Q1), high-side switching FET (HSFET, Q2), low-
side switching FET (LSFET, Q3), and battery FET
(BATFET, Q4) between system and battery. The
devices use narrow VDC power path management,
regulating the system slightly above the battery
•
•
•
voltage without dropping below
a
configurable
minimum system voltage. The low impedance power
path optimizes switch-mode operation efficiency,
reduces battery charging time, extends battery life
during discharging phase, and the ultra-low 0.15-μA
ship mode current extends battery shelf life. The I2C
serial interface with charging and system settings
makes the BQ25620 and BQ25622 truly flexible
solutions.
– 3.9-V to 18-V wide input operating voltage
range with 26-V absolute maximum input
voltage
– Maximizes source power with input voltage
regulation (VINDPM) and input current
regulation (IINDPM)
– VINDPM threshold automatically tracks battery
voltage
Device Information
PART NUMBER
BQ25620
BQ25622
PACKAGE(1)
BODY SIZE (NOM)
2.50 mm × 3.00 mm
2.50 mm × 3.00 mm
WQFN (18)
WQFN (18)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
Efficient battery operation with 15-mΩ BATFET
Narrow VDC (NVDC) power path management
System
1 uH
– System instant-on with depleted or no battery
– Battery supplement when adapter is fully
loaded
Load
3.4 - 18V
VBUS
SW
USB
Detection
USB
D+/D- (620)
•
•
Flexible autonomous or I2C-controlled modes
Integrated 12-bit ADC for voltage, current,
temperature monitoring
BTST
SYS
TS_BIAS (622)
ILIM (622)
2.6 – 4.85V
REGN (620)
TS_BIAS (622)
REGN
•
High accuracy
I2C Bus
PG
BQ25620
BQ25622
– ±0.5% charge voltage regulation
– ±5% charge current regulation
– ±5% input current regulation
Safety
Host
CE
TS
BAT
•
1.8 – 4.8V
QON
– Thermal regulation and thermal shutdown
– Input, system, battery overvoltage protection
– Battery, converter overcurrent protection
– Charging safety timer
GND
Optional
2 Applications
BQ25620/2 Simplified Application Diagram
•
•
Tablet
Gaming and Computer Accessories
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25620, BQ25622
SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison.........................................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................16
8.7 Typical Characteristics..............................................18
9 Detailed Description......................................................20
9.1 Overview...................................................................20
9.2 Functional Block Diagram.........................................21
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................33
9.5 Programming............................................................ 35
9.6 Register Maps...........................................................38
10 Application and Implementation................................65
10.1 Application Information........................................... 65
10.2 Typical Application.................................................. 65
11 Power Supply Recommendations..............................71
12 Layout...........................................................................72
12.1 Layout Guidelines................................................... 72
12.2 Layout Example...................................................... 72
13 Device and Documentation Support..........................75
13.1 Device Support....................................................... 75
13.2 Documentation Support.......................................... 75
13.3 Receiving Notification of Documentation Updates..75
13.4 Support Resources................................................. 75
13.5 Trademarks.............................................................75
13.6 Electrostatic Discharge Caution..............................75
13.7 Glossary..................................................................75
14 Mechanical, Packaging, and Orderable
Information.................................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2022) to Revision A (October 2022)
Page
•
Changed BQ25622 from Preview to Production Data........................................................................................ 1
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5 Description (continued)
The BQ25620 supports a wide range of input sources, including standard USB host port, USB charging port,
and USB compliant high voltage adapter. It sets the default input current limit based on the built-in D+/D- USB
adapter detection interface. BQ25622 has an ILIM pin to set the default input current limit and a TS_BIAS
pin for controlled thermistor bias. The device is compliant with USB 2.0 and USB 3.0 power specifications for
input current and voltage regulation and meets USB On-the-Go (OTG) operation power rating specification with
constant current limit up to 3.2 A.
The power path management regulates the system slightly above battery voltage but does not drop below
the programmable minimum system voltage. With this feature, the system maintains operation even when the
battery is completely depleted or removed. When the input current limit or input voltage limit is reached, the
power path management automatically reduces the charge current. As the system load continues to increase,
the battery starts to discharge until the system power requirement is met. This supplement mode prevents
overloading the input source.
The BQ25620 and BQ25622 initiate and complete a charging cycle without host control. By sensing the battery
voltage, it charges the battery in four different phases: trickle charge, pre-charge, constant current (CC) charge,
and constant voltage (CV) charge. At the end of the charging cycle, the charger automatically terminates when
the charge current is below a preset threshold and the battery voltage is higher than the recharge threshold.
Termination is supported for all TS pin temperature zones.
The BQ25620 and BQ25622 provide various safety features for battery charging and system operations,
including battery negative temperature coefficient thermistor monitoring, charging safety timer, and overvoltage
and overcurrent protections. The thermal regulation reduces charge current when the junction temperature
exceeds the programmable threshold. The STAT output reports the charging status and any fault conditions.
Other safety features include battery temperature sensing for charge mode and OTG boost mode, thermal
shutdown and input UVLO and overvoltage protection. The PG output indicates if a good power source is
present. The INT output notifies the host when a fault occurs or status changes.
The BQ25620 and BQ25622 are available in a 18-pin, 2.5 mm × 3.0 mm WQFN package.
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SLUSEG2A – SEPTEMBER 2022 – REVISED OCTOBER 2022
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6 Device Comparison
Table 6-1. Device Comparison
FUNCTION
BQ25611D
4V - 13.5V
I2C
BQ25616
4V - 13.5V
Standalone
BQ25620
3.9V - 18V
I2C
BQ25622
Input Voltage Range
Part Configuration
3.9V - 18V
I2C
3.5 - 4.3V (100mV per
step); 4.3 - 4.52V (10mV
per step)
Programmable Charge
Voltage
4.1V / 4.2V / 4.35V
3.5 - 4.8V (10mV per step) 3.5 - 4.8V (10mV per step)
D+/D- USB Detection
ILIM Pin
Yes
Yes
Yes
Yes
No
Yes
No
JEITA
No
JEITA
TS Profile
HOT/COLD
9.5μA
JEITA
Quiescent Battery Current
OTG
9.5μA
1.5μA
1.5μA
Yes
Yes
Yes
Yes
OTG Current Limit
ADC
1.2A
1.2A
3.2A
3.2A
None
None
12-bit ADC
2.5x3mm2 QFN (18)
12-bit ADC
2.5x3mm2 QFN (18)
Package
4x4mm2 QFN (24)
4x4mm2 QFN (24)
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7 Pin Configuration and Functions
14
CE
1
BTST
REGN
PG
2
3
4
13
12
11
SCL
BQ25620
RYK
2.5mm x 3mm
SDA
INT
D-
D+
5
10
STAT
Figure 7-1. BQ25620 Pinout, 18-Pin WQFN Top View
14
1
BTST
CE
REGN
PG
2
3
4
13
12
11
SCL
SDA
INT
BQ25622
RYK
2.5mm x 3mm
ILIM
TS_BIAS
5
10
STAT
Figure 7-2. BQ25622 Pinout, 18-Pin WQFN Top View
Table 7-1. Pin Functions
NAME
NO.
TYPE(1)
DESCRIPTION
BQ25622
BQ25620
High Side Switching MOSFET Gate Driver Power Supply – Connect a 10V or higher
rating, 47nF ceramic capacitor between SW and BTST as the bootstrap capacitor for driving
high side switching MOSFET (Q2).
BTST
1
P
The Charger Internal Linear Regulator Output – Internally, REGN is connected to the
anode of the boost-strap diode. Connect a 10V or higher rating, 4.7μF ceramic capacitor
from REGN to power ground, The capacitor should be placed close to the IC. The REGN
LDO output is used for the internal MOSFETs gate driving voltage and for biasing the
external TS pin thermistor in BQ25620.
REGN
2
P
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Table 7-1. Pin Functions (continued)
NAME
NO.
TYPE(1)
DESCRIPTION
BQ25622
BQ25620
Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10kΩ
resistor. LOW indicates an input source of VVBUS_UVLO < VBUS < VVBUS_OVP. Failing poor
source detection or triggering the sleep comparator ( VBUS < VBAT + VSLEEP ) also causes
PG to transition HIGH.
PG
3
DO
Input Current Limit Setting Input Pin – ILIM pin sets the input current limit as IINREG
=
KILIM / RILIM, where RILIM is connected from ILIM pin to GND. The input current is limited to
the lower of the two values set by ILIM pin and IINDPM register bits. The ILIM pin can also
be used to monitor input current. The input current is proportional to the voltage on ILIM pin
and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8). The ILIM pin function is disabled
when EN_EXTILIM bit is set to 0.
ILIM
D-
4
5
AIO
Negative Line of the USB Data Line Pair – D+/D- based USB host/charging port detection.
The detection includes data contact detection (DCD), primary and secondary detection in
BC1.2.
Bias for the TS Resistor Voltage Divider – Provides the bias voltage for the TS resistor
voltage divider.
P
TS_BIAS
D+
Positive Line of the USB Data Line Pair – D+/D- based USB host/charging port detection.
The detection includes data contact detection (DCD), primary and secondary detection in
BC1.2.
AIO
Temperature Qualification Voltage Input – Connect a negative temperature coefficient
thermistor. Program temperature window with a resistor divider from TS pin bias reference
(REGN in BQ25620, TS_BIAS in BQ25622) to TS, then to GND. Charge suspends when TS
pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor.
TS
6
7
AI
DI
BATFET Enable or System Power Reset Control Input – If the charger is in ship mode, a
logic low on this pin with tSM_EXIT duration forces the device to exit ship mode. If the charger
is not in ship mode, a logic low on this pin with tRST initiates a full system power reset if either
VVBUS < VVBUS_UVLO or BATFET_CTRL_WVBUS = 1. QON has no effect during shutdown
mode. The pin contains an internal pull-up to maintain default high logic.
QON
The Battery Charging Power Connection – Connect to the positive terminal of the battery
pack. The internal BATFET is connected between SYS and BAT.
BAT
SYS
8
9
P
P
The Charger Output Voltage to System –The Buck converter output connection point to
the system. The internal BATFET is connected between SYS and BAT.
Open Drain Charge Status Output – It indicates various charger operations. Connect to the
pull up rail via 10kΩ resistor. LOW indicates charging in progress. HIGH indicates charging
completed or charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz.
Setting DIS_STAT = 1 disables the STAT pin function, causing the pin to be pulled HIGH.
Leave floating if unused.
STAT
INT
10
11
DO
DO
Open Drain Interrupt Output. – Connect to the pull up rail via 10kΩ resistor. The INT pin
sends an active low, 256μs pulse to the host to report the charger device status and faults.
SDA
SCL
12
13
DIO
DI
I2C Interface Data – Connect SDA to the logic rail through a 10 kΩ resistor.
I2C Interface Clock – Connect SCL to the logic rail through a 10 kΩ resistor.
Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and
CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
CE
14
15
DI
P
GND
Ground Return
Switching Node Connecting to Output Inductor – Internally SW is connected to the
source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 47 nF
bootstrap capacitor from SW to BTST.
SW
16
P
HSFET Drain Connection – Internally PMID is connected to the drain of the reverse
blocking MOSFET (RBFET) and the drain of HSFET.
PMID
VBUS
17
18
P
P
Charger Input Voltage – The internal n-channel reverse block MOSFET (RBFET) is
connected between VBUS and PMID with VBUS on source.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,
P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
26
26
6
UNIT
V
VBUS (converter not switching)
PMID (converter not switching)
BAT, SYS (converter not switching)
–0.3
V
–0.3
V
Voltage range (with
respect to GND)
SW
–2 (50ns)
–0.3
21
27
6
V
BTST (when converter switching)
CE, STAT, SCL, SDA, INT, REGN, QON
D+, D-, ILIM, PG, TS, TS_BIAS
V
–0.3
V
–0.3
6
V
Output Sink Current
Differential Voltage
INT, STAT, PG
BTST-SW
6
mA
V
–0.3
–0.3
–0.3
–40
–55
6
PMID-VBUS
6
V
SYS-BAT
6
V
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
18
UNIT
V
VVBUS
VBAT
IVBUS
ISW
Input voltage
3.9
Battery voltage
4.8
3.2
3.5
3.5
6
V
Input current
A
Output current (SW)
A
Fast charging current
A
IBAT
RMS discharge current (continuously)
Peak discharge current (up to 50ms)
Maximum REGN Current
Ambient temperature
A
10
A
IREGN
TA
20
mA
°C
°C
µH
µF
µF
µF
–40
–40
0.68
1
85
TJ
Junction temperature
125
2.2
LSW
Inductor for the switching regulator
VBUS capacitor (without de-rating)
PMID capacitor (without de-rating)
SYS capacitor (without de-rating)
CVBUS
CPMID
CSYS
10
20
500
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8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
CBAT
BAT capacitor (without de-rating)
10
µF
8.4 Thermal Information
BQ25620, BQ25622
THERMAL METRIC(1)
RYK (QFN)
18 pins
60.1
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
42.1
13.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.3
ΨJB
12.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
QUIESCENT CURRENTS
Quiescent battery current (BAT,
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT = 4V, No VBUS, BATFET is
SYS, SW) when the charger is in enabled, I2C enabled, ADC disabled,
the battery only mode, BATFET is system is powered by battery. -40 °C <
IQ_BAT
1.5
3
µA
µA
enabled, ADC is disabled
TJ < 60 °C
Quiescent battery current (BAT,
VBAT = 4V, No VBUS, BATFET is
SYS, SW) when the charger is in enabled, I2C enabled, ADC enabled,
the battery only mode, BATFET is system is powered by battery. -40 °C <
IQ_BAT_ADC
260
0.1
enabled, ADC is enabled
TJ < 60 °C
Quiescent battery current (BAT)
when the charger is in shutdown
mode, BATFET is disabled, ADC
is disabled
VBAT = 4V, No VBUS, BATFET is
disabled, I2C disabled, in shutdown
mode, ADC disabled, TJ < 60 °C
IQ_BAT_SD
0.2 µA
Quiescent battery current (BAT)
when the charger is in ship
mode, BATFET is disabled, ADC
is disabled
VBAT = 4V, No VBUS, BATFET is
disabled, I2C disabled, in ship mode,
ADC disabled, TJ < 60 °C
IQ_BAT_SHIP
0.15
450
0.5 µA
VBUS = 5V, VBAT = 4V, charge disabled,
converter switching, ISYS = 0A, PFM
enabled
IQ_VBUS
Quiescent input current (VBUS)
µA
VBUS = 5V, VBAT = 4V, HIZ mode, ADC
disabled
5
20 µA
35 µA
Quiescent input current (VBUS) in
HIZ
IQ_VBUS_HIZ
VBUS = 15V, VBAT = 4V, HIZ mode, ADC
disabled
20
VBAT = 4.2V, VBUS = 5V, OTG
mode enabled, converter switching,
PFM enabled, IVBUS = 0A, TS float,
TS_IGNORE = 1
Quiescent battery current (BAT,
SYS, SW) in boost OTG mode
IQ_OTG
250
µA
VBUS / VBAT SUPPLY
VVBUS_OP
VBUS operating range
3.9
3.0
18
V
V
VBUS falling to turn off I2C, no
battery
VVBUS_UVLO
VBUS falling
3.15
3.3
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBUS rising for active I2C, no
battery
VVBUS_UVLOZ
VBUS rising
3.2
3.35
3.5
V
VVBUS_OVP
VVBUS_OVPZ
VVBUS_OVP
VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 0
VBUS overvoltage falling hreshold VBUS rising, VBUS_OVP = 0
VBUS overvoltage rising threshold VBUS rising, VBUS_OVP = 1
6.1
5.8
6.4
6.0
6.7
6.2
V
V
V
18.2
18.5
18.8
VBUS overvoltage falling
VBUS falling, VBUS_OVP = 1
threshold
VVBUS_OVPZ
17.4
17.7
18.0
V
VSLEEP
Enter Sleep mode threshold
Exit Sleep mode threshold
(VBUS - VBAT), VBUS falling
(VBUS - VBAT), VBUS rising
9
45
85 mV
VSLEEPZ
115
220
340 mV
BAT voltage for active I2C, turn on
BATFET, no VBUS
VBAT_UVLOZ
VBAT rising
2.3
2.4
2.5
V
VBAT falling, VBAT_UVLO = 0
VBAT falling, VBAT_UVLO = 1
VBAT rising, VBAT_OTG_MIN = 0
VBAT rising, VBAT_OTG_MIN = 1
VBAT falling, VBAT_OTG_MIN = 0
VBAT falling, VBAT_OTG_MIN = 1
VBUS falling
2.1
1.7
2.9
2.5
2.7
2.3
3.6
2.2
1.8
3.0
2.6
2.8
2.4
3.7
2.3
1.9
3.1
2.7
2.9
2.5
V
V
V
V
V
V
V
BAT voltage to turnoff I2C, turn off
BATFET, no VBUS
VBAT_UVLO
BAT voltage rising threshold to
enable OTG mode
VBAT_OTG
BAT voltage falling threshold to
disable OTG mode
VBAT_OTGZ
VPOORSRC
IPOORSRC
Bad adapter detection threshold
Bad adapter detection current
source
10
mA
POWER-PATH MANAGEMENT
ISYS = 0A, VBAT > VSYSMIN, Charge
Disabled. Offset above VBAT
50
mV
mV
VSYS_REG_ACC
Typical system voltage regulation
ISYS = 0A, VBAT < VSYSMIN, Charge
Disabled. Offset above VSYSMIN
230
VSYSMIN_RNG
VSYSMIN register range
2.56
3.52
3.84
V
VSYSMIN_REG_STEP
VSYSMIN register step size
80
mV
Minimum DC system voltage
output
ISYS = 0A, VBAT < VSYSMIN = B00h
(3.52V), Charge Disabled
VSYSMIN_REG_ACC
VSYS_SHORT
3.75
V
V
V
VSYS short voltage falling
threshold to enter forced PFM
0.9
1.1
VSYS short voltage rising
threshold to exit forced PFM
VSYS_SHORTZ
BATTERY CHARGER
VREG_RANGE
Typical charge voltage regulation
range
3.50
4.80
V
VREG_STEP
Typical charge voltage step
Charge voltage accuracy
10
80
mV
%
TJ = 25°C
–0.3
–0.4
0.3
0.4
VREG_ACC
TJ = –10°C - 85°C
%
Typical charge current regulation
range
ICHG_RANGE
ICHG_STEP
0.08
3.52
A
mA
%
Typical charge current regulation
step
VBAT = 3.1V or 3.8V, ICHG = 1760mA, TJ
= –10°C - 85°C
–5
–5.5
–5.5
5
5.5
5.5
VBAT = 3.1V or 3.8V, ICHG = 1040mA, TJ
= –10°C - 85°C
ICHG_ACC
Charge current accuracy
%
VBAT = 3.1V or 3.8V, ICHG = 320mA, TJ
= –10°C - 85°C
%
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
620 mA
mA
IPRECHG_RANGE
IPRECHG_STEP
Typical pre-charge current range
Typical pre-charge current step
20
20
VBAT = 2.5V, IPRECHG = 500mA, TJ =
–10°C - 85°C
–12
–12
12
12
15
%
%
%
Pre-charge current accuracy when VBAT = 2.5V, IPRECHG = 200mA, TJ =
IPRECHG_ACC
VBAT below VSYSMIN setting
–10°C - 85°C
VBAT = 2.5V, IPRECHG = 100mA, TJ =
–10°C - 85°C
–15
10
ITERM_RANGE
ITERM_STEP
Typical termination current range
Typical termination current step
620 mA
mA
10
ITERM = 20mA, TJ = –10°C - 85°C
ITERM = 100mA, TJ = –10°C - 85°C
ITERM = 300mA, TJ = –10°C - 85°C
–60
–15
–13
60
15
13
%
%
%
ITERM_ACC
Termination current accuracy
Battery short voltage rising
threshold to start pre-charge
VBAT_SHORTZ
VBAT_SHORT
VBAT_SHORT
VBAT rising
2.25
2.05
1.85
V
V
V
Battery short voltage falling
threshold to stop pre-charge
VBAT falling, VBAT_UVLO=0
VBAT falling, VBAT_UVLO=1
Battery short voltage falling
threshold to stop pre-charge
VBAT < VBAT_SHORTZ, ITRICKLE = 0
VBAT < VBAT_SHORTZ, ITRICKLE = 1
Transition from pre-charge to fast charge
Transition from fast charge to pre-charge
VBAT falling, VRECHG = 0
15
62
25
82
35 mA
Battery short trickle charging
current
IBAT_SHORT
102 mA
VBAT_LOWVZ
VBAT_LOWV
Battery voltage rising threshold
Battery voltage falling threshold
2.9
2.7
3.0
2.8
100
200
30
3.1
2.9
V
V
mV
mV
mA
mA
mA
Battery recharge threshold below
VREG
VRECHG
VBAT falling, VRECHG = 1
IPMID_LOAD
IBAT_LOAD
ISYS_LOAD
BATFET
PMID discharge load current
Battery discharge load current
System discharge load current
20
20
20
30
30
MOSFET on resistance from SYS
to BAT
RBATFET
15
25 mΩ
BATTERY PROTECTIONS
Battery overvoltage rising
threshold
VBAT_OVP
As percentage of VREG
As percentage of VREG
103
101
6
104
102
105
%
%
A
Battery overvoltage falling
threshold
VBAT_OVPZ
IBATFET_OCP
103
BATFET over-current rising
threshold
IBAT_PK = 00
IBAT_PK = 01
IBAT_PK = 10
IBAT_PK = 11
1.5
3
A
A
A
A
Battery discharging peak current
rising threshold
IBAT_PK
6
12
INPUT VOLTAGE / CURRENT REGULATION
Typical input voltage regulation
range
VINDPM_RANGE
VINDPM_STEP
3.8
16.8
V
Typical input voltage regulation
step
40
mV
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VINDPM=4.6V
–4
4
3
2
%
%
%
VINDPM_ACC
Input voltage regulation accuracy VINDPM=8V
VINDPM=16V
–3
–2
VBAT = 3.9V, VINDPM_BAT_TRACK=1,
VINDPM = 4V
VINDPM_BAT_TRACK
IINDPM_RANGE
IINDPM_STEP
Battery tracking VINDPM accuracy
4.15
0.04
4.3
20
4.45
3.2
V
A
Typical input current regulation
range
Typical input current regulation
step
mA
IINDPM = 500mA, VBUS=5V
450
810
475
855
500 mA
900 mA
1500 mA
IINDPM_ACC
Input current regulation accuracy IINDPM = 900mA, VBUS=5V
IINDPM = 1500mA, VBUS=5V
1350
1425
ILIM Pin Scale Factor, IINREG =
INREG = 1.6 A
KILIM
2250
2500
2750 AΩ
KILIM / RILIM
D+ / D- DETECTION
VD+D-_0p6V_SRC
ID+D-_LKG
D+/D- voltage source (600 mV)
Leakage current into D+/D-
1 mA load on D+/D-
HiZ mode
400
–1
600
800 mV
1
µA
V
D+/D- comparator threshold for
non-standard adapter
VD+D-_2p8
VD+D-_2p0
2.55
1.85
2.85
D+/D- comparator threshold for
non-standard adapter
2.15
V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG = 1
TREG = 0
120
60
°C
°C
Junction temperature regulation
accuracy
TREG
Thermal Shutdown Rising
Threshold
TSHUT
Temperature Increasing
140
30
°C
°C
Thermal Shutdown Falling
TSHUT_HYS
Hysteresis
Temperature Decreasing by TSHUT_HYS
THERMISTOR COMPARATORS (CHARGE MODE)
As Percentage to TS pin bias reference
(-5°C w/ 103AT), TS_TH1_TH2_TH3
= 100, 101, 110
75.0
72.8
73.9
71.7
75.5
73.3
74.4
72.2
76.0
73.8
74.9
72.7
%
%
%
%
TS pin rising voltage threshold
for TH1 comparator to
transition from TS_COOL to
TS_COLD. Charge suspended
above this voltage.
VTS_COLD
As Percentage to TS pin bias reference
(0°C w/ 103AT), Fixed JEITA threshold or
TS_TH1_TH2_TH3 = 000, 001, 010, 011,
111
As Percentage to TS pin bias reference
(-2.5°C w/ 103AT), TS_TH1_TH2_TH3
= 100, 101, 110
TS pin falling voltage threshold
for TH1 comparator to
transition from TS_COLD to
TS_COOL. TS_COOL charge
settings resume below this
voltage.
VTS_COLDZ
As Percentage to TS pin bias reference
(2.5°C w/ 103AT), Fixed JEITA threshold
or TS_TH1_TH2_TH3 = 000, 001, 010,
011, 111
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
As Percentage to TS pin bias reference
(5°C w/ 103AT), TS_ISET_COOL = 00 or
TS_TH1_TH2_TH3 = 000, 100
70.6
71.1
71.6
68.9
%
%
As Percentage to TS pin bias reference
(10°C w/ 103AT), TS_ISET_COOL = 01
or TS_TH1_TH2_TH3 = 001, 101, 110,
111
TS pin rising voltage threshold
for TH2 comparator to
67.9
68.4
VTS_COOL
transition from TS_PRECOOL to
TS_COOL. TS_COOL charging
settings used above this voltage.
As Percentage to TS pin bias reference
(15°C w/ 103AT), TS_ISET_COOL = 10
or TS_TH1_TH2_TH3 = 010
65.0
61.9
69.3
65.5
62.4
69.8
66.0
62.9
70.3
%
%
%
As Percentage to TS pin bias reference
(20°C w/ 103AT), TS_ISET_COOL = 11
or TS_TH1_TH2_TH3 = 011
As Percentage to TS pin bias reference
(7.5°C w/ 103AT), TS_ISET_COOL = 00
or TS_TH1_TH2_TH3 = 000, 100
As Percentage to TS pin bias reference
(12.5°C w/ 103AT), TS_ISET_COOL = 01
or TS_TH1_TH2_TH3 = 001, 101, 110,
111
TS pin falling voltage threshold
for TH2 comparator to
transition from TS_COOL to
TS_PRECOOL. TS_PRECOOL
charging settings resume below
this voltage.
66.6
67.1
67.6
%
VTS_COOLZ
As Percentage to TS pin bias reference
(17.5°C w/ 103AT), TS_ISET_COOL = 10
or TS_TH1_TH2_TH3 = 010
63.7
60.6
65.0
61.9
63.7
60.6
51.5
47.9
53.3
49.2
64.2
61.1
65.5
62.4
64.2
61.1
52.0
48.4
53.8
49.7
64.7
61.6
66.0
62.9
64.7
61.6
52.5
48.9
54.3
50.2
%
%
%
%
%
%
%
%
%
%
As Percentage to TS pin bias reference
(22.5°C w/ 103AT), TS_ISET_COOL = 11
or TS_TH1_TH2_TH3 = 011
As Percentage to TS pin bias reference
(15°C w/ 103AT), TS_TH1_TH2_TH3 =
000, 001, 100, 101
TS pin rising voltage threshold
for TH3 comparator to
transition from TS_NORMAL to
TS_PRECOOL. TS_PRECOOL
charge settings used above this
voltage.
VTS_PRECOOL
VTS_PRECOOLZ
VTS_PREWARM
VTS_PREWARMZ
As Percentage to TS pin bias reference
(20°C w/ 103AT), TS_TH1_TH2_TH3 =
010, 011, 110, 111
As Percentage to TS pin bias reference
(17.5°C w/ 103AT), TS_TH1_TH2_TH3 =
000, 001, 100, 101
TS pin falling voltage threshold
for TH3 comparator to
transition from TS_PRECOOL to
TS_NORMAL. Normal charging
resumes below this voltage.
As Percentage to TS pin bias reference
(22.5°C w/ 103AT), TS_TH1_TH2_TH3 =
010, 011, 110, 111
As Percentage to TS pin bias reference
(35°C w/ 103AT), TS_TH4_TH5_TH6 =
000, 001, 010, 100, 101
TS pin falling voltage threshold
for TH4 comparator to
transition from TS_NORMAL to
TS_PREWARM. TS_PREWARM
charging settings used below this
voltage.
As Percentage to TS pin bias reference
(40°C w/ 103AT), TS_TH4_TH5_TH6 =
011, 110, 111
As Percentage to TS pin bias reference
(32.5°C w/ 103AT), TS_TH4_TH5_TH6 =
000, 001, 010, 100, 101
TS pin rising voltage threshold
for TH4 comparator to
transition from TS_PREWARM to
TS_NORMAL. Normal charging
resumes above this voltage.
As Percentage to TS pin bias reference
(37.5°C w/ 103AT), TS_TH4_TH5_TH6 =
011, 110, 111
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
As Percentage to TS pin bias reference
(40°C w/ 103AT), TS_ISET_WARM = 00
or TS_TH4_TH5_TH6 = 000, 100
47.9
48.4
48.9
45.3
41.7
38.2
50.2
46.6
43.0
39.5
41.7
%
%
%
%
%
%
%
%
%
As Percentage to TS pin bias reference
(45°C w/ 103AT), TS_ISET_WARM = 01
or TS_TH4_TH5_TH6 = 001, 101, 110
TS pin falling voltage threshold
for TH5 comparator to
transition from TS_PREWARM to
TS_WARM. TS_WARM charging
settings used below this voltage.
44.3
40.7
37.2
49.2
45.6
42.0
38.5
40.7
44.8
41.2
37.7
49.7
46.1
42.5
39
VTS_WARM
As Percentage to TS pin bias reference
(50°C w/ 103AT), TS_ISET_WARM = 10
or TS_TH4_TH5_TH6 = 010, 111
As Percentage to TS pin bias reference
(55°C w/ 103AT), TS_ISET_WARM = 11
or TS_TH4_TH5_TH6 = 011
As Percentage to TS pin bias reference
(37.5°C w/ 103AT), TS_ISET_WARM =
00 or TS_TH4_TH5_TH6 = 000, 100
As Percentage to TS pin bias reference
(42.5°C w/ 103AT), TS_ISET_WARM =
01 or TS_TH4_TH5_TH6 = 001, 101, 110
TS pin rising voltage threshold
for TH5 comparator to
transition from TS_WARM to
TS_PREWARM. TS_PREWARM
charging settings resume above
this voltage.
VTS_WARMZ
As Percentage to TS pin bias reference
(47.5°C w/ 103AT), TS_ISET_WARM =
10 or TS_TH4_TH5_TH6 = 010, 111
As Percentage to TS pin bias reference
(52.5°C w/ 103AT), TS_ISET_WARM =
11 or TS_TH4_TH5_TH6 = 011
As Percentage to TS pin bias reference
(50°C w/ 103AT), TS_TH4_TH5_TH6 =
100 or 101
41.2
TS pin falling voltage threshold
for TH6 comparator to
VTS_HOT
transition from TS_WARM to
TS_HOT. Charging is suspended
below this voltage.
As Percentage to TS pin bias reference
(60°C w/ 103AT), Fixed JEITA threshold
or TS_TH4_TH5_TH6 = 000, 001, 010,
011, 110 or 111
33.9
42.0
35.2
34.4
42.5
35.7
34.9
43.0
36.2
%
%
%
As Percentage to TS pin bias reference
(47.5°C w/ 103AT), TS_TH4_TH5_TH6 =
100 or 101
TS pin rising voltage threshold
for TH6 comparator to
transition from TS_HOT to
TS_WARM. TS_WARM charging
settings resume above this
voltage.
VTS_HOTZ
As Percentage to TS pin bias reference
(57.5°C w/ 103AT), Fixed JEITA threshold
or TS_TH4_TH5_TH6 = 000, 001, 010,
011, 110 or 111
THERMISTOR COMPARATORS (OTG MODE)
As Percentage to TS pin bias reference
(–20°C w/ 103AT), TS_TH_OTG_COLD =
0
TS pin rising voltage
threshold to transition
from TS_OTG_NORMAL to
TS_OTG_COLD. OTG suspended
above this voltage.
79.5
76.6
78.2
75.0
80.0
77.1
78.7
75.5
80.5
77.6
79.2
76.5
%
%
%
%
VTS_ OTG_ COLD
As Percentage to TS pin bias reference
(–10°C w/ 103AT), TS_TH_OTG_COLD =
1
As Percentage to TS pin bias reference
(–15°C w/ 103AT), TS_TH_OTG_COLD =
0
TS pin falling voltage threshold
to transition from TS_OTG_COLD
to TS_OTG_NORMAL. OTG
resumes below this voltage.
VTS_OTG_COLDZ
As Percentage to TS pin bias reference
(–5°C w/ 103AT), TS_TH_OTG_COLD =
1
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
As Percentage to TS pin
bias reference (55°C w/ 103AT),
TS_OTG_HOT = 00
37.2
37.7
38.2
%
TS pin falling voltage
threshold to transition
VTS_OTG_HOT
from TS_OTG_NORMAL to
TS_OTG_HOT. OTG suspended
below this voltage.
As Percentage to TS pin bias reference
(60°C w/ 103AT), TS_OTG_HOT = 01
33.9
30.8
38.5
34.4
31.3
39.0
34.9
31.8
39.5
%
%
%
As Percentage to TS pin bias reference
(65°C w/ 103AT), TS_OTG_HOT = 10
As Percentage to TS pin bias reference
(52.5°C w/ 103AT), TS_OTG_HOT = 00
TS pin rising voltage threshold
to transition from TS_OTG_HOT
to TS_OTG_NORMAL. OTG
resumes above this threshold.
As Percentage to TS pin bias
reference (57.5°C w/ 103AT),
TS_OTG_HOT = 01
35.2
32.0
35.7
32.5
36.2
33.0
%
%
VTS_OTG_HOTZ
As Percentage to TS pin bias
reference (62.5°C w/ 103AT),
TS_OTG_HOT = 10
SWITCHING CONVERTER
FSW
PWM switching frequency
Oscillator frequency
Tj = –40°C-85°C
1.35
1.5
1.65 MHz
MOSFET TURN-ON RESISTANCE
RQ1_ON
VBUS to PMID on resistance
26
55
34 mΩ
78 mΩ
Buck high-side switching MOSFET
turn on resistance between PMID Tj = –40°C-85°C
and SW
RQ2_ON
Buck low-side switching MOSFET
RQ3_ON
turn on resistance between SW
and PGND
Tj = –40°C-85°C
60
90 mΩ
OTG MODE CONVERTER
Typical OTG mode voltage
VOTG_RANGE
VOTG_STEP
VOTG_ACC
VOTG_ACC
IOTG_RANGE
IOTG_STEP
3.8
9.6
V
mV
%
regulation range
Typical OTG mode voltage
regulation step
80
OTG mode voltage regulation
accuracy
IVBUS = 0A, VOTG = 9V
IVBUS = 0A, VOTG = 5V
–2
–3
2
3
OTG mode voltage regulation
accuracy
%
Typical OTG mode current
regulation range
0.1
3.2
A
Typical OTG mode current
regulation step
20
mA
IOTG = 1.8A
IOTG = 1.5A
IOTG = 0.5A
–3
–5
3
5
%
%
%
OTG mode current regulation
accuracy
IOTG_ACC
–10
10
OTG mode undervoltage falling
threshold at PMID
VOTG_UVP
3.4
V
V
OTG mode overvoltage rising
threshold at VBUS
VOTG_VBUS_OVP
10.5
11.0
11.5
5.2
REGN LDO
VVBUS = 5V, IREGN = 20mA
VVBUS = 9V, IREGN = 20mA
Converter switching
4.4
4.8
4.6
5.0
3.2
2.3
V
V
VREGN
REGN LDO output voltage
V
VREGNZ_OK
IREGN_LIM
14
REGN not good falling threshold
REGN LDO current limit
Converter not switching
VVBUS = 5V, VREGN = 4.3V
V
20
mA
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Rising threshold to transition from
TSBIAS good condition to fault
condition
REGN=5V; ISINK applied on TS_BIAS
pin
ITS_BIAS_FAULT
2.5
4.5
8
7
mA
mA
Falling threshold to transition from
TSBIAS fault condition to good
condition
REGN=5V; ISINK applied on TS_BIAS
pin
ITS_BIAS_FAULTZ
2
3.85
ADC MEASUREMENT ACCURACY AND PERFORMANCE
ADC_SAMPLE = 00
24
12
6
ms
ms
ms
ms
bits
bits
bits
bits
ADC_SAMPLE = 01
ADC_SAMPLE = 10
ADC_SAMPLE = 11
ADC_SAMPLE = 00
ADC_SAMPLE = 01
ADC_SAMPLE = 10
ADC_SAMPLE = 11
Conversion-time, Each
Measurement
tADC_CONV
3
11
10
9
12
11
10
9
ADCRES
Effective Resolution
8
ADC MEASUREMENT RANGE AND LSB
ADC Bus Current Reading (both
Range
LSB
–4
0
4
19.85
19.85
5.572
5.572
4.0
A
mA
V
IBUS_ADC
VBUS_ADC
VPMID_ADC
VBAT_ADC
VSYS_ADC
IBAT_ADC
forward and OTG)
2
3.97
3.97
1.99
1.99
2
Range
LSB
ADC VBUS Voltage Reading
mV
V
Range
LSB
0
ADC PMID Voltage Reading
ADC BAT Voltage Reading
ADC SYS Voltage Reading
ADC BAT Current Reading
mV
V
Range
LSB
0
mV
V
Range
LSB
0
mV
A
Range
LSB
-7.5
mA
Range as a percent of REGN (–40 ℃ to
85 ℃ for 103AT)
ADC TS Voltage Reading
ADC TS Voltage Reading
20.9
–40
83.2
%
%
TS_ADC
LSB
0.0961
0.5
Range
LSB
150 °C
°C
TDIE_ADC
ADC Die Temperature Reading
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA
and SCL
VIH
VIL
0.78
V
Input low threshold level, SDA and
SCL
0.42
V
VOL_SDA
IBIAS
Output low threshold level
High-level leakage current
Capacitive load for each bus line
Sink current = 5mA, 1.2V VDD
Pull up rail 1.8V
0.3
1
V
µA
CBUS
400 pF
LOGIC OUTPUT PIN (INT , PG, STAT)
VOL
Output low threshold level
High-level leakage current
Sink current = 5mA
Pull up rail 1.8V
0.3
1
V
IOUT_BIAS
µA
LOGIC INPUT PIN (CE, QON)
VIH_CE
Input high threshold level, /CE
0.78
V
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8.5 Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OVP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIL_CE
Input low threshold level, /CE
High-level leakage current, /CE
Input high threshold level, /QON
Input low threshold level, /QON
Internal /QON pull up
0.4
1
V
µA
V
IIN_BIAS_CE
VIH_QON
VIL_QON
VQON
Pull up rail 1.8V
1.3
0.4
V
/QON is pulled up internally
5
V
RQON
Internal /QON pull up resistance
250
kΩ
8.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS / VBAT POWER UP
VBUS_OVP propagation delay to
tVBUS_OVP_PROP
stop converter, VBUS rising (no
deglitch)
130
200
ns
µs
VBUS OVP deglitch time
to set VBUS_OVP_STAT and
VBUS_OVP_FLAG
tVBUS_OVP
tPOORSRC
Bad adapter detection duration
30
2
ms
s
Bad adapter detection retry wait
time
tPOORSRC_RETRY
Restart the bad adapter detection
after latchoff
tPOORSRC_RESTART
15
30
min
ms
The duration of the pull down
current source applied on VBUS
tVBUS_PD
BATTERY CHARGER
tTERM_DGL
Deglitch time for charge
termination
50
ms
ms
Deglitch time for recharge
threshold at VBAT falling
tRECHG_DGL
256
12
24
36
15
30
45
18 min
36 min
54 min
tTOP_OFF
Typical top-off timer accuracy
Charge safety timer accuracy in
trickle charge
tSAFETY_TRKCHG
0.85
1
1.1 hr
PRECHG_TMR = 0
PRECHG_TMR = 1
CHG_TMR = 0
1.75
0.43
10.5
21.0
2
0.5
2.2 hr
0.55 hr
12.5 hr
24.5 hr
Charge safety timer accuracy in
pre-charge
tSAFETY_PRECHG
11.5
22.5
Charge safety timer accuracy in
fast charge
tSAFETY
CHG_TMR = 1
BATFET CONTROL
Time after writing to
BATFET_DLY = 1
BATFET_DLY = 0
10
20
s
BATFET_CTRL before BATFET
turned off for ship mode or
shutdown
tBATFET_DLY
ms
Deglitch time for QON to be pulled
low in order to exit from Ship
Mode
tSM_EXIT
0.55
9.0
0.65
0.75
11.5
s
Time QON is held low to initiate
system power reset
tQON_RST
10
s
Duration that BATFET is disabled
during system power reset
tBATFET_RST
350
ms
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8.6 Timing Requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
I2C INTERFACE
fSCL
DIGITAL CLOCK AND WATCHDOG
Watchdog Reset time (EN_HIZ =
SCL clock frequency
1.0 MHz
tLP_WDT
100
136
160
160
s
s
1, WATCHDOG = 160s)
Watchdog Reset time (EN_HIZ =
0, WATCHDOG = 160s)
tWDT
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8.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSYS= 20µF, CBAT= 1µF, L= 1µH (unless otherwise specified)
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
55
VBUS = 5V
VBUS = 9V
VBUS = 12V
VBUS = 15V
VBUS = 5V
VBUS = 9V
VBUS = 12V
VBUS = 15V
0
0.5
1
1.5
2
2.5
3
3.5
5
10
50
100
500
1000
Charge Current (A)
System Current (mA)
VBAT = 3.8
DCR = 15mΩ
VSYSMIN = 3.52V
DCR = 15mΩ
Figure 8-1. Charge Efficiency vs. Charge Current
100
Figure 8-2. System Light Load Efficiency vs. System Current
10
VBAT = 3.0V
VBAT = 3.8V
8
95
90
85
80
75
70
65
6
4
2
0
-2
-4
-6
-8
-10
VBAT = 3.2V
VBAT = 3.8V
VBAT = 4.2V
0
0.5
1
1.5
2
2.5
3
3.5
5
10
50
100
500 1000 2000
ICHG Setting (A)
Boost Current (mA)
VBUS = 5V
VOTG = 5.04V
DCR = 15mΩ
Figure 8-4. Charge Current Accuracy vs. ICHG Setting
Figure 8-3. Boost Mode Efficiency vs. Boost Output Current
4.4
4.3
4.35
4.3
4.2
4.1
4
4.25
4.2
3.9
3.8
3.7
4.15
4.1
VREG = 4.1V
VREG = 4.2V
4.05
3.6
VBAT = 3.2V (SYSMIN)
VBAT = 4.2V (Charge Done)
VREG = 4.35V
4
-40
3.5
-20
0
20
40
60 80 100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
System Current (A)
1
Temperature (ꢀC)
Figure 8-5. Charge Voltage Accuracy vs. VREG Setting
VBUS = 12V
Figure 8-6. System Load Regulation for SYSMIN and After
Charge Done
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8.7 Typical Characteristics (continued)
CVBUS = 1µF, CPMID= 10µF, CSYS= 20µF, CBAT= 1µF, L= 1µH (unless otherwise specified)
1
-1
3
2
-40ꢀC
25ꢀC
85ꢀC
-3
1
-5
-7
0
-9
-1
-2
-3
-11
-13
-15
-40ꢀC
25ꢀC
85ꢀC
0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
IINDPM Setting (A)
VOTG Setting (V)
VBUS = 5V
VBAT = 3.8V
Figure 8-7. Input Current Regulation Accuracy vs. IINDPM
Setting
Figure 8-8. Boost Voltage Regulation vs VOTG Setting
10
8
-40ꢀC
25ꢀC
85ꢀC
6
4
2
0
-2
-4
-6
-8
-10
0.5
1
1.5
2
2.5
IOTG Setting (A)
VBAT = 3.8V
VOTG = 5.04V
Figure 8-9. Boost Current Regulation Accuracy vs. IOTG Setting
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9 Detailed Description
9.1 Overview
BQ25620 and BQ25622 are highly-integrated 3.5A switch-mode battery chargers for single-cell Li-ion and
Li-polymer batteries. The device includes input reverse-blocking FET (RBFET, Q1), high-side switching FET
(HSFET, Q2), low-side switching FET (LSFET, Q3), battery FET (BATFET, Q4), and bootstrap diode for the
high-side gate driver.
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9.2 Functional Block Diagram
PMID
VBUS
RBFET (Q1)
VVBUS_UVLO
+
–
VBUS_UVLO
IBUS
VVBUS
Q1 Gate
Control
VBAT + VSLEEP
+
–
REGN
EN_REGN
SLEEP
VVBUS
REGN
LDO
EN_HIZ
VVBUS
+
–
VBUS_OV
VVBUS_OV
BTST
VO_REF
VVBUS
+
VBUS_OVP_BOOST
VOTG_OVP
VVBUS
+
–
IQ2
+
VOTG
–
Q2_UCP_BOOST
Q3_OCP_BOOST
HSFET (Q2)
VOTG_HSZCP
VVBUS
–
–
SW
IQ3
+
VINDPM
+
REGN
VOTG_BAT
IBUS
–
BATSNS
+
CONVERTER
Control
IINDPM
+
–
–
BATOVP
UCP
LSFET (Q3)
IQ2
VBAT_OVP
IC_TJ
+
GND
TREG
–
ILSFET_UCP
BATSNS
+
+
–
+
Q2_OCP
IHSFET_OCP
BTST - VSW
VBTST_REFRESH
SYS
+
VBAT_REG
IQ3
–
+
–
–
VSYSMIN
ICHG
V
EN_HIZ
–
+
–
REFRESH
ICHG_REG
EN_CHG
SYS
EN_OTG
GND
ICHG
VBAT_REG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
VPOORSRC
Converter
Control State
Machine
+
–
BAT
REF
DAC
VVBUS
IC_TJ
TSHUT
POORSRC
TSHUT
BATSNS
AMP
+
–
BATSNS
ILIM
IBUS
VBUS
VPMID
IBAT
D+
D-
VQON
Input
Source
Detection
USB
Adapter
ADC
VBAT
VSYS
VTS
PG
QON
TDIE
VREG -VRECHG
BATSNS
+
RECHRG
BQ25620 / 622
Block Diagram
–
ICHG
STAT
INT
+
–
TERMINATION
ITERM
CHARGE
CONTROL
STATE
REGN
VBAT_LOWV
+
–
BATLOWV
TS_BIAS
TS
BATSNS
VBAT_SHORT
BATSNS
MACHINE
+
–
BATSHORT
SUSPEND
I2C
Interface
VTS
Battery
Temperature
Sensing
SCL SDA
CE
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9.3 Feature Description
9.3.1 Power-On-Reset (POR)
BQ25620 and BQ25622 power internal bias circuits from the higher voltage of VBUS and BAT. When either
voltage rises above its undervoltage lockout (UVLO) threshold, all registers are reset to their POR values and
the I2C interface is enabled for communication. A non-maskable INT pulse is generated, after which the host can
access all of the registers.
9.3.2 Device Power Up from Battery
If only the battery is present and the VBAT is above depletion threshold (VBAT_UVLOZ), BQ25620 and BQ25622
perform a power-on reset then turns on the BATFET to connect the battery to system. The REGN LDO output
remains off to minimize the quiescent current. The low RDSON of BATFET and the low quiescent current on BAT
minimize the conduction loss and maximize the battery run time.
9.3.3 Device Power Up from Input Source
When a valid input source is plugged in with VBAT < VBAT_UVLOZ, BQ25620 and BQ25622 perform a power-on
reset then checks the input source voltage to turn on the REGN LDO and all the bias circuits. It detects and sets
the input current limit before the buck converter is started. The power up sequence from input source is as listed:
1. REGN LDO power up (Section 9.3.3.1)
2. Poor source qualification (Section 9.3.3.2)
3. Input source type detection using D+/D– to set input current limit (IINDPM) register and input source type
(Section 9.3.3.3)
4. Input voltage limit threshold setting (Section 9.3.3.5)
5. Converter power-up (Section 9.3.3.6)
9.3.3.1 REGN LDO Power Up
The REGN LDO regulator supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN
LDO also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well.
The REGN is enabled when all the below conditions are valid:
•
•
•
•
VBUS above VVBUS_UVLOZ
VBUS above VBAT + VSLEEPZ
EN_HIZ = 0
After 220-ms delay is completed
If any one of the above conditions is not valid, the REGN LDO and the converter power stage remain off with the
converter disabled. In this state, the battery supplies power to the system.
9.3.3.2 Poor Source Qualification
After the REGN LDO powers up, the device checks the current capability of the input source. The input source
has to meet the following requirements in order to move forward to the next power on steps.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC
Once these conditions are met, BQ25620 and BQ25622 proceed to input source type detection.
If a poor source is detected (when pulling IPOORSRC, VVBUS drops below VPOORSRC), BQ25620 and BQ25622
wait for tPOORSRC_RETRY and then repeat the poor source qualification routine. After 7 consecutive failures, the
device sets EN_HIZ = 1 and goes to HIZ mode. VBUS_STAT remains at 000 (not powered from VBUS) and
there is no change to VBUS_FLAG.
After tPOORSRC_RESTART (15 minutes typical) in HIZ latchoff from seven consecutive poor source failures, the poor
source detection routine restarts.
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9.3.3.3 D+/D– Detection Sets Input Current Limit (BQ25620 Only)
After the REGN LDO is powered, the adapter has been qualified as a good source, and AUTO_INDET_EN bit
= 1 (POR default), BQ25620 runs input source detection through D+/D– lines to detect USB Battery Charging
Specification 1.2 (BC1.2) input sources (CDP / SDP / DCP) and non-standard adapters. If DCP is detected,
BQ25620 runs HVDCP detection if either EN_9V or EN_12V is 1. The detection algorithm runs automatically
each time that VBUS is plugged in, updating the IINDPM according to Table 9-2. If AUTO_INDET_EN = 0, the
detection algorithm is not run and IINDPM remains unchanged. The host can force the detection algorithm to run
and update IINDPM by setting FORCE_INDET to 1.
The USB BC1.2 is able to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and
Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the
non-standard adapter detection is applied to set the input current limit.
The secondary detection is used to distinguish two types of charging ports (CDP and DCP). Most of the time, a
CDP requires the portable device (such as smart phone, tablet) to send back an enumeration within 2.5 seconds
of CDP plug-in. Otherwise, the port reverts back to SDP even though the D+/D– detection indicates CDP.
Upon the completion of input source type detection, the following registers are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. VBUS_STAT bits are updated to indicate the detected input source type
After detection completes, the host can over-write the IINDPM register to change the input current limit if
needed.
Divider 1: 1A
Non-Standard
Adapter
Divider 2: 2.1A
Divider 3: 2.4A
Divider 4: 1A
DCP
(1.5A)
Adapter Plug-in
or
FORCE_INDET
DCP/CDP
Data Contact
Detec on
Secondary
Detection
HVDCP
(1.5A)
VBUS Detec on
Primary Detec on
HVDCP
USB BC1.2 Standard
DCP
SDP
CDP
(1.5A)
(500mA)
(1.5A)
Figure 9-1. D+/D– Detection Flow
If DCP is detected (VBUS_STAT = 011), BQ25620 turns on VD+D-_0p6V_SRC on D+ if EN_DCP_BIAS is set to
1. Setting EN_DCP_BIAS to 0 while VBUS_STAT = 011 disables the VD+D-_0p6V_SRC on D+ pin, and setting
EN_DCP_BIAS to 1 while VBUS_STAT = 011 enables the VD+D-_0p6V_SRC on D+ pin. The EN_HIZ bit has priority
over EN_DCP_BIAS.
High Voltage Dedicated Charging Port (HVDCP) is used to negotiate either 9V or 12V from the power source if
BC1.2 DCP support is detected.
In order to remain in 9V or 12V HVDCP, BQ25620 must maintain a bias on D+ and D-, resulting in higher
quiescent current. The host may remove this bias and associated quiescent current by setting EN_9V and
EN_12V to 0 at any time. Setting EN_9V and EN_12V to 0 when an HVDCP adapter is providing either 9V or
12V causes the adapter to revert to 5V DCP operation.
The non-standard detection is used to distinguish vendor specific adapters based on their unique dividers on the
D+/D- pins. Comparators detect the voltage applied on each pin and determine the input current limit according
to Table 9-1.
Table 9-1. Non-Standard Adapter Detection
INPUT CURRENT
NON-STANDARD ADAPTER
D+ THRESHOLD
D– THRESHOLD
LIMIT (A)
Divider 1
VD+ within VD+D-_2p0
VD– within VD+D-_2p8
1
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Table 9-1. Non-Standard Adapter Detection (continued)
INPUT CURRENT
NON-STANDARD ADAPTER
D+ THRESHOLD
D– THRESHOLD
LIMIT (A)
Divider 2
Divider 3
VD+ within VD+D-_2p8
VD+ within VD+D-_2p8
VD– within VD+D-_2p0
VD– within VD+D-_2p8
2.1
2.4
Table 9-2. Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION
INPUT CURRENT LIMIT (IINLIM)
VBUS_STAT
USB SDP (USB500)
500 mA
1.5 A
1.5 A
1 A
0x1
0x2
0x3
0x5
0x5
0x5
0x6
0x4
USB CDP
USB DCP
Divider 1
Divider 2
2.1 A
2.4 A
1.5 A
500mA
Divider 3
HVDCP
Unknown 5-V Adapter
9.3.3.4 ILIM Pin (BQ25622 Only)
The ILIM pin clamps the input current limit to IINREG = KILIM / RILIM, where RILIM is connected from the ILIM pin
to GND. The ILIM pin can be used to limit the input current limit from 100 mA - 3.2 A. The input current is limited
to the lower of the two values set by the ILIM pin and IINDPM register bits. The ILIM pin can also be used to
monitor input current. The input current is proportional to the voltage on the ILIM pin and can be calculated by
IIN = (KILIM x VILIM) / (RILIM x 0.8). The ILIM pin function is disabled when the EN_EXTILIM bit is set to 0.
An RC filter in parallel with RILIM is required when the input current setting on the ILIM pin is either:
•
•
below 400 mA or
above 2 A when using a 2.2-μH inductor
The value for the RC filter is 1.2 kΩ and 330 nF, respectively.
9.3.3.5 Input Voltage Limit Threshold Setting (VINDPM Threshold)
BQ25620 and BQ25622 support a wide range of input voltage limit (3.8 V – 16.8V). Its POR default VINDPM
threshold is set at 4.6V. BQ25620 and BQ25622 also support dynamic VINDPM tracking, which tracks the
battery voltage to ensure a sufficient margin between input and battery voltages for proper operation of the buck
converter. This function is enabled via the VINDPM_BAT_TRACK register bit. When enabled, the actual input
voltage limit is the higher of the VINDPM register or VINDPM_BAT_TRACK (VBAT + 400 mV typical offset.)
9.3.3.6 Converter Power-Up
After the input current and voltage limits are set, the converter is enabled and the HSFET and LSFET start
switching. If battery charging is disabled, the BATFET turns off. Otherwise, the BATFET stays on to charge the
battery. Converter startup requires the following conditions:
•
•
•
•
•
•
VBUS has passed poor source qualification ( Section 9.3.3.2 )
VBUS > VBAT + VSLEEPZ
VVBUS < VVBUS_OVP
EN_HIZ = 0
VSYS < VSYS_OVP
TJ < TSHUT
BQ25620 and BQ25622 provide soft start when the system rail is ramped up by setting IINDPM to its lowest
programmable value and stepping up through each available setting until reaching the value set by IINDPM
register. Concurrently, the system short protection limits the output current to approximately 0.5A when the
system rail is below VSYS_SHORT
.
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These devices use a highly efficient 1.5 MHz, fixed frequency pulse width modulated (PWM) step-down
switching regulator. The internally compensated feedback loop keep tight control of the switching frequency
under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter
design.
The device switches to pulse frequency modulation (PFM) control at light load condition. The PFM_FWD_DIS
and PFM_OTG_DIS bits can be used to disable the PFM operation in buck and boost respectively.
9.3.4 Power Path Management
BQ25620 and BQ25622 accommodate a wide range of input sources from USB, wall adapter, wireless charger,
to car charger. They provide automatic power path selection to supply the system from input source, battery, or
both.
9.3.4.1 Narrow VDC Architecture
BQ25620 and BQ25622 use the Narrow VDC architecture (NVDC) with BATFET separating system from battery.
The minimum system voltage is set by VSYSMIN register setting. Even with a fully depleted battery, the system
is regulated to the minimum system voltage. If charging is enabled, the BATFET operates in linear mode (LDO
mode). The default minimum system voltage at POR is 3.52 V.
As the battery voltage rises above the minimum system voltage, the BATFET is turned fully on. When battery
charging is disabled and VBAT is above the minimum system voltage setting, or charging is terminated, the
system is regulated 50mV (typical) above battery voltage.
9.3.4.2 Dynamic Power Management
To meet the USB maximum current limit and avoid overloading the adapter, the device features Dynamic Power
Management (DPM), which continuously monitors the input current and input voltage. When the input source
is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below the input
voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input
current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts
to drop. Once the system voltage falls below the battery voltage by VSUPP, the device automatically enters the
supplement mode where the BATFET turns on and the battery starts discharging so that the system is supported
from both the input source and battery.
9.3.4.3 High Impedance Mode
The host may place BQ25620 and BQ25622 into high impedance mode by writing EN_HIZ = 1. In high
impedance mode, RBFET (Q1), HSFET (Q2) and LSFET (Q3) are turned off. The RBFET and HSFET block
current flow to and from VBUS, putting the VBUS pin into a high impedance state. The BATFET (Q4) is turned
on to connect the BAT to SYS. During high impedance mode, REGN is disabled and the digital clock is slowed to
conserve power.
9.3.5 Battery Charging Management
BQ25620 and BQ25622 charge 1-cell Li-Ion battery with up to 3.5 A charge current. The 15 mΩ BATFET
improves charging efficiency and minimizes the voltage drop during discharging.
9.3.5.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG bit = 1 and CE pin is LOW), BQ25620 and BQ25622 autonomously
complete a charging cycle without host involvement. The device default charging parameters are listed in Table
9-3. The host can always control the charging operations and optimize the charging parameters by writing to the
corresponding registers through I2C.
Table 9-3. Charging Parameter Default Setting
TOPOFF
TIMER
VREG
VRECHG
ITRICKLE
IPRECHG
ICHG
ITERM
BQ25620
4.2V
VREG - 100 mV
20 mA
100 mA
1040 mA
60 mA
Disabled
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Table 9-3. Charging Parameter Default Setting (continued)
TOPOFF
TIMER
VREG
VRECHG
ITRICKLE
IPRECHG
ICHG
ITERM
BQ25622
4.2V
VREG - 100 mV
20 mA
100 mA
1040 mA
60 mA
Disabled
A new charge cycle starts when the following conditions are valid:
•
•
•
•
•
Converter starts per the conditions in Section 9.3.3.6
EN_CHG = 1
CE pin is low
No thermistor fault on TS
No safety timer fault
BQ25620 and BQ25622 automatically terminate the charging cycle when the charging current is below
termination threshold, battery voltage is above recharge threshold, and device not is in DPM or thermal
regulation. When a fully charged battery is discharged below VRECHG, the device automatically starts a new
charging cycle. After charging terminates, toggling CE pin or EN_CHG bit also initiates a new charging cycle.
The STAT output indicates the charging status. Refer to Section 9.3.8.2 for details of STAT pin operation.
In addition, the status register (CHG_STAT) indicates the different charging phases: 00-charging disabled or
terminated, 01-constant current, 10 constant voltage, 11-topoff charging.
9.3.5.2 Battery Charging Profile
BQ25620 and BQ25622 charges the battery in five phases: trickle charge, pre-charge, constant current, constant
voltage and an optional top-off charging phase. At the beginning of a charging cycle, the device checks the
battery voltage and regulates current and voltage accordingly.
Regula on Voltage
VREG
Ba ery Voltage
Charge Current
ICHG
Charge Current
VBAT_LOWVZ (3 V)
VBAT_SHORTZ (2.25 V)
IPRECHG
ITERM
IBAT_SHORT
Fast Charge and Voltage Regula on
Trickle Charge
Pre-charge
Top-o Timer
(op onal)
Safety Timer
Expira on
Figure 9-2. Battery Charging Profile
9.3.5.3 Charging Termination
BQ25620 and BQ25622 terminate a charge cycle when the battery voltage is above recharge threshold, the
converter is in constant-voltage regulation and the current is below ITERM. Because constant-voltage regulation
is required for termination, BQ25620 and BQ25622 do not terminate while IINDPM, VINDPM or thermal
regulation loops are active. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and the BATFET can turn on again to engage supplement mode. Termination can
be permanently disabled by writing 0 to EN_TERM bit prior to charge termination.
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At low termination currents, due to the comparator offset, the actual termination current may be 10 mA-20 mA
higher than the termination target. in order to compensate for comparator offset, a programmable top-off timer
can be applied after termination is detected. The top-off timer follows safety timer constraints, such that if the
safety timers suspend, so does the top-off timer. Similarly, if the safety timers count at half-clock rate, so does
the top-off timer. Refer to Section 9.3.5.5 for the list of conditions. The host can read CHG_STAT to find out the
termination status.
Top-off timer gets reset by any of the following conditions:
1. Charging cycle stop and restart (toggle CE pin, toggle EN_CHG bit, charged battery falls below recharge
threshold or adapter removed and replugged)
2. Termination status low to high
3. REG_RST register bit is set
The top-off timer settings are read in after is detected by the charger. Programming a top-off timer value after
termination has no effect unless a recharge cycle is initiated. CHG_FLAG is set to 1 when entering top-off timer
segment and again when the top-off timer expires.
9.3.5.4 Thermistor Qualification
BQ25620 and BQ25622 provide a single thermistor input for battery temperature monitoring. The TS pin input of
the battery temperature can be ignored by the charger if TS_IGNORE = 1. When the TS pin feedback is ignored,
the charger considers the TS to always be valid for charging and OTG modes, and TS_STAT always reports
000. The TS pin may be left floating if TS_IGNORE is set to 1.
When TS_IGNORE=1, the TS_ADC channel is disabled, with TS_ADC_DIS forced to 1; Attempting to write to 0
is ignored.
When TS_IGNORE = 0, the charger adjusts the charging profile based on the TS pin feedback information
according to the configurable profile described in Section 9.3.5.4.1. When the battery temperature crosses from
one temperature range to another, TS_STAT is updated accordingly, and the charger sets the FLAG bit for the
newly-entered temperature range. If TS_MASK is set to 0, any change to TS_STAT, including a transition to
TS_NORMAL, generates an INT pulse.
9.3.5.4.1 Advanced Temperature Profile in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and
high temperature ranges. As battery technology continues to evolve, battery manufacturers have released
temperature safety specifications that extend beyond the JEITA standard. BQ25620 and BQ25622 feature
a highly flexible temperature-based charging profile to meet these advanced specifications while remaining
backwards compatible with the original JEITA standard. Figure 8-3 shows the programmability for charger
behavior under different battery temperature (TS) operating regions.
Percentage of
ICHG / CHG_RATE
Charging Voltage
programmable
programmable
programmable
100%
VREG
VREG -100mV
VREG -200mV
VREG -300mV
TS_VSET_SYM
40%
20%
suspend
TH1
TH2
TS_PRECOOL
TH4
TH5
TH6
TH1
TH2
TS_PRECOOL
TH4
TH5
TH6
TH3
TH3
TS_COLD TS_COOL
TS_NORMAL
TS_PREWARM TS_WARM TS_HOT
TS_COLD TS_COOL
TS_NORMAL
TS_PREWARM TS_WARM TS_HOT
TS Temperature
TS Temperature
Figure 9-3. TS Charging Values
Charging safety timer is adjusted within the temperature zones to reflect changes to the charging current. When
IPRECHG and ICHG are reduced to 20% or 40% in the cool or warm temperature zones, the charging safety
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timer counts at half rate. If charging is suspended, the safety timer is suspended, the STAT pin blinks and
CHG_STAT is set to 00 (not charging or charge terminated.)
9.3.5.4.2 TS Pin Thermistor Configuration
The typical TS resistor network is illustrated below.
REGN
10 kΩ
TS
Figure 9-4. TS Resistor Network
The value of RT1 and RT2 are determined from the resistance of the thermistor at 0 and 60 ºC (RTH0degC and
RTH60degC) and the corresponding voltage thresholds VTS_0degC and VTS_60degC (expressed as percentage of
REGN with value between 0 and 1.) For the most accurate thermistor curve fitting, use the rising threshold for
VTS_COLD at 0 ºC and the falling threshold for VTS_HOT at 60 ºC, regardless of the actual register settings for
TS_TH1_TH2_TH3 and TS_TH4_TH5_TH6.
1
1
RTH
× RTH
1
×
60degC
−
0degC
×
V
V
TS_0degC
TS_60degC
RT2 =
RT1 =
(1)
(2)
1
RTH
V
− 1 − RTH
0degC
×
− 1
60degC
V
V
TS_60degC
TS_0degC
1
− 1
TS_0degC
1
R
1
+
RTH
T2
0degC
Assuming a 103AT NTC thermistor on the battery pack, the RT1 and RT2 are calculated to be 5.30 kΩ and 31.1
kΩ respectively.
9.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
For battery protection during boost OTG, BQ25620 and BQ25622 monitor the battery temperature to be within
the TS_TH_OTG_COLD to TS_TH_OTG_HOT register settings. For a 103AT NTC thermistor with RT1 of 5.3
kΩ and RT2 of 31.1 kΩ, TS_TH_OTG_COLD default is -10°C and TS_TH_OTG_HOT default is 60°C. When
temperature is outside of this range, the OTG mode is suspended with REGN remaining on. In addition,
VBUS_STAT bits are set to 000, TS_STAT is set to 001 (TS_OTG_COLD) or 010 (TS_OTG_HOT), and
TS_FLAG is set. Once the battery temperature returns to normal temperature, the boost OTG is restarted and
TS_STAT returns to 000 (TS_NORMAL).
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IOTG
Suspended
TH_OTG_COLD
TH_OTG_HOT
TS_OTG_HOT
TS_OTG_COLD
TS_NORMAL
TS Temperature
Figure 9-5. TS Pin Thermistor Sense Threshold in Boost Mode
9.3.5.4.4 JEITA Charge Rate Scaling
The TS_ISET_PRECOOL, TS_ISET_COOL, TS_ISET_PREWARM and TS_ISET_WARM cool and warm
charge current fold backs are based on a 1C charging rate.
A setting of TS_ISET_COOL = 01 sets ICHG_COOL = 20% ICHG1C. When the battery enters the TS_COOL
temperature zone, the current is reduced to 20% of the 1C charging rate. In order to convert the charging
foldback, the host must set the CHG_RATE register to the C rate for the battery. This scales the fold back
accordingly, producing an ICHG_COOL as shown in Equation 3:
I
CHG_COOL
I
=
× JEITA_ISETC
(3)
CHG
CHG_RATE
When TS_ISET_PRECOOL, TS_ISET_COOL, TS_ISET_PREWARM or TS_ISET_WARM is set to either 00
(suspend) or 11 (unchanged), the CHG_RATE setting has no effect. A summary is provided in Table 9-4.
Table 9-4. ICHG Fold Back
TS_ISET_PRECOOL, TS_ISET_COOL,
TS_ISET_PREWARM or TS_ISET_WARM
FOLD-BACK CURRENT AS PERCENTAGE
OF ICHG
CHG_RATE
00
Any
0% (Suspended)
20%
01 (20%)
00 (1C)
01 (2C)
10 (4C)
11 (6C)
00 (1C)
01 (2C)
10 (4C)
11 (6C)
Any
10%
5%
3.3%
10 (40%)
40%
20%
10%
6.6%
11
100%
9.3.5.4.5 TS_BIAS Pin (BQ25622 Only)
The BQ25622 has the TS_BIAS pin to isolate the battery temperature sensing thermistor and associated
resistor-divider from REGN. The 103AT thermistor with typical resistor-divider network requires about 400 μA
to bias. The BQ25622 provides the TS_BIAS pin, which is internally connected to the REGN LDO via a back-to-
back MOSFET switch. When no temperature measurement is being taken, the switch is disabled to disconnect
the thermistor and resistor-divider from the REGN LDO, saving the 400 μA bias current from being expended
unnecessarily.
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The TS_BIAS pin has short-circuit protection. If a short is detected on the TS_BIAS pin, the switch is disabled
to disconnect the short from REGN. If this condition occurs, TS_STAT register is set to 0x3. Charging and OTG
modes are suspended until the short is removed.
9.3.5.5 Charging Safety Timers
BQ25620 and BQ25622 have three built-in safety timers to prevent extended charging cycle due to abnormal
battery conditions. The fast charge safety timer and pre-charge safety timers are set through I2C CHG_TMR and
PRECHG_TMR fields, respectively. The trickle charge timer is fixed at 1 hour.
The trickle charging, pre-charging and fast charging safety timers can be disabled by setting
EN_SAFETY_TMRS = 0. EN_SAFETY_TMRS can be enabled anytime regardless of which charging stage
the charger is in. Each timer starts to count as soon as the following two conditions are simultaneously true:
EN_SAFETY_TMRS=1 and the corresponding charging stage is active.
When either the fast charging, trickle charging or pre-charging safety timer expires, the SAFETY_TMR_STAT
and SAFETY_TMR_FLAG bits are set to 1.
Events that cause a reduction in charging current also cause the charging safety timer to count at half-clock rate
if TMR2X_EN bit is set.
During faults which suspend charging, the charge, pre-charge and trickle safety timers are also suspended,
regardless of the state of the TMR2X_EN bit. Once the fault goes away, charging resumes and the safety timer
resumes from where it stopped.
The charging safety timer and the charging termination can be disabled at the same time. Under this condition,
the charging keeps running until it is disabled by the host.
9.3.6 USB On-The-Go (OTG)
9.3.6.1 Boost OTG Mode
BQ25620 and BQ25622 support boost converter operation to deliver power from the battery to VBUS. The
output voltage and maximum current are set in the VOTG and IOTG registers, respectively. VBUS_STAT is set
to 111 upon a successful entry into boost OTG. The boost operation is enabled when the following conditions are
met:
1. BAT above VBAT_OTG
2. VBUS less than VBAT+VSLEEP
3. Boost mode operation is enabled (EN_OTG = 1)
4. VTS_OTG_HOT < VTS < VTS_OTG_COLD
5. VREGN > VREGN_OK
6. 30 ms delay after EN_OTG = 1
7. Boost mode regulation voltage in REG0x0C is greater than 105% of battery voltage.
9.3.7 Integrated 12-Bit ADC for Monitoring
BQ25620 and BQ25622 provide an integrated 12-bit ADC for the host to monitor various system parameters.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is disabled by default (ADC_EN=0) to conserve
power. The ADC is allowed to operate if either VBUS > VPOORSRC or VBAT > VBAT_LOWV is valid. If ADC_EN
is set to ‘1’ before VBUS or VBAT reach their respective valid thresholds, then ADC_EN stays '0'. When the
charger enters HIZ mode, the ADC is disabled. The host can re-enable the ADC during HIZ mode by setting
ADC_EN =1.
At battery only condition, if the TS_ADC channel is enabled, the ADC only operates when the battery voltage is
higher than 3.2V (the minimal value to turn on REGN), otherwise, the ADC operates when the battery voltage is
higher than VBAT_LOWV
.
The ADC_DONE_STAT, ADC_DONE_FLAG bits are set when a conversion is complete in one-shot mode only.
During continuous conversion mode, the ADC_DONE_STAT, ADC_DONE_FLAG bits have no meaning and
remain at 0. In one-shot mode, the ADC_EN bit is set to 0 at the completion of the conversion, at the same time
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as the ADC_DONE_FLAG bit is set. In continuous mode, the ADC_EN bit remains at 1 until the user disables
the ADC by setting it to 0.
9.3.8 Status Outputs ( PG, STAT, INT)
9.3.8.1 PG Pin Power Good Indicator
The PG pin (BQ25620 and BQ25622) goes LOW to indicate a good input source when:
•
•
•
•
VVBUS is above VVBUS_UVLOZ
VVBUS is above battery (not in sleep)
VVBUS is below VVBUS_OVP threshold
VVBUS is above VPOORSRC when IPOORSRC current is applied (not a poor source)
9.3.8.2 Charging Status Indicator (STAT)
BQ25620 and BQ25622 indicates charging state on the open drain STAT pin. The STAT pin can drive an LED.
The STAT pin function can be disabled via the DIS_STAT bit.
Table 9-5. STAT Pin State
CHARGING STATE
STAT INDICATOR
LOW
Charging in progress (including recharge)
Not charging, no fault detected. (Includes charging complete, Charge Disabled, no adapter present, in OTG mode.)
HIGH
Charge suspend
Boost Mode suspend
Blinking at 1 Hz
9.3.8.3 Interrupt to Host ( INT)
In many applications, the host does not continually poll the charger status registers. Instead, the INT pin may
be used to notify the host of a status change with a 256-μs INT pulse. Upon receiving the interrupt pulse,
the host may read the flag registers (Charger_Flag_X and FAULT_Flag_X) to determine the event that caused
the interrupt, and for each flagged event, read the corresponding status registers (Charger_Status_X and
FAULT_Status_X) to determine the current state. Once set to 1, the flag bits remain latched at 1 until they are
read by the host, which clears them. The status bits, however, are updated whenever there is a change to status
and always represent the current state of the system.
All of the INT events can be masked off to prevent INT pulses from being sent out when they occur, with the
exception of the initial power-up interrupt. Interrupt events are masked by setting their mask bit in registers
(Charger_Mask_X and FAULT_Mask_X.) Events always cause the corresponding flag bit to be set to 1,
regardless of whether or not the interrupt pulse has been masked.
9.3.9 BATFET Control
BQ25620 and BQ25622 have an integrated, bi-directionally blocking BATFET that can be turned off to remove
leakage current from the battery to the system. The BATFET is controlled by the BATFET_CTRL register bits,
and supports shutdown mode, ship mode and system power reset.
Table 9-6. BATFET Control Modes
ENTRY, WITH ADAPTER, ENTRY, WITH ADAPTER,
MODE
BATFET
I2C
ENTRY, NO ADAPTER
BATFET_CTRL_WVBUS BATFET_CTRL_WVBUS
= 0 = 1
EXIT
Normal
On
Active
N/A
N/A
N/A
N/A
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Table 9-6. BATFET Control Modes (continued)
ENTRY, WITH ADAPTER, ENTRY, WITH ADAPTER,
BATFET_CTRL_WVBUS BATFET_CTRL_WVBUS
= 0 = 1
MODE
BATFET
I2C
ENTRY, NO ADAPTER
Ship mode
Off
Off
Writing BATFET_CTRL = Writing BATFET_CTRL = Writing BATFET_CTRL = QON or
10 turns off BATFET after 10 has no effect while 10 turns off BATFET adapter
BATFET_DLY and enters adapter is present. When after BATFET_DLY. When plug-in
ship mode.
both BATFET_DLY has
expired and the adapter
is removed, the device
turns off BATFET and
both BATFET_DLY has
expired and adapter is
removed, the device
enters ship mode. Writing
enters ship mode. Writing BATFET_CTRL = 00
BATFET_CTRL = 00 before adapter is removed
before adapter is removed turns BATFET on and
aborts ship mode.
aborts ship mode.
System reset
On to Off Active
to On
Writing BATFET_CTRL
= 11 initiates
Writing BATFET_CTRL
= 11 is ignored and
Writing BATFET_CTRL
= 11 initiates
N/A
system reset after
BATFET_DLY. Holding
QON low for tQON_RST
initiates immediate reset
(BATFET_DLY is not
applied.)
BATFET_CTRL resets to system reset after
00. Holding QON low for
tQON_RST is ignored.
BATFET_DLY. Holding
QON low for tQON_RST
initiates immediate reset.
Converter is placed in HIZ
during system reset and
exits HIZ when system
reset completes.
Shutdown mode
Off
Off
Writing BATFET_CTRL = Writing BATFET_CTRL = 01 with adapter present
01 turns off BATFET after is ignored, regardless of BATFET_CTRL_WVBUS
BATFET_DLY and enters setting, and BATFET_CTRL is reset to 00.
shutdown.
Adapter
plug-in
9.3.9.1 Shutdown Mode
For the lowest battery leakage current, the host can shut down BQ25620 and BQ25622 by setting the register
bits BATFET_CTRL to 01. In this mode, the BATFET is turned off to prevent the battery from powering the
system, the I2C is disabled and the charger is totally shut down. BQ25620 and BQ25622 can only be woken up
by plugging in an adapter. When the adapter is plugged in, BQ25620 and BQ25622 start back up with all register
settings in their POR default.
After the host sets BATFET_CTRL to 01, the BATFET turns off after waiting either 20 ms or 10 s as configured
by BATFET_DLY register bit. Shutdown mode can only be entered when VVBUS < VVBUS_UVLO, regardless of the
BATFET_CTRL_WVBUS setting, which has no effect on shutdown mode entry. If the host writes BATFET_CTRL
= 01 with VVBUS > VVBUS_UVLOZ, the request is ignored and the BATFET_CTRL bits are set back to 00.
If the host writes BATFET_CTRL to 01 while boost OTG, BQ25620 and BQ25622 first exit from boost OTG by
setting EN_OTG = 0 and then enters shutdown mode.
QON has no effect during shutdown mode. The internal pull-up on the QON pin is disabled during shutdown to
prevent leakage through the pin.
9.3.9.2 Ship Mode
The host may place BQ25620 and BQ25622 into ship mode by setting BATFET_CTRL = 10. In ship mode, the
BATFET is turned off to prevent the battery from powering the system, and the I2C is disabled. Ship mode has
slightly higher quiescent current than shutdown mode, but QON may be used to exit from ship mode. BQ25620
and BQ25622 are taken out of ship mode by either of these methods:
•
Pulling the QON pin low for tSM_EXIT
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•
VVBUS > VVBUS_UVLOZ (adapter plug-in)
When BQ25620 and BQ25622 exit from ship mode, the registers are reset to their POR values.
Ship mode is only entered when the adapter is not present. Setting BATFET_CTRL = 10 while VVBUS
>
VVBUS_UVLOZ (adapter present) either disables the BATFET or has no immediate effect depending on the setting
of BATFET_CTRL_WVBUS.
When BATFET_CTRL_WVBUS is set to 0 and VVBUS > VVBUS_UVLO (adapter present), setting BATFET_CTRL
= 10 has no immediate effect. If the adapter is removed while BATFET_CTRL is set to 10, then the BATFET is
disabled and the device enters ship mode. The BATFET turns off either after tBATFET_DLY or when the adapter is
removed, whichever comes later.
When BATFET_CTRL_WVBUS is set to 1 and VVBUS > VVBUS_UVLO (adapter present), setting BATFET_CTRL
= 10 turns off the BATFET after tBATFET_DLY. The converter continues to run while the adapter is present,
supplying SYS power from the adapter. If the adapter is removed while BATFET_CTRL is set to 10, BQ25620
and BQ25622 enters ship mode. Ship mode is entered either after tBATFET_DLY or when the adapter is removed,
whichever comes later.
9.3.9.3 System Power Reset
The BATFET functions as a load switch between battery and system when the converter is not running. By
changing the state of BATFET from on to off, systems connected to SYS can be power cycled. Any of the
following conditions initiates a system power reset:
•
•
•
•
BATFET_CTRL_WVBUS = 1 and QON is pulled low for tQON_RST
BATFET_CTRL_WVBUS = 1 and BATFET_CTRL = 11
BATFET_CTRL_WVBUS = 0 and VBUS < VVBUS_UVLO simultaneously with QON pulled low for tQON_RST
BATFET_CTRL_WVBUS = 0 and VBUS < VVBUS_UVLO and BATFET_CTRL = 11
BATFET_CTRL
_WVBUS
Adapter
tQON_RST
tQON_RST
tQON_RST
/QON
ON
ON
ON
BATFET
OFF
tBATFET_RST
OFF
tBATFET_RST
OFF
tBATFET_RST
Enter HIZ
Enter HIZ
BATFET Reset with
BATFET_CTRL_WVBUS=0
BATFET Reset with
BATFET_CTRL_WVBUS=1
Figure 9-6. System Power Reset Timing
When BATFET_CTRL_WVBUS is set to 1, system power reset proceeds if either BATFET_CTRL is set to 11 or
QON is pulled low for tQON_RST, regardless of whether VBUS is present or not . There is a delay of tBATFET_DLY
before initiating the system power reset. If QON is pulled low, there is no delay after the tQON_RST completes,
regardless of BATFET_DLY setting.
The system power reset can be initiated from the battery only condition, from OTG mode or from the forward
charging mode with adapter present. If the system power is reset when the charger is in boost OTG mode, the
boost OTG mode is first stopped by setting EN_OTG = 0.
9.4 Device Functional Modes
9.4.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the
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charger is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and an INT is asserted low to
alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as 1 upon the first read and then 0
upon subsequent reads. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired. All the registers are in the
default settings.
In default mode, the device keeps charging the battery with default 1-hour trickle charging safety timer, 2-hour
pre-charging safety timer and the 12-hour fast charging safety timer. At the end of the 1-hour or 2-hour or
12-hour timer expired, the charging is stopped and the buck converter continues to operate to supply system
load.
A write to any I2C register transitions the charger from default mode to host mode, and initiates the watchdog
timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has
to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set),
or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog expires, the device returns to default mode. The ICHG value is divided in half when the
watchdog timer expires, and a number of other fields are reset to their POR default values as shown in the notes
column of the register tables in Section 9.6. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1,
and an INT is asserted low to alert the host (unless masked by WD_MASK).
Reset
Selective
Registers
Default Mode
WD_STAT=1
POR
I2C Write
Reset
Watchdog
Timer
Yes
Host Mode
WD_STAT=0
I2C Write to
WD_RST
No
Watchdog Timer Expired?
Yes
No
Figure 9-7. Watchdog Timer Flow Chart
9.4.2 Register Bit Reset
Beside the register reset by the watchdog timer in the default mode, the register and the timer could be reset to
the default value by writing the REG_RST bit to 1. The register bits, which can be reset by the REG_RST bit, are
noted in the Register Map section. After the register reset, the REG_RST bit goes back from 1 to 0 automatically.
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9.5 Programming
9.5.1 Serial Interface
BQ25620 and BQ25622 uses I2C compatible interface for flexible charging parameter programming and
instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus
lines are required: a serial data line (SDA), and a serial clock line (SCL).
The device has 7-bit I2C address 0x6B , receiving control inputs from a host device such as a micro-controller
or digital signal processor through register addresses 0x02 – 0x38. The host device initiates all transfers and the
charger responds. Register reads outside of these addresses return 0xFF. When the bus is free, both SDA and
SCL lines are HIGH.
The I2C interface supports standard mode (up to 100 kbits/s), fast mode (up to 400 kbits/s) and fast mode plus
(up to 1 Mbits/s.) These lines are pulled up to a reference voltage via pull-up resistor. The device I2C detection
thresholds support a communication reference voltage from 1.2 V to 5 V.
9.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of data
allowed
Figure 9-8. Bit Transfer on the I2C Bus
9.5.1.2 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the host. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
STOP (P)
Figure 9-9. START and STOP Conditions on the I2C Bus
START (S)
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9.5.1.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the
Most Significant Bit (MSB) first. If target cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the host into a wait state (clock stretching).
Data transfer then continues when the target is ready for another byte of data and releases the SCL line.
Acknowledgement
Acknowledgement
signal from host
signal from target
MSB
SDA
1
2
7
8
9
1
2
8
9
SCL S or Sr
START or
P or Sr
ACK
ACK
STOP or
Repeate
d START
Repeated
START
Figure 9-10. Data Transfer on the I2C Bus
9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after each transmitted byte. The ACK bit allows the target to signal the host that
the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge
9th clock pulse, are generated by the host.
The host releases the SDA line during the acknowledge clock pulse so the target can pull the SDA line LOW and
it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The host can then generate
either a STOP to abort the transfer or a repeated START to start a new transfer.
9.5.1.5 Target Address and Data Direction Bit
After the START signal, a target address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/ W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B).
SDA
S
8
9
8
9
8
9
P
SCL
1-7
1-7
1-7
DATA
START
ADDRESS
R/W ACK
DATA
ACK
ACK
STOP
Figure 9-11. Complete Data Transfer on the I2C Bus
9.5.1.6 Single Write and Read
S
Target Addr
0
ACK
Reg Addr
ACK
Data to Addr
ACK
P
Figure 9-12. Single Write
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S
Target Addr
0
ACK
Reg Addr
ACK
S
Target Addr
ACK
1
Data
NCK
P
Figure 9-13. Single Read
If the register address is not defined, the charger IC sends back NACK and returns to the idle state.
9.5.1.7 Multi-Write and Multi-Read
The charger device supports multi-byte read and multi-byte write of all registers. These multi-byte operations are
allowed to cross register boundaries. For instance, the entire register map may be read in a single operation with
a 39-byte read that starts at register address 0x01.
S
Target Addr
0
ACK
Reg Addr
ACK
Data to Addr
ACK
Data to Addr+1
ACK
Data to Addr+N
ACK
P
Figure 9-14. Multi-Write
S
Target Addr
0
ACK
Reg Addr
ACK
S
Target Addr
ACK
1
Data @ Addr
ACK Data @ Addr+1 ACK
Data @ Addr+N NCK
P
Figure 9-15. Multi-Read
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9.6 Register Maps
I2C Device Address: 0x6B.
9.6.1 Register Programming
The BQ25620 and BQ25622 contain 8-bit and 16-bit registers. When writing to 16-bit registers, I2C transactions
follow the little endian format, starting at the address of the least significant byte and writing both register bytes in
a single 16-bit transaction.
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9.6.2 BQ25620 Registers
Table 9-7 lists the memory-mapped registers for the BQ25620 registers. All register offset addresses not listed in
Table 9-7 should be considered as reserved locations and the register contents should not be modified.
Table 9-7. BQ25620 Registers
Address Acronym
Register Name
Charge Current Limit
Charge Voltage Limit
Input Current Limit
Input Voltage Limit
IOTG regulation
VOTG regulation
Minimal System Voltage
Pre-charge Control
Termination Control
Charge Control 0
Charge Timer Control
Charger Control 1
Charger Control 2
Charger Control 3
Charger Control 4
NTC Control 0
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
0x2
0x4
REG0x02_Charge_Current_Limit
REG0x04_Charge_Voltage_Limit
REG0x06_Input_Current_Limit
REG0x08_Input_Voltage_Limit
REG0x0A_IOTG_regulation
REG0x0C_VOTG_regulation
REG0x0E_Minimal_System_Voltage
REG0x10_Pre-charge_Control
REG0x12_Termination_Control
REG0x14_Charge_Control_0
REG0x15_Charge_Timer_Control
REG0x16_Charger_Control_1
REG0x17_Charger_Control_2
REG0x18_Charger_Control_3
REG0x19_Charger_Control_4
REG0x1A_NTC_Control_0
REG0x1B_NTC_Control_1
REG0x1C_NTC_Control_2
REG0x1D_Charger_Status_0
REG0x1E_Charger_Status_1
REG0x1F_FAULT_Status_0
REG0x20_Charger_Flag_0
REG0x21_Charger_Flag_1
REG0x22_FAULT_Flag_0
REG0x23_Charger_Mask_0
REG0x24_Charger_Mask_1
REG0x25_FAULT_Mask_0
REG0x26_ADC_Control
0x6
0x8
0xA
0xC
0xE
0x10
0x12
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
NTC Control 1
NTC Control 2
Charger Status 0
Charger Status 1
FAULT Status 0
Charger Flag 0
Charger Flag 1
FAULT Flag 0
Charger Mask 0
Charger Mask 1
FAULT Mask 0
ADC Control
REG0x27_ADC_Function_Disable_0
REG0x28_IBUS_ADC
ADC Function Disable 0
IBUS ADC
REG0x2A_IBAT_ADC
IBAT ADC
REG0x2C_VBUS_ADC
VBUS ADC
REG0x2E_VPMID_ADC
VPMID ADC
REG0x30_VBAT_ADC
VBAT ADC
REG0x32_VSYS_ADC
VSYS ADC
REG0x34_TS_ADC
TS ADC
REG0x36_TDIE_ADC
TDIE ADC
REG0x38_Part_Information
Part Information
Complex bit access types are encoded to fit into small table cells. Table 9-8 shows the codes that are used for
access types in this section.
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Table 9-8. BQ25620 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
9.6.2.1 REG0x02_Charge_Current_Limit Register (Address = 0x2) [Reset = X]
REG0x02_Charge_Current_Limit is shown in Figure 9-16 and described in Table 9-9.
Return to the Summary Table.
Charge Current Limit
Figure 9-16. REG0x02_Charge_Current_Limit Register
15
7
14
13
12
11
10
9
1
8
0
RESERVED
R-0x0
ICHG
R/W-X
6
5
4
3
2
ICHG
R/W-X
RESERVED
R-0x0
Table 9-9. REG0x02_Charge_Current_Limit Register Field Descriptions
Bit
Field
Type
Reset
0x0
X
Notes
Description
15:12
11:5
RESERVED
ICHG
R
Reserved
R/W
WATCHDOG Timer
Expiration sets ICHG to
1/2 its previous value
(rounded down)
Reset by:
Charge Current Regulation Limit:
This 16-bit register follows the little-endian convention.
ICHG[5:2] falls in REG0x03[3:0], and ICHG[1:0] falls in
REG0x02[7:6].
POR: 1040mA (1Ah)
REG_RESET
Range: 80mA-3520mA (2h-58h)
Clamped Low
Clamped High
Bit Step: 80mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 160mA
4:0
RESERVED
R
0x0
Reserved
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9.6.2.2 REG0x04_Charge_Voltage_Limit Register (Address = 0x4) [Reset = 0x0D20]
REG0x04_Charge_Voltage_Limit is shown in Figure 9-17 and described in Table 9-10.
Return to the Summary Table.
Charge Voltage Limit
Figure 9-17. REG0x04_Charge_Voltage_Limit Register
15
7
14
6
13
12
11
10
9
8
0
RESERVED
R-0x0
VREG
R/W-0x1A4
5
4
3
2
1
VREG
RESERVED
R-0x0
R/W-0x1A4
Table 9-10. REG0x04_Charge_Voltage_Limit Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:12
11:3
RESERVED
VREG
R
0x0
Reserved
R/W
0x1A4
Reset by:
Battery Voltage Regulation Limit:
REG_RESET
This 16-bit register follows the little-endian convention.
VREG[8:5] falls in REG0x05[3:0], and VREG[4:0] falls
in REG0x04[7:3].
POR: 4200mV (1A4h)
Range: 3500mV-4800mV (15Eh-1E0h)
Clamped Low
Clamped High
Bit Step: 10mV
2:0
RESERVED
R
0x0
Reserved
9.6.2.3 REG0x06_Input_Current_Limit Register (Address = 0x6) [Reset = 0x0A00]
REG0x06_Input_Current_Limit is shown in Figure 9-18 and described in Table 9-11.
Return to the Summary Table.
Input Current Limit
Figure 9-18. REG0x06_Input_Current_Limit Register
15
7
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
IINDPM
R/W-0xA0
5
4
3
2
IINDPM
RESERVED
R-0x0
R/W-0xA0
Table 9-11. REG0x06_Input_Current_Limit Register Field Descriptions
Bit
15:12
Field
Type
Reset
Notes
Description
RESERVED
R
0x0
Reserved
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Table 9-11. REG0x06_Input_Current_Limit Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
11:4
IINDPM
R/W
0xA0
Reset by:
Input Current Regulation Limit:
REG_RESET
Adapter Removal
This 16-bit register follows the little-endian convention.
IINDPM[7:4] falls in REG0x07[3:0], and IINDPM[3:0]
falls in REG0x06[7:4]. BQ25620: Based on D+/D-
detection results:
USB SDP = 500mA
USB CDP = 1.5A
USB DCP = 1.5A
USB HVDCP = 1.5A
Unknown Adapter = 500mA
Non-Standard Adapter = 1A/2.1A/2.4A
POR: 3200mA (A0h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
When the adapter is removed, IINDPM is reset to its
POR value of 3.2 A.
3:0
RESERVED
R
0x0
Reserved
9.6.2.4 REG0x08_Input_Voltage_Limit Register (Address = 0x8) [Reset = 0x0E60]
REG0x08_Input_Voltage_Limit is shown in Figure 9-19 and described in Table 9-12.
Return to the Summary Table.
Input Voltage Limit
Figure 9-19. REG0x08_Input_Voltage_Limit Register
15
7
14
13
12
11
10
9
1
8
0
RESERVED
R-0x0
VINDPM
R/W-0x73
6
5
4
3
2
VINDPM
R/W-0x73
RESERVED
R-0x0
Table 9-12. REG0x08_Input_Voltage_Limit Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:14
13:5
RESERVED
VINDPM
R
0x0
Reserved
R/W
0x73
Absolute Input Voltage Regulation Limit:
This 16-bit register follows the little-endian convention.
VINDPM[8:3] falls in REG0x09[5:0], and VINDPM[2:0]
falls in REG0x08[7:5].
POR: 4600mV (73h)
Range: 3800mV-16800mV (5Fh-1A4h)
Clamped Low
Clamped High
Bit Step: 40mV
4:0
RESERVED
R
0x0
Reserved
9.6.2.5 REG0x0A_IOTG_regulation Register (Address = 0xA) [Reset = 0x0320]
REG0x0A_IOTG_regulation is shown in Figure 9-20 and described in Table 9-13.
Return to the Summary Table.
IOTG regulation
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Figure 9-20. REG0x0A_IOTG_regulation Register
15
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
IOTG
R/W-0x32
7
5
4
3
2
IOTG
RESERVED
R-0x0
R/W-0x32
Table 9-13. REG0x0A_IOTG_regulation Register Field Descriptions
Bit
15:12
11:4
Field
Type
Reset
Notes
Description
RESERVED
IOTG
R
0x0
Reserved
R/W
0x32
Reset by:
OTG mode current regulation limit:
REG_RESET
WATCHDOG
This 16-bit register follows the little-endian convention.
IOTG[7:4] falls in REG0x0B[3:0], and IOTG[3:0] falls in
REG0x0A[7:4].
POR: 1000mA (32h)
Range: 100mA-3200mA (5h-A0h)
Clamped Low
Clamped High
Bit Step: 20mA
3:0
RESERVED
R
0x0
Reserved
9.6.2.6 REG0x0C_VOTG_regulation Register (Address = 0xC) [Reset = 0x0FC0]
REG0x0C_VOTG_regulation is shown in Figure 9-21 and described in Table 9-14.
Return to the Summary Table.
VOTG regulation
Figure 9-21. REG0x0C_VOTG_regulation Register
15
7
14
13
12
11
10
9
1
8
0
RESERVED
R-0x0
VOTG
R/W-0x3F
6
5
4
3
2
VOTG
RESERVED
R-0x0
R/W-0x3F
Table 9-14. REG0x0C_VOTG_regulation Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:13
12:6
RESERVED
VOTG
R
0x0
Reserved
R/W
0x3F
Reset by:
OTG mode regulation voltage:
REG_RESET
This 16-bit register follows the little-endian convention.
VOTG[6:2] falls in REG0x0D[4:0], and VOTG[1:0] falls
in REG0x0C[7:6].
POR: 5040mV (3Fh)
Range: 3840mV-9600mV (30h-78h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0
RESERVED
R
0x0
Reserved
9.6.2.7 REG0x0E_Minimal_System_Voltage Register (Address = 0xE) [Reset = 0x0B00]
REG0x0E_Minimal_System_Voltage is shown in Figure 9-22 and described in Table 9-15.
Return to the Summary Table.
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Minimal System Voltage
Figure 9-22. REG0x0E_Minimal_System_Voltage Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R-0x0
VSYSMIN
R/W-0x2C
7
6
5
4
3
2
VSYSMIN
R/W-0x2C
RESERVED
R-0x0
Table 9-15. REG0x0E_Minimal_System_Voltage Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:12
11:6
RESERVED
VSYSMIN
R
0x0
Reserved
R/W
0x2C
Reset by:
Minimal System Voltage:
REG_RESET
This 16-bit register follows the little-endian
convention. VSYSMIN[5:2] falls in REG0x0F[3:0], and
VSYSMIN[1:0] falls in REG0x0E[7:6].
POR: 3520mV (2Ch)
Range: 2560mV-3840mV (20h-30h)
Clamped Low
Clamped High
Bit Step: 80mV
5:0
RESERVED
R
0x0
Reserved
9.6.2.8 REG0x10_Pre-charge_Control Register (Address = 0x10) [Reset = 0x0050]
REG0x10_Pre-charge_Control is shown in Figure 9-23 and described in Table 9-16.
Return to the Summary Table.
Pre-charge Control
Figure 9-23. REG0x10_Pre-charge_Control Register
15
7
14
6
13
12
11
10
9
8
RESERVED
R-0x0
IPRECHG
R/W-0xA
5
4
3
2
1
0
IPRECHG
R/W-0xA
RESERVED
R-0x0
Table 9-16. REG0x10_Pre-charge_Control Register Field Descriptions
Bit
15:9
8:3
Field
Type
Reset
Notes
Description
RESERVED
IPRECHG
R
0x0
Reserved
R/W
0xA
Reset by:
Pre-charge current regulation limit:
REG_RESET
This 16-bit register follows the little-endian convention.
IPRECHG[4] falls in REG0x11[0], and IPRECHG[3:0]
falls in REG0x10[7:4]
POR: 100mA (Ah)
Range: 20mA-620mA (2h-3Eh)
Clamped Low
Bit Step: 20mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 80mA
2:0
RESERVED
R
0x0
Reserved
9.6.2.9 REG0x12_Termination_Control Register (Address = 0x12) [Reset = 0x0030]
REG0x12_Termination_Control is shown in Figure 9-24 and described in Table 9-17.
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Return to the Summary Table.
Termination Control
Figure 9-24. REG0x12_Termination_Control Register
15
14
13
12
11
10
9
1
8
RESERVED
R-0x0
ITERM
R/W-0xC
7
6
5
4
3
2
0
ITERM
RESERVED
R-0x0
R/W-0xC
Table 9-17. REG0x12_Termination_Control Register Field Descriptions
Bit
15:9
8:2
Field
Type
Reset
Notes
Description
RESERVED
ITERM
R
0x0
Reserved
R/W
0xC
Reset by:
Termination Current Threshold:
REG_RESET
This 16-bit register follows the little-endian convention.
ITERM[5] falls in REG0x13[0], and ITERM[4:0] falls in
REG0x12[7:3].
POR: 60mA (Ch)
Range: 10mA-620mA (2h-7Ch)
Clamped Low
Bit Step: 10mA (2h)
NOTE: When Q4_FULLON=1, this register has a
minimum value of 120mA, so Reset value becomes
120mA in this case
1:0
RESERVED
R
0x0
Reserved
9.6.2.10 REG0x14_Charge_Control_0 Register (Address = 0x14) [Reset = 0x06]
REG0x14_Charge_Control_0 is shown in Figure 9-25 and described in Table 9-18.
Return to the Summary Table.
Charge Control 0
Figure 9-25. REG0x14_Charge_Control_0 Register
7
6
5
4
3
2
1
0
Q1_FULLON
Q4_FULLON
ITRICKLE
TOPOFF_TMR
R/W-0x0
EN_TERM
VINDPM_BAT_TRAC
K
VRECHG
R-0x0
R/W-0x0
R/W-0x0
R/W-0x1
R/W-0x1
R/W-0x0
Table 9-18. REG0x14_Charge_Control_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
Q1_FULLON
R
0x0
Forces RBFET (Q1) into low resistance state (26 mΩ) ,
regardless of IINDPM setting.
0x0 = RBFET RDSON determined by IINDPM setting
(default)
0x1 = RBFET RDSON is always 26 mΩ
6
5
Q4_FULLON
R/W
R/W
0x0
0x0
Forces BATFET (Q4) into low resistance state (15
mΩ), regardless of ICHG setting. (Only applies when
VBAT > VSYSMIN. Otherwise BATFET operates in
linear mode.)
0x0 = BATFET RDSON determined by charge current
(default)
0x1 = BATFET RDSON is always 15 mΩ
ITRICKLE
Reset by:
REG_RESET
Trickle charging current setting:
0b = 20mA (default)
1b = 80mA
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Table 9-18. REG0x14_Charge_Control_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
4:3
TOPOFF_TMR
R/W
0x0
Reset by:
REG_RESET
Top-off timer control:
0x0 = Disabled (default)
0x1 = 15 mins
0x2 = 30 mins
0x3 = 45 mins
2
1
EN_TERM
R/W
0x1
0x1
Reset by:
REG_RESET
WATCHDOG
Enable termination
0x0 = Disable
0x1 = Enable (default)
VINDPM_BAT_TRA R/W
CK
Reset by:
REG_RESET
Sets VINDPM to track BAT voltage. Actual VINDPM
is higher of the VINDPM register value and VBAT +
VINDPM_BAT_TRACK.
0x0 = Disable function (VINDPM set by register)
0x1 = VBAT + 400 mV (default)
0
VRECHG
R/W
0x0
Reset by:
REG_RESET
Battery Recharge Threshold Offset (Below VREG)
0x0 = 100mV (default)
0x1 = 200mV
9.6.2.11 REG0x15_Charge_Timer_Control Register (Address = 0x15) [Reset = 0x5C]
REG0x15_Charge_Timer_Control is shown in Figure 9-26 and described in Table 9-19.
Return to the Summary Table.
Charge Timer Control
Figure 9-26. REG0x15_Charge_Timer_Control Register
7
6
5
4
3
2
1
0
DIS_STAT
R/W-0x0
EN_AUTO_INDET
R/W-0x1
FORCE_INDET
R/W-0x0
EN_DCP_BIAS
R/W-0x1
TMR2X_EN
R/W-0x1
EN_SAFETY_TMRS
R/W-0x1
PRECHG_TMR
R/W-0x0
CHG_TMR
R/W-0x0
Table 9-19. REG0x15_Charge_Timer_Control Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
DIS_STAT
R/W
0x0
Reset by:
REG_RESET
Disable the STAT pin output
0x0 = Enable (default)
0x1 = Disable
6
EN_AUTO_INDET
R/W
0x1
Reset by:
Automatic D+/D- Detection Enable
REG_RESET
WATCHDOG
0x0 = Disable DPDM detection when VBUS is
plugged-in
0x1 = Enable DPDM detection when VBUS is plugged-
in (default)
5
4
FORCE_INDET
EN_DCP_BIAS
R/W
R/W
0x0
0x1
Reset by:
REG_RESET
WATCHDOG
Force D+/D- detection
0x0 = Do not force DPDM detection (default)
0x1 = Force DPDM algorithm, when DPDM detection
is done, this bit is reset to 0
Reset by:
REG_RESET
WATCHDOG
Enable 600 mV bias on D+ pin whenever DCP is
detected by BC1.2 detection algorithm (VBUS_STAT
= 011b.)
0x0 = Disable 600 mV bias on D+ pin
0x1 = Enable 600 mV bias on D+ pin if DCP detected
3
TMR2X_EN
R/W
0x1
Reset by:
2X charging timer control
REG_RESET
0x0 = Trickle charge, pre-charge and fast charge
timer not slowed by 2X during input DPM or thermal
regulation.
0x1 = Trickle charge, pre-charge and fast charge timer
slowed by 2X during input DPM or thermal regulation
(default)
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Table 9-19. REG0x15_Charge_Timer_Control Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
2
EN_SAFETY_TMRS R/W
0x1
Reset by:
Enable fast charge, pre-charge and trickle charge
REG_RESET
WATCHDOG
timers
0x0 = Disable
0x1 = Enable (default)
1
0
PRECHG_TMR
CHG_TMR
R/W
R/W
0x0
0x0
Reset by:
REG_RESET
Pre-charge safety timer setting
0x0 = 2 hrs (default)
0x1 = 0.5 hrs
Reset by:
REG_RESET
Fast charge safety timer setting
0x0 = 12 hrs (default)
0x1 = 24 hrs
9.6.2.12 REG0x16_Charger_Control_1 Register (Address = 0x16) [Reset = 0xA1]
REG0x16_Charger_Control_1 is shown in Figure 9-27 and described in Table 9-20.
Return to the Summary Table.
Charger Control 1
Figure 9-27. REG0x16_Charger_Control_1 Register
7
6
5
4
3
2
1
0
EN_AUTO_IBATDIS
R/W-0x1
FORCE_IBATDIS
R/W-0x0
EN_CHG
R/W-0x1
EN_HIZ
R/W-0x0
FORCE_PMID_DIS
R/W-0x0
WD_RST
R/W-0x0
WATCHDOG
R/W-0x1
Table 9-20. REG0x16_Charger_Control_1 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
EN_AUTO_IBATDIS R/W
0x1
Reset by:
REG_RESET
Enable the auto battery discharging during the battery
OVP fault
0x0 = The charger does NOT apply a discharging
current on BAT during battery OVP triggered
0x1 = The charger does apply a discharging current on
BAT during battery OVP triggered (default)
6
FORCE_IBATDIS
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Force a battery discharging current (~30mA)
0x0 = IDLE (default)
0x1 = Force the charger to apply a discharging current
on BAT
5
4
EN_CHG
EN_HIZ
R/W
R/W
0x1
0x0
Reset by:
REG_RESET
WATCHDOG
Charger enable configuration
0x0 = Charge Disable
0x1 = Charge Enable (default)
Reset by:
Enable HIZ mode.
0x0 = Disable (default)
0x1 = Enable
REG_RESET
WATCHDOG
Adapter Plug In
3
2
FORCE_PMID_DIS R/W
0x0
0x0
0x1
Reset by:
REG_RESET
WATCHDOG
Force a PMID discharge current (~30mA.)
0x0 = Disable (default)
0x1 = Enable
WD_RST
R/W
R/W
Reset by:
REG_RESET
I2C watch dog timer reset
0x0 = Normal (default)
0x1 = Reset (this bit goes back to 0 after timer reset)
1:0
WATCHDOG
Reset by:
REG_RESET
Watchdog timer setting
0x0 = Disable
0x1 = 40s (default)
0x2 = 80s
0x3 = 160s
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9.6.2.13 REG0x17_Charger_Control_2 Register (Address = 0x17) [Reset = 0x4F]
REG0x17_Charger_Control_2 is shown in Figure 9-28 and described in Table 9-21.
Return to the Summary Table.
Charger Control 2
Figure 9-28. REG0x17_Charger_Control_2 Register
7
6
5
4
3
2
1
0
REG_RST
R/W-0x0
TREG
R/W-0x1
SET_CONV_FREQ
R/W-0x0
SET_CONV_STRN
R/W-0x3
RESERVED
R/W-0x1
VBUS_OVP
R/W-0x1
Table 9-21. REG0x17_Charger_Control_2 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
REG_RST
R/W
0x0
REG_RESET
Reset registers to default values and reset timer
Value resets to 0 after reset completes.
0x0 = Not reset (default)
0x1 = Reset
6
TREG
R/W
0x1
0x0
Reset by:
REG_RESET
Thermal regulation thresholds.
0x0 = 60C
0x1 = 120C (default)
5:4
SET_CONV_FREQ R/W
SET_CONV_STRN R/W
Reset by:
REG_RESET
Adjust switching frequency of the converter
0x0 = Nominal, 1.5 MHz (default)
0x1 = -10%, 1.35 MHz
0x2 = +10%, 1.65 MHz
0x3 = RESERVED
3:2
0x3
Reset by:
Adjust the high side and low side drive strength of the
REG_RESET
converter to adjust efficiency versus EMI.
0x0 = weak
0x1 = normal
0x2 = RESERVED
0x3 = strong
1
0
RESERVED
VBUS_OVP
R/W
R/W
0x1
0x1
Reserved
Reset by:
Sets VBUS overvoltage protection threshold
REG_RESET
0x0 = 6.3 V
0x1 = 18.5 V
9.6.2.14 REG0x18_Charger_Control_3 Register (Address = 0x18) [Reset = 0x04]
REG0x18_Charger_Control_3 is shown in Figure 9-29 and described in Table 9-22.
Return to the Summary Table.
Charger Control 3
Figure 9-29. REG0x18_Charger_Control_3 Register
7
6
5
4
3
2
1
0
RESERVED
EN_OTG
PFM_OTG_DIS
PFM_FWD_DIS
BATFET_CTRL_WV
BUS
BATFET_DLY
BATFET_CTRL
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R-0x0
R/W-0x1
Table 9-22. REG0x18_Charger_Control_3 Register Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Notes
Description
RESERVED
EN_OTG
0x0
Reserved
6
0x0
Reset by:
OTG mode control
REG_RESET
WATCHDOG
0b = OTG Disable (default)
1b = OTG Enable
5
PFM_OTG_DIS
R/W
0x0
Reset by:
REG_RESET
Disable PFM in OTG boost mode
0x0 = Enable (Default)
0x1 = Disable
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Table 9-22. REG0x18_Charger_Control_3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
4
PFM_FWD_DIS
R/W
0x0
Reset by:
REG_RESET
Disable PFM in forward buck mode
0x0 = Enable (Default)
0x1 = Disable
3
2
BATFET_CTRL_WV
BUS
R
0x0
0x1
0x0
Optionally allows batfet off or system power reset with
adapter present.
0x0 = 0x0
0x1 = 0x1
BATFET_DLY
R/W
R/W
Reset by:
REG_RESET
Delay time added to the taking action in bits [1:0] of the
BATFET_CTRL
0x0 = Add 20 ms delay time
0x1 = Add 10s delay time (default)
1:0
BATFET_CTRL
Reset by:
BATFET control
REG_RESET
The control logic of the BATFET to force the device
enter different modes.
0x0 = Normal (default)
0x1 = Shutdown Mode
0x2 = Ship Mode
0x3 = System Power Reset
9.6.2.15 REG0x19_Charger_Control_4 Register (Address = 0x19) [Reset = 0xC0]
REG0x19_Charger_Control_4 is shown in Figure 9-30 and described in Table 9-23.
Return to the Summary Table.
Charger Control 4
Figure 9-30. REG0x19_Charger_Control_4 Register
7
6
5
4
3
2
1
0
IBAT_PK
R/W-0x3
VBAT_UVLO
VBAT_OTG_MIN
EN_9V
EN_12V_or_EN_EXT
ILIM
CHG_RATE
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
Table 9-23. REG0x19_Charger_Control_4 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7:6
IBAT_PK
R/W
0x3
Reset by:
Battery discharging peak current protection threshold
REG_RESET
setting
0x0 = 1.5A
0x1 = 3A
0x2 = 6A
0x3 = 12A (default)
5
VBAT_UVLO
R/W
0x0
Reset by:
REG_RESET
Select the VBAT_UVLO falling threshold and
VBAT_SHORT threshold
0x0 = VBAT_UVLO 2.2V, VBAT_SHORT 2.05V
(default)
0x1 = VBAT_UVLO 1.8V, VBAT_SHORT 1.85V
4
3
VBAT_OTG_MIN
EN_9V
R/W
R/W
0x0
0x0
Reset by:
REG_RESET
Select the minimal battery voltage to start the OTG
mode
0x0 = 3V rising / 2.8 falling (default)
0x1 = 2.6V rising / 2.4 falling
Reset by:
REG_RESET
BQ25620: Enable 9V adapter detection
Host has to set EN_12V=EN_9V=0, followed by proper
setting of EN_12V and EN_9V to start a detection.
After successful 9V detection, if EN_9V is set to
0, charger starts a 12V detection (if EN_12V=1),
or releases D+/D- bias and goes back to DCP (if
EN_12V=0). 0b = Disabled (default)
1b = Enabled
BQ25622: RESERVED with default 0
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Table 9-23. REG0x19_Charger_Control_4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
2
EN_12V_or_EN_EX R/W
TILIM
0x0
Reset by:
REG_RESET
WATCHDOG
BQ25620: Enable 12V adapter detection
If EN_12V = EN_9V = 1, charger attempts 12V
negotiation first. If 12V is detected, charger skips 9V
negotiation.
Host has to set EN_12V = EN_9V = 0, followed
by proper setting of EN_12V and EN_9V to start a
negotiation.
After successful 12V negotiation, if EN_12V is set to 0
and EN_9V stays at 1, charger starts 9V negotiation.
0b = Disabled (default)
1b = Enabled
BQ25622:
Enable the external ILIM pin input current regulation
0b = Disabled
1b = Enabled (default)
1:0
CHG_RATE
R/W
0x0
Reset by:
The charge rate definition for the fast charge stage.
REG_RESET
The charging current fold back value is equal to ICHG
register setting times the fold back ratio, then divided
by the charge rate.
0x0 = 1C (default)
0x1 = 2C
0x2 = 4C
0x3 = 6C
9.6.2.16 REG0x1A_NTC_Control_0 Register (Address = 0x1A) [Reset = 0x3D]
REG0x1A_NTC_Control_0 is shown in Figure 9-31 and described in Table 9-24.
Return to the Summary Table.
NTC Control 0
Figure 9-31. REG0x1A_NTC_Control_0 Register
7
6
5
4
3
2
1
0
TS_IGNORE
R/W-0x0
TS_TH_OTG_HOT
R/W-0x1
TS_TH_OTG_COLD
R/W-0x1
TS_ISET_WARM
R/W-0x3
TS_ISET_COOL
R/W-0x1
Table 9-24. REG0x1A_NTC_Control_0 Register Field Descriptions
Bit
Field
TS_IGNORE
Type
Reset
Notes
Description
7
R/W
0x0
Reset by:
REG_RESET
WATCHDOG
Ignore the TS feedback: the charger considers the TS
is always good to allow charging and OTG modes,
TS_STAT reports TS_NORMAL condition.
0x0 = Not ignore (Default)
0x1 = Ignore
6:5
TS_TH_OTG_HOT R/W
0x1
Reset by:
REG_RESET
OTG Mode TS_HOT rising temperature threshold
to transition from normal operation into suspended
OTG mode when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = 55°C
0x1 = 60°C (default)
0x2 = 65°C
0x3 = Disable
4
TS_TH_OTG_COLD R/W
0x1
Reset by:
REG_RESET
OTG Mode TS_COLD falling temperature threshold
to transition from normal operation into suspended
OTG mode when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = -20°C
0x1 = -10°C (default)
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Table 9-24. REG0x1A_NTC_Control_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
3:2
TS_ISET_WARM
R/W
0x3
Reset by:
REG_RESET
TS_WARM Current Setting
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
1:0
TS_ISET_COOL
R/W
0x1
Reset by:
REG_RESET
TS_COOL Current Setting
0x0 = Charge Suspend
0x1 = Set ICHG to 20% (default)
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged
9.6.2.17 REG0x1B_NTC_Control_1 Register (Address = 0x1B) [Reset = 0x25]
REG0x1B_NTC_Control_1 is shown in Figure 9-32 and described in Table 9-25.
Return to the Summary Table.
NTC Control 1
Figure 9-32. REG0x1B_NTC_Control_1 Register
7
6
5
4
3
2
1
0
TS_TH1_TH2_TH3
R/W-0x1
TS_TH4_TH5_TH6
R/W-0x1
TS_VSET_WARM
R/W-0x1
Table 9-25. REG0x1B_NTC_Control_1 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7:5
TS_TH1_TH2_TH3 R/W
0x1
Reset by:
REG_RESET
TH1, TH2 and TH3 comparator falling temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = TH1 is 0°C, TH2 is 5°C, TH3 is 15°C
0x1 = TH1 is 0°C, TH2 is 10°C, TH3 is 15°C (default)
0x2 = TH1 is 0°C, TH2 is 15°C, TH3 is 20°C
0x3 = TH1 is 0°C, TH2 is 20°C, TH3 20°C
0x4 = TH1 is -5°C, TH2 is 5°C, TH3 is 15°C
0x5 = TH1 is -5°C, TH2 is 10°C, TH3 is 15°C
0x6 = TH1 is -5°C, TH2 is 10°C, TH3 is 20°C
0x7 = TH1 is 0°C, TH2 is 10°C, TH3 is 20°C
4:2
TS_TH4_TH5_TH6 R/W
0x1
Reset by:
REG_RESET
TH4, TH5 and TH6 comparator rising temperature
thresholds when a 103AT NTC thermistor is used,
RT1=5.24kΩ and RT2=30.31kΩ.
0x0 = TH4 is 35°C, TH5 is 40°C, TH6 is 60°C
0x1 = TH4 is 35°C, TH5 is 45°C, TH6 is 60°C (default)
0x2 = TH4 is 35°C, TH5 is 50°C, TH6 is 60°C
0x3 = TH4 is 40°C, TH5 is 55°C, TH6 is 60°C
0x4 = TH4 is 35°C, TH5 is 40°C, TH6 is 50°C
0x5 = TH4 is 35°C, TH5 is 45°C, TH6 is 50°C
0x6 = TH4 is 40°C, TH5 is 45°C, TH6 is 60°C
0x7 = TH4 is 40°C, TH5 is 50°C, TH6 is 60°C
1:0
TS_VSET_WARM
R/W
0x1
Reset by:
TS_WARM Voltage Setting
REG_RESET
0x0 = Set VREG to VREG-300mV
0x1 = Set VREG to VREG-200mV (default)
0x2 = Set VREG to VREG-100mV
0x3 = VREG unchanged
9.6.2.18 REG0x1C_NTC_Control_2 Register (Address = 0x1C) [Reset = 0x3F]
REG0x1C_NTC_Control_2 is shown in Figure 9-33 and described in Table 9-26.
Return to the Summary Table.
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NTC Control 2
Figure 9-33. REG0x1C_NTC_Control_2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
TS_VSET_SYM
R/W-0x0
TS_VSET_PREWARM
R/W-0x3
TS_ISET_PREWARM
R/W-0x3
TS_ISET_PRECOOL
R/W-0x3
Table 9-26. REG0x1C_NTC_Control_2 Register Field Descriptions
Bit
7
Field
Type
Reset
Notes
Description
RESERVED
R
0x0
RESERVED
6
TS_VSET_SYM
R/W
0x0
Reset by:
REG_RESET
When this bit is set to 0, the voltage regulation
for TS_PRECOOL and TS_COOL is unchanged.
When this bit is set to 1, TS_PRECOOL uses
the TS_VSET_PREWARM setting of TS_PREWARM
and TS_COOL uses the TS_VSET_WARM setting of
TS_WARM .
0x0 = VREG unchanged (default)
0x1 = TS_COOLx matches TS_WARMx
5:4
3:2
1:0
TS_VSET_PREWAR R/W
M
0x3
0x3
0x3
Reset by:
REG_RESET
Advanced temperature profile voltage setting for
TS_PREWARM (TH4 - TH5)
0x0 = Set VREG to VREG-300mV
0x1 = Set VREG to VREG-200mV
0x2 = Set VREG to VREG-100mV
0x3 = VREG unchanged (default)
TS_ISET_PREWAR R/W
M
Reset by:
REG_RESET
Advanced temperature profile current setting for
TS_PREWARM zone(TH4 - TH5)
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
TS_ISET_PRECOO R/W
L
Reset by:
REG_RESET
Advanced temperature profile current setting for
TS_PRECOOL zone (TH2 - TH3)
0x0 = Charge Suspend
0x1 = Set ICHG to 20%
0x2 = Set ICHG to 40%
0x3 = ICHG unchanged (default)
9.6.2.19 REG0x1D_Charger_Status_0 Register (Address = 0x1D) [Reset = 0x00]
REG0x1D_Charger_Status_0 is shown in Figure 9-34 and described in Table 9-27.
Return to the Summary Table.
Charger Status 0
Figure 9-34. REG0x1D_Charger_Status_0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
ADC_DONE_STAT
R-0x0
TREG_STAT
R-0x0
VSYS_STAT
R-0x0
IINDPM_STAT
R-0x0
VINDPM_STAT
R-0x0
SAFETY_TMR_STAT
R-0x0
WD_STAT
R-0x0
Table 9-27. REG0x1D_Charger_Status_0 Register Field Descriptions
Bit
7
Field
Type
Reset
Notes
Description
RESERVED
R
0x0
Reserved
6
ADC_DONE_STAT
R
0x0
ADC Conversion Status (in one-shot mode only)
Note: Always reads 0 in continuous mode
0x0 = Conversion not complete
0x1 = Conversion complete
5
TREG_STAT
R
0x0
IC Thermal regulation status
0x0 = Normal
0x1 = Device in thermal regulation
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Table 9-27. REG0x1D_Charger_Status_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
4
VSYS_STAT
R
0x0
VSYS Regulation Status (forward mode)
0x0 = Not in VSYSMIN regulation (BAT>VSYSMIN)
0x1 = In VSYSMIN regulation (BAT<VSYSMIN)
3
2
IINDPM_STAT
VINDPM_STAT
R
R
0x0
0x0
In forward mode, indicates that either IINDPM
regulation is active or ILIM pin regulation is active
In OTG mode, indicates that IOTG regulation is active
0x0 = Normal
0x1 = In IINDPM/ILIM regulation or IOTG regulation
VINDPM status (forward mode) or VOTG status (OTG
mode, backup mode)
0x0 = Normal
0x1 = In VINDPM regulation or VOTG regulation
1
0
SAFETY_TMR_STA
T
R
R
0x0
0x0
Fast charge, trickle charge and pre-charge timer status
0x0 = Normal
0x1 = Safety timer expired
WD_STAT
I2C watch dog timer status
0x0 = Normal
0x1 = WD timer expired
9.6.2.20 REG0x1E_Charger_Status_1 Register (Address = 0x1E) [Reset = 0x00]
REG0x1E_Charger_Status_1 is shown in Figure 9-35 and described in Table 9-28.
Return to the Summary Table.
Charger Status 1
Figure 9-35. REG0x1E_Charger_Status_1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
CHG_STAT
R-0x0
VBUS_STAT
R-0x0
Table 9-28. REG0x1E_Charger_Status_1 Register Field Descriptions
Bit
7:5
4:3
Field
Type
Reset
Notes
Description
RESERVED
CHG_STAT
R
0x0
Reserved
R
0x0
Charge Status bits
0x0 = Not Charging or Charge Terminated
0x1 = Trickle Charge, Pre-charge or Fast charge (CC
mode)
0x2 = Taper Charge (CV mode)
0x3 = Top-off Timer Active Charging
2:0
VBUS_STAT
R
0x0
VBUS status bits
BQ25620:
000b = No qualified adapter, or EN_AUTO_INDET = 0.
001b = USB SDP Adapter (500mA)
010b = USB CDP Adapter (1.5A)
011b = USB DCP Adapter (1.5A)
100b = Unknown Adapter (500mA)
101b = Non-Standard Adapter (1A/2.1A/2.4A)
110b = HVDCP adapter (1.5A)
111b = In boost OTG mode
BQ25622:
100b = Unknown Adapter (default IINDPM setting)
9.6.2.21 REG0x1F_FAULT_Status_0 Register (Address = 0x1F) [Reset = 0x00]
REG0x1F_FAULT_Status_0 is shown in Figure 9-36 and described in Table 9-29.
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Return to the Summary Table.
FAULT Status 0
Figure 9-36. REG0x1F_FAULT_Status_0 Register
7
6
5
4
3
2
1
0
VBUS_FAULT_STAT
R-0x0
BAT_FAULT_STAT
R-0x0
SYS_FAULT_STAT
R-0x0
OTG_FAULT_STAT
R-0x0
TSHUT_STAT
R-0x0
TS_STAT
R-0x0
Table 9-29. REG0x1F_FAULT_Status_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
VBUS_FAULT_STAT R
0x0
VBUS fault status, VBUS OVP and sleep comparator
0x0 = Normal
0x1 = Device not switching due to overvoltage
protection or sleep comparator
6
BAT_FAULT_STAT
R
0x0
BAT fault status, IBAT OCP and VBAT OVP
0x0 = Normal
0x1 = Device in battery overcurrent protection or
battery overvoltage protection
5
4
SYS_FAULT_STAT
OTG_FAULT_STAT
R
R
0x0
0x0
VSYS undervoltage and overvoltage status
0x0 = Normal
0x1 = SYS in SYS short circuit or overvoltage
Reverse-current or undervoltage or overvoltage fault
detected at PMID or VBUS during boost OTG
0x0 = Normal
0x1 = Reverse-current fault or PMID or VBUS in
overvoltage or undervoltage during OTG
3
TSHUT_STAT
TS_STAT
R
R
0x0
0x0
IC temperature shutdown status
0x0 = Normal
0x1 = Device in thermal shutdown protection
2:0
The TS temperature zone.
0x0 = TS_NORMAL
0x1 = TS_COLD or TS_OTG_COLD or TS resistor
string power rail is not available.
0x2 = TS_HOT or TS_OTG_HOT
0x3 = TS_COOL
0x4 = TS_WARM
0x5 = TS_PRECOOL
0x6 = TS_PREWARM
0x7 = TS pin bias reference fault
9.6.2.22 REG0x20_Charger_Flag_0 Register (Address = 0x20) [Reset = 0x00]
REG0x20_Charger_Flag_0 is shown in Figure 9-37 and described in Table 9-30.
Return to the Summary Table.
Charger Flag 0
Figure 9-37. REG0x20_Charger_Flag_0 Register
7
6
5
4
3
2
1
0
RESERVED
ADC_DONE_FLAG
TREG_FLAG
VSYS_FLAG
IINDPM_FLAG
VINDPM_FLAG
SAFETY_TMR_FLA
G
WD_FLAG
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
R-0x0
Table 9-30. REG0x20_Charger_Flag_0 Register Field Descriptions
Bit
7
Field
Type
Reset
Notes
Description
RESERVED
R
0x0
Reserved
6
ADC_DONE_FLAG
R
0x0
ADC conversion flag (only in one-shot mode)
0x0 = Conversion not completed
0x1 = Conversion completed
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Table 9-30. REG0x20_Charger_Flag_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
5
TREG_FLAG
R
0x0
IC Thermal regulation flag
0x0 = Normal
0x1 = TREG signal rising threshold detected
4
3
VSYS_FLAG
R
R
0x0
0x0
VSYS min regulation flag
0x0 = Normal
0x1 = Entered or existed VSYS min regulation
IINDPM_FLAG
Indicates that either the IINDPM regulation loop, ILIM
pin regulation or IOTG regulation loop has been
entered.
0x0 = Normal
0x1 = IINDPM, ILIM or IOTG regulation signal rising
edge detected
2
VINDPM_FLAG
R
0x0
VINDPM or VOTG flag
0x0 = Normal
0x1 = VINDPM or VOTG regulation signal rising edge
detected
1
0
SAFETY_TMR_FLA
G
R
R
0x0
0x0
Fast charge, trickle charge and pre-charge timer flag
0x0 = Normal
0x1 = Fast charge timer expired rising edge detected
WD_FLAG
I2C watchdog timer flag
0x0 = Normal
0x1 = WD timer signal rising edge detected
9.6.2.23 REG0x21_Charger_Flag_1 Register (Address = 0x21) [Reset = 0x00]
REG0x21_Charger_Flag_1 is shown in Figure 9-38 and described in Table 9-31.
Return to the Summary Table.
Charger Flag 1
Figure 9-38. REG0x21_Charger_Flag_1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
CHG_FLAG
R-0x0
RESERVED
R-0x0
VBUS_FLAG
R-0x0
Table 9-31. REG0x21_Charger_Flag_1 Register Field Descriptions
Bit
7:4
3
Field
Type
Reset
Notes
Description
RESERVED
CHG_FLAG
R
0x0
Reserved
R
0x0
Charge status flag
0x0 = Normal
0x1 = Charge status changed
2:1
0
RESERVED
VBUS_FLAG
R
R
0x0
0x0
Reserved
VBUS status flag
0x0 = Normal
0x1 = VBUS status changed
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9.6.2.24 REG0x22_FAULT_Flag_0 Register (Address = 0x22) [Reset = 0x00]
REG0x22_FAULT_Flag_0 is shown in Figure 9-39 and described in Table 9-32.
Return to the Summary Table.
FAULT Flag 0
Figure 9-39. REG0x22_FAULT_Flag_0 Register
7
6
5
4
3
2
1
0
VBUS_FAULT_FLAG BAT_FAULT_FLAG
R-0x0 R-0x0
SYS_FAULT_FLAG
R-0x0
OTG_FAULT_FLAG
R-0x0
TSHUT_FLAG
R-0x0
RESERVED
R-0x0
TS_FLAG
R-0x0
Table 9-32. REG0x22_FAULT_Flag_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
6
5
VBUS_FAULT_FLA
G
R
0x0
VBUS overvoltage or sleep flag
0x0 = Normal
0x1 = Entered VBUS OVP or sleep
BAT_FAULT_FLAG
SYS_FAULT_FLAG
R
R
0x0
0x0
IBAT overcurrent and VBAT overvoltage flag
0x0 = Normal
0x1 = Entered battery discharged OCP or VBAT OVP
VSYS overvoltage and SYS short flag
0x0 = Normal
0x1 = Stopped switching due to system overvoltage or
SYS short fault
4
3
OTG_FAULT_FLAG
TSHUT_FLAG
R
R
0x0
0x0
OTG PMID and VBUS reverse-current, undervoltage
and overvoltage flag
0x0 = Normal
0x1 = Stopped OTG due to reverse-current fault, PMID
undervoltage or overvoltage fault
IC thermal shutdown flag
0x0 = Normal
0x1 = TS shutdown signal rising threshold detected
2:1
0
RESERVED
TS_FLAG
R
R
0x0
0x0
Reserved
TS status flag
0x0 = Normal
0x1 = A change to TS status was detected
9.6.2.25 REG0x23_Charger_Mask_0 Register (Address = 0x23) [Reset = 0x00]
REG0x23_Charger_Mask_0 is shown in Figure 9-40 and described in Table 9-33.
Return to the Summary Table.
Charger Mask 0
Figure 9-40. REG0x23_Charger_Mask_0 Register
7
6
5
4
3
2
1
0
RSERVED
ADC_DONE_MASK
TREG_MASK
VSYS_MASK
IINDPM_MASK
VINDPM_MASK
SAFETY_TMR_MAS
K
WD_MASK
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
Table 9-33. REG0x23_Charger_Mask_0 Register Field Descriptions
Bit
7
Field
RSERVED
Type
Reset
Notes
Description
R/W
0x0
Reserved
6
ADC_DONE_MASK R/W
0x0
Reset by:
REG_RESET
ADC conversion mask flag (only in one-shot mode)
0x0 = ADC conversion done does produce INT pulse
0x1 = ADC conversion done does not produce INT
pulse
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Table 9-33. REG0x23_Charger_Mask_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
5
TREG_MASK
R/W
0x0
Reset by:
IC thermal regulation mask flag
REG_RESET
0x0 = Entering TREG does produce INT
0x1 = Entering TREG does not produce INT
4
3
2
1
VSYS_MASK
R/W
R/W
R/W
0x0
0x0
0x0
0x0
Reset by:
REG_RESET
VSYS min regulation mask flag
0x0 = Enter or exit VSYSMIN regulation does produce
INT pulse
0x1 = Enter or exit VSYSMIN regulation does not
produce INT pulse
IINDPM_MASK
VINDPM_MASK
Reset by:
REG_RESET
IINDPM, ILIM or IOTG mask
0x0 = Enter IINDPM, ILIM or IOTG does produce INT
pulse
0x1 = Enter IINDPM, ILIM or IOTG does not produce
INT pulse
Reset by:
REG_RESET
VINDPM or VOTG mask
0x0 = Enter VINDPM or VOTG does produce INT
pulse
0x1 = Enter VINDPM or VOTG does not produce INT
pulse
SAFETY_TMR_MAS R/W
K
Reset by:
REG_RESET
Fast charge, trickle charge and pre-charge timer mask
flag
0x0 = Fast charge, trickle charge or pre-charge timer
expiration does produce INT
0x1 = Fast charge, trickle charge or pre-charge timer
expiration does not produce INT
0
WD_MASK
R/W
0x0
Reset by:
I2C watch dog timer mask
REG_RESET
0x0 = I2C watch dog timer expired does produce INT
pulse
0x1 = I2C watch dog timer expired does not produce
INT pulse
9.6.2.26 REG0x24_Charger_Mask_1 Register (Address = 0x24) [Reset = 0x00]
REG0x24_Charger_Mask_1 is shown in Figure 9-41 and described in Table 9-34.
Return to the Summary Table.
Charger Mask 1
Figure 9-41. REG0x24_Charger_Mask_1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
CHG_MASK
R/W-0x0
RESERVED
R-0x0
VBUS_MASK
R/W-0x0
Table 9-34. REG0x24_Charger_Mask_1 Register Field Descriptions
Bit
7:4
3
Field
Type
Reset
Notes
Description
RESERVED
CHG_MASK
R
0x0
Reserved
R/W
0x0
Reset by:
Charge status mask flag
REG_RESET
0x0 = Charging status change does produce INT
0x1 = Charging status change does not produce INT
2:1
0
RESERVED
R
0x0
0x0
Reserved
VBUS_MASK
R/W
Reset by:
VBUS status mask flag
REG_RESET
0x0 = VBUS status change does produce INT
0x1 = VBUS status change does not produce INT
9.6.2.27 REG0x25_FAULT_Mask_0 Register (Address = 0x25) [Reset = 0x00]
REG0x25_FAULT_Mask_0 is shown in Figure 9-42 and described in Table 9-35.
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Return to the Summary Table.
FAULT Mask 0
Figure 9-42. REG0x25_FAULT_Mask_0 Register
7
6
5
4
3
2
1
0
VBUS_FAULT_MAS BAT_FAULT_MASK SYS_FAULT_MASK OTG_FAULT_MASK
K
TSHUT_MASK
RESERVED
R-0x0
TS_MASK
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
R/W-0x0
Table 9-35. REG0x25_FAULT_Mask_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
VBUS_FAULT_MAS R/W
K
0x0
Reset by:
REG_RESET
VBUS overvoltage and sleep comparator mask flag
0x0 = Entering VBUS OVP or sleep does produce INT
0x1 = Entering VBUS OVP or sleep does not produce
INT
6
BAT_FAULT_MASK R/W
SYS_FAULT_MASK R/W
OTG_FAULT_MASK R/W
0x0
0x0
0x0
Reset by:
REG_RESET
IBAT overcurrent and VBAT overvoltage mask flag
0x0 = IBAT OCP fault or VBAT OVP fault does
produce INT
0x1 = Neither IBAT OCP fault nor VBAT OVP fault
produces INT
5
4
Reset by:
REG_RESET
SYS overvoltage and SYS short mask
0x0 = System overvoltage or SYS short fault does
produce INT
0x1 = Neither system overvoltage nor SYS short fault
produces INT
Reset by:
REG_RESET
OTG VBUS and PMID reverse-current, undervoltage
and overvoltage mask
0x0 = OTG VBUS or PMID reverse-current,
undervoltage fault or overvoltage fault does produce
INT
0x1 = Neither reverse-current fault, OTG PMID or
VBUS undervoltage nor overvoltage fault produces
INT
3
TSHUT_MASK
R/W
0x0
Reset by:
REG_RESET
IC thermal shutdown mask flag
0x0 = TSHUT does produce INT
0x1 = TSHUT does not produce INT
2:1
0
RESERVED
TS_MASK
R
0x0
0x0
R/W
Reset by:
REG_RESET
Temperature charging profile interrupt mask
0x0 = A change to TS temperature zone does produce
INT
0x1 = A change to the TS temperature zone does not
produce INT
9.6.2.28 REG0x26_ADC_Control Register (Address = 0x26) [Reset = 0x30]
REG0x26_ADC_Control is shown in Figure 9-43 and described in Table 9-36.
Return to the Summary Table.
ADC Control
Figure 9-43. REG0x26_ADC_Control Register
7
6
5
4
3
2
1
0
ADC_EN
R/W-0x0
ADC_RATE
R/W-0x0
ADC_SAMPLE
R/W-0x3
ADC_AVG
R/W-0x0
ADC_AVG_INIT
R/W-0x0
RESERVED
R-0x0
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Table 9-36. REG0x26_ADC_Control Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
ADC_EN
R/W
0x0
Reset by:
ADC Control
REG_RESET
WATCHDOG
The registers POR to all 0 's, then after that always
retain the last measurement, and never clear.
0x0 = Disable (default)
0x1 = Enable
6
ADC_RATE
R/W
R/W
0x0
0x3
Reset by:
REG_RESET
ADC conversion rate control
0x0 = Continuous conversion (default)
0x1 = One shot conversion
5:4
ADC_SAMPLE
Reset by:
ADC sample speed
REG_RESET
0x0 = 12 bit effective resolution
0x1 = 11 bit effective resolution
0x2 = 10 bit effective resolution
0x3 = 9 bit effective resolution (default)
3
2
ADC_AVG
R/W
R/W
0x0
0x0
Reset by:
REG_RESET
ADC average control
0x0 = Single value (default)
0x1 = Running average
ADC_AVG_INIT
Reset by:
REG_RESET
ADC average initial value control
0x0 = Start average using the existing register value
(default)
0x1 = Start average using a new ADC conversion
1:0
RESERVED
R
0x0
Reserved
9.6.2.29 REG0x27_ADC_Function_Disable_0 Register (Address = 0x27) [Reset = 0x00]
REG0x27_ADC_Function_Disable_0 is shown in Figure 9-44 and described in Table 9-37.
Return to the Summary Table.
ADC Function Disable 0
Figure 9-44. REG0x27_ADC_Function_Disable_0 Register
7
6
5
4
3
2
1
0
IBUS_ADC_DIS
R/W-0x0
IBAT_ADC_DIS
R/W-0x0
VBUS_ADC_DIS
R/W-0x0
VBAT_ADC_DIS
R/W-0x0
VSYS_ADC_DIS
R/W-0x0
TS_ADC_DIS
R/W-0x0
TDIE_ADC_DIS
R/W-0x0
VPMID_ADC_DIS
R/W-0x0
Table 9-37. REG0x27_ADC_Function_Disable_0 Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
7
IBUS_ADC_DIS
IBAT_ADC_DIS
VBUS_ADC_DIS
VBAT_ADC_DIS
VSYS_ADC_DIS
TS_ADC_DIS
R/W
0x0
Reset by:
REG_RESET
IBUS ADC control
0x0 = Enable (Default)
0x1 = Disable
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
Reset by:
REG_RESET
IBAT ADC control
0x0 = Enable (Default)
0x1 = Disable
Reset by:
REG_RESET
VBUS ADC control
0x0 = Enable (Default)
0x1 = Disable
Reset by:
REG_RESET
VBAT ADC control
0x0 = Enable (Default)
0x1 = Disable
Reset by:
REG_RESET
VSYS ADC control
0x0 = Enable (Default)
0x1 = Disable
Reset by:
TS ADC control
REG_RESET
0x0 = Enable (Default)
0x1 = Disable
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Table 9-37. REG0x27_ADC_Function_Disable_0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Notes
Description
1
TDIE_ADC_DIS
R/W
0x0
Reset by:
REG_RESET
TDIE ADC control
0x0 = Enable (Default)
0x1 = Disable
0
VPMID_ADC_DIS
R/W
0x0
Reset by:
REG_RESET
VPMID ADC control
0x0 = Enable (Default)
0x1 = Disable
9.6.2.30 REG0x28_IBUS_ADC Register (Address = 0x28) [Reset = 0x0000]
REG0x28_IBUS_ADC is shown in Figure 9-45 and described in Table 9-38.
Return to the Summary Table.
IBUS ADC
Figure 9-45. REG0x28_IBUS_ADC Register
15
7
14
6
13
12
11
10
9
1
8
IBUS_ADC
R-0x0
5
4
3
2
0
IBUS_ADC
R-0x0
RESERVED
R-0x0
Table 9-38. REG0x28_IBUS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:1
IBUS_ADC
R
0x0
IBUS ADC reading
Reported in 2 's Complement.
When the current is flowing from VBUS to PMID, IBUS
ADC reports positive value, and when the current
is flowing from PMID to VBUS, IBUS ADC reports
negative value.
POR: 0mA (0h)
Format: 2s Complement
Range: -4000mA-4000mA (7830h-7FFFh), (0h-7D0h)
Clamped Low
Clamped High
Bit Step: 2mA
0
RESERVED
R
0x0
Reserved
9.6.2.31 REG0x2A_IBAT_ADC Register (Address = 0x2A) [Reset = 0x0000]
REG0x2A_IBAT_ADC is shown in Figure 9-46 and described in Table 9-39.
Return to the Summary Table.
IBAT ADC
Figure 9-46. REG0x2A_IBAT_ADC Register
15
7
14
6
13
12
11
10
9
1
8
0
IBAT_ADC
R-0x0
5
4
3
2
IBAT_ADC
R-0x0
RESERVED
R-0x0
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Table 9-39. REG0x2A_IBAT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:2
IBAT_ADC
R
0x0
IBAT ADC reading
Reported in 2 's Complement.
The IBAT ADC reports positive value for the battery
charging current, and negative value for the battery
discharging current.
The IBAT ADC resets to zero when EN_CHG=0.
POR: 0mA (0h)
Format: 2s Complement
Range: -7500mA-4000mA (38ADh-3FFFh), (0h-3E8h)
Clamped Low
Clamped High
Bit Step: 4mA
If polarity of battery current changes from charging
to discharging or vice-versa during the ADC
measurement, the conversion is aborted and the
register reports code 0x8000 (which is code 0x2000
for IBAT_ADC field)
1:0
RESERVED
R
0x0
Reserved
9.6.2.32 REG0x2C_VBUS_ADC Register (Address = 0x2C) [Reset = 0x0000]
REG0x2C_VBUS_ADC is shown in Figure 9-47 and described in Table 9-40.
Return to the Summary Table.
VBUS ADC
Figure 9-47. REG0x2C_VBUS_ADC Register
15
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
VBUS_ADC
R-0x0
7
5
4
3
2
VBUS_ADC
R-0x0
RESERVED
R-0x0
Table 9-40. REG0x2C_VBUS_ADC Register Field Descriptions
Bit
15
Field
Type
Reset
Notes
Description
RESERVED
VBUS_ADC
R
0x0
Reserved
14:2
R
0x0
VBUS ADC reading
POR: 0mV (0h)
Range: 0mV-19850mV (0h-1388h)
Clamped High
Bit Step: 3.97mV
1:0
RESERVED
R
0x0
Reserved
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9.6.2.33 REG0x2E_VPMID_ADC Register (Address = 0x2E) [Reset = 0x0000]
REG0x2E_VPMID_ADC is shown in Figure 9-48 and described in Table 9-41.
Return to the Summary Table.
VPMID ADC
Figure 9-48. REG0x2E_VPMID_ADC Register
15
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
VPMID_ADC
R-0x0
7
5
4
3
2
VPMID_ADC
R-0x0
RESERVED
R-0x0
Table 9-41. REG0x2E_VPMID_ADC Register Field Descriptions
Bit
15
Field
Type
Reset
Notes
Description
RESERVED
VPMID_ADC
R
0x0
Reserved
14:2
R
0x0
VPMID ADC reading
POR: 0mV (0h)
Range: 0mV-19850mV (0h-1388h)
Clamped High
Bit Step: 3.97mV
1:0
RESERVED
R
0x0
Reserved
9.6.2.34 REG0x30_VBAT_ADC Register (Address = 0x30) [Reset = 0x0000]
REG0x30_VBAT_ADC is shown in Figure 9-49 and described in Table 9-42.
Return to the Summary Table.
VBAT ADC
Figure 9-49. REG0x30_VBAT_ADC Register
15
7
14
13
12
11
10
9
1
8
RESERVED
R-0x0
VBAT_ADC
R-0x0
6
5
4
3
2
0
VBAT_ADC
R-0x0
RESERVED
R-0x0
Table 9-42. REG0x30_VBAT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:13
12:1
RESERVED
VBAT_ADC
R
0x0
Reserved
R
0x0
VBAT ADC reading
POR: 0mV (0h)
Range: 0mV-5572mV (0h-AF0h)
Clamped High
Bit Step: 1.99mV
0
RESERVED
R
0x0
Reserved
9.6.2.35 REG0x32_VSYS_ADC Register (Address = 0x32) [Reset = 0x0000]
REG0x32_VSYS_ADC is shown in Figure 9-50 and described in Table 9-43.
Return to the Summary Table.
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VSYS ADC
Figure 9-50. REG0x32_VSYS_ADC Register
15
14
13
12
11
10
9
1
8
RESERVED
R-0x0
VSYS_ADC
R-0x0
7
6
5
4
3
2
0
VSYS_ADC
R-0x0
RESERVED
R-0x0
Table 9-43. REG0x32_VSYS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:13
12:1
RESERVED
VSYS_ADC
R
0x0
Reserved
R
0x0
VSYS ADC reading
POR: 0mV (0h)
Range: 0mV-5572mV (0h-AF0h)
Clamped High
Bit Step: 1.99mV
0
RESERVED
R
0x0
Reserved
9.6.2.36 REG0x34_TS_ADC Register (Address = 0x34) [Reset = 0x0000]
REG0x34_TS_ADC is shown in Figure 9-51 and described in Table 9-44.
Return to the Summary Table.
TS ADC
Figure 9-51. REG0x34_TS_ADC Register
15
7
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
TS_ADC
R-0x0
5
4
3
2
TS_ADC
R-0x0
Table 9-44. REG0x34_TS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:12
11:0
RESERVED
TS_ADC
R
0x0
Reserved
R
0x0
Reset by:
Adapter Plug In
TS ADC reading as TS pin voltage in percentage of
bias reference. Valid with TS pin bias reference active.
POR: 0%(0h)
Range: 0% - 98.3103% (0h-3FFh)
Clamped High
Bit Step: 0.0961%
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9.6.2.37 REG0x36_TDIE_ADC Register (Address = 0x36) [Reset = 0x0000]
REG0x36_TDIE_ADC is shown in Figure 9-52 and described in Table 9-45.
Return to the Summary Table.
TDIE ADC
Figure 9-52. REG0x36_TDIE_ADC Register
15
7
14
6
13
12
11
10
9
1
8
0
RESERVED
R-0x0
TDIE_ADC
R/W-0x0
5
4
3
2
TDIE_ADC
R/W-0x0
Table 9-45. REG0x36_TDIE_ADC Register Field Descriptions
Bit
Field
Type
Reset
Notes
Description
15:12
11:0
RESERVED
TDIE_ADC
R
0x0
Reserved
R/W
0x0
TDIE ADC reading
Reported in 2 's Complement.
POR: 0°C(0h)
Format: 2s Complement
Range: -40°C - 150°C (FB0h-12Ch)
Clamped Low
Clamped High
Bit Step: 0.5°C
9.6.2.38 REG0x38_Part_Information Register (Address = 0x38) [Reset = 0x02]
REG0x38_Part_Information is shown in Figure 9-53 and described in Table 9-46.
Return to the Summary Table.
Part Information
Figure 9-53. REG0x38_Part_Information Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
PN
DEV_REV
R-0x2
R-0x0
Table 9-46. REG0x38_Part_Information Register Field Descriptions
Bit
7:6
5:3
Field
Type
Reset
Notes
Description
RESERVED
PN
R
0x0
Reserved
R
0x0
Device Part number
All the other options are reserved
0h = BQ25620
1h = BQ25622
2:0
DEV_REV
R
0x2
Device Revision
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device
and a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphone and
other portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET,
Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
10.2 Typical Application
Q1
Q2
System
Load
1 uH
3.9 - 18 V
1 µF
SW
VBUS
VBUS
47 nF
BTST
20uF
Q3
4.7 µF
REGN
PMID
0.1 µF
10 µF
GND
SYS
1.85 - 4.85 V
D+
D-
Q4
USB
10 µF
1.8 - 4.8 V
BAT
TS
REGN
SYS
SYS
STAT
PG
VREF
BQ25620
SYS
SDA
SCL
INT
CE
QON
Host
Optional
Figure 10-1. BQ25620 Application Diagram
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Q1
Q2
System
Load
1 uH
3.9 - 18 V
SW
VBUS
VBUS
1 µF
47 nF
BTST
20uF
Q3
4.7 µF
REGN
PMID
10 µF
0.1 µF
GND
SYS
1.85 - 4.85 V
1.8 - 4.8 V
ILIM
Q4
10 µF
BAT
SYS
SYS
TS_BIAS
TS
STAT
PG
VREF
BQ25622
SYS
SDA
SCL
INT
CE
QON
Host
Optional
Figure 10-2. BQ25622 Application Diagram
10.2.1 Design Requirements
Table 10-1. Design Requirements
PARAMETER
VALUE
3.9 -18.0 V
3200 mA
3040 mA
3520 mV
4200 mV
VBUS range
Input current limit (REG0x06-0x07)
Fast charge current (REG0x02-0x03)
Minimum system voltage (REG0x0E-0x0F)
Battery regulation voltage (REG0x04-0x05)
10.2.2 Detailed Design Procedure
10.2.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ≥ ICHG + (1/2) IRIPPLE
(4)
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The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(5)
The maximum inductor ripple current occurs when the duty cycle (D) is approximately 0.5. Usually inductor ripple
is designed between 20% and 40% of the maximum charging current as a trade-off between inductor size and
efficiency.
10.2.2.2 Input Capacitor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using Equation 6.
ICIN = ICHG ´ D ´ (1- D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET (PMID) and source of the low-side MOSFET
(GND). Voltage rating of the capacitor must be higher than normal input voltage level. A rating of 25-V or higher
capacitor is preferred for 15 V input voltage. 10-μF ceramic capacitor is suggested for typical of 3.5A charging
current.
10.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
Equation 7 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(7)
(8)
The output capacitor voltage ripple can be calculated as follows:
V
V
SYS
SYS
8 × L × C
ΔV
=
1 −
V
SYS
2
VBUS
× f
SW
SYS
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for ≥ 10-μF ceramic output capacitor. The
preferred ceramic capacitor is 10-V rating, X7R or X5R.
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10.2.3 Application Curves
VVBUS = 5 V
ICHG = 1 A
VBAT = 3.2 V
VVBUS = 5 V
ICHG = 1 A
VBAT = 3.2 V
Figure 10-3. Power-Up with Charge Enabled
Figure 10-4. Power-Down
VVBUS = 5 V
ICHG = 1 A
VBAT = 3.2 V
VVBUS = 5 V
ICHG = 1 A
VBAT = 3.2 V
Figure 10-5. Charge Enable
Figure 10-6. Charge Disable
VBAT = 3.2 V
VVBUS = 5 V
ICHG = 480mA
VBAT = 3.2 V
Figure 10-7. System Reset by QON without VBUS
Present
Figure 10-8. System Reset by QON with VBUS
Present
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VVBUS = 5 V
ISYS = 50 mA
VBAT = 3.2 V
VVBUS = 5 V
ICHG = 1 A
VVBAT = 3.2 V
Charge Disabled
Figure 10-9. PFM Switching in Buck Mode
Figure 10-10. PWM Switching in Buck Mode
VBAT = 3.8 V
VBOOST = 5.04 V
VVBUS = 5 V
VBAT = 3.2 V
IBOOST = 100 mA
ISYS from 0 A to 1 A
Charge Disabled
Figure 10-12. Boost Mode Power Up
Figure 10-11. System Load Transient
VBAT = 3.8 V
IBOOST = 100 mA
VBOOST = 5.04V
VBAT = 3.8 V
IBOOST= 50 mA
VBOOST = 5.04V
Figure 10-13. Boost Mode Power Down
Figure 10-14. PFM Switching in Boost Mode
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VBAT = 3.8 V
IBOOST= 1 A
VBOOST = 5.04V
VBAT = 3.8 V
VBOOST = 5.04 V
IBOOST from 0 A to 0.5 A
Figure 10-15. PWM Switching in Boost Mode
Figure 10-16. Boost Mode Load Transient
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11 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 18.0
V input with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage >
VBATUVLO connected to BAT.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for lowest switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. For lowest switching noise during forward/charge mode, place the decoupling capacitor CPMID1 and then
bulk capacitor CPMID2 positive terminals as close as possible to PMID pin. Place the capacitor ground
terminal close to the GND pin using the shortest copper trace connection or GND plane on the same layer
as the IC. See Figure 12-2.
2. For lowest switching noise during reverse/OTG mode, place the CSYS1 and CSYS2 output capacitors'
positive terminals near the SYS pin. The capacitors' ground terminals must be via'd down through multiple
vias to an all ground internal layer that returns to IC GND pin through multiple vias under the IC. See Figure
12-2.
3. Since REGN powers the internal gate drivers, place the CREGN capacitor positive terminal close to REGN
pin to minimize switching noise. The capacitor's ground terminal must be via'd down through multiple vias to
an all ground internal layer that returns to IC GND pin through multiple vias under the IC. See Figure 12-2.
4. Place the CVBUS and CBAT capacitors positive terminals as close to the VBUS and BAT pins as possible.
The capacitors' ground terminals must be via'd down through multiple vias to an all ground internal layer that
returns to IC GND pin through multiple vias under the IC. See Figure 12-2.
5. Place the inductor input pin near the positive terminal of the SYS pin capacitors. Due to the PMID capacitor
placement requirements, the inductor's switching node terminal must be via'd down with multiple via's to
a second internal layer with a wide trace that returns to the SW pin with multiple vias. See Figure 12-3.
Using multiple vias ensures that the via's additional resistance is negligible compared to the inductor's
dc resistance and therefore does not impact efficiency. The vias additional series inductance is negligible
compared to the inductor's inductance.
6. Place the BTST capacitor on the opposite side from the IC using vias to connect to the BTST pin and SW
node. See Figure 12-4.
7. A separate analog GND plane for non-power related resistors and capacitors is not required if those
components are placed away from the power components traces and planes.
8. Ensure that the I2C SDA and SCL lines are routed away from the SW node.
Additionally, it is important that the PCB footprint and solder mask for BQ25620 cover the entire length of each
of the pins. GND, SW, PMID, SYS and BAT pins extend further into the package than the other pins. Using the
entire length of these pins reduces parasitic resistance and increases thermal conductivity from the package into
the board.
12.2 Layout Example
+
+
œ
Figure 12-1. High Frequency Current Path
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Figure 12-2. Layout Example: Top Layer (red) and All PGND Internal Layer 2 (brown)
Figure 12-3. Layout Example: Inner Layer 3 (AGND pour; SW node pour; signal routing)
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Figure 12-4. Layout Example: Bottom Layer X-Ray From Top (PGND pour; BTST capacitor; redundant
SW, SYS and BAT pours)
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
BQ25601 and BQ25601D (PWR877) Evaluation Module User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25620RYKR
BQ25622RYKR
ACTIVE
ACTIVE
WQFN-HR
WQFN-HR
RYK
RYK
18
18
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ620
BQ622
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25620RYKR
BQ25622RYKR
WQFN-
HR
RYK
RYK
18
18
3000
3000
180.0
12.4
2.8
3.3
1.1
4.0
12.0
Q2
WQFN-
HR
180.0
12.4
2.8
3.3
1.1
4.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25620RYKR
BQ25622RYKR
WQFN-HR
WQFN-HR
RYK
RYK
18
18
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
WQFN-HR - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RYK0018A
3.1
2.9
B
A
PIN 1 INDEX AREA
2.6
2.4
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
0.525
0.325
3X
0.5
0.3
5X
PKG
0.675
0.475
2X
0.725
2X
0.6
0.525
(0.1) TYP
4X
0.4
9
6
0.9
0.7
10
2X 0.85
5X
5
2X 0.407
2X 0.007
0
PKG
2X 0.393
2X 0.85
1
14
0.25
0.15
22X
15
18
0.519
0.319
0.1
C A B
C
0.05
PIN 1 ID (OPTIONAL)
4226526/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
WQFN-HR - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RYK0018A
2X (0.775)
(0.619)
PKG
2X (0.825)
15
18
(1.141)
4X (0.7)
5X (1)
2X (0.95)
1
14
2X (0.85)
2X (0.393)
PKG
(0)
2X (0.007)
2X (0.407)
22X (0.2)
(R 0.05) TYP
10
5
2X (1.1)
(1.15)
9
6
5X (0.6)
3X (0.625)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226526/A 02/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
WQFN-HR - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
RYK0018A
2X (0.775)
(0.619)
PKG
2X (0.825)
15
18
(1.141)
4X (0.7)
1
5X (1)
2X (0.95)
14
2X (0.85)
2X (0.393)
PKG
(0)
2X (0.007)
2X (0.407)
22X (0.2)
(R 0.05) TYP
10
5
2X (1.1)
(1.15)
9
6
5X (0.6)
3X (0.625)
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 20X
4226526/A 02/2021
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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