BQ25618_技术文档

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

BQ25618/619 具有20mA 终止电流和1A 升压电流的I²C 控制型单芯1.5A 电池充

电器

1 特性

2 应用

• 单芯片解决方案，可以通过适配器或电池为可穿戴

附件充电

• 消费类可穿戴设备、智能手表

• 个人护理和健身

• 耳麦/耳机

• 高效1.5MHz 同步开关模式降压充电器

• 耳塞（真正无线或TWS）充电盒

• 助听器充电盒

– 0.5A 时充电效率为95.5%，1A 时充电效率为

94.5%

– ±0.5% 充电电压调节（10mV 阶跃）

– 充电电压、电流和温度阈值的I²C 可编程JEITA

曲线

3 说明

BQ25618/619 将充电、升压转换器和电压保护功能集

成在单个器件中。该器件为开关充电器提供了业界最低

的终端电流，从而以最大电池容量为可穿戴设备充电。

BQ25618/619 具有出色的低静态电流，可在运输模式

下将电池泄漏降低至 6uA，从而节约电池电量，将器

件的货架期延长一倍。BQ25619 采用 4x4 QFN 封

装，以便于布局。BQ25618 采用 2.0x2.4mm2 WCSP

封装，以支持空间受限的设计。

– 高精度低终止电流20mA±10mA

– 2.5 x 2.0 x 1.0mm³的小电感器尺寸

• 输出范围为4.6V 至5.15V 的升压模式

– 在1A 输出下具有94% 的升压效率

– 集成控制功能，可实现充电模式与升压模式间的

切换

– PMID_GOOD 引脚控制外部PMOS FET，用于

针对故障情况提供保护

器件信息

封装⁽¹⁾

DSBGA (30)

WQFN (24)

封装尺寸（标称值）

2.00mm × 2.40mm

4.00mm × 4.00mm

• 单个输入，支持USB 输入以及高电压适配器或无线

电源

器件型号

BQ25618

BQ25619

– 支持4V 至13.5V 输入电压范围，绝对最大输入

额定值为22V

– 通过I²C（100mA 至3.2A，100mA/阶跃）实

现可编程输入电流限制(IINDPM)

– 通过高达5.4V 的输入电压限制(VINDPM) 进行

最大功率跟踪

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Ear

PMID

Buds

Adapter

Or

Wireless RX

4V œ 13.5V

– 通过VINDPM 阈值自动跟踪电池电压

• 窄VDC (NVDC) 电源路径管理

VBUS

SYS 3.5V-4.6V

SW

I²C Bus

– 无需电池或使用深度放电的电池即可使系统瞬时

启动

• 灵活的I²C 配置和自主充电，可实现出色的系统性

能

Host

SYS

BAT

Host Control

I_CHG

REGN

+

QON

• 高集成度包括所有MOSFET、电流感应和环路补偿

• 低R_DSON19.5mΩBATFET，可更大程度地降低充

电损耗和延长电池运行时间

Optional

TS

– 提供用于运输模式的BATFET 控制，以及使用

和不使用适配器的完全系统复位功能

• 运输模式下具有7µA 低电池泄漏电流

• 在系统待机时具有9.5µA 的低电池泄漏电流

• 高精度电池充电曲线

简化版应用

– ±6% 充电电流调节

– ±7.5% 输入电流调节

– 远程电池检测，可更快地进行充电

– 用于电池完全充电的可编程充电完成计时器

• 安全相关认证：

– 经IEC 62368-1 CB 认证

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDF8

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................31

8.5 Register Maps...........................................................32

9 Application and Implementation..................................46

9.1 Application Information............................................. 46

9.2 Typical Application.................................................... 46

10 Power Supply Recommendations..............................50

11 Layout...........................................................................51

11.1 Layout Guidelines................................................... 51

11.2 Layout Example...................................................... 51

12 Device and Documentation Support..........................53

12.1 Device Support....................................................... 53

12.2 Documentation Support.......................................... 53

12.3 接收文档更新通知................................................... 53

12.4 支持资源..................................................................53

12.5 Trademarks.............................................................53

12.6 Electrostatic Discharge Caution..............................53

12.7 术语表..................................................................... 53

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings........................................ 7

7.2 ESD Ratings............................................................... 7

7.3 Recommended Operating Conditions.........................7

7.4 Thermal Information....................................................8

7.5 Thermal Information....................................................8

7.6 Electrical Characteristics.............................................8

7.7 Timing Requirements................................................13

7.8 Typical Characteristics..............................................14

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................17

Information.................................................................... 54

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (June 2021) to Revision D (December 2021)

Page

• Deleted t_{SU_STA}, t_{HD_DAT}, t_rDA, and t_fDAfrom Timing Requirements.................................................................. 13

Changes from Revision B (September 2019) to Revision C (June 2021)

Page

• 添加了“安全相关认证：经IEC 62368-1 CB 认证............................................................................................. 1

• Changed REG2 ICHG[5:0] 111100: 1430 mA to 111110: 1430 mA and 111100: 1500 mA to 111111: 1500 mA...

32

Changes from Revision A (July 2019) to Revision B (September 2019)

Page

• 添加了BQ25618.................................................................................................................................................1

Changes from Revision * (June 2019) to Revision A (July 2019)

Page

• 将“预告信息”更改为“量产数据”.................................................................................................................. 1

2

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

5 说明（续）

BQ25619/618 是一款高度集成的 1.5A 开关模式电池充电管理和系统电源路径管理器件，适用于锂离子和锂聚合

物电池。它可为可穿戴设备、耳机充电盒等各种应用提供快速充电功能和高输入电压。其低阻抗电源路径对开关

模式运行效率进行了优化，缩短了电池充电时间并延长了放电阶段的电池运行时间。其输入电压和电流调节、低

终止电流和电池远程检测可以为电池提供最大的充电功率。该解决方案在系统和电池之间高度集成输入反向阻断

FET（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以及电池 FET

（BATFET、Q4）。它还集成了自举二极管以进行高侧栅极驱动，从而简化系统设计。具有充电和系统设置的I²C

串行接口使该器件成为一个真正灵活的解决方案。

该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口、兼容 USB 的高电压适配器和无线电源。该器

件符合 USB 2.0 和USB 3.0 电源规格，具有输入电流和电压调节功能。该器件从系统检测电路（如USB PHY 器

件）获取结果。

该器件通过单个电感器将降压充电器和升压稳压器集成在一个解决方案中。升压模式在PMID 引脚上提供5V 电压

（4.6V/4.75V/5V/5.15V 可调）。升压模式用于节省 BOM，可通过控制 PMID_GOOD 来为另一个电池充电。

PMID_GOOD 引脚用于驱动外部PMOS FET，将升压输出PMID 与所连附件断开。

在应用适配器时，电源路径管理将系统电压调节至稍高于电池电压的水平，但不会降至最小系统电压 3.5V 以下

（可编程）。借助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电

流限值或电压限值时，电源路径管理系统会自动减小充电电流。随着系统负载持续增加，电池开始放电，直到满

足系统电源需求。该补充模式可防止输入源过载。

此器件在无需软件控制情况下启动并完成一个充电周期。它感应电池电压并通过三个阶段为电池充电：预充电、

恒定电流和恒定电压。在充电周期的末尾，当充电电流低于预设限值并且电池电压高于再充电阈值时，充电器自

动终止。如果充满电的电池降至再充电阈值以下，则充电器自动开启另一个充电周期。

此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性计

时器以及过压和过流保护。当结温超过 110°C 时，热调节会减小充电电流。状态寄存器报告充电状态和任何故障

状况。通过I²C，VBUS_GD 位指示电源是否正常，而且在发生故障时INT 输出会立即通知主机。

该器件还提供用于BATFET 使能和复位控制的QON 引脚，用来退出低功耗运输模式或完全系统复位功能。

BQ25619 器件采用 24 引脚 4mm × 4mm x 0.75mm 薄型 WQFN 封装，BQ25618 采用 30 焊球 2.0mm × 2.4mm

WCSP 封装。

Submit Document Feedback

3

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

6 Pin Configuration and Functions

1

2

3

4

5

GND

SW

PMID

VBUS

VAC

A

GND

SW

SYS

PMID

BTST

TS

VBUS

REGN

/QON

SDA

NC

B

BAT

PSEL

C

PMID_

GOOD

BAT

D

BAT

/CE

STAT

E

BAT

SYS

BATSNS

/INT

SCL

F

图6-1. BQ25618 YFF Package 30-Pin WCSP Top View

24

23

22

21

20

19

1

2

3

4

5

6

18

VAC

PSEL

PGND

17 PGND

16 SYS

PMID_GOOD

STAT

BQ25619

15

14 BAT

13

SYS

SCL

SDA

BAT

7

8

9

10

11

12

图6-2. BQ25619 RTW Package 24-Pin WQFN Top View

4

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

表6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

BQ25618 NO.

BQ25619 NO.

13

Battery connection point to the positive terminal of the battery pack. The internal

current sensing resistor is connected between SYS and BAT. Connect a 10 µF

closely to the BAT pin.

BAT

C1, D1, E1, F1

P

AIO

P

14

10

Battery voltage sensing pin for charge voltage regulation. In order to minimize

the parasitic trace resistance during charging, BATSNS pin is connected to the

positive terminal of battery pack as close as possible. If BATSNS pin is open or

short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery

voltage through BAT pin.

BATSNS

F3

PWM high-side driver positive supply. Internally, the BTST is connected to the

cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor from

SW to BTST.

BTST

C3

21

CE

E3

9

DI

P

Charge enable pin. When this pin is driven LOW, battery charging is enabled.

17

18

GND

A1, B1

Ground

Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ

resistor. The INT pin sends an active low, 256-µs pulse to the host to report

charger device status and fault.

INT

NC

F4

B5

7

8

DO

Not connected

Boost mode output. Connected to the drain of the reverse blocking MOSFET

(RBFET) and the drain of HSFET. Consider the total input capacitance, put 1 μF

on VBUS to GND, and the rest capacitance on PMID to GND (typical 2x4.7 μF

plus 1 nF).

PMID

A3, B3

23

Open drain active high PMID good indicator. Connect to the pullup rail REGN

through 10-kΩresistor. HIGH indicates PMID voltage is below 5.2 V and the

current through Q1 is below 110% of input current limit. This signal can be used

to drive external PMOS FET to disconnect the PMID under charging load when

Boost mode output voltage is too high or output current is too high.

PMID_GOOD

PSEL

D5

C5

3

2

DO

DI

Power source selection input. HIGH indicates 500-mA input current limit. LOW

indicates 2.4-A input current limit. Once the device gets into Host mode, the host

can program a different input current limit to the IINDPM register.

BATFET enable/reset control input. When the BATFET is in Ship mode, a logic

LOW of t_SHIPMODEduration turns on BATFET to exit Ship mode. When the

BATFET is not in Ship mode, a logic LOW of t_{QON_RST}(minimum 8 s) duration

resets SYS (system power) by turning BATFET off for t_{BATFET_RST}(minimum 250

ms) and then re-enables BATFET to provide full system power reset. The host

chooses the BATFET reset function with VBUS unplug or not through I²C bit

BATFET_RST_WVBUS. The pin is pulled up to V_BATthrough 200 kΩto maintain

default HIGH logic during Ship mode. It has an internal clamp to 6.5 V.

QON

D4

12

DI

PWM low-side driver positive supply output. Internally, REGN is connected to the

anode of the bootstrap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor

from REGN to analog GND. The capacitor should be placed close to the IC.

REGN

C4

22

P

I²C interface clock. Connect SCL to the logic rail through a 10-kΩresistor.

I²C interface data. Connect SDA to the logic rail through a 10-kΩresistor.

SCL

SDA

F5

E4

5

6

DI

DIO

Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ

resistor. The STAT pin indicates charger status.

Charge in progress: LOW

STAT

E5

4

DO

Charge complete or charger in Sleep mode: HIGH

Charge suspend (fault response): Blink at 1 Hz

19

20

Switching node connecting to output inductor. Internally SW is connected to the

source of the n-channel HSFET and the drain of the n-channel LSFET. Connect

the 0.047-μF bootstrap capacitor from SW to BTST.

SW

A2, B2

P

15

16

Converter output connection point. The internal current sensing resistor is

connected between SYS and BAT. Connect a 10 µF (min) closely to the SYS pin.

SYS

C2, D2, E2, F2

Battery temperature qualification voltage input. Connect a negative temperature

coefficient thermistor (NTC). Program temperature window with a resistor divider

from REGN to TS to GND. Charge and Boost mode suspend when TS pin

voltage is out of range. When TS pin is not used, connect a 10-kΩresistor from

REGN to TS and a 10-kΩresistor from TS to GND or set TS_IGNORE to HIGH

to ignore TS pin. It is recommended to use a 103AT-2 thermistor.

TS

D3

A5

11

1

AI

VAC

Input voltage sensing. This pin must be tied to VBUS.

Submit Document Feedback

5

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

表6-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

BQ25618 NO.

BQ25619 NO.

Charger input voltage. The internal n-channel reverse block MOSFET (RBFET)

is connected between VBUS and PMID with VBUS on source. Place a 1-uF

ceramic capacitor from VBUS to GND and place it as close as possible to IC.

VBUS

A4, B4

24

P

Ground reference for the device that is also the thermal pad used to conduct

heat from the device. This connection serves two purposes. The first purpose is

to provide an electrical ground connection for the device. The second purpose is

to provide a low thermal-impedance path from the device die to the PCB. This

pad should be tied externally to a ground plane.

Thermal Pad

P

—

(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output,

P = Power

6

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–2

MAX UNIT

Voltage

Output Sink Current

T_J

VAC (converter not switching)

VBUS (converter not switching)

PMID (converter not switching)

SW

22

16

17

22

7

V

-2

V

–0.3

V

BAT, SYS (converter not switching)

BTST

V

BATSNS (converter not switching)

PSEL, STAT, SCL, SDA, INT, PMID_GOOD, CE, TS, QON

SDA, STAT, INT, PMID_GOOD

Junction temperature

V

7

V

6

mA

°C

150

–40

–55

T_stg

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

±2000

±250

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

13.5

4.52

3.2

1.8

1.5

5

UNIT

V_VBUS

V_BAT

I_VBUS

I_SW

Input voltage

4

V

Battery voltage

Input current

A

Output current (SW)

Fast charging current

RMS discharge current

Ambient temperature

Inductance

A

I_BAT

A

I_BAT

A

T_A

85

°C

µH

µF

–40

L

1

2.2

C_VBUS

C_PMID

C_SYS

C_BAT

C_REGN

VBUS capacitance

PMID capacitance

SYS capacitance

BAT capacitance

REGN capacitance

10

4.7

Submit Document Feedback

7

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.4 Thermal Information

BQ25618

THERMAL METRIC⁽¹⁾

YFF (DSBGA)

UNIT

30 Balls

58.8

0.2

R_θJA

Junction-to-ambient thermal resistance (JEDEC⁽¹⁾

)

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

8.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.4

Ψ_JT

8.3

Ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Thermal Information

BQ25619

THERMAL METRIC⁽¹⁾

RTW (WQFN)

UNIT

24 Pins

35.6

22.7

11.9

0.2

R_θJA

Junction-to-ambient thermal resistance (JEDEC⁽¹⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

)

°C/W

R_θJC(top)

R_θJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

12

Ψ_JB

R_θJC(bot)

2.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.6 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

QUIESCENT CURRENTS

VBAT = 4.5V, VBUS floating or VBUS

= 0V - 5V, SCL, SDA = 0V or 1.8V, T_J

< 85 °C, BATFET enabled

Quiescent battery current (BATSNS,

BAT, SYS, SW)

I_{Q_BAT}

9.5

7

15

µA

VBAT = 4.5V, VBUS floating or VBUS

= 0V - 5V, SCL, SDA = 0V or 1.8V, T_J

< 85 °C, BATFET disabled

Shipmode battery current (BATSNS,

BAT, SYS, SW)

I_{SHIP_BAT}

9.5

Input current (VBUS) in buck mode

when converter is switching

VBUS=5V, charge disabled, converter

switching, ISYS = 0A

I_VBUS

2.3

37

68

mA

µA

VAC/VBUS = 5V, HIZ mode, no battery

50

90

I_{HIZ_VBUS}

Quiescent input current in HIZ

VAC/VBUS = 12V, HIZ mode, no

battery

Quiescent battery current (BATSNS,

BAT, SYS, SW) in boost mode when

converter is switching

VBAT = 4.5V, VBUS = 5V, boost mode

I_BST

enabled, converter switching, I_PMID

0A

=

2.4

mA

VBUS / VBAT SUPPLY

V_{VBUS_OP}

VBUS operating range

VBUS rising for active I2C, no battery VBUS rising

VBUS falling to turnoff I2C, no battery VBUS falling

4

13.5

3.7

V

V_{VBUS_UVLOZ}

V_{VBUS_UVLO}

3.3

3

3.3

8

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.6 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

3.65

3.15

MAX UNIT

V_{VBUS_PRESENT}

V_{VBUS_PRESENTZ}

VBUS to enable REGN

VBUS to disable REGN

VBUS rising

3.9

3.4

V

VBUS falling

VBUS falling, VBUS - VBAT, VBAT =

4V

V_SLEEP

Enter Sleep mode threshold

Exit Sleep mode threshold

15

60

110

340

mV

VBUS rising, VBUS - VBAT, VBAT =

4V

V_SLEEPZ

115

220

VAC rising, OVP[1:0]=00

VAC rising, OVP[1:0]=01

VAC rising, OVP[1:0]=10

VAC rising, OVP[1:0]=11 (default)

VAC falling, OVP[1:0]=00

VAC falling, OVP[1:0]=01

VAC falling, OVP[1:0]=10

VAC falling, OVP[1:0]=11 (default)

VBAT rising

5.45

6.1

5.85

6.4

6.07

6.75

11.55

14.85

5.8

V

VAC overvoltage rising threshold to

turn of switching

10.45

13.5

5.2

11

14.2

5.6

V_ACOV

5.8

6.2

6.45

11.1

VAC overvoltage falling threshold to

resume switching

10

10.7

13.9

13

14.5

V_{BAT_UVLOZ}

V_{BAT_DPLZ}

BAT voltage for active I2C, no VBUS

2.5

BAT depletion rising threshold to turn

on BATFET

VBAT rising

2.35

2.8

V

BAT depletion falling threshold to turn

off BATFET

V_{BAT_DPL}

VBAT falling

VBUS falling

2.18

3.75

2.62

4.0

V

V_POORSRC

Bad adapter detection threshold

3.9

POWER PATH MANAGEMENT

Typical minimum system regulation

voltage

VBAT=3.2V < SYS_MIN = 3.5V, ISYS

= 0A

V_{SYS_MIN}

3.5

3.65

4.7

35

V

VREG = 4.35V, Charge disabled, ISYS

= 0A

V_{SYS_OVP}

R_{ON_RBFET}

R_{ON_HSFET}

R_{ON_LSFET}

System overvoltage threshold

V

Blocking FET on-resistance

(BQ25618)

mΩ

mV

Blocking FET on-resistance

(BQ25619)

45

High-side switching FET on-resistance

(BQ25618)

55

High-side switching FET on-resistance

(BQ25619)

62

Low-side switching FET on-resistance

(BQ25618)

60

Low-side switching FET on-resistance

(BQ25619)

71

BATFET forward voltage in

supplement mode

BAT discharge current 10mA,

converter running

V_BATFET

_

30

FWD

BATTERY CHARGER

Typical charge voltage regulation

range

V_{REG_RANGE}

3.5

4.52

V

V_{REG_STEP}

V_{REG_ACC}

Typical charge voltage step

Charge voltage accuracy

4.3V < VREG < 4.52V

10

mV

V

4.183

4.333

4.432

4.2 4.2168

VREG = 4.2V, T_J= –40°C - 85°C

VREG = 4.35V, T_J= –40°C - 85°C

VREG = 4.45V, T_J= –40°C - 85°C

4.35

4.45

4.367

4.468

V

Typical charge current regulation

range

I_{CHG_RANGE}

0

1.5

A

Submit Document Feedback

9

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.6 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_{CHG_STEP}

Typical charge current regulation step

20

mA

ICHG = 0.24A, VBAT = 3.1V or 3.8V,

T_J= –40°C - 85°C

0.216

0.24

0.264

A

ICHG = 0.72A, VBAT = 3.1V or 3.8V,

T_J= –40°C - 85°C

Fast charge current regulation

accuracy

I_{CHG_ACC}

0.6768

0.72 0.7632

ICHG = 1.50A, VBAT = 3.1V or 3.8V,

T_J= –40°C - 85°C

1.41

20

1.5

1.59

260

I_{PRECHG_RANGE}

I_{PRECHG_STEP}

Typical pre-charge current range

Typical pre-charge current step

mA

20

40

VBAT = 2.6V, IPRECHG = 40mA

VBAT = 2.6V, IPRECHG = 120mA

28

84

20

52

156

260

I_{PRECHG_ACC}

Precharge current accuracy

120

I_{TERM_RANGE}

I_{TERM_STEP}

Typical termination current range

Typical termination current step

20

40

ITERM=40mA, ICHG>260mA,

VREG=4.35V, T_J= 0°C - 85°C

30

10

50

30

mA

V

I_{TERM_ACC}

Termination current accuracy

ITERM=20mA, ICHG<260mA,

VREG=4.35V, T_J= 0°C - 85°C

20

Battery short voltage rising threshold

to start pre-charge

V_{BAT_SHORTZ}

VBAT rising

2.13

2.25

2.35

Battery short voltage falling threshold

to stop pre-charge

V_{BAT_SHORT}

I_{BAT_SHORT}

VBAT falling

1.85

15

3

2

25

2.15

30

V

mA

V

Battery short trickle charging current

VBAT < V_{BAT_SHORTZ}

VBAT rising

Battery LOWV rising threshold to start

fast-charge

3.12

3.24

V_BATLOWV

Battery LOWV falling threshold to stop

fast-charge

VBAT falling

2.7

2.8

2.9

V

VRECHG=0, VBAT falling (default)

VRECHG=1, VBAT falling

90

120

210

150

245

mV

V_RECHG

Battery recharge threshold

185

System discharge load current during

SYSOVP

I_{SYS_LOAD}

30

mA

T_J= -40°C - 85°C

T_J= -40°C - 125°C

19.5

26

30

mΩ

R_{ON_BATFET}

Battery FET on-resistance

BATTERY OVERVOLTAGE PROTECTION

Battery overvoltage rising threshold

Battery overvoltage falling threshold

INPUT VOLTAGE / CURRENT REGULATION

V_{INDPM_RANGE}Typical input voltage regulation range

V_{INDPM_STEP}

VBAT rising, as percentage of VREG

VBAT falling, as percentage of VREG

103

101

104

102

105

103

%

V_{BAT_OVP}

3.9

5.4

V

Typical input voltage regulation step

100

4.5

mV

Typical input voltage regulation

accuracy

V_{INDPM_ACC}

4.365

4.635

V

VINDPM threshold to track battery

voltage

VBAT = 4.35V, VINDPM_BAT_TRACK

= VBAT+200mV

V_{INDPM_TRACK}

4.45

0.1

4.55

4.74

3.2

I_{INDPM_RANGE}

I_{INDPM_STEP}

I_{INDPM_ACC}

Typical input current regulation range

Typical input current regulation step

Input current regulation accuracy

A

100

465

mA

IINDPM = 500mA (T_J=-40°C - 85°C)

IINDPM = 900mA (T_J=-40°C-85°C)

IINDPM = 1500mA (T_J=-40°C-85°C)

450

750

500

900

835

1300

1390

1500

10

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.6 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

THERMAL REGULATION AND THERMAL SHUTDOWN

TREG = 90°C

90

110

150

130

°C

Junction temperature regulation

accuracy

T_REG

TREG = 110°C

T_SHUT

Thermal Shutdown Rising threshold

Thermal Shutdown Falling threshold

Temperature Increasing

Temperature Decreasing

CHARGE MODE THERMISTOR COMPARATOR (JEITA 616J or HOT/COLD 616)

TS pin voltage rising threshold,

Charge suspended above this voltage. 103AT)

As Percentage to REGN (0°C w/

V_{T1_RISE%}

72.4

71.5

73.3

72

74.2

72.5

%

TS pin voltage falling threshold.

Charge re-enabled to 20% of ICHG

and VREG below this

voltage.

V_{T1_FALL%}

As Percentage to REGN

As Percentage to REGN,

JEITA_T2=5°C w/ 103AT

70.25

67.75

64.75

61.75

68.7

70.75

68.25

65.25

62.25

69.2

66.95

64.2

61.2

48.25

44.75

40.7

37.7

49.3

45.8

41.8

39

71.25

68.75

65.75

62.75

69.7

%

As Percentage to REGN,

JEITA_T2=10°C w/ 103AT

TS pin voltage rising threshold,

Charge back to 20% of ICHG and

VREG above this voltage.

V_{T2_RISE%}

V_{T2_FALL%}

V_{T3_FALL%}

V_{T3_RISE%}

As Percentage to REGN,

JEITA_T2=15°C w/ 103AT

As Percentage to REGN,

JEITA_T2=20°C w/ 103AT

As Percentage to REGN,

JEITA_T2=5°C w/ 103AT

As Percentage to REGN,

JEITA_T2=10°C w/ 103AT

66.45

63.7

67.45

64.7

TS pin voltage falling threshold.

Charge back to ICHG and VREG

below this voltage.

As Percentage to REGN,

JEITA_T2=15°C w/ 103AT

As Percentage to REGN,

JEITA_T2=20°C w/ 103AT

60.7

61.7

As Percentage to REGN,

JEITA_T3=40°C w/ 103AT

47.75

44.25

40.2

48.75

45.25

41.2

As Percentage to REGN,

JEITA_T3=45°C w/ 103AT

TS pin voltage falling threshold.

Charge to ICHG and 4.1V below this

voltage.

As Percentage to REGN,

JEITA_T3=50°C w/ 103AT

As Percentage to REGN,

JEITA_T3=55°C w/ 103AT

37.2

38.2

As Percentage to REGN,

JEITA_T3=40°C w/ 103AT

48.8

49.8

As Percentage to REGN,

JEITA_T3=45°C w/ 103AT

45.3

46.3

TS pin voltage rising threshold.

Charge back to ICHG and VREG

above this voltage.

As Percentage to REGN,

JEITA_T3=50°C w/ 103AT

41.3

42.3

As Percentage to REGN,

JEITA_T3=55°C w/ 103AT

38.5

39.5

TS pin voltage falling threshold,

As Percentage to REGN (60°C w/

charge suspended below this voltage. 103AT)

V_{T5_FALL%}

33.7

34.2

35.1

TS pin voltage rising threshold.

V_{T5_RISE%}

Charge back to ICHG and 4.1V above As Percentage to REGN

this voltage.

35

35.5

36

%

BOOST MODE THERMISTOR COMPARATOR (HOT/COLD)

Submit Document Feedback

11

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.6 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TS pin voltage rising threshold, boost

mode is suspended above this

voltage.

As Percentage to REGN (–19.5°C w/

103AT)

V_{BCOLD_RISE%}

79.5

80

80.5

%

As Percentage to REGN (0°C w/

103AT)

V_{BCOLD_FALL%}

V_{BHOT_FALL%}

V_{BHOT_RISE%}

TS pin voltage falling threshold

72

31.2

39

%

TS pin voltage threshold. boost mode As Percentage to REGN, (64°C w/

30.2

1.32

32.2

is suspended below this voltage.

103AT)

As Percentage to REGN, (55°C w/

103AT), REG0C[1:0]=11

TS pin voltage rising threshold

SWITCHING CONVERTER

F_SW

PWM switching frequency

Maximum PWM Duty Cycle

Oscillator frequency

1.5

97

1.68 MHz

%

D_MAX

BOOST MODE CONVERTER

Battery voltage exiting boost mode

V_VBATfalling

2.6

2.9

2.4

2.8

3.0

2.5

2.9

3.15

2.6

V

V_{BATLOWV_OTG}

Battery voltage entering boost mode

Battery voltage exiting boost mode

V_VBATrising

V_{BST_BAT}

BAT fallingVVBAT

Typical boost mode voltage regulation

range

V_{BST_RANGE}

4.6

4.85

5

5.15

V

A

V

Boost mode voltage regulation

accuracy

V_{BST_ACC}

IVBUS = 0A, BOOST_V = 5V

5

6

Boost mode battery discharge current

clamp on BATFET Q4

I_{SYS_OCP_Q4}

Boost mode overvoltage threshold on

PMID

V_{BST_OVP}

5.55

5.8

6.15

REGN LDO

V_VBUS= 5V, I_REGN= 20mA

V_VBUS= 9V, I_REGN= 20mA

V_VBUS= 5V, V_REGN= 3.8V

4.58

5.6

50

4.7

6

4.8

6.5

V

V_REGN

REGN LDO output voltage

REGN LDO current limit

I_REGN

mA

I2C INTERFACE (SCL, SDA)

Input high threshold level, SDA and

SCL

V_IH

Pull up rail 1.8V

1.3

V

V_IL

Input low threshold level

Output low threshold level

High-level leakage current

Input high threshold level, SDA

Input low threshold level

Output low threshold level

High-level leakage current

Input high threshold level, SDA

Input low threshold level

Output low threshold level

High-level leakage current

Pull up rail 1.8V

Sink current = 5mA

Pull up rail 1.8V

Sink current = 5mA

Pull up rail 1.8V

Sink current = 5mA

Pull up rail 1.8V

0.4

1

V

V_OL

I_BIAS

µA

V

V_{IH_SDA}

V_{IL_SDA}

V_{OL_SDA}

I_{BIAS_SDA}

V_{IH_SCL}

V_{IL_SCL}

V_{OL_SCL}

I_{BIAS_SCL}

LOGIC INPUT PIN

V_IH

1.3

0.4

1

V

µA

V

0.4

1

V

µA

Input high threshold level (/CE, PSEL)

Input low threshold level (/CE, PSEL)

1.3

V

V_IL

0.4

1

High-level leakage current (/CE,

PSEL)

I_{IN_BIAS}

Pull up rail 1.8V

µA

12

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.6 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OV}and V_VBUS> V_BAT+ V_SLEEP, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

LOGIC OUTPUT PIN

Output low threshold level (/INT, STAT,

PMID_GOOD)

V_OL

Sink current = 5mA

0.4

1

V

High-level leakage current (/INT, STAT,

PMID_GOOD)

I_{OUT_BIAS}

Pull up rail 1.8V

µA

7.7 Timing Requirements

MIN

NOM

MAX

UNIT

VBUS / VBAT POWER UP

t_{VBUS_OV}

VBUS OVP Reaction-time

130

30

2

ns

ms

s

t_POORSRC

Bad adapter detection duration

t_{POORSRC_RETRY}

BATTERY CHARGER

t_{TERM_DGL}

Bad adapter detection retry wait time

Deglitch time for charge termination

Deglitch time for recharge threshold

30

20

10

ms

min

hr

t_{RECHG_DGL}

t_{TOP_OFF}

Typical top-off timer accuracy TOP_OFF_TIMER[1:0]=10

Charge safety timer accuracy, CHG_TIMER = 20hr

Charge safety timer accuracy, CHG_TIMER = 10hr

24

17

8

36

24

12

t_SAFETY

hr

QON Timing

QON low time to turn on BATFET and exit shipmode (–10℃≤TJ

≤60℃)

t_SHIPMODE

0.9

1.3

s

QON low time before BATFET full system reset (–10℃≤TJ ≤

60℃)

t_{QON_RST}

8

250

10

12

400

15

s

ms

s

t_{BATFET_RST}

t_{BATFET_DLY}

BATFET off time during full system reset (–10℃≤TJ ≤60℃)

Delay time before BATFET turn off in ship mode (–10℃≤TJ ≤

60℃)

I2C INTERFACE

f_SCL

SCL clock frequency

400

kHz

DIGITAL CLOCK AND WATCHDOG

f_LPDIGDigital low-power clock (REGN LDO is disabled)

f_DIG

t_{LP_WDT}

t_WDT

30

500

160

kHz

s

Digital power clock

Watchdog Reset time

Watchdog Reset time (WATCHDOG REG05[5:4] = 160s)

s

Submit Document Feedback

13

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

7.8 Typical Characteristics

100

95

90

85

80

75

70

65

95

90

85

80

75

VBUS = 5 V

VBUS = 9 V

VBUS = 12 V

VBUS = 5 V

VBUS = 9 V

VBUS = 12 V

0

0.2

0.4

0.6

Charge Current (A)

0.8

1

1.2

1.4

1.6

0

0.2

0.4

0.6

Charge Current (A)

0.8

1

1.2

1.4

1.6

Char

BQ25619EVM V_BAT= 3.8V

BQ25618EVM

V_BAT

=

Inductor 1.0µH, DCR = 27 mΩ

Inductor 2.2µH, DCR = 40 mΩ

3.8V

图7-1. Charge Efficiency

图7-2. Charge Efficiency

100

95

90

85

80

75

95

90

85

80

75

VBAT = 3.2 V

VBAT = 3.8 V

VBAT = 4.2 V

VBAT = 3.8 V

VBAT = 3.2 V

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Boost Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Boost Ouput Current (A)

1

OTG_

Boos

BQ25618EVM

V_PMID= 4.6V

1.0 µH Inductor,

BQ25619EVM

V_PMID

=

Inductor 2.2µH, DCR = 40 mΩ

4.6V

DCR = 27 mΩ

图7-3. Boost Efficiency

图7-4. Boost Efficiency

10

9

8

7

6

5

4

3

2

1

0

4.45

4.4

VBUS = 5 V

VBUS = 9 V

V_BATREG= 4.35 V

4.35

4.3

4.25

0

0.2

0.4

0.6

Charge Current (A)

0.8

1

1.2

1.4

1.6

-40

-15

10

35

60

85

110 125

Junction Temperature (èC)

Char

图7-5. Charge Current Accuracy

图7-6. Battery Charge Voltage vs Junction

Temperature

14

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

1.6

4.6

4.5

4.4

4.3

4.2

4.1

4

ICHG = 500 mA

ICHG = 1000 mA

ICHG = 1380 mA

VINDPM = 4.1 V

VINDPM = 4.3 V

VINDPM = 4.4 V

VINDPM = 4.5 V

1.4

1.2

1

0.8

0.6

0.4

-40

-25

-10

5

20

35

50

65

8085

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

Char

VIND

图7-7. Charge Current vs Junction Temperature

图7-8. VINDPM vs Junction Temperature

3.8

1.75

IINDPM = 0.5 A

INDPM = 0.9 A

INDPM = 1.5 A

1.5

1.25

1

3.75

3.7

0.75

0.5

3.65

3.6

0.25

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

-40

-25

-10

5

20

35

Junction Temperature (°C)

50

65

8085

VSYS

IIND

图7-9. SYSMIN Voltage vs Junction Temperature

图7-10. Input Current Limit vs Junction

(VSYS set at 3.5 V)

Temperature

5.25

BOOSTV = 5.0 V

BOOSTV = 5.15 V

5.2

5.15

5.1

5.05

5

-40 -25 -10

5

20 35 50 65 80 95 110 125

Junction Temperature (èC)

VOTG

图7-11. Boost Output Voltage vs Junction Temperature

Submit Document Feedback

15

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8 Detailed Description

8.1 Overview

The BQ25619/618 device is a highly integrated 1.5-A switch-mode battery charger for single cell Li-ion and Li-

polymer battery. It includes an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate

drive.

8.2 Functional Block Diagram

VBUS

PMID

V_{VBUS_UVLOZ}

RBFET (Q1)

+

UVLO

SLEEP

ACOV

V_VBUS

Q1 Gate

Control

œ

I_IN

V_BAT+ V_SLEEP

+

REGN

BTST

EN_REGN

EN_HIZ

VAC

V_VBUS

REGN

LDO

œ

V_VBUS

+

V_{VAC_OV}

œ

FBO

V_VBUS

VBUS_OVP_BOOST

+

V_{OTG_OVP}

œ

I_Q2

Q2_UCP_BOOST

Q3_OCP_BOOST

+

V_{OTG_HSZCP}

V_VBUS

œ

+

œ

+

œ

+

HSFET (Q2)

LSFET (Q3)

I_Q3

V_INDPM

SW

+

V_{OTG_BAT}

I_IN

CONVERTER

Control

œ

REGN

I_INDPM

BAT

+

BATOVP

UCP

104% × V _{BAT_REG}

IC T_J

T_REG

PGND

œ

I_{LSFET_UCP}

BATSNS

I_Q2

Q2_OCP

+

œ

+

œ

+

I_{HSFET_OCP}

I_Q3

SYS

V_{BAT_REG}

œ

V_SYSMIN

V_BTST- V_SW

I_CHG

EN_HIZ

EN_CHARGE

EN_BOOST

+

REFRESH

V_{BTST_REFRESH}

I_{CHG_REG}

œ

SYS

I_CHG

V_{BAT_REG}

I_{CHG_REG}

BATFET

(Q4)

Q4 Gate

Control

I_BADSRC

I_DC

BAT

BAD_SRC

+

REF

DAC

Converter

Control State

Machine

œ

IC T_J

T_SHUT

+

TSHUT

œ

BATSNS

V_BATGD

BAT_GD

+

V_QON

Input Source

Detection

œ

USB

PSEL

Adapter

V_REG-V_RECHG

BATSNS

I_CHG

+

RECHRG

/QON

œ

INT

STAT

+

TERMINATION

BATLOWV

I_TERM

œ

CHARGE

CONTROL

STATE

V_BATLOWV

+

BATSNS

V_SHORT

BQ25618

BQ25619

MACHINE

œ

+

BATSHORT

SUSPEND

PMID_GOOD

BATSNS

I2C

œ

Interface

Battery

Sensing

TS

Thermistor

SCL SDA /CE

16

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3 Feature Description

8.3.1 Power-On-Reset (POR)

The device powers internal bias circuits from the higher voltage of VBUS and BAT. When V_VBUSrises above

V_{VBUS_UVLOZ}or V_BATrises above V_{BAT_UVLOZ}, the sleep comparator, battery depletion comparator, and BATFET

driver are active. The I²C interface is ready for communication and all registers are reset to default values. The

host can access all registers after POR.

8.3.2 Device Power Up From Battery Without Input Source

If only the battery is present and the voltage is above depletion threshold (V_{BAT _DPLZ}), the BATFET turns on and

connects the battery to the system. The REGN stays off to minimize the quiescent current. The low R_DSONof

BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through the BATFET. When the system is overloaded or

shorted (I_BAT> I_{SYS_OCP_Q4}), the device turns off BATFET immediately.

With I²C, when the BATFET turns off due to overcurrent, the device sets the BATFET_DIS bit to indicate the

BATFET is disabled until the input source plugs in again or one of the methods described in 节 8.3.7.2 is applied

to re-enable BATFET.

8.3.3 Power Up From Input Source

When an input source is plugged in, the device checks the input source voltage to turn on the REGN LDO and

all the bias circuits. It detects and sets the input current limit before the buck converter is started. The power-up

sequence from input source is as listed:

1. Power Up REGN LDO, see 节8.3.3.1

2. Poor Source Qualification, see 节8.3.3.2

3. Input Source Type Detection is based on PSEL to set default input current limit (IINDPM threshold), see 节

8.3.3.3

4. Input Voltage Limit Threshold Setting (VINDPM threshold), see 节8.3.3.4

5. Power Up Converter, see 节8.3.3.5

8.3.3.1 Power Up REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. It also provides the

bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN LDO is

enabled when all the below conditions are valid:

• V_VBUS> V_{VBUS_UVLOZ}

• In buck mode, V_VBUS> V_BAT+ V_SLEEPZ

• In boost mode, V_VBUS< V_BAT+ V_SLEEPZ

• After 220-ms delay is completed

During high impedance mode when EN_HIZ bit is 1, REGN LDO turns off. The battery powers up the system.

8.3.3.2 Poor Source Qualification

After the REGN LDO powers up, the device starts to check current capability of the input source. The first step is

poor source detection.

• VBUS voltage above V_POORSRCwhen pulling I_BADSRC(typical 30 mA)

With I²C, once the input source passes poor source detection, the status register bit VBUS_GD is set to 1 and

the INT pin is pulsed to signal to the host.

If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

Submit Document Feedback

17

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.3.3 Input Source Type Detection (IINDPM Threshold)

After poor source detection, the device runs input source detection through the PSEL pin. The PSEL pin sets

input current limit 0.5 A (HIGH) or 2.4 A (LOW). After input source type detection is completed, the PMID_GOOD

pin is asserted to HIGH and the PG_STAT bit goes to 1.

With I²C, after input source type detection is completed, an INT pulse is asserted to the host. In addition, the

following register bits are updated:

1. Input Current Limit (IINDPM) register is updated from detection result

2. VBUS_STAT bit is updated to indicate USB or other input source

3. PG_STAT bit is updated to indicate good adapter plugs in

The host can overwrite the IINDPM register to change the input current limit if needed.

8.3.3.3.1 PSEL Pins Sets Input Current Limit

The device with the PSEL pin directly takes the USB PHY device output to decide whether the input is a USB

host or charging port. When the device operates in host-control mode, the host needs the INDET_EN bit set to 1

to update the IINDPM register. When the device is in default mode, the PSEL value updates IINDPM in real time.

表8-1. Input Current Limit Setting from PSEL

INPUT CURRENT LIMIT

INPUT DETECTION

PSEL PIN

VBUS_STAT

(ILIM)

500 mA

2.4 A

USB SDP

Adapter

HIGH

LOW

001

011

8.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device has two modes to set the VINDPM threshold.

• Fixed VINDPM threshold. VINDPM is in default set at 4.5 V (programmable from 3.9 V to 5.4 V).

• VINDPM threshold tracks the battery voltage to optimize the converter headroom between input and output.

When it is enabled in REG07[1:0], the actual input voltage limit is the higher of the VINDPM setting in register

and V_BAT+ offset voltage in VINDPM_BAT_TRACK[1:0] .

8.3.3.5 Power Up Converter in Buck Mode

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. The

system voltage is powered from the converter instead of the battery. If battery charging is disabled, the BATFET

turns off. Otherwise, the BATFET stays on to charge the battery.

The device provides soft start when the system rail is ramping up. When the system rail is below V_{BAT_SHORT}, the

input current is limited to the lower of 200 mA or IINDPM register setting. The system load should be

appropriately planned not to exceed the 200-mA IINDPM limit. After the system rises above V_{BAT_SHORTZ}, the

device input current limit is the value set by the IINDPM register.

As a battery charger, the device deploys a highly efficient 1.5-MHz step-down switching regulator. The fixed

frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery

voltage, charge current, and temperature simplifying output filter design.

The converter supports PFM operation by default for fast transient response during system voltage regulation

and better light load efficiency. The PFM_DIS bit disables PFM operation if system voltage is not in regulation.

8.3.3.6 HIZ Mode with Adapter Present

By setting the EN_HIZ bit to 1 with adapter, the device enters a high impedance state (HIZ). In HIZ mode, the

system is powered from the battery even with good adapter present. The device is in the low input quiescent

current state with Q1 RBFET, REGN LDO, and the bias circuits off.

18

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.4 Boost Mode Operation From Battery

The device supports boost converter operation to deliver power from the battery to other portable devices

through a USB port. The output voltage is regulated at 5 V (programmable 4.6/4.75/5.0/5.15 V) and output

current is up to 1 A. The user needs to have at least 350 mV between V_BATand Boost mode regulation voltage

(V_BST) to power up Boost mode reliably. For example, the BOOSTV[1:0] setting is recommended to be 4.75 V or

higher if the battery voltage is 4.4 V.

Boost operation is enabled if the conditions below are valid:

1. Register setting: BATFET_DIS = 0, CHG_COFNIG = 0 and BST_CONFIG = 1

2. BAT above V_{BST_BAT}set by MIN_VBAT_SEL bit,

3. VBUS less than V_BAT+ V_SLEEP(in sleep mode) before converter starts.

4. Voltage at TS (thermistor) pin, as a percentage of V_REGN, is within acceptable range (V_{BHOT_RISE%}< V_TS%

V_{BCOLD_FALL%}

<

)

During Boost mode, the status register VBUS_STAT bits are set to 111.

The converter supports PFM operation at light load in Boost mode. The PFM_DIS bit can be used to disable

PFM operation in boost configuration.

The BQ25619/618 keeps the Q1 FET off during Boost mode. During adapter plug-in or removal, the charger

automatically transitions between charging mode and Boost mode by setting the BST_CONFIG bit and

CHG_CONFIG bit both to 1. When the adapter plugs in and the conditions to start a new charge cycle are valid,

the device is in charging mode. If the adapter is removed and the boost enable conditions are valid, the device

transits to Boost mode to power the accessories connected to PMID automatically.

8.3.5 Power Path Management

The device accommodates a wide range of input sources such as USB, wall adapter, or car charger. The device

provides automatic power path selection to supply the system (SYS) from the input source (VBUS), battery

(BAT), or both.

8.3.5.1 Narrow VDC Architecture

When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO

mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage

rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system

and battery is the V_DSof the BATFET.

When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the

system is always regulated at typically 50 mV above the battery voltage. The status register VSYS_STAT bit

goes to 1 when the system is in minimum system voltage regulation.

4.5

Minimum System Voltage

Charge Disabled

Charge Enabled

4.1

4.3

3.9

3.7

3.5

3.3

3.1

2.7

2.9

3.1

3.3

3.5

BAT (V)

3.7

3.9

4.1

4.3

D002

图8-1. System Voltage vs Battery Voltage

Submit Document Feedback

19

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.5.2 Dynamic Power Management

To meet the maximum current limit in the USB specification and avoid overloading the adapter, the device

features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls

below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls

below the input current limit or the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement

mode where the BATFET turns on and the battery starts discharging so that the system is supported from both

the input source and battery.

During DPM mode, the status register bits VINDPM_STAT or IINDPM_STAT go to 1.

8.3.5.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is

regulated so that the minimum BATFET V_DSstays at 30 mV when the current is low. This prevents oscillation

from entering and exiting the supplement mode.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce R_DSONuntil

the BATFET is in full conduction. At this point onwards, the BATFET V_DSlinearly increases with discharge

current. 图 8-2 shows the V-I curve of the BATFET gate regulation operation. The BATFET turns off to exit

supplement mode when the battery is below battery depletion threshold.

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

5

10 15 20 25 30 35 40 45 50 55

V(BAT-SYS) (mV)

D001

Plot1

图8-2. BAFET V-I Curve

8.3.6 Battery Charging Management

The device charges a 1-cell Li-ion battery with up to 1.5-A charge current for a high capacity tablet battery. The

19.5-mΩBATFET improves charging efficiency and minimizes the voltage drop during discharging.

8.3.6.1 Autonomous Charging Cycle

When battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is LOW), the device autonomously

completes a charging cycle without host involvement. The device default charging parameters are listed in 表

8-2. The host configures the power path and charging parameters by writing to the corresponding registers

through I²C.

表8-2. Charging Parameter Default Setting

DEFAULT MODE

Charging voltage

Charging current

BQ25619/618

4.20 V

340 mA

20

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

表8-2. Charging Parameter Default Setting

(continued)

DEFAULT MODE

Pre-charge current

Termination current

Temperature profile

Safety timer

BQ25619/618

40 mA

60 mA

JEITA

10 hours

A new charge cycle starts when the following conditions are valid:

• Converter starts

• Battery charging is enabled (CHG_CONFIG bit = 1 and I_CHGregister is not 0 mA and CE is low)

• No thermistor fault on TS. (TS pin can be ignored by setting TS_IGNORE bit to 1)

• No safety timer fault

• BATFET is not forced to turn off (BATFET_DIS bit = 0)

The device automatically terminates the charging cycle when the charging current is below the termination

threshold, the battery voltage is above the recharge threshold, and the device is not in DPM mode or thermal

regulation. When a fully charged battery is discharged below recharge threshold (selectable through VRECHG

bit), the device automatically starts a new charging cycle. After the charge is done, a toggle of the CE pin or

CHG_CONFIG bit initiates a new charging cycle. Adapter removal and replug will also restart a charging cycle.

The STAT output indicates charging status: charging (LOW), charging complete or charge disable (HIGH), or

charging fault (blinking). The status register (CHRG_STAT) indicates the different charging phases: 00-charging

disable, 01-precharge, 10-fast charge (CC) and constant voltage (CV), 11-charging done. Once a charging cycle

is completed, an INT pulse is asserted to notify the host.

8.3.6.2 Battery Charging Profile

The device charges the battery in five phases: battery short, preconditioning, constant current, constant voltage,

and top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage

and regulates current and voltage accordingly.

Resistance between charger output and battery cell terminal such as board routing, connector, MOSFETs, and

sense resistor can force the charging process to move from constant current to constant voltage too early and

increase charge time. To speed up the charging cycle, the device provides the BATSNS pin to extend the

constant current charge time to deliver maximum power to battery. The BATSNS pin is connected directly to the

battery cell terminal to remotely sense battery cell voltage. BATSNS is by default enabled and can be disabled

through the BATSNS_DIS bit. If BATSNS is connected to GND or left floating, the charger regulates the BAT pin

instead.

表8-3. Charging Current Setting

V_BAT

< 2.2 V

CHARGING CURRENT

DEFAULT SETTING

CHRG_STAT

I_{BAT_SHORT}

25 mA

01

10

2.2 V to 3 V

> 3 V

I_PRECHG

40 mA

I_CHG

340 mA

Submit Document Feedback

21

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

Regulation Voltage

Charge Current

Battery Voltage

Charge Current

V_BATLOWV(3 V)

V_SHORTZ(2.2 V)

I_PRECHG

I_TERM

I_SHORT

Fast Charge and Voltage Regulation

Trickle Charge

Pre-charge

Safety Timer

Expiration

Top-off Timer

图8-3. Battery Charging Profile

8.3.6.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above the recharge threshold, and the current

is below termination current. After the charging cycle has completed, the BATFET turns off. STAT is asserted

HIGH to indicate charging is done. The converter keeps running to power the system, and BATFET can turn on

again to engage 节8.3.5.3.

If the device is in IINDPM/VINDPM regulation, or thermal regulation, the actual charging current will be less than

the termination value. In this case, termination is temporarily disabled.

When termination occurs, the STAT pin goes HIGH. The status register CHRG_STAT is set to 11, and an INT

pulse is asserted to the host. Termination can be disabled by writing 0 to the EN_TERM bit prior to charge

termination.

Termination current is set in REG03[3:0]. For a small capacity battery, the termination current can be set as low

as 20 mA for full charge. Due to the termination current accuracy, the actual termination current may be higher

than the termination target. In order to compensate for termination accuracy, a programmable top-off timer can

be applied after termination is detected . The top-off timer will follow safety timer constraints, such that if the

safety timer is suspended, so will the top-off timer. Similarly, if the safety timer is doubled, so will the termination

top-off timer. The TOPOFF_ACTIVE bit reports whether the top-off timer is active or not. The host can read

CHRG_STAT and TOPOFF_ACTIVE to find out the termination status. The STAT pin stays HIGH during a top-off

timer counting cycle.

Top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer value

(01, 10, 11) after termination has no effect unless a recharge cycle is initiated. The top-off timer immediately

stops if it is disabled (00). An INT is asserted to the host when entering a top-off timer segment as well as when

the top-off timer expires.

8.3.6.4 Thermistor Qualification

The device provides a single thermistor input for battery temperature monitoring.

22

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.6.4.1 JEITA Guideline Compliance During Charging Mode

To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The

guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low

and high temperature ranges.

To initiate a charge cycle, the voltage on TS pin, as a percentage of V_REGN, must be within the V_{T1_FALL%}to

V_{T5_RISE%}thresholds. If the TS voltage percentage exceeds the T1-T5 range, the controller suspends charging,

a TS fault is reported and waits until the battery temperature is within the T1-T5 range.

At cool temperature (T1-T2), the charge current is reduced to a programmable fast charge current (0%, 20%

default, 50%, 100% of I_CHG, by JEITA_ISET). At warm temperature (T3-T5), the charge voltage is reduced to 4.1

V or kept at V_REG(JEITA_VSET), and the charge current can be reduced to a programmable level (0%, 20%,

50%, 100% default). Battery termination is disabled in T3-T5. The charger provides more flexible settings on a

T2 and T3 threshold as well to program the temperature profile beyond JEITA. When T1 is set to 0°C and T5 is

set to 60°C, T2 can be programmed to 5.5°C/10°C (default)/15°C/20°C, and T3 can be programmed to 40°C/

45.5°C (default)/50.5°C/54.5°C.

When the charger does not need to monitor the NTC, the host sets the TS_IGNORE bit to 1 to ignore the TS pin

condition during charging and Boost mode. If the TS_IGNORE bit is set to 1, the TS pin is ignored and the

charger ignores the TS pin input. In this case, the NTC_FAULT bits are 000 to report normal TS status.

JEITA_WARM_ISET

100% of ICHG

(default)

(0%, 20%, 50%, 100%)

JEITA_VSET

4.1V (default)

(VREG or 4.1V)

JEITA_COOL_ISET

20% of ICHG

(default)

(0%,20%,50%,100%)

T3

T1

0

T2

T5

60

10

5

15 20

30 35

45 50

40

25

Battery Thermistor Temperature (°C)

图8-4. JEITA Profile

方程式1 through 方程式2 describe how to calculate resistor divider values on the TS pin.

Submit Document Feedback

23

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

REGN

TS

RT1

RT2

NTC

103AT

图8-5. TS Pin Resistor Network

%

(1)

(2)

%

In the equations above, R_{NTC, T1}is the NTC thermistor resistance value at temperature T1 and R_{NTC, T5}is the

NTC thermistor resistance value at temperature T5. Selecting a 0°C to 60°C range for a Li-ion or Li-polymer

battery then:

• R_NTC,T1= 27.28 kΩ(0°C)

• R_NTC,T5= 3.02 kΩ(60°C)

• RT1 = 5.3 kΩ

• RT2 = 31.14 kΩ

8.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode

For battery protection during Boost mode, the device monitors battery temperature to be within the V_BCOLDand

V_BHOTthresholds. When RT1 is 5.3 kΩ and RT2 is 31.14 kΩ, T_BCOLDdefault is -19.5°C and T_BHOTdefault is

64°C. When the temperature is outside of the temperature thresholds, Boost mode is suspended. In addition, the

VBUS_STAT bits are set to 000 and NTC_FAULT is reported. Once the temperature returns within the

thresholds, Boost mode is recovered and NTC_FAULT is cleared.

8.3.6.5 Charging Safety Timer

The device has a built-in safety timer to prevent an extended charging cycle due to abnormal battery conditions.

The safety timer is 2 hours when the battery is below the V_BATLOWVthreshold and 10 hours (10/20 hours in

REG05[2] ) when the battery is higher than the V_BATLOWVthreshold. When the safety timer expires, the STAT pin

is blinking at 1 Hz to report a safety timer expiration fault.

The user can program the fast charge safety timer through I²C (CHG_TIMER bit REG05[2]). When the safety

timer expires, the fault register CHRG_FAULT bits (REG09[5:4]) are set to 11 and an INT is asserted to the host.

The safety timer (both fast charge and precharge) can be disabled through I²C by setting the EN_TIMER bit.

During IINDPM/VINDPM regulation, thermal regulation, or JEITA cool/warm when fast charge current is reduced,

the safety timer counts at a half clock rate, because the actual charge current is likely below the setting. For

example, if the charger is in input current regulation (IINDPM_STAT = 1) throughout the whole charging cycle,

and the safety time is set to 10 hours, the safety timer will expire in 20 hours. This half clock rate feature can be

disabled by writing 0 to the TMR2X_EN bit.

24

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

During faults of BAT_FAULT, NTC_FAULT that lead to charging suspend, the safety timer is suspended as well.

Once the fault goes away, the timer resumes. If the user stops the current charging cycle, and starts it again, the

timer gets reset (toggle of CE pin or CHG_CONFIG bit).

8.3.7 Ship Mode and QON Pin

8.3.7.1 BATFET Disable (Enter Ship Mode)

To extend battery life and minimize power when the system is powered off during system idle, shipping, or

storage, the device turns off BATFET so that the system voltage is floating to minimize the battery leakage

current. When the host sets the BATFET_DIS bit, the charger can turn off the BATFET immediately or delay by

t_{BATFET_DLY}as configured by the BATFET_DLY bit. To set the device into ship mode with the adapter present, the

host has to first set BATFET_RST_VBUS to 1 and then BATFET_DIS to 1. The charger will turn off the BATFET

(no charging, no supplement) while the adapter is still attached. When the adapter is removed, the charger will

enter ship mode.

8.3.7.2 BATFET Enable (Exit Ship Mode)

When the BATFET is disabled (in ship mode) as indicated by setting BATFET_DIS, one of the following events

can enable the BATFET to restore system power:

1. Plug in adapter

2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)

4. A logic high to low transition on QON pin with t_SHIPMODEdeglitch time to enable BATFET to exit ship mode.

EN_HIZ bit is set to 1 (regardless of adapter present or not). Host has to set EN_HIZ bit to 0 before boost

mode enable. Once adapter plugs in, EN_HIZ will be cleared.

8.3.7.3 BATFET Full System Reset

The BATFET functions as a load switch between the battery and system when an input source is not plugged in.

When BATFET_RST_EN = 1 and BATFET_DIS = 0, the BATFET full system reset function is enabled. By

changing the state of BATFET from on to off, systems connected to SYS can be effectively forced to have a

power-on-reset. After the reset is complete, the device is in the POR state, and all registers are in POR default

settings. The QON pin supports a push-button interface to reset system power without the host by changing the

state of BATFET. Internally, it is pulled up to the V_QONvoltage through a 200-kΩresistor.

When the QON pin is driven to logic low for t_{QON_RST}, the BATFET reset process starts. The BATFET is turned

off for t_{BATFET_RST}and then it is re-enabled to reset system power. This function can be disabled by setting the

BATFET_RST_EN bit to 0.

The BATFET full system reset functions either with or without an adapter present. If BATFET_RST_WVBUS = 1,

the system reset function starts after t_{QON_RST}when the QON pin is pushed to LOW. Once the reset process

starts, the device first goes into HIZ mode to turn off the converter, and then power cycles BATFET. If

BATFET_RST_WVBUS = 0, the system reset function does not start until t_{QON_RST}after the QON pin is pushed

to LOW and the adapter is removed.

After the BATFET full system reset is complete, the device powers up again if EN_HIZ is not set to 1 before the

system reset.

Submit Document Feedback

25

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

Adapter

/QON

SYS

Q4

Control

VQON

/QON

tBATFET_DLY

tSHIPMODE

ON

BATFET Q4

OFF

Enter Shipmode

after BATFET_DIS=1

Exit Shipmode

with /QON

BATFET_RS

T_WVBUS

Adapter

tQON_RST

/QON

ON

Q4

OFF

tBATFET_RST

Enter HIZ

BATFET Reset with

BATFET_RST_WVBUS=0

BATFET Reset with

BATFET_RST_WVBUS=1

图8-6. QON Timing

8.3.8 Status Outputs (STAT, INT , PMID_GOOD)

8.3.8.1 Power Good Indicator (PG_STAT Bit)

The PG_STAT bit goes to 1 to indicate a good input source when:

• V_VBUSabove V_{VBUS_UVLO}

• V_VBUSabove battery (not in sleep)

• V_VBUSbelow V_ACOVthreshold

• V_VBUSabove V_POORSRC(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Completed 节8.3.3.3

8.3.8.2 Charging Status Indicator (STAT)

The device indicates the charging state on the open drain STAT pin. The STAT pin can drive an LED.

表8-4. STAT Pin State

CHARGING STATE

STAT INDICATOR

LOW

Charging in progress (including recharge)

Charging termination (top off timer may be running)

HIGH

Sleep mode, charge disable, Boost mode

HIGH

Charge suspend (input overvoltage, TS fault, safety timer fault, or system overvoltage)

Blinking at 1 Hz

8.3.8.3 Interrupt to Host (INT)

In some applications, the host does not always monitor charger operation. The INT pulse notifies the host on

device operation. The following events generate a 256-μs INT pulse.

• Good input source detected:

– V_VBUSabove battery (not in sleep)

26

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

– V_VBUSbelow V_ACOVthreshold

– V_VBUSabove V_POORSRC(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Input adapter removed

• USB/adapter source identified during 节8.3.3.3.

• Charge complete

• Any FAULT event in REG09

• VINDPM / IINDPM event detected (REG0A[1:0], maskable)

• Top-off timer starts and expires

REG09[7:0] and REG0A[6:4] report charger operation faults and status change to the host. When a fault/status

change occurs, the charger sends out an INT pulse and keeps the state in REG09[7:0]/REG0A[6:4] until the host

reads the registers. Before the host reads REG09[7:0]/REG0A[6:4] and all the ones are cleared, the charger

does not send any INT upon new fault/status change. To read the current status, the host has to read REG09/

REG0A two times consecutively. The first read reports the pre-existing register status and the second read

reports the current register status.

8.3.8.4 PMID Voltage Indicator (PMID_GOOD)

In the BQ25619/618, the accessory devices can be connected to the charger PMID pin to get power either from

the adapter through the Q1 direct path or from battery Boost mode. An optional external PMOS FET can be

placed between the charger PMID pin and accessory input to disconnect the power path during overcurrent and

overvoltage conditions. PMID_GOOD is used to drive an external PMOS FET through an inverter. PMID_GOOD

HIGH turns on an inverter to pull the PMOS FET gate low to turn on the PMOS FET, and PMID_GOOD LOW

turns off the PMOS FET.

Upon adapter plug-in, PMID_GOOD goes from LOW to HIGH when VBUS rises above the battery but below

V_ACOV, and passes poor source detection. During the operation, PMID_GOOD goes from HIGH to LOW if Q1

current exceeds 115% of the IINDPM threshold, (I_{BLK_OCP}), or adapter voltage rises above 5.8 V (V_{BST_OVP}).

The high-voltage adapter over V_{BST_OVP}keeps charging the battery if all conditions are valid. The external

PMOS FET stays off to protect the accessory from an overvoltage fault.

When the adapter is removed, PMID_GOOD goes LOW before battery Boost mode starts.

In battery Boost mode, the device regulates PMID voltage between 4.6 V to 5.15 V as a stable power supply to

the accessory devices. PMID_GOOD goes from LOW to HIGH when PMID voltage rises above 3.8 V

(V_POORSRC). Similar to the adapter present scenario, the PMID valid voltage range is between V_POORSRCand

V_{BST_OVP}. Once PMID voltage is out of this range, PMID_GOOD goes LOW to disconnect the accessory device

from PMID. During Boost mode, all of the conditions to exit Boost mode will drive PMID_GOOD from HIGH to

LOW, including Boost mode disable in register, ACOV, TS fault, battery depleted (V_{BAT_DPL}), BATFET

overcurrent, (I_{SYS_OCP_Q4}), etc.

8.3.9 Protections

8.3.9.1 Voltage and Current Monitoring in Buck Mode

8.3.9.1.1 Input Overvoltage Protection (ACOV)

The input voltage is sensed via the VAC pin . The default OVP threshold is 14.2 V, and can be programmed at

5.7 V/6.4 V/11 V/14.2 V via OVP[1:0] register bits. ACOV event immediately stops converter switching whether in

buck or Boost mode. The device automatically resumes normal operation once the input voltage drops back

below the OVP threshold. During ACOV, REGN LDO is on, and the device does not enter HIZ mode.

During ACOV, the fault register CHRG_FAULT bits are set to 01. An INT pulse is asserted to the host.

8.3.9.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during a load transient so that the components connected to the

system are not damaged due to high voltage. The V_{SYS_OVP}threshold is about 300 mV above battery regulation

voltage when battery charging is terminated. Upon SYSOVP, the converter stops switching immediately to clamp

the overshoot. The charger pulls 30-mA I_{SYS_LOAD}discharge current to bring down the system voltage.

Submit Document Feedback

27

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.9.2 Voltage and Current Monitoring in Boost Mode

8.3.9.2.1 Boost Mode Overvoltage Protection

When PMID voltage rises above the regulation target and exceeds V_{BST_OVP}, the device stops switching

immediately and the device exits Boost mode and PMID_GOOD is pulled low as well. The BST_CONFIG bit is

set to 0. During Boost mode overvoltage, the fault register bit BOOST_FAULT is set to 1 to indicate a fault in

boost operation. An INT is asserted to the host.

8.3.9.2.2 PMID Overcurrent Protection

The BQ25619/618 closely monitors the battery discharge current through BATFET (Q4) to ensure safe Boost

mode operation. During an overcurrent condition when boost input current exceeds I_{SYS_OCP_Q4}, the device

latches off in 100 µs. When an overcurrent condition is detected, the fault register bit BOOST_FAULT is set high

to indicate a fault in boost operation. An INT is asserted to the host.

8.3.9.3 Thermal Regulation and Thermal Shutdown

8.3.9.3.1 Thermal Protection in Buck Mode

Besides the battery temperature monitor on the TS pin, the device monitors the internal junction temperature T_J

to avoid overheating the chip and limits the IC junction temperature in buck mode. When the internal junction

temperature exceeds the thermal regulation limit (110°C), the device lowers down the charge current. During

thermal regulation, the actual charging current is usually below the programmed battery charging current.

Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register

THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and the BATFET when the IC surface

temperature exceeds T_SHUT150°C. The BATFET and converter are enabled to recover when IC temperature is

130°C. The fault register CHRG_FAULT is set to 10 during thermal shutdown and an INT is asserted to the host.

8.3.9.3.2 Thermal Protection in Boost Mode

Besides the battery temperature monitor on the TS pin, the device monitors the internal junction temperature to

provide thermal shutdown during Boost mode. When the IC junction temperature exceeds T_SHUT150°C, Boost

mode is disabled by setting the BST_CONFIG bit low. When the IC junction temperature is below 145°C, the

host can re-enable Boost mode.

8.3.9.4 Battery Protection

8.3.9.4.1 Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above battery regulation voltage. When battery overvoltage

occurs, the charger device immediately stops switching. The fault register BAT_FAULT bit goes high and an INT

is asserted to the host.

8.3.9.4.2 Battery Overdischarge Protection

When the battery is discharged below V_{BAT_DPL_FALL}, the BATFET latches off to protect the battery from

overdischarge. To recover from overdischarge latch-off, an input source plug-in is required at VAC/VBUS.

8.3.9.4.3 System Overcurrent Protection

I_{SYS_OCP_Q4}sets the battery discharge current limit. Once I_BAT> I_{SYS_OCP_Q4}, the charger latches off Q4 and puts

the device into Ship mode. All methods to exit Ship mode are valid to bring the part out of Q4 latch-off.

8.3.10 Serial Interface

The device uses an I²C compatible interface for flexible charging parameter programming and instantaneous

device status reporting. I²C^TMis a bi-directional 2-wire serial interface developed by Philips Semiconductor (now

NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL).

Devices can be considered as masters or slaves when performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any

device addressed is considered a slave.

28

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

The device operates as a slave device with address 6AH, receiving control inputs from the master device like a

microcontroller or a digital signal processor through REG00 to REG0C. A register read beyond REG0C returns

0xFF. The I²C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits),

connecting to the positive supply voltage via a current source or pullup resistor. When the bus is free, both lines

are HIGH. The SDA and SCL pins are open drain.

8.3.10.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Data line stable;

Data valid

Change of data

allowed

图8-7. Bit Transfer on the I²C Bus

8.3.10.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The

bus is considered busy after the START condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

START (S)

STOP (P)

图8-8. TS START and STOP conditions

8.3.10.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data

transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

Acknowledgement

signal from slave

Acknowledgement

signal from receiver

MSB

1

SDA

SCL

2

7

8

9

1

2

8

9

S or Sr

P or Sr

START or

Repeated

START

STOP or

Repeated

START

ACK

图8-9. Data Transfer on the I²C Bus

Submit Document Feedback

29

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge ninth clock pulse, are generated by the master. The transmitter releases the SDA line during the

acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH

period of this clock pulse.

When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.10.5 Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction

bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

1 - 7

8

9

1-7

8

9

1-7

8

9

S

P

SCL

START

ADDRESS

R / W

ACK

DATA

ACK

DATA

ACK

STOP

图8-10. Complete Data Transfer

8.3.10.6 Single Read and Write

If the register address is not defined, the charger IC sends back NACK and goes back to the idle state.

1

7

1

0

1

8

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

Data to Addr

ACK

P

图8-11. Single Write

1

7

1

8

1

7

1

S

Slave Address

0

ACK

Reg Addr

ACK

S

Slave Addr

1

ACK

8

1

Data

NCK

P

图8-12. Single Read

8.3.10.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG0C.

1

7

1

0

1

8

1

S

Slave Address

ACK

Reg Addr

ACK

8

1

8

1

8

1

Data to Addr

ACK

Data to Addr + N

ACK

Data to Addr + N

ACK

P

图8-13. Multi-Write

30

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

1

7

1

0

1

8

1

7

1

S

Slave Address

ACK

Reg Addr

ACK

S

Slave Address

ACK

8

1

8

1

8

1

Data @ Addr

ACK

Data @ Addr + 1

ACK

Data @ Addr + N NCK

P

图8-14. Multi-Read

REG09[7:0]/REG0A[6:4] are fault/status change registers. They keep all of the fault/status information from the

last read until the host issues a new read. For example, if a Charge Safety Timer Expiration fault occurs but

recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when

it is read the second time. In order to get the fault information at present, the host has to read REG09/REG0A for

the second time.

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default

mode, the device can be used as an autonomous charger with no host or while the host is in sleep mode. When

the charger is in default mode, the WATCHDOG_FAULT bit is HIGH. When the charger is in host mode, the

WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All

registers are in the default settings.

In default mode, the device keeps charging the battery with the 10-hour fast charging safety timer. At the end of

the 10-hour, charging is stopped and the buck converter continues to operate to supply system load. Any write

command to the device transitions the charger from default mode to host mode. All device parameters can be

programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing a

1 to the WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable the

watchdog timer by setting the WATCHDOG bits = 00.

All device parameters can be programmed by the host. To keep the device in host mode, the host has to reset

the watchdog timer by writing a 1 to the WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT

bit is set), or disable the watchdog timer by setting the WATCHDOG bits = 00.

POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Start watchdog timer

Host programs registers

Y

I2C Write?

N

Default Mode

Reset watchdog timer

Reset selective registers

Y

WD_RST bit = 1?

N

Y

N

I2C Write?

Watchdog Timer

Expired?

图8-15. Watchdog Timer Flow Chart

Submit Document Feedback

31

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5 Register Maps

I²C Slave Address: 6AH

Default I²C Slave Address: 0x6A (1101 010B + R/ W)

表8-5. I²C Registers

Address

00h

Access Type

Acronym

REG00

REG01

REG02

REG03

REG04

REG05

REG06

REG07

REG08

REG09

REG0A

REG0B

REG0C

Register Name

Section

Go

R/W

R

Input Current Limit

Charger Control 0

Charge Current Limit

Precharge and Termination Current Limit

Battery Voltage Limit

Charger Control 1

Charger Control 2

Charger Control 3

Charger Status 0

01h

Go

02h

Go

03h

Go

04h

Go

05h

Go

06h

Go

07h

Go

08h

Go

09h

R

Charger Status 1

Go

0Ah

0Bh

0Ch

R

Charger Status 2

Go

R

Part Information

Go

R/W

Charger Control 4

Go

Complex bit access types are encoded to fit into small table cells. 表 8-6 shows the codes that are used for

access types in this section.

表8-6. I²C Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

Reset Value

-n

Value after reset

Undefined value

-X

32

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.1 Input Current Limit Register (Address = 00h) [Reset = 17h]

图8-16. REG00 Register

7

0

6

0

5

0

4

3

2

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-7. REG00 Field Descriptions

Bit

Field

POR

Type

Reset

Description

HIZ mode enable in buck mode.

0 –Disable (default)

1 –Enable

by REG_RST

by Watchdog

7

EN_HIZ

0

R/W

When charger does not monitor the NTC, host sets this bit to 1 to

ignore the TS pin condition during charging and boost mode.

0 –Include TS pin into charge and boost mode enable

6

TS_IGNORE

0

R/W

by REG_RST conditions. (default)

1 –Ignore TS pin. Always consider TS is good to allow charging

and boost mode. NTC_FAULT bits are 000 to report normal

status.

Select either BATSNS pin or BAT pin to regulate battery voltage.

0 –Enable BATSNS in battery CV regulation. If the device fails

by REG_RST BATSNS open/short detection (BATSNS_STAT = 1). Battery

voltage is regulated through BAT pin. (default)

5

BATSNS_DIS

0

R/W

1 –Disable BATSNS. Use BAT pin in battery CV regulation.

4

3

2

1

IINDPM[4]

IINDPM[3]

IINDPM[2]

IINDPM[1]

1

0

1

R/W

by REG_RST 1600 mA

by REG_RST 800 mA

by REG_RST 400 mA

by REG_RST 200 mA

Input current limit setting (maximum limit, not

typical)

Offset: 100 mA

Range: 100 mA (000000) –3.2 A (11111)

Default: 2400 mA (10111)

IINDPM bits are changed automatically after

节8.3.3.3 is completed

PSEL HIGH = 500 mA

PSEL LOW = 2.4 A

0

IINDPM[0]

1

R/W

by REG_RST 100 mA

Host can reprogram IINDPM register bits after

input source detection is completed.

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

33

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.2 Charger Control 0 Register (Address = 01h) [Reset = 1Ah]

图8-17. REG01 Register

7

0

6

0

5

0

4

3

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-8. REG01 Field Descriptions

Bit Field

POR Type Reset

Description

PFM disable in both buck and boost mode.

R/W by REG_RST 0 –PFM enable (default)

1 –PFM disable

7

6

PFM_DIS

0

I²C Watchdog timer reset. Back to 0 after watchdog timer reset

0 –Normal (default)

1 –Reset

by REG_RST

by Watchdog

WD_RST

R/W

Boost mode enable. In charging case application, based on adapter

plug-in or removal, the charger will automatically transit between

charging mode and boost mode by setting BST_CONFIG bit and

CHG_CONFIG bit both to 1.

by REG_RST

by Watchdog

5

BST_CONFIG

0

R/W

0 –Boost mode disable (default)

1 –Boost mode enable

Battery charging buck mode enable. Charging is enabled when CE pin

is pulled low, CHG_CONFIG bit is 1 and charge current is not zero.

by Watchdog 0 –Charge Disable

1 –Charge Enable (default)

by REG_RST

4

CHG_CONFIG

1

R/W

3

2

SYS_MIN[2]

SYS_MIN[1]

1

0

R/W by REG_RST System minimum voltage setting.

000 –2.6 V

R/W by REG_RST

001 –2.8 V

010 –3 V

011 –3.2 V

100 –3.4 V

101 –3.5 V (default)

110 –3.6 V

1

0

SYS_MIN[0]

1

0

R/W by REG_RST

111 –3.7 V

Minimum battery voltage when exiting boost mode. The rising threshold

allows the device to start boost mode if other conditions are valid.

0 –2.8 V V_BATfalling, 3 V rising (default)

MIN_VBAT_SEL

R/W by REG_RST

1 –2.5 V V_BATfalling, 2.8 V rising

LEGEND: R/W = Read/Write; R = Read only

34

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.3 Charge Current Limit Register (Address = 02h) [Reset = 91h]

图8-18. REG02 Register

7

1

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-9. REG02 Field Descriptions

Bit

Field

POR

Type

Reset

Description

7

Reserved

1

R/W

In buck mode, charger will fully turn on Q1 RBFET according

to this bit setting when IINDPM is below 700 mA. When

IINDPM is over 700 mA, Q1 is always fully on.

0 –Partially turn on Q1 for better regulation accuracy when

IINDPM is below 700 mA. (default)

6

Q1_FULLON

0

R/W

by REG_RST

1 –Fully turn on Q1 for better efficiency when IINDPM is

below 700 mA.

R/W

by REG_RST

by Watchdog

5

4

3

2

1

0

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

0

1

0

1

640 mA

Fast charge current setting

by REG_RST

by Watchdog

320 mA

160 mA

80 mA

40 mA

20 mA

Default: 340 mA (010001)

Range: 0 mA (0000001) –

1180 mA (111011), 20 mA/

step

111100: 1290 mA

111101: 1360 mA

111110: 1430 mA

111111: 1500 mA

I_CHG0 mA disables charge.

by REG_RST

by Watchdog

R/W

by REG_RST

by Watchdog

R/W

by REG_RST

by Watchdog

by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

35

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.4 Precharge and Termination Current Limit Register (Address = 03h) [Reset = 12h]

图8-19. REG03 Register

7

0

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-10. REG03 Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST

by Watchdog

7

6

5

4

3

2

1

0

IPRECHG[3]

0

1

0

1

0

R/W

160 mA

Precharge current setting

Default: 40 mA (0001)

Range: 20 mA (0000) –260 mA

(1100)

Offset: 20 mA

Note: I_PRECHG> 260 mA is

clamped to 260 mA (1100)

by REG_RST

by Watchdog

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

ITERM[3]

80 mA

40 mA

20 mA

160 mA

80 mA

40 mA

20 mA

by REG_RST

by Watchdog

by REG_RST

by Watchdog

by REG_RST

by Watchdog

Termination current setting

Default: 60 mA (0010)

Range: 20 mA –260 mA (1100)

Offset: 20 mA

Note: I_TERM> 260 mA is clamped

to 260 mA (1100)

by REG_RST

by Watchdog

ITERM[2]

by REG_RST

by Watchdog

ITERM[1]

by REG_RST

by Watchdog

ITERM[0]

LEGEND: R/W = Read/Write; R = Read only

36

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.5 Battery Voltage Limit Register (Address = 04h) [Reset = 40h]

图8-20. REG04 Register

7

0

6

1

5

0

4

3

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-11. REG04 Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST Battery voltage setting, also called V_REG

by Watchdog Default: 4.200 V (01000)

.

7

6

5

4

VBATREG[4]

0

1

0

R/W

00000 –3.504 V

00001 –3.600 V

00010 –3.696 V

00011 –3.800 V

by REG_RST

by Watchdog

VBATREG[3]

VBATREG[2]

VBATREG[1]

by REG_RST

by Watchdog

00100 –3.904 V

by REG_RST

by Watchdog

00101 –4.000 V

00110 –4.100 V

00111 –4.150 V

01000 –4.200 V

by REG_RST

3

VBATREG[0]

0

R/W

by Watchdog 01001 - 11111 –4.300 V - 4.520 V, 10 mV/step

01110 4.350 V, 10011 4.400 V, 11000 4.450 V, 11101 4.500 V

by REG_RST Top-off timer setting.

2

1

TOPOFF_TIMER[1]

TOPOFF_TIMER[0]

0

R/W

by Watchdog

00 –Disabled (default)

01 –15 minutes

10 –30 minutes

11 –45 minutes

by REG_RST

by Watchdog

by REG_RST Battery recharge threshold setting.

by Watchdog

0

VRECHG

0

R/W

0 –120 mV (default)

1 –210 mV

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

37

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.6 Charger Control 1 Register (Address = 05h) [Reset = 9Eh]

图8-21. REG05 Register

7

1

6

0

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-12. REG05 Field Descriptions

Bit

Field

POR

Type

Reset

Description

Battery charging termination enable.

0 –Disable

1 –Enable (default)

by REG_RST

by Watchdog

7

EN_TERM

1

R/W

by REG_RST

by Watchdog

6

5

Reserved

0

R/W

Reserved

by REG_RST Watchdog timer setting.

by Watchdog

WATCHDOG[1]

00 –Disable timer

01 –40 s (default)

10 –80 s

by REG_RST

by Watchdog

4

3

WATCHDOG[0]

EN_TIMER

1

R/W

11 –160 s

Battery charging safety timer enable, including both fast

charge and precharge timers. Precharge timer is 2 hours.

Fast charge timer is set by REG05[2]

0 –Disable

by REG_RST

by Watchdog

1 –Enable timer (default)

Battery fast charging safety timer setting.

0 –20 hrs

1 –10 hrs (default)

by REG_RST

by Watchdog

2

1

CHG_TIMER

TREG

1

R/W

Thermal regulation threshold:

0 –90°C

1 –110°C (default)

by REG_RST

by Watchdog

Battery voltage setting during JEITA warm (T3 - T5,

typically 45C - 60C)

by Watchdog 0 –Set charge voltage to 4.1 V (max) (default)

1 –Set charge voltage to V_REG

by REG_RST

0

JEITA_VSET (45C-60C)

0

R/W

LEGEND: R/W = Read/Write; R = Read only

38

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.7 Charger Control 2 Register (Address = 06h) [Reset = E6h]

图8-22. REG06 Register

7

1

6

1

5

1

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-13. REG06 Field Descriptions

Bit Field

POR Type Reset

Description

7

6

5

4

OVP[1]

1

0

R/W by REG_RST V_ACOVthreshold during buck mode and boost mode.

00 –5.85 V

01 –6.4 V (5-V input)

10 –11 V (9-V input)

OVP[0]

R/W by REG_RST

11 –14.2 V (12-V input) (default)

BOOSTV[1]

BOOSTV[0]

R/W by REG_RST Boost regulation voltage setting

00 –4.6 V

01 –4.75 V

10 –5.0 V (default)

R/W by REG_RST

11 –5.15 V

3

2

1

0

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

0

1

0

R/W by REG_RST 800 mV

R/W by REG_RST 400 mV

R/W by REG_RST 200 mV

R/W by REG_RST 100 mV

VINDPM threshold setting

Default: 4.5 V (0110)

Range: 3.9 V (0000) –5.4 V

(1111)

Offset: 3.9 V

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

39

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.8 Charger Control 3 Register (Address = 07h) [Reset = 4Ch]

图8-23. REG07 Register

7

0

6

1

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-14. REG07 Field Descriptions

Bit Field

POR Type Reset

Description

Force input source type detection. After the detection is complete, this

bit returns to 0.

by Watchdog 0 –Not in input current limit detection. (default)

1 –Force input current limit detection when adapter is present.

by REG_RST

7

6

IINDET_EN

0

1

R/W

Safety timer is slowed by 2X during input DPM, JEITA cool/warm or

thermal regulation.

by REG_RST

TMR2X_EN

0 –Disable. Safety timer duration is set by REG05[2].

by Watchdog

1 –Safety timer slowed by 2X during input DPM (both V and I) or

JEITA cool/warm (except I_CHG=100%), or thermal regulation. (default)

BATFET Q4 ON/OFF control. Set this bit to 1 to enter ship mode. To

reset the device with adapter present, the host shall set

BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.

0 –Turn on Q4. (default)

1 –Turn off Q4 after t_{BATFET_DLY}delay time (REG07[3])

5

4

3

BATFET_DIS

0

1

R/W by REG_RST

Start BATFET full system reset with or without adapter present.

0 –Start BATFET full system reset after adapter is removed from

VBUS. (default)

BATFET_RST_WVBUS

BATFET_DLY

1 –Start BATFET full system reset when adapter is present on VBUS.

Delay from BATFET_DIS (REG07[5]) set to 1 to BATFET turn off during

ship mode.

R/W by REG_RST 0 –Turn off BATFET immediately when BATFET_DIS bit is set.

1 –Turn off BATFET after t_{BATFET_DLY}(typ 10 s) when BATFET_DIS bit

is set. (default)

Enable BATFET full system reset. The time to start of BATFET full

system reset is based on the setting of BATFET_RST_WVBUS bit.

by REG_RST

by Watchdog 0 –Disable BATFET reset function

1 –Enable BATFET reset function when REG07[5] is also 1. (default)

2

1

BATFET_RST_EN

1

0

R/W

VINDPM_BAT_TRACK[1]

R/W by REG_RST Sets VINDPM to track BAT voltage. Actual VINDPM is higher of register

value and V_BAT+ VINDPM_BAT_TRACK.

00 –Disable function (VINDPM set by register) (default)

01 –V_BAT+ 200 mV

10 –V_BAT+ 250 mV

11 –V_BAT+ 300 mV

0

VINDPM_BAT_TRACK[0]

0

R/W by REG_RST

LEGEND: R/W = Read/Write; R = Read only

40

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.9 Charger Status 0 Register (Address = 08h)

图8-24. REG08

7

x

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-15. REG08 Field Descriptions

Bit Field

POR Type

Reset

Description

7

6

VBUS_STAT[2]

x

R

NA

VBUS Status register

000 –No input

001 –USB host SDP (500 mA) →PSEL pin HIGH

011 –Adapter 2.4 A →PSEL pin LOW

111 –Boost mode

VBUS_STAT[1]

VBUS_STAT[0]

CHRG_STAT[1]

NA

5

4

x

R

NA

Software current limit is reported in IINDPM register

Charging status:

00 –Not charging

01 –Precharge or trickle charge (< V_BATLOWV

10 –Fast charging

11 –Charge termination

)

3

2

CHRG_STAT[0]

PG_STAT

x

R

NA

Power Good status:

0 –Power Not Good

1 –Power Good

0 –Not in thermal regulation

1 –In thermal regulation

1

0

THERM_STAT

VSYS_STAT

x

R

NA

0 –Not in SYS_MIN regulation (V_BAT> V_{SYS_MIN}

1 –In SYS_MIN regulation (V_BAT< V_{SYS_MIN}

)

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

41

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.10 Charger Status 1 Register (Address = 09h)

图8-25. REG09 Register

7

1

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-16. REG09 Field Descriptions

Bit Field

POR Type Reset

Description

0 –Normal, device is in host mode,

7

WATCHDOG_FAULT

1

R

NA

1 –Watchdog timer expiration, device is in default mode.

0 –Normal

1 –Fault detected in boost mode (any conditions that are not valid for

boost operation), including VBUS overloaded (BST_OVP) or battery is

too low (BST_BAT)

6

BOOST_FAULT

x

5

4

CHRG_FAULT[1]

CHRG_FAULT[0]

x

R

NA

00 –Normal

01 –Input fault

10 –Thermal shutdown

11 –Charge safety timer expiration

0 –Normal,

1 –Battery overvoltage.

3

BAT_FAULT

x

R

NA

2

1

NTC_FAULT[2]

NTC_FAULT[1]

x

R

NA

TS fault in buck mode

000 –Normal

010 –Warm

011 –Cool

101 –Cold

110 –Hot

0

NTC_FAULT[0]

x

R

NA

TS fault in boost mode

000 –Normal

101 –Cold

110 –Hot

LEGEND: R/W = Read/Write; R = Read only

42

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.11 Charger Status 2 Register (Address = 0Ah)

图8-26. REG0A Register

7

x

6

x

5

x

4

3

2

x

1

0

x

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-17. REG0A Field Descriptions

Bit Field

POR Type Reset

Description

0 –VBUS does not pass poor source detection

1 –VBUS passes poor source detection

7

6

5

VBUS_GD

x

R

NA

0 –Not in VINDPM

1 –In VINDPM

VINDPM_STAT

IINDPM_STAT

0 –Not in IINDPM

1 –In IINDPM

0 –BATSNS pin is in good connection. Regulation battery voltage

through BATSNS pin.

1 –BATSNS pin is open/short. Regulate battery voltage through BAT

4

BATSNS_STAT

x

R

NA

pin.

0 –Top off timer not counting.

1 –Top off timer counting

3

2

TOPOFF_ACTIVE

ACOV_STAT

x

R

NA

0 –Not in ACOV

1 –In ACOV

Allow or block INT pulse assertion to host during VINDPM.

1

0

VINDPM_INT_ MASK

IINDPM_INT_ MASK

0

R/W by REG_RST 0 –INT is asserted to host during VINDPM (default).

1 –No INT pulse asserted to host during VINDPM.

Allow or block INT pulse assertion to host during IINDPM

R/W by REG_RST 0 –INT is asserted to host during IINDPM (default).

1 –No INT pulse asserted to host during IINDPM.

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

43

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.12 Part Information Register (Address = 0Bh)

图8-27. REG0B Register

7

0

6

0

5

1

4

3

2

1

0

1

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-18. REG0B Field Descriptions

Bit Field

POR Type Reset

Description

Register reset

0 –Keep current register setting (default).

1 –Reset to default register value and reset safety timer. This bit

7

REG_RST

0

R/W NA

returns to 0 after register reset is completed.

6

5

4

3

2

PN[3]

0

1

0

1

R

NA

PN[2]

Reserved

PN[1]

PN[0]

Reserved

1

0

R

NA

Reserved

LEGEND: R/W = Read/Write; R = Read only

44

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

8.5.13 Charger Control 4 Register (Address = 0Ch) [Reset = 75h]

图8-28. REG0C

7

0

6

1

5

1

4

3

2

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表8-19. REG0C Field Descriptions

Bit Field

POR Type Reset

Description

by REG_RST Fast charge current setting during cool temperature range (T1 - T2), as

by Watchdog percentage of I_CHGin REG02[5:0].

00 –No Charge

7

6

5

4

JEITA_COOL_ISET [1]

0

1

R/W

01 –20% of I_CHG(default)

10 –50% of I_CHG

11 –100% of I_CHG(safety timer does not become 2X)

by REG_RST

by Watchdog

JEITA_COOL_ISET [0]

JEITA_WARM_ISET [1]

JEITA_WARM_ISET [0]

by REG_RST Fast charge current setting during warm temperature range (T3 - T5), as

by Watchdog percentage of I_CHGin REG02[5:0].

00 –No Charge

01 –20% of I_CHG

10 –50% of I_CHG

11 –100% of I_CHG(safety timer does not become 2X) (default)

by REG_RST

by Watchdog

by REG_RST

by Watchdog

00 –VT2% = 70.75% (5.5°C)

01 –VT2% = 68.25% (10°C) (default)

10 –VT2% = 65.25% (15°C)

11 –VT2% = 62.25% (20°C)

3

2

1

0

JEITA_VT2 [1]

JEITA_VT2 [0]

JEITA_VT3 [1]

JEITA_VT3 [0]

0

1

0

1

R/W

by REG_RST

by Watchdog

by REG_RST

by Watchdog

00 –VT3% = 48.25% (40°C)

01 –VT3% = 44.75% (44.5°C) (default)

10 –VT3% = 40.75% (50.5°C)

11 –VT3% = 37.75% (54.5°C)

by REG_RST

by Watchdog

LEGEND: R/W = Read/Write; R = Read only

Submit Document Feedback

45

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

A typical application consists of the device configured as an I²C controlled power path management device and

a single cell battery charger for Li-ion and Li-polymer batteries used in a wide range of smart phones and other

portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The

device also integrates a bootstrap diode for the high-side gate drive.

9.2 Typical Application

INPUT

4 Vœ 13.5 V

Max 22V

SYSTEM

3.5V-4.52V

VAC

Optional

1µH

SW

VBUS

10kΩ

Q1

1µF

Q2

10µF

BTST

47nF

Q3

Optional

VPB

REGN

Ear Phone

PMID

4. 7µF

15kΩ

10µF

20kΩ

PGND

SYS

REGN

Q4

STAT

VREF

BAT

PMID_GOOD

10µF

BATSNS

SDA

SCL

/INT

/CE

REGN

Host

TS

+

Optional if

TS_IGNORE=1

/QON

USB

PHY

PSEL

Optional

BQ25618

BQ25619

图9-1. BQ25619 Application Diagram with Optional PMOS

See the BQ25618 BMS024 Evaluation Module User's Guide and BQ25619 BMS025 Evaluation Module EVM

User's Guide for complete schematic and component placement with trace and via locations.

46

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

9.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

表9-1. Design Parameters

PARAMETER

VALUE

4 V to 13.5 V

2.4 A

V_VBUSvoltage range

Input current limit (REG00[4:0] )

Fast charge current limit (REG02[5:0] )

Minimum system voltage (REG01[3:1])

Battery regulation voltage (REG04[7:3] )

1.024 A

3.5 V

4.2 V

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor

saturation current higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I

_SAT≥I_CHG+ (1/2) I_RIPPLE

(3)

The inductor ripple current depends on the input voltage (V_VBUS), the duty cycle (D = V_BAT/V_VBUS), the switching

frequency (f_S) and the inductance (L).

V_IN´D ´ (1- D)

=

I_RIPPLE

fs ´ L

(4)

The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually

inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off

between inductor size and efficiency for a practical design.

For compact solution size and efficiency at high current, a 1-µH inductor is recommended. To achieve better light

load efficiency during boost mode (output current below 500 mA), the device also supports a 2.2-µH inductor

with a 10-µF (min) cap on the system.

9.2.2.2 Input Capacitor and Resistor

Design the input capacitance to provide enough ripple current rating to absorb the input switching ripple current.

Worst case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not

operate at 50% duty cycle, then the worst case capacitor RMS current I_CINoccurs where the duty cycle is closest

to 50% and can be estimated using 方程式5.

I_CIN= I_CHG´ D ´ (1- D)

(5)

A low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be

placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The

voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V or higher rated

capacitor is preferred for a 12-V input voltage. Minimum capacitance of 10 μF is suggested for typical of 1.5-A

charging current.

During high current output over 700 mA in boost mode, a 10-kΩpull-down resistor on VBUS is recommended to

keep VBUS low in case Q1 RBFET leakage gets high.

9.2.2.3 Output Capacitor

Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.

方程式6 shows the output capacitor RMS current I_COUTcalculation.

Submit Document Feedback

47

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

I_RIPPLE

I_COUT

=

» 0.29 ´ I_RIPPLE

2 ´

3

(6)

The output capacitor voltage ripple can be calculated as follows:

æ

ç

è

ö

V_OUT

8LCfs²

V_OUT

V

DV_O=

1-

÷

^INø

(7)

At certain input and output voltages and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC.

The charger device has internal loop compensation optimized for >10-μF ceramic output capacitance. The

preferred ceramic capacitor is 10-V rating, X7R or X5R.

9.2.3 Application Curves

V_VBUS= 5 V

V_BAT= 3.8 V

V_VBUS= 5 V

V_BAT= 3.8 V

图9-2. VBUS Plugged In and Unplugged with

图9-3. VBUS Plugged In with Boost Mode Enabled

Boost Mode Disabled

V_VBUS= 5 V

V_BAT= 3.8 V

VBoost = 5 V

V_VBUS= 5 V

V_BAT= 3.2 V

图9-4. VBUS Unplugged with Boost Mode Enabled

图9-5. Power Up with Charge Disabled

48

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

I_CHG= 1.5 A

V_VBUS= 5 V

V_BAT= 3.2 V

I_SYS= 0 - 2 A

I_CHG= 1.5 A

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 1 A

图9-6. Power Up with Charge Enabled

图9-7. System Load Transient Response

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 2 A

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 1 A

I_SYS= 0 –2 A

I_SYS= 0 –4 A

I_CHG= 1 A

I_CHG= 1.5 A

图9-8. System Load Transient Respose

图9-9. System Load Transient Response

V_VBUS= 5 V

V_BAT= 3.7 V

IINDPM = 2 A

I_SYS= 0 –4 A

I_CHG= 1.5 A

图9-10. System Load Transient Response

Submit Document Feedback

49

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

10 Power Supply Recommendations

In order to provide an output voltage on SYS, the battery charger requires a power supply between 4 V and 13.5

V input with at least a 100-mA current rating connected to VBUS and a single-cell Li-ion battery with battery

voltage greater than V_{BAT_UVLOZ}connected to BAT. The source current rating needs to be at least 3 A in order for

the buck converter of the charger to provide maximum output power to SYS.

50

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize the high frequency current path loop (see 图 11-1) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the

proper layout.

1. Place an input capacitor as close as possible to the PMID pin and GND pin connections and use the shortest

copper trace connection or GND plane. Add a 1-nF small size (such as 0402 or 0201) decoupling cap for the

high frequency noise filter and EMI improvement.

2. Place the inductor input pin as close as possible to SW pin. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not

use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other

trace or plane.

3. Put the output capacitor near to the inductor and the device. Ground connections need to be tied to the IC

ground with a short copper trace connection or GND plane.

4. Route the analog ground separately from power ground. Connect the analog ground and connect power

ground separately. Connect the analog ground and power ground together using the thermal pad as the

single ground connection point. Or use a 0-Ωresistor to tie the analog ground to power ground.

5. Use a single ground connection to tie the charger power ground to the charger analog ground just beneath

the device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

6. Place the decoupling capacitors next to the IC pins and make the trace connection as short as possible.

7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB

ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on

the other layers.

8. Ensure that the number and sizes of vias allow enough copper for a given current path.

See the BQ25618 BMS024 Evaluation Module User's Guide and BQ25619 BMS025 Evaluation Module EVM

User's Guide for the recommended component placement with trace and via locations. For the VQFN

information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB

Attachment Application Report.

11.2 Layout Example

+

œ

图11-1. High Frequency Current Path

Submit Document Feedback

51

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

图11-2. Layout Example

52

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• BQ25619 BMS025 Evaluation Module User's Guide

• BQ25618 BMS024 Evaluation Module User's Guide

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

53

Product Folder Links: BQ25618 BQ25619

BQ25618, BQ25619

ZHCSJZ6D –JUNE 2019 –REVISED DECEMBER 2021

www.ti.com.cn

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

54

Submit Document Feedback

Product Folder Links: BQ25618 BQ25619

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25618YFFR

BQ25618YFFT

BQ25619RTWR

BQ25619RTWT

DSBGA

WQFN

YFF

30

24

3000

250

180.0

330.0

180.0

8.4

2.09

4.25

2.59

4.25

0.78

1.15

4.0

8.0

Q1

Q2

RTW

3000

250

12.4

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25618YFFR

BQ25618YFFT

BQ25619RTWR

BQ25619RTWT

DSBGA

WQFN

YFF

30

24

3000

250

182.0

367.0

210.0

182.0

367.0

185.0

20.0

35.0

RTW

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

YFF0030

DSBGA - 0.625 mm max height

S

C

A

L

E

4

.

5

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

BALL TYP

0.30

0.12

1.6 TYP

SYMM

F

E

D: Max = 2.392 mm, Min =2.332 mm

E: Max = 1.992 mm, Min =1.931 mm

D

C

SYMM

2

TYP

B

A

0.4 TYP

1

2

4

5

3

0.3

30X

0.4 TYP

0.2

0.015

C A B

4219433/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFF0030

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

30X ( 0.23)

(0.4) TYP

2

4

5

1

A

B

C

SYMM

D

E

F

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

(

0.23)

(

0.23)

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219433/A 03/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFF0030

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

30X ( 0.25)

(R0.05) TYP

1

3

2

4

5

A

B

(0.4)

TYP

METAL

TYP

C

D

E

F

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4219433/A 03/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

GENERIC PACKAGE VIEW

RTW 24

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224801/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25618
厂家：	TEXAS INSTRUMENTS
描述：	采用 WCSP 封装、具有 20mA 终止电流和 1A 升压操作的 I2C 控制型 1.5A 单节降压型电池充电器电池
文件：	总66页 (文件大小：3691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25618 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E