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bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

具有系统功率监测器和处理器热量监测器的 bq25700A SMBus 多化合物电

池降压/升压充电控制器

1 特性

•

输入电流优化器 (ICO) 可获取最大输入功率

为任意化学电池充电：Li+、LiFePO4、镍镉、镍

氢、铅酸

1

•

从各种输入源为 1 至 4 节电池充电

–

3.5V 至 24V 输入工作电压

•

封装：32 引脚 4 x 4 WQFN

支持 USB 2.0、USB 3.0、USB 3.1 (Type-C)

和 USB_PD 输入电流设置

2 应用

–

在降压和升压操作之间进行无缝转换

•

超极本、笔记本、可拆卸电脑、平板电脑和移动电

源

提供输入电流和电压调节（IDPM 和 VDPM）以

防电源过载

•

工业用和医疗用设备

带可充电电池的便携式设备

•

用于 CPU 节流的功率/电流监控器

–

综合 PROCHOT 设置，符合 IMVP8

输入和电池电流监控器

3 说明

系统功率监控器，符合 IMVP8

bq25700A 是一种同步 NVDC 电池降压/升压充电控制

器，为空间受限的多化合物电池充电应用提供了组件数

量少的高效解决方案。

•

窄 VDC (NVDC) 电源路径管理

–

无需电池或使用深度放电的电池亦可瞬时启动

适配器满载时，电池可为系统补充电量

NVDC-1 配置可将系统电压稳定在电池电压范围内，

但不会低于系统最小电压。即便在电池完全放电或被取

出时，系统也仍会继续工作。当负载功率超过输入源额

定值时，电池会进入补电模式并防止系统崩溃。

从电池给 USB 端口加电 (USB OTG)

–

输出 4.48V 至 20.8V 与 USB PD 兼容

输出电流限制高达 6.35A

•

用于 1µH 至 3.3µH 电感器的 800kHz 或 1.2MHz

可编程开关频率

The bq25700A 从 USB 适配器、高电压 USB PD 源和

传统适配器等各种输入源为电池充电。

可通过主机控制接口实现灵活系统配置

–

SMBus (bq25700A) 端口用于优化系统性能和

状态报告

器件信息 ⁽¹⁾

器件型号

bq25700A

封装

WQFN (32)

封装尺寸（标称值）

–

硬件引脚可用于设置输入电流限制，无需 EC 控

制

4.00mm × 4.00mm

•

集成型 ADC 可监控电压、电流和功率

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

高精度调节和监控

–

±0.5% 充电电压调节

±2% 输入/充电电流调节

±2% 输入/充电电流监控

±5% 功率监控器

703A I2C

VSYS

Adapter

3.5V œ 24V

BATT

(1S-4S)

Q2

Q3

Q1

Q4

•

安全性

HIDRV1

SW1BTST1BTST2SW2

HIDRV2

LODRV1

LODRV2

–

热关断

SYS

VBUS

ACN

ACP

BATDRV

SRP

bq25700A

输入、系统、电池过电压保护

SRN

MOSFET 电感过流保护

低电池静态电流

Host

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCQ8

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

8.5 Programming .......................................................... 30

8.6 Register Map........................................................... 32

Application and Implementation ........................ 65

9.1 Application Information .......................................... 65

9.2 Typical Application .................................................. 65

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings ............................................................ 8

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics........................................... 9

7.6 Timing Requirements.............................................. 17

7.7 Typical Characteristics ........................................... 18

Detailed Description ............................................ 21

8.1 Overview ................................................................ 21

8.2 Functional Block Diagram ...................................... 22

8.3 Feature Description................................................. 23

8.4 Device Functional Modes........................................ 29

9

10 Power Supply Recommendations ..................... 72

11 Layout................................................................... 73

11.1 Layout Guidelines ................................................. 73

11.2 Layout Example .................................................... 73

12 器件和文档支持 ..................................................... 75

12.1 器件支持 ............................................................... 75

12.2 文档支持 ............................................................... 75

12.3 接收文档更新通知 ................................................. 75

12.4 社区资源................................................................ 75

12.5 商标....................................................................... 75

12.6 静电放电警告......................................................... 75

12.7 术语表 ................................................................... 75

13 机械、封装和可订购信息....................................... 76

8

4 修订历史记录

Changes from Original (May 2017) to Revision A

Page

•

已删除删除了“特性”中补电模式下的理想二极管运行 ............................................................................................................ 1

已更改将 2.2µH 改为 3.3µH 并删除了“特性”中的低厚度 ..................................................................................................... 1

已添加在“特性”中增加了可监控电压、电流和功率的集成型 ADC......................................................................................... 1

已更改将“说明”中的输入源从“过载”改为 “防止系统崩溃” ....................................................................................................... 1

Changed 18.5 V for 3-cell, and 19.5 for 4-cell to 19.5 V for 3-cell/4-cell in CELL_BATPRESZ description.......................... 5

Changed I to O for CMPOUT I/O ........................................................................................................................................... 6

Changed V_(IADP)to V_(IADPT)in IADPT description ................................................................................................................... 6

Deleted minimum 10-ms and added minimum to PROCHOT description ............................................................................ 6

Changed REG0x3B to REG0x3D in V_{DPM_REG_ACC}Test Conditions in Electrical Characteristics ........................................ 11

Changed REG0x3D to REG0x3B in V_{OTG_REG_ACC}Test Conditions in Electrical Characteristics ........................................ 11

Changed REG0x12[15] = 0 to REG0x12[15] = 1 in Test Conditions for I_{BAT_BATFET_ON}........................................................ 11

Changed I_BATOVPtest condition from: on SRP and SRN to: on VSYS pin............................................................................ 14

Added overbar to (BATDRV) in heading ............................................................................................................................. 16

已添加 overbar to PROCHOT in Overview .......................................................................................................................... 21

已更改 18.5V to 19.5V in 3S row SYSOVP column in 表 1 ................................................................................................. 23

已更改 0 to 0 A, lowside to low-side, and LSFET turn-on to LSFET turn-on when the HSFET is off in Continuous

Conduction Mode (CCM) ..................................................................................................................................................... 24

•

已更改 Pulse Frequency Modulation (PFM) ........................................................................................................................ 24

已更改 during forward mode to during forward supplement mode in High-Accuracy Current Sense Amplifier (IADPT

and IBAT).............................................................................................................................................................................. 25

•

已更改 Processor Hot Indication .......................................................................................................................................... 26

已更改 IADP to IADPT in 图 13 ............................................................................................................................................ 27

已更改 bq2570x to bq2570xA in 图 14 ................................................................................................................................ 28

已添加 overbar to PROCHOT in PROCHOT Status ........................................................................................................... 28

2

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

修订历史记录 (接下页)

•

已更改 subscript of I_{LIM2_VTH}in Input Overcurrent Protection (ACOC).................................................................................. 28

已更改 3s – 18.5 V to 3s/4s – 19.5 V in System Overvoltage Protection (SYSOVP) .......................................................... 29

已添加 REG to Battery Charging ......................................................................................................................................... 29

已更改 0 mA – 6350 mA to 50 mA – 6400 mA for 3Fh in 表 6 ........................................................................................... 33

已更改 Device Address to DeviceID for FFh in 表 6 ........................................................................................................... 33

已添加 <default at POR> to PWM_FREQ description in 表 7 ............................................................................................. 35

已添加 sentence to IBAT_GAIN description in 表 8 ............................................................................................................ 35

已更改 LDO to internal resistor in EN_LDO description in 表 8 .......................................................................................... 35

已删除 Independent Comparator Reference in 表 10 .......................................................................................................... 36

已删除 Independent Comparator Polarity in 表 10 .............................................................................................................. 37

已删除 Independent Comparator Deglitch Time in 表 10 .................................................................................................... 37

已添加 independent to FORCE_LATCHOFF description in 表 10 ...................................................................................... 37

已添加 <default at POR> to BATFETOFF_ HIZ description in 表 14 .................................................................................. 40

已添加 <default at POR> to PSYS_OTG_ IDCHG description in 表 14 .............................................................................. 40

已添加 PROCHOT Pulse Extension Enable to EN_PROCHOT_EXT description in 表 16.................................................. 41

已添加 There is a 128 mA offset. to IDCHG_VTH description in 表 17 ............................................................................... 43

已更改 0 mA to 000000b in IDCHG_VTH description in 表 17 ............................................................................................ 43

已更改 text in ChargeCurrent Register (SMBus address = 14h) [reset = 0h] ..................................................................... 49

已删除 text and changed larger to 20-mΩ in Input Current Registers ................................................................................. 54

已添加 paragraph to IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]............... 55

已更改 Minimum System Voltage from 614 mV to 6144 mV in Design Requirements........................................................ 66

已删除 Input Snubber and Filter for Voltage Spike Damping section ................................................................................. 66

3

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

5 说明（续）

在加电期间，充电器基于输入源和电池状况，将转换器设置为降压、升压或降压/升压配置。充电器自动在降压、升

压、降压/升压配置间转换，无需主机控制。

在无输入源的情况下，bq25700A 可通过 1 到 4 节电池支持 On-the-Go (OTG) 功能，从而在 VBUS 上生成 4.48V

至 20.8V 电压。在 OTG 模式下，充电器调节输出电压和输出电流。

bq25700A 可监控适配器电流、电池电流和系统功率。灵活编程的 PROCHOT 输出直达 CPU，可根据需要降低其

频率。

4

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

6 Pin Configuration and Functions

RSN Package

32-Pin WQFN

Top View

VBUS

ACN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

HIDRV2

SW2

ACP

VSYS

CHRG_OK

EN_OTG

ILIM_HIZ

VDDA

BATDRV

SRP

Thermal

Pad

SRN

CELL_BATPRESZ

COMP2

IADPT

Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

Input current sense resistor negative input. The leakage on ACP and ACN are matched. The

series resistors on the ACP and ACN pins are placed between sense resistor and filter cap.

Refer to Application and Implementation for ACP/ACN filter design.

ACN

ACP

2

PWR

Input current sense resistor positive input. The leakage on ACP and ACN are matched. The

series resistors on the ACP and ACN pins are placed between sense resistor and filter cap.

Refer to Application and Implementation for ACP/ACN filter design.

3

P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the

BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to

regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on

during fast charge and supplement mode.

BATDRV

21

O

Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor

between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.

BTST1

BTST2

30

25

PWR

Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor

between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.

Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from

VDDA. CELL_BATPRESZ pin also sets SYSOVP threshold to 5 V for 1-cell, 12 V for 2-cell,

and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below V_{CELL_BATPRESZ_FALL}to

indicate battery removal. The device exits LEARN mode, and disables charge. REG0x15()

goes back to default.

CELL_BATPRESZ

18

I

5

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NUMBER

Open drain active high indicator to inform the system good power source is connected to the

charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or

falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below

3.2 V or rises above 26 V, CHRG_OK is LOW. When fault occurs, CHRG_OK is asserted

LOW.

CHRG_OK

4

O

Input of independent comparator. The independent comparator compares the voltage sensed

on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference,

output polarity and deglitch time is selectable by SMBus. With polarity HIGH (REG0x30[6] =

1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW

(REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in

use, tie CMPIN to ground.

CMPIN

14

I

Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup

supply rail. Internal reference, output polarity and deglitch time are selectable by SMBus.

CMPOUT

COMP2

COMP1

15

17

16

O

I

Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin

RC network.

Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin

RC network.

I

Active HIGH to enable OTG mode. When EN_OTG pin is HIGH and REG0x32[13] is HIGH,

OTG can be enabled, refer to USB On-The-Go (OTG) for details of how to enable OTG

function

EN_OTG

5

I

Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET

gate.

HIDRV1

HIDRV2

31

24

O

Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET

gate.

Buffered adapter current output. V_(IADPT)= 20 or 40 × (V_(ACP)– V_(ACN)). With ratio selectable

in REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in

use. For 2.2 µH, the resistor is 137 kΩ. Place 100-pF or less ceramic decoupling capacitor

from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.

IADPT

IBAT

8

9

I/O

O

Buffered battery current selected by SMBus. V_(IBAT)= 8 or 16 × (V_(SRP)– V_(SRN)) for charge

current, or V_(IBAT)= 8 or 16 × (V_(SRN)– V_(SRP)) for discharge current, with ratio selectable in

REG0x12[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground.

This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.

Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from

supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V_{(ILIM_HIZ)}= 1 V + 40

× IDPM × RAC, in which IDPM is the target input current. The input current limit used by the

charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below

0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is

above 0.8 V, the device is out of Hi-Z mode.

ILIM_HIZ

LODRV1

6

I

Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET

gate.

29

O

Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET

gate.

LODRV2

PGND

26

27

O

GND

Device power ground.

Active low open drain output of processor hot indicator. It monitors adapter input current,

battery discharge current, and system voltage. After any event in the PROCHOT profile is

triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x33[5:2].

PROCHOT

11

10

28

O

Current mode system power monitor. The output current is proportional to the total power

from the adapter and battery. The gain is selectable through SMBus. Place a resistor from

PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output

voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering.

PSYS

O

6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS

above V_{VBUS_CONVEN}. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power

ground. REGN pin output is for power stage gate drive.

REGN

PWR

SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a

10-kΩ pullup resistor according to SMBus specifications.

SCL

SDA

13

12

I

SMBus open-drain data I/O. Connect to data line from the host controller or smart battery.

Connect a 10-kΩ pullup resistor according to SMBus specifications.

I/O

6

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NUMBER

Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well.

Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering.

Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering.

The leakage current on SRP and SRN are matched. For reverse battery plug-in protection,

10-Ω series resistors are placed on SRP and SRN.

SRN

19

PWR

Charge current sense resistor positive input. Connect 0.1-μF ceramic capacitor from SRP to

SRN to provide differential mode filtering. The leakage current on SRP and SRN are

matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and

SRN. Connect SRP pin with optional 0.1-uF ceramic capacitor to GND for common-mode

filtering.

SRP

20

PWR

Buck mode high side power MOSFET driver source. Connect to the source of the high side

n-channel MOSFET.

SW1

32

23

1

PWR

Boost mode high side power MOSFET driver source. Connect to the source of the high side

n-channel MOSFET.

SW2

Charger input voltage. An input low pass filter of 1Ω and 0.47 µF (minimum) is

recommended.

VBUS

VDDA

VSYS

Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF

ceramic capacitor from VDDA to power ground.

7

Charger system voltage sensing. The system voltage regulation limit is programmed in

REG0x15() and REG0x3E().

22

Exposed pad beneath the IC. Analog ground and power ground star-connected near the IC's

ground. Always solder thermal pad to the board, and have vias on the thermal pad plane

connecting to power ground planes. It also serves as a thermal pad to dissipate the heat.

Thermal pad

–

7

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

–2.0

–0.3

–4.0

MAX

30

36

7

UNIT

SRN, SRP, ACN, ACP, VBUS, VSYS, BATDRV

SW1, SW2

BTST1, BTST2, HIDRV1, HIDRV2

LODRV1, LODRV2 (2% duty cycle)

HIDRV1, HIDRV2 (2% duty cycle)

36

30

Voltage

V

SW1, SW2 (2% duty cycle)

SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ,

ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2,

CMPIN, CMPOUT, EN_OTG

–0.3

7

PROCHOT

–0.3

–0.5

–40

5.5

3.6

7

IADPT, IBAT, PSYS

BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2

Differential voltage

V

SRP-SRN, ACP-ACN

0.5

155

Junction temperature range, T_J

Storage temperature, T_stg

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

24

UNIT

ACN, ACP, VBUS

0

SRN, SRP, VSYS, BATDRV

SW1, SW2

19.2

24

–2

0

BTST1, BTST2, HIDRV1, HIDRV2

30

Voltage

V

SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1,

LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT

0

6.5

PROCHOT

0

5.3

3.3

IADPT, IBAT, PSYS

BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2

SRP-SRN, ACP-ACN

0

6.5

Differential

voltage

V

–0.35

–40

0.35

125

85

Junction temperature, T_J

°C

Operating free-air temperature, T_A

8

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

7.4 Thermal Information

bq25700A

THERMAL METRIC⁽¹⁾

RSN (WQFN)

UNIT

32 PINS

37.2

26.1

7.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

7.8

R_θJC(bot)

2.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

Input voltage operating range

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{INPUT_OP}

3.5

26

V

REGULATION ACCURACY

MAX SYSTEM VOLTAGE REGULATION

System voltage regulation,

measured on V_SYS

V_{SYSMAX_RNG}

1.024

19.2

V

V_SRN+ 160 mV

REG0x15() = 0x41A0H

(16.800 V)

–2%

–3%

2%

3%

V

REG0x15() = 0x3130H

(12.592 V)

System voltage regulation

accuracy (charge disable)

V_{SYSMAX_ACC}

REG0x15() = 0x20D0H

(8.400 V)

REG0x15() = 0x1060H

(4.192 V)

MINIMUM SYSTEM VOLTAGE REGULATION

System voltage regulation,

V_{SYSMIN_RNG}

1.024

19.2

V

measured on V_SYS

12.288

9.216

6.144

3.584

REG0x3E() = 0x3000H

REG0x3E() = 0x2400H

REG0x3E() = 0x1800H

REG0x3E() = 0x0E00H

–2%

2%

V

Minimum system voltage

regulation accuracy (charge

enable, VBAT below

V_{SYSMIN_REG_ACC}

REG0x3E() setting)

–3%

3%

–3%

4%

CHARGE VOLTAGE REGULATION

V_{BAT_RNG}

Battery voltage regulation

1.024

–0.5%

–0.6%

–1.1%

19.2

0.5%

0.6%

1.2%

V

16.8

12.592

8.4

REG0x15() = 0x41A0H

REG0x15() = 0x3130H

REG0x15() = 0x20D0H

REG0x15() = 0x1060H

V

Battery voltage regulation

accuracy (charge enable)

(0°C to 85°C)

V_{BAT_REG_ACC}

4.192

9

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

MAX UNIT

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

CHARGE CURRENT REGULATION IN FAST CHARGE

Charge current regulation

differential voltage range

VIREG_CHG = VSRP –

VSRN

V_{IREG_CHG_RNG}

0

81.28

mV

mA

4096

2048

1024

512

REG0x14() = 0x1000H

REG0x14() = 0x0800H

REG0x14() = 0x0400H

REG0x14() = 0x0200H

–3%

–4%

2%

3%

mA

Charge current regulation

accuracy 10-mΩ current

sensing resistor, VBAT above

0x3E() setting (0°C to 85°C)

I_{CHRG_REG_ACC}

–5%

6%

–12%

12%

CHARGE CURRENT REGULATION IN LDO MODE

CELL 2s-4s

384

mA

CELL 1 s, V_SRN< 3 V

I_CLAMP

Pre-charge current clamp

CELL 1 s, 3 V < V_SRN

VSYSMIN

<

2

A

REG0x14() = 0x0180H

384

mA

2S-4S

–15%

–25%

15%

25%

1S

REG0x14() = 0x0100H

256

192

128

mA

Pre-charge current regulation

accuracy with 10-Ω SRP/SRN

series resistor, VBAT below

REG0x3E() setting (0°C to

85°C)

2S-4S

–20%

–35%

20%

35%

I_{PRECHRG_REG_ACC}

1S

REG0x14() = 0x00C0H

2S-4S

–25%

–50%

25%

50%

1S

REG0x14() = 0x0080H

2S-4S

mA

µA

–30%

–12

30%

10

SRP, SRN leakage current

mismatch (0°C to 85°C)

I_{LEAK_SRP_SRN}

INPUT CURRENT REGULATION

Input current regulation

V_{IREG_DPM_RNG}

V_{IREG_DPM}= V_ACP– V_ACN

0.5

64

mV

differential voltage range

REG0x3F() = 0x4FFFH

REG0x3F() = 0x3BFFH

REG0x3F() = 0x1DFFH

REG0x3F() = 0x09FFH

3820

2830

1350

340

4000

3000

1500

500

mA

Input current regulation

accuracy (–40°C to 105°C)

with 10-Ω ACP/ACN series

resistor

I_{DPM_REG_ACC}

ACP, ACN leakage current

mismatch

I_{LEAK_ACP_ACN}

–16

1

10

4

µA

V

Voltage Range for input

current regulation

V_{IREG_DPM_RNG_ILIM}

V_{ILIM_HIZ}= 2.6 V

V_{ILIM_HIZ}= 2.2 V

V_{ILIM_HIZ}= 1.6 V

V_{ILIM_HIZ}= 1.2 V

3800

2800

1300

300

4000

3000

1500

500

4200

3200

1700

700

1

mA

µA

Input Current Regulation

Accuracy on ILIM_HIZ pin

V_{ILIM_HIZ}= 1 V + 40 × IDPM ×

R_AC, with 10-Ω ACP/ACN

series resistor

I_{DPM_REG_ACC_ILIM}

I_{LEAK_ILIM}

I_{LIM_HIZ}pin leakage

–1

INPUT VOLTAGE REGULATION

V_{IREG_DPM_RNG}Input voltage regulation range Voltage on VBUS

3.2

19.52

V

10

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–2%

TYP

MAX UNIT

REG0x3D()=0x3C80H

18688

mV

2%

mV

REG0x3D()=0x1E00H

REG0x3D()=0x0500H

10880

4480

Input voltage regulation

V_{DPM_REG_ACC}

accuracy

–2.5%

–3%

2.5%

mV

5%

OTG CURRENT REGULATION

Input current regulation

V_{IOTG_REG_RNG}

V_{IREG_DPM}= V_ACP– V_ACN

0

81.28

mV

differential voltage range

Input current regulation

accuracy with 50-mA LSB,

with 10-Ω ACP/ACN series

resistor

REG0x3C() = 0x3C00H

REG0x3C() = 0x1E00H

REG0x3C() = 0x0A00H

2800

1300

300

3000

1500

500

3200

1700

700

mA

I_{OTG_ACC}

OTG VOLTAGE REGULATION

V_{IREG_DPM_RNG}

Input voltage regulation range Voltage on VBUS

4.48

–2%

–3%

20.8

2%

3%

V

20.032

12.032

5.056

REG0x3B()=0x3CC0H

REG0x3B()=0x1D80H

REG0x3B()=0x0240H

V

OTG voltage regulation

accuracy

V_{OTG_REG_ACC}

REFERENCE AND BUFFER

REGN REGULATOR

REGN regulator voltage (0

mA–60 mA)

V_{REGN_REG}

V_DROPOUT

I_{REGN_LIM_Charging}

C_REGN

V_VBUS= 10 V

5.7

3.8

50

2.2

1

6

4.3

65

6.3

4.6

V

REGN voltage in drop out

mode

V_VBUS= 5 V, I_LOAD= 20 mA

REGN current limit when

converter is enabled

V_VBUS= 10 V, force V_REGN

4 V

=

mA

µF

REGN output capacitor

required for stability

I_LOAD= 100 µA to 50 mA

REGN output capacitor

required for stability

C_VDDA

QUIESCENT CURRENT

VBAT = 18 V, REG0x12[15]

= 1, in low power mode

22

45

µA

VBAT = 18 V, REG0x12[15]

= 1, REG0x30[14:13] = 01,

REGN off

105

175

System powered by battery.

VBAT=18 V, REG0x12[15] =

1, REG0x30[14:13] = 10,

REGN off

BATFET on. I_SRN+ I_SRP

+

60

860

960

90

1150

1250

µA

I_{BAT_BATFET_ON}

I_SW2+ I_BTST2+ I_SW1+ I_BTST1

_ACP+ I_ACN+ I_VBUS+ I_VSYS

+

VBAT = 18 V, REG0x12[15]

= 0, REG0x30[12] = 0,

REGN on, EN_PSYS

VBAT = 18 V, REG0x12[15]

= 0, REG0x30[12] = 1,

REGN on

Input current during PFM in

buck mode, no load, I_VBUS

+

VIN = 20 V, VBAT = 12.6 V,

3 s, REG0x12[10] = 0;

MOSFET Qg = 4 nC

I_{AC_SW_LIGHT_buck}

I_ACP+ I_ACN+ I_VSYS+ I_SRP

I_SRN+ I_SW1+ I_BTST+ I_SW2

I_BTST2

+

2.2

mA

11

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input current during PFM in

boost mode, no load, I_VBUS

I_ACP+ I_ACN+ I_VSYS+ I_SRP

I_SRN+ I_SW1+ I_BTST2+ I_SW2

I_BTST2

+

VIN = 5 V, VBAT = 8.4 V, 2

s, REG0x12[10] = 0;

MOSFET Qg = 4 nC

I_{AC_SW_LIGHT_boost}

+

2.7

mA

+

Input current during PFM in

buck boost mode, no load,

VIN = 12 V, VBAT = 12 V,

REG0x12[10] = 0; MOSFET

Qg = 4 nC

I_{AC_SW_LIGHT_buckboost}I_VBUS+ I_ACP+ I_ACN+ I_VSYS

I_SRP+ I_SRN+ I_SW1+ I_BTST1

+

2.4

mA

I_SW2+ I_BTST2

VBAT = 8.4 V, VBUS = 5 V,

800-kHz switching

frequency, MOSFET Qg = 4

nC

3

4.2

6.2

3.2

Quiescent current during PFM VBAT = 8.4 V, VBUS = 12

in OTG mode I_VBUS+ I_ACP

I_ACN+ I_VSYS+ I_SRP+ I_SRN

I_SW1+ I_BTST2+ I_SW2+ I_BTST2

+

V, 800-kHz switching

frequency, MOSFET Qg = 4

nC

I_{OTG_STANDBY}

mA

VBAT = 8.4 V, VBUS = 20

V, 800-kHz switching

frequency, MOSFET Qg = 4

nC

V_{ACP/N_OP}

V_{IADPT_CLAMP}

I_IADPT

Input common mode range

I_ADPToutput clamp voltage

I_ADPToutput current

Voltage on ACP/ACN

3.8

3.1

26

3.3

1

V

mA

V_(IADPT)/ V_(ACP-ACN)

REG0x12[4] = 0

,

20

40

V/V

A_IADPT

Input current sensing gain

V_(IADPT)/ V_(ACP-ACN)

REG0x12[4] = 1

V_(ACP-ACN)= 40.96 mV

V_(ACP-ACN)= 20.48 mV

V_(ACP-ACN)=10.24 mV

V_(ACP-ACN)= 5.12 mV

–2%

–3%

2%

3%

Input current monitor

accuracy

V_{IADPT_ACC}

–6%

6%

–10%

10%

Maximum output load

capacitance

C_{IADPT_MAX}

100

pF

V_{SRP/N_OP}

V_{IBAT_CLAMP}

I_IBAT

Battery common mode range Voltage on SRP/SRN

IBAT output clamp voltage

2.5

18

3.3

1

V

3.05

3.2

IBAT output current

mA

V_(IBAT)/ V_(SRN-SRP)

REG0x12[3] = 0,

,

8

V/V

Charge and discharge current

sensing gain on IBAT pin

A_IBAT

V_(IBAT)/ V_(SRN-SRP)

REG0x12[3] = 1,

16

V_(SRN-SRP)= 40.96 mV

V_(SRN-SRP)= 20.48 mV

V_(SRN-SRP)=10.24 mV

V_(SRN-SRP)= 5.12 mV

–2%

–3%

2%

4%

Charge and discharge current

monitor accuracy on IBAT pin

I_{IBAT_CHG_ACC}

–6%

6%

–12%

12%

Maximum output load

capacitance

C_{IBAT_MAX}

100

pF

SYSTEM POWER SENSE AMPLIFIER

V_PSYSPSYS output voltage range

I_PSYS

0

3.3

V

PSYS output current

PSYS system gain

160

µA

V_(PSYS)/ (P_(IN)+ P_(BAT))

REG0x30[9] = 1

,

A_PSYS

1

µA/W

12

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Adapter only with system

power = 19.5 V / 45 W, T_A

0 to 85°C

=

–5%

5%

Adapter only with system

power = 19.5 V / 45 W, T_A

–40 to 125°C

–7%

–5%

6%

5%

6%

PSYS gain accuracy

V_{PSYS_ACC}

(REG0x30[9] = 1)

Battery only with system

power = 11 V / 44 W, T_A= 0

to 85°C

Battery only with system

power = 11 V / 44 W, T_A

–40 to 125°C

=

–6%

3

V_{PSYS_CLAMP}

PSYS clamp voltage

3.3

V

COMPARATOR

VBUS UNDER VOLTAGE LOCKOUT COMPARATOR

VBUS undervoltage rising

V_{VBUS_UVLOZ}

threshold

VBUS rising

VBUS falling

2.34

2.2

2.55

2.4

2.77

2.6

V

VBUS undervoltage falling

V_{VBUS_UVLO}

threshold

VBUS undervoltage

V_{VBUS_UVLO_HYST}

150

3.5

mV

V

hysteresis

VBUS converter enable rising

V_{VBUS_CONVEN}

threshold

VBUS rising

VBUS falling

3.2

2.9

3.9

3.5

VBUS converter enable falling

V_{VBUS_CONVENZ}

threshold

3.2

V

VBUS converter enable

V_{VBUS_CONVEN_HYST}

400

mV

hysteresis

BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR

VBAT undervoltage rising

threshold

V_{VBAT_UVLOZ}

V_{VBAT_UVLO}

V_{VBAT_UVLO_HYST}

V_{VBAT_OTGEN}

VSRN rising

2.35

2.2

2.55

2.4

2.75

2.6

V

VBAT undervoltage falling

threshold

VSRN falling

VBAT undervoltage

hysteresis

150

3.55

mV

V

VBAT OTG enable rising

threshold

VSRN rising

VSRN falling

3.3

3

3.75

3.4

VBAT OTG enable falling

threshold

V_{VBAT_OTGENZ}

3.2

V

V_{VBAT_OTGEN_HYST}

VBAT OTG enable hysteresis

350

mV

VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)

VBUS undervoltage falling

threshold

As percentage of

REG0x3B()

V_{VBUS_OTG_UV}

t_{VBUS_OTG_UV}

85.0%

7

VBUS undervoltage deglitch

time

ms

VBUS OVER VOLTAGE COMPARATOR (OTG MODE)

VBUS overvoltage rising

As percentage of

REG0x3B()

V_{VBUS_OTG_OV}

threshold

105%

10

VBUS Over-Voltage Deglitch

Time

t_{VBUS_OTG_OV}

LDO mode to fast charge

V_{BAT_SYSMIN_RISE}

as percentage of 0x3E()

98%

100%

97.5%

102%

mode threshold, VSRN rising

LDO mode to fast charge

V_{BAT_SYSMIN_FALL}

mode threshold, VSRN falling

13

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

MAX UNIT

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

Fast charge mode to LDO

V_{BAT_SYSMIN_HYST}

as percentage of 0x3E()

2.5%

mode threshold hysteresis

BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Thresold for 1S)

V_{BATLV_FALL}

V_{BATLV_RISE}

V_{BATLV_RHYST}

BATLOWV falling threshold

BATLOWV rising threshold

BATLOWV hysteresis

1 s

2.80

3.00

200

V

mV

INPUT OVER-VOLTAGE COMPARATOR (ACOVP)

VBUS overvoltage rising

V_{ACOV_RISE}

threshold

VBUS rising

VBUS falling

25

24

26

27

25

V

VBUS overvoltage falling

V_{ACOV_FALL}

threshold

24.5

1.5

V

V_{ACOV_HYST}

VBUS overvoltage hysteresis

VBUS overvoltage rising

deglitch

VBUS rising to stop

converter

t_{ACOV_RISE_DEG}

100

µs

VBUS overvoltage falling

deglitch

VBUS falling to start

converter

t_{ACOV_FALL_DEG}

1

ms

INPUT OVER CURRENT COMPARATOR (ACOC)

ACP to ACN rising threshold, Voltage across input sense

V_ACOC

w.r.t. ILIM2 in

REG0x33[15:11]

resistor rising, Reg0x31[2] =

1

195%

210%

225%

Measure between ACP and

ACN

V_{ACOC_FLOOR}

V_{ACOC_CEILING}

t_{ACOC_DEG_RISE}

t_{ACOC_RELAX}

Set IDPM to minimum

Set IDPM to maximum

44

50

180

250

56

mV

µs

Measure between ACP and

ACN

172

188

Deglitch time to trigger

ACOC

Rising deglitch time

Relax time

Relax time before converter

starts again

ms

SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)

1 s

2 s

3 s

4 s

1 s

2 s

3 s

4 s

4.85

11.7

19

5

12

5.1

12.2

20

System overvoltage rising

V_{SYSOVP_RISE}

V

threshold to turn off converter

19.5

4.8

19

20

11.5

19

System overvoltage falling

threshold

V_{SYSOVP_FALL}

V

19

Discharge current when

I_SYSOVP

SYSOVP stop switching was on SYS

triggered

20

mA

BAT OVER-VOLTAGE COMPARATOR (BATOVP)

Overvoltage rising threshold

as percentage of V_{BAT_REG}in

REG0x15()

1 s, 4.2 V

2 s - 4 s

102.5%

100%

104%

102%

2%

106%

105%

104%

103%

V_{BATOVP_RISE}

Overvoltage falling threshold 1 s

as percentage of VBAT_REG

in REG0x15()

V_{BATOVP_FALL}

2 s - 4 s

100%

Overvoltage hysteresis as

percentage of V_{BAT_REG}in

REG0x15()

1 s

V_{BATOVP_HYST}

2 s - 4 s

2%

Discharge current during

BATOVP

I_BATOVP

on VSYS pin

20

mA

14

bq25700A

www.ti.com.cn

ZHCSGD7A –MAY 2017–REVISED MAY 2018

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Overvoltage rising deglitch to

t_{BATOVP_RISE}

turn off BATDRV to disable

charge

20

ms

CONVERTER OVER-CURRENT COMPARATOR (Q2)

Reg0x31[5]=1

150

210

45

VOCP_limit_Q2

Converter Over-Current Limit

System Short or SRN<2.5 V

mV

Reg0x31[5]=0

Reg0x31[5]=1

Reg0x31[5]=0

VOCP_limit_SYSSH

ORT_Q2

60

CONVERTER OVER-CURRENT COMPARATOR (ACX)

Reg0x31[4]=1

Reg0x31[4]=0

Reg0x31[4]=1

Reg0x31[4]=0

150

280

90

VOCP_limit_ACX

Converter Over-Current Limit

System Short or SRN<2.5 V

mV

VOCP_limit_SYSSH

ORT_ACX

150

THERMAL SHUTDOWN COMPARATOR

Thermal shutdown rising

temperature

T_{SHUT_RISE}

Temperature increasing

Temperature reducing

155

°C

Thermal shutdown falling

temperature

T_{SHUTF_FALL}

T_{SHUT_HYS}

t_{SHUT_RDEG}

135

20

°C

µs

Thermal shutdown hysteresis

Thermal shutdown rising

deglitch

100

Thermal shutdown falling

deglitch

t_{SHUT_FHYS}

12

ms

VSYS PROCHOT COMPARATOR

Reg0x33[7:6] = 00, 1 s

Reg0x33[7:6] = 00, 2–4 s

Reg0x33[7:6] = 01, 1 s

Reg0x33[7:6] = 01, 2–4 s

Reg0x33[7:6] = 10, 1 s

Reg0x33[7:6] = 10, 2–4 s

Reg0x33[7:6] = 11, 1 s

Reg0x33[7:6] = 11, 2–4 s

2.85

5.75

3.1

V

2.95

5.8

3.25

6.1

V

5.95

3.3

V_SYSthreshold falling

threshold

V_{SYS_PROCHOT}

6.25

3.5

6.5

V_SYSrising deglitch for

throttling

t_{SYS_PRO_RISE_DEG}

8

µs

ICRIT PROCHOT COMPARATOR

Input current rising threshold Reg0x33[15:11] = 00000

for throttling as 10% above

105%

142%

110%

150%

116%

156%

V_{ICRIT_PRO}

Reg0x33[15:11] = 01001

ILIM2 (REG0x33[15:11])

INOM PROCHOT COMPARATOR

INOM rising threshold as 10%

above IIN (REG0x3F())

IDCHG PROCHOT COMPARATOR

IDCHG threshold for throttling

V_{INOM_PRO}

105%

95%

110%

6272

116%

102%

mA

V_{IDCHG_PRO}

Reg0x34[15:10] =001100

for IDSCHG of 6 A

INDEPENDENT COMPARATOR

Reg0x30[7] = 1, CMPIN

falling

1.17

2.27

1.2

2.3

1.23

2.33

V

Independent comparator

threshold

V_{INDEP_CMP}

Reg0x30[7] = 0, CMPIN

falling

15

bq25700A

ZHCSGD7A –MAY 2017–REVISED MAY 2018

www.ti.com.cn

Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Independent comparator

Reg0x3B[6] = 0, CMPIN

falling

V_{INDEP_CMP_HYS}

hysteresis

100

mV

POWER MOSFET DRIVER

PWM OSCILLATOR AND RAMP

Reg0x12[9] = 0

Reg0x12[9] = 1

1020

680

1200

800

1380

920

kHz

F_SW

PWM switching frequency

BATFET GATE DRIVER (BATDRV)

Gate drive voltage on

BATFET

V_{BATDRV_ON}

8.5

10

30

11.5

V

Drain-source voltage on

BATFET during ideal diode

operation

V_{BATDRV_DIODE}

mV

Measured by sourcing 10-µA

current to BATDRV

R_{BATDRV_ON}

R_{BATDRV_OFF}

3

4

6

kΏ

Measured by sinking 10-µA

current from BATDRV

1.2

2.1

PWM HIGH SIDE DRIVER (HIDRV Q1)

High side driver (HSD) turnon

resistance

R_{DS_HI_ON_Q1}

V_BTST1– V_SW1= 5 V

6

Ω

High side driver turnoff

resistance

R_{DS_HI_OFF_Q1}

1.3

2.2

4.6

V_BTST1– V_SW1when low

side refresh pulse is

requested

Bootstrap refresh comparator

falling threshold voltage

V_{BTST1_REFRESH}

3.2

3.7

V

PWM HIGH SIDE DRIVER (HIDRV Q4)

High side driver (HSD) turnon

R_{DS_HI_ON_Q4}

V_BTST2– V_SW2= 5 V

6

Ω

resistance

High side driver turnoff

resistance

R_{DS_HI_OFF_Q4}

1.5

2.4

4.6

V_BTST2– V_SW2when low

side refresh pulse is

requested

Bootstrap refresh comparator

falling threshold voltage

V_{BTST2_REFRESH}

3.3

3.7

V

PWM LOW SIDE DRIVER (LODRV Q2)

Low side driver (LSD) turnon

R_{DS_LO_ON_Q2}

V_BTST1– V_SW1= 5.5 V

6

Ω

resistance

Low side driver turnoff

resistance

R_{DS_LO_OFF_Q2}

1.7

2.6

4.6

PWM LOW SIDE DRIVER (LODRV Q3)

Low side driver (LSD) turnon

resistance

R_{DS_LO_ON_Q3}

V_BTST2– V_SW2= 5.5 V

7.6

2.9

Ω

Low side driver turnoff

resistance

R_{DS_LO_OFF_Q3}

INTERNAL SOFT START During Charge Enable

SSSTEP_DAC

Soft Start Step Size

Soft Start Step Time

64

8

mA

µs

INTEGRATED BTST DIODE (D1)

V_{F_D1}

V_{R_D1}

Forward bias voltage

Reverse breakdown voltage

I_F= 20 mA at 25°C

I_R= 2 µA at 25°C

0.8

V

20

INTEGRATED BTST DIODE (D2)

V_{F_D2}

Forward bias voltage

Reverse breakdown voltage

I_F= 20 mA at 25°C

I_R= 2 µA at 25°C

V

V_{R_D2}

PWM DRIVERS TIMING

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Electrical Characteristics (continued)

over T_J= –40 to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INTERFACE

LOGIC INPUT (SDA, SCL, EN_OTG)

V_{IN_ LO}

V_{IN_ HI}

Input low threshold

Input high threshold

SMBus

SMBus (bq25700A)

0.8

V

2.1

–1

LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)

V_{OUT_ LO}

Output saturation voltage

Leakage current

5-mA drain current

V = 7 V

0.4

1

V

V_{OUT_ LEAK}

mA

LOGIC OUTPUT OPEN DRAIN SDA

V_{OUT_ LO_SDA}

Output Saturation Voltage

Leakage Current

5 mA drain current

V = 7V

0.4

1

V

V_{OUT_ LEAK_SDA}

mA

LOGIC OUTPUT OPEN DRAIN CHRG_OK

V_{OUT_ LO_CHRG_OK}Output Saturation Voltage

5 mA drain current

V = 7V

0.4

1

V

V_{OUT_ LEAK _CHRG_OK}Leakage Current

mA

LOGIC OUTPUT OPEN DRAIN CMPOUT

V_{OUT_ LO_CMPOUT}

Output Saturation Voltage

Leakage Current

5 mA drain current

V = 7V

0.4

1

V

V_{OUT_ LEAK _CMPOUT}

mA

LOGIC OUTPUT OPEN DRAIN (PROCHOT)

50-Ω pullup to 1.05 V / 5-mA

load

V_{OUT_ LO_PROCHOT}Output saturation voltage

300

1

mV

mA

V_{OUT_ LEAK_PROCHOT}Leakage current

V = 5.5 V

–1

ANALOG INPUT (ILIM_HIZ)

Voltage to get out of HIZ

mode

V_{HIZ_ LO}

ILIM_HIZ pin rising

ILIM_HIZ pin falling

0.8

V

V_{HIZ_ HIGH}

Voltage to enable HIZ mode

0.4

ANALOG INPUT (CELL_BATPRESZ)

REGN = 6 V, as percentage

of REGN

V_{CELL_4S}

V_{CELL_3S}

V_{CELL_2S}

V_{CELL_1S}

4S

3S

2S

1S

68.4%

51.7%

35%

75%

55%

40%

25%

REGN = 6 V, as percentage

of REGN

65%

49.1%

31.6%

REGN = 6 V, as percentage

of REGN

REGN = 6 V, as percentage

of REGN

18.4%

18%

V_{CELL_BATPRESZ_RISE}Battery is present

V_{CELL_BATPRESZ_FALL}Battery is removed

ANALOG INPUT (COMP1, COMP2)

CELL_BATPRESZ falling

15%

I_{LEAK_COMP1}

I_{LEAK_COMP2}

COMP1 Leakage

COMP2 Leakage

–120

120

nA

7.6 Timing Requirements

MIN TYP MAX UNIT

SMBus TIMING CHARACTERISTICS

t_r

SCLK/SDATA rise time

SCLK/SDATA fall time

1

300

50

µs

ns

µs

t_f

t_W(H)

t_W(L)

t_SU(STA)

t_H(STA)

SCLK pulse width high

SCLK Pulse Width Low

Setup time for START condition

4

4.7

4

START condition hold time after which first clock pulse is generated

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Timing Requirements (接下页)

MIN TYP MAX UNIT

t_SU(DAT)

t_H(DTA)

t_SU(STOP)

t_(BUF)

Data setup time

250

300

4

ns

Data hold time

Setup time for STOP condition

Bus free time between START and STOP condition

Clock Frequency

µs

4.7

10

µs

F_S(CL)

100

35

KHz

HOST COMMUNICATION FAILURE

t_timeout

t_BOOT

SMBus bus release timeout⁽¹⁾

25

10

ms

s

Deglitch for watchdog reset signal

Watchdog timeout period, ChargeOption() bit [14:13] = 01⁽²⁾

Watchdog timeout period, ChargeOption() bit bit [14:13] = 10⁽²⁾

Watchdog timeout period, ChargeOption() bit bit [14:13] = 11⁽²⁾(default)

35

44

88

53

105

210

t_WDI

70

s

140

175

s

(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have

detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave

must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25

ms).

(2) User can adjust threshold via SMBus ChargeOption() REG0x12.

7.7 Typical Characteristics

90

85

80

75

70

65

60

90

85

80

75

70

65

60

VOUT = 6.1 V

VOUT = 8.4 V

VOUT = 9.2 V

VOUT = 12.5 V

VOUT = 6.1 V

VOUT = 8.4 V

VOUT = 9.2 V

VOUT = 12.5 V

0

0.01

0.02

0.03

0.04

0.05

0

0.01

0.02

0.03

0.04

0.05

Output Current (A)

D001

VIN = 5 V

VIN = 12 V

图 1. Light Load Efficiency

图 2. Light Load Efficiency

90

85

80

75

70

65

60

96

94

92

90

88

86

84

82

80

VOUT = 6.1 V

VOUT = 3.7 V

VOUT = 8.4 V

VOUT = 9.2 V

VOUT = 12.5 V

VOUT = 7.4 V

VOUT = 11.1 V

VOUT = 14.8 V

0

0.01

0.02

0.03

0.04

0.05

0

1

2

3

4

5

6

Output Current (A)

D001

VIN = 20 V

VIN = 5 V

图 3. Light Load Efficiency

图 4. System Efficiency

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Typical Characteristics (接下页)

98

96

94

92

90

88

86

84

82

80

98

96

94

92

90

88

86

84

82

80

VOUT = 3.7 V

VOUT = 7.4 V

VOUT = 11.1 V

VOUT = 14.8 V

VOUT = 3.7 V

VOUT = 7.4 V

VOUT = 11.1 V

VOUT = 14.8 V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Output Current (A)

D001

VIN = 9 V

VIN = 12 V

图 5. System Efficiency

图 6. System Efficiency

98

96

94

92

90

88

86

84

82

80

96

94

92

90

88

86

84

82

80

VOTG = 5 V

VOTG = 12 V

VOTG = 20 V

VOUT = 3.7 V

VOUT = 7.4 V

VOUT = 11.1 V

VOUT = 14.8 V

0

1

2

3

4

5

6

0

1

2

3

4

5

Output Current (A)

D001

VIN = 20 V

图 7. System Efficiency

图 8. OTG Efficiency with 1S Battery

96

94

92

90

88

86

84

82

80

98

96

94

92

90

88

86

84

82

80

VOTG = 5 V

VOTG = 12 V

VOTG = 20 V

VOTG = 5 V

VOTG = 12 V

VOTG = 20 V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Output Current (A)

D001

图 9. OTG Efficiency with 2S Battery

图 10. OTG Efficiency with 3S Battery

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Typical Characteristics (接下页)

98

96

94

92

90

88

86

84

82

VOTG = 5 V

VOTG = 12 V

VOTG = 20 V

80

0

1

2

3

4

5

6

Output Current (A)

D001

图 11. OTG Efficiency with 4S Battery

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8 Detailed Description

8.1 Overview

The bq25700A is a buck boost NVDC (narrow voltage DC) charge controller for multi-chemistry portable

applications such as notebook, detachable, ultrabook, tablet and other mobile devices with rechargeable

batteries. It provides seamless transition between converter operation modes (buck, boost, or buck boost), fast

transient response, and high light load efficiency.

The bq25700A supports wide range of power sources, including USB PD ports, legacy USB ports, traditional AC-

DC adapters, etc. It takes input voltage from 3.5 V to 24 V, and charges battery of 1-4 series. It also supports

USB On-The-Go (OTG) to provide 4.48V to 20.8V output at USB port.

The bq25700A features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter

overloading. During battery charging, as the system power increases, the charging current will reduce to maintain

total input current below adapter rating. If system power demand temporarily exceeds adapter rating, the

bq25700A supports NVDC architecture to allow battery discharge energy to supplement system power. For

details, refer to System Voltage Regulation section.

In order to be compliant with an Intel IMVP8 compliant system, the bq25700A includes PSYS function to monitor

the total platform power from adapter and battery. Besides PSYS, it provides both an independent input current

buffer (IADPT) and a battery current buffer (IBAT) with highly accurate current sense amplifiers. If the platform

power exceeds the available power from adapter and battery, a PROCHOT signal is asserted to CPU so that the

CPU optimizes its performance to the power available to the system.

The SMBus controls input current, charge current and charge voltage registers with high resolution, high

accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements.

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8.2 Functional Block Diagram

4

CHRG_OK

CHRG_OK_DRV

50ms Rising

Deglitch

bq25700A Block Diagram

** programmable in register

EN_REGN

50ms Rising

Deglitch

3.9V

26V

1

VBUS

VREF_CMP**

14

CMP_DEG**

CMPIN

ACOVP

15

CMPOUT

VREF_VDPM or VREF_VOTG

VSNS_VDPM or VSYS_VOTG

COMP1

COMP2

16

17

EN_HIZ

VREF_ILIM

6

Decoder

ILIM_HIZ

VSYS

VREF_IDPM, or VREF_IOTG

2

3

LDO Mode

Gate Control

ACP

ACN

VSNS_IDPM, or VSNS_IOTG

21

BATDRV

20X**

VSYS-10V

8

9

IADPT

IBAT

VSNS_ICHG

30

31

32

7

BTST1

VSNS_IDCHG

HIDRV1

Loop Selector

and

Error Amplifier

SW1

16X

PWM

VREF_ICHG

VSNS_ICHG

VDDA

EN_REGN

20

19

REGN

LDO

SRP

SRN

REGN

28

20X**

EN_HIZ

EN_LEARN

EN_LDO

VREF_VBAT

VSNS_VBAT

EN_CHRG

EN_OTG

PWM

Driver

Logic

29

27

25

24

23

LODRV1

PGND

BTST2

HIDRV2

SW2

22

VREF_VSYS

VSNS_VSYS

VSYS

VSNS_VSYS

ACN

Over

Current

Over

Voltage

Detect

VSNS_VBAT

VSNS_ICHG

VSNS_IDCHG

VSNS_IDPM

VSNS_VDPM

(ACP-ACN)

SRN

10

12

PSYS

SDA

(SRN-SRP)

26

18

LODRV2

EN_HIZ

SMBUS

Interface

EN_LEARN

EN_LDO

EN_CHRG

EN_OTG

BATPRESZ

CELL_CONFIG

ChargeOption0()

ChargeOption1()

ChargeOption2()

ChargeCurrent()

ChargeVoltage()

InputCurrent()

InputVoltage()

MinSysVoltage()

OTGVoltage()

OTGCurrent()

Decoder

CELL_BATPRESZ

VREF_VSYS

13

5

SCL

VREF_VBAT

VREF_ICHG

VREF_IDPM

VREF_VDPM

VREF_IOTG

VREF_VOTG

Loop

Regulation

Reference

IADPT

IBAT

EN_OTG

Processor

Hot

11

PROCHOT

VSYS

CHRG_OK

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ZHCSGD7A –MAY 2017–REVISED MAY 2018

8.3 Feature Description

8.3.1 Power-Up from Battery Without DC Source

If only battery is present and the voltage is above V_{VBAT_UVLOZ}, the BATFET turns on and connects battery to

system. By default, the charger is in low power mode (REG0x12[15] = 1) with lowest quiescent current. The LDO

stays off. When device moves to performance mode (REG0x12[15] = 0), The host enables IBAT buffer through

SMBus to monitor discharge current. For PSYS, PROCHOT or independent comparator, REGN LDO is enabled

for an accurate reference.

8.3.2 Power-Up From DC Source

When an input source plugs in, the charger checks the input source voltage to turn on LDO and all the bias

circuits. It sets the input current limit before the converter starts.

The power-up sequence from DC source is as follows:

1. 50 ms after VBUS above V_{VBUS_CONVEN}, enable 6 V LDO and CHRG_OK goes HIGH

2. Input voltage and current limit setup

3. Battery CELL configuration

4. 150 ms after VBUS above V_{VBUS_CONVEN}, converter powers up.

8.3.2.1 CHRG_OK Indicator

CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the

following conditions are valid:

•

VBUS is above V_{VBUS_CONVEN}

VBUS is below V_ACOV

No MOSFET/inductor, or over-voltage, over-current, thermal shutdown fault

8.3.2.2 Input Voltage and Current Limit Setup

After CHRG_OK goes HIGH, the charger sets default input current limit in REG0x3F() to 3.30 A. The actual input

current limit is the lower setting of REG0x3F() and ILIM_HIZ pin.

Charger initiates a VBUS voltage measurement without any load (VBUS at no load). The default VINDPM

threshold is VBUS at no load – 1.28 V.

After input current and voltage limits are set, the charger device is ready to power up. The host can always

update input current and voltage limit based on input source type.

8.3.2.3 Battery Cell Configuration

CELL_BATPRESZ pin is biased with resistors from REGN to CELL_BATPRESZ to GND. After VDDA LDO is

activated, the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. Refer to

Electrical Characteristics for CELL setting thresholds.

表 1. Battery Cell Configuration

CELL COUNT

PIN VOLTAGE w.r.t. VDDA

BATTERY VOLTAGE (REG0x15)

SYSOVP

19.5V

12V

4S

3S

2S

1S

75%

55%

40%

25%

16.800V

12.592V

8.400V

4.192V

5V

8.3.2.4 Device Hi-Z State

The charger enters Hi-Z mode when ILIM_HIZ pin voltage is below 0.4 V or REG0x32[15] is set to 1. During Hi-Z

mode, the input source is present, and the charger is in the low quiescent current mode with REGN LDO

enabled.

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8.3.3 USB On-The-Go (OTG)

The device supports USB OTG operation to deliver power from the battery to other portable devices through

USB port. The OTG mode output voltage is set in REG0x3B(). The OTG mode output current is set in

REG0x3C(). The OTG operation can be enabled if the conditions are valid:

•

Valid battery voltage is set REG0x15()

OTG output voltage is set in REG0x3B() and output current is set in REG0x3C()

EN_OTG pin is HIGH and REG0x32[12] = 1

VBUS is below V_{VBUS_UVLO}

10 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK

pin goes HIGH if REG0x12[11] = 1.

8.3.4 Converter Operation

The charger employs a synchronous buck-boost converter that allows charging from a standard 5-V or a high-

voltage power source. The charger operates in buck, buck-boost and boost mode. The buck-boost can operate

uninterruptedly and continuously across the three operation modes.

表 2. MOSFET Operation

MODE

Q1

BUCK

Switching

OFF

BUCK-BOOST

Switching

BOOST

ON

Q2

Switching

OFF

Q3

Switching

Q4

ON

Switching

8.3.4.1 Inductor Setting through IADPT Pin

The charger reads the inductor value through the IADPT pin.

表 3. Inductor Setting on IADPT Pin

INDUCTOR IN USE

1 µH

RESISTOR ON IADPT PIN

93 kΩ

137 kΩ

169 kΩ

2.2 µH

3.3 µH

8.3.4.2 Continuous Conduction Mode (CCM)

With sufficient charge current, the inductor current does not cross 0 A, which is defined as CCM. The controller

starts a new cycle with ramp coming up from 200 mV. As long as error amplifier output voltage is above the ramp

voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error amplifier output

voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and

LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent

cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the

low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on

when the HSFET is off keeps the power dissipation low and allows safe charging at high currents.

8.3.4.3 Pulse Frequency Modulation (PFM)

In order to improve converter light-load efficiency, the bq25700A switches to PFM control at light load. The

effective switching frequency will decrease accordingly when system load decreases. The minimum frequency

can be limit to 25 kHz (ChargeOption0() bit[10]=1).

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8.3.5 Current and Power Monitor

8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)

As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current

during forward charging, or output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT

voltage is 20× or 40× the differential voltage across ACP and ACN. IBAT voltage is 8x/16× (during charging), or

8×/16× (during discharging) of the differential across SRP and SRN. After input voltage or battery voltage is

above UVLO, IADPT output becomes valid. To lower the voltage on current monitoring, a resistor divider from

CSA output to GND can be used and accuracy over temperature can still be achieved.

•

V_(IADPT)= 20 or 40 × (V_(ACP)– V_(ACN)) during forward mode, or 20 or 40 × (V_(ACN)– V_(ACP)) during reverse OTG

mode.

•

V_(IBAT)= 8 or 16 × (V_(SRP)– V_(SRN)) during forward mode.

V_(IBAT)= 8 or 16 × (V_(SRN)– V_(SRP)) during forward supplement mode, or reverse OTG mode.

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An

additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional

response delay. The CSA output voltage is clamped at 3.3 V.

8.3.5.2 High-Accuracy Power Sense Amplifier (PSYS)

The charger monitors total system power. During forward mode, the input adapter powers system. During

reverse OTG mode, the battery powers the system and VBUS output. The ratio of PSYS current and total power

K_PSYScan be programmed in REG0x30[9] with default 1 μA/W. The input and charge sense resistors (RAC and

RSR) are programmed in REG0x30[11:10]. PSYS voltage can be calculated with 公式 1 where IIN>0 when

adapter is in forward charging, and IBAT>0 when the battery is in discharge when the battery is in discharge.

V_PSYS= R_PSYSìK_PSYS(V_ACPìI_IN+ V_BATìI_BAT

)

(1)

For proper PSYS functionality, RAC and RSR values are limited to 10 mΩ and 20 mΩ.

8.3.6 Input Source Dynamic Power Manage

Refer to Input Current and Input Voltage Registers for Dynamic Power Management.

8.3.7 Two-Level Adapter Current Limit (Peak Power Mode)

Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The

charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and

minimize battery discharge during CPU turbo mode. Peak power mode is enabled in

REG0x31[13](EN_PKPWR_IDPM) or REG0x31[12(EN_PKPWR_VSYS)]. The DC current limit, or I_LIM1, is the

same as adapter DC current, set in REG0x3F(). The overloading current, or I_LIM2, is set in REG0x33[15:11], as a

percentage of I_LIM1.

When the charger detects input current surge and battery discharge due to load transient, it applies I_LIM2for

T_OVLDin REG0x31[15:14], first, and then I_LIM1for up to T_MAX– T_OVLDtime. T_MAXis programmed in REG0x31[9:8].

After T_MAX,if the load is still high, another peak power cycle starts. Charging is disabled during T_MAX,; once T_MAX,

expires, charging continues. If T_OVLDis programmed higher than T_MAX, then peak power mode is always on.

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ICRIT

ILIM2

ILIM1

TOVLD

TMAX

IVBUS

ISYS

IBAT

Battery Discharge

PROCHOT

图 12. Two-Level Adapter Current Limit Timing Diagram

8.3.8 Processor Hot Indication

When CPU is running turbo mode, the system peak power may exceed available power from adapter and battery

together. The adapter current and battery discharge peak current, or system voltage drop is indication that

system power is too high. The charger processor hot function monitors these events, and PROCHOT pulse is

asserted. Once CPU receives PROCHOT pulse from charger, it slows down to reduce system power. The

processor hot function monitors these events, and PROCHOT pulse is asserted.

The PROCHOT triggering events include:

•

ICRIT: adapter peak current, as 110% of I_LIM2

INOM: adapter average current (110% of input current limit)

IDCHG: battery discharge current

VSYS: system voltage on VSYS

Adapter Removal: upon adapter removal (CHRG_OK pin HIGH to LOW)

Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW)

CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are

programmable through SMBus. Each triggering event can be individually enabled in REG0x34[6:0]. When any

event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms programmable in

0x33[4:3]. At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended.

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ICRIT

IADPT

Adjustable

Deglitch

1.05V

INOM

IDCHG

50 Ω

PROCHOT

Ref_DCHG

10 ms

Debounce

Ref

<0.3V

10 ms

VSRP

20 µs

Deglitch

CELL_BATPRESZ

(one shot on pin falling edge)

CHRG_OK

(one shot on pin falling edge)

CMPOUT

图 13. PROCHOT Profile

8.3.8.1 PROCHOT During Low Power Mode

During low power mode (REG0x12[15] = 1), the charger offers a low quiescent current (~150 µA). Low power

PROCHOT function uses the independent comparator to monitor battery discharge current and system voltage,

and assert PROCHOT to CPU.

Below lists the register setting to enable PROCHOT during low power mode.

•

REG0x12[15] = 1

REG0x34[5:0] = 000000

REG0x30[6:4] = 100

Independent comparator threshold is always 1.2 V

When REG0x30[14] = 1, charger monitors discharge current. Connect CMPIN to voltage proportional to IBAT

pin. PROCHOT triggers from HIGH to LOW when CMPIN voltage falls below 1.2 V.

•

When REG0x30[13] = 1, charger monitors system voltage. Connect CMPIN to voltage proportional to system.

PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above 1.2 V.

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PROCHOT

1.2 V

Independent

Comparator

Voltage î

V_SYS

CMPIN

Voltage î ⁽V_SRNœ V_SRP

)

bq2570xA

图 14. PROCHOT Low Power Mode Implementation

8.3.8.2 PROCHOT Status

REG0x21[6:0] reports which event in the profile triggers PROCHOT by setting the corresponding bit to 1. The

status bit can be reset back to 0 after it is read by host, and current PROCHOT event is no longer active.

Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B is

also active. Both status bits will be HIGH. At the end of the 10 ms PROCHOT pulse, if PROCHOT is still active

(either by A or B), the PROCHOT pulse is extended.

8.3.9 Device Protection

8.3.9.1 Watchdog Timer

The charger includes watchdog timer to terminate charging if the charger does not receive a write

MaxChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable via REG0x12[14:13]). When

watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent() resets to zero. Battery

charging is suspended. Write MaxChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset

watchdog timer and resume charging. Writing REG0x12[14:13] = 00 to disable watchdog timer also resumes

charging.

8.3.9.2 Input Overvoltage Protection (ACOV)

The charger has fixed ACOV voltage. When VBUS pin voltage is higher than ACOV, it is considered as adapter

over voltage. CHRG_OK will be pulled low, and converter will be disabled. As system falls below battery voltage,

BATFET will be turned on. When VBUS pin voltage falls below ACOV, it is considered as adapter voltage returns

back to normal voltage. CHRG_OK is pulled high by external pull up resistor. The converter resumes if enable

conditions are valid.

8.3.9.3 Input Overcurrent Protection (ACOC)

If the input current exceeds the 1.25× or 2× (REG0x31[2]) of I_{LIM2_VTH}(REG0x33[15:11]) set point, converter

stops switching. After 300 ms, converter starts switching again.

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8.3.9.4 System Overvoltage Protection (SYSOVP)

When the converter starts up, the bq25700A reads CELL pin configuration and sets MaxChargeVoltage() and

SYSOVP threshold (1s – 5 V, 2s – 12 V, 3s/4s – 19.5 V). Before REGx15() is written by the host, the battery

configuration will change with CELL pin voltage. When SYSOVP happens, the device latches off the converter.

REG20[4] is set as 1. The user can clear latch-off by either writing 0 to the SYSOVP bit or removing and

plugging in the adapter again. After latch-off is cleared, the converter starts again.

8.3.9.5 Battery Overvoltage Protection (BATOVP)

Battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery.

The BATOVP threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in REG0x15().

8.3.9.6 Battery Short

If BAT voltage falls below SYSMIN during charging, the maximum current is limited to 384 mA.

8.3.9.7 Thermal Shutdown (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the

ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for self-

protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction

temperature falls below 135°C. During thermal shut down, the LDO current limit is reduced to 16 mA and REGN

LDO stays off. When the temperature falls below 135°C, charge can be resumed with soft start.

8.4 Device Functional Modes

8.4.1 Forward Mode

When input source is connected to VBUS, bq25700A is in forward mode to regulate system and charge battery.

8.4.1.1 System Voltage Regulation with Narrow VDC Architecture

The bq25700A employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is

regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode).

As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in

supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System

voltage is regulated 160 mV above battery voltage when BATFET is off (no charging or no supplement current).

See System Voltage Regulation for details on system voltage regulation and register programming.

8.4.1.2 Battery Charging

The bq25700A charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. Based on

CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2V/cell to ChargeVoltage(), or

REG0x15(). According to battery capacity, the host programs appropriate charge current to ChargeCurrent(), or

REG0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting

REG0x12[0] to 1, or setting ChargeCurrent() to zero.

See Feature Description for details on register programming.

8.4.2 USB On-The-Go

The bq25700A supports USB OTG functionality to deliver power from the battery to other portable devices

through USB port (reverse mode). The OTG output voltage is compliant with USB PD specification, including 5 V,

9 V, 15 V, and 20 V (REG0x3B()). The output current regulation is compliant with USB type C specification,

including 500 mA, 1.5 A, 3 A and 5 A (REG0x3C()).

Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve

efficiency.

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8.5 Programming

The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as

summarized in 表 6. The SMBUS address is 12h (0001001_X), where X is the read/write bit. The ManufacturerID

and DeviceID registers are assigned identify the charger device. The ManufacturerID register command always

returns 40h.

8.5.1 SMBus Interface

The bq25700A device operates as a slave, receiving control inputs from the embedded controller host through

the SMBus interface. The bq25700A device uses a simplified subset of the commands documented in System

Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq25700A device

uses the SMBus read-word and write-word protocols (shown in 表 4 and 表 5) to communicate with the smart

battery. The device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not

initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID

register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication starts when VCC is above V_(UVLO)

.

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose

pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.

Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while

SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-to-

high transition on SDA, while SCL is high. The bus is then free for another transmission. 图 15 and 图 16 show

the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are

transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the

start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock

cycles are required to transfer each byte in or out of the device because either the master or the slave

acknowledges the receipt of the correct byte during the ninth clock cycle. The bq25700A supports the charger

commands listed in 表 4.

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Programming (接下页)

8.5.1.1 SMBus Write-Word and Read-Word Protocols

表 4. Write-Word Format

S

SLAVE

W

ACK

COMMAND

BYTE⁽¹⁾

ACK

LOW DATA

BYTE⁽¹⁾

ACK

HIGH DATA

BYTE⁽¹⁾

ACK

P

(1)(2)

(1)(3)

(4)(5)

(1)(6)

ADDRESS⁽¹⁾

7 bits

1b

0

1b

0

8 bits

1b

0

8 bits

1b

0

8 bits

1b

0

MSB LSB

(1) Master to slave

(2) S = Start condition or repeated start condition

(3) W = Write bit (logic-low)

(4) Slave to master (shaded gray)

(5) ACK = Acknowledge (logic-low)

(6) P = Stop condition

表 5. Read-Word Format

S⁽¹⁾

SLAVE

W

ACK COMMAND ACK S⁽¹⁾

SLAVE

R⁽¹⁾ACK LOW DATA ACK HIGH DATA NACK

P

(2)

(1)(3)

(4)(5)

(2)

(6)

(4)(5)

(1)(5)

(1)(7)

(1)(8)

ADDRESS⁽¹⁾

BYTE⁽¹⁾

8 bits

ADDRESS⁽¹⁾

BYTE⁽⁴⁾

8 bits

BYTE⁽⁴⁾

8 bits

7 bits

1b

0

1b

0

1b

0

7 bits

1b

1

1b

0

1b

0

1b

1

MSB LSB

(1) Master to slave

(2) S = Start condition or repeated start condition

(3) W = Write bit (logic-low)

(4) Slave to master (shaded gray)

(5) ACK = Acknowledge (logic-low)

(6) R = Read bit (logic-high)

(7) NACK = Not acknowledge (logic-high)

(8) P = Stop condition

8.5.1.2 Timing Diagrams

A

B

C

D

E

F

G

H

I

J

K

L

M

t_LOWt_HIGH

SMBCLK

SMBDATA

t_SU:STAt_HD:STA

A = Start condition

t_SU:DATt_HD:DAT

t_HD:DAT

t_SU:STOt_BUF

H = LSB of data clocked into slave

I = Slave pulls SMBDATA line low

B = MSB of address clocked into slave

C = LSB of address clocked into slave

D = R/W bit clocked into slave

J = Acknowledge clocked into master

K = Acknowledge clock pulse

E = Slave pulls SMBDATA line low

F = ACKNOWLEDGE bit clocked into master

G = MSB of data clocked into slave

L = Stop condition, data executed by slave

M = New start condition

图 15. SMBus Write Timing

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A

B

C

D

E

F

G

H

I

J

K

t_LOWt_HIGH

SMBCLK

SMBDATA

t_SU:STAt_HD:STA

t_SU:DAT

t_HD:DAT

t_SU:DAT

t_SU:STOt_BUF

A = START CONDITION

E = SLAVE PULLS SMBDATA LINE LOW

I = ACKNOWLEDGE CLOCK PULSE

A = Start condition

G = MSB of data clocked into master

B = MSB of address clocked into slave

C = LSB of address clocked into slave

D = R/W bit clocked into slave

H = LSB of data clocked into master

I = Acknowledge clock pulse

J = Stop condition

E = Slave pulls SMBDATA line low

F = ACKNOWLEDGE bit clocked into master

K = New start condition

图 16. SMBus Read Timing

8.6 Register Map

表 6. Charger Command Summary

SMBus

ADDR

REGISTER NAME

TYPE

DESCRIPTION

LINKS

12h

14h

ChargeOption0()

ChargeCurrent()

R/W

Charge Option 0

Go

R/W

7-bit charge current setting

LSB 64 mA, Range 8128 mA

15h

MaxChargeVoltage()

11-bit charge voltage setting

Go

LSB 16 mV, Default: 1S-4192mV, 2S-8400mV,

3S-12592mV, 4S-16800mV

30h

31h

32h

33h

34h

35h

20h

21h

22h

ChargeOption1()

ChargeOption2()

ChargeOption3()

ProchotOption0()

ProchotOption1()

ADCOption()

R/W

R

Charge Option 1

Charge Option 2

Charge Option 3

PROCHOT Option 0

PROCHOT Option 1

ADC Option

Go

ChargerStatus()

ProchotStatus()

IIN_DPM()

Charger Status

Prochot Status

R

7-bit input current limit in use

LSB: 50 mA, Range: 50 mA - 6400 mA

23h

ADCVBUS/PSYS()

R

8-bit digital output of input voltage,

8-bit digital output of system power

PSYS: Full range: 3.06 V, LSB: 12 mV

VBUS: Full range: 3.2 V - 19.52 V, LSB 64 mV

Go

24h

ADCIBAT()

8-bit digital output of battery charge current,

8-bit digital output of battery discharge current

ICHG: Full range 8.128 A, LSB 64 mA

Go

IDCHG: Full range: 32.512 A, LSB: 256 mA

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Register Map (接下页)

表 6. Charger Command Summary (接下页)

SMBus

ADDR

REGISTER NAME

TYPE

DESCRIPTION

LINKS

25h

ADCIINCMPIN()

R

8-bit digital output of input current,

Go

8-bit digital output of CMPIN voltage

POR State - IIN: Full range: 12.75 A, LSB 50 mA

CMPIN: Full range 3.06 V, LSB: 12 mV

26h

ADCVSYSVBAT()

8-bit digital output of system voltage,

8-bit digital output of battery voltage

VSYS: Full range: 2.88 V - 19.2 V, LSB: 64 mV

VBAT: Full range : 2.88 V - 19.2 V, LSB 64 mV

3Bh

3Ch

3Dh

3Eh

OTGVoltage()

R/W

8-bit OTG voltage setting

LSB 64 mV, Range: 4480 – 20800 mV

Go

OTGCurrent()

7-bit OTG output current setting

LSB 50 mA, Range: 0 A – 6350 mA

InputVoltage()

8-bit input voltage setting

LSB 64 mV, Range: 3200 mV – 19520 mV

MinSystemVoltage()

6-Bit minimum system voltage setting

LSB: 256 mV, Range: 1024 mV - 16182 mV

Default: 1S-3.584V, 2S-6.144V, 3S-9.216V, 4S-

12.288V

3Fh

IIN_HOST()

R/W

6-bit Input current limit set by host

Go

LSB: 50 mA, Range: 50 mA - 6400 mA

FEh

FFh

ManufacturerID()

DeviceID()

R

Manufacturer ID - 0x0040H

Device ID

Go

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8.6.1 Setting Charge and PROCHOT Options

8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]

图 17. ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh]

15

14

13

12

11

10

9

8

EN_LWPWR

WDTMR_ADJ

R/W

IDPM_AUTO_

DISABLE

OTG_ON_

CHRGOK

EN_OOA

PWM_FREQ

Reserved

R/W

7

R/W

6

5

4

3

2

1

0

Reserved

R/W

EN_LEARN

R/W

IADPT_GAIN

R/W

IBAT_GAIN

R/W

EN_LDO

R/W

EN_IDPM

R/W

CHRG_INHIBIT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

EN_LWPWR

R/W

1b

Low Power Mode Enable

0b: Disable Low Power Mode. Device in performance mode with battery only.

The PROCHOT, current/power monitor buffer and comparator follow register

setting.

1b: Enable Low Power Mode. Device in low power mode with battery only for

lowest quiescent current. PROCHOT, discharge current monitor buffer, power

monitor buffer and independent comparator are disabled. ADC is not available

in Low Power Mode. Independent comparator can be enabled by setting either

REG0X30()[14] or [13] to 1. <default at POR>

14-13

WDTMR_ADJ

R/W

11b

WATCHDOG Timer Adjust

Set maximum delay between consecutive SMBus write of charge voltage or

charge current command.

If device does not receive a write on the REG0x15() or the REG0x14() within

the watchdog time period, the charger will be suspended by setting the

REG0x14() to 0 mA.

After expiration, the timer will resume upon the write of REG0x14(),

REG0x15() or REG0x12[14:13]. The charger will resume if the values are

valid.

00b: Disable Watchdog Timer

01b: Enabled, 5 sec

10b: Enabled, 88 sec

11b: Enable Watchdog Timer, 175 sec <default at POR>

12

IDPM_AUTO_

DISABLE

R/W

0b

IDPM Auto Disable

When CELL_BATPRESZ pin is LOW, the charger automatically disables the

IDPM function by setting EN_IDPM (REG0x12[1]) to 0. The host can enable

IDPM function later by writing EN_IDPM bit (REG0x12[1]) to 1.

0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes

LOW. <default at POR>

1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes

LOW.

11

10

OTG_ON_

CHRGOK

R/W

0b

Add OTG to CHRG_OK

Drive CHRG_OK to HIGH when the device is in OTG mode.

0b: Disable <default at POR>

1b: Enable

EN_OOA

Out-of-Audio Enable

0b: No limit of PFM burst frequency <default at POR>

1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise

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表 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions (接下页)

FIELD

PWM_FREQ

TYPE

RESET

DESCRIPTION

BIT

9

R/W

1b

Switching Frequency

Two converter switching frequencies. One for small inductor and the other for

big inductor.

Recommend 800 kHz with 2.2 µH or 3.3 µH, and 1.2 MHz with 1 µH or 1.5 µH.

0b: 1200 kHz

1b: 800 kHz <default at POR>

Reserved

8

Reserved

R/W

0b

表 8. ChargeOption0 Register (SMBus address = 12h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

5

Reserved

R/W

00b

0b

Reserved

EN_LEARN

LEARN function allows the battery to discharge while the adapter is present. It

calibrates the battery gas gauge over a complete discharge/charge cycle.

When the battery voltage is below battery depletion threshold, the system

switches back to adapter input by the host. When CELL_BATPRESZ pin is

LOW, the device exits LEARN mode and this bit is set back to 0.

0b: Disable LEARN Mode <default at POR>

1b: Enable LEARN Mode

4

3

2

IADPT_GAIN

IBAT_GAIN

EN_LDO

R/W

0b

1b

IADPT Amplifier Ratio

The ratio of voltage on IADPT and voltage across ACP and ACN.

0b: 20× <default at POR>

1b: 40×

IBAT Amplifier Ratio

The ratio of voltage on IBAT and voltage across SRP and SRN

0b: 8×

1b: 16× <default at POR>

LDO Mode Enable

When battery voltage is below minimum system voltage (REG0x3E()), the

charger is in pre-charge with LDO mode enabled.

0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery

pack internal resistor. The system is regulated by the MaxChargeVoltage

register.

1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register

and clamped below 384 mA (2 cell – 4 cell) or 2A (1 cell). The system is

regulated by the MinSystemVoltage register. <default at POR>

1

0

EN_IDPM

R/W

1b

0b

IDPM Enable

Host writes this bit to enable IDPM regulation loop. When the IDPM is disabled

by the charger (refer to IDPM_AUTO_DISABLE), this bit goes LOW.

0b: IDPM disabled

1b: IDPM enabled <default at POR>

CHRG_INHIBIT

Charge Inhibit

When this bit is 0, battery charging will start with valid values in the

MaxChargeVoltage register and the ChargeCurrent register.

0b: Enable Charge <default at POR>

1b: Inhibit Charge

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8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h]

图 18. ChargeOption1 Register (SMBus address = 30h) [reset = 211h]

15

14

13

12

EN_PSYS

R/W

11

RSNS_RAC

R/W

10

RSNS_RSR

R/W

9

8

EN_IBAT

R/W

EN_PROCHOT_LPWR

R/W

PSYS_RATIO

R/W

Reserved

R/W

7

6

5

4

3

2

1

0

CMP_REF

CMP_POL

CMP_DEG

R/W

FORCE_

LATCHOFF

Reserved

EN_SHIP_

DCHG

AUTO_

WAKEUP_EN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 9. ChargeOption1 Register (SMBus address = 30h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET DESCRIPTION

15

EN_IBAT

R/W

0b

IBAT Enable

Enable the IBAT output buffer. In low power mode (REG0x12[15] = 1), IBAT

buffer is always disabled regardless of this bit value.

0b Turn off IBAT buffer to minimize Iq <default at POR>

1b: Turn on IBAT buffer

14-13 EN_PROCHOT

_LPWR

R/W

00b

Enable PROCHOT during battery only low power mode

With battery only, enable IDCHG or VSYS in PROCHOT with low power

consumption. Do not enable this function with adapter present. Refer to

PROCHOT During Low Power Mode for more details.

00b: Disable low power PROCHOT <default at POR>

01b: Enable IDCHG low power PROCHOT

10b: Enable VSYS low power PROCHOT

11b: Reserved

12

EN_PSYS

R/W

0b

PSYS Enable

Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low

power mode (REG0x12[15] = 1), PSYS sensing and buffer are always disabled

regardless of this bit value.

0b: Turn off PSYS buffer to minimize Iq <default at POR>

1b: Turn on PSYS buffer

11

10

9

RSNS_RAC

RSNS_RSR

PSYS_RATIO

R/W

0b

1b

Input sense resistor RAC

0b: 10 mΩ <default at POR>

1b: 20 mΩ

Charge sense resistor RSR

0b: 10 mΩ <default at POR>

1b: 20 mΩ

PSYS Gain

Ratio of PSYS output current vs total input and battery power with 10-mΩ sense

resistor.

0b: 0.25 µA/W

1b: 1 µA/W <default at POR>

8

Reserved

R/W

0b

Reserved

表 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET DESCRIPTION

7

CMP_REF

R/W

0b

Independent Comparator internal Reference

0b: 2.3 V <default at POR>

1b: 1.2 V

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ZHCSGD7A –MAY 2017–REVISED MAY 2018

表 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions (接下页)

FIELD

TYPE

RESET DESCRIPTION

BIT

6

CMP_POL

R/W

0b

Independent Comparator output Polarity

0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal

hysteresis) <default at POR>

1b: When CMPIN is below internal threshold, CMPOUT is LOW (external

hysteresis)

5-4

CMP_DEG

R/W

01b

Independent comparator deglitch time, only applied to the falling edge of

CMPOUT (HIGH → LOW).

00b: Independent comparator is disabled

01b: Independent comparator is enabled with output deglitch time 1 µs <default

at POR>

10b: Independent comparator is enabled with output deglitch time of 2 ms

11b: Independent comparator is enabled with output deglitch time of 5 sec

3

FORCE_LATCHOFF

R/W

0b

Force Power Path Off

When independent comparator triggers, charger turns off Q1 and Q4 (same as

disable converter) so that the system is disconnected from the input source. At

the same time, CHRG_OK signal goes to LOW to notify the system.

0b: Disable this function <default at POR>

1b: Enable this function

2

1

Reserved

R/W

0b

Reserved

EN_SHIP_DCHG

Discharge SRN for Shipping Mode

When this bit is 1, discharge SRN pin down below 3.8 V in 140 ms. When 140

ms is over, this bit is reset to 0.

0b: Disable shipping mode <default at POR>

1b: Enable shipping mode

0

AUTO_WAKEUP_EN

R/W

1b

Auto Wakeup Enable

When this bit is HIGH, if the battery is below minimum system voltage

(REG0x3E()), the device will automatically enable 128 mA charging current for

30 mins. When the battery is charged up above minimum system voltage, charge

will terminate and the bit is reset to LOW.

0b: Disable

1b: Enable <default at POR>

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8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]

图 19. ChargeOption2 Register (SMBus address = 31h) [reset = 2B7]

15

14

13

12

11

10

9

8

PKPWR_TOVLD_DEG

EN_PKPWR_

IDPM

EN_PKPWR_

VSYS

PKPWR_

OVLD_STAT

PKPWR_

RELAX_STAT

PKPWR_TMAX[1:0]

R/W

7

6

5

4

3

2

1

0

EN_EXTILIM

EN_ICHG

_IDCHG

Q2_OCP

ACX_OCP

EN_ACOC

ACOC_VTH

EN_BATOC

BATOC_VTH

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 11. ChargeOption2 Register (SMBus address = 31h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

PKPWR_

TOVLD_DEG

R/W

00b

Input Overload time in Peak Power Mode

00b: 1 ms <default at POR>

01b: 2 ms

10b: 10 ms

11b: 20 ms

13

EN_PKPWR_IDPM

EN_PKPWR_VSYS

R/W

0b

Enable Peak Power Mode triggered by input current overshoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon

adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by input current overshoot

1b: Enable peak power mode triggered by input current overshoot.

12

Enable Peak Power Mode triggered by system voltage under-shoot

If REG0x31[13:12] are 00b, peak power mode is disabled. Upon

adapter removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by system voltage under-shoot

1b: Enable peak power mode triggered by system voltage under-shoot.

11

10

PKPWR_

OVLD_STAT

R/W

0b

Indicator that the device is in overloading cycle. Write 0 to get out of

overloading cycle.

0b: Not in peak power mode. <default at POR>

1b: In peak power mode.

PKPWR_

RELAX_STAT

0b

Indicator that the device is in relaxation cycle. Write 0 to get out of

relaxation cycle.

0b: Not in relaxation cycle. <default at POR>

1b: In relaxation mode.

9-8

PKPWR_

TMAX[1:0]

10b

Peak power mode overload and relax cycle time.

When REG0x31[15:14] is programmed longer than REG0x31[9:8],

there is no relax time.

00b: 5 ms

01b: 10 ms

10b: 20 ms <default at POR>

11b: 40 ms

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ZHCSGD7A –MAY 2017–REVISED MAY 2018

表 12. ChargeOption2 Register (SMBus address = 31h) Field Descriptions

FIELD

TYPE

RESET

DESCRIPTION

BIT

7

EN_EXTILIM

R/W

1b

Enable ILIM_HIZ pin to set input current limit

0b: Input current limit is set by REG0x3F.

1b: Input current limit is set by the lower value of ILIM_HIZ pin and

REG0x3F. <default at POR>

6

5

EN_ICHG

_IDCHG

R/W

0b

1b

0b: IBAT pin as discharge current. <default at POR>

1b: IBAT pin as charge current.

Q2_OCP

Q2 OCP threshold by sensing Q2 VDS

0b: 210 mV

1b: 150 mV <default at POR>

4

3

ACX_OCP

EN_ACOC

R/W

1b

0b

Input current OCP threshold by sensing ACP-ACN.

0b: 280 mV

1b: 150 mV <default at POR>

ACOC Enable

Input overcurrent (ACOC) protection by sensing the voltage across

ACP and ACN. Upon ACOC (after 100-µs blank-out time), converter is

disabled.

0b: Disable ACOC <default at POR>

1b: ACOC threshold 125% or 200% ICRIT

2

1

ACOC_VTH

EN_BATOC

R/W

1b

ACOC Limit

Set MOSFET OCP threshold as percentage of IDPM with current

sensed from R_AC.

0b: 125% of ICRIT

1b: 200% of ICRIT <default at POR>

BATOC Enable

Battery discharge overcurrent (BATOC) protection by sensing the

voltage across SRN and SRP. Upon BATOC, converter is disabled.

0b: Disable BATOC

1b: BATOC threshold 125% or 200% PROCHOT IDCHG <default at

POR>

0

BATOC_VTH

R/W

1b

Set battery discharge overcurrent threshold as percentage of

PROCHOT battery discharge current limit.

0b: 125% of PROCHOT IDCHG

1b: 200% of PROCHOT IDCHG <default at POR>

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8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h]

图 20. ChargeOption3 Register (SMBus address = 32h) [reset = 0h]

15

14

13

12

11

10

9

8

0

EN_HIZ

RESET_REG

RESET_

VINDPM

EN_OTG

EN_ICO_MOD

E

Reserved

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

1

2

Reserved

BATFETOFF_

HIZ

PSYS_OTG_

IDCHG

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W

表 13. ChargeOption3 Register (SMBus address = 32h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

EN_HIZ

R/W

0b

Device Hi-Z Mode Enable

When the charger is in Hi-Z mode, the device draws minimal quiescent

current. With VBUS above UVLO. REGN LDO stays on, and system

powers from battery.

0b: Device not in Hi-Z mode <default at POR>

1b: Device in Hi-Z mode

14

RESET_REG

R/W

0b

Reset Registers

All the registers go back to the default setting except the VINDPM

register.

0b: Idle <default at POR>

1b: Reset all the registers to default values. After reset, this bit goes back

to 0.

13

12

RESET_VINDPM

EN_OTG

R/W

0b

Reset VINDPM Threshold

0b: Idle

1b: Converter is disabled to measure VINDPM threshold. After VINDPM

measurement is done, this bit goes back to 0 and converter starts.

OTG Mode Enable

Enable device in OTG mode when EN_OTG pin is HIGH.

0b: Disable OTG <default at POR>

1b: Enable OTG mode to supply VBUS from battery.

11

EN_ICO_MODE

Reserved

R/W

0b

Enable ICO Algorithm

0b: Disable ICO algorithm. <default at POR>

1b: Enable ICO algorithm.

10-8

000b

Reserved

表 14. ChargeOption3 Register (SMBus address = 32h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-2

1

Reserved

R/W

000000b

0b

Reserved

BATFETOFF_

HIZ

Control BATFET during HIZ mode.

0b: BATFET on during Hi-Z <default at POR>

1b: BATFET off during Hi-Z

0

PSYS_OTG_

IDCHG

R/W

0b

PSYS function during OTG mode.

0b: PSYS as battery discharge power minus OTG output power <default

at POR>

1b: PSYS as battery discharge power only

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8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]

图 21. ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h]

15-11

ILIM2_VTH

R/W

10-9

ICRIT_DEG

R/W

8

Reserved

R/W

7-6

5

4-3

2

1

0

VSYS_VTH

EN_PROCHOT

_EXT

PROCHOT_WIDTH

PROCHOT_

CLEAR

INOM_DEG

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 15. ProchotOption0 Register (SMBus address = 33h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11 ILIM2_VTH

R/W

01001b

I_LIM2Threshold

5 bits, percentage of IDPM in 0x3FH. Measure current between ACP and ACN.

Trigger when the current is above this threshold:

00001b - 11001b: 110% - 230%, step 5%

11010b - 11110b: 250% - 450%, step 50%

11111b: Out of Range (Ignored)

Default 150%, or 01001

10-9

ICRIT_DEG

R/W

01b

ICRIT Deglitch time

ICRIT threshold is set to be 110% of

.

ILIM2

Typical ICRIT deglitch time to trigger PROCHOT.

00b: 15 µs

01b: 100 µs <default at POR>

10b: 400 µs (max 500 us)

11b: 800 µs (max 1 ms)

8

Reserved

R/W

0b

Reserved

表 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

VSYS_VTH

R/W

01b

VSYS Threshold

Measure on VSYS with fixed 20-µs deglitch time. Trigger when SYS pin voltage is

below the threshold.

00b: 5.75 V (2-4 s) or 2.85 V (1 s)

01b: 6 V (2-4 s) or 3.1 V (1 s) <default at POR>

10b: 6.25 V (2-4 s) or 3.35 V (1 s)

11b: 6.5 V (2-4 s) or 3.6 V (1 s)

5

EN_PROCHOT

_EXT

R/W

0b

PROCHOT Pulse Extension Enable

When pulse extension is enabled, keep the PROCHOT pin voltage LOW until host

writes 0x33[2] = 0.

0b: Disable pulse extension <default at POR>

1b: Enable pulse extension

4-3

PROCHOT

_WIDTH

10b

PROCHOT Pulse Width

Minimum PROCHOT pulse width when REG0x33[5] = 0

00b: 100 µs

01b: 1 ms

10b: 10 ms <default at POR>

11b: 5 ms

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表 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions (接下页)

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

2

PROCHOT

_CLEAR

R/W

1b

PROCHOT Pulse Clear

Clear PROCHOT pulse when 0x33[5] = 1.

0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH.

1b: Idle <default at POR>

1

INOM_DEG

R/W

0b

INOM Deglitch Time

INOM is always 10% above IDPM in 0x3FH. Measure current between ACP and

ACN.

Trigger when the current is above this threshold.

0b: 1 ms (must be max) <default at POR>

1b: 50 ms (max 60 ms)

0

Reserved

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8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]

图 22. ProchotOption1 Register (SMBus address = 34h) [reset = 8120h]

15-10

9-8

IDCHG_VTH

R/W

IDCHG_DEG

R/W

7

6

5

4

3

2

1

0

Reserved

PROCHOT_PR

OFILE_IC

PP_ICRIT

PP_INOM

PP_IDCHG

PP_VSYS

PP_BATPRES

PP_ACOK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 17. ProchotOption1 Register (SMBus address = 34h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-10

IDCHG_VTH

R/W

100000b

IDCHG Threshold

6 bit, range, range 0 A to 32256 mA, step 512 mA. There is a 128 mA offset

Measure current between SRN and SRP.

Trigger when the discharge current is above the threshold.

If the value is programmed to 000000b PROCHOT is always triggered.

Default: 16384 mA or 100000b

9-8

IDCHG_DEG

R/W

01b

IDCHG Deglitch Time

00b: 1.6 ms

01b: 100 µs <default at POR>

10b: 6 ms

11b: 12 ms

表 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

6

Reserved

R/W

0b

Reserved

PROCHOT

_PROFILE_COMP

PROCHOT Profile

When all the REG0x34[6:0] bits are 0, PROCHOT function is disabled.

Bit6 Independent comparator

0b: disable <default at POR>

1b: enable

5

4

3

2

1

PROCHOT

_PROFILE_ICRIT

R/W

1b

0b

0b: disable

1b: enable <default at POR>

PROCHOT

_PROFILE_INOM

0b: disable <default at POR>

1b: enable

PROCHOT

_PROFILE_IDCHG

0b: disable <default at POR>

1b: enable

PROCHOT

_PROFILE_VSYS

0b: disable <default at POR>

1b: enable

PROCHOT

_PROFILE_BATPRES

0b: disable <default at POR>

1b: enable (one-shot falling edge triggered)

If BATPRES is enabled in PROCHOT after the battery is removed, it will

immediately send out one-shot PROCHOT pulse.

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表 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions (接下页)

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

0

PROCHOT

_PROFILE_ACOK

R/W

0b

0b: disable <default at POR>

1b: enable

ChargeOption0[15] = 0 to assert PROCHOT pulse after adapter removal.

If PROCHOT_PROFILE_ACOK is enabled in PROCHOT after the adapter is

removed, it will be pulled low.

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8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]

图 23. ADCOption Register (SMBus address = 35h) [reset = 2000h]

15

14

13

12-8

ADC_CONV

ADC_START

ADC_

Reserved

FULLSCALE

R/W

7

R/W

6

R/W

5

R/W

2

4

3

1

0

EN_ADC_

CMPIN

EN_ADC_

VBUS

EN_ADC_

PSYS

EN_ADC_

IIN

EN_ADC_

IDCHG

EN_ADC_

ICHG

EN_ADC_

VSYS

EN_ADC_

VBAT

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC

is disabled in low power mode. When enabling ADC, the device exit low power mode at battery only.

表 19. ADCOption Register (SMBus address = 35h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

ADC_CONV

R/W

0b

Typical ADC conversion time is 10 ms.

0b: One-shot update. Do one set of conversion updates to registers

REG0x23(), REG0x24(), REG0x25(), and REG0x26() after ADC_START =

1.

1b: Continuous update. Do a set of conversion updates to registers

REG0x23(), REG0x24(), REG0x25(), and REG0x26() every 1 sec.

14

13

ADC_START

R/W

0b

1b

0b: No ADC conversion

1b: Start ADC conversion. After the one-shot update is complete, this bit

automatically resets to zero

ADC_

FULLSCALE

ADC input voltage range. When input voltage is below 5 V, or battery is 1S,

full scale 2.04 V is recommended.

0b: 2.04 V

1b: 3.06 V <default at POR>

Reserved

12-8

Reserved

R/W

00000b

表 20. ADCOption Register (SMBus address = 35h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

6

5

4

3

2

1

0

EN_ADC_CMPIN

R/W

0b

0b: Disable <default at POR>

1b: Enable

EN_ADC_VBUS

EN_ADC_PSYS

EN_ADC_IIN

R/W

0b

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

EN_ADC_IDCHG

EN_ADC_ICHG

EN_ADC_VSYS

EN_ADC_VBAT

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

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8.6.2 Charge and PROCHOT Status

8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]

图 24. ChargerStatus Register (SMBus address = 20h) [reset = 0000h]

15

AC_STAT

R

14

ICO_DONE

R

13

Reserved

R

12

IN_VINDPM

R

11

IN_IINDPM

R

10

IN_FCHRG

R

9

IN_PCHRG

R

8

IN_OTG

R

7

6

5

4

3

2

1

0

Fault ACOV

Fault BATOC

Fault ACOC

SYSOVP_

STAT

Reserved

Fault Latchoff

Fault_OTG_

OVP

Fault_OTG_

OCP

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 21. ChargerStatus Register (SMBus address = 20h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

AC_STAT

R

0b

Input source status, same as CHRG_OK pin

0b: Input not present

1b: Input is present

14

ICO_DONE

R

0b

After the ICO routine is successfully executed, the bit goes 1.

0b: ICO is not complete

1b: ICO is complete

13

12

Reserved

R

0b

Reserved

IN_VINDPM

0b: Charger is not in VINDPM during forward mode, or voltage

regulation during OTG mode

1b: Charger is in VINDPM during forward mode, or voltage

regulation during OTG mode

11

10

9

IN_IINDPM

IN_FCHRG

IN_PCHRG

IN_OTG

R

0b

0b: Charger is not in IINDPM

1b: Charger is in IINDPM

0b: Charger is not in fast charge

1b: Charger is in fast charger

0b: Charger is not in pre-charge

1b: Charger is in pre-charge

8

0b: Charger is not in OTG

1b: Charge is in OTG

表 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

6

5

Fault ACOV

R

0b

The faults are latched until a read from host.

0b: No fault

1b: ACOV

Fault BATOC

Fault ACOC

R

0b

The faults are latched until a read from host.

0b: No fault

1b: BATOC

The faults are latched until a read from host.

0b: No fault

1b: ACOC

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SMBus

ZHCSGD7A –MAY 2017–REVISED MAY 2018

表 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions (接下页)

FIELD

TYPE

RESET

DESCRIPTION

BIT

4

SYSOVP_STAT

R

0b

SYSOVP Status and Clear

When the SYSOVP occurs, this bit is HIGH. During the SYSOVP,

the converter is disabled.

After the SYSOVP is removed, the user must write a 0 to this bit or

unplug the adapter to clear the SYSOVP condition to enable the

converter again.

0b: Not in SYSOVP <default at POR>

1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the

SYSOVP latch.

3

2

Reserved

R

0b

Reserved

Fault Latchoff

The faults are latched until a read from host.

0b: No fault

1b: Latch off (REG0x30[3])

1

0

Fault_OTG_OVP

Fault_OTG_UCP

R

0b

The faults are latched until a read from host.

0b: No fault

1b: OTG OVP

The faults are latched until a read from host.

0b: No fault

1b: OTG OCP

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8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h]

图 25. ProchotStatus Register (SMBus address = 21h) [reset = 0h]

15-8

Reserved

R

7

6

5

4

3

2

1

0

Reserved

STAT_COMP

STAT_ICRIT

STAT_INOM

STAT_IDCHG

STAT_VSYS

STAT_Battery_ STAT_Adapter

Removal

_Removal

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 23. ProchotStatus Register (SMBus address = 21h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

Reserved

R

0000000

0b

Reserved

表 24. ProchotStatus Register (SMBus address = 21h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

6

Reserved

R

0b

Reserved

STAT_COMP

0b: Not triggered

1b: Triggered

5

4

3

2

1

0

STAT_ICRIT

R

0b

0b: Not triggered

1b: Triggered

STAT_INOM

0b: Not triggered

1b: Triggered

STAT_IDCHG

0b: Not triggered

1b: Triggered

STAT_VSYS

0b: Not triggered

1b: Triggered

STAT_Battery_Removal

STAT_Adapter_Removal

0b: Not triggered

1b: Triggered

0b: Not triggered

1b: Triggered

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8.6.3 ChargeCurrent Register (SMBus address = 14h) [reset = 0h]

To set the charge current, write a 16-bit ChargeCurrent() command (REG0x14h()) using the data format listed in

表 25 and 表 26.

With 10-mΩ sense resistor, the charger provides charge current range of 64 mA to 8.128 A, with a 64-mA step

resolution. Upon POR, ChargeCurrent() is 0 A. Any conditions for CHRG_OK low except ACOV will reset

ChargeCurrent() to zero. CELL_BATPRESZ going LOW (battery removal) will reset the ChargeCurrent() register

to 0 A.

Charge current is not reset in ACOC, TSHUT, power path latch off (REG0x30[1]), and SYSOVP.

A 0.1-µF capacitor between SRP and SRN for differential mode filtering is recommended; an optional 0.1-µF

capacitor between SRN and ground, and an optional 0.1-µF capacitor between SRP and ground for common

mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1 µF in order to properly sense

the voltage across SRP and SRN for cycle-by-cycle current detection.

The SRP and SRN pins are used to sense voltage drop across RSR with default value of 10 mΩ. However,

resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a

higher regulation accuracy; but, at the expense of higher conduction loss. A current sensing resistor value no

more than 20 mΩ is suggested.

图 26. ChargeCurrent Register With 10-mΩ Sense Resistor (SMBus address = 14h) [reset = 0h]

15

14

13

12

11

10

9

8

Reserved

Charge

Current, bit 6

Current, bit 5

Current, bit 4

Current, bit 3

Current, bit 2

R/W

6

R/W

4

R/W

3

R/W

1

R/W

0

7

5

2

Charge

Reserved

Current, bit 1

Current, bit 0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field

Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-13

12

Reserved

R/W

000b

0b

Not used. 1 = invalid write.

Charge Current, bit 6

0 = Adds 0 mA of charger current.

1 = Adds 4096 mA of charger current.

11

10

9

Charge Current, bit 5

Charge Current, bit 4

Charge Current, bit 3

Charge Current, bit 2

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 2048 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 1024 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 512 mA of charger current.

8

0 = Adds 0 mA of charger current.

1 = Adds 256 mA of charger current.

表 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field

Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Charge Current, bit 1

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 128 mA of charger current.

6

Charge Current, bit 0

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 64 mA of charger current.

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表 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field

Descriptions (接下页)

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

5-0

Reserved

R/W

000000b

Not used. Value Ignored.

8.6.3.1 Battery Pre-Charge Current Clamp

During pre-charge, BATFET works in linear mode or LDO mode (default REG0x12[2] = 1). For 2-4 cell battery,

the system is regulated at minimum system voltage in REG0x3E() and the pre-charge current is clamped at 384

mA. For 1 cell battery, the pre-charge to fast charge threshold is 3 V, and the pre-charge current is clamped at

384 mA. However, the BATFET stays in LDO mode operation till battery voltage is above minimum system

voltage (~3.6 V). During battery voltage from 3 V to 3.6 V, the fast charge current is clamped at 2 A.

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8.6.4 MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin

setting]

To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x15()) using the data

format listed in 表 27 and 表 28. The charger provides charge voltage range from 1.024 V to 19.200 V, with 16-

mV step resolution. Any write below 1.024 V or above 19.200 V is ignored. Upon POR or when charge is

disabled, the system is regulated at the MaxChargeVoltage register.

Upon POR, REG0x15() is by default set as 4192 mV for 1 s, 8400 mV for 2 s, 12592 mV for 3 s or 16800 mV for

4 s. After CHRG_OK, if host writes REG0x14() before REG0x15(), the charge will start after the write to

REG0x14().If the battery is different from 4.2 V/cell, the host has to write to REG0x15() before REG0x14() for

correct battery voltage setting. Writing REG0x15() to 0 will set REG0x15() to default value on CELL_BATPRESZ

pin, and force REG0x14() to zero to disable charge.

The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the

battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to the device as

possible to decouple high frequency noise.

图 27. MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin

setting]

15

14

13

12

11

10

9

8

Reserved

Max Charge

Voltage, bit 10

Max Charge

Voltage, bit 9

Max Charge

Voltage, bit 8

Max Charge

Voltage, bit 7

Max Charge

Voltage, bit 6

Max Charge

Voltage, bit 5

Max Charge

Voltage, bit 4

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Max Charge

Voltage, bit 3

Max Charge

Voltage, bit 2

Max Charge

Voltage, bit 1

Max Charge

Voltage, bit 0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

14

Reserved

R/W

0b

Not used. 1 = invalid write.

Max Charge Voltage, bit 10

0 = Adds 0 mV of charger voltage.

1 = Adds 16384 mV of charger voltage.

13

12

11

10

9

Max Charge Voltage, bit 9

Max Charge Voltage, bit 8

Max Charge Voltage, bit 7

Max Charge Voltage, bit 6

Max Charge Voltage, bit 5

Max Charge Voltage, bit 4

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 8192 mV of charger voltage

0 = Adds 0 mV of charger voltage.

1 = Adds 4096 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 2048 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 1024 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 512 mV of charger voltage.

8

0 = Adds 0 mV of charger voltage.

1 = Adds 256 mV of charger voltage.

表 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Max Charge Voltage, bit 3

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 128 mV of charger voltage.

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表 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions (接下页)

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

6

Max Charge Voltage, bit 2

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 64 mV of charger voltage.

5

Max Charge Voltage, bit 1

Max Charge Voltage, bit 0

Reserved

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 32 mV of charger voltage.

4

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 16 mV of charger voltage.

3-0

0000b

Not used. Value Ignored.

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8.6.5 MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin

setting]

To set the minimum system voltage, write a 16-bit MinSystemVoltage register command (REG0x3E()) using the

data format listed in 表 29 and 表 30. The charger provides minimum system voltage range from 1.024 V to

16.128 V, with 256-mV step resolution. Any write below 1.024 V or above 16.128 V is ignored. Upon POR, the

MinSystemVoltage register is 3.584 V for 1 S, 6.144 V for 2 S and 9.216 V for 3 S, and 12.288 V for 4 S.

图 28. MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin

setting]

15

7

14

6

13

12

11

10

9

8

Reserved

R/W

Min System

Voltage, bit 5

Min System

Voltage, bit 4

Min System

Voltage, bit 3

Min System

Voltage, bit 2

Min System

Voltage, bit 1

Min System

Voltage, bit 0

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

13

Reserved

R/W

00b

0b

Not used. 1 = invalid write.

Min System Voltage, bit 5

0 = Adds 0 mV of system voltage.

1 = Adds 8192 mV of system voltage.

12

11

10

9

Min System Voltage, bit 4

Min System Voltage, bit 3

Min System Voltage, bit 2

Min System Voltage, bit 1

Min System Voltage, bit 0

R/W

0b

0 = Adds 0 mV of system voltage.

1 = Adds 4096mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 2048 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 1024 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 512 mV of system voltage.

8

0 = Adds 0 mV of system voltage.

1 = Adds 256 mV of system voltage.

表 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R/W

0000000

0b

Not used. Value Ignored.

8.6.5.1 System Voltage Regulation

The device employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by REG0x3E(). Even with a deeply depleted battery, the system is regulated

above the minimum system voltage with BATFET.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the

minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference

between the system and battery is the VDS of BATFET. System voltage is regulated 160 mV above battery

voltage when BATFET is off (no charging or no supplement current).

When BATFET is removed, the system node VSYS is shorted to SRP. Before the converter starts operation,

LDO mode needs to be disabled. The following sequence is required to configure charger without BATFET.

1. Before adapter plugs in, put the charger into HIZ mode. (either pull pin 6 ILIM_HIZ to ground, or set

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REG0x32[15] to 1)

2. Set 0x12[2] to 0 to disable LDO mode.

3. Set 0x30[0] to 0 to disable auto-wakeup mode.

4. Check if battery voltage is properly programmed (REG0x15)

5. Set pre-charge/charge current (REG0x14)

6. Put the device out of HIZ mode. (Release ILIM_HIZ from ground and set REG0x32[15]=0).

In order to prevent any accidental SW mistakes, the host sets low input current limit (a few hundred milliamps)

when device is out of HIZ.

8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management

The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for

the system load or to charge the battery. When the input current exceeds the input current setting, or the input

voltage falls below the input voltage setting, the charger decreases the charge current to provide priority to the

system load. As the system current rises, the available charge current drops accordingly towards zero. If the

system load keeps increasing after the charge current drops down to zero, the system voltage starts to drop. As

the system voltage drops below the battery voltage, the battery will discharge to supply the heavy system load.

8.6.6.1 Input Current Registers

To set the maximum input current limit, write a 16-bit IIN_HOST register command (REG0x3F()) using the data

format listed in 表 31 and 表 32. When using a 10-mΩ sense resistor, the charger provides an input-current limit

range of 50 mA to 6400 mA, with 50-mA resolution. The default current limit is 3.3 A. Due to the USB current

setting requirement, the register setting specifies the maximum current instead of the typical current. Upon

adapter removal, the input current limit is reset to the default value of 3.3 A. The register offset is 50 mA. With

code 0, the input current limit is 50 mA.

The ACP and ACN pins are used to sense R_ACwith the default value of 10 mΩ. For a 20-mΩ sense resistor, a

larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss.

Instead of using the internal DPM loop, the user can build up an external input current regulation loop and have

the feedback signal on the ILIM_HIZ pin.

V

= 1V + 40´ V

(

- V_ACN= 1+ 40´I_DPM´R_AC

)

ILIM_HIZ

ACP

(2)

In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above

4.0 V.

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8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h]

The register offset is 50 mA. With code 0, the input current limit readback is 50 mA.

图 29. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]

15

14

13

12

11

10

9

8

Reserved

Input Current

set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit

6

5

4

3

2

1

0

R/W

7

R/W

6

5

4

3

2

1

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 31. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

14

Reserved

R/W

0b

1b

Not used. 1 = invalid write.

Input Current set by host, bit 6

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.

13

12

11

10

9

Input Current set by host, bit 5

Input Current set by host, bit 4

Input Current set by host, bit 3

Input Current set by host, bit 2

Input Current set by host, bit 1

Input Current set by host, bit 0

R/W

0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 800 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.

8

0 = Adds 0 mA of input current.

1 = Adds 50 mA of input current.

表 32. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R

0000000

0b

Not used. Value Ignored.

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8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]

IIN_DPM register reflects the actual input current limit programmed in the register, either from host or from ICO.

After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual

DPM limit is reported in REG0x22(). The register offset is 50 mA. With code 0, the input current limit read-back is

50 mA.

图 30. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h]

15

14

13

12

11

10

9

8

Reserved

Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in

DPM, bit 6

R

DPM, bit 5

R

DPM, bit 4

R

DPM, bit 3

R

DPM, bit 2

R

DPM, bit 1

R

DPM, bit 0

R

7

6

5

4

3

2

1

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 33. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

14

Reserved

R

0b

Not used. 1 = invalid write.

Input Current in DPM, bit 6

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.

13

12

11

10

9

Input Current in DPM, bit 5

Input Current in DPM, bit 4

Input Current in DPM, bit 3

Input Current in DPM, bit 2

Input Current in DPM, bit 1

Input Current in DPM, bit 0

R

0b

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 800mA of input current

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.

8

0 = Adds 0 mA of input current.

1 = Adds 50 mA of input current.

表 34. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R

00000000b

Not used. Value Ignored.

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8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]

To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x3D()) using the data format

listed in 表 35 and 表 36.

If the input voltage drops more than the InputVoltage register allows, the device enters DPM and reduces the

charge current. The default offset voltage is 1.28 V below the no-load VBUS voltage. The DC offset is 3.2 V

(0000000).

图 31. InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]

15

7

14

13

12

11

10

9

8

Reserved

R/W

Input Voltage,

bit 7

Input Voltage,

bit 6

Input Voltage,

bit 5

Input Voltage,

bit 4

Input Voltage,

bit 3

Input Voltage,

bit 2

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

6

Input Voltage,

bit 1

Input Voltage,

bit 0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 35. InputVoltage Register (SMBus address = 3Dh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

13

Reserved

R/W

00b

0b

Not used. 1 = invalid write.

Input Voltage, bit 7

0 = Adds 0 mV of input voltage.

1 = Adds 8192 mV of input voltage.

12

11

10

9

Input Voltage, bit 6

Input Voltage, bit 5

Input Voltage, bit 4

Input Voltage, bit 3

Input Voltage, bit 2

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 4096mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 2048 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 1024 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 512 mV of input voltage.

8

0 = Adds 0 mV of input voltage.

1 = Adds 256 mV of input voltage.

表 36. InputVoltage Register (SMBus address = 3Dh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Input Voltage, bit 1

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 128 mV of input voltage.

6

Input Voltage, bit 0

Reserved

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 64 mV of input voltage

5-0

000000b

Not used. Value Ignored.

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8.6.7 OTGVoltage Register (SMBus address = 3Bh) [reset = 0h]

To set the OTG output voltage limit, write to REG0x3B() using the data format listed in 表 37 and 表 38. The DC

offset is 4.48 V (0000000).

图 32. OTGVoltage Register (SMBus address = 3Bh) [reset = 0h]

15

7

14

6

13

12

11

10

9

8

Reserved

R/W

OTG Voltage,

bit 7

OTG Voltage,

bit 6

OTG Voltage,

bit 5

OTG Voltage,

bit 4

OTG Voltage,

bit 3

OTG Voltage,

bit 2

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

OTG Voltage,

bit 1

OTG Voltage,

bit 0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 37. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

13

Reserved

R/W

00b

0b

Not used. 1 = invalid write.

OTG Voltage, bit 7

0 = Adds 0 mV of OTG voltage.

1 = Adds 8192 mV of OTG voltage.

12

11

10

9

OTG Voltage, bit 6

OTG Voltage, bit 5

OTG Voltage, bit 4

OTG Voltage, bit 3

OTG Voltage, bit 2

R/W

0b

0 = Adds 0 mV of OTG voltage.

1 = Adds 4096 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 2048 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 1024 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 512 mV of OTG voltage.

8

0 = Adds 0 mV of OTG voltage.

1 = Adds 256 mV of OTG voltage.

表 38. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

OTG Voltage, bit 1

R/W

0b

0 = Adds 0 mV of OTG voltage.

1 = Adds 128 mV of OTG voltage.

6

OTG Voltage, bit 0

Reserved

R/W

0b

0 = Adds 0 mV of OTG voltage.

1 = Adds 64 mV of OTG voltage.

5-0

000000b

Not used. Value Ignored.

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8.6.8 OTGCurrent Register (SMBus address = 3Ch) [reset = 0h]

To set the OTG output current limit, write to REG0x3C() using the data format listed in 表 39 and 表 40.

图 33. OTGCurrent Register (SMBus address = 3Ch) [reset = 0h]

15

14

13

12

11

10

9

8

Reserved

OTG Current

set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit

6

5

4

3

2

1

0

R/W

7

R/W

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 39. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

14

Reserved

R/W

0b

Not used. 1 = invalid write.

OTG Current set by host, bit 6

0 = Adds 0 mA of OTG current.

1 = Adds 3200 mA of OTG current.

13

12

11

10

9

OTG Current set by host, bit 5

OTG Current set by host, bit 4

OTG Current set by host, bit 3

OTG Current set by host, bit 2

OTG Current set by host, bit 1

OTG Current set by host, bit 0

R/W

0b

0 = Adds 0 mA of OTG current.

1 = Adds 1600mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 800 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 400 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 200 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 100 mA of OTG current.

8

0 = Adds 0 mA of OTG current.

1 = Adds 50 mA of OTG current.

表 40. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R/W

00000000

b

Not used. Value Ignored.

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8.6.9 ADCVBUS/PSYS Register (SMBus address = 23h)

•

PSYS: Full range: 3.06 V, LSB: 12 mV

VBUS: Full range: 3200 mV to 19520 mV, LSB: 64 mV

图 34. ADCVBUS/PSYS Register (SMBus address = 23h)

15

R

7

14

R

6

13

R

5

12

R

4

11

R

3

10

R

2

9

R

1

8

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 41. ADCVBUS/PSYS Register Field Descriptions

BIT

15-8

7-0

FIELD

TYPE

RESET

DESCRIPTION

R

8-bit Digital Output of Input Voltage

8-bit Digital Output of System Power

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8.6.10 ADCIBAT Register (SMBus address = 24h)

•

ICHG: Full range: 8.128 A, LSB: 64 mA

IDCHG: Full range: 32.512 A, LSB: 256 mA

图 35. ADCIBAT Register (SMBus address = 24h)

15

Reserved

7

14

R

6

13

R

5

12

R

4

11

R

3

10

R

2

9

R

1

8

R

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 42. ADCIBAT Register Field Descriptions

BIT

15

FIELD

TYPE

RESET

DESCRIPTION

Reserved

R

Not used. Value ignored.

14-8

7

7-bit Digital Output of Battery Charge Current

Not used. Value ignored.

Reserved

6-0

7-bit Digital Output of Battery Discharge Current

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8.6.11 ADCIINCMPIN Register (SMBus address = 25h)

•

IIN: Full range: 12.75 A, LSB: 50 mA

CMPIN: Full range: 3.06 V, LSB: 12 mV

图 36. ADCIINCMPIN Register (SMBus address = 25h)

15

R

7

14

R

6

13

R

5

12

R

4

11

R

3

10

R

2

9

R

1

8

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 43. ADCIINCMPIN Register Field Descriptions

BIT

15-8

7-0

FIELD

TYPE

RESET

DESCRIPTION

R

8-bit Digital Output of Input Current

8-bit Digital Output of CMPIN voltage

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8.6.12 ADCVSYSVBAT Register (SMBus address = 26h)

•

VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV

VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV

图 37. ADCVSYSVBAT Register (SMBus address = 26h) (reset = )

15

R

7

14

R

6

13

R

5

12

R

4

11

R

3

10

R

2

9

R

1

8

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 44. ADCVSYSVBAT Register Field Descriptions

BIT

15-8

7-0

FIELD

TYPE

RESET

DESCRIPTION

R

8-bit Digital Output of System Voltage

8-bit Digital Output of Battery Voltage

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8.6.13 ID Registers

8.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]

图 38. ManufactureID Register (SMBus address = FEh) [reset = 0040h]

15-0

MANUFACTURE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 45. ManufactureID Register Field Descriptions

SMBus

BIT

FIELD

TYPE

RESET

DESCRIPTION (READ ONLY)

40h

15-0

MANUFACTURE_ID

R

8.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]

图 39. Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]

15-8

Reserved

R

7-0

DEVICE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 46. Device ID (DeviceAddress) Register Field Descriptions

SMBus

FIELD

TYPE

RESET

DESCRIPTION (READ ONLY)

BIT

15-8

7-0

Reserved

R

0b

Reserved

DEVICE_ID

SMBus: 79h

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The bq2570xEVM-732 evaluation module (EVM) is a complete charger module for evaluating the bq25700A. The

application curves were taken using the bq2570xEVM-732. Refer to the EVM user's guide (SLUUBG6) for EVM

information.

9.2 Typical Application

VSYS

6x10mF

2.2uH

RAC=10mW

RSR=10mW

ADAPTER

2.2W

Q2

6x10mF

BATT

10nF

Q3

Q1

Q4

47nF

1mF

10W

1W

Optional

snubber

15nF

HIDRV1

VBUS

SW1BTST1 BTST2 SW2

HIDRV2

LODRV2

LODRV1

SYS

470nF

BATDRV

SRP

ACN

ACP

10W

SRN

REGN

VDDA

REGN

ILIM_HIZ

1uF

2.2œ3.3uF

VDDA

GND

bq25700A

350kW

CELL_BATPRESZ

250kW

COMP1

COMP2

IADPT

IBAT

PSYS

100pF

100kW

30kW

CHRG_OK

SDA SCL

CMPOUT

CMPIN

50W

PROCHOT

1.05V

EN_OTG

10kW

To CPU

10kW

3.3V or 1.8V

Host

(SMBus)

图 40. Application Diagram

9.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

3.5 V < Adapter Voltage < 24 V

3.2 A for 65 W adapter

Input Voltage⁽¹⁾

(1)

Input Current Limit

Battery Charge Voltage⁽²⁾

8400 mV for 2s battery

(1) Refer to adapter specification for settings for Input Voltage and Input Current Limit.

(2) Refer to battery specification for settings.

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Typical Application (接下页)

DESIGN PARAMETER

Battery Charge Current⁽²⁾

Minimum System Voltage⁽²⁾

EXAMPLE VALUE

3072 mA for 2s battery

6144 mV for 2s battery

9.2.2 Detailed Design Procedure

The parameters are configurable using the evaluation software. The simplified application circuit (see 图 40, as

the application diagram) shows the minimum component requirements. Inductor, capacitor, and MOSFET

selection are explained in the rest of this section. Refer to the EVM user's guide (SLUUBG6) for the complete

application schematic.

9.2.2.1 ACP-ACN Input Filter

The bq25700A has average current mode control. The input current sensing through ACP/ACN is critical to

recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-ACN

which overwhelms converter sensed inductor current information, so it is difficult to manage parasitic inductance

created based on different PCB layout. Bigger parasitic inductance will generate bigger sense current ringing

which will cause the average current control loop to go into oscillation.

For real system board condition, we suggest to use below circuit design to get best result and filter noise induced

from different PCB parasitic factor. With time constant of filter from 47 nsec to 200 nsec, the filtering on ringing is

effective and in the meantime, the delay of on the sensed signal is small and therefore poses no concern for

average current mode control.

RAC

Q1

4~6x10uF

(0805)

1nF+10nF

(0402)

RACN

RACP

10ohm

CDIFF

Open

CACN

CACP

15nF

ACP

ACN

HIDRV1

bq2570x

图 41. ACN-ACP Input Filter

9.2.2.2 Inductor Selection

The bq25700A has two selectable fixed switching frequency. Higher switching frequency allows the use of

smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current

(I_CHG) plus half the ripple current (I_RIPPLE):

I_SAT³ I_CHG+ (1/2) I_RIPPLE

(3)

The inductor ripple current in buck operation depends on input voltage (V_IN), duty cycle (D_BUCK= V_OUT/V_IN),

switching frequency (f_S) and inductance (L):

V

´ D ´ (1 - D)

IN

I_{RIPPLE_BUCK}

=

f_S´ L

(4)

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During boost operation, the duty cycle is:

D_BOOST= 1 – (V_IN/V_BAT

)

and the ripple current is:

I_{RIPPLE_BOOST}= (VIN × D_BOOST) / (f_S× L)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging

voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives

the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to

16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20 – 40%) maximum charging current as a trade-off between

inductor size and efficiency for a practical design.

9.2.2.3 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5 in buck mode. If the converter does not

operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to

50% and can be estimated by 公式 5:

I_CIN= I_CHG

´

D × (1 - D)

(5)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred

for 19 V - 20 V input voltage. Minimum 4 - 6 pcs of 10-µF 0805 size capacitor is suggested for 45 - 65 W adapter

design.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is

applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant

capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's

datasheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage

rating or nominal capacitance value in order to get the required value at the operating point.

9.2.2.4 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. In buck

mode the output capacitor RMS current is given:

To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed

between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum

6 pcs of 10-µF 0805 size capacitor is suggested to be placed by the inductor. Place the capacitors after Q4

drain. Place minimum 10 µF after the charge current sense resistor for best stability.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is

applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant

capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data

sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage

rating or nominal capacitance value in order to get the required value at the operating point.

9.2.2.5 Power MOSFETs Selection

Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are

internally integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are

preferred for 19 V - 20 V input voltage.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction

loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,

R_DS(ON), and the gate-to-drain charge, Q_GD. For the bottom side MOSFET, FOM is defined as the product of the

MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

FOM_top= R_DS(on)x Q_GD; FOM_bottom= R_DS(on)x Q_G

(6)

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON)has higher cost with the same

package size.

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The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle

(D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance (R_DS(ON)), input voltage (V_IN), switching frequency

(f_S), turn on time (t_on) and turn off time (t_off):

1

2

= D ´ I_CHG´ R_DS(on)

P

+

´ V ´ I_CHG´ (t_on+ t_off) ´ f_s

IN

top

2

(7)

The first item represents the conduction loss. Usually MOSFET R_DS(ON)increases by 50% with 100°C junction

temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are

given by:

Q_SW

t_on

=

, t_off=

I_on

I_off

(8)

where Q_swis the switching charge, I_onis the turn-on gate driving current and I_offis the turn-off gate driving

current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge

(Q_GD) and gate-to-source charge (Q_GS):

1

Q_SW= Q_GD

+

´ Q_GS

2

(9)

Gate driving current can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on

gate resistance (R_on) and turn-off gate resistance (R_off) of the gate driver:

V_REGN- V_plt

V_plt

I_on

=

, I_off=

R_on

R_off

(10)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in

synchronous continuous conduction mode:

P_bottom= (1 - D) x I_CHG²x R_DS(on)

(11)

When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the

freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss

depends on its forward voltage drop (V_F), non-synchronous mode charging current (I_NONSYNC), and duty cycle (D).

P_D= V_Fx I_NONSYNCx (1 - D)

(12)

The maximum charging current in non-synchronous mode can be up to 0.25 A for a 10-mΩ charging current

sensing resistor or 0.5 A if battery voltage is below 2.5 V. The minimum duty cycle happens at lowest battery

voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the

maximum non-synchronous mode charging current.

9.2.3 Application Curves

CH1: VBUS

CH2: VDDA

CH1: VBUS

CH2: VDDA

CH3: CHRG_OK

CH4: VSYS

2-cell without battery

图 42. Power Up from 20 V

图 43. Power Up from 5 V

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CH1: VBUS

CH2: SW1

CH3: SW2

CH4: VSYS with 9Vos

CH4: IL

3-cell VBAT = 10 V

VBUS 5 V to 20 V

图 44. Power Off from 12 V

图 45. System Regulation

CH2: SW1

CH1: HIDRV1

CH2: SW1

CH3: LODRV1

CH3: SW2

CH4: IL

CH1: IL

VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA

图 46. PFM Operation

图 47. PWM Operation

CH2: SW2

CH2: SW1

CH3: SW2

CH1: HIDRV2

CH3: LODRV2

CH4: IL

VBUS = 5 V, VBAT = 10 V

VBUS = 12 V, VBAT = 12 V

图 49. Switching During Buck Boost Mode

图 48. Switching During Boost Mode

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CH1: VSYS

CH2: IIN

CH1: VSYS

CH2: IIN

CH3: ISYS

VBUS = 12 V/3.3 A, 3-cell, VSYS = 9 V, Without battery

VBUS = 9 V/3.3 A, 3-cell, VSYS = 9 V, Without battery

图 50. System Regulation in Buck Mode

图 51. System Regulation in Buck Boost Mode

CH1: VSYS

CH2: IIN

CH3: ISYS

CH4: IBAT

CH3: ISYS

VBUS = 5 V/3.3 A, 3-cell, VSYS = 9 V, Without battery

VBUS = 20 V/3.3 V, VBAT = 7.5 V

图 52. System Regulation in Boost Mode

图 53. Input Current Regulation in Buck Mode

CH2:IIN

CH1: EN_OTG

CH2: VBUS

CH3:ISYS

CH4:IBAT

VBUS = 5 V/3.3 V, VBAT = 7.5 V

VBUS = 5 V

图 54. Input Current in Boost Mode

图 55. OTG Power Up from 8 V Battery

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CH1: SCL

CH2: VBUS

CH3: SW2

VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA

图 56. OTG Voltage Ramp Up

图 57. OTG Power Off

CH2: VBUS

CH3: IVBUS

VBAT = 10 V, VBUS = 20 V

图 58. OTG Load Transient

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10 Power Supply Recommendations

The valid adapter range is from 3.5 V (V_{VBUS_CONVEN}) to 24 V (ACOV) with at least 500-mA current rating. When

CHRG_OK goes HIGH, the system is powered from adapter through the charger. When adapter is removed, the

system is connected to battery through BATFET. Typically the battery depletion threshold should be greater than

the minimum system voltage so that the battery capacity can be fully utilized for maximum battery life.

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11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Layout Example section) is important to prevent

electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for

proper layout. Layout PCB according to this specific order is essential.

1. Place the input capacitor as close as possible to the supply of the switching MOSFET and ground

connections. Use a short copper trace connection. These parts must be placed on the same layer of PCB

using vias to make this connection.

2. The device must be placed close to the gate pins of the switching MOSFET. Keep the gate drive signal

traces short for a clean MOSFET drive. The device can be placed on the other side of the PCB of switching

MOSFETs.

3. Place an inductor input pin as close as possible to the output pin of the switching MOSFET. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to

carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the device in same layer, close to each other (minimize

loop area) and do not route the sense leads through a high-current path (see 图 60 for Kelvin connection for

best current accuracy). Place a decoupling capacitor on these traces next to the device.

5. Place an output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor

ground before connecting to system ground.

7. Use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath

the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise

coupling.

8. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using power pad as the single ground

connection point. Or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to

analog ground in this case if possible).

9. Decoupling capacitors must be placed next to the device pins. Make trace connection as short as possible.

10. It is critical that the exposed power pad on the backside of the device package be soldered to the PCB

ground.

11. The via size and number should be enough for a given current path. See the EVM design (SLUUBG6) for

the recommended component placement with trace and via locations. For WQFN information, see SLUA271.

11.2 Layout Example

11.2.1 Layout Consideration of Current Path

R1

L1

V_BAT

PHASE

High

Frequency

Current

Path

V_IN

BAT

GND

C2

C1

图 59. High Frequency Current Path

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Layout Example (接下页)

11.2.2 Layout Consideration of Short Circuit Protection

Charge Current Direction

R_SNS

To Inductor

To Capacitor and battery

Current Sensing Direction

To SRP and SRN pin

图 60. Sensing Resistor PCB Layout

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12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

半导体和集成电路封装热指标应用报告 SPRA953

bq2570x 评估模块用户指南SLUUBG6

QFN/SON PCB 连接应用报告 SLUA271

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

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13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

76

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jun-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25700ARSNR

BQ25700ARSNT

QFN

RSN

32

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Jun-2018

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25700ARSNR

BQ25700ARSNT

QFN

RSN

32

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

重要声明和免责声明

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型号：	BQ25700A
厂家：	TEXAS INSTRUMENTS
描述：	具有系统功率监控器和处理器的 SMBus 1 至 4 节 NVDC 降压/升压电池充电控制器电池控制器监控
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BQ25700A [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E