BQ25730_技术文档

BQ25730

SLUSE65 – FEBRUARY 2021

BQ25730 I²C 1- to 5-Cell Buck-Boost Narrow VDC Battery Charge Controller with

Power Path Control and USB-C PD 3.0 OTG Output

– Thermal shutdown

1 Features

– Input, system, battery overvoltage protection

•

Power path control through battery MOSFET

implementing independent system voltage instant-

on with no battery or depleted battery

400-kHz/800-kHz programmable switching

frequency for high efficiency/high power density

Buck-boost narrow voltage DC (NVDC) charger for

USB-C Power Delivery (PD) interface platform

– 3.5-V to 26-V input range to charge 1- to 5-cell

battery

– Charge current up to 16.2 A/8.1 A with 128-

mA/64-mA resolution based on 5-mΩ/10-mΩ

sensing resistor

– Input current limit up to 10 A/6.35 A with 100-

mA/50-mA resolution based on 5-mΩ/10-mΩ

sensing resistor

– Support USB 2.0, USB 3.0, USB 3.1 and USB

Power Delivery (PD)

– Input Current Optimizer (ICO) to extract max

input power without overloading the adapter

– Seamless transition between buck, buck-boost,

and boost operations

– Input current and voltage regulation (IINDPM

and VINDPM) against source overload

TI patented switching frequency dithering pattern

for EMI noise reduction

– Input, MOSFET, inductor overcurrent protection

Package: 32-Pin 4.0 mm × 4.0 mm WQFN

•

2 Applications

•

Oxygen concentrator, ventilators,vacuum robot

Tablet (multimedia), wireless speaker

3 Description

The BQ25730 is a synchronous NVDC buck-boost

battery charge controller to charge a 1- to 5-cell

battery from a wide range of input sources including

USB adapter, high voltage USB-C Power Delivery

(PD) sources, and traditional adapters. It offers a low

component count, high efficiency solution for space

constrained, 1- to 5-cell battery charging applications.

The Narrow VDC buck-boost architecture avoid direct

power path from input source to system voltage

which implements wide input voltage range and

narrow system voltage range at same time. Narrow

system voltage range is valuable for faster battery

supplement and lower MOSFET rating for next stage

converter.

Device Information

•

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

BQ25730

WQFN (32) 4.00 mm × 4.00 mm

TI patented Pass Through Mode (PTM) for system

power efficiency improvement and battery fast

charging achieving 99% efficiency.

Input and battery current monitor through

dedicated pins

Integrated 8-bit ADC to monitor voltage, current

and power

Battery MOSFET ideal diode operation in

supplement mode to support system when adapter

is fully loaded

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

VSYS

Q2

Q3

Q1

Q4

VBUS

3.5V-26V

HIDRV1 LODRV1 SW1

SW2 LODRV2 HIDRV2

VBUS

ACN

SYS

/BATDRV

BQ25730

SRP

SRN

ACP

•

Power up USB port from battery (USB OTG)

– 3-V to 24-V OTG with 8-mV resolution

– Output current limit up to 12.7 A/6.35 A with

100-mA/50-mA resolution based on 5-mΩ/10-

mΩ sensing resistor

Host (I2C)

•

I²C host control interface for flexible system

configuration

Application Diagram

High accuracy for the regulation and monitor

– ±0.5% Charge voltage regulation

– ±3% Charge current regulation

– ±2.5% Input current regulation

– ±2% Input/charge current monitor

Safety

•

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

BQ25730

SLUSE65 – FEBRUARY 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Device Comparison Table...............................................4

7 Pin Configuration and Functions...................................5

8 Specifications.................................................................. 8

8.1 Absolute Maximum Ratings........................................ 8

8.2 ESD Ratings............................................................... 8

8.3 Recommended Operating Conditions.........................8

8.4 Thermal Information....................................................9

8.5 Electrical Characteristics(BQ25730)...........................9

8.6 Timing Requirements................................................19

8.7 Typical Characteristics..............................................21

9 Detailed Description......................................................25

9.1 Overview...................................................................25

9.2 Functional Block Diagram.........................................26

9.3 Feature Description...................................................27

9.4 Device Functional Modes..........................................38

9.5 Programming............................................................ 39

9.6 Register Map.............................................................43

10 Application and Implementation................................87

10.1 Application Information........................................... 87

10.2 Typical Application.................................................. 87

11 Power Supply Recommendations..............................97

12 Layout...........................................................................98

12.1 Layout Guidelines................................................... 98

12.2 Layout Example...................................................... 99

13 Device and Documentation Support........................101

13.1 Device Support..................................................... 101

13.2 Documentation Support........................................ 101

13.3 Support Resources............................................... 101

13.4 Trademarks...........................................................101

13.5 Electrostatic Discharge Caution............................101

13.6 Glossary................................................................101

14 Mechanical, Packaging, and Orderable

Information.................................................................. 102

4 Revision History

DATE

REVISION

NOTES

February 2021

*

Initial release.

2

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5 Description (continued)

The NVDC configuration allows the system to be regulated based on battery voltage, but not drop below system

minimum voltage. The system keeps operating even when the battery is completely discharged or removed.

When load power exceeds input source rating, the battery goes into supplement mode and prevents the system

from crashing.

During power up, the charger sets the converter to a buck, boost, or buck-boost configuration based on the input

source and battery conditions. The charger seamlessly transitions between the buck, boost, and buck-boost

operation modes without host control.

In the absence of an input source, the BQ25730 supports the USB On-the-Go (OTG) function from a 1- to 5-cell

battery to generate an adjustable 3-V to 24-V output on VBUS with 8-mV resolution. The OTG output voltage

transition slew rate can be configured to comply with the USB-PD 3.0 PPS specification.

The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping

occurs in a timely fashion so that the device(s) connected to the dock can avoid experiencing momentary power

loss or glitching. This device integrates FRS in compliance with the PD specification.

TI patented switching frequency dithering pattern can significantly reduce EMI noise over the whole conductive

EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide flexibility for

different applications to simplify EMI noise filter design.

The charger can be operated in the TI patented Pass Through Mode (PTM) to improve efficiency over the full

load range. In PTM, input power is directly passed through the charger to the system. Switching losses of the

MOSFETs and inductor core loss can be saved for high efficiency operation.

The BQ25730 is available in a 32-pin 4 mm × 4 mm WQFN package.

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6 Device Comparison Table

BQ25710

SMBus

09h

BQ25713

I²C

BQ25792

I²C

BQ25730

I²C

BQ25731

Interface

I²C

Device Address

6Bh

Integrated

MOSFET

Integrated MOSFET/Controller

Controller

Maximum Charge Current

Switching Frequency (Hz)

Cell Count

8.128 A

800 k/1.2 M

1s to 4s

8.128 A

800 k/1.2 M

1s to 4s

5 A

750 k/1.5 M

1s to 4s

Integrated

NA

16.256 A

400 k/800 k

1s to 5s

16.256 A

400 k/800 k

1s to 5s

Input Current Sense Resistor

Independent Comparator Latch

10 mΩ/20 mΩ

Non Latch

10 mΩ/20 mΩ

5 mΩ/10 mΩ

Latch/Non latch

(default)

Latch/Non latch

(default)

Non Latch

2.4 V

2.2 V

2.4 V ~ 8.0 V

(0.8-V step size)

Default: 2.4 V

1.6 V

VSYS_UVP

2.4 V

OTG Voltage Range

Frequency Dithering

BATFET Power Path

Pre-charge LDO Mode

3.0 V to 20.8 V

2.8 V to 22 V

3.0 V to 24 V

No

Yes

No

Yes

No

Yes

No

4

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7 Pin Configuration and Functions

VBUS

ACN

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

HIDRV2

SW2

ACP

VSYS

BATDRV

SRP

CHRG_OK

OTG/VAP/FRS

ILIM_HIZ

VDDA

Thermal

Pad

SRN

CELL_BATPRESZ

COMP2

IADPT

Figure 7-1. RSN Package 32-Pin WQFN Top View

Table 7-1. Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

Input current sense amplifier negative input. The leakage on ACP and ACN are matched. A

RC low-pass filter is required to be placed between the sense resistor and the ACN pin to

suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.2 for

ACP/ACN filter design.

ACN

ACP

2

PWR

Input current sense amplifier positive input. The leakage on ACP and ACN are matched. A

RC low-pass filter is required to be placed between the sense resistor and the ACP pin to

suppress the high frequency noise in the input current signal. Refer to Section 10.2.2.2 for

ACP/ACN filter design.

3

PWR

O

P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the

BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to

regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on

during fast charge and works as an ideal-diode in supplement mode.

BATDRV

21

Buck mode high-side power MOSFET driver power supply. Connect a 0.047-µF capacitor

between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.

BTST1

BTST2

30

25

PWR

Boost mode high-side power MOSFET driver power supply. Connect a 0.047-μF capacitor

between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.

Battery cell selection pin for 1- to 5- cell battery setting. CELL_BATPRESZ pin is biased

from VDDA through a resistor divider. CELL_BATPRESZ pin also sets SYSOVP thresholds

to 5 V for 1-cell, 12 V for 2-cell and 19.5 V for 3-cell/4-cell. CELL_BATPRESZ pin is

pulled below V_{CELL_BATPRESZ_FALL}to indicate battery removal. After battery is removed the

charge voltage register REG0x05/04h() goes back to default. No external cap is allowed

at CELL_BATPRESZ pin. The device exits LEARN mode and disables charge when

CELL_BATPRESZ pin is pulled low (upon battery removal).

CELL_BATPRESZ

18

I

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Table 7-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NUMBER

Open drain active high indicator to inform the system good power source is connected to

the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5

V and falls below 25.8 V, CHRG_OK is HIGH after 50-ms deglitch time. When VBUS falls

below 3.2 V or rises above 26.8 V, CHRG_OK is LOW. When one of SYSOVP, SYSUVP,

ACOC, TSHUT, BATOVP, BATOC or force converter off faults occurs, CHRG_OK is asserted

LOW.

CHRG_OK

4

O

Input of independent comparator. The independent comparator compares the voltage

sensed on CMPIN pin with internal reference, and its output is on CMPOUT pin. Internal

reference, output polarity and deglitch time is selectable by the I²C host. With polarity HIGH

(CMP_POL = 1b), place a resistor between CMPIN and CMPOUT to program hysteresis.

With polarity LOW (CMP_POL = 0b), the internal hysteresis is 100 mV. If the independent

comparator is not in use, tie CMPIN to ground.

CMPIN

14

15

I

Open-drain output of independent comparator. Place a pullup resistor from CMPOUT to

pullup supply rail. Internal reference, output polarity and deglitch time are selectable by the

I²C host. If the independent comparator is not in use, float CMPOUT pin.

CMPOUT

O

Buck boost converter compensation pin 2. Refer to Section 9.3.12 for COMP2 pin RC

network.

COMP2

COMP1

17

16

I

Buck boost converter compensation pin 1. Refer to Section 9.3.12 for COMP1 pin RC

network.

Active HIGH to enable OTG or FRS modes. 1) When OTG_VAP_MODE=1b and

EN_OTG=1b, pulling high this pin can enable OTG mode. 2) When OTG_VAP_MODE=1b

and EN_FRS=1b, pulling high this pin can enable FRS mode in forward operation.

OTG/VAP/FRS

5

I

Buck mode high-side power MOSFET (Q1) driver. Connect to high-side n-channel MOSFET

gate.

HIDRV1

HIDRV2

31

24

O

Boost mode high-side power MOSFET(Q4) driver. Connect to high-side n-channel MOSFET

gate.

The adapter current monitoring output pin. V_IADPT= 20 or 40 × (V_ACP– V_ACN) with ratio

selectable through IADPT_GAIN bit. This pin is also used to program the inductance used in

the application. Refer to Section 9.3.11 for selecting resistor from the IADPT pin to ground .

For a 4.7-µH inductance, the resistor is 191-kΩ or 187-kΩ standard value. Place a 100-pF

or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is

clamped below 3.3 V.

IADPT

IBAT

8

9

O

The battery current monitoring output pin. V_IBAT= 8 or 16 × (V_SRP– V_SRN) for charge

current, or V_IBAT= 8 or 16 × (V_SRN– V_SRP) for discharge current, with ratio selectable

through IBAT_GAIN bit. Place a 100-pF or less ceramic decoupling capacitor from IBAT pin

to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.

Input current limit setting pin. Program ILIM_HIZ voltage by connecting a resistor divider

from VDDA rail to ground. The pin voltage is calculated as: V_{(ILIM_HIZ)}= 1 V + 40 × IDPM ×

Rac, in which IDPM is the target input current limit.

When EN_EXTILIM = 1b the input current limit used by the charger is the lower setting of

ILIM_HIZ pin and IIN_HOST register. When EN_EXTILIM = 0b input current limit is only

determined by IIN_HOST register.

When the pin voltage is below 0.4 V, the device enters high impedance (HIZ) mode with

low quiescent current. When the pin voltage is above 0.8 V, the device is out of HIZ mode.

The ILIM_HIZ pin voltage is continuous read and used for updating current limit setting (If

EN_EXTILIM=1b ), this allows dynamic change input current limit setting by adjusting this pin

voltage.

ILIM_HIZ

LODRV1

6

I

Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET

gate.

29

O

Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET

gate.

LODRV2

PGND

26

27

O

GND

Device power ground.

Active low open drain output indicator. It monitors adapter input current, battery discharge

current, and system voltage. After any event in the PROCHOT profile is triggered, a pulse is

asserted. The minimum pulse width is adjustable through PROCHOT_WIDTH bits.

PROCHOT

11

O

6

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Table 7-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NUMBER

Current mode system power monitor. The output current is proportional to the total power

from the adapter and the battery. The gain is selectable through I²C. Place a resistor from

PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output

voltage is clamped at 3.3 V. Place a capacitor in parallel with the resistor for filtering.

PSYS

REGN

10

O

6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS

above V_{VBUS_CONVEN}. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power

ground. REGN pin output is for power stage gate drive.

28

PWR

I²C clock input. Connect to clock line from the host controller or smart battery. Connect a

10-kΩ pullup resistor according to specifications.

SCL

SDA

13

12

I

I²C open-drain data I/O. Connect to data line from the host controller or smart battery.

Connect a 10-kΩ pullup resistor according to I²C specifications.

I/O

Charge current sense amplifier negative input. SRN pin is for battery voltage sensing as

well. Connect a 0.1-μF filter cap cross battery charging sensing resistor and use 10-Ω

contact resistor between SRN pin and battery charging sensing resistor. The leakage current

on SRP and SRN are matched.

SRN

SRP

19

20

PWR

Charge current sense amplifier positive input. Connect a 0.1-μF filter cap cross battery

charging sensing resistor and use 10-Ω contact resistor between SRP pin and battery

charging sensing resistor. The leakage current on SRP and SRN are matched.

Buck mode switching node. Connect to the source of the buck half bridge high side n-

channel MOSFET.

SW1

32

23

1

PWR

Boost mode switching node. Connect to the source of the boost half bridge high side

n-channel MOSFET.

SW2

Charger input voltage. An input low pass filter of 1 Ω and 0.47 µF (minimum) is

recommended.

VBUS

VDDA

Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF

ceramic capacitor from VDDA to power ground.

7

Charger system voltage sensing. The system voltage regulation maximum limit is

programmed in ChargeVoltage register plus 150 mV and regulation minimum limit is

programmed in VSYS_MIN register.

VSYS

22

–

PWR

–

Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on

the thermal pad plane connecting to power ground planes. It serves as a thermal pad to

dissipate the heat.

Thermal pad

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–2

MAX

32

38

7

UNIT

SRN, SRP, ACN, ACP, VBUS, VSYS

SW1, SW2

BTST1, BTST2, HIDRV1, HIDRV2, BATDRV

LODRV1, LODRV2 (25nS)

HIDRV1, HIDRV2 (25nS)

–0.3

–4

38

32

Voltage

V

SW1, SW2 (25nS)

–4

SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,

LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/

FRS,

–0.3

7

PROCHOT

–0.3

–0.5

–40

5.5

3.6

7

IADPT, IBAT, COMP1

BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2

SRP-SRN, ACP-ACN

Differential

Voltage

V

0.5

150

Temperature

Junction temperature range, T_J

Storage temperature, T_stg

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0

NOM

MAX

26

UNIT

ACN, ACP, VBUS

SRN, SRP, VSYS

0

23.15

26

SW1, SW2

–2

0

BTST1, BTST2, HIDRV1, HIDRV2, BATDRV

32

Voltage

V

SDA, SCL, REGN, PSYS, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ,

LODRV1, LODRV2, VDDA, COMP2, CMPIN, CMPOUT,OTG/VAP/FRS

0

6.5

PROCHOT

0

5.3

3.3

IADPT, IBAT, COMP1

BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2

SRP-SRN, ACP-ACN

0

6.5

Differential

Voltage

–0.5

0

0.5

V

BATDRV-VSYS

10.8

8

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8.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

–20

NOM

MAX

125

85

UNIT

Junction temperature range, T_J

Temperature

°C

Storage temperature, T_stg

8.4 Thermal Information

BQ25730

THERMAL METRIC⁽¹⁾

RSN (WQFN)

UNIT

32 PINS

37.2

26.1

7.8

R_θJA

Junction-to-ambient thermal resistance (JEDEC⁽¹⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

)

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Ψ_JB

7.8

R_θJC(bot)

2.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics(BQ25730)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

Input voltage

operating range

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{INPUT_OP}

3.5

26

V

MAX SYSTEM VOLTAGE REGULATION

System Voltage

Regulation, measured

on V_SYS(charge

disabled)

V_{SYSMAX_RNG}

1.024

–2%

23.15

V

System voltage

regulation accuracy

(charge disabled and

OOA disabled)

V_SRN

150 mV

+

V_{SYSMAX_ACC}

REG0x05/04() = 0x5208H (21.000 V)

2%

V_SRN

150 mV

+

V

REG0x05/04() = 0x41A0H (16.800 V)

REG0x05/04() = 0x3138H (12.600 V)

REG0x05/04() = 0x20D0H (8.400 V)

REG0x05/04() = 0x1068H (4.200 V)

–2%

–3%

1.00

2%

V_SRN

150 mV

+

System voltage

regulation accuracy

V_{SYSMAX_ACC}

(charge disabled and

V_SRN

150 mV

+

EN_OOA=0b)

3%

V_SRN

150 mV

+

3%

MINIMUM SYSTEM VOLTAGE REGULATION

System Voltage

Regulation, measured

on V_SYS

V_{SYS_MIN_RNG}

23.00

V

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Minimum System

15.40

V

Voltage Regulation

Accuracy (VBAT

below REG0x3E()

setting,OOA disabled)

V_{SYS_MIN_REG_ACC}

REG0x0D/0C() = 0x9A00H

–2%

12.30

9.20

6.60

3.60

V

–2%

V

REG0x0D/0C() = 0x7B00H

REG0x0D/0C() = 0x5C00H

REG0x0D/0C() = 0x4200H

REG0x0D/0C() = 0x2400H

–2%

–3%

Minimum System

Voltage Regulation

Accuracy (VBAT

below REG0x0D/0C()

setting, EN_OOA=0b)

–2%

V

V_{SYS_MIN_REG_ACC}

–3%

V

–3%

CHARGE VOLTAGE REGULATION

Battery voltage

V_{BAT_RNG}

regulation

1.024

23.00

0.5%

V

Battery voltage

regulation accuracy

(0°C to 85°C)

21

V_{BAT_REG_ACC}

REG0x05/04() = 0x5208H

–0.5%

16.8

12.6

8.4

V

REG0x05/04() = 0x41A0H

REG0x05/04() = 0x3138H

REG0x05/04() = 0x20D0H

REG0x05/04() = 0x1068H

–0.5%

–0.6%

–1.1%

0.5%

Battery voltage

regulation accuracy

(0°C to 85°C)

V_{BAT_REG_ACC}

0.6%

4.2

1.45%

CHARGE CURRENT REGULATION IN FAST CHARGE

Charge current

V_{IREG_CHG_RNG}

regulation differential V_{IREG_CHG}= V_SRP– V_SRN

0

81.28 mV

voltage range

8192

4096

2048

1024

mA

3.0%

REG0x03/02() = 0x1000H

REG0x03/02() = 0x0800H

REG0x03/02() = 0x0400H

REG0x03/02() = 0x0200H

–3.0%

–5.0%

–12%

–18%

Charge current

mA

regulation accuracy

5-mΩ R_SRsensing

resistor, VBAT above

VSYS_MIN(Reg0x0D

/0C)setting(0°C to

85°C)

6.0%

I_{CHRG_REG_ACC}

mA

13.5%

mA

21.5%

CHARGE CURRENT REGULATION IN LDO MODE

CELL(≥2 S),VSRN < VSYS_MIN

384

2

mA

A

Pre-charge current

clamp under low

battery voltage

I_CLAMP

CELL 1 S, VSRN < 3 V

CELL 1 S, 3 V < VSRN < VSYS_MIN

10

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REG0x03/02() = 0x00C0H

384

mA

Pre-charge current

regulation accuracy

with 5-mΩ R_SR

resistor, VBAT

below REG0x0D/0C()

setting (0°C to 85°C)

≥2S

–25.0%

–50.0%

25.0%

50.0%

mA

I_{PRECHRG_REG_ACC}

1S

REG0x03/02() = 0x0080H

≥2S

256

–30.0%

–13.5

30.0%

SRP, SRN leakage

current mismatch

(0°C to 85°C)

I_{LEAK_SRP_SRN}

10.0 µA

INPUT CURRENT REGULATION

Input current

regulation differential

V_{IREG_DPM_RNG}

voltage range with

10-mΩ R_ACsensing

resistor

V_{IREG_DPM}= V_ACP– V_ACN

0.5

64 mV

REG0x0F/0E() = 0x4E00H

REG0x0F/0E() = 0x3A00H

REG0x0F/0E() = 0x1C00H

REG0x0F/0E() = 0x0800H

7600

5600

2600

600

7800

5800

2800

800

8000 mA

6000 mA

3000 mA

1000 mA

Input current

regulation accuracy

(-40°C to 105°C) with

5-mΩ R_ACsensing

resistor

I_{IIN_DPM_REG_ACC}

ACP, ACN leakage

current mismatch

I_{LEAK_ACP_ACN}

–16

10 µA

Voltage range

for input current

regulation (ILIM_HIZ

Pin)

V_{IREG_DPM_RNG_ILIM}

1.15

4

V

Input Current

Regulation Accuracy

on ILIM_HIZ pin

V_{ILIM_HIZ}= 2.6 V

V_{ILIM_HIZ}= 2.2 V

V_{ILIM_HIZ}= 1.6 V

7600

5600

2600

8000

6000

3000

8400 mA

6400 mA

3400 mA

I_{IIN_DPM_REG_ACC_ILIM}V_{ILIM_HIZ}= 1 V + 40

× I_DPM× R_AC, with

5-mΩ R_ACsensing

resistor

V_{ILIM_HIZ}= 1.2 V

600

–1

1000

1400 mA

ILIM_HIZ pin leakage

current

I_{LEAK_ILIM}

1

µA

INPUT VOLTAGE REGULATION

Input voltage

V_{DPM_RNG}

Voltage on VBUS

3.2

19.52

V

regulation range

REG0x0B/0A()=0x3C80H

18688

10880

4480

mV

–3.5%

–4.5%

–8%

2%

3%

REG0x0B/0A()=0x1E00H

REG0x0B/0A()=0x0500H

mV

Input voltage

V_{DPM_REG_ACC}

regulation accuracy

5.5%

OTG CURRENT REGULATION

OTG output current

V_{IOTG_REG_RNG}

regulation differential V_{IOTG_REG}= V_ACP– V_ACN

voltage range

0

81.28 mV

OTG output current

regulation accuracy

with 100-mA LSB

and 5-mΩ R_ACseries

resistor

REG0x09/08() = 0x3C00H

REG0x09/08() = 0x1E00H

5600

2600

6000

3000

6400 mA

3400 mA

I_{OTG_ACC}

REG0x09/08() = 0x0A00H

600

1000

1400 mA

OTG VOLTAGE REGULATION

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OTG voltage

V_{OTG_REG_RNG}

regulation range(OOA Voltage on VBUS

disabled)

3

24.00

V

REG0x07/06()=0x2CECH

23.00

12.00

5.00

–2%

–4%

2%

OTG voltage

regulation

accuracy(OOA

disabled)

REG0x07/06()=0x1770H

REG0x07/06()=0x09C4H

V

V_{OTG_REG_ACC}

3.5%

REGN REGULATOR

REGN regulator

voltage (0 mA – 60

mA)

V_{REGN_REG}

V_VBUS= 10 V

5.7

3.8

50

6

4.3

65

6.3

4.6

V

REGN voltage in drop

out mode

V_DROPOUT

V_VBUS= 5 V, I_LOAD= 20 mA

V_VBUS= 10 V, force V_REGN=4 V

REGN current limit

when converter is

enabled

I_{REGN_LIM}

mA

QUIESCENT CURRENT

VBAT = 18 V, REG0x01[7] = 1,REG0x31[6] = 0b, in

low-power mode, Disable PSYS

22

35

45 µA

60 µA

VBAT = 18 V, REG0x01[7] = 1, REG0x31[6] =

1b, REG0x31[5:4] = 11b,REGN off, Disable PSYS,

Enable low power PROCHOT

System powered by

battery. BATFET on.

I_SRN+ I_SRP+ I_SW2

I_BTST2+ I_SW1+ I_BTST1

+ I_ACP+ I_ACN+ I_VBUS

+ I_VSYS

+

I_{BAT_BATFET_ON}

VBAT = 18 V, REG0x01[7]= 0,REG0x31[5:4]= 11b,

REGN on, Disable PSYS, In performance mode

880

980

1170 µA

1270 µA

VBAT = 18 V, REG0x01[7] = 0, REG0x31[5:4]

= 00b, REGN on, Enable PSYS, In performance

mode

Input current during

PFM in buck mode,

no load, I_VBUS+ I_ACPVIN = 20 V, VBAT = 12.6 V, 3s, REG0x01[2] = 0;

+ I_ACN+ I_VSYS+ I_SRPMOSFET Qg = 4 nC

+ I_SRN+ I_SW1+ I_BTST

I_{AC_SW_LIGHT_buck}

I_{AC_SW_LIGHT_boost}

I_{AC_SW_LIGHT_buckboost}

2.2

2.7

2.4

mA

+ I_SW2+ I_BTST2

Input current during

PFM in boost mode,

no load, I_VBUS+ I_ACPVIN = 5 V, VBAT = 8.4 V, 2s, REG0x01[2] = 0;

+ I_ACN+ I_VSYS+ I_SRPMOSFET Qg = 4 nC

+ I_SRN+ I_SW1+ I_BTST2

+ I_SW2+ I_BTST2

Input current during

PFM in buck boost

mode, no load, I_VBUSVIN = 12 V, VBAT = 12 V, REG0x01[2] = 0;

+ I_ACP+ I_ACN+ I_VSYSMOSFET Qg = 4 nC

+ I_SRP+ I_SRN+ I_SW1

+

I_BTST1+ I_SW2+ I_BTST2

Quiescent current

during PFM in OTG

mode, EN_OOA=0b,

VBAT = 8.4 V, VBUS = 5 V, 800 kHz switching

frequency, MOSFET Qg = 4nC

3

4.2

6.2

mA

VBAT = 8.4 V, VBUS = 12 V, 800 kHz switching

frequency, MOSFET Qg = 4nC

I_{OTG_STANDBY}

I_VBUS+ I_ACP+ I_ACN

I_VSYS+ I_SRP+ I_SRN

+

VBAT = 8.4 V, VBUS = 20 V, 800 kHz switching

frequency, MOSFET Qg = 4nC

I_SW1+ I_BTST2+ I_SW2

I_BTST2

+

CURRENT SENSE AMPLIFIER

12

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input common mode

range

V_{ACP_ACN_OP}

Voltage on ACP/ACN

3.8

26

V

I_ADPToutput clamp

voltage

V_{IADPT_CLAMP}

I_IADPT

3.1

3.2

3.3

1

I_ADPToutput current

mA

V/V

V_(IADPT)/ V_(ACP-ACN), REG0x00[4] = 0

V_(IADPT)/ V_(ACP-ACN), REG0x00[4] = 1

V_(ACP-ACN)= 40.96 mV

20

40

Input current sensing

gain

A_IADPT

–2%

–3%

2%

3%

V_(ACP-ACN)= 20.48 mV

Input current monitor

accuracy

V_{IADPT_ACC}

V_(ACP-ACN)=10.24 mV

–6%

6%

V_(ACP-ACN)= 5.12 mV

–10%

10%

Maximum

C_{IADPT_MAX}

capacitance at IADPT

100 pF

Battery common

mode range

V_{SRP_SRN_OP}

Voltage on SRP/SRN

2.5

23.15

V

IBAT output clamp

voltage

V_{IBAT_CLAMP}

I_IBAT

3.05

3.2

3.3

1

IBAT output current

mA

V/V

Charge and

V_(IBAT)/ V_(SRN-SRP), REG0x00[3] = 0,

V_(IBAT)/ V_(SRN-SRP), REG0x00[3] = 1,

8

discharge current

sensing gain on IBAT

A_IBAT

16

V/V

V_(SRN-SRP)= 40.96 mV

V_(SRN-SRP)= 20.48 mV

V_(SRN-SRP)=10.24 mV

V_(SRN-SRP)= 5.12 mV

–2%

–4%

2%

4%

Charge and

discharge current

monitor accuracy on

IBAT pin

I_{IBAT_CHG_ACC}

–7%

7%

–15%

15%

Maximum

C_{IBAT_MAX}

capacitance at IBAT

100 pF

SYSTEM POWER SENSE AMPLIFIER

PSYS output voltage

range

V_PSYS

0

3.3

V

I_PSYS

PSYS output current

PSYS system gain

160 µA

µA/W

4%

I_(PSYS)/ (P_(IN)+P_(BAT)), REG0x31[5:4] =

00b;REG0x31[1] = 1b

A_PSYS

1

I_(PSYS)/ P_(IN), REG0x31[5:4]= 01b;REG0x31[1] = 1b

Adapter only with system power = 19.5 V / 45 W, TA

= 0 to 85°C

–4%

–3%

PSYS gain accuracy

(REG0x30[13:12] =

00b)

Battery only with system power = 11 V / 44 W, TA =

0 to 85°C

3%

4%

V_{PSYS_ACC}

PSYS gain accuracy

(REG0x30[13:12] =

01b)

Adapter only with system power = 19.5 V / 45 W, TA

= 0 to 85°C

–4%

3

V_{PSYS_CLAMP}

PSYS clamp voltage

3.3

V

VSYS UNDER VOLTAGE LOCKOUT COMPARATOR

VSYS undervoltage

rising threshold(≥1S)

V_{SYS_UVLOZ}

V_{SYS_UVLO}

VSYS rising

2.3

2.2

2.5

2.4

2.65

2.55

V

VSYS undervoltage

falling threshold(≥1S)

VSYS falling REG3D[7:5]=000b

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

VSYS undervoltage

hysteresis(≥1S)

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{SYS_UVLO_HYST}

100

mV

VBUS UNDER VOLTAGE LOCKOUT COMPARATOR

VBUS undervoltage

rising threshold

V_{VBUS_UVLOZ}

V_{VBUS_UVLO}

VBUS rising

2.35

2.2

2.55

2.4

2.80

2.6

V

VBUS undervoltage

falling threshold

VBUS falling

VBUS undervoltage

hysteresis

V_{VBUS_UVLO_HYST}

150

mV

VBUS converter

enable rising

threshold

V_{VBUS_CONVEN}

VBUS rising

VBUS falling

3.2

2.9

3.5

3.9

3.5

V

VBUS converter

enable falling

threshold

V_{VBUS_CONVENZ}

3.2

V

VBUS converter

enable hysteresis

V_{VBUS_CONVEN_HYST}

300

mV

BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR

VBAT undervoltage

rising threshold

V_{VBAT_UVLOZ}

VSRN rising

VSRN falling

2.35

2.2

2.55

2.4

2.80

2.6

V

VBAT undervoltage

falling threshold

V_{VBAT_UVLO}

VBAT undervoltage

hysteresis

V_{VBAT_UVLO_HYST}

V_{VBAT_OTGEN}

V_{VBAT_OTGENZ}

V_{VBAT_OTGEN_HYST}

150

3.55

2.4

mV

V

VBAT OTG enable

rising threshold

VSRN rising

VSRN falling

3.25

2.15

3.85

2.65

VBAT OTG enable

falling threshold

V

VBAT OTG enable

hysteresis

1150

mV

VBUS UNDER VOLTAGE COMPARATOR (OTG MODE)

VBUS undervoltage

falling threshold

V_{VBUS_OTG_UV}

t_{VBUS_OTG_UV}

As percentage of REG0x07/06()

85%

7

VBUS time

undervoltage deglitch

ms

VBUS OVER VOLTAGE COMPARATOR (OTG MODE)

VBUS overvoltage

V_{VBUS_OTG_OV}

t_{VBUS_OTG_OV}

As percentage of REG0x07/06()

110%

10

rising threshold

VBUS Time

Overvoltage Deglitch

PRE-CHARGE to FAST CHARGE TRANSITION(For ≥2S)

LDO mode to

fast charge mode

threshold, VSRN

rising

V_{BAT_VSYS_MIN_RISE}

as percentage of 0x0D/0C()

98%

100%

102%

LDO mode to

fast charge mode

threshold, VSRN

falling

V_{BAT_VSYS_MIN_FALL}

as percentage of 0x0D/0C()

97.5%

2.5%

Fast charge mode to

LDO mode threshold as percentage of 0x0D/0C()

hysteresis

V_{BAT_VSYS_MIN_HYST}

BATTERY LOW VOLTAGE COMPARATOR (Pre-charge to Fast Charge Threshold for 1S)

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

BATLOWV falling

threshold

V_{BATLV_FALL}

2.8

V

BATLOWV rising

threshold

V_{BATLV_RISE}

3

V

V_{BATLV_RHYST}

BATLOWV hysteresis

200

mV

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

VBUS overvoltage

rising threshold

V_{VBUSOV_RISE}

VBUS rising

VBUS falling

26.0

25.0

26.8

25.8

1.0

100

1

27.7

26.7

V

VBUS overvoltage

falling threshold

V_{VBUSOV_FALL}

VBUS overvoltage

hysteresis

V_{VBUSOV_HYST}

t_{VBUSOV_RISE_DEG}

t_{VBUSOV_FALL_DEG}

V

VBUS deglitch

overvoltage rising

VBUS converter rising to stop converter

VBUS converter falling to start converter

us

ms

VBUS deglitch

overvoltage falling

INPUT OVER CURRENT COMPARATOR (ACOC)

ACP to ACN

rising threshold, w.r.t.

ILIM2_VTH

Voltage across input sense resistor rising,

Reg0x32[2]= 1

V_ACOC

180%

200%

220%

Measure between

ACP and ACN

V_{ACOC_FLOOR}

V_{ACOC_CEILING}

Set IIN_DPM to minimum

Set IIN_DPM to maximum

44

50

56 mV

Measure between

ACP and ACN

172

180

188 mV

t_{ACOC_DEG_RISE}

t_{ACOC_RELAX}

Rising deglitch time

Relax time

Deglitch time to trigger ACOC

250

us

Relax time before converter starts again

ms

SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP)

1 s

5.8

11.7

19

6

12

6.1

12.2

20

V

2 s

System overvoltage

V_{SYSOVP_RISE}

rising threshold to

turnoff converter

3 s

4 s

5 s

1 s

2 s

3 s

4 s

5 s

19.5

25

19

20

24

26

5.5

11.7

19.3

24.5

System overvoltage

falling threshold

V_{SYSOVP_FALL}

Discharge current

when SYSOVP

stop switching was

triggered

I_SYSOVP

on VSYS pin

20

mA

BAT OVER-VOLTAGE COMPARATOR (BATOVP)

Overvoltage rising

threshold as

percentage of

VBAT_REG in

REG0x05/04h()

1 s

102.3%

104%

106%

105%

V_{BATOVP_RISE}

≥2 s

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Overvoltage falling

1 s

100%

102%

104%

threshold as

V_{BATOVP_FALL}

percentage of

VBAT_REG in

REG0x05/04h()

≥2 s

1 s

100%

102%

2%

103%

Overvoltage

hysteresis as

percentage of

VBAT_REG in

REG0x05/04h()

V_{BATOVP_HYST}

≥2 s

2%

Discharge current

during BATOVP

I_BATOVP

Discharge current through VSYS pin

20

mA

CONVERTER OVER-CURRENT COMPARATOR (Q2)

Converter Over-

Reg0x32[5]=1b

150

210

mV

Current Limit across

Q2 MOSFET drain to

source voltage

V_{OCP_lim_Q2}

Reg0x32[5]=0b

Reg0x32[5]=1b

Reg0x32[5]=0b

45

60

mV

System Short or SRN

< 2.4 V

V_{OCP_lim_SYSSHRT_Q2}

CONVERTER OVER-CURRENT COMPARATOR (ACX)

Reg0x32[4]=1b; RSNS_RAC=0b

150

100

280

200

90

mV

Converter Over-

Current Limit across

ACP-ACN input

current sensing

resistor

Reg0x32[4]=1b; RSNS_RAC=1b

Reg0x32[4]=0b;RSNS_RAC=0b

Reg0x32[4]=0b; RSNS_RAC=1b

Reg0x32[4]=1b;RSNS_RAC=0b

Reg0x32[4]=1b;RSNS_RAC=1b

Reg0x32[4]=0b;RSNS_RAC=0b

Reg0x32[4]=0b;RSNS_RAC=1b

V_{OCP_lim_ACX}

60

System Short or SRN

< 2.4 V

V_{OCP_lim_SYSSHRT_ACX}

150

120

THERMAL SHUTDOWN COMPARATOR

Thermal shutdown

T_{SHUT_RISE}

Temperature increasing

Temperature reducing

155

135

20

°C

us

rising temperature

Thermal shutdown

T_{SHUTF_FALL}

falling temperature

Thermal shutdown

T_{SHUT_HYS}

hysteresis

Thermal deglitch

t_{SHUT_RDEG}

100

12

shutdown rising

Thermal deglitch

t_{SHUT_FHYS}

ms

shutdown falling

ICRIT PROCHOT COMPARATOR

Input current rising

threshold for throttling

as 10% above

ILIM2_VTH

INOM PROCHOT COMPARATOR

INOM rising threshold

I_{ICRIT_PRO}

Only when ILIM2 setting is higher than 2A

105%

96%

110%

117%

116%

I_{INOM_PRO}

as 10% above

IIN_DPM

110%

BATTERY DISCHARGE CURRENT LIMIT PROCHOT COMPARATOR(IDCHG)

16.384

A

IDCHG threshold1 for Reg0x39[7:2]=010000b, with 5mΩ R_SRcurrent

I_{DCHG_TH1}

throttling CPU

sensing resistor

103%

16

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

IDCHG threshold1

deglitch time

I_{DCHG_DEG1}

I_{DCHG_TH2}

t_{DCHG_DEG2}

Reg0x39h[1:0]=01b

1.25

sec

IDCHG threshold2 for

throttling for IDSCHG

of 6 A

24.576

A

Reg0x39[7:2]=010000b 3C[5:3]=001b,with 5mΩ

R_SRcurrent sensing resistor

96%

103%

IDCHG threshold2

deglitch time

Reg0x3C[7:6]=01b

1.6

ms

INDEPENDENT COMPARATOR

Reg0x30h[7]= 1, CMPIN falling

Reg0x30h[7]= 0, CMPIN falling

1.17

2.27

1.2

2.3

1.23

2.33

V

Independent

V_{INDEP_CMP}

comparator threshold

Independent

comparator

hysteresis

V_{INDEP_CMP_HYS}

CMPIN falling

100

mV

POWER MOSFET DRIVER

PWM OSCILLATOR AND RAMP

Reg0x01[1] = 0

Reg0x01[1] = 1

680

340

800

400

920 kHz

460 kHz

PWM switching

frequency

F_SW

BATFET GATE DRIVER (BATDRV)

Gate drive voltage on

BATFET

V_{BATDRV_ON}

8.5

10

30

11.5

V

Drain-source voltage

on BATFET during

ideal diode operation

V_{BATDRV_DIODE}

mV

Measured by

R_{BATDRV_ON}

sourcing 10 µA

current to BATDRV

3

4

6

kΩ

Measured by sinking

10 µA current from

BATDRV

R_{BATDRV_OFF}

1.2

2.1 kΩ

PWM HIGH SIDE DRIVER (HIDRV Q1)

The resistance of the

R_{DS_HI_ON_Q1}

R_{DS_HI_OFF_Q1}

V_{BTST1_REFRESH}

gate driver loop for

turning on Q1

V_BTST1- V_SW1= 5 V

6

1.3

3.7

Ω

The resistance of the

gate driver loop for

turning off Q1

V_BTST1- V_SW1= 5 V

2.2

4.6

Ω

V

Bootstrap refresh

comparator falling

threshold voltage

V_BTST1- V_SW1when low-side refresh pulse is

requested

3.2

PWM HIGH SIDE DRIVER (HIDRV Q4)

The resistance of the

R_{DS_HI_ON_Q4}

R_{DS_HI_OFF_Q4}

V_{BTST2_REFRESH}

gate driver loop for

turning on Q4

V_BTST2- V_SW2= 5 V

6

1.5

3.7

Ω

V

The resistance of the

gate driver loop for

turning off Q4

V_BTST2- V_SW2= 5 V

2.4

4.6

Bootstrap refresh

comparator falling

threshold voltage

V_BTST2- V_SW2when low-side refresh pulse is

requested

3.3

PWM LOW SIDE DRIVER (LODRV Q2)

The resistance of the

R_{DS_LO_ON_Q2}

gate driver loop for

turning on Q2

V_BTST1- V_SW1= 5.5 V

6

Ω

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_BTST1- V_SW1= 5.5 V

MIN

TYP

MAX UNIT

The resistance of the

gate driver loop for

turning off Q2

R_{DS_LO_OFF_Q2}

1.7

2.6

Ω

PWM LOW SIDE DRIVER (LODRV Q3)

The resistance of the

R_{DS_LO_ON_Q3}

gate driver loop for

turning on Q3

V_BTST2- V_SW2= 5.5 V

6.8

2.2

Ω

The resistance of the

gate driver loop for

turning off Q3

R_{DS_LO_OFF_Q3}

V_BTST2- V_SW2= 5.5 V

4.6

INTERNAL SOFT START During Charge Enable

Charge current soft-

SS_{STEP_SIZE}

64

8

mA

us

start step size

Charge current soft-

SS_{STEP_TIME}

start duration time for

each step

INTEGRATED BTST DIODE (D1)

V_{F_D1}Forward bias voltage IF = 20 mA at 25°C

0.8

V

Reverse breakdown

voltage

V_{R_D1}

IR = 2 µA at 25°C

20

INTEGRATED BTST DIODE (D2)

V_{F_D2}

Forward bias voltage IF = 20 mA at 25°C

V

Reverse breakdown

IR = 2 µA at 25°C

voltage

V_{R_D2}

20

INTERFACE

LOGIC INPUT (SDA, SCL)

V_{IN_ LO}Input low threshold

V_{IN_ HI}Input high threshold

I²C

0.4

V

1.3

LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)

Output saturation

voltage

V_{OUT_ LO}

5 mA drain current

Voltage = 7 V

0.4

1

V

V_{OUT_ LEAK}

Leakage current

–1

µA

LOGIC INPUT (OTG/VAP/FRS pin)

V_{IN_ LO_OTG}Input low threshold

V_{IN_ HI_OTG}Input high threshold

0.4

V

1.3

LOGIC OUTPUT OPEN DRAIN SDA

Output Saturation

Voltage

V_{OUT_ LO_SDA}

V_{OUT_ LEAK_SDA}

5 mA drain current

Voltage = 7 V

0.4

1

V

Leakage Current

–1

µA

LOGIC OUTPUT OPEN DRAIN CHRG_OK

Output Saturation

V_{OUT_ LO_CHRG_OK}

5 mA drain current

Voltage = 7 V

0.4

1

V

Voltage

V_{OUT_ LEAK _CHRG_OK}Leakage Current

µA

LOGIC OUTPUT OPEN DRAIN CMPOUT

Output Saturation

V_{OUT_ LO_CMPOUT}

5 mA drain current

Voltage = 7 V

0.4

1

V

Voltage

V_{OUT_ LEAK _CMPOUT}

Leakage Current

µA

LOGIC OUTPUT OPEN DRAIN (PROCHOT)

18

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8.5 Electrical Characteristics(BQ25730) (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUSOV_FALL}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output saturation

V_{OUT_ LO_PROCHOT}

50 Ω pullup to 1.05 V / 5-mA

300 mV

voltage

V_{OUT_ LEAK_PROCHOT}Leakage current

ANALOG INPUT (ILIM_HIZ)

Voltage = 5.5 V

–1

1

µA

Voltage to get out of

HIZ mode

V_{HIZ_ LO}

ILIM_HIZ pin rising

ILIM_HIZ pin falling

0.8

V

Voltage to enable HIZ

mode

V_{HIZ_ HIGH}

0.4

ANALOG INPUT (CELL_BATPRESZ)

CELL_BATPRESZ pin voltage as percentage of

REGN = 6 V

V_{CELL_5S}

V_{CELL_4S}

V_{CELL_3S}

V_{CELL_2S}

V_{CELL_1S}

5s

90%

68.4%

51.7%

35%

100%

75%

55%

40%

25%

CELL_BATPRESZ pin voltage as percentage of

REGN = 6 V

4s setting

3s setting

2s setting

1s setting

81.5%

65%

CELL_BATPRESZ pin voltage as percentage of

REGN = 6 V

CELL_BATPRESZ pin voltage as percentage of

REGN = 6 V

48.5%

31.6%

CELL_BATPRESZ pin voltage as percentage of

REGN = 6 V

18.4%

18%

V_{CELL_BATPRESZ_RISE}Battery is present

V_{CELL_BATPRESZ_FALL}Battery is removed

ANALOG INPUT (COMP1, COMP2)

CELL_BATPRESZ rising

CELL_BATPRESZ falling

15%

I_{LEAK_COMP1}

I_{LEAK_COMP2}

COMP1 Leakage

COMP2 Leakage

–120

120 nA

8.6 Timing Requirements

MIN

NOM

MAX

UNIT

I²C TIMING CHARACTERISTICS

t_r

SCL/SDA rise time

SCL/SDA fall time

SCL pulse width high

SCL pulse width low

300

50

ns

µs

ns

µs

kHz

t_f

t_HIGH

t_LOW

t_SU:STA

t_HD:STA

t_SU:DAT

t_HD:DAT

t_SU:STO

t_BUF

0.6

1.3

0.6

100

300

0.6

1.3

10

Setup time for START condition

Start condition hold time after which first clock pulse is generated

Data setup time

Data hold time

Set up time for STOP condition

Bus free time between START and STOP conditions

Clock frequency

f_SCL

400

35

HOST COMMUNICATION FAILURE

t_TIMEOUT

t_BOOT

I²C bus release timeout⁽¹⁾

25

10

4

ms

s

Deglitch for watchdog reset signal

Watchdog timeout period, REG0x01[6:5]=01

Watchdog timeout period, REG0x01[6:5]=10

Watchdog timeout period, REG0x01[6:5]=11

5.5

88

7

105

210

t_WDI

70

140

s

175

s

(1) Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected

a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a host and a target must

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adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a host (10 ms) and a target (25

ms).

20

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8.7 Typical Characteristics

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

VOUT=4.2V

VOUT=8.4V

VOUT=12.6V

VOUT=16.8V

VOUT=21.0V

VOUT=4.2V

VOUT=8.4V

VOUT=12.6V

VOUT=16.8V

VOUT=21.0V

0

0.01

0.02

0.03

0.04

0.05

0

0.01

0.02

0.03

0.04

0.05

Output Current(A)

VIN = 5 V

R_AC=5mΩ

PFM mode

R_SR=5mΩ

VOUT=System Voltage

Inductance=4.7uH

VIN = 9 V

R_AC=5mΩ

PFM mode

R_SR=5mΩ

VOUT=System Voltage

Inductance=4.7uH

Figure 8-1. Light Load System Efficiency

Figure 8-2. Light Load System Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

45

40

VOUT=4.2V

VOUT=8.4V

VOUT=12.6V

VOUT=16.8V

VOUT=21.0V

VOUT=8.4V

VOUT=12.6V

VOUT=16.8V

VOUT=21.0V

0

0.01

0.02

0.03

0.04

0.05

0

0.01

0.02

0.03

0.04

0.05

Output Current(A)

VIN = 15 V

R_AC=5mΩ

PFM mode

R_SR=5mΩ

VOUT=System Voltage

Inductance=4.7uH

VIN = 20 V

R_AC=5mΩ

PFM mode

R_SR=5mΩ

VOUT=System Voltage

Inductance=4.7uH

Figure 8-3. Light Load System Efficiency

Figure 8-4. Light Load System Efficiency

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8.7 Typical Characteristics (continued)

100

98

96

94

92

90

88

100

98

96

94

92

90

88

86

84

82

VOUT=3.7V

86

84

82

VOUT=7.4V

VOUT=11.1V

VOUT=14.8V

VOUT=18.5V

VOUT=7.4V

VOUT=11.1V

VOUT=14.8V

VOUT=18.5V

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10 11 12

Output Current(A)

VIN = 5 V

CCM

Fs=400kHz

R_SR=5mΩ

VOUT=System Voltage

VIN = 9 V

CCM

Fs=400kHz

R_SR=5mΩ

VOUT=System Voltage

R_AC=5mΩ

Inductance=4.7uH

R_AC=5mΩ

Inductance=4.7uH

Figure 8-5. System Efficiency

Figure 8-6. System Efficiency

100

98

96

94

92

90

88

86

84

82

100

98

96

94

92

90

88

86

84

82

VOUT=3.7V

VOUT=7.4V

VOUT=11.1V

VOUT=14.8V

VOUT=18.5V

VOUT=3.7V

VOUT=7.4V

VOUT=11.1V

VOUT=14.8V

VOUT=18.5V

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10 11 12

Output Current(A)

VIN = 15 V

CCM

Fs=400kHz

R_SR=5mΩ

VOUT=System Voltage

VIN = 20 V

CCM

Fs=400kHz

R_SR=5mΩ

VOUT=System Voltage

R_AC=5mΩ

Inductance=4.7uH

R_AC=5mΩ

Inductance=4.7uH

Figure 8-7. System Efficiency

Figure 8-8. System Efficiency

22

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8.7 Typical Characteristics (continued)

100

98

96

94

92

90

88

100

98

96

94

92

90

88

86

84

82

VOUT=3.7V

86

84

82

VOUT=7.4V

VOUT=11.1V

VOUT=14.8V

VOUT=18.5V

VOTG=5V

VOTG=9V

VOTG=15V

VOTG=20V

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

Output Current(A)

PTM Mode

R_SR=5mΩ

VOUT=System Voltage

Inductance=4.7uH

VBAT= 4 V

R_AC=5mΩ

CCM Fs=400kHz

R_AC=5mΩ

R_SR=5mΩ Inductance=4.7uH

Figure 8-9. PTM Mode System Efficiency

Figure 8-10. OTG Efficiency with 1S Battery

100

98

96

94

92

90

88

86

84

82

100

98

96

94

92

90

88

86

84

82

VOTG=5V

VOTG=9V

VOTG=15V

VOTG=20V

VOTG=9V

VOTG=15V

VOTG=20V

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

Output Current(A)

VBAT= 8 V

R_AC=5mΩ

CCM Fs=400kHz

VBAT= 12 V

R_AC=5mΩ

CCM Fs=400kHz

R_SR=5mΩ Inductance=4.7uH

Figure 8-11. OTG Efficiency with 2S Battery

Figure 8-12. OTG Efficiency with 3S Battery

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8.7 Typical Characteristics (continued)

100

98

96

94

92

90

88

100

98

96

94

92

90

88

86

84

82

86

84

82

VOTG=5V

VOTG=9V

VOTG=15V

VOTG=20V

VOTG=5V

VOTG=9V

VOTG=15V

VOTG=20V

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

Output Current(A)

VBAT= 16 V

R_AC=5mΩ

CCM Fs=400kHz

VBAT= 20 V

R_AC=5mΩ

CCM Fs=400kHz

R_SR=5mΩ Inductance=4.7uH

Figure 8-13. OTG Efficiency with 4S Battery

Figure 8-14. OTG Efficiency with 5S Battery

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9 Detailed Description

9.1 Overview

The BQ25730 is a narrow VDC buck-boost charger controller for oxygen concentrator, ventilator, and portable

electronics such as tablet and other mobile devices with rechargeable batteries. It provides seamless transition

between different converter operation modes (buck, boost, or buck-boost), fast transient response, and high light

load efficiency.

The BQ25730 supports a wide range of power sources, including USB-C PD ports, legacy USB ports, traditional

AC-DC adapters, and so forth. It takes input voltage from 3.5 V to 26 V and charges a battery of 1 to 5 cells in

series. In the absence of an input source, the BQ25730 supports the USB On-the-Go (OTG) function from a 1- to

5-cell battery to generate an adjustable 3 V to 24 V at the USB port with 8-mV resolution.

The BQ25730 features Dynamic Power Management (DPM) to limit input power and avoid AC adapter

overloading. During battery charging, as system power increases, charging current is reduced to maintain total

input current below adapter rating. If system power demand temporarily exceeds adapter rating, the BQ25730

supports the NVDC architecture to allow battery discharge energy to supplement system power.

The latest version of the USB-C PD specification includes Fast Role Swap (FRS) to ensure power role swapping

occurs in a timely fashion so that the device(s) connected to the dock never experience momentary power loss

or glitching. The device integrates FRS with compliance to the USB-C PD specification.

The TI patented switching frequency dithering pattern can significantly reduce EMI noise over the entire

conductive EMI frequency range (150 kHz to 30 MHz). Multiple dithering scale options are available to provide

flexibility for different applications to simplify EMI noise filter design.

The I²C host controls input current, charge current, and charge voltage registers with high resolution, high

accuracy regulation limits.

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9.2 Functional Block Diagram

4

CHRG_OK

CHRG_OK_DRV

50ms Rising

Deglitch

Block Diagram

** programmable in register

EN_REGN

50ms Rising

Deglitch

3.5V

1

VBUS

VREF_CMP**

CMP_DEG**

14

15

CMPIN

ACOV

26.8V

CMPOUT

VREF_VINDPM or VREF_VOTG

COMP1

COMP2

16

17

VDDA

VSNS_VINDPM or VSYS_VOTG

EN_HIZ

ILIM_HIZ

VREF_ILIM

6

Decoder

VSYS

VREF_IIN_DPM, or VREF_IOTG

2

3

ACP

ACN

VSNS_IIN_DPM, or VSNS_IOTG

LDO Mode

Gate Control

BATDRV

21

20X/40X

VSYS-10V

20X/40X

VSNS_IOTG

30

31

32

7

BTST1

IADPT

IBAT

HIDRV1

Loop Selector

and

Error Ampli er

8

9

VSNS_IIN

VSNS_ICHG

SW1

VSNS_IDCHG

16X/8X

PWM

VDDA

EN_REGN

REGN

LDO

REGN

VREF_ICHG

VSNS_ICHG

28

EN_HIZ

EN_LEARN

EN_LDO

20

19

SRP

SRN

16X/8X

EN_CHRG

EN_OTG

VREF_VBAT

PWM

Driver

Logic

29

27

25

24

23

LODRV1

PGND

BTST2

HIDRV2

SW2

VSNS_VBAT

VREF_VSYS

22

VSYS

VSNS_VSYS

VSNS_VBAT

ACN

PSYS

(ACP-ACN)

SRN

VSNS_ICHG Over Current

10

VSNS_IDCHG

Over Voltage

(SRN-SRP)

VSNS_IIN_DPM

VSNS_VINDPM

26

LODRV2

Detect

EN_HIZ

I2C

Interface

EN_LEARN

EN_LDO

EN_CHRG

EN_OTG

BATPRESZ

12

SDA

ChargeOp on0()

ChargeOp on1()

ChargeOp on2()

ChargeCurrent()

ChargeVoltage()

InputCurrent()

InputVoltage()

MinSysVoltage()

OTGVoltage()

Decoder

CELL_CONFIG

18

CELL_BATPRESZ

VREF_VSYS

13

5

SCL

VREF_VBAT

VREF_ICHG

Loop

Regula on

Reference

IADPT

IBAT

VREF_IIN_DPM

VREF_VINDPM

VREF_IOTG

OTG/VAP/FRS

Processor

Hot

11

PROCHOT

VSYS

VREF_VOTG

CHRG_OK

OTGCurrent()

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9.3 Feature Description

9.3.1 Power-Up Sequence

The device powers up from the higher voltage of VBUS or VBAT through integrated power selector. The charger

starts POR (power on reset) when VBUS exceeds V_{VBUS_UVLOZ}or VBAT exceeds V_{VBAT_UVLOZ}. 5 ms after either

VBUS or VBAT becomes valid, the charger resets all the registers to the default state. Another 5 ms later, the

user registers become accessible to the host.

Power up sequence when the charger is powered up from VBUS:

•

After VBUS above V_{VBUS_UVLOZ}, enable 6-V LDO REGN pin and VDDA pin voltage increase accordingly.

CHRG_OK pin goes HIGH and the AC_STAT is configured to 1.

After passing VBUS qualification, the REGN voltage is setup. VINDPM is detected in VBUS steady state

voltage and IIN_DPM is detected at ILIM_HIZ pin steady state voltage.

Battery CELL configuration is read at CELL_BATPRESZ pin voltage and compared to VDDA to determine

cell configuration. Corresponding the default value of ChargeVoltage register (REG0x05/04()), ChargeCurrent

register (Reg0x03/02), VSYS_MIN register (Reg0x0D/0C) and SYSOVP threshold are loaded.

Converter powers up.

•

Power up sequence when the charger is powered up from VBAT:

•

If only battery is present and the voltage is above V_{VBAT_UVLOZ}, charger wakes up and the BATFET is turned

on and connecting the battery to system.

By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The

REGN LDO stays off. The Quiescent current is minimized. PROCHOT is available through the independent

comparator by setting EN_PROCHOT_LPWR=1b.

•

The adapter present comparator is activated, to monitor the VBUS voltage.

SDA and SDL lines stand by waiting for host commands.

Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT

buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS, PROCHOT or the independent

comparator also can be enabled by the host.

•

In performance mode, the REGN LDO is always available to provide an accurate reference and gate drive

voltage for the converter.

9.3.2 Two-Level Battery Discharge Current Limit

To prevent the triggering of battery overcurrent protection and avoid battery wear-out, two battery current

limit levels (IDCHG_TH1 and IDCHG_TH2) PROCHOT profiles are recommended to be enabled. Define

IDCHG_TH1 through REG0x39h[7:2], IDCHG_TH2 is set through REG0x3Ch[5:3] for fixed percentage of

IDCHG_TH1. There are dedicated de-glitch time setting registers(IDCHG_DEG1 and IDCHG_DEG2) for both

IDCHG_TH1 and IDCHG_TH2.

•

When battery discharge current is continuously higher than IDCHG_TH1 for more than IDCHG_DEG1 de-

glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH1,

then the time counter resets automatically. STAT_IDCHG1 bit will be set to 1 after PROCHOT is triggered.

Set PP_IDCHG1=1b to enable IDCHG_TH1 for triggering PROCHOT.

•

When battery discharge current is continuously higher than IDCHG_TH2 for more than IDCHG_DEG2 de-

glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH2,

then the time counter resets automatically. STAT_IDCHG2 bit will be set to 1 after PROCHOT is triggered.

Set PP_IDCHG2=1b to enable IDCHG_TH2 for triggering PROCHOT.

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IDCHG_TH2

IDCHG_TH1

0A

/PROCHOT

IDCHG_DEG1

IDCHG_DEG2

Figure 9-1. Two-Level Battery Discharging Current Trigger PROCHOT Diagram

9.3.3 Fast Role Swap Feature

Fast Role Swap (FRS) means charger quickly swaps from power sink role to power source role to provide an

OTG output voltage to accessories when the original power source is disconnected. This feature is defined to

transfer the charger from forward mode to OTG mode quickly without dropping VBUS voltage per USB-C PD

specification requirement.Please contact factory for more detail information about FRS mode.

9.3.4 CHRG_OK Indicator

CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the

following conditions are valid:

•

VBUS is above V_{VBUS_CONVEN}

VBUS is below V_{ACOV_FALL}

No faults triggered such as: SYSOVP/SYSUVP/ACOC/TSHUT/BATOVP/BATOC/force converter off.

9.3.5 Input and Charge Current Sensing

The charger supports 10 mΩ and 5 mΩ for both input current sensing and charge current sensing. By default, 5

mΩ is enabled by POR setting RSNS_RAC=1b and RSNS_RSR=1b, if 10-mΩ sensing is used please configure

RSNS_RAC=0b and RSNS_RSR=0b. Lower current sensing resistor can help improve overall charge efficiency

especially under heavy load. At same time PSYS,IADPT,IBAT pin accuracy and IINDPM/ICHG/IOTG regulation

accuracy get worse due to effective signal reduction in comparison to error signal components.

When RSNS_RAC=RSNS_RSR=0b and 10 mΩ is used for both input and charge current sensing, the pre-

charge current clamp is 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V ), the maximum IIN_HOST setting is

clamped at 6.35 A, and the maximum charge current is clamped at 8.128 A.

When RSNS_RAC=RSNS_RSR=1b and 5 mΩ is used for both input and charge current sensing, the charger

will internally compensate pre-charge current clamp to be 384 mA (2 A for 1S if VSYS_MIN>VBAT>3 V )

under 5-mΩ current sensing which keeps consistent between 10 mΩ and 5 mΩ. Under 5-mΩ current sensing

application charge current range is doubled to 16.256 A. Based on EN_FAST_5MOHM register bit status and

IADPT pin resistor the maximum input current can be configured referring to Table 9-1:

For defined current sense resistors (10 mΩ/5 mΩ), PSYS function is still valid when unsymmetrical input current

sense and charge current sense resistors are used. But RSNS_RAC and RSNS_RSR bit status have to be

consistent with practical resistors used in the system.

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Table 9-1. Maximum Input Current Limit Configuration Table

INDUCTANCE (IADPT Pin

Resistance)

MAXIMUM INPUT CURRENT LIMIT

(IINDPM)

EN_FAST_5MOHM

RSR_RAC BIT

Xb

1b

0b

Xb

RSNS_RAC=0b

RSNS_RAC=1b

RSNS_RAC=0b

RSNS_RAC=1b

6.35 A

10 A

1.0 uH(90.9 kΩ)

1.5 uH(121 kΩ)

2.2 uH(137 kΩ)

6.35 A

10 A

3.3 uH(169 kΩ)

9.3.6 Input Voltage and Current Limit Setup

The actual input current limit being adopted by the device is the lower setting of IIN_DPM and ILIM_HIZ pin.

Register IIN_DPM input current limit setting will reset for below scenarios:

•

When adapter is removed (CHRG_OK is not valid). Note when adapter is removed IIN_HOST will be reset

one time to 3.25 A, under battery only host is still able to overwrite IIN_HOST register with a new value. If the

adapter plug back in and CHRG_OK is pulled up, IIN_HOST will not be reset again.

•

When input current optimization (ICO) is executed (EN_ICO_MODE=1b), the charger will automatically detect

the optimized input current limit based on adapter output characteristic. The final IIN_DPM register setting

could be different from IIN_HOST after ICO.

The voltage regulation loop of the charger regulates the input voltage to prevent the input adapter collapsing.

The VINDPM threshold should be configured based on no load input voltage level.Charger initiates a VBUS

voltage measurement without any load (VBUS at no load) right before the converter is enabled. The default

VINDPM threshold is VBUS at no load – 1.28 V. Host can adjust VINDPM threshold after device POR through

InputVoltage register(0x0B/0Ah[]), range from 3.2V to 19.52V with LSB 64mV.

After input current and voltage limits are set, the charger device is ready to power up. The host can always

program the input current and voltage limit after the charger being powered up based on the input source type.

9.3.7 Battery Cell Configuration

CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated

(VDDA rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No

external cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because

of battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and

Maximum charge voltage (REG0x15) follow 1 cell default setting 4.2 V. VSYS and VBAT ADC offset is also

determined by CELL_BATPRESZ pin setting, under 1S-4S VSYS/VBAT ADC holds 2.88-V offset, however under

5S detection VSYS/VBAT ADC only holds 8.16-V offset to cover higher voltage range. Refer to Table 9-2 for

CELL_BATPRESZ pin configuration typical voltage for swept cell count.

Table 9-2. Battery Cell Configuration

PIN VOLTAGE w.r.t.

VDDA

CHARGEVOLTAGE

(REG0x05/04h)

VSYS/VBAT

ADC OFFSET

CELL COUNT

SYSOVP

VSYS_MIN

5S

100%(Directly connect to

VDDA)

21.000 V

25 V

15.4 V

8.16 V

4S

75%

55%

40%

25%

0%

16.800 V

12.600 V

8.400 V

4.200 V

19.5 V

12 V

12.3 V

9.2 V

6.6 V

3.6 V

2.88 V

3S

2S

1S

6 V

Battery removal

25 V

9.3.8 Device HIZ State

When input source is present, the charger can enter HIZ mode (converter shuts off) when ILIM_HIZ pin voltage

is below 0.4 V or EN_HIZ is set to 1b. The charger is in the low quiescent current mode with REGN LDO

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enabled, ADC circuits are disactivated to reduce quiescent current. In order to exit HIZ mode, ILIM_HIZ pin

voltage has to be higher than 0.8 V and EN_HIZ bit has to be set to 0b.

9.3.9 USB On-The-Go (OTG)

The device supports USB OTG operation to deliver power from the battery to other portable devices through

USB port. The OTG mode output voltage is set in OTGVoltage register REG0x07/06() with 8-mV LSB range

from 3.0 V to 24 V. The OTG mode output current is set in OTGCurrent register REG0x09() with 100-mA LSB

range from 0 A to 12.7 A under 5-mΩ input current sensing. Both OTG voltage and OTG current are qualified for

USB-C™ programed power supply (PPS) specification in terms of resolution and accuracy. The OTG mode can

be enabled following below steps:

•

Set target OTG current limit in OTGCurrent register, VBUS is below V_{VBUS_CONVENZ}

Set OTG_VAP_MODE = 1b and EN_OTG = 1b.

OTG/VAP/FRS pin is pulled high.

15 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK

pin goes HIGH if OTG_ON_CHRGOK= 1b.

.

OTG/VAP/FRS pin is used as multi-function to enable OTG and FRS mode.

9.3.10 Converter Operation

The charger operates in buck, buck-boost and boost mode under different VBUS and VSYS combination. The

buck-boost can operate seamlessly across the three operation modes. The 4 main switches operating status

under continuous conduction mode (CCM) are listed below for reference.

Table 9-3. MOSFET Operation

MODE

Q1

BUCK

Switching

OFF

BUCK-BOOST

BOOST

ON

Switching

Q2

Switching

OFF

Q3

Switching

Q4

ON

Switching

9.3.11 Inductance Detection Through IADPT Pin

The charger reads both converter operation frequency and the inductance value through the resistance tied to

IADPT pin before the converter starts up. The resistances recommended for 2.2-μH (800 kHz), 3.3-μH (800 kHz)

and 4.7-μH (400 kHz) inductance refers to Table 9-4. A surface mount chip resistor with ±3% or better tolerance

must to be used for an accurate inductance detection.

Table 9-4. Inductor Detection through IADPT Resistance

INDUCTOR IN USE

RESISTOR ON IADPT PIN

137 kΩ or 140 kΩ

169 kΩ

2.2 µH (recommended for 800 kHz)

3.3 µH (recommended for 800 kHz)

4.7 µH (recommended for 400 kHz)

191 kΩ or 187 kΩ

9.3.12 Converter Compensation

The charger employs two compensation pins COMP1 and COMP2 for converter compensation purpose,

appropriate RC network is needed to guarantee converter steady state and transient operation. Under different

operation frequency corresponding RC network value needs to be configured respectively as shown in below

table. The definition of these RC components can be referred to Figure 9-2. It is not recommended to change the

compensation network value due to the complexity of various operation modes.

Table 9-5. Compensation Configuration

COMPONENT

INDUCTOR

COMP1 R1

COMP1 C11

COMP1 C12

COMP2 R2

COMP2 C21

COMP2 C22

VALUE

400 kHz

4.7 μH

40.2 kΩ

4.7 nF

33 pF

15 kΩ

680 pF

15 pF

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Table 9-5. Compensation Configuration (continued)

COMPONENT

VALUE

INDUCTOR

COMP1 R1

COMP1 C11

COMP1 C12

COMP2 R2

COMP2 C21

COMP2 C22

800 kHz

3.3 μH

2.2 μH

16.9 kΩ

3.3 nF

33 pF

15 kΩ

10 kΩ

1200 pF

15 pF

COMP1

COMP2

R1

R2

C12

C22

C11

C21

Figure 9-2. Compensation RC Network

9.3.13 Continuous Conduction Mode (CCM)

With sufficient charge or system current, the inductor current does not cross 0 A, which is defined as CCM. The

controller starts a new cycle with ramp coming up from 200 mV. As long as the error amplifier output voltage

is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error

amplifier output voltage, HSFET turns off and low-side MOSFET (LSFET) turns on. At the end of the cycle,

ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during

transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the

body-diode of the low-side power MOSFET conducts the inductor current.

During CCM, the inductor current always flows. Having the LSFET turn-on when the HSFET is off keeps the

power dissipation low and allows safe charging at high currents.

9.3.14 Pulse Frequency Modulation (PFM)

In order to improve converter light-load efficiency, BQ25730 switches to PFM operation at light load. The

effective switching frequency will decrease accordingly when system load decreases. The minimum frequency

can be limited to 25 kHz when the OOA feature is enabled (EN_OOA=1b) to avoid audible noise.

9.3.15 Switching Frequency and Dithering Feature

Normally, the IC switches in fixed frequency which can be adjusted through PWM_FREQ register bit. The

Charger also support frequency dithering function to improve EMI performance. This function is disabled by

default with setting EN_DITHER=00b. It can be enabled by setting EN_DITHER=01/10/11b, the switching

frequency is not fixed when dithering is enabled. It varies within determined range by EN_DITHER setting,

01/10/11b is corresponding to ±2%/4%/6% switching frequency. Please contact factory for more detail

information.

9.3.16 Current and Power Monitor

9.3.16.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)

A high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, or

output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the

differential voltage across ACP and ACN. IBAT voltage is 8×/16× of the differential across SRP and SRN. After

input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current

monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be

achieved.

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•

V_IADPT= 20 or 40 × (V_ACP– V_ACN) during forward mode, or 20 or 40 × (V_ACN– V_ACP) during reverse OTG

mode.

•

V_IBAT= 8 or 16 × (V_SRP– V_SRN) during forward charging mode.

V_IBAT= 8 or 16 × (V_SRN– V_SRP) during forward supplement mode, reverse OTG mode and battery only

discharge scenario.

A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An

additional RC filter is optional. Note that RC filtering has additional response delay. The CSA output voltage is

clamped at 3.3 V.

9.3.16.2 High-Accuracy Power Sense Amplifier (PSYS)

The charger monitors total system power. During forward mode, the input adapter powers the system. During

reverse OTG mode and battery only discharge scenario, the battery powers the system and VBUS output. The

ratio of PSYS pin output current and total system power, K_PSYS, can be programmed in PSYS_RATIO register

bit with default 1 μA/W. The input and charge sense resistors (R_ACand R_SR) are selected in RSNS_RAC bit and

RSNS_RSR bit. By default, PSYS_CONFIG=00b and PSYS voltage can be calculated with Equation 1, where

I_IN>0 when the charger is in forward charging and I_IN<0 when charger is in OTG operation; where I_BAT>0 when

the battery is in charging and I_BAT<0 when battery is discharging.

V_PSYS=R_PSYS·K_PSYS(V_ACP·I_IN+V_SYS·I_BAT

)

(1)

R_ACand R_SRvalues are not limited to symmetrical both 5 mΩ or both 10 mΩ. For defined current sense resistors

(10 mΩ/5 mΩ), PSYS function is still valid when R_AC=5 mΩ(RSNS_RAC=1b) and R_SR=10 mΩ(RSNS_RAC=0b),

vice versa. As long as RSNS_RAC and RSNS_RSR bit status are consistent with practical resistors used in the

system.

Charger can block IBAT contribution to above equation by setting PSYS_CONFIG =01b in forward mode and

block IBUS contribution to above equation by setting PSYS_OTG_IDCHG=1b in OTG mode.

To minimize the quiescent current, the PSYS function is disabled by default PSYS_CONFIG = 11b.

Table 9-6. PSYS Configuration Table

OTG

MODE PSYS

PSYS_OTG_IDCHG

BITS

FORWARD MODE PSYS

CONFIGURATION

CASE #

PSYS_CONFIG BITS

CONFIGURATION

1

00b

01b

11b

10b

0b

1b

Xb

PSYS = PBUS+PBAT

PSYS = PBUS

PSYS = PBUS + PBAT

PSYS =PBAT

2

3

PSYS = 0

4

PSYS = 0 (Disabled)

PSYS = 0 (Reserved)

PSYS = 0 (Disabled)

PSYS = 0 (Reserved)

5 (Reserved)

9.3.17 Input Source Dynamic Power Management

The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for

the system load and/or charging the battery. When the input current exceeds the input current setting (IIN_DPM),

or the input voltage falls below the input voltage setting (VINDPM), the charger decreases the charge current to

provide priority to the system load. As the system current rises, the available charge current drops accordingly

towards zero. If the system load keeps increasing after the charge current drops down to zero, the system

voltage starts to drop. As the system voltage drops below the battery voltage, the battery will discharge to

supplement the heavy system load.

9.3.18 Input Current Optimizer (ICO)

For a recognized input adapter, IINDPM can be configured precisely to prevent adapter collapasing. When a

third party unknown adapter is used, then input voltage regulation (VINDPM) feature can be leveraged to prevent

input crash. With the increasing of input current, voltage drops along the input cable also increases and voltage

measured it charger input port decreases accordingly. VINDPM feature can limit input power from adapter by

regulating VBUS at certain value configured at InputVoltage register(0x0Bh/0Ah[]). However, the adapter may

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still overheat when it is kept running at its voltage limit for a long period of time. Therefore, it is preferred to

operate the third party adapter slightly under its current rating. The Input Current Optimizer (ICO) feature can

automatically maximize the power of unknown input adapter without continuously working under VINDPM. Note

the ICO feature can only be employed when the adapter input current limit is at least 500 mA. Please contact

factory for more detail information about ICO feature.

9.3.19 Two-Level Adapter Current Limit (Peak Power Mode)

Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The

charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability

and minimize battery discharge during system load transient. The level 1 current limit, or I_LIM1, is the same as

adapter DC current, set in IIN_DPM register. The level 2 overloading current, or I_LIM2, is set in ILIM2_VTH, as a

percentage of I_LIM1

.

When the charger detects input current surge and battery discharge due to load transient (both the adapter

and battery support the system together), or when the charger detects the system voltage starts to drop below

VSYS_MIN setting due to load transient (only the adapter supports the system), the charger will first apply I_LIM2

for T_OVLD(PKPWR_TOVLD_DEG register bits), and then I_LIM1for up to T_MAX– T_OVLDtime. T_MAXis programmed

in PKPWR_TMAX register bits. After T_MAX,if the load is still high, another peak power cycle starts. Charging is

disabled during T_MAXand T_OVLDalready expires; once T_MAX,expires, a new cycle starts and resumes charging

automatically.

To prepare entering peak power follow below steps:

•

Set EN_IIN_DPM=1b to enable input current dynamic power management.

Set EN_EXTILIM=0b to disable external current limit.

Set register IIN_HOST based on adapter output current rating as the level 1 current limit(I_LIM1

Set register bits ILIM2_VTH according to the adapter overload capability as the level 2 current limit(I_LIM2) .

Set register bits PKPWR_TOVLD_DEG as I_LIM2effective duration time for each peak power mode operation

cycle based on adapter capability.

)

•

Set register bits PKPWR_TMAX as each peak power mode operation cycling time based on adapter

capability.

Depends on the battery existence and charge status peak power mode can be finally enabled with two different

approaches:

•

When battery is depleted in which VBAT is lower than VSYS_MIN setting or battery is removed, host need

to set EN_PKPWR_VSYS=1b to enable peak power mode triggered by system voltage undershoot. The

under-shoot threshold is the VSYS_MIN register setting which is the system regulation point before load

transient happens. Typical application waveform refer to Figure 10-22.

•

When battery is not depleted in which VBAT is higher than VSYS_MIN setting, host need to set

EN_PKPWR_IIN_DPM=1b to enable peak power mode triggered by input current overshoot. The overshoot

threshold is IIN_DPM register which is same as the level 1 current limit (I_LIM1). Typical application waveform

refer to Figure 10-23.

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ICRIT_DEG

ICRIT

ILIM2

ILIM1

TOVLD

TMAX

IBUS

ISYS

IBAT

0A

Ba ery Discharge

PROCHOT_WIDTH

PROCHOT

Figure 9-3. Two-Level Adapter Current Limit Timing Diagram

9.3.20 Processor Hot Indication

The events monitored by the processor hot function includes:

•

ICRIT: adapter peak current, as 110% of I_LIM2

INOM: adapter average current (110% of IIN_DPM)

IDCHG1: battery discharge current level 1

IDCHG2: battery discharge current level 2, note IDCHG2 threshold is always larger than IDCHG1 threshold

determined by IDCHG_TH2 register setting.

•

VBUS_VAP: VBUS threshold to trigger PROCHOT in VAP mode 2 and 3.

VSYS: system voltage on VSYS pin

Adapter Removal: upon adapter removal (VBUS is lower than ACOK_TH=3.2 V same as V_{VBUS_CONVENZ}

threshold)

•

Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW)

CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW)

VINDPM: VBUS lower than 83%/91%/100% of VINDPM setting. The effective threshold PROCHOT_VINDPM

is determined by combination of register PROCHOT_VINDPM_80_90 bit and LOWER_PROCHOT_VINDPM

bit:

– PROCHOT_VINDPM=VINDPM register setting: LOWER_PROCHOT_VINDPM=0b;

– PROCHOT_VINDPM=83% VINDPM register setting:

LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=0b;

– PROCHOT_VINDPM=91% VINDPM register setting:

LOWER_PROCHOT_VINDPM=1b;PROCHOT_VINDPM_80_90=1b;

EXIT_VAP: Every time when the charger exits VAP mode.

•

The threshold of ICRIT, IDCHG1,IDCHG2,VSYS or VINDPM, and the deglitch time of ICRIT, INOM, IDCHG1,

IDCHG2, or CMPOUT are programmable through I²C register bits. Except the PROCHOT_EXIT_VAP is always

enabled, the other triggering events can be individually enabled in ProchotOption1[7:0], PP_IDCHG2 and

PP_VBUS_VAP. When any enabled event in PROCHOT profile is triggered, PROCHOT is asserted low for

a single pulse with minimal width programmable in PROCHOT_WIDTH register bits. At the end of the single

pulse, if the PROCHOT event is still active, the pulse gets extended until the event is removed.

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If the PROCHOT pulse extension mode is enabled by setting EN_PROCHOT_EXT= 1b, the PROCHOT pin will

be kept low until host writes PROCHOT_CLEAR= 0b, even if the triggering event has been removed.

If the PROCHOT_VINDPM or PROCHOT_EXIT_VAP is triggered, PROCHOT pin will always stay low until

the host clears it, no matter the PROCHOT is in one pulse mode or in extended mode. In order to clear

PROCHOT_VINDPM, host needs to write 0 to STAT_VINDPM. In order to clear PROCHOT_EXIT_VAP, host

needs to write 0 to STAT_EXIT_VAP.

PP_ICRIT

IADPT

+

ICRIT

Adjustable

Deglitch

Low Pass

Filter

PP_INOM

+

EXIT_VAP

(triggered by IN_VAP

falling edge)

INOM

1.05V

PP_IDCHG2

IDCHG2

IDCHG1

+

IDCHG_VTH2

PP_IDCHG1

PROCHOT

+

IDCHG_VTH1

VSYS_VTH2

10ms

Debounce

PP_VSYS

+

VSYS

VBUS

10ms

Fixed

Deglitch

4us

PP_VINDPM

A*VINDPM

+

Fixed

Deglitch

4us

PP_VBUS_VAP

PP_ACOK

VBUS_VAP_TH

+

V_{VBUS_CONVENZ}

PP_CMP

PP_BATPRES

CELL_BATPRESZ

(one shot on pin falling edge)

VBUS

(one shot on pin falling edge)

CMPOUT

Figure 9-4. PROCHOT Profile

9.3.20.1 PROCHOT During Low Power Mode

During low power mode (EN_LWPWR = 1), the charger offers a low power PROCHOT function with very low

quiescent current consumption (~35 μA), which uses the independent comparator to monitor the system voltage,

and assert PROCHOT to CPU if the system power is too high and resulting system voltage is lower than specific

threshold.

Below lists the register setting to enable PROCHOT monitoring system voltage in low power mode.

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•

EN_LWPWR = 1b to enable charger low power mode.

REG0x34[7:0] = 00h

REG0x30[6:4] = 000b

Independent comparator threshold is always 1.2 V

When EN_PROCHOT_LPWR = 1b, charger monitors system voltage. Connect CMPIN to voltage

proportional to system voltage. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above

1.2 V.

PROCHOT

1.2 V

Independent

Comparator

CMPIN

Voltage îV_SYS

Figure 9-5. PROCHOT Low Power Mode Implementation

9.3.20.2 PROCHOT Status

report which event in the profile triggers PROCHOT if the corresponding bit is set to 1. The status bit can be

reset back to 0 after it is read by the host, when the current PROCHOT event is not active any more.

Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B

is also active. Both status bits will be HIGH. At the end of the 10-ms PROCHOT pulse, if any of the PROCHOT

event is still active (either A or B), the PROCHOT pulse is extended.

9.3.21 Device Protection

9.3.21.1 Watchdog Timer

The charger includes a watchdog timer to terminate charging if the charger does not receive a

write ChargeVoltage() or write ChargeCurrent() command within 175s (default value and adjustable via

WDTMR_ADJ). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent()

resets to 0 A . Write ChargeVoltage() or write ChargeCurrent() commands must be resent to reset watchdog

timer. Writing WDTMR_ADJ = 00b to disable watchdog timer or update new watchdog timer values can also

reset watchdog timer. New non-zero charge current value has to be written to ChargeCurrent() register to

resume charging after watchdog timer expires.

9.3.21.2 Input Overvoltage Protection (ACOV)

The charger has fixed ACOV voltage threshold with hysteresis. When VBUS pin voltage is higher than

V_{ACOV_RISE}for more than 100 μs, it is considered as adapter overvoltage. CHRG_OK pin will be pulled low

by the charger, and the converter will be disabled. As system falls below battery voltage, BATFET will be turned

on. When VBUS pin voltage falls below V_{ACOV_FALL}for more than 1 ms, it is considered as adapter voltage

returns back to normal voltage. CHRG_OK pin is pulled high by external pull-up resistor. The converter resumes

if enable conditions are valid.

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9.3.21.3 Input Overcurrent Protection (ACOC)

If the input current exceeds the 1.33× or 2× of ILIM2_VTH set point ACOC_TH (adjustable through ACOC_VTH),

after 250-μs rising edge de-glitch time converter stops switching because of input overcurrent protection

(ACOC). ACOC is a non-latch fault, if input current falls below set point, after 250-ms falling edge de-glitch

time converter starts switching again. ACOC is disabled by default and need to be enabled by configuring

EN_ACOC=1b. When ACOC is triggered, its corresponding status bit Fault ACOC will be set and it can be

cleared by host read.

9.3.21.4 System Overvoltage Protection (SYSOVP)

When the converter starts up, the BQ25730 reads CELL_BATPRESZ pin configuration and sets ChargeVoltage()

and SYSOVP threshold (1s – 6 V, 2s – 12 V, 3s/4s – 19.5 V and 5s – 25 V ). Before ChargeVoltage() is written

by the host, the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device

latches off the converter. Fault SYSOVP status bit is set to 1. The user can clear latch-off by either writing 0

to the Fault SYSOVP status bit or removing and plugging in the adapter again. After latch-off is cleared, the

converter starts again.

9.3.21.5 Battery Overvoltage Protection (BATOVP)

Battery overvoltage may happen when user plugs in a wrong battery or a wrong regulation voltage is written

into ChargeVoltage() register. The BATOVP rising threshold is 104% of regulation voltage set in ChargeVoltage()

register, and falling threshold is 102% of regulation voltage set in ChargeVoltage() register. When BATOVP rising

condition is triggered: if charge is enabled (charge current is not 0A) converter should shut down with both

HS MOSFET and LS MOSFET turned off; if charge is disabled the converter should keep operating without

disturbance until battery rise up system voltage to be high enough trigger SYSOVP. There is no user status bit

to monitor. Note VBAT voltage used for BATOVP detection is based on SRN pin measurement. When BATOVP

is triggered with charge enabled, 40-mA discharge current is added on VSYS pin will help discharge battery

voltage.

9.3.21.6 Battery Discharge Overcurrent Protection (BATOC)

The charger monitors the battery discharge current to provide the battery overcurrent protection (BATOC)

through voltage across SRN and SRP. BATOC can be enabled by configuring EN_BATOC=1b. BATOC threshold

is selected either 133% of IDCHG_TH2 or 200% IDCHG_TH2 through BATOC_VTH bit. The threshold is also

clamped between 100 mV and 360 mV SRN-SRP cross voltage.

When discharge current is higher than the threshold after 250-μs deglitch time, BATOC fault is triggered, status

bit Fault BATOC is set accordingly. Converter shuts down when BATOC is asserted to disable OTG operation

and reduce discharge current. BATFET status is not impacted if need to supplement power to system.

BATOC is not a latch fault, therefore after BATOC fault is removed, with 250-ms relax time, converter resume

switching automatically. But status bit Fault BATOC is only cleared by host read.

9.3.21.7 Battery Short Protection (BATSP)

For multicell operation, if BAT voltage falls below VSYS_MIN during charging, the maximum charger current

is limited to 384 mA. For single-cell operation, if BAT voltage falls below 3.0 V during charging, the maximum

charge current is limited to 384 mA; if BAT voltage is between 3.0 V and VSYS_MIN then maximum charge

current is limited to 2 A. Note VBAT voltage used for battery short detection is based on SRN pin measurement.

9.3.21.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode

The charger VSYS_UVP is enabled by POR ( VSYS_UVP_ENZ=0b) and can be disabled by writing

VSYS_UVP_ENZ=1b. This protection is mainly defined to protect converter from system short circuit under

both startup and steady state process. VSYS pin is used to monitor the system voltage, when VSYS is lower

than 2.4 V (configurable through VSYS_UVP register bits), there is 2-ms deglitch time, the IIN_DPM is clamped

to 0.5 A by the charger itself.

If hiccup mode is enabled with VSYS_UVP_NO_HICCUP = 0b, after 2-ms deglitch time, the charger should shut

down for 500 ms.The charger will restart for 10 ms if VSYS is still lower than 2.4 V, the charger should shut

down again. This hiccup mode will be tried continuously, if the charger restart failed for 7 times in 90 second, the

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charger will be latched off. Fault VSYS_UVP bit will be set to 1 to report a system short fault. The charger only

can be enabled again by writing Fault VSYS_UVP bit to 0b.

If hiccup mode is disabled VSYS_UVP_NO_HICCUP = 1b. After 2-ms deglitch time, the charger should shut

down and latched off. Fault VSYS_UVP bit will be set to 1 to report a system short fault. The charger only can be

enabled again once the host writes Fault VSYS_UVP bit to 0b.

9.3.21.9 Thermal Shutdown (TSHUT)

The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to

the ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for

self-protection whenever the junction temperature reaches the 155°C. The charger stays off until the junction

temperature falls below 135°C. During thermal shut down, the REGN LDO current limit is reduced to 16 mA and

stays on. When the temperature falls below 135°C, charge can be resumed with soft start.

When thermal shut down is triggered, TSHUT status bit will be triggered. This status bit keep triggered until host

read to clear it. If TSHUT is still present during host read, then this bit will try to be cleared when host read but

finally keep triggered because TSHUT still exists.

9.4 Device Functional Modes

9.4.1 Forward Mode

When input source is connected to VBUS, BQ25730 is in forward mode to regulate system and charge battery.

9.4.1.1 System Voltage Regulation with Narrow VDC Architecture

The device employs Narrow VDC architecture (NVDC) with BATFET separating the system from the battery. The

minimum system voltage is set by VSYS_MIN register REG0x0D/0C(). Even with a depleted battery, the system

is regulated above the minimum system voltage.

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is regulated at VSYS_MIN register value. As the battery voltage rises above the minimum

system voltage, system voltage is regulated 150 mV above battery voltage when BATFET is turned off (no

charging or no supplement current). When in charging or in supplement mode, the voltage difference between

the system and battery is the V_DSof the BATFET and the BATFET is fully on.

9.4.1.2 Battery Charging

The BQ25730 charges 1- to 5-cell battery in constant current (CC), and constant voltage (CV) mode. Based on

CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2 V/cell to ChargeVoltage(). According

to battery capacity, the host programs appropriate charge current to ChargeCurrent() register. When battery is

full or battery is not in good condition to charge, host terminates charge by setting CHRG_INHIBIT bit to 1b, or

setting ChargeCurrent() to zero.

9.4.2 USB On-The-Go

The BQ25730 supports USB OTG functionality to deliver power from the battery to other portable devices

through USB port (reverse mode). The OTG output voltage is compliant with USB-C PD specification, including

5 V, 9 V, 15 V, and 20 V. The output current regulation is compliant with USB-C PD specification, including 500

mA, 1.5 A, 3 A and 5 A, and so forth.

Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve

efficiency.

9.4.3 Pass Through Mode (PTM)-Patented Technology

The charger can be operated in the pass through mode (PTM) to improve efficiency. In PTM, the Buck and Boost

high-side FETs (Q1 and Q4) are both turned on, while the Buck and Boost low-side FETs are both turned off.

The input power is directly passed through the charger to the system. The switching losses of MOSFETs and

the inductor core loss are saved. The charger quiescent current under PTM mode is also minimized to further

increase light load efficiency. Charger will be transition from normal Buck-Boost operation to PTM operation by

setting EN_PTM = 1b; and will transition out of PTM mode with host control by setting EN_PTM =0b. Please

contact factory for more detail information about PTM mode.

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9.5 Programming

The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as

summarized in Section 9.5.1.7. The I²C address is 6Bh(0b1101011) consist of 7 bits. Adding read(1b) and

write(0b) to the end of address 7bits, the total 8bits data format address should be D6h (1101011_0 for write)/

D7h(1101011_1 for read). The ManufacturerID and DeviceID registers are assigned to identify the charger

device. The ManufacturerID register command always returns 40h.

9.5.1 I²C Serial Interface

The BQ25730 uses I²C compatible interface for flexible charging parameter programming and instantaneous

device status reporting. I²C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial

data line (SDA) and a serial clock line (SCL). Devices can be considered as host or target when performing data

transfers. A host is the device which initiates a data transfer on the bus and generates the clock signals to permit

that transfer. At that time, any device addressed is considered a target device.

The device operates as a target device with address D6h, receiving control inputs from the host device like micro

controller or a digital signal processor through REG00-REG3F. The I²C interface supports both standard mode

(up to 100 kHz), and fast mode (up to 400 kHz). connecting to the positive supply voltage via a current source or

pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

9.5.1.1 Timing Diagrams

SCL

SDA

A = Start condition

H = LSB of data clocked into target

I = Target pulls SDA line low

B = MSB of address clocked into target

C = LSB of address clocked into target

D = R/W bit clocked into target

E = Target pulls SDA line low

J = Acknowledge clocked into host

K = Acknowledge clock pulse

L = Stop condition, data executed by target

M = New start condition

F = ACKNOWLEDGE bit clocked into host

G = MSB of data clocked into target

Figure 9-6. I²C Write Timing

SCL

SDA

A = Start condition

G = MSB of data clocked into host

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B = MSB of address clocked into target

C = LSB of address clocked into target

D = R/W bit clocked into target

H = LSB of data clocked into host

I = Acknowledge clock pulse

J = Stop condition

E = Target pulls SDA line low

K = New start condition

F = ACKNOWLEDGE bit clocked into host

Figure 9-7. I²C Read Timing

9.5.1.2 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Data line stable;

Data valid

Change

of data

allowed

Figure 9-8. Bit Transfer on the I²C Bus

9.5.1.3 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the host. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

START (S)

Figure 9-9. START and STOP Conditions

9.5.1.4 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

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Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the host into a wait state (clock stretching). Data

transfer then continues when the target is ready for another byte of data and release the clock line SCL.

Acknowledgement

signal from receiver

signal from slave

MSB

SDA

S or Sr

1

2

7

8

9

1

2

8

9

P or Sr

SCL

ACK

START or

Repeated

START

STOP or

Repeated

START

Figure 9-10. Data Transfer on the I²C Bus

9.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9th clock pulse, are generated by the host.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The host can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

9.5.1.6 Target Address and Data Direction Bit

After the START, a target address is sent. This address is 7 bits long followed by the eighth bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

S

8

9

8

9

8

9

P

SCL

1-7

START

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

Figure 9-11. Complete Data Transfer

9.5.1.7 Single Read and Write

Figure 9-12. Single Write

Figure 9-13. Single Read

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If the register address is not defined, the charger IC send back NACK and go back to the idle state.

9.5.1.8 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write.

Figure 9-14. Multi Write

Figure 9-15. Multi Read

9.5.1.9 Write 2-Byte I²C Commands

A few I²C commands combine two 8-bit registers together to form a complete value. These commands include:

•

ChargeCurrent()

ChargeVoltage()

IIN_DPM()

OTGVoltage()

InputVoltage()

Host has to write LSB bit first and then move on to MSB bit. No other command can be inserted in between

these two writes. The charger waits for the complete write to the two registers to decide whether to accept or

ignore the new value.

After the completion of LSB and MSB bytes, the two bytes will be updated at the same time. If host writes MSB

byte first, the command will be ignored. If the time between write of LSB and MSB bytes exceeds watchdog

timer, both the LSB and MSB commands will be ignored.

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9.6 Register Map

Table 9-7. Charger Command Summary

I²C ADDR

(MSB/LSB)

REGISTER NAME

ChargeOption0()

TYPE

R/W

DESCRIPTION

LINKS

01/00h

03/02h

Charge Option 0

Go

ChargeCurrent()

R/W

7-bit charge current setting

LSB 128 mA, Range 0 mA – 16256 mA

(R_SR=5mΩ)

05/04h

ChargeVoltage()

R/W

12-bit charge voltage setting

Go

LSB 8 mV, Default: 1S-4200mV, 2S-8400mV,

3S-12600mV, 4S-16800mV, 5S-21000mV

07/06h

09/08h

OTGVoltage()

OTGCurrent()

R/W

12-bit OTG voltage setting

LSB 8 mV, Range: 3000 mV – 24000 mV

Go

7-bit OTG output current setting

LSB 100 mA, Range: 0 A – 12700 mA

(R_AC=5mΩ)

0B/0Ah

0D/0Ch

InputVoltage()

VSYS_MIN()

R/W

8-bit input voltage setting

LSB 64 mV, Range: 3200 mV – 19520 mV

Go

8-Bit minimum system voltage setting

LSB: 100 mV, Range: 1000 mV - 23000 mV

Default: 1S-3.6V, 2S-6.6V, 3S-9.2V, 4S-12.3V,

5S-15.4V

0F/0Eh

IIN_HOST()

R/W

6-bit Input current limit set by host

LSB: 100-mA, Range: 100 mA - 10000 mA with

100 mA offset (R_AC=5mΩ)

Go

21/20h

23/22h

25/24h

ChargerStatus()

ProchotStatus()

IIN_DPM()

R with R/W Charger Status

bits

Go

R and R/W Prochot Status

bits

R

7-bit input current limit in use

LSB: 50 mA, Range: 100 mA - 10000 mA

(R_AC=5mΩ)

27/26h

29/28h

ADCVBUS/PSYS()

ADCIBAT()

R

8-bit digital output of input voltage,

Go

8-bit digital output of system power

PSYS: Full range: 3.06 V, LSB: 12 mV

VBUS: Full range: 0 V - 24.48 V, LSB 96 mV

R

7-bit digital output of battery charge current,

7-bit digital output of battery discharge current

ICHG: Full range 16.256 A, LSB 128 mA

IDCHG: Full range: 65.024 A, LSB: 512 mA

(R_SR=5mΩ)

2B/2Ah

2D/2Ch

ADCIINCMPIN()

ADCVSYSVBAT()

8-bit digital output of input current,

8-bit digital output of CMPIN voltage

POR State - IIN: Full range: 25.5 A, LSB 100 mA

(R_AC=5mΩ)

Go

CMPIN: Full range 3.06 V, LSB: 12 mV

8-bit digital output of system voltage,

8-bit digital output of battery voltage

VSYS: Full range: 2.88 V - 19.2 V, LSB: 64 mV

(1S-4S)

VSYS: Full range: 8.16 V - 24.48 V, LSB: 64 mV

(5S)

VBAT: Full range : 2.88 V - 19.2 V, LSB 64 mV

(1S-4S)

VBAT: Full range : 8.16 V - 24.48 V, LSB 64 mV

(5S)

2Eh

ManufacturerID()

DeviceID()

R

Manufacturer ID - 0x0040H

Device ID

Go

2Fh

R

31/30h

ChargeOption1()

R/W

Charge Option 1

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Table 9-7. Charger Command Summary (continued)

I²C ADDR

(MSB/LSB)

REGISTER NAME

TYPE

R/W

DESCRIPTION

33/32h

35/34h

37/36h

39/38h

3B/3Ah

3D/3Ch

3F/3Eh

ChargeOption2()

ChargeOption3()

Charge Option 2

Charge Option 3

Go

R/W

ProchotOption0()

ProchotOption1()

ADCOption()

PROCHOT Option 0

PROCHOT Option 1

ADC Option

ChargeOption4()

Vmin Active Protection()

Charge Option 4

Vmin Active Protection

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9.6.1 ChargeOption0 Register (I²C address = 01/00h) [reset = E70Eh]

Figure 9-14. ChargeOption0 Register (I²C address = 01/00h) [reset = E70Eh]

7

6

5

4

3

2

1

0

EN_LWPWR

WDTMR_ADJ

R/W

IIN_DPM_AUT OTG_ON_CH

EN_OOA

PWM_FREQ LOW_PTM_RIP

PLE

O_DISABLE

RGOK

R/W

7

R/W

1

R/W

0

6

5

4

3

2

EN_CMP_LAT VSYS_UVP_E

EN_LEARN

IADPT_GAIN

IBAT_GAIN

EN_LDO

EN_IIN_DPM CHRG_INHIBIT

CH

NZ

R/W

R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-8. ChargeOption0 Register (I²C address = 01h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

EN_LWPWR

R/W

1b

Low Power Mode Enable, under low power mode lowest quiescent current is

achieved when only battery exist. It is not recommended to enable low power

mode when adapter present.

0b: Disable Low Power Mode. Device in performance mode with battery only.

The PROCHOT, current/power monitor buffer and comparator follow register

setting.

1b: Enable Low Power Mode. Device in low power mode with battery only

for lowest quiescent current. The REGN is off. The PROCHOT, discharge

current monitor buffer, power monitor buffer and independent comparator are

disabled. ADC is not available in Low Power Mode. Independent comparator

and its low power mode PROCHOT profile can be enabled by setting

EN_PROCHOT_LPWR bit to 1b. <default at POR>

6-5

WDTMR_ADJ

R/W

11b

WATCHDOG Timer Adjust

Set maximum delay between consecutive Host write of charge voltage or

charge current command.

If device does not receive a write on the REG0x15() or the REG0x14()

within the watchdog time period, the charger will be suspended by setting

the REG0x14() to 0 mA .

After expiration, the timer will resume upon the write of REG0x14(),

REG0x15() or REG0x12[14:13].

00b: Disable Watchdog Timer

01b: Enabled, 5 sec

10b: Enabled, 88 sec

11b: Enable Watchdog Timer, 175 sec <default at POR>

4

IIN_DPM_AUTO_DISAB R/W

LE

0b

IIN_DPM Auto Disable

When CELL_BATPRESZ pin is LOW, the charger automatically disables the

IIN_DPM function by setting EN_IIN_DPM (REG0x12[1]) to 0. The host can

enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x12[1]) to 1.

0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ

goes LOW. <default at POR>

1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes

LOW.

3

OTG_ON_CHRGOK

R/W

0b

Add OTG to CHRG_OK

Drive CHRG_OK to HIGH when the device is in OTG mode.

0b: Disable <default at POR>

1b: Enable

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Table 9-8. ChargeOption0 Register (I²C address = 01h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

2

EN_OOA

R/W

1b

Out-of-Audio Enable

In both forward mode and OTG mode, switching frequency reduces with

diminishing load, under extreme light load condition the switching frequency

could be lower than 25 kHz which is already in audible frequency range. By

configuring EN_OOA=1b, the minimum PFM burst frequency is clamped at

around 25 kHz to avoid any audible noise.

0b: No limit of PFM burst frequency

1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise

1

0

PWM_FREQ

R/W

1b

Switching Frequency Selection: Recommend 800 kHz with 2.2 µH, and 400

kHz with 4.7 µH.

0b: 800kHz

1b: 400 kHz<default at POR>

LOW_PTM_RIPPLE

PTM mode input voltage and current ripple reduction

0b: Disable

1b: Enable <default at POR>

Table 9-9. ChargeOption0 Register (I²C address = 00h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

EN_CMP_LATCH

R/W

0b

The EN_CMP_LATCH bit, will latch the independent comparator output after

it is triggered at low state. If enabled in PROCHOT profile REG34H[6]=1 ,

STAT_COMP bit REG0x21[6] keep 1b after triggered until read by host and

clear

0b: Independent comparator output will not latch when it is low<default at

POR>

1b: Independent comparator output will latch when it is low, host can clear

CMPOUT pin by toggling this REG0x12[7] bit.

6

5

VSYS_UVP_ENZ

EN_LEARN

R/W

0b

To disable system under voltage protection.

0b: VSYS under voltage protection is enabled <default at POR>

1b: VSYS under voltage protection is disabled

LEARN mode allows the battery to discharge and converter to shut off while

the adapter is present . It calibrates the battery gas gauge over a complete

discharge/charge cycle. When the host determines the battery voltage is

below battery depletion threshold, the host switch the system back to adapter

input by writing this bit back to 0b.

0b: Disable LEARN Mode <default at POR>

1b: Enable LEARN Mode

4

3

IADPT_GAIN

IBAT_GAIN

R/W

0b

1b

IADPT Amplifier Ratio

The ratio of voltage on IADPT and voltage across ACP and ACN.

0b: 20× <default at POR>

1b: 40×

IBAT Amplifier Ratio

The ratio of voltage on IBAT and voltage across SRP and SRN

0b: 8×

1b: 16× <default at POR>

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Table 9-9. ChargeOption0 Register (I²C address = 00h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

2

EN_LDO

R/W

1b

LDO Mode Enable

When battery voltage is below minimum system voltage (REG0x3E()), the

charger is in pre-charge with LDO mode enabled.

0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery

pack internal resistor. The system is regulated by the MaxChargeVoltage

register.

1b: Enable LDO mode, Precharge current is set by the ChargeCurrent

register and clamped below 384 mA (2 cell – 4 cell, 1cell VBAT<3.0V) or 2A

(1cell 3.0V<VBAT<3.6V). The system is regulated by the VSYS_MIN register.

1

0

EN_IIN_DPM

R/W

1b

0b

IIN_DPM Enable

Host writes this bit to enable IIN_DPM regulation loop. When the IIN_DPM

is disabled by the charger (refer to IIN_DPM_AUTO_DISABLE), this bit goes

LOW.

0b: IIN_DPM disabled

1b: IIN_DPM enabled <default at POR>

CHRG_INHIBIT

Charge Inhibit

When this bit is 0, battery charging will start with valid values in the

ChargeVoltage() register and the ChargeCurrent register.

0b: Enable Charge <default at POR>

1b: Inhibit Charge

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9.6.2 ChargeCurrent Register (I²C address = 03/02h) [reset = 0000h]

To set the charge current, write 16-bit ChargeCurrent() command (REG0x03/02h()) using the data format listed

Figure 9-15.

With 5-mΩ sense resistor, the charger provides charge current range of 0 A to 16.256 A, with a 128-mA step

resolution. With 10-mΩ sense resistor, the charger provides charge current range of 0 A to 8.128 A, with a

64-mA step resolution.

Upon POR, ChargeCurrent() is 0 A. Below scenarios will also reset Charge current to zero:

•

CELL_BATPRESZ going LOW (battery removal).

STAT_AC is not valid(Adapter removal).

RESET_REG is asserted and reset all registers.

Charge voltage is written to be 0 V.

Watch dog event is triggered.

Charge current is not reset in force converter latch off fault (REG0x20[2]), and ACOC/TSHUT/SYSOVP/ACOV/

VSYS_UVP/BATOVP/BATOC faults.

Figure 9-15. ChargeCurrent Register (I²C address = 03/02h) [reset = 0000h]

7

6

5

4

3

2

1

0

Reserved

Charge Current, Charge Current, Charge Current, Charge Current, Charge Current,

bit 6

R/W

4

bit 5

R/W

3

bit 4

bit 3

R/W

1

bit 2

R/W

0

R/W

6

R/W

7

5

2

Charge Current, Charge Current,

Reserved

bit 1

bit 0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-10. Charge Current Register with 5-mΩ Sense Resistor (I²C address = 03h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-5

Reserved

R/W

000b

Not used. 1 = invalid write.

4

3

2

1

0

Charge Current, bit 6

Charge Current, bit 5

Charge Current, bit 4

Charge Current, bit 3

Charge Current, bit 2

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 8192 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 4096 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 2048 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 1024 mA of charger current.

0 = Adds 0 mA of charger current.

1 = Adds 512 mA of charger current.

Table 9-11. Charge Current Register with 5-mΩ Sense Resistor (I²C address = 02h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Charge Current, bit 1

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 256 mA of charger current.

6

Charge Current, bit 0

Reserved

R/W

0b

0 = Adds 0 mA of charger current.

1 = Adds 128 mA of charger current.

5-0

000000b

Not used. Value Ignored.

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9.6.2.1 Battery Pre-Charge Current Clamp

During pre-charge, BATFET works in linear mode (LDO mode) (default EN_LDO= 1b). For 2-4 cell battery, the

system is regulated at VSYS_MIN register and the pre-charge current is clamped at 384 mA. For 1 cell battery,

the pre-charge to fast charge threshold is 3 V, and the pre-charge current is clamped at 384 mA. However, the

BATFET stays in LDO mode operation untill battery voltage is above minimum system voltage (~3.6 V). During

battery voltage from 3 V to 3.6 V, the fast charge current is clamped at 2 A.

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9.6.3 ChargeVoltage Register (I²C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]

To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x05/04h()) using the

data format listed in Figure 9-16, Table 9-12, and Table 9-13. The charger provides charge voltage range from

1.024 V to 23.000 V, with 8-mV step resolution. Any write below 1.024 V or above 23.000 V is ignored.

Upon POR, ChargeVoltage() is by default set as 4200 mV for 1 s, 8400 mV for 2 s, 12600 mV for 3 s or 16800

mV for 4 s, 21000 mV for 5s. After CHRG_OK goes high, the charge will start when the host writes the charging

current to ChargeCurrent() register, the default charging voltage is used if ChargeVoltage() is not programmed. If

the battery is different from 4.2 V/cell, the host has to write to ChargeVoltage() before ChargeCurrent() register

for correct battery voltage setting. Writing ChargeVoltage() to 0 should keep ChargeVoltage() value unchanged,

and force ChargeCurrent() register to zero to disable charge.

The SRN pin senses the battery voltage for voltage regulation and should be connected as close to the battery

as possible.

Figure 9-16. ChargeVoltage Register (I²C address = 05/04h) [reset value based on CELL_BATPRESZ pin

setting]

7

6

5

4

3

2

1

0

Reserved

Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage,

bit 11

R/W

6

bit 10

R/W

5

bit 9

R/W

4

bit 8

R/W

3

bit 7

R/W

2

bit 6

bit 5

R/W

0

R/W

7

R/W

1

Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage, Charge Voltage,

Reserved

bit 4

bit 3

bit 2

bit 1

bit 0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-12. ChargeVoltage Register (I²C address = 05h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Reserved

R/W

0b

Not used. 1 = invalid write.

6

5

4

3

2

1

0

Charge Voltage, bit 11

Charge Voltage, bit 10

Charge Voltage, bit 9

Charge Voltage, bit 8

Charge Voltage, bit 7

Charge Voltage, bit 6

Charge Voltage, bit 5

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 16384 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 8192 mV of charger voltage

0 = Adds 0 mV of charger voltage.

1 = Adds 4096 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 2048 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 1024 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 512 mV of charger voltage.

0 = Adds 0 mV of charger voltage.

1 = Adds 256 mV of charger voltage.

Table 9-13. ChargeVoltage Register (I²C address = 04h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Charge Voltage, bit 4

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 128 mV of charger voltage.

6

Charge Voltage, bit 3

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 64 mV of charger voltage.

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Table 9-13. ChargeVoltage Register (I²C address = 04h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

5

Charge Voltage, bit 2

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 32 mV of charger voltage.

4

3

Charge Voltage, bit 1

Charge Voltage, bit 0

Reserved

R/W

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 16 mV of charger voltage.

0b

0 = Adds 0 mV of charger voltage.

1 = Adds 8 mV of charger voltage.

2-0

000b

Not used. Value Ignored.

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9.6.4 ChargerStatus Register (I²C address = 21/20h) [reset = 0000h]

Figure 9-17. ChargerStatus Register (I²C address = 21/20h) [reset = 0000h]

7

6

5

4

3

2

1

0

STAT_AC

ICO_DONE

IN_VAP

IN_VINDPM

IN_IIN_DPM

IN_FCHRG

IN_PCHRG

IN_OTG

R

4

R

3

R

2

R

1

R

0

7

6

5

Fault ACOV

Fault BATOC

Fault ACOC

FAULT

SYSOVP

Fault VSYS

_UVP

Fault

Force_Converte

r_Off

Fault_OTG

_OVP

Fault_OTG

_UVP

R

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-14. ChargerStatus Register (I²C address = 21h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

STAT_AC

R

0b

Input source status. STAT_AC is valid as long as VBUS go within

3.5-V to 26-V range. It is different from CHRG_OK bit, When

CHRG_OK is valid, STAT_AC must be valid, but if STAT_AC is valid,

it is not necessary CHRG_OK is valid. There are Force converter

off, ACOC, TSHUT , SYSOVP, VSYS_UVP, BATOVP can pull low

CHRG_OK.

0b: Input not present

1b: Input is present

6

5

ICO_DONE

IN_VAP

R

0b

After the ICO routine is successfully executed, the bit goes 1.

0b: ICO is not complete

1b: ICO is complete

0b: Charger is not operated in VAP mode

1b: Charger is operated in VAP mode

Digital status bit indicates VAP has enabled(1) or disabled(0). The

enable of VAP mode only follows the host command, which is not

blocked by any status of /PROCHOT. The exit of VAP mode also

follows the host command, except that any faults will exit VAP mode

automatically. STAT_EXIT_VAP (REG0x21[8]) becomes 1 which will

pull low /PROCHOT until host clear.

The host can enable VAP by setting OTG/VAP/FRS pin high and

0x32[5]=0, disable VAP by setting either OTG/VAP/FRS pin low

or 0x32[5]=1. Any faults in VAP When IN_VAP bit goes 0->1,

charger should disable VINDPM, IIN_DPM, ICRIT, ILIM pin, disable

PP_ACOK if it is enabled, enable PP_VSYS if it is disabled. When

IN_VAP bit goes 1->0, charger should enable VINDPM, IIN_DPM,

ICRIT, ILIM pin function.

4

IN_VINDPM

R

0b

0b: Charger is not in VINDPM during forward mode, or voltage

regulation during OTG mode

1b: Charger is in VINDPM during forward mode, or voltage

regulation during OTG mode

3

2

1

IN_IIN_DPM

IN_FCHRG

IN_PCHRG

R

0b

0b: Charger is not in IIN_DPM during forward mode.

1b: Charger is not in IIN_DPM during forward mode.

0b: Charger is not in fast charge

1b: Charger is in fast charger

0b: Charger is not in pre-charge

1b: Charger is in pre-charge

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Table 9-14. ChargerStatus Register (I²C address = 21h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

0

IN_OTG

R

0b

0b: Charger is not in OTG

1b: Charge is in OTG

Table 9-15. ChargerStatus Register (I²C address = 20h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Fault ACOV

R

0b

The status are latched if triggered until a read from host.

0b: No fault

1b: ACOV

6

Fault BATOC

R

0b

The status is latched if triggered until a read from host. Fault

indicator for BATOC only during normal operation. However, in PTM

mode when EN_BATOC=1b, this status bit is fault indicator for both

BATOVP and BATOC; when EN_BATOC=0b, this status bit is not

effective.

0b: No fault

1b: BATOC is triggered

5

4

Fault ACOC

R

0b

The status is latched if triggered until a read from host.

0b: No fault

1b: ACOC

Fault SYSOVP

R/W

SYSOVP Status and Clear. SYSOVP fault is latched until a clear

from host by writing this bit to 0.

When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the

converter is disabled.

After the SYSOVP is removed, the user must write a 0 to this bit

or unplug the adapter to clear the SYSOVP condition to enable the

converter again.

0b: Not in SYSOVP <default at POR>

1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the

SYSOVP latch.

3

2

Fault VSYS_UVP

R/W

0b

VSYS_UVP fault status and clear. VSYS_UVP fault is latched until a

clear from host by writing this bit to 0.

0b: No fault <default at POR>

1b: When system voltage is lower than VSYS_UVP, then 7 times

restart tries are failed.

Fault Force_Converter_Off

R

The status is latched if triggered until a read from host.

0b: No fault

1b: Force converter off triggered (when FORCE_CONV_OFF

(REG0x30[3])=1b)

1

0

Fault_OTG_OVP

Fault_OTG_UVP

R

0b

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG OVP fault is triggered

The status is latched if triggered until a read from host.

0b: No fault

1b: OTG UVP fault is triggered

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9.6.5 ProchotStatus Register (I²C address = 23/22h) [reset = B800h]

All the status bits in REG0x23[7,2],REG0x23[6:0] will be cleared after host read.

Figure 9-18. ProchotStatus Register (I²C address = 23/22h) [reset = B800h]

7

6

5

4

3

2

1

0

Reserved

EN_PROCHOT

_EXT

PROCHOT_WIDTH

PROCHOT_CL

EAR

Reserved

STAT_VAP_FAI STAT_EXIT_VA

L

R/W

1

P

R/W

0

R

7

R/W

6

R/W

R

5

4

3

2

STAT_VINDPM STAT_COMP

STAT_ICRIT

STAT_INOM

STAT_IDCHG1

STAT_VSYS

STAT_BAT_Re STAT_ADPT_R

moval

emoval

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-16. ProchotStatus Register (I²C address = 23h) Field Descriptions

BIT

7

FIELD

TYPE

RESET

DESCRIPTION

Reserved

R

1b

Reserved

6

EN_PROCHOT _EXT

R/W

0b

PROCHOT Pulse Extension Enable. When pulse extension is

enabled, keep the PROCHOT pin voltage LOW until host writes

PROCHOT _CLEAR = 0b.

0b: Disable pulse extension <default at POR>

1b: Enable pulse extension

5-4

PROCHOT _WIDTH

PROCHOT _CLEAR

R/W

11b

PROCHOT Pulse Width Minimum PROCHOT pulse width when

EN_PROCHOT _EXT = 0b

00b: 100 us

01b: 1 ms

10b: 5 ms

11b: 10 ms <default at POR>

3

1b

PROCHOT Pulse Clear.

Clear PROCHOT pulse when EN_PROCHOT _EXT = 1b.

0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH

1b: Idle <default at POR>

2

1

TSHUT

R

0b

TSHUT trigger:

0b: TSHUT is not triggered

1b: TSHUT is triggered

STAT_VAP_FAIL

R/W

This status bit reports a failure to load VBUS 7 consecutive times

in VAP mode, which indicates the battery voltage might be not

high enough to enter VAP mode, or the VAP loading current

settings are too high.

0b: Not is VAP failure <default at POR>

1b: In VAP failure, the charger exits VAP mode, and latches off

until the host writes this bit to 0.

0

STAT_EXIT_VAP

R/W

0b

When the charger is operated in VAP mode, it can exit VAP

by either being disabled through host, or there are ACOV/ACOC/

SYSOVP/BATOVP/VSYS_UVP faults.

0b: PROCHOT_EXIT_VAP is not active <default at POR>

1b: PROCHOT_EXIT_VAP is active, PROCHOT pin is low until

host writes this status bit to 0.

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Table 9-17. ProchotStatus Register (I²C address = 22h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

STAT_VINDPM

R/W

0b

PROCHOT Profile VINDPM status bit

0b: Not triggered

1b: Triggered, PROCHOT pin is low until host writes this status bit

to 0 when PP_VINDPM = 1b

6

5

4

3

2

1

0

STAT_COMP

R

0b

PROCHOT Profile CMPOUT status bit. The status is latched until

a read from host.

0b: Not triggered

1b: Triggered

STAT_ICRIT

PROCHOT Profile ICRIT status bit. The status is latched until a

read from host.

0b: Not triggered

1b: Triggered

STAT_INOM

PROCHOT Profile INOM status bit. The status is latched until a

read from host.

0b: Not triggered

1b: Triggered

STAT_IDCHG1

STAT_VSYS

PROCHOT Profile IDCHG1 status bit. The status is latched until a

read from host.

0b: Not triggered

1b: Triggered

PROCHOT Profile VSYS status bit. The status is latched until a

read from host.

0b: Not triggered

1b: Triggered

STAT_Battery_Removal

STAT_Adapter_Removal

PROCHOT Profile Battery Removal status bit. The status is

latched until a read from host.

0b: Not triggered

1b: Triggered

PROCHOT Profile Adapter Removal status bit. The status is

latched until a read from host.

0b: Not triggered

1b: Triggered

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9.6.6 IIN_DPM Register (I²C address = 25/24h) [reset = 4100h]

IIN_DPM register reflects the actual input current limit programmed in the register, either from IIN_HOST register

or from ICO.

After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual

DPM limit is reported in IIN_DPM register.

To read the nominal or typical input current limit

•

When using a 10-mΩ sense resistor (RSNS_RAC=0b). There is 50-mA offset at code 0. Note this offset is

only applied to code 0, not applied to other codes.

When using a 5-mΩ sense resistor (RSNS_RAC=1b). There is 100-mA offset at code 0. Note this offset is

only applied to code 0, not applied to other codes.

To read the maximum input current limit, need to add 100 mA/200 mA offset based on above nominal input

current limit reading approach.

•

When using a 10-mΩ sense resistor (RSNS_RAC=0b). There is 150-mA offset at code 0 and this 150 mA

offset is only applied to code 0, 100-mA offset should be added for all other non-zero codes.

When using a 5-mΩ sense resistor (RSNS_RAC=1b). There is 300-mA offset at code 0 and this 300 mA

offset is only applied to code 0, 200-mA offset should be added for all other non-zero codes

Figure 9-19. IIN_DPM Register with 10-mΩ Sense Resistor (I²C address = 25/24h) [reset = 4100h]

7

6

5

4

3

2

1

0

Reserved

Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in

DPM, bit 6

DPM, bit 5

DPM, bit 4

DPM, bit 3

DPM, bit 2

DPM, bit 1

DPM, bit 0

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-18. IIN_DPM Register with 5-mΩ Sense Resistor (I²C address = 25h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Reserved

R

0b

Not used. 1 = invalid write.

6

5

4

3

2

1

0

Input Current in DPM, bit 6

Input Current in DPM, bit 5

Input Current in DPM, bit 4

Input Current in DPM, bit 3

Input Current in DPM, bit 2

Input Current in DPM, bit 1

Input Current in DPM, bit 0

R

0b

0 = Adds 0 mA of input current.

1 = Adds 6400 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 800mA of input current

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.

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Table 9-19. IIN_DPM Register with 5-mΩ Sense Resistor (I²C address = 24h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R

00000000b

Not used. Value Ignored.

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9.6.7 ADCVBUS/PSYS Register (I²C address = 27/26h)

•

PSYS: Full range: 3.06 V, LSB: 12 mV (ADC_FULLSCALE=1b)

PSYS: Full range: 2.04 V, LSB: 8 mV (ADC_FULLSCALE=0b)

VBUS: Full range: 0 mV to 24480 mV, LSB: 96 mV

Figure 9-20. ADCVBUS/PSYS Register (I²C address = 27/26h)

7

R

7

6

R

6

5

R

5

4

R

4

3

R

3

2

R

2

1

R

1

0

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-20. ADCVBUS Register (I²C address = 27h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of Input Voltage

Table 9-21. ADCPSYS Register (I²C address = 26h) Field Descriptions

BIT

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of System Power

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9.6.8 ADCIBAT Register (I²C address = 29/28h)

•

ICHG: Full range when using a 10-mΩ sense resistor (RSNS_RSR=0b):8.128 A, LSB: 64 mA.

ICHG: Full range when using a 5-mΩ sense resistor (RSNS_RSR=1b):16.256A,LSB: 128 mA.

IDCHG: Full range when using a 10-mΩ sense resistor (RSNS_RSR=0b):32.512 A, LSB: 256 mA. Note when

discharge current is higher than 32.512 A, the ADC will report 32.512 A

•

IDCHG: Full range when using a 5-mΩ sense resistor (RSNS_RSR=1b):65.024A,LSB: 512 mA. Note when

discharge current is higher than 65.024 A, the ADC will report 65.024 A

Figure 9-21. ADCIBAT Register (I²C address = 29/28h)

7

6

R

6

5

R

5

4

R

4

3

R

3

2

R

2

1

R

1

0

R

0

Reserved

7

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-22. ADCICHG Register (I²C address = 29h) Field Descriptions

BIT

7

FIELD

TYPE

RESET

DESCRIPTION

Reserved

R

Not used. Value ignored.

6-0

7-bit Digital Output of Battery Charge Current

Table 9-23. ADCIDCHG Register (I²C address = 28h) Field Descriptions

BIT

7

FIELD

TYPE

RESET

DESCRIPTION

Reserved

R

Not used. Value ignored.

6-0

7-bit Digital Output of Battery Discharge Current

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9.6.9 ADCIIN/CMPIN Register (I²C address = 2B/2Ah)

•

IIN Full range: When using a 10-mΩ sense resistor (RSNS_RAC=0b): 12.75 A, LSB: 50 mA.

IIN Full range: When using a 5-mΩ sense resistor (RSNS_RAC=1b): 25.5A, LSB:100 mA.

CMPIN Full range: 3.06 V, LSB: 12 mV (ADC_FULLSCALE=1b)

CMPIN Full range: 2.04 V, LSB: 8 mV (ADC_FULLSCALE=0b)

Figure 9-22. ADCIIN/CMPIN Register (I²C address = 2B/2Ah)

7

R

7

6

R

6

5

R

5

4

R

4

3

R

3

2

R

2

1

R

1

0

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-24. ADCIIN Register (I²C address = 2Bh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of Input Current

Table 9-25. ADCCMPIN Register (I²C address = 2Ah) Field Descriptions

BIT

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of CMPIN voltage

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9.6.10 ADCVSYS/VBAT Register (I²C address = 2D/2Ch)

•

VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)

VSYS: Full range: 8.16 V to 24.48 V, LSB: 64 mV (5S)

VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV (1S-4S)

VBAT: Full range: 8.16 V to 24.48 V, LSB: 64 mV (5S)

Figure 9-23. ADCVSYS/VBAT Register (I²C address = 2D/2Ch)

7

R

7

6

R

6

5

R

5

4

R

4

3

R

3

2

R

2

1

0

R

1

R

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-26. ADCVSYS Register (I²C address = 2Dh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of System Voltage

Table 9-27. ADCVSYSVBAT Register (I²C address = 2Ch) Field Descriptions

BIT

TYPE

RESET

DESCRIPTION

7-0

R

8-bit Digital Output of Battery Voltage

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9.6.11 ChargeOption1 Register (I²C address = 31/30h) [reset = 3F00h]

Figure 9-24. ChargeOption1 Register (I²C address = 31/30h) [reset = 3300h]

7

6

5

4

3

2

1

0

EN_IBAT

EN_PROCHOT

_LPWR

PSYS_CONFIG

R/W

RSNS_RAC

RSNS_RSR

PSYS_RATIO EN_FAST_5MO

HM

R/W

3

R/W

1

R/W

0

7

6

5

4

2

CMP_REF

CMP_POL

CMP_DEG

R/W

FORCE_CON

V_OFF

EN_PTM

EN_SHIP_DCH AUTO_WAKEU

G

P_EN

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-28. ChargeOption1 Register (I²C address = 31h) Field Descriptions

BIT

FIELD

TYPE

RESET DESCRIPTION

7

EN_IBAT

R/W

0b

IBAT Enable

Enable the IBAT output buffer. In low power mode (EN_LWPWR=1b), IBAT

buffer is always disabled regardless of this bit value.

0b Turn off IBAT buffer to minimize Iq <default at POR>

1b: Turn on IBAT buffer

6

EN_PROCHOT_LPWR

R/W

0b

Enable PROCHOT during battery only low power mode

With battery only, enable VSYS in PROCHOT with low power consumption. Do

not enable this function with adapter present. Refer to Section 9.3.20.1 for more

details.

0b: Disable Independent Comparator low power PROCHOT <default at POR>

1b: Enable Independent Comparator low power PROCHOT

5-4

PSYS_CONFIG

11b

PSYS Enable and Definition Register

Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low

power mode (EN_LWPWR=1b), PSYS sensing and buffer are always disabled

regardless of this bit value.

00b: PSYS=PBUS+PBAT

01b: PSYS=PBUS

10b: Reserved

11b: Turn off PSYS buffer to minimize Iq<default at POR>

3

2

1

RSNS_RAC

RSNS_RSR

PSYS_RATIO

R/W

1b

Input sense resistor R_AC

0b: 10 mΩ

1b: 5 mΩ <default at POR>

Charge sense resistor R_SR

0b: 10 mΩ

1b: 5 mΩ <default at POR>

PSYS Gain

Ratio of PSYS output current vs total system power

0b: 0.25 µA/W

1b: 1 µA/W <default at POR>

62

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Table 9-28. ChargeOption1 Register (I²C address = 31h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET DESCRIPTION

0

EN_FAST_5MOHM

R/W

1b

Enable fast compensation to increase bandwidth under 5 mΩ RAC

(RSNS_RAC=1b) for input current up to 6.4-A application (the fast

compensation will only work when IADPT pin is configured less than 160 kΩ)

0b: Turn off bandwidth promotion under RSNS_RAC=1b

(Note when this bit configured as 0b, IIN_HOST DAC can be extended up to

10 A, writing IIN_HOST value higher than 10 A will be neglected, the ICHG

regulation loop will be slower to guarantee stability under 6.4-A to 10-A input

current range)

1b: Turn on bandwidth promotion under RSNS_RAC=1b <default at POR>

(Note when this bit configured as 1b, IIN_HOST DAC is clamped at 6.4 A,

writing IIN_HOST value higher than 6.4 A will be neglected, the ICHG regulation

loop will be faster within 6.4-A input current range)

Table 9-29. ChargeOption1 Register (I²C address = 30h) Field Descriptions

BIT

FIELD

TYPE

RESET DESCRIPTION

7

CMP_REF

R/W

0b

Independent Comparator internal Reference

0b: 2.3 V <default at POR>

1b: 1.2 V

6

CMP_POL

CMP_DEG

R/W

0b

Independent Comparator output Polarity

0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal

hysteresis) <default at POR>

1b: When CMPIN is below internal threshold, CMPOUT is LOW (external

hysteresis)

5-4

00b

Independent comparator deglitch time, only applied to the falling edge of

CMPOUT (HIGH → LOW).

00b: Independent comparator is enabled with output deglitch time 5 µs <default

at POR>

01b: Independent comparator is enabled with output deglitch time of 2 ms

10b: Independent comparator is enabled with output deglitch time of 20 ms

11b: Independent comparator is enabled with output deglitch time of 5 sec

3

FORCE_CONV_OFF

R/W

0b

Force Converter Off function

When independent comparator triggers, (CMPOUT pin pulled down) converter

latches off, at the same time, CHRG_OK signal goes LOW to notify the system.

Charge current is also set to zero internally, but charge current register setting

keeps the same. To get out of converter latches off, firstly the CMPOUT should

be released to high and secondly FORCE_CONV_OFF bit should be cleared

(=0b).

0b: Disable this function <default at POR>

1b: Enable this function

2

EN_PTM

R/W

0b

PTM enable register bit, it will automatically reset to zero

0b: disable PTM. <default at POR>

1b: enable PTM.

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Table 9-29. ChargeOption1 Register (I²C address = 30h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET DESCRIPTION

1

EN_SHIP_DCHG

R/W

0b

Discharge SRN for Shipping Mode. Used to discharge VBAT pin capacitor

voltage which is necessary for battery gauge device shipping mode.

When this bit is 1, discharge SRN pin down in 140 ms 20 mA. When 140 ms is

over, this bit is reset to 0b automatically. If this bit is written to 0b by host before

140 ms expires, VSYS should stop discharging immediately. Note if after 140-ms

SRN voltage is still not low enough for battery gauge device entering ship mode,

the host may need to start a new 140-ms discharge cycle.

0b: Disable shipping mode <default at POR>

1b: Enable shipping mode

0

AUTO_WAKEUP_EN

R/W

0b

Auto Wakeup Enable

When this bit is HIGH, if the battery is below VSYS_MIN , the device should

automatically enable 128-mA charging current for 30 mins. When the battery is

charged up above minimum system voltage, charge will terminate and the bit is

reset to LOW. The charger will also exit auto wake up if host write a new charge

current value to charge current register Reg0x14().

0b: Disable <default at POR>

1b: Enable

64

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9.6.12 ChargeOption2 Register (I²C address = 33/32h) [reset = 00B7]

Figure 9-25. ChargeOption2 Register (I²C address = 33/32h) [reset = 00B7]

7

6

5

4

3

2

1

0

PKPWR_TOVLD_DEG

R/W

EN_PKPWR_II EN_PKPWR_V PKPWR_OVLD PKPWR_RELA

PKPWR_TMAX[1:0]

R/W

N_DPM

SYS

_STAT

X_STAT

R/W

7

6

5

4

3

2

1

0

EN_EXTILIM

EN_ICHG_IDC

HG

Q2_OCP

ACX_OCP

EN_ACOC

ACOC_VTH

EN_BATOC

BATOC_VTH

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-30. ChargeOption2 Register (I²C address = 33h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

PKPWR_TOVLD_DEG

R/W

00b

Input Overload time in Peak Power Mode

00b: 1 ms <default at POR>

01b: 2 ms

10b: 5 ms

11b: 10 ms

5

4

EN_PKPWR_IIN_DPM

R/W

0b

Enable Peak Power Mode triggered by input current overshoot

If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter

removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by input current overshoot

1b: Enable peak power mode triggered by input current overshoot.

EN_PKPWR_VSYS

Enable Peak Power Mode triggered by system voltage under-shoot

If REG0x33[5:4] are 00b, peak power mode is disabled. Upon adapter

removal, the bits are reset to 00b.

0b: Disable peak power mode triggered by system voltage under-shoot

1b: Enable peak power mode triggered by system voltage under-shoot.

3

2

STAT_PKPWR_OVLD

STAT_PKPWR_RELAX

PKPWR_TMAX[1:0]

R/W

0b

Indicator that the device is in overloading cycle. Write 0 to get out of

overloading cycle.

0b: Not in peak power mode. <default at POR>

1b: In peak power mode.

0b

Indicator that the device is in relaxation cycle. Write 0 to get out of

relaxation cycle.

0b: Not in relaxation cycle. <default at POR>

1b: In relaxation mode.

1-0

00b

Peak power mode overload and relax cycle time.

00b: 20 ms <default at POR>

01b: 40 ms

10b: 80 ms

11b: 1 sec

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Table 9-31. ChargeOption2 Register (I²C address = 32h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

EN_EXTILIM

R/W

1b

Enable ILIM_HIZ pin to set input current limit

0b: Input current limit is set by IIN_DPM register..

1b: Input current limit is set by the lower value of ILIM_HIZ pin and

IIN_DPM register.. <default at POR>

6

5

EN_ICHG_IDCHG

Q2_OCP

R/W

0b

1b

0b: IBAT pin as discharge current. <default at POR>

1b: IBAT pin as charge current.

Q2 OCP threshold by sensing Q2 VDS

0b: 210 mV

1b: 150 mV <default at POR>

4

ACX_OCP

R/W

1b

Fixed Input current OCP threshold by sensing ACP-ACN, converter

is disabled immediately when triggered non latch protection resume

switching automatically after ACX comparator release.

0b: 280 mV(RSNS_RAC=0b)/200 mV(RSNS_RAC=1b)

1b: 150 mV(RSNS_RAC=0b)/100 mV(RSNS_RAC=1b) <default at

POR>

3

EN_ACOC

R/W

0b

ACOC Enable

Configurable Input overcurrent (ACOC) protection by sensing the

voltage across ACP and ACN. Upon ACOC (after 250-μs blank-out

time), converter is disabled. Non latch fault, after 250-ms falling edge

de-glitch time converter starts switching automatically.

0b: Disable ACOC <default at POR>

1b: ACOC threshold 133% or 200% ILIM2

2

1

ACOC_VTH

EN_BATOC

R/W

1b

ACOC Limit

Set MOSFET OCP threshold as percentage of IIN_DPM with current

sensed from R_AC.

0b: 133% of ILIM2

1b: 200% of ILIM2 <default at POR>

BATOC

Battery discharge overcurrent (BATOC) protection by sensing the

voltage across SRN and SRP. Upon BATOC, converter is disabled.

0b: Disable BATOC

1b: Enable BATOC threshold 133% or 200% PROCHOT IDCHG_TH2

0

BATOC_VTH

R/W

1b

Set battery discharge overcurrent threshold as percentage of

PROCHOT battery discharge current limit. Note when SRN and SRP

common voltage is low for 1S application, the BATOC threshold could

be derating.

0b: 133% of PROCHOT IDCHG_TH2

1b: 200% of PROCHOT IDCHG _TH2<default at POR>

66

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9.6.13 ChargeOption3 Register (I²C address = 35/34h) [reset = 0434h]

Figure 9-26. ChargeOption3 Register (I²C address = 35/34h) [reset = 0434h]

7

6

5

4

3

2

1

0

EN_HIZ

RESET_REG RESET_VINDP

M

EN_OTG

EN_ICO_MOD EN_PORT_CT EN_VSYS_MIN EN_OTG_BIGC

E

RL

_SOFT_SR

AP

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

2

1

0

BATFET_ENZ EN_VBUS_VAP OTG_VAP_MO

DE

IL_AVG

R/W

CMP_EN

BATFETOFF_H PSYS_OTG_ID

IZ

CHG

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-32. ChargeOption3 Register (I²C address = 35h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

EN_HIZ

R/W

0b

Device HIZ Mode Enable

When the charger is in HIZ mode, the device draws minimal quiescent

current. With VBUS above UVLO. REGN LDO stays on, and system

powers from battery.

0b: Device not in HIZ mode <default at POR>

1b: Device in HIZ mode

6

5

RESET_REG

R/W

0b

Reset Registers

All the registers are reset to POR default setting except the VINDPM

register.

0b: Idle <default at POR>

1b: Reset all the registers to default values. After reset, this bit goes back

to 0.

RESET_VINDPM

Reset VINDPM Threshold

0b: Idle

1b: Converter is disabled to measure VINDPM threshold. After VINDPM

measurement is done, this bit goes back to 0 and converter starts.

(When battery voltage is lower than VSYS_MIN this function is not

recommended due to potential risk to crash system during VINDPM

measurement .)

4

EN_OTG

R/W

0b

OTG Mode Enable

Enable device in OTG mode when OTG/VAP/FRS pin is HIGH.

0b: Disable OTG <default at POR>

1b: Enable OTG mode to supply VBUS from battery.

3

2

1

EN_ICO_MODE

R/W

0b

1b

0b

Enable ICO Algorithm

0b: Disable ICO algorithm. <default at POR>

1b: Enable ICO algorithm.

EN_PORT_CTRL

Enable BATFET control

0b: Disable BATFET control pin by HIZ BATDRV pin

1b: Enable BATFET control pin by activate BATDRV pin

EN_VSYS_MIN_SOFT_SR

Enable VSYS_MIN soft slew rate transition

0b: Disable VSYS_MIN soft slew rate transition <default at POR>

1b:Enable VSYS_MIN soft slew rate transition (1LSB/8μs=12.5mV/μs)

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Table 9-32. ChargeOption3 Register (I²C address = 35h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

0

EN_OTG_BIGCAP

R/W

0b

Enable OTG compensation for VBUS effective capacitance larger than 33

μF

0b: Disable OTG large VBUS capacitance compensation (Recommended

for VBUS effective capacitance smaller than 33 μF) <default at POR>

1b: Enable OTG large VBUS capacitance compensation (Recommended

for VBUS effective capacitance larger than 33 μF)

Table 9-33. ChargeOption3 Register (I²C address = 34h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

BATFET_ENZ

R/W

0b

Turn off BATFET under battery only mode. If charger is not in battery only

mode this bit is not allowed to be written to 1. Under battery only OTG

mode, this bit is forced to be 0b.

0b: Not force turn off BATFET <default at POR>

1b: Force turn off BATFET

6

5

EN_VBUS_VAP

R/W

0b

1b

Enable the VBUS VAP for VAP operation mode 2&3

0b: Disabled <default at POR>

1b: Enabled

OTG_VAP_MODE

The selection of the external OTG/VAP/FRS pin control. Don't

recommend to change pin control after OTG/VAP/FRS pin is pulled high.

0b: the external OTG/VAP/FRS pin controls the EN/DIS VAP mode

1b: the external OTG/VAP/FRS pin controls the EN/DIS OTG mode

4-3

IL_AVG

R/W

10b

Converter inductor average current clamp. It is recommended to choose

the smallest option which is higher than maximum possible converter

average inductor current.

00b: 6A

01b: 10A

10b: 15A <default at POR>

11b: Disabled

2

1

0

CMP_EN

R/W

1b

0b

Enable Independent Comparator with effective low.

0b: Disabled

1b: Enabled <default at POR>

BATFETOFF_HIZ

PSYS_OTG_IDCHG

Control BATFET on/off during charger HIZ mode.

0b: BATFET on during charger HIZ mode <default at POR>

1b: BATFET off during charger HIZ mode

PSYS function during OTG mode.

0b: PSYS as battery discharge power minus OTG output power <default

at POR>

1b: PSYS as battery discharge power only

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9.6.14 ProchotOption0 Register (I²C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]

To set VSYS_TH1 threshold to trigger discharging VBUS in VAP mode, write a 6-bit Vmin Active Protection

register command (REG0x37<7:2>()) using the data format listed in Figure 9-27, Table 9-34, and Table 9-35.

The charger Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the

thresholds. The threshold range from 3.2 V (000000b) to 9.5 V (111111b) for 2s~5s and 3.2 V (000000b) to 3.9

V (000111b) for 1S, with 100-mV step resolution. There is a fixed DC offset which is 3.2 V. Under 1S application

writing beyond 3.9 V will be ignored. For example 000111b and xxx111b result in same VSYS_TH1 setting 3.9

V. Upon POR, the VSYS_TH1 threshold to trigger VBUS discharge in VAP mode is 3.4 V (000010b) for 1S and

6.400 V (100000b) for 2s~5s.

Figure 9-27. ProchotOption0 Register (I²C address = 37/36h) [reset = 4A81h(2S~5s) 4A09(1S)]

7

6

5

4

3

2

1

0

ILIM2_VTH

ICRIT_DEG

R/W

PROCHOT_VI

NDPM_80_90

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

0

2

1

VSYS_TH1

INOM_DEG LOWER_PRO

CHOT_VINDP

M

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-34. ProchotOption0 Register (I²C address = 37h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-3

ILIM2_VTH

R/W

01001b

I_LIM2Threshold

5 bits, percentage of IIN_DPM in 0x22H. Measure current between ACP and

ACN.

Trigger when the current is above this threshold:

00001b - 11001b: 110% - 230%, step 5%

11010b - 11110b: 250% - 450%, step 50%

11111b: Out of Range (Ignored)

Default 150%, or 01001

2-1

ICRIT_DEG

R/W

01b

ICRIT Deglitch time

ICRIT threshold is set to be 110% of _ILIM2

.

Typical ICRIT deglitch time to trigger PROCHOT.

00b: 15 µs

01b: 100 µs <default at POR>

10b: 400 µs (max 500 μs)

11b: 800 µs (max 1 ms)

0

PROCHOT_VINDPM_ R/W

80_90

0b

Lower threshold of the PROCHOT_VINDPM comparator

When REG0x33[0]=1, the threshold of the PROCHOT_VINDPM comparator is

determined by this bit setting.

0b: 83% of VinDPM threshold <default at POR>.

1b: 91% of VinDPM threshold

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Table 9-35. ProchotOption0 Register (I²C address = 36h) Field Descriptions

BIT

FIELD

TYPE

RESET

100000b( VSYS Threshold to trigger discharging VBUS in VAP mode.

2S~5s) Measure on VSYS with fixed 5-µs deglitch time. Trigger when SYS pin voltage is

000010b( below the thresholds. There is a fixed DC offset which is 3.2 V.

DESCRIPTION

7-2

VSYS_TH1

R/W

1S)

2S - 5s battery (Default: 6.4 V)

000000b- 111111b: 3.2 V - 9.5 V with 100-mV step size.

1S battery (Default: 3.4 V)

XXX000b - XXX111b: 3.2 V - 3.9 V with 100-mV step size.

1

0

INOM_DEG

R/W

0b

INOM Deglitch Time

INOM is always 10% above IIN_DPM register setting. Measure current between

ACP and ACN.

Trigger when the current is above this threshold.

0b: 1 ms(max) <default at POR>

1b: 60 ms(max)

LOWER_PROCHOT_ R/W

VINDPM

1b

Enable the lower threshold of the PROCHOT_VINDPM comparator

0b: the threshold of the PROCHOT_VINDPM comparator follows the same

VINDPM REG0x3D() setting.

1b: the threshold of the PROCHOT_VINDPM comparator is lower and determined

by PROCHOT_VINDPM_80_90 bit setting. <default at POR>

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9.6.15 ProchotOption1 Register (I²C address = 39/38h) [reset = 41A0h]

Figure 9-28. ProchotOption1 Register (I²C address = 39/38h) [reset = 41A0h]

7

6

5

4

3

2

1

0

IDCHG_TH1

IDCHG_DEG1

R/W

5

R/W

7

6

4

3

2

1

0

PP_VINDPM

R/W

PP_COMP

R/W

PP_ICRIT

R/W

PP_INOM

R/W

PP_IDCHG1

R/W

PP_VSYS

R/W

PP_BATPRES

R/W

PP_ACOK

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

When the REG0x38h[7:0] are set to be disabled, the PROCHOT event associated with that bit will not be

reported in the PROCHOT status register REG0x22h[7:0] any more, and the PROCHOT pin will not be pulled

low any more if the event happens.

Table 9-36. ProchotOption1 Register (I²C address = 39h) Field Descriptions

BIT

FIELD

TYPE

RESET DESCRIPTION

7-2

IDCHG_TH1

R/W

010000b

IDCHG level 1 Threshold

6 bit, range, range 0 A to 64512 mA, step 1024 mA.

Measure current between SRN and SRP.

Trigger when the discharge current is above the threshold.

If the value is programmed to 000000b PROCHOT is always triggered.

Default: 16256 mA or 010000b

1-0

IDCHG_DEG1

R/W

00b

IDCHG level 1 Deglitch Time

00b: 78 ms

01b: 1.25s <default at POR>

10b: 5s

11b: 20s

Table 9-37. ProchotOption1 Register (I²C address = 38h) Field Descriptions

BIT

FIELD

TYPE

RESET DESCRIPTION

7

PP_VINDPM

R/W

1b

VINDPM PROCHOT Profile

When all the REG0x38[7:0] , REG0x3D[1], REG0x3C[2]bits are 0, PROCHOT

function is disabled.

0b: disable

1b: enable<default at POR>

6

PP_COMP

R/W

0b

Independent comparator PROCHOT Profile

When not in low power mode(Battery only), use this bit to control independent

comparator PROCHOT profiles.

When in low power mode(Battery only), this bit will lose controllability

to independent comparator PROCHOT profiles. Need to use

EN_PROCHOT_LPWR to enable independent comparator and its PROCHOT

profile.

0b: disable <default at POR>

1b: enable

5

4

PP_ICRIT

PP_INOM

R/W

1b

0b

ICRIT PROCHOT Profile

0b: disable

1b: enable <default at POR>

INOM PROCHOT Profile

0b: disable <default at POR>

1b: enable

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Table 9-37. ProchotOption1 Register (I²C address = 38h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET DESCRIPTION

3

PP_IDCHG1

R/W

0b

IDCHG1 PROCHOT Profile

0b: disable <default at POR>

1b: enable

2

1

PP_VSYS

R/W

VSYS PROCHOT Profile

0b: disable <default at POR>

1b: enable

PP_BATPRES

Battery removal PROCHOT Profile

0b: disable <default at POR>

1b: enable (one-shot falling edge triggered)

If BATPRES is enabled in PROCHOT after the battery is removed, it will

immediately send out one-shot PROCHOT pulse.

0

PP_ACOK

R/W

0b

Adapter removal PROCHOT Profile

0b: disable <default at POR>

1b: enable

EN_LWPWR= 0b to assert PROCHOT pulse after adapter removal.

If PP_ACOK is enabled in PROCHOT after the adapter is removed, it will be

pulled low.

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9.6.16 ADCOption Register (I²C address = 3B/3Ah) [reset = 2000h]

Figure 9-29. ADCOption Register (I²C address = 3B/3Ah) [reset = 2000h]

7

6

5

4

3

2

1

0

ADC_CONV

ADC_START ADC_FULLSCA

LE

Reserved

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

EN_ADC_CMPI EN_ADC_VBU EN_ADC_PSY

EN_ADC_IIN EN_ADC_IDCH EN_ADC_ICHG EN_ADC_VSY EN_ADC_VBAT

N

S

G

S

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC

is disabled in low power mode. Before enabling ADC, low power mode should be disabled first.

Table 9-38. ADCOption Register (I²C address = 3Bh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

ADC_CONV

R/W

0b

Typical each ADC channel conversion time is 25 ms maximum. Total ADC

conversion time is the product of 25 ms and enabled channel counts.

0b: One-shot update. Do one set of conversion updates to registers

REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C() after

ADC_START = 1.

1b: Continuous update. Do a set of conversion updates to registers

REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C()every 1

sec.

6

5

ADC_START

R/W

0b

1b

0b: No ADC conversion

1b: Start ADC conversion. After the one-shot update is complete, this bit

automatically resets to zero

ADC_FULLSCALE

ADC input voltage range adjustment for PSYS and CMPIN ADC Channels.

2.04-V full scale holds 8 mV/LSB resolution and 3.06-V full scale holds 12

mV/LSB resolution

0b: 2.04 V

1b: 3.06 V <default at POR>(Not accurate for REGN<6-V application (VBUS

& VSYS< 6V))

4-0

Reserved

R/W

00000b

Reserved

Table 9-39. ADCOption Register (I²C address = 3Ah) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

EN_ADC_CMPIN

R/W

0b

0b: Disable <default at POR>

1b: Enable

6

5

4

3

2

EN_ADC_VBUS

EN_ADC_PSYS

EN_ADC_IIN

R/W

0b

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

EN_ADC_IDCHG

EN_ADC_ICHG

0b: Disable <default at POR>

1b: Enable

0b: Disable <default at POR>

1b: Enable

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Table 9-39. ADCOption Register (I²C address = 3Ah) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

1

EN_ADC_VSYS

R/W

0b

0b: Disable <default at POR>

1b: Enable

0

EN_ADC_VBAT

R/W

0b

0b: Disable <default at POR>

1b: Enable

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9.6.17 ChargeOption4 Register (I²C address = 3D/3Ch) [reset = 0048h]

Figure 9-30. ChargeOption4 Register (I²C address = 3D/3Ch) [reset = 0048h]

7

6

5

4

3

2

1

0

VSYS_UVP

EN_Dither

R/W

VSYS_UVP_N PP_VBUS_VAP STAT_VBUS_V

O_HICCUP

AP

R/W

6

R/W

R

5

4

3

2

1

0

STAT_PTM

R

IDCHG_DEG2

R/W

IDCHG_TH2

R/W

PP_IDCHG2

R/W

STAT_IDCHG2

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-40. ChargeOption4 Register (I²C address = 3Dh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-5

VSYS_UVP

R/W

000b

VSYS Under Voltage Lock Out After UVP is triggered the charger enters

hiccup mode, and then the charger is latched off if the restart fails 7

times in 90s The hiccup mode during the UVP can be disabled by setting

0x37[10]=1.

VSYS_UVP

000b

1S~5s

VSYS_UVP

100b

1S~5s

5.6 V

2.4 V(Default)

3.2 V

4.0 V

4.8 V

101b

6.4 V

7.2 V

8.0 V

001b

010b

011b

110b

111b

4-3

EN_DITHER

R/W

00b

Frequency Dither configuration

00b: Disable Dithering<default at POR>

01b: Dither 1X (±2% Fs dithering range)

10b: Dither 2X (±4% Fs dithering range)

11b: Dither 3X (±6% Fs dithering range)

2

1

0

VSYS_UVP_NO_HICCUP

PP_VBUS_VAP

R/W

R

0b

Disable VSYS_UVP Hiccup mode operation:

0b: Enable VSYS_UVP Hiccup mode <default at POR>

1b: Disable VSYS_UVP Hiccup mode

VBUS_VAP PROCHOT Profile

0b: disable <default at POR>

0b: enable

STAT_VBUS_VAP

PROCHOT profile VBUS_VAP status bit. The status is latched until a read

from host.

0b: Not triggered <default at POR>

1b: Triggered

Table 9-41. ChargeOption4 Register (I²C address = 3Ch) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

IDCHG_DEG2

R/W

01b

Battery discharge current limit 2 deglitch time(minimum value)

00b: 100 μs

01b: 1.6 ms <default at POR>

10b: 6 ms

11b: 12 ms

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Table 9-41. ChargeOption4 Register (I²C address = 3Ch) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

5-3

IDCHG_TH2

R/W

001b

Battery discharge current limit2 based on percentage of IDCHG_TH1.

Note IDCHG_TH2 setting higher than 32256 mA should lose accuracy

de-rating between target value and 32256 mA. (Recommend not to set

higher than 20 A for 1S OTG boost operation)

000b: 125% IDCHG_TH1

001b: 150% IDCHG_TH1 <default at POR>

010b: 175% IDCHG_TH1

011b: 200% IDCHG_TH1

100b: 250% IDCHG_TH1

101b: 300% IDCHG_TH1

110b: 350% IDCHG_TH1

111b: 400% IDCHG_TH1

2

1

0

PP_IDCHG2

STAT_IDCHG2

STAT_PTM

R/W

R

0b

IDCHG2 PROCHOT Profile

0b: disable <default at POR>

1b: enable

The status is latched until a read from host.

0b: Not triggered <default at POR>

1b: Triggered

R

PTM operation status bit monitor

0b: Not in PTM Operation <default at POR>

1b: In PTM Operation

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9.6.18 Vmin Active Protection Register (I²C address = 3F/3Eh) [reset = 006Ch(2s~5s)/0004h(1S)]

To set the VAP VBUS PROCHOT trigger threshold, write a 7-bit Vmin Active Protection register command

(REG0x3F[7:1]) using the data format listed in Figure 9-31 and Table 9-42. The charger provides VAP mode

VBUS PROCHOT trigger threshold range from 3.2 V (0000000b) to 15.9 V (1111111b), with 100-mV step

resolution. There is a fixed offset of 3.2 V. Upon POR, the VBUS PROCHOT trigger threshold is 3.2 V

(0000000b).

To set VSYS_TH2 Threshold to assert STAT_VSYS, write a 6-bit Vmin Active Protection register command

(REG0x3E[7:2]) using the data format listed in Figure 9-31 and Table 9-43. The charger Measure on VSYS with

fixed 5-µs deglitch time. Trigger when SYS pin voltage is below the thresholds. The threshold range from 3.2

V (000000b) to 9.5 V (111111b) for 2s~5s and 3.2 V (000000b) to 3.9 V (000111b) for 1S, with 100-mV step

resolution. There is a fixed DC offset which is 3.2 V. Under 1S application writing beyond 3.9 V will be ignored.

For example, xxx111b and 000111b result in same VSYS_TH2 setting 3.9 V. Upon POR, the VSYS PROCHOT

trigger threshold is 3.2 V (000000b) for 1S and 5.9 V (011011b) for 2s~5s .

Figure 9-31. Vmin Active Protection Register (I²C address = 3F/3Eh) [reset = 0070h/0004h]

7

6

5

4

3

2

1

0

VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_TH VBUS_VAP_T VBUS_VAP_TH VBUS_VAP_TH

Reserved

Bit6

Bit5

Bit4

Bit3

H Bit2

Bit1

Bit0

R/W

7

6

5

4

3

2

1

0

VSYS_TH2 Bit6 VSYS_TH2 Bit5 VSYS_TH2 Bit4 VSYS_TH2 Bit3 VSYS_TH2

Bit2

VSYS_TH2 Bit1 EN_TH2_FOLL

OW_TH1

EN_FRS

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-42. Vmin Active Protection Register (I²C address = 3Fh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

VBUS_VAP_TH, Bit6

R/W

0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 6400 mV of VAP Mode VBUS PROCHOT trigger voltage

threshold

6

5

VBUS_VAP_TH, Bit5

VBUS_VAP_TH, Bit4

R/W

0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 3200 mV of VAP Mode VBUS PROCHOT trigger voltage

threshold

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 1600 mV of VAP Mode VBUS PROCHOT trigger voltage

threshold

4

3

2

1

0

VBUS_VAP_TH, Bit3

VBUS_VAP_TH, Bit2

VBUS_VAP_TH, Bit1

VBUS_VAP_TH, Bit0

Reserve

R/W

0b

0 = Adds 0 mV of VAP Mode VBUS PROCHOT trigger voltage threshold

1 = Adds 800 mV of VAP mode VBUS PROCHOT trigger voltage threshold

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 400 mV of VAP mode VBUS PROCHOT trigger voltage threshold

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 200 mV of VAP mode VBUS PROCHOT trigger voltage threshold

0 = Adds 0 mV of VAP mode VBUS PROCHOT trigger voltage threshold

1 = Adds 100 mV of VAP mode VBUS PROCHOT trigger voltage threshold

Reserve

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Table 9-43. Vmin Active Protection Register (I²C address = 3Eh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

VSYS_TH2, Bit5

R/W

0b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 3200 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

6

5

4

3

2

1

VSYS_TH2, Bit4

VSYS_TH2, Bit3

VSYS_TH2, Bit2

VSYS_TH2, Bit1

VSYS_TH2, Bit0

R/W

1b(2S~5s 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

)

1 = Adds 1600 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

0b(1S)

1b(2S~5s 0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

)

1 = Adds 800 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

0b(1S)

0b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 400 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

0b(1S)

1b(2S~5s

)

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 200 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

1b

0 = Adds 0 mV of VAP mode VSYS PROCHOT trigger voltage threshold

1 = Adds 100 mV of VAP mode VSYS PROCHOT trigger voltage

threshold

EN_VSYSTH2_FOLLOW_VS R/W

YSTH1

0b

Enable internal VSYS_TH2 follow VSYS_TH1 setting neglecting register

REG37[7:2] setting

0b: disable <default at POR>

1b: enable

0

EN_FRS

R/W

0b

Fast Role Swap feature enable (note not recommend to change EN_FRS

during OTG operation, the FRS bit from 0 to 1 change will disable power

stage for about 200 μs (Fs = 400 kHz). HIZ mode holds higher priority, If

EN_HIZ=1b, this EN_FRS bit should be forced to 0b.

0b: disable <default at POR>

1b: enable

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9.6.19 OTGVoltage Register (I²C address = 07/06h) [reset = 09C4h]

To set the OTG output voltage limit, write to REG0x07/06h() using the data format listed in Figure 9-32, Table

9-44, and Table 9-45.

The DAC is clamped in digital core at minimal 3 V and maximum 24.0 V during normal OTG operation. Any

register writing lower than the minimal or higher than the maximum will be ignored.

Figure 9-32. OTGVoltage Register (I²C address = 07/06h) [reset = 09C4h]

7

6

5

4

3

2

1

0

Reserved

R/W

OTG Voltage,

bit 11

OTG Voltage,

bit 10

OTG Voltage,

bit 9

OTG Voltage,

bit 8

OTG Voltage,

bit 7

OTG Voltage,

bit 6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

OTG Voltage,

bit 5

OTG Voltage,

bit 4

OTG Voltage,

bit 3

OTG Voltage,

bit 2

OTG Voltage,

bit 1

OTG Voltage,

bit 0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-44. OTGVoltage Register (I²C address = 07h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

Reserved

R/W

00b

Not used. 1 = invalid write.

13

12

11

10

9

OTG Voltage, bit 11

OTG Voltage, bit 10

OTG Voltage, bit 9

OTG Voltage, bit 8

OTG Voltage, bit 7

OTG Voltage, bit 6

R/W

0b

1b

0b

1b

0 = Adds 0 mV of OTG voltage.

1 = Adds 16384 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 8192 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 4096 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 2048 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 1024 mV of OTG voltage.

8

0 = Adds 0 mV of OTG voltage.

1 = Adds 512 mV of OTG voltage.

Table 9-45. OTGVoltage Register (I²C address = 06h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

OTG Voltage, bit 5

R/W

1b

0 = Adds 0 mV of OTG voltage.

1 = Adds 256 mV of OTG voltage.

6

5

4

3

2

OTG Voltage, bit 4

OTG Voltage, bit 3

OTG Voltage, bit 2

OTG Voltage, bit 1

OTG Voltage, bit 0

R/W

1b

0b

1b

0 = Adds 0 mV of OTG voltage.

1 = Adds 128 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 64 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 32 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 16 mV of OTG voltage.

0 = Adds 0 mV of OTG voltage.

1 = Adds 8 mV of OTG voltage.

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Table 9-45. OTGVoltage Register (I²C address = 06h) Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

1-0

Reserved

R/W

00b

Not used. Value Ignored.

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9.6.20 OTGCurrent Register (I²C address = 09/08h) [reset = 3C00h]

To set the OTG output current limit, write to REG0x09() using the data format listed in Figure 9-33 and Table

9-46.

Figure 9-33. OTGCurrent Register (I²C address = 09/08h) [reset = 3C00h]

7

6

5

4

3

2

1

0

Reserved

OTG Current

set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit

6

5

4

3

2

1

0

R/W

7

R/W

6

5

4

3

2

1

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-46. OTGCurrent Register (I²C address = 09h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Reserved

R/W

0b

Not used. 1 = invalid write.

6

5

4

3

2

1

0

OTG Current set by host, bit 6

OTG Current set by host, bit 5

OTG Current set by host, bit 4

OTG Current set by host, bit 3

OTG Current set by host, bit 2

OTG Current set by host, bit 1

OTG Current set by host, bit 0

R/W

0b

1b

0b

0 = Adds 0 mA of OTG current.

1 = Adds 3200 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 1600 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 800 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 400 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 200 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 100 mA of OTG current.

0 = Adds 0 mA of OTG current.

1 = Adds 50 mA of OTG current.

Table 9-47. OTGCurrent Register (I²C address = 08h) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R/W

00000000b

Not used. Value Ignored.

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9.6.21 InputVoltage(VINDPM) Register (I²C address = 0B/0Ah) [reset =VBUS-1.28V]

To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x0B/0A()) using the data

format listed in Figure 9-34, Table 9-48, and Table 9-49.

If the input voltage drops more than the InputVoltage register allows, the device enters VINDPM and reduces the

charge current. The default setting is 1.28 V below the no-load VBUS voltage. There is a fixed DC offset 3.2 V

for all codes.

Figure 9-34. InputVoltage Register (I²C address = 0B/0Ah) [reset = VBUS-1.28V]

7

6

5

4

3

2

1

0

Reserved

R/W

Input Voltage,

bit 7

Input Voltage,

bit 6

Input Voltage,

bit 5

Input Voltage,

bit 4

Input Voltage,

bit 3

Input Voltage,

bit 2

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

Input Voltage,

bit 1

Input Voltage,

bit 0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-48. InputVoltage Register (I²C address = 0Bh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

Reserved

R/W

00b

Not used. 1 = invalid write.

5

4

3

2

1

0

Input Voltage, bit 7

Input Voltage, bit 6

Input Voltage, bit 5

Input Voltage, bit 4

Input Voltage, bit 3

Input Voltage, bit 2

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 8192 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 4096 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 2048 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 1024 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 512 mV of input voltage.

0 = Adds 0 mV of input voltage.

1 = Adds 256 mV of input voltage.

Table 9-49. InputVoltage Register (I²C address = 0Ah) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Input Voltage, bit 1

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 128 mV of input voltage.

6

Input Voltage, bit 0

Reserved

R/W

0b

0 = Adds 0 mV of input voltage.

1 = Adds 64 mV of input voltage

5-0

000000b

Not used. Value Ignored.

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9.6.22 VSYS_MIN Register (I²C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]

To set the minimum system voltage, write a 16-bit VSYS_MIN register command (REG0x3E()) using the data

format listed in Figure 9-35, Table 9-50 , and Table 9-51 . The charger provides minimum system voltage range

from 1.0V to 23.0V, with 100-mV step resolution. Any write below 1.0V or above 23.0V is ignored. Upon POR,

the VSYS_MIN register is 3.6 V for 1 S, 6.6V for 2 S and 9.2 V for 3 S, and 12.3 V for 4 S, and 15.4 V for 5S.

Writing VSYS_MIN to 0 will set it to the default value based on CELL_BATPRESZ pin.

Figure 9-35. VSYS_MIN Register (I²C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin

setting]

7

6

5

4

3

2

1

0

VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit VSYS_MIN, bit

7

R/W

7

6

R/W

6

5

R/W

5

4

R/W

4

3

R/W

3

2

R/W

2

1

R/W

1

0

R/W

0

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-50. VSYS_MIN Register (I²C address = 0Dh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Min System Voltage, bit 7

R/W

0b

0 = Adds 0 mV of system voltage.

1 = Adds 12800 mV of system voltage.

6

5

4

3

2

1

0

Min System Voltage, bit 6

Min System Voltage, bit 5

Min System Voltage, bit 4

Min System Voltage, bit 3

Min System Voltage, bit 2

Min System Voltage, bit 1

Min System Voltage, bit 0

R/W

0b

0 = Adds 0 mV of system voltage.

1 = Adds 6400mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 3200 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 1600 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 800 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 400 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 200 mV of system voltage.

0 = Adds 0 mV of system voltage.

1 = Adds 100 mV of system voltage.

Table 9-51. VSYS_MIN Register (I²C address = 0Ch) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R/W

00000000

b

Not used. Value Ignored.

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9.6.23 IIN_HOST Register (I²C address = 0F/0Eh) [reset = 2000h]

To set the nominal or typical input current limit based on the adapter rated current. Write a 7-bit IIN_HOST

register command using the data format listed below.

When using a 10-mΩ sense resistor (RSNS_RAC=0b), the charger provides a nominal input-current limit range

of 50 mA to 6350 mA, with 50-mA resolution. The upper boundary is implemented through DAC clamp, writing

value higher than limitation will be neglected. The lower boundary is implemented through 50-mA offset at code

0. Note this offset is only applied to code 0, not applied to other codes. The default nominal input current limit is

3.25 A. Upon adapter removal, the input current limit is reset to the default value of 3.25 A.

When using a 5-mΩ sense resistor (RSNS_RAC=1b) referring to Section 9.3.5, the input-current limit range can

be found under certain IADPT pin, EN_FAST_5MOHM bit status. The lower boundary is implemented through

100-mA offset at code 0. Note this offset is only applied to code 0, not applied to other codes. The default current

limit is 3.2 A. Due to the USB current setting requirement, the register setting specifies the maximum current

instead of the typical current. Upon adapter removal, the nominal input current limit is reset to the default value

of 3.2 A.

To set the maximum input current limit based on adapter rated current. Additional 100-mA (10-mΩ sense

resistor)/200-mA (5-mΩ sense resistor) offset should be added based on above nominal input current limit to

obtain the maximum input current limit.

The ACP and ACN pins are used to sense R_ACwith the default value of 5 mΩ. For a 10-mΩ sense resistor, a

larger sense voltage is given and a better regulation accuracy, but at the cost of higher conduction loss.

Instead of using the internal IIN_DPM loop, the user can build up an external input current regulation loop and

have the feedback signal on the ILIM_HIZ pin.

In order to disable ILIM_HIZ pin, the host can write EN_EXTILIM=0b to disable ILIM_HIZ pin, or pull ILIM_HIZ

pin above 4.0 V.

Figure 9-36. IIN_HOST Register (I²C address = 0F/0Eh) [reset = 4100h]

7

6

5

4

3

2

1

0

Reserved

Input Current

set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit set by host, bit

6

R/W

6

5

R/W

5

4

R/W

4

3

R/W

3

2

R/W

2

1

R/W

1

0

R/W

0

R/W

7

Reserved

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-52. IIN_HOST Register With 5-mΩ Sense Resistor (I²C address = 0Fh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7

Reserved

R/W

0b

Not used. 1 = invalid write.

6

5

4

3

2

Input Current set by host, bit 6

Input Current set by host, bit 5

Input Current set by host, bit 4

Input Current set by host, bit 3

Input Current set by host, bit 2

R/W

0b

1b

0b

0 = Adds 0 mA of input current.

1 = Adds 6400 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 3200 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 1600 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 800 mA of input current.

0 = Adds 0 mA of input current.

1 = Adds 400 mA of input current.

84

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Table 9-52. IIN_HOST Register With 5-mΩ Sense Resistor (I²C address = 0Fh) Field Descriptions

(continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

1

Input Current set by host, bit 1

R/W

0b

0 = Adds 0 mA of input current.

1 = Adds 200 mA of input current.

0

Input Current set by host, bit 0

R/W

0b

0 = Adds 0 mA of input current.

1 = Adds 100 mA of input current.

Table 9-53. IIN_HOST Register With 5-mΩ Sense Resistor (I²C address = 0Eh) Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

Reserved

R

00000000

b

Not used. Value Ignored.

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9.6.24 ID Registers

9.6.24.1 ManufactureID Register (I²C address = 2Eh) [reset = 40h]

Figure 9-37. ManufactureID Register (I²C address = 2Eh) [reset = 40h]

7-0

Manufacturer ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-54. ManufactureID Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION (READ ONLY)

7-0

MANUFACTURE_ID

R

40h

9.6.24.2 Device ID (DeviceAddress) Register (I²C address = 2Fh) [reset = D5h]

Figure 9-38. Device ID (DeviceAddress) Register (I²C address = 2Fh) [reset = D5h]

7-0

DEVICE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-55. Device ID (DeviceAddress) Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-0

DEVICE_ID

R

BQ25730: 11 01 0101b (D5h)

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10 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The BQ2573xEVM evaluation module (EVM) is a complete charger module for evaluating the BQ25730. The

application curves were taken using the BQ2573xEVM.

As shown in Figure 10-1, at the charger VSYS terminal, a minimum 7-μF effective MLCC capacitance (7 × 10-μF

0603 package MLCC) is suggested for a 45-W to 65-W adapter, and two more 10-μF MLCC capacitors are

needed when power reaches 90 W. Overall 50-μF effective capacitance on VSYS net is necessary (POSCAP

is preferred). These capacitors do not have to be placed at the charger VSYS output terminal; all capacitors

connected to VSYS net can be counted including the input capacitor of the next stage converters.

10.2 Typical Application

VSYS

2x33uF

4.7uH

RAC=5m ꢀꢁ m

RSR=5m ꢀꢁ m

VBUS

!"!

Q2

BATT

(1-5s)

Q3

Q1

Q4

1nF

10nF

33nF

47nF

1uF

6x10uF

7x10uF

2x10uF

0.1uF

10

1.0uF

1x33uF

(Optional)

#"$$

HIDRV1

HIDRV2

10

SYS

BATDRV

SRP

33nF

10nF

ACN

ACP

10

SRN

VDDA

ILIM_HIZ

380k

220k

REGN

1uF

2.2–3.3uF

VDDA

PGND

BQ25730

350k

VBUS

CELL_BATPRES

250k

4.7nF 40.2k

33pF

COMP1

COMP2

IADPT

IBAT

PSYS

15pF

100pF

191k

680pF

15k

10k

30k

PROCHOT

3.3V or 1.8V

To Host

10k

3.3V or 1.8V

10k

Host

(I2C)

Figure 10-1. Application Diagram of BQ25730 with Power Path

10.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

3.5 V < Adapter Voltage < 26V

Input Voltage⁽²⁾

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DESIGN PARAMETER

EXAMPLE VALUE

3.2 A for 65-W adapter

8400 mV for 2s battery

3072 mA for 2s battery

6600 mV for 2s battery

Input Current Limit ⁽²⁾

Battery Charge Voltage⁽¹⁾

Battery Charge Current⁽¹⁾

Minimum System Voltage⁽¹⁾

(1) Refer to battery specification for settings.

(2) Refer to adapter specification for settings for Input Voltage and Input Current Limit.

10.2.2 Detailed Design Procedure

The parameters are configurable using the evaluation software. The simplified application circuit (see Figure

10-1, as the application diagram) shows the minimum component requirements. Inductor, capacitor, and

MOSFET selection are explained in the rest of this section. Refer to the EVM user's guide for the complete

application schematic.

10.2.2.1 Input Snubber and Filter for Voltage Spike Damping

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second

order system. The voltage spike at VBUS pin maybe beyond IC maximum voltage rating and damage IC. The

input filter must be carefully designed and tested to prevent overvoltage event on VBUS pin.

There are several methods to damp or limit the overvoltage spike during adapter hot plug-in. An electrolytic

capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin

voltage rating. A high current capability TVS Zener diode can also limit the overvoltage level to an IC safe level.

However these two solutions may not save cost or have small size.

A cost effective and small size solution is shown in Figure 10-2. The R1 and C1 are composed of a damping RC

network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used

for reverse voltage protection for VBUS pin. C2 is VBUS pin decoupling capacitor and it should be placed as

close as possible to VBUS pin. C2 value should be less than C1 value so R1 can dominate the equivalent ESR

value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when

adapter hot plug-in. R2 and C2 should have 10-µs time constant to limit the dv/dt on VBUS pin to reduce inrush

current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle

inrush current power loss according to resistor manufacturer’s data sheet. The filter components' value always

need to be verified with real application and minor adjustments may need to fit in the real application circuit.

D1

R2(0805)

1W

R1(2010)

2W

Adapter

connector

VBUS pin

C1

2.2mF

C2

0.47-1mF

Figure 10-2. Input Filter

10.2.2.2 ACP-ACN Input Filter

The BQ25730 has average current mode control. The input current sensing through ACP/ACN is critical to

recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-

ACN which overwhelms converter sensed inductor current information. It is also difficult to manage parasitic

inductance created based on different PCB layout. Larger parasitic inductance will generate larger sense current

ringing which could cause the average current control loop to go into oscillation. Therefore ACP-ACN sensing

information need to be conditioned.

For real system board condition, we suggest using below circuit design to get best result and filter noise induced

from different PCB parasitic factor. With time constant of filter from 47 ns to 200 ns, the filter is effective and the

delay of on the sensed signal is small, therefore there is no concern for average current mode control. If 400-kHz

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switching frequency is employed, 10 nF is recommended for C_DIFF; if 800-kHz switching frequency is chosen,

then C_DIFFcan be left open.

RAC

Q1

6x10uF

RACN

RACP

4.99ohm

10nF(0402) 1nF(0402)

CDIFF

10nF for 400kHz

Open for 800kHz

CACN

33nF

CACP

33nF

ACP

ACN

HIDRV1

Figure 10-3. ACN-ACP Input Filter

10.2.2.3 Inductor Selection

The BQ25730 has two selectable fixed switching frequency. Higher switching frequency allows the use of

smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current

(I_CHG) plus half the ripple current (I_RIPPLE):

I_SAT³ I_CHG+ (1/2) I_RIPPLE

(2)

The inductor ripple current in buck operation depends on input voltage (V_IN), duty cycle (D_BUCK= V_OUT/V_IN),

switching frequency (f_S) and inductance (L):

I_{RIPPLE_BUCK}= V_IN× D_BUCK× (1-D_BUCK) / (f_S× L)

During boost operation, the duty cycle is:

(3)

D_BOOST= 1 – (V_IN/V_BAT

)

and the ripple current is:

I_{RIPPLE_BOOST}= (V_IN× D_BOOST) / (f_S× L)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging

voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives

the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to

16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20 – 40%) maximum charging current as a trade-off between

inductor size and efficiency for a practical design.

10.2.2.4 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current (plus system current there is any system load) when duty cycle

is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS

current occurs where the duty cycle is closest to 50% and can be estimated by Equation 4:

I_CIN= I_CHG

´

D × (1 - D)

(4)

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Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed in front of R_ACcurrent sensing and as close as possible to the power stage half bridge MOSFETs.

Capacitance after R_ACbefore power stage half bridge should be limited to 10 nF + 1 nF referring to Figure 10-3

diagram. Because too large capacitance after R_ACcould filter out R_ACcurrent sensing ripple information. Voltage

rating of the capacitor must be higher than normal input voltage level, 25-V rating or higher capacitor is preferred

for 19-V to 20-V input voltage.

Ceramic capacitors (MLCC) show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias

voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead

to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the

manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary

to choose a higher voltage rating or nominal capacitance value in order to get the required effective capacitance

value at the operating point.

10.2.2.5 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. To

get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed

between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum

7 pcs of 10-μF 0603 package capacitor is suggested to be placed as close as possible to Q3&Q4 half bridge

(between Q4 drain and Q3 source terminal). Total minimum output effective capacitance along VSYS distribution

line is 50 μF refers to Table 10-1. Recommend to place minimum 20-μF MLCC capacitors after the charge

current sense resistor for best stability.

Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias

voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead

to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the

manufacturer's data sheet about the derating performance with a dc bias voltage applied. It may be necessary

to choose a higher voltage rating or nominal capacitance value in order to get the required capacitance value at

the operating point. Considering the 25-V 0603 package MLCC capacitance derating under 21-V to 23-V output

voltage, the recommended practical capacitors configuration at VSYS output terminal can also be found in

Table 10-1. Tantalum capacitors (POSCAP) can avoid dc-bias effect and temperature variation effect which are

recommend to be used along VSYS output distribution line to meet total minimum effective output capacitance

requirement.

Table 10-1. Minimum Output Capacitance Requirement

OUTPUT CAPACITORS vs TOTAL INPUT

65 W

90 W

130 W

POWER

Minimum Effective Output Capacitance

50 μF

Minimum output capacitors at charger VSYS 7*10 μF (0603 25 V MLCC)

output terminal

9*10 μF (0603 25 V MLCC)

Additional output capacitors along VSYS

distribution line

2*22 μF (25 V~35 V

POSCAP)

2*22 μF (25 V~35 V

POSCAP)

2*22 μF (25 V~35 V

POSCAP)

10.2.2.6 Power MOSFETs Selection

Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are

integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred for

19-V to 20-V input voltage.

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction

loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,

R_DS(ON), and the gate-to-drain charge, Q_GD. For the bottom side MOSFET, FOM is defined as the product of the

MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

FOM_top= R_DS(on)· Q_GD; FOM_bottom= R_DS(on)· Q_G

(5)

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON)has higher cost with the same

package size.

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The top-side MOSFET loss includes conduction loss and switching loss. Taking buck mode operation as

an example the power loss is a function of duty cycle (D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-

resistance (R_{DS(ON)_top}), input voltage (V_IN), switching frequency (f_S), turn-on time (t_on) and turn-off time (t_off):

P_top=P_{con_top}+P_{sw_top}

(6)

(7)

(8)

P_{con_top}=D · I_{L_RMS}²· R_{DS(on)_top}

I_{L_RMS}²=I_{L_DC}²+I_ripple²/12

;

•

I_{L_DC}is the average inductor DC current under buck mode;

I_rippleis the inductor current ripple peak-to-peak value;

P_{sw_top}=P_{IV_top}+P_{Qoss_top}+P_{Gate_top}

;

(9)

The first item P_{con_top}represents the conduction loss which is straight forward. The second term P_{sw_top}

represents the multiple switching loss items in top MOSFET including voltage and current overlap losses

(P_{IV_top}), MOSFET parasitic output capacitance loss (P_{Qoss_top}) and gate drive loss (P_{Gate_top}). To calculate

voltage and current overlap losses (P_{IV_top}):

P_{IV_top}=0.5x V_IN· I_valley· t_on· f_S+0.5x V_IN· I_peak· t_off· f_S

I_valley=I_{L_DC}- 0.5 · I_ripple(inductor current valley value);

I_peak=I_{L_DC}+ 0.5 · I_ripple(inductor current peak value);

(10)

(11)

(12)

•

t_onis the MOSFET turn-on time that V_DSfalling time from V_INto almost zero (MOSFET turn on conduction

voltage);

t_offis the MOSFET turn-off time that I_DSfalling time from I_peakto zero;

The MOSFET turn-on and turn-off times are given by:

Q_SWQ_SW

, t_off=

t_on

=

I_on

I_off

(13)

where Q_swis the switching charge, I_onis the turn-on gate driving current, and I_offis the turn-off gate driving

current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge

(Q_GD) and gate-to-source charge (Q_GS):

Q_sw=Q_GD+Q_GS

(14)

Gate driving current can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total turn-on

gate resistance (R_on), and turn-off gate resistance (R_off) of the gate driver:

V_REGN- V_plt

V_plt

I_on

=

, I_off=

R_on

R_off

(15)

(16)

To calculate top MOSFET parasitic output capacitance loss (P_{Qoss_top}):

P_{Qoss_top}=0.5 · V_IN· Q_oss· f_S

•

Q_ossis the MOSFET parasitic output charge which can be found in MOSFET datasheet;

To calculate top MOSFET gate drive loss (P_{Gate_top}):

P_{Gate_top}=V_IN· Q_{Gate_top}· f_S

(17)

•

Q_{Gate_top}is the top MOSFET gate charge which can be found in MOSFET datasheet;

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•

Note here V_INis used instead of real gate drive voltage 6 V because, the gate drive 6 V is generated based

on LDO from V_INunder buck mode, the total gate drive related loss are all considered when V_INis used for

gate drive loss calculation .

The bottom-side MOSFET loss also includes conduction loss and switching loss:

P_bottom=P_{con_bottom}+P_{sw_bottom}

(18)

(19)

(20)

P_{con_bottom}=(1 - D) · I_{L_RMS}²· R_{DS(on)_bottom}

;

P_{sw_bottom}=P_{RR_bottom}+P_{Dead_bottom}+P_{Gate_bottom}

;

The first item P_{con_bottom}represents the conduction loss which is straight forward. The second term P_{sw_bottom}

represents the multiple switching loss items in bottom MOSFET including reverse recovery losses (P_{RR_bottom}),

Dead time body diode conduction loss (P_{Dead_bottom}) and gate drive loss (P_{Gate_bottom}). The detail calculation can

be found below:

P_{RR_bottom}=V_IN· Q_rr· f_S

(21)

•

Q_rris the bottom MOSFET reverse recovery charge which can be found in MOSFET data sheet;

P_{Dead_bottom}=V_F· I_valley· f_S· t_{dead_rise}+V_F· I_peak· f_S· t_{dead_fall}

(22)

•

V_Fis the body diode forward conduction voltage drop;

t_{dead_rise}is the SW rising edge deadtime between top and bottom MOSFETs which is around 40 ns;

t_{dead_fall}is the SW falling edge deadtime between top and bottom MOSFETs which is around 30 ns;

P_{Gate_bottom}can follow the same method as top MOSFET gate drive loss calculation approach refer to Equation

17.

P-channel MOSFETs is used for battery charging BATFET. The gate drivers are internally integrated into the IC

with 10 V of gate drive voltage. 20 V or higher voltage rating MOSFETs are preferred for 1- to 4-cell battery

application, 30 V or higher voltage rating MOSFETs are preferred for 5-cell battery application, the Ciss of

P-channel MOSFET should be chosen less than 5 nF.

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10.2.3 Application Curves

CH1: VBUS

CH2: VDDA

CH1: VBUS

CH2: VDDA

CH3: CHRG_OK

CH4: VSYS

2-cell without battery

Figure 10-4. Power Up From 20 V

Figure 10-5. Power Up From 5 V

CH1: VBUS

CH2: SW1

CH3: SW2

CH4: VSYS with 9Vos

CH4: IL

3-cell VBAT = 10 V

VBUS 5 V to 20 V

Figure 10-6. Power Off From 12 V

Figure 10-7. Line Regulation

CH2: SW1

CH1: HIDRV1

CH2: SW1

CH3: LODRV1

CH3: SW2

CH1: IL

CH4: IL

VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA

VBUS = 20 V, VSYS = 10 V, ISYS = 2 A

Figure 10-8. PFM Operation

Figure 10-9. PWM Operation

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CH2: SW2

CH2: SW1

CH3: SW2

CH1: HIDRV2

CH3: LODRV2

CH4: IL

VBUS = 5 V, VBAT = 10 V

VBUS = 12 V, VBAT = 12 V

Figure 10-10. Switching During Boost Mode

Figure 10-11. Switching During Buck Boost Mode

CH1: VSYS

CH2: IIN

CH1: VSYS

CH2: IIN

CH3: ISYS

VBUS = 9 V/3.25 A, 3-cell, VSYS = 9 V, Without battery

VBUS = 12 V/3.25 A, 3-cell, VSYS = 9 V, Without battery

Figure 10-13. System Regulation in Buck Boost

Mode

Figure 10-12. System Regulation in Buck Mode

CH1: VSYS

CH2: IIN

CH3: ISYS

CH4: IBAT

CH3: ISYS

VBUS = 5 V/3.25 A, 3-cell, VSYS = 9 V, Without battery

VBUS = 20 V/3.25 A, VBAT = 7.5 V

Figure 10-14. System Regulation in Boost Mode

Figure 10-15. Input Current Regulation in Buck

Mode

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CH2:IIN

CH1: EN_OTG

CH2: VBUS

CH3:ISYS

CH4:IBAT

VBUS = 5 V/3.25 A, VBAT = 7.5 V

VBUS = 5 V

Figure 10-16. Input Current in Boost Mode

Figure 10-17. OTG Power Up from 8-V Battery

CH1: SCL

CH2: VBUS

CH3: SW2

VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA

Figure 10-19. OTG Power Off

Figure 10-18. OTG Voltage Ramp Up

CH2: VBUS

CH1:VBUS

CH2:FRS Pin

CH4:ISYS

CH3:IBUS

CH3: IVBUS

VBAT = 10 V, VBUS = 20 V

VBUS = 20 V, VOTG = 5 V, ISYS = 5 A,VBAT = 14.8 V

Figure 10-20. OTG Load Transient

Figure 10-21. FRS Transition Waveform

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VBUS = 20 V

T_MAX= 20 ms

IIN_DPM = 2 A

T_OVLD= 10 ms

ILIM2_VTH = 200%

VSYS_MIN = 12.3

V

VBUS = 20 V

T_MAX= 20 ms

ISYS = 1 to 6 A

IIN_DPM = 2 A

T_OVLD= 10 ms

ICHG = 0 A

ILIM2_VTH = 200%

VBAT = 12.8 V

ISYS = 1 to 6 A

ICHG = 0 A

Figure 10-23. Peak Power Mode IBUS Trigger

Figure 10-22. Peak Power Mode VSYS Trigger

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11 Power Supply Recommendations

The valid adapter range is from 3.5 V (V_{VBUS_CONVEN}) to 26 V with at least 500-mA current rating. When

CHRG_OK goes HIGH, the system is powered from adapter through the charger. When adapter is removed, the

system is connected to battery through BATFET. Typically the battery depletion threshold should be greater than

the VSYS_MIN so that the battery capacity can be fully utilized for maximum battery run time.

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12 Layout

12.1 Layout Guidelines

Proper layout of the components to minimize high frequency current path loop (see Section 12.2) is important

to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout

priority list for proper layout.

Table 12-1. PCB Layout Guidelines

RULES COMPONENTS

FUNCTION

IMPACT

GUIDELINES

1

PCB layer stack up Thermal, efficiency, Multi- layer PCB is suggested. Allocate at least one ground layer.

signal integrity

The BQ257XXEVM uses a 4-layer PCB (top layer, ground layer,

signal layer and bottom layer).

2

CBUS, RAC, Q1, Input loop

High frequency

noise, ripple

VBUS capacitors, RAC, Q1 and Q2 form a small loop 1. It is best

to put them on the same side. Connect them with large copper to

reduce the parasitic resistance. Move part of CBUS to the other

side of PCB for high density design. After RAC before Q1 and

Q2 power stage recommend to put 10 nF + 1 nF (0402 package)

decoupling capacitors as close as possible to IC to decoupling

switching loop high frequency noise.

Q2

3

4

5

R_AC, Q1, L1, Q4

CSYS, Q3, Q4

QBAT, R_SR

Current path

Output loop

Current path

Efficiency

The current path from VBUS to VSYS, through R_AC, Q1, L1, Q4,

has low impedance. Pay attention to via resistance if they are not

on the same side. The number of vias can be estimated as 1 to

2A/via for a 10-mil via with 1 oz. copper thickness.

High frequency

noise, ripple

VSYS capacitors, Q3 and Q4 form a small loop 2. It is best to

put them on the same side. Connect them with large copper to

reduce the parasitic resistance. Move part of CSYS to the other

side of PCB for high density design.

Efficiency, battery

voltage detection

Place QBAT and R_SRnear the battery terminal. The current

path from VBAT to VSYS, through R_SRand QBAT, has low

impedance. Pay attention to via resistance if they are not on the

same side. The device detects the battery voltage through SRN

near battery terminal.

6

7

Q1, Q2, L1, Q3,

Q4

Power stage

Thermal, efficiency Place Q1, Q2, L1, Q3 and Q4 next to each other. Allow

enough copper area for thermal dissipation. The copper area

is suggested to be 2x to 4x of the pad size. Multiple thermal

vias can be used to connect more copper layers together and

dissipate more heat.

R_AC, R_SR

Current sense

Regulation accuracy Use Kelvin-sensing technique for R_ACand R_SRcurrent sense

resistors. Connect the current sense traces to the center of the

pads, and run current sense traces as differential pairs.

8

9

Small capacitors

BST capacitors

IC bypass caps

HS gate drive

Noise, jittering,

ripple

Place VBUS cap, VCC cap, REGN caps near IC.

High frequency

noise, ripple

Place HS MOSFET boost strap circuit capacitor close to IC and

on the same side of PCB board. Capacitors SW1/2 nodes are

recommended to use wide copper polygon to connect to power

stage and capacitors BST1/2 node are recommended to use at

least 8mil trace to connected to IC BST1/2 pins.

98

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Table 12-1. PCB Layout Guidelines (continued)

RULES COMPONENTS

FUNCTION

IMPACT

GUIDELINES

10

Ground partition

Measurement

Separate analog ground(AGND) and power grounds(PGND) is

accuracy, regulation preferred. PGND should be used for all power stage related

accuracy, jitters,

ripple

ground net. AGND should be used for all sensing, compensation

and control network ground for example ACP/ACN/COMP1/

COMP2/CMPIN/CMPOUT/IADPT/IBAT/PSYS. Connect all

analog grounds to a dedicated low-impedance copper plane,

which is tied to the power ground underneath the IC exposed

pad. If possible, use dedicated COMP1, COMP2 AGND traces.

Connect analog ground and power ground together using power

pad as the single ground connection point.

12.2 Layout Example

12.2.1 Layout Example Reference Top View

Based on the above layout guidelines, the buck-boost charger layout example top view is shown below including

all the key power components.

Figure 12-1. Buck-Boost Charger Layout Reference Example Top View

12.2.2 Inner Layer Layout and Routing Example

For both input sensing resistor and charging current sensing resistor, differential sensing and routing method are

suggested and highlighted in below figure. Use wide trace for gate drive traces, minimum 15 mil trace width.

Connect all analog grounds to a dedicated low-impedance copper plane, which is tied to the power ground

underneath the IC exposed pad. Suggest using dedicated COMP1, COMP2 analog ground traces shown in

below figure.

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Figure 12-2. Buck-Boost Charger Gate Drive/Current Sensing/AGND Signal Layer Routing Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

•

Semiconductor and IC Package Thermal Metrics Application Report

BQ2571x Evaluation Module User's Guide

QFN/SON PCB Attachment Application Report

13.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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IMPORTANT NOTICE AND DISCLAIMER

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25730
厂家：	TEXAS INSTRUMENTS
描述：	具有电源路径和 USB-C™ PD OTG 的 I2C 1 至 5 节电池 NVDC 降压/升压电池充电控制器电池控制器光电二极管
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中文：	中文翻译
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